Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 12:14:17.910216 lava-dispatcher, installed at version: 2023.05.1
2 12:14:17.910436 start: 0 validate
3 12:14:17.910570 Start time: 2023-06-06 12:14:17.910563+00:00 (UTC)
4 12:14:17.910708 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:14:17.910899 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:14:18.193698 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:14:18.193895 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:14:18.488641 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:14:18.488829 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:14:18.767592 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:14:18.767807 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:14:19.058229 validate duration: 1.15
14 12:14:19.058499 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:14:19.058602 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:14:19.058694 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:14:19.058819 Not decompressing ramdisk as can be used compressed.
18 12:14:19.058925 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230527.0/arm64/rootfs.cpio.gz
19 12:14:19.058995 saving as /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/ramdisk/rootfs.cpio.gz
20 12:14:19.059057 total size: 34405874 (32MB)
21 12:14:19.060111 progress 0% (0MB)
22 12:14:19.069528 progress 5% (1MB)
23 12:14:19.078464 progress 10% (3MB)
24 12:14:19.087566 progress 15% (4MB)
25 12:14:19.096435 progress 20% (6MB)
26 12:14:19.105517 progress 25% (8MB)
27 12:14:19.114772 progress 30% (9MB)
28 12:14:19.124052 progress 35% (11MB)
29 12:14:19.133126 progress 40% (13MB)
30 12:14:19.142566 progress 45% (14MB)
31 12:14:19.151634 progress 50% (16MB)
32 12:14:19.160906 progress 55% (18MB)
33 12:14:19.169948 progress 60% (19MB)
34 12:14:19.179246 progress 65% (21MB)
35 12:14:19.188363 progress 70% (22MB)
36 12:14:19.197646 progress 75% (24MB)
37 12:14:19.206858 progress 80% (26MB)
38 12:14:19.216146 progress 85% (27MB)
39 12:14:19.225106 progress 90% (29MB)
40 12:14:19.234229 progress 95% (31MB)
41 12:14:19.243294 progress 100% (32MB)
42 12:14:19.243558 32MB downloaded in 0.18s (177.85MB/s)
43 12:14:19.243716 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:14:19.243959 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:14:19.244048 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:14:19.244132 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:14:19.244261 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:14:19.244335 saving as /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/kernel/Image
50 12:14:19.244401 total size: 45746688 (43MB)
51 12:14:19.244464 No compression specified
52 12:14:19.245745 progress 0% (0MB)
53 12:14:19.258242 progress 5% (2MB)
54 12:14:19.271551 progress 10% (4MB)
55 12:14:19.284135 progress 15% (6MB)
56 12:14:19.297420 progress 20% (8MB)
57 12:14:19.310144 progress 25% (10MB)
58 12:14:19.322076 progress 30% (13MB)
59 12:14:19.334213 progress 35% (15MB)
60 12:14:19.346317 progress 40% (17MB)
61 12:14:19.358437 progress 45% (19MB)
62 12:14:19.370576 progress 50% (21MB)
63 12:14:19.382530 progress 55% (24MB)
64 12:14:19.394627 progress 60% (26MB)
65 12:14:19.406762 progress 65% (28MB)
66 12:14:19.419091 progress 70% (30MB)
67 12:14:19.431138 progress 75% (32MB)
68 12:14:19.443155 progress 80% (34MB)
69 12:14:19.455222 progress 85% (37MB)
70 12:14:19.467309 progress 90% (39MB)
71 12:14:19.479172 progress 95% (41MB)
72 12:14:19.491085 progress 100% (43MB)
73 12:14:19.491232 43MB downloaded in 0.25s (176.76MB/s)
74 12:14:19.491382 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:14:19.491620 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:14:19.491709 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:14:19.491799 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:14:19.491942 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:14:19.492019 saving as /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/dtb/mt8192-asurada-spherion-r0.dtb
81 12:14:19.492084 total size: 46924 (0MB)
82 12:14:19.492145 No compression specified
83 12:14:19.493225 progress 69% (0MB)
84 12:14:19.493502 progress 100% (0MB)
85 12:14:19.493660 0MB downloaded in 0.00s (28.44MB/s)
86 12:14:19.493783 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:14:19.494010 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:14:19.494096 start: 1.4 download-retry (timeout 00:10:00) [common]
90 12:14:19.494184 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 12:14:19.494299 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:14:19.494375 saving as /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/modules/modules.tar
93 12:14:19.494440 total size: 8553528 (8MB)
94 12:14:19.494502 Using unxz to decompress xz
95 12:14:19.498119 progress 0% (0MB)
96 12:14:19.519581 progress 5% (0MB)
97 12:14:19.543830 progress 10% (0MB)
98 12:14:19.575487 progress 15% (1MB)
99 12:14:19.602238 progress 20% (1MB)
100 12:14:19.628289 progress 25% (2MB)
101 12:14:19.654355 progress 30% (2MB)
102 12:14:19.681257 progress 35% (2MB)
103 12:14:19.706740 progress 40% (3MB)
104 12:14:19.733230 progress 45% (3MB)
105 12:14:19.758604 progress 50% (4MB)
106 12:14:19.783521 progress 55% (4MB)
107 12:14:19.808374 progress 60% (4MB)
108 12:14:19.834700 progress 65% (5MB)
109 12:14:19.860800 progress 70% (5MB)
110 12:14:19.885935 progress 75% (6MB)
111 12:14:19.912787 progress 80% (6MB)
112 12:14:19.938455 progress 85% (6MB)
113 12:14:19.964161 progress 90% (7MB)
114 12:14:19.987992 progress 95% (7MB)
115 12:14:20.015044 progress 100% (8MB)
116 12:14:20.019796 8MB downloaded in 0.53s (15.53MB/s)
117 12:14:20.020080 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:14:20.020354 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:14:20.020448 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:14:20.020544 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:14:20.020627 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:14:20.020717 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:14:20.020942 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6
125 12:14:20.021076 makedir: /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin
126 12:14:20.021182 makedir: /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/tests
127 12:14:20.021283 makedir: /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/results
128 12:14:20.021393 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-add-keys
129 12:14:20.021578 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-add-sources
130 12:14:20.021743 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-background-process-start
131 12:14:20.021913 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-background-process-stop
132 12:14:20.022072 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-common-functions
133 12:14:20.022230 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-echo-ipv4
134 12:14:20.022385 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-install-packages
135 12:14:20.022540 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-installed-packages
136 12:14:20.022694 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-os-build
137 12:14:20.022858 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-probe-channel
138 12:14:20.022983 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-probe-ip
139 12:14:20.023106 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-target-ip
140 12:14:20.023228 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-target-mac
141 12:14:20.023349 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-target-storage
142 12:14:20.023474 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-test-case
143 12:14:20.023595 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-test-event
144 12:14:20.023715 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-test-feedback
145 12:14:20.023837 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-test-raise
146 12:14:20.023959 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-test-reference
147 12:14:20.024079 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-test-runner
148 12:14:20.024202 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-test-set
149 12:14:20.024322 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-test-shell
150 12:14:20.024444 Updating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-install-packages (oe)
151 12:14:20.024591 Updating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/bin/lava-installed-packages (oe)
152 12:14:20.024716 Creating /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/environment
153 12:14:20.024816 LAVA metadata
154 12:14:20.024890 - LAVA_JOB_ID=10605437
155 12:14:20.024958 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:14:20.025059 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:14:20.025125 skipped lava-vland-overlay
158 12:14:20.025200 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:14:20.025280 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:14:20.025342 skipped lava-multinode-overlay
161 12:14:20.025418 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:14:20.025500 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:14:20.025574 Loading test definitions
164 12:14:20.025665 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:14:20.025742 Using /lava-10605437 at stage 0
166 12:14:20.026052 uuid=10605437_1.5.2.3.1 testdef=None
167 12:14:20.026140 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:14:20.026226 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:14:20.026728 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:14:20.026967 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:14:20.027569 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:14:20.027813 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:14:20.028402 runner path: /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/0/tests/0_cros-ec test_uuid 10605437_1.5.2.3.1
176 12:14:20.028555 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:14:20.028761 Creating lava-test-runner.conf files
179 12:14:20.028825 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605437/lava-overlay-kiafj6n6/lava-10605437/0 for stage 0
180 12:14:20.028913 - 0_cros-ec
181 12:14:20.029008 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:14:20.029093 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:14:20.035814 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:14:20.035926 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:14:20.036019 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:14:20.036113 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:14:20.036247 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:14:20.997601 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:14:20.997981 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:14:20.998135 extracting modules file /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605437/extract-overlay-ramdisk-3qe0eq4v/ramdisk
191 12:14:21.228076 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:14:21.228250 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:14:21.228350 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605437/compress-overlay-fl5pbkes/overlay-1.5.2.4.tar.gz to ramdisk
194 12:14:21.228432 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605437/compress-overlay-fl5pbkes/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605437/extract-overlay-ramdisk-3qe0eq4v/ramdisk
195 12:14:21.236415 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:14:21.236564 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:14:21.236686 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:14:21.236809 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:14:21.236916 Building ramdisk /var/lib/lava/dispatcher/tmp/10605437/extract-overlay-ramdisk-3qe0eq4v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605437/extract-overlay-ramdisk-3qe0eq4v/ramdisk
200 12:14:21.884310 >> 269476 blocks
201 12:14:26.720226 rename /var/lib/lava/dispatcher/tmp/10605437/extract-overlay-ramdisk-3qe0eq4v/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/ramdisk/ramdisk.cpio.gz
202 12:14:26.720683 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:14:26.720828 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 12:14:26.720958 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 12:14:26.721104 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/kernel/Image'
206 12:14:39.239356 Returned 0 in 12 seconds
207 12:14:39.339969 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/kernel/image.itb
208 12:14:40.007542 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:14:40.008027 output: Created: Tue Jun 6 13:14:39 2023
210 12:14:40.008199 output: Image 0 (kernel-1)
211 12:14:40.008294 output: Description:
212 12:14:40.008403 output: Created: Tue Jun 6 13:14:39 2023
213 12:14:40.008543 output: Type: Kernel Image
214 12:14:40.008632 output: Compression: lzma compressed
215 12:14:40.008765 output: Data Size: 10094623 Bytes = 9858.03 KiB = 9.63 MiB
216 12:14:40.008853 output: Architecture: AArch64
217 12:14:40.008977 output: OS: Linux
218 12:14:40.009146 output: Load Address: 0x00000000
219 12:14:40.009259 output: Entry Point: 0x00000000
220 12:14:40.009394 output: Hash algo: crc32
221 12:14:40.009503 output: Hash value: fd97082e
222 12:14:40.009602 output: Image 1 (fdt-1)
223 12:14:40.009688 output: Description: mt8192-asurada-spherion-r0
224 12:14:40.009806 output: Created: Tue Jun 6 13:14:39 2023
225 12:14:40.009890 output: Type: Flat Device Tree
226 12:14:40.009989 output: Compression: uncompressed
227 12:14:40.010089 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:14:40.010175 output: Architecture: AArch64
229 12:14:40.010277 output: Hash algo: crc32
230 12:14:40.010377 output: Hash value: 1df858fa
231 12:14:40.010461 output: Image 2 (ramdisk-1)
232 12:14:40.010559 output: Description: unavailable
233 12:14:40.010659 output: Created: Tue Jun 6 13:14:39 2023
234 12:14:40.010745 output: Type: RAMDisk Image
235 12:14:40.010856 output: Compression: Unknown Compression
236 12:14:40.010955 output: Data Size: 47369159 Bytes = 46258.94 KiB = 45.17 MiB
237 12:14:40.011042 output: Architecture: AArch64
238 12:14:40.011157 output: OS: Linux
239 12:14:40.011239 output: Load Address: unavailable
240 12:14:40.011321 output: Entry Point: unavailable
241 12:14:40.011437 output: Hash algo: crc32
242 12:14:40.011522 output: Hash value: 0af0a48e
243 12:14:40.011605 output: Default Configuration: 'conf-1'
244 12:14:40.011717 output: Configuration 0 (conf-1)
245 12:14:40.011802 output: Description: mt8192-asurada-spherion-r0
246 12:14:40.011887 output: Kernel: kernel-1
247 12:14:40.012000 output: Init Ramdisk: ramdisk-1
248 12:14:40.012082 output: FDT: fdt-1
249 12:14:40.012180 output: Loadables: kernel-1
250 12:14:40.012281 output:
251 12:14:40.012546 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 12:14:40.012693 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 12:14:40.012845 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 12:14:40.012987 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 12:14:40.013106 No LXC device requested
256 12:14:40.013251 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:14:40.013367 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 12:14:40.013507 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:14:40.013612 Checking files for TFTP limit of 4294967296 bytes.
260 12:14:40.014287 end: 1 tftp-deploy (duration 00:00:21) [common]
261 12:14:40.014423 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:14:40.014546 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:14:40.014713 substitutions:
264 12:14:40.014810 - {DTB}: 10605437/tftp-deploy-0d56fqfp/dtb/mt8192-asurada-spherion-r0.dtb
265 12:14:40.014942 - {INITRD}: 10605437/tftp-deploy-0d56fqfp/ramdisk/ramdisk.cpio.gz
266 12:14:40.015032 - {KERNEL}: 10605437/tftp-deploy-0d56fqfp/kernel/Image
267 12:14:40.015124 - {LAVA_MAC}: None
268 12:14:40.015212 - {PRESEED_CONFIG}: None
269 12:14:40.015302 - {PRESEED_LOCAL}: None
270 12:14:40.015387 - {RAMDISK}: 10605437/tftp-deploy-0d56fqfp/ramdisk/ramdisk.cpio.gz
271 12:14:40.015476 - {ROOT_PART}: None
272 12:14:40.015562 - {ROOT}: None
273 12:14:40.015647 - {SERVER_IP}: 192.168.201.1
274 12:14:40.015731 - {TEE}: None
275 12:14:40.015814 Parsed boot commands:
276 12:14:40.015901 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:14:40.016118 Parsed boot commands: tftpboot 192.168.201.1 10605437/tftp-deploy-0d56fqfp/kernel/image.itb 10605437/tftp-deploy-0d56fqfp/kernel/cmdline
278 12:14:40.016235 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:14:40.016354 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:14:40.016478 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:14:40.016594 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:14:40.016695 Not connected, no need to disconnect.
283 12:14:40.016798 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:14:40.016914 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:14:40.017010 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 12:14:40.020693 Setting prompt string to ['lava-test: # ']
287 12:14:40.021099 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:14:40.021247 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:14:40.021383 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:14:40.021512 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:14:40.021849 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 12:14:45.154750 >> Command sent successfully.
293 12:14:45.157167 Returned 0 in 5 seconds
294 12:14:45.257570 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:14:45.258124 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:14:45.258228 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:14:45.258321 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:14:45.258409 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:14:45.258481 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:14:45.258903 [Enter `^Ec?' for help]
302 12:14:45.429877
303 12:14:45.430029
304 12:14:45.430105 F0: 102B 0000
305 12:14:45.430168
306 12:14:45.430228 F3: 1001 0000 [0200]
307 12:14:45.430289
308 12:14:45.433637 F3: 1001 0000
309 12:14:45.433722
310 12:14:45.433790 F7: 102D 0000
311 12:14:45.433853
312 12:14:45.433913 F1: 0000 0000
313 12:14:45.437464
314 12:14:45.437566 V0: 0000 0000 [0001]
315 12:14:45.437661
316 12:14:45.437751 00: 0007 8000
317 12:14:45.437844
318 12:14:45.440607 01: 0000 0000
319 12:14:45.440681
320 12:14:45.440742 BP: 0C00 0209 [0000]
321 12:14:45.440801
322 12:14:45.444452 G0: 1182 0000
323 12:14:45.444526
324 12:14:45.444587 EC: 0000 0021 [4000]
325 12:14:45.444646
326 12:14:45.448249 S7: 0000 0000 [0000]
327 12:14:45.448359
328 12:14:45.448439 CC: 0000 0000 [0001]
329 12:14:45.448501
330 12:14:45.451773 T0: 0000 0040 [010F]
331 12:14:45.451874
332 12:14:45.451942 Jump to BL
333 12:14:45.452005
334 12:14:45.476645
335 12:14:45.476755
336 12:14:45.476823
337 12:14:45.484009 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:14:45.487681 ARM64: Exception handlers installed.
339 12:14:45.491266 ARM64: Testing exception
340 12:14:45.494460 ARM64: Done test exception
341 12:14:45.501403 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:14:45.511319 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:14:45.517970 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:14:45.527940 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:14:45.534280 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:14:45.541247 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:14:45.553305 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:14:45.560065 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:14:45.579738 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:14:45.582766 WDT: Last reset was cold boot
351 12:14:45.585934 SPI1(PAD0) initialized at 2873684 Hz
352 12:14:45.589760 SPI5(PAD0) initialized at 992727 Hz
353 12:14:45.593019 VBOOT: Loading verstage.
354 12:14:45.599696 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:14:45.602751 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:14:45.605776 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:14:45.609537 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:14:45.616873 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:14:45.623388 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:14:45.634196 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:14:45.634284
362 12:14:45.634350
363 12:14:45.644437 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:14:45.647346 ARM64: Exception handlers installed.
365 12:14:45.650622 ARM64: Testing exception
366 12:14:45.650696 ARM64: Done test exception
367 12:14:45.657521 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:14:45.660578 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:14:45.675220 Probing TPM: . done!
370 12:14:45.675389 TPM ready after 0 ms
371 12:14:45.681931 Connected to device vid:did:rid of 1ae0:0028:00
372 12:14:45.732361 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 12:14:45.732534 Initialized TPM device CR50 revision 0
374 12:14:45.744248 tlcl_send_startup: Startup return code is 0
375 12:14:45.744353 TPM: setup succeeded
376 12:14:45.755646 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:14:45.764368 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:14:45.775932 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:14:45.785963 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:14:45.788953 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:14:45.792593 in-header: 03 07 00 00 08 00 00 00
382 12:14:45.796593 in-data: aa e4 47 04 13 02 00 00
383 12:14:45.799973 Chrome EC: UHEPI supported
384 12:14:45.807348 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:14:45.811060 in-header: 03 9d 00 00 08 00 00 00
386 12:14:45.814749 in-data: 10 20 20 08 00 00 00 00
387 12:14:45.814906 Phase 1
388 12:14:45.818040 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:14:45.825916 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:14:45.829489 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:14:45.833428 Recovery requested (1009000e)
392 12:14:45.839652 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:14:45.844762 tlcl_extend: response is 0
394 12:14:45.852799 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:14:45.858431 tlcl_extend: response is 0
396 12:14:45.865049 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:14:45.886065 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 12:14:45.893538 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:14:45.893675
400 12:14:45.893776
401 12:14:45.900421 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:14:45.904475 ARM64: Exception handlers installed.
403 12:14:45.907973 ARM64: Testing exception
404 12:14:45.910882 ARM64: Done test exception
405 12:14:45.931002 pmic_efuse_setting: Set efuses in 11 msecs
406 12:14:45.934574 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:14:45.938467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:14:45.946094 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:14:45.949910 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:14:45.953167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:14:45.960882 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:14:45.964864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:14:45.968186 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:14:45.975211 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:14:45.978484 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:14:45.981812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:14:45.988797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:14:45.991734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:14:45.995359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:14:46.002072 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:14:46.008889 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:14:46.015531 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:14:46.018941 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:14:46.025534 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:14:46.032583 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:14:46.036331 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:14:46.043830 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:14:46.046875 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:14:46.053927 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:14:46.060744 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:14:46.063924 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:14:46.070799 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:14:46.074194 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:14:46.081072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:14:46.084072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:14:46.091181 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:14:46.094787 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:14:46.098561 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:14:46.106218 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:14:46.109768 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:14:46.113518 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:14:46.120688 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:14:46.124218 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:14:46.131402 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:14:46.134618 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:14:46.137779 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:14:46.144682 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:14:46.147793 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:14:46.151017 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:14:46.157976 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:14:46.161148 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:14:46.164567 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:14:46.167679 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:14:46.174526 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:14:46.177894 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:14:46.180907 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:14:46.184016 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:14:46.194175 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:14:46.200693 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:14:46.207158 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:14:46.213927 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:14:46.223967 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:14:46.226873 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:14:46.234075 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:14:46.237491 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:14:46.243636 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 12:14:46.250445 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:14:46.253808 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 12:14:46.257353 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:14:46.268041 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 12:14:46.271206 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 12:14:46.278054 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 12:14:46.281115 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 12:14:46.284405 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 12:14:46.287537 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 12:14:46.291400 ADC[4]: Raw value=898150 ID=7
477 12:14:46.294528 ADC[3]: Raw value=213440 ID=1
478 12:14:46.297686 RAM Code: 0x71
479 12:14:46.301222 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 12:14:46.304387 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 12:14:46.314252 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 12:14:46.321806 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 12:14:46.324760 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 12:14:46.328248 in-header: 03 07 00 00 08 00 00 00
485 12:14:46.331311 in-data: aa e4 47 04 13 02 00 00
486 12:14:46.334237 Chrome EC: UHEPI supported
487 12:14:46.341745 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 12:14:46.344542 in-header: 03 d5 00 00 08 00 00 00
489 12:14:46.348146 in-data: 98 20 60 08 00 00 00 00
490 12:14:46.351806 MRC: failed to locate region type 0.
491 12:14:46.356298 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 12:14:46.359193 DRAM-K: Running full calibration
493 12:14:46.366175 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 12:14:46.366271 header.status = 0x0
495 12:14:46.369504 header.version = 0x6 (expected: 0x6)
496 12:14:46.373342 header.size = 0xd00 (expected: 0xd00)
497 12:14:46.376614 header.flags = 0x0
498 12:14:46.383134 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 12:14:46.399645 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 12:14:46.406633 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 12:14:46.410191 dram_init: ddr_geometry: 2
502 12:14:46.413105 [EMI] MDL number = 2
503 12:14:46.413189 [EMI] Get MDL freq = 0
504 12:14:46.416309 dram_init: ddr_type: 0
505 12:14:46.416392 is_discrete_lpddr4: 1
506 12:14:46.420139 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 12:14:46.420236
508 12:14:46.423519
509 12:14:46.423634 [Bian_co] ETT version 0.0.0.1
510 12:14:46.429938 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 12:14:46.430023
512 12:14:46.433060 dramc_set_vcore_voltage set vcore to 650000
513 12:14:46.436167 Read voltage for 800, 4
514 12:14:46.436337 Vio18 = 0
515 12:14:46.436422 Vcore = 650000
516 12:14:46.440032 Vdram = 0
517 12:14:46.440159 Vddq = 0
518 12:14:46.440256 Vmddr = 0
519 12:14:46.443301 dram_init: config_dvfs: 1
520 12:14:46.446330 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 12:14:46.453049 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 12:14:46.456100 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 12:14:46.459899 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 12:14:46.463502 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 12:14:46.469665 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 12:14:46.469754 MEM_TYPE=3, freq_sel=18
527 12:14:46.472871 sv_algorithm_assistance_LP4_1600
528 12:14:46.476110 ============ PULL DRAM RESETB DOWN ============
529 12:14:46.482661 ========== PULL DRAM RESETB DOWN end =========
530 12:14:46.485906 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 12:14:46.489915 ===================================
532 12:14:46.492474 LPDDR4 DRAM CONFIGURATION
533 12:14:46.495865 ===================================
534 12:14:46.495949 EX_ROW_EN[0] = 0x0
535 12:14:46.499838 EX_ROW_EN[1] = 0x0
536 12:14:46.499922 LP4Y_EN = 0x0
537 12:14:46.503021 WORK_FSP = 0x0
538 12:14:46.503105 WL = 0x2
539 12:14:46.506175 RL = 0x2
540 12:14:46.509586 BL = 0x2
541 12:14:46.509677 RPST = 0x0
542 12:14:46.512745 RD_PRE = 0x0
543 12:14:46.512828 WR_PRE = 0x1
544 12:14:46.516014 WR_PST = 0x0
545 12:14:46.516098 DBI_WR = 0x0
546 12:14:46.519113 DBI_RD = 0x0
547 12:14:46.519197 OTF = 0x1
548 12:14:46.522334 ===================================
549 12:14:46.526333 ===================================
550 12:14:46.526466 ANA top config
551 12:14:46.529507 ===================================
552 12:14:46.532686 DLL_ASYNC_EN = 0
553 12:14:46.536397 ALL_SLAVE_EN = 1
554 12:14:46.540028 NEW_RANK_MODE = 1
555 12:14:46.540149 DLL_IDLE_MODE = 1
556 12:14:46.543171 LP45_APHY_COMB_EN = 1
557 12:14:46.546890 TX_ODT_DIS = 1
558 12:14:46.549962 NEW_8X_MODE = 1
559 12:14:46.553759 ===================================
560 12:14:46.553848 ===================================
561 12:14:46.557564 data_rate = 1600
562 12:14:46.561455 CKR = 1
563 12:14:46.564564 DQ_P2S_RATIO = 8
564 12:14:46.567658 ===================================
565 12:14:46.571527 CA_P2S_RATIO = 8
566 12:14:46.571643 DQ_CA_OPEN = 0
567 12:14:46.575407 DQ_SEMI_OPEN = 0
568 12:14:46.578865 CA_SEMI_OPEN = 0
569 12:14:46.582502 CA_FULL_RATE = 0
570 12:14:46.582684 DQ_CKDIV4_EN = 1
571 12:14:46.586290 CA_CKDIV4_EN = 1
572 12:14:46.589758 CA_PREDIV_EN = 0
573 12:14:46.593383 PH8_DLY = 0
574 12:14:46.593467 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 12:14:46.596620 DQ_AAMCK_DIV = 4
576 12:14:46.600616 CA_AAMCK_DIV = 4
577 12:14:46.604080 CA_ADMCK_DIV = 4
578 12:14:46.607759 DQ_TRACK_CA_EN = 0
579 12:14:46.607843 CA_PICK = 800
580 12:14:46.611637 CA_MCKIO = 800
581 12:14:46.614768 MCKIO_SEMI = 0
582 12:14:46.617946 PLL_FREQ = 3068
583 12:14:46.621661 DQ_UI_PI_RATIO = 32
584 12:14:46.624877 CA_UI_PI_RATIO = 0
585 12:14:46.628511 ===================================
586 12:14:46.631537 ===================================
587 12:14:46.631621 memory_type:LPDDR4
588 12:14:46.634632 GP_NUM : 10
589 12:14:46.637734 SRAM_EN : 1
590 12:14:46.637818 MD32_EN : 0
591 12:14:46.641393 ===================================
592 12:14:46.644455 [ANA_INIT] >>>>>>>>>>>>>>
593 12:14:46.647965 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 12:14:46.651544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 12:14:46.654448 ===================================
596 12:14:46.657988 data_rate = 1600,PCW = 0X7600
597 12:14:46.661121 ===================================
598 12:14:46.664589 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 12:14:46.667714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 12:14:46.674531 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 12:14:46.677891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 12:14:46.680960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 12:14:46.684685 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 12:14:46.688020 [ANA_INIT] flow start
605 12:14:46.691814 [ANA_INIT] PLL >>>>>>>>
606 12:14:46.691943 [ANA_INIT] PLL <<<<<<<<
607 12:14:46.695547 [ANA_INIT] MIDPI >>>>>>>>
608 12:14:46.695661 [ANA_INIT] MIDPI <<<<<<<<
609 12:14:46.699002 [ANA_INIT] DLL >>>>>>>>
610 12:14:46.702686 [ANA_INIT] flow end
611 12:14:46.706481 ============ LP4 DIFF to SE enter ============
612 12:14:46.709920 ============ LP4 DIFF to SE exit ============
613 12:14:46.710050 [ANA_INIT] <<<<<<<<<<<<<
614 12:14:46.713865 [Flow] Enable top DCM control >>>>>
615 12:14:46.717195 [Flow] Enable top DCM control <<<<<
616 12:14:46.721059 Enable DLL master slave shuffle
617 12:14:46.728667 ==============================================================
618 12:14:46.728818 Gating Mode config
619 12:14:46.735194 ==============================================================
620 12:14:46.735306 Config description:
621 12:14:46.745012 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 12:14:46.751666 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 12:14:46.758469 SELPH_MODE 0: By rank 1: By Phase
624 12:14:46.761861 ==============================================================
625 12:14:46.764815 GAT_TRACK_EN = 1
626 12:14:46.768379 RX_GATING_MODE = 2
627 12:14:46.771956 RX_GATING_TRACK_MODE = 2
628 12:14:46.774671 SELPH_MODE = 1
629 12:14:46.778536 PICG_EARLY_EN = 1
630 12:14:46.781495 VALID_LAT_VALUE = 1
631 12:14:46.784931 ==============================================================
632 12:14:46.787904 Enter into Gating configuration >>>>
633 12:14:46.791251 Exit from Gating configuration <<<<
634 12:14:46.794927 Enter into DVFS_PRE_config >>>>>
635 12:14:46.808036 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 12:14:46.811816 Exit from DVFS_PRE_config <<<<<
637 12:14:46.811904 Enter into PICG configuration >>>>
638 12:14:46.815027 Exit from PICG configuration <<<<
639 12:14:46.818965 [RX_INPUT] configuration >>>>>
640 12:14:46.822165 [RX_INPUT] configuration <<<<<
641 12:14:46.825921 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 12:14:46.833008 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 12:14:46.840331 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 12:14:46.844101 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 12:14:46.851073 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 12:14:46.858331 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 12:14:46.862262 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 12:14:46.865950 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 12:14:46.869478 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 12:14:46.873065 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 12:14:46.876615 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 12:14:46.883950 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 12:14:46.884037 ===================================
654 12:14:46.887473 LPDDR4 DRAM CONFIGURATION
655 12:14:46.891374 ===================================
656 12:14:46.894889 EX_ROW_EN[0] = 0x0
657 12:14:46.895002 EX_ROW_EN[1] = 0x0
658 12:14:46.898104 LP4Y_EN = 0x0
659 12:14:46.898188 WORK_FSP = 0x0
660 12:14:46.901941 WL = 0x2
661 12:14:46.902053 RL = 0x2
662 12:14:46.902148 BL = 0x2
663 12:14:46.905691 RPST = 0x0
664 12:14:46.905775 RD_PRE = 0x0
665 12:14:46.909358 WR_PRE = 0x1
666 12:14:46.909468 WR_PST = 0x0
667 12:14:46.913185 DBI_WR = 0x0
668 12:14:46.913268 DBI_RD = 0x0
669 12:14:46.916948 OTF = 0x1
670 12:14:46.920906 ===================================
671 12:14:46.924146 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 12:14:46.927805 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 12:14:46.930755 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 12:14:46.934421 ===================================
675 12:14:46.938308 LPDDR4 DRAM CONFIGURATION
676 12:14:46.942043 ===================================
677 12:14:46.942129 EX_ROW_EN[0] = 0x10
678 12:14:46.945232 EX_ROW_EN[1] = 0x0
679 12:14:46.945311 LP4Y_EN = 0x0
680 12:14:46.949130 WORK_FSP = 0x0
681 12:14:46.949214 WL = 0x2
682 12:14:46.952422 RL = 0x2
683 12:14:46.952504 BL = 0x2
684 12:14:46.956603 RPST = 0x0
685 12:14:46.956686 RD_PRE = 0x0
686 12:14:46.960158 WR_PRE = 0x1
687 12:14:46.960241 WR_PST = 0x0
688 12:14:46.963751 DBI_WR = 0x0
689 12:14:46.963846 DBI_RD = 0x0
690 12:14:46.963912 OTF = 0x1
691 12:14:46.967520 ===================================
692 12:14:46.974534 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 12:14:46.978297 nWR fixed to 40
694 12:14:46.982142 [ModeRegInit_LP4] CH0 RK0
695 12:14:46.982226 [ModeRegInit_LP4] CH0 RK1
696 12:14:46.985965 [ModeRegInit_LP4] CH1 RK0
697 12:14:46.989458 [ModeRegInit_LP4] CH1 RK1
698 12:14:46.989544 match AC timing 13
699 12:14:46.993164 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 12:14:46.996225 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 12:14:47.003617 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 12:14:47.007464 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 12:14:47.010725 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 12:14:47.015344 [EMI DOE] emi_dcm 0
705 12:14:47.018345 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 12:14:47.018431 ==
707 12:14:47.022412 Dram Type= 6, Freq= 0, CH_0, rank 0
708 12:14:47.026022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 12:14:47.026138 ==
710 12:14:47.029329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 12:14:47.036484 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 12:14:47.046627 [CA 0] Center 38 (7~69) winsize 63
713 12:14:47.049981 [CA 1] Center 37 (7~68) winsize 62
714 12:14:47.053867 [CA 2] Center 35 (5~66) winsize 62
715 12:14:47.057667 [CA 3] Center 35 (5~66) winsize 62
716 12:14:47.060894 [CA 4] Center 34 (4~65) winsize 62
717 12:14:47.063977 [CA 5] Center 34 (4~64) winsize 61
718 12:14:47.064063
719 12:14:47.067992 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 12:14:47.068073
721 12:14:47.071539 [CATrainingPosCal] consider 1 rank data
722 12:14:47.071620 u2DelayCellTimex100 = 270/100 ps
723 12:14:47.079234 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 12:14:47.082468 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 12:14:47.086293 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 12:14:47.090001 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 12:14:47.090095 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 12:14:47.093676 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
729 12:14:47.093778
730 12:14:47.100797 CA PerBit enable=1, Macro0, CA PI delay=34
731 12:14:47.100899
732 12:14:47.100980 [CBTSetCACLKResult] CA Dly = 34
733 12:14:47.104663 CS Dly: 6 (0~37)
734 12:14:47.104753 ==
735 12:14:47.108489 Dram Type= 6, Freq= 0, CH_0, rank 1
736 12:14:47.112381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 12:14:47.112463 ==
738 12:14:47.115688 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 12:14:47.122145 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 12:14:47.132494 [CA 0] Center 38 (7~69) winsize 63
741 12:14:47.135655 [CA 1] Center 38 (7~69) winsize 63
742 12:14:47.138974 [CA 2] Center 35 (5~66) winsize 62
743 12:14:47.142502 [CA 3] Center 35 (5~66) winsize 62
744 12:14:47.145474 [CA 4] Center 34 (4~65) winsize 62
745 12:14:47.149203 [CA 5] Center 34 (4~65) winsize 62
746 12:14:47.149301
747 12:14:47.151779 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 12:14:47.151895
749 12:14:47.155189 [CATrainingPosCal] consider 2 rank data
750 12:14:47.159060 u2DelayCellTimex100 = 270/100 ps
751 12:14:47.162472 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 12:14:47.168892 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 12:14:47.172307 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 12:14:47.175298 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 12:14:47.178781 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 12:14:47.181827 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 12:14:47.181939
758 12:14:47.185705 CA PerBit enable=1, Macro0, CA PI delay=34
759 12:14:47.185820
760 12:14:47.188797 [CBTSetCACLKResult] CA Dly = 34
761 12:14:47.188891 CS Dly: 6 (0~38)
762 12:14:47.188976
763 12:14:47.194975 ----->DramcWriteLeveling(PI) begin...
764 12:14:47.195065 ==
765 12:14:47.198729 Dram Type= 6, Freq= 0, CH_0, rank 0
766 12:14:47.201961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 12:14:47.202074 ==
768 12:14:47.204983 Write leveling (Byte 0): 31 => 31
769 12:14:47.208881 Write leveling (Byte 1): 31 => 31
770 12:14:47.211812 DramcWriteLeveling(PI) end<-----
771 12:14:47.211928
772 12:14:47.212034 ==
773 12:14:47.215099 Dram Type= 6, Freq= 0, CH_0, rank 0
774 12:14:47.218477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 12:14:47.218568 ==
776 12:14:47.221534 [Gating] SW mode calibration
777 12:14:47.228628 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 12:14:47.235246 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 12:14:47.238484 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 12:14:47.241870 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 12:14:47.248209 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 12:14:47.251476 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
783 12:14:47.254859 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 12:14:47.261347 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 12:14:47.265195 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 12:14:47.268382 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 12:14:47.271814 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 12:14:47.279120 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:14:47.282765 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:14:47.286335 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:14:47.289845 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:14:47.295925 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:14:47.299741 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:14:47.303344 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:14:47.307062 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:14:47.313685 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:14:47.316893 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
798 12:14:47.320144 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 12:14:47.326589 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:14:47.329835 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:14:47.333860 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:14:47.340211 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:14:47.343379 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:14:47.346427 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:14:47.353115 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:14:47.357103 0 9 12 | B1->B0 | 2828 3333 | 1 1 | (1 1) (1 1)
807 12:14:47.360180 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 12:14:47.366859 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 12:14:47.370054 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 12:14:47.373139 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 12:14:47.379899 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 12:14:47.383770 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 12:14:47.386792 0 10 8 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
814 12:14:47.393236 0 10 12 | B1->B0 | 2b2b 2424 | 0 0 | (0 1) (0 0)
815 12:14:47.396595 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:14:47.400216 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:14:47.406606 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:14:47.409600 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 12:14:47.413162 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 12:14:47.419465 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 12:14:47.422967 0 11 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
822 12:14:47.426434 0 11 12 | B1->B0 | 3333 4545 | 0 0 | (0 0) (1 1)
823 12:14:47.433040 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 12:14:47.436476 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 12:14:47.439525 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 12:14:47.446427 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 12:14:47.449551 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 12:14:47.452769 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 12:14:47.456271 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 12:14:47.463048 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
831 12:14:47.466046 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 12:14:47.469220 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 12:14:47.476090 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 12:14:47.479400 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 12:14:47.482383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 12:14:47.489526 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 12:14:47.492699 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:14:47.495851 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:14:47.502733 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:14:47.505980 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:14:47.508978 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:14:47.515555 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:14:47.519013 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:14:47.522601 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:14:47.529069 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 12:14:47.532184 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 12:14:47.535523 Total UI for P1: 0, mck2ui 16
848 12:14:47.538721 best dqsien dly found for B0: ( 0, 14, 8)
849 12:14:47.542256 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 12:14:47.548639 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 12:14:47.548723 Total UI for P1: 0, mck2ui 16
852 12:14:47.555448 best dqsien dly found for B1: ( 0, 14, 14)
853 12:14:47.558512 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
854 12:14:47.562104 best DQS1 dly(MCK, UI, PI) = (0, 14, 14)
855 12:14:47.562190
856 12:14:47.565265 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
857 12:14:47.568991 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 14)
858 12:14:47.572321 [Gating] SW calibration Done
859 12:14:47.572405 ==
860 12:14:47.575338 Dram Type= 6, Freq= 0, CH_0, rank 0
861 12:14:47.578876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
862 12:14:47.578960 ==
863 12:14:47.581799 RX Vref Scan: 0
864 12:14:47.581881
865 12:14:47.581947 RX Vref 0 -> 0, step: 1
866 12:14:47.582009
867 12:14:47.585532 RX Delay -130 -> 252, step: 16
868 12:14:47.591881 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
869 12:14:47.595068 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
870 12:14:47.598282 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
871 12:14:47.601918 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
872 12:14:47.605155 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
873 12:14:47.608464 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
874 12:14:47.615136 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
875 12:14:47.618617 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
876 12:14:47.621610 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
877 12:14:47.625090 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
878 12:14:47.631476 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
879 12:14:47.635134 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
880 12:14:47.638684 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
881 12:14:47.641937 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
882 12:14:47.644774 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
883 12:14:47.651405 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
884 12:14:47.651491 ==
885 12:14:47.655126 Dram Type= 6, Freq= 0, CH_0, rank 0
886 12:14:47.658356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
887 12:14:47.658440 ==
888 12:14:47.658507 DQS Delay:
889 12:14:47.661458 DQS0 = 0, DQS1 = 0
890 12:14:47.661542 DQM Delay:
891 12:14:47.665107 DQM0 = 80, DQM1 = 69
892 12:14:47.665191 DQ Delay:
893 12:14:47.667808 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
894 12:14:47.671381 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
895 12:14:47.674495 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
896 12:14:47.678154 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
897 12:14:47.678237
898 12:14:47.678302
899 12:14:47.678363 ==
900 12:14:47.681290 Dram Type= 6, Freq= 0, CH_0, rank 0
901 12:14:47.685245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
902 12:14:47.685330 ==
903 12:14:47.685397
904 12:14:47.685457
905 12:14:47.688417 TX Vref Scan disable
906 12:14:47.691706 == TX Byte 0 ==
907 12:14:47.694979 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
908 12:14:47.698246 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
909 12:14:47.701474 == TX Byte 1 ==
910 12:14:47.704641 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
911 12:14:47.707961 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
912 12:14:47.708049 ==
913 12:14:47.711691 Dram Type= 6, Freq= 0, CH_0, rank 0
914 12:14:47.717969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
915 12:14:47.718099 ==
916 12:14:47.729531 TX Vref=22, minBit 5, minWin=26, winSum=428
917 12:14:47.733305 TX Vref=24, minBit 11, minWin=26, winSum=436
918 12:14:47.736480 TX Vref=26, minBit 0, minWin=27, winSum=437
919 12:14:47.739574 TX Vref=28, minBit 9, minWin=27, winSum=443
920 12:14:47.743146 TX Vref=30, minBit 9, minWin=27, winSum=441
921 12:14:47.749852 TX Vref=32, minBit 12, minWin=26, winSum=441
922 12:14:47.753023 [TxChooseVref] Worse bit 9, Min win 27, Win sum 443, Final Vref 28
923 12:14:47.753112
924 12:14:47.755987 Final TX Range 1 Vref 28
925 12:14:47.756132
926 12:14:47.756230 ==
927 12:14:47.759286 Dram Type= 6, Freq= 0, CH_0, rank 0
928 12:14:47.762900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 12:14:47.766172 ==
930 12:14:47.766258
931 12:14:47.766324
932 12:14:47.766386 TX Vref Scan disable
933 12:14:47.769977 == TX Byte 0 ==
934 12:14:47.772965 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
935 12:14:47.779534 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
936 12:14:47.779631 == TX Byte 1 ==
937 12:14:47.782716 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
938 12:14:47.789803 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
939 12:14:47.789910
940 12:14:47.790090 [DATLAT]
941 12:14:47.790179 Freq=800, CH0 RK0
942 12:14:47.790267
943 12:14:47.793122 DATLAT Default: 0xa
944 12:14:47.793191 0, 0xFFFF, sum = 0
945 12:14:47.796352 1, 0xFFFF, sum = 0
946 12:14:47.796438 2, 0xFFFF, sum = 0
947 12:14:47.799516 3, 0xFFFF, sum = 0
948 12:14:47.802949 4, 0xFFFF, sum = 0
949 12:14:47.803032 5, 0xFFFF, sum = 0
950 12:14:47.806622 6, 0xFFFF, sum = 0
951 12:14:47.806705 7, 0xFFFF, sum = 0
952 12:14:47.810091 8, 0xFFFF, sum = 0
953 12:14:47.810175 9, 0x0, sum = 1
954 12:14:47.810241 10, 0x0, sum = 2
955 12:14:47.813101 11, 0x0, sum = 3
956 12:14:47.813245 12, 0x0, sum = 4
957 12:14:47.816298 best_step = 10
958 12:14:47.816381
959 12:14:47.816482 ==
960 12:14:47.819885 Dram Type= 6, Freq= 0, CH_0, rank 0
961 12:14:47.823115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
962 12:14:47.823190 ==
963 12:14:47.826352 RX Vref Scan: 1
964 12:14:47.826433
965 12:14:47.826498 Set Vref Range= 32 -> 127
966 12:14:47.826559
967 12:14:47.829942 RX Vref 32 -> 127, step: 1
968 12:14:47.830024
969 12:14:47.833288 RX Delay -111 -> 252, step: 8
970 12:14:47.833371
971 12:14:47.836190 Set Vref, RX VrefLevel [Byte0]: 32
972 12:14:47.839994 [Byte1]: 32
973 12:14:47.840088
974 12:14:47.842848 Set Vref, RX VrefLevel [Byte0]: 33
975 12:14:47.845956 [Byte1]: 33
976 12:14:47.850145
977 12:14:47.850281 Set Vref, RX VrefLevel [Byte0]: 34
978 12:14:47.853478 [Byte1]: 34
979 12:14:47.857726
980 12:14:47.857807 Set Vref, RX VrefLevel [Byte0]: 35
981 12:14:47.860780 [Byte1]: 35
982 12:14:47.865482
983 12:14:47.865607 Set Vref, RX VrefLevel [Byte0]: 36
984 12:14:47.868509 [Byte1]: 36
985 12:14:47.873004
986 12:14:47.873138 Set Vref, RX VrefLevel [Byte0]: 37
987 12:14:47.876654 [Byte1]: 37
988 12:14:47.881059
989 12:14:47.881223 Set Vref, RX VrefLevel [Byte0]: 38
990 12:14:47.884222 [Byte1]: 38
991 12:14:47.888532
992 12:14:47.888651 Set Vref, RX VrefLevel [Byte0]: 39
993 12:14:47.891832 [Byte1]: 39
994 12:14:47.896215
995 12:14:47.896324 Set Vref, RX VrefLevel [Byte0]: 40
996 12:14:47.899366 [Byte1]: 40
997 12:14:47.904102
998 12:14:47.904187 Set Vref, RX VrefLevel [Byte0]: 41
999 12:14:47.907258 [Byte1]: 41
1000 12:14:47.911032
1001 12:14:47.911143 Set Vref, RX VrefLevel [Byte0]: 42
1002 12:14:47.914675 [Byte1]: 42
1003 12:14:47.919339
1004 12:14:47.919446 Set Vref, RX VrefLevel [Byte0]: 43
1005 12:14:47.922401 [Byte1]: 43
1006 12:14:47.926885
1007 12:14:47.926966 Set Vref, RX VrefLevel [Byte0]: 44
1008 12:14:47.930143 [Byte1]: 44
1009 12:14:47.934613
1010 12:14:47.934741 Set Vref, RX VrefLevel [Byte0]: 45
1011 12:14:47.937880 [Byte1]: 45
1012 12:14:47.942393
1013 12:14:47.942482 Set Vref, RX VrefLevel [Byte0]: 46
1014 12:14:47.945562 [Byte1]: 46
1015 12:14:47.949741
1016 12:14:47.949828 Set Vref, RX VrefLevel [Byte0]: 47
1017 12:14:47.953326 [Byte1]: 47
1018 12:14:47.958176
1019 12:14:47.958289 Set Vref, RX VrefLevel [Byte0]: 48
1020 12:14:47.960505 [Byte1]: 48
1021 12:14:47.964663
1022 12:14:47.967764 Set Vref, RX VrefLevel [Byte0]: 49
1023 12:14:47.971535 [Byte1]: 49
1024 12:14:47.971621
1025 12:14:47.974495 Set Vref, RX VrefLevel [Byte0]: 50
1026 12:14:47.978156 [Byte1]: 50
1027 12:14:47.978237
1028 12:14:47.981266 Set Vref, RX VrefLevel [Byte0]: 51
1029 12:14:47.984395 [Byte1]: 51
1030 12:14:47.984482
1031 12:14:47.987767 Set Vref, RX VrefLevel [Byte0]: 52
1032 12:14:47.990985 [Byte1]: 52
1033 12:14:47.995718
1034 12:14:47.995807 Set Vref, RX VrefLevel [Byte0]: 53
1035 12:14:47.998711 [Byte1]: 53
1036 12:14:48.002824
1037 12:14:48.002917 Set Vref, RX VrefLevel [Byte0]: 54
1038 12:14:48.006708 [Byte1]: 54
1039 12:14:48.010747
1040 12:14:48.010840 Set Vref, RX VrefLevel [Byte0]: 55
1041 12:14:48.013924 [Byte1]: 55
1042 12:14:48.018623
1043 12:14:48.018709 Set Vref, RX VrefLevel [Byte0]: 56
1044 12:14:48.021761 [Byte1]: 56
1045 12:14:48.025945
1046 12:14:48.029226 Set Vref, RX VrefLevel [Byte0]: 57
1047 12:14:48.029305 [Byte1]: 57
1048 12:14:48.033819
1049 12:14:48.033903 Set Vref, RX VrefLevel [Byte0]: 58
1050 12:14:48.036975 [Byte1]: 58
1051 12:14:48.041481
1052 12:14:48.041565 Set Vref, RX VrefLevel [Byte0]: 59
1053 12:14:48.044491 [Byte1]: 59
1054 12:14:48.049051
1055 12:14:48.049133 Set Vref, RX VrefLevel [Byte0]: 60
1056 12:14:48.052139 [Byte1]: 60
1057 12:14:48.056366
1058 12:14:48.056475 Set Vref, RX VrefLevel [Byte0]: 61
1059 12:14:48.060018 [Byte1]: 61
1060 12:14:48.064174
1061 12:14:48.064257 Set Vref, RX VrefLevel [Byte0]: 62
1062 12:14:48.067682 [Byte1]: 62
1063 12:14:48.071784
1064 12:14:48.071866 Set Vref, RX VrefLevel [Byte0]: 63
1065 12:14:48.075559 [Byte1]: 63
1066 12:14:48.079241
1067 12:14:48.079347 Set Vref, RX VrefLevel [Byte0]: 64
1068 12:14:48.082904 [Byte1]: 64
1069 12:14:48.087184
1070 12:14:48.087296 Set Vref, RX VrefLevel [Byte0]: 65
1071 12:14:48.090448 [Byte1]: 65
1072 12:14:48.095132
1073 12:14:48.095215 Set Vref, RX VrefLevel [Byte0]: 66
1074 12:14:48.098388 [Byte1]: 66
1075 12:14:48.102343
1076 12:14:48.102425 Set Vref, RX VrefLevel [Byte0]: 67
1077 12:14:48.105602 [Byte1]: 67
1078 12:14:48.110256
1079 12:14:48.110339 Set Vref, RX VrefLevel [Byte0]: 68
1080 12:14:48.113485 [Byte1]: 68
1081 12:14:48.117923
1082 12:14:48.118005 Set Vref, RX VrefLevel [Byte0]: 69
1083 12:14:48.121190 [Byte1]: 69
1084 12:14:48.125565
1085 12:14:48.125647 Set Vref, RX VrefLevel [Byte0]: 70
1086 12:14:48.128685 [Byte1]: 70
1087 12:14:48.133052
1088 12:14:48.133134 Set Vref, RX VrefLevel [Byte0]: 71
1089 12:14:48.136290 [Byte1]: 71
1090 12:14:48.140835
1091 12:14:48.140915 Set Vref, RX VrefLevel [Byte0]: 72
1092 12:14:48.143821 [Byte1]: 72
1093 12:14:48.148395
1094 12:14:48.148478 Set Vref, RX VrefLevel [Byte0]: 73
1095 12:14:48.151815 [Byte1]: 73
1096 12:14:48.155922
1097 12:14:48.156015 Set Vref, RX VrefLevel [Byte0]: 74
1098 12:14:48.159182 [Byte1]: 74
1099 12:14:48.163358
1100 12:14:48.163468 Set Vref, RX VrefLevel [Byte0]: 75
1101 12:14:48.166980 [Byte1]: 75
1102 12:14:48.171575
1103 12:14:48.171657 Set Vref, RX VrefLevel [Byte0]: 76
1104 12:14:48.174616 [Byte1]: 76
1105 12:14:48.178740
1106 12:14:48.178869 Set Vref, RX VrefLevel [Byte0]: 77
1107 12:14:48.182443 [Byte1]: 77
1108 12:14:48.186795
1109 12:14:48.186916 Set Vref, RX VrefLevel [Byte0]: 78
1110 12:14:48.189825 [Byte1]: 78
1111 12:14:48.194209
1112 12:14:48.194291 Set Vref, RX VrefLevel [Byte0]: 79
1113 12:14:48.197802 [Byte1]: 79
1114 12:14:48.201903
1115 12:14:48.202000 Final RX Vref Byte 0 = 55 to rank0
1116 12:14:48.205003 Final RX Vref Byte 1 = 58 to rank0
1117 12:14:48.208157 Final RX Vref Byte 0 = 55 to rank1
1118 12:14:48.211464 Final RX Vref Byte 1 = 58 to rank1==
1119 12:14:48.215015 Dram Type= 6, Freq= 0, CH_0, rank 0
1120 12:14:48.222014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1121 12:14:48.222093 ==
1122 12:14:48.222158 DQS Delay:
1123 12:14:48.222216 DQS0 = 0, DQS1 = 0
1124 12:14:48.225183 DQM Delay:
1125 12:14:48.225257 DQM0 = 82, DQM1 = 68
1126 12:14:48.228477 DQ Delay:
1127 12:14:48.231684 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1128 12:14:48.235125 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1129 12:14:48.238333 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =64
1130 12:14:48.241623 DQ12 =72, DQ13 =76, DQ14 =76, DQ15 =76
1131 12:14:48.241698
1132 12:14:48.241758
1133 12:14:48.248540 [DQSOSCAuto] RK0, (LSB)MR18= 0x2423, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1134 12:14:48.251559 CH0 RK0: MR19=606, MR18=2423
1135 12:14:48.258402 CH0_RK0: MR19=0x606, MR18=0x2423, DQSOSC=400, MR23=63, INC=92, DEC=61
1136 12:14:48.258480
1137 12:14:48.261306 ----->DramcWriteLeveling(PI) begin...
1138 12:14:48.261407 ==
1139 12:14:48.265050 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 12:14:48.268130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 12:14:48.268213 ==
1142 12:14:48.271543 Write leveling (Byte 0): 32 => 32
1143 12:14:48.274528 Write leveling (Byte 1): 32 => 32
1144 12:14:48.278038 DramcWriteLeveling(PI) end<-----
1145 12:14:48.278121
1146 12:14:48.278184 ==
1147 12:14:48.281839 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 12:14:48.285309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 12:14:48.285391 ==
1150 12:14:48.287899 [Gating] SW mode calibration
1151 12:14:48.294644 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1152 12:14:48.301607 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1153 12:14:48.304560 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 12:14:48.307805 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 12:14:48.314785 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1156 12:14:48.317768 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:14:48.321493 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:14:48.327679 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:14:48.331504 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:14:48.334505 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:14:48.341202 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:14:48.344441 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:14:48.347684 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:14:48.395197 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:14:48.395343 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:14:48.395409 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:14:48.395671 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:14:48.395749 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:14:48.395811 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:14:48.395868 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1171 12:14:48.396015 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1172 12:14:48.396112 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:14:48.396222 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:14:48.439117 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:14:48.439247 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:14:48.439342 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:14:48.439647 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:14:48.439720 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:14:48.439825 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
1180 12:14:48.439903 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1181 12:14:48.439965 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:14:48.440021 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:14:48.440087 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:14:48.473779 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:14:48.473903 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:14:48.474174 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 1)
1187 12:14:48.474243 0 10 8 | B1->B0 | 3333 2626 | 0 0 | (0 1) (0 0)
1188 12:14:48.474307 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:14:48.474452 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:14:48.474533 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:14:48.474783 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:14:48.477974 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:14:48.481455 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:14:48.484339 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1195 12:14:48.491122 0 11 8 | B1->B0 | 3535 3e3e | 0 0 | (0 0) (0 0)
1196 12:14:48.494504 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1197 12:14:48.498014 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:14:48.504275 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:14:48.507882 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:14:48.511104 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:14:48.514591 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:14:48.522267 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1203 12:14:48.526118 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1204 12:14:48.529340 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1205 12:14:48.532406 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:14:48.539167 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:14:48.542990 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:14:48.546518 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:14:48.550005 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:14:48.556151 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:14:48.559448 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:14:48.563125 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:14:48.569484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:14:48.572958 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:14:48.576160 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:14:48.582431 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:14:48.585991 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:14:48.589048 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1219 12:14:48.596080 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1220 12:14:48.599546 Total UI for P1: 0, mck2ui 16
1221 12:14:48.602671 best dqsien dly found for B0: ( 0, 14, 4)
1222 12:14:48.605685 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1223 12:14:48.609524 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 12:14:48.612415 Total UI for P1: 0, mck2ui 16
1225 12:14:48.615905 best dqsien dly found for B1: ( 0, 14, 10)
1226 12:14:48.619076 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1227 12:14:48.622271 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1228 12:14:48.625756
1229 12:14:48.629321 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1230 12:14:48.632505 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1231 12:14:48.635481 [Gating] SW calibration Done
1232 12:14:48.635563 ==
1233 12:14:48.639354 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 12:14:48.642512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 12:14:48.642619 ==
1236 12:14:48.642711 RX Vref Scan: 0
1237 12:14:48.645704
1238 12:14:48.645784 RX Vref 0 -> 0, step: 1
1239 12:14:48.645849
1240 12:14:48.648900 RX Delay -130 -> 252, step: 16
1241 12:14:48.652326 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1242 12:14:48.658854 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1243 12:14:48.662001 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1244 12:14:48.665401 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1245 12:14:48.668353 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1246 12:14:48.672071 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1247 12:14:48.678767 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1248 12:14:48.681950 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1249 12:14:48.685011 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1250 12:14:48.688697 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1251 12:14:48.691884 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1252 12:14:48.698420 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1253 12:14:48.702002 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1254 12:14:48.705193 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1255 12:14:48.708577 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1256 12:14:48.711512 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1257 12:14:48.714946 ==
1258 12:14:48.718379 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 12:14:48.721628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 12:14:48.721711 ==
1261 12:14:48.721776 DQS Delay:
1262 12:14:48.724763 DQS0 = 0, DQS1 = 0
1263 12:14:48.724845 DQM Delay:
1264 12:14:48.727855 DQM0 = 76, DQM1 = 69
1265 12:14:48.727938 DQ Delay:
1266 12:14:48.731552 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1267 12:14:48.734707 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1268 12:14:48.737883 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1269 12:14:48.741505 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1270 12:14:48.741588
1271 12:14:48.741652
1272 12:14:48.741713 ==
1273 12:14:48.744528 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 12:14:48.747607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 12:14:48.747690 ==
1276 12:14:48.747755
1277 12:14:48.747818
1278 12:14:48.751422 TX Vref Scan disable
1279 12:14:48.754570 == TX Byte 0 ==
1280 12:14:48.757702 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1281 12:14:48.761253 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1282 12:14:48.764439 == TX Byte 1 ==
1283 12:14:48.767720 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1284 12:14:48.770744 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1285 12:14:48.770849 ==
1286 12:14:48.774498 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 12:14:48.780802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 12:14:48.780886 ==
1289 12:14:48.792438 TX Vref=22, minBit 0, minWin=27, winSum=437
1290 12:14:48.795476 TX Vref=24, minBit 11, minWin=26, winSum=436
1291 12:14:48.799020 TX Vref=26, minBit 1, minWin=27, winSum=441
1292 12:14:48.802389 TX Vref=28, minBit 1, minWin=27, winSum=439
1293 12:14:48.805425 TX Vref=30, minBit 1, minWin=27, winSum=441
1294 12:14:48.812151 TX Vref=32, minBit 2, minWin=27, winSum=442
1295 12:14:48.815665 [TxChooseVref] Worse bit 2, Min win 27, Win sum 442, Final Vref 32
1296 12:14:48.815746
1297 12:14:48.818727 Final TX Range 1 Vref 32
1298 12:14:48.818839
1299 12:14:48.818937 ==
1300 12:14:48.822244 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 12:14:48.825342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 12:14:48.828476 ==
1303 12:14:48.828557
1304 12:14:48.828620
1305 12:14:48.828678 TX Vref Scan disable
1306 12:14:48.832322 == TX Byte 0 ==
1307 12:14:48.835828 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1308 12:14:48.842504 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1309 12:14:48.842585 == TX Byte 1 ==
1310 12:14:48.845533 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1311 12:14:48.852208 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1312 12:14:48.852288
1313 12:14:48.852351 [DATLAT]
1314 12:14:48.852410 Freq=800, CH0 RK1
1315 12:14:48.852466
1316 12:14:48.855435 DATLAT Default: 0xa
1317 12:14:48.855515 0, 0xFFFF, sum = 0
1318 12:14:48.859073 1, 0xFFFF, sum = 0
1319 12:14:48.859155 2, 0xFFFF, sum = 0
1320 12:14:48.862212 3, 0xFFFF, sum = 0
1321 12:14:48.865693 4, 0xFFFF, sum = 0
1322 12:14:48.865777 5, 0xFFFF, sum = 0
1323 12:14:48.868967 6, 0xFFFF, sum = 0
1324 12:14:48.869049 7, 0xFFFF, sum = 0
1325 12:14:48.872213 8, 0xFFFF, sum = 0
1326 12:14:48.872299 9, 0x0, sum = 1
1327 12:14:48.875643 10, 0x0, sum = 2
1328 12:14:48.875725 11, 0x0, sum = 3
1329 12:14:48.875790 12, 0x0, sum = 4
1330 12:14:48.878863 best_step = 10
1331 12:14:48.878958
1332 12:14:48.879020 ==
1333 12:14:48.881874 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 12:14:48.885483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 12:14:48.885564 ==
1336 12:14:48.888538 RX Vref Scan: 0
1337 12:14:48.888619
1338 12:14:48.888681 RX Vref 0 -> 0, step: 1
1339 12:14:48.891819
1340 12:14:48.891898 RX Delay -111 -> 252, step: 8
1341 12:14:48.898779 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1342 12:14:48.902511 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1343 12:14:48.905541 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1344 12:14:48.909019 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1345 12:14:48.911999 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1346 12:14:48.919109 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1347 12:14:48.922013 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1348 12:14:48.925498 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1349 12:14:48.929146 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1350 12:14:48.931981 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1351 12:14:48.938965 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1352 12:14:48.942299 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1353 12:14:48.945725 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1354 12:14:48.948805 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1355 12:14:48.955460 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1356 12:14:48.958507 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1357 12:14:48.958587 ==
1358 12:14:48.961679 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 12:14:48.965474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 12:14:48.965556 ==
1361 12:14:48.968454 DQS Delay:
1362 12:14:48.968533 DQS0 = 0, DQS1 = 0
1363 12:14:48.968595 DQM Delay:
1364 12:14:48.972157 DQM0 = 79, DQM1 = 71
1365 12:14:48.972237 DQ Delay:
1366 12:14:48.975150 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =76
1367 12:14:48.978275 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1368 12:14:48.982053 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1369 12:14:48.985233 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =80
1370 12:14:48.985312
1371 12:14:48.985375
1372 12:14:48.995179 [DQSOSCAuto] RK1, (LSB)MR18= 0x4822, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1373 12:14:48.995261 CH0 RK1: MR19=606, MR18=4822
1374 12:14:49.001459 CH0_RK1: MR19=0x606, MR18=0x4822, DQSOSC=391, MR23=63, INC=96, DEC=64
1375 12:14:49.004925 [RxdqsGatingPostProcess] freq 800
1376 12:14:49.011798 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 12:14:49.014766 Pre-setting of DQS Precalculation
1378 12:14:49.018260 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 12:14:49.018341 ==
1380 12:14:49.021179 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 12:14:49.028245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 12:14:49.028326 ==
1383 12:14:49.031262 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 12:14:49.037876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 12:14:49.047692 [CA 0] Center 36 (6~67) winsize 62
1386 12:14:49.050874 [CA 1] Center 36 (6~67) winsize 62
1387 12:14:49.053902 [CA 2] Center 34 (5~64) winsize 60
1388 12:14:49.057278 [CA 3] Center 34 (4~64) winsize 61
1389 12:14:49.061032 [CA 4] Center 34 (4~64) winsize 61
1390 12:14:49.063672 [CA 5] Center 34 (4~64) winsize 61
1391 12:14:49.063754
1392 12:14:49.067343 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1393 12:14:49.067426
1394 12:14:49.070411 [CATrainingPosCal] consider 1 rank data
1395 12:14:49.073981 u2DelayCellTimex100 = 270/100 ps
1396 12:14:49.077053 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 12:14:49.083901 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 12:14:49.087041 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1399 12:14:49.090336 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 12:14:49.094045 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1401 12:14:49.096918 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1402 12:14:49.096999
1403 12:14:49.100700 CA PerBit enable=1, Macro0, CA PI delay=34
1404 12:14:49.100781
1405 12:14:49.103978 [CBTSetCACLKResult] CA Dly = 34
1406 12:14:49.104058 CS Dly: 5 (0~36)
1407 12:14:49.106982 ==
1408 12:14:49.110214 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 12:14:49.113326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 12:14:49.113407 ==
1411 12:14:49.117050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 12:14:49.123536 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 12:14:49.133476 [CA 0] Center 37 (7~67) winsize 61
1414 12:14:49.136583 [CA 1] Center 36 (6~67) winsize 62
1415 12:14:49.140184 [CA 2] Center 35 (5~65) winsize 61
1416 12:14:49.143648 [CA 3] Center 34 (4~64) winsize 61
1417 12:14:49.146930 [CA 4] Center 34 (4~65) winsize 62
1418 12:14:49.149956 [CA 5] Center 33 (3~64) winsize 62
1419 12:14:49.150037
1420 12:14:49.153325 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1421 12:14:49.153407
1422 12:14:49.157241 [CATrainingPosCal] consider 2 rank data
1423 12:14:49.160093 u2DelayCellTimex100 = 270/100 ps
1424 12:14:49.163594 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1425 12:14:49.170060 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 12:14:49.173507 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1427 12:14:49.177439 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 12:14:49.180872 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 12:14:49.184591 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1430 12:14:49.184676
1431 12:14:49.188353 CA PerBit enable=1, Macro0, CA PI delay=34
1432 12:14:49.188439
1433 12:14:49.188504 [CBTSetCACLKResult] CA Dly = 34
1434 12:14:49.192230 CS Dly: 6 (0~38)
1435 12:14:49.192314
1436 12:14:49.195712 ----->DramcWriteLeveling(PI) begin...
1437 12:14:49.195798 ==
1438 12:14:49.199287 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 12:14:49.202669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 12:14:49.202753 ==
1441 12:14:49.206164 Write leveling (Byte 0): 31 => 31
1442 12:14:49.209300 Write leveling (Byte 1): 31 => 31
1443 12:14:49.213046 DramcWriteLeveling(PI) end<-----
1444 12:14:49.213128
1445 12:14:49.213192 ==
1446 12:14:49.216207 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 12:14:49.219687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 12:14:49.219769 ==
1449 12:14:49.222707 [Gating] SW mode calibration
1450 12:14:49.229439 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 12:14:49.235827 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 12:14:49.239312 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 12:14:49.242860 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1454 12:14:49.249436 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 12:14:49.252614 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:14:49.256322 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:14:49.262570 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:14:49.265754 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:14:49.269504 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:14:49.276091 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:14:49.279109 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:14:49.282645 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:14:49.289177 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:14:49.292850 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:14:49.296141 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:14:49.302296 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:14:49.305360 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:14:49.309023 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:14:49.315332 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1470 12:14:49.319051 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1471 12:14:49.322187 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:14:49.328968 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:14:49.332005 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:14:49.334956 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:14:49.341710 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:14:49.345477 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:14:49.348354 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:14:49.355106 0 9 8 | B1->B0 | 2a2a 2929 | 1 0 | (1 1) (0 0)
1479 12:14:49.358732 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:14:49.361929 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:14:49.365550 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:14:49.371909 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:14:49.374972 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:14:49.378663 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 12:14:49.385445 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 12:14:49.388350 0 10 8 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (1 0)
1487 12:14:49.391892 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:14:49.398305 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:14:49.401583 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:14:49.404771 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:14:49.411648 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:14:49.414746 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:14:49.418406 0 11 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1494 12:14:49.425218 0 11 8 | B1->B0 | 3636 4141 | 0 0 | (0 0) (0 0)
1495 12:14:49.428321 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:14:49.431500 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:14:49.438194 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:14:49.441128 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:14:49.444673 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:14:49.451150 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 12:14:49.454545 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 12:14:49.458140 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1503 12:14:49.464480 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:14:49.467829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:14:49.471455 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:14:49.478120 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:14:49.481052 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:14:49.484743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:14:49.491295 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:14:49.494284 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:14:49.497744 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:14:49.504429 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:14:49.507505 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:14:49.511279 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:14:49.517401 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:14:49.521411 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:14:49.524253 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1518 12:14:49.531226 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1519 12:14:49.531309 Total UI for P1: 0, mck2ui 16
1520 12:14:49.534483 best dqsien dly found for B0: ( 0, 14, 6)
1521 12:14:49.540647 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 12:14:49.544421 Total UI for P1: 0, mck2ui 16
1523 12:14:49.547565 best dqsien dly found for B1: ( 0, 14, 6)
1524 12:14:49.550723 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1525 12:14:49.554415 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1526 12:14:49.554496
1527 12:14:49.557147 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1528 12:14:49.560641 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1529 12:14:49.564075 [Gating] SW calibration Done
1530 12:14:49.564156 ==
1531 12:14:49.567149 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 12:14:49.570685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 12:14:49.570766 ==
1534 12:14:49.573643 RX Vref Scan: 0
1535 12:14:49.573724
1536 12:14:49.577351 RX Vref 0 -> 0, step: 1
1537 12:14:49.577432
1538 12:14:49.577501 RX Delay -130 -> 252, step: 16
1539 12:14:49.584098 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1540 12:14:49.587125 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1541 12:14:49.590294 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1542 12:14:49.593921 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1543 12:14:49.596962 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1544 12:14:49.603924 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1545 12:14:49.607141 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1546 12:14:49.610762 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1547 12:14:49.613791 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1548 12:14:49.616964 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1549 12:14:49.623708 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1550 12:14:49.626788 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1551 12:14:49.630456 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1552 12:14:49.633597 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1553 12:14:49.640336 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1554 12:14:49.643492 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1555 12:14:49.643573 ==
1556 12:14:49.646864 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 12:14:49.650445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 12:14:49.650527 ==
1559 12:14:49.650592 DQS Delay:
1560 12:14:49.653566 DQS0 = 0, DQS1 = 0
1561 12:14:49.653647 DQM Delay:
1562 12:14:49.656696 DQM0 = 80, DQM1 = 70
1563 12:14:49.656777 DQ Delay:
1564 12:14:49.659823 DQ0 =85, DQ1 =77, DQ2 =61, DQ3 =77
1565 12:14:49.663520 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1566 12:14:49.666531 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1567 12:14:49.669860 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1568 12:14:49.669940
1569 12:14:49.670003
1570 12:14:49.670061 ==
1571 12:14:49.673324 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 12:14:49.676284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 12:14:49.679698 ==
1574 12:14:49.679778
1575 12:14:49.679842
1576 12:14:49.679900 TX Vref Scan disable
1577 12:14:49.683121 == TX Byte 0 ==
1578 12:14:49.686638 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1579 12:14:49.689610 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1580 12:14:49.693236 == TX Byte 1 ==
1581 12:14:49.696388 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1582 12:14:49.700335 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1583 12:14:49.703175 ==
1584 12:14:49.706194 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 12:14:49.709806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 12:14:49.709890 ==
1587 12:14:49.722211 TX Vref=22, minBit 0, minWin=27, winSum=439
1588 12:14:49.725360 TX Vref=24, minBit 1, minWin=26, winSum=440
1589 12:14:49.728395 TX Vref=26, minBit 7, minWin=27, winSum=445
1590 12:14:49.732157 TX Vref=28, minBit 1, minWin=27, winSum=446
1591 12:14:49.735258 TX Vref=30, minBit 9, minWin=27, winSum=448
1592 12:14:49.742033 TX Vref=32, minBit 9, minWin=27, winSum=450
1593 12:14:49.745184 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 32
1594 12:14:49.745283
1595 12:14:49.748862 Final TX Range 1 Vref 32
1596 12:14:49.748960
1597 12:14:49.749058 ==
1598 12:14:49.752661 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 12:14:49.755792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 12:14:49.755875 ==
1601 12:14:49.755955
1602 12:14:49.756049
1603 12:14:49.758922 TX Vref Scan disable
1604 12:14:49.762024 == TX Byte 0 ==
1605 12:14:49.765249 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1606 12:14:49.768890 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1607 12:14:49.771936 == TX Byte 1 ==
1608 12:14:49.775710 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1609 12:14:49.778550 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1610 12:14:49.782215
1611 12:14:49.782299 [DATLAT]
1612 12:14:49.782364 Freq=800, CH1 RK0
1613 12:14:49.782426
1614 12:14:49.785462 DATLAT Default: 0xa
1615 12:14:49.785545 0, 0xFFFF, sum = 0
1616 12:14:49.788889 1, 0xFFFF, sum = 0
1617 12:14:49.788975 2, 0xFFFF, sum = 0
1618 12:14:49.791790 3, 0xFFFF, sum = 0
1619 12:14:49.791874 4, 0xFFFF, sum = 0
1620 12:14:49.795232 5, 0xFFFF, sum = 0
1621 12:14:49.798321 6, 0xFFFF, sum = 0
1622 12:14:49.798404 7, 0xFFFF, sum = 0
1623 12:14:49.801966 8, 0xFFFF, sum = 0
1624 12:14:49.802049 9, 0x0, sum = 1
1625 12:14:49.802116 10, 0x0, sum = 2
1626 12:14:49.805177 11, 0x0, sum = 3
1627 12:14:49.805260 12, 0x0, sum = 4
1628 12:14:49.808782 best_step = 10
1629 12:14:49.808893
1630 12:14:49.808962 ==
1631 12:14:49.811946 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 12:14:49.815500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 12:14:49.815583 ==
1634 12:14:49.818488 RX Vref Scan: 1
1635 12:14:49.818570
1636 12:14:49.818635 Set Vref Range= 32 -> 127
1637 12:14:49.821840
1638 12:14:49.821922 RX Vref 32 -> 127, step: 1
1639 12:14:49.821987
1640 12:14:49.825183 RX Delay -111 -> 252, step: 8
1641 12:14:49.825266
1642 12:14:49.828758 Set Vref, RX VrefLevel [Byte0]: 32
1643 12:14:49.831825 [Byte1]: 32
1644 12:14:49.834773
1645 12:14:49.834862 Set Vref, RX VrefLevel [Byte0]: 33
1646 12:14:49.838480 [Byte1]: 33
1647 12:14:49.842752
1648 12:14:49.842866 Set Vref, RX VrefLevel [Byte0]: 34
1649 12:14:49.845984 [Byte1]: 34
1650 12:14:49.850413
1651 12:14:49.850522 Set Vref, RX VrefLevel [Byte0]: 35
1652 12:14:49.853641 [Byte1]: 35
1653 12:14:49.857969
1654 12:14:49.858052 Set Vref, RX VrefLevel [Byte0]: 36
1655 12:14:49.861191 [Byte1]: 36
1656 12:14:49.865627
1657 12:14:49.865710 Set Vref, RX VrefLevel [Byte0]: 37
1658 12:14:49.868800 [Byte1]: 37
1659 12:14:49.873131
1660 12:14:49.873213 Set Vref, RX VrefLevel [Byte0]: 38
1661 12:14:49.876642 [Byte1]: 38
1662 12:14:49.880918
1663 12:14:49.881000 Set Vref, RX VrefLevel [Byte0]: 39
1664 12:14:49.883995 [Byte1]: 39
1665 12:14:49.888087
1666 12:14:49.888168 Set Vref, RX VrefLevel [Byte0]: 40
1667 12:14:49.891670 [Byte1]: 40
1668 12:14:49.895784
1669 12:14:49.895866 Set Vref, RX VrefLevel [Byte0]: 41
1670 12:14:49.899351 [Byte1]: 41
1671 12:14:49.903506
1672 12:14:49.903588 Set Vref, RX VrefLevel [Byte0]: 42
1673 12:14:49.907181 [Byte1]: 42
1674 12:14:49.911811
1675 12:14:49.911893 Set Vref, RX VrefLevel [Byte0]: 43
1676 12:14:49.914714 [Byte1]: 43
1677 12:14:49.919104
1678 12:14:49.919186 Set Vref, RX VrefLevel [Byte0]: 44
1679 12:14:49.922175 [Byte1]: 44
1680 12:14:49.926396
1681 12:14:49.926479 Set Vref, RX VrefLevel [Byte0]: 45
1682 12:14:49.930009 [Byte1]: 45
1683 12:14:49.934504
1684 12:14:49.934586 Set Vref, RX VrefLevel [Byte0]: 46
1685 12:14:49.937434 [Byte1]: 46
1686 12:14:49.941838
1687 12:14:49.941920 Set Vref, RX VrefLevel [Byte0]: 47
1688 12:14:49.944903 [Byte1]: 47
1689 12:14:49.949352
1690 12:14:49.949435 Set Vref, RX VrefLevel [Byte0]: 48
1691 12:14:49.953046 [Byte1]: 48
1692 12:14:49.957521
1693 12:14:49.957603 Set Vref, RX VrefLevel [Byte0]: 49
1694 12:14:49.960570 [Byte1]: 49
1695 12:14:49.964995
1696 12:14:49.965077 Set Vref, RX VrefLevel [Byte0]: 50
1697 12:14:49.968101 [Byte1]: 50
1698 12:14:49.972536
1699 12:14:49.972619 Set Vref, RX VrefLevel [Byte0]: 51
1700 12:14:49.975532 [Byte1]: 51
1701 12:14:49.980372
1702 12:14:49.980453 Set Vref, RX VrefLevel [Byte0]: 52
1703 12:14:49.983315 [Byte1]: 52
1704 12:14:49.987551
1705 12:14:49.987633 Set Vref, RX VrefLevel [Byte0]: 53
1706 12:14:49.991251 [Byte1]: 53
1707 12:14:49.995323
1708 12:14:49.995409 Set Vref, RX VrefLevel [Byte0]: 54
1709 12:14:49.998807 [Byte1]: 54
1710 12:14:50.003019
1711 12:14:50.003101 Set Vref, RX VrefLevel [Byte0]: 55
1712 12:14:50.006560 [Byte1]: 55
1713 12:14:50.010462
1714 12:14:50.010544 Set Vref, RX VrefLevel [Byte0]: 56
1715 12:14:50.014449 [Byte1]: 56
1716 12:14:50.018755
1717 12:14:50.018858 Set Vref, RX VrefLevel [Byte0]: 57
1718 12:14:50.022116 [Byte1]: 57
1719 12:14:50.025763
1720 12:14:50.025845 Set Vref, RX VrefLevel [Byte0]: 58
1721 12:14:50.032336 [Byte1]: 58
1722 12:14:50.032419
1723 12:14:50.035906 Set Vref, RX VrefLevel [Byte0]: 59
1724 12:14:50.039216 [Byte1]: 59
1725 12:14:50.039299
1726 12:14:50.042626 Set Vref, RX VrefLevel [Byte0]: 60
1727 12:14:50.045545 [Byte1]: 60
1728 12:14:50.048715
1729 12:14:50.048797 Set Vref, RX VrefLevel [Byte0]: 61
1730 12:14:50.052470 [Byte1]: 61
1731 12:14:50.056891
1732 12:14:50.056999 Set Vref, RX VrefLevel [Byte0]: 62
1733 12:14:50.059636 [Byte1]: 62
1734 12:14:50.064195
1735 12:14:50.064294 Set Vref, RX VrefLevel [Byte0]: 63
1736 12:14:50.067388 [Byte1]: 63
1737 12:14:50.071921
1738 12:14:50.072005 Set Vref, RX VrefLevel [Byte0]: 64
1739 12:14:50.075143 [Byte1]: 64
1740 12:14:50.079563
1741 12:14:50.079644 Set Vref, RX VrefLevel [Byte0]: 65
1742 12:14:50.083072 [Byte1]: 65
1743 12:14:50.086992
1744 12:14:50.087077 Set Vref, RX VrefLevel [Byte0]: 66
1745 12:14:50.090759 [Byte1]: 66
1746 12:14:50.095123
1747 12:14:50.095204 Set Vref, RX VrefLevel [Byte0]: 67
1748 12:14:50.098282 [Byte1]: 67
1749 12:14:50.102495
1750 12:14:50.102576 Set Vref, RX VrefLevel [Byte0]: 68
1751 12:14:50.105968 [Byte1]: 68
1752 12:14:50.110303
1753 12:14:50.110384 Set Vref, RX VrefLevel [Byte0]: 69
1754 12:14:50.113352 [Byte1]: 69
1755 12:14:50.118038
1756 12:14:50.118119 Set Vref, RX VrefLevel [Byte0]: 70
1757 12:14:50.121140 [Byte1]: 70
1758 12:14:50.125471
1759 12:14:50.125552 Set Vref, RX VrefLevel [Byte0]: 71
1760 12:14:50.128702 [Byte1]: 71
1761 12:14:50.132962
1762 12:14:50.133042 Set Vref, RX VrefLevel [Byte0]: 72
1763 12:14:50.136074 [Byte1]: 72
1764 12:14:50.140867
1765 12:14:50.140948 Set Vref, RX VrefLevel [Byte0]: 73
1766 12:14:50.143899 [Byte1]: 73
1767 12:14:50.148519
1768 12:14:50.148599 Final RX Vref Byte 0 = 55 to rank0
1769 12:14:50.151444 Final RX Vref Byte 1 = 54 to rank0
1770 12:14:50.155159 Final RX Vref Byte 0 = 55 to rank1
1771 12:14:50.158417 Final RX Vref Byte 1 = 54 to rank1==
1772 12:14:50.161512 Dram Type= 6, Freq= 0, CH_1, rank 0
1773 12:14:50.168266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1774 12:14:50.168351 ==
1775 12:14:50.168416 DQS Delay:
1776 12:14:50.168475 DQS0 = 0, DQS1 = 0
1777 12:14:50.171422 DQM Delay:
1778 12:14:50.171506 DQM0 = 81, DQM1 = 72
1779 12:14:50.175078 DQ Delay:
1780 12:14:50.178385 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1781 12:14:50.181548 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1782 12:14:50.184570 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1783 12:14:50.188351 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
1784 12:14:50.188457
1785 12:14:50.188528
1786 12:14:50.195059 [DQSOSCAuto] RK0, (LSB)MR18= 0x111b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1787 12:14:50.198108 CH1 RK0: MR19=606, MR18=111B
1788 12:14:50.204625 CH1_RK0: MR19=0x606, MR18=0x111B, DQSOSC=403, MR23=63, INC=90, DEC=60
1789 12:14:50.204711
1790 12:14:50.207683 ----->DramcWriteLeveling(PI) begin...
1791 12:14:50.207767 ==
1792 12:14:50.211222 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 12:14:50.214189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 12:14:50.214273 ==
1795 12:14:50.217886 Write leveling (Byte 0): 26 => 26
1796 12:14:50.221119 Write leveling (Byte 1): 27 => 27
1797 12:14:50.224388 DramcWriteLeveling(PI) end<-----
1798 12:14:50.224469
1799 12:14:50.224533 ==
1800 12:14:50.227445 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 12:14:50.231399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 12:14:50.231483 ==
1803 12:14:50.234316 [Gating] SW mode calibration
1804 12:14:50.240976 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1805 12:14:50.247665 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1806 12:14:50.250578 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1807 12:14:50.257702 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1808 12:14:50.260695 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:14:50.263744 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:14:50.270541 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:14:50.273876 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:14:50.277462 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:14:50.283656 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:14:50.287396 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:14:50.290458 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:14:50.297341 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:14:50.300293 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:14:50.303467 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:14:50.310372 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:14:50.313356 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:14:50.316886 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:14:50.323741 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:14:50.327026 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1824 12:14:50.330031 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1825 12:14:50.336746 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:14:50.339831 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:14:50.343508 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:14:50.349845 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:14:50.353410 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:14:50.356403 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1831 12:14:50.362742 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1832 12:14:50.366329 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1833 12:14:50.369448 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 12:14:50.375989 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 12:14:50.379659 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 12:14:50.382710 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 12:14:50.389541 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 12:14:50.392783 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 12:14:50.395785 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 1)
1840 12:14:50.402299 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
1841 12:14:50.405526 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:14:50.408764 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:14:50.415713 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:14:50.418856 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:14:50.421912 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:14:50.428532 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1847 12:14:50.432117 0 11 4 | B1->B0 | 2b2b 3d3d | 0 0 | (1 1) (0 0)
1848 12:14:50.435076 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1849 12:14:50.442175 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 12:14:50.445319 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 12:14:50.448474 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 12:14:50.455251 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 12:14:50.458383 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 12:14:50.462220 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 12:14:50.468480 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1856 12:14:50.471573 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:14:50.475125 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:14:50.481399 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:14:50.484665 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:14:50.488451 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:14:50.494510 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:14:50.498355 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:14:50.501375 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:14:50.507892 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:14:50.511637 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:14:50.514852 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:14:50.521216 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:14:50.524951 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:14:50.527913 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:14:50.531513 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:14:50.537906 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1872 12:14:50.541492 Total UI for P1: 0, mck2ui 16
1873 12:14:50.544321 best dqsien dly found for B0: ( 0, 14, 2)
1874 12:14:50.547918 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1875 12:14:50.551036 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 12:14:50.554142 Total UI for P1: 0, mck2ui 16
1877 12:14:50.557816 best dqsien dly found for B1: ( 0, 14, 6)
1878 12:14:50.560926 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1879 12:14:50.567716 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1880 12:14:50.567802
1881 12:14:50.570723 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1882 12:14:50.574474 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1883 12:14:50.577868 [Gating] SW calibration Done
1884 12:14:50.577950 ==
1885 12:14:50.580859 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 12:14:50.584177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 12:14:50.584259 ==
1888 12:14:50.584323 RX Vref Scan: 0
1889 12:14:50.584383
1890 12:14:50.587923 RX Vref 0 -> 0, step: 1
1891 12:14:50.588004
1892 12:14:50.590967 RX Delay -130 -> 252, step: 16
1893 12:14:50.594016 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1894 12:14:50.597780 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1895 12:14:50.604384 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1896 12:14:50.607248 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1897 12:14:50.610944 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1898 12:14:50.613904 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1899 12:14:50.617231 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1900 12:14:50.623970 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1901 12:14:50.627257 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1902 12:14:50.631022 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1903 12:14:50.634065 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1904 12:14:50.637220 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1905 12:14:50.643818 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1906 12:14:50.647174 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1907 12:14:50.650497 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1908 12:14:50.653934 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1909 12:14:50.654018 ==
1910 12:14:50.656894 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 12:14:50.663752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1912 12:14:50.663837 ==
1913 12:14:50.663902 DQS Delay:
1914 12:14:50.666945 DQS0 = 0, DQS1 = 0
1915 12:14:50.667029 DQM Delay:
1916 12:14:50.670581 DQM0 = 79, DQM1 = 73
1917 12:14:50.670665 DQ Delay:
1918 12:14:50.673650 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1919 12:14:50.676907 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1920 12:14:50.680306 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1921 12:14:50.683300 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1922 12:14:50.683382
1923 12:14:50.683447
1924 12:14:50.683523 ==
1925 12:14:50.686654 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 12:14:50.690282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 12:14:50.690379 ==
1928 12:14:50.690444
1929 12:14:50.690505
1930 12:14:50.693435 TX Vref Scan disable
1931 12:14:50.696640 == TX Byte 0 ==
1932 12:14:50.700286 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1933 12:14:50.703427 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1934 12:14:50.706560 == TX Byte 1 ==
1935 12:14:50.710219 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1936 12:14:50.713135 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1937 12:14:50.713217 ==
1938 12:14:50.716850 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 12:14:50.719825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 12:14:50.722856 ==
1941 12:14:50.734324 TX Vref=22, minBit 1, minWin=28, winSum=452
1942 12:14:50.738111 TX Vref=24, minBit 0, minWin=28, winSum=455
1943 12:14:50.741192 TX Vref=26, minBit 1, minWin=28, winSum=457
1944 12:14:50.744275 TX Vref=28, minBit 3, minWin=28, winSum=460
1945 12:14:50.747877 TX Vref=30, minBit 1, minWin=28, winSum=463
1946 12:14:50.750871 TX Vref=32, minBit 5, minWin=27, winSum=458
1947 12:14:50.757367 [TxChooseVref] Worse bit 1, Min win 28, Win sum 463, Final Vref 30
1948 12:14:50.757466
1949 12:14:50.760799 Final TX Range 1 Vref 30
1950 12:14:50.760882
1951 12:14:50.760946 ==
1952 12:14:50.764192 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 12:14:50.767471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 12:14:50.767600 ==
1955 12:14:50.770660
1956 12:14:50.770757
1957 12:14:50.770823 TX Vref Scan disable
1958 12:14:50.774476 == TX Byte 0 ==
1959 12:14:50.777527 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1960 12:14:50.784236 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1961 12:14:50.784320 == TX Byte 1 ==
1962 12:14:50.787251 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1963 12:14:50.794147 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1964 12:14:50.794231
1965 12:14:50.794296 [DATLAT]
1966 12:14:50.794356 Freq=800, CH1 RK1
1967 12:14:50.794415
1968 12:14:50.797319 DATLAT Default: 0xa
1969 12:14:50.797400 0, 0xFFFF, sum = 0
1970 12:14:50.801029 1, 0xFFFF, sum = 0
1971 12:14:50.804189 2, 0xFFFF, sum = 0
1972 12:14:50.804271 3, 0xFFFF, sum = 0
1973 12:14:50.807153 4, 0xFFFF, sum = 0
1974 12:14:50.807235 5, 0xFFFF, sum = 0
1975 12:14:50.810973 6, 0xFFFF, sum = 0
1976 12:14:50.811055 7, 0xFFFF, sum = 0
1977 12:14:50.814164 8, 0xFFFF, sum = 0
1978 12:14:50.814246 9, 0x0, sum = 1
1979 12:14:50.817519 10, 0x0, sum = 2
1980 12:14:50.817601 11, 0x0, sum = 3
1981 12:14:50.817666 12, 0x0, sum = 4
1982 12:14:50.820673 best_step = 10
1983 12:14:50.820753
1984 12:14:50.820816 ==
1985 12:14:50.823930 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 12:14:50.827123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 12:14:50.827200 ==
1988 12:14:50.830792 RX Vref Scan: 0
1989 12:14:50.830923
1990 12:14:50.833925 RX Vref 0 -> 0, step: 1
1991 12:14:50.834005
1992 12:14:50.834087 RX Delay -111 -> 252, step: 8
1993 12:14:50.841268 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1994 12:14:50.844595 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1995 12:14:50.847644 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
1996 12:14:50.850776 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1997 12:14:50.854363 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1998 12:14:50.861197 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1999 12:14:50.864348 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2000 12:14:50.867744 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2001 12:14:50.871248 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2002 12:14:50.874130 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2003 12:14:50.881052 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2004 12:14:50.884128 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2005 12:14:50.887909 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2006 12:14:50.890750 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2007 12:14:50.897310 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2008 12:14:50.900797 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2009 12:14:50.900881 ==
2010 12:14:50.904493 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 12:14:50.907564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 12:14:50.907646 ==
2013 12:14:50.907710 DQS Delay:
2014 12:14:50.911298 DQS0 = 0, DQS1 = 0
2015 12:14:50.911379 DQM Delay:
2016 12:14:50.914388 DQM0 = 77, DQM1 = 74
2017 12:14:50.914502 DQ Delay:
2018 12:14:50.917581 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2019 12:14:50.920550 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2020 12:14:50.924209 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2021 12:14:50.927572 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2022 12:14:50.927647
2023 12:14:50.927709
2024 12:14:50.937415 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c35, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2025 12:14:50.937528 CH1 RK1: MR19=606, MR18=1C35
2026 12:14:50.944178 CH1_RK1: MR19=0x606, MR18=0x1C35, DQSOSC=396, MR23=63, INC=94, DEC=62
2027 12:14:50.947534 [RxdqsGatingPostProcess] freq 800
2028 12:14:50.953700 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2029 12:14:50.957354 Pre-setting of DQS Precalculation
2030 12:14:50.960872 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2031 12:14:50.967153 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2032 12:14:50.977410 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2033 12:14:50.977526
2034 12:14:50.977619
2035 12:14:50.977709 [Calibration Summary] 1600 Mbps
2036 12:14:50.980293 CH 0, Rank 0
2037 12:14:50.980389 SW Impedance : PASS
2038 12:14:50.983978 DUTY Scan : NO K
2039 12:14:50.987044 ZQ Calibration : PASS
2040 12:14:50.987118 Jitter Meter : NO K
2041 12:14:50.990795 CBT Training : PASS
2042 12:14:50.993948 Write leveling : PASS
2043 12:14:50.994041 RX DQS gating : PASS
2044 12:14:50.997011 RX DQ/DQS(RDDQC) : PASS
2045 12:14:51.000653 TX DQ/DQS : PASS
2046 12:14:51.000736 RX DATLAT : PASS
2047 12:14:51.004113 RX DQ/DQS(Engine): PASS
2048 12:14:51.007296 TX OE : NO K
2049 12:14:51.007377 All Pass.
2050 12:14:51.007440
2051 12:14:51.007499 CH 0, Rank 1
2052 12:14:51.010497 SW Impedance : PASS
2053 12:14:51.013586 DUTY Scan : NO K
2054 12:14:51.013666 ZQ Calibration : PASS
2055 12:14:51.016834 Jitter Meter : NO K
2056 12:14:51.020369 CBT Training : PASS
2057 12:14:51.020449 Write leveling : PASS
2058 12:14:51.023487 RX DQS gating : PASS
2059 12:14:51.027024 RX DQ/DQS(RDDQC) : PASS
2060 12:14:51.027132 TX DQ/DQS : PASS
2061 12:14:51.030221 RX DATLAT : PASS
2062 12:14:51.033298 RX DQ/DQS(Engine): PASS
2063 12:14:51.033380 TX OE : NO K
2064 12:14:51.033445 All Pass.
2065 12:14:51.036953
2066 12:14:51.037034 CH 1, Rank 0
2067 12:14:51.040158 SW Impedance : PASS
2068 12:14:51.040240 DUTY Scan : NO K
2069 12:14:51.043427 ZQ Calibration : PASS
2070 12:14:51.043509 Jitter Meter : NO K
2071 12:14:51.047218 CBT Training : PASS
2072 12:14:51.050484 Write leveling : PASS
2073 12:14:51.050565 RX DQS gating : PASS
2074 12:14:51.053579 RX DQ/DQS(RDDQC) : PASS
2075 12:14:51.056902 TX DQ/DQS : PASS
2076 12:14:51.056983 RX DATLAT : PASS
2077 12:14:51.060023 RX DQ/DQS(Engine): PASS
2078 12:14:51.063639 TX OE : NO K
2079 12:14:51.063721 All Pass.
2080 12:14:51.063785
2081 12:14:51.063844 CH 1, Rank 1
2082 12:14:51.066736 SW Impedance : PASS
2083 12:14:51.070046 DUTY Scan : NO K
2084 12:14:51.070127 ZQ Calibration : PASS
2085 12:14:51.073638 Jitter Meter : NO K
2086 12:14:51.076753 CBT Training : PASS
2087 12:14:51.076834 Write leveling : PASS
2088 12:14:51.079776 RX DQS gating : PASS
2089 12:14:51.083255 RX DQ/DQS(RDDQC) : PASS
2090 12:14:51.083335 TX DQ/DQS : PASS
2091 12:14:51.086860 RX DATLAT : PASS
2092 12:14:51.086959 RX DQ/DQS(Engine): PASS
2093 12:14:51.089788 TX OE : NO K
2094 12:14:51.089870 All Pass.
2095 12:14:51.089935
2096 12:14:51.093410 DramC Write-DBI off
2097 12:14:51.096805 PER_BANK_REFRESH: Hybrid Mode
2098 12:14:51.096886 TX_TRACKING: ON
2099 12:14:51.099801 [GetDramInforAfterCalByMRR] Vendor 6.
2100 12:14:51.103244 [GetDramInforAfterCalByMRR] Revision 606.
2101 12:14:51.109929 [GetDramInforAfterCalByMRR] Revision 2 0.
2102 12:14:51.110011 MR0 0x3b3b
2103 12:14:51.110076 MR8 0x5151
2104 12:14:51.112892 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 12:14:51.112974
2106 12:14:51.116155 MR0 0x3b3b
2107 12:14:51.116236 MR8 0x5151
2108 12:14:51.119987 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 12:14:51.120069
2110 12:14:51.129718 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2111 12:14:51.132733 [FAST_K] Save calibration result to emmc
2112 12:14:51.136386 [FAST_K] Save calibration result to emmc
2113 12:14:51.139471 dram_init: config_dvfs: 1
2114 12:14:51.142977 dramc_set_vcore_voltage set vcore to 662500
2115 12:14:51.146341 Read voltage for 1200, 2
2116 12:14:51.146447 Vio18 = 0
2117 12:14:51.146545 Vcore = 662500
2118 12:14:51.149429 Vdram = 0
2119 12:14:51.149509 Vddq = 0
2120 12:14:51.149573 Vmddr = 0
2121 12:14:51.155983 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2122 12:14:51.159564 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2123 12:14:51.162738 MEM_TYPE=3, freq_sel=15
2124 12:14:51.165741 sv_algorithm_assistance_LP4_1600
2125 12:14:51.169369 ============ PULL DRAM RESETB DOWN ============
2126 12:14:51.172520 ========== PULL DRAM RESETB DOWN end =========
2127 12:14:51.178804 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2128 12:14:51.182504 ===================================
2129 12:14:51.182586 LPDDR4 DRAM CONFIGURATION
2130 12:14:51.185646 ===================================
2131 12:14:51.189303 EX_ROW_EN[0] = 0x0
2132 12:14:51.192321 EX_ROW_EN[1] = 0x0
2133 12:14:51.192402 LP4Y_EN = 0x0
2134 12:14:51.195573 WORK_FSP = 0x0
2135 12:14:51.195654 WL = 0x4
2136 12:14:51.198754 RL = 0x4
2137 12:14:51.198899 BL = 0x2
2138 12:14:51.202529 RPST = 0x0
2139 12:14:51.202609 RD_PRE = 0x0
2140 12:14:51.205494 WR_PRE = 0x1
2141 12:14:51.205583 WR_PST = 0x0
2142 12:14:51.208685 DBI_WR = 0x0
2143 12:14:51.208787 DBI_RD = 0x0
2144 12:14:51.212321 OTF = 0x1
2145 12:14:51.215371 ===================================
2146 12:14:51.218802 ===================================
2147 12:14:51.218946 ANA top config
2148 12:14:51.221977 ===================================
2149 12:14:51.225153 DLL_ASYNC_EN = 0
2150 12:14:51.228785 ALL_SLAVE_EN = 0
2151 12:14:51.232031 NEW_RANK_MODE = 1
2152 12:14:51.232105 DLL_IDLE_MODE = 1
2153 12:14:51.235366 LP45_APHY_COMB_EN = 1
2154 12:14:51.239016 TX_ODT_DIS = 1
2155 12:14:51.242019 NEW_8X_MODE = 1
2156 12:14:51.245307 ===================================
2157 12:14:51.248960 ===================================
2158 12:14:51.252088 data_rate = 2400
2159 12:14:51.252159 CKR = 1
2160 12:14:51.255344 DQ_P2S_RATIO = 8
2161 12:14:51.258503 ===================================
2162 12:14:51.261635 CA_P2S_RATIO = 8
2163 12:14:51.265329 DQ_CA_OPEN = 0
2164 12:14:51.268324 DQ_SEMI_OPEN = 0
2165 12:14:51.271516 CA_SEMI_OPEN = 0
2166 12:14:51.271606 CA_FULL_RATE = 0
2167 12:14:51.275068 DQ_CKDIV4_EN = 0
2168 12:14:51.278162 CA_CKDIV4_EN = 0
2169 12:14:51.281957 CA_PREDIV_EN = 0
2170 12:14:51.285221 PH8_DLY = 17
2171 12:14:51.288436 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2172 12:14:51.288533 DQ_AAMCK_DIV = 4
2173 12:14:51.291596 CA_AAMCK_DIV = 4
2174 12:14:51.294712 CA_ADMCK_DIV = 4
2175 12:14:51.297907 DQ_TRACK_CA_EN = 0
2176 12:14:51.301245 CA_PICK = 1200
2177 12:14:51.304653 CA_MCKIO = 1200
2178 12:14:51.308307 MCKIO_SEMI = 0
2179 12:14:51.311504 PLL_FREQ = 2366
2180 12:14:51.311606 DQ_UI_PI_RATIO = 32
2181 12:14:51.314615 CA_UI_PI_RATIO = 0
2182 12:14:51.318187 ===================================
2183 12:14:51.321713 ===================================
2184 12:14:51.324822 memory_type:LPDDR4
2185 12:14:51.328413 GP_NUM : 10
2186 12:14:51.328488 SRAM_EN : 1
2187 12:14:51.331457 MD32_EN : 0
2188 12:14:51.334656 ===================================
2189 12:14:51.334729 [ANA_INIT] >>>>>>>>>>>>>>
2190 12:14:51.338316 <<<<<< [CONFIGURE PHASE]: ANA_TX
2191 12:14:51.341451 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2192 12:14:51.344985 ===================================
2193 12:14:51.348138 data_rate = 2400,PCW = 0X5b00
2194 12:14:51.351390 ===================================
2195 12:14:51.354617 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2196 12:14:51.361585 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 12:14:51.367869 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 12:14:51.371056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2199 12:14:51.374840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2200 12:14:51.377857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2201 12:14:51.381435 [ANA_INIT] flow start
2202 12:14:51.381537 [ANA_INIT] PLL >>>>>>>>
2203 12:14:51.384580 [ANA_INIT] PLL <<<<<<<<
2204 12:14:51.387595 [ANA_INIT] MIDPI >>>>>>>>
2205 12:14:51.387690 [ANA_INIT] MIDPI <<<<<<<<
2206 12:14:51.390759 [ANA_INIT] DLL >>>>>>>>
2207 12:14:51.394770 [ANA_INIT] DLL <<<<<<<<
2208 12:14:51.394900 [ANA_INIT] flow end
2209 12:14:51.400712 ============ LP4 DIFF to SE enter ============
2210 12:14:51.404368 ============ LP4 DIFF to SE exit ============
2211 12:14:51.407580 [ANA_INIT] <<<<<<<<<<<<<
2212 12:14:51.410774 [Flow] Enable top DCM control >>>>>
2213 12:14:51.414166 [Flow] Enable top DCM control <<<<<
2214 12:14:51.417397 Enable DLL master slave shuffle
2215 12:14:51.420977 ==============================================================
2216 12:14:51.423921 Gating Mode config
2217 12:14:51.427481 ==============================================================
2218 12:14:51.430474 Config description:
2219 12:14:51.440731 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2220 12:14:51.447157 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2221 12:14:51.450295 SELPH_MODE 0: By rank 1: By Phase
2222 12:14:51.457402 ==============================================================
2223 12:14:51.460381 GAT_TRACK_EN = 1
2224 12:14:51.464121 RX_GATING_MODE = 2
2225 12:14:51.467246 RX_GATING_TRACK_MODE = 2
2226 12:14:51.470461 SELPH_MODE = 1
2227 12:14:51.470570 PICG_EARLY_EN = 1
2228 12:14:51.473707 VALID_LAT_VALUE = 1
2229 12:14:51.480483 ==============================================================
2230 12:14:51.483590 Enter into Gating configuration >>>>
2231 12:14:51.486699 Exit from Gating configuration <<<<
2232 12:14:51.490502 Enter into DVFS_PRE_config >>>>>
2233 12:14:51.500066 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2234 12:14:51.503202 Exit from DVFS_PRE_config <<<<<
2235 12:14:51.506825 Enter into PICG configuration >>>>
2236 12:14:51.510136 Exit from PICG configuration <<<<
2237 12:14:51.513779 [RX_INPUT] configuration >>>>>
2238 12:14:51.516803 [RX_INPUT] configuration <<<<<
2239 12:14:51.523356 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2240 12:14:51.526972 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2241 12:14:51.533576 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2242 12:14:51.540062 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2243 12:14:51.546800 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 12:14:51.553002 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 12:14:51.556776 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2246 12:14:51.559891 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2247 12:14:51.562999 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2248 12:14:51.569926 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2249 12:14:51.573060 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2250 12:14:51.576747 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2251 12:14:51.579792 ===================================
2252 12:14:51.582816 LPDDR4 DRAM CONFIGURATION
2253 12:14:51.586694 ===================================
2254 12:14:51.586780 EX_ROW_EN[0] = 0x0
2255 12:14:51.589808 EX_ROW_EN[1] = 0x0
2256 12:14:51.589891 LP4Y_EN = 0x0
2257 12:14:51.593032 WORK_FSP = 0x0
2258 12:14:51.596148 WL = 0x4
2259 12:14:51.596231 RL = 0x4
2260 12:14:51.600047 BL = 0x2
2261 12:14:51.600129 RPST = 0x0
2262 12:14:51.603109 RD_PRE = 0x0
2263 12:14:51.603216 WR_PRE = 0x1
2264 12:14:51.606238 WR_PST = 0x0
2265 12:14:51.606319 DBI_WR = 0x0
2266 12:14:51.609320 DBI_RD = 0x0
2267 12:14:51.609401 OTF = 0x1
2268 12:14:51.612634 ===================================
2269 12:14:51.616397 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2270 12:14:51.622665 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2271 12:14:51.626377 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2272 12:14:51.629293 ===================================
2273 12:14:51.633065 LPDDR4 DRAM CONFIGURATION
2274 12:14:51.636096 ===================================
2275 12:14:51.636180 EX_ROW_EN[0] = 0x10
2276 12:14:51.639589 EX_ROW_EN[1] = 0x0
2277 12:14:51.639671 LP4Y_EN = 0x0
2278 12:14:51.642568 WORK_FSP = 0x0
2279 12:14:51.642682 WL = 0x4
2280 12:14:51.646140 RL = 0x4
2281 12:14:51.649613 BL = 0x2
2282 12:14:51.649696 RPST = 0x0
2283 12:14:51.652564 RD_PRE = 0x0
2284 12:14:51.652675 WR_PRE = 0x1
2285 12:14:51.656520 WR_PST = 0x0
2286 12:14:51.656605 DBI_WR = 0x0
2287 12:14:51.659022 DBI_RD = 0x0
2288 12:14:51.659104 OTF = 0x1
2289 12:14:51.662752 ===================================
2290 12:14:51.669229 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2291 12:14:51.669382 ==
2292 12:14:51.672400 Dram Type= 6, Freq= 0, CH_0, rank 0
2293 12:14:51.676019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2294 12:14:51.676102 ==
2295 12:14:51.679115 [Duty_Offset_Calibration]
2296 12:14:51.682322 B0:2 B1:0 CA:3
2297 12:14:51.682401
2298 12:14:51.685293 [DutyScan_Calibration_Flow] k_type=0
2299 12:14:51.693942
2300 12:14:51.694022 ==CLK 0==
2301 12:14:51.697216 Final CLK duty delay cell = 0
2302 12:14:51.700617 [0] MAX Duty = 5062%(X100), DQS PI = 20
2303 12:14:51.703743 [0] MIN Duty = 4875%(X100), DQS PI = 58
2304 12:14:51.706761 [0] AVG Duty = 4968%(X100)
2305 12:14:51.706883
2306 12:14:51.710543 CH0 CLK Duty spec in!! Max-Min= 187%
2307 12:14:51.713888 [DutyScan_Calibration_Flow] ====Done====
2308 12:14:51.713966
2309 12:14:51.717033 [DutyScan_Calibration_Flow] k_type=1
2310 12:14:51.732101
2311 12:14:51.732183 ==DQS 0 ==
2312 12:14:51.735762 Final DQS duty delay cell = 0
2313 12:14:51.738812 [0] MAX Duty = 5062%(X100), DQS PI = 12
2314 12:14:51.741947 [0] MIN Duty = 4907%(X100), DQS PI = 0
2315 12:14:51.742027 [0] AVG Duty = 4984%(X100)
2316 12:14:51.745448
2317 12:14:51.745527 ==DQS 1 ==
2318 12:14:51.748813 Final DQS duty delay cell = -4
2319 12:14:51.752275 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2320 12:14:51.755138 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2321 12:14:51.758775 [-4] AVG Duty = 4937%(X100)
2322 12:14:51.758878
2323 12:14:51.761761 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2324 12:14:51.761840
2325 12:14:51.765601 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2326 12:14:51.768221 [DutyScan_Calibration_Flow] ====Done====
2327 12:14:51.768300
2328 12:14:51.771944 [DutyScan_Calibration_Flow] k_type=3
2329 12:14:51.789835
2330 12:14:51.789918 ==DQM 0 ==
2331 12:14:51.793022 Final DQM duty delay cell = 0
2332 12:14:51.796237 [0] MAX Duty = 5124%(X100), DQS PI = 28
2333 12:14:51.799631 [0] MIN Duty = 4876%(X100), DQS PI = 0
2334 12:14:51.799710 [0] AVG Duty = 5000%(X100)
2335 12:14:51.802683
2336 12:14:51.802764 ==DQM 1 ==
2337 12:14:51.806469 Final DQM duty delay cell = 4
2338 12:14:51.809856 [4] MAX Duty = 5124%(X100), DQS PI = 50
2339 12:14:51.812999 [4] MIN Duty = 5031%(X100), DQS PI = 12
2340 12:14:51.816289 [4] AVG Duty = 5077%(X100)
2341 12:14:51.816369
2342 12:14:51.819362 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2343 12:14:51.819441
2344 12:14:51.822666 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2345 12:14:51.825724 [DutyScan_Calibration_Flow] ====Done====
2346 12:14:51.825827
2347 12:14:51.829651 [DutyScan_Calibration_Flow] k_type=2
2348 12:14:51.844411
2349 12:14:51.844496 ==DQ 0 ==
2350 12:14:51.847651 Final DQ duty delay cell = -4
2351 12:14:51.851160 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2352 12:14:51.854582 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2353 12:14:51.857457 [-4] AVG Duty = 4969%(X100)
2354 12:14:51.857539
2355 12:14:51.857603 ==DQ 1 ==
2356 12:14:51.861095 Final DQ duty delay cell = -4
2357 12:14:51.864165 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2358 12:14:51.867722 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2359 12:14:51.870738 [-4] AVG Duty = 4938%(X100)
2360 12:14:51.870869
2361 12:14:51.873896 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2362 12:14:51.873977
2363 12:14:51.877298 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2364 12:14:51.880312 [DutyScan_Calibration_Flow] ====Done====
2365 12:14:51.880395 ==
2366 12:14:51.883676 Dram Type= 6, Freq= 0, CH_1, rank 0
2367 12:14:51.887244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 12:14:51.887327 ==
2369 12:14:51.890316 [Duty_Offset_Calibration]
2370 12:14:51.893564 B0:1 B1:-2 CA:0
2371 12:14:51.893646
2372 12:14:51.896702 [DutyScan_Calibration_Flow] k_type=0
2373 12:14:51.905915
2374 12:14:51.905998 ==CLK 0==
2375 12:14:51.909079 Final CLK duty delay cell = 4
2376 12:14:51.912129 [4] MAX Duty = 5156%(X100), DQS PI = 0
2377 12:14:51.915727 [4] MIN Duty = 5031%(X100), DQS PI = 26
2378 12:14:51.915809 [4] AVG Duty = 5093%(X100)
2379 12:14:51.918846
2380 12:14:51.918941 CH1 CLK Duty spec in!! Max-Min= 125%
2381 12:14:51.925929 [DutyScan_Calibration_Flow] ====Done====
2382 12:14:51.926029
2383 12:14:51.928967 [DutyScan_Calibration_Flow] k_type=1
2384 12:14:51.944415
2385 12:14:51.944559 ==DQS 0 ==
2386 12:14:51.947579 Final DQS duty delay cell = -4
2387 12:14:51.950703 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2388 12:14:51.954030 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2389 12:14:51.957414 [-4] AVG Duty = 4953%(X100)
2390 12:14:51.957516
2391 12:14:51.957638 ==DQS 1 ==
2392 12:14:51.960448 Final DQS duty delay cell = 0
2393 12:14:51.964017 [0] MAX Duty = 5093%(X100), DQS PI = 34
2394 12:14:51.967299 [0] MIN Duty = 4875%(X100), DQS PI = 10
2395 12:14:51.970361 [0] AVG Duty = 4984%(X100)
2396 12:14:51.970445
2397 12:14:51.973877 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2398 12:14:51.973960
2399 12:14:51.976831 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2400 12:14:51.980435 [DutyScan_Calibration_Flow] ====Done====
2401 12:14:51.980563
2402 12:14:51.983476 [DutyScan_Calibration_Flow] k_type=3
2403 12:14:52.001826
2404 12:14:52.001915 ==DQM 0 ==
2405 12:14:52.004845 Final DQM duty delay cell = 4
2406 12:14:52.008809 [4] MAX Duty = 5156%(X100), DQS PI = 52
2407 12:14:52.011627 [4] MIN Duty = 5031%(X100), DQS PI = 20
2408 12:14:52.014941 [4] AVG Duty = 5093%(X100)
2409 12:14:52.015017
2410 12:14:52.015079 ==DQM 1 ==
2411 12:14:52.018648 Final DQM duty delay cell = 0
2412 12:14:52.021799 [0] MAX Duty = 5031%(X100), DQS PI = 4
2413 12:14:52.024764 [0] MIN Duty = 4907%(X100), DQS PI = 46
2414 12:14:52.028455 [0] AVG Duty = 4969%(X100)
2415 12:14:52.028533
2416 12:14:52.031613 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2417 12:14:52.031696
2418 12:14:52.034625 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2419 12:14:52.038733 [DutyScan_Calibration_Flow] ====Done====
2420 12:14:52.038873
2421 12:14:52.041538 [DutyScan_Calibration_Flow] k_type=2
2422 12:14:52.057942
2423 12:14:52.058030 ==DQ 0 ==
2424 12:14:52.061534 Final DQ duty delay cell = 0
2425 12:14:52.064562 [0] MAX Duty = 5062%(X100), DQS PI = 0
2426 12:14:52.068171 [0] MIN Duty = 4969%(X100), DQS PI = 12
2427 12:14:52.068276 [0] AVG Duty = 5015%(X100)
2428 12:14:52.071270
2429 12:14:52.071372 ==DQ 1 ==
2430 12:14:52.074692 Final DQ duty delay cell = 0
2431 12:14:52.077896 [0] MAX Duty = 5125%(X100), DQS PI = 14
2432 12:14:52.081381 [0] MIN Duty = 4969%(X100), DQS PI = 58
2433 12:14:52.081465 [0] AVG Duty = 5047%(X100)
2434 12:14:52.084840
2435 12:14:52.088006 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2436 12:14:52.088090
2437 12:14:52.090950 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2438 12:14:52.094535 [DutyScan_Calibration_Flow] ====Done====
2439 12:14:52.098120 nWR fixed to 30
2440 12:14:52.098229 [ModeRegInit_LP4] CH0 RK0
2441 12:14:52.101258 [ModeRegInit_LP4] CH0 RK1
2442 12:14:52.104500 [ModeRegInit_LP4] CH1 RK0
2443 12:14:52.107588 [ModeRegInit_LP4] CH1 RK1
2444 12:14:52.107689 match AC timing 7
2445 12:14:52.110714 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2446 12:14:52.117536 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2447 12:14:52.121285 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2448 12:14:52.127628 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2449 12:14:52.130722 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2450 12:14:52.130859 ==
2451 12:14:52.134419 Dram Type= 6, Freq= 0, CH_0, rank 0
2452 12:14:52.137386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2453 12:14:52.137493 ==
2454 12:14:52.144516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2455 12:14:52.150610 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2456 12:14:52.158160 [CA 0] Center 40 (10~71) winsize 62
2457 12:14:52.161502 [CA 1] Center 39 (9~70) winsize 62
2458 12:14:52.164614 [CA 2] Center 36 (6~66) winsize 61
2459 12:14:52.167776 [CA 3] Center 35 (5~66) winsize 62
2460 12:14:52.170927 [CA 4] Center 34 (4~65) winsize 62
2461 12:14:52.174577 [CA 5] Center 33 (3~63) winsize 61
2462 12:14:52.174695
2463 12:14:52.177617 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2464 12:14:52.177725
2465 12:14:52.180866 [CATrainingPosCal] consider 1 rank data
2466 12:14:52.184554 u2DelayCellTimex100 = 270/100 ps
2467 12:14:52.187502 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2468 12:14:52.194165 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2469 12:14:52.197747 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2470 12:14:52.200823 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2471 12:14:52.204503 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2472 12:14:52.207722 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2473 12:14:52.207812
2474 12:14:52.210791 CA PerBit enable=1, Macro0, CA PI delay=33
2475 12:14:52.210889
2476 12:14:52.214280 [CBTSetCACLKResult] CA Dly = 33
2477 12:14:52.217529 CS Dly: 7 (0~38)
2478 12:14:52.217611 ==
2479 12:14:52.220968 Dram Type= 6, Freq= 0, CH_0, rank 1
2480 12:14:52.224079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2481 12:14:52.224189 ==
2482 12:14:52.230408 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2483 12:14:52.234232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2484 12:14:52.244161 [CA 0] Center 40 (10~71) winsize 62
2485 12:14:52.247596 [CA 1] Center 39 (9~70) winsize 62
2486 12:14:52.250727 [CA 2] Center 35 (5~66) winsize 62
2487 12:14:52.253865 [CA 3] Center 35 (5~66) winsize 62
2488 12:14:52.256957 [CA 4] Center 34 (4~65) winsize 62
2489 12:14:52.260939 [CA 5] Center 33 (3~63) winsize 61
2490 12:14:52.261022
2491 12:14:52.263662 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2492 12:14:52.263733
2493 12:14:52.266801 [CATrainingPosCal] consider 2 rank data
2494 12:14:52.270097 u2DelayCellTimex100 = 270/100 ps
2495 12:14:52.276947 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2496 12:14:52.280645 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2497 12:14:52.283454 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2498 12:14:52.287034 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2499 12:14:52.290120 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2500 12:14:52.293668 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2501 12:14:52.293755
2502 12:14:52.296928 CA PerBit enable=1, Macro0, CA PI delay=33
2503 12:14:52.297014
2504 12:14:52.300481 [CBTSetCACLKResult] CA Dly = 33
2505 12:14:52.303409 CS Dly: 7 (0~39)
2506 12:14:52.303494
2507 12:14:52.306856 ----->DramcWriteLeveling(PI) begin...
2508 12:14:52.306955 ==
2509 12:14:52.310205 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 12:14:52.313876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 12:14:52.313963 ==
2512 12:14:52.316657 Write leveling (Byte 0): 34 => 34
2513 12:14:52.319861 Write leveling (Byte 1): 31 => 31
2514 12:14:52.323482 DramcWriteLeveling(PI) end<-----
2515 12:14:52.323566
2516 12:14:52.323631 ==
2517 12:14:52.326647 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 12:14:52.330288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 12:14:52.330374 ==
2520 12:14:52.333399 [Gating] SW mode calibration
2521 12:14:52.339758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2522 12:14:52.346729 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2523 12:14:52.349741 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2524 12:14:52.352910 0 15 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2525 12:14:52.359867 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 12:14:52.362926 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 12:14:52.366222 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 12:14:52.373201 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 12:14:52.376236 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 12:14:52.379601 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2531 12:14:52.385819 1 0 0 | B1->B0 | 3030 2828 | 0 0 | (0 1) (0 0)
2532 12:14:52.389591 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 12:14:52.392515 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 12:14:52.399082 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 12:14:52.402928 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 12:14:52.405655 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 12:14:52.412815 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 12:14:52.415587 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2539 12:14:52.419239 1 1 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2540 12:14:52.425747 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2541 12:14:52.429348 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 12:14:52.432277 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 12:14:52.439148 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 12:14:52.442293 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 12:14:52.445403 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 12:14:52.452383 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 12:14:52.455469 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2548 12:14:52.459026 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2549 12:14:52.465275 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:14:52.468974 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:14:52.472024 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:14:52.478823 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:14:52.482020 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:14:52.485770 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:14:52.492447 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:14:52.495431 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:14:52.498492 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:14:52.505433 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:14:52.508312 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:14:52.511960 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:14:52.518655 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:14:52.521721 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:14:52.525331 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2564 12:14:52.531595 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2565 12:14:52.531686 Total UI for P1: 0, mck2ui 16
2566 12:14:52.538250 best dqsien dly found for B0: ( 1, 4, 0)
2567 12:14:52.542003 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 12:14:52.545087 Total UI for P1: 0, mck2ui 16
2569 12:14:52.548096 best dqsien dly found for B1: ( 1, 4, 4)
2570 12:14:52.551815 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2571 12:14:52.555094 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2572 12:14:52.555217
2573 12:14:52.558380 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2574 12:14:52.562097 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2575 12:14:52.565101 [Gating] SW calibration Done
2576 12:14:52.565184 ==
2577 12:14:52.567989 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 12:14:52.571812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 12:14:52.571903 ==
2580 12:14:52.575114 RX Vref Scan: 0
2581 12:14:52.575199
2582 12:14:52.578294 RX Vref 0 -> 0, step: 1
2583 12:14:52.578377
2584 12:14:52.578442 RX Delay -40 -> 252, step: 8
2585 12:14:52.585204 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2586 12:14:52.588199 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2587 12:14:52.591334 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2588 12:14:52.594672 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2589 12:14:52.597842 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2590 12:14:52.604670 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2591 12:14:52.607597 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2592 12:14:52.611030 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2593 12:14:52.614817 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2594 12:14:52.617510 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2595 12:14:52.624744 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2596 12:14:52.627989 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2597 12:14:52.630796 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2598 12:14:52.634784 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2599 12:14:52.637594 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2600 12:14:52.644119 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2601 12:14:52.644204 ==
2602 12:14:52.647313 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 12:14:52.651198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 12:14:52.651285 ==
2605 12:14:52.651381 DQS Delay:
2606 12:14:52.653831 DQS0 = 0, DQS1 = 0
2607 12:14:52.653916 DQM Delay:
2608 12:14:52.657765 DQM0 = 113, DQM1 = 102
2609 12:14:52.657848 DQ Delay:
2610 12:14:52.660727 DQ0 =115, DQ1 =111, DQ2 =115, DQ3 =107
2611 12:14:52.664390 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2612 12:14:52.667474 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =95
2613 12:14:52.670674 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2614 12:14:52.670785
2615 12:14:52.670895
2616 12:14:52.673703 ==
2617 12:14:52.673786 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 12:14:52.680761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 12:14:52.680848 ==
2620 12:14:52.680913
2621 12:14:52.680973
2622 12:14:52.683938 TX Vref Scan disable
2623 12:14:52.684045 == TX Byte 0 ==
2624 12:14:52.687109 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2625 12:14:52.693970 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2626 12:14:52.694054 == TX Byte 1 ==
2627 12:14:52.697253 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2628 12:14:52.703625 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2629 12:14:52.703764 ==
2630 12:14:52.706818 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 12:14:52.709932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 12:14:52.710039 ==
2633 12:14:52.722723 TX Vref=22, minBit 1, minWin=25, winSum=412
2634 12:14:52.725783 TX Vref=24, minBit 7, minWin=25, winSum=421
2635 12:14:52.729308 TX Vref=26, minBit 4, minWin=26, winSum=429
2636 12:14:52.732540 TX Vref=28, minBit 10, minWin=26, winSum=429
2637 12:14:52.736062 TX Vref=30, minBit 12, minWin=26, winSum=431
2638 12:14:52.742638 TX Vref=32, minBit 2, minWin=26, winSum=427
2639 12:14:52.745622 [TxChooseVref] Worse bit 12, Min win 26, Win sum 431, Final Vref 30
2640 12:14:52.745730
2641 12:14:52.749185 Final TX Range 1 Vref 30
2642 12:14:52.749271
2643 12:14:52.749336 ==
2644 12:14:52.752410 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 12:14:52.755662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 12:14:52.759383 ==
2647 12:14:52.759466
2648 12:14:52.759529
2649 12:14:52.759590 TX Vref Scan disable
2650 12:14:52.762598 == TX Byte 0 ==
2651 12:14:52.765634 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2652 12:14:52.772299 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2653 12:14:52.772396 == TX Byte 1 ==
2654 12:14:52.775985 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2655 12:14:52.782344 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2656 12:14:52.782441
2657 12:14:52.782512 [DATLAT]
2658 12:14:52.782606 Freq=1200, CH0 RK0
2659 12:14:52.782666
2660 12:14:52.785438 DATLAT Default: 0xd
2661 12:14:52.785510 0, 0xFFFF, sum = 0
2662 12:14:52.789005 1, 0xFFFF, sum = 0
2663 12:14:52.792175 2, 0xFFFF, sum = 0
2664 12:14:52.792250 3, 0xFFFF, sum = 0
2665 12:14:52.795926 4, 0xFFFF, sum = 0
2666 12:14:52.796007 5, 0xFFFF, sum = 0
2667 12:14:52.799074 6, 0xFFFF, sum = 0
2668 12:14:52.799147 7, 0xFFFF, sum = 0
2669 12:14:52.802234 8, 0xFFFF, sum = 0
2670 12:14:52.802314 9, 0xFFFF, sum = 0
2671 12:14:52.805888 10, 0xFFFF, sum = 0
2672 12:14:52.805970 11, 0xFFFF, sum = 0
2673 12:14:52.809101 12, 0x0, sum = 1
2674 12:14:52.809184 13, 0x0, sum = 2
2675 12:14:52.812247 14, 0x0, sum = 3
2676 12:14:52.812319 15, 0x0, sum = 4
2677 12:14:52.815578 best_step = 13
2678 12:14:52.815649
2679 12:14:52.815717 ==
2680 12:14:52.819119 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 12:14:52.822465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 12:14:52.822539 ==
2683 12:14:52.822601 RX Vref Scan: 1
2684 12:14:52.822668
2685 12:14:52.825473 Set Vref Range= 32 -> 127
2686 12:14:52.825547
2687 12:14:52.829279 RX Vref 32 -> 127, step: 1
2688 12:14:52.829364
2689 12:14:52.832086 RX Delay -37 -> 252, step: 4
2690 12:14:52.832162
2691 12:14:52.835559 Set Vref, RX VrefLevel [Byte0]: 32
2692 12:14:52.839063 [Byte1]: 32
2693 12:14:52.839145
2694 12:14:52.842144 Set Vref, RX VrefLevel [Byte0]: 33
2695 12:14:52.845487 [Byte1]: 33
2696 12:14:52.848931
2697 12:14:52.849002 Set Vref, RX VrefLevel [Byte0]: 34
2698 12:14:52.852584 [Byte1]: 34
2699 12:14:52.857487
2700 12:14:52.857564 Set Vref, RX VrefLevel [Byte0]: 35
2701 12:14:52.860732 [Byte1]: 35
2702 12:14:52.864945
2703 12:14:52.865018 Set Vref, RX VrefLevel [Byte0]: 36
2704 12:14:52.868716 [Byte1]: 36
2705 12:14:52.873541
2706 12:14:52.873643 Set Vref, RX VrefLevel [Byte0]: 37
2707 12:14:52.876530 [Byte1]: 37
2708 12:14:52.880970
2709 12:14:52.881058 Set Vref, RX VrefLevel [Byte0]: 38
2710 12:14:52.884347 [Byte1]: 38
2711 12:14:52.889249
2712 12:14:52.889362 Set Vref, RX VrefLevel [Byte0]: 39
2713 12:14:52.892277 [Byte1]: 39
2714 12:14:52.897280
2715 12:14:52.897384 Set Vref, RX VrefLevel [Byte0]: 40
2716 12:14:52.900388 [Byte1]: 40
2717 12:14:52.905494
2718 12:14:52.905596 Set Vref, RX VrefLevel [Byte0]: 41
2719 12:14:52.908648 [Byte1]: 41
2720 12:14:52.913083
2721 12:14:52.913158 Set Vref, RX VrefLevel [Byte0]: 42
2722 12:14:52.916771 [Byte1]: 42
2723 12:14:52.921259
2724 12:14:52.921345 Set Vref, RX VrefLevel [Byte0]: 43
2725 12:14:52.924216 [Byte1]: 43
2726 12:14:52.928977
2727 12:14:52.929079 Set Vref, RX VrefLevel [Byte0]: 44
2728 12:14:52.932499 [Byte1]: 44
2729 12:14:52.937502
2730 12:14:52.937611 Set Vref, RX VrefLevel [Byte0]: 45
2731 12:14:52.940266 [Byte1]: 45
2732 12:14:52.945004
2733 12:14:52.945138 Set Vref, RX VrefLevel [Byte0]: 46
2734 12:14:52.948814 [Byte1]: 46
2735 12:14:52.953214
2736 12:14:52.953316 Set Vref, RX VrefLevel [Byte0]: 47
2737 12:14:52.956712 [Byte1]: 47
2738 12:14:52.961288
2739 12:14:52.961366 Set Vref, RX VrefLevel [Byte0]: 48
2740 12:14:52.964364 [Byte1]: 48
2741 12:14:52.969376
2742 12:14:52.969494 Set Vref, RX VrefLevel [Byte0]: 49
2743 12:14:52.972588 [Byte1]: 49
2744 12:14:52.977580
2745 12:14:52.977709 Set Vref, RX VrefLevel [Byte0]: 50
2746 12:14:52.980474 [Byte1]: 50
2747 12:14:52.985555
2748 12:14:52.985704 Set Vref, RX VrefLevel [Byte0]: 51
2749 12:14:52.988557 [Byte1]: 51
2750 12:14:52.993009
2751 12:14:52.993151 Set Vref, RX VrefLevel [Byte0]: 52
2752 12:14:52.996760 [Byte1]: 52
2753 12:14:53.001259
2754 12:14:53.001359 Set Vref, RX VrefLevel [Byte0]: 53
2755 12:14:53.004308 [Byte1]: 53
2756 12:14:53.009439
2757 12:14:53.009541 Set Vref, RX VrefLevel [Byte0]: 54
2758 12:14:53.012667 [Byte1]: 54
2759 12:14:53.016914
2760 12:14:53.017016 Set Vref, RX VrefLevel [Byte0]: 55
2761 12:14:53.020670 [Byte1]: 55
2762 12:14:53.025027
2763 12:14:53.025125 Set Vref, RX VrefLevel [Byte0]: 56
2764 12:14:53.028262 [Byte1]: 56
2765 12:14:53.033133
2766 12:14:53.033238 Set Vref, RX VrefLevel [Byte0]: 57
2767 12:14:53.036652 [Byte1]: 57
2768 12:14:53.041463
2769 12:14:53.041576 Set Vref, RX VrefLevel [Byte0]: 58
2770 12:14:53.044469 [Byte1]: 58
2771 12:14:53.049177
2772 12:14:53.049279 Set Vref, RX VrefLevel [Byte0]: 59
2773 12:14:53.052292 [Byte1]: 59
2774 12:14:53.057229
2775 12:14:53.057333 Set Vref, RX VrefLevel [Byte0]: 60
2776 12:14:53.060286 [Byte1]: 60
2777 12:14:53.065086
2778 12:14:53.065186 Set Vref, RX VrefLevel [Byte0]: 61
2779 12:14:53.068462 [Byte1]: 61
2780 12:14:53.072924
2781 12:14:53.073044 Set Vref, RX VrefLevel [Byte0]: 62
2782 12:14:53.076591 [Byte1]: 62
2783 12:14:53.081356
2784 12:14:53.081439 Set Vref, RX VrefLevel [Byte0]: 63
2785 12:14:53.084342 [Byte1]: 63
2786 12:14:53.089429
2787 12:14:53.089513 Set Vref, RX VrefLevel [Byte0]: 64
2788 12:14:53.092592 [Byte1]: 64
2789 12:14:53.097060
2790 12:14:53.097166 Set Vref, RX VrefLevel [Byte0]: 65
2791 12:14:53.100763 [Byte1]: 65
2792 12:14:53.105068
2793 12:14:53.105154 Set Vref, RX VrefLevel [Byte0]: 66
2794 12:14:53.108261 [Byte1]: 66
2795 12:14:53.113363
2796 12:14:53.113471 Set Vref, RX VrefLevel [Byte0]: 67
2797 12:14:53.116774 [Byte1]: 67
2798 12:14:53.121209
2799 12:14:53.121289 Set Vref, RX VrefLevel [Byte0]: 68
2800 12:14:53.124236 [Byte1]: 68
2801 12:14:53.129497
2802 12:14:53.129593 Set Vref, RX VrefLevel [Byte0]: 69
2803 12:14:53.132524 [Byte1]: 69
2804 12:14:53.136829
2805 12:14:53.140636 Set Vref, RX VrefLevel [Byte0]: 70
2806 12:14:53.140726 [Byte1]: 70
2807 12:14:53.145340
2808 12:14:53.145433 Set Vref, RX VrefLevel [Byte0]: 71
2809 12:14:53.148486 [Byte1]: 71
2810 12:14:53.153084
2811 12:14:53.153190 Set Vref, RX VrefLevel [Byte0]: 72
2812 12:14:53.156733 [Byte1]: 72
2813 12:14:53.161164
2814 12:14:53.161275 Set Vref, RX VrefLevel [Byte0]: 73
2815 12:14:53.164452 [Byte1]: 73
2816 12:14:53.168986
2817 12:14:53.169091 Final RX Vref Byte 0 = 62 to rank0
2818 12:14:53.172393 Final RX Vref Byte 1 = 53 to rank0
2819 12:14:53.176023 Final RX Vref Byte 0 = 62 to rank1
2820 12:14:53.179132 Final RX Vref Byte 1 = 53 to rank1==
2821 12:14:53.182192 Dram Type= 6, Freq= 0, CH_0, rank 0
2822 12:14:53.189012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 12:14:53.189105 ==
2824 12:14:53.189172 DQS Delay:
2825 12:14:53.189234 DQS0 = 0, DQS1 = 0
2826 12:14:53.192743 DQM Delay:
2827 12:14:53.192828 DQM0 = 112, DQM1 = 101
2828 12:14:53.195922 DQ Delay:
2829 12:14:53.198960 DQ0 =110, DQ1 =112, DQ2 =112, DQ3 =108
2830 12:14:53.202438 DQ4 =114, DQ5 =104, DQ6 =120, DQ7 =120
2831 12:14:53.205947 DQ8 =92, DQ9 =84, DQ10 =102, DQ11 =92
2832 12:14:53.209114 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2833 12:14:53.209191
2834 12:14:53.209254
2835 12:14:53.215967 [DQSOSCAuto] RK0, (LSB)MR18= 0xf9f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2836 12:14:53.219101 CH0 RK0: MR19=303, MR18=F9F9
2837 12:14:53.225601 CH0_RK0: MR19=0x303, MR18=0xF9F9, DQSOSC=412, MR23=63, INC=38, DEC=25
2838 12:14:53.225691
2839 12:14:53.228657 ----->DramcWriteLeveling(PI) begin...
2840 12:14:53.228746 ==
2841 12:14:53.232335 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 12:14:53.238628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 12:14:53.238710 ==
2844 12:14:53.241718 Write leveling (Byte 0): 33 => 33
2845 12:14:53.241805 Write leveling (Byte 1): 29 => 29
2846 12:14:53.245485 DramcWriteLeveling(PI) end<-----
2847 12:14:53.245565
2848 12:14:53.245651 ==
2849 12:14:53.248702 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 12:14:53.255142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 12:14:53.255227 ==
2852 12:14:53.258576 [Gating] SW mode calibration
2853 12:14:53.265096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2854 12:14:53.268207 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2855 12:14:53.275367 0 15 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2856 12:14:53.278661 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 12:14:53.281673 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 12:14:53.288661 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 12:14:53.291625 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 12:14:53.294921 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 12:14:53.301553 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2862 12:14:53.304666 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
2863 12:14:53.308517 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
2864 12:14:53.314762 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 12:14:53.317831 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 12:14:53.321686 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 12:14:53.328081 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 12:14:53.331756 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 12:14:53.335186 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2870 12:14:53.341357 1 0 28 | B1->B0 | 2626 4242 | 0 0 | (0 0) (0 0)
2871 12:14:53.344437 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2872 12:14:53.348285 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 12:14:53.354640 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 12:14:53.357835 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 12:14:53.361314 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 12:14:53.364966 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 12:14:53.371447 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2878 12:14:53.374580 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2879 12:14:53.378094 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 12:14:53.384646 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 12:14:53.388007 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 12:14:53.391118 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:14:53.397831 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:14:53.401055 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:14:53.404722 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:14:53.411052 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:14:53.414867 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:14:53.417844 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:14:53.424198 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:14:53.427487 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:14:53.431149 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:14:53.437477 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:14:53.441362 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2894 12:14:53.444322 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2895 12:14:53.450620 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2896 12:14:53.450706 Total UI for P1: 0, mck2ui 16
2897 12:14:53.457489 best dqsien dly found for B0: ( 1, 3, 26)
2898 12:14:53.460627 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 12:14:53.464237 Total UI for P1: 0, mck2ui 16
2900 12:14:53.467685 best dqsien dly found for B1: ( 1, 4, 0)
2901 12:14:53.470681 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2902 12:14:53.474158 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2903 12:14:53.474264
2904 12:14:53.477125 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2905 12:14:53.480859 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2906 12:14:53.483819 [Gating] SW calibration Done
2907 12:14:53.483890 ==
2908 12:14:53.487469 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 12:14:53.490528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 12:14:53.490606 ==
2911 12:14:53.494098 RX Vref Scan: 0
2912 12:14:53.494197
2913 12:14:53.497242 RX Vref 0 -> 0, step: 1
2914 12:14:53.497320
2915 12:14:53.497383 RX Delay -40 -> 252, step: 8
2916 12:14:53.503877 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2917 12:14:53.507058 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2918 12:14:53.510779 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2919 12:14:53.514104 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2920 12:14:53.517080 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2921 12:14:53.524138 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2922 12:14:53.527181 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2923 12:14:53.530515 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2924 12:14:53.533717 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2925 12:14:53.536948 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2926 12:14:53.543860 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2927 12:14:53.547116 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2928 12:14:53.550182 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2929 12:14:53.554119 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2930 12:14:53.557277 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2931 12:14:53.563552 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2932 12:14:53.563631 ==
2933 12:14:53.566689 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 12:14:53.570358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 12:14:53.570452 ==
2936 12:14:53.570517 DQS Delay:
2937 12:14:53.573287 DQS0 = 0, DQS1 = 0
2938 12:14:53.573373 DQM Delay:
2939 12:14:53.576732 DQM0 = 112, DQM1 = 102
2940 12:14:53.576814 DQ Delay:
2941 12:14:53.579958 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2942 12:14:53.583522 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2943 12:14:53.586716 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2944 12:14:53.590205 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2945 12:14:53.590288
2946 12:14:53.590353
2947 12:14:53.593354 ==
2948 12:14:53.596895 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 12:14:53.599842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 12:14:53.599925 ==
2951 12:14:53.599990
2952 12:14:53.600049
2953 12:14:53.603425 TX Vref Scan disable
2954 12:14:53.603508 == TX Byte 0 ==
2955 12:14:53.606534 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2956 12:14:53.613399 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2957 12:14:53.613484 == TX Byte 1 ==
2958 12:14:53.619916 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2959 12:14:53.623179 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2960 12:14:53.623265 ==
2961 12:14:53.626340 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 12:14:53.629475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 12:14:53.629558 ==
2964 12:14:53.642419 TX Vref=22, minBit 2, minWin=26, winSum=429
2965 12:14:53.645446 TX Vref=24, minBit 1, minWin=26, winSum=434
2966 12:14:53.648664 TX Vref=26, minBit 0, minWin=27, winSum=436
2967 12:14:53.652396 TX Vref=28, minBit 0, minWin=27, winSum=440
2968 12:14:53.655463 TX Vref=30, minBit 10, minWin=26, winSum=442
2969 12:14:53.662333 TX Vref=32, minBit 10, minWin=26, winSum=441
2970 12:14:53.665480 [TxChooseVref] Worse bit 0, Min win 27, Win sum 440, Final Vref 28
2971 12:14:53.665562
2972 12:14:53.668592 Final TX Range 1 Vref 28
2973 12:14:53.668687
2974 12:14:53.668781 ==
2975 12:14:53.672336 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 12:14:53.675588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 12:14:53.678483 ==
2978 12:14:53.678594
2979 12:14:53.678673
2980 12:14:53.678749 TX Vref Scan disable
2981 12:14:53.682095 == TX Byte 0 ==
2982 12:14:53.685573 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2983 12:14:53.692308 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2984 12:14:53.692396 == TX Byte 1 ==
2985 12:14:53.695360 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2986 12:14:53.702306 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2987 12:14:53.702390
2988 12:14:53.702455 [DATLAT]
2989 12:14:53.702515 Freq=1200, CH0 RK1
2990 12:14:53.702573
2991 12:14:53.705509 DATLAT Default: 0xd
2992 12:14:53.708324 0, 0xFFFF, sum = 0
2993 12:14:53.708439 1, 0xFFFF, sum = 0
2994 12:14:53.711910 2, 0xFFFF, sum = 0
2995 12:14:53.711994 3, 0xFFFF, sum = 0
2996 12:14:53.715098 4, 0xFFFF, sum = 0
2997 12:14:53.715182 5, 0xFFFF, sum = 0
2998 12:14:53.718285 6, 0xFFFF, sum = 0
2999 12:14:53.718369 7, 0xFFFF, sum = 0
3000 12:14:53.721980 8, 0xFFFF, sum = 0
3001 12:14:53.722065 9, 0xFFFF, sum = 0
3002 12:14:53.725046 10, 0xFFFF, sum = 0
3003 12:14:53.725130 11, 0xFFFF, sum = 0
3004 12:14:53.728233 12, 0x0, sum = 1
3005 12:14:53.728360 13, 0x0, sum = 2
3006 12:14:53.731878 14, 0x0, sum = 3
3007 12:14:53.732035 15, 0x0, sum = 4
3008 12:14:53.735164 best_step = 13
3009 12:14:53.735246
3010 12:14:53.735311 ==
3011 12:14:53.738269 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 12:14:53.742213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 12:14:53.742296 ==
3014 12:14:53.742361 RX Vref Scan: 0
3015 12:14:53.745179
3016 12:14:53.745261 RX Vref 0 -> 0, step: 1
3017 12:14:53.745326
3018 12:14:53.748235 RX Delay -37 -> 252, step: 4
3019 12:14:53.755185 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3020 12:14:53.758315 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3021 12:14:53.761362 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3022 12:14:53.765424 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3023 12:14:53.768539 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3024 12:14:53.774816 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3025 12:14:53.778017 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3026 12:14:53.781721 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3027 12:14:53.784702 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3028 12:14:53.788203 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3029 12:14:53.791444 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3030 12:14:53.798016 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3031 12:14:53.801107 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3032 12:14:53.804401 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3033 12:14:53.807981 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3034 12:14:53.814382 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3035 12:14:53.814491 ==
3036 12:14:53.817893 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 12:14:53.821228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 12:14:53.821333 ==
3039 12:14:53.821426 DQS Delay:
3040 12:14:53.824761 DQS0 = 0, DQS1 = 0
3041 12:14:53.824863 DQM Delay:
3042 12:14:53.827777 DQM0 = 111, DQM1 = 101
3043 12:14:53.827919 DQ Delay:
3044 12:14:53.831574 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3045 12:14:53.834599 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3046 12:14:53.837637 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =94
3047 12:14:53.841652 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3048 12:14:53.841746
3049 12:14:53.841824
3050 12:14:53.850953 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3051 12:14:53.854951 CH0 RK1: MR19=403, MR18=10F8
3052 12:14:53.858026 CH0_RK1: MR19=0x403, MR18=0x10F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3053 12:14:53.861193 [RxdqsGatingPostProcess] freq 1200
3054 12:14:53.867423 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3055 12:14:53.871165 best DQS0 dly(2T, 0.5T) = (0, 12)
3056 12:14:53.874395 best DQS1 dly(2T, 0.5T) = (0, 12)
3057 12:14:53.877538 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3058 12:14:53.880684 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3059 12:14:53.884607 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 12:14:53.887694 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 12:14:53.890749 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 12:14:53.894102 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 12:14:53.894185 Pre-setting of DQS Precalculation
3064 12:14:53.900584 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3065 12:14:53.900670 ==
3066 12:14:53.904056 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 12:14:53.907660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 12:14:53.907742 ==
3069 12:14:53.913927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3070 12:14:53.920504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3071 12:14:53.928835 [CA 0] Center 38 (8~68) winsize 61
3072 12:14:53.931465 [CA 1] Center 38 (8~69) winsize 62
3073 12:14:53.935046 [CA 2] Center 35 (5~65) winsize 61
3074 12:14:53.938511 [CA 3] Center 34 (4~65) winsize 62
3075 12:14:53.941416 [CA 4] Center 35 (5~65) winsize 61
3076 12:14:53.944839 [CA 5] Center 34 (4~64) winsize 61
3077 12:14:53.944923
3078 12:14:53.948410 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3079 12:14:53.948494
3080 12:14:53.951472 [CATrainingPosCal] consider 1 rank data
3081 12:14:53.954657 u2DelayCellTimex100 = 270/100 ps
3082 12:14:53.958428 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3083 12:14:53.964780 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
3084 12:14:53.967846 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3085 12:14:53.970971 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3086 12:14:53.974302 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3087 12:14:53.978238 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3088 12:14:53.978322
3089 12:14:53.981070 CA PerBit enable=1, Macro0, CA PI delay=34
3090 12:14:53.981154
3091 12:14:53.984622 [CBTSetCACLKResult] CA Dly = 34
3092 12:14:53.987660 CS Dly: 6 (0~37)
3093 12:14:53.987744 ==
3094 12:14:53.991276 Dram Type= 6, Freq= 0, CH_1, rank 1
3095 12:14:53.994320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 12:14:53.994405 ==
3097 12:14:54.001137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 12:14:54.004514 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3099 12:14:54.013896 [CA 0] Center 38 (8~68) winsize 61
3100 12:14:54.017180 [CA 1] Center 38 (8~69) winsize 62
3101 12:14:54.020285 [CA 2] Center 35 (5~66) winsize 62
3102 12:14:54.023963 [CA 3] Center 34 (4~65) winsize 62
3103 12:14:54.027449 [CA 4] Center 35 (5~65) winsize 61
3104 12:14:54.030501 [CA 5] Center 33 (3~64) winsize 62
3105 12:14:54.030586
3106 12:14:54.033599 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3107 12:14:54.033684
3108 12:14:54.037050 [CATrainingPosCal] consider 2 rank data
3109 12:14:54.040148 u2DelayCellTimex100 = 270/100 ps
3110 12:14:54.043607 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3111 12:14:54.050279 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
3112 12:14:54.053378 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3113 12:14:54.057246 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3114 12:14:54.060405 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3115 12:14:54.063409 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3116 12:14:54.063491
3117 12:14:54.066462 CA PerBit enable=1, Macro0, CA PI delay=34
3118 12:14:54.066544
3119 12:14:54.069605 [CBTSetCACLKResult] CA Dly = 34
3120 12:14:54.073326 CS Dly: 8 (0~41)
3121 12:14:54.073417
3122 12:14:54.076473 ----->DramcWriteLeveling(PI) begin...
3123 12:14:54.076557 ==
3124 12:14:54.079826 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 12:14:54.082939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 12:14:54.083024 ==
3127 12:14:54.086757 Write leveling (Byte 0): 23 => 23
3128 12:14:54.089833 Write leveling (Byte 1): 30 => 30
3129 12:14:54.093109 DramcWriteLeveling(PI) end<-----
3130 12:14:54.093207
3131 12:14:54.093303 ==
3132 12:14:54.096200 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 12:14:54.100071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 12:14:54.100170 ==
3135 12:14:54.103274 [Gating] SW mode calibration
3136 12:14:54.109373 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3137 12:14:54.116648 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3138 12:14:54.119548 0 15 0 | B1->B0 | 2726 2828 | 1 1 | (0 0) (0 0)
3139 12:14:54.122966 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 12:14:54.129534 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 12:14:54.133084 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 12:14:54.135870 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 12:14:54.142931 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 12:14:54.145808 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 12:14:54.149106 0 15 28 | B1->B0 | 3333 3333 | 1 1 | (1 0) (1 0)
3146 12:14:54.156046 1 0 0 | B1->B0 | 2424 2424 | 0 0 | (1 0) (0 0)
3147 12:14:54.159404 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 12:14:54.162180 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 12:14:54.169268 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 12:14:54.172198 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 12:14:54.176142 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 12:14:54.182351 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 12:14:54.185561 1 0 28 | B1->B0 | 3535 3333 | 1 0 | (0 0) (0 0)
3154 12:14:54.188720 1 1 0 | B1->B0 | 4141 4242 | 0 1 | (0 0) (0 0)
3155 12:14:54.195159 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 12:14:54.198942 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 12:14:54.201840 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 12:14:54.208546 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 12:14:54.212156 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 12:14:54.215252 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 12:14:54.222079 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3162 12:14:54.225193 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 12:14:54.228172 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 12:14:54.235072 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 12:14:54.238130 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:14:54.241846 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:14:54.248260 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:14:54.251699 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:14:54.254585 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:14:54.261385 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:14:54.264559 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:14:54.268078 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:14:54.274859 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:14:54.278026 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:14:54.281303 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:14:54.288135 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:14:54.291334 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3178 12:14:54.294800 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 12:14:54.297912 Total UI for P1: 0, mck2ui 16
3180 12:14:54.301173 best dqsien dly found for B0: ( 1, 3, 28)
3181 12:14:54.304803 Total UI for P1: 0, mck2ui 16
3182 12:14:54.307907 best dqsien dly found for B1: ( 1, 3, 28)
3183 12:14:54.311192 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3184 12:14:54.314252 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3185 12:14:54.314350
3186 12:14:54.320920 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3187 12:14:54.324030 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3188 12:14:54.327759 [Gating] SW calibration Done
3189 12:14:54.327841 ==
3190 12:14:54.330842 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 12:14:54.334389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 12:14:54.334501 ==
3193 12:14:54.334580 RX Vref Scan: 0
3194 12:14:54.334669
3195 12:14:54.337381 RX Vref 0 -> 0, step: 1
3196 12:14:54.337461
3197 12:14:54.340662 RX Delay -40 -> 252, step: 8
3198 12:14:54.344388 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3199 12:14:54.347231 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3200 12:14:54.353896 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3201 12:14:54.357673 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3202 12:14:54.360581 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3203 12:14:54.363788 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3204 12:14:54.367311 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3205 12:14:54.373872 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3206 12:14:54.377109 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3207 12:14:54.380555 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3208 12:14:54.383733 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3209 12:14:54.386841 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3210 12:14:54.393783 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3211 12:14:54.396901 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3212 12:14:54.400691 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3213 12:14:54.403869 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3214 12:14:54.403977 ==
3215 12:14:54.407004 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 12:14:54.413401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 12:14:54.413493 ==
3218 12:14:54.413587 DQS Delay:
3219 12:14:54.413695 DQS0 = 0, DQS1 = 0
3220 12:14:54.417148 DQM Delay:
3221 12:14:54.417235 DQM0 = 116, DQM1 = 108
3222 12:14:54.420211 DQ Delay:
3223 12:14:54.423893 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3224 12:14:54.427160 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =119
3225 12:14:54.430277 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =103
3226 12:14:54.433489 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =111
3227 12:14:54.433561
3228 12:14:54.433632
3229 12:14:54.433690 ==
3230 12:14:54.436672 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 12:14:54.439803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 12:14:54.443397 ==
3233 12:14:54.443496
3234 12:14:54.443570
3235 12:14:54.443691 TX Vref Scan disable
3236 12:14:54.447044 == TX Byte 0 ==
3237 12:14:54.450037 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3238 12:14:54.453664 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3239 12:14:54.456776 == TX Byte 1 ==
3240 12:14:54.460340 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3241 12:14:54.463103 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3242 12:14:54.463185 ==
3243 12:14:54.466886 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 12:14:54.473370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 12:14:54.473453 ==
3246 12:14:54.484414 TX Vref=22, minBit 1, minWin=24, winSum=405
3247 12:14:54.487974 TX Vref=24, minBit 1, minWin=24, winSum=411
3248 12:14:54.491275 TX Vref=26, minBit 1, minWin=24, winSum=414
3249 12:14:54.494448 TX Vref=28, minBit 1, minWin=25, winSum=422
3250 12:14:54.497564 TX Vref=30, minBit 0, minWin=25, winSum=421
3251 12:14:54.504063 TX Vref=32, minBit 1, minWin=25, winSum=413
3252 12:14:54.508070 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28
3253 12:14:54.508164
3254 12:14:54.510970 Final TX Range 1 Vref 28
3255 12:14:54.511068
3256 12:14:54.511134 ==
3257 12:14:54.514112 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 12:14:54.517341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 12:14:54.520994 ==
3260 12:14:54.521095
3261 12:14:54.521195
3262 12:14:54.521283 TX Vref Scan disable
3263 12:14:54.524035 == TX Byte 0 ==
3264 12:14:54.527596 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3265 12:14:54.534290 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3266 12:14:54.534391 == TX Byte 1 ==
3267 12:14:54.537470 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3268 12:14:54.541140 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3269 12:14:54.544578
3270 12:14:54.544679 [DATLAT]
3271 12:14:54.544777 Freq=1200, CH1 RK0
3272 12:14:54.544866
3273 12:14:54.547545 DATLAT Default: 0xd
3274 12:14:54.547616 0, 0xFFFF, sum = 0
3275 12:14:54.550700 1, 0xFFFF, sum = 0
3276 12:14:54.550773 2, 0xFFFF, sum = 0
3277 12:14:54.553895 3, 0xFFFF, sum = 0
3278 12:14:54.557628 4, 0xFFFF, sum = 0
3279 12:14:54.557713 5, 0xFFFF, sum = 0
3280 12:14:54.560689 6, 0xFFFF, sum = 0
3281 12:14:54.560774 7, 0xFFFF, sum = 0
3282 12:14:54.564159 8, 0xFFFF, sum = 0
3283 12:14:54.564244 9, 0xFFFF, sum = 0
3284 12:14:54.567303 10, 0xFFFF, sum = 0
3285 12:14:54.567388 11, 0xFFFF, sum = 0
3286 12:14:54.570793 12, 0x0, sum = 1
3287 12:14:54.570915 13, 0x0, sum = 2
3288 12:14:54.573911 14, 0x0, sum = 3
3289 12:14:54.574029 15, 0x0, sum = 4
3290 12:14:54.577490 best_step = 13
3291 12:14:54.577570
3292 12:14:54.577671 ==
3293 12:14:54.580666 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 12:14:54.583905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 12:14:54.583983 ==
3296 12:14:54.584046 RX Vref Scan: 1
3297 12:14:54.584113
3298 12:14:54.587468 Set Vref Range= 32 -> 127
3299 12:14:54.587568
3300 12:14:54.590938 RX Vref 32 -> 127, step: 1
3301 12:14:54.591010
3302 12:14:54.593954 RX Delay -21 -> 252, step: 4
3303 12:14:54.594034
3304 12:14:54.597050 Set Vref, RX VrefLevel [Byte0]: 32
3305 12:14:54.600262 [Byte1]: 32
3306 12:14:54.600347
3307 12:14:54.603915 Set Vref, RX VrefLevel [Byte0]: 33
3308 12:14:54.607181 [Byte1]: 33
3309 12:14:54.610740
3310 12:14:54.610882 Set Vref, RX VrefLevel [Byte0]: 34
3311 12:14:54.613897 [Byte1]: 34
3312 12:14:54.619050
3313 12:14:54.619149 Set Vref, RX VrefLevel [Byte0]: 35
3314 12:14:54.622283 [Byte1]: 35
3315 12:14:54.626753
3316 12:14:54.626825 Set Vref, RX VrefLevel [Byte0]: 36
3317 12:14:54.629654 [Byte1]: 36
3318 12:14:54.634400
3319 12:14:54.634501 Set Vref, RX VrefLevel [Byte0]: 37
3320 12:14:54.637611 [Byte1]: 37
3321 12:14:54.642608
3322 12:14:54.642681 Set Vref, RX VrefLevel [Byte0]: 38
3323 12:14:54.645616 [Byte1]: 38
3324 12:14:54.650406
3325 12:14:54.650487 Set Vref, RX VrefLevel [Byte0]: 39
3326 12:14:54.653439 [Byte1]: 39
3327 12:14:54.658472
3328 12:14:54.658547 Set Vref, RX VrefLevel [Byte0]: 40
3329 12:14:54.661695 [Byte1]: 40
3330 12:14:54.666261
3331 12:14:54.666334 Set Vref, RX VrefLevel [Byte0]: 41
3332 12:14:54.669696 [Byte1]: 41
3333 12:14:54.674395
3334 12:14:54.674476 Set Vref, RX VrefLevel [Byte0]: 42
3335 12:14:54.677223 [Byte1]: 42
3336 12:14:54.681828
3337 12:14:54.681930 Set Vref, RX VrefLevel [Byte0]: 43
3338 12:14:54.685308 [Byte1]: 43
3339 12:14:54.690026
3340 12:14:54.690113 Set Vref, RX VrefLevel [Byte0]: 44
3341 12:14:54.692960 [Byte1]: 44
3342 12:14:54.697637
3343 12:14:54.697717 Set Vref, RX VrefLevel [Byte0]: 45
3344 12:14:54.701313 [Byte1]: 45
3345 12:14:54.705920
3346 12:14:54.705999 Set Vref, RX VrefLevel [Byte0]: 46
3347 12:14:54.709000 [Byte1]: 46
3348 12:14:54.713916
3349 12:14:54.713996 Set Vref, RX VrefLevel [Byte0]: 47
3350 12:14:54.717299 [Byte1]: 47
3351 12:14:54.721672
3352 12:14:54.721752 Set Vref, RX VrefLevel [Byte0]: 48
3353 12:14:54.727807 [Byte1]: 48
3354 12:14:54.727887
3355 12:14:54.731642 Set Vref, RX VrefLevel [Byte0]: 49
3356 12:14:54.734716 [Byte1]: 49
3357 12:14:54.734818
3358 12:14:54.737779 Set Vref, RX VrefLevel [Byte0]: 50
3359 12:14:54.741532 [Byte1]: 50
3360 12:14:54.745398
3361 12:14:54.745478 Set Vref, RX VrefLevel [Byte0]: 51
3362 12:14:54.749044 [Byte1]: 51
3363 12:14:54.753264
3364 12:14:54.753358 Set Vref, RX VrefLevel [Byte0]: 52
3365 12:14:54.756967 [Byte1]: 52
3366 12:14:54.761464
3367 12:14:54.761564 Set Vref, RX VrefLevel [Byte0]: 53
3368 12:14:54.764383 [Byte1]: 53
3369 12:14:54.769370
3370 12:14:54.769451 Set Vref, RX VrefLevel [Byte0]: 54
3371 12:14:54.772432 [Byte1]: 54
3372 12:14:54.777350
3373 12:14:54.777436 Set Vref, RX VrefLevel [Byte0]: 55
3374 12:14:54.780438 [Byte1]: 55
3375 12:14:54.785405
3376 12:14:54.785558 Set Vref, RX VrefLevel [Byte0]: 56
3377 12:14:54.788278 [Byte1]: 56
3378 12:14:54.793081
3379 12:14:54.793215 Set Vref, RX VrefLevel [Byte0]: 57
3380 12:14:54.796598 [Byte1]: 57
3381 12:14:54.800728
3382 12:14:54.800834 Set Vref, RX VrefLevel [Byte0]: 58
3383 12:14:54.804441 [Byte1]: 58
3384 12:14:54.808760
3385 12:14:54.808909 Set Vref, RX VrefLevel [Byte0]: 59
3386 12:14:54.811898 [Byte1]: 59
3387 12:14:54.817054
3388 12:14:54.817149 Set Vref, RX VrefLevel [Byte0]: 60
3389 12:14:54.820390 [Byte1]: 60
3390 12:14:54.824473
3391 12:14:54.824567 Set Vref, RX VrefLevel [Byte0]: 61
3392 12:14:54.827703 [Byte1]: 61
3393 12:14:54.832803
3394 12:14:54.832884 Set Vref, RX VrefLevel [Byte0]: 62
3395 12:14:54.835839 [Byte1]: 62
3396 12:14:54.840953
3397 12:14:54.841062 Set Vref, RX VrefLevel [Byte0]: 63
3398 12:14:54.843906 [Byte1]: 63
3399 12:14:54.848346
3400 12:14:54.848429 Set Vref, RX VrefLevel [Byte0]: 64
3401 12:14:54.851611 [Byte1]: 64
3402 12:14:54.856410
3403 12:14:54.856503 Set Vref, RX VrefLevel [Byte0]: 65
3404 12:14:54.859331 [Byte1]: 65
3405 12:14:54.864294
3406 12:14:54.864376 Set Vref, RX VrefLevel [Byte0]: 66
3407 12:14:54.867638 [Byte1]: 66
3408 12:14:54.871947
3409 12:14:54.872047 Set Vref, RX VrefLevel [Byte0]: 67
3410 12:14:54.875588 [Byte1]: 67
3411 12:14:54.880096
3412 12:14:54.880174 Set Vref, RX VrefLevel [Byte0]: 68
3413 12:14:54.883137 [Byte1]: 68
3414 12:14:54.888269
3415 12:14:54.888353 Set Vref, RX VrefLevel [Byte0]: 69
3416 12:14:54.891162 [Byte1]: 69
3417 12:14:54.895902
3418 12:14:54.896004 Final RX Vref Byte 0 = 58 to rank0
3419 12:14:54.899367 Final RX Vref Byte 1 = 49 to rank0
3420 12:14:54.902409 Final RX Vref Byte 0 = 58 to rank1
3421 12:14:54.906162 Final RX Vref Byte 1 = 49 to rank1==
3422 12:14:54.908973 Dram Type= 6, Freq= 0, CH_1, rank 0
3423 12:14:54.915953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 12:14:54.916070 ==
3425 12:14:54.916177 DQS Delay:
3426 12:14:54.916279 DQS0 = 0, DQS1 = 0
3427 12:14:54.919552 DQM Delay:
3428 12:14:54.919629 DQM0 = 118, DQM1 = 109
3429 12:14:54.922707 DQ Delay:
3430 12:14:54.925901 DQ0 =120, DQ1 =114, DQ2 =108, DQ3 =116
3431 12:14:54.929399 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =116
3432 12:14:54.932378 DQ8 =96, DQ9 =100, DQ10 =106, DQ11 =100
3433 12:14:54.935932 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3434 12:14:54.936012
3435 12:14:54.936120
3436 12:14:54.945810 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3437 12:14:54.945921 CH1 RK0: MR19=303, MR18=ECF3
3438 12:14:54.952598 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3439 12:14:54.952696
3440 12:14:54.955805 ----->DramcWriteLeveling(PI) begin...
3441 12:14:54.955890 ==
3442 12:14:54.959000 Dram Type= 6, Freq= 0, CH_1, rank 1
3443 12:14:54.965785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3444 12:14:54.965888 ==
3445 12:14:54.968987 Write leveling (Byte 0): 24 => 24
3446 12:14:54.969066 Write leveling (Byte 1): 26 => 26
3447 12:14:54.972065 DramcWriteLeveling(PI) end<-----
3448 12:14:54.972152
3449 12:14:54.975754 ==
3450 12:14:54.975870 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 12:14:54.981911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 12:14:54.982000 ==
3453 12:14:54.985557 [Gating] SW mode calibration
3454 12:14:54.992185 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3455 12:14:54.995455 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3456 12:14:55.001908 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3457 12:14:55.005291 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 12:14:55.008890 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 12:14:55.015662 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 12:14:55.018798 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 12:14:55.022034 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 12:14:55.028731 0 15 24 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
3463 12:14:55.031875 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3464 12:14:55.034986 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 12:14:55.041684 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 12:14:55.044810 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 12:14:55.048386 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 12:14:55.055041 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 12:14:55.058100 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3470 12:14:55.061396 1 0 24 | B1->B0 | 2929 4444 | 0 0 | (0 0) (0 0)
3471 12:14:55.068150 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 12:14:55.071135 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 12:14:55.074128 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 12:14:55.081369 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 12:14:55.084366 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 12:14:55.087414 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 12:14:55.094181 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3478 12:14:55.097327 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3479 12:14:55.101132 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3480 12:14:55.107478 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 12:14:55.110825 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 12:14:55.114325 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 12:14:55.120842 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 12:14:55.123792 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 12:14:55.127290 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 12:14:55.133615 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 12:14:55.137411 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 12:14:55.140520 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 12:14:55.147381 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 12:14:55.150390 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 12:14:55.153411 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 12:14:55.160293 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 12:14:55.163360 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 12:14:55.167155 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3495 12:14:55.173090 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3496 12:14:55.173184 Total UI for P1: 0, mck2ui 16
3497 12:14:55.180048 best dqsien dly found for B0: ( 1, 3, 24)
3498 12:14:55.183236 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 12:14:55.186507 Total UI for P1: 0, mck2ui 16
3500 12:14:55.190139 best dqsien dly found for B1: ( 1, 3, 28)
3501 12:14:55.193089 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3502 12:14:55.196402 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3503 12:14:55.196495
3504 12:14:55.199685 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3505 12:14:55.203032 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3506 12:14:55.206051 [Gating] SW calibration Done
3507 12:14:55.206149 ==
3508 12:14:55.209294 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 12:14:55.216158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 12:14:55.216262 ==
3511 12:14:55.216354 RX Vref Scan: 0
3512 12:14:55.216435
3513 12:14:55.219722 RX Vref 0 -> 0, step: 1
3514 12:14:55.219810
3515 12:14:55.222950 RX Delay -40 -> 252, step: 8
3516 12:14:55.226274 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3517 12:14:55.229137 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3518 12:14:55.232647 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3519 12:14:55.239452 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3520 12:14:55.242785 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3521 12:14:55.245722 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3522 12:14:55.248860 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3523 12:14:55.252879 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3524 12:14:55.255749 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3525 12:14:55.262556 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3526 12:14:55.265861 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3527 12:14:55.268974 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3528 12:14:55.272177 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3529 12:14:55.278754 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3530 12:14:55.281755 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3531 12:14:55.285425 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3532 12:14:55.285509 ==
3533 12:14:55.288607 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 12:14:55.291724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 12:14:55.291808 ==
3536 12:14:55.295298 DQS Delay:
3537 12:14:55.295380 DQS0 = 0, DQS1 = 0
3538 12:14:55.298458 DQM Delay:
3539 12:14:55.298541 DQM0 = 113, DQM1 = 110
3540 12:14:55.302118 DQ Delay:
3541 12:14:55.305240 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3542 12:14:55.308526 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3543 12:14:55.311639 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =103
3544 12:14:55.315455 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3545 12:14:55.315543
3546 12:14:55.315609
3547 12:14:55.315670 ==
3548 12:14:55.318662 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 12:14:55.321862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 12:14:55.321973 ==
3551 12:14:55.322066
3552 12:14:55.322162
3553 12:14:55.325365 TX Vref Scan disable
3554 12:14:55.328423 == TX Byte 0 ==
3555 12:14:55.332013 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3556 12:14:55.334882 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3557 12:14:55.338398 == TX Byte 1 ==
3558 12:14:55.341988 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3559 12:14:55.344885 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3560 12:14:55.344966 ==
3561 12:14:55.348413 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 12:14:55.354669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 12:14:55.354776 ==
3564 12:14:55.365136 TX Vref=22, minBit 1, minWin=24, winSum=410
3565 12:14:55.368140 TX Vref=24, minBit 0, minWin=25, winSum=420
3566 12:14:55.371925 TX Vref=26, minBit 0, minWin=25, winSum=425
3567 12:14:55.375194 TX Vref=28, minBit 0, minWin=25, winSum=422
3568 12:14:55.378320 TX Vref=30, minBit 1, minWin=25, winSum=423
3569 12:14:55.385067 TX Vref=32, minBit 0, minWin=26, winSum=425
3570 12:14:55.388139 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 32
3571 12:14:55.388217
3572 12:14:55.391682 Final TX Range 1 Vref 32
3573 12:14:55.391759
3574 12:14:55.391826 ==
3575 12:14:55.394861 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 12:14:55.398091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 12:14:55.401132 ==
3578 12:14:55.401214
3579 12:14:55.401277
3580 12:14:55.401336 TX Vref Scan disable
3581 12:14:55.404872 == TX Byte 0 ==
3582 12:14:55.408025 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3583 12:14:55.414650 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3584 12:14:55.414728 == TX Byte 1 ==
3585 12:14:55.417655 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3586 12:14:55.424379 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3587 12:14:55.424454
3588 12:14:55.424522 [DATLAT]
3589 12:14:55.424609 Freq=1200, CH1 RK1
3590 12:14:55.424670
3591 12:14:55.428093 DATLAT Default: 0xd
3592 12:14:55.431293 0, 0xFFFF, sum = 0
3593 12:14:55.431370 1, 0xFFFF, sum = 0
3594 12:14:55.434467 2, 0xFFFF, sum = 0
3595 12:14:55.434541 3, 0xFFFF, sum = 0
3596 12:14:55.437942 4, 0xFFFF, sum = 0
3597 12:14:55.438013 5, 0xFFFF, sum = 0
3598 12:14:55.440903 6, 0xFFFF, sum = 0
3599 12:14:55.440974 7, 0xFFFF, sum = 0
3600 12:14:55.444377 8, 0xFFFF, sum = 0
3601 12:14:55.444499 9, 0xFFFF, sum = 0
3602 12:14:55.447725 10, 0xFFFF, sum = 0
3603 12:14:55.447806 11, 0xFFFF, sum = 0
3604 12:14:55.450695 12, 0x0, sum = 1
3605 12:14:55.450809 13, 0x0, sum = 2
3606 12:14:55.454411 14, 0x0, sum = 3
3607 12:14:55.454489 15, 0x0, sum = 4
3608 12:14:55.457529 best_step = 13
3609 12:14:55.457631
3610 12:14:55.457726 ==
3611 12:14:55.460676 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 12:14:55.464307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 12:14:55.464388 ==
3614 12:14:55.467569 RX Vref Scan: 0
3615 12:14:55.467646
3616 12:14:55.467713 RX Vref 0 -> 0, step: 1
3617 12:14:55.467776
3618 12:14:55.470541 RX Delay -13 -> 252, step: 4
3619 12:14:55.477409 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3620 12:14:55.480802 iDelay=195, Bit 1, Center 110 (47 ~ 174) 128
3621 12:14:55.483759 iDelay=195, Bit 2, Center 104 (39 ~ 170) 132
3622 12:14:55.487516 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3623 12:14:55.490595 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3624 12:14:55.497390 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3625 12:14:55.500602 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3626 12:14:55.503713 iDelay=195, Bit 7, Center 112 (47 ~ 178) 132
3627 12:14:55.507395 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3628 12:14:55.510572 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3629 12:14:55.516862 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3630 12:14:55.520639 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3631 12:14:55.523836 iDelay=195, Bit 12, Center 122 (63 ~ 182) 120
3632 12:14:55.526959 iDelay=195, Bit 13, Center 122 (63 ~ 182) 120
3633 12:14:55.533614 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3634 12:14:55.536912 iDelay=195, Bit 15, Center 122 (63 ~ 182) 120
3635 12:14:55.537017 ==
3636 12:14:55.539965 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 12:14:55.543148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 12:14:55.543250 ==
3639 12:14:55.547156 DQS Delay:
3640 12:14:55.547228 DQS0 = 0, DQS1 = 0
3641 12:14:55.547288 DQM Delay:
3642 12:14:55.549864 DQM0 = 114, DQM1 = 114
3643 12:14:55.549959 DQ Delay:
3644 12:14:55.553001 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =112
3645 12:14:55.556509 DQ4 =110, DQ5 =124, DQ6 =126, DQ7 =112
3646 12:14:55.559936 DQ8 =100, DQ9 =104, DQ10 =116, DQ11 =106
3647 12:14:55.566080 DQ12 =122, DQ13 =122, DQ14 =120, DQ15 =122
3648 12:14:55.566183
3649 12:14:55.566274
3650 12:14:55.572953 [DQSOSCAuto] RK1, (LSB)MR18= 0xf808, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3651 12:14:55.576524 CH1 RK1: MR19=304, MR18=F808
3652 12:14:55.582784 CH1_RK1: MR19=0x304, MR18=0xF808, DQSOSC=406, MR23=63, INC=39, DEC=26
3653 12:14:55.586036 [RxdqsGatingPostProcess] freq 1200
3654 12:14:55.589685 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3655 12:14:55.592623 best DQS0 dly(2T, 0.5T) = (0, 11)
3656 12:14:55.596343 best DQS1 dly(2T, 0.5T) = (0, 11)
3657 12:14:55.599811 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3658 12:14:55.602747 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3659 12:14:55.606035 best DQS0 dly(2T, 0.5T) = (0, 11)
3660 12:14:55.609157 best DQS1 dly(2T, 0.5T) = (0, 11)
3661 12:14:55.612800 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3662 12:14:55.615924 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3663 12:14:55.619091 Pre-setting of DQS Precalculation
3664 12:14:55.625424 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3665 12:14:55.632497 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3666 12:14:55.638382 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3667 12:14:55.638468
3668 12:14:55.638532
3669 12:14:55.642183 [Calibration Summary] 2400 Mbps
3670 12:14:55.642267 CH 0, Rank 0
3671 12:14:55.645364 SW Impedance : PASS
3672 12:14:55.648579 DUTY Scan : NO K
3673 12:14:55.648661 ZQ Calibration : PASS
3674 12:14:55.651941 Jitter Meter : NO K
3675 12:14:55.654946 CBT Training : PASS
3676 12:14:55.655074 Write leveling : PASS
3677 12:14:55.658588 RX DQS gating : PASS
3678 12:14:55.661938 RX DQ/DQS(RDDQC) : PASS
3679 12:14:55.662021 TX DQ/DQS : PASS
3680 12:14:55.665306 RX DATLAT : PASS
3681 12:14:55.668601 RX DQ/DQS(Engine): PASS
3682 12:14:55.668682 TX OE : NO K
3683 12:14:55.668747 All Pass.
3684 12:14:55.671615
3685 12:14:55.671696 CH 0, Rank 1
3686 12:14:55.675230 SW Impedance : PASS
3687 12:14:55.675312 DUTY Scan : NO K
3688 12:14:55.678300 ZQ Calibration : PASS
3689 12:14:55.678386 Jitter Meter : NO K
3690 12:14:55.681797 CBT Training : PASS
3691 12:14:55.684870 Write leveling : PASS
3692 12:14:55.685007 RX DQS gating : PASS
3693 12:14:55.688468 RX DQ/DQS(RDDQC) : PASS
3694 12:14:55.691938 TX DQ/DQS : PASS
3695 12:14:55.692100 RX DATLAT : PASS
3696 12:14:55.694645 RX DQ/DQS(Engine): PASS
3697 12:14:55.697797 TX OE : NO K
3698 12:14:55.697880 All Pass.
3699 12:14:55.697945
3700 12:14:55.698005 CH 1, Rank 0
3701 12:14:55.701438 SW Impedance : PASS
3702 12:14:55.705027 DUTY Scan : NO K
3703 12:14:55.705147 ZQ Calibration : PASS
3704 12:14:55.707834 Jitter Meter : NO K
3705 12:14:55.711118 CBT Training : PASS
3706 12:14:55.711197 Write leveling : PASS
3707 12:14:55.714266 RX DQS gating : PASS
3708 12:14:55.717415 RX DQ/DQS(RDDQC) : PASS
3709 12:14:55.717491 TX DQ/DQS : PASS
3710 12:14:55.720620 RX DATLAT : PASS
3711 12:14:55.724373 RX DQ/DQS(Engine): PASS
3712 12:14:55.724452 TX OE : NO K
3713 12:14:55.727573 All Pass.
3714 12:14:55.727646
3715 12:14:55.727707 CH 1, Rank 1
3716 12:14:55.730609 SW Impedance : PASS
3717 12:14:55.730708 DUTY Scan : NO K
3718 12:14:55.733775 ZQ Calibration : PASS
3719 12:14:55.737523 Jitter Meter : NO K
3720 12:14:55.737625 CBT Training : PASS
3721 12:14:55.740553 Write leveling : PASS
3722 12:14:55.743609 RX DQS gating : PASS
3723 12:14:55.743715 RX DQ/DQS(RDDQC) : PASS
3724 12:14:55.746847 TX DQ/DQS : PASS
3725 12:14:55.750755 RX DATLAT : PASS
3726 12:14:55.750879 RX DQ/DQS(Engine): PASS
3727 12:14:55.753903 TX OE : NO K
3728 12:14:55.753991 All Pass.
3729 12:14:55.754058
3730 12:14:55.757055 DramC Write-DBI off
3731 12:14:55.760222 PER_BANK_REFRESH: Hybrid Mode
3732 12:14:55.760309 TX_TRACKING: ON
3733 12:14:55.770173 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3734 12:14:55.773698 [FAST_K] Save calibration result to emmc
3735 12:14:55.776726 dramc_set_vcore_voltage set vcore to 650000
3736 12:14:55.780322 Read voltage for 600, 5
3737 12:14:55.780417 Vio18 = 0
3738 12:14:55.780485 Vcore = 650000
3739 12:14:55.783633 Vdram = 0
3740 12:14:55.783733 Vddq = 0
3741 12:14:55.783800 Vmddr = 0
3742 12:14:55.789942 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3743 12:14:55.793640 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3744 12:14:55.796652 MEM_TYPE=3, freq_sel=19
3745 12:14:55.800360 sv_algorithm_assistance_LP4_1600
3746 12:14:55.803376 ============ PULL DRAM RESETB DOWN ============
3747 12:14:55.806288 ========== PULL DRAM RESETB DOWN end =========
3748 12:14:55.813221 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3749 12:14:55.816315 ===================================
3750 12:14:55.820005 LPDDR4 DRAM CONFIGURATION
3751 12:14:55.823188 ===================================
3752 12:14:55.823271 EX_ROW_EN[0] = 0x0
3753 12:14:55.826382 EX_ROW_EN[1] = 0x0
3754 12:14:55.826457 LP4Y_EN = 0x0
3755 12:14:55.829540 WORK_FSP = 0x0
3756 12:14:55.829624 WL = 0x2
3757 12:14:55.832647 RL = 0x2
3758 12:14:55.832724 BL = 0x2
3759 12:14:55.836495 RPST = 0x0
3760 12:14:55.836573 RD_PRE = 0x0
3761 12:14:55.839652 WR_PRE = 0x1
3762 12:14:55.839735 WR_PST = 0x0
3763 12:14:55.842453 DBI_WR = 0x0
3764 12:14:55.846004 DBI_RD = 0x0
3765 12:14:55.846091 OTF = 0x1
3766 12:14:55.849076 ===================================
3767 12:14:55.852907 ===================================
3768 12:14:55.852993 ANA top config
3769 12:14:55.856124 ===================================
3770 12:14:55.859387 DLL_ASYNC_EN = 0
3771 12:14:55.862508 ALL_SLAVE_EN = 1
3772 12:14:55.865569 NEW_RANK_MODE = 1
3773 12:14:55.869087 DLL_IDLE_MODE = 1
3774 12:14:55.869176 LP45_APHY_COMB_EN = 1
3775 12:14:55.872265 TX_ODT_DIS = 1
3776 12:14:55.875893 NEW_8X_MODE = 1
3777 12:14:55.878985 ===================================
3778 12:14:55.882011 ===================================
3779 12:14:55.885671 data_rate = 1200
3780 12:14:55.888755 CKR = 1
3781 12:14:55.892006 DQ_P2S_RATIO = 8
3782 12:14:55.895305 ===================================
3783 12:14:55.895452 CA_P2S_RATIO = 8
3784 12:14:55.898947 DQ_CA_OPEN = 0
3785 12:14:55.902028 DQ_SEMI_OPEN = 0
3786 12:14:55.905661 CA_SEMI_OPEN = 0
3787 12:14:55.908416 CA_FULL_RATE = 0
3788 12:14:55.911831 DQ_CKDIV4_EN = 1
3789 12:14:55.911915 CA_CKDIV4_EN = 1
3790 12:14:55.915212 CA_PREDIV_EN = 0
3791 12:14:55.918267 PH8_DLY = 0
3792 12:14:55.921527 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3793 12:14:55.925232 DQ_AAMCK_DIV = 4
3794 12:14:55.928286 CA_AAMCK_DIV = 4
3795 12:14:55.928370 CA_ADMCK_DIV = 4
3796 12:14:55.931402 DQ_TRACK_CA_EN = 0
3797 12:14:55.935255 CA_PICK = 600
3798 12:14:55.937891 CA_MCKIO = 600
3799 12:14:55.941637 MCKIO_SEMI = 0
3800 12:14:55.944860 PLL_FREQ = 2288
3801 12:14:55.947918 DQ_UI_PI_RATIO = 32
3802 12:14:55.951247 CA_UI_PI_RATIO = 0
3803 12:14:55.951331 ===================================
3804 12:14:55.954331 ===================================
3805 12:14:55.958100 memory_type:LPDDR4
3806 12:14:55.961226 GP_NUM : 10
3807 12:14:55.961310 SRAM_EN : 1
3808 12:14:55.964327 MD32_EN : 0
3809 12:14:55.967476 ===================================
3810 12:14:55.971239 [ANA_INIT] >>>>>>>>>>>>>>
3811 12:14:55.974151 <<<<<< [CONFIGURE PHASE]: ANA_TX
3812 12:14:55.977799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3813 12:14:55.980842 ===================================
3814 12:14:55.983950 data_rate = 1200,PCW = 0X5800
3815 12:14:55.987658 ===================================
3816 12:14:55.990652 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3817 12:14:55.993906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3818 12:14:56.000678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3819 12:14:56.003695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3820 12:14:56.007027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3821 12:14:56.010645 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3822 12:14:56.013736 [ANA_INIT] flow start
3823 12:14:56.017280 [ANA_INIT] PLL >>>>>>>>
3824 12:14:56.017402 [ANA_INIT] PLL <<<<<<<<
3825 12:14:56.020143 [ANA_INIT] MIDPI >>>>>>>>
3826 12:14:56.024039 [ANA_INIT] MIDPI <<<<<<<<
3827 12:14:56.027110 [ANA_INIT] DLL >>>>>>>>
3828 12:14:56.027193 [ANA_INIT] flow end
3829 12:14:56.030264 ============ LP4 DIFF to SE enter ============
3830 12:14:56.036636 ============ LP4 DIFF to SE exit ============
3831 12:14:56.036720 [ANA_INIT] <<<<<<<<<<<<<
3832 12:14:56.039829 [Flow] Enable top DCM control >>>>>
3833 12:14:56.043710 [Flow] Enable top DCM control <<<<<
3834 12:14:56.047045 Enable DLL master slave shuffle
3835 12:14:56.053339 ==============================================================
3836 12:14:56.056559 Gating Mode config
3837 12:14:56.059609 ==============================================================
3838 12:14:56.063383 Config description:
3839 12:14:56.073189 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3840 12:14:56.079366 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3841 12:14:56.083021 SELPH_MODE 0: By rank 1: By Phase
3842 12:14:56.089186 ==============================================================
3843 12:14:56.092864 GAT_TRACK_EN = 1
3844 12:14:56.095791 RX_GATING_MODE = 2
3845 12:14:56.099306 RX_GATING_TRACK_MODE = 2
3846 12:14:56.102458 SELPH_MODE = 1
3847 12:14:56.102543 PICG_EARLY_EN = 1
3848 12:14:56.105680 VALID_LAT_VALUE = 1
3849 12:14:56.112178 ==============================================================
3850 12:14:56.115759 Enter into Gating configuration >>>>
3851 12:14:56.119270 Exit from Gating configuration <<<<
3852 12:14:56.122301 Enter into DVFS_PRE_config >>>>>
3853 12:14:56.132217 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3854 12:14:56.135235 Exit from DVFS_PRE_config <<<<<
3855 12:14:56.138959 Enter into PICG configuration >>>>
3856 12:14:56.142033 Exit from PICG configuration <<<<
3857 12:14:56.145132 [RX_INPUT] configuration >>>>>
3858 12:14:56.148927 [RX_INPUT] configuration <<<<<
3859 12:14:56.154925 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3860 12:14:56.158549 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3861 12:14:56.164773 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3862 12:14:56.171575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3863 12:14:56.178236 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3864 12:14:56.184653 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3865 12:14:56.187714 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3866 12:14:56.191314 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3867 12:14:56.194478 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3868 12:14:56.201077 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3869 12:14:56.204623 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3870 12:14:56.207923 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3871 12:14:56.210979 ===================================
3872 12:14:56.213985 LPDDR4 DRAM CONFIGURATION
3873 12:14:56.217238 ===================================
3874 12:14:56.220908 EX_ROW_EN[0] = 0x0
3875 12:14:56.221033 EX_ROW_EN[1] = 0x0
3876 12:14:56.224058 LP4Y_EN = 0x0
3877 12:14:56.224173 WORK_FSP = 0x0
3878 12:14:56.227413 WL = 0x2
3879 12:14:56.227494 RL = 0x2
3880 12:14:56.230472 BL = 0x2
3881 12:14:56.230570 RPST = 0x0
3882 12:14:56.233862 RD_PRE = 0x0
3883 12:14:56.233948 WR_PRE = 0x1
3884 12:14:56.237885 WR_PST = 0x0
3885 12:14:56.237963 DBI_WR = 0x0
3886 12:14:56.240354 DBI_RD = 0x0
3887 12:14:56.240454 OTF = 0x1
3888 12:14:56.244015 ===================================
3889 12:14:56.250381 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3890 12:14:56.253676 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3891 12:14:56.256763 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3892 12:14:56.260433 ===================================
3893 12:14:56.263439 LPDDR4 DRAM CONFIGURATION
3894 12:14:56.266675 ===================================
3895 12:14:56.270418 EX_ROW_EN[0] = 0x10
3896 12:14:56.270529 EX_ROW_EN[1] = 0x0
3897 12:14:56.273474 LP4Y_EN = 0x0
3898 12:14:56.273574 WORK_FSP = 0x0
3899 12:14:56.276438 WL = 0x2
3900 12:14:56.276539 RL = 0x2
3901 12:14:56.279701 BL = 0x2
3902 12:14:56.279784 RPST = 0x0
3903 12:14:56.283313 RD_PRE = 0x0
3904 12:14:56.283398 WR_PRE = 0x1
3905 12:14:56.286682 WR_PST = 0x0
3906 12:14:56.290152 DBI_WR = 0x0
3907 12:14:56.290240 DBI_RD = 0x0
3908 12:14:56.293078 OTF = 0x1
3909 12:14:56.296153 ===================================
3910 12:14:56.299516 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3911 12:14:56.304795 nWR fixed to 30
3912 12:14:56.308458 [ModeRegInit_LP4] CH0 RK0
3913 12:14:56.308592 [ModeRegInit_LP4] CH0 RK1
3914 12:14:56.311714 [ModeRegInit_LP4] CH1 RK0
3915 12:14:56.314691 [ModeRegInit_LP4] CH1 RK1
3916 12:14:56.314822 match AC timing 17
3917 12:14:56.321252 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3918 12:14:56.324908 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3919 12:14:56.328149 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3920 12:14:56.334723 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3921 12:14:56.337607 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3922 12:14:56.337740 ==
3923 12:14:56.341174 Dram Type= 6, Freq= 0, CH_0, rank 0
3924 12:14:56.344249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3925 12:14:56.344361 ==
3926 12:14:56.350753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3927 12:14:56.357800 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3928 12:14:56.361033 [CA 0] Center 37 (7~67) winsize 61
3929 12:14:56.364107 [CA 1] Center 37 (7~67) winsize 61
3930 12:14:56.367678 [CA 2] Center 35 (5~65) winsize 61
3931 12:14:56.370744 [CA 3] Center 35 (5~65) winsize 61
3932 12:14:56.373962 [CA 4] Center 34 (4~65) winsize 62
3933 12:14:56.377572 [CA 5] Center 34 (4~64) winsize 61
3934 12:14:56.377745
3935 12:14:56.380819 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3936 12:14:56.380949
3937 12:14:56.383776 [CATrainingPosCal] consider 1 rank data
3938 12:14:56.387359 u2DelayCellTimex100 = 270/100 ps
3939 12:14:56.390551 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3940 12:14:56.394045 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3941 12:14:56.397118 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3942 12:14:56.403913 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3943 12:14:56.407150 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3944 12:14:56.410216 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3945 12:14:56.410313
3946 12:14:56.413534 CA PerBit enable=1, Macro0, CA PI delay=34
3947 12:14:56.413621
3948 12:14:56.417108 [CBTSetCACLKResult] CA Dly = 34
3949 12:14:56.417215 CS Dly: 5 (0~36)
3950 12:14:56.417281 ==
3951 12:14:56.420226 Dram Type= 6, Freq= 0, CH_0, rank 1
3952 12:14:56.426600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 12:14:56.426724 ==
3954 12:14:56.429859 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3955 12:14:56.436648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3956 12:14:56.440288 [CA 0] Center 37 (7~67) winsize 61
3957 12:14:56.443312 [CA 1] Center 36 (6~67) winsize 62
3958 12:14:56.446904 [CA 2] Center 35 (5~65) winsize 61
3959 12:14:56.450109 [CA 3] Center 35 (5~65) winsize 61
3960 12:14:56.453114 [CA 4] Center 34 (3~65) winsize 63
3961 12:14:56.456865 [CA 5] Center 34 (4~64) winsize 61
3962 12:14:56.456984
3963 12:14:56.459706 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3964 12:14:56.459786
3965 12:14:56.463259 [CATrainingPosCal] consider 2 rank data
3966 12:14:56.466344 u2DelayCellTimex100 = 270/100 ps
3967 12:14:56.469925 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3968 12:14:56.476042 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3969 12:14:56.479839 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3970 12:14:56.483074 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3971 12:14:56.486622 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3972 12:14:56.489727 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3973 12:14:56.489814
3974 12:14:56.492788 CA PerBit enable=1, Macro0, CA PI delay=34
3975 12:14:56.492863
3976 12:14:56.496456 [CBTSetCACLKResult] CA Dly = 34
3977 12:14:56.499208 CS Dly: 5 (0~37)
3978 12:14:56.499283
3979 12:14:56.502819 ----->DramcWriteLeveling(PI) begin...
3980 12:14:56.502934 ==
3981 12:14:56.506055 Dram Type= 6, Freq= 0, CH_0, rank 0
3982 12:14:56.509094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 12:14:56.509170 ==
3984 12:14:56.512258 Write leveling (Byte 0): 31 => 31
3985 12:14:56.515702 Write leveling (Byte 1): 31 => 31
3986 12:14:56.518773 DramcWriteLeveling(PI) end<-----
3987 12:14:56.518874
3988 12:14:56.518938 ==
3989 12:14:56.522487 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 12:14:56.525588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 12:14:56.525670 ==
3992 12:14:56.528863 [Gating] SW mode calibration
3993 12:14:56.535726 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3994 12:14:56.541865 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3995 12:14:56.545565 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 12:14:56.551718 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 12:14:56.555493 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 12:14:56.558580 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 1)
3999 12:14:56.565276 0 9 16 | B1->B0 | 3333 2525 | 0 0 | (0 0) (0 0)
4000 12:14:56.568827 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 12:14:56.571836 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 12:14:56.578622 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 12:14:56.581715 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 12:14:56.584871 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 12:14:56.591855 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 12:14:56.594945 0 10 12 | B1->B0 | 2626 2d2d | 0 1 | (0 0) (0 0)
4007 12:14:56.598088 0 10 16 | B1->B0 | 3232 3939 | 0 0 | (0 0) (0 0)
4008 12:14:56.604788 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4009 12:14:56.608064 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 12:14:56.611174 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 12:14:56.617496 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 12:14:56.621206 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 12:14:56.624371 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 12:14:56.630617 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 12:14:56.634140 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4016 12:14:56.637182 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:14:56.643695 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 12:14:56.646895 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 12:14:56.650692 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 12:14:56.656731 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 12:14:56.659979 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 12:14:56.663704 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 12:14:56.670085 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 12:14:56.673489 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 12:14:56.676578 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 12:14:56.683155 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 12:14:56.686735 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 12:14:56.689855 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 12:14:56.696278 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 12:14:56.699337 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 12:14:56.703274 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4032 12:14:56.709901 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 12:14:56.712844 Total UI for P1: 0, mck2ui 16
4034 12:14:56.715913 best dqsien dly found for B0: ( 0, 13, 16)
4035 12:14:56.715996 Total UI for P1: 0, mck2ui 16
4036 12:14:56.722748 best dqsien dly found for B1: ( 0, 13, 18)
4037 12:14:56.725881 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4038 12:14:56.729584 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4039 12:14:56.729666
4040 12:14:56.732733 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4041 12:14:56.735684 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4042 12:14:56.739241 [Gating] SW calibration Done
4043 12:14:56.739323 ==
4044 12:14:56.742721 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 12:14:56.745660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 12:14:56.745743 ==
4047 12:14:56.749098 RX Vref Scan: 0
4048 12:14:56.749180
4049 12:14:56.752276 RX Vref 0 -> 0, step: 1
4050 12:14:56.752358
4051 12:14:56.752423 RX Delay -230 -> 252, step: 16
4052 12:14:56.759314 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4053 12:14:56.762587 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4054 12:14:56.765629 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4055 12:14:56.768784 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4056 12:14:56.775506 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4057 12:14:56.779077 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4058 12:14:56.782042 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4059 12:14:56.785484 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4060 12:14:56.792077 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4061 12:14:56.795218 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4062 12:14:56.798803 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4063 12:14:56.801845 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4064 12:14:56.808910 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4065 12:14:56.811836 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4066 12:14:56.815120 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4067 12:14:56.818780 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4068 12:14:56.818902 ==
4069 12:14:56.821956 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 12:14:56.828121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 12:14:56.828204 ==
4072 12:14:56.828269 DQS Delay:
4073 12:14:56.831866 DQS0 = 0, DQS1 = 0
4074 12:14:56.831948 DQM Delay:
4075 12:14:56.832014 DQM0 = 38, DQM1 = 29
4076 12:14:56.834990 DQ Delay:
4077 12:14:56.838298 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4078 12:14:56.841391 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4079 12:14:56.844932 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4080 12:14:56.847837 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4081 12:14:56.847924
4082 12:14:56.847989
4083 12:14:56.848048 ==
4084 12:14:56.851232 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 12:14:56.854685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 12:14:56.854768 ==
4087 12:14:56.854842
4088 12:14:56.854934
4089 12:14:56.858084 TX Vref Scan disable
4090 12:14:56.861488 == TX Byte 0 ==
4091 12:14:56.864612 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4092 12:14:56.867828 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4093 12:14:56.870979 == TX Byte 1 ==
4094 12:14:56.874188 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4095 12:14:56.877791 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4096 12:14:56.877884 ==
4097 12:14:56.880747 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 12:14:56.884445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 12:14:56.887759 ==
4100 12:14:56.887841
4101 12:14:56.887921
4102 12:14:56.887986 TX Vref Scan disable
4103 12:14:56.891291 == TX Byte 0 ==
4104 12:14:56.894818 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4105 12:14:56.901299 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4106 12:14:56.901384 == TX Byte 1 ==
4107 12:14:56.904920 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4108 12:14:56.911438 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4109 12:14:56.911521
4110 12:14:56.911586 [DATLAT]
4111 12:14:56.911647 Freq=600, CH0 RK0
4112 12:14:56.911707
4113 12:14:56.914598 DATLAT Default: 0x9
4114 12:14:56.917549 0, 0xFFFF, sum = 0
4115 12:14:56.917633 1, 0xFFFF, sum = 0
4116 12:14:56.921030 2, 0xFFFF, sum = 0
4117 12:14:56.921118 3, 0xFFFF, sum = 0
4118 12:14:56.924704 4, 0xFFFF, sum = 0
4119 12:14:56.924788 5, 0xFFFF, sum = 0
4120 12:14:56.927890 6, 0xFFFF, sum = 0
4121 12:14:56.927974 7, 0xFFFF, sum = 0
4122 12:14:56.931205 8, 0x0, sum = 1
4123 12:14:56.931288 9, 0x0, sum = 2
4124 12:14:56.934095 10, 0x0, sum = 3
4125 12:14:56.934179 11, 0x0, sum = 4
4126 12:14:56.934244 best_step = 9
4127 12:14:56.934305
4128 12:14:56.938131 ==
4129 12:14:56.941250 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 12:14:56.944476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 12:14:56.944559 ==
4132 12:14:56.944625 RX Vref Scan: 1
4133 12:14:56.944686
4134 12:14:56.947549 RX Vref 0 -> 0, step: 1
4135 12:14:56.947631
4136 12:14:56.950610 RX Delay -195 -> 252, step: 8
4137 12:14:56.950692
4138 12:14:56.954262 Set Vref, RX VrefLevel [Byte0]: 62
4139 12:14:56.957693 [Byte1]: 53
4140 12:14:56.957775
4141 12:14:56.960716 Final RX Vref Byte 0 = 62 to rank0
4142 12:14:56.964328 Final RX Vref Byte 1 = 53 to rank0
4143 12:14:56.967360 Final RX Vref Byte 0 = 62 to rank1
4144 12:14:56.970871 Final RX Vref Byte 1 = 53 to rank1==
4145 12:14:56.973985 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 12:14:56.977037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 12:14:56.980277 ==
4148 12:14:56.980359 DQS Delay:
4149 12:14:56.980424 DQS0 = 0, DQS1 = 0
4150 12:14:56.983998 DQM Delay:
4151 12:14:56.984081 DQM0 = 35, DQM1 = 28
4152 12:14:56.986841 DQ Delay:
4153 12:14:56.990098 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4154 12:14:56.993975 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4155 12:14:56.994057 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4156 12:14:56.999933 DQ12 =32, DQ13 =36, DQ14 =40, DQ15 =36
4157 12:14:57.000040
4158 12:14:57.000132
4159 12:14:57.006793 [DQSOSCAuto] RK0, (LSB)MR18= 0x4241, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4160 12:14:57.009834 CH0 RK0: MR19=808, MR18=4241
4161 12:14:57.016755 CH0_RK0: MR19=0x808, MR18=0x4241, DQSOSC=397, MR23=63, INC=166, DEC=110
4162 12:14:57.016838
4163 12:14:57.019811 ----->DramcWriteLeveling(PI) begin...
4164 12:14:57.019894 ==
4165 12:14:57.023297 Dram Type= 6, Freq= 0, CH_0, rank 1
4166 12:14:57.026436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 12:14:57.026519 ==
4168 12:14:57.029994 Write leveling (Byte 0): 35 => 35
4169 12:14:57.033167 Write leveling (Byte 1): 31 => 31
4170 12:14:57.036804 DramcWriteLeveling(PI) end<-----
4171 12:14:57.036887
4172 12:14:57.036951 ==
4173 12:14:57.039777 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 12:14:57.042832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 12:14:57.042942 ==
4176 12:14:57.046636 [Gating] SW mode calibration
4177 12:14:57.052968 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4178 12:14:57.059787 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4179 12:14:57.062859 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 12:14:57.069368 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 12:14:57.072972 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 12:14:57.075969 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4183 12:14:57.082760 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4184 12:14:57.086003 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 12:14:57.089085 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 12:14:57.095751 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 12:14:57.099376 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 12:14:57.102538 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 12:14:57.108929 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4190 12:14:57.112182 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4191 12:14:57.115852 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
4192 12:14:57.122174 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 12:14:57.125803 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 12:14:57.128939 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 12:14:57.135157 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 12:14:57.138319 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 12:14:57.142127 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 12:14:57.148267 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4199 12:14:57.151971 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 12:14:57.155034 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 12:14:57.161802 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 12:14:57.165015 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 12:14:57.168243 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 12:14:57.174693 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 12:14:57.178219 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 12:14:57.181359 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 12:14:57.187824 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 12:14:57.191482 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 12:14:57.194651 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 12:14:57.200881 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 12:14:57.204366 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 12:14:57.207399 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 12:14:57.214097 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 12:14:57.217788 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4215 12:14:57.220819 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 12:14:57.223915 Total UI for P1: 0, mck2ui 16
4217 12:14:57.227456 best dqsien dly found for B0: ( 0, 13, 12)
4218 12:14:57.231144 Total UI for P1: 0, mck2ui 16
4219 12:14:57.234211 best dqsien dly found for B1: ( 0, 13, 14)
4220 12:14:57.237350 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4221 12:14:57.240910 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4222 12:14:57.244128
4223 12:14:57.247276 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4224 12:14:57.251009 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4225 12:14:57.254030 [Gating] SW calibration Done
4226 12:14:57.254111 ==
4227 12:14:57.257137 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 12:14:57.260812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 12:14:57.260896 ==
4230 12:14:57.260963 RX Vref Scan: 0
4231 12:14:57.263813
4232 12:14:57.263882 RX Vref 0 -> 0, step: 1
4233 12:14:57.263941
4234 12:14:57.266818 RX Delay -230 -> 252, step: 16
4235 12:14:57.270658 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4236 12:14:57.276950 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4237 12:14:57.280435 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4238 12:14:57.283952 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4239 12:14:57.286750 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4240 12:14:57.290439 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4241 12:14:57.297115 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4242 12:14:57.300312 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4243 12:14:57.303347 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4244 12:14:57.306803 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4245 12:14:57.313442 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4246 12:14:57.316361 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4247 12:14:57.319971 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4248 12:14:57.323538 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4249 12:14:57.329606 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4250 12:14:57.333401 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4251 12:14:57.333475 ==
4252 12:14:57.336339 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 12:14:57.340008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 12:14:57.340104 ==
4255 12:14:57.342833 DQS Delay:
4256 12:14:57.342923 DQS0 = 0, DQS1 = 0
4257 12:14:57.346506 DQM Delay:
4258 12:14:57.346579 DQM0 = 36, DQM1 = 30
4259 12:14:57.346639 DQ Delay:
4260 12:14:57.349556 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4261 12:14:57.352622 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4262 12:14:57.355814 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4263 12:14:57.359450 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4264 12:14:57.359526
4265 12:14:57.359598
4266 12:14:57.362750 ==
4267 12:14:57.362842 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 12:14:57.369482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 12:14:57.369558 ==
4270 12:14:57.369621
4271 12:14:57.369687
4272 12:14:57.372587 TX Vref Scan disable
4273 12:14:57.372690 == TX Byte 0 ==
4274 12:14:57.378952 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4275 12:14:57.382027 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4276 12:14:57.382139 == TX Byte 1 ==
4277 12:14:57.388646 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4278 12:14:57.392126 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4279 12:14:57.392204 ==
4280 12:14:57.395769 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 12:14:57.398600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 12:14:57.398679 ==
4283 12:14:57.398742
4284 12:14:57.398802
4285 12:14:57.401727 TX Vref Scan disable
4286 12:14:57.404964 == TX Byte 0 ==
4287 12:14:57.408766 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4288 12:14:57.414950 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4289 12:14:57.415062 == TX Byte 1 ==
4290 12:14:57.418445 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4291 12:14:57.425045 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4292 12:14:57.425143
4293 12:14:57.425290 [DATLAT]
4294 12:14:57.425384 Freq=600, CH0 RK1
4295 12:14:57.425485
4296 12:14:57.428007 DATLAT Default: 0x9
4297 12:14:57.431936 0, 0xFFFF, sum = 0
4298 12:14:57.432031 1, 0xFFFF, sum = 0
4299 12:14:57.434733 2, 0xFFFF, sum = 0
4300 12:14:57.434811 3, 0xFFFF, sum = 0
4301 12:14:57.437839 4, 0xFFFF, sum = 0
4302 12:14:57.437948 5, 0xFFFF, sum = 0
4303 12:14:57.441279 6, 0xFFFF, sum = 0
4304 12:14:57.441357 7, 0xFFFF, sum = 0
4305 12:14:57.444851 8, 0x0, sum = 1
4306 12:14:57.444933 9, 0x0, sum = 2
4307 12:14:57.448275 10, 0x0, sum = 3
4308 12:14:57.448449 11, 0x0, sum = 4
4309 12:14:57.448558 best_step = 9
4310 12:14:57.448652
4311 12:14:57.451462 ==
4312 12:14:57.454555 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 12:14:57.457930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 12:14:57.458007 ==
4315 12:14:57.458079 RX Vref Scan: 0
4316 12:14:57.458138
4317 12:14:57.460837 RX Vref 0 -> 0, step: 1
4318 12:14:57.460936
4319 12:14:57.464021 RX Delay -195 -> 252, step: 8
4320 12:14:57.470724 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4321 12:14:57.474484 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4322 12:14:57.477829 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4323 12:14:57.480900 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4324 12:14:57.487147 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4325 12:14:57.490826 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4326 12:14:57.493810 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4327 12:14:57.497567 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4328 12:14:57.500675 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4329 12:14:57.507176 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4330 12:14:57.510212 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4331 12:14:57.513677 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4332 12:14:57.517038 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4333 12:14:57.523759 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4334 12:14:57.526716 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4335 12:14:57.530382 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4336 12:14:57.530506 ==
4337 12:14:57.533439 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 12:14:57.539847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 12:14:57.539926 ==
4340 12:14:57.539997 DQS Delay:
4341 12:14:57.540057 DQS0 = 0, DQS1 = 0
4342 12:14:57.543649 DQM Delay:
4343 12:14:57.543761 DQM0 = 34, DQM1 = 28
4344 12:14:57.546745 DQ Delay:
4345 12:14:57.549834 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4346 12:14:57.553085 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4347 12:14:57.556266 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4348 12:14:57.560134 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4349 12:14:57.560219
4350 12:14:57.560284
4351 12:14:57.566418 [DQSOSCAuto] RK1, (LSB)MR18= 0x6533, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4352 12:14:57.569321 CH0 RK1: MR19=808, MR18=6533
4353 12:14:57.576259 CH0_RK1: MR19=0x808, MR18=0x6533, DQSOSC=390, MR23=63, INC=172, DEC=114
4354 12:14:57.579394 [RxdqsGatingPostProcess] freq 600
4355 12:14:57.583084 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4356 12:14:57.586261 Pre-setting of DQS Precalculation
4357 12:14:57.592472 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4358 12:14:57.592548 ==
4359 12:14:57.596039 Dram Type= 6, Freq= 0, CH_1, rank 0
4360 12:14:57.598936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 12:14:57.599008 ==
4362 12:14:57.605942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4363 12:14:57.612500 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4364 12:14:57.615473 [CA 0] Center 36 (6~66) winsize 61
4365 12:14:57.619209 [CA 1] Center 36 (6~67) winsize 62
4366 12:14:57.622153 [CA 2] Center 34 (4~65) winsize 62
4367 12:14:57.625797 [CA 3] Center 34 (4~65) winsize 62
4368 12:14:57.629012 [CA 4] Center 34 (4~65) winsize 62
4369 12:14:57.632341 [CA 5] Center 34 (4~65) winsize 62
4370 12:14:57.632413
4371 12:14:57.635366 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4372 12:14:57.635452
4373 12:14:57.639075 [CATrainingPosCal] consider 1 rank data
4374 12:14:57.642156 u2DelayCellTimex100 = 270/100 ps
4375 12:14:57.645118 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4376 12:14:57.648849 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4377 12:14:57.651677 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4378 12:14:57.655268 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4379 12:14:57.658388 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4380 12:14:57.665205 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4381 12:14:57.665334
4382 12:14:57.668550 CA PerBit enable=1, Macro0, CA PI delay=34
4383 12:14:57.668673
4384 12:14:57.671452 [CBTSetCACLKResult] CA Dly = 34
4385 12:14:57.671557 CS Dly: 6 (0~37)
4386 12:14:57.671658 ==
4387 12:14:57.675090 Dram Type= 6, Freq= 0, CH_1, rank 1
4388 12:14:57.678232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 12:14:57.681234 ==
4390 12:14:57.685026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4391 12:14:57.691403 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4392 12:14:57.694630 [CA 0] Center 36 (6~66) winsize 61
4393 12:14:57.697791 [CA 1] Center 36 (6~67) winsize 62
4394 12:14:57.700982 [CA 2] Center 34 (4~65) winsize 62
4395 12:14:57.704861 [CA 3] Center 34 (4~65) winsize 62
4396 12:14:57.707750 [CA 4] Center 34 (4~65) winsize 62
4397 12:14:57.710851 [CA 5] Center 34 (4~65) winsize 62
4398 12:14:57.710942
4399 12:14:57.714030 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4400 12:14:57.714138
4401 12:14:57.717699 [CATrainingPosCal] consider 2 rank data
4402 12:14:57.720706 u2DelayCellTimex100 = 270/100 ps
4403 12:14:57.724502 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4404 12:14:57.727565 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4405 12:14:57.734158 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4406 12:14:57.737962 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4407 12:14:57.740884 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4408 12:14:57.744305 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4409 12:14:57.744398
4410 12:14:57.747312 CA PerBit enable=1, Macro0, CA PI delay=34
4411 12:14:57.747400
4412 12:14:57.750895 [CBTSetCACLKResult] CA Dly = 34
4413 12:14:57.751007 CS Dly: 6 (0~37)
4414 12:14:57.753881
4415 12:14:57.757363 ----->DramcWriteLeveling(PI) begin...
4416 12:14:57.757469 ==
4417 12:14:57.760326 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 12:14:57.764390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 12:14:57.764480 ==
4420 12:14:57.767163 Write leveling (Byte 0): 30 => 30
4421 12:14:57.770222 Write leveling (Byte 1): 31 => 31
4422 12:14:57.773901 DramcWriteLeveling(PI) end<-----
4423 12:14:57.774020
4424 12:14:57.774118 ==
4425 12:14:57.777195 Dram Type= 6, Freq= 0, CH_1, rank 0
4426 12:14:57.780162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 12:14:57.780253 ==
4428 12:14:57.783278 [Gating] SW mode calibration
4429 12:14:57.790005 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4430 12:14:57.796508 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4431 12:14:57.799603 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4432 12:14:57.803336 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 12:14:57.810039 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 12:14:57.813261 0 9 12 | B1->B0 | 3333 3131 | 1 1 | (1 0) (1 1)
4435 12:14:57.816328 0 9 16 | B1->B0 | 2929 2b2b | 1 1 | (1 1) (1 0)
4436 12:14:57.823131 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 12:14:57.826127 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 12:14:57.829668 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 12:14:57.836350 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 12:14:57.839530 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 12:14:57.842675 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 12:14:57.849295 0 10 12 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
4443 12:14:57.852853 0 10 16 | B1->B0 | 3e3e 4141 | 0 0 | (0 0) (0 0)
4444 12:14:57.855821 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 12:14:57.862737 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 12:14:57.865664 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 12:14:57.869236 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 12:14:57.875963 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 12:14:57.879056 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 12:14:57.882206 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4451 12:14:57.889238 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4452 12:14:57.892299 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 12:14:57.895429 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 12:14:57.902334 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 12:14:57.905361 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:14:57.908794 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:14:57.915597 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 12:14:57.918581 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 12:14:57.921609 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 12:14:57.928487 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 12:14:57.931587 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 12:14:57.935218 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 12:14:57.941211 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 12:14:57.944900 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 12:14:57.947964 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 12:14:57.954692 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4467 12:14:57.957763 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 12:14:57.960897 Total UI for P1: 0, mck2ui 16
4469 12:14:57.964623 best dqsien dly found for B0: ( 0, 13, 12)
4470 12:14:57.967757 Total UI for P1: 0, mck2ui 16
4471 12:14:57.970772 best dqsien dly found for B1: ( 0, 13, 14)
4472 12:14:57.974279 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4473 12:14:57.977680 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4474 12:14:57.977776
4475 12:14:57.980660 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4476 12:14:57.987491 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4477 12:14:57.987611 [Gating] SW calibration Done
4478 12:14:57.990421 ==
4479 12:14:57.990507 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 12:14:57.997612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 12:14:57.997701 ==
4482 12:14:57.997767 RX Vref Scan: 0
4483 12:14:57.997829
4484 12:14:58.000844 RX Vref 0 -> 0, step: 1
4485 12:14:58.000924
4486 12:14:58.003904 RX Delay -230 -> 252, step: 16
4487 12:14:58.007152 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4488 12:14:58.010240 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4489 12:14:58.016853 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4490 12:14:58.020634 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4491 12:14:58.023771 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4492 12:14:58.026836 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4493 12:14:58.033865 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4494 12:14:58.036857 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4495 12:14:58.040315 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4496 12:14:58.043262 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4497 12:14:58.047129 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4498 12:14:58.053726 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4499 12:14:58.056887 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4500 12:14:58.059665 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4501 12:14:58.063366 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4502 12:14:58.069720 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4503 12:14:58.069852 ==
4504 12:14:58.073285 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 12:14:58.076386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 12:14:58.076478 ==
4507 12:14:58.076544 DQS Delay:
4508 12:14:58.079483 DQS0 = 0, DQS1 = 0
4509 12:14:58.079567 DQM Delay:
4510 12:14:58.082987 DQM0 = 39, DQM1 = 28
4511 12:14:58.083078 DQ Delay:
4512 12:14:58.086412 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4513 12:14:58.089446 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4514 12:14:58.093194 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4515 12:14:58.096332 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4516 12:14:58.096437
4517 12:14:58.096503
4518 12:14:58.096564 ==
4519 12:14:58.099582 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 12:14:58.106359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 12:14:58.106446 ==
4522 12:14:58.106511
4523 12:14:58.106571
4524 12:14:58.106628 TX Vref Scan disable
4525 12:14:58.109429 == TX Byte 0 ==
4526 12:14:58.112678 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4527 12:14:58.119397 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4528 12:14:58.119480 == TX Byte 1 ==
4529 12:14:58.123255 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4530 12:14:58.129348 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4531 12:14:58.129441 ==
4532 12:14:58.132442 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 12:14:58.136150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 12:14:58.136234 ==
4535 12:14:58.136300
4536 12:14:58.136361
4537 12:14:58.139354 TX Vref Scan disable
4538 12:14:58.142301 == TX Byte 0 ==
4539 12:14:58.145802 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4540 12:14:58.149446 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4541 12:14:58.152485 == TX Byte 1 ==
4542 12:14:58.156095 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4543 12:14:58.159143 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4544 12:14:58.159226
4545 12:14:58.159292 [DATLAT]
4546 12:14:58.162810 Freq=600, CH1 RK0
4547 12:14:58.162903
4548 12:14:58.165739 DATLAT Default: 0x9
4549 12:14:58.165822 0, 0xFFFF, sum = 0
4550 12:14:58.168722 1, 0xFFFF, sum = 0
4551 12:14:58.168807 2, 0xFFFF, sum = 0
4552 12:14:58.172295 3, 0xFFFF, sum = 0
4553 12:14:58.172379 4, 0xFFFF, sum = 0
4554 12:14:58.175791 5, 0xFFFF, sum = 0
4555 12:14:58.175875 6, 0xFFFF, sum = 0
4556 12:14:58.179001 7, 0xFFFF, sum = 0
4557 12:14:58.179085 8, 0x0, sum = 1
4558 12:14:58.182187 9, 0x0, sum = 2
4559 12:14:58.182272 10, 0x0, sum = 3
4560 12:14:58.185199 11, 0x0, sum = 4
4561 12:14:58.185283 best_step = 9
4562 12:14:58.185348
4563 12:14:58.185409 ==
4564 12:14:58.189046 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 12:14:58.191960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 12:14:58.192048 ==
4567 12:14:58.195557 RX Vref Scan: 1
4568 12:14:58.195641
4569 12:14:58.198635 RX Vref 0 -> 0, step: 1
4570 12:14:58.198745
4571 12:14:58.198845 RX Delay -195 -> 252, step: 8
4572 12:14:58.201696
4573 12:14:58.201778 Set Vref, RX VrefLevel [Byte0]: 58
4574 12:14:58.205446 [Byte1]: 49
4575 12:14:58.209882
4576 12:14:58.209955 Final RX Vref Byte 0 = 58 to rank0
4577 12:14:58.213302 Final RX Vref Byte 1 = 49 to rank0
4578 12:14:58.216864 Final RX Vref Byte 0 = 58 to rank1
4579 12:14:58.220009 Final RX Vref Byte 1 = 49 to rank1==
4580 12:14:58.223561 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 12:14:58.229889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 12:14:58.229976 ==
4583 12:14:58.230041 DQS Delay:
4584 12:14:58.233120 DQS0 = 0, DQS1 = 0
4585 12:14:58.233194 DQM Delay:
4586 12:14:58.233256 DQM0 = 41, DQM1 = 30
4587 12:14:58.236559 DQ Delay:
4588 12:14:58.239700 DQ0 =48, DQ1 =40, DQ2 =28, DQ3 =36
4589 12:14:58.242777 DQ4 =36, DQ5 =52, DQ6 =52, DQ7 =36
4590 12:14:58.246119 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4591 12:14:58.249763 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4592 12:14:58.249840
4593 12:14:58.249921
4594 12:14:58.256230 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d2a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
4595 12:14:58.259223 CH1 RK0: MR19=808, MR18=1D2A
4596 12:14:58.265986 CH1_RK0: MR19=0x808, MR18=0x1D2A, DQSOSC=401, MR23=63, INC=163, DEC=108
4597 12:14:58.266110
4598 12:14:58.269006 ----->DramcWriteLeveling(PI) begin...
4599 12:14:58.269083 ==
4600 12:14:58.272628 Dram Type= 6, Freq= 0, CH_1, rank 1
4601 12:14:58.276051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 12:14:58.276125 ==
4603 12:14:58.279382 Write leveling (Byte 0): 31 => 31
4604 12:14:58.282267 Write leveling (Byte 1): 29 => 29
4605 12:14:58.286060 DramcWriteLeveling(PI) end<-----
4606 12:14:58.286134
4607 12:14:58.286203 ==
4608 12:14:58.289009 Dram Type= 6, Freq= 0, CH_1, rank 1
4609 12:14:58.295749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 12:14:58.295839 ==
4611 12:14:58.295909 [Gating] SW mode calibration
4612 12:14:58.305861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4613 12:14:58.308868 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4614 12:14:58.311937 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 12:14:58.318816 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4616 12:14:58.321750 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4617 12:14:58.328288 0 9 12 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (1 0)
4618 12:14:58.331361 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
4619 12:14:58.335260 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 12:14:58.341506 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 12:14:58.344650 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 12:14:58.348472 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 12:14:58.351589 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 12:14:58.358471 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
4625 12:14:58.361563 0 10 12 | B1->B0 | 3333 3a3a | 0 0 | (0 0) (0 0)
4626 12:14:58.364513 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4627 12:14:58.371317 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 12:14:58.374421 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 12:14:58.377838 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 12:14:58.384199 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 12:14:58.387699 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 12:14:58.390798 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4633 12:14:58.397629 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4634 12:14:58.400695 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 12:14:58.407301 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 12:14:58.410518 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 12:14:58.414177 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 12:14:58.420641 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 12:14:58.423826 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 12:14:58.427026 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 12:14:58.433717 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 12:14:58.437403 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 12:14:58.440498 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 12:14:58.446625 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 12:14:58.450477 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 12:14:58.453577 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 12:14:58.460029 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 12:14:58.463582 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 12:14:58.466701 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 12:14:58.469851 Total UI for P1: 0, mck2ui 16
4651 12:14:58.473529 best dqsien dly found for B0: ( 0, 13, 10)
4652 12:14:58.476479 Total UI for P1: 0, mck2ui 16
4653 12:14:58.480178 best dqsien dly found for B1: ( 0, 13, 10)
4654 12:14:58.483578 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4655 12:14:58.486759 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4656 12:14:58.486873
4657 12:14:58.490074 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4658 12:14:58.496451 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4659 12:14:58.496535 [Gating] SW calibration Done
4660 12:14:58.499839 ==
4661 12:14:58.502795 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 12:14:58.506420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 12:14:58.506507 ==
4664 12:14:58.506652 RX Vref Scan: 0
4665 12:14:58.506771
4666 12:14:58.509520 RX Vref 0 -> 0, step: 1
4667 12:14:58.509618
4668 12:14:58.513150 RX Delay -230 -> 252, step: 16
4669 12:14:58.516478 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4670 12:14:58.519601 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4671 12:14:58.526040 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4672 12:14:58.529173 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4673 12:14:58.532859 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4674 12:14:58.535875 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4675 12:14:58.542709 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4676 12:14:58.545850 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4677 12:14:58.549095 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4678 12:14:58.552255 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4679 12:14:58.556039 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4680 12:14:58.562377 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4681 12:14:58.565489 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4682 12:14:58.568717 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4683 12:14:58.575735 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4684 12:14:58.578659 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4685 12:14:58.578740 ==
4686 12:14:58.582195 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 12:14:58.585068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 12:14:58.585151 ==
4689 12:14:58.589057 DQS Delay:
4690 12:14:58.589155 DQS0 = 0, DQS1 = 0
4691 12:14:58.589249 DQM Delay:
4692 12:14:58.592297 DQM0 = 37, DQM1 = 30
4693 12:14:58.592378 DQ Delay:
4694 12:14:58.595226 DQ0 =49, DQ1 =33, DQ2 =17, DQ3 =33
4695 12:14:58.598690 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4696 12:14:58.602246 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4697 12:14:58.605327 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4698 12:14:58.605425
4699 12:14:58.605533
4700 12:14:58.605623 ==
4701 12:14:58.608532 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 12:14:58.615024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 12:14:58.615100 ==
4704 12:14:58.615173
4705 12:14:58.615248
4706 12:14:58.615307 TX Vref Scan disable
4707 12:14:58.618628 == TX Byte 0 ==
4708 12:14:58.621884 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4709 12:14:58.628780 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4710 12:14:58.628866 == TX Byte 1 ==
4711 12:14:58.631866 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4712 12:14:58.638652 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4713 12:14:58.638737 ==
4714 12:14:58.641830 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 12:14:58.644893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 12:14:58.645002 ==
4717 12:14:58.645097
4718 12:14:58.645182
4719 12:14:58.648161 TX Vref Scan disable
4720 12:14:58.651362 == TX Byte 0 ==
4721 12:14:58.655159 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4722 12:14:58.658055 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4723 12:14:58.661376 == TX Byte 1 ==
4724 12:14:58.664916 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4725 12:14:58.667983 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4726 12:14:58.668084
4727 12:14:58.671080 [DATLAT]
4728 12:14:58.671203 Freq=600, CH1 RK1
4729 12:14:58.671301
4730 12:14:58.674988 DATLAT Default: 0x9
4731 12:14:58.675090 0, 0xFFFF, sum = 0
4732 12:14:58.678084 1, 0xFFFF, sum = 0
4733 12:14:58.678183 2, 0xFFFF, sum = 0
4734 12:14:58.681017 3, 0xFFFF, sum = 0
4735 12:14:58.681117 4, 0xFFFF, sum = 0
4736 12:14:58.684788 5, 0xFFFF, sum = 0
4737 12:14:58.684863 6, 0xFFFF, sum = 0
4738 12:14:58.687733 7, 0xFFFF, sum = 0
4739 12:14:58.687804 8, 0x0, sum = 1
4740 12:14:58.691315 9, 0x0, sum = 2
4741 12:14:58.691389 10, 0x0, sum = 3
4742 12:14:58.694392 11, 0x0, sum = 4
4743 12:14:58.694461 best_step = 9
4744 12:14:58.694519
4745 12:14:58.694576 ==
4746 12:14:58.697358 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 12:14:58.700939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 12:14:58.704271 ==
4749 12:14:58.704352 RX Vref Scan: 0
4750 12:14:58.704415
4751 12:14:58.707563 RX Vref 0 -> 0, step: 1
4752 12:14:58.707635
4753 12:14:58.710490 RX Delay -195 -> 252, step: 8
4754 12:14:58.714097 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4755 12:14:58.717164 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4756 12:14:58.723926 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4757 12:14:58.726912 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4758 12:14:58.730510 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4759 12:14:58.733639 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4760 12:14:58.740484 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4761 12:14:58.743464 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4762 12:14:58.746797 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4763 12:14:58.749952 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4764 12:14:58.756921 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4765 12:14:58.759823 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4766 12:14:58.763110 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4767 12:14:58.766764 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4768 12:14:58.773163 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4769 12:14:58.776323 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4770 12:14:58.776432 ==
4771 12:14:58.779997 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 12:14:58.783237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 12:14:58.783320 ==
4774 12:14:58.786118 DQS Delay:
4775 12:14:58.786199 DQS0 = 0, DQS1 = 0
4776 12:14:58.789901 DQM Delay:
4777 12:14:58.789982 DQM0 = 37, DQM1 = 31
4778 12:14:58.790046 DQ Delay:
4779 12:14:58.793009 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =32
4780 12:14:58.796091 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4781 12:14:58.799574 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4782 12:14:58.802633 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =40
4783 12:14:58.802749
4784 12:14:58.802863
4785 12:14:58.812923 [DQSOSCAuto] RK1, (LSB)MR18= 0x3453, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
4786 12:14:58.816236 CH1 RK1: MR19=808, MR18=3453
4787 12:14:58.822557 CH1_RK1: MR19=0x808, MR18=0x3453, DQSOSC=394, MR23=63, INC=168, DEC=112
4788 12:14:58.822687 [RxdqsGatingPostProcess] freq 600
4789 12:14:58.829280 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4790 12:14:58.832354 Pre-setting of DQS Precalculation
4791 12:14:58.835814 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4792 12:14:58.845540 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4793 12:14:58.852092 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4794 12:14:58.852220
4795 12:14:58.852340
4796 12:14:58.855869 [Calibration Summary] 1200 Mbps
4797 12:14:58.855949 CH 0, Rank 0
4798 12:14:58.859016 SW Impedance : PASS
4799 12:14:58.859152 DUTY Scan : NO K
4800 12:14:58.862090 ZQ Calibration : PASS
4801 12:14:58.865955 Jitter Meter : NO K
4802 12:14:58.866099 CBT Training : PASS
4803 12:14:58.868988 Write leveling : PASS
4804 12:14:58.872031 RX DQS gating : PASS
4805 12:14:58.872127 RX DQ/DQS(RDDQC) : PASS
4806 12:14:58.875241 TX DQ/DQS : PASS
4807 12:14:58.878967 RX DATLAT : PASS
4808 12:14:58.879046 RX DQ/DQS(Engine): PASS
4809 12:14:58.882196 TX OE : NO K
4810 12:14:58.882279 All Pass.
4811 12:14:58.882343
4812 12:14:58.885192 CH 0, Rank 1
4813 12:14:58.885295 SW Impedance : PASS
4814 12:14:58.888859 DUTY Scan : NO K
4815 12:14:58.892152 ZQ Calibration : PASS
4816 12:14:58.892228 Jitter Meter : NO K
4817 12:14:58.895294 CBT Training : PASS
4818 12:14:58.898374 Write leveling : PASS
4819 12:14:58.898448 RX DQS gating : PASS
4820 12:14:58.902002 RX DQ/DQS(RDDQC) : PASS
4821 12:14:58.905127 TX DQ/DQS : PASS
4822 12:14:58.905210 RX DATLAT : PASS
4823 12:14:58.908207 RX DQ/DQS(Engine): PASS
4824 12:14:58.911661 TX OE : NO K
4825 12:14:58.911793 All Pass.
4826 12:14:58.911890
4827 12:14:58.911966 CH 1, Rank 0
4828 12:14:58.914817 SW Impedance : PASS
4829 12:14:58.918340 DUTY Scan : NO K
4830 12:14:58.918423 ZQ Calibration : PASS
4831 12:14:58.921587 Jitter Meter : NO K
4832 12:14:58.921687 CBT Training : PASS
4833 12:14:58.924815 Write leveling : PASS
4834 12:14:58.927942 RX DQS gating : PASS
4835 12:14:58.928040 RX DQ/DQS(RDDQC) : PASS
4836 12:14:58.931624 TX DQ/DQS : PASS
4837 12:14:58.934759 RX DATLAT : PASS
4838 12:14:58.934849 RX DQ/DQS(Engine): PASS
4839 12:14:58.937921 TX OE : NO K
4840 12:14:58.938022 All Pass.
4841 12:14:58.938122
4842 12:14:58.941544 CH 1, Rank 1
4843 12:14:58.941625 SW Impedance : PASS
4844 12:14:58.944394 DUTY Scan : NO K
4845 12:14:58.947928 ZQ Calibration : PASS
4846 12:14:58.948010 Jitter Meter : NO K
4847 12:14:58.950922 CBT Training : PASS
4848 12:14:58.954700 Write leveling : PASS
4849 12:14:58.954814 RX DQS gating : PASS
4850 12:14:58.958005 RX DQ/DQS(RDDQC) : PASS
4851 12:14:58.961092 TX DQ/DQS : PASS
4852 12:14:58.961197 RX DATLAT : PASS
4853 12:14:58.964496 RX DQ/DQS(Engine): PASS
4854 12:14:58.967449 TX OE : NO K
4855 12:14:58.967550 All Pass.
4856 12:14:58.967629
4857 12:14:58.971214 DramC Write-DBI off
4858 12:14:58.971300 PER_BANK_REFRESH: Hybrid Mode
4859 12:14:58.974361 TX_TRACKING: ON
4860 12:14:58.980678 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4861 12:14:58.987542 [FAST_K] Save calibration result to emmc
4862 12:14:58.990524 dramc_set_vcore_voltage set vcore to 662500
4863 12:14:58.990617 Read voltage for 933, 3
4864 12:14:58.994204 Vio18 = 0
4865 12:14:58.994293 Vcore = 662500
4866 12:14:58.994360 Vdram = 0
4867 12:14:58.997217 Vddq = 0
4868 12:14:58.997301 Vmddr = 0
4869 12:14:59.000313 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4870 12:14:59.007222 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4871 12:14:59.010244 MEM_TYPE=3, freq_sel=17
4872 12:14:59.013436 sv_algorithm_assistance_LP4_1600
4873 12:14:59.016935 ============ PULL DRAM RESETB DOWN ============
4874 12:14:59.020546 ========== PULL DRAM RESETB DOWN end =========
4875 12:14:59.026610 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4876 12:14:59.030551 ===================================
4877 12:14:59.030642 LPDDR4 DRAM CONFIGURATION
4878 12:14:59.033378 ===================================
4879 12:14:59.036688 EX_ROW_EN[0] = 0x0
4880 12:14:59.039756 EX_ROW_EN[1] = 0x0
4881 12:14:59.039837 LP4Y_EN = 0x0
4882 12:14:59.043377 WORK_FSP = 0x0
4883 12:14:59.043460 WL = 0x3
4884 12:14:59.046551 RL = 0x3
4885 12:14:59.046636 BL = 0x2
4886 12:14:59.050072 RPST = 0x0
4887 12:14:59.050155 RD_PRE = 0x0
4888 12:14:59.053063 WR_PRE = 0x1
4889 12:14:59.053145 WR_PST = 0x0
4890 12:14:59.056403 DBI_WR = 0x0
4891 12:14:59.056490 DBI_RD = 0x0
4892 12:14:59.059535 OTF = 0x1
4893 12:14:59.062610 ===================================
4894 12:14:59.066294 ===================================
4895 12:14:59.066381 ANA top config
4896 12:14:59.069334 ===================================
4897 12:14:59.073102 DLL_ASYNC_EN = 0
4898 12:14:59.076072 ALL_SLAVE_EN = 1
4899 12:14:59.079165 NEW_RANK_MODE = 1
4900 12:14:59.079252 DLL_IDLE_MODE = 1
4901 12:14:59.083027 LP45_APHY_COMB_EN = 1
4902 12:14:59.086029 TX_ODT_DIS = 1
4903 12:14:59.089073 NEW_8X_MODE = 1
4904 12:14:59.092816 ===================================
4905 12:14:59.095950 ===================================
4906 12:14:59.098960 data_rate = 1866
4907 12:14:59.099045 CKR = 1
4908 12:14:59.102383 DQ_P2S_RATIO = 8
4909 12:14:59.106005 ===================================
4910 12:14:59.109158 CA_P2S_RATIO = 8
4911 12:14:59.112219 DQ_CA_OPEN = 0
4912 12:14:59.115677 DQ_SEMI_OPEN = 0
4913 12:14:59.118641 CA_SEMI_OPEN = 0
4914 12:14:59.122441 CA_FULL_RATE = 0
4915 12:14:59.122529 DQ_CKDIV4_EN = 1
4916 12:14:59.125416 CA_CKDIV4_EN = 1
4917 12:14:59.129122 CA_PREDIV_EN = 0
4918 12:14:59.132031 PH8_DLY = 0
4919 12:14:59.135314 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4920 12:14:59.138560 DQ_AAMCK_DIV = 4
4921 12:14:59.138647 CA_AAMCK_DIV = 4
4922 12:14:59.141820 CA_ADMCK_DIV = 4
4923 12:14:59.144887 DQ_TRACK_CA_EN = 0
4924 12:14:59.148485 CA_PICK = 933
4925 12:14:59.151808 CA_MCKIO = 933
4926 12:14:59.155272 MCKIO_SEMI = 0
4927 12:14:59.158202 PLL_FREQ = 3732
4928 12:14:59.158284 DQ_UI_PI_RATIO = 32
4929 12:14:59.161792 CA_UI_PI_RATIO = 0
4930 12:14:59.164821 ===================================
4931 12:14:59.168419 ===================================
4932 12:14:59.171721 memory_type:LPDDR4
4933 12:14:59.174720 GP_NUM : 10
4934 12:14:59.174856 SRAM_EN : 1
4935 12:14:59.178175 MD32_EN : 0
4936 12:14:59.181356 ===================================
4937 12:14:59.184386 [ANA_INIT] >>>>>>>>>>>>>>
4938 12:14:59.188261 <<<<<< [CONFIGURE PHASE]: ANA_TX
4939 12:14:59.191280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4940 12:14:59.194318 ===================================
4941 12:14:59.194434 data_rate = 1866,PCW = 0X8f00
4942 12:14:59.197456 ===================================
4943 12:14:59.201018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4944 12:14:59.207438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4945 12:14:59.214313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4946 12:14:59.217306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4947 12:14:59.220437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4948 12:14:59.223939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4949 12:14:59.227599 [ANA_INIT] flow start
4950 12:14:59.230474 [ANA_INIT] PLL >>>>>>>>
4951 12:14:59.230593 [ANA_INIT] PLL <<<<<<<<
4952 12:14:59.234106 [ANA_INIT] MIDPI >>>>>>>>
4953 12:14:59.237053 [ANA_INIT] MIDPI <<<<<<<<
4954 12:14:59.237169 [ANA_INIT] DLL >>>>>>>>
4955 12:14:59.240434 [ANA_INIT] flow end
4956 12:14:59.243896 ============ LP4 DIFF to SE enter ============
4957 12:14:59.247135 ============ LP4 DIFF to SE exit ============
4958 12:14:59.250236 [ANA_INIT] <<<<<<<<<<<<<
4959 12:14:59.253409 [Flow] Enable top DCM control >>>>>
4960 12:14:59.257006 [Flow] Enable top DCM control <<<<<
4961 12:14:59.260220 Enable DLL master slave shuffle
4962 12:14:59.266642 ==============================================================
4963 12:14:59.266738 Gating Mode config
4964 12:14:59.273247 ==============================================================
4965 12:14:59.276689 Config description:
4966 12:14:59.283217 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4967 12:14:59.292843 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4968 12:14:59.296440 SELPH_MODE 0: By rank 1: By Phase
4969 12:14:59.302886 ==============================================================
4970 12:14:59.306068 GAT_TRACK_EN = 1
4971 12:14:59.306209 RX_GATING_MODE = 2
4972 12:14:59.309875 RX_GATING_TRACK_MODE = 2
4973 12:14:59.312902 SELPH_MODE = 1
4974 12:14:59.316111 PICG_EARLY_EN = 1
4975 12:14:59.319171 VALID_LAT_VALUE = 1
4976 12:14:59.326052 ==============================================================
4977 12:14:59.329130 Enter into Gating configuration >>>>
4978 12:14:59.332657 Exit from Gating configuration <<<<
4979 12:14:59.335787 Enter into DVFS_PRE_config >>>>>
4980 12:14:59.346006 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4981 12:14:59.348897 Exit from DVFS_PRE_config <<<<<
4982 12:14:59.352565 Enter into PICG configuration >>>>
4983 12:14:59.355726 Exit from PICG configuration <<<<
4984 12:14:59.358779 [RX_INPUT] configuration >>>>>
4985 12:14:59.362360 [RX_INPUT] configuration <<<<<
4986 12:14:59.365507 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4987 12:14:59.372433 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4988 12:14:59.378769 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4989 12:14:59.385448 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4990 12:14:59.392107 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4991 12:14:59.395372 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4992 12:14:59.401610 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4993 12:14:59.405629 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4994 12:14:59.408697 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4995 12:14:59.411677 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4996 12:14:59.418685 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4997 12:14:59.421747 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 12:14:59.424860 ===================================
4999 12:14:59.428749 LPDDR4 DRAM CONFIGURATION
5000 12:14:59.431803 ===================================
5001 12:14:59.431911 EX_ROW_EN[0] = 0x0
5002 12:14:59.434839 EX_ROW_EN[1] = 0x0
5003 12:14:59.434958 LP4Y_EN = 0x0
5004 12:14:59.438578 WORK_FSP = 0x0
5005 12:14:59.438694 WL = 0x3
5006 12:14:59.441531 RL = 0x3
5007 12:14:59.441617 BL = 0x2
5008 12:14:59.444682 RPST = 0x0
5009 12:14:59.444800 RD_PRE = 0x0
5010 12:14:59.448154 WR_PRE = 0x1
5011 12:14:59.448266 WR_PST = 0x0
5012 12:14:59.451522 DBI_WR = 0x0
5013 12:14:59.454529 DBI_RD = 0x0
5014 12:14:59.454665 OTF = 0x1
5015 12:14:59.458047 ===================================
5016 12:14:59.461613 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5017 12:14:59.464578 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5018 12:14:59.471364 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5019 12:14:59.474519 ===================================
5020 12:14:59.478045 LPDDR4 DRAM CONFIGURATION
5021 12:14:59.481108 ===================================
5022 12:14:59.481189 EX_ROW_EN[0] = 0x10
5023 12:14:59.484652 EX_ROW_EN[1] = 0x0
5024 12:14:59.484773 LP4Y_EN = 0x0
5025 12:14:59.487654 WORK_FSP = 0x0
5026 12:14:59.487761 WL = 0x3
5027 12:14:59.491292 RL = 0x3
5028 12:14:59.491371 BL = 0x2
5029 12:14:59.494481 RPST = 0x0
5030 12:14:59.494584 RD_PRE = 0x0
5031 12:14:59.497622 WR_PRE = 0x1
5032 12:14:59.501163 WR_PST = 0x0
5033 12:14:59.501271 DBI_WR = 0x0
5034 12:14:59.504229 DBI_RD = 0x0
5035 12:14:59.504330 OTF = 0x1
5036 12:14:59.507321 ===================================
5037 12:14:59.513755 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5038 12:14:59.517603 nWR fixed to 30
5039 12:14:59.521311 [ModeRegInit_LP4] CH0 RK0
5040 12:14:59.521399 [ModeRegInit_LP4] CH0 RK1
5041 12:14:59.524372 [ModeRegInit_LP4] CH1 RK0
5042 12:14:59.527543 [ModeRegInit_LP4] CH1 RK1
5043 12:14:59.527631 match AC timing 9
5044 12:14:59.534111 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5045 12:14:59.537440 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5046 12:14:59.540945 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5047 12:14:59.547362 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5048 12:14:59.550618 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5049 12:14:59.550746 ==
5050 12:14:59.553857 Dram Type= 6, Freq= 0, CH_0, rank 0
5051 12:14:59.557246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5052 12:14:59.557334 ==
5053 12:14:59.563823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5054 12:14:59.570284 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5055 12:14:59.573300 [CA 0] Center 38 (8~69) winsize 62
5056 12:14:59.576993 [CA 1] Center 38 (7~69) winsize 63
5057 12:14:59.579988 [CA 2] Center 35 (6~65) winsize 60
5058 12:14:59.583576 [CA 3] Center 34 (4~65) winsize 62
5059 12:14:59.587117 [CA 4] Center 34 (4~65) winsize 62
5060 12:14:59.590048 [CA 5] Center 33 (3~64) winsize 62
5061 12:14:59.590134
5062 12:14:59.593262 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5063 12:14:59.593367
5064 12:14:59.596882 [CATrainingPosCal] consider 1 rank data
5065 12:14:59.599995 u2DelayCellTimex100 = 270/100 ps
5066 12:14:59.603493 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5067 12:14:59.606675 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5068 12:14:59.609861 CA2 delay=35 (6~65),Diff = 2 PI (12 cell)
5069 12:14:59.616512 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5070 12:14:59.619685 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5071 12:14:59.623301 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5072 12:14:59.623385
5073 12:14:59.626407 CA PerBit enable=1, Macro0, CA PI delay=33
5074 12:14:59.626522
5075 12:14:59.629496 [CBTSetCACLKResult] CA Dly = 33
5076 12:14:59.629599 CS Dly: 7 (0~38)
5077 12:14:59.629703 ==
5078 12:14:59.633170 Dram Type= 6, Freq= 0, CH_0, rank 1
5079 12:14:59.639595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 12:14:59.639723 ==
5081 12:14:59.642586 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 12:14:59.649445 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5083 12:14:59.653208 [CA 0] Center 38 (8~69) winsize 62
5084 12:14:59.656270 [CA 1] Center 38 (8~69) winsize 62
5085 12:14:59.659374 [CA 2] Center 35 (5~66) winsize 62
5086 12:14:59.663142 [CA 3] Center 35 (5~65) winsize 61
5087 12:14:59.666080 [CA 4] Center 34 (4~65) winsize 62
5088 12:14:59.669261 [CA 5] Center 33 (3~64) winsize 62
5089 12:14:59.669370
5090 12:14:59.672842 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5091 12:14:59.672950
5092 12:14:59.675821 [CATrainingPosCal] consider 2 rank data
5093 12:14:59.679540 u2DelayCellTimex100 = 270/100 ps
5094 12:14:59.682643 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5095 12:14:59.688854 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5096 12:14:59.692298 CA2 delay=35 (6~65),Diff = 2 PI (12 cell)
5097 12:14:59.695948 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5098 12:14:59.699115 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5099 12:14:59.702709 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5100 12:14:59.702839
5101 12:14:59.705816 CA PerBit enable=1, Macro0, CA PI delay=33
5102 12:14:59.705927
5103 12:14:59.708999 [CBTSetCACLKResult] CA Dly = 33
5104 12:14:59.712121 CS Dly: 7 (0~39)
5105 12:14:59.712207
5106 12:14:59.715771 ----->DramcWriteLeveling(PI) begin...
5107 12:14:59.715853 ==
5108 12:14:59.719159 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 12:14:59.722008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 12:14:59.722086 ==
5111 12:14:59.725647 Write leveling (Byte 0): 29 => 29
5112 12:14:59.728761 Write leveling (Byte 1): 29 => 29
5113 12:14:59.732036 DramcWriteLeveling(PI) end<-----
5114 12:14:59.732116
5115 12:14:59.732180 ==
5116 12:14:59.735161 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 12:14:59.738359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 12:14:59.738431 ==
5119 12:14:59.742160 [Gating] SW mode calibration
5120 12:14:59.748443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5121 12:14:59.755219 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5122 12:14:59.758142 0 14 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5123 12:14:59.764877 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5124 12:14:59.767814 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 12:14:59.771584 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 12:14:59.777964 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 12:14:59.781930 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 12:14:59.784755 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 12:14:59.791040 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 0) (1 0)
5130 12:14:59.794541 0 15 0 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (1 1)
5131 12:14:59.797781 0 15 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5132 12:14:59.804230 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 12:14:59.807849 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 12:14:59.810901 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 12:14:59.817695 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 12:14:59.820769 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 12:14:59.824417 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5138 12:14:59.830760 1 0 0 | B1->B0 | 2b2b 3c3c | 0 0 | (0 0) (0 0)
5139 12:14:59.833900 1 0 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5140 12:14:59.837833 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 12:14:59.844218 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 12:14:59.847186 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 12:14:59.850289 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 12:14:59.857296 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 12:14:59.860617 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5146 12:14:59.863412 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5147 12:14:59.870067 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5148 12:14:59.873574 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 12:14:59.876657 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 12:14:59.883283 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 12:14:59.886452 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 12:14:59.889942 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 12:14:59.896506 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 12:14:59.899516 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 12:14:59.903073 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 12:14:59.909260 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 12:14:59.912669 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 12:14:59.916043 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 12:14:59.922507 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 12:14:59.926311 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 12:14:59.929480 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5162 12:14:59.935617 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5163 12:14:59.939288 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 12:14:59.942488 Total UI for P1: 0, mck2ui 16
5165 12:14:59.945661 best dqsien dly found for B0: ( 1, 2, 30)
5166 12:14:59.948845 Total UI for P1: 0, mck2ui 16
5167 12:14:59.952673 best dqsien dly found for B1: ( 1, 3, 2)
5168 12:14:59.955757 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5169 12:14:59.958816 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5170 12:14:59.958919
5171 12:14:59.962179 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5172 12:14:59.965791 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5173 12:14:59.968880 [Gating] SW calibration Done
5174 12:14:59.968999 ==
5175 12:14:59.971952 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 12:14:59.975379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 12:14:59.978354 ==
5178 12:14:59.978493 RX Vref Scan: 0
5179 12:14:59.978591
5180 12:14:59.982171 RX Vref 0 -> 0, step: 1
5181 12:14:59.982279
5182 12:14:59.985292 RX Delay -80 -> 252, step: 8
5183 12:14:59.988256 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5184 12:14:59.991898 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5185 12:14:59.995017 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5186 12:14:59.998080 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5187 12:15:00.001743 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5188 12:15:00.008361 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5189 12:15:00.011947 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5190 12:15:00.015086 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5191 12:15:00.018132 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5192 12:15:00.021689 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5193 12:15:00.028231 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5194 12:15:00.031302 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5195 12:15:00.035087 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5196 12:15:00.038186 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5197 12:15:00.044943 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5198 12:15:00.048099 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5199 12:15:00.048223 ==
5200 12:15:00.051481 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 12:15:00.054577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 12:15:00.054700 ==
5203 12:15:00.057587 DQS Delay:
5204 12:15:00.057699 DQS0 = 0, DQS1 = 0
5205 12:15:00.057806 DQM Delay:
5206 12:15:00.061385 DQM0 = 94, DQM1 = 81
5207 12:15:00.061497 DQ Delay:
5208 12:15:00.064533 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5209 12:15:00.067587 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5210 12:15:00.070730 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5211 12:15:00.074327 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =87
5212 12:15:00.074473
5213 12:15:00.074620
5214 12:15:00.074756 ==
5215 12:15:00.077317 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 12:15:00.083900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 12:15:00.084054 ==
5218 12:15:00.084166
5219 12:15:00.084267
5220 12:15:00.084363 TX Vref Scan disable
5221 12:15:00.087920 == TX Byte 0 ==
5222 12:15:00.090769 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5223 12:15:00.097515 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5224 12:15:00.097647 == TX Byte 1 ==
5225 12:15:00.100713 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5226 12:15:00.107818 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5227 12:15:00.107953 ==
5228 12:15:00.110873 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 12:15:00.113841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 12:15:00.113950 ==
5231 12:15:00.114018
5232 12:15:00.114113
5233 12:15:00.117728 TX Vref Scan disable
5234 12:15:00.117845 == TX Byte 0 ==
5235 12:15:00.124287 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5236 12:15:00.127141 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5237 12:15:00.127292 == TX Byte 1 ==
5238 12:15:00.134045 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5239 12:15:00.137095 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5240 12:15:00.137214
5241 12:15:00.137322 [DATLAT]
5242 12:15:00.140731 Freq=933, CH0 RK0
5243 12:15:00.140842
5244 12:15:00.140946 DATLAT Default: 0xd
5245 12:15:00.143820 0, 0xFFFF, sum = 0
5246 12:15:00.147203 1, 0xFFFF, sum = 0
5247 12:15:00.147318 2, 0xFFFF, sum = 0
5248 12:15:00.150195 3, 0xFFFF, sum = 0
5249 12:15:00.150290 4, 0xFFFF, sum = 0
5250 12:15:00.153863 5, 0xFFFF, sum = 0
5251 12:15:00.153982 6, 0xFFFF, sum = 0
5252 12:15:00.157064 7, 0xFFFF, sum = 0
5253 12:15:00.157181 8, 0xFFFF, sum = 0
5254 12:15:00.160204 9, 0xFFFF, sum = 0
5255 12:15:00.160315 10, 0x0, sum = 1
5256 12:15:00.163370 11, 0x0, sum = 2
5257 12:15:00.163486 12, 0x0, sum = 3
5258 12:15:00.167104 13, 0x0, sum = 4
5259 12:15:00.167224 best_step = 11
5260 12:15:00.167321
5261 12:15:00.167414 ==
5262 12:15:00.170337 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 12:15:00.173415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 12:15:00.173533 ==
5265 12:15:00.176513 RX Vref Scan: 1
5266 12:15:00.176643
5267 12:15:00.179693 RX Vref 0 -> 0, step: 1
5268 12:15:00.179810
5269 12:15:00.179917 RX Delay -69 -> 252, step: 4
5270 12:15:00.183262
5271 12:15:00.183381 Set Vref, RX VrefLevel [Byte0]: 62
5272 12:15:00.186791 [Byte1]: 53
5273 12:15:00.191678
5274 12:15:00.191771 Final RX Vref Byte 0 = 62 to rank0
5275 12:15:00.195071 Final RX Vref Byte 1 = 53 to rank0
5276 12:15:00.198133 Final RX Vref Byte 0 = 62 to rank1
5277 12:15:00.201318 Final RX Vref Byte 1 = 53 to rank1==
5278 12:15:00.204493 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 12:15:00.211146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 12:15:00.211256 ==
5281 12:15:00.211325 DQS Delay:
5282 12:15:00.214841 DQS0 = 0, DQS1 = 0
5283 12:15:00.214965 DQM Delay:
5284 12:15:00.215063 DQM0 = 95, DQM1 = 83
5285 12:15:00.217846 DQ Delay:
5286 12:15:00.221349 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5287 12:15:00.224461 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5288 12:15:00.227874 DQ8 =76, DQ9 =70, DQ10 =82, DQ11 =76
5289 12:15:00.231421 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =90
5290 12:15:00.231539
5291 12:15:00.231635
5292 12:15:00.237877 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5293 12:15:00.241261 CH0 RK0: MR19=505, MR18=1212
5294 12:15:00.247563 CH0_RK0: MR19=0x505, MR18=0x1212, DQSOSC=416, MR23=63, INC=62, DEC=41
5295 12:15:00.247684
5296 12:15:00.250659 ----->DramcWriteLeveling(PI) begin...
5297 12:15:00.250777 ==
5298 12:15:00.254513 Dram Type= 6, Freq= 0, CH_0, rank 1
5299 12:15:00.257588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 12:15:00.257692 ==
5301 12:15:00.260907 Write leveling (Byte 0): 32 => 32
5302 12:15:00.264293 Write leveling (Byte 1): 31 => 31
5303 12:15:00.267313 DramcWriteLeveling(PI) end<-----
5304 12:15:00.267438
5305 12:15:00.267533 ==
5306 12:15:00.270693 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 12:15:00.273785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 12:15:00.277600 ==
5309 12:15:00.277716 [Gating] SW mode calibration
5310 12:15:00.287009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5311 12:15:00.290640 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5312 12:15:00.293485 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5313 12:15:00.300649 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 12:15:00.303841 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 12:15:00.307049 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 12:15:00.313867 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 12:15:00.316905 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 12:15:00.320081 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 12:15:00.326757 0 14 28 | B1->B0 | 3333 2828 | 1 0 | (1 1) (0 0)
5320 12:15:00.329799 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
5321 12:15:00.333571 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 12:15:00.339738 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 12:15:00.343126 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 12:15:00.346538 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 12:15:00.352705 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 12:15:00.356493 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5327 12:15:00.359710 0 15 28 | B1->B0 | 2b2b 3939 | 0 0 | (0 0) (0 0)
5328 12:15:00.366532 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5329 12:15:00.369719 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 12:15:00.372722 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 12:15:00.379522 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 12:15:00.382608 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 12:15:00.385756 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 12:15:00.392842 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 12:15:00.395812 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5336 12:15:00.399251 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5337 12:15:00.405629 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 12:15:00.409127 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 12:15:00.412501 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 12:15:00.418727 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 12:15:00.422047 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 12:15:00.425678 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 12:15:00.431784 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 12:15:00.435356 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 12:15:00.441940 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 12:15:00.444720 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 12:15:00.448267 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 12:15:00.454627 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 12:15:00.458345 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 12:15:00.461315 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5351 12:15:00.467809 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5352 12:15:00.471541 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5353 12:15:00.474657 Total UI for P1: 0, mck2ui 16
5354 12:15:00.477773 best dqsien dly found for B0: ( 1, 2, 26)
5355 12:15:00.480920 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 12:15:00.484732 Total UI for P1: 0, mck2ui 16
5357 12:15:00.487825 best dqsien dly found for B1: ( 1, 2, 30)
5358 12:15:00.491030 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5359 12:15:00.494094 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5360 12:15:00.494181
5361 12:15:00.501039 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5362 12:15:00.504052 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5363 12:15:00.504141 [Gating] SW calibration Done
5364 12:15:00.507138 ==
5365 12:15:00.510847 Dram Type= 6, Freq= 0, CH_0, rank 1
5366 12:15:00.513795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5367 12:15:00.513913 ==
5368 12:15:00.514019 RX Vref Scan: 0
5369 12:15:00.514086
5370 12:15:00.517301 RX Vref 0 -> 0, step: 1
5371 12:15:00.517416
5372 12:15:00.520821 RX Delay -80 -> 252, step: 8
5373 12:15:00.524049 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5374 12:15:00.527163 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5375 12:15:00.530361 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5376 12:15:00.537270 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5377 12:15:00.540258 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5378 12:15:00.543905 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5379 12:15:00.546977 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5380 12:15:00.550430 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5381 12:15:00.557075 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5382 12:15:00.560586 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5383 12:15:00.563754 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5384 12:15:00.566920 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5385 12:15:00.573551 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5386 12:15:00.576761 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5387 12:15:00.579996 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5388 12:15:00.583242 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5389 12:15:00.583354 ==
5390 12:15:00.586461 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 12:15:00.589548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 12:15:00.593242 ==
5393 12:15:00.593357 DQS Delay:
5394 12:15:00.593453 DQS0 = 0, DQS1 = 0
5395 12:15:00.596434 DQM Delay:
5396 12:15:00.596537 DQM0 = 92, DQM1 = 83
5397 12:15:00.599734 DQ Delay:
5398 12:15:00.599838 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =87
5399 12:15:00.603453 DQ4 =91, DQ5 =75, DQ6 =107, DQ7 =103
5400 12:15:00.606284 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5401 12:15:00.613178 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5402 12:15:00.613309
5403 12:15:00.613417
5404 12:15:00.613512 ==
5405 12:15:00.616224 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 12:15:00.619716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 12:15:00.619827 ==
5408 12:15:00.619920
5409 12:15:00.620012
5410 12:15:00.622639 TX Vref Scan disable
5411 12:15:00.622759 == TX Byte 0 ==
5412 12:15:00.629428 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5413 12:15:00.632694 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5414 12:15:00.632813 == TX Byte 1 ==
5415 12:15:00.639393 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5416 12:15:00.642849 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5417 12:15:00.642964 ==
5418 12:15:00.645738 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 12:15:00.649640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 12:15:00.649759 ==
5421 12:15:00.649861
5422 12:15:00.649952
5423 12:15:00.652605 TX Vref Scan disable
5424 12:15:00.655861 == TX Byte 0 ==
5425 12:15:00.659005 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5426 12:15:00.662485 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5427 12:15:00.665699 == TX Byte 1 ==
5428 12:15:00.669340 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5429 12:15:00.672211 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5430 12:15:00.675902
5431 12:15:00.675989 [DATLAT]
5432 12:15:00.676056 Freq=933, CH0 RK1
5433 12:15:00.676119
5434 12:15:00.678835 DATLAT Default: 0xb
5435 12:15:00.678923 0, 0xFFFF, sum = 0
5436 12:15:00.682382 1, 0xFFFF, sum = 0
5437 12:15:00.682520 2, 0xFFFF, sum = 0
5438 12:15:00.685588 3, 0xFFFF, sum = 0
5439 12:15:00.688878 4, 0xFFFF, sum = 0
5440 12:15:00.689008 5, 0xFFFF, sum = 0
5441 12:15:00.692159 6, 0xFFFF, sum = 0
5442 12:15:00.692289 7, 0xFFFF, sum = 0
5443 12:15:00.695217 8, 0xFFFF, sum = 0
5444 12:15:00.695344 9, 0xFFFF, sum = 0
5445 12:15:00.699039 10, 0x0, sum = 1
5446 12:15:00.699152 11, 0x0, sum = 2
5447 12:15:00.702233 12, 0x0, sum = 3
5448 12:15:00.702341 13, 0x0, sum = 4
5449 12:15:00.702438 best_step = 11
5450 12:15:00.702528
5451 12:15:00.705411 ==
5452 12:15:00.708490 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 12:15:00.711720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 12:15:00.711830 ==
5455 12:15:00.711933 RX Vref Scan: 0
5456 12:15:00.712025
5457 12:15:00.715133 RX Vref 0 -> 0, step: 1
5458 12:15:00.715238
5459 12:15:00.718246 RX Delay -77 -> 252, step: 4
5460 12:15:00.725141 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5461 12:15:00.728170 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5462 12:15:00.731398 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5463 12:15:00.734966 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5464 12:15:00.738263 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5465 12:15:00.741854 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5466 12:15:00.748325 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5467 12:15:00.751434 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5468 12:15:00.754576 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5469 12:15:00.758182 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5470 12:15:00.761296 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5471 12:15:00.768285 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5472 12:15:00.771454 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5473 12:15:00.774440 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5474 12:15:00.778208 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5475 12:15:00.781377 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5476 12:15:00.784318 ==
5477 12:15:00.784449 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 12:15:00.791224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 12:15:00.791376 ==
5480 12:15:00.791484 DQS Delay:
5481 12:15:00.794099 DQS0 = 0, DQS1 = 0
5482 12:15:00.794207 DQM Delay:
5483 12:15:00.797315 DQM0 = 92, DQM1 = 85
5484 12:15:00.797453 DQ Delay:
5485 12:15:00.800969 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5486 12:15:00.804170 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5487 12:15:00.807468 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5488 12:15:00.810591 DQ12 =90, DQ13 =92, DQ14 =94, DQ15 =94
5489 12:15:00.810713
5490 12:15:00.810816
5491 12:15:00.817184 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5492 12:15:00.820994 CH0 RK1: MR19=505, MR18=2B0C
5493 12:15:00.827055 CH0_RK1: MR19=0x505, MR18=0x2B0C, DQSOSC=408, MR23=63, INC=65, DEC=43
5494 12:15:00.830764 [RxdqsGatingPostProcess] freq 933
5495 12:15:00.837340 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5496 12:15:00.840234 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 12:15:00.843691 best DQS1 dly(2T, 0.5T) = (0, 11)
5498 12:15:00.846721 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 12:15:00.849895 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5500 12:15:00.850008 best DQS0 dly(2T, 0.5T) = (0, 10)
5501 12:15:00.853712 best DQS1 dly(2T, 0.5T) = (0, 10)
5502 12:15:00.856973 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5503 12:15:00.860138 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5504 12:15:00.863184 Pre-setting of DQS Precalculation
5505 12:15:00.869970 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5506 12:15:00.870115 ==
5507 12:15:00.873190 Dram Type= 6, Freq= 0, CH_1, rank 0
5508 12:15:00.876736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 12:15:00.876856 ==
5510 12:15:00.882948 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5511 12:15:00.889636 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5512 12:15:00.893433 [CA 0] Center 38 (8~68) winsize 61
5513 12:15:00.896364 [CA 1] Center 38 (8~69) winsize 62
5514 12:15:00.899693 [CA 2] Center 35 (6~65) winsize 60
5515 12:15:00.902764 [CA 3] Center 35 (5~65) winsize 61
5516 12:15:00.906125 [CA 4] Center 35 (6~65) winsize 60
5517 12:15:00.909755 [CA 5] Center 34 (5~64) winsize 60
5518 12:15:00.909871
5519 12:15:00.912950 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5520 12:15:00.913061
5521 12:15:00.916139 [CATrainingPosCal] consider 1 rank data
5522 12:15:00.919272 u2DelayCellTimex100 = 270/100 ps
5523 12:15:00.922929 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5524 12:15:00.925993 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5525 12:15:00.929671 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5526 12:15:00.932820 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5527 12:15:00.935965 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5528 12:15:00.938986 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5529 12:15:00.939098
5530 12:15:00.945765 CA PerBit enable=1, Macro0, CA PI delay=34
5531 12:15:00.945886
5532 12:15:00.949279 [CBTSetCACLKResult] CA Dly = 34
5533 12:15:00.949392 CS Dly: 7 (0~38)
5534 12:15:00.949495 ==
5535 12:15:00.952567 Dram Type= 6, Freq= 0, CH_1, rank 1
5536 12:15:00.955556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 12:15:00.955669 ==
5538 12:15:00.962465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5539 12:15:00.968614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5540 12:15:00.972323 [CA 0] Center 38 (8~69) winsize 62
5541 12:15:00.975267 [CA 1] Center 38 (8~69) winsize 62
5542 12:15:00.978356 [CA 2] Center 36 (6~66) winsize 61
5543 12:15:00.982083 [CA 3] Center 35 (5~66) winsize 62
5544 12:15:00.985295 [CA 4] Center 35 (5~66) winsize 62
5545 12:15:00.988556 [CA 5] Center 34 (4~65) winsize 62
5546 12:15:00.988675
5547 12:15:00.991513 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5548 12:15:00.991631
5549 12:15:00.995241 [CATrainingPosCal] consider 2 rank data
5550 12:15:00.998221 u2DelayCellTimex100 = 270/100 ps
5551 12:15:01.001263 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5552 12:15:01.005132 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5553 12:15:01.008259 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5554 12:15:01.011375 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5555 12:15:01.018371 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5556 12:15:01.021547 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5557 12:15:01.021671
5558 12:15:01.024686 CA PerBit enable=1, Macro0, CA PI delay=34
5559 12:15:01.024802
5560 12:15:01.027834 [CBTSetCACLKResult] CA Dly = 34
5561 12:15:01.027925 CS Dly: 7 (0~39)
5562 12:15:01.028003
5563 12:15:01.031420 ----->DramcWriteLeveling(PI) begin...
5564 12:15:01.031537 ==
5565 12:15:01.034477 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 12:15:01.041459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 12:15:01.041603 ==
5568 12:15:01.044669 Write leveling (Byte 0): 26 => 26
5569 12:15:01.047809 Write leveling (Byte 1): 28 => 28
5570 12:15:01.051256 DramcWriteLeveling(PI) end<-----
5571 12:15:01.051359
5572 12:15:01.051477 ==
5573 12:15:01.054374 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 12:15:01.057865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 12:15:01.057973 ==
5576 12:15:01.060978 [Gating] SW mode calibration
5577 12:15:01.067798 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5578 12:15:01.074199 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5579 12:15:01.077464 0 14 0 | B1->B0 | 2d2d 2e2e | 0 1 | (0 0) (1 1)
5580 12:15:01.080995 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 12:15:01.087297 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 12:15:01.091251 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 12:15:01.094225 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 12:15:01.097102 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 12:15:01.103795 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 12:15:01.107496 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (1 0) (1 0)
5587 12:15:01.110590 0 15 0 | B1->B0 | 2c2c 2c2c | 0 0 | (0 0) (0 0)
5588 12:15:01.117378 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 12:15:01.120690 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 12:15:01.123681 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 12:15:01.130312 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 12:15:01.133470 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 12:15:01.137200 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 12:15:01.143673 0 15 28 | B1->B0 | 2929 2a2a | 0 0 | (0 0) (0 0)
5595 12:15:01.146789 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5596 12:15:01.153039 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 12:15:01.157029 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 12:15:01.159860 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 12:15:01.166324 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 12:15:01.169977 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 12:15:01.173057 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 12:15:01.180018 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 12:15:01.183009 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5604 12:15:01.186218 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 12:15:01.193015 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:15:01.196281 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:15:01.199480 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 12:15:01.206031 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 12:15:01.209023 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 12:15:01.212712 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 12:15:01.218997 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 12:15:01.222120 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 12:15:01.225950 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 12:15:01.232229 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 12:15:01.235699 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 12:15:01.238873 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 12:15:01.245867 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 12:15:01.248995 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5619 12:15:01.252129 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 12:15:01.255371 Total UI for P1: 0, mck2ui 16
5621 12:15:01.259036 best dqsien dly found for B0: ( 1, 2, 28)
5622 12:15:01.261921 Total UI for P1: 0, mck2ui 16
5623 12:15:01.265410 best dqsien dly found for B1: ( 1, 2, 28)
5624 12:15:01.269104 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5625 12:15:01.272160 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5626 12:15:01.272266
5627 12:15:01.275505 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5628 12:15:01.281735 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5629 12:15:01.281857 [Gating] SW calibration Done
5630 12:15:01.281953 ==
5631 12:15:01.285457 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 12:15:01.291841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 12:15:01.291953 ==
5634 12:15:01.292026 RX Vref Scan: 0
5635 12:15:01.292089
5636 12:15:01.295000 RX Vref 0 -> 0, step: 1
5637 12:15:01.295114
5638 12:15:01.298615 RX Delay -80 -> 252, step: 8
5639 12:15:01.301731 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5640 12:15:01.304766 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5641 12:15:01.308404 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5642 12:15:01.314553 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5643 12:15:01.318118 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5644 12:15:01.321284 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5645 12:15:01.324454 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5646 12:15:01.327811 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5647 12:15:01.334757 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5648 12:15:01.338041 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5649 12:15:01.340831 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5650 12:15:01.344670 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5651 12:15:01.347910 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5652 12:15:01.350905 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5653 12:15:01.357472 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5654 12:15:01.361200 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5655 12:15:01.361317 ==
5656 12:15:01.364363 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 12:15:01.367575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 12:15:01.367696 ==
5659 12:15:01.370621 DQS Delay:
5660 12:15:01.370734 DQS0 = 0, DQS1 = 0
5661 12:15:01.370840 DQM Delay:
5662 12:15:01.374078 DQM0 = 96, DQM1 = 89
5663 12:15:01.374200 DQ Delay:
5664 12:15:01.377140 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5665 12:15:01.380675 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5666 12:15:01.384188 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5667 12:15:01.387227 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5668 12:15:01.387352
5669 12:15:01.387482
5670 12:15:01.387576 ==
5671 12:15:01.390398 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 12:15:01.397188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 12:15:01.397311 ==
5674 12:15:01.397409
5675 12:15:01.397500
5676 12:15:01.397588 TX Vref Scan disable
5677 12:15:01.401025 == TX Byte 0 ==
5678 12:15:01.404286 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5679 12:15:01.411024 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5680 12:15:01.411192 == TX Byte 1 ==
5681 12:15:01.414048 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5682 12:15:01.420774 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5683 12:15:01.420909 ==
5684 12:15:01.424349 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 12:15:01.427794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 12:15:01.427895 ==
5687 12:15:01.427965
5688 12:15:01.428027
5689 12:15:01.431072 TX Vref Scan disable
5690 12:15:01.431155 == TX Byte 0 ==
5691 12:15:01.437142 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5692 12:15:01.440399 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5693 12:15:01.444013 == TX Byte 1 ==
5694 12:15:01.447075 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5695 12:15:01.450333 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5696 12:15:01.450425
5697 12:15:01.450517 [DATLAT]
5698 12:15:01.454124 Freq=933, CH1 RK0
5699 12:15:01.454266
5700 12:15:01.454366 DATLAT Default: 0xd
5701 12:15:01.457224 0, 0xFFFF, sum = 0
5702 12:15:01.460485 1, 0xFFFF, sum = 0
5703 12:15:01.460619 2, 0xFFFF, sum = 0
5704 12:15:01.463660 3, 0xFFFF, sum = 0
5705 12:15:01.463785 4, 0xFFFF, sum = 0
5706 12:15:01.467295 5, 0xFFFF, sum = 0
5707 12:15:01.467427 6, 0xFFFF, sum = 0
5708 12:15:01.470603 7, 0xFFFF, sum = 0
5709 12:15:01.470731 8, 0xFFFF, sum = 0
5710 12:15:01.473766 9, 0xFFFF, sum = 0
5711 12:15:01.473889 10, 0x0, sum = 1
5712 12:15:01.477038 11, 0x0, sum = 2
5713 12:15:01.477158 12, 0x0, sum = 3
5714 12:15:01.479868 13, 0x0, sum = 4
5715 12:15:01.480031 best_step = 11
5716 12:15:01.480161
5717 12:15:01.480284 ==
5718 12:15:01.483516 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 12:15:01.486395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 12:15:01.489867 ==
5721 12:15:01.490015 RX Vref Scan: 1
5722 12:15:01.490148
5723 12:15:01.493620 RX Vref 0 -> 0, step: 1
5724 12:15:01.493772
5725 12:15:01.493896 RX Delay -61 -> 252, step: 4
5726 12:15:01.496803
5727 12:15:01.496949 Set Vref, RX VrefLevel [Byte0]: 58
5728 12:15:01.499918 [Byte1]: 49
5729 12:15:01.505025
5730 12:15:01.505189 Final RX Vref Byte 0 = 58 to rank0
5731 12:15:01.508340 Final RX Vref Byte 1 = 49 to rank0
5732 12:15:01.511519 Final RX Vref Byte 0 = 58 to rank1
5733 12:15:01.514715 Final RX Vref Byte 1 = 49 to rank1==
5734 12:15:01.518364 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 12:15:01.524722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 12:15:01.524906 ==
5737 12:15:01.525053 DQS Delay:
5738 12:15:01.527544 DQS0 = 0, DQS1 = 0
5739 12:15:01.527682 DQM Delay:
5740 12:15:01.527809 DQM0 = 99, DQM1 = 91
5741 12:15:01.531164 DQ Delay:
5742 12:15:01.534275 DQ0 =104, DQ1 =96, DQ2 =86, DQ3 =94
5743 12:15:01.537990 DQ4 =98, DQ5 =108, DQ6 =112, DQ7 =96
5744 12:15:01.541137 DQ8 =80, DQ9 =84, DQ10 =90, DQ11 =86
5745 12:15:01.544410 DQ12 =102, DQ13 =96, DQ14 =98, DQ15 =98
5746 12:15:01.544514
5747 12:15:01.544603
5748 12:15:01.551168 [DQSOSCAuto] RK0, (LSB)MR18= 0x9, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5749 12:15:01.554476 CH1 RK0: MR19=505, MR18=9
5750 12:15:01.560739 CH1_RK0: MR19=0x505, MR18=0x9, DQSOSC=419, MR23=63, INC=61, DEC=41
5751 12:15:01.560850
5752 12:15:01.564359 ----->DramcWriteLeveling(PI) begin...
5753 12:15:01.564455 ==
5754 12:15:01.567584 Dram Type= 6, Freq= 0, CH_1, rank 1
5755 12:15:01.570659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 12:15:01.570758 ==
5757 12:15:01.574367 Write leveling (Byte 0): 25 => 25
5758 12:15:01.577370 Write leveling (Byte 1): 26 => 26
5759 12:15:01.580763 DramcWriteLeveling(PI) end<-----
5760 12:15:01.580858
5761 12:15:01.580928 ==
5762 12:15:01.583755 Dram Type= 6, Freq= 0, CH_1, rank 1
5763 12:15:01.587042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 12:15:01.587198 ==
5765 12:15:01.590564 [Gating] SW mode calibration
5766 12:15:01.597225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5767 12:15:01.603687 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5768 12:15:01.606807 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5769 12:15:01.613668 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 12:15:01.616813 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 12:15:01.619997 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 12:15:01.626292 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 12:15:01.630042 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5774 12:15:01.633089 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5775 12:15:01.639605 0 14 28 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
5776 12:15:01.643143 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5777 12:15:01.646256 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 12:15:01.652921 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 12:15:01.656098 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 12:15:01.659286 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 12:15:01.665630 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 12:15:01.669337 0 15 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5783 12:15:01.672550 0 15 28 | B1->B0 | 3535 4545 | 1 0 | (0 0) (0 0)
5784 12:15:01.679393 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5785 12:15:01.682604 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 12:15:01.685902 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 12:15:01.692235 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 12:15:01.695743 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 12:15:01.698785 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 12:15:01.705311 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 12:15:01.708718 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5792 12:15:01.712328 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 12:15:01.718407 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 12:15:01.722135 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 12:15:01.725371 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 12:15:01.731667 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 12:15:01.734870 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 12:15:01.738515 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 12:15:01.745084 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 12:15:01.748270 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 12:15:01.751422 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 12:15:01.758345 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 12:15:01.761330 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 12:15:01.765063 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 12:15:01.771284 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 12:15:01.774435 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5807 12:15:01.778275 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5808 12:15:01.781341 Total UI for P1: 0, mck2ui 16
5809 12:15:01.784421 best dqsien dly found for B0: ( 1, 2, 24)
5810 12:15:01.791533 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 12:15:01.794640 Total UI for P1: 0, mck2ui 16
5812 12:15:01.797710 best dqsien dly found for B1: ( 1, 2, 26)
5813 12:15:01.800891 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5814 12:15:01.804574 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5815 12:15:01.804668
5816 12:15:01.807617 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5817 12:15:01.810966 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5818 12:15:01.814576 [Gating] SW calibration Done
5819 12:15:01.814694 ==
5820 12:15:01.817650 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 12:15:01.820901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 12:15:01.821014 ==
5823 12:15:01.824261 RX Vref Scan: 0
5824 12:15:01.824371
5825 12:15:01.827254 RX Vref 0 -> 0, step: 1
5826 12:15:01.827360
5827 12:15:01.827463 RX Delay -80 -> 252, step: 8
5828 12:15:01.834369 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5829 12:15:01.837360 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5830 12:15:01.840545 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5831 12:15:01.843754 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5832 12:15:01.847351 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5833 12:15:01.854000 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5834 12:15:01.857382 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5835 12:15:01.860475 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5836 12:15:01.863381 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5837 12:15:01.867027 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5838 12:15:01.870178 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5839 12:15:01.876405 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5840 12:15:01.880228 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5841 12:15:01.883336 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5842 12:15:01.886539 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5843 12:15:01.889849 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5844 12:15:01.889969 ==
5845 12:15:01.892988 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 12:15:01.900082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 12:15:01.900177 ==
5848 12:15:01.900243 DQS Delay:
5849 12:15:01.903106 DQS0 = 0, DQS1 = 0
5850 12:15:01.903212 DQM Delay:
5851 12:15:01.906254 DQM0 = 94, DQM1 = 91
5852 12:15:01.906366 DQ Delay:
5853 12:15:01.909386 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5854 12:15:01.913182 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5855 12:15:01.916259 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =87
5856 12:15:01.919711 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5857 12:15:01.919803
5858 12:15:01.919870
5859 12:15:01.919932 ==
5860 12:15:01.923010 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 12:15:01.926416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 12:15:01.926524 ==
5863 12:15:01.926616
5864 12:15:01.926707
5865 12:15:01.929565 TX Vref Scan disable
5866 12:15:01.932612 == TX Byte 0 ==
5867 12:15:01.935849 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5868 12:15:01.939649 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5869 12:15:01.942753 == TX Byte 1 ==
5870 12:15:01.945925 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5871 12:15:01.949617 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5872 12:15:01.949705 ==
5873 12:15:01.952649 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 12:15:01.959531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 12:15:01.959672 ==
5876 12:15:01.959771
5877 12:15:01.959861
5878 12:15:01.959965 TX Vref Scan disable
5879 12:15:01.963484 == TX Byte 0 ==
5880 12:15:01.966400 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5881 12:15:01.973241 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5882 12:15:01.973341 == TX Byte 1 ==
5883 12:15:01.976333 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5884 12:15:01.982735 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5885 12:15:01.982856
5886 12:15:01.982935 [DATLAT]
5887 12:15:01.982998 Freq=933, CH1 RK1
5888 12:15:01.983058
5889 12:15:01.986026 DATLAT Default: 0xb
5890 12:15:01.989989 0, 0xFFFF, sum = 0
5891 12:15:01.990083 1, 0xFFFF, sum = 0
5892 12:15:01.992963 2, 0xFFFF, sum = 0
5893 12:15:01.993055 3, 0xFFFF, sum = 0
5894 12:15:01.996043 4, 0xFFFF, sum = 0
5895 12:15:01.996164 5, 0xFFFF, sum = 0
5896 12:15:01.999128 6, 0xFFFF, sum = 0
5897 12:15:01.999213 7, 0xFFFF, sum = 0
5898 12:15:02.003030 8, 0xFFFF, sum = 0
5899 12:15:02.003114 9, 0xFFFF, sum = 0
5900 12:15:02.006104 10, 0x0, sum = 1
5901 12:15:02.006217 11, 0x0, sum = 2
5902 12:15:02.009486 12, 0x0, sum = 3
5903 12:15:02.009602 13, 0x0, sum = 4
5904 12:15:02.012565 best_step = 11
5905 12:15:02.012670
5906 12:15:02.012763 ==
5907 12:15:02.015639 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 12:15:02.018891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 12:15:02.019003 ==
5910 12:15:02.019094 RX Vref Scan: 0
5911 12:15:02.019159
5912 12:15:02.022436 RX Vref 0 -> 0, step: 1
5913 12:15:02.022543
5914 12:15:02.025541 RX Delay -61 -> 252, step: 4
5915 12:15:02.031928 iDelay=203, Bit 0, Center 98 (3 ~ 194) 192
5916 12:15:02.035528 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5917 12:15:02.038687 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5918 12:15:02.041880 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5919 12:15:02.045179 iDelay=203, Bit 4, Center 92 (-1 ~ 186) 188
5920 12:15:02.051884 iDelay=203, Bit 5, Center 104 (11 ~ 198) 188
5921 12:15:02.055067 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5922 12:15:02.058503 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5923 12:15:02.061910 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
5924 12:15:02.064908 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5925 12:15:02.068721 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5926 12:15:02.075280 iDelay=203, Bit 11, Center 88 (-1 ~ 178) 180
5927 12:15:02.078418 iDelay=203, Bit 12, Center 102 (15 ~ 190) 176
5928 12:15:02.081679 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5929 12:15:02.084773 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5930 12:15:02.092169 iDelay=203, Bit 15, Center 100 (11 ~ 190) 180
5931 12:15:02.092275 ==
5932 12:15:02.095259 Dram Type= 6, Freq= 0, CH_1, rank 1
5933 12:15:02.098405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5934 12:15:02.098522 ==
5935 12:15:02.098616 DQS Delay:
5936 12:15:02.101297 DQS0 = 0, DQS1 = 0
5937 12:15:02.101381 DQM Delay:
5938 12:15:02.104591 DQM0 = 94, DQM1 = 94
5939 12:15:02.104677 DQ Delay:
5940 12:15:02.107691 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =92
5941 12:15:02.111657 DQ4 =92, DQ5 =104, DQ6 =106, DQ7 =92
5942 12:15:02.114686 DQ8 =80, DQ9 =88, DQ10 =94, DQ11 =88
5943 12:15:02.117925 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =100
5944 12:15:02.118005
5945 12:15:02.118069
5946 12:15:02.128097 [DQSOSCAuto] RK1, (LSB)MR18= 0xd21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
5947 12:15:02.128197 CH1 RK1: MR19=505, MR18=D21
5948 12:15:02.134067 CH1_RK1: MR19=0x505, MR18=0xD21, DQSOSC=411, MR23=63, INC=64, DEC=42
5949 12:15:02.137747 [RxdqsGatingPostProcess] freq 933
5950 12:15:02.144183 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5951 12:15:02.147164 best DQS0 dly(2T, 0.5T) = (0, 10)
5952 12:15:02.150878 best DQS1 dly(2T, 0.5T) = (0, 10)
5953 12:15:02.154134 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5954 12:15:02.157258 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5955 12:15:02.160402 best DQS0 dly(2T, 0.5T) = (0, 10)
5956 12:15:02.160503 best DQS1 dly(2T, 0.5T) = (0, 10)
5957 12:15:02.164090 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5958 12:15:02.167156 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5959 12:15:02.170921 Pre-setting of DQS Precalculation
5960 12:15:02.176995 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5961 12:15:02.183512 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5962 12:15:02.190582 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5963 12:15:02.190718
5964 12:15:02.190816
5965 12:15:02.193737 [Calibration Summary] 1866 Mbps
5966 12:15:02.196828 CH 0, Rank 0
5967 12:15:02.196934 SW Impedance : PASS
5968 12:15:02.200047 DUTY Scan : NO K
5969 12:15:02.203156 ZQ Calibration : PASS
5970 12:15:02.203267 Jitter Meter : NO K
5971 12:15:02.206392 CBT Training : PASS
5972 12:15:02.210222 Write leveling : PASS
5973 12:15:02.210299 RX DQS gating : PASS
5974 12:15:02.213366 RX DQ/DQS(RDDQC) : PASS
5975 12:15:02.213474 TX DQ/DQS : PASS
5976 12:15:02.216591 RX DATLAT : PASS
5977 12:15:02.219998 RX DQ/DQS(Engine): PASS
5978 12:15:02.220078 TX OE : NO K
5979 12:15:02.223588 All Pass.
5980 12:15:02.223676
5981 12:15:02.223741 CH 0, Rank 1
5982 12:15:02.226897 SW Impedance : PASS
5983 12:15:02.226975 DUTY Scan : NO K
5984 12:15:02.229969 ZQ Calibration : PASS
5985 12:15:02.233099 Jitter Meter : NO K
5986 12:15:02.233229 CBT Training : PASS
5987 12:15:02.236664 Write leveling : PASS
5988 12:15:02.239911 RX DQS gating : PASS
5989 12:15:02.240024 RX DQ/DQS(RDDQC) : PASS
5990 12:15:02.243008 TX DQ/DQS : PASS
5991 12:15:02.246133 RX DATLAT : PASS
5992 12:15:02.246212 RX DQ/DQS(Engine): PASS
5993 12:15:02.249925 TX OE : NO K
5994 12:15:02.250003 All Pass.
5995 12:15:02.250066
5996 12:15:02.252857 CH 1, Rank 0
5997 12:15:02.252963 SW Impedance : PASS
5998 12:15:02.256025 DUTY Scan : NO K
5999 12:15:02.259787 ZQ Calibration : PASS
6000 12:15:02.259876 Jitter Meter : NO K
6001 12:15:02.263007 CBT Training : PASS
6002 12:15:02.266190 Write leveling : PASS
6003 12:15:02.266273 RX DQS gating : PASS
6004 12:15:02.269382 RX DQ/DQS(RDDQC) : PASS
6005 12:15:02.272539 TX DQ/DQS : PASS
6006 12:15:02.272625 RX DATLAT : PASS
6007 12:15:02.276370 RX DQ/DQS(Engine): PASS
6008 12:15:02.279644 TX OE : NO K
6009 12:15:02.279732 All Pass.
6010 12:15:02.279799
6011 12:15:02.279861 CH 1, Rank 1
6012 12:15:02.282537 SW Impedance : PASS
6013 12:15:02.286021 DUTY Scan : NO K
6014 12:15:02.286107 ZQ Calibration : PASS
6015 12:15:02.289010 Jitter Meter : NO K
6016 12:15:02.292233 CBT Training : PASS
6017 12:15:02.292320 Write leveling : PASS
6018 12:15:02.295796 RX DQS gating : PASS
6019 12:15:02.295896 RX DQ/DQS(RDDQC) : PASS
6020 12:15:02.299296 TX DQ/DQS : PASS
6021 12:15:02.302406 RX DATLAT : PASS
6022 12:15:02.302483 RX DQ/DQS(Engine): PASS
6023 12:15:02.305798 TX OE : NO K
6024 12:15:02.305882 All Pass.
6025 12:15:02.305947
6026 12:15:02.308928 DramC Write-DBI off
6027 12:15:02.312336 PER_BANK_REFRESH: Hybrid Mode
6028 12:15:02.312421 TX_TRACKING: ON
6029 12:15:02.322306 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6030 12:15:02.325386 [FAST_K] Save calibration result to emmc
6031 12:15:02.328592 dramc_set_vcore_voltage set vcore to 650000
6032 12:15:02.331963 Read voltage for 400, 6
6033 12:15:02.332048 Vio18 = 0
6034 12:15:02.335539 Vcore = 650000
6035 12:15:02.335626 Vdram = 0
6036 12:15:02.335692 Vddq = 0
6037 12:15:02.335754 Vmddr = 0
6038 12:15:02.342237 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6039 12:15:02.348277 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6040 12:15:02.348388 MEM_TYPE=3, freq_sel=20
6041 12:15:02.351851 sv_algorithm_assistance_LP4_800
6042 12:15:02.354853 ============ PULL DRAM RESETB DOWN ============
6043 12:15:02.361777 ========== PULL DRAM RESETB DOWN end =========
6044 12:15:02.365068 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6045 12:15:02.368120 ===================================
6046 12:15:02.371991 LPDDR4 DRAM CONFIGURATION
6047 12:15:02.374991 ===================================
6048 12:15:02.375072 EX_ROW_EN[0] = 0x0
6049 12:15:02.378008 EX_ROW_EN[1] = 0x0
6050 12:15:02.378086 LP4Y_EN = 0x0
6051 12:15:02.381748 WORK_FSP = 0x0
6052 12:15:02.381824 WL = 0x2
6053 12:15:02.385030 RL = 0x2
6054 12:15:02.387869 BL = 0x2
6055 12:15:02.387988 RPST = 0x0
6056 12:15:02.391602 RD_PRE = 0x0
6057 12:15:02.391716 WR_PRE = 0x1
6058 12:15:02.394596 WR_PST = 0x0
6059 12:15:02.394709 DBI_WR = 0x0
6060 12:15:02.398082 DBI_RD = 0x0
6061 12:15:02.398195 OTF = 0x1
6062 12:15:02.401107 ===================================
6063 12:15:02.405008 ===================================
6064 12:15:02.408063 ANA top config
6065 12:15:02.411273 ===================================
6066 12:15:02.411386 DLL_ASYNC_EN = 0
6067 12:15:02.414517 ALL_SLAVE_EN = 1
6068 12:15:02.418293 NEW_RANK_MODE = 1
6069 12:15:02.421394 DLL_IDLE_MODE = 1
6070 12:15:02.421507 LP45_APHY_COMB_EN = 1
6071 12:15:02.424684 TX_ODT_DIS = 1
6072 12:15:02.427864 NEW_8X_MODE = 1
6073 12:15:02.431191 ===================================
6074 12:15:02.434412 ===================================
6075 12:15:02.437555 data_rate = 800
6076 12:15:02.440734 CKR = 1
6077 12:15:02.444455 DQ_P2S_RATIO = 4
6078 12:15:02.447430 ===================================
6079 12:15:02.447547 CA_P2S_RATIO = 4
6080 12:15:02.450669 DQ_CA_OPEN = 0
6081 12:15:02.453881 DQ_SEMI_OPEN = 1
6082 12:15:02.457496 CA_SEMI_OPEN = 1
6083 12:15:02.460357 CA_FULL_RATE = 0
6084 12:15:02.463726 DQ_CKDIV4_EN = 0
6085 12:15:02.463845 CA_CKDIV4_EN = 1
6086 12:15:02.467513 CA_PREDIV_EN = 0
6087 12:15:02.470845 PH8_DLY = 0
6088 12:15:02.473727 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6089 12:15:02.477417 DQ_AAMCK_DIV = 0
6090 12:15:02.480567 CA_AAMCK_DIV = 0
6091 12:15:02.483579 CA_ADMCK_DIV = 4
6092 12:15:02.483699 DQ_TRACK_CA_EN = 0
6093 12:15:02.486703 CA_PICK = 800
6094 12:15:02.490268 CA_MCKIO = 400
6095 12:15:02.493491 MCKIO_SEMI = 400
6096 12:15:02.497083 PLL_FREQ = 3016
6097 12:15:02.500184 DQ_UI_PI_RATIO = 32
6098 12:15:02.503717 CA_UI_PI_RATIO = 32
6099 12:15:02.506587 ===================================
6100 12:15:02.510222 ===================================
6101 12:15:02.510350 memory_type:LPDDR4
6102 12:15:02.513340 GP_NUM : 10
6103 12:15:02.516651 SRAM_EN : 1
6104 12:15:02.516765 MD32_EN : 0
6105 12:15:02.519803 ===================================
6106 12:15:02.522910 [ANA_INIT] >>>>>>>>>>>>>>
6107 12:15:02.526661 <<<<<< [CONFIGURE PHASE]: ANA_TX
6108 12:15:02.529902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6109 12:15:02.532963 ===================================
6110 12:15:02.536800 data_rate = 800,PCW = 0X7400
6111 12:15:02.539841 ===================================
6112 12:15:02.542988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6113 12:15:02.546327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6114 12:15:02.559626 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6115 12:15:02.562529 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6116 12:15:02.566012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6117 12:15:02.569133 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6118 12:15:02.572341 [ANA_INIT] flow start
6119 12:15:02.576087 [ANA_INIT] PLL >>>>>>>>
6120 12:15:02.576202 [ANA_INIT] PLL <<<<<<<<
6121 12:15:02.579240 [ANA_INIT] MIDPI >>>>>>>>
6122 12:15:02.582382 [ANA_INIT] MIDPI <<<<<<<<
6123 12:15:02.582497 [ANA_INIT] DLL >>>>>>>>
6124 12:15:02.585609 [ANA_INIT] flow end
6125 12:15:02.588778 ============ LP4 DIFF to SE enter ============
6126 12:15:02.595727 ============ LP4 DIFF to SE exit ============
6127 12:15:02.595851 [ANA_INIT] <<<<<<<<<<<<<
6128 12:15:02.598801 [Flow] Enable top DCM control >>>>>
6129 12:15:02.602301 [Flow] Enable top DCM control <<<<<
6130 12:15:02.605929 Enable DLL master slave shuffle
6131 12:15:02.612306 ==============================================================
6132 12:15:02.612431 Gating Mode config
6133 12:15:02.618764 ==============================================================
6134 12:15:02.621900 Config description:
6135 12:15:02.632031 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6136 12:15:02.638653 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6137 12:15:02.641776 SELPH_MODE 0: By rank 1: By Phase
6138 12:15:02.648721 ==============================================================
6139 12:15:02.651696 GAT_TRACK_EN = 0
6140 12:15:02.654953 RX_GATING_MODE = 2
6141 12:15:02.655070 RX_GATING_TRACK_MODE = 2
6142 12:15:02.658019 SELPH_MODE = 1
6143 12:15:02.661856 PICG_EARLY_EN = 1
6144 12:15:02.664983 VALID_LAT_VALUE = 1
6145 12:15:02.671227 ==============================================================
6146 12:15:02.674903 Enter into Gating configuration >>>>
6147 12:15:02.678056 Exit from Gating configuration <<<<
6148 12:15:02.681242 Enter into DVFS_PRE_config >>>>>
6149 12:15:02.690823 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6150 12:15:02.694630 Exit from DVFS_PRE_config <<<<<
6151 12:15:02.697681 Enter into PICG configuration >>>>
6152 12:15:02.701025 Exit from PICG configuration <<<<
6153 12:15:02.704603 [RX_INPUT] configuration >>>>>
6154 12:15:02.707585 [RX_INPUT] configuration <<<<<
6155 12:15:02.711408 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6156 12:15:02.717712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6157 12:15:02.724353 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6158 12:15:02.730640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6159 12:15:02.737008 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6160 12:15:02.743915 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6161 12:15:02.747005 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6162 12:15:02.750689 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6163 12:15:02.753810 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6164 12:15:02.760037 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6165 12:15:02.763380 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6166 12:15:02.767173 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6167 12:15:02.770277 ===================================
6168 12:15:02.773393 LPDDR4 DRAM CONFIGURATION
6169 12:15:02.776656 ===================================
6170 12:15:02.776785 EX_ROW_EN[0] = 0x0
6171 12:15:02.780018 EX_ROW_EN[1] = 0x0
6172 12:15:02.783181 LP4Y_EN = 0x0
6173 12:15:02.783297 WORK_FSP = 0x0
6174 12:15:02.786281 WL = 0x2
6175 12:15:02.786392 RL = 0x2
6176 12:15:02.790089 BL = 0x2
6177 12:15:02.790203 RPST = 0x0
6178 12:15:02.793351 RD_PRE = 0x0
6179 12:15:02.793462 WR_PRE = 0x1
6180 12:15:02.796228 WR_PST = 0x0
6181 12:15:02.796338 DBI_WR = 0x0
6182 12:15:02.799380 DBI_RD = 0x0
6183 12:15:02.799490 OTF = 0x1
6184 12:15:02.803151 ===================================
6185 12:15:02.806185 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6186 12:15:02.813094 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6187 12:15:02.816264 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6188 12:15:02.819302 ===================================
6189 12:15:02.822528 LPDDR4 DRAM CONFIGURATION
6190 12:15:02.826051 ===================================
6191 12:15:02.826134 EX_ROW_EN[0] = 0x10
6192 12:15:02.829096 EX_ROW_EN[1] = 0x0
6193 12:15:02.832763 LP4Y_EN = 0x0
6194 12:15:02.832844 WORK_FSP = 0x0
6195 12:15:02.835890 WL = 0x2
6196 12:15:02.836002 RL = 0x2
6197 12:15:02.839124 BL = 0x2
6198 12:15:02.839202 RPST = 0x0
6199 12:15:02.842259 RD_PRE = 0x0
6200 12:15:02.842363 WR_PRE = 0x1
6201 12:15:02.845401 WR_PST = 0x0
6202 12:15:02.845475 DBI_WR = 0x0
6203 12:15:02.849245 DBI_RD = 0x0
6204 12:15:02.849356 OTF = 0x1
6205 12:15:02.852306 ===================================
6206 12:15:02.858682 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6207 12:15:02.863453 nWR fixed to 30
6208 12:15:02.866586 [ModeRegInit_LP4] CH0 RK0
6209 12:15:02.866698 [ModeRegInit_LP4] CH0 RK1
6210 12:15:02.869847 [ModeRegInit_LP4] CH1 RK0
6211 12:15:02.873448 [ModeRegInit_LP4] CH1 RK1
6212 12:15:02.873559 match AC timing 19
6213 12:15:02.879773 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6214 12:15:02.882895 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6215 12:15:02.886164 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6216 12:15:02.892788 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6217 12:15:02.896722 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6218 12:15:02.896833 ==
6219 12:15:02.899223 Dram Type= 6, Freq= 0, CH_0, rank 0
6220 12:15:02.902925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6221 12:15:02.903007 ==
6222 12:15:02.909779 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6223 12:15:02.915699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6224 12:15:02.919381 [CA 0] Center 36 (8~64) winsize 57
6225 12:15:02.922668 [CA 1] Center 36 (8~64) winsize 57
6226 12:15:02.925946 [CA 2] Center 36 (8~64) winsize 57
6227 12:15:02.928921 [CA 3] Center 36 (8~64) winsize 57
6228 12:15:02.932447 [CA 4] Center 36 (8~64) winsize 57
6229 12:15:02.935973 [CA 5] Center 36 (8~64) winsize 57
6230 12:15:02.936062
6231 12:15:02.939065 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6232 12:15:02.939170
6233 12:15:02.942399 [CATrainingPosCal] consider 1 rank data
6234 12:15:02.945503 u2DelayCellTimex100 = 270/100 ps
6235 12:15:02.949346 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 12:15:02.952308 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 12:15:02.955501 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 12:15:02.958804 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 12:15:02.962478 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 12:15:02.965330 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 12:15:02.965436
6242 12:15:02.972231 CA PerBit enable=1, Macro0, CA PI delay=36
6243 12:15:02.972344
6244 12:15:02.972439 [CBTSetCACLKResult] CA Dly = 36
6245 12:15:02.975341 CS Dly: 1 (0~32)
6246 12:15:02.975424 ==
6247 12:15:02.978589 Dram Type= 6, Freq= 0, CH_0, rank 1
6248 12:15:02.981734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6249 12:15:02.981838 ==
6250 12:15:02.988646 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6251 12:15:02.995447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6252 12:15:02.998603 [CA 0] Center 36 (8~64) winsize 57
6253 12:15:03.001729 [CA 1] Center 36 (8~64) winsize 57
6254 12:15:03.004814 [CA 2] Center 36 (8~64) winsize 57
6255 12:15:03.008194 [CA 3] Center 36 (8~64) winsize 57
6256 12:15:03.011911 [CA 4] Center 36 (8~64) winsize 57
6257 12:15:03.011999 [CA 5] Center 36 (8~64) winsize 57
6258 12:15:03.014776
6259 12:15:03.017950 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6260 12:15:03.018030
6261 12:15:03.021748 [CATrainingPosCal] consider 2 rank data
6262 12:15:03.025086 u2DelayCellTimex100 = 270/100 ps
6263 12:15:03.027907 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 12:15:03.031151 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 12:15:03.034714 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 12:15:03.037994 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 12:15:03.041558 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 12:15:03.044721 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 12:15:03.044832
6270 12:15:03.047722 CA PerBit enable=1, Macro0, CA PI delay=36
6271 12:15:03.050826
6272 12:15:03.050923 [CBTSetCACLKResult] CA Dly = 36
6273 12:15:03.054237 CS Dly: 1 (0~32)
6274 12:15:03.054316
6275 12:15:03.057848 ----->DramcWriteLeveling(PI) begin...
6276 12:15:03.057930 ==
6277 12:15:03.061150 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 12:15:03.064201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 12:15:03.064281 ==
6280 12:15:03.067176 Write leveling (Byte 0): 40 => 8
6281 12:15:03.070755 Write leveling (Byte 1): 40 => 8
6282 12:15:03.074028 DramcWriteLeveling(PI) end<-----
6283 12:15:03.074140
6284 12:15:03.074234 ==
6285 12:15:03.077091 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 12:15:03.080248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 12:15:03.083369 ==
6288 12:15:03.083450 [Gating] SW mode calibration
6289 12:15:03.093639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6290 12:15:03.096723 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6291 12:15:03.100336 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6292 12:15:03.106629 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6293 12:15:03.110381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6294 12:15:03.113352 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 12:15:03.119900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6296 12:15:03.123785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 12:15:03.126563 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 12:15:03.132863 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 12:15:03.136621 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 12:15:03.139632 Total UI for P1: 0, mck2ui 16
6301 12:15:03.143124 best dqsien dly found for B0: ( 0, 14, 24)
6302 12:15:03.146202 Total UI for P1: 0, mck2ui 16
6303 12:15:03.149394 best dqsien dly found for B1: ( 0, 14, 24)
6304 12:15:03.152840 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6305 12:15:03.155968 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6306 12:15:03.156049
6307 12:15:03.159149 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6308 12:15:03.165981 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6309 12:15:03.166065 [Gating] SW calibration Done
6310 12:15:03.169251 ==
6311 12:15:03.172333 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 12:15:03.176141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 12:15:03.176220 ==
6314 12:15:03.176283 RX Vref Scan: 0
6315 12:15:03.176342
6316 12:15:03.178668 RX Vref 0 -> 0, step: 1
6317 12:15:03.178773
6318 12:15:03.182488 RX Delay -410 -> 252, step: 16
6319 12:15:03.185753 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6320 12:15:03.192581 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6321 12:15:03.195778 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6322 12:15:03.198914 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6323 12:15:03.202081 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6324 12:15:03.208670 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6325 12:15:03.211690 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6326 12:15:03.215000 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6327 12:15:03.218768 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6328 12:15:03.225274 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6329 12:15:03.228586 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6330 12:15:03.231651 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6331 12:15:03.235338 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6332 12:15:03.241611 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6333 12:15:03.244787 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6334 12:15:03.248412 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6335 12:15:03.248504 ==
6336 12:15:03.251334 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 12:15:03.257908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 12:15:03.257989 ==
6339 12:15:03.258052 DQS Delay:
6340 12:15:03.261376 DQS0 = 59, DQS1 = 59
6341 12:15:03.261489 DQM Delay:
6342 12:15:03.261585 DQM0 = 18, DQM1 = 10
6343 12:15:03.264544 DQ Delay:
6344 12:15:03.268442 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6345 12:15:03.271432 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6346 12:15:03.271516 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6347 12:15:03.277656 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6348 12:15:03.277739
6349 12:15:03.277804
6350 12:15:03.277864 ==
6351 12:15:03.281414 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 12:15:03.284547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 12:15:03.284636 ==
6354 12:15:03.284703
6355 12:15:03.284764
6356 12:15:03.287778 TX Vref Scan disable
6357 12:15:03.287891 == TX Byte 0 ==
6358 12:15:03.294675 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 12:15:03.297646 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 12:15:03.297765 == TX Byte 1 ==
6361 12:15:03.300775 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6362 12:15:03.307239 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6363 12:15:03.307316 ==
6364 12:15:03.310889 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 12:15:03.313967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 12:15:03.314039 ==
6367 12:15:03.314099
6368 12:15:03.314158
6369 12:15:03.317569 TX Vref Scan disable
6370 12:15:03.317674 == TX Byte 0 ==
6371 12:15:03.323906 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 12:15:03.327353 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 12:15:03.327463 == TX Byte 1 ==
6374 12:15:03.334023 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 12:15:03.337218 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 12:15:03.337342
6377 12:15:03.337440 [DATLAT]
6378 12:15:03.340370 Freq=400, CH0 RK0
6379 12:15:03.340506
6380 12:15:03.340600 DATLAT Default: 0xf
6381 12:15:03.343953 0, 0xFFFF, sum = 0
6382 12:15:03.344067 1, 0xFFFF, sum = 0
6383 12:15:03.346968 2, 0xFFFF, sum = 0
6384 12:15:03.347079 3, 0xFFFF, sum = 0
6385 12:15:03.350265 4, 0xFFFF, sum = 0
6386 12:15:03.350379 5, 0xFFFF, sum = 0
6387 12:15:03.353745 6, 0xFFFF, sum = 0
6388 12:15:03.353869 7, 0xFFFF, sum = 0
6389 12:15:03.356765 8, 0xFFFF, sum = 0
6390 12:15:03.356880 9, 0xFFFF, sum = 0
6391 12:15:03.360336 10, 0xFFFF, sum = 0
6392 12:15:03.363378 11, 0xFFFF, sum = 0
6393 12:15:03.363488 12, 0xFFFF, sum = 0
6394 12:15:03.366846 13, 0x0, sum = 1
6395 12:15:03.366961 14, 0x0, sum = 2
6396 12:15:03.369998 15, 0x0, sum = 3
6397 12:15:03.370109 16, 0x0, sum = 4
6398 12:15:03.370208 best_step = 14
6399 12:15:03.373224
6400 12:15:03.373337 ==
6401 12:15:03.377229 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 12:15:03.380295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 12:15:03.380407 ==
6404 12:15:03.380506 RX Vref Scan: 1
6405 12:15:03.380601
6406 12:15:03.383277 RX Vref 0 -> 0, step: 1
6407 12:15:03.383384
6408 12:15:03.386593 RX Delay -359 -> 252, step: 8
6409 12:15:03.386704
6410 12:15:03.389751 Set Vref, RX VrefLevel [Byte0]: 62
6411 12:15:03.392991 [Byte1]: 53
6412 12:15:03.397379
6413 12:15:03.397488 Final RX Vref Byte 0 = 62 to rank0
6414 12:15:03.400658 Final RX Vref Byte 1 = 53 to rank0
6415 12:15:03.403778 Final RX Vref Byte 0 = 62 to rank1
6416 12:15:03.407027 Final RX Vref Byte 1 = 53 to rank1==
6417 12:15:03.410106 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 12:15:03.417047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 12:15:03.417158 ==
6420 12:15:03.417252 DQS Delay:
6421 12:15:03.420087 DQS0 = 60, DQS1 = 68
6422 12:15:03.420194 DQM Delay:
6423 12:15:03.423779 DQM0 = 16, DQM1 = 13
6424 12:15:03.423890 DQ Delay:
6425 12:15:03.426864 DQ0 =16, DQ1 =20, DQ2 =16, DQ3 =16
6426 12:15:03.430238 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6427 12:15:03.433671 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6428 12:15:03.436616 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6429 12:15:03.436728
6430 12:15:03.436822
6431 12:15:03.443092 [DQSOSCAuto] RK0, (LSB)MR18= 0x8584, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6432 12:15:03.446811 CH0 RK0: MR19=C0C, MR18=8584
6433 12:15:03.452868 CH0_RK0: MR19=0xC0C, MR18=0x8584, DQSOSC=393, MR23=63, INC=382, DEC=254
6434 12:15:03.452990 ==
6435 12:15:03.456072 Dram Type= 6, Freq= 0, CH_0, rank 1
6436 12:15:03.459877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 12:15:03.459990 ==
6438 12:15:03.462921 [Gating] SW mode calibration
6439 12:15:03.469744 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6440 12:15:03.475983 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6441 12:15:03.479119 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6442 12:15:03.486056 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 12:15:03.489164 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 12:15:03.492468 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 12:15:03.499288 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 12:15:03.502398 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 12:15:03.505575 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 12:15:03.511942 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 12:15:03.515705 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 12:15:03.519083 Total UI for P1: 0, mck2ui 16
6451 12:15:03.522108 best dqsien dly found for B0: ( 0, 14, 24)
6452 12:15:03.525218 Total UI for P1: 0, mck2ui 16
6453 12:15:03.528777 best dqsien dly found for B1: ( 0, 14, 24)
6454 12:15:03.531723 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6455 12:15:03.535350 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6456 12:15:03.535465
6457 12:15:03.538463 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6458 12:15:03.541632 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6459 12:15:03.544798 [Gating] SW calibration Done
6460 12:15:03.544914 ==
6461 12:15:03.548066 Dram Type= 6, Freq= 0, CH_0, rank 1
6462 12:15:03.554707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 12:15:03.554821 ==
6464 12:15:03.554916 RX Vref Scan: 0
6465 12:15:03.555013
6466 12:15:03.558069 RX Vref 0 -> 0, step: 1
6467 12:15:03.558177
6468 12:15:03.561627 RX Delay -410 -> 252, step: 16
6469 12:15:03.564717 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6470 12:15:03.567822 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6471 12:15:03.574316 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6472 12:15:03.577904 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6473 12:15:03.580963 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6474 12:15:03.584775 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6475 12:15:03.590960 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6476 12:15:03.594798 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6477 12:15:03.597819 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6478 12:15:03.601136 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6479 12:15:03.607357 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6480 12:15:03.610538 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6481 12:15:03.614382 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6482 12:15:03.617443 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6483 12:15:03.623861 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6484 12:15:03.627074 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6485 12:15:03.627159 ==
6486 12:15:03.630749 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 12:15:03.633873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 12:15:03.633984 ==
6489 12:15:03.637524 DQS Delay:
6490 12:15:03.637638 DQS0 = 59, DQS1 = 59
6491 12:15:03.640889 DQM Delay:
6492 12:15:03.641006 DQM0 = 16, DQM1 = 10
6493 12:15:03.641119 DQ Delay:
6494 12:15:03.643797 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6495 12:15:03.647396 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6496 12:15:03.650543 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6497 12:15:03.653728 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6498 12:15:03.653811
6499 12:15:03.653877
6500 12:15:03.653955 ==
6501 12:15:03.656924 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 12:15:03.663758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 12:15:03.663881 ==
6504 12:15:03.663981
6505 12:15:03.664074
6506 12:15:03.667125 TX Vref Scan disable
6507 12:15:03.667230 == TX Byte 0 ==
6508 12:15:03.670032 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6509 12:15:03.676599 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6510 12:15:03.676718 == TX Byte 1 ==
6511 12:15:03.680066 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6512 12:15:03.683541 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6513 12:15:03.686680 ==
6514 12:15:03.689954 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 12:15:03.693068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 12:15:03.693187 ==
6517 12:15:03.693283
6518 12:15:03.693376
6519 12:15:03.696281 TX Vref Scan disable
6520 12:15:03.696393 == TX Byte 0 ==
6521 12:15:03.700030 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6522 12:15:03.706220 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6523 12:15:03.706339 == TX Byte 1 ==
6524 12:15:03.710002 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6525 12:15:03.716293 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6526 12:15:03.716388
6527 12:15:03.716454 [DATLAT]
6528 12:15:03.716516 Freq=400, CH0 RK1
6529 12:15:03.716576
6530 12:15:03.719592 DATLAT Default: 0xe
6531 12:15:03.722776 0, 0xFFFF, sum = 0
6532 12:15:03.722886 1, 0xFFFF, sum = 0
6533 12:15:03.725879 2, 0xFFFF, sum = 0
6534 12:15:03.725991 3, 0xFFFF, sum = 0
6535 12:15:03.729716 4, 0xFFFF, sum = 0
6536 12:15:03.729829 5, 0xFFFF, sum = 0
6537 12:15:03.732763 6, 0xFFFF, sum = 0
6538 12:15:03.732874 7, 0xFFFF, sum = 0
6539 12:15:03.735819 8, 0xFFFF, sum = 0
6540 12:15:03.735928 9, 0xFFFF, sum = 0
6541 12:15:03.739438 10, 0xFFFF, sum = 0
6542 12:15:03.739561 11, 0xFFFF, sum = 0
6543 12:15:03.742514 12, 0xFFFF, sum = 0
6544 12:15:03.742635 13, 0x0, sum = 1
6545 12:15:03.745628 14, 0x0, sum = 2
6546 12:15:03.745740 15, 0x0, sum = 3
6547 12:15:03.748837 16, 0x0, sum = 4
6548 12:15:03.748959 best_step = 14
6549 12:15:03.749062
6550 12:15:03.749174 ==
6551 12:15:03.752350 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 12:15:03.759077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 12:15:03.759176 ==
6554 12:15:03.759246 RX Vref Scan: 0
6555 12:15:03.759330
6556 12:15:03.762171 RX Vref 0 -> 0, step: 1
6557 12:15:03.762280
6558 12:15:03.765341 RX Delay -359 -> 252, step: 8
6559 12:15:03.772975 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6560 12:15:03.775169 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6561 12:15:03.778805 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6562 12:15:03.785407 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6563 12:15:03.788731 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6564 12:15:03.791874 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6565 12:15:03.795037 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6566 12:15:03.801740 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6567 12:15:03.804991 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6568 12:15:03.808290 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6569 12:15:03.811278 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6570 12:15:03.818144 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6571 12:15:03.821717 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6572 12:15:03.824915 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6573 12:15:03.828006 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6574 12:15:03.834944 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6575 12:15:03.835064 ==
6576 12:15:03.838191 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 12:15:03.841430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 12:15:03.841537 ==
6579 12:15:03.841627 DQS Delay:
6580 12:15:03.844297 DQS0 = 60, DQS1 = 72
6581 12:15:03.844374 DQM Delay:
6582 12:15:03.848004 DQM0 = 11, DQM1 = 18
6583 12:15:03.848092 DQ Delay:
6584 12:15:03.851212 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6585 12:15:03.854274 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6586 12:15:03.858022 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6587 12:15:03.861032 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =24
6588 12:15:03.861116
6589 12:15:03.861181
6590 12:15:03.871071 [DQSOSCAuto] RK1, (LSB)MR18= 0xc87c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6591 12:15:03.871167 CH0 RK1: MR19=C0C, MR18=C87C
6592 12:15:03.877341 CH0_RK1: MR19=0xC0C, MR18=0xC87C, DQSOSC=385, MR23=63, INC=398, DEC=265
6593 12:15:03.880819 [RxdqsGatingPostProcess] freq 400
6594 12:15:03.887223 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6595 12:15:03.890891 best DQS0 dly(2T, 0.5T) = (0, 10)
6596 12:15:03.893833 best DQS1 dly(2T, 0.5T) = (0, 10)
6597 12:15:03.897339 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6598 12:15:03.900615 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6599 12:15:03.903548 best DQS0 dly(2T, 0.5T) = (0, 10)
6600 12:15:03.907113 best DQS1 dly(2T, 0.5T) = (0, 10)
6601 12:15:03.910514 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6602 12:15:03.913966 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6603 12:15:03.914079 Pre-setting of DQS Precalculation
6604 12:15:03.920127 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6605 12:15:03.920218 ==
6606 12:15:03.923333 Dram Type= 6, Freq= 0, CH_1, rank 0
6607 12:15:03.927278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 12:15:03.927389 ==
6609 12:15:03.933696 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6610 12:15:03.940299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6611 12:15:03.943481 [CA 0] Center 36 (8~64) winsize 57
6612 12:15:03.946618 [CA 1] Center 36 (8~64) winsize 57
6613 12:15:03.949848 [CA 2] Center 36 (8~64) winsize 57
6614 12:15:03.953032 [CA 3] Center 36 (8~64) winsize 57
6615 12:15:03.956750 [CA 4] Center 36 (8~64) winsize 57
6616 12:15:03.956837 [CA 5] Center 36 (8~64) winsize 57
6617 12:15:03.960042
6618 12:15:03.963216 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6619 12:15:03.963300
6620 12:15:03.966342 [CATrainingPosCal] consider 1 rank data
6621 12:15:03.970283 u2DelayCellTimex100 = 270/100 ps
6622 12:15:03.973110 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 12:15:03.976386 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 12:15:03.979491 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 12:15:03.982657 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 12:15:03.986319 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 12:15:03.989273 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 12:15:03.989361
6629 12:15:03.992424 CA PerBit enable=1, Macro0, CA PI delay=36
6630 12:15:03.996188
6631 12:15:03.996295 [CBTSetCACLKResult] CA Dly = 36
6632 12:15:03.999176 CS Dly: 1 (0~32)
6633 12:15:03.999279 ==
6634 12:15:04.002624 Dram Type= 6, Freq= 0, CH_1, rank 1
6635 12:15:04.005652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 12:15:04.005760 ==
6637 12:15:04.012226 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6638 12:15:04.019042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6639 12:15:04.022231 [CA 0] Center 36 (8~64) winsize 57
6640 12:15:04.025851 [CA 1] Center 36 (8~64) winsize 57
6641 12:15:04.029133 [CA 2] Center 36 (8~64) winsize 57
6642 12:15:04.029212 [CA 3] Center 36 (8~64) winsize 57
6643 12:15:04.032276 [CA 4] Center 36 (8~64) winsize 57
6644 12:15:04.035516 [CA 5] Center 36 (8~64) winsize 57
6645 12:15:04.035625
6646 12:15:04.042206 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6647 12:15:04.042314
6648 12:15:04.045375 [CATrainingPosCal] consider 2 rank data
6649 12:15:04.048571 u2DelayCellTimex100 = 270/100 ps
6650 12:15:04.051679 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 12:15:04.055694 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 12:15:04.058724 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 12:15:04.061862 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 12:15:04.064912 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 12:15:04.068849 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 12:15:04.068929
6657 12:15:04.071958 CA PerBit enable=1, Macro0, CA PI delay=36
6658 12:15:04.072042
6659 12:15:04.074950 [CBTSetCACLKResult] CA Dly = 36
6660 12:15:04.078387 CS Dly: 1 (0~32)
6661 12:15:04.078465
6662 12:15:04.081605 ----->DramcWriteLeveling(PI) begin...
6663 12:15:04.081691 ==
6664 12:15:04.084703 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 12:15:04.088426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 12:15:04.088512 ==
6667 12:15:04.091555 Write leveling (Byte 0): 40 => 8
6668 12:15:04.094894 Write leveling (Byte 1): 40 => 8
6669 12:15:04.097901 DramcWriteLeveling(PI) end<-----
6670 12:15:04.098013
6671 12:15:04.098100 ==
6672 12:15:04.101598 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 12:15:04.104556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 12:15:04.104662 ==
6675 12:15:04.108001 [Gating] SW mode calibration
6676 12:15:04.114364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6677 12:15:04.120752 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6678 12:15:04.124724 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6679 12:15:04.130730 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6680 12:15:04.134117 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6681 12:15:04.137741 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 12:15:04.144006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6683 12:15:04.147069 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 12:15:04.150932 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 12:15:04.157068 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 12:15:04.160345 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 12:15:04.163543 Total UI for P1: 0, mck2ui 16
6688 12:15:04.167291 best dqsien dly found for B0: ( 0, 14, 24)
6689 12:15:04.170557 Total UI for P1: 0, mck2ui 16
6690 12:15:04.173758 best dqsien dly found for B1: ( 0, 14, 24)
6691 12:15:04.176969 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6692 12:15:04.180119 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6693 12:15:04.180241
6694 12:15:04.183224 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6695 12:15:04.187070 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6696 12:15:04.190198 [Gating] SW calibration Done
6697 12:15:04.190310 ==
6698 12:15:04.193331 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 12:15:04.200332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 12:15:04.200458 ==
6701 12:15:04.200557 RX Vref Scan: 0
6702 12:15:04.200649
6703 12:15:04.203384 RX Vref 0 -> 0, step: 1
6704 12:15:04.203496
6705 12:15:04.206567 RX Delay -410 -> 252, step: 16
6706 12:15:04.209540 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6707 12:15:04.213241 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6708 12:15:04.219694 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6709 12:15:04.223046 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6710 12:15:04.226160 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6711 12:15:04.229338 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6712 12:15:04.236166 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6713 12:15:04.239257 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6714 12:15:04.242486 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6715 12:15:04.246031 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6716 12:15:04.252413 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6717 12:15:04.255579 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6718 12:15:04.259141 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6719 12:15:04.265414 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6720 12:15:04.269128 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6721 12:15:04.272397 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6722 12:15:04.272515 ==
6723 12:15:04.275628 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 12:15:04.278987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 12:15:04.282281 ==
6726 12:15:04.282393 DQS Delay:
6727 12:15:04.282486 DQS0 = 51, DQS1 = 59
6728 12:15:04.285312 DQM Delay:
6729 12:15:04.285420 DQM0 = 12, DQM1 = 11
6730 12:15:04.288851 DQ Delay:
6731 12:15:04.288961 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6732 12:15:04.291804 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6733 12:15:04.295542 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6734 12:15:04.298794 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6735 12:15:04.298916
6736 12:15:04.299012
6737 12:15:04.299105 ==
6738 12:15:04.301779 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 12:15:04.308808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 12:15:04.308928 ==
6741 12:15:04.309027
6742 12:15:04.309119
6743 12:15:04.311814 TX Vref Scan disable
6744 12:15:04.311922 == TX Byte 0 ==
6745 12:15:04.315518 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 12:15:04.321874 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 12:15:04.321995 == TX Byte 1 ==
6748 12:15:04.324819 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6749 12:15:04.331541 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6750 12:15:04.331665 ==
6751 12:15:04.335125 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 12:15:04.338496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 12:15:04.338613 ==
6754 12:15:04.338713
6755 12:15:04.338808
6756 12:15:04.341821 TX Vref Scan disable
6757 12:15:04.341930 == TX Byte 0 ==
6758 12:15:04.344873 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 12:15:04.350944 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 12:15:04.351057 == TX Byte 1 ==
6761 12:15:04.354643 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 12:15:04.361040 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 12:15:04.361157
6764 12:15:04.361253 [DATLAT]
6765 12:15:04.364111 Freq=400, CH1 RK0
6766 12:15:04.364219
6767 12:15:04.364313 DATLAT Default: 0xf
6768 12:15:04.367884 0, 0xFFFF, sum = 0
6769 12:15:04.367997 1, 0xFFFF, sum = 0
6770 12:15:04.371162 2, 0xFFFF, sum = 0
6771 12:15:04.371272 3, 0xFFFF, sum = 0
6772 12:15:04.374652 4, 0xFFFF, sum = 0
6773 12:15:04.374761 5, 0xFFFF, sum = 0
6774 12:15:04.377558 6, 0xFFFF, sum = 0
6775 12:15:04.377668 7, 0xFFFF, sum = 0
6776 12:15:04.380774 8, 0xFFFF, sum = 0
6777 12:15:04.380888 9, 0xFFFF, sum = 0
6778 12:15:04.384020 10, 0xFFFF, sum = 0
6779 12:15:04.384131 11, 0xFFFF, sum = 0
6780 12:15:04.387122 12, 0xFFFF, sum = 0
6781 12:15:04.390868 13, 0x0, sum = 1
6782 12:15:04.390982 14, 0x0, sum = 2
6783 12:15:04.391082 15, 0x0, sum = 3
6784 12:15:04.393986 16, 0x0, sum = 4
6785 12:15:04.394085 best_step = 14
6786 12:15:04.394151
6787 12:15:04.397533 ==
6788 12:15:04.397647 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 12:15:04.403821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 12:15:04.403909 ==
6791 12:15:04.403977 RX Vref Scan: 1
6792 12:15:04.404038
6793 12:15:04.406921 RX Vref 0 -> 0, step: 1
6794 12:15:04.406999
6795 12:15:04.410216 RX Delay -359 -> 252, step: 8
6796 12:15:04.410295
6797 12:15:04.413934 Set Vref, RX VrefLevel [Byte0]: 58
6798 12:15:04.417035 [Byte1]: 49
6799 12:15:04.420336
6800 12:15:04.420427 Final RX Vref Byte 0 = 58 to rank0
6801 12:15:04.423986 Final RX Vref Byte 1 = 49 to rank0
6802 12:15:04.427373 Final RX Vref Byte 0 = 58 to rank1
6803 12:15:04.430294 Final RX Vref Byte 1 = 49 to rank1==
6804 12:15:04.433873 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 12:15:04.440698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 12:15:04.440815 ==
6807 12:15:04.440911 DQS Delay:
6808 12:15:04.444136 DQS0 = 56, DQS1 = 68
6809 12:15:04.444221 DQM Delay:
6810 12:15:04.444288 DQM0 = 13, DQM1 = 14
6811 12:15:04.447182 DQ Delay:
6812 12:15:04.450287 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6813 12:15:04.450399 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6814 12:15:04.453718 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6815 12:15:04.456764 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6816 12:15:04.459944
6817 12:15:04.460056
6818 12:15:04.466842 [DQSOSCAuto] RK0, (LSB)MR18= 0x5165, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 399 ps
6819 12:15:04.470018 CH1 RK0: MR19=C0C, MR18=5165
6820 12:15:04.476693 CH1_RK0: MR19=0xC0C, MR18=0x5165, DQSOSC=397, MR23=63, INC=374, DEC=249
6821 12:15:04.476820 ==
6822 12:15:04.479975 Dram Type= 6, Freq= 0, CH_1, rank 1
6823 12:15:04.483286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 12:15:04.483402 ==
6825 12:15:04.486707 [Gating] SW mode calibration
6826 12:15:04.493080 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6827 12:15:04.499881 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6828 12:15:04.502896 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6829 12:15:04.505999 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6830 12:15:04.513102 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6831 12:15:04.516356 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 12:15:04.519576 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6833 12:15:04.526284 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 12:15:04.528999 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 12:15:04.532769 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 12:15:04.538950 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 12:15:04.542716 Total UI for P1: 0, mck2ui 16
6838 12:15:04.545880 best dqsien dly found for B0: ( 0, 14, 24)
6839 12:15:04.549136 Total UI for P1: 0, mck2ui 16
6840 12:15:04.552196 best dqsien dly found for B1: ( 0, 14, 24)
6841 12:15:04.555723 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6842 12:15:04.558655 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6843 12:15:04.558772
6844 12:15:04.562407 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6845 12:15:04.565511 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6846 12:15:04.568840 [Gating] SW calibration Done
6847 12:15:04.568950 ==
6848 12:15:04.572062 Dram Type= 6, Freq= 0, CH_1, rank 1
6849 12:15:04.575327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 12:15:04.575438 ==
6851 12:15:04.578604 RX Vref Scan: 0
6852 12:15:04.578716
6853 12:15:04.582156 RX Vref 0 -> 0, step: 1
6854 12:15:04.582270
6855 12:15:04.582369 RX Delay -410 -> 252, step: 16
6856 12:15:04.588543 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6857 12:15:04.592297 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6858 12:15:04.595426 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6859 12:15:04.601776 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6860 12:15:04.604923 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6861 12:15:04.608232 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6862 12:15:04.611843 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6863 12:15:04.618093 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6864 12:15:04.622091 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6865 12:15:04.625116 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6866 12:15:04.628171 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6867 12:15:04.634967 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6868 12:15:04.638725 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6869 12:15:04.641641 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6870 12:15:04.644644 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6871 12:15:04.651359 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6872 12:15:04.651481 ==
6873 12:15:04.654393 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 12:15:04.657799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 12:15:04.657888 ==
6876 12:15:04.661123 DQS Delay:
6877 12:15:04.661206 DQS0 = 59, DQS1 = 59
6878 12:15:04.661272 DQM Delay:
6879 12:15:04.664696 DQM0 = 19, DQM1 = 13
6880 12:15:04.664780 DQ Delay:
6881 12:15:04.667855 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6882 12:15:04.671344 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6883 12:15:04.674279 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6884 12:15:04.677546 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6885 12:15:04.677632
6886 12:15:04.677717
6887 12:15:04.677795 ==
6888 12:15:04.680873 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 12:15:04.687646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 12:15:04.687733 ==
6891 12:15:04.687819
6892 12:15:04.687898
6893 12:15:04.687976 TX Vref Scan disable
6894 12:15:04.690967 == TX Byte 0 ==
6895 12:15:04.693986 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6896 12:15:04.697154 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6897 12:15:04.700386 == TX Byte 1 ==
6898 12:15:04.704308 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6899 12:15:04.707570 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6900 12:15:04.707655 ==
6901 12:15:04.710714 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 12:15:04.716970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 12:15:04.717057 ==
6904 12:15:04.717141
6905 12:15:04.717220
6906 12:15:04.717325 TX Vref Scan disable
6907 12:15:04.720602 == TX Byte 0 ==
6908 12:15:04.724010 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6909 12:15:04.727010 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6910 12:15:04.730158 == TX Byte 1 ==
6911 12:15:04.733321 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6912 12:15:04.736959 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6913 12:15:04.740078
6914 12:15:04.740163 [DATLAT]
6915 12:15:04.740247 Freq=400, CH1 RK1
6916 12:15:04.740328
6917 12:15:04.743169 DATLAT Default: 0xe
6918 12:15:04.743270 0, 0xFFFF, sum = 0
6919 12:15:04.746700 1, 0xFFFF, sum = 0
6920 12:15:04.746812 2, 0xFFFF, sum = 0
6921 12:15:04.750292 3, 0xFFFF, sum = 0
6922 12:15:04.750378 4, 0xFFFF, sum = 0
6923 12:15:04.753213 5, 0xFFFF, sum = 0
6924 12:15:04.753299 6, 0xFFFF, sum = 0
6925 12:15:04.756951 7, 0xFFFF, sum = 0
6926 12:15:04.760185 8, 0xFFFF, sum = 0
6927 12:15:04.760272 9, 0xFFFF, sum = 0
6928 12:15:04.763237 10, 0xFFFF, sum = 0
6929 12:15:04.763324 11, 0xFFFF, sum = 0
6930 12:15:04.766360 12, 0xFFFF, sum = 0
6931 12:15:04.766446 13, 0x0, sum = 1
6932 12:15:04.769938 14, 0x0, sum = 2
6933 12:15:04.770023 15, 0x0, sum = 3
6934 12:15:04.773172 16, 0x0, sum = 4
6935 12:15:04.773257 best_step = 14
6936 12:15:04.773323
6937 12:15:04.773384 ==
6938 12:15:04.776402 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 12:15:04.779414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 12:15:04.779502 ==
6941 12:15:04.783534 RX Vref Scan: 0
6942 12:15:04.783616
6943 12:15:04.786362 RX Vref 0 -> 0, step: 1
6944 12:15:04.786444
6945 12:15:04.789576 RX Delay -359 -> 252, step: 8
6946 12:15:04.796313 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6947 12:15:04.799875 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6948 12:15:04.802902 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6949 12:15:04.806085 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6950 12:15:04.812723 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6951 12:15:04.815714 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6952 12:15:04.818756 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6953 12:15:04.822523 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6954 12:15:04.828732 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6955 12:15:04.832563 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6956 12:15:04.835683 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6957 12:15:04.838751 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6958 12:15:04.845436 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6959 12:15:04.849124 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6960 12:15:04.852464 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6961 12:15:04.858808 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6962 12:15:04.858906 ==
6963 12:15:04.861871 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 12:15:04.865510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 12:15:04.865595 ==
6966 12:15:04.865661 DQS Delay:
6967 12:15:04.868260 DQS0 = 60, DQS1 = 64
6968 12:15:04.868342 DQM Delay:
6969 12:15:04.871874 DQM0 = 13, DQM1 = 10
6970 12:15:04.871956 DQ Delay:
6971 12:15:04.875119 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6972 12:15:04.878438 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6973 12:15:04.881614 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6974 12:15:04.884808 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6975 12:15:04.884913
6976 12:15:04.885005
6977 12:15:04.891832 [DQSOSCAuto] RK1, (LSB)MR18= 0x71a2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6978 12:15:04.894970 CH1 RK1: MR19=C0C, MR18=71A2
6979 12:15:04.901642 CH1_RK1: MR19=0xC0C, MR18=0x71A2, DQSOSC=389, MR23=63, INC=390, DEC=260
6980 12:15:04.905205 [RxdqsGatingPostProcess] freq 400
6981 12:15:04.911458 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6982 12:15:04.914745 best DQS0 dly(2T, 0.5T) = (0, 10)
6983 12:15:04.914822 best DQS1 dly(2T, 0.5T) = (0, 10)
6984 12:15:04.917797 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6985 12:15:04.921637 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6986 12:15:04.924713 best DQS0 dly(2T, 0.5T) = (0, 10)
6987 12:15:04.927809 best DQS1 dly(2T, 0.5T) = (0, 10)
6988 12:15:04.931426 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6989 12:15:04.934804 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6990 12:15:04.937852 Pre-setting of DQS Precalculation
6991 12:15:04.944511 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6992 12:15:04.950725 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6993 12:15:04.957353 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6994 12:15:04.957444
6995 12:15:04.957531
6996 12:15:04.960975 [Calibration Summary] 800 Mbps
6997 12:15:04.961054 CH 0, Rank 0
6998 12:15:04.963999 SW Impedance : PASS
6999 12:15:04.967586 DUTY Scan : NO K
7000 12:15:04.967664 ZQ Calibration : PASS
7001 12:15:04.970714 Jitter Meter : NO K
7002 12:15:04.973590 CBT Training : PASS
7003 12:15:04.973701 Write leveling : PASS
7004 12:15:04.977347 RX DQS gating : PASS
7005 12:15:04.980674 RX DQ/DQS(RDDQC) : PASS
7006 12:15:04.980758 TX DQ/DQS : PASS
7007 12:15:04.983976 RX DATLAT : PASS
7008 12:15:04.987142 RX DQ/DQS(Engine): PASS
7009 12:15:04.987225 TX OE : NO K
7010 12:15:04.990311 All Pass.
7011 12:15:04.990394
7012 12:15:04.990459 CH 0, Rank 1
7013 12:15:04.993611 SW Impedance : PASS
7014 12:15:04.993693 DUTY Scan : NO K
7015 12:15:04.996782 ZQ Calibration : PASS
7016 12:15:05.000557 Jitter Meter : NO K
7017 12:15:05.000663 CBT Training : PASS
7018 12:15:05.004038 Write leveling : NO K
7019 12:15:05.006805 RX DQS gating : PASS
7020 12:15:05.006920 RX DQ/DQS(RDDQC) : PASS
7021 12:15:05.010127 TX DQ/DQS : PASS
7022 12:15:05.013315 RX DATLAT : PASS
7023 12:15:05.013403 RX DQ/DQS(Engine): PASS
7024 12:15:05.016933 TX OE : NO K
7025 12:15:05.017019 All Pass.
7026 12:15:05.017104
7027 12:15:05.020170 CH 1, Rank 0
7028 12:15:05.020255 SW Impedance : PASS
7029 12:15:05.023147 DUTY Scan : NO K
7030 12:15:05.023233 ZQ Calibration : PASS
7031 12:15:05.026910 Jitter Meter : NO K
7032 12:15:05.029527 CBT Training : PASS
7033 12:15:05.032696 Write leveling : PASS
7034 12:15:05.032778 RX DQS gating : PASS
7035 12:15:05.036212 RX DQ/DQS(RDDQC) : PASS
7036 12:15:05.036296 TX DQ/DQS : PASS
7037 12:15:05.039345 RX DATLAT : PASS
7038 12:15:05.042962 RX DQ/DQS(Engine): PASS
7039 12:15:05.043063 TX OE : NO K
7040 12:15:05.045988 All Pass.
7041 12:15:05.046075
7042 12:15:05.046140 CH 1, Rank 1
7043 12:15:05.049140 SW Impedance : PASS
7044 12:15:05.049226 DUTY Scan : NO K
7045 12:15:05.052955 ZQ Calibration : PASS
7046 12:15:05.056092 Jitter Meter : NO K
7047 12:15:05.056175 CBT Training : PASS
7048 12:15:05.059338 Write leveling : NO K
7049 12:15:05.062655 RX DQS gating : PASS
7050 12:15:05.062764 RX DQ/DQS(RDDQC) : PASS
7051 12:15:05.065523 TX DQ/DQS : PASS
7052 12:15:05.069188 RX DATLAT : PASS
7053 12:15:05.069297 RX DQ/DQS(Engine): PASS
7054 12:15:05.072115 TX OE : NO K
7055 12:15:05.072199 All Pass.
7056 12:15:05.072264
7057 12:15:05.075536 DramC Write-DBI off
7058 12:15:05.078821 PER_BANK_REFRESH: Hybrid Mode
7059 12:15:05.078913 TX_TRACKING: ON
7060 12:15:05.088751 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7061 12:15:05.092113 [FAST_K] Save calibration result to emmc
7062 12:15:05.095460 dramc_set_vcore_voltage set vcore to 725000
7063 12:15:05.098610 Read voltage for 1600, 0
7064 12:15:05.098725 Vio18 = 0
7065 12:15:05.101879 Vcore = 725000
7066 12:15:05.101991 Vdram = 0
7067 12:15:05.102087 Vddq = 0
7068 12:15:05.102179 Vmddr = 0
7069 12:15:05.108863 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7070 12:15:05.115060 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7071 12:15:05.115166 MEM_TYPE=3, freq_sel=13
7072 12:15:05.118429 sv_algorithm_assistance_LP4_3733
7073 12:15:05.121607 ============ PULL DRAM RESETB DOWN ============
7074 12:15:05.128491 ========== PULL DRAM RESETB DOWN end =========
7075 12:15:05.131673 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7076 12:15:05.134750 ===================================
7077 12:15:05.138179 LPDDR4 DRAM CONFIGURATION
7078 12:15:05.141703 ===================================
7079 12:15:05.141785 EX_ROW_EN[0] = 0x0
7080 12:15:05.144643 EX_ROW_EN[1] = 0x0
7081 12:15:05.144745 LP4Y_EN = 0x0
7082 12:15:05.147937 WORK_FSP = 0x1
7083 12:15:05.151735 WL = 0x5
7084 12:15:05.151812 RL = 0x5
7085 12:15:05.154733 BL = 0x2
7086 12:15:05.154808 RPST = 0x0
7087 12:15:05.157770 RD_PRE = 0x0
7088 12:15:05.157873 WR_PRE = 0x1
7089 12:15:05.161546 WR_PST = 0x1
7090 12:15:05.161649 DBI_WR = 0x0
7091 12:15:05.164696 DBI_RD = 0x0
7092 12:15:05.164769 OTF = 0x1
7093 12:15:05.167710 ===================================
7094 12:15:05.171323 ===================================
7095 12:15:05.174368 ANA top config
7096 12:15:05.177809 ===================================
7097 12:15:05.177916 DLL_ASYNC_EN = 0
7098 12:15:05.180666 ALL_SLAVE_EN = 0
7099 12:15:05.184205 NEW_RANK_MODE = 1
7100 12:15:05.187955 DLL_IDLE_MODE = 1
7101 12:15:05.190790 LP45_APHY_COMB_EN = 1
7102 12:15:05.190901 TX_ODT_DIS = 0
7103 12:15:05.193868 NEW_8X_MODE = 1
7104 12:15:05.197682 ===================================
7105 12:15:05.200822 ===================================
7106 12:15:05.204151 data_rate = 3200
7107 12:15:05.207115 CKR = 1
7108 12:15:05.210244 DQ_P2S_RATIO = 8
7109 12:15:05.213966 ===================================
7110 12:15:05.217306 CA_P2S_RATIO = 8
7111 12:15:05.217415 DQ_CA_OPEN = 0
7112 12:15:05.220268 DQ_SEMI_OPEN = 0
7113 12:15:05.223401 CA_SEMI_OPEN = 0
7114 12:15:05.226766 CA_FULL_RATE = 0
7115 12:15:05.230435 DQ_CKDIV4_EN = 0
7116 12:15:05.233672 CA_CKDIV4_EN = 0
7117 12:15:05.233777 CA_PREDIV_EN = 0
7118 12:15:05.236788 PH8_DLY = 12
7119 12:15:05.240213 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7120 12:15:05.243249 DQ_AAMCK_DIV = 4
7121 12:15:05.246807 CA_AAMCK_DIV = 4
7122 12:15:05.249753 CA_ADMCK_DIV = 4
7123 12:15:05.253278 DQ_TRACK_CA_EN = 0
7124 12:15:05.253365 CA_PICK = 1600
7125 12:15:05.256321 CA_MCKIO = 1600
7126 12:15:05.259541 MCKIO_SEMI = 0
7127 12:15:05.263166 PLL_FREQ = 3068
7128 12:15:05.266313 DQ_UI_PI_RATIO = 32
7129 12:15:05.269944 CA_UI_PI_RATIO = 0
7130 12:15:05.273163 ===================================
7131 12:15:05.276483 ===================================
7132 12:15:05.279550 memory_type:LPDDR4
7133 12:15:05.279631 GP_NUM : 10
7134 12:15:05.282747 SRAM_EN : 1
7135 12:15:05.282853 MD32_EN : 0
7136 12:15:05.285748 ===================================
7137 12:15:05.289317 [ANA_INIT] >>>>>>>>>>>>>>
7138 12:15:05.292860 <<<<<< [CONFIGURE PHASE]: ANA_TX
7139 12:15:05.295927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7140 12:15:05.299268 ===================================
7141 12:15:05.302843 data_rate = 3200,PCW = 0X7600
7142 12:15:05.306065 ===================================
7143 12:15:05.309111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7144 12:15:05.316062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7145 12:15:05.319297 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7146 12:15:05.326212 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7147 12:15:05.329264 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7148 12:15:05.332314 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7149 12:15:05.332428 [ANA_INIT] flow start
7150 12:15:05.336239 [ANA_INIT] PLL >>>>>>>>
7151 12:15:05.339486 [ANA_INIT] PLL <<<<<<<<
7152 12:15:05.339599 [ANA_INIT] MIDPI >>>>>>>>
7153 12:15:05.342672 [ANA_INIT] MIDPI <<<<<<<<
7154 12:15:05.345620 [ANA_INIT] DLL >>>>>>>>
7155 12:15:05.345729 [ANA_INIT] DLL <<<<<<<<
7156 12:15:05.348927 [ANA_INIT] flow end
7157 12:15:05.352537 ============ LP4 DIFF to SE enter ============
7158 12:15:05.359406 ============ LP4 DIFF to SE exit ============
7159 12:15:05.359521 [ANA_INIT] <<<<<<<<<<<<<
7160 12:15:05.362419 [Flow] Enable top DCM control >>>>>
7161 12:15:05.365574 [Flow] Enable top DCM control <<<<<
7162 12:15:05.368698 Enable DLL master slave shuffle
7163 12:15:05.375428 ==============================================================
7164 12:15:05.375515 Gating Mode config
7165 12:15:05.381663 ==============================================================
7166 12:15:05.385297 Config description:
7167 12:15:05.394792 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7168 12:15:05.401482 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7169 12:15:05.405143 SELPH_MODE 0: By rank 1: By Phase
7170 12:15:05.411638 ==============================================================
7171 12:15:05.415118 GAT_TRACK_EN = 1
7172 12:15:05.415208 RX_GATING_MODE = 2
7173 12:15:05.418135 RX_GATING_TRACK_MODE = 2
7174 12:15:05.421843 SELPH_MODE = 1
7175 12:15:05.425059 PICG_EARLY_EN = 1
7176 12:15:05.428184 VALID_LAT_VALUE = 1
7177 12:15:05.434669 ==============================================================
7178 12:15:05.437925 Enter into Gating configuration >>>>
7179 12:15:05.441744 Exit from Gating configuration <<<<
7180 12:15:05.444967 Enter into DVFS_PRE_config >>>>>
7181 12:15:05.454683 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7182 12:15:05.457810 Exit from DVFS_PRE_config <<<<<
7183 12:15:05.461398 Enter into PICG configuration >>>>
7184 12:15:05.464424 Exit from PICG configuration <<<<
7185 12:15:05.468024 [RX_INPUT] configuration >>>>>
7186 12:15:05.471170 [RX_INPUT] configuration <<<<<
7187 12:15:05.474721 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7188 12:15:05.480934 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7189 12:15:05.487996 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7190 12:15:05.494511 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7191 12:15:05.497422 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7192 12:15:05.504140 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7193 12:15:05.510630 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7194 12:15:05.514133 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7195 12:15:05.517115 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7196 12:15:05.520885 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7197 12:15:05.524131 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7198 12:15:05.530351 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7199 12:15:05.534211 ===================================
7200 12:15:05.537314 LPDDR4 DRAM CONFIGURATION
7201 12:15:05.540698 ===================================
7202 12:15:05.540822 EX_ROW_EN[0] = 0x0
7203 12:15:05.543622 EX_ROW_EN[1] = 0x0
7204 12:15:05.543731 LP4Y_EN = 0x0
7205 12:15:05.546867 WORK_FSP = 0x1
7206 12:15:05.546978 WL = 0x5
7207 12:15:05.550614 RL = 0x5
7208 12:15:05.550724 BL = 0x2
7209 12:15:05.553817 RPST = 0x0
7210 12:15:05.553928 RD_PRE = 0x0
7211 12:15:05.556896 WR_PRE = 0x1
7212 12:15:05.557007 WR_PST = 0x1
7213 12:15:05.560012 DBI_WR = 0x0
7214 12:15:05.563706 DBI_RD = 0x0
7215 12:15:05.563823 OTF = 0x1
7216 12:15:05.566761 ===================================
7217 12:15:05.570361 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7218 12:15:05.573382 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7219 12:15:05.580015 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7220 12:15:05.583063 ===================================
7221 12:15:05.586157 LPDDR4 DRAM CONFIGURATION
7222 12:15:05.589976 ===================================
7223 12:15:05.590088 EX_ROW_EN[0] = 0x10
7224 12:15:05.593220 EX_ROW_EN[1] = 0x0
7225 12:15:05.593347 LP4Y_EN = 0x0
7226 12:15:05.596307 WORK_FSP = 0x1
7227 12:15:05.596440 WL = 0x5
7228 12:15:05.600058 RL = 0x5
7229 12:15:05.600173 BL = 0x2
7230 12:15:05.602853 RPST = 0x0
7231 12:15:05.602964 RD_PRE = 0x0
7232 12:15:05.606354 WR_PRE = 0x1
7233 12:15:05.609389 WR_PST = 0x1
7234 12:15:05.609499 DBI_WR = 0x0
7235 12:15:05.613149 DBI_RD = 0x0
7236 12:15:05.613258 OTF = 0x1
7237 12:15:05.615879 ===================================
7238 12:15:05.622782 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7239 12:15:05.622908 ==
7240 12:15:05.626400 Dram Type= 6, Freq= 0, CH_0, rank 0
7241 12:15:05.629336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7242 12:15:05.629449 ==
7243 12:15:05.632471 [Duty_Offset_Calibration]
7244 12:15:05.635849 B0:2 B1:0 CA:3
7245 12:15:05.635957
7246 12:15:05.639305 [DutyScan_Calibration_Flow] k_type=0
7247 12:15:05.647708
7248 12:15:05.647827 ==CLK 0==
7249 12:15:05.650968 Final CLK duty delay cell = 0
7250 12:15:05.654134 [0] MAX Duty = 5031%(X100), DQS PI = 12
7251 12:15:05.657328 [0] MIN Duty = 4875%(X100), DQS PI = 54
7252 12:15:05.660499 [0] AVG Duty = 4953%(X100)
7253 12:15:05.660612
7254 12:15:05.663696 CH0 CLK Duty spec in!! Max-Min= 156%
7255 12:15:05.667644 [DutyScan_Calibration_Flow] ====Done====
7256 12:15:05.667726
7257 12:15:05.670287 [DutyScan_Calibration_Flow] k_type=1
7258 12:15:05.687113
7259 12:15:05.687220 ==DQS 0 ==
7260 12:15:05.690139 Final DQS duty delay cell = 0
7261 12:15:05.693293 [0] MAX Duty = 5094%(X100), DQS PI = 14
7262 12:15:05.696939 [0] MIN Duty = 4906%(X100), DQS PI = 46
7263 12:15:05.699918 [0] AVG Duty = 5000%(X100)
7264 12:15:05.700002
7265 12:15:05.700067 ==DQS 1 ==
7266 12:15:05.703274 Final DQS duty delay cell = -4
7267 12:15:05.706896 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7268 12:15:05.709868 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7269 12:15:05.713376 [-4] AVG Duty = 4906%(X100)
7270 12:15:05.713479
7271 12:15:05.716357 CH0 DQS 0 Duty spec in!! Max-Min= 188%
7272 12:15:05.716456
7273 12:15:05.719997 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7274 12:15:05.723186 [DutyScan_Calibration_Flow] ====Done====
7275 12:15:05.723272
7276 12:15:05.726721 [DutyScan_Calibration_Flow] k_type=3
7277 12:15:05.745146
7278 12:15:05.745258 ==DQM 0 ==
7279 12:15:05.748247 Final DQM duty delay cell = 0
7280 12:15:05.752045 [0] MAX Duty = 5156%(X100), DQS PI = 30
7281 12:15:05.755247 [0] MIN Duty = 4875%(X100), DQS PI = 0
7282 12:15:05.758230 [0] AVG Duty = 5015%(X100)
7283 12:15:05.758341
7284 12:15:05.758433 ==DQM 1 ==
7285 12:15:05.761438 Final DQM duty delay cell = 4
7286 12:15:05.764590 [4] MAX Duty = 5187%(X100), DQS PI = 60
7287 12:15:05.768396 [4] MIN Duty = 5031%(X100), DQS PI = 12
7288 12:15:05.771618 [4] AVG Duty = 5109%(X100)
7289 12:15:05.771703
7290 12:15:05.774788 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7291 12:15:05.774881
7292 12:15:05.778104 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7293 12:15:05.781689 [DutyScan_Calibration_Flow] ====Done====
7294 12:15:05.781774
7295 12:15:05.784618 [DutyScan_Calibration_Flow] k_type=2
7296 12:15:05.801600
7297 12:15:05.801733 ==DQ 0 ==
7298 12:15:05.804833 Final DQ duty delay cell = -4
7299 12:15:05.807821 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7300 12:15:05.811468 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7301 12:15:05.814466 [-4] AVG Duty = 4938%(X100)
7302 12:15:05.814589
7303 12:15:05.814682 ==DQ 1 ==
7304 12:15:05.818018 Final DQ duty delay cell = 0
7305 12:15:05.821150 [0] MAX Duty = 5156%(X100), DQS PI = 60
7306 12:15:05.824612 [0] MIN Duty = 5000%(X100), DQS PI = 16
7307 12:15:05.827638 [0] AVG Duty = 5078%(X100)
7308 12:15:05.827718
7309 12:15:05.830802 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7310 12:15:05.830906
7311 12:15:05.834314 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7312 12:15:05.837387 [DutyScan_Calibration_Flow] ====Done====
7313 12:15:05.837464 ==
7314 12:15:05.841122 Dram Type= 6, Freq= 0, CH_1, rank 0
7315 12:15:05.843953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7316 12:15:05.844041 ==
7317 12:15:05.847668 [Duty_Offset_Calibration]
7318 12:15:05.847756 B0:1 B1:-2 CA:0
7319 12:15:05.850714
7320 12:15:05.850823 [DutyScan_Calibration_Flow] k_type=0
7321 12:15:05.862363
7322 12:15:05.862460 ==CLK 0==
7323 12:15:05.865365 Final CLK duty delay cell = 0
7324 12:15:05.868857 [0] MAX Duty = 5062%(X100), DQS PI = 20
7325 12:15:05.871985 [0] MIN Duty = 4844%(X100), DQS PI = 58
7326 12:15:05.875593 [0] AVG Duty = 4953%(X100)
7327 12:15:05.875674
7328 12:15:05.878753 CH1 CLK Duty spec in!! Max-Min= 218%
7329 12:15:05.881912 [DutyScan_Calibration_Flow] ====Done====
7330 12:15:05.881993
7331 12:15:05.885029 [DutyScan_Calibration_Flow] k_type=1
7332 12:15:05.901153
7333 12:15:05.901272 ==DQS 0 ==
7334 12:15:05.904224 Final DQS duty delay cell = -4
7335 12:15:05.908133 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7336 12:15:05.911193 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7337 12:15:05.914185 [-4] AVG Duty = 4906%(X100)
7338 12:15:05.914266
7339 12:15:05.914329 ==DQS 1 ==
7340 12:15:05.917966 Final DQS duty delay cell = 0
7341 12:15:05.920907 [0] MAX Duty = 5093%(X100), DQS PI = 58
7342 12:15:05.924171 [0] MIN Duty = 4844%(X100), DQS PI = 24
7343 12:15:05.927618 [0] AVG Duty = 4968%(X100)
7344 12:15:05.927701
7345 12:15:05.930707 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7346 12:15:05.930790
7347 12:15:05.934404 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7348 12:15:05.937253 [DutyScan_Calibration_Flow] ====Done====
7349 12:15:05.937335
7350 12:15:05.940624 [DutyScan_Calibration_Flow] k_type=3
7351 12:15:05.958532
7352 12:15:05.958672 ==DQM 0 ==
7353 12:15:05.961533 Final DQM duty delay cell = 0
7354 12:15:05.965332 [0] MAX Duty = 5031%(X100), DQS PI = 24
7355 12:15:05.968278 [0] MIN Duty = 4813%(X100), DQS PI = 56
7356 12:15:05.971522 [0] AVG Duty = 4922%(X100)
7357 12:15:05.971602
7358 12:15:05.971664 ==DQM 1 ==
7359 12:15:05.974681 Final DQM duty delay cell = 0
7360 12:15:05.978295 [0] MAX Duty = 5062%(X100), DQS PI = 34
7361 12:15:05.981546 [0] MIN Duty = 4875%(X100), DQS PI = 26
7362 12:15:05.984795 [0] AVG Duty = 4968%(X100)
7363 12:15:05.984884
7364 12:15:05.987835 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7365 12:15:05.987916
7366 12:15:05.990910 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7367 12:15:05.994678 [DutyScan_Calibration_Flow] ====Done====
7368 12:15:05.994789
7369 12:15:05.997664 [DutyScan_Calibration_Flow] k_type=2
7370 12:15:06.015211
7371 12:15:06.015313 ==DQ 0 ==
7372 12:15:06.018360 Final DQ duty delay cell = 0
7373 12:15:06.021663 [0] MAX Duty = 5093%(X100), DQS PI = 22
7374 12:15:06.025360 [0] MIN Duty = 4907%(X100), DQS PI = 46
7375 12:15:06.025441 [0] AVG Duty = 5000%(X100)
7376 12:15:06.028434
7377 12:15:06.028539 ==DQ 1 ==
7378 12:15:06.032081 Final DQ duty delay cell = 0
7379 12:15:06.035279 [0] MAX Duty = 5156%(X100), DQS PI = 36
7380 12:15:06.038421 [0] MIN Duty = 4969%(X100), DQS PI = 24
7381 12:15:06.038518 [0] AVG Duty = 5062%(X100)
7382 12:15:06.041797
7383 12:15:06.045136 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7384 12:15:06.045249
7385 12:15:06.048098 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7386 12:15:06.051553 [DutyScan_Calibration_Flow] ====Done====
7387 12:15:06.054926 nWR fixed to 30
7388 12:15:06.057990 [ModeRegInit_LP4] CH0 RK0
7389 12:15:06.058073 [ModeRegInit_LP4] CH0 RK1
7390 12:15:06.061423 [ModeRegInit_LP4] CH1 RK0
7391 12:15:06.064806 [ModeRegInit_LP4] CH1 RK1
7392 12:15:06.064890 match AC timing 5
7393 12:15:06.071450 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7394 12:15:06.074454 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7395 12:15:06.077776 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7396 12:15:06.084339 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7397 12:15:06.087540 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7398 12:15:06.087627 [MiockJmeterHQA]
7399 12:15:06.087691
7400 12:15:06.091427 [DramcMiockJmeter] u1RxGatingPI = 0
7401 12:15:06.094663 0 : 4363, 4137
7402 12:15:06.094779 4 : 4252, 4027
7403 12:15:06.097810 8 : 4363, 4137
7404 12:15:06.097895 12 : 4257, 4029
7405 12:15:06.100933 16 : 4258, 4029
7406 12:15:06.101018 20 : 4363, 4138
7407 12:15:06.101092 24 : 4252, 4027
7408 12:15:06.103903 28 : 4252, 4027
7409 12:15:06.104016 32 : 4253, 4026
7410 12:15:06.107589 36 : 4258, 4032
7411 12:15:06.107674 40 : 4366, 4139
7412 12:15:06.110387 44 : 4252, 4027
7413 12:15:06.110499 48 : 4363, 4137
7414 12:15:06.114096 52 : 4255, 4029
7415 12:15:06.114208 56 : 4250, 4027
7416 12:15:06.114304 60 : 4250, 4027
7417 12:15:06.117274 64 : 4360, 4138
7418 12:15:06.117357 68 : 4250, 4027
7419 12:15:06.120286 72 : 4360, 4137
7420 12:15:06.120370 76 : 4250, 4027
7421 12:15:06.124002 80 : 4250, 4027
7422 12:15:06.124086 84 : 4250, 4026
7423 12:15:06.127026 88 : 4254, 4032
7424 12:15:06.127109 92 : 4360, 4137
7425 12:15:06.127176 96 : 4250, 4026
7426 12:15:06.130709 100 : 4361, 4138
7427 12:15:06.130820 104 : 4360, 3868
7428 12:15:06.133935 108 : 4250, 2
7429 12:15:06.134020 112 : 4250, 0
7430 12:15:06.137100 116 : 4253, 0
7431 12:15:06.137184 120 : 4360, 0
7432 12:15:06.137251 124 : 4360, 0
7433 12:15:06.140763 128 : 4247, 0
7434 12:15:06.140847 132 : 4250, 0
7435 12:15:06.143995 136 : 4360, 0
7436 12:15:06.144094 140 : 4361, 0
7437 12:15:06.144190 144 : 4250, 0
7438 12:15:06.146967 148 : 4250, 0
7439 12:15:06.147080 152 : 4250, 0
7440 12:15:06.147187 156 : 4250, 0
7441 12:15:06.150706 160 : 4250, 0
7442 12:15:06.150845 164 : 4250, 0
7443 12:15:06.153451 168 : 4255, 0
7444 12:15:06.153547 172 : 4361, 0
7445 12:15:06.153613 176 : 4360, 0
7446 12:15:06.156950 180 : 4250, 0
7447 12:15:06.157050 184 : 4250, 0
7448 12:15:06.160399 188 : 4360, 0
7449 12:15:06.160481 192 : 4361, 0
7450 12:15:06.160563 196 : 4250, 0
7451 12:15:06.163382 200 : 4250, 0
7452 12:15:06.163465 204 : 4250, 0
7453 12:15:06.166846 208 : 4250, 0
7454 12:15:06.166941 212 : 4250, 0
7455 12:15:06.167022 216 : 4250, 0
7456 12:15:06.169904 220 : 4252, 0
7457 12:15:06.169982 224 : 4360, 0
7458 12:15:06.173809 228 : 4250, 0
7459 12:15:06.173893 232 : 4250, 0
7460 12:15:06.173975 236 : 4361, 1339
7461 12:15:06.176884 240 : 4250, 4027
7462 12:15:06.176962 244 : 4250, 4027
7463 12:15:06.180017 248 : 4361, 4138
7464 12:15:06.180100 252 : 4360, 4137
7465 12:15:06.183397 256 : 4248, 4025
7466 12:15:06.183481 260 : 4361, 4138
7467 12:15:06.186592 264 : 4360, 4137
7468 12:15:06.186701 268 : 4250, 4026
7469 12:15:06.189736 272 : 4250, 4027
7470 12:15:06.189819 276 : 4250, 4027
7471 12:15:06.192896 280 : 4250, 4027
7472 12:15:06.193014 284 : 4250, 4026
7473 12:15:06.196749 288 : 4250, 4026
7474 12:15:06.196863 292 : 4250, 4027
7475 12:15:06.196967 296 : 4250, 4027
7476 12:15:06.199904 300 : 4360, 4137
7477 12:15:06.200013 304 : 4361, 4137
7478 12:15:06.203182 308 : 4248, 4025
7479 12:15:06.203295 312 : 4361, 4138
7480 12:15:06.206381 316 : 4360, 4137
7481 12:15:06.206491 320 : 4250, 4026
7482 12:15:06.210058 324 : 4250, 4026
7483 12:15:06.210166 328 : 4250, 4027
7484 12:15:06.213017 332 : 4250, 4027
7485 12:15:06.213118 336 : 4250, 4027
7486 12:15:06.215973 340 : 4250, 4027
7487 12:15:06.216088 344 : 4250, 4027
7488 12:15:06.219734 348 : 4250, 4027
7489 12:15:06.219822 352 : 4360, 4125
7490 12:15:06.222666 356 : 4361, 2898
7491 12:15:06.222800 360 : 4248, 1
7492 12:15:06.222923
7493 12:15:06.225978 MIOCK jitter meter ch=0
7494 12:15:06.226065
7495 12:15:06.229614 1T = (360-108) = 252 dly cells
7496 12:15:06.233014 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7497 12:15:06.233115 ==
7498 12:15:06.236257 Dram Type= 6, Freq= 0, CH_0, rank 0
7499 12:15:06.242886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7500 12:15:06.243008 ==
7501 12:15:06.246152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7502 12:15:06.252636 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7503 12:15:06.255647 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7504 12:15:06.262295 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7505 12:15:06.270271 [CA 0] Center 44 (14~75) winsize 62
7506 12:15:06.273358 [CA 1] Center 43 (13~74) winsize 62
7507 12:15:06.276916 [CA 2] Center 40 (11~69) winsize 59
7508 12:15:06.280457 [CA 3] Center 39 (10~68) winsize 59
7509 12:15:06.283629 [CA 4] Center 37 (8~67) winsize 60
7510 12:15:06.286824 [CA 5] Center 37 (7~67) winsize 61
7511 12:15:06.286938
7512 12:15:06.289975 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7513 12:15:06.290086
7514 12:15:06.293743 [CATrainingPosCal] consider 1 rank data
7515 12:15:06.296830 u2DelayCellTimex100 = 258/100 ps
7516 12:15:06.303745 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7517 12:15:06.306822 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7518 12:15:06.310060 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7519 12:15:06.312992 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7520 12:15:06.316766 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7521 12:15:06.319935 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7522 12:15:06.320044
7523 12:15:06.322823 CA PerBit enable=1, Macro0, CA PI delay=37
7524 12:15:06.322945
7525 12:15:06.326455 [CBTSetCACLKResult] CA Dly = 37
7526 12:15:06.329597 CS Dly: 11 (0~42)
7527 12:15:06.333493 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7528 12:15:06.336581 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7529 12:15:06.336688 ==
7530 12:15:06.339798 Dram Type= 6, Freq= 0, CH_0, rank 1
7531 12:15:06.346107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 12:15:06.346219 ==
7533 12:15:06.349834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7534 12:15:06.356486 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7535 12:15:06.359597 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7536 12:15:06.366321 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7537 12:15:06.374008 [CA 0] Center 44 (14~75) winsize 62
7538 12:15:06.377460 [CA 1] Center 43 (13~74) winsize 62
7539 12:15:06.380561 [CA 2] Center 39 (10~69) winsize 60
7540 12:15:06.383890 [CA 3] Center 39 (10~69) winsize 60
7541 12:15:06.387524 [CA 4] Center 37 (8~67) winsize 60
7542 12:15:06.390785 [CA 5] Center 37 (7~67) winsize 61
7543 12:15:06.390906
7544 12:15:06.394161 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7545 12:15:06.394298
7546 12:15:06.400690 [CATrainingPosCal] consider 2 rank data
7547 12:15:06.400817 u2DelayCellTimex100 = 258/100 ps
7548 12:15:06.406726 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7549 12:15:06.410084 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7550 12:15:06.413319 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7551 12:15:06.416824 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7552 12:15:06.420161 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7553 12:15:06.423403 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7554 12:15:06.423510
7555 12:15:06.426564 CA PerBit enable=1, Macro0, CA PI delay=37
7556 12:15:06.426681
7557 12:15:06.430486 [CBTSetCACLKResult] CA Dly = 37
7558 12:15:06.433648 CS Dly: 11 (0~43)
7559 12:15:06.436909 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7560 12:15:06.440302 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7561 12:15:06.440408
7562 12:15:06.443412 ----->DramcWriteLeveling(PI) begin...
7563 12:15:06.446595 ==
7564 12:15:06.449950 Dram Type= 6, Freq= 0, CH_0, rank 0
7565 12:15:06.453153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7566 12:15:06.453267 ==
7567 12:15:06.456299 Write leveling (Byte 0): 35 => 35
7568 12:15:06.459571 Write leveling (Byte 1): 28 => 28
7569 12:15:06.462737 DramcWriteLeveling(PI) end<-----
7570 12:15:06.462856
7571 12:15:06.462952 ==
7572 12:15:06.465997 Dram Type= 6, Freq= 0, CH_0, rank 0
7573 12:15:06.469286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 12:15:06.469399 ==
7575 12:15:06.472597 [Gating] SW mode calibration
7576 12:15:06.479455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7577 12:15:06.486083 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7578 12:15:06.489708 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 12:15:06.492926 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 12:15:06.498825 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 12:15:06.502899 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 12:15:06.505931 1 4 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
7583 12:15:06.512590 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7584 12:15:06.515175 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7585 12:15:06.519101 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 12:15:06.525702 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 12:15:06.528711 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 12:15:06.531931 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 12:15:06.538747 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7590 12:15:06.541656 1 5 16 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
7591 12:15:06.544876 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7592 12:15:06.551325 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
7593 12:15:06.554938 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 12:15:06.557997 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 12:15:06.564528 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 12:15:06.567729 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 12:15:06.571083 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 12:15:06.577853 1 6 16 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7599 12:15:06.581452 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7600 12:15:06.584649 1 6 24 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
7601 12:15:06.590962 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 12:15:06.594605 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 12:15:06.597716 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 12:15:06.604170 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 12:15:06.607888 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 12:15:06.611366 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7607 12:15:06.617556 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7608 12:15:06.620708 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7609 12:15:06.624035 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7610 12:15:06.630362 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 12:15:06.633815 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 12:15:06.637091 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 12:15:06.644261 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 12:15:06.647301 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 12:15:06.650564 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 12:15:06.657036 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 12:15:06.660446 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 12:15:06.663591 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 12:15:06.670196 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 12:15:06.673480 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 12:15:06.676896 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7622 12:15:06.683478 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7623 12:15:06.686699 Total UI for P1: 0, mck2ui 16
7624 12:15:06.689802 best dqsien dly found for B0: ( 1, 9, 12)
7625 12:15:06.693503 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7626 12:15:06.696414 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7627 12:15:06.703592 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 12:15:06.706543 Total UI for P1: 0, mck2ui 16
7629 12:15:06.709798 best dqsien dly found for B1: ( 1, 9, 24)
7630 12:15:06.712928 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7631 12:15:06.716354 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7632 12:15:06.716473
7633 12:15:06.720104 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7634 12:15:06.723038 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7635 12:15:06.726204 [Gating] SW calibration Done
7636 12:15:06.726314 ==
7637 12:15:06.730036 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 12:15:06.732944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 12:15:06.733131 ==
7640 12:15:06.736083 RX Vref Scan: 0
7641 12:15:06.736231
7642 12:15:06.739109 RX Vref 0 -> 0, step: 1
7643 12:15:06.739215
7644 12:15:06.739310 RX Delay 0 -> 252, step: 8
7645 12:15:06.745940 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7646 12:15:06.749566 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7647 12:15:06.752579 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7648 12:15:06.756114 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7649 12:15:06.759218 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7650 12:15:06.765702 iDelay=192, Bit 5, Center 115 (64 ~ 167) 104
7651 12:15:06.768918 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7652 12:15:06.772260 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7653 12:15:06.775497 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7654 12:15:06.779287 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7655 12:15:06.785856 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7656 12:15:06.789111 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7657 12:15:06.792268 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7658 12:15:06.795608 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7659 12:15:06.801965 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7660 12:15:06.805497 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7661 12:15:06.805620 ==
7662 12:15:06.808585 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 12:15:06.811647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 12:15:06.811767 ==
7665 12:15:06.815342 DQS Delay:
7666 12:15:06.815458 DQS0 = 0, DQS1 = 0
7667 12:15:06.815562 DQM Delay:
7668 12:15:06.818247 DQM0 = 128, DQM1 = 123
7669 12:15:06.818362 DQ Delay:
7670 12:15:06.821949 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7671 12:15:06.824979 DQ4 =127, DQ5 =115, DQ6 =135, DQ7 =135
7672 12:15:06.831746 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7673 12:15:06.834893 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7674 12:15:06.835013
7675 12:15:06.835119
7676 12:15:06.835221 ==
7677 12:15:06.838273 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 12:15:06.841354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 12:15:06.841468 ==
7680 12:15:06.841570
7681 12:15:06.841663
7682 12:15:06.844702 TX Vref Scan disable
7683 12:15:06.848546 == TX Byte 0 ==
7684 12:15:06.851663 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7685 12:15:06.854715 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7686 12:15:06.858445 == TX Byte 1 ==
7687 12:15:06.861558 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7688 12:15:06.864602 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7689 12:15:06.864685 ==
7690 12:15:06.867803 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 12:15:06.871080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 12:15:06.874722 ==
7693 12:15:06.886412
7694 12:15:06.889608 TX Vref early break, caculate TX vref
7695 12:15:06.892872 TX Vref=16, minBit 8, minWin=20, winSum=348
7696 12:15:06.896129 TX Vref=18, minBit 8, minWin=21, winSum=365
7697 12:15:06.899566 TX Vref=20, minBit 8, minWin=21, winSum=372
7698 12:15:06.902628 TX Vref=22, minBit 8, minWin=22, winSum=380
7699 12:15:06.906504 TX Vref=24, minBit 8, minWin=22, winSum=390
7700 12:15:06.912477 TX Vref=26, minBit 8, minWin=23, winSum=399
7701 12:15:06.915812 TX Vref=28, minBit 8, minWin=24, winSum=399
7702 12:15:06.919018 TX Vref=30, minBit 8, minWin=23, winSum=390
7703 12:15:06.922817 TX Vref=32, minBit 9, minWin=21, winSum=382
7704 12:15:06.926152 TX Vref=34, minBit 9, minWin=21, winSum=372
7705 12:15:06.932676 [TxChooseVref] Worse bit 8, Min win 24, Win sum 399, Final Vref 28
7706 12:15:06.932760
7707 12:15:06.935752 Final TX Range 0 Vref 28
7708 12:15:06.935833
7709 12:15:06.935917 ==
7710 12:15:06.938908 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 12:15:06.942225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 12:15:06.942324 ==
7713 12:15:06.942414
7714 12:15:06.942501
7715 12:15:06.945588 TX Vref Scan disable
7716 12:15:06.952041 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7717 12:15:06.952127 == TX Byte 0 ==
7718 12:15:06.955468 u2DelayCellOfst[0]=15 cells (4 PI)
7719 12:15:06.958633 u2DelayCellOfst[1]=18 cells (5 PI)
7720 12:15:06.962775 u2DelayCellOfst[2]=15 cells (4 PI)
7721 12:15:06.965147 u2DelayCellOfst[3]=15 cells (4 PI)
7722 12:15:06.968892 u2DelayCellOfst[4]=11 cells (3 PI)
7723 12:15:06.971821 u2DelayCellOfst[5]=0 cells (0 PI)
7724 12:15:06.975190 u2DelayCellOfst[6]=22 cells (6 PI)
7725 12:15:06.978488 u2DelayCellOfst[7]=22 cells (6 PI)
7726 12:15:06.981827 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7727 12:15:06.985192 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7728 12:15:06.988401 == TX Byte 1 ==
7729 12:15:06.991933 u2DelayCellOfst[8]=0 cells (0 PI)
7730 12:15:06.995164 u2DelayCellOfst[9]=3 cells (1 PI)
7731 12:15:06.998341 u2DelayCellOfst[10]=7 cells (2 PI)
7732 12:15:07.001711 u2DelayCellOfst[11]=7 cells (2 PI)
7733 12:15:07.001797 u2DelayCellOfst[12]=15 cells (4 PI)
7734 12:15:07.005125 u2DelayCellOfst[13]=11 cells (3 PI)
7735 12:15:07.008029 u2DelayCellOfst[14]=18 cells (5 PI)
7736 12:15:07.011274 u2DelayCellOfst[15]=11 cells (3 PI)
7737 12:15:07.018360 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7738 12:15:07.021416 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7739 12:15:07.021501 DramC Write-DBI on
7740 12:15:07.024733 ==
7741 12:15:07.027948 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 12:15:07.031352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 12:15:07.031437 ==
7744 12:15:07.031503
7745 12:15:07.031563
7746 12:15:07.034340 TX Vref Scan disable
7747 12:15:07.034423 == TX Byte 0 ==
7748 12:15:07.040844 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7749 12:15:07.040955 == TX Byte 1 ==
7750 12:15:07.044662 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7751 12:15:07.047381 DramC Write-DBI off
7752 12:15:07.047459
7753 12:15:07.047524 [DATLAT]
7754 12:15:07.050691 Freq=1600, CH0 RK0
7755 12:15:07.050793
7756 12:15:07.050881 DATLAT Default: 0xf
7757 12:15:07.054717 0, 0xFFFF, sum = 0
7758 12:15:07.054820 1, 0xFFFF, sum = 0
7759 12:15:07.057497 2, 0xFFFF, sum = 0
7760 12:15:07.057613 3, 0xFFFF, sum = 0
7761 12:15:07.061255 4, 0xFFFF, sum = 0
7762 12:15:07.063965 5, 0xFFFF, sum = 0
7763 12:15:07.064082 6, 0xFFFF, sum = 0
7764 12:15:07.067172 7, 0xFFFF, sum = 0
7765 12:15:07.067284 8, 0xFFFF, sum = 0
7766 12:15:07.070643 9, 0xFFFF, sum = 0
7767 12:15:07.070745 10, 0xFFFF, sum = 0
7768 12:15:07.073972 11, 0xFFFF, sum = 0
7769 12:15:07.074109 12, 0xFFFF, sum = 0
7770 12:15:07.077019 13, 0xFFFF, sum = 0
7771 12:15:07.077143 14, 0x0, sum = 1
7772 12:15:07.080836 15, 0x0, sum = 2
7773 12:15:07.080970 16, 0x0, sum = 3
7774 12:15:07.084117 17, 0x0, sum = 4
7775 12:15:07.084231 best_step = 15
7776 12:15:07.084335
7777 12:15:07.084435 ==
7778 12:15:07.087542 Dram Type= 6, Freq= 0, CH_0, rank 0
7779 12:15:07.093779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7780 12:15:07.093916 ==
7781 12:15:07.094007 RX Vref Scan: 1
7782 12:15:07.094087
7783 12:15:07.097143 Set Vref Range= 24 -> 127
7784 12:15:07.097235
7785 12:15:07.100615 RX Vref 24 -> 127, step: 1
7786 12:15:07.100729
7787 12:15:07.100834 RX Delay 11 -> 252, step: 4
7788 12:15:07.103696
7789 12:15:07.103786 Set Vref, RX VrefLevel [Byte0]: 24
7790 12:15:07.106510 [Byte1]: 24
7791 12:15:07.110957
7792 12:15:07.111056 Set Vref, RX VrefLevel [Byte0]: 25
7793 12:15:07.114076 [Byte1]: 25
7794 12:15:07.118597
7795 12:15:07.118715 Set Vref, RX VrefLevel [Byte0]: 26
7796 12:15:07.121963 [Byte1]: 26
7797 12:15:07.126474
7798 12:15:07.126588 Set Vref, RX VrefLevel [Byte0]: 27
7799 12:15:07.129681 [Byte1]: 27
7800 12:15:07.134148
7801 12:15:07.134265 Set Vref, RX VrefLevel [Byte0]: 28
7802 12:15:07.137278 [Byte1]: 28
7803 12:15:07.141638
7804 12:15:07.141733 Set Vref, RX VrefLevel [Byte0]: 29
7805 12:15:07.145338 [Byte1]: 29
7806 12:15:07.149481
7807 12:15:07.149573 Set Vref, RX VrefLevel [Byte0]: 30
7808 12:15:07.152712 [Byte1]: 30
7809 12:15:07.156937
7810 12:15:07.157032 Set Vref, RX VrefLevel [Byte0]: 31
7811 12:15:07.160267 [Byte1]: 31
7812 12:15:07.164255
7813 12:15:07.164345 Set Vref, RX VrefLevel [Byte0]: 32
7814 12:15:07.167482 [Byte1]: 32
7815 12:15:07.172166
7816 12:15:07.172260 Set Vref, RX VrefLevel [Byte0]: 33
7817 12:15:07.175451 [Byte1]: 33
7818 12:15:07.180028
7819 12:15:07.180126 Set Vref, RX VrefLevel [Byte0]: 34
7820 12:15:07.183209 [Byte1]: 34
7821 12:15:07.186927
7822 12:15:07.187023 Set Vref, RX VrefLevel [Byte0]: 35
7823 12:15:07.190458 [Byte1]: 35
7824 12:15:07.194949
7825 12:15:07.195041 Set Vref, RX VrefLevel [Byte0]: 36
7826 12:15:07.198178 [Byte1]: 36
7827 12:15:07.202774
7828 12:15:07.202896 Set Vref, RX VrefLevel [Byte0]: 37
7829 12:15:07.206067 [Byte1]: 37
7830 12:15:07.209751
7831 12:15:07.209870 Set Vref, RX VrefLevel [Byte0]: 38
7832 12:15:07.213121 [Byte1]: 38
7833 12:15:07.217849
7834 12:15:07.217989 Set Vref, RX VrefLevel [Byte0]: 39
7835 12:15:07.220964 [Byte1]: 39
7836 12:15:07.225507
7837 12:15:07.225603 Set Vref, RX VrefLevel [Byte0]: 40
7838 12:15:07.228677 [Byte1]: 40
7839 12:15:07.233121
7840 12:15:07.233215 Set Vref, RX VrefLevel [Byte0]: 41
7841 12:15:07.236398 [Byte1]: 41
7842 12:15:07.240410
7843 12:15:07.240498 Set Vref, RX VrefLevel [Byte0]: 42
7844 12:15:07.243779 [Byte1]: 42
7845 12:15:07.248328
7846 12:15:07.248418 Set Vref, RX VrefLevel [Byte0]: 43
7847 12:15:07.251632 [Byte1]: 43
7848 12:15:07.255963
7849 12:15:07.256061 Set Vref, RX VrefLevel [Byte0]: 44
7850 12:15:07.258676 [Byte1]: 44
7851 12:15:07.263107
7852 12:15:07.263250 Set Vref, RX VrefLevel [Byte0]: 45
7853 12:15:07.266880 [Byte1]: 45
7854 12:15:07.271188
7855 12:15:07.271322 Set Vref, RX VrefLevel [Byte0]: 46
7856 12:15:07.274437 [Byte1]: 46
7857 12:15:07.278911
7858 12:15:07.279037 Set Vref, RX VrefLevel [Byte0]: 47
7859 12:15:07.281886 [Byte1]: 47
7860 12:15:07.286388
7861 12:15:07.286519 Set Vref, RX VrefLevel [Byte0]: 48
7862 12:15:07.289595 [Byte1]: 48
7863 12:15:07.293895
7864 12:15:07.294033 Set Vref, RX VrefLevel [Byte0]: 49
7865 12:15:07.297281 [Byte1]: 49
7866 12:15:07.301135
7867 12:15:07.301270 Set Vref, RX VrefLevel [Byte0]: 50
7868 12:15:07.304919 [Byte1]: 50
7869 12:15:07.308835
7870 12:15:07.308969 Set Vref, RX VrefLevel [Byte0]: 51
7871 12:15:07.312699 [Byte1]: 51
7872 12:15:07.316952
7873 12:15:07.317087 Set Vref, RX VrefLevel [Byte0]: 52
7874 12:15:07.320147 [Byte1]: 52
7875 12:15:07.323978
7876 12:15:07.324106 Set Vref, RX VrefLevel [Byte0]: 53
7877 12:15:07.327635 [Byte1]: 53
7878 12:15:07.331968
7879 12:15:07.332099 Set Vref, RX VrefLevel [Byte0]: 54
7880 12:15:07.335075 [Byte1]: 54
7881 12:15:07.339172
7882 12:15:07.339308 Set Vref, RX VrefLevel [Byte0]: 55
7883 12:15:07.343144 [Byte1]: 55
7884 12:15:07.347219
7885 12:15:07.347313 Set Vref, RX VrefLevel [Byte0]: 56
7886 12:15:07.350230 [Byte1]: 56
7887 12:15:07.354751
7888 12:15:07.354885 Set Vref, RX VrefLevel [Byte0]: 57
7889 12:15:07.358099 [Byte1]: 57
7890 12:15:07.362481
7891 12:15:07.362609 Set Vref, RX VrefLevel [Byte0]: 58
7892 12:15:07.365522 [Byte1]: 58
7893 12:15:07.369847
7894 12:15:07.369980 Set Vref, RX VrefLevel [Byte0]: 59
7895 12:15:07.372907 [Byte1]: 59
7896 12:15:07.377344
7897 12:15:07.377469 Set Vref, RX VrefLevel [Byte0]: 60
7898 12:15:07.381016 [Byte1]: 60
7899 12:15:07.384832
7900 12:15:07.384951 Set Vref, RX VrefLevel [Byte0]: 61
7901 12:15:07.388685 [Byte1]: 61
7902 12:15:07.392551
7903 12:15:07.392676 Set Vref, RX VrefLevel [Byte0]: 62
7904 12:15:07.396235 [Byte1]: 62
7905 12:15:07.400649
7906 12:15:07.400785 Set Vref, RX VrefLevel [Byte0]: 63
7907 12:15:07.403761 [Byte1]: 63
7908 12:15:07.407929
7909 12:15:07.408054 Set Vref, RX VrefLevel [Byte0]: 64
7910 12:15:07.411323 [Byte1]: 64
7911 12:15:07.415819
7912 12:15:07.415958 Set Vref, RX VrefLevel [Byte0]: 65
7913 12:15:07.418854 [Byte1]: 65
7914 12:15:07.423505
7915 12:15:07.423638 Set Vref, RX VrefLevel [Byte0]: 66
7916 12:15:07.426372 [Byte1]: 66
7917 12:15:07.430748
7918 12:15:07.430886 Set Vref, RX VrefLevel [Byte0]: 67
7919 12:15:07.434059 [Byte1]: 67
7920 12:15:07.438387
7921 12:15:07.438516 Set Vref, RX VrefLevel [Byte0]: 68
7922 12:15:07.441645 [Byte1]: 68
7923 12:15:07.446226
7924 12:15:07.446347 Set Vref, RX VrefLevel [Byte0]: 69
7925 12:15:07.449497 [Byte1]: 69
7926 12:15:07.453919
7927 12:15:07.454047 Set Vref, RX VrefLevel [Byte0]: 70
7928 12:15:07.457391 [Byte1]: 70
7929 12:15:07.461018
7930 12:15:07.461142 Set Vref, RX VrefLevel [Byte0]: 71
7931 12:15:07.464388 [Byte1]: 71
7932 12:15:07.468687
7933 12:15:07.468814 Set Vref, RX VrefLevel [Byte0]: 72
7934 12:15:07.472362 [Byte1]: 72
7935 12:15:07.476546
7936 12:15:07.476668 Set Vref, RX VrefLevel [Byte0]: 73
7937 12:15:07.479672 [Byte1]: 73
7938 12:15:07.483832
7939 12:15:07.483963 Set Vref, RX VrefLevel [Byte0]: 74
7940 12:15:07.487705 [Byte1]: 74
7941 12:15:07.491845
7942 12:15:07.491983 Set Vref, RX VrefLevel [Byte0]: 75
7943 12:15:07.494776 [Byte1]: 75
7944 12:15:07.499207
7945 12:15:07.499343 Set Vref, RX VrefLevel [Byte0]: 76
7946 12:15:07.502242 [Byte1]: 76
7947 12:15:07.506833
7948 12:15:07.506963 Final RX Vref Byte 0 = 64 to rank0
7949 12:15:07.510148 Final RX Vref Byte 1 = 62 to rank0
7950 12:15:07.513600 Final RX Vref Byte 0 = 64 to rank1
7951 12:15:07.516558 Final RX Vref Byte 1 = 62 to rank1==
7952 12:15:07.519850 Dram Type= 6, Freq= 0, CH_0, rank 0
7953 12:15:07.527200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 12:15:07.527354 ==
7955 12:15:07.527461 DQS Delay:
7956 12:15:07.529685 DQS0 = 0, DQS1 = 0
7957 12:15:07.529800 DQM Delay:
7958 12:15:07.529898 DQM0 = 126, DQM1 = 119
7959 12:15:07.532928 DQ Delay:
7960 12:15:07.536662 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
7961 12:15:07.539877 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7962 12:15:07.543091 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7963 12:15:07.546757 DQ12 =124, DQ13 =124, DQ14 =132, DQ15 =126
7964 12:15:07.546906
7965 12:15:07.547004
7966 12:15:07.547093
7967 12:15:07.549911 [DramC_TX_OE_Calibration] TA2
7968 12:15:07.553073 Original DQ_B0 (3 6) =30, OEN = 27
7969 12:15:07.556578 Original DQ_B1 (3 6) =30, OEN = 27
7970 12:15:07.559772 24, 0x0, End_B0=24 End_B1=24
7971 12:15:07.562860 25, 0x0, End_B0=25 End_B1=25
7972 12:15:07.562965 26, 0x0, End_B0=26 End_B1=26
7973 12:15:07.566104 27, 0x0, End_B0=27 End_B1=27
7974 12:15:07.569367 28, 0x0, End_B0=28 End_B1=28
7975 12:15:07.572645 29, 0x0, End_B0=29 End_B1=29
7976 12:15:07.572760 30, 0x0, End_B0=30 End_B1=30
7977 12:15:07.575674 31, 0x4141, End_B0=30 End_B1=30
7978 12:15:07.579625 Byte0 end_step=30 best_step=27
7979 12:15:07.582195 Byte1 end_step=30 best_step=27
7980 12:15:07.586115 Byte0 TX OE(2T, 0.5T) = (3, 3)
7981 12:15:07.589255 Byte1 TX OE(2T, 0.5T) = (3, 3)
7982 12:15:07.589391
7983 12:15:07.589495
7984 12:15:07.595729 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
7985 12:15:07.599406 CH0 RK0: MR19=303, MR18=1010
7986 12:15:07.605915 CH0_RK0: MR19=0x303, MR18=0x1010, DQSOSC=401, MR23=63, INC=22, DEC=15
7987 12:15:07.606064
7988 12:15:07.609078 ----->DramcWriteLeveling(PI) begin...
7989 12:15:07.609205 ==
7990 12:15:07.612344 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 12:15:07.615663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 12:15:07.615760 ==
7993 12:15:07.619159 Write leveling (Byte 0): 32 => 32
7994 12:15:07.622145 Write leveling (Byte 1): 28 => 28
7995 12:15:07.625108 DramcWriteLeveling(PI) end<-----
7996 12:15:07.625209
7997 12:15:07.625278 ==
7998 12:15:07.628959 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 12:15:07.635422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 12:15:07.635542 ==
8001 12:15:07.635614 [Gating] SW mode calibration
8002 12:15:07.645100 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8003 12:15:07.648232 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8004 12:15:07.654702 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 12:15:07.658621 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 12:15:07.661334 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 12:15:07.667886 1 4 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8008 12:15:07.671674 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8009 12:15:07.674799 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 12:15:07.681302 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 12:15:07.684380 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 12:15:07.687687 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 12:15:07.694847 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 12:15:07.698012 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8015 12:15:07.701155 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
8016 12:15:07.707937 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8017 12:15:07.711057 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
8018 12:15:07.714102 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 12:15:07.720685 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 12:15:07.723953 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 12:15:07.727797 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 12:15:07.734112 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8023 12:15:07.737258 1 6 12 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8024 12:15:07.740596 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8025 12:15:07.747261 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 12:15:07.750360 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 12:15:07.753850 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 12:15:07.760967 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 12:15:07.763552 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 12:15:07.766873 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 12:15:07.770178 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8032 12:15:07.777187 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8033 12:15:07.780247 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8034 12:15:07.783392 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 12:15:07.790107 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 12:15:07.793891 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 12:15:07.796980 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 12:15:07.803383 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 12:15:07.806561 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 12:15:07.810257 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 12:15:07.817172 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 12:15:07.820188 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 12:15:07.823356 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 12:15:07.830161 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 12:15:07.833139 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 12:15:07.836260 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8047 12:15:07.843248 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8048 12:15:07.846113 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8049 12:15:07.849752 Total UI for P1: 0, mck2ui 16
8050 12:15:07.852867 best dqsien dly found for B0: ( 1, 9, 8)
8051 12:15:07.855929 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8052 12:15:07.863075 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 12:15:07.866325 Total UI for P1: 0, mck2ui 16
8054 12:15:07.869538 best dqsien dly found for B1: ( 1, 9, 18)
8055 12:15:07.872702 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8056 12:15:07.876082 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8057 12:15:07.876186
8058 12:15:07.879488 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8059 12:15:07.882113 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8060 12:15:07.885380 [Gating] SW calibration Done
8061 12:15:07.885480 ==
8062 12:15:07.888616 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 12:15:07.892306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 12:15:07.895334 ==
8065 12:15:07.895460 RX Vref Scan: 0
8066 12:15:07.895557
8067 12:15:07.898727 RX Vref 0 -> 0, step: 1
8068 12:15:07.898822
8069 12:15:07.898904 RX Delay 0 -> 252, step: 8
8070 12:15:07.905049 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8071 12:15:07.908418 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8072 12:15:07.911696 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8073 12:15:07.914795 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8074 12:15:07.921612 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8075 12:15:07.924863 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8076 12:15:07.928071 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8077 12:15:07.931271 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8078 12:15:07.934628 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8079 12:15:07.941358 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8080 12:15:07.944786 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8081 12:15:07.947815 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8082 12:15:07.951376 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8083 12:15:07.954586 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8084 12:15:07.961038 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8085 12:15:07.964628 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8086 12:15:07.964741 ==
8087 12:15:07.967809 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 12:15:07.971166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 12:15:07.971276 ==
8090 12:15:07.974533 DQS Delay:
8091 12:15:07.974668 DQS0 = 0, DQS1 = 0
8092 12:15:07.978006 DQM Delay:
8093 12:15:07.978097 DQM0 = 127, DQM1 = 121
8094 12:15:07.978162 DQ Delay:
8095 12:15:07.984197 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8096 12:15:07.987898 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8097 12:15:07.990946 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8098 12:15:07.994201 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8099 12:15:07.994301
8100 12:15:07.994365
8101 12:15:07.994427 ==
8102 12:15:07.997560 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 12:15:08.000762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 12:15:08.000879 ==
8105 12:15:08.000950
8106 12:15:08.001011
8107 12:15:08.003803 TX Vref Scan disable
8108 12:15:08.007715 == TX Byte 0 ==
8109 12:15:08.010763 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8110 12:15:08.014052 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8111 12:15:08.017033 == TX Byte 1 ==
8112 12:15:08.020745 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8113 12:15:08.023651 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8114 12:15:08.023765 ==
8115 12:15:08.027510 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 12:15:08.033683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 12:15:08.033825 ==
8118 12:15:08.046777
8119 12:15:08.049999 TX Vref early break, caculate TX vref
8120 12:15:08.053272 TX Vref=16, minBit 8, minWin=21, winSum=360
8121 12:15:08.056294 TX Vref=18, minBit 9, minWin=21, winSum=366
8122 12:15:08.059972 TX Vref=20, minBit 8, minWin=22, winSum=375
8123 12:15:08.062958 TX Vref=22, minBit 8, minWin=23, winSum=387
8124 12:15:08.066551 TX Vref=24, minBit 8, minWin=23, winSum=391
8125 12:15:08.072917 TX Vref=26, minBit 8, minWin=23, winSum=399
8126 12:15:08.076465 TX Vref=28, minBit 8, minWin=24, winSum=399
8127 12:15:08.079542 TX Vref=30, minBit 9, minWin=22, winSum=397
8128 12:15:08.082792 TX Vref=32, minBit 8, minWin=22, winSum=392
8129 12:15:08.085881 TX Vref=34, minBit 8, minWin=22, winSum=381
8130 12:15:08.093125 TX Vref=36, minBit 8, minWin=21, winSum=376
8131 12:15:08.096167 [TxChooseVref] Worse bit 8, Min win 24, Win sum 399, Final Vref 28
8132 12:15:08.096280
8133 12:15:08.099038 Final TX Range 0 Vref 28
8134 12:15:08.099145
8135 12:15:08.099212 ==
8136 12:15:08.102680 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 12:15:08.105783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 12:15:08.108984 ==
8139 12:15:08.109097
8140 12:15:08.109164
8141 12:15:08.109227 TX Vref Scan disable
8142 12:15:08.116238 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8143 12:15:08.116390 == TX Byte 0 ==
8144 12:15:08.119465 u2DelayCellOfst[0]=11 cells (3 PI)
8145 12:15:08.122471 u2DelayCellOfst[1]=22 cells (6 PI)
8146 12:15:08.125601 u2DelayCellOfst[2]=11 cells (3 PI)
8147 12:15:08.129347 u2DelayCellOfst[3]=11 cells (3 PI)
8148 12:15:08.132253 u2DelayCellOfst[4]=7 cells (2 PI)
8149 12:15:08.135920 u2DelayCellOfst[5]=0 cells (0 PI)
8150 12:15:08.139178 u2DelayCellOfst[6]=18 cells (5 PI)
8151 12:15:08.142181 u2DelayCellOfst[7]=18 cells (5 PI)
8152 12:15:08.145912 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8153 12:15:08.149133 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8154 12:15:08.152307 == TX Byte 1 ==
8155 12:15:08.155281 u2DelayCellOfst[8]=0 cells (0 PI)
8156 12:15:08.158793 u2DelayCellOfst[9]=3 cells (1 PI)
8157 12:15:08.161985 u2DelayCellOfst[10]=11 cells (3 PI)
8158 12:15:08.165302 u2DelayCellOfst[11]=7 cells (2 PI)
8159 12:15:08.168867 u2DelayCellOfst[12]=15 cells (4 PI)
8160 12:15:08.171702 u2DelayCellOfst[13]=11 cells (3 PI)
8161 12:15:08.175339 u2DelayCellOfst[14]=18 cells (5 PI)
8162 12:15:08.178433 u2DelayCellOfst[15]=15 cells (4 PI)
8163 12:15:08.182188 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8164 12:15:08.185217 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8165 12:15:08.188327 DramC Write-DBI on
8166 12:15:08.188436 ==
8167 12:15:08.191489 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 12:15:08.195430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 12:15:08.195605 ==
8170 12:15:08.195692
8171 12:15:08.195766
8172 12:15:08.198523 TX Vref Scan disable
8173 12:15:08.198627 == TX Byte 0 ==
8174 12:15:08.204784 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8175 12:15:08.204956 == TX Byte 1 ==
8176 12:15:08.208406 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8177 12:15:08.211665 DramC Write-DBI off
8178 12:15:08.211769
8179 12:15:08.211837 [DATLAT]
8180 12:15:08.214851 Freq=1600, CH0 RK1
8181 12:15:08.214967
8182 12:15:08.215076 DATLAT Default: 0xf
8183 12:15:08.218131 0, 0xFFFF, sum = 0
8184 12:15:08.221533 1, 0xFFFF, sum = 0
8185 12:15:08.221688 2, 0xFFFF, sum = 0
8186 12:15:08.224844 3, 0xFFFF, sum = 0
8187 12:15:08.225000 4, 0xFFFF, sum = 0
8188 12:15:08.228485 5, 0xFFFF, sum = 0
8189 12:15:08.228627 6, 0xFFFF, sum = 0
8190 12:15:08.231388 7, 0xFFFF, sum = 0
8191 12:15:08.231511 8, 0xFFFF, sum = 0
8192 12:15:08.234743 9, 0xFFFF, sum = 0
8193 12:15:08.234927 10, 0xFFFF, sum = 0
8194 12:15:08.237851 11, 0xFFFF, sum = 0
8195 12:15:08.237993 12, 0xFFFF, sum = 0
8196 12:15:08.240864 13, 0xCFFF, sum = 0
8197 12:15:08.240989 14, 0x0, sum = 1
8198 12:15:08.244673 15, 0x0, sum = 2
8199 12:15:08.244816 16, 0x0, sum = 3
8200 12:15:08.247942 17, 0x0, sum = 4
8201 12:15:08.248052 best_step = 15
8202 12:15:08.248122
8203 12:15:08.248184 ==
8204 12:15:08.251204 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 12:15:08.257273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 12:15:08.257414 ==
8207 12:15:08.257485 RX Vref Scan: 0
8208 12:15:08.257548
8209 12:15:08.261178 RX Vref 0 -> 0, step: 1
8210 12:15:08.261307
8211 12:15:08.264765 RX Delay 3 -> 252, step: 4
8212 12:15:08.267665 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8213 12:15:08.270578 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8214 12:15:08.277286 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8215 12:15:08.280270 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8216 12:15:08.284207 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8217 12:15:08.287291 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8218 12:15:08.290582 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8219 12:15:08.297136 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8220 12:15:08.300297 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8221 12:15:08.303585 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8222 12:15:08.306699 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8223 12:15:08.310211 iDelay=191, Bit 11, Center 110 (55 ~ 166) 112
8224 12:15:08.316810 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8225 12:15:08.320034 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8226 12:15:08.323278 iDelay=191, Bit 14, Center 126 (67 ~ 186) 120
8227 12:15:08.326419 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8228 12:15:08.326563 ==
8229 12:15:08.329644 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 12:15:08.336716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 12:15:08.336847 ==
8232 12:15:08.336917 DQS Delay:
8233 12:15:08.339906 DQS0 = 0, DQS1 = 0
8234 12:15:08.340024 DQM Delay:
8235 12:15:08.343305 DQM0 = 125, DQM1 = 117
8236 12:15:08.343435 DQ Delay:
8237 12:15:08.346211 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8238 12:15:08.349484 DQ4 =124, DQ5 =112, DQ6 =136, DQ7 =134
8239 12:15:08.353104 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =110
8240 12:15:08.356312 DQ12 =124, DQ13 =122, DQ14 =126, DQ15 =124
8241 12:15:08.356430
8242 12:15:08.356524
8243 12:15:08.356587
8244 12:15:08.359634 [DramC_TX_OE_Calibration] TA2
8245 12:15:08.362744 Original DQ_B0 (3 6) =30, OEN = 27
8246 12:15:08.365865 Original DQ_B1 (3 6) =30, OEN = 27
8247 12:15:08.369102 24, 0x0, End_B0=24 End_B1=24
8248 12:15:08.372617 25, 0x0, End_B0=25 End_B1=25
8249 12:15:08.372719 26, 0x0, End_B0=26 End_B1=26
8250 12:15:08.376031 27, 0x0, End_B0=27 End_B1=27
8251 12:15:08.378891 28, 0x0, End_B0=28 End_B1=28
8252 12:15:08.382587 29, 0x0, End_B0=29 End_B1=29
8253 12:15:08.385574 30, 0x0, End_B0=30 End_B1=30
8254 12:15:08.385679 31, 0x4545, End_B0=30 End_B1=30
8255 12:15:08.389165 Byte0 end_step=30 best_step=27
8256 12:15:08.392658 Byte1 end_step=30 best_step=27
8257 12:15:08.395646 Byte0 TX OE(2T, 0.5T) = (3, 3)
8258 12:15:08.398825 Byte1 TX OE(2T, 0.5T) = (3, 3)
8259 12:15:08.398952
8260 12:15:08.399022
8261 12:15:08.405810 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8262 12:15:08.408828 CH0 RK1: MR19=303, MR18=210F
8263 12:15:08.415213 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8264 12:15:08.418780 [RxdqsGatingPostProcess] freq 1600
8265 12:15:08.425034 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8266 12:15:08.428339 best DQS0 dly(2T, 0.5T) = (1, 1)
8267 12:15:08.428471 best DQS1 dly(2T, 0.5T) = (1, 1)
8268 12:15:08.431732 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8269 12:15:08.434975 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8270 12:15:08.438258 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 12:15:08.441616 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 12:15:08.444857 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 12:15:08.448150 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 12:15:08.451535 Pre-setting of DQS Precalculation
8275 12:15:08.457766 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8276 12:15:08.457906 ==
8277 12:15:08.461069 Dram Type= 6, Freq= 0, CH_1, rank 0
8278 12:15:08.464946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 12:15:08.465063 ==
8280 12:15:08.471412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8281 12:15:08.474773 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8282 12:15:08.478062 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8283 12:15:08.484338 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8284 12:15:08.493163 [CA 0] Center 41 (12~71) winsize 60
8285 12:15:08.496255 [CA 1] Center 42 (13~72) winsize 60
8286 12:15:08.499686 [CA 2] Center 37 (9~66) winsize 58
8287 12:15:08.502607 [CA 3] Center 37 (8~66) winsize 59
8288 12:15:08.505763 [CA 4] Center 37 (8~67) winsize 60
8289 12:15:08.509795 [CA 5] Center 36 (7~66) winsize 60
8290 12:15:08.509942
8291 12:15:08.512763 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8292 12:15:08.512881
8293 12:15:08.519329 [CATrainingPosCal] consider 1 rank data
8294 12:15:08.519465 u2DelayCellTimex100 = 258/100 ps
8295 12:15:08.525697 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8296 12:15:08.528893 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8297 12:15:08.532163 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8298 12:15:08.536064 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8299 12:15:08.538847 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8300 12:15:08.542169 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8301 12:15:08.542276
8302 12:15:08.545927 CA PerBit enable=1, Macro0, CA PI delay=36
8303 12:15:08.546023
8304 12:15:08.549044 [CBTSetCACLKResult] CA Dly = 36
8305 12:15:08.552142 CS Dly: 9 (0~40)
8306 12:15:08.555332 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8307 12:15:08.558580 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8308 12:15:08.558700 ==
8309 12:15:08.562026 Dram Type= 6, Freq= 0, CH_1, rank 1
8310 12:15:08.569060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 12:15:08.569190 ==
8312 12:15:08.571632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 12:15:08.578230 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 12:15:08.582234 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 12:15:08.588333 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 12:15:08.596388 [CA 0] Center 42 (13~71) winsize 59
8317 12:15:08.599671 [CA 1] Center 42 (12~72) winsize 61
8318 12:15:08.602709 [CA 2] Center 38 (9~67) winsize 59
8319 12:15:08.606375 [CA 3] Center 36 (7~66) winsize 60
8320 12:15:08.609333 [CA 4] Center 37 (8~67) winsize 60
8321 12:15:08.612507 [CA 5] Center 36 (6~66) winsize 61
8322 12:15:08.612629
8323 12:15:08.615842 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8324 12:15:08.615996
8325 12:15:08.622285 [CATrainingPosCal] consider 2 rank data
8326 12:15:08.622431 u2DelayCellTimex100 = 258/100 ps
8327 12:15:08.628961 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8328 12:15:08.632235 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8329 12:15:08.635304 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8330 12:15:08.638853 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8331 12:15:08.641957 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8332 12:15:08.645186 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8333 12:15:08.645295
8334 12:15:08.648977 CA PerBit enable=1, Macro0, CA PI delay=36
8335 12:15:08.649072
8336 12:15:08.652225 [CBTSetCACLKResult] CA Dly = 36
8337 12:15:08.655399 CS Dly: 10 (0~43)
8338 12:15:08.658938 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 12:15:08.661926 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 12:15:08.662049
8341 12:15:08.665091 ----->DramcWriteLeveling(PI) begin...
8342 12:15:08.668185 ==
8343 12:15:08.668282 Dram Type= 6, Freq= 0, CH_1, rank 0
8344 12:15:08.675233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 12:15:08.675379 ==
8346 12:15:08.678323 Write leveling (Byte 0): 25 => 25
8347 12:15:08.681428 Write leveling (Byte 1): 27 => 27
8348 12:15:08.685192 DramcWriteLeveling(PI) end<-----
8349 12:15:08.685300
8350 12:15:08.685365 ==
8351 12:15:08.688360 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 12:15:08.691524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 12:15:08.691637 ==
8354 12:15:08.694428 [Gating] SW mode calibration
8355 12:15:08.701033 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8356 12:15:08.707914 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8357 12:15:08.711143 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 12:15:08.714283 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 12:15:08.721114 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 12:15:08.724577 1 4 12 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
8361 12:15:08.727695 1 4 16 | B1->B0 | 3232 3130 | 0 1 | (1 1) (0 0)
8362 12:15:08.733751 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 12:15:08.737602 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 12:15:08.740802 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 12:15:08.747542 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 12:15:08.750737 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 12:15:08.754028 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 12:15:08.760543 1 5 12 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
8369 12:15:08.763679 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8370 12:15:08.766984 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 12:15:08.773266 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 12:15:08.777267 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 12:15:08.779669 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 12:15:08.786656 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 12:15:08.790048 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 12:15:08.793290 1 6 12 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (0 0)
8377 12:15:08.799779 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8378 12:15:08.802999 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 12:15:08.806290 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 12:15:08.812725 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 12:15:08.815823 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 12:15:08.819614 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 12:15:08.825684 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 12:15:08.829305 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8385 12:15:08.832417 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8386 12:15:08.839486 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8387 12:15:08.842711 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 12:15:08.846110 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 12:15:08.852791 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 12:15:08.855768 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 12:15:08.859044 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 12:15:08.865924 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 12:15:08.868888 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 12:15:08.872209 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 12:15:08.879131 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 12:15:08.882071 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 12:15:08.885155 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 12:15:08.892093 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 12:15:08.895247 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 12:15:08.898484 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8401 12:15:08.904718 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8402 12:15:08.908397 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 12:15:08.911321 Total UI for P1: 0, mck2ui 16
8404 12:15:08.915087 best dqsien dly found for B0: ( 1, 9, 14)
8405 12:15:08.918031 Total UI for P1: 0, mck2ui 16
8406 12:15:08.921703 best dqsien dly found for B1: ( 1, 9, 14)
8407 12:15:08.924515 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8408 12:15:08.928276 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8409 12:15:08.928403
8410 12:15:08.931119 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8411 12:15:08.937784 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8412 12:15:08.937926 [Gating] SW calibration Done
8413 12:15:08.941407 ==
8414 12:15:08.941541 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 12:15:08.947867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 12:15:08.948005 ==
8417 12:15:08.948104 RX Vref Scan: 0
8418 12:15:08.948198
8419 12:15:08.950986 RX Vref 0 -> 0, step: 1
8420 12:15:08.951091
8421 12:15:08.954100 RX Delay 0 -> 252, step: 8
8422 12:15:08.957823 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8423 12:15:08.960968 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8424 12:15:08.964234 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8425 12:15:08.970937 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8426 12:15:08.974174 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8427 12:15:08.977433 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8428 12:15:08.980492 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8429 12:15:08.984232 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8430 12:15:08.990346 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8431 12:15:08.993841 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8432 12:15:08.997059 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8433 12:15:09.000448 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8434 12:15:09.007251 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8435 12:15:09.010323 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8436 12:15:09.013285 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8437 12:15:09.017015 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8438 12:15:09.017110 ==
8439 12:15:09.020006 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 12:15:09.026738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 12:15:09.026895 ==
8442 12:15:09.026996 DQS Delay:
8443 12:15:09.029796 DQS0 = 0, DQS1 = 0
8444 12:15:09.029922 DQM Delay:
8445 12:15:09.029994 DQM0 = 132, DQM1 = 125
8446 12:15:09.033558 DQ Delay:
8447 12:15:09.036365 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8448 12:15:09.040001 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8449 12:15:09.042919 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8450 12:15:09.046415 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8451 12:15:09.046517
8452 12:15:09.046604
8453 12:15:09.046704 ==
8454 12:15:09.049680 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 12:15:09.056352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 12:15:09.056488 ==
8457 12:15:09.056595
8458 12:15:09.056698
8459 12:15:09.056800 TX Vref Scan disable
8460 12:15:09.059531 == TX Byte 0 ==
8461 12:15:09.062515 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8462 12:15:09.069403 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8463 12:15:09.069546 == TX Byte 1 ==
8464 12:15:09.072581 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8465 12:15:09.079610 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8466 12:15:09.079739 ==
8467 12:15:09.082847 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 12:15:09.085598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 12:15:09.085727 ==
8470 12:15:09.098719
8471 12:15:09.102184 TX Vref early break, caculate TX vref
8472 12:15:09.105081 TX Vref=16, minBit 5, minWin=21, winSum=360
8473 12:15:09.108244 TX Vref=18, minBit 1, minWin=23, winSum=377
8474 12:15:09.111318 TX Vref=20, minBit 5, minWin=23, winSum=387
8475 12:15:09.114525 TX Vref=22, minBit 1, minWin=23, winSum=393
8476 12:15:09.118131 TX Vref=24, minBit 11, minWin=24, winSum=407
8477 12:15:09.124440 TX Vref=26, minBit 0, minWin=25, winSum=418
8478 12:15:09.127931 TX Vref=28, minBit 0, minWin=25, winSum=422
8479 12:15:09.131509 TX Vref=30, minBit 6, minWin=24, winSum=414
8480 12:15:09.134620 TX Vref=32, minBit 0, minWin=24, winSum=404
8481 12:15:09.137728 TX Vref=34, minBit 1, minWin=23, winSum=392
8482 12:15:09.144265 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8483 12:15:09.144415
8484 12:15:09.147804 Final TX Range 0 Vref 28
8485 12:15:09.147889
8486 12:15:09.147955 ==
8487 12:15:09.150702 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 12:15:09.154394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 12:15:09.154488 ==
8490 12:15:09.154555
8491 12:15:09.154617
8492 12:15:09.157636 TX Vref Scan disable
8493 12:15:09.164007 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8494 12:15:09.164129 == TX Byte 0 ==
8495 12:15:09.167330 u2DelayCellOfst[0]=22 cells (6 PI)
8496 12:15:09.170590 u2DelayCellOfst[1]=18 cells (5 PI)
8497 12:15:09.173776 u2DelayCellOfst[2]=0 cells (0 PI)
8498 12:15:09.177536 u2DelayCellOfst[3]=7 cells (2 PI)
8499 12:15:09.180758 u2DelayCellOfst[4]=11 cells (3 PI)
8500 12:15:09.184002 u2DelayCellOfst[5]=26 cells (7 PI)
8501 12:15:09.187217 u2DelayCellOfst[6]=22 cells (6 PI)
8502 12:15:09.190446 u2DelayCellOfst[7]=11 cells (3 PI)
8503 12:15:09.193690 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8504 12:15:09.197046 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8505 12:15:09.200241 == TX Byte 1 ==
8506 12:15:09.203536 u2DelayCellOfst[8]=0 cells (0 PI)
8507 12:15:09.206851 u2DelayCellOfst[9]=3 cells (1 PI)
8508 12:15:09.210218 u2DelayCellOfst[10]=11 cells (3 PI)
8509 12:15:09.213523 u2DelayCellOfst[11]=7 cells (2 PI)
8510 12:15:09.216781 u2DelayCellOfst[12]=15 cells (4 PI)
8511 12:15:09.216898 u2DelayCellOfst[13]=18 cells (5 PI)
8512 12:15:09.219999 u2DelayCellOfst[14]=18 cells (5 PI)
8513 12:15:09.223321 u2DelayCellOfst[15]=18 cells (5 PI)
8514 12:15:09.230070 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8515 12:15:09.233199 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8516 12:15:09.233323 DramC Write-DBI on
8517 12:15:09.236437 ==
8518 12:15:09.239977 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 12:15:09.243073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 12:15:09.243168 ==
8521 12:15:09.243237
8522 12:15:09.243300
8523 12:15:09.246281 TX Vref Scan disable
8524 12:15:09.246390 == TX Byte 0 ==
8525 12:15:09.252801 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8526 12:15:09.252911 == TX Byte 1 ==
8527 12:15:09.256767 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8528 12:15:09.259633 DramC Write-DBI off
8529 12:15:09.259750
8530 12:15:09.259820 [DATLAT]
8531 12:15:09.262784 Freq=1600, CH1 RK0
8532 12:15:09.262910
8533 12:15:09.263008 DATLAT Default: 0xf
8534 12:15:09.266026 0, 0xFFFF, sum = 0
8535 12:15:09.266115 1, 0xFFFF, sum = 0
8536 12:15:09.269833 2, 0xFFFF, sum = 0
8537 12:15:09.272762 3, 0xFFFF, sum = 0
8538 12:15:09.272851 4, 0xFFFF, sum = 0
8539 12:15:09.275806 5, 0xFFFF, sum = 0
8540 12:15:09.275897 6, 0xFFFF, sum = 0
8541 12:15:09.279873 7, 0xFFFF, sum = 0
8542 12:15:09.279964 8, 0xFFFF, sum = 0
8543 12:15:09.282969 9, 0xFFFF, sum = 0
8544 12:15:09.283055 10, 0xFFFF, sum = 0
8545 12:15:09.286234 11, 0xFFFF, sum = 0
8546 12:15:09.286359 12, 0xFFFF, sum = 0
8547 12:15:09.289571 13, 0x8FFF, sum = 0
8548 12:15:09.289697 14, 0x0, sum = 1
8549 12:15:09.292661 15, 0x0, sum = 2
8550 12:15:09.292781 16, 0x0, sum = 3
8551 12:15:09.295708 17, 0x0, sum = 4
8552 12:15:09.295801 best_step = 15
8553 12:15:09.295868
8554 12:15:09.295930 ==
8555 12:15:09.298900 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 12:15:09.305401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 12:15:09.305551 ==
8558 12:15:09.305654 RX Vref Scan: 1
8559 12:15:09.305748
8560 12:15:09.308642 Set Vref Range= 24 -> 127
8561 12:15:09.308746
8562 12:15:09.312355 RX Vref 24 -> 127, step: 1
8563 12:15:09.312466
8564 12:15:09.312561 RX Delay 11 -> 252, step: 4
8565 12:15:09.315739
8566 12:15:09.315848 Set Vref, RX VrefLevel [Byte0]: 24
8567 12:15:09.319118 [Byte1]: 24
8568 12:15:09.323038
8569 12:15:09.323141 Set Vref, RX VrefLevel [Byte0]: 25
8570 12:15:09.326204 [Byte1]: 25
8571 12:15:09.331025
8572 12:15:09.331135 Set Vref, RX VrefLevel [Byte0]: 26
8573 12:15:09.334134 [Byte1]: 26
8574 12:15:09.338385
8575 12:15:09.338534 Set Vref, RX VrefLevel [Byte0]: 27
8576 12:15:09.341347 [Byte1]: 27
8577 12:15:09.346134
8578 12:15:09.346280 Set Vref, RX VrefLevel [Byte0]: 28
8579 12:15:09.349258 [Byte1]: 28
8580 12:15:09.353668
8581 12:15:09.353809 Set Vref, RX VrefLevel [Byte0]: 29
8582 12:15:09.356788 [Byte1]: 29
8583 12:15:09.361080
8584 12:15:09.361183 Set Vref, RX VrefLevel [Byte0]: 30
8585 12:15:09.364187 [Byte1]: 30
8586 12:15:09.368901
8587 12:15:09.369031 Set Vref, RX VrefLevel [Byte0]: 31
8588 12:15:09.372132 [Byte1]: 31
8589 12:15:09.376648
8590 12:15:09.376753 Set Vref, RX VrefLevel [Byte0]: 32
8591 12:15:09.379843 [Byte1]: 32
8592 12:15:09.383746
8593 12:15:09.383880 Set Vref, RX VrefLevel [Byte0]: 33
8594 12:15:09.387048 [Byte1]: 33
8595 12:15:09.391504
8596 12:15:09.391611 Set Vref, RX VrefLevel [Byte0]: 34
8597 12:15:09.394629 [Byte1]: 34
8598 12:15:09.399172
8599 12:15:09.399274 Set Vref, RX VrefLevel [Byte0]: 35
8600 12:15:09.402433 [Byte1]: 35
8601 12:15:09.406970
8602 12:15:09.407087 Set Vref, RX VrefLevel [Byte0]: 36
8603 12:15:09.410030 [Byte1]: 36
8604 12:15:09.414278
8605 12:15:09.414382 Set Vref, RX VrefLevel [Byte0]: 37
8606 12:15:09.417888 [Byte1]: 37
8607 12:15:09.421973
8608 12:15:09.422071 Set Vref, RX VrefLevel [Byte0]: 38
8609 12:15:09.424984 [Byte1]: 38
8610 12:15:09.429386
8611 12:15:09.429484 Set Vref, RX VrefLevel [Byte0]: 39
8612 12:15:09.433300 [Byte1]: 39
8613 12:15:09.436966
8614 12:15:09.437074 Set Vref, RX VrefLevel [Byte0]: 40
8615 12:15:09.440675 [Byte1]: 40
8616 12:15:09.445086
8617 12:15:09.445187 Set Vref, RX VrefLevel [Byte0]: 41
8618 12:15:09.448026 [Byte1]: 41
8619 12:15:09.452203
8620 12:15:09.452328 Set Vref, RX VrefLevel [Byte0]: 42
8621 12:15:09.455925 [Byte1]: 42
8622 12:15:09.460065
8623 12:15:09.460192 Set Vref, RX VrefLevel [Byte0]: 43
8624 12:15:09.463133 [Byte1]: 43
8625 12:15:09.467914
8626 12:15:09.468050 Set Vref, RX VrefLevel [Byte0]: 44
8627 12:15:09.470935 [Byte1]: 44
8628 12:15:09.475668
8629 12:15:09.475798 Set Vref, RX VrefLevel [Byte0]: 45
8630 12:15:09.478653 [Byte1]: 45
8631 12:15:09.482656
8632 12:15:09.482786 Set Vref, RX VrefLevel [Byte0]: 46
8633 12:15:09.486132 [Byte1]: 46
8634 12:15:09.490528
8635 12:15:09.490632 Set Vref, RX VrefLevel [Byte0]: 47
8636 12:15:09.493680 [Byte1]: 47
8637 12:15:09.498112
8638 12:15:09.498246 Set Vref, RX VrefLevel [Byte0]: 48
8639 12:15:09.501286 [Byte1]: 48
8640 12:15:09.505842
8641 12:15:09.505980 Set Vref, RX VrefLevel [Byte0]: 49
8642 12:15:09.509200 [Byte1]: 49
8643 12:15:09.513113
8644 12:15:09.513240 Set Vref, RX VrefLevel [Byte0]: 50
8645 12:15:09.516399 [Byte1]: 50
8646 12:15:09.520867
8647 12:15:09.520971 Set Vref, RX VrefLevel [Byte0]: 51
8648 12:15:09.524173 [Byte1]: 51
8649 12:15:09.529024
8650 12:15:09.529160 Set Vref, RX VrefLevel [Byte0]: 52
8651 12:15:09.531597 [Byte1]: 52
8652 12:15:09.536190
8653 12:15:09.536302 Set Vref, RX VrefLevel [Byte0]: 53
8654 12:15:09.539425 [Byte1]: 53
8655 12:15:09.544054
8656 12:15:09.544193 Set Vref, RX VrefLevel [Byte0]: 54
8657 12:15:09.547595 [Byte1]: 54
8658 12:15:09.551441
8659 12:15:09.551543 Set Vref, RX VrefLevel [Byte0]: 55
8660 12:15:09.554765 [Byte1]: 55
8661 12:15:09.559288
8662 12:15:09.559393 Set Vref, RX VrefLevel [Byte0]: 56
8663 12:15:09.562460 [Byte1]: 56
8664 12:15:09.566760
8665 12:15:09.566909 Set Vref, RX VrefLevel [Byte0]: 57
8666 12:15:09.570130 [Byte1]: 57
8667 12:15:09.574536
8668 12:15:09.574653 Set Vref, RX VrefLevel [Byte0]: 58
8669 12:15:09.577536 [Byte1]: 58
8670 12:15:09.581681
8671 12:15:09.581813 Set Vref, RX VrefLevel [Byte0]: 59
8672 12:15:09.585503 [Byte1]: 59
8673 12:15:09.589340
8674 12:15:09.589442 Set Vref, RX VrefLevel [Byte0]: 60
8675 12:15:09.592750 [Byte1]: 60
8676 12:15:09.597065
8677 12:15:09.597174 Set Vref, RX VrefLevel [Byte0]: 61
8678 12:15:09.600178 [Byte1]: 61
8679 12:15:09.604730
8680 12:15:09.604889 Set Vref, RX VrefLevel [Byte0]: 62
8681 12:15:09.607811 [Byte1]: 62
8682 12:15:09.612684
8683 12:15:09.612812 Set Vref, RX VrefLevel [Byte0]: 63
8684 12:15:09.615978 [Byte1]: 63
8685 12:15:09.619977
8686 12:15:09.620094 Set Vref, RX VrefLevel [Byte0]: 64
8687 12:15:09.623326 [Byte1]: 64
8688 12:15:09.627369
8689 12:15:09.627522 Set Vref, RX VrefLevel [Byte0]: 65
8690 12:15:09.630711 [Byte1]: 65
8691 12:15:09.635515
8692 12:15:09.635649 Set Vref, RX VrefLevel [Byte0]: 66
8693 12:15:09.638265 [Byte1]: 66
8694 12:15:09.642957
8695 12:15:09.643076 Set Vref, RX VrefLevel [Byte0]: 67
8696 12:15:09.646372 [Byte1]: 67
8697 12:15:09.650414
8698 12:15:09.650545 Set Vref, RX VrefLevel [Byte0]: 68
8699 12:15:09.653746 [Byte1]: 68
8700 12:15:09.657741
8701 12:15:09.657872 Set Vref, RX VrefLevel [Byte0]: 69
8702 12:15:09.661621 [Byte1]: 69
8703 12:15:09.665506
8704 12:15:09.665610 Set Vref, RX VrefLevel [Byte0]: 70
8705 12:15:09.668883 [Byte1]: 70
8706 12:15:09.673177
8707 12:15:09.673277 Set Vref, RX VrefLevel [Byte0]: 71
8708 12:15:09.676600 [Byte1]: 71
8709 12:15:09.680645
8710 12:15:09.680739 Set Vref, RX VrefLevel [Byte0]: 72
8711 12:15:09.684111 [Byte1]: 72
8712 12:15:09.688490
8713 12:15:09.688592 Final RX Vref Byte 0 = 58 to rank0
8714 12:15:09.691845 Final RX Vref Byte 1 = 56 to rank0
8715 12:15:09.695445 Final RX Vref Byte 0 = 58 to rank1
8716 12:15:09.698184 Final RX Vref Byte 1 = 56 to rank1==
8717 12:15:09.701934 Dram Type= 6, Freq= 0, CH_1, rank 0
8718 12:15:09.708029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8719 12:15:09.708140 ==
8720 12:15:09.708208 DQS Delay:
8721 12:15:09.711310 DQS0 = 0, DQS1 = 0
8722 12:15:09.711396 DQM Delay:
8723 12:15:09.711461 DQM0 = 131, DQM1 = 123
8724 12:15:09.715054 DQ Delay:
8725 12:15:09.717787 DQ0 =136, DQ1 =128, DQ2 =120, DQ3 =126
8726 12:15:09.721633 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8727 12:15:09.724908 DQ8 =110, DQ9 =114, DQ10 =122, DQ11 =116
8728 12:15:09.728083 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8729 12:15:09.728177
8730 12:15:09.728243
8731 12:15:09.728306
8732 12:15:09.731506 [DramC_TX_OE_Calibration] TA2
8733 12:15:09.734591 Original DQ_B0 (3 6) =30, OEN = 27
8734 12:15:09.737716 Original DQ_B1 (3 6) =30, OEN = 27
8735 12:15:09.741158 24, 0x0, End_B0=24 End_B1=24
8736 12:15:09.744287 25, 0x0, End_B0=25 End_B1=25
8737 12:15:09.744378 26, 0x0, End_B0=26 End_B1=26
8738 12:15:09.747583 27, 0x0, End_B0=27 End_B1=27
8739 12:15:09.750786 28, 0x0, End_B0=28 End_B1=28
8740 12:15:09.753997 29, 0x0, End_B0=29 End_B1=29
8741 12:15:09.754088 30, 0x0, End_B0=30 End_B1=30
8742 12:15:09.757285 31, 0x5151, End_B0=30 End_B1=30
8743 12:15:09.761102 Byte0 end_step=30 best_step=27
8744 12:15:09.764332 Byte1 end_step=30 best_step=27
8745 12:15:09.767630 Byte0 TX OE(2T, 0.5T) = (3, 3)
8746 12:15:09.770762 Byte1 TX OE(2T, 0.5T) = (3, 3)
8747 12:15:09.770912
8748 12:15:09.771010
8749 12:15:09.777286 [DQSOSCAuto] RK0, (LSB)MR18= 0x70d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8750 12:15:09.780392 CH1 RK0: MR19=303, MR18=70D
8751 12:15:09.787159 CH1_RK0: MR19=0x303, MR18=0x70D, DQSOSC=403, MR23=63, INC=22, DEC=15
8752 12:15:09.787270
8753 12:15:09.790646 ----->DramcWriteLeveling(PI) begin...
8754 12:15:09.790762 ==
8755 12:15:09.794130 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 12:15:09.797131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 12:15:09.797221 ==
8758 12:15:09.800658 Write leveling (Byte 0): 24 => 24
8759 12:15:09.803618 Write leveling (Byte 1): 26 => 26
8760 12:15:09.807194 DramcWriteLeveling(PI) end<-----
8761 12:15:09.807291
8762 12:15:09.807357 ==
8763 12:15:09.810343 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 12:15:09.813729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 12:15:09.816796 ==
8766 12:15:09.816888 [Gating] SW mode calibration
8767 12:15:09.827285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8768 12:15:09.830260 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8769 12:15:09.833576 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 12:15:09.840258 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 12:15:09.843603 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8772 12:15:09.847114 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
8773 12:15:09.853272 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 12:15:09.856609 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 12:15:09.859957 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 12:15:09.866632 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 12:15:09.869802 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 12:15:09.873147 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8779 12:15:09.879176 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
8780 12:15:09.882459 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8781 12:15:09.888888 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 12:15:09.892662 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 12:15:09.895837 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 12:15:09.902367 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 12:15:09.905903 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 12:15:09.908812 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 12:15:09.915902 1 6 8 | B1->B0 | 2929 4343 | 1 0 | (0 0) (0 0)
8788 12:15:09.918645 1 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8789 12:15:09.921781 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 12:15:09.929136 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 12:15:09.932083 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 12:15:09.935305 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 12:15:09.938375 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 12:15:09.945553 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 12:15:09.948612 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8796 12:15:09.951587 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8797 12:15:09.958674 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 12:15:09.961765 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 12:15:09.965058 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 12:15:09.971383 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 12:15:09.974591 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 12:15:09.978477 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 12:15:09.984959 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 12:15:09.988096 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 12:15:09.991357 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 12:15:09.997982 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 12:15:10.001139 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 12:15:10.004511 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 12:15:10.010854 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 12:15:10.014682 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 12:15:10.017801 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8812 12:15:10.024344 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8813 12:15:10.027570 Total UI for P1: 0, mck2ui 16
8814 12:15:10.030656 best dqsien dly found for B0: ( 1, 9, 8)
8815 12:15:10.034554 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 12:15:10.037687 Total UI for P1: 0, mck2ui 16
8817 12:15:10.040729 best dqsien dly found for B1: ( 1, 9, 12)
8818 12:15:10.043938 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8819 12:15:10.046958 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8820 12:15:10.047056
8821 12:15:10.050802 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8822 12:15:10.057256 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8823 12:15:10.057373 [Gating] SW calibration Done
8824 12:15:10.057441 ==
8825 12:15:10.060425 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 12:15:10.066838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 12:15:10.066956 ==
8828 12:15:10.067026 RX Vref Scan: 0
8829 12:15:10.067093
8830 12:15:10.070097 RX Vref 0 -> 0, step: 1
8831 12:15:10.070179
8832 12:15:10.073770 RX Delay 0 -> 252, step: 8
8833 12:15:10.076710 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8834 12:15:10.080025 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8835 12:15:10.083435 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8836 12:15:10.090285 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8837 12:15:10.093603 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8838 12:15:10.096540 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8839 12:15:10.099785 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8840 12:15:10.103557 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8841 12:15:10.109828 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8842 12:15:10.113345 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8843 12:15:10.116486 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8844 12:15:10.119533 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8845 12:15:10.126380 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8846 12:15:10.129738 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8847 12:15:10.132874 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8848 12:15:10.136506 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8849 12:15:10.136612 ==
8850 12:15:10.139654 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 12:15:10.142852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 12:15:10.146098 ==
8853 12:15:10.146201 DQS Delay:
8854 12:15:10.146271 DQS0 = 0, DQS1 = 0
8855 12:15:10.149209 DQM Delay:
8856 12:15:10.149297 DQM0 = 128, DQM1 = 128
8857 12:15:10.152622 DQ Delay:
8858 12:15:10.156315 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =123
8859 12:15:10.159781 DQ4 =123, DQ5 =139, DQ6 =143, DQ7 =127
8860 12:15:10.162692 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8861 12:15:10.165959 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =139
8862 12:15:10.166124
8863 12:15:10.166247
8864 12:15:10.166361 ==
8865 12:15:10.169244 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 12:15:10.172873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 12:15:10.175811 ==
8868 12:15:10.175907
8869 12:15:10.175974
8870 12:15:10.176034 TX Vref Scan disable
8871 12:15:10.179023 == TX Byte 0 ==
8872 12:15:10.182735 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8873 12:15:10.186081 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8874 12:15:10.189313 == TX Byte 1 ==
8875 12:15:10.192604 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8876 12:15:10.195817 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8877 12:15:10.198940 ==
8878 12:15:10.202077 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 12:15:10.205845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 12:15:10.205951 ==
8881 12:15:10.218597
8882 12:15:10.222176 TX Vref early break, caculate TX vref
8883 12:15:10.225073 TX Vref=16, minBit 0, minWin=22, winSum=388
8884 12:15:10.228948 TX Vref=18, minBit 0, minWin=23, winSum=396
8885 12:15:10.231995 TX Vref=20, minBit 0, minWin=23, winSum=406
8886 12:15:10.234954 TX Vref=22, minBit 0, minWin=23, winSum=411
8887 12:15:10.238687 TX Vref=24, minBit 0, minWin=25, winSum=420
8888 12:15:10.245226 TX Vref=26, minBit 0, minWin=24, winSum=425
8889 12:15:10.248421 TX Vref=28, minBit 5, minWin=25, winSum=426
8890 12:15:10.251553 TX Vref=30, minBit 1, minWin=24, winSum=422
8891 12:15:10.254717 TX Vref=32, minBit 1, minWin=24, winSum=415
8892 12:15:10.258389 TX Vref=34, minBit 0, minWin=23, winSum=405
8893 12:15:10.264643 TX Vref=36, minBit 1, minWin=23, winSum=396
8894 12:15:10.268350 [TxChooseVref] Worse bit 5, Min win 25, Win sum 426, Final Vref 28
8895 12:15:10.268463
8896 12:15:10.271513 Final TX Range 0 Vref 28
8897 12:15:10.271603
8898 12:15:10.271689 ==
8899 12:15:10.275005 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 12:15:10.277841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 12:15:10.281041 ==
8902 12:15:10.281139
8903 12:15:10.281229
8904 12:15:10.281309 TX Vref Scan disable
8905 12:15:10.288435 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8906 12:15:10.288555 == TX Byte 0 ==
8907 12:15:10.291456 u2DelayCellOfst[0]=18 cells (5 PI)
8908 12:15:10.294873 u2DelayCellOfst[1]=15 cells (4 PI)
8909 12:15:10.297874 u2DelayCellOfst[2]=0 cells (0 PI)
8910 12:15:10.301061 u2DelayCellOfst[3]=7 cells (2 PI)
8911 12:15:10.304644 u2DelayCellOfst[4]=7 cells (2 PI)
8912 12:15:10.308036 u2DelayCellOfst[5]=22 cells (6 PI)
8913 12:15:10.311031 u2DelayCellOfst[6]=22 cells (6 PI)
8914 12:15:10.314408 u2DelayCellOfst[7]=7 cells (2 PI)
8915 12:15:10.317873 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8916 12:15:10.321397 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8917 12:15:10.324225 == TX Byte 1 ==
8918 12:15:10.327195 u2DelayCellOfst[8]=0 cells (0 PI)
8919 12:15:10.330773 u2DelayCellOfst[9]=7 cells (2 PI)
8920 12:15:10.334144 u2DelayCellOfst[10]=15 cells (4 PI)
8921 12:15:10.337288 u2DelayCellOfst[11]=7 cells (2 PI)
8922 12:15:10.340655 u2DelayCellOfst[12]=15 cells (4 PI)
8923 12:15:10.343820 u2DelayCellOfst[13]=22 cells (6 PI)
8924 12:15:10.347294 u2DelayCellOfst[14]=18 cells (5 PI)
8925 12:15:10.350228 u2DelayCellOfst[15]=18 cells (5 PI)
8926 12:15:10.353799 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8927 12:15:10.356991 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8928 12:15:10.360828 DramC Write-DBI on
8929 12:15:10.360937 ==
8930 12:15:10.363807 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 12:15:10.366877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 12:15:10.367002 ==
8933 12:15:10.367134
8934 12:15:10.367215
8935 12:15:10.370014 TX Vref Scan disable
8936 12:15:10.370117 == TX Byte 0 ==
8937 12:15:10.376940 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8938 12:15:10.377054 == TX Byte 1 ==
8939 12:15:10.383356 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8940 12:15:10.383475 DramC Write-DBI off
8941 12:15:10.383566
8942 12:15:10.383647 [DATLAT]
8943 12:15:10.386857 Freq=1600, CH1 RK1
8944 12:15:10.386962
8945 12:15:10.389819 DATLAT Default: 0xf
8946 12:15:10.389924 0, 0xFFFF, sum = 0
8947 12:15:10.392890 1, 0xFFFF, sum = 0
8948 12:15:10.392985 2, 0xFFFF, sum = 0
8949 12:15:10.396886 3, 0xFFFF, sum = 0
8950 12:15:10.396980 4, 0xFFFF, sum = 0
8951 12:15:10.399845 5, 0xFFFF, sum = 0
8952 12:15:10.399941 6, 0xFFFF, sum = 0
8953 12:15:10.403276 7, 0xFFFF, sum = 0
8954 12:15:10.403377 8, 0xFFFF, sum = 0
8955 12:15:10.406291 9, 0xFFFF, sum = 0
8956 12:15:10.406383 10, 0xFFFF, sum = 0
8957 12:15:10.409303 11, 0xFFFF, sum = 0
8958 12:15:10.409396 12, 0xFFFF, sum = 0
8959 12:15:10.412453 13, 0x8FFF, sum = 0
8960 12:15:10.412544 14, 0x0, sum = 1
8961 12:15:10.416212 15, 0x0, sum = 2
8962 12:15:10.416309 16, 0x0, sum = 3
8963 12:15:10.419373 17, 0x0, sum = 4
8964 12:15:10.419465 best_step = 15
8965 12:15:10.419552
8966 12:15:10.419633 ==
8967 12:15:10.422591 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 12:15:10.429988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 12:15:10.430111 ==
8970 12:15:10.430205 RX Vref Scan: 0
8971 12:15:10.430287
8972 12:15:10.432916 RX Vref 0 -> 0, step: 1
8973 12:15:10.433004
8974 12:15:10.436152 RX Delay 3 -> 252, step: 4
8975 12:15:10.439515 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8976 12:15:10.442454 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8977 12:15:10.449361 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8978 12:15:10.452467 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8979 12:15:10.455471 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8980 12:15:10.459031 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8981 12:15:10.462094 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8982 12:15:10.468765 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8983 12:15:10.471887 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8984 12:15:10.475462 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8985 12:15:10.479110 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8986 12:15:10.482115 iDelay=195, Bit 11, Center 122 (67 ~ 178) 112
8987 12:15:10.488819 iDelay=195, Bit 12, Center 134 (79 ~ 190) 112
8988 12:15:10.491765 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8989 12:15:10.495186 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8990 12:15:10.498852 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8991 12:15:10.498963 ==
8992 12:15:10.502336 Dram Type= 6, Freq= 0, CH_1, rank 1
8993 12:15:10.508445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8994 12:15:10.508565 ==
8995 12:15:10.508661 DQS Delay:
8996 12:15:10.511610 DQS0 = 0, DQS1 = 0
8997 12:15:10.511701 DQM Delay:
8998 12:15:10.514691 DQM0 = 128, DQM1 = 125
8999 12:15:10.514814 DQ Delay:
9000 12:15:10.518467 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =126
9001 12:15:10.521606 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9002 12:15:10.524765 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =122
9003 12:15:10.528189 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =134
9004 12:15:10.528285
9005 12:15:10.528351
9006 12:15:10.528412
9007 12:15:10.531244 [DramC_TX_OE_Calibration] TA2
9008 12:15:10.534478 Original DQ_B0 (3 6) =30, OEN = 27
9009 12:15:10.538210 Original DQ_B1 (3 6) =30, OEN = 27
9010 12:15:10.541592 24, 0x0, End_B0=24 End_B1=24
9011 12:15:10.544566 25, 0x0, End_B0=25 End_B1=25
9012 12:15:10.544666 26, 0x0, End_B0=26 End_B1=26
9013 12:15:10.547856 27, 0x0, End_B0=27 End_B1=27
9014 12:15:10.550791 28, 0x0, End_B0=28 End_B1=28
9015 12:15:10.554641 29, 0x0, End_B0=29 End_B1=29
9016 12:15:10.557694 30, 0x0, End_B0=30 End_B1=30
9017 12:15:10.557791 31, 0x4545, End_B0=30 End_B1=30
9018 12:15:10.561168 Byte0 end_step=30 best_step=27
9019 12:15:10.564352 Byte1 end_step=30 best_step=27
9020 12:15:10.567972 Byte0 TX OE(2T, 0.5T) = (3, 3)
9021 12:15:10.570994 Byte1 TX OE(2T, 0.5T) = (3, 3)
9022 12:15:10.571110
9023 12:15:10.571178
9024 12:15:10.577704 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9025 12:15:10.580880 CH1 RK1: MR19=303, MR18=F1B
9026 12:15:10.587741 CH1_RK1: MR19=0x303, MR18=0xF1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9027 12:15:10.591017 [RxdqsGatingPostProcess] freq 1600
9028 12:15:10.597476 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9029 12:15:10.597594 best DQS0 dly(2T, 0.5T) = (1, 1)
9030 12:15:10.600607 best DQS1 dly(2T, 0.5T) = (1, 1)
9031 12:15:10.603894 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9032 12:15:10.607100 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9033 12:15:10.610217 best DQS0 dly(2T, 0.5T) = (1, 1)
9034 12:15:10.613602 best DQS1 dly(2T, 0.5T) = (1, 1)
9035 12:15:10.617229 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9036 12:15:10.620549 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9037 12:15:10.623571 Pre-setting of DQS Precalculation
9038 12:15:10.627329 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9039 12:15:10.637113 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9040 12:15:10.643328 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9041 12:15:10.643457
9042 12:15:10.643526
9043 12:15:10.647040 [Calibration Summary] 3200 Mbps
9044 12:15:10.647128 CH 0, Rank 0
9045 12:15:10.650141 SW Impedance : PASS
9046 12:15:10.650229 DUTY Scan : NO K
9047 12:15:10.653396 ZQ Calibration : PASS
9048 12:15:10.656844 Jitter Meter : NO K
9049 12:15:10.656936 CBT Training : PASS
9050 12:15:10.659852 Write leveling : PASS
9051 12:15:10.663637 RX DQS gating : PASS
9052 12:15:10.663729 RX DQ/DQS(RDDQC) : PASS
9053 12:15:10.666844 TX DQ/DQS : PASS
9054 12:15:10.669757 RX DATLAT : PASS
9055 12:15:10.669861 RX DQ/DQS(Engine): PASS
9056 12:15:10.672958 TX OE : PASS
9057 12:15:10.673047 All Pass.
9058 12:15:10.673112
9059 12:15:10.676659 CH 0, Rank 1
9060 12:15:10.676745 SW Impedance : PASS
9061 12:15:10.679641 DUTY Scan : NO K
9062 12:15:10.683171 ZQ Calibration : PASS
9063 12:15:10.683285 Jitter Meter : NO K
9064 12:15:10.686271 CBT Training : PASS
9065 12:15:10.689434 Write leveling : PASS
9066 12:15:10.689548 RX DQS gating : PASS
9067 12:15:10.693138 RX DQ/DQS(RDDQC) : PASS
9068 12:15:10.696460 TX DQ/DQS : PASS
9069 12:15:10.696551 RX DATLAT : PASS
9070 12:15:10.699752 RX DQ/DQS(Engine): PASS
9071 12:15:10.702855 TX OE : PASS
9072 12:15:10.702967 All Pass.
9073 12:15:10.703034
9074 12:15:10.703094 CH 1, Rank 0
9075 12:15:10.706242 SW Impedance : PASS
9076 12:15:10.709456 DUTY Scan : NO K
9077 12:15:10.709544 ZQ Calibration : PASS
9078 12:15:10.712636 Jitter Meter : NO K
9079 12:15:10.712722 CBT Training : PASS
9080 12:15:10.715856 Write leveling : PASS
9081 12:15:10.719536 RX DQS gating : PASS
9082 12:15:10.719623 RX DQ/DQS(RDDQC) : PASS
9083 12:15:10.722647 TX DQ/DQS : PASS
9084 12:15:10.726092 RX DATLAT : PASS
9085 12:15:10.726186 RX DQ/DQS(Engine): PASS
9086 12:15:10.729263 TX OE : PASS
9087 12:15:10.729348 All Pass.
9088 12:15:10.729414
9089 12:15:10.732465 CH 1, Rank 1
9090 12:15:10.732549 SW Impedance : PASS
9091 12:15:10.736132 DUTY Scan : NO K
9092 12:15:10.739089 ZQ Calibration : PASS
9093 12:15:10.739176 Jitter Meter : NO K
9094 12:15:10.742791 CBT Training : PASS
9095 12:15:10.746077 Write leveling : PASS
9096 12:15:10.746165 RX DQS gating : PASS
9097 12:15:10.748998 RX DQ/DQS(RDDQC) : PASS
9098 12:15:10.752778 TX DQ/DQS : PASS
9099 12:15:10.752870 RX DATLAT : PASS
9100 12:15:10.755848 RX DQ/DQS(Engine): PASS
9101 12:15:10.758983 TX OE : PASS
9102 12:15:10.759071 All Pass.
9103 12:15:10.759136
9104 12:15:10.759196 DramC Write-DBI on
9105 12:15:10.762142 PER_BANK_REFRESH: Hybrid Mode
9106 12:15:10.765389 TX_TRACKING: ON
9107 12:15:10.772424 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9108 12:15:10.782117 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9109 12:15:10.788882 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9110 12:15:10.791887 [FAST_K] Save calibration result to emmc
9111 12:15:10.795059 sync common calibartion params.
9112 12:15:10.798723 sync cbt_mode0:1, 1:1
9113 12:15:10.798816 dram_init: ddr_geometry: 2
9114 12:15:10.802098 dram_init: ddr_geometry: 2
9115 12:15:10.805146 dram_init: ddr_geometry: 2
9116 12:15:10.808252 0:dram_rank_size:100000000
9117 12:15:10.808348 1:dram_rank_size:100000000
9118 12:15:10.814628 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9119 12:15:10.818487 DFS_SHUFFLE_HW_MODE: ON
9120 12:15:10.821808 dramc_set_vcore_voltage set vcore to 725000
9121 12:15:10.821905 Read voltage for 1600, 0
9122 12:15:10.824978 Vio18 = 0
9123 12:15:10.825098 Vcore = 725000
9124 12:15:10.825190 Vdram = 0
9125 12:15:10.828394 Vddq = 0
9126 12:15:10.828506 Vmddr = 0
9127 12:15:10.831668 switch to 3200 Mbps bootup
9128 12:15:10.831784 [DramcRunTimeConfig]
9129 12:15:10.834895 PHYPLL
9130 12:15:10.834981 DPM_CONTROL_AFTERK: ON
9131 12:15:10.837723 PER_BANK_REFRESH: ON
9132 12:15:10.841474 REFRESH_OVERHEAD_REDUCTION: ON
9133 12:15:10.841572 CMD_PICG_NEW_MODE: OFF
9134 12:15:10.845132 XRTWTW_NEW_MODE: ON
9135 12:15:10.845218 XRTRTR_NEW_MODE: ON
9136 12:15:10.847651 TX_TRACKING: ON
9137 12:15:10.847739 RDSEL_TRACKING: OFF
9138 12:15:10.851279 DQS Precalculation for DVFS: ON
9139 12:15:10.854166 RX_TRACKING: OFF
9140 12:15:10.854277 HW_GATING DBG: ON
9141 12:15:10.857868 ZQCS_ENABLE_LP4: ON
9142 12:15:10.857958 RX_PICG_NEW_MODE: ON
9143 12:15:10.860868 TX_PICG_NEW_MODE: ON
9144 12:15:10.860955 ENABLE_RX_DCM_DPHY: ON
9145 12:15:10.864637 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9146 12:15:10.867902 DUMMY_READ_FOR_TRACKING: OFF
9147 12:15:10.871265 !!! SPM_CONTROL_AFTERK: OFF
9148 12:15:10.874510 !!! SPM could not control APHY
9149 12:15:10.874600 IMPEDANCE_TRACKING: ON
9150 12:15:10.877454 TEMP_SENSOR: ON
9151 12:15:10.877541 HW_SAVE_FOR_SR: OFF
9152 12:15:10.880601 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9153 12:15:10.883716 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9154 12:15:10.887250 Read ODT Tracking: ON
9155 12:15:10.891083 Refresh Rate DeBounce: ON
9156 12:15:10.891180 DFS_NO_QUEUE_FLUSH: ON
9157 12:15:10.893838 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9158 12:15:10.897399 ENABLE_DFS_RUNTIME_MRW: OFF
9159 12:15:10.900385 DDR_RESERVE_NEW_MODE: ON
9160 12:15:10.900475 MR_CBT_SWITCH_FREQ: ON
9161 12:15:10.903806 =========================
9162 12:15:10.923105 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9163 12:15:10.926071 dram_init: ddr_geometry: 2
9164 12:15:10.944635 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9165 12:15:10.947604 dram_init: dram init end (result: 0)
9166 12:15:10.954281 DRAM-K: Full calibration passed in 24582 msecs
9167 12:15:10.958338 MRC: failed to locate region type 0.
9168 12:15:10.958448 DRAM rank0 size:0x100000000,
9169 12:15:10.960894 DRAM rank1 size=0x100000000
9170 12:15:10.970619 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9171 12:15:10.977751 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9172 12:15:10.984044 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9173 12:15:10.994362 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9174 12:15:10.994497 DRAM rank0 size:0x100000000,
9175 12:15:10.997399 DRAM rank1 size=0x100000000
9176 12:15:10.997488 CBMEM:
9177 12:15:11.000584 IMD: root @ 0xfffff000 254 entries.
9178 12:15:11.003992 IMD: root @ 0xffffec00 62 entries.
9179 12:15:11.007196 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9180 12:15:11.013561 WARNING: RO_VPD is uninitialized or empty.
9181 12:15:11.016585 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9182 12:15:11.024682 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9183 12:15:11.037341 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9184 12:15:11.049011 BS: romstage times (exec / console): total (unknown) / 24046 ms
9185 12:15:11.049179
9186 12:15:11.049281
9187 12:15:11.058330 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9188 12:15:11.061479 ARM64: Exception handlers installed.
9189 12:15:11.065292 ARM64: Testing exception
9190 12:15:11.068520 ARM64: Done test exception
9191 12:15:11.068617 Enumerating buses...
9192 12:15:11.071387 Show all devs... Before device enumeration.
9193 12:15:11.074588 Root Device: enabled 1
9194 12:15:11.078377 CPU_CLUSTER: 0: enabled 1
9195 12:15:11.078507 CPU: 00: enabled 1
9196 12:15:11.081592 Compare with tree...
9197 12:15:11.081701 Root Device: enabled 1
9198 12:15:11.084726 CPU_CLUSTER: 0: enabled 1
9199 12:15:11.087963 CPU: 00: enabled 1
9200 12:15:11.088090 Root Device scanning...
9201 12:15:11.091472 scan_static_bus for Root Device
9202 12:15:11.094310 CPU_CLUSTER: 0 enabled
9203 12:15:11.098151 scan_static_bus for Root Device done
9204 12:15:11.101105 scan_bus: bus Root Device finished in 8 msecs
9205 12:15:11.101224 done
9206 12:15:11.107636 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9207 12:15:11.111417 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9208 12:15:11.117997 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9209 12:15:11.124213 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9210 12:15:11.124337 Allocating resources...
9211 12:15:11.127287 Reading resources...
9212 12:15:11.131354 Root Device read_resources bus 0 link: 0
9213 12:15:11.134236 DRAM rank0 size:0x100000000,
9214 12:15:11.134333 DRAM rank1 size=0x100000000
9215 12:15:11.140760 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9216 12:15:11.140900 CPU: 00 missing read_resources
9217 12:15:11.146847 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9218 12:15:11.151126 Root Device read_resources bus 0 link: 0 done
9219 12:15:11.154054 Done reading resources.
9220 12:15:11.157277 Show resources in subtree (Root Device)...After reading.
9221 12:15:11.160809 Root Device child on link 0 CPU_CLUSTER: 0
9222 12:15:11.163737 CPU_CLUSTER: 0 child on link 0 CPU: 00
9223 12:15:11.173834 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9224 12:15:11.173970 CPU: 00
9225 12:15:11.180153 Root Device assign_resources, bus 0 link: 0
9226 12:15:11.183577 CPU_CLUSTER: 0 missing set_resources
9227 12:15:11.186762 Root Device assign_resources, bus 0 link: 0 done
9228 12:15:11.190482 Done setting resources.
9229 12:15:11.193434 Show resources in subtree (Root Device)...After assigning values.
9230 12:15:11.199928 Root Device child on link 0 CPU_CLUSTER: 0
9231 12:15:11.202887 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 12:15:11.209831 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 12:15:11.213137 CPU: 00
9234 12:15:11.213246 Done allocating resources.
9235 12:15:11.219743 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9236 12:15:11.223195 Enabling resources...
9237 12:15:11.223302 done.
9238 12:15:11.226309 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9239 12:15:11.229980 Initializing devices...
9240 12:15:11.230078 Root Device init
9241 12:15:11.233227 init hardware done!
9242 12:15:11.236391 0x00000018: ctrlr->caps
9243 12:15:11.236498 52.000 MHz: ctrlr->f_max
9244 12:15:11.239352 0.400 MHz: ctrlr->f_min
9245 12:15:11.242382 0x40ff8080: ctrlr->voltages
9246 12:15:11.242463 sclk: 390625
9247 12:15:11.242526 Bus Width = 1
9248 12:15:11.246220 sclk: 390625
9249 12:15:11.246316 Bus Width = 1
9250 12:15:11.249431 Early init status = 3
9251 12:15:11.252659 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9252 12:15:11.256510 in-header: 03 fc 00 00 01 00 00 00
9253 12:15:11.259585 in-data: 00
9254 12:15:11.262872 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9255 12:15:11.267978 in-header: 03 fd 00 00 00 00 00 00
9256 12:15:11.271145 in-data:
9257 12:15:11.274238 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9258 12:15:11.277988 in-header: 03 fc 00 00 01 00 00 00
9259 12:15:11.281805 in-data: 00
9260 12:15:11.284739 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9261 12:15:11.290409 in-header: 03 fd 00 00 00 00 00 00
9262 12:15:11.293856 in-data:
9263 12:15:11.296833 [SSUSB] Setting up USB HOST controller...
9264 12:15:11.300089 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9265 12:15:11.303887 [SSUSB] phy power-on done.
9266 12:15:11.307053 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9267 12:15:11.314175 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9268 12:15:11.317142 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9269 12:15:11.323581 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9270 12:15:11.330168 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9271 12:15:11.336775 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9272 12:15:11.343426 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9273 12:15:11.349854 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9274 12:15:11.353156 SPM: binary array size = 0x9dc
9275 12:15:11.356171 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9276 12:15:11.362623 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9277 12:15:11.369942 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9278 12:15:11.376398 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9279 12:15:11.379751 configure_display: Starting display init
9280 12:15:11.413807 anx7625_power_on_init: Init interface.
9281 12:15:11.416998 anx7625_disable_pd_protocol: Disabled PD feature.
9282 12:15:11.419979 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9283 12:15:11.448105 anx7625_start_dp_work: Secure OCM version=00
9284 12:15:11.451269 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9285 12:15:11.466336 sp_tx_get_edid_block: EDID Block = 1
9286 12:15:11.568629 Extracted contents:
9287 12:15:11.572070 header: 00 ff ff ff ff ff ff 00
9288 12:15:11.575183 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9289 12:15:11.578817 version: 01 04
9290 12:15:11.581823 basic params: 95 1f 11 78 0a
9291 12:15:11.585055 chroma info: 76 90 94 55 54 90 27 21 50 54
9292 12:15:11.588565 established: 00 00 00
9293 12:15:11.594696 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9294 12:15:11.602001 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9295 12:15:11.604966 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9296 12:15:11.611544 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9297 12:15:11.618400 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9298 12:15:11.621413 extensions: 00
9299 12:15:11.621510 checksum: fb
9300 12:15:11.621574
9301 12:15:11.627910 Manufacturer: IVO Model 57d Serial Number 0
9302 12:15:11.628006 Made week 0 of 2020
9303 12:15:11.631125 EDID version: 1.4
9304 12:15:11.631215 Digital display
9305 12:15:11.634293 6 bits per primary color channel
9306 12:15:11.634380 DisplayPort interface
9307 12:15:11.638167 Maximum image size: 31 cm x 17 cm
9308 12:15:11.641128 Gamma: 220%
9309 12:15:11.641216 Check DPMS levels
9310 12:15:11.647678 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9311 12:15:11.651052 First detailed timing is preferred timing
9312 12:15:11.651145 Established timings supported:
9313 12:15:11.654043 Standard timings supported:
9314 12:15:11.657346 Detailed timings
9315 12:15:11.660607 Hex of detail: 383680a07038204018303c0035ae10000019
9316 12:15:11.667498 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9317 12:15:11.670719 0780 0798 07c8 0820 hborder 0
9318 12:15:11.673966 0438 043b 0447 0458 vborder 0
9319 12:15:11.677202 -hsync -vsync
9320 12:15:11.677291 Did detailed timing
9321 12:15:11.683584 Hex of detail: 000000000000000000000000000000000000
9322 12:15:11.687493 Manufacturer-specified data, tag 0
9323 12:15:11.690721 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9324 12:15:11.694267 ASCII string: InfoVision
9325 12:15:11.697289 Hex of detail: 000000fe00523134304e574635205248200a
9326 12:15:11.700444 ASCII string: R140NWF5 RH
9327 12:15:11.700533 Checksum
9328 12:15:11.703609 Checksum: 0xfb (valid)
9329 12:15:11.706723 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9330 12:15:11.710211 DSI data_rate: 832800000 bps
9331 12:15:11.716798 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9332 12:15:11.720050 anx7625_parse_edid: pixelclock(138800).
9333 12:15:11.723197 hactive(1920), hsync(48), hfp(24), hbp(88)
9334 12:15:11.726698 vactive(1080), vsync(12), vfp(3), vbp(17)
9335 12:15:11.729828 anx7625_dsi_config: config dsi.
9336 12:15:11.736259 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9337 12:15:11.750533 anx7625_dsi_config: success to config DSI
9338 12:15:11.753632 anx7625_dp_start: MIPI phy setup OK.
9339 12:15:11.757597 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9340 12:15:11.760809 mtk_ddp_mode_set invalid vrefresh 60
9341 12:15:11.764026 main_disp_path_setup
9342 12:15:11.764119 ovl_layer_smi_id_en
9343 12:15:11.766960 ovl_layer_smi_id_en
9344 12:15:11.767046 ccorr_config
9345 12:15:11.767111 aal_config
9346 12:15:11.771018 gamma_config
9347 12:15:11.771105 postmask_config
9348 12:15:11.773526 dither_config
9349 12:15:11.777026 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9350 12:15:11.783310 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9351 12:15:11.786668 Root Device init finished in 553 msecs
9352 12:15:11.789888 CPU_CLUSTER: 0 init
9353 12:15:11.796978 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9354 12:15:11.803429 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9355 12:15:11.803545 APU_MBOX 0x190000b0 = 0x10001
9356 12:15:11.806314 APU_MBOX 0x190001b0 = 0x10001
9357 12:15:11.809643 APU_MBOX 0x190005b0 = 0x10001
9358 12:15:11.812893 APU_MBOX 0x190006b0 = 0x10001
9359 12:15:11.819405 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9360 12:15:11.829606 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9361 12:15:11.842105 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9362 12:15:11.848212 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9363 12:15:11.860053 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9364 12:15:11.869137 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9365 12:15:11.872893 CPU_CLUSTER: 0 init finished in 81 msecs
9366 12:15:11.876067 Devices initialized
9367 12:15:11.879085 Show all devs... After init.
9368 12:15:11.879204 Root Device: enabled 1
9369 12:15:11.882320 CPU_CLUSTER: 0: enabled 1
9370 12:15:11.885571 CPU: 00: enabled 1
9371 12:15:11.889406 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9372 12:15:11.892576 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9373 12:15:11.895873 ELOG: NV offset 0x57f000 size 0x1000
9374 12:15:11.902700 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9375 12:15:11.908701 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9376 12:15:11.912513 ELOG: Event(17) added with size 13 at 2023-06-06 12:15:17 UTC
9377 12:15:11.919216 out: cmd=0x121: 03 db 21 01 00 00 00 00
9378 12:15:11.922406 in-header: 03 4b 00 00 2c 00 00 00
9379 12:15:11.932124 in-data: 13 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9380 12:15:11.938638 ELOG: Event(A1) added with size 10 at 2023-06-06 12:15:17 UTC
9381 12:15:11.945082 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9382 12:15:11.952080 ELOG: Event(A0) added with size 9 at 2023-06-06 12:15:17 UTC
9383 12:15:11.955050 elog_add_boot_reason: Logged dev mode boot
9384 12:15:11.962016 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9385 12:15:11.962134 Finalize devices...
9386 12:15:11.965205 Devices finalized
9387 12:15:11.968505 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9388 12:15:11.972133 Writing coreboot table at 0xffe64000
9389 12:15:11.975196 0. 000000000010a000-0000000000113fff: RAMSTAGE
9390 12:15:11.981344 1. 0000000040000000-00000000400fffff: RAM
9391 12:15:11.985040 2. 0000000040100000-000000004032afff: RAMSTAGE
9392 12:15:11.988104 3. 000000004032b000-00000000545fffff: RAM
9393 12:15:11.991613 4. 0000000054600000-000000005465ffff: BL31
9394 12:15:11.994783 5. 0000000054660000-00000000ffe63fff: RAM
9395 12:15:12.001200 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9396 12:15:12.004561 7. 0000000100000000-000000023fffffff: RAM
9397 12:15:12.007795 Passing 5 GPIOs to payload:
9398 12:15:12.011032 NAME | PORT | POLARITY | VALUE
9399 12:15:12.017667 EC in RW | 0x000000aa | low | undefined
9400 12:15:12.021153 EC interrupt | 0x00000005 | low | undefined
9401 12:15:12.024773 TPM interrupt | 0x000000ab | high | undefined
9402 12:15:12.031544 SD card detect | 0x00000011 | high | undefined
9403 12:15:12.034492 speaker enable | 0x00000093 | high | undefined
9404 12:15:12.038171 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9405 12:15:12.041522 in-header: 03 f9 00 00 02 00 00 00
9406 12:15:12.044549 in-data: 02 00
9407 12:15:12.047763 ADC[4]: Raw value=894081 ID=7
9408 12:15:12.051024 ADC[3]: Raw value=213070 ID=1
9409 12:15:12.051114 RAM Code: 0x71
9410 12:15:12.054591 ADC[6]: Raw value=74722 ID=0
9411 12:15:12.057855 ADC[5]: Raw value=211960 ID=1
9412 12:15:12.057948 SKU Code: 0x1
9413 12:15:12.064067 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9414 12:15:12.064161 coreboot table: 964 bytes.
9415 12:15:12.067021 IMD ROOT 0. 0xfffff000 0x00001000
9416 12:15:12.070626 IMD SMALL 1. 0xffffe000 0x00001000
9417 12:15:12.073675 RO MCACHE 2. 0xffffc000 0x00001104
9418 12:15:12.077367 CONSOLE 3. 0xfff7c000 0x00080000
9419 12:15:12.080672 FMAP 4. 0xfff7b000 0x00000452
9420 12:15:12.084002 TIME STAMP 5. 0xfff7a000 0x00000910
9421 12:15:12.087183 VBOOT WORK 6. 0xfff66000 0x00014000
9422 12:15:12.090359 RAMOOPS 7. 0xffe66000 0x00100000
9423 12:15:12.093441 COREBOOT 8. 0xffe64000 0x00002000
9424 12:15:12.096995 IMD small region:
9425 12:15:12.100090 IMD ROOT 0. 0xffffec00 0x00000400
9426 12:15:12.103807 VPD 1. 0xffffeba0 0x0000004c
9427 12:15:12.107121 MMC STATUS 2. 0xffffeb80 0x00000004
9428 12:15:12.113535 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9429 12:15:12.113648 Probing TPM: done!
9430 12:15:12.119964 Connected to device vid:did:rid of 1ae0:0028:00
9431 12:15:12.127163 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9432 12:15:12.130614 Initialized TPM device CR50 revision 0
9433 12:15:12.133552 Checking cr50 for pending updates
9434 12:15:12.139322 Reading cr50 TPM mode
9435 12:15:12.147492 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9436 12:15:12.154116 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9437 12:15:12.194239 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9438 12:15:12.197705 Checking segment from ROM address 0x40100000
9439 12:15:12.204030 Checking segment from ROM address 0x4010001c
9440 12:15:12.207768 Loading segment from ROM address 0x40100000
9441 12:15:12.207876 code (compression=0)
9442 12:15:12.217136 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9443 12:15:12.224339 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9444 12:15:12.224464 it's not compressed!
9445 12:15:12.230143 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9446 12:15:12.237237 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9447 12:15:12.255133 Loading segment from ROM address 0x4010001c
9448 12:15:12.255266 Entry Point 0x80000000
9449 12:15:12.258296 Loaded segments
9450 12:15:12.261342 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9451 12:15:12.267977 Jumping to boot code at 0x80000000(0xffe64000)
9452 12:15:12.275014 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9453 12:15:12.281432 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9454 12:15:12.288864 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9455 12:15:12.292827 Checking segment from ROM address 0x40100000
9456 12:15:12.295831 Checking segment from ROM address 0x4010001c
9457 12:15:12.302246 Loading segment from ROM address 0x40100000
9458 12:15:12.302403 code (compression=1)
9459 12:15:12.309017 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9460 12:15:12.318863 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9461 12:15:12.319039 using LZMA
9462 12:15:12.328051 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9463 12:15:12.334198 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9464 12:15:12.337532 Loading segment from ROM address 0x4010001c
9465 12:15:12.337636 Entry Point 0x54601000
9466 12:15:12.340480 Loaded segments
9467 12:15:12.344037 NOTICE: MT8192 bl31_setup
9468 12:15:12.350821 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9469 12:15:12.354742 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9470 12:15:12.357919 WARNING: region 0:
9471 12:15:12.361511 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 12:15:12.361604 WARNING: region 1:
9473 12:15:12.367907 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9474 12:15:12.371447 WARNING: region 2:
9475 12:15:12.374577 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9476 12:15:12.377499 WARNING: region 3:
9477 12:15:12.384017 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9478 12:15:12.384131 WARNING: region 4:
9479 12:15:12.390691 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 12:15:12.390797 WARNING: region 5:
9481 12:15:12.394255 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 12:15:12.397258 WARNING: region 6:
9483 12:15:12.400346 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 12:15:12.404112 WARNING: region 7:
9485 12:15:12.407342 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 12:15:12.413631 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9487 12:15:12.416851 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9488 12:15:12.424069 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9489 12:15:12.427403 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9490 12:15:12.430452 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9491 12:15:12.437200 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9492 12:15:12.440556 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9493 12:15:12.443617 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9494 12:15:12.450018 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9495 12:15:12.453323 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9496 12:15:12.460677 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9497 12:15:12.463661 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9498 12:15:12.466777 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9499 12:15:12.473551 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9500 12:15:12.477125 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9501 12:15:12.480497 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9502 12:15:12.486397 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9503 12:15:12.489734 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9504 12:15:12.496935 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9505 12:15:12.500197 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9506 12:15:12.503356 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9507 12:15:12.509776 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9508 12:15:12.513648 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9509 12:15:12.516756 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9510 12:15:12.523133 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9511 12:15:12.526749 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9512 12:15:12.533253 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9513 12:15:12.536469 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9514 12:15:12.543212 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9515 12:15:12.546330 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9516 12:15:12.549945 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9517 12:15:12.556424 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9518 12:15:12.559770 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9519 12:15:12.562799 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9520 12:15:12.566505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9521 12:15:12.573075 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9522 12:15:12.576245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9523 12:15:12.579371 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9524 12:15:12.585793 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9525 12:15:12.589542 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9526 12:15:12.592776 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9527 12:15:12.596002 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9528 12:15:12.602814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9529 12:15:12.605897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9530 12:15:12.608989 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9531 12:15:12.612092 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9532 12:15:12.619214 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9533 12:15:12.622596 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9534 12:15:12.625505 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9535 12:15:12.632459 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9536 12:15:12.635556 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9537 12:15:12.642367 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9538 12:15:12.645267 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9539 12:15:12.651906 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9540 12:15:12.655594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9541 12:15:12.658726 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9542 12:15:12.665607 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9543 12:15:12.668592 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9544 12:15:12.675280 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9545 12:15:12.678689 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9546 12:15:12.685174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9547 12:15:12.688408 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9548 12:15:12.695250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9549 12:15:12.698191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9550 12:15:12.702081 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9551 12:15:12.708716 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9552 12:15:12.712089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9553 12:15:12.718280 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9554 12:15:12.722016 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9555 12:15:12.728391 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9556 12:15:12.732031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9557 12:15:12.735275 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9558 12:15:12.741513 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9559 12:15:12.745299 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9560 12:15:12.751670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9561 12:15:12.754861 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9562 12:15:12.762019 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9563 12:15:12.765146 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9564 12:15:12.768550 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9565 12:15:12.775127 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9566 12:15:12.778338 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9567 12:15:12.784804 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9568 12:15:12.788128 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9569 12:15:12.795041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9570 12:15:12.798486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9571 12:15:12.801635 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9572 12:15:12.808231 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9573 12:15:12.811437 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9574 12:15:12.817992 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9575 12:15:12.821621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9576 12:15:12.828200 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9577 12:15:12.831256 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9578 12:15:12.837977 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9579 12:15:12.841136 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9580 12:15:12.847613 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9581 12:15:12.851345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9582 12:15:12.854374 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9583 12:15:12.861087 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9584 12:15:12.864197 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9585 12:15:12.867355 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9586 12:15:12.871010 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9587 12:15:12.877701 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9588 12:15:12.880985 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9589 12:15:12.887634 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9590 12:15:12.891073 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9591 12:15:12.894347 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9592 12:15:12.900655 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9593 12:15:12.903897 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9594 12:15:12.910228 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9595 12:15:12.914074 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9596 12:15:12.917534 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9597 12:15:12.923964 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9598 12:15:12.927525 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9599 12:15:12.933673 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9600 12:15:12.936681 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9601 12:15:12.940122 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9602 12:15:12.947095 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9603 12:15:12.950127 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9604 12:15:12.953409 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9605 12:15:12.959945 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9606 12:15:12.963245 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9607 12:15:12.967047 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9608 12:15:12.969912 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9609 12:15:12.976777 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9610 12:15:12.979985 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9611 12:15:12.983347 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9612 12:15:12.989823 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9613 12:15:12.993056 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9614 12:15:12.999893 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9615 12:15:13.003226 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9616 12:15:13.006344 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9617 12:15:13.012917 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9618 12:15:13.016188 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9619 12:15:13.022815 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9620 12:15:13.026313 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9621 12:15:13.029421 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9622 12:15:13.035922 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9623 12:15:13.039494 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9624 12:15:13.045609 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9625 12:15:13.049477 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9626 12:15:13.052605 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9627 12:15:13.059042 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9628 12:15:13.062677 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9629 12:15:13.069049 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9630 12:15:13.072237 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9631 12:15:13.076216 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9632 12:15:13.082526 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9633 12:15:13.086067 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9634 12:15:13.092357 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9635 12:15:13.095768 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9636 12:15:13.099391 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9637 12:15:13.106049 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9638 12:15:13.109382 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9639 12:15:13.112777 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9640 12:15:13.119527 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9641 12:15:13.123136 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9642 12:15:13.129206 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9643 12:15:13.132542 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9644 12:15:13.135607 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9645 12:15:13.142580 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9646 12:15:13.145752 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9647 12:15:13.151930 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9648 12:15:13.155376 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9649 12:15:13.158292 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9650 12:15:13.165233 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9651 12:15:13.168422 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9652 12:15:13.174743 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9653 12:15:13.178294 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9654 12:15:13.181381 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9655 12:15:13.188205 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9656 12:15:13.192080 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9657 12:15:13.198581 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9658 12:15:13.201761 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9659 12:15:13.205297 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9660 12:15:13.211345 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9661 12:15:13.214460 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9662 12:15:13.221491 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9663 12:15:13.225049 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9664 12:15:13.228122 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9665 12:15:13.234631 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9666 12:15:13.237886 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9667 12:15:13.244637 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9668 12:15:13.247678 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9669 12:15:13.250937 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9670 12:15:13.257490 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9671 12:15:13.260736 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9672 12:15:13.267959 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9673 12:15:13.271040 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9674 12:15:13.274189 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9675 12:15:13.281541 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9676 12:15:13.283834 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9677 12:15:13.290750 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9678 12:15:13.293914 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9679 12:15:13.297173 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9680 12:15:13.304457 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9681 12:15:13.307732 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9682 12:15:13.313856 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9683 12:15:13.317152 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9684 12:15:13.323529 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9685 12:15:13.326975 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9686 12:15:13.329933 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9687 12:15:13.337371 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9688 12:15:13.340340 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9689 12:15:13.346958 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9690 12:15:13.350154 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9691 12:15:13.356657 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9692 12:15:13.360118 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9693 12:15:13.363173 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9694 12:15:13.369535 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9695 12:15:13.373355 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9696 12:15:13.379885 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9697 12:15:13.382797 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9698 12:15:13.389396 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9699 12:15:13.392546 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9700 12:15:13.396323 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9701 12:15:13.402743 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9702 12:15:13.405991 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9703 12:15:13.412474 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9704 12:15:13.415818 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9705 12:15:13.422262 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9706 12:15:13.425896 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9707 12:15:13.429167 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9708 12:15:13.435866 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9709 12:15:13.439126 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9710 12:15:13.445425 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9711 12:15:13.448731 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9712 12:15:13.455177 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9713 12:15:13.458459 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9714 12:15:13.465049 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9715 12:15:13.468254 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9716 12:15:13.471607 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9717 12:15:13.475296 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9718 12:15:13.478323 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9719 12:15:13.485228 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9720 12:15:13.488352 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9721 12:15:13.491460 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9722 12:15:13.498063 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9723 12:15:13.502159 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9724 12:15:13.505207 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9725 12:15:13.511994 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9726 12:15:13.515084 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9727 12:15:13.521140 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9728 12:15:13.524600 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9729 12:15:13.528135 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9730 12:15:13.534772 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9731 12:15:13.537963 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9732 12:15:13.544343 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9733 12:15:13.547739 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9734 12:15:13.551019 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9735 12:15:13.557646 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9736 12:15:13.560862 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9737 12:15:13.564187 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9738 12:15:13.570774 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9739 12:15:13.573923 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9740 12:15:13.577592 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9741 12:15:13.583883 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9742 12:15:13.587529 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9743 12:15:13.593869 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9744 12:15:13.597123 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9745 12:15:13.600304 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9746 12:15:13.606707 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9747 12:15:13.610248 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9748 12:15:13.616635 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9749 12:15:13.620603 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9750 12:15:13.623603 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9751 12:15:13.630108 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9752 12:15:13.633180 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9753 12:15:13.640218 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9754 12:15:13.643532 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9755 12:15:13.646925 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9756 12:15:13.650018 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9757 12:15:13.653518 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9758 12:15:13.659821 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9759 12:15:13.663036 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9760 12:15:13.666401 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9761 12:15:13.669620 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9762 12:15:13.676481 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9763 12:15:13.679357 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9764 12:15:13.682684 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9765 12:15:13.685904 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9766 12:15:13.692383 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9767 12:15:13.696085 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9768 12:15:13.702305 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9769 12:15:13.705797 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9770 12:15:13.708798 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9771 12:15:13.715607 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9772 12:15:13.718803 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9773 12:15:13.725456 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9774 12:15:13.728589 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9775 12:15:13.731861 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9776 12:15:13.738677 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9777 12:15:13.741905 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9778 12:15:13.748595 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9779 12:15:13.751962 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9780 12:15:13.758551 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9781 12:15:13.761808 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9782 12:15:13.768273 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9783 12:15:13.771610 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9784 12:15:13.775022 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9785 12:15:13.781487 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9786 12:15:13.784678 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9787 12:15:13.791093 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9788 12:15:13.794367 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9789 12:15:13.801227 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9790 12:15:13.804510 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9791 12:15:13.807498 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9792 12:15:13.814395 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9793 12:15:13.817641 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9794 12:15:13.824065 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9795 12:15:13.827441 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9796 12:15:13.830585 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9797 12:15:13.837679 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9798 12:15:13.841096 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9799 12:15:13.847302 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9800 12:15:13.850368 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9801 12:15:13.853904 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9802 12:15:13.860385 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9803 12:15:13.863741 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9804 12:15:13.870459 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9805 12:15:13.873503 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9806 12:15:13.880066 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9807 12:15:13.883278 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9808 12:15:13.886558 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9809 12:15:13.892861 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9810 12:15:13.896144 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9811 12:15:13.903175 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9812 12:15:13.906293 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9813 12:15:13.912976 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9814 12:15:13.916377 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9815 12:15:13.919530 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9816 12:15:13.926194 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9817 12:15:13.929356 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9818 12:15:13.935949 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9819 12:15:13.939701 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9820 12:15:13.946011 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9821 12:15:13.949288 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9822 12:15:13.952391 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9823 12:15:13.959165 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9824 12:15:13.962171 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9825 12:15:13.969394 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9826 12:15:13.972397 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9827 12:15:13.975571 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9828 12:15:13.982063 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9829 12:15:13.985309 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9830 12:15:13.991802 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9831 12:15:13.995002 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9832 12:15:14.001589 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9833 12:15:14.005053 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9834 12:15:14.007978 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9835 12:15:14.014812 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9836 12:15:14.018055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9837 12:15:14.024318 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9838 12:15:14.027628 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9839 12:15:14.034283 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9840 12:15:14.038129 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9841 12:15:14.041354 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9842 12:15:14.047644 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9843 12:15:14.050789 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9844 12:15:14.057649 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9845 12:15:14.060931 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9846 12:15:14.067451 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9847 12:15:14.071184 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9848 12:15:14.073789 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9849 12:15:14.080446 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9850 12:15:14.084328 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9851 12:15:14.090818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9852 12:15:14.094068 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9853 12:15:14.100666 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9854 12:15:14.104085 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9855 12:15:14.110887 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9856 12:15:14.113804 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9857 12:15:14.116797 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9858 12:15:14.123926 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9859 12:15:14.127079 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9860 12:15:14.134028 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9861 12:15:14.137258 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9862 12:15:14.143445 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9863 12:15:14.146582 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9864 12:15:14.153525 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9865 12:15:14.156891 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9866 12:15:14.160096 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9867 12:15:14.166613 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9868 12:15:14.169518 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9869 12:15:14.176632 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9870 12:15:14.179806 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9871 12:15:14.186509 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9872 12:15:14.189416 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9873 12:15:14.196550 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9874 12:15:14.199633 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9875 12:15:14.206281 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9876 12:15:14.209757 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9877 12:15:14.213134 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9878 12:15:14.219347 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9879 12:15:14.222440 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9880 12:15:14.229116 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9881 12:15:14.232356 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9882 12:15:14.238929 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9883 12:15:14.242729 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9884 12:15:14.248909 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9885 12:15:14.252210 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9886 12:15:14.255575 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9887 12:15:14.262348 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9888 12:15:14.265610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9889 12:15:14.272028 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9890 12:15:14.274916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9891 12:15:14.281527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9892 12:15:14.284728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9893 12:15:14.291198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9894 12:15:14.294982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9895 12:15:14.301620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9896 12:15:14.304815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9897 12:15:14.311262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9898 12:15:14.314865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9899 12:15:14.321149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9900 12:15:14.324435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9901 12:15:14.330739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9902 12:15:14.333845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9903 12:15:14.340440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9904 12:15:14.343969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9905 12:15:14.350456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9906 12:15:14.353466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9907 12:15:14.360475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9908 12:15:14.363733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9909 12:15:14.370193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9910 12:15:14.373275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9911 12:15:14.380333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9912 12:15:14.383552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9913 12:15:14.389519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9914 12:15:14.393400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9915 12:15:14.399755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9916 12:15:14.403050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9917 12:15:14.409628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9918 12:15:14.412874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9919 12:15:14.419816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9920 12:15:14.422749 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9921 12:15:14.426274 INFO: [APUAPC] vio 0
9922 12:15:14.429611 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9923 12:15:14.435940 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9924 12:15:14.439111 INFO: [APUAPC] D0_APC_0: 0x400510
9925 12:15:14.439196 INFO: [APUAPC] D0_APC_1: 0x0
9926 12:15:14.442850 INFO: [APUAPC] D0_APC_2: 0x1540
9927 12:15:14.446234 INFO: [APUAPC] D0_APC_3: 0x0
9928 12:15:14.449300 INFO: [APUAPC] D1_APC_0: 0xffffffff
9929 12:15:14.452373 INFO: [APUAPC] D1_APC_1: 0xffffffff
9930 12:15:14.455592 INFO: [APUAPC] D1_APC_2: 0x3fffff
9931 12:15:14.459040 INFO: [APUAPC] D1_APC_3: 0x0
9932 12:15:14.462227 INFO: [APUAPC] D2_APC_0: 0xffffffff
9933 12:15:14.465799 INFO: [APUAPC] D2_APC_1: 0xffffffff
9934 12:15:14.468798 INFO: [APUAPC] D2_APC_2: 0x3fffff
9935 12:15:14.472029 INFO: [APUAPC] D2_APC_3: 0x0
9936 12:15:14.475175 INFO: [APUAPC] D3_APC_0: 0xffffffff
9937 12:15:14.478743 INFO: [APUAPC] D3_APC_1: 0xffffffff
9938 12:15:14.481925 INFO: [APUAPC] D3_APC_2: 0x3fffff
9939 12:15:14.485279 INFO: [APUAPC] D3_APC_3: 0x0
9940 12:15:14.488595 INFO: [APUAPC] D4_APC_0: 0xffffffff
9941 12:15:14.491764 INFO: [APUAPC] D4_APC_1: 0xffffffff
9942 12:15:14.495613 INFO: [APUAPC] D4_APC_2: 0x3fffff
9943 12:15:14.498816 INFO: [APUAPC] D4_APC_3: 0x0
9944 12:15:14.502073 INFO: [APUAPC] D5_APC_0: 0xffffffff
9945 12:15:14.505251 INFO: [APUAPC] D5_APC_1: 0xffffffff
9946 12:15:14.508466 INFO: [APUAPC] D5_APC_2: 0x3fffff
9947 12:15:14.511782 INFO: [APUAPC] D5_APC_3: 0x0
9948 12:15:14.515259 INFO: [APUAPC] D6_APC_0: 0xffffffff
9949 12:15:14.518292 INFO: [APUAPC] D6_APC_1: 0xffffffff
9950 12:15:14.521461 INFO: [APUAPC] D6_APC_2: 0x3fffff
9951 12:15:14.524728 INFO: [APUAPC] D6_APC_3: 0x0
9952 12:15:14.528470 INFO: [APUAPC] D7_APC_0: 0xffffffff
9953 12:15:14.531674 INFO: [APUAPC] D7_APC_1: 0xffffffff
9954 12:15:14.534817 INFO: [APUAPC] D7_APC_2: 0x3fffff
9955 12:15:14.538134 INFO: [APUAPC] D7_APC_3: 0x0
9956 12:15:14.541454 INFO: [APUAPC] D8_APC_0: 0xffffffff
9957 12:15:14.544700 INFO: [APUAPC] D8_APC_1: 0xffffffff
9958 12:15:14.547776 INFO: [APUAPC] D8_APC_2: 0x3fffff
9959 12:15:14.551528 INFO: [APUAPC] D8_APC_3: 0x0
9960 12:15:14.554721 INFO: [APUAPC] D9_APC_0: 0xffffffff
9961 12:15:14.557939 INFO: [APUAPC] D9_APC_1: 0xffffffff
9962 12:15:14.561077 INFO: [APUAPC] D9_APC_2: 0x3fffff
9963 12:15:14.564820 INFO: [APUAPC] D9_APC_3: 0x0
9964 12:15:14.568161 INFO: [APUAPC] D10_APC_0: 0xffffffff
9965 12:15:14.571300 INFO: [APUAPC] D10_APC_1: 0xffffffff
9966 12:15:14.574798 INFO: [APUAPC] D10_APC_2: 0x3fffff
9967 12:15:14.578161 INFO: [APUAPC] D10_APC_3: 0x0
9968 12:15:14.581014 INFO: [APUAPC] D11_APC_0: 0xffffffff
9969 12:15:14.584030 INFO: [APUAPC] D11_APC_1: 0xffffffff
9970 12:15:14.587368 INFO: [APUAPC] D11_APC_2: 0x3fffff
9971 12:15:14.590505 INFO: [APUAPC] D11_APC_3: 0x0
9972 12:15:14.594508 INFO: [APUAPC] D12_APC_0: 0xffffffff
9973 12:15:14.597919 INFO: [APUAPC] D12_APC_1: 0xffffffff
9974 12:15:14.600985 INFO: [APUAPC] D12_APC_2: 0x3fffff
9975 12:15:14.604433 INFO: [APUAPC] D12_APC_3: 0x0
9976 12:15:14.607429 INFO: [APUAPC] D13_APC_0: 0xffffffff
9977 12:15:14.610668 INFO: [APUAPC] D13_APC_1: 0xffffffff
9978 12:15:14.613992 INFO: [APUAPC] D13_APC_2: 0x3fffff
9979 12:15:14.617164 INFO: [APUAPC] D13_APC_3: 0x0
9980 12:15:14.620429 INFO: [APUAPC] D14_APC_0: 0xffffffff
9981 12:15:14.623675 INFO: [APUAPC] D14_APC_1: 0xffffffff
9982 12:15:14.627015 INFO: [APUAPC] D14_APC_2: 0x3fffff
9983 12:15:14.630244 INFO: [APUAPC] D14_APC_3: 0x0
9984 12:15:14.633738 INFO: [APUAPC] D15_APC_0: 0xffffffff
9985 12:15:14.637333 INFO: [APUAPC] D15_APC_1: 0xffffffff
9986 12:15:14.640613 INFO: [APUAPC] D15_APC_2: 0x3fffff
9987 12:15:14.643679 INFO: [APUAPC] D15_APC_3: 0x0
9988 12:15:14.647017 INFO: [APUAPC] APC_CON: 0x4
9989 12:15:14.650446 INFO: [NOCDAPC] D0_APC_0: 0x0
9990 12:15:14.653505 INFO: [NOCDAPC] D0_APC_1: 0x0
9991 12:15:14.656617 INFO: [NOCDAPC] D1_APC_0: 0x0
9992 12:15:14.659684 INFO: [NOCDAPC] D1_APC_1: 0xfff
9993 12:15:14.659781 INFO: [NOCDAPC] D2_APC_0: 0x0
9994 12:15:14.662961 INFO: [NOCDAPC] D2_APC_1: 0xfff
9995 12:15:14.666773 INFO: [NOCDAPC] D3_APC_0: 0x0
9996 12:15:14.669761 INFO: [NOCDAPC] D3_APC_1: 0xfff
9997 12:15:14.673086 INFO: [NOCDAPC] D4_APC_0: 0x0
9998 12:15:14.676619 INFO: [NOCDAPC] D4_APC_1: 0xfff
9999 12:15:14.679597 INFO: [NOCDAPC] D5_APC_0: 0x0
10000 12:15:14.682771 INFO: [NOCDAPC] D5_APC_1: 0xfff
10001 12:15:14.686462 INFO: [NOCDAPC] D6_APC_0: 0x0
10002 12:15:14.689355 INFO: [NOCDAPC] D6_APC_1: 0xfff
10003 12:15:14.692669 INFO: [NOCDAPC] D7_APC_0: 0x0
10004 12:15:14.696405 INFO: [NOCDAPC] D7_APC_1: 0xfff
10005 12:15:14.696490 INFO: [NOCDAPC] D8_APC_0: 0x0
10006 12:15:14.699579 INFO: [NOCDAPC] D8_APC_1: 0xfff
10007 12:15:14.702740 INFO: [NOCDAPC] D9_APC_0: 0x0
10008 12:15:14.705916 INFO: [NOCDAPC] D9_APC_1: 0xfff
10009 12:15:14.709242 INFO: [NOCDAPC] D10_APC_0: 0x0
10010 12:15:14.712450 INFO: [NOCDAPC] D10_APC_1: 0xfff
10011 12:15:14.715627 INFO: [NOCDAPC] D11_APC_0: 0x0
10012 12:15:14.718791 INFO: [NOCDAPC] D11_APC_1: 0xfff
10013 12:15:14.722695 INFO: [NOCDAPC] D12_APC_0: 0x0
10014 12:15:14.725457 INFO: [NOCDAPC] D12_APC_1: 0xfff
10015 12:15:14.728921 INFO: [NOCDAPC] D13_APC_0: 0x0
10016 12:15:14.732133 INFO: [NOCDAPC] D13_APC_1: 0xfff
10017 12:15:14.735575 INFO: [NOCDAPC] D14_APC_0: 0x0
10018 12:15:14.738749 INFO: [NOCDAPC] D14_APC_1: 0xfff
10019 12:15:14.742239 INFO: [NOCDAPC] D15_APC_0: 0x0
10020 12:15:14.745668 INFO: [NOCDAPC] D15_APC_1: 0xfff
10021 12:15:14.745760 INFO: [NOCDAPC] APC_CON: 0x4
10022 12:15:14.748571 INFO: [APUAPC] set_apusys_apc done
10023 12:15:14.752168 INFO: [DEVAPC] devapc_init done
10024 12:15:14.758255 INFO: GICv3 without legacy support detected.
10025 12:15:14.762093 INFO: ARM GICv3 driver initialized in EL3
10026 12:15:14.765357 INFO: Maximum SPI INTID supported: 639
10027 12:15:14.768685 INFO: BL31: Initializing runtime services
10028 12:15:14.775070 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10029 12:15:14.778217 INFO: SPM: enable CPC mode
10030 12:15:14.781255 INFO: mcdi ready for mcusys-off-idle and system suspend
10031 12:15:14.788104 INFO: BL31: Preparing for EL3 exit to normal world
10032 12:15:14.791211 INFO: Entry point address = 0x80000000
10033 12:15:14.794395 INFO: SPSR = 0x8
10034 12:15:14.798721
10035 12:15:14.798834
10036 12:15:14.798948
10037 12:15:14.802526 Starting depthcharge on Spherion...
10038 12:15:14.802631
10039 12:15:14.802730 Wipe memory regions:
10040 12:15:14.802832
10041 12:15:14.803494 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10042 12:15:14.803605 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10043 12:15:14.803694 Setting prompt string to ['asurada:']
10044 12:15:14.803783 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10045 12:15:14.805765 [0x00000040000000, 0x00000054600000)
10046 12:15:14.928244
10047 12:15:14.928382 [0x00000054660000, 0x00000080000000)
10048 12:15:15.188701
10049 12:15:15.188843 [0x000000821a7280, 0x000000ffe64000)
10050 12:15:15.933591
10051 12:15:15.933770 [0x00000100000000, 0x00000240000000)
10052 12:15:17.824053
10053 12:15:17.827591 Initializing XHCI USB controller at 0x11200000.
10054 12:15:18.866321
10055 12:15:18.869699 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10056 12:15:18.869790
10057 12:15:18.869856
10058 12:15:18.869916
10059 12:15:18.870193 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 12:15:18.970540 asurada: tftpboot 192.168.201.1 10605437/tftp-deploy-0d56fqfp/kernel/image.itb 10605437/tftp-deploy-0d56fqfp/kernel/cmdline
10062 12:15:18.970689 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 12:15:18.970820 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10064 12:15:18.975410 tftpboot 192.168.201.1 10605437/tftp-deploy-0d56fqfp/kernel/image.itp-deploy-0d56fqfp/kernel/cmdline
10065 12:15:18.975497
10066 12:15:18.975563 Waiting for link
10067 12:15:19.135803
10068 12:15:19.135941 R8152: Initializing
10069 12:15:19.136009
10070 12:15:19.138556 Version 6 (ocp_data = 5c30)
10071 12:15:19.138669
10072 12:15:19.142190 R8152: Done initializing
10073 12:15:19.142271
10074 12:15:19.142340 Adding net device
10075 12:15:21.045294
10076 12:15:21.045460 done.
10077 12:15:21.045555
10078 12:15:21.045644 MAC: 00:24:32:30:78:ff
10079 12:15:21.045731
10080 12:15:21.048655 Sending DHCP discover... done.
10081 12:15:21.048758
10082 12:15:21.052557 Waiting for reply... done.
10083 12:15:21.052646
10084 12:15:21.055182 Sending DHCP request... done.
10085 12:15:21.055263
10086 12:15:21.060408 Waiting for reply... done.
10087 12:15:21.060489
10088 12:15:21.060553 My ip is 192.168.201.21
10089 12:15:21.060613
10090 12:15:21.063743 The DHCP server ip is 192.168.201.1
10091 12:15:21.063824
10092 12:15:21.070270 TFTP server IP predefined by user: 192.168.201.1
10093 12:15:21.070371
10094 12:15:21.077045 Bootfile predefined by user: 10605437/tftp-deploy-0d56fqfp/kernel/image.itb
10095 12:15:21.077128
10096 12:15:21.080286 Sending tftp read request... done.
10097 12:15:21.080369
10098 12:15:21.083679 Waiting for the transfer...
10099 12:15:21.083777
10100 12:15:21.615281 00000000 ################################################################
10101 12:15:21.615412
10102 12:15:22.184292 00080000 ################################################################
10103 12:15:22.184431
10104 12:15:22.730778 00100000 ################################################################
10105 12:15:22.730944
10106 12:15:23.303809 00180000 ################################################################
10107 12:15:23.303964
10108 12:15:23.861706 00200000 ################################################################
10109 12:15:23.861841
10110 12:15:24.423373 00280000 ################################################################
10111 12:15:24.423510
10112 12:15:24.988019 00300000 ################################################################
10113 12:15:24.988146
10114 12:15:25.596413 00380000 ################################################################
10115 12:15:25.596580
10116 12:15:26.194250 00400000 ################################################################
10117 12:15:26.194392
10118 12:15:26.745740 00480000 ################################################################
10119 12:15:26.745901
10120 12:15:27.366109 00500000 ################################################################
10121 12:15:27.366281
10122 12:15:27.913085 00580000 ################################################################
10123 12:15:27.913222
10124 12:15:28.458530 00600000 ################################################################
10125 12:15:28.458660
10126 12:15:28.992979 00680000 ################################################################
10127 12:15:28.993144
10128 12:15:29.523242 00700000 ################################################################
10129 12:15:29.523380
10130 12:15:30.048051 00780000 ################################################################
10131 12:15:30.048211
10132 12:15:30.565601 00800000 ################################################################
10133 12:15:30.565792
10134 12:15:31.084554 00880000 ################################################################
10135 12:15:31.084727
10136 12:15:31.667479 00900000 ################################################################
10137 12:15:31.667642
10138 12:15:32.206687 00980000 ################################################################
10139 12:15:32.206861
10140 12:15:32.746661 00a00000 ################################################################
10141 12:15:32.746823
10142 12:15:33.277928 00a80000 ################################################################
10143 12:15:33.278076
10144 12:15:33.815437 00b00000 ################################################################
10145 12:15:33.815572
10146 12:15:34.354270 00b80000 ################################################################
10147 12:15:34.354425
10148 12:15:34.889333 00c00000 ################################################################
10149 12:15:34.889520
10150 12:15:35.419254 00c80000 ################################################################
10151 12:15:35.419427
10152 12:15:35.987194 00d00000 ################################################################
10153 12:15:35.987376
10154 12:15:36.520855 00d80000 ################################################################
10155 12:15:36.521049
10156 12:15:37.063636 00e00000 ################################################################
10157 12:15:37.063777
10158 12:15:37.603745 00e80000 ################################################################
10159 12:15:37.603878
10160 12:15:38.148078 00f00000 ################################################################
10161 12:15:38.148214
10162 12:15:38.672010 00f80000 ################################################################
10163 12:15:38.672182
10164 12:15:39.195998 01000000 ################################################################
10165 12:15:39.196142
10166 12:15:39.728861 01080000 ################################################################
10167 12:15:39.728994
10168 12:15:40.262138 01100000 ################################################################
10169 12:15:40.262307
10170 12:15:40.853239 01180000 ################################################################
10171 12:15:40.853423
10172 12:15:41.377008 01200000 ################################################################
10173 12:15:41.377187
10174 12:15:41.907273 01280000 ################################################################
10175 12:15:41.907417
10176 12:15:42.480051 01300000 ################################################################
10177 12:15:42.480190
10178 12:15:43.006880 01380000 ################################################################
10179 12:15:43.007022
10180 12:15:43.552119 01400000 ################################################################
10181 12:15:43.552271
10182 12:15:44.115885 01480000 ################################################################
10183 12:15:44.116028
10184 12:15:44.663519 01500000 ################################################################
10185 12:15:44.663680
10186 12:15:45.183168 01580000 ################################################################
10187 12:15:45.183331
10188 12:15:45.718803 01600000 ################################################################
10189 12:15:45.718974
10190 12:15:46.244693 01680000 ################################################################
10191 12:15:46.244834
10192 12:15:46.775629 01700000 ################################################################
10193 12:15:46.775790
10194 12:15:47.296067 01780000 ################################################################
10195 12:15:47.296206
10196 12:15:47.826355 01800000 ################################################################
10197 12:15:47.826492
10198 12:15:48.355436 01880000 ################################################################
10199 12:15:48.355598
10200 12:15:48.918814 01900000 ################################################################
10201 12:15:48.918983
10202 12:15:49.452837 01980000 ################################################################
10203 12:15:49.452972
10204 12:15:50.021556 01a00000 ################################################################
10205 12:15:50.021687
10206 12:15:50.570023 01a80000 ################################################################
10207 12:15:50.570195
10208 12:15:51.123703 01b00000 ################################################################
10209 12:15:51.123867
10210 12:15:51.700399 01b80000 ################################################################
10211 12:15:51.700537
10212 12:15:52.258013 01c00000 ################################################################
10213 12:15:52.258149
10214 12:15:52.830101 01c80000 ################################################################
10215 12:15:52.830269
10216 12:15:53.368943 01d00000 ################################################################
10217 12:15:53.369114
10218 12:15:53.911758 01d80000 ################################################################
10219 12:15:53.911893
10220 12:15:54.483324 01e00000 ################################################################
10221 12:15:54.483461
10222 12:15:55.041437 01e80000 ################################################################
10223 12:15:55.041567
10224 12:15:55.597447 01f00000 ################################################################
10225 12:15:55.597585
10226 12:15:56.145839 01f80000 ################################################################
10227 12:15:56.146013
10228 12:15:56.670674 02000000 ################################################################
10229 12:15:56.670826
10230 12:15:57.206264 02080000 ################################################################
10231 12:15:57.206435
10232 12:15:57.746333 02100000 ################################################################
10233 12:15:57.746462
10234 12:15:58.283017 02180000 ################################################################
10235 12:15:58.283152
10236 12:15:58.843601 02200000 ################################################################
10237 12:15:58.843738
10238 12:15:59.453558 02280000 ################################################################
10239 12:15:59.453689
10240 12:16:00.009358 02300000 ################################################################
10241 12:16:00.009507
10242 12:16:00.570290 02380000 ################################################################
10243 12:16:00.570455
10244 12:16:01.154201 02400000 ################################################################
10245 12:16:01.154379
10246 12:16:01.750999 02480000 ################################################################
10247 12:16:01.751144
10248 12:16:02.398066 02500000 ################################################################
10249 12:16:02.398225
10250 12:16:03.059951 02580000 ################################################################
10251 12:16:03.060098
10252 12:16:03.634855 02600000 ################################################################
10253 12:16:03.635002
10254 12:16:04.216903 02680000 ################################################################
10255 12:16:04.217071
10256 12:16:04.755802 02700000 ################################################################
10257 12:16:04.755969
10258 12:16:05.285978 02780000 ################################################################
10259 12:16:05.286149
10260 12:16:05.855117 02800000 ################################################################
10261 12:16:05.855248
10262 12:16:06.520880 02880000 ################################################################
10263 12:16:06.521430
10264 12:16:07.107452 02900000 ################################################################
10265 12:16:07.107617
10266 12:16:07.644565 02980000 ################################################################
10267 12:16:07.644704
10268 12:16:08.184637 02a00000 ################################################################
10269 12:16:08.184785
10270 12:16:08.736963 02a80000 ################################################################
10271 12:16:08.737127
10272 12:16:09.321340 02b00000 ################################################################
10273 12:16:09.321499
10274 12:16:09.885679 02b80000 ################################################################
10275 12:16:09.885836
10276 12:16:10.503986 02c00000 ################################################################
10277 12:16:10.504160
10278 12:16:11.186049 02c80000 ################################################################
10279 12:16:11.186200
10280 12:16:11.793691 02d00000 ################################################################
10281 12:16:11.794235
10282 12:16:12.470543 02d80000 ################################################################
10283 12:16:12.471282
10284 12:16:13.084900 02e00000 ################################################################
10285 12:16:13.085418
10286 12:16:13.744368 02e80000 ################################################################
10287 12:16:13.745079
10288 12:16:14.320391 02f00000 ################################################################
10289 12:16:14.320537
10290 12:16:14.996373 02f80000 ################################################################
10291 12:16:14.997058
10292 12:16:15.688512 03000000 ################################################################
10293 12:16:15.689210
10294 12:16:16.342727 03080000 ################################################################
10295 12:16:16.342904
10296 12:16:16.924594 03100000 ################################################################
10297 12:16:16.924742
10298 12:16:17.546284 03180000 ################################################################
10299 12:16:17.546422
10300 12:16:18.192990 03200000 ################################################################
10301 12:16:18.193142
10302 12:16:18.759359 03280000 ################################################################
10303 12:16:18.759508
10304 12:16:19.329670 03300000 ################################################################
10305 12:16:19.329822
10306 12:16:19.908736 03380000 ################################################################
10307 12:16:19.908921
10308 12:16:20.484995 03400000 ################################################################
10309 12:16:20.485132
10310 12:16:21.040501 03480000 ################################################################
10311 12:16:21.040644
10312 12:16:21.699783 03500000 ################################################################
10313 12:16:21.700388
10314 12:16:22.351484 03580000 ################################################################
10315 12:16:22.352060
10316 12:16:22.945680 03600000 ################################################################
10317 12:16:22.945832
10318 12:16:23.316061 03680000 ############################################# done.
10319 12:16:23.316222
10320 12:16:23.319803 The bootfile was 57512738 bytes long.
10321 12:16:23.319943
10322 12:16:23.322761 Sending tftp read request... done.
10323 12:16:23.322903
10324 12:16:23.322985 Waiting for the transfer...
10325 12:16:23.323078
10326 12:16:23.326363 00000000 # done.
10327 12:16:23.326463
10328 12:16:23.332918 Command line loaded dynamically from TFTP file: 10605437/tftp-deploy-0d56fqfp/kernel/cmdline
10329 12:16:23.333003
10330 12:16:23.346332 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10331 12:16:23.346470
10332 12:16:23.346571 Loading FIT.
10333 12:16:23.346668
10334 12:16:23.349851 Image ramdisk-1 has 47369159 bytes.
10335 12:16:23.349935
10336 12:16:23.352794 Image fdt-1 has 46924 bytes.
10337 12:16:23.352877
10338 12:16:23.355766 Image kernel-1 has 10094623 bytes.
10339 12:16:23.355850
10340 12:16:23.365540 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10341 12:16:23.365631
10342 12:16:23.382419 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10343 12:16:23.382520
10344 12:16:23.385244 Choosing best match conf-1 for compat google,spherion-rev2.
10345 12:16:23.388978
10346 12:16:23.392222 Connected to device vid:did:rid of 1ae0:0028:00
10347 12:16:23.480349
10348 12:16:23.483552 tpm_get_response: command 0x17b, return code 0x0
10349 12:16:23.483640
10350 12:16:23.486722 ec_init: CrosEC protocol v3 supported (256, 248)
10351 12:16:23.491054
10352 12:16:23.494228 tpm_cleanup: add release locality here.
10353 12:16:23.494309
10354 12:16:23.494373 Shutting down all USB controllers.
10355 12:16:23.497349
10356 12:16:23.497430 Removing current net device
10357 12:16:23.497495
10358 12:16:23.504180 Exiting depthcharge with code 4 at timestamp: 98024070
10359 12:16:23.504263
10360 12:16:23.507390 LZMA decompressing kernel-1 to 0x821a6718
10361 12:16:23.507472
10362 12:16:23.511095 LZMA decompressing kernel-1 to 0x40000000
10363 12:16:24.779963
10364 12:16:24.780478 jumping to kernel
10365 12:16:24.781904 end: 2.2.4 bootloader-commands (duration 00:01:10) [common]
10366 12:16:24.782420 start: 2.2.5 auto-login-action (timeout 00:03:15) [common]
10367 12:16:24.782797 Setting prompt string to ['Linux version [0-9]']
10368 12:16:24.783159 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10369 12:16:24.783501 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10370 12:16:24.861700
10371 12:16:24.864297 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10372 12:16:24.868579 start: 2.2.5.1 login-action (timeout 00:03:15) [common]
10373 12:16:24.869035 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10374 12:16:24.869460 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10375 12:16:24.869834 Using line separator: #'\n'#
10376 12:16:24.870144 No login prompt set.
10377 12:16:24.870456 Parsing kernel messages
10378 12:16:24.870741 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10379 12:16:24.871289 [login-action] Waiting for messages, (timeout 00:03:15)
10380 12:16:24.887928 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
10381 12:16:24.890942 [ 0.000000] random: crng init done
10382 12:16:24.894360 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10383 12:16:24.897527 [ 0.000000] efi: UEFI not found.
10384 12:16:24.907418 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10385 12:16:24.914088 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10386 12:16:24.924236 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10387 12:16:24.933839 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10388 12:16:24.940290 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10389 12:16:24.946646 [ 0.000000] printk: bootconsole [mtk8250] enabled
10390 12:16:24.953590 [ 0.000000] NUMA: No NUMA configuration found
10391 12:16:24.959827 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10392 12:16:24.963348 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10393 12:16:24.966149 [ 0.000000] Zone ranges:
10394 12:16:24.973076 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10395 12:16:24.976440 [ 0.000000] DMA32 empty
10396 12:16:24.982700 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10397 12:16:24.986481 [ 0.000000] Movable zone start for each node
10398 12:16:24.989637 [ 0.000000] Early memory node ranges
10399 12:16:24.996170 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10400 12:16:25.002396 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10401 12:16:25.009540 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10402 12:16:25.016046 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10403 12:16:25.022682 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10404 12:16:25.028812 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10405 12:16:25.085641 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10406 12:16:25.091919 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10407 12:16:25.098774 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10408 12:16:25.102029 [ 0.000000] psci: probing for conduit method from DT.
10409 12:16:25.108390 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10410 12:16:25.111681 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10411 12:16:25.118537 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10412 12:16:25.121839 [ 0.000000] psci: SMC Calling Convention v1.2
10413 12:16:25.128225 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10414 12:16:25.131139 [ 0.000000] Detected VIPT I-cache on CPU0
10415 12:16:25.138265 [ 0.000000] CPU features: detected: GIC system register CPU interface
10416 12:16:25.144557 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10417 12:16:25.151020 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10418 12:16:25.158074 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10419 12:16:25.167868 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10420 12:16:25.174123 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10421 12:16:25.177432 [ 0.000000] alternatives: applying boot alternatives
10422 12:16:25.184170 [ 0.000000] Fallback order for Node 0: 0
10423 12:16:25.190724 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10424 12:16:25.194279 [ 0.000000] Policy zone: Normal
10425 12:16:25.207033 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10426 12:16:25.217383 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10427 12:16:25.227473 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10428 12:16:25.237205 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10429 12:16:25.244020 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10430 12:16:25.247156 <6>[ 0.000000] software IO TLB: area num 8.
10431 12:16:25.303847 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10432 12:16:25.452724 <6>[ 0.000000] Memory: 7926684K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 426084K reserved, 32768K cma-reserved)
10433 12:16:25.459456 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10434 12:16:25.466082 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10435 12:16:25.469345 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10436 12:16:25.476234 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10437 12:16:25.482697 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10438 12:16:25.485691 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10439 12:16:25.495705 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10440 12:16:25.502015 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10441 12:16:25.508734 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10442 12:16:25.515505 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10443 12:16:25.518588 <6>[ 0.000000] GICv3: 608 SPIs implemented
10444 12:16:25.522240 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10445 12:16:25.528510 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10446 12:16:25.532090 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10447 12:16:25.538563 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10448 12:16:25.552007 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10449 12:16:25.564862 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10450 12:16:25.571251 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10451 12:16:25.579343 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10452 12:16:25.592340 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10453 12:16:25.599226 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10454 12:16:25.605827 <6>[ 0.009226] Console: colour dummy device 80x25
10455 12:16:25.615545 <6>[ 0.013953] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10456 12:16:25.622882 <6>[ 0.024395] pid_max: default: 32768 minimum: 301
10457 12:16:25.626120 <6>[ 0.029268] LSM: Security Framework initializing
10458 12:16:25.632351 <6>[ 0.034167] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10459 12:16:25.641928 <6>[ 0.041982] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10460 12:16:25.652367 <6>[ 0.051360] cblist_init_generic: Setting adjustable number of callback queues.
10461 12:16:25.658931 <6>[ 0.058812] cblist_init_generic: Setting shift to 3 and lim to 1.
10462 12:16:25.661710 <6>[ 0.065151] cblist_init_generic: Setting shift to 3 and lim to 1.
10463 12:16:25.668692 <6>[ 0.071558] rcu: Hierarchical SRCU implementation.
10464 12:16:25.675102 <6>[ 0.076571] rcu: Max phase no-delay instances is 1000.
10465 12:16:25.681564 <6>[ 0.083587] EFI services will not be available.
10466 12:16:25.684531 <6>[ 0.088556] smp: Bringing up secondary CPUs ...
10467 12:16:25.692841 <6>[ 0.093610] Detected VIPT I-cache on CPU1
10468 12:16:25.699274 <6>[ 0.093681] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10469 12:16:25.705559 <6>[ 0.093715] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10470 12:16:25.708731 <6>[ 0.094050] Detected VIPT I-cache on CPU2
10471 12:16:25.718553 <6>[ 0.094097] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10472 12:16:25.725623 <6>[ 0.094113] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10473 12:16:25.729026 <6>[ 0.094374] Detected VIPT I-cache on CPU3
10474 12:16:25.735521 <6>[ 0.094419] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10475 12:16:25.742409 <6>[ 0.094433] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10476 12:16:25.748894 <6>[ 0.094734] CPU features: detected: Spectre-v4
10477 12:16:25.752180 <6>[ 0.094740] CPU features: detected: Spectre-BHB
10478 12:16:25.755346 <6>[ 0.094746] Detected PIPT I-cache on CPU4
10479 12:16:25.761731 <6>[ 0.094803] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10480 12:16:25.768228 <6>[ 0.094819] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10481 12:16:25.775320 <6>[ 0.095114] Detected PIPT I-cache on CPU5
10482 12:16:25.781668 <6>[ 0.095177] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10483 12:16:25.788045 <6>[ 0.095193] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10484 12:16:25.791009 <6>[ 0.095479] Detected PIPT I-cache on CPU6
10485 12:16:25.801301 <6>[ 0.095544] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10486 12:16:25.807889 <6>[ 0.095560] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10487 12:16:25.811075 <6>[ 0.095858] Detected PIPT I-cache on CPU7
10488 12:16:25.818023 <6>[ 0.095923] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10489 12:16:25.823860 <6>[ 0.095938] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10490 12:16:25.827428 <6>[ 0.095985] smp: Brought up 1 node, 8 CPUs
10491 12:16:25.834087 <6>[ 0.237291] SMP: Total of 8 processors activated.
10492 12:16:25.840571 <6>[ 0.242212] CPU features: detected: 32-bit EL0 Support
10493 12:16:25.847031 <6>[ 0.247576] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10494 12:16:25.853859 <6>[ 0.256430] CPU features: detected: Common not Private translations
10495 12:16:25.860354 <6>[ 0.262906] CPU features: detected: CRC32 instructions
10496 12:16:25.867276 <6>[ 0.268291] CPU features: detected: RCpc load-acquire (LDAPR)
10497 12:16:25.870485 <6>[ 0.274251] CPU features: detected: LSE atomic instructions
10498 12:16:25.876822 <6>[ 0.280067] CPU features: detected: Privileged Access Never
10499 12:16:25.883185 <6>[ 0.285883] CPU features: detected: RAS Extension Support
10500 12:16:25.890011 <6>[ 0.291491] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10501 12:16:25.893378 <6>[ 0.298715] CPU: All CPU(s) started at EL2
10502 12:16:25.899822 <6>[ 0.303031] alternatives: applying system-wide alternatives
10503 12:16:25.910253 <6>[ 0.313744] devtmpfs: initialized
10504 12:16:25.922902 <6>[ 0.322556] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10505 12:16:25.932097 <6>[ 0.332521] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10506 12:16:25.938933 <6>[ 0.340736] pinctrl core: initialized pinctrl subsystem
10507 12:16:25.942699 <6>[ 0.347391] DMI not present or invalid.
10508 12:16:25.948625 <6>[ 0.351798] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10509 12:16:25.958466 <6>[ 0.358682] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10510 12:16:25.964951 <6>[ 0.366262] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10511 12:16:25.975080 <6>[ 0.374486] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10512 12:16:25.981325 <6>[ 0.382729] audit: initializing netlink subsys (disabled)
10513 12:16:25.988175 <5>[ 0.388424] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10514 12:16:25.994804 <6>[ 0.389128] thermal_sys: Registered thermal governor 'step_wise'
10515 12:16:26.001816 <6>[ 0.396392] thermal_sys: Registered thermal governor 'power_allocator'
10516 12:16:26.004957 <6>[ 0.402646] cpuidle: using governor menu
10517 12:16:26.011305 <6>[ 0.413606] NET: Registered PF_QIPCRTR protocol family
10518 12:16:26.017786 <6>[ 0.419084] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10519 12:16:26.024927 <6>[ 0.426186] ASID allocator initialised with 32768 entries
10520 12:16:26.028039 <6>[ 0.432770] Serial: AMBA PL011 UART driver
10521 12:16:26.038066 <4>[ 0.441450] Trying to register duplicate clock ID: 134
10522 12:16:26.092220 <6>[ 0.498550] KASLR enabled
10523 12:16:26.106158 <6>[ 0.506228] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10524 12:16:26.112873 <6>[ 0.513240] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10525 12:16:26.119291 <6>[ 0.519730] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10526 12:16:26.125785 <6>[ 0.526735] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10527 12:16:26.132745 <6>[ 0.533222] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10528 12:16:26.138801 <6>[ 0.540229] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10529 12:16:26.145252 <6>[ 0.546717] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10530 12:16:26.151972 <6>[ 0.553721] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10531 12:16:26.155951 <6>[ 0.561195] ACPI: Interpreter disabled.
10532 12:16:26.164310 <6>[ 0.567622] iommu: Default domain type: Translated
10533 12:16:26.170817 <6>[ 0.572732] iommu: DMA domain TLB invalidation policy: strict mode
10534 12:16:26.174203 <5>[ 0.579392] SCSI subsystem initialized
10535 12:16:26.180562 <6>[ 0.583627] usbcore: registered new interface driver usbfs
10536 12:16:26.187644 <6>[ 0.589358] usbcore: registered new interface driver hub
10537 12:16:26.190518 <6>[ 0.594910] usbcore: registered new device driver usb
10538 12:16:26.197642 <6>[ 0.601017] pps_core: LinuxPPS API ver. 1 registered
10539 12:16:26.207307 <6>[ 0.606209] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10540 12:16:26.210461 <6>[ 0.615552] PTP clock support registered
10541 12:16:26.214290 <6>[ 0.619792] EDAC MC: Ver: 3.0.0
10542 12:16:26.221390 <6>[ 0.624989] FPGA manager framework
10543 12:16:26.228418 <6>[ 0.628666] Advanced Linux Sound Architecture Driver Initialized.
10544 12:16:26.231728 <6>[ 0.635431] vgaarb: loaded
10545 12:16:26.238200 <6>[ 0.638586] clocksource: Switched to clocksource arch_sys_counter
10546 12:16:26.241180 <5>[ 0.645033] VFS: Disk quotas dquot_6.6.0
10547 12:16:26.248603 <6>[ 0.649219] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10548 12:16:26.251417 <6>[ 0.656411] pnp: PnP ACPI: disabled
10549 12:16:26.259816 <6>[ 0.663138] NET: Registered PF_INET protocol family
10550 12:16:26.269399 <6>[ 0.668744] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10551 12:16:26.280885 <6>[ 0.681044] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10552 12:16:26.290800 <6>[ 0.689856] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10553 12:16:26.297666 <6>[ 0.697826] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10554 12:16:26.306999 <6>[ 0.706523] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10555 12:16:26.313915 <6>[ 0.716262] TCP: Hash tables configured (established 65536 bind 65536)
10556 12:16:26.320267 <6>[ 0.723116] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10557 12:16:26.330455 <6>[ 0.730313] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10558 12:16:26.336828 <6>[ 0.737991] NET: Registered PF_UNIX/PF_LOCAL protocol family
10559 12:16:26.340023 <6>[ 0.744082] RPC: Registered named UNIX socket transport module.
10560 12:16:26.347075 <6>[ 0.750230] RPC: Registered udp transport module.
10561 12:16:26.350426 <6>[ 0.755160] RPC: Registered tcp transport module.
10562 12:16:26.359956 <6>[ 0.760093] RPC: Registered tcp NFSv4.1 backchannel transport module.
10563 12:16:26.363125 <6>[ 0.766760] PCI: CLS 0 bytes, default 64
10564 12:16:26.366615 <6>[ 0.771141] Unpacking initramfs...
10565 12:16:26.376528 <6>[ 0.774970] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10566 12:16:26.383170 <6>[ 0.783650] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10567 12:16:26.389585 <6>[ 0.792476] kvm [1]: IPA Size Limit: 40 bits
10568 12:16:26.392625 <6>[ 0.797003] kvm [1]: GICv3: no GICV resource entry
10569 12:16:26.399409 <6>[ 0.802024] kvm [1]: disabling GICv2 emulation
10570 12:16:26.405981 <6>[ 0.806707] kvm [1]: GIC system register CPU interface enabled
10571 12:16:26.409419 <6>[ 0.812875] kvm [1]: vgic interrupt IRQ18
10572 12:16:26.416045 <6>[ 0.817229] kvm [1]: VHE mode initialized successfully
10573 12:16:26.419293 <5>[ 0.823687] Initialise system trusted keyrings
10574 12:16:26.425594 <6>[ 0.828501] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10575 12:16:26.435352 <6>[ 0.838519] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10576 12:16:26.441838 <5>[ 0.844901] NFS: Registering the id_resolver key type
10577 12:16:26.445007 <5>[ 0.850202] Key type id_resolver registered
10578 12:16:26.451413 <5>[ 0.854616] Key type id_legacy registered
10579 12:16:26.457815 <6>[ 0.858912] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10580 12:16:26.465160 <6>[ 0.865829] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10581 12:16:26.471255 <6>[ 0.873576] 9p: Installing v9fs 9p2000 file system support
10582 12:16:26.508407 <5>[ 0.911590] Key type asymmetric registered
10583 12:16:26.511167 <5>[ 0.915919] Asymmetric key parser 'x509' registered
10584 12:16:26.521376 <6>[ 0.921061] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10585 12:16:26.524886 <6>[ 0.928677] io scheduler mq-deadline registered
10586 12:16:26.527845 <6>[ 0.933445] io scheduler kyber registered
10587 12:16:26.546413 <6>[ 0.950176] EINJ: ACPI disabled.
10588 12:16:26.578646 <4>[ 0.975416] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10589 12:16:26.588230 <4>[ 0.986039] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10590 12:16:26.602919 <6>[ 1.006712] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10591 12:16:26.610988 <6>[ 1.014613] printk: console [ttyS0] disabled
10592 12:16:26.638962 <6>[ 1.039257] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10593 12:16:26.645877 <6>[ 1.048729] printk: console [ttyS0] enabled
10594 12:16:26.649199 <6>[ 1.048729] printk: console [ttyS0] enabled
10595 12:16:26.655495 <6>[ 1.057624] printk: bootconsole [mtk8250] disabled
10596 12:16:26.658825 <6>[ 1.057624] printk: bootconsole [mtk8250] disabled
10597 12:16:26.665373 <6>[ 1.068637] SuperH (H)SCI(F) driver initialized
10598 12:16:26.668511 <6>[ 1.073891] msm_serial: driver initialized
10599 12:16:26.682772 <6>[ 1.082756] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10600 12:16:26.692244 <6>[ 1.091299] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10601 12:16:26.699343 <6>[ 1.099843] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10602 12:16:26.708928 <6>[ 1.108474] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10603 12:16:26.718929 <6>[ 1.117180] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10604 12:16:26.725813 <6>[ 1.125899] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10605 12:16:26.735384 <6>[ 1.134440] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10606 12:16:26.741752 <6>[ 1.143248] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10607 12:16:26.751802 <6>[ 1.151790] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10608 12:16:26.763751 <6>[ 1.167390] loop: module loaded
10609 12:16:26.770774 <6>[ 1.173348] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10610 12:16:26.793124 <4>[ 1.196611] mtk-pmic-keys: Failed to locate of_node [id: -1]
10611 12:16:26.799989 <6>[ 1.203323] megasas: 07.719.03.00-rc1
10612 12:16:26.809015 <6>[ 1.212693] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10613 12:16:26.818576 <6>[ 1.221973] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10614 12:16:26.834316 <6>[ 1.237883] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10615 12:16:26.893711 <6>[ 1.290554] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10616 12:16:28.390105 <6>[ 2.793831] Freeing initrd memory: 46252K
10617 12:16:28.400336 <6>[ 2.803772] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10618 12:16:28.410591 <6>[ 2.814660] tun: Universal TUN/TAP device driver, 1.6
10619 12:16:28.414620 <6>[ 2.820715] thunder_xcv, ver 1.0
10620 12:16:28.417708 <6>[ 2.824221] thunder_bgx, ver 1.0
10621 12:16:28.420797 <6>[ 2.827718] nicpf, ver 1.0
10622 12:16:28.431365 <6>[ 2.831717] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10623 12:16:28.434649 <6>[ 2.839193] hns3: Copyright (c) 2017 Huawei Corporation.
10624 12:16:28.441103 <6>[ 2.844781] hclge is initializing
10625 12:16:28.444219 <6>[ 2.848362] e1000: Intel(R) PRO/1000 Network Driver
10626 12:16:28.450908 <6>[ 2.853491] e1000: Copyright (c) 1999-2006 Intel Corporation.
10627 12:16:28.457764 <6>[ 2.859522] e1000e: Intel(R) PRO/1000 Network Driver
10628 12:16:28.460791 <6>[ 2.864741] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10629 12:16:28.467324 <6>[ 2.870927] igb: Intel(R) Gigabit Ethernet Network Driver
10630 12:16:28.474083 <6>[ 2.876578] igb: Copyright (c) 2007-2014 Intel Corporation.
10631 12:16:28.480736 <6>[ 2.882413] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10632 12:16:28.487333 <6>[ 2.888932] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10633 12:16:28.490737 <6>[ 2.895389] sky2: driver version 1.30
10634 12:16:28.497678 <6>[ 2.900358] VFIO - User Level meta-driver version: 0.3
10635 12:16:28.504668 <6>[ 2.908565] usbcore: registered new interface driver usb-storage
10636 12:16:28.511273 <6>[ 2.915012] usbcore: registered new device driver onboard-usb-hub
10637 12:16:28.520390 <6>[ 2.924110] mt6397-rtc mt6359-rtc: registered as rtc0
10638 12:16:28.530240 <6>[ 2.929594] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:16:34 UTC (1686053794)
10639 12:16:28.533431 <6>[ 2.939208] i2c_dev: i2c /dev entries driver
10640 12:16:28.550254 <6>[ 2.950793] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10641 12:16:28.557732 <6>[ 2.960973] sdhci: Secure Digital Host Controller Interface driver
10642 12:16:28.563811 <6>[ 2.967409] sdhci: Copyright(c) Pierre Ossman
10643 12:16:28.570728 <6>[ 2.972803] Synopsys Designware Multimedia Card Interface Driver
10644 12:16:28.573664 <6>[ 2.979426] mmc0: CQHCI version 5.10
10645 12:16:28.580005 <6>[ 2.979952] sdhci-pltfm: SDHCI platform and OF driver helper
10646 12:16:28.588402 <6>[ 2.991685] ledtrig-cpu: registered to indicate activity on CPUs
10647 12:16:28.598614 <6>[ 2.999076] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10648 12:16:28.605176 <6>[ 3.006482] usbcore: registered new interface driver usbhid
10649 12:16:28.608345 <6>[ 3.012317] usbhid: USB HID core driver
10650 12:16:28.615283 <6>[ 3.016560] spi_master spi0: will run message pump with realtime priority
10651 12:16:28.664216 <6>[ 3.061826] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10652 12:16:28.683461 <6>[ 3.077201] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10653 12:16:28.686849 <6>[ 3.090745] mmc0: Command Queue Engine enabled
10654 12:16:28.693811 <6>[ 3.092312] cros-ec-spi spi0.0: Chrome EC device registered
10655 12:16:28.700641 <6>[ 3.095490] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10656 12:16:28.703955 <6>[ 3.108633] mmcblk0: mmc0:0001 DA4128 116 GiB
10657 12:16:28.717562 <6>[ 3.118378] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10658 12:16:28.724718 <6>[ 3.120693] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10659 12:16:28.731197 <6>[ 3.129784] NET: Registered PF_PACKET protocol family
10660 12:16:28.734299 <6>[ 3.134729] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10661 12:16:28.740549 <6>[ 3.139046] 9pnet: Installing 9P2000 support
10662 12:16:28.744138 <6>[ 3.144784] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10663 12:16:28.750537 <5>[ 3.148712] Key type dns_resolver registered
10664 12:16:28.757047 <6>[ 3.154529] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10665 12:16:28.760422 <6>[ 3.159043] registered taskstats version 1
10666 12:16:28.764239 <5>[ 3.169319] Loading compiled-in X.509 certificates
10667 12:16:28.799058 <4>[ 3.196589] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10668 12:16:28.809273 <4>[ 3.207266] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10669 12:16:28.819512 <3>[ 3.220042] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10670 12:16:28.831235 <6>[ 3.235608] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10671 12:16:28.838294 <6>[ 3.242358] xhci-mtk 11200000.usb: xHCI Host Controller
10672 12:16:28.844659 <6>[ 3.247863] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10673 12:16:28.854711 <6>[ 3.255710] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10674 12:16:28.861970 <6>[ 3.265142] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10675 12:16:28.868582 <6>[ 3.271374] xhci-mtk 11200000.usb: xHCI Host Controller
10676 12:16:28.874993 <6>[ 3.276870] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10677 12:16:28.881086 <6>[ 3.284532] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10678 12:16:28.888632 <6>[ 3.292421] hub 1-0:1.0: USB hub found
10679 12:16:28.891769 <6>[ 3.296455] hub 1-0:1.0: 1 port detected
10680 12:16:28.901943 <6>[ 3.300815] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10681 12:16:28.904844 <6>[ 3.309611] hub 2-0:1.0: USB hub found
10682 12:16:28.907953 <6>[ 3.313647] hub 2-0:1.0: 1 port detected
10683 12:16:28.916458 <6>[ 3.320817] mtk-msdc 11f70000.mmc: Got CD GPIO
10684 12:16:28.934507 <6>[ 3.335277] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10685 12:16:28.940953 <6>[ 3.343323] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10686 12:16:28.951197 <4>[ 3.351292] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10687 12:16:28.961026 <6>[ 3.360966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10688 12:16:28.967403 <6>[ 3.369049] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10689 12:16:28.977697 <6>[ 3.377084] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10690 12:16:28.984233 <6>[ 3.385001] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10691 12:16:28.990797 <6>[ 3.392822] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10692 12:16:29.000297 <6>[ 3.400650] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10693 12:16:29.010767 <6>[ 3.411280] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10694 12:16:29.020743 <6>[ 3.419652] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10695 12:16:29.026936 <6>[ 3.427996] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10696 12:16:29.037058 <6>[ 3.436339] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10697 12:16:29.044321 <6>[ 3.444682] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10698 12:16:29.053639 <6>[ 3.453025] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10699 12:16:29.060636 <6>[ 3.461368] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10700 12:16:29.069887 <6>[ 3.469711] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10701 12:16:29.077251 <6>[ 3.478053] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10702 12:16:29.086566 <6>[ 3.486397] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10703 12:16:29.093599 <6>[ 3.494749] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10704 12:16:29.103314 <6>[ 3.503092] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10705 12:16:29.109781 <6>[ 3.511435] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10706 12:16:29.120016 <6>[ 3.519781] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10707 12:16:29.126392 <6>[ 3.528129] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10708 12:16:29.132810 <6>[ 3.536981] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10709 12:16:29.140014 <6>[ 3.544452] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10710 12:16:29.147078 <6>[ 3.551550] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10711 12:16:29.157541 <6>[ 3.558714] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10712 12:16:29.164078 <6>[ 3.566046] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10713 12:16:29.174048 <6>[ 3.572955] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10714 12:16:29.181014 <6>[ 3.582097] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10715 12:16:29.190748 <6>[ 3.591224] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10716 12:16:29.200522 <6>[ 3.600527] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10717 12:16:29.210391 <6>[ 3.610004] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10718 12:16:29.220061 <6>[ 3.619478] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10719 12:16:29.230281 <6>[ 3.628604] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10720 12:16:29.236233 <6>[ 3.638078] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10721 12:16:29.246585 <6>[ 3.647204] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10722 12:16:29.256306 <6>[ 3.656512] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10723 12:16:29.269297 <6>[ 3.666678] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10724 12:16:29.275887 <6>[ 3.677883] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10725 12:16:29.297895 <6>[ 3.698858] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10726 12:16:29.325391 <6>[ 3.729380] hub 2-1:1.0: USB hub found
10727 12:16:29.328949 <6>[ 3.733786] hub 2-1:1.0: 3 ports detected
10728 12:16:29.450052 <6>[ 3.850863] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10729 12:16:29.604945 <6>[ 4.008524] hub 1-1:1.0: USB hub found
10730 12:16:29.608138 <6>[ 4.012972] hub 1-1:1.0: 4 ports detected
10731 12:16:29.686667 <6>[ 4.087097] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10732 12:16:29.930002 <6>[ 4.330859] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10733 12:16:30.062525 <6>[ 4.466962] hub 1-1.4:1.0: USB hub found
10734 12:16:30.066330 <6>[ 4.471614] hub 1-1.4:1.0: 2 ports detected
10735 12:16:30.362195 <6>[ 4.762854] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10736 12:16:30.553406 <6>[ 4.954859] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10737 12:16:41.570771 <6>[ 15.979416] ALSA device list:
10738 12:16:41.576830 <6>[ 15.982673] No soundcards found.
10739 12:16:41.589492 <6>[ 15.995051] Freeing unused kernel memory: 8384K
10740 12:16:41.592620 <6>[ 15.999980] Run /init as init process
10741 12:16:41.623493 <6>[ 16.028873] NET: Registered PF_INET6 protocol family
10742 12:16:41.629866 <6>[ 16.035375] Segment Routing with IPv6
10743 12:16:41.632904 <6>[ 16.039372] In-situ OAM (IOAM) with IPv6
10744 12:16:41.668298 <30>[ 16.053690] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10745 12:16:41.671385 <30>[ 16.077483] systemd[1]: Detected architecture arm64.
10746 12:16:41.671496
10747 12:16:41.677604 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10748 12:16:41.677691
10749 12:16:41.697259 <30>[ 16.102937] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10750 12:16:41.847846 <30>[ 16.250209] systemd[1]: Queued start job for default target Graphical Interface.
10751 12:16:41.890777 <30>[ 16.296172] systemd[1]: Created slice system-getty.slice.
10752 12:16:41.897546 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10753 12:16:41.914229 <30>[ 16.319467] systemd[1]: Created slice system-modprobe.slice.
10754 12:16:41.920475 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10755 12:16:41.937697 <30>[ 16.343345] systemd[1]: Created slice system-serial\x2dgetty.slice.
10756 12:16:41.947938 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10757 12:16:41.962450 <30>[ 16.367911] systemd[1]: Created slice User and Session Slice.
10758 12:16:41.968704 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10759 12:16:41.989079 <30>[ 16.391397] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10760 12:16:41.998783 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10761 12:16:42.017376 <30>[ 16.419424] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10762 12:16:42.023828 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10763 12:16:42.043874 <30>[ 16.442892] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10764 12:16:42.050426 <30>[ 16.454913] systemd[1]: Reached target Local Encrypted Volumes.
10765 12:16:42.057111 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10766 12:16:42.073703 <30>[ 16.479218] systemd[1]: Reached target Paths.
10767 12:16:42.076949 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10768 12:16:42.092886 <30>[ 16.498907] systemd[1]: Reached target Remote File Systems.
10769 12:16:42.099631 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10770 12:16:42.113214 <30>[ 16.518843] systemd[1]: Reached target Slices.
10771 12:16:42.116321 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10772 12:16:42.133238 <30>[ 16.538908] systemd[1]: Reached target Swap.
10773 12:16:42.136249 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10774 12:16:42.157040 <30>[ 16.559146] systemd[1]: Listening on initctl Compatibility Named Pipe.
10775 12:16:42.163820 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10776 12:16:42.170242 <30>[ 16.573859] systemd[1]: Listening on Journal Audit Socket.
10777 12:16:42.176708 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10778 12:16:42.190068 <30>[ 16.595159] systemd[1]: Listening on Journal Socket (/dev/log).
10779 12:16:42.196075 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10780 12:16:42.214226 <30>[ 16.619643] systemd[1]: Listening on Journal Socket.
10781 12:16:42.220786 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10782 12:16:42.237034 <30>[ 16.639233] systemd[1]: Listening on Network Service Netlink Socket.
10783 12:16:42.243693 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10784 12:16:42.257855 <30>[ 16.663639] systemd[1]: Listening on udev Control Socket.
10785 12:16:42.264641 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10786 12:16:42.282529 <30>[ 16.687565] systemd[1]: Listening on udev Kernel Socket.
10787 12:16:42.288556 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10788 12:16:42.321654 <30>[ 16.727111] systemd[1]: Mounting Huge Pages File System...
10789 12:16:42.327817 Mounting [0;1;39mHuge Pages File System[0m...
10790 12:16:42.343598 <30>[ 16.748868] systemd[1]: Mounting POSIX Message Queue File System...
10791 12:16:42.350388 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10792 12:16:42.367661 <30>[ 16.772900] systemd[1]: Mounting Kernel Debug File System...
10793 12:16:42.373674 Mounting [0;1;39mKernel Debug File System[0m...
10794 12:16:42.392961 <30>[ 16.795154] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10795 12:16:42.403574 <30>[ 16.806119] systemd[1]: Starting Create list of static device nodes for the current kernel...
10796 12:16:42.410464 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10797 12:16:42.427610 <30>[ 16.833221] systemd[1]: Starting Load Kernel Module configfs...
10798 12:16:42.434321 Starting [0;1;39mLoad Kernel Module configfs[0m...
10799 12:16:42.451631 <30>[ 16.857217] systemd[1]: Starting Load Kernel Module drm...
10800 12:16:42.458642 Starting [0;1;39mLoad Kernel Module drm[0m...
10801 12:16:42.476852 <30>[ 16.879087] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10802 12:16:42.510091 <30>[ 16.915531] systemd[1]: Starting Journal Service...
10803 12:16:42.513180 Starting [0;1;39mJournal Service[0m...
10804 12:16:42.532208 <30>[ 16.937669] systemd[1]: Starting Load Kernel Modules...
10805 12:16:42.538556 Starting [0;1;39mLoad Kernel Modules[0m...
10806 12:16:42.559563 <30>[ 16.961612] systemd[1]: Starting Remount Root and Kernel File Systems...
10807 12:16:42.565644 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10808 12:16:42.580184 <30>[ 16.985429] systemd[1]: Starting Coldplug All udev Devices...
10809 12:16:42.586394 Starting [0;1;39mColdplug All udev Devices[0m...
10810 12:16:42.603968 <30>[ 17.009513] systemd[1]: Mounted Huge Pages File System.
10811 12:16:42.610672 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10812 12:16:42.626357 <30>[ 17.031683] systemd[1]: Started Journal Service.
10813 12:16:42.632615 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10814 12:16:42.646778 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10815 12:16:42.662214 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10816 12:16:42.681404 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10817 12:16:42.703222 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10818 12:16:42.718799 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10819 12:16:42.734337 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10820 12:16:42.758798 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10821 12:16:42.773009 See 'systemctl status systemd-remount-fs.service' for details.
10822 12:16:42.826436 Mounting [0;1;39mKernel Configuration File System[0m...
10823 12:16:42.844324 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10824 12:16:42.860906 <46>[ 17.263467] systemd-journald[174]: Received client request to flush runtime journal.
10825 12:16:42.869540 Starting [0;1;39mLoad/Save Random Seed[0m...
10826 12:16:42.888601 Starting [0;1;39mApply Kernel Variables[0m...
10827 12:16:42.905330 Starting [0;1;39mCreate System Users[0m...
10828 12:16:42.925662 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10829 12:16:42.945608 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10830 12:16:42.962446 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10831 12:16:42.978084 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10832 12:16:42.998472 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10833 12:16:43.018322 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10834 12:16:43.069913 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10835 12:16:43.092227 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10836 12:16:43.105597 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10837 12:16:43.125265 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10838 12:16:43.173672 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10839 12:16:43.200976 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10840 12:16:43.222043 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10841 12:16:43.241750 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10842 12:16:43.286701 Starting [0;1;39mNetwork Service[0m...
10843 12:16:43.310456 Starting [0;1;39mNetwork Time Synchronization[0m...
10844 12:16:43.330180 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10845 12:16:43.367716 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10846 12:16:43.390205 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10847 12:16:43.422246 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10848 12:16:43.433093 <6>[ 17.835794] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10849 12:16:43.446806 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10850 12:16:43.453481 <6>[ 17.858952] remoteproc remoteproc0: scp is available
10851 12:16:43.463280 <4>[ 17.864466] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10852 12:16:43.469623 <6>[ 17.874782] remoteproc remoteproc0: powering up scp
10853 12:16:43.479647 <4>[ 17.880215] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10854 12:16:43.486466 <3>[ 17.890061] remoteproc remoteproc0: request_firmware failed: -2
10855 12:16:43.496398 <3>[ 17.898120] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 12:16:43.502622 <6>[ 17.905788] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10857 12:16:43.512817 <3>[ 17.906271] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 12:16:43.519297 <6>[ 17.914823] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10859 12:16:43.526156 <3>[ 17.922034] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 12:16:43.535749 <6>[ 17.929645] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10861 12:16:43.545482 <6>[ 17.946510] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10862 12:16:43.555291 [[0;32m OK [<4>[ 17.956093] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10863 12:16:43.558790 <4>[ 17.956093] Fallback method does not support PEC.
10864 12:16:43.569041 0m] Created slic<3>[ 17.957212] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10865 12:16:43.578363 e [0;1;39msyste<3>[ 17.980220] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10866 12:16:43.588196 m-systemd\x2dbac<3>[ 17.989403] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 12:16:43.598123 klight.slice[0m<3>[ 17.998828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10868 12:16:43.598209 .
10869 12:16:43.604947 <3>[ 18.008383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 12:16:43.618337 [[0;32m OK [0m] Reached target [0;1;39mSyst<3>[ 18.021174] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 12:16:43.621707 em Time Set[0m.
10872 12:16:43.625234 <6>[ 18.031733] mc: Linux media interface: v0.10
10873 12:16:43.640701 [[0;32m OK [<3>[ 18.043371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 12:16:43.651134 0m] Reached targ<4>[ 18.047547] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10875 12:16:43.661156 <3>[ 18.050610] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 12:16:43.667337 <3>[ 18.067828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 12:16:43.677334 et [0;1;39mSyst<4>[ 18.070436] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10878 12:16:43.684293 <3>[ 18.079623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10879 12:16:43.690506 em Time Synchron<6>[ 18.091292] usbcore: registered new interface driver r8152
10880 12:16:43.700659 <3>[ 18.095142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 12:16:43.700745 ized[0m.
10882 12:16:43.707234 <6>[ 18.096038] videodev: Linux video capture interface: v2.00
10883 12:16:43.714134 <6>[ 18.101527] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10884 12:16:43.720248 <6>[ 18.101542] pci_bus 0000:00: root bus resource [bus 00-ff]
10885 12:16:43.727068 <6>[ 18.101553] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10886 12:16:43.736825 <6>[ 18.101558] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10887 12:16:43.743345 <6>[ 18.101599] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10888 12:16:43.750584 <6>[ 18.101622] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10889 12:16:43.754287 <6>[ 18.101706] pci 0000:00:00.0: supports D1 D2
10890 12:16:43.760463 <6>[ 18.101710] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10891 12:16:43.770671 <6>[ 18.104963] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10892 12:16:43.777618 <3>[ 18.110516] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10893 12:16:43.783786 <6>[ 18.117573] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10894 12:16:43.793837 <3>[ 18.123913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10895 12:16:43.800196 <3>[ 18.123944] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10896 12:16:43.810436 <3>[ 18.123968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10897 12:16:43.817005 <3>[ 18.123983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10898 12:16:43.823780 <6>[ 18.130286] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10899 12:16:43.834107 <3>[ 18.137470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10900 12:16:43.840603 <6>[ 18.147347] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10901 12:16:43.850286 <6>[ 18.163245] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10902 12:16:43.857370 <6>[ 18.165537] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10903 12:16:43.867203 <3>[ 18.169452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 12:16:43.876940 <6>[ 18.173076] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10905 12:16:43.879915 <6>[ 18.181218] pci 0000:01:00.0: supports D1 D2
10906 12:16:43.886777 <6>[ 18.191165] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10907 12:16:43.893293 <6>[ 18.195198] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10908 12:16:43.904172 <6>[ 18.195213] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10909 12:16:43.910485 <6>[ 18.219766] usbcore: registered new interface driver cdc_ether
10910 12:16:43.920469 <4>[ 18.230959] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10911 12:16:43.924024 <6>[ 18.236337] Bluetooth: Core ver 2.22
10912 12:16:43.930941 <6>[ 18.238668] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10913 12:16:43.937328 <6>[ 18.238708] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10914 12:16:43.947027 <6>[ 18.238717] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10915 12:16:43.953548 <6>[ 18.238730] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10916 12:16:43.963529 <6>[ 18.238746] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10917 12:16:43.970049 <6>[ 18.238762] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10918 12:16:43.977280 <6>[ 18.238777] pci 0000:00:00.0: PCI bridge to [bus 01]
10919 12:16:43.983937 <6>[ 18.238785] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10920 12:16:43.990382 <6>[ 18.238964] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10921 12:16:43.997314 <6>[ 18.239841] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10922 12:16:44.004072 <4>[ 18.243437] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10923 12:16:44.010972 <6>[ 18.243801] usbcore: registered new interface driver r8153_ecm
10924 12:16:44.017610 <6>[ 18.243805] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10925 12:16:44.020312 <6>[ 18.251483] NET: Registered PF_BLUETOOTH protocol family
10926 12:16:44.030566 <5>[ 18.271844] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10927 12:16:44.037589 <6>[ 18.277740] Bluetooth: HCI device and connection manager initialized
10928 12:16:44.044365 <6>[ 18.286813] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10929 12:16:44.050524 <6>[ 18.287759] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10930 12:16:44.054290 <6>[ 18.291588] Bluetooth: HCI socket layer initialized
10931 12:16:44.060845 <6>[ 18.293217] remoteproc remoteproc0: powering up scp
10932 12:16:44.070255 <4>[ 18.293270] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10933 12:16:44.077421 <3>[ 18.293280] remoteproc remoteproc0: request_firmware failed: -2
10934 12:16:44.083519 <3>[ 18.293284] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10935 12:16:44.093394 <3>[ 18.299077] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10936 12:16:44.100292 <5>[ 18.301101] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10937 12:16:44.107175 <4>[ 18.301192] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10938 12:16:44.113722 <6>[ 18.301201] cfg80211: failed to load regulatory.db
10939 12:16:44.120238 <6>[ 18.305822] Bluetooth: L2CAP socket layer initialized
10940 12:16:44.130220 <6>[ 18.308794] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10941 12:16:44.136847 <6>[ 18.308976] usbcore: registered new interface driver uvcvideo
10942 12:16:44.146742 <3>[ 18.312953] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 12:16:44.153507 <3>[ 18.313814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10944 12:16:44.163396 <3>[ 18.341985] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 12:16:44.169620 <6>[ 18.349031] Bluetooth: SCO socket layer initialized
10946 12:16:44.172976 <6>[ 18.371087] r8152 2-1.3:1.0 eth0: v1.12.13
10947 12:16:44.183061 <3>[ 18.392623] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 12:16:44.189658 <6>[ 18.393128] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10949 12:16:44.196424 <6>[ 18.393241] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10950 12:16:44.202617 <6>[ 18.405857] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10951 12:16:44.206320 <6>[ 18.410755] mt7921e 0000:01:00.0: ASIC revision: 79610010
10952 12:16:44.212759 <6>[ 18.421687] usbcore: registered new interface driver btusb
10953 12:16:44.222649 <4>[ 18.422257] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10954 12:16:44.229223 <3>[ 18.422268] Bluetooth: hci0: Failed to load firmware file (-2)
10955 12:16:44.235905 <3>[ 18.422271] Bluetooth: hci0: Failed to set up firmware (-2)
10956 12:16:44.245892 <4>[ 18.422274] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10957 12:16:44.255843 <3>[ 18.435427] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 12:16:44.265316 <4>[ 18.529538] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10959 12:16:44.275671 <3>[ 18.563760] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 12:16:44.285118 <4>[ 18.676961] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10961 12:16:44.292047 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10962 12:16:44.345671 Starting [0;1;39mNetwork Name Resolution[0m...
10963 12:16:44.365640 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10964 12:16:44.407638 <4>[ 18.806817] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10965 12:16:44.491972 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10966 12:16:44.525889 <4>[ 18.925123] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10967 12:16:44.567932 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10968 12:16:44.581610 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10969 12:16:44.600638 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10970 12:16:44.613229 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10971 12:16:44.634258 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10972 12:16:44.647585 <4>[ 19.045530] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10973 12:16:44.654192 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10974 12:16:44.660397 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10975 12:16:44.681134 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10976 12:16:44.693503 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10977 12:16:44.709010 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10978 12:16:44.728657 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10979 12:16:44.765841 <4>[ 19.164926] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10980 12:16:44.779654 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10981 12:16:44.808333 Starting [0;1;39mUser Login Management[0m...
10982 12:16:44.823936 Starting [0;1;39mPermit User Sessions[0m...
10983 12:16:44.841134 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10984 12:16:44.857750 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10985 12:16:44.878311 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10986 12:16:44.892599 <4>[ 19.291911] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10987 12:16:44.942293 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10988 12:16:44.959772 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10989 12:16:44.977386 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10990 12:16:44.994815 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10991 12:16:45.003495 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10992 12:16:45.018792 <4>[ 19.418096] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10993 12:16:45.025092 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10994 12:16:45.089282 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10995 12:16:45.114768 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10996 12:16:45.143463 <4>[ 19.542715] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10997 12:16:45.143583
10998 12:16:45.143650
10999 12:16:45.150257 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11000 12:16:45.150365
11001 12:16:45.153139 debian-bullseye-arm64 login: root (automatic login)
11002 12:16:45.153275
11003 12:16:45.153354
11004 12:16:45.177102 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023 aarch64
11005 12:16:45.177269
11006 12:16:45.183789 The programs included with the Debian GNU/Linux system are free software;
11007 12:16:45.190730 the exact distribution terms for each program are described in the
11008 12:16:45.194140 individual files in /usr/share/doc/*/copyright.
11009 12:16:45.194223
11010 12:16:45.200378 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11011 12:16:45.204323 permitted by applicable law.
11012 12:16:45.204667 Matched prompt #10: / #
11014 12:16:45.204897 Setting prompt string to ['/ #']
11015 12:16:45.204990 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11017 12:16:45.205182 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11018 12:16:45.205268 start: 2.2.6 expect-shell-connection (timeout 00:02:55) [common]
11019 12:16:45.205339 Setting prompt string to ['/ #']
11020 12:16:45.205398 Forcing a shell prompt, looking for ['/ #']
11022 12:16:45.255623 / #
11023 12:16:45.255784 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11024 12:16:45.255904 Waiting using forced prompt support (timeout 00:02:30)
11025 12:16:45.302995 <4>[ 19.665087] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11026 12:16:45.303129
11027 12:16:45.303402 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11028 12:16:45.303496 start: 2.2.7 export-device-env (timeout 00:02:55) [common]
11029 12:16:45.303589 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11030 12:16:45.303671 end: 2.2 depthcharge-retry (duration 00:02:05) [common]
11031 12:16:45.303756 end: 2 depthcharge-action (duration 00:02:05) [common]
11032 12:16:45.303841 start: 3 lava-test-retry (timeout 00:05:00) [common]
11033 12:16:45.303924 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11034 12:16:45.303993 Using namespace: common
11036 12:16:45.404312 / # #
11037 12:16:45.404506 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11038 12:16:45.404652 #<3>[ 19.782924] mt7921e 0000:01:00.0: hardware init failed
11039 12:16:45.409116
11040 12:16:45.409397 Using /lava-10605437
11042 12:16:45.509794 / # export SHELL=/bin/sh
11043 12:16:45.514871 export SHELL=/bin/sh
11045 12:16:45.615417 / # . /lava-10605437/environment
11046 12:16:45.620477 . /lava-10605437/environment
11048 12:16:45.721023 / # /lava-10605437/bin/lava-test-runner /lava-10605437/0
11049 12:16:45.721183 Test shell timeout: 10s (minimum of the action and connection timeout)
11050 12:16:45.726788 /lava-10605437/bin/lava-test-runner /lava-10605437/0
11051 12:16:45.745839 + export TESTRUN_ID=0_cros-ec
11052 12:16:45.752453 +<8>[ 20.156870] <LAVA_SIGNAL_STARTRUN 0_cros-ec 10605437_1.5.2.3.1>
11053 12:16:45.752735 Received signal: <STARTRUN> 0_cros-ec 10605437_1.5.2.3.1
11054 12:16:45.752839 Starting test lava.0_cros-ec (10605437_1.5.2.3.1)
11055 12:16:45.752956 Skipping test definition patterns.
11056 12:16:45.755614 cd /lava-10605437/0/tests/0_cros-ec
11057 12:16:45.759178 + cat uuid
11058 12:16:45.759288 + UUID=10605437_1.5.2.3.1
11059 12:16:45.762295 + set +x
11060 12:16:45.765924 + python3 -m cros.runners.lava_runner -v
11061 12:16:45.932995 <6>[ 20.335333] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11062 12:16:45.938873 <6>[ 20.343487] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11063 12:16:46.458411 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11064 12:16:46.465288 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11065 12:16:46.468325
11066 12:16:46.471538 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11068 12:16:46.474703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11069 12:16:46.481401 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11070 12:16:46.487775 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11071 12:16:46.487858
11072 12:16:46.498032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11073 12:16:46.498290 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11075 12:16:46.501267 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11076 12:16:46.511626 Checks the cros-ec gyros<8>[ 20.915122] <LAVA_SIGNAL_ENDRUN 0_cros-ec 10605437_1.5.2.3.1>
11077 12:16:46.511888 Received signal: <ENDRUN> 0_cros-ec 10605437_1.5.2.3.1
11078 12:16:46.511982 Ending use of test pattern.
11079 12:16:46.512055 Ending test lava.0_cros-ec (10605437_1.5.2.3.1), duration 0.76
11081 12:16:46.514346 cope IIO ABI. ... skipped 'No cros-ec-gyro found'
11082 12:16:46.514433
11083 12:16:46.521404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11084 12:16:46.521664 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11086 12:16:46.527464 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11087 12:16:46.534198 Checks the standard ABI for the main Embedded Controller. ... ok
11088 12:16:46.534283
11089 12:16:46.537289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11090 12:16:46.537539 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11092 12:16:46.544160 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11093 12:16:46.551074 Checks the main Embedded controller character device. ... ok
11094 12:16:46.551158
11095 12:16:46.553864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11096 12:16:46.554115 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11098 12:16:46.560705 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11099 12:16:46.567321 Checks basic comunication with the main Embedded controller. ... ok
11100 12:16:46.567424
11101 12:16:46.574056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11102 12:16:46.574313 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11104 12:16:46.576944 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11105 12:16:46.587113 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11106 12:16:46.587202
11107 12:16:46.590216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11108 12:16:46.590467 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11110 12:16:46.597053 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11111 12:16:46.603293 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11112 12:16:46.603375
11113 12:16:46.610371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11114 12:16:46.610619 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11116 12:16:46.616345 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11117 12:16:46.623619 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11118 12:16:46.623707
11119 12:16:46.629571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11120 12:16:46.629827 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11122 12:16:46.633362 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11123 12:16:46.642812 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11124 12:16:46.642934
11125 12:16:46.646020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11126 12:16:46.646281 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11128 12:16:46.653117 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11129 12:16:46.662733 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11130 12:16:46.662862
11131 12:16:46.666257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11132 12:16:46.666501 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11134 12:16:46.672733 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11135 12:16:46.679467 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11136 12:16:46.679544
11137 12:16:46.685977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11138 12:16:46.686256 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11140 12:16:46.692682 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11141 12:16:46.698761 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11142 12:16:46.698918
11143 12:16:46.705413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11144 12:16:46.705672 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11146 12:16:46.712320 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11147 12:16:46.718729 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11148 12:16:46.718841
11149 12:16:46.725596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11150 12:16:46.725856 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11152 12:16:46.732047 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11153 12:16:46.738778 Check the cros battery ABI. ... skipped 'No BAT found'
11154 12:16:46.738919
11155 12:16:46.745518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11156 12:16:46.745801 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11158 12:16:46.751856 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11159 12:16:46.758235 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11160 12:16:46.758314
11161 12:16:46.764936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11162 12:16:46.765211 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11164 12:16:46.768617 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11165 12:16:46.774656 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11166 12:16:46.778380
11167 12:16:46.781317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11168 12:16:46.781592 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11170 12:16:46.788342 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11171 12:16:46.794989 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11172 12:16:46.795073
11173 12:16:46.801165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11174 12:16:46.801248
11175 12:16:46.801481 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11177 12:16:46.807830 ----------------------------------------------------------------------
11178 12:16:46.811607 Ran 18 tests in 0.010s
11179 12:16:46.811688
11180 12:16:46.811752 OK (skipped=15)
11181 12:16:46.814633 + set +x
11182 12:16:46.814716 <LAVA_TEST_RUNNER EXIT>
11183 12:16:46.814951 ok: lava_test_shell seems to have completed
11184 12:16:46.815118 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11185 12:16:46.815212 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11186 12:16:46.815296 end: 3 lava-test-retry (duration 00:00:02) [common]
11187 12:16:46.815379 start: 4 finalize (timeout 00:07:32) [common]
11188 12:16:46.815464 start: 4.1 power-off (timeout 00:00:30) [common]
11189 12:16:46.815615 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11190 12:16:46.891306 >> Command sent successfully.
11191 12:16:46.893762 Returned 0 in 0 seconds
11192 12:16:46.994165 end: 4.1 power-off (duration 00:00:00) [common]
11194 12:16:46.994486 start: 4.2 read-feedback (timeout 00:07:32) [common]
11195 12:16:46.994739 Listened to connection for namespace 'common' for up to 1s
11196 12:16:47.994912 Finalising connection for namespace 'common'
11197 12:16:47.995118 Disconnecting from shell: Finalise
11198 12:16:47.995219 / #
11199 12:16:48.095522 end: 4.2 read-feedback (duration 00:00:01) [common]
11200 12:16:48.095708 end: 4 finalize (duration 00:00:01) [common]
11201 12:16:48.095850 Cleaning after the job
11202 12:16:48.095977 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/ramdisk
11203 12:16:48.100846 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/kernel
11204 12:16:48.106758 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/dtb
11205 12:16:48.106980 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605437/tftp-deploy-0d56fqfp/modules
11206 12:16:48.112402 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605437
11207 12:16:48.212074 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605437
11208 12:16:48.212250 Job finished correctly