Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 34
1 12:16:36.134448 lava-dispatcher, installed at version: 2023.05.1
2 12:16:36.134652 start: 0 validate
3 12:16:36.134784 Start time: 2023-06-06 12:16:36.134775+00:00 (UTC)
4 12:16:36.134903 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:16:36.135026 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 12:16:36.419538 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:16:36.419727 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:16:36.705623 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:16:36.706365 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:16:36.993232 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:16:36.993971 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:16:37.284735 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:16:37.285385 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:16:37.582002 validate duration: 1.45
16 12:16:37.583174 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:16:37.583670 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:16:37.584210 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:16:37.584831 Not decompressing ramdisk as can be used compressed.
20 12:16:37.585267 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/initrd.cpio.gz
21 12:16:37.585624 saving as /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/ramdisk/initrd.cpio.gz
22 12:16:37.585954 total size: 5624321 (5MB)
23 12:16:37.590860 progress 0% (0MB)
24 12:16:37.599171 progress 5% (0MB)
25 12:16:37.605744 progress 10% (0MB)
26 12:16:37.609815 progress 15% (0MB)
27 12:16:37.613642 progress 20% (1MB)
28 12:16:37.616706 progress 25% (1MB)
29 12:16:37.619555 progress 30% (1MB)
30 12:16:37.622337 progress 35% (1MB)
31 12:16:37.624487 progress 40% (2MB)
32 12:16:37.626896 progress 45% (2MB)
33 12:16:37.628794 progress 50% (2MB)
34 12:16:37.630891 progress 55% (2MB)
35 12:16:37.632699 progress 60% (3MB)
36 12:16:37.634579 progress 65% (3MB)
37 12:16:37.636472 progress 70% (3MB)
38 12:16:37.638062 progress 75% (4MB)
39 12:16:37.639811 progress 80% (4MB)
40 12:16:37.641349 progress 85% (4MB)
41 12:16:37.642955 progress 90% (4MB)
42 12:16:37.644487 progress 95% (5MB)
43 12:16:37.645897 progress 100% (5MB)
44 12:16:37.646086 5MB downloaded in 0.06s (89.19MB/s)
45 12:16:37.646241 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:16:37.646481 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:16:37.646569 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:16:37.646655 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:16:37.646783 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:16:37.646856 saving as /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/kernel/Image
52 12:16:37.646918 total size: 45746688 (43MB)
53 12:16:37.646979 No compression specified
54 12:16:37.648083 progress 0% (0MB)
55 12:16:37.659466 progress 5% (2MB)
56 12:16:37.670971 progress 10% (4MB)
57 12:16:37.682362 progress 15% (6MB)
58 12:16:37.693733 progress 20% (8MB)
59 12:16:37.705208 progress 25% (10MB)
60 12:16:37.716624 progress 30% (13MB)
61 12:16:37.728046 progress 35% (15MB)
62 12:16:37.739533 progress 40% (17MB)
63 12:16:37.751167 progress 45% (19MB)
64 12:16:37.762710 progress 50% (21MB)
65 12:16:37.774155 progress 55% (24MB)
66 12:16:37.785903 progress 60% (26MB)
67 12:16:37.797450 progress 65% (28MB)
68 12:16:37.808931 progress 70% (30MB)
69 12:16:37.820372 progress 75% (32MB)
70 12:16:37.831659 progress 80% (34MB)
71 12:16:37.843131 progress 85% (37MB)
72 12:16:37.854913 progress 90% (39MB)
73 12:16:37.866302 progress 95% (41MB)
74 12:16:37.877627 progress 100% (43MB)
75 12:16:37.877752 43MB downloaded in 0.23s (189.00MB/s)
76 12:16:37.877899 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:16:37.878132 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:16:37.878223 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:16:37.878312 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:16:37.878444 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:16:37.878515 saving as /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/dtb/mt8192-asurada-spherion-r0.dtb
83 12:16:37.878581 total size: 46924 (0MB)
84 12:16:37.878643 No compression specified
85 12:16:37.879754 progress 69% (0MB)
86 12:16:37.880023 progress 100% (0MB)
87 12:16:37.880177 0MB downloaded in 0.00s (28.09MB/s)
88 12:16:37.880297 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:16:37.880525 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:16:37.880650 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:16:37.880733 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:16:37.880843 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 12:16:37.880911 saving as /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/nfsrootfs/full.rootfs.tar
95 12:16:37.880971 total size: 195125384 (186MB)
96 12:16:37.881031 Using unxz to decompress xz
97 12:16:37.884624 progress 0% (0MB)
98 12:16:38.431556 progress 5% (9MB)
99 12:16:38.920684 progress 10% (18MB)
100 12:16:39.496601 progress 15% (27MB)
101 12:16:39.772336 progress 20% (37MB)
102 12:16:40.216564 progress 25% (46MB)
103 12:16:40.793134 progress 30% (55MB)
104 12:16:41.333824 progress 35% (65MB)
105 12:16:41.881860 progress 40% (74MB)
106 12:16:42.453806 progress 45% (83MB)
107 12:16:43.058386 progress 50% (93MB)
108 12:16:43.647129 progress 55% (102MB)
109 12:16:44.281325 progress 60% (111MB)
110 12:16:44.670855 progress 65% (120MB)
111 12:16:44.748407 progress 70% (130MB)
112 12:16:44.895886 progress 75% (139MB)
113 12:16:44.968713 progress 80% (148MB)
114 12:16:45.015017 progress 85% (158MB)
115 12:16:45.103008 progress 90% (167MB)
116 12:16:45.466448 progress 95% (176MB)
117 12:16:46.020121 progress 100% (186MB)
118 12:16:46.026168 186MB downloaded in 8.15s (22.85MB/s)
119 12:16:46.026458 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:16:46.026722 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:16:46.026814 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:16:46.026904 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:16:46.027052 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:16:46.027127 saving as /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/modules/modules.tar
126 12:16:46.027190 total size: 8553528 (8MB)
127 12:16:46.027254 Using unxz to decompress xz
128 12:16:46.030944 progress 0% (0MB)
129 12:16:46.051506 progress 5% (0MB)
130 12:16:46.074660 progress 10% (0MB)
131 12:16:46.104967 progress 15% (1MB)
132 12:16:46.130232 progress 20% (1MB)
133 12:16:46.154474 progress 25% (2MB)
134 12:16:46.178871 progress 30% (2MB)
135 12:16:46.204376 progress 35% (2MB)
136 12:16:46.228486 progress 40% (3MB)
137 12:16:46.253201 progress 45% (3MB)
138 12:16:46.277579 progress 50% (4MB)
139 12:16:46.301555 progress 55% (4MB)
140 12:16:46.324668 progress 60% (4MB)
141 12:16:46.348315 progress 65% (5MB)
142 12:16:46.374148 progress 70% (5MB)
143 12:16:46.399014 progress 75% (6MB)
144 12:16:46.424904 progress 80% (6MB)
145 12:16:46.449386 progress 85% (6MB)
146 12:16:46.473742 progress 90% (7MB)
147 12:16:46.496931 progress 95% (7MB)
148 12:16:46.523826 progress 100% (8MB)
149 12:16:46.528370 8MB downloaded in 0.50s (16.28MB/s)
150 12:16:46.528677 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:16:46.528937 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:16:46.529085 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:16:46.529229 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:16:50.132268 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10605447/extract-nfsrootfs-apxzj0_7
156 12:16:50.132469 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:16:50.132611 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:16:50.132776 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse
159 12:16:50.132903 makedir: /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin
160 12:16:50.133005 makedir: /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/tests
161 12:16:50.133099 makedir: /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/results
162 12:16:50.133199 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-add-keys
163 12:16:50.133339 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-add-sources
164 12:16:50.133461 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-background-process-start
165 12:16:50.133589 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-background-process-stop
166 12:16:50.133710 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-common-functions
167 12:16:50.133836 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-echo-ipv4
168 12:16:50.133956 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-install-packages
169 12:16:50.134075 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-installed-packages
170 12:16:50.134192 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-os-build
171 12:16:50.134311 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-probe-channel
172 12:16:50.134430 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-probe-ip
173 12:16:50.134586 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-target-ip
174 12:16:50.134704 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-target-mac
175 12:16:50.134843 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-target-storage
176 12:16:50.134978 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-test-case
177 12:16:50.135097 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-test-event
178 12:16:50.135216 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-test-feedback
179 12:16:50.135335 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-test-raise
180 12:16:50.135452 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-test-reference
181 12:16:50.135573 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-test-runner
182 12:16:50.135692 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-test-set
183 12:16:50.135811 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-test-shell
184 12:16:50.135931 Updating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-add-keys (debian)
185 12:16:50.136076 Updating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-add-sources (debian)
186 12:16:50.136219 Updating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-install-packages (debian)
187 12:16:50.136358 Updating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-installed-packages (debian)
188 12:16:50.136494 Updating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/bin/lava-os-build (debian)
189 12:16:50.136656 Creating /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/environment
190 12:16:50.136753 LAVA metadata
191 12:16:50.136822 - LAVA_JOB_ID=10605447
192 12:16:50.136885 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:16:50.136982 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:16:50.137047 skipped lava-vland-overlay
195 12:16:50.137120 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:16:50.137198 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:16:50.137261 skipped lava-multinode-overlay
198 12:16:50.137334 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:16:50.137411 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:16:50.137482 Loading test definitions
201 12:16:50.137573 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:16:50.137643 Using /lava-10605447 at stage 0
203 12:16:50.137910 uuid=10605447_1.6.2.3.1 testdef=None
204 12:16:50.137998 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:16:50.138113 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:16:50.138549 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:16:50.138773 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:16:50.139310 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:16:50.139541 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:16:50.140063 runner path: /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/0/tests/0_timesync-off test_uuid 10605447_1.6.2.3.1
213 12:16:50.140212 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:16:50.140437 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:16:50.140707 Using /lava-10605447 at stage 0
217 12:16:50.140809 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:16:50.140888 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/0/tests/1_kselftest-alsa'
219 12:16:56.558120 Running '/usr/bin/git checkout kernelci.org
220 12:16:56.708121 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 12:16:56.708891 uuid=10605447_1.6.2.3.5 testdef=None
222 12:16:56.709048 end: 1.6.2.3.5 git-repo-action (duration 00:00:07) [common]
224 12:16:56.709295 start: 1.6.2.3.6 test-overlay (timeout 00:09:41) [common]
225 12:16:56.710034 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:16:56.710266 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:41) [common]
228 12:16:56.711236 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:16:56.711473 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:41) [common]
231 12:16:56.712407 runner path: /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/0/tests/1_kselftest-alsa test_uuid 10605447_1.6.2.3.5
232 12:16:56.712501 BOARD='mt8192-asurada-spherion-r0'
233 12:16:56.712609 BRANCH='cip-gitlab'
234 12:16:56.712671 SKIPFILE='/dev/null'
235 12:16:56.712731 SKIP_INSTALL='True'
236 12:16:56.712789 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:16:56.712848 TST_CASENAME=''
238 12:16:56.712904 TST_CMDFILES='alsa'
239 12:16:56.713046 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:16:56.713258 Creating lava-test-runner.conf files
242 12:16:56.713323 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605447/lava-overlay-nyiz0zse/lava-10605447/0 for stage 0
243 12:16:56.713415 - 0_timesync-off
244 12:16:56.713486 - 1_kselftest-alsa
245 12:16:56.713583 end: 1.6.2.3 test-definition (duration 00:00:07) [common]
246 12:16:56.713671 start: 1.6.2.4 compress-overlay (timeout 00:09:41) [common]
247 12:17:04.210021 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 12:17:04.210186 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 12:17:04.210316 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:17:04.210416 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
251 12:17:04.210506 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 12:17:04.373059 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:17:04.373434 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
254 12:17:04.373547 extracting modules file /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605447/extract-nfsrootfs-apxzj0_7
255 12:17:04.583498 extracting modules file /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605447/extract-overlay-ramdisk-vbmq8ww8/ramdisk
256 12:17:04.792495 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:17:04.792684 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
258 12:17:04.792781 [common] Applying overlay to NFS
259 12:17:04.792854 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605447/compress-overlay-l1rwui4k/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605447/extract-nfsrootfs-apxzj0_7
260 12:17:05.704841 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:17:05.705027 start: 1.6.6 configure-preseed-file (timeout 00:09:32) [common]
262 12:17:05.705124 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:17:05.705211 start: 1.6.7 compress-ramdisk (timeout 00:09:32) [common]
264 12:17:05.705294 Building ramdisk /var/lib/lava/dispatcher/tmp/10605447/extract-overlay-ramdisk-vbmq8ww8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605447/extract-overlay-ramdisk-vbmq8ww8/ramdisk
265 12:17:06.019485 >> 128929 blocks
266 12:17:08.103954 rename /var/lib/lava/dispatcher/tmp/10605447/extract-overlay-ramdisk-vbmq8ww8/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/ramdisk/ramdisk.cpio.gz
267 12:17:08.104389 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:17:08.104506 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 12:17:08.104651 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 12:17:08.104760 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/kernel/Image'
271 12:17:20.089727 Returned 0 in 11 seconds
272 12:17:20.190414 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/kernel/image.itb
273 12:17:20.513265 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:17:20.513636 output: Created: Tue Jun 6 13:17:20 2023
275 12:17:20.513712 output: Image 0 (kernel-1)
276 12:17:20.513778 output: Description:
277 12:17:20.513842 output: Created: Tue Jun 6 13:17:20 2023
278 12:17:20.513904 output: Type: Kernel Image
279 12:17:20.513965 output: Compression: lzma compressed
280 12:17:20.514026 output: Data Size: 10094623 Bytes = 9858.03 KiB = 9.63 MiB
281 12:17:20.514083 output: Architecture: AArch64
282 12:17:20.514141 output: OS: Linux
283 12:17:20.514199 output: Load Address: 0x00000000
284 12:17:20.514258 output: Entry Point: 0x00000000
285 12:17:20.514317 output: Hash algo: crc32
286 12:17:20.514371 output: Hash value: fd97082e
287 12:17:20.514425 output: Image 1 (fdt-1)
288 12:17:20.514478 output: Description: mt8192-asurada-spherion-r0
289 12:17:20.514532 output: Created: Tue Jun 6 13:17:20 2023
290 12:17:20.514586 output: Type: Flat Device Tree
291 12:17:20.514640 output: Compression: uncompressed
292 12:17:20.514693 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 12:17:20.514747 output: Architecture: AArch64
294 12:17:20.514800 output: Hash algo: crc32
295 12:17:20.514853 output: Hash value: 1df858fa
296 12:17:20.514906 output: Image 2 (ramdisk-1)
297 12:17:20.514959 output: Description: unavailable
298 12:17:20.515013 output: Created: Tue Jun 6 13:17:20 2023
299 12:17:20.515066 output: Type: RAMDisk Image
300 12:17:20.515120 output: Compression: Unknown Compression
301 12:17:20.515174 output: Data Size: 18607087 Bytes = 18170.98 KiB = 17.75 MiB
302 12:17:20.515228 output: Architecture: AArch64
303 12:17:20.515281 output: OS: Linux
304 12:17:20.515334 output: Load Address: unavailable
305 12:17:20.515387 output: Entry Point: unavailable
306 12:17:20.515440 output: Hash algo: crc32
307 12:17:20.515493 output: Hash value: d756b9cd
308 12:17:20.515546 output: Default Configuration: 'conf-1'
309 12:17:20.515599 output: Configuration 0 (conf-1)
310 12:17:20.515652 output: Description: mt8192-asurada-spherion-r0
311 12:17:20.515705 output: Kernel: kernel-1
312 12:17:20.515781 output: Init Ramdisk: ramdisk-1
313 12:17:20.515836 output: FDT: fdt-1
314 12:17:20.515890 output: Loadables: kernel-1
315 12:17:20.515944 output:
316 12:17:20.516141 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 12:17:20.516234 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 12:17:20.516333 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 12:17:20.516428 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 12:17:20.516508 No LXC device requested
321 12:17:20.516630 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:17:20.516713 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 12:17:20.516790 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:17:20.516859 Checking files for TFTP limit of 4294967296 bytes.
325 12:17:20.517342 end: 1 tftp-deploy (duration 00:00:43) [common]
326 12:17:20.517448 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:17:20.517540 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:17:20.517662 substitutions:
329 12:17:20.517731 - {DTB}: 10605447/tftp-deploy-nuzl_41d/dtb/mt8192-asurada-spherion-r0.dtb
330 12:17:20.517797 - {INITRD}: 10605447/tftp-deploy-nuzl_41d/ramdisk/ramdisk.cpio.gz
331 12:17:20.517857 - {KERNEL}: 10605447/tftp-deploy-nuzl_41d/kernel/Image
332 12:17:20.517916 - {LAVA_MAC}: None
333 12:17:20.517974 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10605447/extract-nfsrootfs-apxzj0_7
334 12:17:20.518031 - {NFS_SERVER_IP}: 192.168.201.1
335 12:17:20.518088 - {PRESEED_CONFIG}: None
336 12:17:20.518144 - {PRESEED_LOCAL}: None
337 12:17:20.518198 - {RAMDISK}: 10605447/tftp-deploy-nuzl_41d/ramdisk/ramdisk.cpio.gz
338 12:17:20.518254 - {ROOT_PART}: None
339 12:17:20.518309 - {ROOT}: None
340 12:17:20.518363 - {SERVER_IP}: 192.168.201.1
341 12:17:20.518418 - {TEE}: None
342 12:17:20.518471 Parsed boot commands:
343 12:17:20.518525 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:17:20.518697 Parsed boot commands: tftpboot 192.168.201.1 10605447/tftp-deploy-nuzl_41d/kernel/image.itb 10605447/tftp-deploy-nuzl_41d/kernel/cmdline
345 12:17:20.518786 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:17:20.518870 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:17:20.518977 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:17:20.519066 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:17:20.519140 Not connected, no need to disconnect.
350 12:17:20.519216 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:17:20.519297 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:17:20.519366 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
353 12:17:20.522832 Setting prompt string to ['lava-test: # ']
354 12:17:20.523186 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:17:20.523298 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:17:20.523399 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:17:20.523491 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:17:20.523724 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 12:17:25.672498 >> Command sent successfully.
360 12:17:25.682424 Returned 0 in 5 seconds
361 12:17:25.783636 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:17:25.785152 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:17:25.785676 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:17:25.786146 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:17:25.786506 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:17:25.786879 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:17:25.788108 [Enter `^Ec?' for help]
369 12:17:25.948128
370 12:17:25.948749
371 12:17:25.949101 F0: 102B 0000
372 12:17:25.949426
373 12:17:25.949889 F3: 1001 0000 [0200]
374 12:17:25.950269
375 12:17:25.951740 F3: 1001 0000
376 12:17:25.952191
377 12:17:25.952728 F7: 102D 0000
378 12:17:25.953087
379 12:17:25.954886 F1: 0000 0000
380 12:17:25.955320
381 12:17:25.955685 V0: 0000 0000 [0001]
382 12:17:25.956006
383 12:17:25.958002 00: 0007 8000
384 12:17:25.958453
385 12:17:25.958803 01: 0000 0000
386 12:17:25.959133
387 12:17:25.959449 BP: 0C00 0209 [0000]
388 12:17:25.961811
389 12:17:25.962251 G0: 1182 0000
390 12:17:25.962600
391 12:17:25.962926 EC: 0000 0021 [4000]
392 12:17:25.963238
393 12:17:25.965098 S7: 0000 0000 [0000]
394 12:17:25.965552
395 12:17:25.968284 CC: 0000 0000 [0001]
396 12:17:25.968764
397 12:17:25.969119 T0: 0000 0040 [010F]
398 12:17:25.969463
399 12:17:25.969796 Jump to BL
400 12:17:25.970215
401 12:17:25.995543
402 12:17:25.996269
403 12:17:25.996858
404 12:17:26.002135 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:17:26.005961 ARM64: Exception handlers installed.
406 12:17:26.009605 ARM64: Testing exception
407 12:17:26.012928 ARM64: Done test exception
408 12:17:26.020342 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:17:26.030550 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:17:26.037468 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:17:26.047037 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:17:26.053989 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:17:26.060317 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:17:26.071324 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:17:26.077701 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:17:26.097691 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:17:26.100820 WDT: Last reset was cold boot
418 12:17:26.103939 SPI1(PAD0) initialized at 2873684 Hz
419 12:17:26.107604 SPI5(PAD0) initialized at 992727 Hz
420 12:17:26.110566 VBOOT: Loading verstage.
421 12:17:26.117611 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:17:26.120607 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:17:26.123895 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:17:26.127453 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:17:26.134964 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:17:26.141706 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:17:26.152859 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:17:26.153572
429 12:17:26.154203
430 12:17:26.162460 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:17:26.166096 ARM64: Exception handlers installed.
432 12:17:26.169249 ARM64: Testing exception
433 12:17:26.169692 ARM64: Done test exception
434 12:17:26.175611 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:17:26.179296 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:17:26.193859 Probing TPM: . done!
437 12:17:26.194306 TPM ready after 0 ms
438 12:17:26.200599 Connected to device vid:did:rid of 1ae0:0028:00
439 12:17:26.207381 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 12:17:26.210563 Initialized TPM device CR50 revision 0
441 12:17:26.260625 tlcl_send_startup: Startup return code is 0
442 12:17:26.261148 TPM: setup succeeded
443 12:17:26.272975 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:17:26.281983 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:17:26.288733 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:17:26.302065 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:17:26.305168 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:17:26.308615 in-header: 03 07 00 00 08 00 00 00
449 12:17:26.311793 in-data: aa e4 47 04 13 02 00 00
450 12:17:26.314978 Chrome EC: UHEPI supported
451 12:17:26.321641 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:17:26.324926 in-header: 03 ad 00 00 08 00 00 00
453 12:17:26.328092 in-data: 00 20 20 08 00 00 00 00
454 12:17:26.328563 Phase 1
455 12:17:26.331542 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:17:26.338256 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:17:26.345443 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:17:26.348234 Recovery requested (1009000e)
459 12:17:26.351888 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:17:26.360680 tlcl_extend: response is 0
461 12:17:26.368782 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:17:26.374094 tlcl_extend: response is 0
463 12:17:26.380486 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:17:26.401029 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 12:17:26.408127 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:17:26.408612
467 12:17:26.409056
468 12:17:26.419024 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:17:26.422163 ARM64: Exception handlers installed.
470 12:17:26.422615 ARM64: Testing exception
471 12:17:26.425328 ARM64: Done test exception
472 12:17:26.447141 pmic_efuse_setting: Set efuses in 11 msecs
473 12:17:26.450371 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:17:26.457064 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:17:26.460758 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:17:26.463809 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:17:26.470943 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:17:26.473995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:17:26.480964 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:17:26.484120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:17:26.490447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:17:26.494283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:17:26.497401 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:17:26.503827 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:17:26.507560 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:17:26.513718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:17:26.520622 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:17:26.524076 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:17:26.530385 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:17:26.537469 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:17:26.540421 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:17:26.546870 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:17:26.553681 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:17:26.556650 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:17:26.564133 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:17:26.571470 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:17:26.575298 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:17:26.581921 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:17:26.585050 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:17:26.592545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:17:26.595704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:17:26.602760 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:17:26.605918 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:17:26.609834 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:17:26.617021 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:17:26.620196 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:17:26.626827 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:17:26.630486 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:17:26.634373 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:17:26.641296 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:17:26.645209 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:17:26.648371 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:17:26.655226 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:17:26.658237 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:17:26.661368 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:17:26.668302 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:17:26.671337 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:17:26.674488 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:17:26.681461 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:17:26.684623 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:17:26.688313 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:17:26.694452 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:17:26.698280 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:17:26.701399 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:17:26.707737 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:17:26.717691 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:17:26.720952 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:17:26.731224 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:17:26.738019 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:17:26.744429 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:17:26.748032 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:17:26.751148 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:17:26.759313 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
534 12:17:26.766356 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:17:26.769366 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 12:17:26.772556 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:17:26.783498 [RTC]rtc_get_frequency_meter,154: input=15, output=834
538 12:17:26.793022 [RTC]rtc_get_frequency_meter,154: input=7, output=708
539 12:17:26.803169 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 12:17:26.812342 [RTC]rtc_get_frequency_meter,154: input=13, output=803
541 12:17:26.821406 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 12:17:26.831193 [RTC]rtc_get_frequency_meter,154: input=12, output=787
543 12:17:26.841064 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 12:17:26.844336 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 12:17:26.851187 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 12:17:26.854720 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:17:26.857889 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:17:26.865038 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:17:26.867945 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:17:26.871484 ADC[4]: Raw value=903031 ID=7
551 12:17:26.872039 ADC[3]: Raw value=213652 ID=1
552 12:17:26.874486 RAM Code: 0x71
553 12:17:26.878022 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:17:26.884811 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:17:26.891096 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:17:26.897984 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:17:26.901082 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:17:26.904750 in-header: 03 07 00 00 08 00 00 00
559 12:17:26.907745 in-data: aa e4 47 04 13 02 00 00
560 12:17:26.910819 Chrome EC: UHEPI supported
561 12:17:26.917823 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:17:26.920883 in-header: 03 dd 00 00 08 00 00 00
563 12:17:26.924586 in-data: 90 20 60 08 00 00 00 00
564 12:17:26.927674 MRC: failed to locate region type 0.
565 12:17:26.934112 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:17:26.937555 DRAM-K: Running full calibration
567 12:17:26.944154 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:17:26.944804 header.status = 0x0
569 12:17:26.947716 header.version = 0x6 (expected: 0x6)
570 12:17:26.951035 header.size = 0xd00 (expected: 0xd00)
571 12:17:26.954090 header.flags = 0x0
572 12:17:26.960944 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:17:26.977132 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 12:17:26.983751 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:17:26.987425 dram_init: ddr_geometry: 2
576 12:17:26.990674 [EMI] MDL number = 2
577 12:17:26.991295 [EMI] Get MDL freq = 0
578 12:17:26.993959 dram_init: ddr_type: 0
579 12:17:26.994553 is_discrete_lpddr4: 1
580 12:17:26.997121 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:17:26.997556
582 12:17:26.997898
583 12:17:27.000741 [Bian_co] ETT version 0.0.0.1
584 12:17:27.006615 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:17:27.006700
586 12:17:27.010176 dramc_set_vcore_voltage set vcore to 650000
587 12:17:27.013328 Read voltage for 800, 4
588 12:17:27.013411 Vio18 = 0
589 12:17:27.013477 Vcore = 650000
590 12:17:27.017014 Vdram = 0
591 12:17:27.017098 Vddq = 0
592 12:17:27.017164 Vmddr = 0
593 12:17:27.020138 dram_init: config_dvfs: 1
594 12:17:27.023413 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:17:27.030420 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:17:27.033522 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 12:17:27.036663 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 12:17:27.040187 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 12:17:27.046806 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 12:17:27.046891 MEM_TYPE=3, freq_sel=18
601 12:17:27.049986 sv_algorithm_assistance_LP4_1600
602 12:17:27.053087 ============ PULL DRAM RESETB DOWN ============
603 12:17:27.059944 ========== PULL DRAM RESETB DOWN end =========
604 12:17:27.063030 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:17:27.066295 ===================================
606 12:17:27.069979 LPDDR4 DRAM CONFIGURATION
607 12:17:27.073202 ===================================
608 12:17:27.073278 EX_ROW_EN[0] = 0x0
609 12:17:27.076382 EX_ROW_EN[1] = 0x0
610 12:17:27.076468 LP4Y_EN = 0x0
611 12:17:27.079565 WORK_FSP = 0x0
612 12:17:27.079649 WL = 0x2
613 12:17:27.083357 RL = 0x2
614 12:17:27.083440 BL = 0x2
615 12:17:27.086413 RPST = 0x0
616 12:17:27.089987 RD_PRE = 0x0
617 12:17:27.090071 WR_PRE = 0x1
618 12:17:27.093134 WR_PST = 0x0
619 12:17:27.093218 DBI_WR = 0x0
620 12:17:27.096366 DBI_RD = 0x0
621 12:17:27.096449 OTF = 0x1
622 12:17:27.099942 ===================================
623 12:17:27.103045 ===================================
624 12:17:27.106211 ANA top config
625 12:17:27.109407 ===================================
626 12:17:27.109491 DLL_ASYNC_EN = 0
627 12:17:27.113117 ALL_SLAVE_EN = 1
628 12:17:27.116220 NEW_RANK_MODE = 1
629 12:17:27.119513 DLL_IDLE_MODE = 1
630 12:17:27.119636 LP45_APHY_COMB_EN = 1
631 12:17:27.122720 TX_ODT_DIS = 1
632 12:17:27.125924 NEW_8X_MODE = 1
633 12:17:27.129618 ===================================
634 12:17:27.133059 ===================================
635 12:17:27.136089 data_rate = 1600
636 12:17:27.139643 CKR = 1
637 12:17:27.142746 DQ_P2S_RATIO = 8
638 12:17:27.145673 ===================================
639 12:17:27.145759 CA_P2S_RATIO = 8
640 12:17:27.149322 DQ_CA_OPEN = 0
641 12:17:27.152299 DQ_SEMI_OPEN = 0
642 12:17:27.155925 CA_SEMI_OPEN = 0
643 12:17:27.158928 CA_FULL_RATE = 0
644 12:17:27.162679 DQ_CKDIV4_EN = 1
645 12:17:27.162766 CA_CKDIV4_EN = 1
646 12:17:27.165794 CA_PREDIV_EN = 0
647 12:17:27.168884 PH8_DLY = 0
648 12:17:27.172090 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:17:27.175816 DQ_AAMCK_DIV = 4
650 12:17:27.178976 CA_AAMCK_DIV = 4
651 12:17:27.179061 CA_ADMCK_DIV = 4
652 12:17:27.182135 DQ_TRACK_CA_EN = 0
653 12:17:27.185341 CA_PICK = 800
654 12:17:27.189091 CA_MCKIO = 800
655 12:17:27.192171 MCKIO_SEMI = 0
656 12:17:27.195746 PLL_FREQ = 3068
657 12:17:27.198927 DQ_UI_PI_RATIO = 32
658 12:17:27.199013 CA_UI_PI_RATIO = 0
659 12:17:27.201960 ===================================
660 12:17:27.205649 ===================================
661 12:17:27.208878 memory_type:LPDDR4
662 12:17:27.212087 GP_NUM : 10
663 12:17:27.212171 SRAM_EN : 1
664 12:17:27.215182 MD32_EN : 0
665 12:17:27.218878 ===================================
666 12:17:27.222060 [ANA_INIT] >>>>>>>>>>>>>>
667 12:17:27.225243 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:17:27.228587 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:17:27.232221 ===================================
670 12:17:27.232306 data_rate = 1600,PCW = 0X7600
671 12:17:27.235421 ===================================
672 12:17:27.238495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:17:27.245501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:17:27.252184 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:17:27.255945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:17:27.258787 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:17:27.262397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:17:27.265632 [ANA_INIT] flow start
679 12:17:27.265740 [ANA_INIT] PLL >>>>>>>>
680 12:17:27.268787 [ANA_INIT] PLL <<<<<<<<
681 12:17:27.272426 [ANA_INIT] MIDPI >>>>>>>>
682 12:17:27.272555 [ANA_INIT] MIDPI <<<<<<<<
683 12:17:27.275822 [ANA_INIT] DLL >>>>>>>>
684 12:17:27.278796 [ANA_INIT] flow end
685 12:17:27.282042 ============ LP4 DIFF to SE enter ============
686 12:17:27.285800 ============ LP4 DIFF to SE exit ============
687 12:17:27.289149 [ANA_INIT] <<<<<<<<<<<<<
688 12:17:27.292545 [Flow] Enable top DCM control >>>>>
689 12:17:27.295790 [Flow] Enable top DCM control <<<<<
690 12:17:27.298854 Enable DLL master slave shuffle
691 12:17:27.305907 ==============================================================
692 12:17:27.306343 Gating Mode config
693 12:17:27.312092 ==============================================================
694 12:17:27.312564 Config description:
695 12:17:27.321932 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:17:27.328830 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:17:27.335787 SELPH_MODE 0: By rank 1: By Phase
698 12:17:27.338854 ==============================================================
699 12:17:27.342046 GAT_TRACK_EN = 1
700 12:17:27.346140 RX_GATING_MODE = 2
701 12:17:27.348995 RX_GATING_TRACK_MODE = 2
702 12:17:27.352183 SELPH_MODE = 1
703 12:17:27.355960 PICG_EARLY_EN = 1
704 12:17:27.359225 VALID_LAT_VALUE = 1
705 12:17:27.362254 ==============================================================
706 12:17:27.365779 Enter into Gating configuration >>>>
707 12:17:27.368993 Exit from Gating configuration <<<<
708 12:17:27.372166 Enter into DVFS_PRE_config >>>>>
709 12:17:27.385472 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:17:27.388700 Exit from DVFS_PRE_config <<<<<
711 12:17:27.392393 Enter into PICG configuration >>>>
712 12:17:27.392881 Exit from PICG configuration <<<<
713 12:17:27.395600 [RX_INPUT] configuration >>>>>
714 12:17:27.398920 [RX_INPUT] configuration <<<<<
715 12:17:27.405646 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:17:27.409484 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:17:27.416364 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:17:27.423864 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:17:27.427565 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:17:27.434639 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:17:27.438327 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:17:27.441450 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:17:27.448297 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:17:27.451530 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:17:27.455080 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:17:27.458870 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:17:27.462432 ===================================
728 12:17:27.465806 LPDDR4 DRAM CONFIGURATION
729 12:17:27.469962 ===================================
730 12:17:27.470409 EX_ROW_EN[0] = 0x0
731 12:17:27.473374 EX_ROW_EN[1] = 0x0
732 12:17:27.473925 LP4Y_EN = 0x0
733 12:17:27.477085 WORK_FSP = 0x0
734 12:17:27.477525 WL = 0x2
735 12:17:27.480878 RL = 0x2
736 12:17:27.481317 BL = 0x2
737 12:17:27.484781 RPST = 0x0
738 12:17:27.485222 RD_PRE = 0x0
739 12:17:27.485574 WR_PRE = 0x1
740 12:17:27.487857 WR_PST = 0x0
741 12:17:27.488310 DBI_WR = 0x0
742 12:17:27.491817 DBI_RD = 0x0
743 12:17:27.492259 OTF = 0x1
744 12:17:27.495738 ===================================
745 12:17:27.499715 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:17:27.503307 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:17:27.510080 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:17:27.513774 ===================================
749 12:17:27.514222 LPDDR4 DRAM CONFIGURATION
750 12:17:27.517544 ===================================
751 12:17:27.521352 EX_ROW_EN[0] = 0x10
752 12:17:27.521794 EX_ROW_EN[1] = 0x0
753 12:17:27.524942 LP4Y_EN = 0x0
754 12:17:27.525530 WORK_FSP = 0x0
755 12:17:27.528839 WL = 0x2
756 12:17:27.529321 RL = 0x2
757 12:17:27.532448 BL = 0x2
758 12:17:27.532999 RPST = 0x0
759 12:17:27.533338 RD_PRE = 0x0
760 12:17:27.536424 WR_PRE = 0x1
761 12:17:27.536952 WR_PST = 0x0
762 12:17:27.540059 DBI_WR = 0x0
763 12:17:27.540762 DBI_RD = 0x0
764 12:17:27.542726 OTF = 0x1
765 12:17:27.546329 ===================================
766 12:17:27.553848 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:17:27.557611 nWR fixed to 40
768 12:17:27.558096 [ModeRegInit_LP4] CH0 RK0
769 12:17:27.560739 [ModeRegInit_LP4] CH0 RK1
770 12:17:27.561237 [ModeRegInit_LP4] CH1 RK0
771 12:17:27.564453 [ModeRegInit_LP4] CH1 RK1
772 12:17:27.568093 match AC timing 13
773 12:17:27.571765 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:17:27.574799 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:17:27.577868 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:17:27.585418 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:17:27.588395 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:17:27.592196 [EMI DOE] emi_dcm 0
779 12:17:27.595418 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:17:27.595853 ==
781 12:17:27.598630 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:17:27.601720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:17:27.602161 ==
784 12:17:27.608637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:17:27.615061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:17:27.623125 [CA 0] Center 37 (6~68) winsize 63
787 12:17:27.626748 [CA 1] Center 37 (7~68) winsize 62
788 12:17:27.629872 [CA 2] Center 34 (4~65) winsize 62
789 12:17:27.633619 [CA 3] Center 34 (4~65) winsize 62
790 12:17:27.636875 [CA 4] Center 33 (3~64) winsize 62
791 12:17:27.640049 [CA 5] Center 33 (3~64) winsize 62
792 12:17:27.640497
793 12:17:27.643085 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 12:17:27.643533
795 12:17:27.646783 [CATrainingPosCal] consider 1 rank data
796 12:17:27.650378 u2DelayCellTimex100 = 270/100 ps
797 12:17:27.653205 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 12:17:27.656827 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 12:17:27.663182 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 12:17:27.666824 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 12:17:27.670038 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 12:17:27.673144 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 12:17:27.673782
804 12:17:27.676592 CA PerBit enable=1, Macro0, CA PI delay=33
805 12:17:27.677037
806 12:17:27.679656 [CBTSetCACLKResult] CA Dly = 33
807 12:17:27.680095 CS Dly: 6 (0~37)
808 12:17:27.680440 ==
809 12:17:27.683259 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:17:27.689701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:17:27.690144 ==
812 12:17:27.692852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:17:27.699633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:17:27.709666 [CA 0] Center 37 (6~68) winsize 63
815 12:17:27.712947 [CA 1] Center 37 (7~68) winsize 62
816 12:17:27.716107 [CA 2] Center 34 (4~65) winsize 62
817 12:17:27.719512 [CA 3] Center 34 (4~65) winsize 62
818 12:17:27.722978 [CA 4] Center 33 (3~64) winsize 62
819 12:17:27.726075 [CA 5] Center 33 (3~64) winsize 62
820 12:17:27.726532
821 12:17:27.729134 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 12:17:27.729568
823 12:17:27.732924 [CATrainingPosCal] consider 2 rank data
824 12:17:27.736110 u2DelayCellTimex100 = 270/100 ps
825 12:17:27.739126 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
826 12:17:27.742371 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 12:17:27.746190 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 12:17:27.749938 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 12:17:27.753615 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 12:17:27.760345 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 12:17:27.760921
832 12:17:27.763966 CA PerBit enable=1, Macro0, CA PI delay=33
833 12:17:27.764781
834 12:17:27.767436 [CBTSetCACLKResult] CA Dly = 33
835 12:17:27.767976 CS Dly: 6 (0~38)
836 12:17:27.768419
837 12:17:27.770673 ----->DramcWriteLeveling(PI) begin...
838 12:17:27.771134 ==
839 12:17:27.773952 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:17:27.777658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:17:27.778102 ==
842 12:17:27.781111 Write leveling (Byte 0): 32 => 32
843 12:17:27.784100 Write leveling (Byte 1): 30 => 30
844 12:17:27.787708 DramcWriteLeveling(PI) end<-----
845 12:17:27.788279
846 12:17:27.788752 ==
847 12:17:27.790852 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:17:27.793960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:17:27.797725 ==
850 12:17:27.798179 [Gating] SW mode calibration
851 12:17:27.807154 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:17:27.810955 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:17:27.813829 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:17:27.820706 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 12:17:27.823700 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 12:17:27.826769 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 12:17:27.833656 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:17:27.836774 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:17:27.839998 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:17:27.847042 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:17:27.850227 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:17:27.853266 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:17:27.860075 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:17:27.863811 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:17:27.866708 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:17:27.873499 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:17:27.876723 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:17:27.880397 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:17:27.883512 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:17:27.890318 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 12:17:27.893414 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 12:17:27.897083 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:17:27.903515 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:17:27.906635 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:17:27.909889 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:17:27.916790 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:17:27.919812 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:17:27.923669 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:17:27.929994 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
880 12:17:27.932980 0 9 12 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
881 12:17:27.936731 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:17:27.943038 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:17:27.946171 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:17:27.950038 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:17:27.956403 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:17:27.959469 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
887 12:17:27.963254 0 10 8 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (1 1)
888 12:17:27.969594 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
889 12:17:27.972739 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:17:27.976363 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:17:27.982695 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:17:27.986475 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:17:27.989610 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:17:27.996213 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 12:17:27.999956 0 11 8 | B1->B0 | 2525 3d3d | 0 0 | (0 0) (0 0)
896 12:17:28.003345 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
897 12:17:28.009468 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:17:28.013151 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:17:28.016450 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:17:28.022655 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:17:28.026247 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:17:28.029468 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 12:17:28.036245 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 12:17:28.039464 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:17:28.042428 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:17:28.049595 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:17:28.052747 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:17:28.055914 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:17:28.062883 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:17:28.066526 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:17:28.070463 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:17:28.074224 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:17:28.077959 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:17:28.085198 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:17:28.089107 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:17:28.092580 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:17:28.096127 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:17:28.099670 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 12:17:28.107013 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 12:17:28.110719 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 12:17:28.111158 Total UI for P1: 0, mck2ui 16
922 12:17:28.114523 best dqsien dly found for B0: ( 0, 14, 8)
923 12:17:28.118014 Total UI for P1: 0, mck2ui 16
924 12:17:28.122049 best dqsien dly found for B1: ( 0, 14, 10)
925 12:17:28.125092 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 12:17:28.128892 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 12:17:28.129557
928 12:17:28.132052 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 12:17:28.135959 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 12:17:28.139491 [Gating] SW calibration Done
931 12:17:28.139959 ==
932 12:17:28.143033 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:17:28.146332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:17:28.146799 ==
935 12:17:28.149911 RX Vref Scan: 0
936 12:17:28.150339
937 12:17:28.153215 RX Vref 0 -> 0, step: 1
938 12:17:28.153647
939 12:17:28.153989 RX Delay -130 -> 252, step: 16
940 12:17:28.160123 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 12:17:28.163048 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 12:17:28.166243 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 12:17:28.169987 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 12:17:28.173075 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 12:17:28.180087 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 12:17:28.183821 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
947 12:17:28.187010 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 12:17:28.191210 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 12:17:28.194669 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 12:17:28.198275 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 12:17:28.202005 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 12:17:28.204903 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
953 12:17:28.211788 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 12:17:28.214986 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 12:17:28.219331 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 12:17:28.220059 ==
957 12:17:28.222070 Dram Type= 6, Freq= 0, CH_0, rank 0
958 12:17:28.225313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 12:17:28.225745 ==
960 12:17:28.228614 DQS Delay:
961 12:17:28.229045 DQS0 = 0, DQS1 = 0
962 12:17:28.231518 DQM Delay:
963 12:17:28.231949 DQM0 = 85, DQM1 = 71
964 12:17:28.234931 DQ Delay:
965 12:17:28.235361 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 12:17:28.238009 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
967 12:17:28.241123 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 12:17:28.244880 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
969 12:17:28.247917
970 12:17:28.248343
971 12:17:28.248787 ==
972 12:17:28.251299 Dram Type= 6, Freq= 0, CH_0, rank 0
973 12:17:28.254907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 12:17:28.255338 ==
975 12:17:28.255682
976 12:17:28.256002
977 12:17:28.258037 TX Vref Scan disable
978 12:17:28.258467 == TX Byte 0 ==
979 12:17:28.264462 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 12:17:28.268207 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 12:17:28.268682 == TX Byte 1 ==
982 12:17:28.274540 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
983 12:17:28.277557 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
984 12:17:28.277998 ==
985 12:17:28.280760 Dram Type= 6, Freq= 0, CH_0, rank 0
986 12:17:28.284604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 12:17:28.285043 ==
988 12:17:28.298415 TX Vref=22, minBit 8, minWin=27, winSum=443
989 12:17:28.301938 TX Vref=24, minBit 13, minWin=26, winSum=442
990 12:17:28.305013 TX Vref=26, minBit 8, minWin=27, winSum=447
991 12:17:28.308477 TX Vref=28, minBit 10, minWin=27, winSum=449
992 12:17:28.311561 TX Vref=30, minBit 8, minWin=27, winSum=450
993 12:17:28.318378 TX Vref=32, minBit 8, minWin=27, winSum=446
994 12:17:28.321816 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 30
995 12:17:28.322269
996 12:17:28.325083 Final TX Range 1 Vref 30
997 12:17:28.325520
998 12:17:28.325860 ==
999 12:17:28.328191 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 12:17:28.331705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 12:17:28.334437 ==
1002 12:17:28.334872
1003 12:17:28.335216
1004 12:17:28.335534 TX Vref Scan disable
1005 12:17:28.338272 == TX Byte 0 ==
1006 12:17:28.342088 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1007 12:17:28.348271 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1008 12:17:28.348751 == TX Byte 1 ==
1009 12:17:28.351892 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1010 12:17:28.357994 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1011 12:17:28.358433
1012 12:17:28.358779 [DATLAT]
1013 12:17:28.359100 Freq=800, CH0 RK0
1014 12:17:28.359411
1015 12:17:28.361611 DATLAT Default: 0xa
1016 12:17:28.362049 0, 0xFFFF, sum = 0
1017 12:17:28.364777 1, 0xFFFF, sum = 0
1018 12:17:28.365219 2, 0xFFFF, sum = 0
1019 12:17:28.368549 3, 0xFFFF, sum = 0
1020 12:17:28.371659 4, 0xFFFF, sum = 0
1021 12:17:28.372105 5, 0xFFFF, sum = 0
1022 12:17:28.374812 6, 0xFFFF, sum = 0
1023 12:17:28.375325 7, 0xFFFF, sum = 0
1024 12:17:28.378044 8, 0xFFFF, sum = 0
1025 12:17:28.378509 9, 0x0, sum = 1
1026 12:17:28.381736 10, 0x0, sum = 2
1027 12:17:28.382170 11, 0x0, sum = 3
1028 12:17:28.382513 12, 0x0, sum = 4
1029 12:17:28.384916 best_step = 10
1030 12:17:28.385344
1031 12:17:28.385682 ==
1032 12:17:28.388022 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 12:17:28.391245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 12:17:28.391672 ==
1035 12:17:28.394948 RX Vref Scan: 1
1036 12:17:28.395374
1037 12:17:28.398205 Set Vref Range= 32 -> 127
1038 12:17:28.398631
1039 12:17:28.398965 RX Vref 32 -> 127, step: 1
1040 12:17:28.399282
1041 12:17:28.401408 RX Delay -111 -> 252, step: 8
1042 12:17:28.401835
1043 12:17:28.404621 Set Vref, RX VrefLevel [Byte0]: 32
1044 12:17:28.408152 [Byte1]: 32
1045 12:17:28.411306
1046 12:17:28.411734 Set Vref, RX VrefLevel [Byte0]: 33
1047 12:17:28.414430 [Byte1]: 33
1048 12:17:28.418648
1049 12:17:28.419074 Set Vref, RX VrefLevel [Byte0]: 34
1050 12:17:28.422187 [Byte1]: 34
1051 12:17:28.426793
1052 12:17:28.427216 Set Vref, RX VrefLevel [Byte0]: 35
1053 12:17:28.429950 [Byte1]: 35
1054 12:17:28.434278
1055 12:17:28.434712 Set Vref, RX VrefLevel [Byte0]: 36
1056 12:17:28.437381 [Byte1]: 36
1057 12:17:28.442300
1058 12:17:28.442731 Set Vref, RX VrefLevel [Byte0]: 37
1059 12:17:28.445447 [Byte1]: 37
1060 12:17:28.449327
1061 12:17:28.449754 Set Vref, RX VrefLevel [Byte0]: 38
1062 12:17:28.452478 [Byte1]: 38
1063 12:17:28.456857
1064 12:17:28.457284 Set Vref, RX VrefLevel [Byte0]: 39
1065 12:17:28.460344 [Byte1]: 39
1066 12:17:28.464778
1067 12:17:28.465204 Set Vref, RX VrefLevel [Byte0]: 40
1068 12:17:28.467963 [Byte1]: 40
1069 12:17:28.472379
1070 12:17:28.472855 Set Vref, RX VrefLevel [Byte0]: 41
1071 12:17:28.475792 [Byte1]: 41
1072 12:17:28.480116
1073 12:17:28.480709 Set Vref, RX VrefLevel [Byte0]: 42
1074 12:17:28.483150 [Byte1]: 42
1075 12:17:28.487710
1076 12:17:28.488238 Set Vref, RX VrefLevel [Byte0]: 43
1077 12:17:28.491371 [Byte1]: 43
1078 12:17:28.495242
1079 12:17:28.495683 Set Vref, RX VrefLevel [Byte0]: 44
1080 12:17:28.499141 [Byte1]: 44
1081 12:17:28.502837
1082 12:17:28.503293 Set Vref, RX VrefLevel [Byte0]: 45
1083 12:17:28.506601 [Byte1]: 45
1084 12:17:28.511007
1085 12:17:28.511438 Set Vref, RX VrefLevel [Byte0]: 46
1086 12:17:28.514107 [Byte1]: 46
1087 12:17:28.518580
1088 12:17:28.519106 Set Vref, RX VrefLevel [Byte0]: 47
1089 12:17:28.521551 [Byte1]: 47
1090 12:17:28.525757
1091 12:17:28.526213 Set Vref, RX VrefLevel [Byte0]: 48
1092 12:17:28.529413 [Byte1]: 48
1093 12:17:28.533720
1094 12:17:28.534276 Set Vref, RX VrefLevel [Byte0]: 49
1095 12:17:28.537468 [Byte1]: 49
1096 12:17:28.541284
1097 12:17:28.541715 Set Vref, RX VrefLevel [Byte0]: 50
1098 12:17:28.545065 [Byte1]: 50
1099 12:17:28.548941
1100 12:17:28.549363 Set Vref, RX VrefLevel [Byte0]: 51
1101 12:17:28.552784 [Byte1]: 51
1102 12:17:28.556624
1103 12:17:28.557047 Set Vref, RX VrefLevel [Byte0]: 52
1104 12:17:28.560512 [Byte1]: 52
1105 12:17:28.564560
1106 12:17:28.565179 Set Vref, RX VrefLevel [Byte0]: 53
1107 12:17:28.567621 [Byte1]: 53
1108 12:17:28.571889
1109 12:17:28.572310 Set Vref, RX VrefLevel [Byte0]: 54
1110 12:17:28.575675 [Byte1]: 54
1111 12:17:28.579359
1112 12:17:28.579791 Set Vref, RX VrefLevel [Byte0]: 55
1113 12:17:28.582515 [Byte1]: 55
1114 12:17:28.587198
1115 12:17:28.587729 Set Vref, RX VrefLevel [Byte0]: 56
1116 12:17:28.590591 [Byte1]: 56
1117 12:17:28.595075
1118 12:17:28.595679 Set Vref, RX VrefLevel [Byte0]: 57
1119 12:17:28.598800 [Byte1]: 57
1120 12:17:28.602679
1121 12:17:28.603113 Set Vref, RX VrefLevel [Byte0]: 58
1122 12:17:28.605927 [Byte1]: 58
1123 12:17:28.610680
1124 12:17:28.611411 Set Vref, RX VrefLevel [Byte0]: 59
1125 12:17:28.613924 [Byte1]: 59
1126 12:17:28.618171
1127 12:17:28.618679 Set Vref, RX VrefLevel [Byte0]: 60
1128 12:17:28.621154 [Byte1]: 60
1129 12:17:28.625351
1130 12:17:28.625891 Set Vref, RX VrefLevel [Byte0]: 61
1131 12:17:28.628464 [Byte1]: 61
1132 12:17:28.632887
1133 12:17:28.636348 Set Vref, RX VrefLevel [Byte0]: 62
1134 12:17:28.639665 [Byte1]: 62
1135 12:17:28.640180
1136 12:17:28.643459 Set Vref, RX VrefLevel [Byte0]: 63
1137 12:17:28.647159 [Byte1]: 63
1138 12:17:28.647741
1139 12:17:28.651131 Set Vref, RX VrefLevel [Byte0]: 64
1140 12:17:28.654149 [Byte1]: 64
1141 12:17:28.654824
1142 12:17:28.657916 Set Vref, RX VrefLevel [Byte0]: 65
1143 12:17:28.661624 [Byte1]: 65
1144 12:17:28.662051
1145 12:17:28.665359 Set Vref, RX VrefLevel [Byte0]: 66
1146 12:17:28.668978 [Byte1]: 66
1147 12:17:28.669547
1148 12:17:28.672465 Set Vref, RX VrefLevel [Byte0]: 67
1149 12:17:28.675757 [Byte1]: 67
1150 12:17:28.676195
1151 12:17:28.679554 Set Vref, RX VrefLevel [Byte0]: 68
1152 12:17:28.682400 [Byte1]: 68
1153 12:17:28.686153
1154 12:17:28.689952 Set Vref, RX VrefLevel [Byte0]: 69
1155 12:17:28.690392 [Byte1]: 69
1156 12:17:28.694330
1157 12:17:28.694756 Set Vref, RX VrefLevel [Byte0]: 70
1158 12:17:28.697541 [Byte1]: 70
1159 12:17:28.701863
1160 12:17:28.702305 Set Vref, RX VrefLevel [Byte0]: 71
1161 12:17:28.705030 [Byte1]: 71
1162 12:17:28.709644
1163 12:17:28.710190 Set Vref, RX VrefLevel [Byte0]: 72
1164 12:17:28.712813 [Byte1]: 72
1165 12:17:28.718046
1166 12:17:28.718580 Set Vref, RX VrefLevel [Byte0]: 73
1167 12:17:28.720938 [Byte1]: 73
1168 12:17:28.725211
1169 12:17:28.725798 Set Vref, RX VrefLevel [Byte0]: 74
1170 12:17:28.728252 [Byte1]: 74
1171 12:17:28.732661
1172 12:17:28.733091 Set Vref, RX VrefLevel [Byte0]: 75
1173 12:17:28.736187 [Byte1]: 75
1174 12:17:28.740436
1175 12:17:28.740920 Set Vref, RX VrefLevel [Byte0]: 76
1176 12:17:28.743483 [Byte1]: 76
1177 12:17:28.747915
1178 12:17:28.748341 Set Vref, RX VrefLevel [Byte0]: 77
1179 12:17:28.751118 [Byte1]: 77
1180 12:17:28.755554
1181 12:17:28.756008 Set Vref, RX VrefLevel [Byte0]: 78
1182 12:17:28.758745 [Byte1]: 78
1183 12:17:28.763176
1184 12:17:28.763606 Set Vref, RX VrefLevel [Byte0]: 79
1185 12:17:28.766290 [Byte1]: 79
1186 12:17:28.770563
1187 12:17:28.771012 Set Vref, RX VrefLevel [Byte0]: 80
1188 12:17:28.773708 [Byte1]: 80
1189 12:17:28.778329
1190 12:17:28.778762 Set Vref, RX VrefLevel [Byte0]: 81
1191 12:17:28.781529 [Byte1]: 81
1192 12:17:28.785882
1193 12:17:28.786341 Set Vref, RX VrefLevel [Byte0]: 82
1194 12:17:28.789088 [Byte1]: 82
1195 12:17:28.793542
1196 12:17:28.794025 Set Vref, RX VrefLevel [Byte0]: 83
1197 12:17:28.797160 [Byte1]: 83
1198 12:17:28.801673
1199 12:17:28.802135 Final RX Vref Byte 0 = 63 to rank0
1200 12:17:28.805427 Final RX Vref Byte 1 = 57 to rank0
1201 12:17:28.808558 Final RX Vref Byte 0 = 63 to rank1
1202 12:17:28.812558 Final RX Vref Byte 1 = 57 to rank1==
1203 12:17:28.816261 Dram Type= 6, Freq= 0, CH_0, rank 0
1204 12:17:28.819940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1205 12:17:28.820393 ==
1206 12:17:28.820827 DQS Delay:
1207 12:17:28.823742 DQS0 = 0, DQS1 = 0
1208 12:17:28.824175 DQM Delay:
1209 12:17:28.827456 DQM0 = 87, DQM1 = 75
1210 12:17:28.827909 DQ Delay:
1211 12:17:28.831198 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1212 12:17:28.831628 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1213 12:17:28.834758 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1214 12:17:28.837958 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1215 12:17:28.838386
1216 12:17:28.842084
1217 12:17:28.849388 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f21, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1218 12:17:28.849823 CH0 RK0: MR19=606, MR18=3F21
1219 12:17:28.857007 CH0_RK0: MR19=0x606, MR18=0x3F21, DQSOSC=393, MR23=63, INC=95, DEC=63
1220 12:17:28.857439
1221 12:17:28.860589 ----->DramcWriteLeveling(PI) begin...
1222 12:17:28.861028 ==
1223 12:17:28.864419 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 12:17:28.868018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1225 12:17:28.868453 ==
1226 12:17:28.871303 Write leveling (Byte 0): 32 => 32
1227 12:17:28.915013 Write leveling (Byte 1): 31 => 31
1228 12:17:28.915541 DramcWriteLeveling(PI) end<-----
1229 12:17:28.915907
1230 12:17:28.916223 ==
1231 12:17:28.916552 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 12:17:28.916890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 12:17:28.917191 ==
1234 12:17:28.917487 [Gating] SW mode calibration
1235 12:17:28.918092 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1236 12:17:28.918422 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1237 12:17:28.918722 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1238 12:17:28.919011 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1239 12:17:28.919301 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1240 12:17:28.959665 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1241 12:17:28.960209 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:17:28.960601 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:17:28.960931 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:17:28.961557 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:17:28.961892 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:17:28.962199 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:17:28.962496 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:17:28.962788 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 12:17:28.963075 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 12:17:29.003445 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 12:17:29.003973 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 12:17:29.004325 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 12:17:29.005004 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 12:17:29.005347 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1255 12:17:29.005657 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1256 12:17:29.005961 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 12:17:29.006255 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 12:17:29.006554 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 12:17:29.007053 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 12:17:29.035418 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 12:17:29.035983 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 12:17:29.036354 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 12:17:29.037043 0 9 8 | B1->B0 | 2323 2f2f | 1 1 | (1 1) (1 1)
1264 12:17:29.037386 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1265 12:17:29.037697 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 12:17:29.038002 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 12:17:29.039387 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1268 12:17:29.042859 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1269 12:17:29.045506 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1270 12:17:29.049301 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1271 12:17:29.052370 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
1272 12:17:29.059077 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1273 12:17:29.062162 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1274 12:17:29.065850 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 12:17:29.072149 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1276 12:17:29.076020 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1277 12:17:29.079104 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1278 12:17:29.086024 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1279 12:17:29.089275 0 11 8 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
1280 12:17:29.092278 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1281 12:17:29.099022 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 12:17:29.102364 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 12:17:29.105960 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 12:17:29.112254 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1285 12:17:29.116039 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 12:17:29.119051 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1287 12:17:29.125407 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1288 12:17:29.129292 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 12:17:29.132415 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 12:17:29.139096 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 12:17:29.142188 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 12:17:29.145402 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 12:17:29.148902 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 12:17:29.155341 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 12:17:29.158345 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 12:17:29.161914 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 12:17:29.168723 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 12:17:29.171862 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 12:17:29.175120 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 12:17:29.181555 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1301 12:17:29.185058 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1302 12:17:29.188904 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1303 12:17:29.195093 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1304 12:17:29.198204 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1305 12:17:29.201748 Total UI for P1: 0, mck2ui 16
1306 12:17:29.204897 best dqsien dly found for B0: ( 0, 14, 8)
1307 12:17:29.208486 Total UI for P1: 0, mck2ui 16
1308 12:17:29.211644 best dqsien dly found for B1: ( 0, 14, 8)
1309 12:17:29.214832 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1310 12:17:29.217956 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1311 12:17:29.218034
1312 12:17:29.221700 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1313 12:17:29.224893 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1314 12:17:29.228138 [Gating] SW calibration Done
1315 12:17:29.228236 ==
1316 12:17:29.231318 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 12:17:29.234542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 12:17:29.238327 ==
1319 12:17:29.238443 RX Vref Scan: 0
1320 12:17:29.238539
1321 12:17:29.241374 RX Vref 0 -> 0, step: 1
1322 12:17:29.241450
1323 12:17:29.244452 RX Delay -130 -> 252, step: 16
1324 12:17:29.248099 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1325 12:17:29.251076 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1326 12:17:29.254734 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1327 12:17:29.257901 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1328 12:17:29.264616 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1329 12:17:29.268178 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1330 12:17:29.271261 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1331 12:17:29.274409 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1332 12:17:29.278006 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1333 12:17:29.284390 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1334 12:17:29.288159 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1335 12:17:29.291376 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1336 12:17:29.294556 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1337 12:17:29.297651 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1338 12:17:29.304422 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1339 12:17:29.308065 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1340 12:17:29.308154 ==
1341 12:17:29.311025 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 12:17:29.314240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 12:17:29.314325 ==
1344 12:17:29.317955 DQS Delay:
1345 12:17:29.318039 DQS0 = 0, DQS1 = 0
1346 12:17:29.318105 DQM Delay:
1347 12:17:29.321125 DQM0 = 86, DQM1 = 77
1348 12:17:29.321208 DQ Delay:
1349 12:17:29.324362 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1350 12:17:29.327472 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1351 12:17:29.331185 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1352 12:17:29.334221 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1353 12:17:29.334305
1354 12:17:29.334371
1355 12:17:29.337419 ==
1356 12:17:29.337502 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 12:17:29.344187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 12:17:29.344274 ==
1359 12:17:29.344342
1360 12:17:29.344404
1361 12:17:29.347248 TX Vref Scan disable
1362 12:17:29.347330 == TX Byte 0 ==
1363 12:17:29.350832 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1364 12:17:29.357535 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1365 12:17:29.357623 == TX Byte 1 ==
1366 12:17:29.360458 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1367 12:17:29.367391 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1368 12:17:29.367497 ==
1369 12:17:29.370970 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 12:17:29.373949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 12:17:29.374032 ==
1372 12:17:29.387079 TX Vref=22, minBit 4, minWin=27, winSum=445
1373 12:17:29.390207 TX Vref=24, minBit 3, minWin=27, winSum=446
1374 12:17:29.393911 TX Vref=26, minBit 5, minWin=27, winSum=449
1375 12:17:29.397042 TX Vref=28, minBit 8, minWin=27, winSum=446
1376 12:17:29.400107 TX Vref=30, minBit 8, minWin=27, winSum=447
1377 12:17:29.407016 TX Vref=32, minBit 9, minWin=27, winSum=444
1378 12:17:29.410537 [TxChooseVref] Worse bit 5, Min win 27, Win sum 449, Final Vref 26
1379 12:17:29.410620
1380 12:17:29.413554 Final TX Range 1 Vref 26
1381 12:17:29.413636
1382 12:17:29.413700 ==
1383 12:17:29.416728 Dram Type= 6, Freq= 0, CH_0, rank 1
1384 12:17:29.420376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1385 12:17:29.420460 ==
1386 12:17:29.423525
1387 12:17:29.423605
1388 12:17:29.423668 TX Vref Scan disable
1389 12:17:29.427237 == TX Byte 0 ==
1390 12:17:29.430555 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1391 12:17:29.433846 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1392 12:17:29.437179 == TX Byte 1 ==
1393 12:17:29.440229 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1394 12:17:29.444216 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1395 12:17:29.447321
1396 12:17:29.447508 [DATLAT]
1397 12:17:29.447605 Freq=800, CH0 RK1
1398 12:17:29.447692
1399 12:17:29.450408 DATLAT Default: 0xa
1400 12:17:29.450576 0, 0xFFFF, sum = 0
1401 12:17:29.454511 1, 0xFFFF, sum = 0
1402 12:17:29.454738 2, 0xFFFF, sum = 0
1403 12:17:29.457408 3, 0xFFFF, sum = 0
1404 12:17:29.457632 4, 0xFFFF, sum = 0
1405 12:17:29.460421 5, 0xFFFF, sum = 0
1406 12:17:29.463716 6, 0xFFFF, sum = 0
1407 12:17:29.463935 7, 0xFFFF, sum = 0
1408 12:17:29.467319 8, 0xFFFF, sum = 0
1409 12:17:29.467504 9, 0x0, sum = 1
1410 12:17:29.467648 10, 0x0, sum = 2
1411 12:17:29.470595 11, 0x0, sum = 3
1412 12:17:29.470811 12, 0x0, sum = 4
1413 12:17:29.473724 best_step = 10
1414 12:17:29.474057
1415 12:17:29.474269 ==
1416 12:17:29.477364 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 12:17:29.481000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 12:17:29.481371 ==
1419 12:17:29.484097 RX Vref Scan: 0
1420 12:17:29.484510
1421 12:17:29.484870 RX Vref 0 -> 0, step: 1
1422 12:17:29.485178
1423 12:17:29.487264 RX Delay -111 -> 252, step: 8
1424 12:17:29.494495 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1425 12:17:29.497496 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1426 12:17:29.500702 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1427 12:17:29.504610 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1428 12:17:29.507730 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1429 12:17:29.513829 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1430 12:17:29.517139 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1431 12:17:29.521242 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1432 12:17:29.524301 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1433 12:17:29.527366 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1434 12:17:29.534017 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1435 12:17:29.537130 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1436 12:17:29.540895 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1437 12:17:29.543990 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1438 12:17:29.550438 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1439 12:17:29.553589 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1440 12:17:29.554014 ==
1441 12:17:29.556784 Dram Type= 6, Freq= 0, CH_0, rank 1
1442 12:17:29.560586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 12:17:29.561293 ==
1444 12:17:29.563525 DQS Delay:
1445 12:17:29.564082 DQS0 = 0, DQS1 = 0
1446 12:17:29.564600 DQM Delay:
1447 12:17:29.567133 DQM0 = 85, DQM1 = 77
1448 12:17:29.567791 DQ Delay:
1449 12:17:29.570058 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1450 12:17:29.573827 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1451 12:17:29.576912 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1452 12:17:29.580085 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1453 12:17:29.580507
1454 12:17:29.580874
1455 12:17:29.590170 [DQSOSCAuto] RK1, (LSB)MR18= 0x4109, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
1456 12:17:29.593267 CH0 RK1: MR19=606, MR18=4109
1457 12:17:29.596581 CH0_RK1: MR19=0x606, MR18=0x4109, DQSOSC=393, MR23=63, INC=95, DEC=63
1458 12:17:29.600290 [RxdqsGatingPostProcess] freq 800
1459 12:17:29.606512 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1460 12:17:29.609586 Pre-setting of DQS Precalculation
1461 12:17:29.612944 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1462 12:17:29.613367 ==
1463 12:17:29.617053 Dram Type= 6, Freq= 0, CH_1, rank 0
1464 12:17:29.622727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 12:17:29.623309 ==
1466 12:17:29.626380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1467 12:17:29.633172 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1468 12:17:29.642501 [CA 0] Center 36 (6~67) winsize 62
1469 12:17:29.645754 [CA 1] Center 36 (6~67) winsize 62
1470 12:17:29.648948 [CA 2] Center 34 (4~65) winsize 62
1471 12:17:29.652682 [CA 3] Center 34 (3~65) winsize 63
1472 12:17:29.655786 [CA 4] Center 34 (4~65) winsize 62
1473 12:17:29.659109 [CA 5] Center 34 (3~65) winsize 63
1474 12:17:29.659655
1475 12:17:29.662695 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1476 12:17:29.663130
1477 12:17:29.665939 [CATrainingPosCal] consider 1 rank data
1478 12:17:29.668806 u2DelayCellTimex100 = 270/100 ps
1479 12:17:29.672465 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1480 12:17:29.675597 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 12:17:29.682434 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 12:17:29.685634 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1483 12:17:29.689179 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 12:17:29.692321 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1485 12:17:29.692791
1486 12:17:29.695479 CA PerBit enable=1, Macro0, CA PI delay=34
1487 12:17:29.695907
1488 12:17:29.699420 [CBTSetCACLKResult] CA Dly = 34
1489 12:17:29.699960 CS Dly: 5 (0~36)
1490 12:17:29.702611 ==
1491 12:17:29.703142 Dram Type= 6, Freq= 0, CH_1, rank 1
1492 12:17:29.709350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 12:17:29.709788 ==
1494 12:17:29.712408 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1495 12:17:29.718615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1496 12:17:29.728473 [CA 0] Center 36 (6~67) winsize 62
1497 12:17:29.732082 [CA 1] Center 37 (7~67) winsize 61
1498 12:17:29.735220 [CA 2] Center 34 (4~65) winsize 62
1499 12:17:29.738986 [CA 3] Center 34 (3~65) winsize 63
1500 12:17:29.742000 [CA 4] Center 34 (4~65) winsize 62
1501 12:17:29.745119 [CA 5] Center 34 (3~65) winsize 63
1502 12:17:29.745547
1503 12:17:29.748375 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1504 12:17:29.748823
1505 12:17:29.752124 [CATrainingPosCal] consider 2 rank data
1506 12:17:29.755390 u2DelayCellTimex100 = 270/100 ps
1507 12:17:29.758337 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1508 12:17:29.765066 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1509 12:17:29.768147 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1510 12:17:29.771837 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1511 12:17:29.774827 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1512 12:17:29.778480 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1513 12:17:29.778910
1514 12:17:29.781492 CA PerBit enable=1, Macro0, CA PI delay=34
1515 12:17:29.781923
1516 12:17:29.785317 [CBTSetCACLKResult] CA Dly = 34
1517 12:17:29.785745 CS Dly: 6 (0~38)
1518 12:17:29.788321
1519 12:17:29.791462 ----->DramcWriteLeveling(PI) begin...
1520 12:17:29.791893 ==
1521 12:17:29.795149 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 12:17:29.798598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 12:17:29.799044 ==
1524 12:17:29.801890 Write leveling (Byte 0): 27 => 27
1525 12:17:29.804798 Write leveling (Byte 1): 30 => 30
1526 12:17:29.808444 DramcWriteLeveling(PI) end<-----
1527 12:17:29.808932
1528 12:17:29.809310 ==
1529 12:17:29.811516 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 12:17:29.814644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 12:17:29.815234 ==
1532 12:17:29.817918 [Gating] SW mode calibration
1533 12:17:29.824711 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1534 12:17:29.831150 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1535 12:17:29.834170 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1536 12:17:29.837768 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1537 12:17:29.844056 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:17:29.847821 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:17:29.850916 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:17:29.857731 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:17:29.861016 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:17:29.864194 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:17:29.870543 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:17:29.873703 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:17:29.877377 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:17:29.883919 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 12:17:29.887010 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 12:17:29.890809 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 12:17:29.897208 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 12:17:29.900101 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 12:17:29.903894 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 12:17:29.910074 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1553 12:17:29.913755 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1554 12:17:29.916989 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 12:17:29.920055 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 12:17:29.927057 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 12:17:29.930258 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 12:17:29.933299 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 12:17:29.940127 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 12:17:29.943821 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 12:17:29.946892 0 9 8 | B1->B0 | 2b2b 3232 | 0 0 | (0 0) (0 0)
1562 12:17:29.953793 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1563 12:17:29.957023 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 12:17:29.960090 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1565 12:17:29.966363 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1566 12:17:29.970096 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1567 12:17:29.973388 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1568 12:17:29.979743 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1569 12:17:29.983434 0 10 8 | B1->B0 | 2e2e 2626 | 1 0 | (1 0) (0 0)
1570 12:17:29.986335 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 12:17:29.992856 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 12:17:29.996143 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 12:17:29.999830 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1574 12:17:30.006236 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1575 12:17:30.009902 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1576 12:17:30.013181 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1577 12:17:30.019365 0 11 8 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
1578 12:17:30.023172 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 12:17:30.026346 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 12:17:30.032699 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 12:17:30.036404 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 12:17:30.039595 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 12:17:30.046367 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 12:17:30.049376 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1585 12:17:30.052520 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1586 12:17:30.059553 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 12:17:30.062847 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 12:17:30.066044 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 12:17:30.072403 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 12:17:30.076128 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 12:17:30.079275 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 12:17:30.085892 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 12:17:30.089089 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 12:17:30.092934 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 12:17:30.099005 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 12:17:30.102206 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 12:17:30.106017 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1598 12:17:30.112065 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1599 12:17:30.115717 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1600 12:17:30.118995 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1601 12:17:30.125325 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1602 12:17:30.125406 Total UI for P1: 0, mck2ui 16
1603 12:17:30.132068 best dqsien dly found for B0: ( 0, 14, 4)
1604 12:17:30.132165 Total UI for P1: 0, mck2ui 16
1605 12:17:30.135350 best dqsien dly found for B1: ( 0, 14, 6)
1606 12:17:30.141706 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1607 12:17:30.145392 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1608 12:17:30.145464
1609 12:17:30.148390 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1610 12:17:30.151981 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1611 12:17:30.155077 [Gating] SW calibration Done
1612 12:17:30.155150 ==
1613 12:17:30.158816 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 12:17:30.161955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 12:17:30.162028 ==
1616 12:17:30.165064 RX Vref Scan: 0
1617 12:17:30.165151
1618 12:17:30.165243 RX Vref 0 -> 0, step: 1
1619 12:17:30.165316
1620 12:17:30.168181 RX Delay -130 -> 252, step: 16
1621 12:17:30.171426 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1622 12:17:30.178403 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1623 12:17:30.181528 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1624 12:17:30.185288 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1625 12:17:30.188493 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1626 12:17:30.191514 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1627 12:17:30.198213 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1628 12:17:30.201691 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1629 12:17:30.204767 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1630 12:17:30.208444 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1631 12:17:30.211533 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1632 12:17:30.218028 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1633 12:17:30.221658 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1634 12:17:30.224793 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1635 12:17:30.227928 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1636 12:17:30.231840 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1637 12:17:30.234997 ==
1638 12:17:30.238142 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 12:17:30.241317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 12:17:30.241421 ==
1641 12:17:30.241513 DQS Delay:
1642 12:17:30.245012 DQS0 = 0, DQS1 = 0
1643 12:17:30.245113 DQM Delay:
1644 12:17:30.248083 DQM0 = 89, DQM1 = 78
1645 12:17:30.248189 DQ Delay:
1646 12:17:30.251352 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1647 12:17:30.254486 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1648 12:17:30.258079 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1649 12:17:30.261259 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1650 12:17:30.261356
1651 12:17:30.261431
1652 12:17:30.261502 ==
1653 12:17:30.264438 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 12:17:30.268185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 12:17:30.268299 ==
1656 12:17:30.268387
1657 12:17:30.271568
1658 12:17:30.271682 TX Vref Scan disable
1659 12:17:30.274630 == TX Byte 0 ==
1660 12:17:30.277824 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1661 12:17:30.280998 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1662 12:17:30.284368 == TX Byte 1 ==
1663 12:17:30.288207 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1664 12:17:30.291412 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1665 12:17:30.291841 ==
1666 12:17:30.294486 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 12:17:30.301243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 12:17:30.301674 ==
1669 12:17:30.313323 TX Vref=22, minBit 10, minWin=26, winSum=441
1670 12:17:30.316919 TX Vref=24, minBit 8, minWin=27, winSum=447
1671 12:17:30.319741 TX Vref=26, minBit 9, minWin=27, winSum=451
1672 12:17:30.323328 TX Vref=28, minBit 11, minWin=27, winSum=452
1673 12:17:30.326415 TX Vref=30, minBit 10, minWin=27, winSum=449
1674 12:17:30.333380 TX Vref=32, minBit 8, minWin=27, winSum=445
1675 12:17:30.336465 [TxChooseVref] Worse bit 11, Min win 27, Win sum 452, Final Vref 28
1676 12:17:30.336940
1677 12:17:30.339992 Final TX Range 1 Vref 28
1678 12:17:30.340450
1679 12:17:30.340838 ==
1680 12:17:30.343415 Dram Type= 6, Freq= 0, CH_1, rank 0
1681 12:17:30.346518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1682 12:17:30.349694 ==
1683 12:17:30.350119
1684 12:17:30.350473
1685 12:17:30.350784 TX Vref Scan disable
1686 12:17:30.353550 == TX Byte 0 ==
1687 12:17:30.356785 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1688 12:17:30.363304 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1689 12:17:30.363742 == TX Byte 1 ==
1690 12:17:30.366592 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1691 12:17:30.373766 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1692 12:17:30.374199
1693 12:17:30.374624 [DATLAT]
1694 12:17:30.374967 Freq=800, CH1 RK0
1695 12:17:30.375293
1696 12:17:30.376875 DATLAT Default: 0xa
1697 12:17:30.377380 0, 0xFFFF, sum = 0
1698 12:17:30.380065 1, 0xFFFF, sum = 0
1699 12:17:30.380651 2, 0xFFFF, sum = 0
1700 12:17:30.383177 3, 0xFFFF, sum = 0
1701 12:17:30.387012 4, 0xFFFF, sum = 0
1702 12:17:30.387438 5, 0xFFFF, sum = 0
1703 12:17:30.390033 6, 0xFFFF, sum = 0
1704 12:17:30.390461 7, 0xFFFF, sum = 0
1705 12:17:30.393195 8, 0xFFFF, sum = 0
1706 12:17:30.393644 9, 0x0, sum = 1
1707 12:17:30.396482 10, 0x0, sum = 2
1708 12:17:30.396948 11, 0x0, sum = 3
1709 12:17:30.397295 12, 0x0, sum = 4
1710 12:17:30.400209 best_step = 10
1711 12:17:30.400670
1712 12:17:30.401014 ==
1713 12:17:30.403404 Dram Type= 6, Freq= 0, CH_1, rank 0
1714 12:17:30.406358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1715 12:17:30.406786 ==
1716 12:17:30.409934 RX Vref Scan: 1
1717 12:17:30.410359
1718 12:17:30.413374 Set Vref Range= 32 -> 127
1719 12:17:30.413956
1720 12:17:30.414313 RX Vref 32 -> 127, step: 1
1721 12:17:30.414632
1722 12:17:30.416382 RX Delay -95 -> 252, step: 8
1723 12:17:30.416834
1724 12:17:30.419567 Set Vref, RX VrefLevel [Byte0]: 32
1725 12:17:30.422867 [Byte1]: 32
1726 12:17:30.426522
1727 12:17:30.426947 Set Vref, RX VrefLevel [Byte0]: 33
1728 12:17:30.429550 [Byte1]: 33
1729 12:17:30.433880
1730 12:17:30.434317 Set Vref, RX VrefLevel [Byte0]: 34
1731 12:17:30.437032 [Byte1]: 34
1732 12:17:30.441367
1733 12:17:30.441799 Set Vref, RX VrefLevel [Byte0]: 35
1734 12:17:30.445176 [Byte1]: 35
1735 12:17:30.448966
1736 12:17:30.449388 Set Vref, RX VrefLevel [Byte0]: 36
1737 12:17:30.452622 [Byte1]: 36
1738 12:17:30.456439
1739 12:17:30.460213 Set Vref, RX VrefLevel [Byte0]: 37
1740 12:17:30.463297 [Byte1]: 37
1741 12:17:30.463726
1742 12:17:30.466495 Set Vref, RX VrefLevel [Byte0]: 38
1743 12:17:30.470052 [Byte1]: 38
1744 12:17:30.470550
1745 12:17:30.473137 Set Vref, RX VrefLevel [Byte0]: 39
1746 12:17:30.476448 [Byte1]: 39
1747 12:17:30.476936
1748 12:17:30.479653 Set Vref, RX VrefLevel [Byte0]: 40
1749 12:17:30.482941 [Byte1]: 40
1750 12:17:30.487113
1751 12:17:30.487563 Set Vref, RX VrefLevel [Byte0]: 41
1752 12:17:30.490328 [Byte1]: 41
1753 12:17:30.494642
1754 12:17:30.495068 Set Vref, RX VrefLevel [Byte0]: 42
1755 12:17:30.498102 [Byte1]: 42
1756 12:17:30.502572
1757 12:17:30.503101 Set Vref, RX VrefLevel [Byte0]: 43
1758 12:17:30.505440 [Byte1]: 43
1759 12:17:30.509778
1760 12:17:30.510200 Set Vref, RX VrefLevel [Byte0]: 44
1761 12:17:30.513232 [Byte1]: 44
1762 12:17:30.517427
1763 12:17:30.517849 Set Vref, RX VrefLevel [Byte0]: 45
1764 12:17:30.520859 [Byte1]: 45
1765 12:17:30.525055
1766 12:17:30.525475 Set Vref, RX VrefLevel [Byte0]: 46
1767 12:17:30.527997 [Byte1]: 46
1768 12:17:30.533039
1769 12:17:30.533461 Set Vref, RX VrefLevel [Byte0]: 47
1770 12:17:30.535908 [Byte1]: 47
1771 12:17:30.540312
1772 12:17:30.540780 Set Vref, RX VrefLevel [Byte0]: 48
1773 12:17:30.543540 [Byte1]: 48
1774 12:17:30.548296
1775 12:17:30.548873 Set Vref, RX VrefLevel [Byte0]: 49
1776 12:17:30.551087 [Byte1]: 49
1777 12:17:30.555487
1778 12:17:30.556016 Set Vref, RX VrefLevel [Byte0]: 50
1779 12:17:30.558678 [Byte1]: 50
1780 12:17:30.563358
1781 12:17:30.563886 Set Vref, RX VrefLevel [Byte0]: 51
1782 12:17:30.566477 [Byte1]: 51
1783 12:17:30.570486
1784 12:17:30.570911 Set Vref, RX VrefLevel [Byte0]: 52
1785 12:17:30.574090 [Byte1]: 52
1786 12:17:30.578338
1787 12:17:30.578877 Set Vref, RX VrefLevel [Byte0]: 53
1788 12:17:30.581407 [Byte1]: 53
1789 12:17:30.585914
1790 12:17:30.586482 Set Vref, RX VrefLevel [Byte0]: 54
1791 12:17:30.592620 [Byte1]: 54
1792 12:17:30.593162
1793 12:17:30.595732 Set Vref, RX VrefLevel [Byte0]: 55
1794 12:17:30.598839 [Byte1]: 55
1795 12:17:30.599263
1796 12:17:30.602147 Set Vref, RX VrefLevel [Byte0]: 56
1797 12:17:30.605309 [Byte1]: 56
1798 12:17:30.605733
1799 12:17:30.608855 Set Vref, RX VrefLevel [Byte0]: 57
1800 12:17:30.612043 [Byte1]: 57
1801 12:17:30.616580
1802 12:17:30.617020 Set Vref, RX VrefLevel [Byte0]: 58
1803 12:17:30.619374 [Byte1]: 58
1804 12:17:30.623600
1805 12:17:30.624023 Set Vref, RX VrefLevel [Byte0]: 59
1806 12:17:30.627179 [Byte1]: 59
1807 12:17:30.631394
1808 12:17:30.631818 Set Vref, RX VrefLevel [Byte0]: 60
1809 12:17:30.634527 [Byte1]: 60
1810 12:17:30.638748
1811 12:17:30.639170 Set Vref, RX VrefLevel [Byte0]: 61
1812 12:17:30.642351 [Byte1]: 61
1813 12:17:30.647015
1814 12:17:30.647539 Set Vref, RX VrefLevel [Byte0]: 62
1815 12:17:30.650404 [Byte1]: 62
1816 12:17:30.654133
1817 12:17:30.654661 Set Vref, RX VrefLevel [Byte0]: 63
1818 12:17:30.657688 [Byte1]: 63
1819 12:17:30.662029
1820 12:17:30.662558 Set Vref, RX VrefLevel [Byte0]: 64
1821 12:17:30.665118 [Byte1]: 64
1822 12:17:30.669452
1823 12:17:30.669877 Set Vref, RX VrefLevel [Byte0]: 65
1824 12:17:30.672433 [Byte1]: 65
1825 12:17:30.676816
1826 12:17:30.677238 Set Vref, RX VrefLevel [Byte0]: 66
1827 12:17:30.680440 [Byte1]: 66
1828 12:17:30.684803
1829 12:17:30.685237 Set Vref, RX VrefLevel [Byte0]: 67
1830 12:17:30.687888 [Byte1]: 67
1831 12:17:30.692387
1832 12:17:30.692880 Set Vref, RX VrefLevel [Byte0]: 68
1833 12:17:30.695886 [Byte1]: 68
1834 12:17:30.700083
1835 12:17:30.700549 Set Vref, RX VrefLevel [Byte0]: 69
1836 12:17:30.703218 [Byte1]: 69
1837 12:17:30.707540
1838 12:17:30.707972 Set Vref, RX VrefLevel [Byte0]: 70
1839 12:17:30.710757 [Byte1]: 70
1840 12:17:30.715288
1841 12:17:30.715839 Set Vref, RX VrefLevel [Byte0]: 71
1842 12:17:30.718180 [Byte1]: 71
1843 12:17:30.722518
1844 12:17:30.723054 Set Vref, RX VrefLevel [Byte0]: 72
1845 12:17:30.726048 [Byte1]: 72
1846 12:17:30.730361
1847 12:17:30.730795 Set Vref, RX VrefLevel [Byte0]: 73
1848 12:17:30.733347 [Byte1]: 73
1849 12:17:30.737864
1850 12:17:30.738303 Final RX Vref Byte 0 = 56 to rank0
1851 12:17:30.741105 Final RX Vref Byte 1 = 63 to rank0
1852 12:17:30.744018 Final RX Vref Byte 0 = 56 to rank1
1853 12:17:30.747610 Final RX Vref Byte 1 = 63 to rank1==
1854 12:17:30.750842 Dram Type= 6, Freq= 0, CH_1, rank 0
1855 12:17:30.757148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 12:17:30.757588 ==
1857 12:17:30.758021 DQS Delay:
1858 12:17:30.760870 DQS0 = 0, DQS1 = 0
1859 12:17:30.761305 DQM Delay:
1860 12:17:30.761737 DQM0 = 87, DQM1 = 79
1861 12:17:30.763985 DQ Delay:
1862 12:17:30.767111 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1863 12:17:30.770870 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1864 12:17:30.774031 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1865 12:17:30.777032 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1866 12:17:30.777466
1867 12:17:30.777894
1868 12:17:30.783901 [DQSOSCAuto] RK0, (LSB)MR18= 0x301c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1869 12:17:30.787631 CH1 RK0: MR19=606, MR18=301C
1870 12:17:30.794099 CH1_RK0: MR19=0x606, MR18=0x301C, DQSOSC=397, MR23=63, INC=93, DEC=62
1871 12:17:30.794635
1872 12:17:30.797301 ----->DramcWriteLeveling(PI) begin...
1873 12:17:30.797746 ==
1874 12:17:30.800376 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 12:17:30.803615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 12:17:30.804156 ==
1877 12:17:30.807293 Write leveling (Byte 0): 27 => 27
1878 12:17:30.810460 Write leveling (Byte 1): 28 => 28
1879 12:17:30.813688 DramcWriteLeveling(PI) end<-----
1880 12:17:30.814122
1881 12:17:30.814553 ==
1882 12:17:30.817274 Dram Type= 6, Freq= 0, CH_1, rank 1
1883 12:17:30.820379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1884 12:17:30.823691 ==
1885 12:17:30.824239 [Gating] SW mode calibration
1886 12:17:30.830577 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1887 12:17:30.836988 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1888 12:17:30.840548 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1889 12:17:30.846835 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1890 12:17:30.850342 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:17:30.853377 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:17:30.860184 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:17:30.863328 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:17:30.866617 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:17:30.873362 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:17:30.876487 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:17:30.879683 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:17:30.886542 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:17:30.889536 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:17:30.893283 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:17:30.900070 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:17:30.903351 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 12:17:30.906521 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 12:17:30.913389 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1905 12:17:30.916612 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1906 12:17:30.919765 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1907 12:17:30.926396 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 12:17:30.929711 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 12:17:30.932745 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 12:17:30.935890 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 12:17:30.943055 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 12:17:30.945944 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 12:17:30.949607 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 12:17:30.956020 0 9 8 | B1->B0 | 3232 2828 | 0 1 | (0 0) (1 1)
1915 12:17:30.959656 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 12:17:30.962559 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 12:17:30.969268 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 12:17:30.972590 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 12:17:30.975862 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 12:17:30.982907 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 12:17:30.985980 0 10 4 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 0)
1922 12:17:30.989023 0 10 8 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (1 0)
1923 12:17:30.995774 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 12:17:30.998779 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 12:17:31.002535 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 12:17:31.008759 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 12:17:31.012255 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 12:17:31.015372 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 12:17:31.022093 0 11 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1930 12:17:31.025450 0 11 8 | B1->B0 | 3e3d 3939 | 1 0 | (0 0) (0 0)
1931 12:17:31.028418 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 12:17:31.035392 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 12:17:31.038548 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 12:17:31.041634 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 12:17:31.048364 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 12:17:31.051928 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 12:17:31.054849 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1938 12:17:31.061849 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1939 12:17:31.064869 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:17:31.068408 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 12:17:31.074700 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 12:17:31.077882 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 12:17:31.081540 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 12:17:31.087853 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 12:17:31.091595 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 12:17:31.094873 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 12:17:31.101633 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 12:17:31.104788 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 12:17:31.107920 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 12:17:31.114816 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 12:17:31.117965 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 12:17:31.120999 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 12:17:31.127834 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1954 12:17:31.130921 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1955 12:17:31.134652 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1956 12:17:31.137786 Total UI for P1: 0, mck2ui 16
1957 12:17:31.140880 best dqsien dly found for B0: ( 0, 14, 6)
1958 12:17:31.144727 Total UI for P1: 0, mck2ui 16
1959 12:17:31.147912 best dqsien dly found for B1: ( 0, 14, 6)
1960 12:17:31.150879 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1961 12:17:31.154049 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1962 12:17:31.154134
1963 12:17:31.157735 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1964 12:17:31.164312 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1965 12:17:31.164397 [Gating] SW calibration Done
1966 12:17:31.164464 ==
1967 12:17:31.167782 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 12:17:31.174383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 12:17:31.174475 ==
1970 12:17:31.174542 RX Vref Scan: 0
1971 12:17:31.174604
1972 12:17:31.177537 RX Vref 0 -> 0, step: 1
1973 12:17:31.177622
1974 12:17:31.180786 RX Delay -130 -> 252, step: 16
1975 12:17:31.183967 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1976 12:17:31.187609 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1977 12:17:31.190768 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1978 12:17:31.197814 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1979 12:17:31.200850 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1980 12:17:31.204389 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1981 12:17:31.207164 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1982 12:17:31.211016 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1983 12:17:31.217701 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1984 12:17:31.220773 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1985 12:17:31.223920 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1986 12:17:31.227532 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1987 12:17:31.230743 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1988 12:17:31.237573 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1989 12:17:31.240771 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1990 12:17:31.243898 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1991 12:17:31.243981 ==
1992 12:17:31.247080 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 12:17:31.250663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 12:17:31.253803 ==
1995 12:17:31.253895 DQS Delay:
1996 12:17:31.253959 DQS0 = 0, DQS1 = 0
1997 12:17:31.256982 DQM Delay:
1998 12:17:31.257065 DQM0 = 86, DQM1 = 78
1999 12:17:31.260140 DQ Delay:
2000 12:17:31.260223 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
2001 12:17:31.263690 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2002 12:17:31.267126 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2003 12:17:31.270669 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2004 12:17:31.273613
2005 12:17:31.273711
2006 12:17:31.273777 ==
2007 12:17:31.277404 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 12:17:31.280331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 12:17:31.280420 ==
2010 12:17:31.280484
2011 12:17:31.280586
2012 12:17:31.283548 TX Vref Scan disable
2013 12:17:31.283631 == TX Byte 0 ==
2014 12:17:31.290430 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2015 12:17:31.293643 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2016 12:17:31.293727 == TX Byte 1 ==
2017 12:17:31.300022 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2018 12:17:31.303843 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2019 12:17:31.303928 ==
2020 12:17:31.306951 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 12:17:31.309977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 12:17:31.310060 ==
2023 12:17:31.323937 TX Vref=22, minBit 0, minWin=27, winSum=445
2024 12:17:31.327145 TX Vref=24, minBit 8, minWin=27, winSum=446
2025 12:17:31.330977 TX Vref=26, minBit 1, minWin=27, winSum=447
2026 12:17:31.334202 TX Vref=28, minBit 0, minWin=28, winSum=452
2027 12:17:31.337393 TX Vref=30, minBit 8, minWin=27, winSum=450
2028 12:17:31.343577 TX Vref=32, minBit 8, minWin=27, winSum=450
2029 12:17:31.347308 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 28
2030 12:17:31.347410
2031 12:17:31.350452 Final TX Range 1 Vref 28
2032 12:17:31.350523
2033 12:17:31.350584 ==
2034 12:17:31.353694 Dram Type= 6, Freq= 0, CH_1, rank 1
2035 12:17:31.356793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2036 12:17:31.360019 ==
2037 12:17:31.360122
2038 12:17:31.360213
2039 12:17:31.360309 TX Vref Scan disable
2040 12:17:31.363816 == TX Byte 0 ==
2041 12:17:31.367427 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2042 12:17:31.374094 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2043 12:17:31.374176 == TX Byte 1 ==
2044 12:17:31.377108 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2045 12:17:31.383697 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2046 12:17:31.383782
2047 12:17:31.383877 [DATLAT]
2048 12:17:31.383938 Freq=800, CH1 RK1
2049 12:17:31.383998
2050 12:17:31.386948 DATLAT Default: 0xa
2051 12:17:31.387077 0, 0xFFFF, sum = 0
2052 12:17:31.390618 1, 0xFFFF, sum = 0
2053 12:17:31.393712 2, 0xFFFF, sum = 0
2054 12:17:31.393797 3, 0xFFFF, sum = 0
2055 12:17:31.396917 4, 0xFFFF, sum = 0
2056 12:17:31.397002 5, 0xFFFF, sum = 0
2057 12:17:31.400146 6, 0xFFFF, sum = 0
2058 12:17:31.400244 7, 0xFFFF, sum = 0
2059 12:17:31.403960 8, 0xFFFF, sum = 0
2060 12:17:31.404044 9, 0x0, sum = 1
2061 12:17:31.407156 10, 0x0, sum = 2
2062 12:17:31.407239 11, 0x0, sum = 3
2063 12:17:31.407306 12, 0x0, sum = 4
2064 12:17:31.410275 best_step = 10
2065 12:17:31.410358
2066 12:17:31.410422 ==
2067 12:17:31.413948 Dram Type= 6, Freq= 0, CH_1, rank 1
2068 12:17:31.416931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2069 12:17:31.417015 ==
2070 12:17:31.420032 RX Vref Scan: 0
2071 12:17:31.420115
2072 12:17:31.423808 RX Vref 0 -> 0, step: 1
2073 12:17:31.423891
2074 12:17:31.423956 RX Delay -95 -> 252, step: 8
2075 12:17:31.430666 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2076 12:17:31.433748 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2077 12:17:31.437532 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2078 12:17:31.440746 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2079 12:17:31.443948 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2080 12:17:31.450496 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2081 12:17:31.454272 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2082 12:17:31.457347 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2083 12:17:31.460347 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2084 12:17:31.464096 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2085 12:17:31.470386 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2086 12:17:31.473565 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2087 12:17:31.477275 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2088 12:17:31.480351 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2089 12:17:31.486901 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2090 12:17:31.490472 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2091 12:17:31.490558 ==
2092 12:17:31.493573 Dram Type= 6, Freq= 0, CH_1, rank 1
2093 12:17:31.496791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2094 12:17:31.496905 ==
2095 12:17:31.499927 DQS Delay:
2096 12:17:31.500004 DQS0 = 0, DQS1 = 0
2097 12:17:31.500069 DQM Delay:
2098 12:17:31.503720 DQM0 = 87, DQM1 = 78
2099 12:17:31.503794 DQ Delay:
2100 12:17:31.506931 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2101 12:17:31.510041 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2102 12:17:31.513194 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2103 12:17:31.516914 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2104 12:17:31.517007
2105 12:17:31.517075
2106 12:17:31.526705 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2107 12:17:31.526827 CH1 RK1: MR19=606, MR18=1C14
2108 12:17:31.533638 CH1_RK1: MR19=0x606, MR18=0x1C14, DQSOSC=402, MR23=63, INC=91, DEC=60
2109 12:17:31.536808 [RxdqsGatingPostProcess] freq 800
2110 12:17:31.543645 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2111 12:17:31.546881 Pre-setting of DQS Precalculation
2112 12:17:31.550028 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2113 12:17:31.556990 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2114 12:17:31.566868 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2115 12:17:31.566953
2116 12:17:31.567022
2117 12:17:31.570072 [Calibration Summary] 1600 Mbps
2118 12:17:31.570156 CH 0, Rank 0
2119 12:17:31.573237 SW Impedance : PASS
2120 12:17:31.573330 DUTY Scan : NO K
2121 12:17:31.577002 ZQ Calibration : PASS
2122 12:17:31.577091 Jitter Meter : NO K
2123 12:17:31.580070 CBT Training : PASS
2124 12:17:31.583808 Write leveling : PASS
2125 12:17:31.583916 RX DQS gating : PASS
2126 12:17:31.586971 RX DQ/DQS(RDDQC) : PASS
2127 12:17:31.589992 TX DQ/DQS : PASS
2128 12:17:31.590098 RX DATLAT : PASS
2129 12:17:31.593608 RX DQ/DQS(Engine): PASS
2130 12:17:31.596779 TX OE : NO K
2131 12:17:31.596857 All Pass.
2132 12:17:31.596925
2133 12:17:31.596986 CH 0, Rank 1
2134 12:17:31.599935 SW Impedance : PASS
2135 12:17:31.603684 DUTY Scan : NO K
2136 12:17:31.603773 ZQ Calibration : PASS
2137 12:17:31.606839 Jitter Meter : NO K
2138 12:17:31.609966 CBT Training : PASS
2139 12:17:31.610051 Write leveling : PASS
2140 12:17:31.613428 RX DQS gating : PASS
2141 12:17:31.616628 RX DQ/DQS(RDDQC) : PASS
2142 12:17:31.616715 TX DQ/DQS : PASS
2143 12:17:31.620289 RX DATLAT : PASS
2144 12:17:31.620376 RX DQ/DQS(Engine): PASS
2145 12:17:31.623325 TX OE : NO K
2146 12:17:31.623399 All Pass.
2147 12:17:31.623466
2148 12:17:31.626866 CH 1, Rank 0
2149 12:17:31.626953 SW Impedance : PASS
2150 12:17:31.629779 DUTY Scan : NO K
2151 12:17:31.633530 ZQ Calibration : PASS
2152 12:17:31.633614 Jitter Meter : NO K
2153 12:17:31.636593 CBT Training : PASS
2154 12:17:31.639780 Write leveling : PASS
2155 12:17:31.639865 RX DQS gating : PASS
2156 12:17:31.643580 RX DQ/DQS(RDDQC) : PASS
2157 12:17:31.646670 TX DQ/DQS : PASS
2158 12:17:31.646746 RX DATLAT : PASS
2159 12:17:31.649848 RX DQ/DQS(Engine): PASS
2160 12:17:31.653066 TX OE : NO K
2161 12:17:31.653152 All Pass.
2162 12:17:31.653222
2163 12:17:31.653284 CH 1, Rank 1
2164 12:17:31.656649 SW Impedance : PASS
2165 12:17:31.659738 DUTY Scan : NO K
2166 12:17:31.659824 ZQ Calibration : PASS
2167 12:17:31.662963 Jitter Meter : NO K
2168 12:17:31.666747 CBT Training : PASS
2169 12:17:31.666830 Write leveling : PASS
2170 12:17:31.669771 RX DQS gating : PASS
2171 12:17:31.672954 RX DQ/DQS(RDDQC) : PASS
2172 12:17:31.673044 TX DQ/DQS : PASS
2173 12:17:31.676733 RX DATLAT : PASS
2174 12:17:31.676824 RX DQ/DQS(Engine): PASS
2175 12:17:31.679717 TX OE : NO K
2176 12:17:31.679830 All Pass.
2177 12:17:31.679939
2178 12:17:31.682821 DramC Write-DBI off
2179 12:17:31.686573 PER_BANK_REFRESH: Hybrid Mode
2180 12:17:31.686660 TX_TRACKING: ON
2181 12:17:31.689605 [GetDramInforAfterCalByMRR] Vendor 6.
2182 12:17:31.693366 [GetDramInforAfterCalByMRR] Revision 606.
2183 12:17:31.699513 [GetDramInforAfterCalByMRR] Revision 2 0.
2184 12:17:31.699595 MR0 0x3b3b
2185 12:17:31.699670 MR8 0x5151
2186 12:17:31.703152 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2187 12:17:31.703228
2188 12:17:31.706398 MR0 0x3b3b
2189 12:17:31.706472 MR8 0x5151
2190 12:17:31.709504 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2191 12:17:31.709577
2192 12:17:31.719689 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2193 12:17:31.722880 [FAST_K] Save calibration result to emmc
2194 12:17:31.725969 [FAST_K] Save calibration result to emmc
2195 12:17:31.729727 dram_init: config_dvfs: 1
2196 12:17:31.732619 dramc_set_vcore_voltage set vcore to 662500
2197 12:17:31.736171 Read voltage for 1200, 2
2198 12:17:31.736272 Vio18 = 0
2199 12:17:31.736371 Vcore = 662500
2200 12:17:31.739431 Vdram = 0
2201 12:17:31.739536 Vddq = 0
2202 12:17:31.739626 Vmddr = 0
2203 12:17:31.746049 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2204 12:17:31.749175 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2205 12:17:31.752340 MEM_TYPE=3, freq_sel=15
2206 12:17:31.756033 sv_algorithm_assistance_LP4_1600
2207 12:17:31.759128 ============ PULL DRAM RESETB DOWN ============
2208 12:17:31.762312 ========== PULL DRAM RESETB DOWN end =========
2209 12:17:31.769317 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2210 12:17:31.772366 ===================================
2211 12:17:31.772444 LPDDR4 DRAM CONFIGURATION
2212 12:17:31.775548 ===================================
2213 12:17:31.779339 EX_ROW_EN[0] = 0x0
2214 12:17:31.782515 EX_ROW_EN[1] = 0x0
2215 12:17:31.782596 LP4Y_EN = 0x0
2216 12:17:31.785655 WORK_FSP = 0x0
2217 12:17:31.785738 WL = 0x4
2218 12:17:31.788910 RL = 0x4
2219 12:17:31.788993 BL = 0x2
2220 12:17:31.792017 RPST = 0x0
2221 12:17:31.792100 RD_PRE = 0x0
2222 12:17:31.795634 WR_PRE = 0x1
2223 12:17:31.795717 WR_PST = 0x0
2224 12:17:31.798765 DBI_WR = 0x0
2225 12:17:31.798865 DBI_RD = 0x0
2226 12:17:31.802236 OTF = 0x1
2227 12:17:31.805686 ===================================
2228 12:17:31.808740 ===================================
2229 12:17:31.808909 ANA top config
2230 12:17:31.811859 ===================================
2231 12:17:31.815759 DLL_ASYNC_EN = 0
2232 12:17:31.818837 ALL_SLAVE_EN = 0
2233 12:17:31.821911 NEW_RANK_MODE = 1
2234 12:17:31.821995 DLL_IDLE_MODE = 1
2235 12:17:31.825797 LP45_APHY_COMB_EN = 1
2236 12:17:31.828960 TX_ODT_DIS = 1
2237 12:17:31.832018 NEW_8X_MODE = 1
2238 12:17:31.835665 ===================================
2239 12:17:31.838748 ===================================
2240 12:17:31.841820 data_rate = 2400
2241 12:17:31.841904 CKR = 1
2242 12:17:31.845581 DQ_P2S_RATIO = 8
2243 12:17:31.848638 ===================================
2244 12:17:31.851853 CA_P2S_RATIO = 8
2245 12:17:31.854987 DQ_CA_OPEN = 0
2246 12:17:31.858582 DQ_SEMI_OPEN = 0
2247 12:17:31.861844 CA_SEMI_OPEN = 0
2248 12:17:31.861928 CA_FULL_RATE = 0
2249 12:17:31.865486 DQ_CKDIV4_EN = 0
2250 12:17:31.868632 CA_CKDIV4_EN = 0
2251 12:17:31.872321 CA_PREDIV_EN = 0
2252 12:17:31.875326 PH8_DLY = 17
2253 12:17:31.875410 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2254 12:17:31.878535 DQ_AAMCK_DIV = 4
2255 12:17:31.881620 CA_AAMCK_DIV = 4
2256 12:17:31.885411 CA_ADMCK_DIV = 4
2257 12:17:31.888557 DQ_TRACK_CA_EN = 0
2258 12:17:31.891727 CA_PICK = 1200
2259 12:17:31.895385 CA_MCKIO = 1200
2260 12:17:31.895467 MCKIO_SEMI = 0
2261 12:17:31.898455 PLL_FREQ = 2366
2262 12:17:31.901993 DQ_UI_PI_RATIO = 32
2263 12:17:31.904923 CA_UI_PI_RATIO = 0
2264 12:17:31.908437 ===================================
2265 12:17:31.911513 ===================================
2266 12:17:31.914756 memory_type:LPDDR4
2267 12:17:31.917911 GP_NUM : 10
2268 12:17:31.918010 SRAM_EN : 1
2269 12:17:31.921604 MD32_EN : 0
2270 12:17:31.924783 ===================================
2271 12:17:31.924889 [ANA_INIT] >>>>>>>>>>>>>>
2272 12:17:31.927902 <<<<<< [CONFIGURE PHASE]: ANA_TX
2273 12:17:31.931676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2274 12:17:31.934769 ===================================
2275 12:17:31.937988 data_rate = 2400,PCW = 0X5b00
2276 12:17:31.941425 ===================================
2277 12:17:31.944410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2278 12:17:31.951168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2279 12:17:31.954485 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2280 12:17:31.961318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2281 12:17:31.964447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2282 12:17:31.968120 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2283 12:17:31.971337 [ANA_INIT] flow start
2284 12:17:31.971419 [ANA_INIT] PLL >>>>>>>>
2285 12:17:31.974564 [ANA_INIT] PLL <<<<<<<<
2286 12:17:31.977604 [ANA_INIT] MIDPI >>>>>>>>
2287 12:17:31.977703 [ANA_INIT] MIDPI <<<<<<<<
2288 12:17:31.981341 [ANA_INIT] DLL >>>>>>>>
2289 12:17:31.984497 [ANA_INIT] DLL <<<<<<<<
2290 12:17:31.984603 [ANA_INIT] flow end
2291 12:17:31.990890 ============ LP4 DIFF to SE enter ============
2292 12:17:31.994649 ============ LP4 DIFF to SE exit ============
2293 12:17:31.997940 [ANA_INIT] <<<<<<<<<<<<<
2294 12:17:31.998022 [Flow] Enable top DCM control >>>>>
2295 12:17:32.000826 [Flow] Enable top DCM control <<<<<
2296 12:17:32.004439 Enable DLL master slave shuffle
2297 12:17:32.011154 ==============================================================
2298 12:17:32.014201 Gating Mode config
2299 12:17:32.017398 ==============================================================
2300 12:17:32.021126 Config description:
2301 12:17:32.031080 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2302 12:17:32.037568 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2303 12:17:32.041176 SELPH_MODE 0: By rank 1: By Phase
2304 12:17:32.047769 ==============================================================
2305 12:17:32.050788 GAT_TRACK_EN = 1
2306 12:17:32.053786 RX_GATING_MODE = 2
2307 12:17:32.057613 RX_GATING_TRACK_MODE = 2
2308 12:17:32.057725 SELPH_MODE = 1
2309 12:17:32.060770 PICG_EARLY_EN = 1
2310 12:17:32.063810 VALID_LAT_VALUE = 1
2311 12:17:32.070668 ==============================================================
2312 12:17:32.073805 Enter into Gating configuration >>>>
2313 12:17:32.077077 Exit from Gating configuration <<<<
2314 12:17:32.080918 Enter into DVFS_PRE_config >>>>>
2315 12:17:32.090310 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2316 12:17:32.093598 Exit from DVFS_PRE_config <<<<<
2317 12:17:32.097343 Enter into PICG configuration >>>>
2318 12:17:32.100503 Exit from PICG configuration <<<<
2319 12:17:32.103631 [RX_INPUT] configuration >>>>>
2320 12:17:32.106794 [RX_INPUT] configuration <<<<<
2321 12:17:32.110288 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2322 12:17:32.116873 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2323 12:17:32.123751 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2324 12:17:32.130602 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2325 12:17:32.133793 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2326 12:17:32.140205 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2327 12:17:32.146766 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2328 12:17:32.150291 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2329 12:17:32.153823 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2330 12:17:32.156931 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2331 12:17:32.163287 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2332 12:17:32.166980 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 12:17:32.170101 ===================================
2334 12:17:32.173485 LPDDR4 DRAM CONFIGURATION
2335 12:17:32.176596 ===================================
2336 12:17:32.176687 EX_ROW_EN[0] = 0x0
2337 12:17:32.180327 EX_ROW_EN[1] = 0x0
2338 12:17:32.180413 LP4Y_EN = 0x0
2339 12:17:32.183439 WORK_FSP = 0x0
2340 12:17:32.183516 WL = 0x4
2341 12:17:32.186480 RL = 0x4
2342 12:17:32.186558 BL = 0x2
2343 12:17:32.190317 RPST = 0x0
2344 12:17:32.190407 RD_PRE = 0x0
2345 12:17:32.193540 WR_PRE = 0x1
2346 12:17:32.193629 WR_PST = 0x0
2347 12:17:32.196548 DBI_WR = 0x0
2348 12:17:32.199909 DBI_RD = 0x0
2349 12:17:32.199990 OTF = 0x1
2350 12:17:32.203137 ===================================
2351 12:17:32.206390 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2352 12:17:32.210030 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2353 12:17:32.216914 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2354 12:17:32.219842 ===================================
2355 12:17:32.223460 LPDDR4 DRAM CONFIGURATION
2356 12:17:32.226437 ===================================
2357 12:17:32.226573 EX_ROW_EN[0] = 0x10
2358 12:17:32.229698 EX_ROW_EN[1] = 0x0
2359 12:17:32.229777 LP4Y_EN = 0x0
2360 12:17:32.232830 WORK_FSP = 0x0
2361 12:17:32.232913 WL = 0x4
2362 12:17:32.236680 RL = 0x4
2363 12:17:32.236761 BL = 0x2
2364 12:17:32.239924 RPST = 0x0
2365 12:17:32.240006 RD_PRE = 0x0
2366 12:17:32.242986 WR_PRE = 0x1
2367 12:17:32.243079 WR_PST = 0x0
2368 12:17:32.246727 DBI_WR = 0x0
2369 12:17:32.246814 DBI_RD = 0x0
2370 12:17:32.249729 OTF = 0x1
2371 12:17:32.252691 ===================================
2372 12:17:32.259825 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2373 12:17:32.259908 ==
2374 12:17:32.262942 Dram Type= 6, Freq= 0, CH_0, rank 0
2375 12:17:32.266073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 12:17:32.266155 ==
2377 12:17:32.269837 [Duty_Offset_Calibration]
2378 12:17:32.269917 B0:1 B1:-1 CA:0
2379 12:17:32.269980
2380 12:17:32.272850 [DutyScan_Calibration_Flow] k_type=0
2381 12:17:32.283522
2382 12:17:32.283604 ==CLK 0==
2383 12:17:32.287155 Final CLK duty delay cell = 0
2384 12:17:32.290422 [0] MAX Duty = 5125%(X100), DQS PI = 24
2385 12:17:32.294077 [0] MIN Duty = 4907%(X100), DQS PI = 8
2386 12:17:32.294159 [0] AVG Duty = 5016%(X100)
2387 12:17:32.294222
2388 12:17:32.297159 CH0 CLK Duty spec in!! Max-Min= 218%
2389 12:17:32.304143 [DutyScan_Calibration_Flow] ====Done====
2390 12:17:32.304236
2391 12:17:32.307324 [DutyScan_Calibration_Flow] k_type=1
2392 12:17:32.321481
2393 12:17:32.321563 ==DQS 0 ==
2394 12:17:32.324670 Final DQS duty delay cell = -4
2395 12:17:32.328121 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2396 12:17:32.331153 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2397 12:17:32.334841 [-4] AVG Duty = 4968%(X100)
2398 12:17:32.334922
2399 12:17:32.334984 ==DQS 1 ==
2400 12:17:32.338031 Final DQS duty delay cell = -4
2401 12:17:32.341133 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2402 12:17:32.344459 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2403 12:17:32.347750 [-4] AVG Duty = 4938%(X100)
2404 12:17:32.347831
2405 12:17:32.350821 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2406 12:17:32.350902
2407 12:17:32.353907 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2408 12:17:32.357674 [DutyScan_Calibration_Flow] ====Done====
2409 12:17:32.357755
2410 12:17:32.360790 [DutyScan_Calibration_Flow] k_type=3
2411 12:17:32.379698
2412 12:17:32.379884 ==DQM 0 ==
2413 12:17:32.383005 Final DQM duty delay cell = 0
2414 12:17:32.386032 [0] MAX Duty = 5031%(X100), DQS PI = 16
2415 12:17:32.389925 [0] MIN Duty = 4875%(X100), DQS PI = 8
2416 12:17:32.390138 [0] AVG Duty = 4953%(X100)
2417 12:17:32.392510
2418 12:17:32.392741 ==DQM 1 ==
2419 12:17:32.396276 Final DQM duty delay cell = 4
2420 12:17:32.399572 [4] MAX Duty = 5187%(X100), DQS PI = 14
2421 12:17:32.402947 [4] MIN Duty = 5000%(X100), DQS PI = 24
2422 12:17:32.405723 [4] AVG Duty = 5093%(X100)
2423 12:17:32.405983
2424 12:17:32.409602 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2425 12:17:32.409924
2426 12:17:32.412630 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2427 12:17:32.415899 [DutyScan_Calibration_Flow] ====Done====
2428 12:17:32.416197
2429 12:17:32.419159 [DutyScan_Calibration_Flow] k_type=2
2430 12:17:32.435407
2431 12:17:32.435825 ==DQ 0 ==
2432 12:17:32.438713 Final DQ duty delay cell = -4
2433 12:17:32.441937 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2434 12:17:32.445819 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2435 12:17:32.448902 [-4] AVG Duty = 4969%(X100)
2436 12:17:32.449417
2437 12:17:32.449745 ==DQ 1 ==
2438 12:17:32.452110 Final DQ duty delay cell = 0
2439 12:17:32.456077 [0] MAX Duty = 5093%(X100), DQS PI = 4
2440 12:17:32.459112 [0] MIN Duty = 4969%(X100), DQS PI = 40
2441 12:17:32.459628 [0] AVG Duty = 5031%(X100)
2442 12:17:32.461794
2443 12:17:32.465645 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2444 12:17:32.466169
2445 12:17:32.468930 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2446 12:17:32.472124 [DutyScan_Calibration_Flow] ====Done====
2447 12:17:32.472577 ==
2448 12:17:32.475131 Dram Type= 6, Freq= 0, CH_1, rank 0
2449 12:17:32.478852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2450 12:17:32.479271 ==
2451 12:17:32.482076 [Duty_Offset_Calibration]
2452 12:17:32.482496 B0:-1 B1:1 CA:1
2453 12:17:32.482820
2454 12:17:32.485199 [DutyScan_Calibration_Flow] k_type=0
2455 12:17:32.495937
2456 12:17:32.496510 ==CLK 0==
2457 12:17:32.498921 Final CLK duty delay cell = 0
2458 12:17:32.502628 [0] MAX Duty = 5156%(X100), DQS PI = 20
2459 12:17:32.505915 [0] MIN Duty = 4969%(X100), DQS PI = 60
2460 12:17:32.509093 [0] AVG Duty = 5062%(X100)
2461 12:17:32.509522
2462 12:17:32.512129 CH1 CLK Duty spec in!! Max-Min= 187%
2463 12:17:32.515467 [DutyScan_Calibration_Flow] ====Done====
2464 12:17:32.516026
2465 12:17:32.519319 [DutyScan_Calibration_Flow] k_type=1
2466 12:17:32.534742
2467 12:17:32.534841 ==DQS 0 ==
2468 12:17:32.537716 Final DQS duty delay cell = 0
2469 12:17:32.541472 [0] MAX Duty = 5156%(X100), DQS PI = 48
2470 12:17:32.544533 [0] MIN Duty = 4938%(X100), DQS PI = 6
2471 12:17:32.548199 [0] AVG Duty = 5047%(X100)
2472 12:17:32.548383
2473 12:17:32.548474 ==DQS 1 ==
2474 12:17:32.551182 Final DQS duty delay cell = 0
2475 12:17:32.555055 [0] MAX Duty = 5062%(X100), DQS PI = 8
2476 12:17:32.557912 [0] MIN Duty = 4969%(X100), DQS PI = 58
2477 12:17:32.561018 [0] AVG Duty = 5015%(X100)
2478 12:17:32.561155
2479 12:17:32.564300 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2480 12:17:32.564454
2481 12:17:32.567906 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2482 12:17:32.571119 [DutyScan_Calibration_Flow] ====Done====
2483 12:17:32.571296
2484 12:17:32.574080 [DutyScan_Calibration_Flow] k_type=3
2485 12:17:32.590631
2486 12:17:32.591151 ==DQM 0 ==
2487 12:17:32.593705 Final DQM duty delay cell = -4
2488 12:17:32.597176 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2489 12:17:32.600611 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2490 12:17:32.603700 [-4] AVG Duty = 4969%(X100)
2491 12:17:32.604128
2492 12:17:32.604659 ==DQM 1 ==
2493 12:17:32.606965 Final DQM duty delay cell = 0
2494 12:17:32.610131 [0] MAX Duty = 5187%(X100), DQS PI = 6
2495 12:17:32.613963 [0] MIN Duty = 4969%(X100), DQS PI = 28
2496 12:17:32.617281 [0] AVG Duty = 5078%(X100)
2497 12:17:32.617727
2498 12:17:32.620512 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2499 12:17:32.620971
2500 12:17:32.623589 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2501 12:17:32.626774 [DutyScan_Calibration_Flow] ====Done====
2502 12:17:32.627200
2503 12:17:32.630467 [DutyScan_Calibration_Flow] k_type=2
2504 12:17:32.647067
2505 12:17:32.647589 ==DQ 0 ==
2506 12:17:32.650807 Final DQ duty delay cell = 0
2507 12:17:32.654040 [0] MAX Duty = 5156%(X100), DQS PI = 28
2508 12:17:32.657062 [0] MIN Duty = 4907%(X100), DQS PI = 6
2509 12:17:32.657491 [0] AVG Duty = 5031%(X100)
2510 12:17:32.660697
2511 12:17:32.661242 ==DQ 1 ==
2512 12:17:32.663700 Final DQ duty delay cell = 0
2513 12:17:32.666990 [0] MAX Duty = 5124%(X100), DQS PI = 10
2514 12:17:32.670745 [0] MIN Duty = 4938%(X100), DQS PI = 62
2515 12:17:32.671283 [0] AVG Duty = 5031%(X100)
2516 12:17:32.673612
2517 12:17:32.676905 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2518 12:17:32.677339
2519 12:17:32.680425 CH1 DQ 1 Duty spec in!! Max-Min= 186%
2520 12:17:32.683249 [DutyScan_Calibration_Flow] ====Done====
2521 12:17:32.687078 nWR fixed to 30
2522 12:17:32.687632 [ModeRegInit_LP4] CH0 RK0
2523 12:17:32.690255 [ModeRegInit_LP4] CH0 RK1
2524 12:17:32.693237 [ModeRegInit_LP4] CH1 RK0
2525 12:17:32.696436 [ModeRegInit_LP4] CH1 RK1
2526 12:17:32.696903 match AC timing 7
2527 12:17:32.703467 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2528 12:17:32.706463 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2529 12:17:32.709700 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2530 12:17:32.716713 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2531 12:17:32.720011 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2532 12:17:32.720440 ==
2533 12:17:32.722946 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 12:17:32.727234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 12:17:32.727766 ==
2536 12:17:32.733206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2537 12:17:32.740040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2538 12:17:32.747039 [CA 0] Center 39 (9~70) winsize 62
2539 12:17:32.750644 [CA 1] Center 39 (9~69) winsize 61
2540 12:17:32.753805 [CA 2] Center 35 (5~66) winsize 62
2541 12:17:32.757026 [CA 3] Center 35 (4~66) winsize 63
2542 12:17:32.760922 [CA 4] Center 33 (4~63) winsize 60
2543 12:17:32.764297 [CA 5] Center 33 (4~63) winsize 60
2544 12:17:32.764954
2545 12:17:32.767071 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2546 12:17:32.767558
2547 12:17:32.770201 [CATrainingPosCal] consider 1 rank data
2548 12:17:32.773982 u2DelayCellTimex100 = 270/100 ps
2549 12:17:32.777162 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2550 12:17:32.783301 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2551 12:17:32.786832 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2552 12:17:32.790349 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2553 12:17:32.793455 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2554 12:17:32.796468 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2555 12:17:32.797006
2556 12:17:32.800298 CA PerBit enable=1, Macro0, CA PI delay=33
2557 12:17:32.800824
2558 12:17:32.803446 [CBTSetCACLKResult] CA Dly = 33
2559 12:17:32.803877 CS Dly: 8 (0~39)
2560 12:17:32.806741 ==
2561 12:17:32.809804 Dram Type= 6, Freq= 0, CH_0, rank 1
2562 12:17:32.813441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 12:17:32.813871 ==
2564 12:17:32.816602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2565 12:17:32.823028 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2566 12:17:32.833099 [CA 0] Center 39 (9~70) winsize 62
2567 12:17:32.836208 [CA 1] Center 39 (9~70) winsize 62
2568 12:17:32.839167 [CA 2] Center 35 (5~66) winsize 62
2569 12:17:32.842291 [CA 3] Center 34 (4~65) winsize 62
2570 12:17:32.845753 [CA 4] Center 33 (3~64) winsize 62
2571 12:17:32.848937 [CA 5] Center 33 (3~63) winsize 61
2572 12:17:32.849363
2573 12:17:32.852494 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2574 12:17:32.853225
2575 12:17:32.856053 [CATrainingPosCal] consider 2 rank data
2576 12:17:32.859376 u2DelayCellTimex100 = 270/100 ps
2577 12:17:32.862613 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2578 12:17:32.869058 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2579 12:17:32.872247 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2580 12:17:32.875973 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2581 12:17:32.878958 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2582 12:17:32.882136 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2583 12:17:32.882569
2584 12:17:32.885737 CA PerBit enable=1, Macro0, CA PI delay=33
2585 12:17:32.886180
2586 12:17:32.888789 [CBTSetCACLKResult] CA Dly = 33
2587 12:17:32.892351 CS Dly: 9 (0~41)
2588 12:17:32.892823
2589 12:17:32.895817 ----->DramcWriteLeveling(PI) begin...
2590 12:17:32.896280 ==
2591 12:17:32.899080 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 12:17:32.902019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 12:17:32.902453 ==
2594 12:17:32.905201 Write leveling (Byte 0): 31 => 31
2595 12:17:32.909077 Write leveling (Byte 1): 30 => 30
2596 12:17:32.912073 DramcWriteLeveling(PI) end<-----
2597 12:17:32.912511
2598 12:17:32.912892 ==
2599 12:17:32.915185 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 12:17:32.919083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 12:17:32.919519 ==
2602 12:17:32.922522 [Gating] SW mode calibration
2603 12:17:32.928406 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2604 12:17:32.934986 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2605 12:17:32.938747 0 15 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2606 12:17:32.941870 0 15 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2607 12:17:32.948924 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2608 12:17:32.951651 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 12:17:32.955134 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 12:17:32.961816 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 12:17:32.965106 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 12:17:32.968466 0 15 28 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
2613 12:17:32.975065 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
2614 12:17:32.978052 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2615 12:17:32.981721 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 12:17:32.988333 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 12:17:32.991493 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 12:17:32.994372 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 12:17:33.001602 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 12:17:33.004497 1 0 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2621 12:17:33.007691 1 1 0 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
2622 12:17:33.014568 1 1 4 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2623 12:17:33.017823 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 12:17:33.020974 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 12:17:33.028029 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 12:17:33.031135 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 12:17:33.034214 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 12:17:33.040588 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2629 12:17:33.044350 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2630 12:17:33.047526 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 12:17:33.054249 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 12:17:33.057142 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 12:17:33.060849 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 12:17:33.067147 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 12:17:33.070911 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 12:17:33.074049 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 12:17:33.080794 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 12:17:33.084028 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 12:17:33.087098 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 12:17:33.093837 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 12:17:33.096966 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 12:17:33.100106 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 12:17:33.106889 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 12:17:33.110550 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2645 12:17:33.113541 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2646 12:17:33.116937 Total UI for P1: 0, mck2ui 16
2647 12:17:33.120395 best dqsien dly found for B0: ( 1, 3, 28)
2648 12:17:33.126722 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2649 12:17:33.130453 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2650 12:17:33.133539 Total UI for P1: 0, mck2ui 16
2651 12:17:33.136687 best dqsien dly found for B1: ( 1, 4, 2)
2652 12:17:33.140164 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2653 12:17:33.143533 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2654 12:17:33.144074
2655 12:17:33.146478 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2656 12:17:33.150389 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2657 12:17:33.153415 [Gating] SW calibration Done
2658 12:17:33.153855 ==
2659 12:17:33.156391 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 12:17:33.159959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 12:17:33.160423 ==
2662 12:17:33.163050 RX Vref Scan: 0
2663 12:17:33.163484
2664 12:17:33.166582 RX Vref 0 -> 0, step: 1
2665 12:17:33.167020
2666 12:17:33.167446 RX Delay -40 -> 252, step: 8
2667 12:17:33.173354 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2668 12:17:33.176485 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2669 12:17:33.179591 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2670 12:17:33.182792 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2671 12:17:33.189636 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2672 12:17:33.192754 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2673 12:17:33.196772 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2674 12:17:33.199215 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2675 12:17:33.202892 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2676 12:17:33.206066 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2677 12:17:33.213045 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2678 12:17:33.215885 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2679 12:17:33.219192 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2680 12:17:33.222316 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2681 12:17:33.229259 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2682 12:17:33.232552 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2683 12:17:33.232992 ==
2684 12:17:33.235696 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 12:17:33.238917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 12:17:33.239373 ==
2687 12:17:33.242083 DQS Delay:
2688 12:17:33.242511 DQS0 = 0, DQS1 = 0
2689 12:17:33.242955 DQM Delay:
2690 12:17:33.245791 DQM0 = 119, DQM1 = 107
2691 12:17:33.246241 DQ Delay:
2692 12:17:33.249053 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2693 12:17:33.252279 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2694 12:17:33.255492 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2695 12:17:33.262278 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2696 12:17:33.262709
2697 12:17:33.263152
2698 12:17:33.263475 ==
2699 12:17:33.265214 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 12:17:33.268847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 12:17:33.269301 ==
2702 12:17:33.269639
2703 12:17:33.269953
2704 12:17:33.272553 TX Vref Scan disable
2705 12:17:33.272986 == TX Byte 0 ==
2706 12:17:33.279116 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2707 12:17:33.282197 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2708 12:17:33.282632 == TX Byte 1 ==
2709 12:17:33.289276 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2710 12:17:33.291909 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2711 12:17:33.292384 ==
2712 12:17:33.295503 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 12:17:33.298574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 12:17:33.299008 ==
2715 12:17:33.311569 TX Vref=22, minBit 2, minWin=25, winSum=417
2716 12:17:33.314595 TX Vref=24, minBit 1, minWin=25, winSum=425
2717 12:17:33.317996 TX Vref=26, minBit 4, minWin=26, winSum=429
2718 12:17:33.321386 TX Vref=28, minBit 5, minWin=26, winSum=429
2719 12:17:33.325222 TX Vref=30, minBit 5, minWin=26, winSum=428
2720 12:17:33.331661 TX Vref=32, minBit 1, minWin=26, winSum=426
2721 12:17:33.334582 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 26
2722 12:17:33.335024
2723 12:17:33.337644 Final TX Range 1 Vref 26
2724 12:17:33.338079
2725 12:17:33.338422 ==
2726 12:17:33.341500 Dram Type= 6, Freq= 0, CH_0, rank 0
2727 12:17:33.344629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2728 12:17:33.345065 ==
2729 12:17:33.347652
2730 12:17:33.348081
2731 12:17:33.348424 TX Vref Scan disable
2732 12:17:33.350874 == TX Byte 0 ==
2733 12:17:33.354669 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2734 12:17:33.361013 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2735 12:17:33.361447 == TX Byte 1 ==
2736 12:17:33.364321 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2737 12:17:33.371329 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2738 12:17:33.371768
2739 12:17:33.372123 [DATLAT]
2740 12:17:33.372449 Freq=1200, CH0 RK0
2741 12:17:33.372811
2742 12:17:33.374329 DATLAT Default: 0xd
2743 12:17:33.374819 0, 0xFFFF, sum = 0
2744 12:17:33.377360 1, 0xFFFF, sum = 0
2745 12:17:33.380916 2, 0xFFFF, sum = 0
2746 12:17:33.381357 3, 0xFFFF, sum = 0
2747 12:17:33.384446 4, 0xFFFF, sum = 0
2748 12:17:33.384930 5, 0xFFFF, sum = 0
2749 12:17:33.387629 6, 0xFFFF, sum = 0
2750 12:17:33.388061 7, 0xFFFF, sum = 0
2751 12:17:33.391318 8, 0xFFFF, sum = 0
2752 12:17:33.391783 9, 0xFFFF, sum = 0
2753 12:17:33.393916 10, 0xFFFF, sum = 0
2754 12:17:33.394344 11, 0xFFFF, sum = 0
2755 12:17:33.397648 12, 0x0, sum = 1
2756 12:17:33.398123 13, 0x0, sum = 2
2757 12:17:33.400885 14, 0x0, sum = 3
2758 12:17:33.401321 15, 0x0, sum = 4
2759 12:17:33.403912 best_step = 13
2760 12:17:33.404337
2761 12:17:33.404732 ==
2762 12:17:33.407903 Dram Type= 6, Freq= 0, CH_0, rank 0
2763 12:17:33.411030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2764 12:17:33.411560 ==
2765 12:17:33.411906 RX Vref Scan: 1
2766 12:17:33.413851
2767 12:17:33.414278 Set Vref Range= 32 -> 127
2768 12:17:33.414618
2769 12:17:33.417624 RX Vref 32 -> 127, step: 1
2770 12:17:33.418052
2771 12:17:33.420802 RX Delay -21 -> 252, step: 4
2772 12:17:33.421330
2773 12:17:33.424245 Set Vref, RX VrefLevel [Byte0]: 32
2774 12:17:33.427425 [Byte1]: 32
2775 12:17:33.427949
2776 12:17:33.430686 Set Vref, RX VrefLevel [Byte0]: 33
2777 12:17:33.434197 [Byte1]: 33
2778 12:17:33.437506
2779 12:17:33.438025 Set Vref, RX VrefLevel [Byte0]: 34
2780 12:17:33.441095 [Byte1]: 34
2781 12:17:33.445656
2782 12:17:33.446174 Set Vref, RX VrefLevel [Byte0]: 35
2783 12:17:33.448635 [Byte1]: 35
2784 12:17:33.453858
2785 12:17:33.454593 Set Vref, RX VrefLevel [Byte0]: 36
2786 12:17:33.456833 [Byte1]: 36
2787 12:17:33.461181
2788 12:17:33.461609 Set Vref, RX VrefLevel [Byte0]: 37
2789 12:17:33.464948 [Byte1]: 37
2790 12:17:33.469232
2791 12:17:33.469714 Set Vref, RX VrefLevel [Byte0]: 38
2792 12:17:33.472417 [Byte1]: 38
2793 12:17:33.477041
2794 12:17:33.477465 Set Vref, RX VrefLevel [Byte0]: 39
2795 12:17:33.480607 [Byte1]: 39
2796 12:17:33.484845
2797 12:17:33.485276 Set Vref, RX VrefLevel [Byte0]: 40
2798 12:17:33.488453 [Byte1]: 40
2799 12:17:33.492956
2800 12:17:33.493384 Set Vref, RX VrefLevel [Byte0]: 41
2801 12:17:33.496721 [Byte1]: 41
2802 12:17:33.501025
2803 12:17:33.501453 Set Vref, RX VrefLevel [Byte0]: 42
2804 12:17:33.504174 [Byte1]: 42
2805 12:17:33.509213
2806 12:17:33.509641 Set Vref, RX VrefLevel [Byte0]: 43
2807 12:17:33.512365 [Byte1]: 43
2808 12:17:33.516814
2809 12:17:33.517239 Set Vref, RX VrefLevel [Byte0]: 44
2810 12:17:33.520191 [Byte1]: 44
2811 12:17:33.525070
2812 12:17:33.525501 Set Vref, RX VrefLevel [Byte0]: 45
2813 12:17:33.528352 [Byte1]: 45
2814 12:17:33.533145
2815 12:17:33.533676 Set Vref, RX VrefLevel [Byte0]: 46
2816 12:17:33.536180 [Byte1]: 46
2817 12:17:33.540666
2818 12:17:33.541177 Set Vref, RX VrefLevel [Byte0]: 47
2819 12:17:33.543841 [Byte1]: 47
2820 12:17:33.548825
2821 12:17:33.549264 Set Vref, RX VrefLevel [Byte0]: 48
2822 12:17:33.551989 [Byte1]: 48
2823 12:17:33.556560
2824 12:17:33.557080 Set Vref, RX VrefLevel [Byte0]: 49
2825 12:17:33.559591 [Byte1]: 49
2826 12:17:33.564723
2827 12:17:33.565147 Set Vref, RX VrefLevel [Byte0]: 50
2828 12:17:33.567969 [Byte1]: 50
2829 12:17:33.572028
2830 12:17:33.572500 Set Vref, RX VrefLevel [Byte0]: 51
2831 12:17:33.575733 [Byte1]: 51
2832 12:17:33.580549
2833 12:17:33.581157 Set Vref, RX VrefLevel [Byte0]: 52
2834 12:17:33.583576 [Byte1]: 52
2835 12:17:33.588121
2836 12:17:33.588608 Set Vref, RX VrefLevel [Byte0]: 53
2837 12:17:33.591684 [Byte1]: 53
2838 12:17:33.596053
2839 12:17:33.596478 Set Vref, RX VrefLevel [Byte0]: 54
2840 12:17:33.599743 [Byte1]: 54
2841 12:17:33.603944
2842 12:17:33.604372 Set Vref, RX VrefLevel [Byte0]: 55
2843 12:17:33.607136 [Byte1]: 55
2844 12:17:33.612027
2845 12:17:33.612454 Set Vref, RX VrefLevel [Byte0]: 56
2846 12:17:33.615177 [Byte1]: 56
2847 12:17:33.620188
2848 12:17:33.620704 Set Vref, RX VrefLevel [Byte0]: 57
2849 12:17:33.623330 [Byte1]: 57
2850 12:17:33.628278
2851 12:17:33.628844 Set Vref, RX VrefLevel [Byte0]: 58
2852 12:17:33.631470 [Byte1]: 58
2853 12:17:33.636006
2854 12:17:33.636437 Set Vref, RX VrefLevel [Byte0]: 59
2855 12:17:33.639192 [Byte1]: 59
2856 12:17:33.643552
2857 12:17:33.644074 Set Vref, RX VrefLevel [Byte0]: 60
2858 12:17:33.647262 [Byte1]: 60
2859 12:17:33.651709
2860 12:17:33.652243 Set Vref, RX VrefLevel [Byte0]: 61
2861 12:17:33.655106 [Byte1]: 61
2862 12:17:33.659574
2863 12:17:33.660196 Set Vref, RX VrefLevel [Byte0]: 62
2864 12:17:33.663210 [Byte1]: 62
2865 12:17:33.667400
2866 12:17:33.667873 Set Vref, RX VrefLevel [Byte0]: 63
2867 12:17:33.670861 [Byte1]: 63
2868 12:17:33.675608
2869 12:17:33.676036 Set Vref, RX VrefLevel [Byte0]: 64
2870 12:17:33.678663 [Byte1]: 64
2871 12:17:33.683605
2872 12:17:33.684082 Set Vref, RX VrefLevel [Byte0]: 65
2873 12:17:33.686354 [Byte1]: 65
2874 12:17:33.691285
2875 12:17:33.691859 Set Vref, RX VrefLevel [Byte0]: 66
2876 12:17:33.694915 [Byte1]: 66
2877 12:17:33.698847
2878 12:17:33.699277 Set Vref, RX VrefLevel [Byte0]: 67
2879 12:17:33.702420 [Byte1]: 67
2880 12:17:33.707658
2881 12:17:33.708226 Set Vref, RX VrefLevel [Byte0]: 68
2882 12:17:33.710779 [Byte1]: 68
2883 12:17:33.715236
2884 12:17:33.715780 Set Vref, RX VrefLevel [Byte0]: 69
2885 12:17:33.718119 [Byte1]: 69
2886 12:17:33.723107
2887 12:17:33.723538 Set Vref, RX VrefLevel [Byte0]: 70
2888 12:17:33.726129 [Byte1]: 70
2889 12:17:33.731030
2890 12:17:33.731563 Set Vref, RX VrefLevel [Byte0]: 71
2891 12:17:33.733991 [Byte1]: 71
2892 12:17:33.739084
2893 12:17:33.739608 Set Vref, RX VrefLevel [Byte0]: 72
2894 12:17:33.741943 [Byte1]: 72
2895 12:17:33.747104
2896 12:17:33.747531 Set Vref, RX VrefLevel [Byte0]: 73
2897 12:17:33.750578 [Byte1]: 73
2898 12:17:33.754833
2899 12:17:33.755365 Set Vref, RX VrefLevel [Byte0]: 74
2900 12:17:33.757901 [Byte1]: 74
2901 12:17:33.762740
2902 12:17:33.763270 Set Vref, RX VrefLevel [Byte0]: 75
2903 12:17:33.766228 [Byte1]: 75
2904 12:17:33.770808
2905 12:17:33.771342 Set Vref, RX VrefLevel [Byte0]: 76
2906 12:17:33.773897 [Byte1]: 76
2907 12:17:33.778690
2908 12:17:33.779118 Set Vref, RX VrefLevel [Byte0]: 77
2909 12:17:33.781843 [Byte1]: 77
2910 12:17:33.786178
2911 12:17:33.786604 Final RX Vref Byte 0 = 61 to rank0
2912 12:17:33.789928 Final RX Vref Byte 1 = 55 to rank0
2913 12:17:33.793368 Final RX Vref Byte 0 = 61 to rank1
2914 12:17:33.796286 Final RX Vref Byte 1 = 55 to rank1==
2915 12:17:33.799499 Dram Type= 6, Freq= 0, CH_0, rank 0
2916 12:17:33.806508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 12:17:33.806958 ==
2918 12:17:33.807322 DQS Delay:
2919 12:17:33.809123 DQS0 = 0, DQS1 = 0
2920 12:17:33.809573 DQM Delay:
2921 12:17:33.809923 DQM0 = 118, DQM1 = 107
2922 12:17:33.812777 DQ Delay:
2923 12:17:33.816484 DQ0 =116, DQ1 =118, DQ2 =114, DQ3 =116
2924 12:17:33.819752 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2925 12:17:33.822853 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =100
2926 12:17:33.826069 DQ12 =114, DQ13 =112, DQ14 =120, DQ15 =116
2927 12:17:33.826497
2928 12:17:33.826831
2929 12:17:33.833241 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 405 ps
2930 12:17:33.836224 CH0 RK0: MR19=403, MR18=DF8
2931 12:17:33.843111 CH0_RK0: MR19=0x403, MR18=0xDF8, DQSOSC=405, MR23=63, INC=39, DEC=26
2932 12:17:33.843649
2933 12:17:33.846000 ----->DramcWriteLeveling(PI) begin...
2934 12:17:33.846434 ==
2935 12:17:33.849652 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 12:17:33.853051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 12:17:33.855729 ==
2938 12:17:33.856165 Write leveling (Byte 0): 33 => 33
2939 12:17:33.858971 Write leveling (Byte 1): 31 => 31
2940 12:17:33.862988 DramcWriteLeveling(PI) end<-----
2941 12:17:33.864126
2942 12:17:33.865081 ==
2943 12:17:33.865908 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 12:17:33.872832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 12:17:33.873260 ==
2946 12:17:33.875912 [Gating] SW mode calibration
2947 12:17:33.882857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2948 12:17:33.885779 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2949 12:17:33.892622 0 15 0 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
2950 12:17:33.895602 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2951 12:17:33.899266 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2952 12:17:33.905785 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 12:17:33.908748 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 12:17:33.912048 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 12:17:33.919189 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2956 12:17:33.922234 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
2957 12:17:33.925343 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2958 12:17:33.929165 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 12:17:33.935444 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 12:17:33.938694 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 12:17:33.942363 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 12:17:33.949309 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 12:17:33.952197 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 12:17:33.955257 1 0 28 | B1->B0 | 2727 3939 | 0 0 | (0 0) (0 0)
2965 12:17:33.962328 1 1 0 | B1->B0 | 3232 4646 | 0 0 | (1 1) (0 0)
2966 12:17:33.965251 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 12:17:33.968391 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 12:17:33.975293 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 12:17:33.978355 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 12:17:33.981556 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 12:17:33.988359 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2972 12:17:33.991566 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2973 12:17:33.994687 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2974 12:17:34.001566 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 12:17:34.004614 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 12:17:34.008229 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 12:17:34.014826 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 12:17:34.017750 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 12:17:34.021362 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 12:17:34.027991 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 12:17:34.031030 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 12:17:34.034120 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 12:17:34.041246 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 12:17:34.044344 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 12:17:34.047465 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 12:17:34.054057 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 12:17:34.057671 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2988 12:17:34.060797 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2989 12:17:34.067799 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2990 12:17:34.067872 Total UI for P1: 0, mck2ui 16
2991 12:17:34.070894 best dqsien dly found for B0: ( 1, 3, 26)
2992 12:17:34.077609 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2993 12:17:34.080925 Total UI for P1: 0, mck2ui 16
2994 12:17:34.084681 best dqsien dly found for B1: ( 1, 4, 0)
2995 12:17:34.087859 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2996 12:17:34.091001 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2997 12:17:34.091084
2998 12:17:34.094105 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2999 12:17:34.097313 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3000 12:17:34.100961 [Gating] SW calibration Done
3001 12:17:34.101045 ==
3002 12:17:34.103969 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 12:17:34.107573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 12:17:34.107657 ==
3005 12:17:34.110501 RX Vref Scan: 0
3006 12:17:34.110584
3007 12:17:34.114063 RX Vref 0 -> 0, step: 1
3008 12:17:34.114191
3009 12:17:34.114258 RX Delay -40 -> 252, step: 8
3010 12:17:34.120592 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3011 12:17:34.123700 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3012 12:17:34.127172 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3013 12:17:34.130319 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3014 12:17:34.133512 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3015 12:17:34.140362 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3016 12:17:34.143560 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3017 12:17:34.147414 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3018 12:17:34.150617 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3019 12:17:34.153694 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3020 12:17:34.160380 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3021 12:17:34.163517 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3022 12:17:34.166696 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3023 12:17:34.170518 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3024 12:17:34.173653 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3025 12:17:34.179915 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3026 12:17:34.179999 ==
3027 12:17:34.183675 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 12:17:34.186902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 12:17:34.186987 ==
3030 12:17:34.187054 DQS Delay:
3031 12:17:34.190026 DQS0 = 0, DQS1 = 0
3032 12:17:34.190109 DQM Delay:
3033 12:17:34.193270 DQM0 = 116, DQM1 = 108
3034 12:17:34.193353 DQ Delay:
3035 12:17:34.196497 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3036 12:17:34.200323 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3037 12:17:34.203425 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3038 12:17:34.206963 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
3039 12:17:34.207046
3040 12:17:34.210040
3041 12:17:34.210123 ==
3042 12:17:34.213036 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 12:17:34.216769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 12:17:34.216853 ==
3045 12:17:34.216919
3046 12:17:34.216980
3047 12:17:34.220437 TX Vref Scan disable
3048 12:17:34.220564 == TX Byte 0 ==
3049 12:17:34.226396 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3050 12:17:34.229904 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3051 12:17:34.229988 == TX Byte 1 ==
3052 12:17:34.236486 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3053 12:17:34.239682 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3054 12:17:34.239766 ==
3055 12:17:34.243444 Dram Type= 6, Freq= 0, CH_0, rank 1
3056 12:17:34.246707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 12:17:34.246791 ==
3058 12:17:34.259294 TX Vref=22, minBit 1, minWin=26, winSum=421
3059 12:17:34.262342 TX Vref=24, minBit 1, minWin=26, winSum=423
3060 12:17:34.265916 TX Vref=26, minBit 1, minWin=26, winSum=430
3061 12:17:34.269082 TX Vref=28, minBit 1, minWin=26, winSum=430
3062 12:17:34.272099 TX Vref=30, minBit 10, minWin=26, winSum=429
3063 12:17:34.278887 TX Vref=32, minBit 12, minWin=25, winSum=426
3064 12:17:34.281949 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 26
3065 12:17:34.282046
3066 12:17:34.285715 Final TX Range 1 Vref 26
3067 12:17:34.285799
3068 12:17:34.285866 ==
3069 12:17:34.288796 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 12:17:34.292459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 12:17:34.295569 ==
3072 12:17:34.295661
3073 12:17:34.295727
3074 12:17:34.295824 TX Vref Scan disable
3075 12:17:34.298725 == TX Byte 0 ==
3076 12:17:34.302670 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3077 12:17:34.308895 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3078 12:17:34.309021 == TX Byte 1 ==
3079 12:17:34.312051 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3080 12:17:34.319007 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3081 12:17:34.319093
3082 12:17:34.319160 [DATLAT]
3083 12:17:34.319223 Freq=1200, CH0 RK1
3084 12:17:34.319283
3085 12:17:34.321965 DATLAT Default: 0xd
3086 12:17:34.322050 0, 0xFFFF, sum = 0
3087 12:17:34.325707 1, 0xFFFF, sum = 0
3088 12:17:34.325794 2, 0xFFFF, sum = 0
3089 12:17:34.328636 3, 0xFFFF, sum = 0
3090 12:17:34.332165 4, 0xFFFF, sum = 0
3091 12:17:34.332252 5, 0xFFFF, sum = 0
3092 12:17:34.335119 6, 0xFFFF, sum = 0
3093 12:17:34.335206 7, 0xFFFF, sum = 0
3094 12:17:34.338603 8, 0xFFFF, sum = 0
3095 12:17:34.338690 9, 0xFFFF, sum = 0
3096 12:17:34.341764 10, 0xFFFF, sum = 0
3097 12:17:34.341852 11, 0xFFFF, sum = 0
3098 12:17:34.345602 12, 0x0, sum = 1
3099 12:17:34.345689 13, 0x0, sum = 2
3100 12:17:34.348788 14, 0x0, sum = 3
3101 12:17:34.348875 15, 0x0, sum = 4
3102 12:17:34.351867 best_step = 13
3103 12:17:34.351953
3104 12:17:34.352021 ==
3105 12:17:34.355619 Dram Type= 6, Freq= 0, CH_0, rank 1
3106 12:17:34.358800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 12:17:34.358879 ==
3108 12:17:34.358946 RX Vref Scan: 0
3109 12:17:34.359008
3110 12:17:34.361888 RX Vref 0 -> 0, step: 1
3111 12:17:34.361973
3112 12:17:34.365023 RX Delay -21 -> 252, step: 4
3113 12:17:34.368519 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3114 12:17:34.375335 iDelay=199, Bit 1, Center 120 (47 ~ 194) 148
3115 12:17:34.378470 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3116 12:17:34.381713 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3117 12:17:34.385455 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3118 12:17:34.388509 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3119 12:17:34.394917 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3120 12:17:34.398627 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3121 12:17:34.401738 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3122 12:17:34.404846 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3123 12:17:34.408066 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3124 12:17:34.415064 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3125 12:17:34.418125 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3126 12:17:34.421725 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3127 12:17:34.425291 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3128 12:17:34.431416 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3129 12:17:34.431502 ==
3130 12:17:34.435049 Dram Type= 6, Freq= 0, CH_0, rank 1
3131 12:17:34.437980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 12:17:34.438067 ==
3133 12:17:34.438135 DQS Delay:
3134 12:17:34.441551 DQS0 = 0, DQS1 = 0
3135 12:17:34.441636 DQM Delay:
3136 12:17:34.445145 DQM0 = 116, DQM1 = 108
3137 12:17:34.445230 DQ Delay:
3138 12:17:34.448353 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =114
3139 12:17:34.451548 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3140 12:17:34.454669 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3141 12:17:34.458484 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =116
3142 12:17:34.458570
3143 12:17:34.458638
3144 12:17:34.467921 [DQSOSCAuto] RK1, (LSB)MR18= 0x9e3, (MSB)MR19= 0x403, tDQSOscB0 = 422 ps tDQSOscB1 = 406 ps
3145 12:17:34.471647 CH0 RK1: MR19=403, MR18=9E3
3146 12:17:34.474583 CH0_RK1: MR19=0x403, MR18=0x9E3, DQSOSC=406, MR23=63, INC=39, DEC=26
3147 12:17:34.477749 [RxdqsGatingPostProcess] freq 1200
3148 12:17:34.484744 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3149 12:17:34.487876 best DQS0 dly(2T, 0.5T) = (0, 11)
3150 12:17:34.491033 best DQS1 dly(2T, 0.5T) = (0, 12)
3151 12:17:34.494145 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3152 12:17:34.497927 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3153 12:17:34.501132 best DQS0 dly(2T, 0.5T) = (0, 11)
3154 12:17:34.504119 best DQS1 dly(2T, 0.5T) = (0, 12)
3155 12:17:34.507960 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3156 12:17:34.511243 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3157 12:17:34.511363 Pre-setting of DQS Precalculation
3158 12:17:34.517632 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3159 12:17:34.517744 ==
3160 12:17:34.520734 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 12:17:34.524315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 12:17:34.524417 ==
3163 12:17:34.530978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3164 12:17:34.537617 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3165 12:17:34.544890 [CA 0] Center 37 (7~67) winsize 61
3166 12:17:34.548630 [CA 1] Center 37 (7~68) winsize 62
3167 12:17:34.551725 [CA 2] Center 34 (4~64) winsize 61
3168 12:17:34.554968 [CA 3] Center 33 (3~64) winsize 62
3169 12:17:34.558263 [CA 4] Center 34 (4~64) winsize 61
3170 12:17:34.561684 [CA 5] Center 33 (3~64) winsize 62
3171 12:17:34.561877
3172 12:17:34.564658 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3173 12:17:34.564826
3174 12:17:34.568465 [CATrainingPosCal] consider 1 rank data
3175 12:17:34.571886 u2DelayCellTimex100 = 270/100 ps
3176 12:17:34.574846 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3177 12:17:34.581745 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3178 12:17:34.584725 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3179 12:17:34.588406 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3180 12:17:34.591490 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3181 12:17:34.594912 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3182 12:17:34.595249
3183 12:17:34.598105 CA PerBit enable=1, Macro0, CA PI delay=33
3184 12:17:34.598542
3185 12:17:34.601505 [CBTSetCACLKResult] CA Dly = 33
3186 12:17:34.605215 CS Dly: 6 (0~37)
3187 12:17:34.605657 ==
3188 12:17:34.608505 Dram Type= 6, Freq= 0, CH_1, rank 1
3189 12:17:34.611953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 12:17:34.612482 ==
3191 12:17:34.617835 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3192 12:17:34.621566 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3193 12:17:34.630666 [CA 0] Center 37 (7~68) winsize 62
3194 12:17:34.634486 [CA 1] Center 38 (8~68) winsize 61
3195 12:17:34.637462 [CA 2] Center 34 (4~65) winsize 62
3196 12:17:34.641251 [CA 3] Center 33 (3~64) winsize 62
3197 12:17:34.644183 [CA 4] Center 34 (4~65) winsize 62
3198 12:17:34.647779 [CA 5] Center 33 (3~64) winsize 62
3199 12:17:34.648216
3200 12:17:34.650780 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3201 12:17:34.651213
3202 12:17:34.654446 [CATrainingPosCal] consider 2 rank data
3203 12:17:34.657570 u2DelayCellTimex100 = 270/100 ps
3204 12:17:34.660644 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3205 12:17:34.667530 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3206 12:17:34.670596 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3207 12:17:34.673893 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3208 12:17:34.677573 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3209 12:17:34.680804 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3210 12:17:34.681274
3211 12:17:34.683722 CA PerBit enable=1, Macro0, CA PI delay=33
3212 12:17:34.684302
3213 12:17:34.687356 [CBTSetCACLKResult] CA Dly = 33
3214 12:17:34.690596 CS Dly: 7 (0~40)
3215 12:17:34.691040
3216 12:17:34.693660 ----->DramcWriteLeveling(PI) begin...
3217 12:17:34.694093 ==
3218 12:17:34.697493 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 12:17:34.700610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 12:17:34.701042 ==
3221 12:17:34.703784 Write leveling (Byte 0): 25 => 25
3222 12:17:34.707088 Write leveling (Byte 1): 27 => 27
3223 12:17:34.710295 DramcWriteLeveling(PI) end<-----
3224 12:17:34.710719
3225 12:17:34.711058 ==
3226 12:17:34.713421 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 12:17:34.717321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 12:17:34.717746 ==
3229 12:17:34.719912 [Gating] SW mode calibration
3230 12:17:34.726743 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3231 12:17:34.733538 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3232 12:17:34.737035 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3233 12:17:34.740111 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3234 12:17:34.746335 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3235 12:17:34.750120 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3236 12:17:34.753034 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3237 12:17:34.759401 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3238 12:17:34.763132 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3239 12:17:34.766292 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
3240 12:17:34.773057 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3241 12:17:34.776429 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3242 12:17:34.779648 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3243 12:17:34.785793 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3244 12:17:34.789385 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3245 12:17:34.792559 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3246 12:17:34.799442 1 0 24 | B1->B0 | 2626 3c3c | 0 0 | (0 0) (0 0)
3247 12:17:34.802673 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3248 12:17:34.806147 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 12:17:34.812090 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3250 12:17:34.816066 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3251 12:17:34.819022 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 12:17:34.825464 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3253 12:17:34.829135 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 12:17:34.832274 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3255 12:17:34.838942 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3256 12:17:34.842415 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 12:17:34.845467 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 12:17:34.852617 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 12:17:34.855606 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 12:17:34.859145 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 12:17:34.865781 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 12:17:34.868981 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 12:17:34.872235 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 12:17:34.879049 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 12:17:34.881982 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 12:17:34.885751 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 12:17:34.891955 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 12:17:34.895386 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 12:17:34.898500 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 12:17:34.905208 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3271 12:17:34.908277 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3272 12:17:34.912063 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 12:17:34.915427 Total UI for P1: 0, mck2ui 16
3274 12:17:34.918659 best dqsien dly found for B0: ( 1, 3, 26)
3275 12:17:34.921682 Total UI for P1: 0, mck2ui 16
3276 12:17:34.924793 best dqsien dly found for B1: ( 1, 3, 26)
3277 12:17:34.927967 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3278 12:17:34.931008 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3279 12:17:34.931097
3280 12:17:34.938008 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3281 12:17:34.941622 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3282 12:17:34.942077 [Gating] SW calibration Done
3283 12:17:34.944966 ==
3284 12:17:34.947835 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 12:17:34.951496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 12:17:34.951965 ==
3287 12:17:34.952339 RX Vref Scan: 0
3288 12:17:34.952718
3289 12:17:34.955023 RX Vref 0 -> 0, step: 1
3290 12:17:34.955473
3291 12:17:34.957846 RX Delay -40 -> 252, step: 8
3292 12:17:34.961338 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3293 12:17:34.964867 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3294 12:17:34.968173 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3295 12:17:34.975104 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3296 12:17:34.978326 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3297 12:17:34.981457 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3298 12:17:34.984442 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3299 12:17:34.987830 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3300 12:17:34.994749 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3301 12:17:34.997886 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3302 12:17:35.001356 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3303 12:17:35.004557 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3304 12:17:35.007883 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3305 12:17:35.014472 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3306 12:17:35.018195 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3307 12:17:35.021426 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3308 12:17:35.021927 ==
3309 12:17:35.024704 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 12:17:35.027915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 12:17:35.028354 ==
3312 12:17:35.031088 DQS Delay:
3313 12:17:35.031522 DQS0 = 0, DQS1 = 0
3314 12:17:35.034251 DQM Delay:
3315 12:17:35.034689 DQM0 = 117, DQM1 = 109
3316 12:17:35.037955 DQ Delay:
3317 12:17:35.041029 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3318 12:17:35.044593 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3319 12:17:35.047706 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3320 12:17:35.050838 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3321 12:17:35.051364
3322 12:17:35.051746
3323 12:17:35.052177 ==
3324 12:17:35.054321 Dram Type= 6, Freq= 0, CH_1, rank 0
3325 12:17:35.057498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3326 12:17:35.057933 ==
3327 12:17:35.058280
3328 12:17:35.058602
3329 12:17:35.061093 TX Vref Scan disable
3330 12:17:35.064042 == TX Byte 0 ==
3331 12:17:35.067567 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3332 12:17:35.071025 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3333 12:17:35.074377 == TX Byte 1 ==
3334 12:17:35.077641 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3335 12:17:35.080674 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3336 12:17:35.081102 ==
3337 12:17:35.083950 Dram Type= 6, Freq= 0, CH_1, rank 0
3338 12:17:35.087677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3339 12:17:35.090822 ==
3340 12:17:35.100908 TX Vref=22, minBit 8, minWin=25, winSum=419
3341 12:17:35.104337 TX Vref=24, minBit 10, minWin=25, winSum=428
3342 12:17:35.107500 TX Vref=26, minBit 9, minWin=25, winSum=429
3343 12:17:35.110647 TX Vref=28, minBit 10, minWin=26, winSum=436
3344 12:17:35.114360 TX Vref=30, minBit 8, minWin=26, winSum=435
3345 12:17:35.120723 TX Vref=32, minBit 9, minWin=26, winSum=430
3346 12:17:35.123903 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 28
3347 12:17:35.124332
3348 12:17:35.127741 Final TX Range 1 Vref 28
3349 12:17:35.128172
3350 12:17:35.128513 ==
3351 12:17:35.130890 Dram Type= 6, Freq= 0, CH_1, rank 0
3352 12:17:35.133947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3353 12:17:35.136953 ==
3354 12:17:35.137380
3355 12:17:35.137717
3356 12:17:35.138027 TX Vref Scan disable
3357 12:17:35.140812 == TX Byte 0 ==
3358 12:17:35.143933 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3359 12:17:35.147553 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3360 12:17:35.150717 == TX Byte 1 ==
3361 12:17:35.154333 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3362 12:17:35.157509 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3363 12:17:35.161040
3364 12:17:35.161458 [DATLAT]
3365 12:17:35.161789 Freq=1200, CH1 RK0
3366 12:17:35.162097
3367 12:17:35.164108 DATLAT Default: 0xd
3368 12:17:35.164560 0, 0xFFFF, sum = 0
3369 12:17:35.167231 1, 0xFFFF, sum = 0
3370 12:17:35.167491 2, 0xFFFF, sum = 0
3371 12:17:35.170817 3, 0xFFFF, sum = 0
3372 12:17:35.171145 4, 0xFFFF, sum = 0
3373 12:17:35.174005 5, 0xFFFF, sum = 0
3374 12:17:35.177594 6, 0xFFFF, sum = 0
3375 12:17:35.178023 7, 0xFFFF, sum = 0
3376 12:17:35.180466 8, 0xFFFF, sum = 0
3377 12:17:35.180828 9, 0xFFFF, sum = 0
3378 12:17:35.184192 10, 0xFFFF, sum = 0
3379 12:17:35.184645 11, 0xFFFF, sum = 0
3380 12:17:35.187130 12, 0x0, sum = 1
3381 12:17:35.187480 13, 0x0, sum = 2
3382 12:17:35.191028 14, 0x0, sum = 3
3383 12:17:35.191439 15, 0x0, sum = 4
3384 12:17:35.191701 best_step = 13
3385 12:17:35.191939
3386 12:17:35.194258 ==
3387 12:17:35.197391 Dram Type= 6, Freq= 0, CH_1, rank 0
3388 12:17:35.200387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3389 12:17:35.200726 ==
3390 12:17:35.200980 RX Vref Scan: 1
3391 12:17:35.201252
3392 12:17:35.204285 Set Vref Range= 32 -> 127
3393 12:17:35.204679
3394 12:17:35.207075 RX Vref 32 -> 127, step: 1
3395 12:17:35.207402
3396 12:17:35.210844 RX Delay -21 -> 252, step: 4
3397 12:17:35.211283
3398 12:17:35.213816 Set Vref, RX VrefLevel [Byte0]: 32
3399 12:17:35.217100 [Byte1]: 32
3400 12:17:35.217648
3401 12:17:35.220817 Set Vref, RX VrefLevel [Byte0]: 33
3402 12:17:35.224016 [Byte1]: 33
3403 12:17:35.227472
3404 12:17:35.227991 Set Vref, RX VrefLevel [Byte0]: 34
3405 12:17:35.230801 [Byte1]: 34
3406 12:17:35.235652
3407 12:17:35.236174 Set Vref, RX VrefLevel [Byte0]: 35
3408 12:17:35.238535 [Byte1]: 35
3409 12:17:35.242989
3410 12:17:35.243406 Set Vref, RX VrefLevel [Byte0]: 36
3411 12:17:35.246179 [Byte1]: 36
3412 12:17:35.251318
3413 12:17:35.251735 Set Vref, RX VrefLevel [Byte0]: 37
3414 12:17:35.254445 [Byte1]: 37
3415 12:17:35.259131
3416 12:17:35.259663 Set Vref, RX VrefLevel [Byte0]: 38
3417 12:17:35.262016 [Byte1]: 38
3418 12:17:35.266976
3419 12:17:35.267396 Set Vref, RX VrefLevel [Byte0]: 39
3420 12:17:35.270602 [Byte1]: 39
3421 12:17:35.274850
3422 12:17:35.275267 Set Vref, RX VrefLevel [Byte0]: 40
3423 12:17:35.278439 [Byte1]: 40
3424 12:17:35.282587
3425 12:17:35.283018 Set Vref, RX VrefLevel [Byte0]: 41
3426 12:17:35.286148 [Byte1]: 41
3427 12:17:35.290312
3428 12:17:35.290735 Set Vref, RX VrefLevel [Byte0]: 42
3429 12:17:35.294143 [Byte1]: 42
3430 12:17:35.298721
3431 12:17:35.299145 Set Vref, RX VrefLevel [Byte0]: 43
3432 12:17:35.301849 [Byte1]: 43
3433 12:17:35.306549
3434 12:17:35.306972 Set Vref, RX VrefLevel [Byte0]: 44
3435 12:17:35.309656 [Byte1]: 44
3436 12:17:35.314361
3437 12:17:35.317708 Set Vref, RX VrefLevel [Byte0]: 45
3438 12:17:35.320893 [Byte1]: 45
3439 12:17:35.321327
3440 12:17:35.324490 Set Vref, RX VrefLevel [Byte0]: 46
3441 12:17:35.327986 [Byte1]: 46
3442 12:17:35.328563
3443 12:17:35.330874 Set Vref, RX VrefLevel [Byte0]: 47
3444 12:17:35.334085 [Byte1]: 47
3445 12:17:35.338464
3446 12:17:35.338897 Set Vref, RX VrefLevel [Byte0]: 48
3447 12:17:35.341573 [Byte1]: 48
3448 12:17:35.346092
3449 12:17:35.346527 Set Vref, RX VrefLevel [Byte0]: 49
3450 12:17:35.349190 [Byte1]: 49
3451 12:17:35.354551
3452 12:17:35.355088 Set Vref, RX VrefLevel [Byte0]: 50
3453 12:17:35.357208 [Byte1]: 50
3454 12:17:35.362282
3455 12:17:35.362731 Set Vref, RX VrefLevel [Byte0]: 51
3456 12:17:35.365151 [Byte1]: 51
3457 12:17:35.370348
3458 12:17:35.370780 Set Vref, RX VrefLevel [Byte0]: 52
3459 12:17:35.373219 [Byte1]: 52
3460 12:17:35.378051
3461 12:17:35.378533 Set Vref, RX VrefLevel [Byte0]: 53
3462 12:17:35.381066 [Byte1]: 53
3463 12:17:35.385744
3464 12:17:35.386376 Set Vref, RX VrefLevel [Byte0]: 54
3465 12:17:35.388638 [Byte1]: 54
3466 12:17:35.393522
3467 12:17:35.393956 Set Vref, RX VrefLevel [Byte0]: 55
3468 12:17:35.396794 [Byte1]: 55
3469 12:17:35.401415
3470 12:17:35.401873 Set Vref, RX VrefLevel [Byte0]: 56
3471 12:17:35.404459 [Byte1]: 56
3472 12:17:35.409521
3473 12:17:35.409980 Set Vref, RX VrefLevel [Byte0]: 57
3474 12:17:35.412852 [Byte1]: 57
3475 12:17:35.417041
3476 12:17:35.417483 Set Vref, RX VrefLevel [Byte0]: 58
3477 12:17:35.420505 [Byte1]: 58
3478 12:17:35.425169
3479 12:17:35.425596 Set Vref, RX VrefLevel [Byte0]: 59
3480 12:17:35.428367 [Byte1]: 59
3481 12:17:35.433394
3482 12:17:35.433832 Set Vref, RX VrefLevel [Byte0]: 60
3483 12:17:35.436571 [Byte1]: 60
3484 12:17:35.441116
3485 12:17:35.441542 Set Vref, RX VrefLevel [Byte0]: 61
3486 12:17:35.444280 [Byte1]: 61
3487 12:17:35.449394
3488 12:17:35.449922 Set Vref, RX VrefLevel [Byte0]: 62
3489 12:17:35.452432 [Byte1]: 62
3490 12:17:35.456748
3491 12:17:35.457212 Set Vref, RX VrefLevel [Byte0]: 63
3492 12:17:35.460044 [Byte1]: 63
3493 12:17:35.465183
3494 12:17:35.465705 Set Vref, RX VrefLevel [Byte0]: 64
3495 12:17:35.468108 [Byte1]: 64
3496 12:17:35.473020
3497 12:17:35.473582 Set Vref, RX VrefLevel [Byte0]: 65
3498 12:17:35.476096 [Byte1]: 65
3499 12:17:35.480469
3500 12:17:35.481049 Set Vref, RX VrefLevel [Byte0]: 66
3501 12:17:35.484189 [Byte1]: 66
3502 12:17:35.488511
3503 12:17:35.489128 Set Vref, RX VrefLevel [Byte0]: 67
3504 12:17:35.491945 [Byte1]: 67
3505 12:17:35.496789
3506 12:17:35.497212 Set Vref, RX VrefLevel [Byte0]: 68
3507 12:17:35.499862 [Byte1]: 68
3508 12:17:35.504282
3509 12:17:35.504814 Final RX Vref Byte 0 = 51 to rank0
3510 12:17:35.508139 Final RX Vref Byte 1 = 51 to rank0
3511 12:17:35.511224 Final RX Vref Byte 0 = 51 to rank1
3512 12:17:35.514571 Final RX Vref Byte 1 = 51 to rank1==
3513 12:17:35.517577 Dram Type= 6, Freq= 0, CH_1, rank 0
3514 12:17:35.524297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 12:17:35.524805 ==
3516 12:17:35.525244 DQS Delay:
3517 12:17:35.527613 DQS0 = 0, DQS1 = 0
3518 12:17:35.528148 DQM Delay:
3519 12:17:35.528689 DQM0 = 116, DQM1 = 110
3520 12:17:35.530679 DQ Delay:
3521 12:17:35.534496 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =112
3522 12:17:35.537573 DQ4 =114, DQ5 =126, DQ6 =124, DQ7 =112
3523 12:17:35.540916 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =100
3524 12:17:35.544043 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3525 12:17:35.544478
3526 12:17:35.544944
3527 12:17:35.553839 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3528 12:17:35.554369 CH1 RK0: MR19=403, MR18=5F8
3529 12:17:35.560593 CH1_RK0: MR19=0x403, MR18=0x5F8, DQSOSC=408, MR23=63, INC=39, DEC=26
3530 12:17:35.561037
3531 12:17:35.563657 ----->DramcWriteLeveling(PI) begin...
3532 12:17:35.564091 ==
3533 12:17:35.566768 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 12:17:35.573970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 12:17:35.574403 ==
3536 12:17:35.576856 Write leveling (Byte 0): 25 => 25
3537 12:17:35.577330 Write leveling (Byte 1): 29 => 29
3538 12:17:35.580456 DramcWriteLeveling(PI) end<-----
3539 12:17:35.580955
3540 12:17:35.583815 ==
3541 12:17:35.584255 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 12:17:35.590325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 12:17:35.590770 ==
3544 12:17:35.593188 [Gating] SW mode calibration
3545 12:17:35.599874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3546 12:17:35.603302 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3547 12:17:35.610172 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3548 12:17:35.613267 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3549 12:17:35.616360 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3550 12:17:35.622865 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3551 12:17:35.626069 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3552 12:17:35.629036 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3553 12:17:35.635972 0 15 24 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
3554 12:17:35.639084 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 0)
3555 12:17:35.642138 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3556 12:17:35.649155 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3557 12:17:35.652360 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3558 12:17:35.655438 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3559 12:17:35.662510 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3560 12:17:35.665591 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3561 12:17:35.668767 1 0 24 | B1->B0 | 3c3c 2c2c | 0 1 | (0 0) (0 0)
3562 12:17:35.675598 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3563 12:17:35.678668 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 12:17:35.681720 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3565 12:17:35.688464 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3566 12:17:35.692030 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 12:17:35.695529 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 12:17:35.701852 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3569 12:17:35.704897 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3570 12:17:35.708636 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3571 12:17:35.714895 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 12:17:35.718539 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 12:17:35.721724 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 12:17:35.728044 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 12:17:35.731154 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 12:17:35.734804 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 12:17:35.741056 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 12:17:35.744861 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 12:17:35.747923 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 12:17:35.754671 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 12:17:35.757766 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 12:17:35.760989 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 12:17:35.767909 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 12:17:35.771124 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 12:17:35.774298 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 12:17:35.780589 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3587 12:17:35.784359 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3588 12:17:35.787489 Total UI for P1: 0, mck2ui 16
3589 12:17:35.790579 best dqsien dly found for B0: ( 1, 3, 28)
3590 12:17:35.794326 Total UI for P1: 0, mck2ui 16
3591 12:17:35.797460 best dqsien dly found for B1: ( 1, 3, 28)
3592 12:17:35.800340 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3593 12:17:35.803926 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3594 12:17:35.804005
3595 12:17:35.806957 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3596 12:17:35.810455 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3597 12:17:35.813647 [Gating] SW calibration Done
3598 12:17:35.813724 ==
3599 12:17:35.816819 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 12:17:35.823704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 12:17:35.823783 ==
3602 12:17:35.823865 RX Vref Scan: 0
3603 12:17:35.823927
3604 12:17:35.826847 RX Vref 0 -> 0, step: 1
3605 12:17:35.826918
3606 12:17:35.830028 RX Delay -40 -> 252, step: 8
3607 12:17:35.833763 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3608 12:17:35.836842 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3609 12:17:35.840505 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3610 12:17:35.846998 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3611 12:17:35.850145 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3612 12:17:35.853362 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3613 12:17:35.856898 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3614 12:17:35.859961 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3615 12:17:35.866876 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3616 12:17:35.869952 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3617 12:17:35.873064 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3618 12:17:35.876890 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3619 12:17:35.880013 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3620 12:17:35.886205 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3621 12:17:35.889986 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3622 12:17:35.893055 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3623 12:17:35.893136 ==
3624 12:17:35.896205 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 12:17:35.899762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 12:17:35.899843 ==
3627 12:17:35.902947 DQS Delay:
3628 12:17:35.903022 DQS0 = 0, DQS1 = 0
3629 12:17:35.906559 DQM Delay:
3630 12:17:35.906638 DQM0 = 117, DQM1 = 109
3631 12:17:35.909745 DQ Delay:
3632 12:17:35.912705 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3633 12:17:35.916371 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3634 12:17:35.919483 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3635 12:17:35.923163 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3636 12:17:35.923251
3637 12:17:35.923319
3638 12:17:35.923381 ==
3639 12:17:35.926340 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 12:17:35.929466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 12:17:35.929542 ==
3642 12:17:35.929606
3643 12:17:35.929685
3644 12:17:35.932691 TX Vref Scan disable
3645 12:17:35.935878 == TX Byte 0 ==
3646 12:17:35.939010 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3647 12:17:35.942669 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3648 12:17:35.945808 == TX Byte 1 ==
3649 12:17:35.948933 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3650 12:17:35.952685 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3651 12:17:35.952764 ==
3652 12:17:35.955755 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 12:17:35.962664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 12:17:35.962752 ==
3655 12:17:35.973059 TX Vref=22, minBit 9, minWin=24, winSum=417
3656 12:17:35.976341 TX Vref=24, minBit 8, minWin=25, winSum=427
3657 12:17:35.979557 TX Vref=26, minBit 8, minWin=25, winSum=430
3658 12:17:35.982685 TX Vref=28, minBit 8, minWin=26, winSum=431
3659 12:17:35.986553 TX Vref=30, minBit 8, minWin=26, winSum=433
3660 12:17:35.992817 TX Vref=32, minBit 15, minWin=25, winSum=429
3661 12:17:35.995844 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 30
3662 12:17:35.995930
3663 12:17:35.999008 Final TX Range 1 Vref 30
3664 12:17:35.999093
3665 12:17:35.999160 ==
3666 12:17:36.002690 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 12:17:36.005711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 12:17:36.009543 ==
3669 12:17:36.009619
3670 12:17:36.009683
3671 12:17:36.009742 TX Vref Scan disable
3672 12:17:36.012500 == TX Byte 0 ==
3673 12:17:36.016091 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3674 12:17:36.022764 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3675 12:17:36.022849 == TX Byte 1 ==
3676 12:17:36.025767 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3677 12:17:36.032741 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3678 12:17:36.032826
3679 12:17:36.032892 [DATLAT]
3680 12:17:36.032953 Freq=1200, CH1 RK1
3681 12:17:36.033012
3682 12:17:36.035930 DATLAT Default: 0xd
3683 12:17:36.039196 0, 0xFFFF, sum = 0
3684 12:17:36.039281 1, 0xFFFF, sum = 0
3685 12:17:36.042334 2, 0xFFFF, sum = 0
3686 12:17:36.042418 3, 0xFFFF, sum = 0
3687 12:17:36.045422 4, 0xFFFF, sum = 0
3688 12:17:36.045507 5, 0xFFFF, sum = 0
3689 12:17:36.049050 6, 0xFFFF, sum = 0
3690 12:17:36.049134 7, 0xFFFF, sum = 0
3691 12:17:36.052259 8, 0xFFFF, sum = 0
3692 12:17:36.052343 9, 0xFFFF, sum = 0
3693 12:17:36.055412 10, 0xFFFF, sum = 0
3694 12:17:36.055497 11, 0xFFFF, sum = 0
3695 12:17:36.059035 12, 0x0, sum = 1
3696 12:17:36.059119 13, 0x0, sum = 2
3697 12:17:36.062153 14, 0x0, sum = 3
3698 12:17:36.062237 15, 0x0, sum = 4
3699 12:17:36.065290 best_step = 13
3700 12:17:36.065454
3701 12:17:36.065561 ==
3702 12:17:36.069090 Dram Type= 6, Freq= 0, CH_1, rank 1
3703 12:17:36.072183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3704 12:17:36.072273 ==
3705 12:17:36.075435 RX Vref Scan: 0
3706 12:17:36.075540
3707 12:17:36.075620 RX Vref 0 -> 0, step: 1
3708 12:17:36.075681
3709 12:17:36.078551 RX Delay -21 -> 252, step: 4
3710 12:17:36.085496 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3711 12:17:36.088640 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3712 12:17:36.091645 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3713 12:17:36.094820 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3714 12:17:36.098740 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3715 12:17:36.105039 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3716 12:17:36.108704 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3717 12:17:36.111873 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3718 12:17:36.115007 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3719 12:17:36.118569 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3720 12:17:36.125040 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3721 12:17:36.127962 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3722 12:17:36.131634 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3723 12:17:36.134956 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3724 12:17:36.138167 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3725 12:17:36.145154 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3726 12:17:36.145238 ==
3727 12:17:36.148401 Dram Type= 6, Freq= 0, CH_1, rank 1
3728 12:17:36.151447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3729 12:17:36.151531 ==
3730 12:17:36.151636 DQS Delay:
3731 12:17:36.154591 DQS0 = 0, DQS1 = 0
3732 12:17:36.154675 DQM Delay:
3733 12:17:36.158277 DQM0 = 116, DQM1 = 109
3734 12:17:36.158360 DQ Delay:
3735 12:17:36.161398 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3736 12:17:36.164448 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =114
3737 12:17:36.167561 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3738 12:17:36.174554 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3739 12:17:36.174637
3740 12:17:36.174703
3741 12:17:36.181265 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 415 ps
3742 12:17:36.184325 CH1 RK1: MR19=303, MR18=F2EC
3743 12:17:36.191165 CH1_RK1: MR19=0x303, MR18=0xF2EC, DQSOSC=415, MR23=63, INC=38, DEC=25
3744 12:17:36.194484 [RxdqsGatingPostProcess] freq 1200
3745 12:17:36.197434 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3746 12:17:36.201214 best DQS0 dly(2T, 0.5T) = (0, 11)
3747 12:17:36.204400 best DQS1 dly(2T, 0.5T) = (0, 11)
3748 12:17:36.207547 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3749 12:17:36.210726 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3750 12:17:36.213791 best DQS0 dly(2T, 0.5T) = (0, 11)
3751 12:17:36.217562 best DQS1 dly(2T, 0.5T) = (0, 11)
3752 12:17:36.220568 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3753 12:17:36.223547 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3754 12:17:36.227170 Pre-setting of DQS Precalculation
3755 12:17:36.230164 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3756 12:17:36.240176 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3757 12:17:36.247239 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3758 12:17:36.247331
3759 12:17:36.247398
3760 12:17:36.250420 [Calibration Summary] 2400 Mbps
3761 12:17:36.250492 CH 0, Rank 0
3762 12:17:36.253593 SW Impedance : PASS
3763 12:17:36.253665 DUTY Scan : NO K
3764 12:17:36.257226 ZQ Calibration : PASS
3765 12:17:36.260381 Jitter Meter : NO K
3766 12:17:36.260453 CBT Training : PASS
3767 12:17:36.263419 Write leveling : PASS
3768 12:17:36.266453 RX DQS gating : PASS
3769 12:17:36.266528 RX DQ/DQS(RDDQC) : PASS
3770 12:17:36.270299 TX DQ/DQS : PASS
3771 12:17:36.273354 RX DATLAT : PASS
3772 12:17:36.273433 RX DQ/DQS(Engine): PASS
3773 12:17:36.276442 TX OE : NO K
3774 12:17:36.276573 All Pass.
3775 12:17:36.276640
3776 12:17:36.280070 CH 0, Rank 1
3777 12:17:36.280145 SW Impedance : PASS
3778 12:17:36.283211 DUTY Scan : NO K
3779 12:17:36.286391 ZQ Calibration : PASS
3780 12:17:36.286467 Jitter Meter : NO K
3781 12:17:36.289514 CBT Training : PASS
3782 12:17:36.293209 Write leveling : PASS
3783 12:17:36.293299 RX DQS gating : PASS
3784 12:17:36.296403 RX DQ/DQS(RDDQC) : PASS
3785 12:17:36.299548 TX DQ/DQS : PASS
3786 12:17:36.299626 RX DATLAT : PASS
3787 12:17:36.303202 RX DQ/DQS(Engine): PASS
3788 12:17:36.306353 TX OE : NO K
3789 12:17:36.306430 All Pass.
3790 12:17:36.306503
3791 12:17:36.306575 CH 1, Rank 0
3792 12:17:36.309546 SW Impedance : PASS
3793 12:17:36.312737 DUTY Scan : NO K
3794 12:17:36.312807 ZQ Calibration : PASS
3795 12:17:36.315894 Jitter Meter : NO K
3796 12:17:36.319658 CBT Training : PASS
3797 12:17:36.319757 Write leveling : PASS
3798 12:17:36.322765 RX DQS gating : PASS
3799 12:17:36.322836 RX DQ/DQS(RDDQC) : PASS
3800 12:17:36.325910 TX DQ/DQS : PASS
3801 12:17:36.329338 RX DATLAT : PASS
3802 12:17:36.329416 RX DQ/DQS(Engine): PASS
3803 12:17:36.332340 TX OE : NO K
3804 12:17:36.332442 All Pass.
3805 12:17:36.332573
3806 12:17:36.335997 CH 1, Rank 1
3807 12:17:36.336106 SW Impedance : PASS
3808 12:17:36.339050 DUTY Scan : NO K
3809 12:17:36.342282 ZQ Calibration : PASS
3810 12:17:36.342357 Jitter Meter : NO K
3811 12:17:36.345450 CBT Training : PASS
3812 12:17:36.349289 Write leveling : PASS
3813 12:17:36.349367 RX DQS gating : PASS
3814 12:17:36.352431 RX DQ/DQS(RDDQC) : PASS
3815 12:17:36.355626 TX DQ/DQS : PASS
3816 12:17:36.355708 RX DATLAT : PASS
3817 12:17:36.358665 RX DQ/DQS(Engine): PASS
3818 12:17:36.362124 TX OE : NO K
3819 12:17:36.362230 All Pass.
3820 12:17:36.362321
3821 12:17:36.365094 DramC Write-DBI off
3822 12:17:36.365172 PER_BANK_REFRESH: Hybrid Mode
3823 12:17:36.368777 TX_TRACKING: ON
3824 12:17:36.378167 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3825 12:17:36.381905 [FAST_K] Save calibration result to emmc
3826 12:17:36.385045 dramc_set_vcore_voltage set vcore to 650000
3827 12:17:36.385122 Read voltage for 600, 5
3828 12:17:36.388815 Vio18 = 0
3829 12:17:36.388925 Vcore = 650000
3830 12:17:36.389019 Vdram = 0
3831 12:17:36.392100 Vddq = 0
3832 12:17:36.392211 Vmddr = 0
3833 12:17:36.398180 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3834 12:17:36.401390 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3835 12:17:36.405132 MEM_TYPE=3, freq_sel=19
3836 12:17:36.408304 sv_algorithm_assistance_LP4_1600
3837 12:17:36.411508 ============ PULL DRAM RESETB DOWN ============
3838 12:17:36.414604 ========== PULL DRAM RESETB DOWN end =========
3839 12:17:36.421419 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3840 12:17:36.424539 ===================================
3841 12:17:36.424655 LPDDR4 DRAM CONFIGURATION
3842 12:17:36.428224 ===================================
3843 12:17:36.431281 EX_ROW_EN[0] = 0x0
3844 12:17:36.434752 EX_ROW_EN[1] = 0x0
3845 12:17:36.434875 LP4Y_EN = 0x0
3846 12:17:36.437688 WORK_FSP = 0x0
3847 12:17:36.437799 WL = 0x2
3848 12:17:36.441306 RL = 0x2
3849 12:17:36.441412 BL = 0x2
3850 12:17:36.444590 RPST = 0x0
3851 12:17:36.444692 RD_PRE = 0x0
3852 12:17:36.447658 WR_PRE = 0x1
3853 12:17:36.447764 WR_PST = 0x0
3854 12:17:36.450839 DBI_WR = 0x0
3855 12:17:36.450917 DBI_RD = 0x0
3856 12:17:36.454680 OTF = 0x1
3857 12:17:36.457916 ===================================
3858 12:17:36.461101 ===================================
3859 12:17:36.461172 ANA top config
3860 12:17:36.464272 ===================================
3861 12:17:36.467836 DLL_ASYNC_EN = 0
3862 12:17:36.471036 ALL_SLAVE_EN = 1
3863 12:17:36.474180 NEW_RANK_MODE = 1
3864 12:17:36.474257 DLL_IDLE_MODE = 1
3865 12:17:36.477318 LP45_APHY_COMB_EN = 1
3866 12:17:36.481063 TX_ODT_DIS = 1
3867 12:17:36.483976 NEW_8X_MODE = 1
3868 12:17:36.487099 ===================================
3869 12:17:36.490772 ===================================
3870 12:17:36.494019 data_rate = 1200
3871 12:17:36.494124 CKR = 1
3872 12:17:36.497177 DQ_P2S_RATIO = 8
3873 12:17:36.500893 ===================================
3874 12:17:36.504087 CA_P2S_RATIO = 8
3875 12:17:36.507343 DQ_CA_OPEN = 0
3876 12:17:36.510369 DQ_SEMI_OPEN = 0
3877 12:17:36.513576 CA_SEMI_OPEN = 0
3878 12:17:36.513662 CA_FULL_RATE = 0
3879 12:17:36.517438 DQ_CKDIV4_EN = 1
3880 12:17:36.520489 CA_CKDIV4_EN = 1
3881 12:17:36.523694 CA_PREDIV_EN = 0
3882 12:17:36.526768 PH8_DLY = 0
3883 12:17:36.530470 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3884 12:17:36.530596 DQ_AAMCK_DIV = 4
3885 12:17:36.533536 CA_AAMCK_DIV = 4
3886 12:17:36.537095 CA_ADMCK_DIV = 4
3887 12:17:36.540176 DQ_TRACK_CA_EN = 0
3888 12:17:36.543677 CA_PICK = 600
3889 12:17:36.546921 CA_MCKIO = 600
3890 12:17:36.550090 MCKIO_SEMI = 0
3891 12:17:36.553302 PLL_FREQ = 2288
3892 12:17:36.553412 DQ_UI_PI_RATIO = 32
3893 12:17:36.556435 CA_UI_PI_RATIO = 0
3894 12:17:36.560261 ===================================
3895 12:17:36.563429 ===================================
3896 12:17:36.566630 memory_type:LPDDR4
3897 12:17:36.569630 GP_NUM : 10
3898 12:17:36.569750 SRAM_EN : 1
3899 12:17:36.573355 MD32_EN : 0
3900 12:17:36.576328 ===================================
3901 12:17:36.579509 [ANA_INIT] >>>>>>>>>>>>>>
3902 12:17:36.579638 <<<<<< [CONFIGURE PHASE]: ANA_TX
3903 12:17:36.583139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3904 12:17:36.586233 ===================================
3905 12:17:36.589445 data_rate = 1200,PCW = 0X5800
3906 12:17:36.593087 ===================================
3907 12:17:36.596287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3908 12:17:36.602576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3909 12:17:36.609562 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3910 12:17:36.612713 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3911 12:17:36.615928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3912 12:17:36.619481 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3913 12:17:36.622907 [ANA_INIT] flow start
3914 12:17:36.623068 [ANA_INIT] PLL >>>>>>>>
3915 12:17:36.625990 [ANA_INIT] PLL <<<<<<<<
3916 12:17:36.629348 [ANA_INIT] MIDPI >>>>>>>>
3917 12:17:36.632403 [ANA_INIT] MIDPI <<<<<<<<
3918 12:17:36.632556 [ANA_INIT] DLL >>>>>>>>
3919 12:17:36.636391 [ANA_INIT] flow end
3920 12:17:36.639018 ============ LP4 DIFF to SE enter ============
3921 12:17:36.642916 ============ LP4 DIFF to SE exit ============
3922 12:17:36.645705 [ANA_INIT] <<<<<<<<<<<<<
3923 12:17:36.649266 [Flow] Enable top DCM control >>>>>
3924 12:17:36.652411 [Flow] Enable top DCM control <<<<<
3925 12:17:36.655600 Enable DLL master slave shuffle
3926 12:17:36.662647 ==============================================================
3927 12:17:36.662897 Gating Mode config
3928 12:17:36.669107 ==============================================================
3929 12:17:36.669618 Config description:
3930 12:17:36.679615 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3931 12:17:36.685845 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3932 12:17:36.692171 SELPH_MODE 0: By rank 1: By Phase
3933 12:17:36.695833 ==============================================================
3934 12:17:36.699008 GAT_TRACK_EN = 1
3935 12:17:36.702095 RX_GATING_MODE = 2
3936 12:17:36.705726 RX_GATING_TRACK_MODE = 2
3937 12:17:36.708766 SELPH_MODE = 1
3938 12:17:36.712628 PICG_EARLY_EN = 1
3939 12:17:36.715790 VALID_LAT_VALUE = 1
3940 12:17:36.722243 ==============================================================
3941 12:17:36.725352 Enter into Gating configuration >>>>
3942 12:17:36.728502 Exit from Gating configuration <<<<
3943 12:17:36.731729 Enter into DVFS_PRE_config >>>>>
3944 12:17:36.741957 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3945 12:17:36.745207 Exit from DVFS_PRE_config <<<<<
3946 12:17:36.748139 Enter into PICG configuration >>>>
3947 12:17:36.751878 Exit from PICG configuration <<<<
3948 12:17:36.754987 [RX_INPUT] configuration >>>>>
3949 12:17:36.755425 [RX_INPUT] configuration <<<<<
3950 12:17:36.762003 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3951 12:17:36.768684 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3952 12:17:36.771835 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3953 12:17:36.778685 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3954 12:17:36.784918 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3955 12:17:36.791446 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3956 12:17:36.794577 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3957 12:17:36.797741 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3958 12:17:36.804666 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3959 12:17:36.807831 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3960 12:17:36.811035 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3961 12:17:36.817646 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3962 12:17:36.820932 ===================================
3963 12:17:36.821362 LPDDR4 DRAM CONFIGURATION
3964 12:17:36.824150 ===================================
3965 12:17:36.827441 EX_ROW_EN[0] = 0x0
3966 12:17:36.831386 EX_ROW_EN[1] = 0x0
3967 12:17:36.831819 LP4Y_EN = 0x0
3968 12:17:36.834709 WORK_FSP = 0x0
3969 12:17:36.835272 WL = 0x2
3970 12:17:36.837884 RL = 0x2
3971 12:17:36.838316 BL = 0x2
3972 12:17:36.840961 RPST = 0x0
3973 12:17:36.841393 RD_PRE = 0x0
3974 12:17:36.843791 WR_PRE = 0x1
3975 12:17:36.844224 WR_PST = 0x0
3976 12:17:36.847544 DBI_WR = 0x0
3977 12:17:36.848114 DBI_RD = 0x0
3978 12:17:36.850569 OTF = 0x1
3979 12:17:36.853814 ===================================
3980 12:17:36.857408 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3981 12:17:36.860309 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3982 12:17:36.866746 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3983 12:17:36.870447 ===================================
3984 12:17:36.870876 LPDDR4 DRAM CONFIGURATION
3985 12:17:36.873761 ===================================
3986 12:17:36.876958 EX_ROW_EN[0] = 0x10
3987 12:17:36.879978 EX_ROW_EN[1] = 0x0
3988 12:17:36.880406 LP4Y_EN = 0x0
3989 12:17:36.883775 WORK_FSP = 0x0
3990 12:17:36.884196 WL = 0x2
3991 12:17:36.886533 RL = 0x2
3992 12:17:36.886975 BL = 0x2
3993 12:17:36.889949 RPST = 0x0
3994 12:17:36.890510 RD_PRE = 0x0
3995 12:17:36.893417 WR_PRE = 0x1
3996 12:17:36.893903 WR_PST = 0x0
3997 12:17:36.896610 DBI_WR = 0x0
3998 12:17:36.897039 DBI_RD = 0x0
3999 12:17:36.899754 OTF = 0x1
4000 12:17:36.903043 ===================================
4001 12:17:36.909965 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4002 12:17:36.912954 nWR fixed to 30
4003 12:17:36.916668 [ModeRegInit_LP4] CH0 RK0
4004 12:17:36.917044 [ModeRegInit_LP4] CH0 RK1
4005 12:17:36.919894 [ModeRegInit_LP4] CH1 RK0
4006 12:17:36.923108 [ModeRegInit_LP4] CH1 RK1
4007 12:17:36.923540 match AC timing 17
4008 12:17:36.929460 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4009 12:17:36.933243 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4010 12:17:36.936456 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4011 12:17:36.942754 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4012 12:17:36.946362 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4013 12:17:36.946798 ==
4014 12:17:36.949614 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 12:17:36.952604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 12:17:36.953039 ==
4017 12:17:36.959330 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4018 12:17:36.965846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4019 12:17:36.969171 [CA 0] Center 36 (6~66) winsize 61
4020 12:17:36.972941 [CA 1] Center 36 (6~66) winsize 61
4021 12:17:36.976021 [CA 2] Center 34 (3~65) winsize 63
4022 12:17:36.979047 [CA 3] Center 34 (4~65) winsize 62
4023 12:17:36.982333 [CA 4] Center 33 (3~64) winsize 62
4024 12:17:36.985420 [CA 5] Center 33 (3~64) winsize 62
4025 12:17:36.985853
4026 12:17:36.989121 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4027 12:17:36.989737
4028 12:17:36.992063 [CATrainingPosCal] consider 1 rank data
4029 12:17:36.995471 u2DelayCellTimex100 = 270/100 ps
4030 12:17:36.999023 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4031 12:17:37.002008 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4032 12:17:37.005259 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4033 12:17:37.008901 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4034 12:17:37.015107 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4035 12:17:37.018874 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4036 12:17:37.019307
4037 12:17:37.022096 CA PerBit enable=1, Macro0, CA PI delay=33
4038 12:17:37.022523
4039 12:17:37.025286 [CBTSetCACLKResult] CA Dly = 33
4040 12:17:37.025715 CS Dly: 4 (0~35)
4041 12:17:37.026056 ==
4042 12:17:37.028585 Dram Type= 6, Freq= 0, CH_0, rank 1
4043 12:17:37.035129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 12:17:37.035574 ==
4045 12:17:37.038936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4046 12:17:37.045196 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4047 12:17:37.048542 [CA 0] Center 35 (5~66) winsize 62
4048 12:17:37.051596 [CA 1] Center 36 (6~66) winsize 61
4049 12:17:37.054819 [CA 2] Center 33 (3~64) winsize 62
4050 12:17:37.058895 [CA 3] Center 33 (3~64) winsize 62
4051 12:17:37.061446 [CA 4] Center 33 (3~64) winsize 62
4052 12:17:37.065033 [CA 5] Center 33 (2~64) winsize 63
4053 12:17:37.065463
4054 12:17:37.067985 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4055 12:17:37.068415
4056 12:17:37.071783 [CATrainingPosCal] consider 2 rank data
4057 12:17:37.074906 u2DelayCellTimex100 = 270/100 ps
4058 12:17:37.078116 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4059 12:17:37.085013 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4060 12:17:37.088055 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4061 12:17:37.091168 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4062 12:17:37.094336 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4063 12:17:37.097956 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4064 12:17:37.098405
4065 12:17:37.101358 CA PerBit enable=1, Macro0, CA PI delay=33
4066 12:17:37.101785
4067 12:17:37.104322 [CBTSetCACLKResult] CA Dly = 33
4068 12:17:37.107457 CS Dly: 5 (0~38)
4069 12:17:37.107878
4070 12:17:37.111192 ----->DramcWriteLeveling(PI) begin...
4071 12:17:37.111624 ==
4072 12:17:37.114320 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 12:17:37.117495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 12:17:37.117924 ==
4075 12:17:37.121219 Write leveling (Byte 0): 34 => 34
4076 12:17:37.124373 Write leveling (Byte 1): 30 => 30
4077 12:17:37.127576 DramcWriteLeveling(PI) end<-----
4078 12:17:37.128003
4079 12:17:37.128339 ==
4080 12:17:37.131038 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 12:17:37.134798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 12:17:37.135341 ==
4083 12:17:37.137806 [Gating] SW mode calibration
4084 12:17:37.144441 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4085 12:17:37.150491 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4086 12:17:37.154513 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4087 12:17:37.157588 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4088 12:17:37.163992 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4089 12:17:37.167110 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4090 12:17:37.170775 0 9 16 | B1->B0 | 3030 2424 | 1 0 | (1 0) (0 0)
4091 12:17:37.176932 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4092 12:17:37.180714 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4093 12:17:37.184028 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4094 12:17:37.190374 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4095 12:17:37.193542 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4096 12:17:37.196812 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4097 12:17:37.203423 0 10 12 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
4098 12:17:37.206544 0 10 16 | B1->B0 | 3737 4141 | 0 0 | (0 0) (0 0)
4099 12:17:37.210073 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4100 12:17:37.217066 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4101 12:17:37.220015 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 12:17:37.223098 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 12:17:37.230050 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4104 12:17:37.233257 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 12:17:37.236378 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4106 12:17:37.242870 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 12:17:37.246606 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 12:17:37.249823 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 12:17:37.255737 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 12:17:37.259549 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 12:17:37.262863 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 12:17:37.269463 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 12:17:37.272618 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 12:17:37.275646 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 12:17:37.282356 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 12:17:37.286087 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 12:17:37.289246 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 12:17:37.295502 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 12:17:37.299309 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 12:17:37.302431 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 12:17:37.308775 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 12:17:37.312312 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4123 12:17:37.315238 Total UI for P1: 0, mck2ui 16
4124 12:17:37.318864 best dqsien dly found for B0: ( 0, 13, 14)
4125 12:17:37.321982 Total UI for P1: 0, mck2ui 16
4126 12:17:37.325220 best dqsien dly found for B1: ( 0, 13, 14)
4127 12:17:37.328414 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4128 12:17:37.332233 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4129 12:17:37.332876
4130 12:17:37.335360 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4131 12:17:37.341820 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4132 12:17:37.342246 [Gating] SW calibration Done
4133 12:17:37.342583 ==
4134 12:17:37.344976 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 12:17:37.352030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 12:17:37.352645 ==
4137 12:17:37.353071 RX Vref Scan: 0
4138 12:17:37.353459
4139 12:17:37.355210 RX Vref 0 -> 0, step: 1
4140 12:17:37.355634
4141 12:17:37.358467 RX Delay -230 -> 252, step: 16
4142 12:17:37.361452 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4143 12:17:37.364733 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4144 12:17:37.372246 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4145 12:17:37.374852 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4146 12:17:37.377887 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4147 12:17:37.381515 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4148 12:17:37.385083 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4149 12:17:37.391058 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4150 12:17:37.394450 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4151 12:17:37.398096 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4152 12:17:37.401075 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4153 12:17:37.407773 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4154 12:17:37.410968 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4155 12:17:37.414761 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4156 12:17:37.417824 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4157 12:17:37.424385 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4158 12:17:37.424857 ==
4159 12:17:37.427569 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 12:17:37.431083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 12:17:37.431610 ==
4162 12:17:37.431950 DQS Delay:
4163 12:17:37.434133 DQS0 = 0, DQS1 = 0
4164 12:17:37.434557 DQM Delay:
4165 12:17:37.437852 DQM0 = 45, DQM1 = 37
4166 12:17:37.438279 DQ Delay:
4167 12:17:37.440940 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4168 12:17:37.444049 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =49
4169 12:17:37.447271 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4170 12:17:37.450258 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4171 12:17:37.450687
4172 12:17:37.451021
4173 12:17:37.451333 ==
4174 12:17:37.454153 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 12:17:37.457209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 12:17:37.460183 ==
4177 12:17:37.460652
4178 12:17:37.460996
4179 12:17:37.461311 TX Vref Scan disable
4180 12:17:37.463988 == TX Byte 0 ==
4181 12:17:37.467200 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4182 12:17:37.473586 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4183 12:17:37.474086 == TX Byte 1 ==
4184 12:17:37.477299 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4185 12:17:37.483337 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4186 12:17:37.483781 ==
4187 12:17:37.486912 Dram Type= 6, Freq= 0, CH_0, rank 0
4188 12:17:37.489905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 12:17:37.490372 ==
4190 12:17:37.490714
4191 12:17:37.491085
4192 12:17:37.493440 TX Vref Scan disable
4193 12:17:37.496707 == TX Byte 0 ==
4194 12:17:37.499913 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4195 12:17:37.503644 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4196 12:17:37.506742 == TX Byte 1 ==
4197 12:17:37.510000 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4198 12:17:37.513053 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4199 12:17:37.513483
4200 12:17:37.513820 [DATLAT]
4201 12:17:37.516234 Freq=600, CH0 RK0
4202 12:17:37.516779
4203 12:17:37.519955 DATLAT Default: 0x9
4204 12:17:37.520379 0, 0xFFFF, sum = 0
4205 12:17:37.522951 1, 0xFFFF, sum = 0
4206 12:17:37.523391 2, 0xFFFF, sum = 0
4207 12:17:37.526418 3, 0xFFFF, sum = 0
4208 12:17:37.526846 4, 0xFFFF, sum = 0
4209 12:17:37.529286 5, 0xFFFF, sum = 0
4210 12:17:37.529719 6, 0xFFFF, sum = 0
4211 12:17:37.533004 7, 0xFFFF, sum = 0
4212 12:17:37.533435 8, 0x0, sum = 1
4213 12:17:37.536269 9, 0x0, sum = 2
4214 12:17:37.536844 10, 0x0, sum = 3
4215 12:17:37.539338 11, 0x0, sum = 4
4216 12:17:37.539809 best_step = 9
4217 12:17:37.540345
4218 12:17:37.540987 ==
4219 12:17:37.543063 Dram Type= 6, Freq= 0, CH_0, rank 0
4220 12:17:37.546320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 12:17:37.546795 ==
4222 12:17:37.549413 RX Vref Scan: 1
4223 12:17:37.549889
4224 12:17:37.552670 RX Vref 0 -> 0, step: 1
4225 12:17:37.553103
4226 12:17:37.553437 RX Delay -179 -> 252, step: 8
4227 12:17:37.555826
4228 12:17:37.556271 Set Vref, RX VrefLevel [Byte0]: 61
4229 12:17:37.562666 [Byte1]: 55
4230 12:17:37.563090
4231 12:17:37.565785 Final RX Vref Byte 0 = 61 to rank0
4232 12:17:37.569010 Final RX Vref Byte 1 = 55 to rank0
4233 12:17:37.572264 Final RX Vref Byte 0 = 61 to rank1
4234 12:17:37.575295 Final RX Vref Byte 1 = 55 to rank1==
4235 12:17:37.579060 Dram Type= 6, Freq= 0, CH_0, rank 0
4236 12:17:37.581959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 12:17:37.582428 ==
4238 12:17:37.585616 DQS Delay:
4239 12:17:37.586059 DQS0 = 0, DQS1 = 0
4240 12:17:37.586418 DQM Delay:
4241 12:17:37.588503 DQM0 = 44, DQM1 = 32
4242 12:17:37.588955 DQ Delay:
4243 12:17:37.591609 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4244 12:17:37.595059 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4245 12:17:37.598701 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4246 12:17:37.601738 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4247 12:17:37.602129
4248 12:17:37.602451
4249 12:17:37.611795 [DQSOSCAuto] RK0, (LSB)MR18= 0x673e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4250 12:17:37.614872 CH0 RK0: MR19=808, MR18=673E
4251 12:17:37.618663 CH0_RK0: MR19=0x808, MR18=0x673E, DQSOSC=390, MR23=63, INC=172, DEC=114
4252 12:17:37.619102
4253 12:17:37.621915 ----->DramcWriteLeveling(PI) begin...
4254 12:17:37.624951 ==
4255 12:17:37.628648 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 12:17:37.631522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 12:17:37.631980 ==
4258 12:17:37.635111 Write leveling (Byte 0): 32 => 32
4259 12:17:37.638080 Write leveling (Byte 1): 31 => 31
4260 12:17:37.641798 DramcWriteLeveling(PI) end<-----
4261 12:17:37.642254
4262 12:17:37.642592 ==
4263 12:17:37.644985 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 12:17:37.648313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 12:17:37.648783 ==
4266 12:17:37.651451 [Gating] SW mode calibration
4267 12:17:37.657974 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4268 12:17:37.664257 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4269 12:17:37.667983 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4270 12:17:37.671192 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4271 12:17:37.677502 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4272 12:17:37.680750 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
4273 12:17:37.684456 0 9 16 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
4274 12:17:37.691224 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4275 12:17:37.694217 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4276 12:17:37.697317 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4277 12:17:37.704382 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4278 12:17:37.707409 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4279 12:17:37.710523 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4280 12:17:37.717564 0 10 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
4281 12:17:37.720495 0 10 16 | B1->B0 | 3c3c 4343 | 0 0 | (1 1) (0 0)
4282 12:17:37.723759 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4283 12:17:37.730598 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 12:17:37.733714 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 12:17:37.737483 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 12:17:37.743945 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 12:17:37.747202 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4288 12:17:37.750350 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4289 12:17:37.756765 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 12:17:37.760093 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 12:17:37.763830 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 12:17:37.769924 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 12:17:37.773209 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 12:17:37.776961 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 12:17:37.783263 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 12:17:37.787115 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 12:17:37.790223 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 12:17:37.796439 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 12:17:37.800054 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 12:17:37.802834 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 12:17:37.809917 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 12:17:37.812942 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 12:17:37.816414 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 12:17:37.822476 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 12:17:37.826036 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4306 12:17:37.829270 Total UI for P1: 0, mck2ui 16
4307 12:17:37.832290 best dqsien dly found for B0: ( 0, 13, 14)
4308 12:17:37.836030 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4309 12:17:37.839315 Total UI for P1: 0, mck2ui 16
4310 12:17:37.842173 best dqsien dly found for B1: ( 0, 13, 16)
4311 12:17:37.845963 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4312 12:17:37.848877 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4313 12:17:37.849324
4314 12:17:37.855758 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4315 12:17:37.858966 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4316 12:17:37.862219 [Gating] SW calibration Done
4317 12:17:37.862664 ==
4318 12:17:37.865925 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 12:17:37.869026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 12:17:37.869472 ==
4321 12:17:37.870027 RX Vref Scan: 0
4322 12:17:37.870379
4323 12:17:37.872583 RX Vref 0 -> 0, step: 1
4324 12:17:37.873126
4325 12:17:37.876061 RX Delay -230 -> 252, step: 16
4326 12:17:37.879571 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4327 12:17:37.882475 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4328 12:17:37.888567 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4329 12:17:37.892465 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4330 12:17:37.895419 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4331 12:17:37.898618 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4332 12:17:37.905488 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4333 12:17:37.908315 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4334 12:17:37.912027 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4335 12:17:37.915021 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4336 12:17:37.921741 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4337 12:17:37.925246 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4338 12:17:37.928595 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4339 12:17:37.932236 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4340 12:17:37.938434 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4341 12:17:37.942178 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4342 12:17:37.942610 ==
4343 12:17:37.945421 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 12:17:37.948653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 12:17:37.949191 ==
4346 12:17:37.949541 DQS Delay:
4347 12:17:37.951926 DQS0 = 0, DQS1 = 0
4348 12:17:37.952359 DQM Delay:
4349 12:17:37.955339 DQM0 = 41, DQM1 = 35
4350 12:17:37.955895 DQ Delay:
4351 12:17:37.958274 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4352 12:17:37.961949 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4353 12:17:37.965172 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4354 12:17:37.968338 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4355 12:17:37.968995
4356 12:17:37.969364
4357 12:17:37.969705 ==
4358 12:17:37.971417 Dram Type= 6, Freq= 0, CH_0, rank 1
4359 12:17:37.978108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 12:17:37.978651 ==
4361 12:17:37.978993
4362 12:17:37.979295
4363 12:17:37.979627 TX Vref Scan disable
4364 12:17:37.981297 == TX Byte 0 ==
4365 12:17:37.984426 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4366 12:17:37.991492 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4367 12:17:37.991946 == TX Byte 1 ==
4368 12:17:37.994661 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4369 12:17:38.001623 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4370 12:17:38.002045 ==
4371 12:17:38.004705 Dram Type= 6, Freq= 0, CH_0, rank 1
4372 12:17:38.007994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 12:17:38.008412 ==
4374 12:17:38.008770
4375 12:17:38.009078
4376 12:17:38.011834 TX Vref Scan disable
4377 12:17:38.014604 == TX Byte 0 ==
4378 12:17:38.018205 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4379 12:17:38.021271 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4380 12:17:38.024821 == TX Byte 1 ==
4381 12:17:38.027717 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4382 12:17:38.031041 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4383 12:17:38.031568
4384 12:17:38.031977 [DATLAT]
4385 12:17:38.034512 Freq=600, CH0 RK1
4386 12:17:38.034963
4387 12:17:38.037948 DATLAT Default: 0x9
4388 12:17:38.038390 0, 0xFFFF, sum = 0
4389 12:17:38.040775 1, 0xFFFF, sum = 0
4390 12:17:38.041368 2, 0xFFFF, sum = 0
4391 12:17:38.044045 3, 0xFFFF, sum = 0
4392 12:17:38.044474 4, 0xFFFF, sum = 0
4393 12:17:38.047749 5, 0xFFFF, sum = 0
4394 12:17:38.048173 6, 0xFFFF, sum = 0
4395 12:17:38.050788 7, 0xFFFF, sum = 0
4396 12:17:38.051213 8, 0x0, sum = 1
4397 12:17:38.054042 9, 0x0, sum = 2
4398 12:17:38.054469 10, 0x0, sum = 3
4399 12:17:38.057672 11, 0x0, sum = 4
4400 12:17:38.058098 best_step = 9
4401 12:17:38.058452
4402 12:17:38.058763 ==
4403 12:17:38.060819 Dram Type= 6, Freq= 0, CH_0, rank 1
4404 12:17:38.064051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 12:17:38.064474 ==
4406 12:17:38.067171 RX Vref Scan: 0
4407 12:17:38.067587
4408 12:17:38.070387 RX Vref 0 -> 0, step: 1
4409 12:17:38.070803
4410 12:17:38.071130 RX Delay -195 -> 252, step: 8
4411 12:17:38.078594 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4412 12:17:38.081738 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4413 12:17:38.084862 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4414 12:17:38.088785 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4415 12:17:38.095257 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4416 12:17:38.098297 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4417 12:17:38.101351 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4418 12:17:38.104637 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4419 12:17:38.112018 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4420 12:17:38.115173 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4421 12:17:38.117973 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4422 12:17:38.121698 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4423 12:17:38.128359 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4424 12:17:38.131655 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4425 12:17:38.134660 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4426 12:17:38.138265 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4427 12:17:38.138746 ==
4428 12:17:38.140987 Dram Type= 6, Freq= 0, CH_0, rank 1
4429 12:17:38.147641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 12:17:38.148071 ==
4431 12:17:38.148413 DQS Delay:
4432 12:17:38.150960 DQS0 = 0, DQS1 = 0
4433 12:17:38.151414 DQM Delay:
4434 12:17:38.151752 DQM0 = 41, DQM1 = 37
4435 12:17:38.154409 DQ Delay:
4436 12:17:38.158148 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4437 12:17:38.160987 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4438 12:17:38.164129 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4439 12:17:38.167992 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4440 12:17:38.168635
4441 12:17:38.168990
4442 12:17:38.174364 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f12, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4443 12:17:38.178201 CH0 RK1: MR19=808, MR18=5F12
4444 12:17:38.184105 CH0_RK1: MR19=0x808, MR18=0x5F12, DQSOSC=391, MR23=63, INC=171, DEC=114
4445 12:17:38.187535 [RxdqsGatingPostProcess] freq 600
4446 12:17:38.194074 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4447 12:17:38.194511 Pre-setting of DQS Precalculation
4448 12:17:38.201045 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4449 12:17:38.201478 ==
4450 12:17:38.204349 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 12:17:38.207513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 12:17:38.207946 ==
4453 12:17:38.213774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4454 12:17:38.220600 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4455 12:17:38.223711 [CA 0] Center 35 (5~66) winsize 62
4456 12:17:38.226859 [CA 1] Center 35 (5~66) winsize 62
4457 12:17:38.230472 [CA 2] Center 34 (4~65) winsize 62
4458 12:17:38.233595 [CA 3] Center 33 (3~64) winsize 62
4459 12:17:38.236846 [CA 4] Center 34 (4~65) winsize 62
4460 12:17:38.240386 [CA 5] Center 33 (3~64) winsize 62
4461 12:17:38.240850
4462 12:17:38.243459 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4463 12:17:38.243896
4464 12:17:38.247118 [CATrainingPosCal] consider 1 rank data
4465 12:17:38.249982 u2DelayCellTimex100 = 270/100 ps
4466 12:17:38.253558 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4467 12:17:38.256496 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4468 12:17:38.260177 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4469 12:17:38.263045 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4470 12:17:38.266474 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4471 12:17:38.272771 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4472 12:17:38.273283
4473 12:17:38.276464 CA PerBit enable=1, Macro0, CA PI delay=33
4474 12:17:38.276953
4475 12:17:38.280086 [CBTSetCACLKResult] CA Dly = 33
4476 12:17:38.280815 CS Dly: 5 (0~36)
4477 12:17:38.281184 ==
4478 12:17:38.282881 Dram Type= 6, Freq= 0, CH_1, rank 1
4479 12:17:38.289052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 12:17:38.289485 ==
4481 12:17:38.292927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4482 12:17:38.299306 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4483 12:17:38.302563 [CA 0] Center 35 (5~66) winsize 62
4484 12:17:38.305546 [CA 1] Center 36 (6~66) winsize 61
4485 12:17:38.308874 [CA 2] Center 34 (4~65) winsize 62
4486 12:17:38.312607 [CA 3] Center 34 (3~65) winsize 63
4487 12:17:38.315839 [CA 4] Center 34 (4~65) winsize 62
4488 12:17:38.319015 [CA 5] Center 34 (3~65) winsize 63
4489 12:17:38.319445
4490 12:17:38.322211 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4491 12:17:38.322641
4492 12:17:38.325377 [CATrainingPosCal] consider 2 rank data
4493 12:17:38.329046 u2DelayCellTimex100 = 270/100 ps
4494 12:17:38.332203 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4495 12:17:38.339057 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4496 12:17:38.342219 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4497 12:17:38.345748 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4498 12:17:38.348588 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4499 12:17:38.352184 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4500 12:17:38.352673
4501 12:17:38.355614 CA PerBit enable=1, Macro0, CA PI delay=33
4502 12:17:38.356089
4503 12:17:38.358505 [CBTSetCACLKResult] CA Dly = 33
4504 12:17:38.361548 CS Dly: 5 (0~37)
4505 12:17:38.362019
4506 12:17:38.365087 ----->DramcWriteLeveling(PI) begin...
4507 12:17:38.365529 ==
4508 12:17:38.368787 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 12:17:38.371877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 12:17:38.372409 ==
4511 12:17:38.374767 Write leveling (Byte 0): 29 => 29
4512 12:17:38.378603 Write leveling (Byte 1): 29 => 29
4513 12:17:38.381695 DramcWriteLeveling(PI) end<-----
4514 12:17:38.382116
4515 12:17:38.382452 ==
4516 12:17:38.384979 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 12:17:38.388130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 12:17:38.388620 ==
4519 12:17:38.391270 [Gating] SW mode calibration
4520 12:17:38.397792 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4521 12:17:38.404606 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4522 12:17:38.407881 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4523 12:17:38.411279 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4524 12:17:38.418073 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4525 12:17:38.421189 0 9 12 | B1->B0 | 3131 2f2f | 0 1 | (0 0) (1 0)
4526 12:17:38.424346 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4527 12:17:38.430882 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4528 12:17:38.434422 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4529 12:17:38.437439 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4530 12:17:38.444206 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4531 12:17:38.447104 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4532 12:17:38.450876 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4533 12:17:38.457517 0 10 12 | B1->B0 | 3333 3b3b | 0 0 | (0 0) (0 0)
4534 12:17:38.460383 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4535 12:17:38.464157 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4536 12:17:38.470385 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 12:17:38.474086 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4538 12:17:38.477054 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4539 12:17:38.483869 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 12:17:38.487221 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4541 12:17:38.490594 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4542 12:17:38.496460 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 12:17:38.500404 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 12:17:38.503481 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 12:17:38.510250 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 12:17:38.513502 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 12:17:38.516769 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 12:17:38.523035 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 12:17:38.526160 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 12:17:38.529300 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 12:17:38.536193 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 12:17:38.539332 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 12:17:38.543121 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 12:17:38.549185 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 12:17:38.552887 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 12:17:38.555981 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 12:17:38.562504 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4558 12:17:38.565902 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4559 12:17:38.569383 Total UI for P1: 0, mck2ui 16
4560 12:17:38.572494 best dqsien dly found for B0: ( 0, 13, 12)
4561 12:17:38.576139 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4562 12:17:38.579367 Total UI for P1: 0, mck2ui 16
4563 12:17:38.582176 best dqsien dly found for B1: ( 0, 13, 14)
4564 12:17:38.589051 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4565 12:17:38.592088 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4566 12:17:38.592633
4567 12:17:38.595315 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4568 12:17:38.598351 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4569 12:17:38.602302 [Gating] SW calibration Done
4570 12:17:38.602771 ==
4571 12:17:38.605480 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 12:17:38.608491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 12:17:38.608985 ==
4574 12:17:38.611880 RX Vref Scan: 0
4575 12:17:38.612445
4576 12:17:38.612920 RX Vref 0 -> 0, step: 1
4577 12:17:38.613295
4578 12:17:38.614929 RX Delay -230 -> 252, step: 16
4579 12:17:38.621912 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4580 12:17:38.624945 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4581 12:17:38.628695 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4582 12:17:38.632020 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4583 12:17:38.635057 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4584 12:17:38.641760 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4585 12:17:38.644915 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4586 12:17:38.648397 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4587 12:17:38.651483 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4588 12:17:38.658025 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4589 12:17:38.661029 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4590 12:17:38.664461 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4591 12:17:38.667493 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4592 12:17:38.674601 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4593 12:17:38.677654 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4594 12:17:38.681127 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4595 12:17:38.681556 ==
4596 12:17:38.684329 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 12:17:38.687880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 12:17:38.688312 ==
4599 12:17:38.690753 DQS Delay:
4600 12:17:38.691182 DQS0 = 0, DQS1 = 0
4601 12:17:38.694387 DQM Delay:
4602 12:17:38.694814 DQM0 = 50, DQM1 = 39
4603 12:17:38.695196 DQ Delay:
4604 12:17:38.697605 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =41
4605 12:17:38.700909 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =41
4606 12:17:38.704026 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4607 12:17:38.707179 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4608 12:17:38.707605
4609 12:17:38.711104
4610 12:17:38.711654 ==
4611 12:17:38.714147 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 12:17:38.717288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 12:17:38.717745 ==
4614 12:17:38.718084
4615 12:17:38.718399
4616 12:17:38.720506 TX Vref Scan disable
4617 12:17:38.720973 == TX Byte 0 ==
4618 12:17:38.727330 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4619 12:17:38.730440 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4620 12:17:38.730872 == TX Byte 1 ==
4621 12:17:38.737114 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4622 12:17:38.740274 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4623 12:17:38.740766 ==
4624 12:17:38.743415 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 12:17:38.746604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 12:17:38.747035 ==
4627 12:17:38.747375
4628 12:17:38.747688
4629 12:17:38.750373 TX Vref Scan disable
4630 12:17:38.753439 == TX Byte 0 ==
4631 12:17:38.756837 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4632 12:17:38.763333 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4633 12:17:38.763926 == TX Byte 1 ==
4634 12:17:38.766194 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4635 12:17:38.773413 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4636 12:17:38.773840
4637 12:17:38.774194 [DATLAT]
4638 12:17:38.774507 Freq=600, CH1 RK0
4639 12:17:38.774811
4640 12:17:38.776558 DATLAT Default: 0x9
4641 12:17:38.777076 0, 0xFFFF, sum = 0
4642 12:17:38.779763 1, 0xFFFF, sum = 0
4643 12:17:38.782933 2, 0xFFFF, sum = 0
4644 12:17:38.783387 3, 0xFFFF, sum = 0
4645 12:17:38.786561 4, 0xFFFF, sum = 0
4646 12:17:38.787141 5, 0xFFFF, sum = 0
4647 12:17:38.789578 6, 0xFFFF, sum = 0
4648 12:17:38.790018 7, 0xFFFF, sum = 0
4649 12:17:38.793296 8, 0x0, sum = 1
4650 12:17:38.793756 9, 0x0, sum = 2
4651 12:17:38.794118 10, 0x0, sum = 3
4652 12:17:38.796060 11, 0x0, sum = 4
4653 12:17:38.796607 best_step = 9
4654 12:17:38.796985
4655 12:17:38.799627 ==
4656 12:17:38.800150 Dram Type= 6, Freq= 0, CH_1, rank 0
4657 12:17:38.806116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 12:17:38.806557 ==
4659 12:17:38.806928 RX Vref Scan: 1
4660 12:17:38.807290
4661 12:17:38.809172 RX Vref 0 -> 0, step: 1
4662 12:17:38.809784
4663 12:17:38.813036 RX Delay -179 -> 252, step: 8
4664 12:17:38.813477
4665 12:17:38.816293 Set Vref, RX VrefLevel [Byte0]: 51
4666 12:17:38.819466 [Byte1]: 51
4667 12:17:38.819891
4668 12:17:38.822635 Final RX Vref Byte 0 = 51 to rank0
4669 12:17:38.825685 Final RX Vref Byte 1 = 51 to rank0
4670 12:17:38.828862 Final RX Vref Byte 0 = 51 to rank1
4671 12:17:38.832606 Final RX Vref Byte 1 = 51 to rank1==
4672 12:17:38.835713 Dram Type= 6, Freq= 0, CH_1, rank 0
4673 12:17:38.838777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 12:17:38.842026 ==
4675 12:17:38.842504 DQS Delay:
4676 12:17:38.842883 DQS0 = 0, DQS1 = 0
4677 12:17:38.845839 DQM Delay:
4678 12:17:38.846315 DQM0 = 47, DQM1 = 36
4679 12:17:38.849056 DQ Delay:
4680 12:17:38.852136 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4681 12:17:38.852607 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4682 12:17:38.855289 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4683 12:17:38.862151 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4684 12:17:38.862607
4685 12:17:38.863128
4686 12:17:38.868780 [DQSOSCAuto] RK0, (LSB)MR18= 0x492e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4687 12:17:38.871782 CH1 RK0: MR19=808, MR18=492E
4688 12:17:38.878918 CH1_RK0: MR19=0x808, MR18=0x492E, DQSOSC=396, MR23=63, INC=167, DEC=111
4689 12:17:38.879359
4690 12:17:38.882025 ----->DramcWriteLeveling(PI) begin...
4691 12:17:38.882466 ==
4692 12:17:38.885038 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 12:17:38.888787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 12:17:38.889226 ==
4695 12:17:38.891887 Write leveling (Byte 0): 30 => 30
4696 12:17:38.895421 Write leveling (Byte 1): 30 => 30
4697 12:17:38.898292 DramcWriteLeveling(PI) end<-----
4698 12:17:38.898724
4699 12:17:38.899116 ==
4700 12:17:38.901760 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 12:17:38.905267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 12:17:38.905706 ==
4703 12:17:38.908305 [Gating] SW mode calibration
4704 12:17:38.915034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4705 12:17:38.921325 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4706 12:17:38.925230 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4707 12:17:38.931280 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4708 12:17:38.934948 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4709 12:17:38.937974 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 0)
4710 12:17:38.944750 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4711 12:17:38.947987 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4712 12:17:38.951031 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4713 12:17:38.958000 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4714 12:17:38.961085 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4715 12:17:38.964289 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4716 12:17:38.970766 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4717 12:17:38.974470 0 10 12 | B1->B0 | 3636 2727 | 0 0 | (0 0) (0 0)
4718 12:17:38.977625 0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
4719 12:17:38.984380 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 12:17:38.987296 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 12:17:38.991124 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 12:17:38.997775 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 12:17:39.000437 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4724 12:17:39.003970 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4725 12:17:39.010935 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4726 12:17:39.014137 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 12:17:39.017432 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 12:17:39.024185 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 12:17:39.027475 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 12:17:39.030684 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 12:17:39.037424 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 12:17:39.040568 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 12:17:39.043651 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 12:17:39.050078 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 12:17:39.053903 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 12:17:39.056999 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 12:17:39.060148 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 12:17:39.067132 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 12:17:39.070304 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 12:17:39.076662 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 12:17:39.079823 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4742 12:17:39.083375 Total UI for P1: 0, mck2ui 16
4743 12:17:39.086411 best dqsien dly found for B1: ( 0, 13, 10)
4744 12:17:39.090152 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4745 12:17:39.093171 Total UI for P1: 0, mck2ui 16
4746 12:17:39.096368 best dqsien dly found for B0: ( 0, 13, 12)
4747 12:17:39.100052 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4748 12:17:39.102981 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4749 12:17:39.103417
4750 12:17:39.106352 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4751 12:17:39.113069 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4752 12:17:39.113506 [Gating] SW calibration Done
4753 12:17:39.116168 ==
4754 12:17:39.116640 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 12:17:39.123026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 12:17:39.123558 ==
4757 12:17:39.123906 RX Vref Scan: 0
4758 12:17:39.124229
4759 12:17:39.126188 RX Vref 0 -> 0, step: 1
4760 12:17:39.126622
4761 12:17:39.129335 RX Delay -230 -> 252, step: 16
4762 12:17:39.133030 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4763 12:17:39.136134 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4764 12:17:39.142795 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4765 12:17:39.145807 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4766 12:17:39.149446 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4767 12:17:39.152464 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4768 12:17:39.159287 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4769 12:17:39.162285 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4770 12:17:39.166482 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4771 12:17:39.169105 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4772 12:17:39.172177 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4773 12:17:39.179389 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4774 12:17:39.182334 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4775 12:17:39.185426 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4776 12:17:39.189021 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4777 12:17:39.195180 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4778 12:17:39.195621 ==
4779 12:17:39.198774 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 12:17:39.201985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 12:17:39.202427 ==
4782 12:17:39.205532 DQS Delay:
4783 12:17:39.205965 DQS0 = 0, DQS1 = 0
4784 12:17:39.206309 DQM Delay:
4785 12:17:39.208375 DQM0 = 44, DQM1 = 36
4786 12:17:39.208866 DQ Delay:
4787 12:17:39.212112 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4788 12:17:39.215175 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33
4789 12:17:39.218302 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4790 12:17:39.221996 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4791 12:17:39.222463
4792 12:17:39.222836
4793 12:17:39.223164 ==
4794 12:17:39.225129 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 12:17:39.231327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 12:17:39.231785 ==
4797 12:17:39.232137
4798 12:17:39.232457
4799 12:17:39.232843 TX Vref Scan disable
4800 12:17:39.235173 == TX Byte 0 ==
4801 12:17:39.238476 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4802 12:17:39.245289 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4803 12:17:39.245781 == TX Byte 1 ==
4804 12:17:39.248397 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4805 12:17:39.254612 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4806 12:17:39.255043 ==
4807 12:17:39.257969 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 12:17:39.261536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 12:17:39.262169 ==
4810 12:17:39.262567
4811 12:17:39.262887
4812 12:17:39.264495 TX Vref Scan disable
4813 12:17:39.267774 == TX Byte 0 ==
4814 12:17:39.271492 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4815 12:17:39.274652 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4816 12:17:39.277790 == TX Byte 1 ==
4817 12:17:39.280962 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4818 12:17:39.284773 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4819 12:17:39.285205
4820 12:17:39.285545 [DATLAT]
4821 12:17:39.287819 Freq=600, CH1 RK1
4822 12:17:39.288249
4823 12:17:39.291112 DATLAT Default: 0x9
4824 12:17:39.291563 0, 0xFFFF, sum = 0
4825 12:17:39.294209 1, 0xFFFF, sum = 0
4826 12:17:39.294643 2, 0xFFFF, sum = 0
4827 12:17:39.297915 3, 0xFFFF, sum = 0
4828 12:17:39.298352 4, 0xFFFF, sum = 0
4829 12:17:39.300783 5, 0xFFFF, sum = 0
4830 12:17:39.301220 6, 0xFFFF, sum = 0
4831 12:17:39.304013 7, 0xFFFF, sum = 0
4832 12:17:39.304449 8, 0x0, sum = 1
4833 12:17:39.307543 9, 0x0, sum = 2
4834 12:17:39.307978 10, 0x0, sum = 3
4835 12:17:39.310578 11, 0x0, sum = 4
4836 12:17:39.311017 best_step = 9
4837 12:17:39.311355
4838 12:17:39.311669 ==
4839 12:17:39.314165 Dram Type= 6, Freq= 0, CH_1, rank 1
4840 12:17:39.317119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4841 12:17:39.317551 ==
4842 12:17:39.320826 RX Vref Scan: 0
4843 12:17:39.321260
4844 12:17:39.323926 RX Vref 0 -> 0, step: 1
4845 12:17:39.324394
4846 12:17:39.324791 RX Delay -195 -> 252, step: 8
4847 12:17:39.332181 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4848 12:17:39.335436 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4849 12:17:39.338564 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4850 12:17:39.342426 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4851 12:17:39.348762 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4852 12:17:39.351783 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4853 12:17:39.355463 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4854 12:17:39.358519 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4855 12:17:39.362282 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4856 12:17:39.368342 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4857 12:17:39.371917 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4858 12:17:39.375060 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4859 12:17:39.378320 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4860 12:17:39.384742 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4861 12:17:39.387802 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4862 12:17:39.390966 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4863 12:17:39.391093 ==
4864 12:17:39.394643 Dram Type= 6, Freq= 0, CH_1, rank 1
4865 12:17:39.397748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4866 12:17:39.401517 ==
4867 12:17:39.401603 DQS Delay:
4868 12:17:39.401669 DQS0 = 0, DQS1 = 0
4869 12:17:39.404509 DQM Delay:
4870 12:17:39.404630 DQM0 = 45, DQM1 = 37
4871 12:17:39.407597 DQ Delay:
4872 12:17:39.411207 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4873 12:17:39.414304 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =40
4874 12:17:39.417891 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4875 12:17:39.420892 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4876 12:17:39.420976
4877 12:17:39.421042
4878 12:17:39.427665 [DQSOSCAuto] RK1, (LSB)MR18= 0x3023, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
4879 12:17:39.430765 CH1 RK1: MR19=808, MR18=3023
4880 12:17:39.437137 CH1_RK1: MR19=0x808, MR18=0x3023, DQSOSC=400, MR23=63, INC=163, DEC=109
4881 12:17:39.440334 [RxdqsGatingPostProcess] freq 600
4882 12:17:39.443482 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4883 12:17:39.447284 Pre-setting of DQS Precalculation
4884 12:17:39.453429 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4885 12:17:39.460377 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4886 12:17:39.466686 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4887 12:17:39.466765
4888 12:17:39.466830
4889 12:17:39.470405 [Calibration Summary] 1200 Mbps
4890 12:17:39.470476 CH 0, Rank 0
4891 12:17:39.473535 SW Impedance : PASS
4892 12:17:39.476756 DUTY Scan : NO K
4893 12:17:39.476839 ZQ Calibration : PASS
4894 12:17:39.479910 Jitter Meter : NO K
4895 12:17:39.483303 CBT Training : PASS
4896 12:17:39.483386 Write leveling : PASS
4897 12:17:39.486502 RX DQS gating : PASS
4898 12:17:39.489675 RX DQ/DQS(RDDQC) : PASS
4899 12:17:39.489758 TX DQ/DQS : PASS
4900 12:17:39.493527 RX DATLAT : PASS
4901 12:17:39.496032 RX DQ/DQS(Engine): PASS
4902 12:17:39.496115 TX OE : NO K
4903 12:17:39.499808 All Pass.
4904 12:17:39.499917
4905 12:17:39.500004 CH 0, Rank 1
4906 12:17:39.502884 SW Impedance : PASS
4907 12:17:39.503024 DUTY Scan : NO K
4908 12:17:39.506013 ZQ Calibration : PASS
4909 12:17:39.509935 Jitter Meter : NO K
4910 12:17:39.510019 CBT Training : PASS
4911 12:17:39.512824 Write leveling : PASS
4912 12:17:39.515854 RX DQS gating : PASS
4913 12:17:39.515937 RX DQ/DQS(RDDQC) : PASS
4914 12:17:39.519559 TX DQ/DQS : PASS
4915 12:17:39.522588 RX DATLAT : PASS
4916 12:17:39.522698 RX DQ/DQS(Engine): PASS
4917 12:17:39.526306 TX OE : NO K
4918 12:17:39.526391 All Pass.
4919 12:17:39.526456
4920 12:17:39.529223 CH 1, Rank 0
4921 12:17:39.529300 SW Impedance : PASS
4922 12:17:39.532890 DUTY Scan : NO K
4923 12:17:39.536074 ZQ Calibration : PASS
4924 12:17:39.536145 Jitter Meter : NO K
4925 12:17:39.539247 CBT Training : PASS
4926 12:17:39.542513 Write leveling : PASS
4927 12:17:39.542582 RX DQS gating : PASS
4928 12:17:39.545659 RX DQ/DQS(RDDQC) : PASS
4929 12:17:39.548861 TX DQ/DQS : PASS
4930 12:17:39.548958 RX DATLAT : PASS
4931 12:17:39.552018 RX DQ/DQS(Engine): PASS
4932 12:17:39.555296 TX OE : NO K
4933 12:17:39.555370 All Pass.
4934 12:17:39.555431
4935 12:17:39.555491 CH 1, Rank 1
4936 12:17:39.559040 SW Impedance : PASS
4937 12:17:39.562273 DUTY Scan : NO K
4938 12:17:39.562357 ZQ Calibration : PASS
4939 12:17:39.565368 Jitter Meter : NO K
4940 12:17:39.568400 CBT Training : PASS
4941 12:17:39.568500 Write leveling : PASS
4942 12:17:39.572276 RX DQS gating : PASS
4943 12:17:39.572360 RX DQ/DQS(RDDQC) : PASS
4944 12:17:39.575385 TX DQ/DQS : PASS
4945 12:17:39.578478 RX DATLAT : PASS
4946 12:17:39.578562 RX DQ/DQS(Engine): PASS
4947 12:17:39.581774 TX OE : NO K
4948 12:17:39.581858 All Pass.
4949 12:17:39.581924
4950 12:17:39.585378 DramC Write-DBI off
4951 12:17:39.588550 PER_BANK_REFRESH: Hybrid Mode
4952 12:17:39.588647 TX_TRACKING: ON
4953 12:17:39.598290 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4954 12:17:39.601522 [FAST_K] Save calibration result to emmc
4955 12:17:39.604698 dramc_set_vcore_voltage set vcore to 662500
4956 12:17:39.608436 Read voltage for 933, 3
4957 12:17:39.608578 Vio18 = 0
4958 12:17:39.611495 Vcore = 662500
4959 12:17:39.611572 Vdram = 0
4960 12:17:39.611665 Vddq = 0
4961 12:17:39.611755 Vmddr = 0
4962 12:17:39.617906 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4963 12:17:39.624455 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4964 12:17:39.624588 MEM_TYPE=3, freq_sel=17
4965 12:17:39.628016 sv_algorithm_assistance_LP4_1600
4966 12:17:39.631028 ============ PULL DRAM RESETB DOWN ============
4967 12:17:39.637727 ========== PULL DRAM RESETB DOWN end =========
4968 12:17:39.640901 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4969 12:17:39.644659 ===================================
4970 12:17:39.647869 LPDDR4 DRAM CONFIGURATION
4971 12:17:39.651050 ===================================
4972 12:17:39.651122 EX_ROW_EN[0] = 0x0
4973 12:17:39.654539 EX_ROW_EN[1] = 0x0
4974 12:17:39.654930 LP4Y_EN = 0x0
4975 12:17:39.658441 WORK_FSP = 0x0
4976 12:17:39.658869 WL = 0x3
4977 12:17:39.661398 RL = 0x3
4978 12:17:39.664800 BL = 0x2
4979 12:17:39.665229 RPST = 0x0
4980 12:17:39.667887 RD_PRE = 0x0
4981 12:17:39.668316 WR_PRE = 0x1
4982 12:17:39.671885 WR_PST = 0x0
4983 12:17:39.672410 DBI_WR = 0x0
4984 12:17:39.674811 DBI_RD = 0x0
4985 12:17:39.675266 OTF = 0x1
4986 12:17:39.677799 ===================================
4987 12:17:39.681568 ===================================
4988 12:17:39.684775 ANA top config
4989 12:17:39.687944 ===================================
4990 12:17:39.688371 DLL_ASYNC_EN = 0
4991 12:17:39.691057 ALL_SLAVE_EN = 1
4992 12:17:39.694893 NEW_RANK_MODE = 1
4993 12:17:39.697988 DLL_IDLE_MODE = 1
4994 12:17:39.698420 LP45_APHY_COMB_EN = 1
4995 12:17:39.701337 TX_ODT_DIS = 1
4996 12:17:39.704329 NEW_8X_MODE = 1
4997 12:17:39.707452 ===================================
4998 12:17:39.710922 ===================================
4999 12:17:39.714205 data_rate = 1866
5000 12:17:39.717593 CKR = 1
5001 12:17:39.720628 DQ_P2S_RATIO = 8
5002 12:17:39.723979 ===================================
5003 12:17:39.727099 CA_P2S_RATIO = 8
5004 12:17:39.727182 DQ_CA_OPEN = 0
5005 12:17:39.730569 DQ_SEMI_OPEN = 0
5006 12:17:39.733683 CA_SEMI_OPEN = 0
5007 12:17:39.736872 CA_FULL_RATE = 0
5008 12:17:39.739995 DQ_CKDIV4_EN = 1
5009 12:17:39.743248 CA_CKDIV4_EN = 1
5010 12:17:39.743351 CA_PREDIV_EN = 0
5011 12:17:39.746884 PH8_DLY = 0
5012 12:17:39.750570 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5013 12:17:39.753527 DQ_AAMCK_DIV = 4
5014 12:17:39.756667 CA_AAMCK_DIV = 4
5015 12:17:39.759929 CA_ADMCK_DIV = 4
5016 12:17:39.760128 DQ_TRACK_CA_EN = 0
5017 12:17:39.763760 CA_PICK = 933
5018 12:17:39.767059 CA_MCKIO = 933
5019 12:17:39.770290 MCKIO_SEMI = 0
5020 12:17:39.773375 PLL_FREQ = 3732
5021 12:17:39.777103 DQ_UI_PI_RATIO = 32
5022 12:17:39.780502 CA_UI_PI_RATIO = 0
5023 12:17:39.783404 ===================================
5024 12:17:39.786669 ===================================
5025 12:17:39.786973 memory_type:LPDDR4
5026 12:17:39.789851 GP_NUM : 10
5027 12:17:39.793678 SRAM_EN : 1
5028 12:17:39.794069 MD32_EN : 0
5029 12:17:39.796390 ===================================
5030 12:17:39.799518 [ANA_INIT] >>>>>>>>>>>>>>
5031 12:17:39.802650 <<<<<< [CONFIGURE PHASE]: ANA_TX
5032 12:17:39.806480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5033 12:17:39.809499 ===================================
5034 12:17:39.812525 data_rate = 1866,PCW = 0X8f00
5035 12:17:39.816495 ===================================
5036 12:17:39.819728 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5037 12:17:39.823183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5038 12:17:39.829625 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5039 12:17:39.832497 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5040 12:17:39.836222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5041 12:17:39.839179 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5042 12:17:39.842849 [ANA_INIT] flow start
5043 12:17:39.846083 [ANA_INIT] PLL >>>>>>>>
5044 12:17:39.846326 [ANA_INIT] PLL <<<<<<<<
5045 12:17:39.849352 [ANA_INIT] MIDPI >>>>>>>>
5046 12:17:39.852435 [ANA_INIT] MIDPI <<<<<<<<
5047 12:17:39.856331 [ANA_INIT] DLL >>>>>>>>
5048 12:17:39.856762 [ANA_INIT] flow end
5049 12:17:39.859510 ============ LP4 DIFF to SE enter ============
5050 12:17:39.865852 ============ LP4 DIFF to SE exit ============
5051 12:17:39.866279 [ANA_INIT] <<<<<<<<<<<<<
5052 12:17:39.869474 [Flow] Enable top DCM control >>>>>
5053 12:17:39.872638 [Flow] Enable top DCM control <<<<<
5054 12:17:39.875934 Enable DLL master slave shuffle
5055 12:17:39.883164 ==============================================================
5056 12:17:39.883698 Gating Mode config
5057 12:17:39.889286 ==============================================================
5058 12:17:39.892677 Config description:
5059 12:17:39.902506 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5060 12:17:39.908701 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5061 12:17:39.912483 SELPH_MODE 0: By rank 1: By Phase
5062 12:17:39.918842 ==============================================================
5063 12:17:39.921931 GAT_TRACK_EN = 1
5064 12:17:39.925381 RX_GATING_MODE = 2
5065 12:17:39.925815 RX_GATING_TRACK_MODE = 2
5066 12:17:39.928506 SELPH_MODE = 1
5067 12:17:39.932155 PICG_EARLY_EN = 1
5068 12:17:39.935206 VALID_LAT_VALUE = 1
5069 12:17:39.941808 ==============================================================
5070 12:17:39.945235 Enter into Gating configuration >>>>
5071 12:17:39.948748 Exit from Gating configuration <<<<
5072 12:17:39.951881 Enter into DVFS_PRE_config >>>>>
5073 12:17:39.961846 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5074 12:17:39.965042 Exit from DVFS_PRE_config <<<<<
5075 12:17:39.968252 Enter into PICG configuration >>>>
5076 12:17:39.971494 Exit from PICG configuration <<<<
5077 12:17:39.975037 [RX_INPUT] configuration >>>>>
5078 12:17:39.978325 [RX_INPUT] configuration <<<<<
5079 12:17:39.981265 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5080 12:17:39.988050 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5081 12:17:39.994391 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5082 12:17:40.001343 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5083 12:17:40.007900 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5084 12:17:40.011075 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5085 12:17:40.017984 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5086 12:17:40.021277 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5087 12:17:40.024593 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5088 12:17:40.027476 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5089 12:17:40.033965 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5090 12:17:40.037000 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5091 12:17:40.040194 ===================================
5092 12:17:40.043887 LPDDR4 DRAM CONFIGURATION
5093 12:17:40.046948 ===================================
5094 12:17:40.047087 EX_ROW_EN[0] = 0x0
5095 12:17:40.050144 EX_ROW_EN[1] = 0x0
5096 12:17:40.050226 LP4Y_EN = 0x0
5097 12:17:40.053311 WORK_FSP = 0x0
5098 12:17:40.053420 WL = 0x3
5099 12:17:40.056579 RL = 0x3
5100 12:17:40.060450 BL = 0x2
5101 12:17:40.060584 RPST = 0x0
5102 12:17:40.063669 RD_PRE = 0x0
5103 12:17:40.063781 WR_PRE = 0x1
5104 12:17:40.066979 WR_PST = 0x0
5105 12:17:40.067068 DBI_WR = 0x0
5106 12:17:40.070056 DBI_RD = 0x0
5107 12:17:40.070144 OTF = 0x1
5108 12:17:40.073213 ===================================
5109 12:17:40.076875 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5110 12:17:40.083340 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5111 12:17:40.086488 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5112 12:17:40.090235 ===================================
5113 12:17:40.093344 LPDDR4 DRAM CONFIGURATION
5114 12:17:40.096394 ===================================
5115 12:17:40.096537 EX_ROW_EN[0] = 0x10
5116 12:17:40.099556 EX_ROW_EN[1] = 0x0
5117 12:17:40.102782 LP4Y_EN = 0x0
5118 12:17:40.102935 WORK_FSP = 0x0
5119 12:17:40.106531 WL = 0x3
5120 12:17:40.106724 RL = 0x3
5121 12:17:40.109714 BL = 0x2
5122 12:17:40.109916 RPST = 0x0
5123 12:17:40.112780 RD_PRE = 0x0
5124 12:17:40.113022 WR_PRE = 0x1
5125 12:17:40.116811 WR_PST = 0x0
5126 12:17:40.117224 DBI_WR = 0x0
5127 12:17:40.119963 DBI_RD = 0x0
5128 12:17:40.120380 OTF = 0x1
5129 12:17:40.123305 ===================================
5130 12:17:40.129590 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5131 12:17:40.134185 nWR fixed to 30
5132 12:17:40.137186 [ModeRegInit_LP4] CH0 RK0
5133 12:17:40.137792 [ModeRegInit_LP4] CH0 RK1
5134 12:17:40.140822 [ModeRegInit_LP4] CH1 RK0
5135 12:17:40.144043 [ModeRegInit_LP4] CH1 RK1
5136 12:17:40.144466 match AC timing 9
5137 12:17:40.150985 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5138 12:17:40.153637 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5139 12:17:40.157245 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5140 12:17:40.163789 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5141 12:17:40.166954 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5142 12:17:40.167457 ==
5143 12:17:40.169965 Dram Type= 6, Freq= 0, CH_0, rank 0
5144 12:17:40.173969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 12:17:40.174464 ==
5146 12:17:40.180348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5147 12:17:40.186951 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5148 12:17:40.190321 [CA 0] Center 38 (7~69) winsize 63
5149 12:17:40.193683 [CA 1] Center 37 (7~68) winsize 62
5150 12:17:40.196876 [CA 2] Center 34 (4~65) winsize 62
5151 12:17:40.199777 [CA 3] Center 35 (5~65) winsize 61
5152 12:17:40.202881 [CA 4] Center 33 (3~64) winsize 62
5153 12:17:40.206621 [CA 5] Center 33 (3~64) winsize 62
5154 12:17:40.207088
5155 12:17:40.209757 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5156 12:17:40.210403
5157 12:17:40.212848 [CATrainingPosCal] consider 1 rank data
5158 12:17:40.216684 u2DelayCellTimex100 = 270/100 ps
5159 12:17:40.220165 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5160 12:17:40.223255 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5161 12:17:40.226144 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5162 12:17:40.233000 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5163 12:17:40.236105 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5164 12:17:40.239202 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5165 12:17:40.239627
5166 12:17:40.242388 CA PerBit enable=1, Macro0, CA PI delay=33
5167 12:17:40.242816
5168 12:17:40.245890 [CBTSetCACLKResult] CA Dly = 33
5169 12:17:40.246393 CS Dly: 7 (0~38)
5170 12:17:40.246749 ==
5171 12:17:40.249001 Dram Type= 6, Freq= 0, CH_0, rank 1
5172 12:17:40.255742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 12:17:40.256180 ==
5174 12:17:40.259384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5175 12:17:40.266016 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5176 12:17:40.269138 [CA 0] Center 37 (7~68) winsize 62
5177 12:17:40.272317 [CA 1] Center 37 (7~68) winsize 62
5178 12:17:40.275990 [CA 2] Center 34 (4~65) winsize 62
5179 12:17:40.279588 [CA 3] Center 34 (4~65) winsize 62
5180 12:17:40.282444 [CA 4] Center 33 (3~64) winsize 62
5181 12:17:40.285453 [CA 5] Center 33 (3~63) winsize 61
5182 12:17:40.285891
5183 12:17:40.289083 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5184 12:17:40.289519
5185 12:17:40.292245 [CATrainingPosCal] consider 2 rank data
5186 12:17:40.295438 u2DelayCellTimex100 = 270/100 ps
5187 12:17:40.299088 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5188 12:17:40.304951 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5189 12:17:40.308818 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5190 12:17:40.311966 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5191 12:17:40.315187 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5192 12:17:40.318486 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5193 12:17:40.318916
5194 12:17:40.322115 CA PerBit enable=1, Macro0, CA PI delay=33
5195 12:17:40.322663
5196 12:17:40.325047 [CBTSetCACLKResult] CA Dly = 33
5197 12:17:40.328247 CS Dly: 7 (0~39)
5198 12:17:40.328762
5199 12:17:40.331385 ----->DramcWriteLeveling(PI) begin...
5200 12:17:40.331841 ==
5201 12:17:40.335077 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 12:17:40.338270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 12:17:40.338719 ==
5204 12:17:40.341322 Write leveling (Byte 0): 33 => 33
5205 12:17:40.345088 Write leveling (Byte 1): 29 => 29
5206 12:17:40.348189 DramcWriteLeveling(PI) end<-----
5207 12:17:40.348673
5208 12:17:40.349114 ==
5209 12:17:40.351137 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 12:17:40.354815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 12:17:40.355307 ==
5212 12:17:40.357889 [Gating] SW mode calibration
5213 12:17:40.364407 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5214 12:17:40.371509 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5215 12:17:40.374563 0 14 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5216 12:17:40.377580 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5217 12:17:40.384496 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5218 12:17:40.387762 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5219 12:17:40.390751 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5220 12:17:40.397845 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5221 12:17:40.401059 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5222 12:17:40.404778 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
5223 12:17:40.411035 0 15 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
5224 12:17:40.414183 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5225 12:17:40.417865 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5226 12:17:40.424256 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5227 12:17:40.427372 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5228 12:17:40.430909 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5229 12:17:40.437467 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5230 12:17:40.440754 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5231 12:17:40.443934 1 0 0 | B1->B0 | 3232 4141 | 0 0 | (0 0) (0 0)
5232 12:17:40.450257 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5233 12:17:40.454043 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 12:17:40.456435 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 12:17:40.463192 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5236 12:17:40.466922 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5237 12:17:40.469849 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5238 12:17:40.476401 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5239 12:17:40.480197 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5240 12:17:40.483422 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 12:17:40.489541 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 12:17:40.493357 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 12:17:40.496648 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 12:17:40.503086 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 12:17:40.506196 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 12:17:40.509814 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 12:17:40.516925 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 12:17:40.520234 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 12:17:40.523448 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 12:17:40.529605 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 12:17:40.532836 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 12:17:40.536109 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 12:17:40.542845 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 12:17:40.545833 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5255 12:17:40.549662 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5256 12:17:40.556367 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5257 12:17:40.556463 Total UI for P1: 0, mck2ui 16
5258 12:17:40.562510 best dqsien dly found for B0: ( 1, 2, 30)
5259 12:17:40.562616 Total UI for P1: 0, mck2ui 16
5260 12:17:40.569194 best dqsien dly found for B1: ( 1, 3, 0)
5261 12:17:40.572862 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5262 12:17:40.575818 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5263 12:17:40.575957
5264 12:17:40.579643 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5265 12:17:40.582537 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5266 12:17:40.586247 [Gating] SW calibration Done
5267 12:17:40.586616 ==
5268 12:17:40.589639 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 12:17:40.592835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 12:17:40.593263 ==
5271 12:17:40.595741 RX Vref Scan: 0
5272 12:17:40.596193
5273 12:17:40.596586 RX Vref 0 -> 0, step: 1
5274 12:17:40.596918
5275 12:17:40.599051 RX Delay -80 -> 252, step: 8
5276 12:17:40.602167 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5277 12:17:40.608963 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5278 12:17:40.612630 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5279 12:17:40.615887 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5280 12:17:40.618914 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5281 12:17:40.622066 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5282 12:17:40.625087 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5283 12:17:40.631830 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5284 12:17:40.635140 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5285 12:17:40.638270 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5286 12:17:40.641292 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5287 12:17:40.648283 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5288 12:17:40.651455 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5289 12:17:40.654537 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5290 12:17:40.658285 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5291 12:17:40.661313 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5292 12:17:40.661398 ==
5293 12:17:40.664284 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 12:17:40.670996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 12:17:40.671107 ==
5296 12:17:40.671203 DQS Delay:
5297 12:17:40.674192 DQS0 = 0, DQS1 = 0
5298 12:17:40.674281 DQM Delay:
5299 12:17:40.677320 DQM0 = 97, DQM1 = 85
5300 12:17:40.677403 DQ Delay:
5301 12:17:40.680783 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5302 12:17:40.684327 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5303 12:17:40.687856 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5304 12:17:40.690938 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5305 12:17:40.691023
5306 12:17:40.691090
5307 12:17:40.691152 ==
5308 12:17:40.694182 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 12:17:40.697388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 12:17:40.697473 ==
5311 12:17:40.697541
5312 12:17:40.697602
5313 12:17:40.701071 TX Vref Scan disable
5314 12:17:40.704097 == TX Byte 0 ==
5315 12:17:40.707290 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5316 12:17:40.710501 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5317 12:17:40.714084 == TX Byte 1 ==
5318 12:17:40.717278 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5319 12:17:40.720410 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5320 12:17:40.720494 ==
5321 12:17:40.724109 Dram Type= 6, Freq= 0, CH_0, rank 0
5322 12:17:40.730454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 12:17:40.730540 ==
5324 12:17:40.730607
5325 12:17:40.730669
5326 12:17:40.730728 TX Vref Scan disable
5327 12:17:40.734299 == TX Byte 0 ==
5328 12:17:40.738020 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5329 12:17:40.744388 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5330 12:17:40.744474 == TX Byte 1 ==
5331 12:17:40.747593 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5332 12:17:40.754567 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5333 12:17:40.754652
5334 12:17:40.754718 [DATLAT]
5335 12:17:40.754779 Freq=933, CH0 RK0
5336 12:17:40.754839
5337 12:17:40.757778 DATLAT Default: 0xd
5338 12:17:40.757862 0, 0xFFFF, sum = 0
5339 12:17:40.760946 1, 0xFFFF, sum = 0
5340 12:17:40.763931 2, 0xFFFF, sum = 0
5341 12:17:40.764016 3, 0xFFFF, sum = 0
5342 12:17:40.767147 4, 0xFFFF, sum = 0
5343 12:17:40.767232 5, 0xFFFF, sum = 0
5344 12:17:40.770692 6, 0xFFFF, sum = 0
5345 12:17:40.770772 7, 0xFFFF, sum = 0
5346 12:17:40.773894 8, 0xFFFF, sum = 0
5347 12:17:40.773969 9, 0xFFFF, sum = 0
5348 12:17:40.777505 10, 0x0, sum = 1
5349 12:17:40.777591 11, 0x0, sum = 2
5350 12:17:40.780457 12, 0x0, sum = 3
5351 12:17:40.780596 13, 0x0, sum = 4
5352 12:17:40.780664 best_step = 11
5353 12:17:40.784175
5354 12:17:40.784258 ==
5355 12:17:40.787297 Dram Type= 6, Freq= 0, CH_0, rank 0
5356 12:17:40.790863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 12:17:40.790949 ==
5358 12:17:40.791016 RX Vref Scan: 1
5359 12:17:40.791078
5360 12:17:40.793880 RX Vref 0 -> 0, step: 1
5361 12:17:40.793963
5362 12:17:40.797234 RX Delay -61 -> 252, step: 4
5363 12:17:40.797321
5364 12:17:40.800780 Set Vref, RX VrefLevel [Byte0]: 61
5365 12:17:40.803872 [Byte1]: 55
5366 12:17:40.806989
5367 12:17:40.807071 Final RX Vref Byte 0 = 61 to rank0
5368 12:17:40.810165 Final RX Vref Byte 1 = 55 to rank0
5369 12:17:40.813889 Final RX Vref Byte 0 = 61 to rank1
5370 12:17:40.817050 Final RX Vref Byte 1 = 55 to rank1==
5371 12:17:40.820246 Dram Type= 6, Freq= 0, CH_0, rank 0
5372 12:17:40.826570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 12:17:40.826657 ==
5374 12:17:40.826722 DQS Delay:
5375 12:17:40.829922 DQS0 = 0, DQS1 = 0
5376 12:17:40.830010 DQM Delay:
5377 12:17:40.830079 DQM0 = 97, DQM1 = 86
5378 12:17:40.833672 DQ Delay:
5379 12:17:40.836763 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5380 12:17:40.839828 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5381 12:17:40.843695 DQ8 =78, DQ9 =78, DQ10 =86, DQ11 =84
5382 12:17:40.847050 DQ12 =90, DQ13 =88, DQ14 =96, DQ15 =92
5383 12:17:40.847161
5384 12:17:40.847248
5385 12:17:40.853516 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5386 12:17:40.856539 CH0 RK0: MR19=505, MR18=2A11
5387 12:17:40.863434 CH0_RK0: MR19=0x505, MR18=0x2A11, DQSOSC=408, MR23=63, INC=65, DEC=43
5388 12:17:40.863620
5389 12:17:40.866561 ----->DramcWriteLeveling(PI) begin...
5390 12:17:40.866737 ==
5391 12:17:40.870019 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 12:17:40.873630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 12:17:40.874197 ==
5394 12:17:40.876701 Write leveling (Byte 0): 31 => 31
5395 12:17:40.879854 Write leveling (Byte 1): 31 => 31
5396 12:17:40.883457 DramcWriteLeveling(PI) end<-----
5397 12:17:40.883958
5398 12:17:40.884286 ==
5399 12:17:40.886823 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 12:17:40.889912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 12:17:40.893020 ==
5402 12:17:40.893451 [Gating] SW mode calibration
5403 12:17:40.902801 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5404 12:17:40.906481 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5405 12:17:40.909507 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5406 12:17:40.915813 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 12:17:40.919400 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 12:17:40.923106 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 12:17:40.929483 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 12:17:40.932664 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 12:17:40.935929 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5412 12:17:40.942143 0 14 28 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (1 0)
5413 12:17:40.945926 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
5414 12:17:40.952141 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 12:17:40.955863 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 12:17:40.958971 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 12:17:40.965209 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 12:17:40.968578 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 12:17:40.971716 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 12:17:40.978646 0 15 28 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
5421 12:17:40.982079 1 0 0 | B1->B0 | 3636 3d3d | 0 0 | (0 0) (1 1)
5422 12:17:40.985086 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 12:17:40.991752 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 12:17:40.995158 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 12:17:40.998032 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 12:17:41.004633 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 12:17:41.008204 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 12:17:41.011242 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5429 12:17:41.018282 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5430 12:17:41.021282 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 12:17:41.024416 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 12:17:41.030892 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 12:17:41.034769 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 12:17:41.038115 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 12:17:41.044348 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 12:17:41.047646 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 12:17:41.050804 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 12:17:41.057770 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 12:17:41.060925 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 12:17:41.063965 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 12:17:41.070483 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 12:17:41.074341 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 12:17:41.076997 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 12:17:41.083838 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5445 12:17:41.086927 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5446 12:17:41.090530 Total UI for P1: 0, mck2ui 16
5447 12:17:41.093472 best dqsien dly found for B0: ( 1, 2, 28)
5448 12:17:41.096997 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5449 12:17:41.099960 Total UI for P1: 0, mck2ui 16
5450 12:17:41.103547 best dqsien dly found for B1: ( 1, 2, 30)
5451 12:17:41.106777 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5452 12:17:41.110075 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5453 12:17:41.110511
5454 12:17:41.113200 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5455 12:17:41.120127 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5456 12:17:41.120601 [Gating] SW calibration Done
5457 12:17:41.123442 ==
5458 12:17:41.126388 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 12:17:41.130020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 12:17:41.130460 ==
5461 12:17:41.130807 RX Vref Scan: 0
5462 12:17:41.131128
5463 12:17:41.133195 RX Vref 0 -> 0, step: 1
5464 12:17:41.133626
5465 12:17:41.136349 RX Delay -80 -> 252, step: 8
5466 12:17:41.140044 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5467 12:17:41.143476 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5468 12:17:41.146564 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5469 12:17:41.153062 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5470 12:17:41.156209 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5471 12:17:41.160157 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5472 12:17:41.163049 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5473 12:17:41.166120 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5474 12:17:41.169242 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5475 12:17:41.176397 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5476 12:17:41.179153 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5477 12:17:41.182382 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5478 12:17:41.185564 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5479 12:17:41.189534 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5480 12:17:41.195384 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5481 12:17:41.199042 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5482 12:17:41.199126 ==
5483 12:17:41.202045 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 12:17:41.205634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 12:17:41.205718 ==
5486 12:17:41.208637 DQS Delay:
5487 12:17:41.208720 DQS0 = 0, DQS1 = 0
5488 12:17:41.208789 DQM Delay:
5489 12:17:41.212270 DQM0 = 98, DQM1 = 89
5490 12:17:41.212354 DQ Delay:
5491 12:17:41.215045 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5492 12:17:41.218651 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5493 12:17:41.221916 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5494 12:17:41.225022 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5495 12:17:41.225111
5496 12:17:41.225180
5497 12:17:41.225243 ==
5498 12:17:41.228296 Dram Type= 6, Freq= 0, CH_0, rank 1
5499 12:17:41.235704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 12:17:41.235892 ==
5501 12:17:41.235986
5502 12:17:41.236068
5503 12:17:41.236144 TX Vref Scan disable
5504 12:17:41.238908 == TX Byte 0 ==
5505 12:17:41.242014 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5506 12:17:41.249008 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5507 12:17:41.249434 == TX Byte 1 ==
5508 12:17:41.252344 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5509 12:17:41.259423 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5510 12:17:41.259957 ==
5511 12:17:41.262689 Dram Type= 6, Freq= 0, CH_0, rank 1
5512 12:17:41.265608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 12:17:41.266046 ==
5514 12:17:41.266387
5515 12:17:41.266707
5516 12:17:41.268694 TX Vref Scan disable
5517 12:17:41.269124 == TX Byte 0 ==
5518 12:17:41.275188 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5519 12:17:41.278943 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5520 12:17:41.279419 == TX Byte 1 ==
5521 12:17:41.285216 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5522 12:17:41.288369 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5523 12:17:41.288877
5524 12:17:41.289241 [DATLAT]
5525 12:17:41.292072 Freq=933, CH0 RK1
5526 12:17:41.292505
5527 12:17:41.292950 DATLAT Default: 0xb
5528 12:17:41.295176 0, 0xFFFF, sum = 0
5529 12:17:41.295616 1, 0xFFFF, sum = 0
5530 12:17:41.298963 2, 0xFFFF, sum = 0
5531 12:17:41.301789 3, 0xFFFF, sum = 0
5532 12:17:41.302230 4, 0xFFFF, sum = 0
5533 12:17:41.305262 5, 0xFFFF, sum = 0
5534 12:17:41.305706 6, 0xFFFF, sum = 0
5535 12:17:41.308306 7, 0xFFFF, sum = 0
5536 12:17:41.308905 8, 0xFFFF, sum = 0
5537 12:17:41.312065 9, 0xFFFF, sum = 0
5538 12:17:41.312553 10, 0x0, sum = 1
5539 12:17:41.314872 11, 0x0, sum = 2
5540 12:17:41.315459 12, 0x0, sum = 3
5541 12:17:41.318616 13, 0x0, sum = 4
5542 12:17:41.319163 best_step = 11
5543 12:17:41.319511
5544 12:17:41.319836 ==
5545 12:17:41.321440 Dram Type= 6, Freq= 0, CH_0, rank 1
5546 12:17:41.324818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 12:17:41.325255 ==
5548 12:17:41.328360 RX Vref Scan: 0
5549 12:17:41.328834
5550 12:17:41.331709 RX Vref 0 -> 0, step: 1
5551 12:17:41.332217
5552 12:17:41.332771 RX Delay -61 -> 252, step: 4
5553 12:17:41.339301 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5554 12:17:41.342569 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5555 12:17:41.345736 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5556 12:17:41.349480 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5557 12:17:41.352708 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5558 12:17:41.358980 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5559 12:17:41.362083 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5560 12:17:41.365336 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5561 12:17:41.368794 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5562 12:17:41.372482 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5563 12:17:41.378854 iDelay=203, Bit 10, Center 88 (-9 ~ 186) 196
5564 12:17:41.381955 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5565 12:17:41.385160 iDelay=203, Bit 12, Center 90 (-5 ~ 186) 192
5566 12:17:41.388433 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5567 12:17:41.392099 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5568 12:17:41.398200 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5569 12:17:41.398814 ==
5570 12:17:41.401912 Dram Type= 6, Freq= 0, CH_0, rank 1
5571 12:17:41.405079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 12:17:41.405851 ==
5573 12:17:41.406385 DQS Delay:
5574 12:17:41.408409 DQS0 = 0, DQS1 = 0
5575 12:17:41.408907 DQM Delay:
5576 12:17:41.411517 DQM0 = 95, DQM1 = 87
5577 12:17:41.411948 DQ Delay:
5578 12:17:41.415170 DQ0 =92, DQ1 =98, DQ2 =88, DQ3 =94
5579 12:17:41.418177 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5580 12:17:41.421744 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =80
5581 12:17:41.424747 DQ12 =90, DQ13 =92, DQ14 =96, DQ15 =92
5582 12:17:41.425389
5583 12:17:41.425763
5584 12:17:41.434862 [DQSOSCAuto] RK1, (LSB)MR18= 0x23f4, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 410 ps
5585 12:17:41.435300 CH0 RK1: MR19=504, MR18=23F4
5586 12:17:41.441178 CH0_RK1: MR19=0x504, MR18=0x23F4, DQSOSC=410, MR23=63, INC=64, DEC=42
5587 12:17:41.444961 [RxdqsGatingPostProcess] freq 933
5588 12:17:41.451382 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5589 12:17:41.454528 best DQS0 dly(2T, 0.5T) = (0, 10)
5590 12:17:41.457589 best DQS1 dly(2T, 0.5T) = (0, 11)
5591 12:17:41.460878 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5592 12:17:41.464374 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5593 12:17:41.467430 best DQS0 dly(2T, 0.5T) = (0, 10)
5594 12:17:41.467515 best DQS1 dly(2T, 0.5T) = (0, 10)
5595 12:17:41.470704 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5596 12:17:41.473868 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5597 12:17:41.476962 Pre-setting of DQS Precalculation
5598 12:17:41.483360 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5599 12:17:41.483444 ==
5600 12:17:41.487106 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 12:17:41.490242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 12:17:41.490327 ==
5603 12:17:41.497166 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5604 12:17:41.503528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5605 12:17:41.506648 [CA 0] Center 36 (6~67) winsize 62
5606 12:17:41.510272 [CA 1] Center 36 (6~67) winsize 62
5607 12:17:41.513188 [CA 2] Center 34 (4~65) winsize 62
5608 12:17:41.516184 [CA 3] Center 33 (3~64) winsize 62
5609 12:17:41.519775 [CA 4] Center 34 (4~64) winsize 61
5610 12:17:41.522723 [CA 5] Center 33 (3~64) winsize 62
5611 12:17:41.522826
5612 12:17:41.526271 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5613 12:17:41.526375
5614 12:17:41.529947 [CATrainingPosCal] consider 1 rank data
5615 12:17:41.532847 u2DelayCellTimex100 = 270/100 ps
5616 12:17:41.536363 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5617 12:17:41.539365 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5618 12:17:41.542739 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5619 12:17:41.546559 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5620 12:17:41.549544 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5621 12:17:41.555994 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5622 12:17:41.556108
5623 12:17:41.559172 CA PerBit enable=1, Macro0, CA PI delay=33
5624 12:17:41.559321
5625 12:17:41.562881 [CBTSetCACLKResult] CA Dly = 33
5626 12:17:41.563007 CS Dly: 6 (0~37)
5627 12:17:41.563107 ==
5628 12:17:41.566035 Dram Type= 6, Freq= 0, CH_1, rank 1
5629 12:17:41.570106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 12:17:41.573190 ==
5631 12:17:41.576568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5632 12:17:41.583188 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5633 12:17:41.586914 [CA 0] Center 36 (6~67) winsize 62
5634 12:17:41.589718 [CA 1] Center 36 (6~67) winsize 62
5635 12:17:41.592858 [CA 2] Center 34 (4~65) winsize 62
5636 12:17:41.596032 [CA 3] Center 33 (3~64) winsize 62
5637 12:17:41.599098 [CA 4] Center 34 (3~65) winsize 63
5638 12:17:41.603135 [CA 5] Center 33 (3~64) winsize 62
5639 12:17:41.603568
5640 12:17:41.606198 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5641 12:17:41.606635
5642 12:17:41.609353 [CATrainingPosCal] consider 2 rank data
5643 12:17:41.612506 u2DelayCellTimex100 = 270/100 ps
5644 12:17:41.615745 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5645 12:17:41.619151 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5646 12:17:41.622623 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5647 12:17:41.629301 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5648 12:17:41.632405 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5649 12:17:41.636065 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5650 12:17:41.636494
5651 12:17:41.638964 CA PerBit enable=1, Macro0, CA PI delay=33
5652 12:17:41.639404
5653 12:17:41.642489 [CBTSetCACLKResult] CA Dly = 33
5654 12:17:41.642924 CS Dly: 7 (0~39)
5655 12:17:41.643260
5656 12:17:41.646174 ----->DramcWriteLeveling(PI) begin...
5657 12:17:41.649254 ==
5658 12:17:41.649678 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 12:17:41.655511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 12:17:41.655939 ==
5661 12:17:41.658766 Write leveling (Byte 0): 27 => 27
5662 12:17:41.662619 Write leveling (Byte 1): 28 => 28
5663 12:17:41.665533 DramcWriteLeveling(PI) end<-----
5664 12:17:41.665959
5665 12:17:41.666292 ==
5666 12:17:41.668696 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 12:17:41.672419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 12:17:41.672895 ==
5669 12:17:41.675717 [Gating] SW mode calibration
5670 12:17:41.682458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5671 12:17:41.688463 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5672 12:17:41.691843 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5673 12:17:41.695632 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5674 12:17:41.701942 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5675 12:17:41.705585 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5676 12:17:41.708694 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5677 12:17:41.711881 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5678 12:17:41.718621 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
5679 12:17:41.721820 0 14 28 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (1 1)
5680 12:17:41.728596 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5681 12:17:41.731480 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5682 12:17:41.735128 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5683 12:17:41.741723 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5684 12:17:41.745135 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5685 12:17:41.748046 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5686 12:17:41.754952 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5687 12:17:41.758191 0 15 28 | B1->B0 | 3131 3838 | 0 0 | (0 0) (0 0)
5688 12:17:41.761106 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5689 12:17:41.767828 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 12:17:41.770871 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5691 12:17:41.774713 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 12:17:41.781473 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5693 12:17:41.784337 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5694 12:17:41.787416 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5695 12:17:41.794354 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 12:17:41.797352 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 12:17:41.800645 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 12:17:41.807531 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 12:17:41.810562 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 12:17:41.813787 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 12:17:41.820371 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 12:17:41.823513 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 12:17:41.827423 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 12:17:41.833809 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 12:17:41.836884 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 12:17:41.840405 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 12:17:41.847011 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 12:17:41.849917 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 12:17:41.853409 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 12:17:41.857139 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5711 12:17:41.863691 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5712 12:17:41.866757 Total UI for P1: 0, mck2ui 16
5713 12:17:41.869799 best dqsien dly found for B0: ( 1, 2, 24)
5714 12:17:41.873480 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5715 12:17:41.876703 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5716 12:17:41.880292 Total UI for P1: 0, mck2ui 16
5717 12:17:41.883556 best dqsien dly found for B1: ( 1, 2, 30)
5718 12:17:41.889987 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5719 12:17:41.893327 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5720 12:17:41.893757
5721 12:17:41.896480 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5722 12:17:41.899681 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5723 12:17:41.902849 [Gating] SW calibration Done
5724 12:17:41.903281 ==
5725 12:17:41.906429 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 12:17:41.909405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 12:17:41.909929 ==
5728 12:17:41.912588 RX Vref Scan: 0
5729 12:17:41.913021
5730 12:17:41.913353 RX Vref 0 -> 0, step: 1
5731 12:17:41.913667
5732 12:17:41.916391 RX Delay -80 -> 252, step: 8
5733 12:17:41.919422 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5734 12:17:41.926201 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5735 12:17:41.929369 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5736 12:17:41.932876 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5737 12:17:41.935883 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5738 12:17:41.938901 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5739 12:17:41.942357 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5740 12:17:41.948833 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5741 12:17:41.952564 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5742 12:17:41.955316 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5743 12:17:41.958957 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5744 12:17:41.962497 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5745 12:17:41.968970 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5746 12:17:41.971995 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5747 12:17:41.975336 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5748 12:17:41.979012 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5749 12:17:41.979455 ==
5750 12:17:41.982426 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 12:17:41.988654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 12:17:41.989204 ==
5753 12:17:41.989557 DQS Delay:
5754 12:17:41.989872 DQS0 = 0, DQS1 = 0
5755 12:17:41.992327 DQM Delay:
5756 12:17:41.992801 DQM0 = 102, DQM1 = 90
5757 12:17:41.995619 DQ Delay:
5758 12:17:41.998520 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =103
5759 12:17:42.002186 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5760 12:17:42.005275 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5761 12:17:42.008641 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5762 12:17:42.009172
5763 12:17:42.009511
5764 12:17:42.009823 ==
5765 12:17:42.011507 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 12:17:42.014732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 12:17:42.015187 ==
5768 12:17:42.015519
5769 12:17:42.015829
5770 12:17:42.018530 TX Vref Scan disable
5771 12:17:42.021770 == TX Byte 0 ==
5772 12:17:42.024926 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5773 12:17:42.028182 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5774 12:17:42.031269 == TX Byte 1 ==
5775 12:17:42.034809 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5776 12:17:42.037816 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5777 12:17:42.038250 ==
5778 12:17:42.041369 Dram Type= 6, Freq= 0, CH_1, rank 0
5779 12:17:42.044446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 12:17:42.047897 ==
5781 12:17:42.048332
5782 12:17:42.048728
5783 12:17:42.049056 TX Vref Scan disable
5784 12:17:42.051379 == TX Byte 0 ==
5785 12:17:42.055441 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5786 12:17:42.061573 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5787 12:17:42.062036 == TX Byte 1 ==
5788 12:17:42.064562 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5789 12:17:42.071642 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5790 12:17:42.072169
5791 12:17:42.072650 [DATLAT]
5792 12:17:42.073032 Freq=933, CH1 RK0
5793 12:17:42.073381
5794 12:17:42.074383 DATLAT Default: 0xd
5795 12:17:42.074816 0, 0xFFFF, sum = 0
5796 12:17:42.078165 1, 0xFFFF, sum = 0
5797 12:17:42.081422 2, 0xFFFF, sum = 0
5798 12:17:42.081949 3, 0xFFFF, sum = 0
5799 12:17:42.084440 4, 0xFFFF, sum = 0
5800 12:17:42.084923 5, 0xFFFF, sum = 0
5801 12:17:42.087590 6, 0xFFFF, sum = 0
5802 12:17:42.088028 7, 0xFFFF, sum = 0
5803 12:17:42.090799 8, 0xFFFF, sum = 0
5804 12:17:42.091242 9, 0xFFFF, sum = 0
5805 12:17:42.094507 10, 0x0, sum = 1
5806 12:17:42.094948 11, 0x0, sum = 2
5807 12:17:42.097744 12, 0x0, sum = 3
5808 12:17:42.098218 13, 0x0, sum = 4
5809 12:17:42.100755 best_step = 11
5810 12:17:42.101279
5811 12:17:42.101745 ==
5812 12:17:42.104095 Dram Type= 6, Freq= 0, CH_1, rank 0
5813 12:17:42.107207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 12:17:42.107726 ==
5815 12:17:42.108233 RX Vref Scan: 1
5816 12:17:42.110897
5817 12:17:42.111341 RX Vref 0 -> 0, step: 1
5818 12:17:42.111681
5819 12:17:42.114001 RX Delay -61 -> 252, step: 4
5820 12:17:42.114455
5821 12:17:42.117136 Set Vref, RX VrefLevel [Byte0]: 51
5822 12:17:42.120769 [Byte1]: 51
5823 12:17:42.124105
5824 12:17:42.124651 Final RX Vref Byte 0 = 51 to rank0
5825 12:17:42.127246 Final RX Vref Byte 1 = 51 to rank0
5826 12:17:42.131073 Final RX Vref Byte 0 = 51 to rank1
5827 12:17:42.134185 Final RX Vref Byte 1 = 51 to rank1==
5828 12:17:42.137290 Dram Type= 6, Freq= 0, CH_1, rank 0
5829 12:17:42.143817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 12:17:42.144246 ==
5831 12:17:42.144694 DQS Delay:
5832 12:17:42.147246 DQS0 = 0, DQS1 = 0
5833 12:17:42.147714 DQM Delay:
5834 12:17:42.148052 DQM0 = 100, DQM1 = 93
5835 12:17:42.150161 DQ Delay:
5836 12:17:42.154130 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5837 12:17:42.156845 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =96
5838 12:17:42.160357 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =82
5839 12:17:42.163378 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5840 12:17:42.163854
5841 12:17:42.164199
5842 12:17:42.170499 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5843 12:17:42.173565 CH1 RK0: MR19=505, MR18=1D0D
5844 12:17:42.179952 CH1_RK0: MR19=0x505, MR18=0x1D0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5845 12:17:42.180719
5846 12:17:42.183511 ----->DramcWriteLeveling(PI) begin...
5847 12:17:42.183972 ==
5848 12:17:42.186700 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 12:17:42.190048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 12:17:42.193198 ==
5851 12:17:42.193627 Write leveling (Byte 0): 28 => 28
5852 12:17:42.196456 Write leveling (Byte 1): 28 => 28
5853 12:17:42.199628 DramcWriteLeveling(PI) end<-----
5854 12:17:42.200049
5855 12:17:42.200419 ==
5856 12:17:42.202848 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 12:17:42.209790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 12:17:42.210416 ==
5859 12:17:42.213013 [Gating] SW mode calibration
5860 12:17:42.219334 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5861 12:17:42.222456 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5862 12:17:42.229467 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5863 12:17:42.232437 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5864 12:17:42.235828 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5865 12:17:42.242753 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5866 12:17:42.245807 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5867 12:17:42.248812 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5868 12:17:42.255807 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5869 12:17:42.258930 0 14 28 | B1->B0 | 2b2b 2f2f | 0 1 | (0 0) (1 0)
5870 12:17:42.262273 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5871 12:17:42.268729 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5872 12:17:42.272374 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5873 12:17:42.275265 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5874 12:17:42.281779 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5875 12:17:42.285431 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5876 12:17:42.288563 0 15 24 | B1->B0 | 2625 2323 | 1 0 | (0 0) (0 0)
5877 12:17:42.295492 0 15 28 | B1->B0 | 3a3a 2c2c | 0 0 | (0 0) (0 0)
5878 12:17:42.298584 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 12:17:42.301789 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 12:17:42.308597 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5881 12:17:42.311760 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5882 12:17:42.314885 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5883 12:17:42.321918 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5884 12:17:42.325155 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5885 12:17:42.328057 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5886 12:17:42.335022 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 12:17:42.338240 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 12:17:42.341306 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 12:17:42.348347 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 12:17:42.351505 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 12:17:42.354553 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 12:17:42.361137 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 12:17:42.364811 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 12:17:42.367687 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 12:17:42.374058 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 12:17:42.377567 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 12:17:42.381184 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 12:17:42.387651 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 12:17:42.390517 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 12:17:42.394126 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 12:17:42.400413 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5902 12:17:42.401080 Total UI for P1: 0, mck2ui 16
5903 12:17:42.407440 best dqsien dly found for B1: ( 1, 2, 26)
5904 12:17:42.410716 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5905 12:17:42.413822 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5906 12:17:42.417011 Total UI for P1: 0, mck2ui 16
5907 12:17:42.420708 best dqsien dly found for B0: ( 1, 2, 30)
5908 12:17:42.424040 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5909 12:17:42.427288 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5910 12:17:42.427710
5911 12:17:42.433995 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5912 12:17:42.437232 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5913 12:17:42.437658 [Gating] SW calibration Done
5914 12:17:42.440439 ==
5915 12:17:42.443596 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 12:17:42.447183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 12:17:42.447718 ==
5918 12:17:42.448064 RX Vref Scan: 0
5919 12:17:42.448377
5920 12:17:42.451104 RX Vref 0 -> 0, step: 1
5921 12:17:42.451632
5922 12:17:42.454250 RX Delay -80 -> 252, step: 8
5923 12:17:42.457016 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5924 12:17:42.460215 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5925 12:17:42.463831 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5926 12:17:42.469996 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5927 12:17:42.473386 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5928 12:17:42.476891 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5929 12:17:42.480288 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5930 12:17:42.483249 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5931 12:17:42.486968 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5932 12:17:42.493386 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5933 12:17:42.496672 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5934 12:17:42.500203 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5935 12:17:42.503367 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5936 12:17:42.506657 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5937 12:17:42.512955 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5938 12:17:42.516581 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5939 12:17:42.517013 ==
5940 12:17:42.519922 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 12:17:42.523036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 12:17:42.523622 ==
5943 12:17:42.523984 DQS Delay:
5944 12:17:42.526799 DQS0 = 0, DQS1 = 0
5945 12:17:42.527243 DQM Delay:
5946 12:17:42.529784 DQM0 = 100, DQM1 = 91
5947 12:17:42.530227 DQ Delay:
5948 12:17:42.533002 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5949 12:17:42.536171 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5950 12:17:42.539954 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =79
5951 12:17:42.542573 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =103
5952 12:17:42.543001
5953 12:17:42.543337
5954 12:17:42.543645 ==
5955 12:17:42.546236 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 12:17:42.553011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 12:17:42.553438 ==
5958 12:17:42.553773
5959 12:17:42.554084
5960 12:17:42.554378 TX Vref Scan disable
5961 12:17:42.556895 == TX Byte 0 ==
5962 12:17:42.559978 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5963 12:17:42.563260 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5964 12:17:42.566867 == TX Byte 1 ==
5965 12:17:42.569965 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5966 12:17:42.576196 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5967 12:17:42.576771 ==
5968 12:17:42.579777 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 12:17:42.582862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 12:17:42.583289 ==
5971 12:17:42.583627
5972 12:17:42.583938
5973 12:17:42.586337 TX Vref Scan disable
5974 12:17:42.586762 == TX Byte 0 ==
5975 12:17:42.592712 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5976 12:17:42.596176 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5977 12:17:42.599787 == TX Byte 1 ==
5978 12:17:42.602723 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5979 12:17:42.605655 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5980 12:17:42.606104
5981 12:17:42.606546 [DATLAT]
5982 12:17:42.609450 Freq=933, CH1 RK1
5983 12:17:42.609955
5984 12:17:42.612553 DATLAT Default: 0xb
5985 12:17:42.613004 0, 0xFFFF, sum = 0
5986 12:17:42.615589 1, 0xFFFF, sum = 0
5987 12:17:42.616032 2, 0xFFFF, sum = 0
5988 12:17:42.618741 3, 0xFFFF, sum = 0
5989 12:17:42.619174 4, 0xFFFF, sum = 0
5990 12:17:42.622547 5, 0xFFFF, sum = 0
5991 12:17:42.622986 6, 0xFFFF, sum = 0
5992 12:17:42.625646 7, 0xFFFF, sum = 0
5993 12:17:42.626077 8, 0xFFFF, sum = 0
5994 12:17:42.628935 9, 0xFFFF, sum = 0
5995 12:17:42.629368 10, 0x0, sum = 1
5996 12:17:42.632185 11, 0x0, sum = 2
5997 12:17:42.632659 12, 0x0, sum = 3
5998 12:17:42.635236 13, 0x0, sum = 4
5999 12:17:42.635666 best_step = 11
6000 12:17:42.636003
6001 12:17:42.636316 ==
6002 12:17:42.638935 Dram Type= 6, Freq= 0, CH_1, rank 1
6003 12:17:42.642031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6004 12:17:42.644978 ==
6005 12:17:42.645403 RX Vref Scan: 0
6006 12:17:42.645741
6007 12:17:42.648884 RX Vref 0 -> 0, step: 1
6008 12:17:42.649313
6009 12:17:42.652004 RX Delay -61 -> 252, step: 4
6010 12:17:42.654939 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6011 12:17:42.658242 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6012 12:17:42.664878 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6013 12:17:42.667951 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6014 12:17:42.671274 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6015 12:17:42.675141 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
6016 12:17:42.678275 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6017 12:17:42.681497 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6018 12:17:42.687876 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
6019 12:17:42.691433 iDelay=207, Bit 9, Center 86 (-1 ~ 174) 176
6020 12:17:42.694422 iDelay=207, Bit 10, Center 90 (-1 ~ 182) 184
6021 12:17:42.697886 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6022 12:17:42.701418 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6023 12:17:42.707959 iDelay=207, Bit 13, Center 98 (7 ~ 190) 184
6024 12:17:42.711360 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
6025 12:17:42.714335 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
6026 12:17:42.714783 ==
6027 12:17:42.718144 Dram Type= 6, Freq= 0, CH_1, rank 1
6028 12:17:42.721373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6029 12:17:42.721913 ==
6030 12:17:42.724412 DQS Delay:
6031 12:17:42.724889 DQS0 = 0, DQS1 = 0
6032 12:17:42.727432 DQM Delay:
6033 12:17:42.727864 DQM0 = 101, DQM1 = 93
6034 12:17:42.728207 DQ Delay:
6035 12:17:42.731408 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
6036 12:17:42.734780 DQ4 =98, DQ5 =112, DQ6 =114, DQ7 =98
6037 12:17:42.737572 DQ8 =80, DQ9 =86, DQ10 =90, DQ11 =84
6038 12:17:42.744293 DQ12 =102, DQ13 =98, DQ14 =100, DQ15 =104
6039 12:17:42.744789
6040 12:17:42.745139
6041 12:17:42.750642 [DQSOSCAuto] RK1, (LSB)MR18= 0x5fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
6042 12:17:42.754469 CH1 RK1: MR19=504, MR18=5FE
6043 12:17:42.760742 CH1_RK1: MR19=0x504, MR18=0x5FE, DQSOSC=420, MR23=63, INC=61, DEC=40
6044 12:17:42.763800 [RxdqsGatingPostProcess] freq 933
6045 12:17:42.767067 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6046 12:17:42.770885 best DQS0 dly(2T, 0.5T) = (0, 10)
6047 12:17:42.774093 best DQS1 dly(2T, 0.5T) = (0, 10)
6048 12:17:42.777098 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6049 12:17:42.780311 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6050 12:17:42.783649 best DQS0 dly(2T, 0.5T) = (0, 10)
6051 12:17:42.787476 best DQS1 dly(2T, 0.5T) = (0, 10)
6052 12:17:42.790531 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6053 12:17:42.793584 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6054 12:17:42.796945 Pre-setting of DQS Precalculation
6055 12:17:42.800700 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6056 12:17:42.810091 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6057 12:17:42.816764 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6058 12:17:42.817282
6059 12:17:42.817683
6060 12:17:42.820406 [Calibration Summary] 1866 Mbps
6061 12:17:42.820875 CH 0, Rank 0
6062 12:17:42.823463 SW Impedance : PASS
6063 12:17:42.823895 DUTY Scan : NO K
6064 12:17:42.826654 ZQ Calibration : PASS
6065 12:17:42.829754 Jitter Meter : NO K
6066 12:17:42.830181 CBT Training : PASS
6067 12:17:42.833430 Write leveling : PASS
6068 12:17:42.836582 RX DQS gating : PASS
6069 12:17:42.837016 RX DQ/DQS(RDDQC) : PASS
6070 12:17:42.840274 TX DQ/DQS : PASS
6071 12:17:42.843288 RX DATLAT : PASS
6072 12:17:42.843715 RX DQ/DQS(Engine): PASS
6073 12:17:42.846440 TX OE : NO K
6074 12:17:42.846917 All Pass.
6075 12:17:42.847314
6076 12:17:42.850207 CH 0, Rank 1
6077 12:17:42.850782 SW Impedance : PASS
6078 12:17:42.853315 DUTY Scan : NO K
6079 12:17:42.853743 ZQ Calibration : PASS
6080 12:17:42.856577 Jitter Meter : NO K
6081 12:17:42.860087 CBT Training : PASS
6082 12:17:42.860666 Write leveling : PASS
6083 12:17:42.863037 RX DQS gating : PASS
6084 12:17:42.867125 RX DQ/DQS(RDDQC) : PASS
6085 12:17:42.867655 TX DQ/DQS : PASS
6086 12:17:42.869891 RX DATLAT : PASS
6087 12:17:42.872837 RX DQ/DQS(Engine): PASS
6088 12:17:42.873273 TX OE : NO K
6089 12:17:42.876098 All Pass.
6090 12:17:42.876558
6091 12:17:42.876907 CH 1, Rank 0
6092 12:17:42.879210 SW Impedance : PASS
6093 12:17:42.879644 DUTY Scan : NO K
6094 12:17:42.882794 ZQ Calibration : PASS
6095 12:17:42.886299 Jitter Meter : NO K
6096 12:17:42.886731 CBT Training : PASS
6097 12:17:42.889265 Write leveling : PASS
6098 12:17:42.892565 RX DQS gating : PASS
6099 12:17:42.893002 RX DQ/DQS(RDDQC) : PASS
6100 12:17:42.896288 TX DQ/DQS : PASS
6101 12:17:42.899399 RX DATLAT : PASS
6102 12:17:42.899865 RX DQ/DQS(Engine): PASS
6103 12:17:42.902302 TX OE : NO K
6104 12:17:42.902742 All Pass.
6105 12:17:42.903083
6106 12:17:42.906024 CH 1, Rank 1
6107 12:17:42.906459 SW Impedance : PASS
6108 12:17:42.909486 DUTY Scan : NO K
6109 12:17:42.912333 ZQ Calibration : PASS
6110 12:17:42.912882 Jitter Meter : NO K
6111 12:17:42.915771 CBT Training : PASS
6112 12:17:42.919449 Write leveling : PASS
6113 12:17:42.919887 RX DQS gating : PASS
6114 12:17:42.922369 RX DQ/DQS(RDDQC) : PASS
6115 12:17:42.922802 TX DQ/DQS : PASS
6116 12:17:42.926043 RX DATLAT : PASS
6117 12:17:42.928889 RX DQ/DQS(Engine): PASS
6118 12:17:42.929322 TX OE : NO K
6119 12:17:42.932770 All Pass.
6120 12:17:42.933202
6121 12:17:42.933543 DramC Write-DBI off
6122 12:17:42.935870 PER_BANK_REFRESH: Hybrid Mode
6123 12:17:42.939180 TX_TRACKING: ON
6124 12:17:42.945979 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6125 12:17:42.949206 [FAST_K] Save calibration result to emmc
6126 12:17:42.955598 dramc_set_vcore_voltage set vcore to 650000
6127 12:17:42.956147 Read voltage for 400, 6
6128 12:17:42.956591 Vio18 = 0
6129 12:17:42.959231 Vcore = 650000
6130 12:17:42.959794 Vdram = 0
6131 12:17:42.960287 Vddq = 0
6132 12:17:42.962327 Vmddr = 0
6133 12:17:42.965552 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6134 12:17:42.971809 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6135 12:17:42.975480 MEM_TYPE=3, freq_sel=20
6136 12:17:42.975914 sv_algorithm_assistance_LP4_800
6137 12:17:42.982260 ============ PULL DRAM RESETB DOWN ============
6138 12:17:42.985328 ========== PULL DRAM RESETB DOWN end =========
6139 12:17:42.988414 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6140 12:17:42.991551 ===================================
6141 12:17:42.995288 LPDDR4 DRAM CONFIGURATION
6142 12:17:42.998565 ===================================
6143 12:17:43.001813 EX_ROW_EN[0] = 0x0
6144 12:17:43.002289 EX_ROW_EN[1] = 0x0
6145 12:17:43.004909 LP4Y_EN = 0x0
6146 12:17:43.005334 WORK_FSP = 0x0
6147 12:17:43.008629 WL = 0x2
6148 12:17:43.009094 RL = 0x2
6149 12:17:43.011849 BL = 0x2
6150 12:17:43.012355 RPST = 0x0
6151 12:17:43.015002 RD_PRE = 0x0
6152 12:17:43.015640 WR_PRE = 0x1
6153 12:17:43.017862 WR_PST = 0x0
6154 12:17:43.018342 DBI_WR = 0x0
6155 12:17:43.021637 DBI_RD = 0x0
6156 12:17:43.024421 OTF = 0x1
6157 12:17:43.027839 ===================================
6158 12:17:43.031462 ===================================
6159 12:17:43.032023 ANA top config
6160 12:17:43.034437 ===================================
6161 12:17:43.038088 DLL_ASYNC_EN = 0
6162 12:17:43.041298 ALL_SLAVE_EN = 1
6163 12:17:43.041734 NEW_RANK_MODE = 1
6164 12:17:43.044436 DLL_IDLE_MODE = 1
6165 12:17:43.047706 LP45_APHY_COMB_EN = 1
6166 12:17:43.051232 TX_ODT_DIS = 1
6167 12:17:43.051668 NEW_8X_MODE = 1
6168 12:17:43.054576 ===================================
6169 12:17:43.057472 ===================================
6170 12:17:43.060850 data_rate = 800
6171 12:17:43.064401 CKR = 1
6172 12:17:43.067633 DQ_P2S_RATIO = 4
6173 12:17:43.070791 ===================================
6174 12:17:43.074574 CA_P2S_RATIO = 4
6175 12:17:43.077518 DQ_CA_OPEN = 0
6176 12:17:43.077953 DQ_SEMI_OPEN = 1
6177 12:17:43.080826 CA_SEMI_OPEN = 1
6178 12:17:43.084565 CA_FULL_RATE = 0
6179 12:17:43.087679 DQ_CKDIV4_EN = 0
6180 12:17:43.090839 CA_CKDIV4_EN = 1
6181 12:17:43.093887 CA_PREDIV_EN = 0
6182 12:17:43.097632 PH8_DLY = 0
6183 12:17:43.098070 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6184 12:17:43.100729 DQ_AAMCK_DIV = 0
6185 12:17:43.103867 CA_AAMCK_DIV = 0
6186 12:17:43.107208 CA_ADMCK_DIV = 4
6187 12:17:43.110204 DQ_TRACK_CA_EN = 0
6188 12:17:43.113963 CA_PICK = 800
6189 12:17:43.114419 CA_MCKIO = 400
6190 12:17:43.117015 MCKIO_SEMI = 400
6191 12:17:43.120180 PLL_FREQ = 3016
6192 12:17:43.123876 DQ_UI_PI_RATIO = 32
6193 12:17:43.127053 CA_UI_PI_RATIO = 32
6194 12:17:43.130080 ===================================
6195 12:17:43.133558 ===================================
6196 12:17:43.137309 memory_type:LPDDR4
6197 12:17:43.137742 GP_NUM : 10
6198 12:17:43.140235 SRAM_EN : 1
6199 12:17:43.143546 MD32_EN : 0
6200 12:17:43.146669 ===================================
6201 12:17:43.147104 [ANA_INIT] >>>>>>>>>>>>>>
6202 12:17:43.149900 <<<<<< [CONFIGURE PHASE]: ANA_TX
6203 12:17:43.153003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6204 12:17:43.156296 ===================================
6205 12:17:43.160009 data_rate = 800,PCW = 0X7400
6206 12:17:43.163079 ===================================
6207 12:17:43.166269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6208 12:17:43.173103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6209 12:17:43.183194 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6210 12:17:43.189176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6211 12:17:43.192889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6212 12:17:43.195972 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6213 12:17:43.196412 [ANA_INIT] flow start
6214 12:17:43.199174 [ANA_INIT] PLL >>>>>>>>
6215 12:17:43.202370 [ANA_INIT] PLL <<<<<<<<
6216 12:17:43.202854 [ANA_INIT] MIDPI >>>>>>>>
6217 12:17:43.206206 [ANA_INIT] MIDPI <<<<<<<<
6218 12:17:43.209373 [ANA_INIT] DLL >>>>>>>>
6219 12:17:43.209808 [ANA_INIT] flow end
6220 12:17:43.215608 ============ LP4 DIFF to SE enter ============
6221 12:17:43.219328 ============ LP4 DIFF to SE exit ============
6222 12:17:43.222669 [ANA_INIT] <<<<<<<<<<<<<
6223 12:17:43.225997 [Flow] Enable top DCM control >>>>>
6224 12:17:43.229028 [Flow] Enable top DCM control <<<<<
6225 12:17:43.229465 Enable DLL master slave shuffle
6226 12:17:43.235570 ==============================================================
6227 12:17:43.239067 Gating Mode config
6228 12:17:43.242291 ==============================================================
6229 12:17:43.245667 Config description:
6230 12:17:43.255582 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6231 12:17:43.262644 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6232 12:17:43.265573 SELPH_MODE 0: By rank 1: By Phase
6233 12:17:43.271917 ==============================================================
6234 12:17:43.275747 GAT_TRACK_EN = 0
6235 12:17:43.278903 RX_GATING_MODE = 2
6236 12:17:43.281999 RX_GATING_TRACK_MODE = 2
6237 12:17:43.285696 SELPH_MODE = 1
6238 12:17:43.288722 PICG_EARLY_EN = 1
6239 12:17:43.289157 VALID_LAT_VALUE = 1
6240 12:17:43.295105 ==============================================================
6241 12:17:43.298826 Enter into Gating configuration >>>>
6242 12:17:43.302028 Exit from Gating configuration <<<<
6243 12:17:43.305203 Enter into DVFS_PRE_config >>>>>
6244 12:17:43.315328 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6245 12:17:43.318396 Exit from DVFS_PRE_config <<<<<
6246 12:17:43.321617 Enter into PICG configuration >>>>
6247 12:17:43.325452 Exit from PICG configuration <<<<
6248 12:17:43.328735 [RX_INPUT] configuration >>>>>
6249 12:17:43.331517 [RX_INPUT] configuration <<<<<
6250 12:17:43.338461 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6251 12:17:43.341415 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6252 12:17:43.348256 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6253 12:17:43.354851 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6254 12:17:43.361637 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6255 12:17:43.367921 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6256 12:17:43.371599 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6257 12:17:43.374885 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6258 12:17:43.377762 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6259 12:17:43.384748 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6260 12:17:43.387931 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6261 12:17:43.391265 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6262 12:17:43.394217 ===================================
6263 12:17:43.397979 LPDDR4 DRAM CONFIGURATION
6264 12:17:43.401060 ===================================
6265 12:17:43.401492 EX_ROW_EN[0] = 0x0
6266 12:17:43.404182 EX_ROW_EN[1] = 0x0
6267 12:17:43.407549 LP4Y_EN = 0x0
6268 12:17:43.408003 WORK_FSP = 0x0
6269 12:17:43.411353 WL = 0x2
6270 12:17:43.411780 RL = 0x2
6271 12:17:43.414357 BL = 0x2
6272 12:17:43.414804 RPST = 0x0
6273 12:17:43.417530 RD_PRE = 0x0
6274 12:17:43.417997 WR_PRE = 0x1
6275 12:17:43.420665 WR_PST = 0x0
6276 12:17:43.421248 DBI_WR = 0x0
6277 12:17:43.423772 DBI_RD = 0x0
6278 12:17:43.424203 OTF = 0x1
6279 12:17:43.427598 ===================================
6280 12:17:43.430813 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6281 12:17:43.437039 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6282 12:17:43.440748 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6283 12:17:43.443703 ===================================
6284 12:17:43.447636 LPDDR4 DRAM CONFIGURATION
6285 12:17:43.450385 ===================================
6286 12:17:43.450981 EX_ROW_EN[0] = 0x10
6287 12:17:43.454001 EX_ROW_EN[1] = 0x0
6288 12:17:43.457004 LP4Y_EN = 0x0
6289 12:17:43.457436 WORK_FSP = 0x0
6290 12:17:43.460450 WL = 0x2
6291 12:17:43.460919 RL = 0x2
6292 12:17:43.463767 BL = 0x2
6293 12:17:43.464201 RPST = 0x0
6294 12:17:43.467354 RD_PRE = 0x0
6295 12:17:43.467915 WR_PRE = 0x1
6296 12:17:43.470256 WR_PST = 0x0
6297 12:17:43.470689 DBI_WR = 0x0
6298 12:17:43.473953 DBI_RD = 0x0
6299 12:17:43.474484 OTF = 0x1
6300 12:17:43.476892 ===================================
6301 12:17:43.483390 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6302 12:17:43.488647 nWR fixed to 30
6303 12:17:43.491644 [ModeRegInit_LP4] CH0 RK0
6304 12:17:43.492082 [ModeRegInit_LP4] CH0 RK1
6305 12:17:43.494856 [ModeRegInit_LP4] CH1 RK0
6306 12:17:43.497927 [ModeRegInit_LP4] CH1 RK1
6307 12:17:43.498383 match AC timing 19
6308 12:17:43.504800 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6309 12:17:43.507819 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6310 12:17:43.510988 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6311 12:17:43.517853 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6312 12:17:43.521423 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6313 12:17:43.521855 ==
6314 12:17:43.524419 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 12:17:43.527556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 12:17:43.528086 ==
6317 12:17:43.534432 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6318 12:17:43.540774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6319 12:17:43.543796 [CA 0] Center 36 (8~64) winsize 57
6320 12:17:43.547468 [CA 1] Center 36 (8~64) winsize 57
6321 12:17:43.550523 [CA 2] Center 36 (8~64) winsize 57
6322 12:17:43.554174 [CA 3] Center 36 (8~64) winsize 57
6323 12:17:43.557935 [CA 4] Center 36 (8~64) winsize 57
6324 12:17:43.560595 [CA 5] Center 36 (8~64) winsize 57
6325 12:17:43.561037
6326 12:17:43.563588 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6327 12:17:43.564025
6328 12:17:43.567153 [CATrainingPosCal] consider 1 rank data
6329 12:17:43.570547 u2DelayCellTimex100 = 270/100 ps
6330 12:17:43.573699 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 12:17:43.577326 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 12:17:43.580688 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 12:17:43.583837 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 12:17:43.586996 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 12:17:43.590588 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 12:17:43.591023
6337 12:17:43.597067 CA PerBit enable=1, Macro0, CA PI delay=36
6338 12:17:43.597790
6339 12:17:43.598208 [CBTSetCACLKResult] CA Dly = 36
6340 12:17:43.600050 CS Dly: 1 (0~32)
6341 12:17:43.600793 ==
6342 12:17:43.603794 Dram Type= 6, Freq= 0, CH_0, rank 1
6343 12:17:43.606829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 12:17:43.607268 ==
6345 12:17:43.613191 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6346 12:17:43.620109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6347 12:17:43.623244 [CA 0] Center 36 (8~64) winsize 57
6348 12:17:43.626316 [CA 1] Center 36 (8~64) winsize 57
6349 12:17:43.629613 [CA 2] Center 36 (8~64) winsize 57
6350 12:17:43.633375 [CA 3] Center 36 (8~64) winsize 57
6351 12:17:43.633909 [CA 4] Center 36 (8~64) winsize 57
6352 12:17:43.636251 [CA 5] Center 36 (8~64) winsize 57
6353 12:17:43.636851
6354 12:17:43.643406 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6355 12:17:43.643949
6356 12:17:43.646318 [CATrainingPosCal] consider 2 rank data
6357 12:17:43.649168 u2DelayCellTimex100 = 270/100 ps
6358 12:17:43.652784 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6359 12:17:43.655693 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6360 12:17:43.659399 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6361 12:17:43.662989 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6362 12:17:43.665963 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6363 12:17:43.669060 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6364 12:17:43.669521
6365 12:17:43.672550 CA PerBit enable=1, Macro0, CA PI delay=36
6366 12:17:43.673006
6367 12:17:43.675733 [CBTSetCACLKResult] CA Dly = 36
6368 12:17:43.679367 CS Dly: 1 (0~32)
6369 12:17:43.679670
6370 12:17:43.682845 ----->DramcWriteLeveling(PI) begin...
6371 12:17:43.683249 ==
6372 12:17:43.685702 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 12:17:43.688907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 12:17:43.689214 ==
6375 12:17:43.692037 Write leveling (Byte 0): 40 => 8
6376 12:17:43.696003 Write leveling (Byte 1): 32 => 0
6377 12:17:43.699032 DramcWriteLeveling(PI) end<-----
6378 12:17:43.699417
6379 12:17:43.699752 ==
6380 12:17:43.702184 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 12:17:43.705199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 12:17:43.705634 ==
6383 12:17:43.708211 [Gating] SW mode calibration
6384 12:17:43.715350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6385 12:17:43.721537 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6386 12:17:43.724809 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6387 12:17:43.731951 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6388 12:17:43.734924 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6389 12:17:43.738073 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6390 12:17:43.744871 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6391 12:17:43.747969 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6392 12:17:43.751141 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6393 12:17:43.757769 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6394 12:17:43.761506 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6395 12:17:43.764151 Total UI for P1: 0, mck2ui 16
6396 12:17:43.767747 best dqsien dly found for B0: ( 0, 14, 24)
6397 12:17:43.771346 Total UI for P1: 0, mck2ui 16
6398 12:17:43.774423 best dqsien dly found for B1: ( 0, 14, 24)
6399 12:17:43.777523 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6400 12:17:43.781009 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6401 12:17:43.781433
6402 12:17:43.784561 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6403 12:17:43.790728 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6404 12:17:43.791179 [Gating] SW calibration Done
6405 12:17:43.791525 ==
6406 12:17:43.794520 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 12:17:43.800697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 12:17:43.801127 ==
6409 12:17:43.801491 RX Vref Scan: 0
6410 12:17:43.801807
6411 12:17:43.804019 RX Vref 0 -> 0, step: 1
6412 12:17:43.804443
6413 12:17:43.807269 RX Delay -410 -> 252, step: 16
6414 12:17:43.810605 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6415 12:17:43.814136 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6416 12:17:43.820700 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6417 12:17:43.823953 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6418 12:17:43.827045 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6419 12:17:43.830919 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6420 12:17:43.837117 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6421 12:17:43.840683 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6422 12:17:43.843869 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6423 12:17:43.846872 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6424 12:17:43.853585 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6425 12:17:43.856981 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6426 12:17:43.860012 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6427 12:17:43.866658 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6428 12:17:43.870272 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6429 12:17:43.873063 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6430 12:17:43.873491 ==
6431 12:17:43.876496 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 12:17:43.879945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 12:17:43.883133 ==
6434 12:17:43.883548 DQS Delay:
6435 12:17:43.883875 DQS0 = 43, DQS1 = 59
6436 12:17:43.886861 DQM Delay:
6437 12:17:43.887503 DQM0 = 10, DQM1 = 12
6438 12:17:43.890040 DQ Delay:
6439 12:17:43.890564 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6440 12:17:43.893359 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6441 12:17:43.896455 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6442 12:17:43.899527 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6443 12:17:43.900078
6444 12:17:43.900588
6445 12:17:43.902692 ==
6446 12:17:43.903123 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 12:17:43.909964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 12:17:43.910483 ==
6449 12:17:43.910817
6450 12:17:43.911124
6451 12:17:43.912931 TX Vref Scan disable
6452 12:17:43.913351 == TX Byte 0 ==
6453 12:17:43.916132 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6454 12:17:43.923006 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6455 12:17:43.923651 == TX Byte 1 ==
6456 12:17:43.926496 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6457 12:17:43.932593 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6458 12:17:43.933029 ==
6459 12:17:43.935832 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 12:17:43.939495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 12:17:43.939935 ==
6462 12:17:43.940276
6463 12:17:43.940693
6464 12:17:43.942564 TX Vref Scan disable
6465 12:17:43.943000 == TX Byte 0 ==
6466 12:17:43.945665 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6467 12:17:43.952739 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6468 12:17:43.953179 == TX Byte 1 ==
6469 12:17:43.955950 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6470 12:17:43.962335 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6471 12:17:43.962851
6472 12:17:43.963192 [DATLAT]
6473 12:17:43.965540 Freq=400, CH0 RK0
6474 12:17:43.965985
6475 12:17:43.966381 DATLAT Default: 0xf
6476 12:17:43.969134 0, 0xFFFF, sum = 0
6477 12:17:43.969800 1, 0xFFFF, sum = 0
6478 12:17:43.972103 2, 0xFFFF, sum = 0
6479 12:17:43.972581 3, 0xFFFF, sum = 0
6480 12:17:43.975726 4, 0xFFFF, sum = 0
6481 12:17:43.976166 5, 0xFFFF, sum = 0
6482 12:17:43.978686 6, 0xFFFF, sum = 0
6483 12:17:43.979126 7, 0xFFFF, sum = 0
6484 12:17:43.982183 8, 0xFFFF, sum = 0
6485 12:17:43.982838 9, 0xFFFF, sum = 0
6486 12:17:43.985805 10, 0xFFFF, sum = 0
6487 12:17:43.986282 11, 0xFFFF, sum = 0
6488 12:17:43.988734 12, 0xFFFF, sum = 0
6489 12:17:43.989265 13, 0x0, sum = 1
6490 12:17:43.992363 14, 0x0, sum = 2
6491 12:17:43.992951 15, 0x0, sum = 3
6492 12:17:43.995379 16, 0x0, sum = 4
6493 12:17:43.995912 best_step = 14
6494 12:17:43.996253
6495 12:17:43.996609 ==
6496 12:17:43.998827 Dram Type= 6, Freq= 0, CH_0, rank 0
6497 12:17:44.005456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 12:17:44.006009 ==
6499 12:17:44.006367 RX Vref Scan: 1
6500 12:17:44.006689
6501 12:17:44.008778 RX Vref 0 -> 0, step: 1
6502 12:17:44.009211
6503 12:17:44.012132 RX Delay -359 -> 252, step: 8
6504 12:17:44.012698
6505 12:17:44.015513 Set Vref, RX VrefLevel [Byte0]: 61
6506 12:17:44.018943 [Byte1]: 55
6507 12:17:44.021956
6508 12:17:44.022413 Final RX Vref Byte 0 = 61 to rank0
6509 12:17:44.025027 Final RX Vref Byte 1 = 55 to rank0
6510 12:17:44.029023 Final RX Vref Byte 0 = 61 to rank1
6511 12:17:44.032242 Final RX Vref Byte 1 = 55 to rank1==
6512 12:17:44.035089 Dram Type= 6, Freq= 0, CH_0, rank 0
6513 12:17:44.042113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 12:17:44.042633 ==
6515 12:17:44.042977 DQS Delay:
6516 12:17:44.045150 DQS0 = 48, DQS1 = 56
6517 12:17:44.045576 DQM Delay:
6518 12:17:44.045908 DQM0 = 12, DQM1 = 7
6519 12:17:44.048430 DQ Delay:
6520 12:17:44.051660 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6521 12:17:44.054810 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6522 12:17:44.055234 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6523 12:17:44.058994 DQ12 =12, DQ13 =8, DQ14 =16, DQ15 =16
6524 12:17:44.059522
6525 12:17:44.061834
6526 12:17:44.068341 [DQSOSCAuto] RK0, (LSB)MR18= 0xbc7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6527 12:17:44.071404 CH0 RK0: MR19=C0C, MR18=BC7F
6528 12:17:44.078345 CH0_RK0: MR19=0xC0C, MR18=0xBC7F, DQSOSC=386, MR23=63, INC=396, DEC=264
6529 12:17:44.078805 ==
6530 12:17:44.081459 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 12:17:44.084707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 12:17:44.085232 ==
6533 12:17:44.087916 [Gating] SW mode calibration
6534 12:17:44.094856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6535 12:17:44.100990 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6536 12:17:44.104463 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6537 12:17:44.107360 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6538 12:17:44.114478 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6539 12:17:44.117397 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6540 12:17:44.120441 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6541 12:17:44.127537 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6542 12:17:44.130867 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6543 12:17:44.134440 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6544 12:17:44.141067 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6545 12:17:44.141646 Total UI for P1: 0, mck2ui 16
6546 12:17:44.147473 best dqsien dly found for B0: ( 0, 14, 24)
6547 12:17:44.147924 Total UI for P1: 0, mck2ui 16
6548 12:17:44.154090 best dqsien dly found for B1: ( 0, 14, 24)
6549 12:17:44.157091 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6550 12:17:44.161181 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6551 12:17:44.161723
6552 12:17:44.163913 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6553 12:17:44.166840 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6554 12:17:44.170147 [Gating] SW calibration Done
6555 12:17:44.170592 ==
6556 12:17:44.174054 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 12:17:44.177138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 12:17:44.177591 ==
6559 12:17:44.180296 RX Vref Scan: 0
6560 12:17:44.180925
6561 12:17:44.181464 RX Vref 0 -> 0, step: 1
6562 12:17:44.184047
6563 12:17:44.184504 RX Delay -410 -> 252, step: 16
6564 12:17:44.190285 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6565 12:17:44.193317 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6566 12:17:44.196972 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6567 12:17:44.199932 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6568 12:17:44.206391 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6569 12:17:44.210295 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6570 12:17:44.213269 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6571 12:17:44.216280 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6572 12:17:44.223284 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6573 12:17:44.226394 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6574 12:17:44.229590 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6575 12:17:44.236500 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6576 12:17:44.239908 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6577 12:17:44.242892 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6578 12:17:44.246604 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6579 12:17:44.252818 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6580 12:17:44.253383 ==
6581 12:17:44.256053 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 12:17:44.259278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 12:17:44.260225 ==
6584 12:17:44.260743 DQS Delay:
6585 12:17:44.262982 DQS0 = 43, DQS1 = 59
6586 12:17:44.263556 DQM Delay:
6587 12:17:44.266146 DQM0 = 9, DQM1 = 16
6588 12:17:44.266683 DQ Delay:
6589 12:17:44.269036 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6590 12:17:44.272381 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6591 12:17:44.275393 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6592 12:17:44.279414 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6593 12:17:44.279843
6594 12:17:44.280179
6595 12:17:44.280491 ==
6596 12:17:44.282496 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 12:17:44.285742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 12:17:44.286168 ==
6599 12:17:44.286602
6600 12:17:44.288679
6601 12:17:44.289113 TX Vref Scan disable
6602 12:17:44.292313 == TX Byte 0 ==
6603 12:17:44.295248 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6604 12:17:44.298762 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6605 12:17:44.302344 == TX Byte 1 ==
6606 12:17:44.305251 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6607 12:17:44.308666 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6608 12:17:44.309096 ==
6609 12:17:44.312205 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 12:17:44.315336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 12:17:44.319072 ==
6612 12:17:44.319609
6613 12:17:44.319972
6614 12:17:44.320292 TX Vref Scan disable
6615 12:17:44.321960 == TX Byte 0 ==
6616 12:17:44.325031 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6617 12:17:44.328284 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6618 12:17:44.331965 == TX Byte 1 ==
6619 12:17:44.335150 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6620 12:17:44.338198 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6621 12:17:44.338629
6622 12:17:44.341409 [DATLAT]
6623 12:17:44.341836 Freq=400, CH0 RK1
6624 12:17:44.342173
6625 12:17:44.345195 DATLAT Default: 0xe
6626 12:17:44.345619 0, 0xFFFF, sum = 0
6627 12:17:44.348393 1, 0xFFFF, sum = 0
6628 12:17:44.348874 2, 0xFFFF, sum = 0
6629 12:17:44.351628 3, 0xFFFF, sum = 0
6630 12:17:44.352165 4, 0xFFFF, sum = 0
6631 12:17:44.355632 5, 0xFFFF, sum = 0
6632 12:17:44.356176 6, 0xFFFF, sum = 0
6633 12:17:44.358523 7, 0xFFFF, sum = 0
6634 12:17:44.358956 8, 0xFFFF, sum = 0
6635 12:17:44.361649 9, 0xFFFF, sum = 0
6636 12:17:44.362101 10, 0xFFFF, sum = 0
6637 12:17:44.364846 11, 0xFFFF, sum = 0
6638 12:17:44.365281 12, 0xFFFF, sum = 0
6639 12:17:44.367849 13, 0x0, sum = 1
6640 12:17:44.368284 14, 0x0, sum = 2
6641 12:17:44.371070 15, 0x0, sum = 3
6642 12:17:44.371503 16, 0x0, sum = 4
6643 12:17:44.374927 best_step = 14
6644 12:17:44.375353
6645 12:17:44.375691 ==
6646 12:17:44.378115 Dram Type= 6, Freq= 0, CH_0, rank 1
6647 12:17:44.381143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 12:17:44.381576 ==
6649 12:17:44.384886 RX Vref Scan: 0
6650 12:17:44.385445
6651 12:17:44.385793 RX Vref 0 -> 0, step: 1
6652 12:17:44.386115
6653 12:17:44.387977 RX Delay -359 -> 252, step: 8
6654 12:17:44.396218 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6655 12:17:44.399168 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6656 12:17:44.402887 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6657 12:17:44.409325 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6658 12:17:44.412228 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6659 12:17:44.415744 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6660 12:17:44.419408 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6661 12:17:44.422359 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6662 12:17:44.429394 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6663 12:17:44.432576 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6664 12:17:44.435682 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
6665 12:17:44.442768 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6666 12:17:44.446000 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6667 12:17:44.449047 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6668 12:17:44.452236 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6669 12:17:44.459222 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6670 12:17:44.459652 ==
6671 12:17:44.462318 Dram Type= 6, Freq= 0, CH_0, rank 1
6672 12:17:44.465431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 12:17:44.465863 ==
6674 12:17:44.466201 DQS Delay:
6675 12:17:44.469618 DQS0 = 44, DQS1 = 56
6676 12:17:44.470142 DQM Delay:
6677 12:17:44.472583 DQM0 = 8, DQM1 = 10
6678 12:17:44.473011 DQ Delay:
6679 12:17:44.475624 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6680 12:17:44.478797 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6681 12:17:44.482442 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6682 12:17:44.485280 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6683 12:17:44.485707
6684 12:17:44.486050
6685 12:17:44.491786 [DQSOSCAuto] RK1, (LSB)MR18= 0xb642, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6686 12:17:44.494976 CH0 RK1: MR19=C0C, MR18=B642
6687 12:17:44.501536 CH0_RK1: MR19=0xC0C, MR18=0xB642, DQSOSC=387, MR23=63, INC=394, DEC=262
6688 12:17:44.504631 [RxdqsGatingPostProcess] freq 400
6689 12:17:44.511282 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6690 12:17:44.514865 best DQS0 dly(2T, 0.5T) = (0, 10)
6691 12:17:44.514951 best DQS1 dly(2T, 0.5T) = (0, 10)
6692 12:17:44.517795 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6693 12:17:44.521324 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6694 12:17:44.524913 best DQS0 dly(2T, 0.5T) = (0, 10)
6695 12:17:44.527871 best DQS1 dly(2T, 0.5T) = (0, 10)
6696 12:17:44.531574 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6697 12:17:44.534869 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6698 12:17:44.537896 Pre-setting of DQS Precalculation
6699 12:17:44.544831 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6700 12:17:44.544917 ==
6701 12:17:44.547891 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 12:17:44.551057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 12:17:44.551142 ==
6704 12:17:44.557673 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6705 12:17:44.564441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6706 12:17:44.564550 [CA 0] Center 36 (8~64) winsize 57
6707 12:17:44.567725 [CA 1] Center 36 (8~64) winsize 57
6708 12:17:44.570796 [CA 2] Center 36 (8~64) winsize 57
6709 12:17:44.574537 [CA 3] Center 36 (8~64) winsize 57
6710 12:17:44.577506 [CA 4] Center 36 (8~64) winsize 57
6711 12:17:44.580668 [CA 5] Center 36 (8~64) winsize 57
6712 12:17:44.580751
6713 12:17:44.583790 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6714 12:17:44.583874
6715 12:17:44.587616 [CATrainingPosCal] consider 1 rank data
6716 12:17:44.590763 u2DelayCellTimex100 = 270/100 ps
6717 12:17:44.593912 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 12:17:44.600621 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 12:17:44.603624 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 12:17:44.607355 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 12:17:44.610292 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 12:17:44.613865 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 12:17:44.613949
6724 12:17:44.616728 CA PerBit enable=1, Macro0, CA PI delay=36
6725 12:17:44.616839
6726 12:17:44.620361 [CBTSetCACLKResult] CA Dly = 36
6727 12:17:44.623375 CS Dly: 1 (0~32)
6728 12:17:44.623459 ==
6729 12:17:44.626889 Dram Type= 6, Freq= 0, CH_1, rank 1
6730 12:17:44.629948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 12:17:44.630035 ==
6732 12:17:44.636671 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6733 12:17:44.639667 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6734 12:17:44.643498 [CA 0] Center 36 (8~64) winsize 57
6735 12:17:44.646708 [CA 1] Center 36 (8~64) winsize 57
6736 12:17:44.649858 [CA 2] Center 36 (8~64) winsize 57
6737 12:17:44.652941 [CA 3] Center 36 (8~64) winsize 57
6738 12:17:44.656755 [CA 4] Center 36 (8~64) winsize 57
6739 12:17:44.659854 [CA 5] Center 36 (8~64) winsize 57
6740 12:17:44.659937
6741 12:17:44.662937 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6742 12:17:44.663022
6743 12:17:44.666156 [CATrainingPosCal] consider 2 rank data
6744 12:17:44.669939 u2DelayCellTimex100 = 270/100 ps
6745 12:17:44.673061 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6746 12:17:44.676336 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6747 12:17:44.682591 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6748 12:17:44.686402 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6749 12:17:44.689484 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6750 12:17:44.692625 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6751 12:17:44.692708
6752 12:17:44.695765 CA PerBit enable=1, Macro0, CA PI delay=36
6753 12:17:44.695848
6754 12:17:44.699413 [CBTSetCACLKResult] CA Dly = 36
6755 12:17:44.699497 CS Dly: 1 (0~32)
6756 12:17:44.699563
6757 12:17:44.702586 ----->DramcWriteLeveling(PI) begin...
6758 12:17:44.705758 ==
6759 12:17:44.709442 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 12:17:44.712463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 12:17:44.712583 ==
6762 12:17:44.716003 Write leveling (Byte 0): 40 => 8
6763 12:17:44.718942 Write leveling (Byte 1): 32 => 0
6764 12:17:44.722476 DramcWriteLeveling(PI) end<-----
6765 12:17:44.722560
6766 12:17:44.722625 ==
6767 12:17:44.725502 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 12:17:44.729265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 12:17:44.729351 ==
6770 12:17:44.732115 [Gating] SW mode calibration
6771 12:17:44.738719 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6772 12:17:44.745660 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6773 12:17:44.748835 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6774 12:17:44.751975 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6775 12:17:44.759380 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6776 12:17:44.762615 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6777 12:17:44.765667 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6778 12:17:44.772627 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6779 12:17:44.775704 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6780 12:17:44.778874 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6781 12:17:44.785187 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6782 12:17:44.785627 Total UI for P1: 0, mck2ui 16
6783 12:17:44.792087 best dqsien dly found for B0: ( 0, 14, 24)
6784 12:17:44.792552 Total UI for P1: 0, mck2ui 16
6785 12:17:44.798960 best dqsien dly found for B1: ( 0, 14, 24)
6786 12:17:44.801900 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6787 12:17:44.805173 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6788 12:17:44.805609
6789 12:17:44.808289 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6790 12:17:44.812111 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6791 12:17:44.815127 [Gating] SW calibration Done
6792 12:17:44.815560 ==
6793 12:17:44.818311 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 12:17:44.821732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 12:17:44.822188 ==
6796 12:17:44.825285 RX Vref Scan: 0
6797 12:17:44.825714
6798 12:17:44.826180 RX Vref 0 -> 0, step: 1
6799 12:17:44.828071
6800 12:17:44.828707 RX Delay -410 -> 252, step: 16
6801 12:17:44.834695 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6802 12:17:44.838232 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6803 12:17:44.842281 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6804 12:17:44.844912 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6805 12:17:44.851650 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6806 12:17:44.854698 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6807 12:17:44.857847 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6808 12:17:44.861827 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6809 12:17:44.868057 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6810 12:17:44.871220 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6811 12:17:44.875202 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6812 12:17:44.878228 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6813 12:17:44.884334 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6814 12:17:44.887402 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6815 12:17:44.891358 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6816 12:17:44.897490 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6817 12:17:44.897957 ==
6818 12:17:44.900711 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 12:17:44.904441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 12:17:44.904916 ==
6821 12:17:44.905266 DQS Delay:
6822 12:17:44.907521 DQS0 = 43, DQS1 = 51
6823 12:17:44.907952 DQM Delay:
6824 12:17:44.910765 DQM0 = 12, DQM1 = 14
6825 12:17:44.911314 DQ Delay:
6826 12:17:44.914350 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6827 12:17:44.917399 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6828 12:17:44.920937 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6829 12:17:44.923973 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6830 12:17:44.924406
6831 12:17:44.924801
6832 12:17:44.925123 ==
6833 12:17:44.927649 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 12:17:44.930680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 12:17:44.931118 ==
6836 12:17:44.931465
6837 12:17:44.931783
6838 12:17:44.934137 TX Vref Scan disable
6839 12:17:44.937327 == TX Byte 0 ==
6840 12:17:44.940817 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6841 12:17:44.943750 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6842 12:17:44.944178 == TX Byte 1 ==
6843 12:17:44.950495 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6844 12:17:44.954099 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6845 12:17:44.954531 ==
6846 12:17:44.957128 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 12:17:44.960384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 12:17:44.960842 ==
6849 12:17:44.963499
6850 12:17:44.963925
6851 12:17:44.964263 TX Vref Scan disable
6852 12:17:44.966678 == TX Byte 0 ==
6853 12:17:44.970260 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6854 12:17:44.973711 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6855 12:17:44.976809 == TX Byte 1 ==
6856 12:17:44.980036 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6857 12:17:44.983496 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6858 12:17:44.984024
6859 12:17:44.986540 [DATLAT]
6860 12:17:44.987077 Freq=400, CH1 RK0
6861 12:17:44.987426
6862 12:17:44.989850 DATLAT Default: 0xf
6863 12:17:44.990381 0, 0xFFFF, sum = 0
6864 12:17:44.992918 1, 0xFFFF, sum = 0
6865 12:17:44.993441 2, 0xFFFF, sum = 0
6866 12:17:44.996701 3, 0xFFFF, sum = 0
6867 12:17:44.997251 4, 0xFFFF, sum = 0
6868 12:17:44.999571 5, 0xFFFF, sum = 0
6869 12:17:45.000004 6, 0xFFFF, sum = 0
6870 12:17:45.002610 7, 0xFFFF, sum = 0
6871 12:17:45.003045 8, 0xFFFF, sum = 0
6872 12:17:45.006415 9, 0xFFFF, sum = 0
6873 12:17:45.009551 10, 0xFFFF, sum = 0
6874 12:17:45.009989 11, 0xFFFF, sum = 0
6875 12:17:45.012811 12, 0xFFFF, sum = 0
6876 12:17:45.013247 13, 0x0, sum = 1
6877 12:17:45.015765 14, 0x0, sum = 2
6878 12:17:45.016201 15, 0x0, sum = 3
6879 12:17:45.018958 16, 0x0, sum = 4
6880 12:17:45.019400 best_step = 14
6881 12:17:45.019741
6882 12:17:45.020053 ==
6883 12:17:45.022550 Dram Type= 6, Freq= 0, CH_1, rank 0
6884 12:17:45.025555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 12:17:45.026082 ==
6886 12:17:45.029241 RX Vref Scan: 1
6887 12:17:45.029799
6888 12:17:45.032217 RX Vref 0 -> 0, step: 1
6889 12:17:45.032693
6890 12:17:45.033119 RX Delay -343 -> 252, step: 8
6891 12:17:45.035918
6892 12:17:45.036347 Set Vref, RX VrefLevel [Byte0]: 51
6893 12:17:45.038981 [Byte1]: 51
6894 12:17:45.045021
6895 12:17:45.045449 Final RX Vref Byte 0 = 51 to rank0
6896 12:17:45.048043 Final RX Vref Byte 1 = 51 to rank0
6897 12:17:45.051128 Final RX Vref Byte 0 = 51 to rank1
6898 12:17:45.054754 Final RX Vref Byte 1 = 51 to rank1==
6899 12:17:45.057681 Dram Type= 6, Freq= 0, CH_1, rank 0
6900 12:17:45.064487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 12:17:45.065038 ==
6902 12:17:45.065439 DQS Delay:
6903 12:17:45.067505 DQS0 = 44, DQS1 = 56
6904 12:17:45.067928 DQM Delay:
6905 12:17:45.068265 DQM0 = 7, DQM1 = 12
6906 12:17:45.071313 DQ Delay:
6907 12:17:45.074414 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6908 12:17:45.074901 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6909 12:17:45.077541 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6910 12:17:45.080645 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
6911 12:17:45.081068
6912 12:17:45.084500
6913 12:17:45.090853 [DQSOSCAuto] RK0, (LSB)MR18= 0x986f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6914 12:17:45.094130 CH1 RK0: MR19=C0C, MR18=986F
6915 12:17:45.100509 CH1_RK0: MR19=0xC0C, MR18=0x986F, DQSOSC=390, MR23=63, INC=388, DEC=258
6916 12:17:45.101059 ==
6917 12:17:45.104132 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 12:17:45.107417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 12:17:45.107855 ==
6920 12:17:45.110601 [Gating] SW mode calibration
6921 12:17:45.117042 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6922 12:17:45.123664 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6923 12:17:45.126842 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6924 12:17:45.130476 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6925 12:17:45.137040 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6926 12:17:45.139970 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6927 12:17:45.143447 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6928 12:17:45.149989 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6929 12:17:45.153422 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6930 12:17:45.156929 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6931 12:17:45.163555 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6932 12:17:45.164137 Total UI for P1: 0, mck2ui 16
6933 12:17:45.169760 best dqsien dly found for B0: ( 0, 14, 24)
6934 12:17:45.170200 Total UI for P1: 0, mck2ui 16
6935 12:17:45.176495 best dqsien dly found for B1: ( 0, 14, 24)
6936 12:17:45.179635 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6937 12:17:45.183438 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6938 12:17:45.184092
6939 12:17:45.186500 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6940 12:17:45.189583 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6941 12:17:45.192428 [Gating] SW calibration Done
6942 12:17:45.192578 ==
6943 12:17:45.196180 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 12:17:45.199315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 12:17:45.199426 ==
6946 12:17:45.202678 RX Vref Scan: 0
6947 12:17:45.202788
6948 12:17:45.202890 RX Vref 0 -> 0, step: 1
6949 12:17:45.205599
6950 12:17:45.205684 RX Delay -410 -> 252, step: 16
6951 12:17:45.212630 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6952 12:17:45.215737 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6953 12:17:45.218872 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6954 12:17:45.222588 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6955 12:17:45.229029 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6956 12:17:45.232177 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6957 12:17:45.235794 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6958 12:17:45.238958 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6959 12:17:45.246427 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6960 12:17:45.249227 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6961 12:17:45.252817 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6962 12:17:45.255788 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6963 12:17:45.262470 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6964 12:17:45.265385 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6965 12:17:45.268950 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6966 12:17:45.275398 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6967 12:17:45.275978 ==
6968 12:17:45.278556 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 12:17:45.282382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 12:17:45.282811 ==
6971 12:17:45.283148 DQS Delay:
6972 12:17:45.285737 DQS0 = 43, DQS1 = 51
6973 12:17:45.286278 DQM Delay:
6974 12:17:45.288856 DQM0 = 11, DQM1 = 13
6975 12:17:45.289284 DQ Delay:
6976 12:17:45.291999 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6977 12:17:45.295252 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6978 12:17:45.298178 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6979 12:17:45.301929 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6980 12:17:45.302356
6981 12:17:45.302693
6982 12:17:45.303004 ==
6983 12:17:45.305242 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 12:17:45.308457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 12:17:45.308958 ==
6986 12:17:45.309297
6987 12:17:45.309607
6988 12:17:45.311555 TX Vref Scan disable
6989 12:17:45.315186 == TX Byte 0 ==
6990 12:17:45.318432 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6991 12:17:45.321701 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6992 12:17:45.322125 == TX Byte 1 ==
6993 12:17:45.327982 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6994 12:17:45.331681 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6995 12:17:45.332108 ==
6996 12:17:45.334845 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 12:17:45.338087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 12:17:45.338513 ==
6999 12:17:45.341203
7000 12:17:45.341627
7001 12:17:45.341962 TX Vref Scan disable
7002 12:17:45.345036 == TX Byte 0 ==
7003 12:17:45.348085 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
7004 12:17:45.351404 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
7005 12:17:45.354535 == TX Byte 1 ==
7006 12:17:45.357927 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
7007 12:17:45.361414 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7008 12:17:45.361839
7009 12:17:45.362220 [DATLAT]
7010 12:17:45.364363 Freq=400, CH1 RK1
7011 12:17:45.364838
7012 12:17:45.367871 DATLAT Default: 0xe
7013 12:17:45.368291 0, 0xFFFF, sum = 0
7014 12:17:45.370957 1, 0xFFFF, sum = 0
7015 12:17:45.371389 2, 0xFFFF, sum = 0
7016 12:17:45.374430 3, 0xFFFF, sum = 0
7017 12:17:45.374861 4, 0xFFFF, sum = 0
7018 12:17:45.377819 5, 0xFFFF, sum = 0
7019 12:17:45.378252 6, 0xFFFF, sum = 0
7020 12:17:45.380841 7, 0xFFFF, sum = 0
7021 12:17:45.381291 8, 0xFFFF, sum = 0
7022 12:17:45.384573 9, 0xFFFF, sum = 0
7023 12:17:45.385005 10, 0xFFFF, sum = 0
7024 12:17:45.387829 11, 0xFFFF, sum = 0
7025 12:17:45.388258 12, 0xFFFF, sum = 0
7026 12:17:45.391067 13, 0x0, sum = 1
7027 12:17:45.391609 14, 0x0, sum = 2
7028 12:17:45.394118 15, 0x0, sum = 3
7029 12:17:45.394549 16, 0x0, sum = 4
7030 12:17:45.397651 best_step = 14
7031 12:17:45.398074
7032 12:17:45.398402 ==
7033 12:17:45.400783 Dram Type= 6, Freq= 0, CH_1, rank 1
7034 12:17:45.403904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7035 12:17:45.404331 ==
7036 12:17:45.407716 RX Vref Scan: 0
7037 12:17:45.408245
7038 12:17:45.408645 RX Vref 0 -> 0, step: 1
7039 12:17:45.408974
7040 12:17:45.410810 RX Delay -343 -> 252, step: 8
7041 12:17:45.418355 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7042 12:17:45.422201 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7043 12:17:45.425216 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7044 12:17:45.431576 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7045 12:17:45.434764 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7046 12:17:45.438456 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7047 12:17:45.441483 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7048 12:17:45.448370 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7049 12:17:45.451478 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7050 12:17:45.454829 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7051 12:17:45.457804 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
7052 12:17:45.464313 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7053 12:17:45.468043 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7054 12:17:45.471503 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7055 12:17:45.474413 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7056 12:17:45.480940 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7057 12:17:45.481374 ==
7058 12:17:45.484336 Dram Type= 6, Freq= 0, CH_1, rank 1
7059 12:17:45.488182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7060 12:17:45.488647 ==
7061 12:17:45.488994 DQS Delay:
7062 12:17:45.491327 DQS0 = 44, DQS1 = 56
7063 12:17:45.491751 DQM Delay:
7064 12:17:45.494441 DQM0 = 8, DQM1 = 11
7065 12:17:45.494866 DQ Delay:
7066 12:17:45.497718 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
7067 12:17:45.500921 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7068 12:17:45.504058 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7069 12:17:45.507760 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7070 12:17:45.508203
7071 12:17:45.508584
7072 12:17:45.513890 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7073 12:17:45.517702 CH1 RK1: MR19=C0C, MR18=6C5A
7074 12:17:45.524135 CH1_RK1: MR19=0xC0C, MR18=0x6C5A, DQSOSC=396, MR23=63, INC=376, DEC=251
7075 12:17:45.527359 [RxdqsGatingPostProcess] freq 400
7076 12:17:45.533716 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7077 12:17:45.537384 best DQS0 dly(2T, 0.5T) = (0, 10)
7078 12:17:45.540579 best DQS1 dly(2T, 0.5T) = (0, 10)
7079 12:17:45.543839 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7080 12:17:45.547190 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7081 12:17:45.550680 best DQS0 dly(2T, 0.5T) = (0, 10)
7082 12:17:45.551113 best DQS1 dly(2T, 0.5T) = (0, 10)
7083 12:17:45.553688 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7084 12:17:45.557020 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7085 12:17:45.559939 Pre-setting of DQS Precalculation
7086 12:17:45.566930 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7087 12:17:45.573343 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7088 12:17:45.579938 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7089 12:17:45.580378
7090 12:17:45.580772
7091 12:17:45.582893 [Calibration Summary] 800 Mbps
7092 12:17:45.586371 CH 0, Rank 0
7093 12:17:45.586821 SW Impedance : PASS
7094 12:17:45.589829 DUTY Scan : NO K
7095 12:17:45.592805 ZQ Calibration : PASS
7096 12:17:45.593259 Jitter Meter : NO K
7097 12:17:45.596329 CBT Training : PASS
7098 12:17:45.596822 Write leveling : PASS
7099 12:17:45.599417 RX DQS gating : PASS
7100 12:17:45.603499 RX DQ/DQS(RDDQC) : PASS
7101 12:17:45.604038 TX DQ/DQS : PASS
7102 12:17:45.606583 RX DATLAT : PASS
7103 12:17:45.609601 RX DQ/DQS(Engine): PASS
7104 12:17:45.610042 TX OE : NO K
7105 12:17:45.612621 All Pass.
7106 12:17:45.613052
7107 12:17:45.613397 CH 0, Rank 1
7108 12:17:45.616434 SW Impedance : PASS
7109 12:17:45.616931 DUTY Scan : NO K
7110 12:17:45.619639 ZQ Calibration : PASS
7111 12:17:45.623062 Jitter Meter : NO K
7112 12:17:45.623493 CBT Training : PASS
7113 12:17:45.625517 Write leveling : NO K
7114 12:17:45.629305 RX DQS gating : PASS
7115 12:17:45.629741 RX DQ/DQS(RDDQC) : PASS
7116 12:17:45.632590 TX DQ/DQS : PASS
7117 12:17:45.635740 RX DATLAT : PASS
7118 12:17:45.636258 RX DQ/DQS(Engine): PASS
7119 12:17:45.639132 TX OE : NO K
7120 12:17:45.639651 All Pass.
7121 12:17:45.639994
7122 12:17:45.642851 CH 1, Rank 0
7123 12:17:45.643413 SW Impedance : PASS
7124 12:17:45.645688 DUTY Scan : NO K
7125 12:17:45.648658 ZQ Calibration : PASS
7126 12:17:45.649100 Jitter Meter : NO K
7127 12:17:45.652542 CBT Training : PASS
7128 12:17:45.655596 Write leveling : PASS
7129 12:17:45.656022 RX DQS gating : PASS
7130 12:17:45.658814 RX DQ/DQS(RDDQC) : PASS
7131 12:17:45.661967 TX DQ/DQS : PASS
7132 12:17:45.662515 RX DATLAT : PASS
7133 12:17:45.665146 RX DQ/DQS(Engine): PASS
7134 12:17:45.668804 TX OE : NO K
7135 12:17:45.669235 All Pass.
7136 12:17:45.669576
7137 12:17:45.669890 CH 1, Rank 1
7138 12:17:45.672083 SW Impedance : PASS
7139 12:17:45.675129 DUTY Scan : NO K
7140 12:17:45.675560 ZQ Calibration : PASS
7141 12:17:45.678576 Jitter Meter : NO K
7142 12:17:45.681596 CBT Training : PASS
7143 12:17:45.682024 Write leveling : NO K
7144 12:17:45.685343 RX DQS gating : PASS
7145 12:17:45.688311 RX DQ/DQS(RDDQC) : PASS
7146 12:17:45.688779 TX DQ/DQS : PASS
7147 12:17:45.691717 RX DATLAT : PASS
7148 12:17:45.692144 RX DQ/DQS(Engine): PASS
7149 12:17:45.695277 TX OE : NO K
7150 12:17:45.695707 All Pass.
7151 12:17:45.696049
7152 12:17:45.698222 DramC Write-DBI off
7153 12:17:45.701527 PER_BANK_REFRESH: Hybrid Mode
7154 12:17:45.701971 TX_TRACKING: ON
7155 12:17:45.711471 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7156 12:17:45.714480 [FAST_K] Save calibration result to emmc
7157 12:17:45.718312 dramc_set_vcore_voltage set vcore to 725000
7158 12:17:45.721338 Read voltage for 1600, 0
7159 12:17:45.721780 Vio18 = 0
7160 12:17:45.724725 Vcore = 725000
7161 12:17:45.725253 Vdram = 0
7162 12:17:45.725694 Vddq = 0
7163 12:17:45.726102 Vmddr = 0
7164 12:17:45.731047 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7165 12:17:45.737940 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7166 12:17:45.738369 MEM_TYPE=3, freq_sel=13
7167 12:17:45.741089 sv_algorithm_assistance_LP4_3733
7168 12:17:45.744713 ============ PULL DRAM RESETB DOWN ============
7169 12:17:45.751284 ========== PULL DRAM RESETB DOWN end =========
7170 12:17:45.754142 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7171 12:17:45.757835 ===================================
7172 12:17:45.761078 LPDDR4 DRAM CONFIGURATION
7173 12:17:45.764236 ===================================
7174 12:17:45.764696 EX_ROW_EN[0] = 0x0
7175 12:17:45.767756 EX_ROW_EN[1] = 0x0
7176 12:17:45.771133 LP4Y_EN = 0x0
7177 12:17:45.771944 WORK_FSP = 0x1
7178 12:17:45.774168 WL = 0x5
7179 12:17:45.774609 RL = 0x5
7180 12:17:45.777357 BL = 0x2
7181 12:17:45.777874 RPST = 0x0
7182 12:17:45.780336 RD_PRE = 0x0
7183 12:17:45.780830 WR_PRE = 0x1
7184 12:17:45.784338 WR_PST = 0x1
7185 12:17:45.784913 DBI_WR = 0x0
7186 12:17:45.787223 DBI_RD = 0x0
7187 12:17:45.787697 OTF = 0x1
7188 12:17:45.790698 ===================================
7189 12:17:45.794026 ===================================
7190 12:17:45.797204 ANA top config
7191 12:17:45.800201 ===================================
7192 12:17:45.800788 DLL_ASYNC_EN = 0
7193 12:17:45.803755 ALL_SLAVE_EN = 0
7194 12:17:45.807141 NEW_RANK_MODE = 1
7195 12:17:45.810106 DLL_IDLE_MODE = 1
7196 12:17:45.813810 LP45_APHY_COMB_EN = 1
7197 12:17:45.814235 TX_ODT_DIS = 0
7198 12:17:45.816999 NEW_8X_MODE = 1
7199 12:17:45.820049 ===================================
7200 12:17:45.823264 ===================================
7201 12:17:45.827139 data_rate = 3200
7202 12:17:45.829955 CKR = 1
7203 12:17:45.833210 DQ_P2S_RATIO = 8
7204 12:17:45.836776 ===================================
7205 12:17:45.839997 CA_P2S_RATIO = 8
7206 12:17:45.840456 DQ_CA_OPEN = 0
7207 12:17:45.843321 DQ_SEMI_OPEN = 0
7208 12:17:45.846635 CA_SEMI_OPEN = 0
7209 12:17:45.849806 CA_FULL_RATE = 0
7210 12:17:45.853025 DQ_CKDIV4_EN = 0
7211 12:17:45.856247 CA_CKDIV4_EN = 0
7212 12:17:45.856713 CA_PREDIV_EN = 0
7213 12:17:45.860018 PH8_DLY = 12
7214 12:17:45.863290 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7215 12:17:45.866301 DQ_AAMCK_DIV = 4
7216 12:17:45.869545 CA_AAMCK_DIV = 4
7217 12:17:45.873285 CA_ADMCK_DIV = 4
7218 12:17:45.873765 DQ_TRACK_CA_EN = 0
7219 12:17:45.876214 CA_PICK = 1600
7220 12:17:45.879476 CA_MCKIO = 1600
7221 12:17:45.882607 MCKIO_SEMI = 0
7222 12:17:45.885818 PLL_FREQ = 3068
7223 12:17:45.889585 DQ_UI_PI_RATIO = 32
7224 12:17:45.892601 CA_UI_PI_RATIO = 0
7225 12:17:45.896102 ===================================
7226 12:17:45.899548 ===================================
7227 12:17:45.900203 memory_type:LPDDR4
7228 12:17:45.902199 GP_NUM : 10
7229 12:17:45.905719 SRAM_EN : 1
7230 12:17:45.905842 MD32_EN : 0
7231 12:17:45.908797 ===================================
7232 12:17:45.912232 [ANA_INIT] >>>>>>>>>>>>>>
7233 12:17:45.915237 <<<<<< [CONFIGURE PHASE]: ANA_TX
7234 12:17:45.918700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7235 12:17:45.921830 ===================================
7236 12:17:45.925484 data_rate = 3200,PCW = 0X7600
7237 12:17:45.928709 ===================================
7238 12:17:45.931731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7239 12:17:45.935423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7240 12:17:45.941791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7241 12:17:45.948687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7242 12:17:45.951831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7243 12:17:45.955055 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7244 12:17:45.955158 [ANA_INIT] flow start
7245 12:17:45.958120 [ANA_INIT] PLL >>>>>>>>
7246 12:17:45.961322 [ANA_INIT] PLL <<<<<<<<
7247 12:17:45.961427 [ANA_INIT] MIDPI >>>>>>>>
7248 12:17:45.964971 [ANA_INIT] MIDPI <<<<<<<<
7249 12:17:45.968119 [ANA_INIT] DLL >>>>>>>>
7250 12:17:45.968226 [ANA_INIT] DLL <<<<<<<<
7251 12:17:45.971225 [ANA_INIT] flow end
7252 12:17:45.975001 ============ LP4 DIFF to SE enter ============
7253 12:17:45.981247 ============ LP4 DIFF to SE exit ============
7254 12:17:45.981353 [ANA_INIT] <<<<<<<<<<<<<
7255 12:17:45.984385 [Flow] Enable top DCM control >>>>>
7256 12:17:45.988060 [Flow] Enable top DCM control <<<<<
7257 12:17:45.991192 Enable DLL master slave shuffle
7258 12:17:45.997427 ==============================================================
7259 12:17:45.997534 Gating Mode config
7260 12:17:46.004042 ==============================================================
7261 12:17:46.007763 Config description:
7262 12:17:46.017253 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7263 12:17:46.023706 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7264 12:17:46.027036 SELPH_MODE 0: By rank 1: By Phase
7265 12:17:46.034057 ==============================================================
7266 12:17:46.037291 GAT_TRACK_EN = 1
7267 12:17:46.040397 RX_GATING_MODE = 2
7268 12:17:46.040509 RX_GATING_TRACK_MODE = 2
7269 12:17:46.043783 SELPH_MODE = 1
7270 12:17:46.047470 PICG_EARLY_EN = 1
7271 12:17:46.050721 VALID_LAT_VALUE = 1
7272 12:17:46.057047 ==============================================================
7273 12:17:46.060282 Enter into Gating configuration >>>>
7274 12:17:46.064115 Exit from Gating configuration <<<<
7275 12:17:46.067407 Enter into DVFS_PRE_config >>>>>
7276 12:17:46.076934 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7277 12:17:46.080090 Exit from DVFS_PRE_config <<<<<
7278 12:17:46.083867 Enter into PICG configuration >>>>
7279 12:17:46.086971 Exit from PICG configuration <<<<
7280 12:17:46.090094 [RX_INPUT] configuration >>>>>
7281 12:17:46.093295 [RX_INPUT] configuration <<<<<
7282 12:17:46.097237 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7283 12:17:46.103667 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7284 12:17:46.110576 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7285 12:17:46.117218 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7286 12:17:46.123502 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7287 12:17:46.127019 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7288 12:17:46.133438 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7289 12:17:46.136989 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7290 12:17:46.140165 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7291 12:17:46.143312 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7292 12:17:46.150096 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7293 12:17:46.153368 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7294 12:17:46.156400 ===================================
7295 12:17:46.160218 LPDDR4 DRAM CONFIGURATION
7296 12:17:46.163270 ===================================
7297 12:17:46.163871 EX_ROW_EN[0] = 0x0
7298 12:17:46.166299 EX_ROW_EN[1] = 0x0
7299 12:17:46.166942 LP4Y_EN = 0x0
7300 12:17:46.169447 WORK_FSP = 0x1
7301 12:17:46.170108 WL = 0x5
7302 12:17:46.172733 RL = 0x5
7303 12:17:46.173169 BL = 0x2
7304 12:17:46.176324 RPST = 0x0
7305 12:17:46.179392 RD_PRE = 0x0
7306 12:17:46.179819 WR_PRE = 0x1
7307 12:17:46.183163 WR_PST = 0x1
7308 12:17:46.183589 DBI_WR = 0x0
7309 12:17:46.186337 DBI_RD = 0x0
7310 12:17:46.186764 OTF = 0x1
7311 12:17:46.189555 ===================================
7312 12:17:46.192786 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7313 12:17:46.199036 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7314 12:17:46.203105 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7315 12:17:46.205926 ===================================
7316 12:17:46.208952 LPDDR4 DRAM CONFIGURATION
7317 12:17:46.212655 ===================================
7318 12:17:46.213088 EX_ROW_EN[0] = 0x10
7319 12:17:46.215717 EX_ROW_EN[1] = 0x0
7320 12:17:46.216146 LP4Y_EN = 0x0
7321 12:17:46.218787 WORK_FSP = 0x1
7322 12:17:46.219216 WL = 0x5
7323 12:17:46.222351 RL = 0x5
7324 12:17:46.225416 BL = 0x2
7325 12:17:46.225869 RPST = 0x0
7326 12:17:46.228971 RD_PRE = 0x0
7327 12:17:46.229402 WR_PRE = 0x1
7328 12:17:46.232074 WR_PST = 0x1
7329 12:17:46.232504 DBI_WR = 0x0
7330 12:17:46.235695 DBI_RD = 0x0
7331 12:17:46.236124 OTF = 0x1
7332 12:17:46.239124 ===================================
7333 12:17:46.245327 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7334 12:17:46.245758 ==
7335 12:17:46.248985 Dram Type= 6, Freq= 0, CH_0, rank 0
7336 12:17:46.251755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7337 12:17:46.251839 ==
7338 12:17:46.254993 [Duty_Offset_Calibration]
7339 12:17:46.258067 B0:1 B1:-1 CA:0
7340 12:17:46.258201
7341 12:17:46.261386 [DutyScan_Calibration_Flow] k_type=0
7342 12:17:46.269929
7343 12:17:46.270024 ==CLK 0==
7344 12:17:46.273275 Final CLK duty delay cell = 0
7345 12:17:46.277194 [0] MAX Duty = 5125%(X100), DQS PI = 20
7346 12:17:46.280332 [0] MIN Duty = 4907%(X100), DQS PI = 6
7347 12:17:46.283166 [0] AVG Duty = 5016%(X100)
7348 12:17:46.283289
7349 12:17:46.286484 CH0 CLK Duty spec in!! Max-Min= 218%
7350 12:17:46.290073 [DutyScan_Calibration_Flow] ====Done====
7351 12:17:46.290199
7352 12:17:46.293262 [DutyScan_Calibration_Flow] k_type=1
7353 12:17:46.309898
7354 12:17:46.310194 ==DQS 0 ==
7355 12:17:46.313037 Final DQS duty delay cell = -4
7356 12:17:46.316264 [-4] MAX Duty = 5000%(X100), DQS PI = 36
7357 12:17:46.319294 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7358 12:17:46.323071 [-4] AVG Duty = 4922%(X100)
7359 12:17:46.323460
7360 12:17:46.323879 ==DQS 1 ==
7361 12:17:46.326514 Final DQS duty delay cell = 0
7362 12:17:46.329515 [0] MAX Duty = 5156%(X100), DQS PI = 0
7363 12:17:46.332600 [0] MIN Duty = 5031%(X100), DQS PI = 20
7364 12:17:46.336253 [0] AVG Duty = 5093%(X100)
7365 12:17:46.336713
7366 12:17:46.339221 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7367 12:17:46.339642
7368 12:17:46.342624 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7369 12:17:46.345815 [DutyScan_Calibration_Flow] ====Done====
7370 12:17:46.345988
7371 12:17:46.348907 [DutyScan_Calibration_Flow] k_type=3
7372 12:17:46.366498
7373 12:17:46.366582 ==DQM 0 ==
7374 12:17:46.370237 Final DQM duty delay cell = 0
7375 12:17:46.373536 [0] MAX Duty = 5124%(X100), DQS PI = 24
7376 12:17:46.376652 [0] MIN Duty = 4907%(X100), DQS PI = 8
7377 12:17:46.379716 [0] AVG Duty = 5015%(X100)
7378 12:17:46.379789
7379 12:17:46.379851 ==DQM 1 ==
7380 12:17:46.382918 Final DQM duty delay cell = 0
7381 12:17:46.386679 [0] MAX Duty = 5031%(X100), DQS PI = 6
7382 12:17:46.389791 [0] MIN Duty = 4782%(X100), DQS PI = 22
7383 12:17:46.392897 [0] AVG Duty = 4906%(X100)
7384 12:17:46.392970
7385 12:17:46.396674 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7386 12:17:46.396750
7387 12:17:46.399796 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7388 12:17:46.402948 [DutyScan_Calibration_Flow] ====Done====
7389 12:17:46.403022
7390 12:17:46.406193 [DutyScan_Calibration_Flow] k_type=2
7391 12:17:46.423300
7392 12:17:46.423383 ==DQ 0 ==
7393 12:17:46.426245 Final DQ duty delay cell = -4
7394 12:17:46.429876 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7395 12:17:46.432948 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7396 12:17:46.436374 [-4] AVG Duty = 4953%(X100)
7397 12:17:46.436493
7398 12:17:46.436589 ==DQ 1 ==
7399 12:17:46.439505 Final DQ duty delay cell = 0
7400 12:17:46.443070 [0] MAX Duty = 5125%(X100), DQS PI = 4
7401 12:17:46.445932 [0] MIN Duty = 4969%(X100), DQS PI = 38
7402 12:17:46.449601 [0] AVG Duty = 5047%(X100)
7403 12:17:46.449680
7404 12:17:46.452646 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7405 12:17:46.452716
7406 12:17:46.456041 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7407 12:17:46.459273 [DutyScan_Calibration_Flow] ====Done====
7408 12:17:46.459346 ==
7409 12:17:46.462465 Dram Type= 6, Freq= 0, CH_1, rank 0
7410 12:17:46.466099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7411 12:17:46.466178 ==
7412 12:17:46.469228 [Duty_Offset_Calibration]
7413 12:17:46.469300 B0:-1 B1:1 CA:2
7414 12:17:46.469361
7415 12:17:46.472901 [DutyScan_Calibration_Flow] k_type=0
7416 12:17:46.483672
7417 12:17:46.483757 ==CLK 0==
7418 12:17:46.486742 Final CLK duty delay cell = 0
7419 12:17:46.489968 [0] MAX Duty = 5187%(X100), DQS PI = 22
7420 12:17:46.493297 [0] MIN Duty = 5031%(X100), DQS PI = 30
7421 12:17:46.497045 [0] AVG Duty = 5109%(X100)
7422 12:17:46.497120
7423 12:17:46.500227 CH1 CLK Duty spec in!! Max-Min= 156%
7424 12:17:46.503418 [DutyScan_Calibration_Flow] ====Done====
7425 12:17:46.503497
7426 12:17:46.506596 [DutyScan_Calibration_Flow] k_type=1
7427 12:17:46.523576
7428 12:17:46.523657 ==DQS 0 ==
7429 12:17:46.526775 Final DQS duty delay cell = 0
7430 12:17:46.529957 [0] MAX Duty = 5156%(X100), DQS PI = 20
7431 12:17:46.532946 [0] MIN Duty = 4907%(X100), DQS PI = 40
7432 12:17:46.536557 [0] AVG Duty = 5031%(X100)
7433 12:17:46.536632
7434 12:17:46.536693 ==DQS 1 ==
7435 12:17:46.539545 Final DQS duty delay cell = 0
7436 12:17:46.542999 [0] MAX Duty = 5093%(X100), DQS PI = 4
7437 12:17:46.546544 [0] MIN Duty = 5000%(X100), DQS PI = 22
7438 12:17:46.549571 [0] AVG Duty = 5046%(X100)
7439 12:17:46.549661
7440 12:17:46.552712 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7441 12:17:46.552797
7442 12:17:46.556313 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7443 12:17:46.559875 [DutyScan_Calibration_Flow] ====Done====
7444 12:17:46.559960
7445 12:17:46.562959 [DutyScan_Calibration_Flow] k_type=3
7446 12:17:46.579896
7447 12:17:46.579999 ==DQM 0 ==
7448 12:17:46.583550 Final DQM duty delay cell = 0
7449 12:17:46.586732 [0] MAX Duty = 5187%(X100), DQS PI = 6
7450 12:17:46.589863 [0] MIN Duty = 5031%(X100), DQS PI = 40
7451 12:17:46.593604 [0] AVG Duty = 5109%(X100)
7452 12:17:46.593704
7453 12:17:46.593800 ==DQM 1 ==
7454 12:17:46.596730 Final DQM duty delay cell = 0
7455 12:17:46.599953 [0] MAX Duty = 5187%(X100), DQS PI = 34
7456 12:17:46.603052 [0] MIN Duty = 4969%(X100), DQS PI = 0
7457 12:17:46.606329 [0] AVG Duty = 5078%(X100)
7458 12:17:46.606413
7459 12:17:46.609971 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7460 12:17:46.610055
7461 12:17:46.613261 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7462 12:17:46.616326 [DutyScan_Calibration_Flow] ====Done====
7463 12:17:46.616414
7464 12:17:46.619475 [DutyScan_Calibration_Flow] k_type=2
7465 12:17:46.636938
7466 12:17:46.637106 ==DQ 0 ==
7467 12:17:46.640103 Final DQ duty delay cell = 0
7468 12:17:46.643785 [0] MAX Duty = 5156%(X100), DQS PI = 0
7469 12:17:46.646824 [0] MIN Duty = 4906%(X100), DQS PI = 40
7470 12:17:46.646984 [0] AVG Duty = 5031%(X100)
7471 12:17:46.650374
7472 12:17:46.650555 ==DQ 1 ==
7473 12:17:46.653308 Final DQ duty delay cell = 0
7474 12:17:46.656809 [0] MAX Duty = 5156%(X100), DQS PI = 42
7475 12:17:46.660349 [0] MIN Duty = 4969%(X100), DQS PI = 26
7476 12:17:46.663270 [0] AVG Duty = 5062%(X100)
7477 12:17:46.663521
7478 12:17:46.666805 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7479 12:17:46.667122
7480 12:17:46.670000 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7481 12:17:46.673156 [DutyScan_Calibration_Flow] ====Done====
7482 12:17:46.676843 nWR fixed to 30
7483 12:17:46.679766 [ModeRegInit_LP4] CH0 RK0
7484 12:17:46.680207 [ModeRegInit_LP4] CH0 RK1
7485 12:17:46.683012 [ModeRegInit_LP4] CH1 RK0
7486 12:17:46.686731 [ModeRegInit_LP4] CH1 RK1
7487 12:17:46.687170 match AC timing 5
7488 12:17:46.692967 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7489 12:17:46.696055 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7490 12:17:46.699849 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7491 12:17:46.706268 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7492 12:17:46.709419 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7493 12:17:46.709938 [MiockJmeterHQA]
7494 12:17:46.713168
7495 12:17:46.713621 [DramcMiockJmeter] u1RxGatingPI = 0
7496 12:17:46.716312 0 : 4365, 4140
7497 12:17:46.716986 4 : 4253, 4027
7498 12:17:46.719250 8 : 4253, 4026
7499 12:17:46.719870 12 : 4253, 4026
7500 12:17:46.722270 16 : 4252, 4027
7501 12:17:46.722863 20 : 4363, 4137
7502 12:17:46.726118 24 : 4363, 4138
7503 12:17:46.726742 28 : 4253, 4027
7504 12:17:46.727286 32 : 4252, 4027
7505 12:17:46.729152 36 : 4253, 4027
7506 12:17:46.729709 40 : 4252, 4027
7507 12:17:46.732330 44 : 4252, 4027
7508 12:17:46.732968 48 : 4363, 4137
7509 12:17:46.736600 52 : 4252, 4027
7510 12:17:46.737234 56 : 4253, 4027
7511 12:17:46.737771 60 : 4253, 4027
7512 12:17:46.739162 64 : 4252, 4027
7513 12:17:46.739717 68 : 4250, 4027
7514 12:17:46.742400 72 : 4363, 4140
7515 12:17:46.743025 76 : 4360, 4138
7516 12:17:46.745559 80 : 4252, 4029
7517 12:17:46.746245 84 : 4250, 4027
7518 12:17:46.749180 88 : 4250, 4027
7519 12:17:46.749832 92 : 4250, 1073
7520 12:17:46.750380 96 : 4255, 0
7521 12:17:46.752576 100 : 4250, 0
7522 12:17:46.753190 104 : 4250, 0
7523 12:17:46.755943 108 : 4250, 0
7524 12:17:46.756553 112 : 4250, 0
7525 12:17:46.757106 116 : 4250, 0
7526 12:17:46.758940 120 : 4249, 0
7527 12:17:46.759529 124 : 4250, 0
7528 12:17:46.762128 128 : 4361, 0
7529 12:17:46.762240 132 : 4361, 0
7530 12:17:46.762341 136 : 4360, 0
7531 12:17:46.765465 140 : 4250, 0
7532 12:17:46.765579 144 : 4250, 0
7533 12:17:46.765681 148 : 4250, 0
7534 12:17:46.768362 152 : 4250, 0
7535 12:17:46.768489 156 : 4252, 0
7536 12:17:46.771838 160 : 4250, 0
7537 12:17:46.771940 164 : 4253, 0
7538 12:17:46.772042 168 : 4250, 0
7539 12:17:46.775278 172 : 4250, 0
7540 12:17:46.775395 176 : 4250, 0
7541 12:17:46.778295 180 : 4360, 0
7542 12:17:46.778403 184 : 4360, 0
7543 12:17:46.778504 188 : 4249, 0
7544 12:17:46.781956 192 : 4250, 0
7545 12:17:46.782070 196 : 4250, 0
7546 12:17:46.785182 200 : 4361, 0
7547 12:17:46.785293 204 : 4250, 0
7548 12:17:46.785389 208 : 4250, 0
7549 12:17:46.788217 212 : 4250, 0
7550 12:17:46.788320 216 : 4249, 0
7551 12:17:46.791424 220 : 4250, 0
7552 12:17:46.791566 224 : 4250, 199
7553 12:17:46.791669 228 : 4363, 3605
7554 12:17:46.794984 232 : 4253, 4029
7555 12:17:46.795089 236 : 4250, 4027
7556 12:17:46.798084 240 : 4361, 4137
7557 12:17:46.798230 244 : 4250, 4027
7558 12:17:46.801315 248 : 4250, 4027
7559 12:17:46.801455 252 : 4360, 4137
7560 12:17:46.804403 256 : 4250, 4027
7561 12:17:46.804508 260 : 4250, 4027
7562 12:17:46.808269 264 : 4250, 4027
7563 12:17:46.808377 268 : 4250, 4027
7564 12:17:46.811351 272 : 4250, 4027
7565 12:17:46.811457 276 : 4250, 4027
7566 12:17:46.814526 280 : 4361, 4138
7567 12:17:46.814632 284 : 4250, 4027
7568 12:17:46.817662 288 : 4250, 4027
7569 12:17:46.817765 292 : 4361, 4137
7570 12:17:46.817867 296 : 4250, 4027
7571 12:17:46.821453 300 : 4250, 4026
7572 12:17:46.821561 304 : 4360, 4138
7573 12:17:46.824530 308 : 4250, 4027
7574 12:17:46.824610 312 : 4250, 4027
7575 12:17:46.827685 316 : 4250, 4027
7576 12:17:46.827762 320 : 4250, 4027
7577 12:17:46.831408 324 : 4250, 4027
7578 12:17:46.831489 328 : 4250, 4027
7579 12:17:46.834654 332 : 4361, 4138
7580 12:17:46.834769 336 : 4250, 3859
7581 12:17:46.837885 340 : 4250, 2351
7582 12:17:46.837995 344 : 4361, 66
7583 12:17:46.838091
7584 12:17:46.840997 MIOCK jitter meter ch=0
7585 12:17:46.841100
7586 12:17:46.844671 1T = (344-92) = 252 dly cells
7587 12:17:46.847847 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7588 12:17:46.847926 ==
7589 12:17:46.850991 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 12:17:46.857840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 12:17:46.857950 ==
7592 12:17:46.860763 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7593 12:17:46.867285 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7594 12:17:46.870886 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7595 12:17:46.877553 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7596 12:17:46.885245 [CA 0] Center 43 (12~74) winsize 63
7597 12:17:46.888703 [CA 1] Center 42 (12~73) winsize 62
7598 12:17:46.892245 [CA 2] Center 38 (9~68) winsize 60
7599 12:17:46.895288 [CA 3] Center 38 (8~68) winsize 61
7600 12:17:46.898500 [CA 4] Center 36 (7~66) winsize 60
7601 12:17:46.901582 [CA 5] Center 35 (6~65) winsize 60
7602 12:17:46.901660
7603 12:17:46.905382 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7604 12:17:46.905489
7605 12:17:46.911695 [CATrainingPosCal] consider 1 rank data
7606 12:17:46.911777 u2DelayCellTimex100 = 258/100 ps
7607 12:17:46.918431 CA0 delay=43 (12~74),Diff = 8 PI (30 cell)
7608 12:17:46.921635 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7609 12:17:46.924774 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7610 12:17:46.928401 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7611 12:17:46.931546 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7612 12:17:46.934707 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7613 12:17:46.934817
7614 12:17:46.938491 CA PerBit enable=1, Macro0, CA PI delay=35
7615 12:17:46.938618
7616 12:17:46.941558 [CBTSetCACLKResult] CA Dly = 35
7617 12:17:46.944773 CS Dly: 11 (0~42)
7618 12:17:46.947916 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7619 12:17:46.950975 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7620 12:17:46.951096 ==
7621 12:17:46.954702 Dram Type= 6, Freq= 0, CH_0, rank 1
7622 12:17:46.961268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 12:17:46.961386 ==
7624 12:17:46.964316 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7625 12:17:46.970935 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7626 12:17:46.974518 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7627 12:17:46.981027 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7628 12:17:46.989191 [CA 0] Center 43 (13~74) winsize 62
7629 12:17:46.992061 [CA 1] Center 44 (14~74) winsize 61
7630 12:17:46.995663 [CA 2] Center 38 (9~68) winsize 60
7631 12:17:46.999310 [CA 3] Center 38 (9~68) winsize 60
7632 12:17:47.001870 [CA 4] Center 36 (7~66) winsize 60
7633 12:17:47.005670 [CA 5] Center 36 (7~66) winsize 60
7634 12:17:47.005778
7635 12:17:47.008964 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7636 12:17:47.009045
7637 12:17:47.012010 [CATrainingPosCal] consider 2 rank data
7638 12:17:47.015215 u2DelayCellTimex100 = 258/100 ps
7639 12:17:47.018826 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7640 12:17:47.025099 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7641 12:17:47.028942 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7642 12:17:47.032138 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7643 12:17:47.035354 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7644 12:17:47.038494 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7645 12:17:47.038604
7646 12:17:47.041500 CA PerBit enable=1, Macro0, CA PI delay=36
7647 12:17:47.041604
7648 12:17:47.045218 [CBTSetCACLKResult] CA Dly = 36
7649 12:17:47.048392 CS Dly: 11 (0~43)
7650 12:17:47.051670 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7651 12:17:47.054811 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7652 12:17:47.054912
7653 12:17:47.057924 ----->DramcWriteLeveling(PI) begin...
7654 12:17:47.058028 ==
7655 12:17:47.061643 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 12:17:47.068339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 12:17:47.068450 ==
7658 12:17:47.071401 Write leveling (Byte 0): 36 => 36
7659 12:17:47.074547 Write leveling (Byte 1): 26 => 26
7660 12:17:47.074650 DramcWriteLeveling(PI) end<-----
7661 12:17:47.077655
7662 12:17:47.077753 ==
7663 12:17:47.081247 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 12:17:47.084269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 12:17:47.084374 ==
7666 12:17:47.088056 [Gating] SW mode calibration
7667 12:17:47.094363 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7668 12:17:47.097967 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7669 12:17:47.104633 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 12:17:47.107647 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 12:17:47.110808 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 12:17:47.117700 1 4 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7673 12:17:47.120788 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7674 12:17:47.124006 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7675 12:17:47.130916 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7676 12:17:47.134026 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7677 12:17:47.137828 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7678 12:17:47.144069 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7679 12:17:47.147245 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7680 12:17:47.150435 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7681 12:17:47.157421 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7682 12:17:47.160960 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7683 12:17:47.164627 1 5 24 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7684 12:17:47.170837 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7685 12:17:47.173911 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7686 12:17:47.177564 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7687 12:17:47.183835 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7688 12:17:47.187282 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7689 12:17:47.190943 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7690 12:17:47.197372 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7691 12:17:47.200861 1 6 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7692 12:17:47.203662 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7693 12:17:47.210335 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7694 12:17:47.213907 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7695 12:17:47.217038 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7696 12:17:47.223932 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7697 12:17:47.227150 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7698 12:17:47.230139 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7699 12:17:47.237056 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 12:17:47.240213 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 12:17:47.243481 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 12:17:47.250465 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 12:17:47.253691 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 12:17:47.256694 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 12:17:47.263115 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 12:17:47.266779 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 12:17:47.270227 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7708 12:17:47.276049 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7709 12:17:47.279661 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7710 12:17:47.282858 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7711 12:17:47.289662 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7712 12:17:47.292751 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7713 12:17:47.296405 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7714 12:17:47.302869 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7715 12:17:47.303345 Total UI for P1: 0, mck2ui 16
7716 12:17:47.309135 best dqsien dly found for B0: ( 1, 9, 14)
7717 12:17:47.313003 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7718 12:17:47.316152 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7719 12:17:47.319742 Total UI for P1: 0, mck2ui 16
7720 12:17:47.322871 best dqsien dly found for B1: ( 1, 9, 22)
7721 12:17:47.325885 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7722 12:17:47.329095 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7723 12:17:47.329528
7724 12:17:47.335993 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7725 12:17:47.339234 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7726 12:17:47.342424 [Gating] SW calibration Done
7727 12:17:47.342853 ==
7728 12:17:47.345845 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 12:17:47.348734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 12:17:47.349245 ==
7731 12:17:47.352338 RX Vref Scan: 0
7732 12:17:47.352785
7733 12:17:47.353127 RX Vref 0 -> 0, step: 1
7734 12:17:47.353444
7735 12:17:47.355466 RX Delay 0 -> 252, step: 8
7736 12:17:47.358584 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7737 12:17:47.362229 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7738 12:17:47.368416 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7739 12:17:47.372221 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7740 12:17:47.375514 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7741 12:17:47.378659 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7742 12:17:47.381850 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7743 12:17:47.388593 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7744 12:17:47.391567 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7745 12:17:47.395371 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7746 12:17:47.398309 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7747 12:17:47.404782 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7748 12:17:47.408183 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7749 12:17:47.411213 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7750 12:17:47.414936 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7751 12:17:47.418024 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7752 12:17:47.421578 ==
7753 12:17:47.424511 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 12:17:47.427804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 12:17:47.428237 ==
7756 12:17:47.428619 DQS Delay:
7757 12:17:47.431775 DQS0 = 0, DQS1 = 0
7758 12:17:47.432312 DQM Delay:
7759 12:17:47.434551 DQM0 = 136, DQM1 = 125
7760 12:17:47.435123 DQ Delay:
7761 12:17:47.437870 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7762 12:17:47.440798 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =147
7763 12:17:47.444742 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7764 12:17:47.447767 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7765 12:17:47.448203
7766 12:17:47.448584
7767 12:17:47.448918 ==
7768 12:17:47.451025 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 12:17:47.457934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 12:17:47.458467 ==
7771 12:17:47.458997
7772 12:17:47.459510
7773 12:17:47.459941 TX Vref Scan disable
7774 12:17:47.461849 == TX Byte 0 ==
7775 12:17:47.465037 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7776 12:17:47.471379 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7777 12:17:47.471815 == TX Byte 1 ==
7778 12:17:47.474566 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7779 12:17:47.481505 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7780 12:17:47.481952 ==
7781 12:17:47.484503 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 12:17:47.487777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 12:17:47.488207 ==
7784 12:17:47.501250
7785 12:17:47.504124 TX Vref early break, caculate TX vref
7786 12:17:47.507896 TX Vref=16, minBit 11, minWin=21, winSum=363
7787 12:17:47.511103 TX Vref=18, minBit 4, minWin=22, winSum=375
7788 12:17:47.514233 TX Vref=20, minBit 1, minWin=23, winSum=388
7789 12:17:47.517444 TX Vref=22, minBit 4, minWin=23, winSum=402
7790 12:17:47.523999 TX Vref=24, minBit 0, minWin=25, winSum=407
7791 12:17:47.527930 TX Vref=26, minBit 0, minWin=25, winSum=414
7792 12:17:47.530800 TX Vref=28, minBit 0, minWin=24, winSum=415
7793 12:17:47.533752 TX Vref=30, minBit 4, minWin=24, winSum=410
7794 12:17:47.537404 TX Vref=32, minBit 0, minWin=24, winSum=399
7795 12:17:47.540635 TX Vref=34, minBit 7, minWin=23, winSum=389
7796 12:17:47.547173 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
7797 12:17:47.547604
7798 12:17:47.550241 Final TX Range 0 Vref 26
7799 12:17:47.550671
7800 12:17:47.551011 ==
7801 12:17:47.554152 Dram Type= 6, Freq= 0, CH_0, rank 0
7802 12:17:47.557264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7803 12:17:47.557698 ==
7804 12:17:47.558037
7805 12:17:47.558348
7806 12:17:47.560387 TX Vref Scan disable
7807 12:17:47.567377 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7808 12:17:47.567800 == TX Byte 0 ==
7809 12:17:47.570663 u2DelayCellOfst[0]=15 cells (4 PI)
7810 12:17:47.573770 u2DelayCellOfst[1]=18 cells (5 PI)
7811 12:17:47.577063 u2DelayCellOfst[2]=15 cells (4 PI)
7812 12:17:47.580034 u2DelayCellOfst[3]=15 cells (4 PI)
7813 12:17:47.584059 u2DelayCellOfst[4]=11 cells (3 PI)
7814 12:17:47.587275 u2DelayCellOfst[5]=0 cells (0 PI)
7815 12:17:47.590408 u2DelayCellOfst[6]=22 cells (6 PI)
7816 12:17:47.593729 u2DelayCellOfst[7]=22 cells (6 PI)
7817 12:17:47.597207 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7818 12:17:47.600437 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7819 12:17:47.603296 == TX Byte 1 ==
7820 12:17:47.606758 u2DelayCellOfst[8]=0 cells (0 PI)
7821 12:17:47.609978 u2DelayCellOfst[9]=0 cells (0 PI)
7822 12:17:47.613754 u2DelayCellOfst[10]=3 cells (1 PI)
7823 12:17:47.614180 u2DelayCellOfst[11]=0 cells (0 PI)
7824 12:17:47.616718 u2DelayCellOfst[12]=11 cells (3 PI)
7825 12:17:47.620141 u2DelayCellOfst[13]=11 cells (3 PI)
7826 12:17:47.623024 u2DelayCellOfst[14]=11 cells (3 PI)
7827 12:17:47.626591 u2DelayCellOfst[15]=7 cells (2 PI)
7828 12:17:47.633217 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7829 12:17:47.636822 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7830 12:17:47.637249 DramC Write-DBI on
7831 12:17:47.640023 ==
7832 12:17:47.640668 Dram Type= 6, Freq= 0, CH_0, rank 0
7833 12:17:47.646662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7834 12:17:47.647277 ==
7835 12:17:47.647664
7836 12:17:47.648080
7837 12:17:47.649839 TX Vref Scan disable
7838 12:17:47.650421 == TX Byte 0 ==
7839 12:17:47.656328 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7840 12:17:47.656802 == TX Byte 1 ==
7841 12:17:47.659493 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7842 12:17:47.662656 DramC Write-DBI off
7843 12:17:47.663080
7844 12:17:47.663416 [DATLAT]
7845 12:17:47.666697 Freq=1600, CH0 RK0
7846 12:17:47.667413
7847 12:17:47.667771 DATLAT Default: 0xf
7848 12:17:47.669845 0, 0xFFFF, sum = 0
7849 12:17:47.670383 1, 0xFFFF, sum = 0
7850 12:17:47.672772 2, 0xFFFF, sum = 0
7851 12:17:47.673203 3, 0xFFFF, sum = 0
7852 12:17:47.676466 4, 0xFFFF, sum = 0
7853 12:17:47.677055 5, 0xFFFF, sum = 0
7854 12:17:47.679570 6, 0xFFFF, sum = 0
7855 12:17:47.680025 7, 0xFFFF, sum = 0
7856 12:17:47.682545 8, 0xFFFF, sum = 0
7857 12:17:47.686255 9, 0xFFFF, sum = 0
7858 12:17:47.686684 10, 0xFFFF, sum = 0
7859 12:17:47.689357 11, 0xFFFF, sum = 0
7860 12:17:47.689789 12, 0xFFFF, sum = 0
7861 12:17:47.692628 13, 0xFFFF, sum = 0
7862 12:17:47.693058 14, 0x0, sum = 1
7863 12:17:47.695799 15, 0x0, sum = 2
7864 12:17:47.696293 16, 0x0, sum = 3
7865 12:17:47.699305 17, 0x0, sum = 4
7866 12:17:47.699758 best_step = 15
7867 12:17:47.700092
7868 12:17:47.700406 ==
7869 12:17:47.702681 Dram Type= 6, Freq= 0, CH_0, rank 0
7870 12:17:47.706257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7871 12:17:47.709196 ==
7872 12:17:47.709622 RX Vref Scan: 1
7873 12:17:47.709961
7874 12:17:47.712445 Set Vref Range= 24 -> 127
7875 12:17:47.713089
7876 12:17:47.713437 RX Vref 24 -> 127, step: 1
7877 12:17:47.715500
7878 12:17:47.716073 RX Delay 11 -> 252, step: 4
7879 12:17:47.716479
7880 12:17:47.719142 Set Vref, RX VrefLevel [Byte0]: 24
7881 12:17:47.722079 [Byte1]: 24
7882 12:17:47.726144
7883 12:17:47.726570 Set Vref, RX VrefLevel [Byte0]: 25
7884 12:17:47.729292 [Byte1]: 25
7885 12:17:47.733629
7886 12:17:47.734195 Set Vref, RX VrefLevel [Byte0]: 26
7887 12:17:47.736977 [Byte1]: 26
7888 12:17:47.741481
7889 12:17:47.742101 Set Vref, RX VrefLevel [Byte0]: 27
7890 12:17:47.744359 [Byte1]: 27
7891 12:17:47.748867
7892 12:17:47.749291 Set Vref, RX VrefLevel [Byte0]: 28
7893 12:17:47.752236 [Byte1]: 28
7894 12:17:47.756405
7895 12:17:47.756880 Set Vref, RX VrefLevel [Byte0]: 29
7896 12:17:47.759637 [Byte1]: 29
7897 12:17:47.764260
7898 12:17:47.764726 Set Vref, RX VrefLevel [Byte0]: 30
7899 12:17:47.767740 [Byte1]: 30
7900 12:17:47.771947
7901 12:17:47.772447 Set Vref, RX VrefLevel [Byte0]: 31
7902 12:17:47.775190 [Byte1]: 31
7903 12:17:47.779461
7904 12:17:47.779885 Set Vref, RX VrefLevel [Byte0]: 32
7905 12:17:47.782750 [Byte1]: 32
7906 12:17:47.787143
7907 12:17:47.787567 Set Vref, RX VrefLevel [Byte0]: 33
7908 12:17:47.790272 [Byte1]: 33
7909 12:17:47.794902
7910 12:17:47.795530 Set Vref, RX VrefLevel [Byte0]: 34
7911 12:17:47.798011 [Byte1]: 34
7912 12:17:47.802310
7913 12:17:47.802739 Set Vref, RX VrefLevel [Byte0]: 35
7914 12:17:47.805262 [Byte1]: 35
7915 12:17:47.809625
7916 12:17:47.810142 Set Vref, RX VrefLevel [Byte0]: 36
7917 12:17:47.813204 [Byte1]: 36
7918 12:17:47.817654
7919 12:17:47.818092 Set Vref, RX VrefLevel [Byte0]: 37
7920 12:17:47.820822 [Byte1]: 37
7921 12:17:47.825173
7922 12:17:47.825732 Set Vref, RX VrefLevel [Byte0]: 38
7923 12:17:47.828090 [Byte1]: 38
7924 12:17:47.832794
7925 12:17:47.833216 Set Vref, RX VrefLevel [Byte0]: 39
7926 12:17:47.835928 [Byte1]: 39
7927 12:17:47.839919
7928 12:17:47.840368 Set Vref, RX VrefLevel [Byte0]: 40
7929 12:17:47.843726 [Byte1]: 40
7930 12:17:47.847968
7931 12:17:47.848399 Set Vref, RX VrefLevel [Byte0]: 41
7932 12:17:47.851122 [Byte1]: 41
7933 12:17:47.855484
7934 12:17:47.855915 Set Vref, RX VrefLevel [Byte0]: 42
7935 12:17:47.858594 [Byte1]: 42
7936 12:17:47.863068
7937 12:17:47.863629 Set Vref, RX VrefLevel [Byte0]: 43
7938 12:17:47.866768 [Byte1]: 43
7939 12:17:47.870546
7940 12:17:47.870979 Set Vref, RX VrefLevel [Byte0]: 44
7941 12:17:47.874364 [Byte1]: 44
7942 12:17:47.878094
7943 12:17:47.878644 Set Vref, RX VrefLevel [Byte0]: 45
7944 12:17:47.881882 [Byte1]: 45
7945 12:17:47.886282
7946 12:17:47.886819 Set Vref, RX VrefLevel [Byte0]: 46
7947 12:17:47.889361 [Byte1]: 46
7948 12:17:47.893857
7949 12:17:47.894384 Set Vref, RX VrefLevel [Byte0]: 47
7950 12:17:47.896757 [Byte1]: 47
7951 12:17:47.901285
7952 12:17:47.901715 Set Vref, RX VrefLevel [Byte0]: 48
7953 12:17:47.904388 [Byte1]: 48
7954 12:17:47.908793
7955 12:17:47.909225 Set Vref, RX VrefLevel [Byte0]: 49
7956 12:17:47.911767 [Byte1]: 49
7957 12:17:47.916621
7958 12:17:47.917055 Set Vref, RX VrefLevel [Byte0]: 50
7959 12:17:47.919989 [Byte1]: 50
7960 12:17:47.924326
7961 12:17:47.924865 Set Vref, RX VrefLevel [Byte0]: 51
7962 12:17:47.927603 [Byte1]: 51
7963 12:17:47.931919
7964 12:17:47.932476 Set Vref, RX VrefLevel [Byte0]: 52
7965 12:17:47.934648 [Byte1]: 52
7966 12:17:47.939353
7967 12:17:47.939785 Set Vref, RX VrefLevel [Byte0]: 53
7968 12:17:47.942260 [Byte1]: 53
7969 12:17:47.946890
7970 12:17:47.947332 Set Vref, RX VrefLevel [Byte0]: 54
7971 12:17:47.950085 [Byte1]: 54
7972 12:17:47.954304
7973 12:17:47.954739 Set Vref, RX VrefLevel [Byte0]: 55
7974 12:17:47.958045 [Byte1]: 55
7975 12:17:47.961718
7976 12:17:47.962149 Set Vref, RX VrefLevel [Byte0]: 56
7977 12:17:47.965368 [Byte1]: 56
7978 12:17:47.969960
7979 12:17:47.970395 Set Vref, RX VrefLevel [Byte0]: 57
7980 12:17:47.972992 [Byte1]: 57
7981 12:17:47.977529
7982 12:17:47.977972 Set Vref, RX VrefLevel [Byte0]: 58
7983 12:17:47.980572 [Byte1]: 58
7984 12:17:47.984918
7985 12:17:47.985374 Set Vref, RX VrefLevel [Byte0]: 59
7986 12:17:47.987961 [Byte1]: 59
7987 12:17:47.992476
7988 12:17:47.992973 Set Vref, RX VrefLevel [Byte0]: 60
7989 12:17:47.995641 [Byte1]: 60
7990 12:17:48.000031
7991 12:17:48.000468 Set Vref, RX VrefLevel [Byte0]: 61
7992 12:17:48.003245 [Byte1]: 61
7993 12:17:48.007824
7994 12:17:48.008253 Set Vref, RX VrefLevel [Byte0]: 62
7995 12:17:48.010926 [Byte1]: 62
7996 12:17:48.015269
7997 12:17:48.015692 Set Vref, RX VrefLevel [Byte0]: 63
7998 12:17:48.018335 [Byte1]: 63
7999 12:17:48.022992
8000 12:17:48.023415 Set Vref, RX VrefLevel [Byte0]: 64
8001 12:17:48.026322 [Byte1]: 64
8002 12:17:48.030782
8003 12:17:48.031316 Set Vref, RX VrefLevel [Byte0]: 65
8004 12:17:48.033942 [Byte1]: 65
8005 12:17:48.037968
8006 12:17:48.038391 Set Vref, RX VrefLevel [Byte0]: 66
8007 12:17:48.041526 [Byte1]: 66
8008 12:17:48.045739
8009 12:17:48.046163 Set Vref, RX VrefLevel [Byte0]: 67
8010 12:17:48.048713 [Byte1]: 67
8011 12:17:48.053550
8012 12:17:48.053985 Set Vref, RX VrefLevel [Byte0]: 68
8013 12:17:48.059861 [Byte1]: 68
8014 12:17:48.060285
8015 12:17:48.063167 Set Vref, RX VrefLevel [Byte0]: 69
8016 12:17:48.066222 [Byte1]: 69
8017 12:17:48.066653
8018 12:17:48.069899 Set Vref, RX VrefLevel [Byte0]: 70
8019 12:17:48.073268 [Byte1]: 70
8020 12:17:48.076719
8021 12:17:48.077242 Set Vref, RX VrefLevel [Byte0]: 71
8022 12:17:48.079893 [Byte1]: 71
8023 12:17:48.083985
8024 12:17:48.084459 Set Vref, RX VrefLevel [Byte0]: 72
8025 12:17:48.087125 [Byte1]: 72
8026 12:17:48.091350
8027 12:17:48.091771 Set Vref, RX VrefLevel [Byte0]: 73
8028 12:17:48.094943 [Byte1]: 73
8029 12:17:48.099364
8030 12:17:48.099896 Set Vref, RX VrefLevel [Byte0]: 74
8031 12:17:48.102303 [Byte1]: 74
8032 12:17:48.107152
8033 12:17:48.107693 Set Vref, RX VrefLevel [Byte0]: 75
8034 12:17:48.110351 [Byte1]: 75
8035 12:17:48.114533
8036 12:17:48.115127 Set Vref, RX VrefLevel [Byte0]: 76
8037 12:17:48.117608 [Byte1]: 76
8038 12:17:48.121825
8039 12:17:48.122248 Set Vref, RX VrefLevel [Byte0]: 77
8040 12:17:48.125381 [Byte1]: 77
8041 12:17:48.129422
8042 12:17:48.129934 Set Vref, RX VrefLevel [Byte0]: 78
8043 12:17:48.132352 [Byte1]: 78
8044 12:17:48.136783
8045 12:17:48.137206 Set Vref, RX VrefLevel [Byte0]: 79
8046 12:17:48.140651 [Byte1]: 79
8047 12:17:48.145135
8048 12:17:48.145736 Set Vref, RX VrefLevel [Byte0]: 80
8049 12:17:48.148138 [Byte1]: 80
8050 12:17:48.152168
8051 12:17:48.152636 Final RX Vref Byte 0 = 66 to rank0
8052 12:17:48.155444 Final RX Vref Byte 1 = 58 to rank0
8053 12:17:48.159025 Final RX Vref Byte 0 = 66 to rank1
8054 12:17:48.162072 Final RX Vref Byte 1 = 58 to rank1==
8055 12:17:48.165866 Dram Type= 6, Freq= 0, CH_0, rank 0
8056 12:17:48.171969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 12:17:48.172399 ==
8058 12:17:48.172783 DQS Delay:
8059 12:17:48.175200 DQS0 = 0, DQS1 = 0
8060 12:17:48.175623 DQM Delay:
8061 12:17:48.175961 DQM0 = 133, DQM1 = 123
8062 12:17:48.179272 DQ Delay:
8063 12:17:48.182149 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8064 12:17:48.185190 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8065 12:17:48.188471 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =118
8066 12:17:48.191656 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
8067 12:17:48.192205
8068 12:17:48.192585
8069 12:17:48.192904
8070 12:17:48.195398 [DramC_TX_OE_Calibration] TA2
8071 12:17:48.198695 Original DQ_B0 (3 6) =30, OEN = 27
8072 12:17:48.201554 Original DQ_B1 (3 6) =30, OEN = 27
8073 12:17:48.204875 24, 0x0, End_B0=24 End_B1=24
8074 12:17:48.208077 25, 0x0, End_B0=25 End_B1=25
8075 12:17:48.208537 26, 0x0, End_B0=26 End_B1=26
8076 12:17:48.211979 27, 0x0, End_B0=27 End_B1=27
8077 12:17:48.214866 28, 0x0, End_B0=28 End_B1=28
8078 12:17:48.218259 29, 0x0, End_B0=29 End_B1=29
8079 12:17:48.218793 30, 0x0, End_B0=30 End_B1=30
8080 12:17:48.221309 31, 0x4141, End_B0=30 End_B1=30
8081 12:17:48.224629 Byte0 end_step=30 best_step=27
8082 12:17:48.227960 Byte1 end_step=30 best_step=27
8083 12:17:48.231102 Byte0 TX OE(2T, 0.5T) = (3, 3)
8084 12:17:48.234040 Byte1 TX OE(2T, 0.5T) = (3, 3)
8085 12:17:48.234466
8086 12:17:48.234799
8087 12:17:48.241107 [DQSOSCAuto] RK0, (LSB)MR18= 0x2314, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
8088 12:17:48.244341 CH0 RK0: MR19=303, MR18=2314
8089 12:17:48.251058 CH0_RK0: MR19=0x303, MR18=0x2314, DQSOSC=392, MR23=63, INC=24, DEC=16
8090 12:17:48.251570
8091 12:17:48.254052 ----->DramcWriteLeveling(PI) begin...
8092 12:17:48.254584 ==
8093 12:17:48.258185 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 12:17:48.260956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 12:17:48.261504 ==
8096 12:17:48.264036 Write leveling (Byte 0): 36 => 36
8097 12:17:48.267764 Write leveling (Byte 1): 28 => 28
8098 12:17:48.271111 DramcWriteLeveling(PI) end<-----
8099 12:17:48.271639
8100 12:17:48.271981 ==
8101 12:17:48.273816 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 12:17:48.280766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 12:17:48.281197 ==
8104 12:17:48.281536 [Gating] SW mode calibration
8105 12:17:48.290665 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8106 12:17:48.294139 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8107 12:17:48.300406 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8108 12:17:48.303495 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8109 12:17:48.307456 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8110 12:17:48.310542 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8111 12:17:48.316645 1 4 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8112 12:17:48.320326 1 4 20 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
8113 12:17:48.326512 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8114 12:17:48.329988 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8115 12:17:48.333525 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8116 12:17:48.340191 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8117 12:17:48.343660 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8118 12:17:48.346822 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8119 12:17:48.353281 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8120 12:17:48.356354 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8121 12:17:48.359872 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8122 12:17:48.366807 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8123 12:17:48.369700 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8124 12:17:48.373076 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8125 12:17:48.379599 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8126 12:17:48.382752 1 6 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8127 12:17:48.386027 1 6 16 | B1->B0 | 2a2a 4545 | 1 0 | (0 0) (0 0)
8128 12:17:48.392947 1 6 20 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
8129 12:17:48.396256 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8130 12:17:48.399359 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8131 12:17:48.405565 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8132 12:17:48.409537 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8133 12:17:48.412755 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8134 12:17:48.416119 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8135 12:17:48.422485 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8136 12:17:48.425799 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8137 12:17:48.428928 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 12:17:48.435410 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 12:17:48.438904 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 12:17:48.445490 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 12:17:48.448790 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 12:17:48.452003 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 12:17:48.459016 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 12:17:48.462009 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 12:17:48.465034 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 12:17:48.472089 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 12:17:48.475334 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 12:17:48.478385 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 12:17:48.482025 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8150 12:17:48.488448 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8151 12:17:48.492038 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8152 12:17:48.494810 Total UI for P1: 0, mck2ui 16
8153 12:17:48.498412 best dqsien dly found for B0: ( 1, 9, 10)
8154 12:17:48.501459 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8155 12:17:48.508073 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8156 12:17:48.511385 Total UI for P1: 0, mck2ui 16
8157 12:17:48.515262 best dqsien dly found for B1: ( 1, 9, 16)
8158 12:17:48.517860 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8159 12:17:48.521478 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8160 12:17:48.521904
8161 12:17:48.524640 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8162 12:17:48.527892 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8163 12:17:48.531742 [Gating] SW calibration Done
8164 12:17:48.532270 ==
8165 12:17:48.534671 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 12:17:48.537778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 12:17:48.540991 ==
8168 12:17:48.541437 RX Vref Scan: 0
8169 12:17:48.541823
8170 12:17:48.544385 RX Vref 0 -> 0, step: 1
8171 12:17:48.544856
8172 12:17:48.545275 RX Delay 0 -> 252, step: 8
8173 12:17:48.551186 iDelay=208, Bit 0, Center 131 (80 ~ 183) 104
8174 12:17:48.554532 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8175 12:17:48.557844 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8176 12:17:48.560717 iDelay=208, Bit 3, Center 127 (72 ~ 183) 112
8177 12:17:48.564373 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8178 12:17:48.570875 iDelay=208, Bit 5, Center 123 (64 ~ 183) 120
8179 12:17:48.574004 iDelay=208, Bit 6, Center 139 (80 ~ 199) 120
8180 12:17:48.577037 iDelay=208, Bit 7, Center 147 (88 ~ 207) 120
8181 12:17:48.580855 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8182 12:17:48.587072 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8183 12:17:48.590896 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8184 12:17:48.594314 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8185 12:17:48.597465 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8186 12:17:48.600366 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8187 12:17:48.607341 iDelay=208, Bit 14, Center 143 (88 ~ 199) 112
8188 12:17:48.610295 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8189 12:17:48.610723 ==
8190 12:17:48.613338 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 12:17:48.617136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 12:17:48.617567 ==
8193 12:17:48.620690 DQS Delay:
8194 12:17:48.621267 DQS0 = 0, DQS1 = 0
8195 12:17:48.621632 DQM Delay:
8196 12:17:48.623829 DQM0 = 133, DQM1 = 129
8197 12:17:48.624369 DQ Delay:
8198 12:17:48.626768 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8199 12:17:48.629937 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
8200 12:17:48.637070 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8201 12:17:48.640187 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8202 12:17:48.640801
8203 12:17:48.641153
8204 12:17:48.641522 ==
8205 12:17:48.643182 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 12:17:48.646298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 12:17:48.646725 ==
8208 12:17:48.647060
8209 12:17:48.647368
8210 12:17:48.650155 TX Vref Scan disable
8211 12:17:48.653224 == TX Byte 0 ==
8212 12:17:48.656218 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8213 12:17:48.659604 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8214 12:17:48.663615 == TX Byte 1 ==
8215 12:17:48.666408 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8216 12:17:48.669440 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8217 12:17:48.669867 ==
8218 12:17:48.673322 Dram Type= 6, Freq= 0, CH_0, rank 1
8219 12:17:48.676237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8220 12:17:48.679169 ==
8221 12:17:48.692613
8222 12:17:48.695856 TX Vref early break, caculate TX vref
8223 12:17:48.699792 TX Vref=16, minBit 1, minWin=22, winSum=380
8224 12:17:48.702796 TX Vref=18, minBit 0, minWin=23, winSum=384
8225 12:17:48.706237 TX Vref=20, minBit 0, minWin=23, winSum=394
8226 12:17:48.709725 TX Vref=22, minBit 3, minWin=23, winSum=404
8227 12:17:48.712942 TX Vref=24, minBit 3, minWin=24, winSum=411
8228 12:17:48.719177 TX Vref=26, minBit 0, minWin=24, winSum=412
8229 12:17:48.722719 TX Vref=28, minBit 0, minWin=24, winSum=411
8230 12:17:48.726079 TX Vref=30, minBit 0, minWin=24, winSum=407
8231 12:17:48.729111 TX Vref=32, minBit 0, minWin=24, winSum=397
8232 12:17:48.732332 TX Vref=34, minBit 0, minWin=24, winSum=391
8233 12:17:48.736097 TX Vref=36, minBit 1, minWin=22, winSum=378
8234 12:17:48.742424 [TxChooseVref] Worse bit 0, Min win 24, Win sum 412, Final Vref 26
8235 12:17:48.742876
8236 12:17:48.745879 Final TX Range 0 Vref 26
8237 12:17:48.746413
8238 12:17:48.746761 ==
8239 12:17:48.748711 Dram Type= 6, Freq= 0, CH_0, rank 1
8240 12:17:48.752583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 12:17:48.753107 ==
8242 12:17:48.753454
8243 12:17:48.755427
8244 12:17:48.755891 TX Vref Scan disable
8245 12:17:48.762579 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8246 12:17:48.763126 == TX Byte 0 ==
8247 12:17:48.765433 u2DelayCellOfst[0]=15 cells (4 PI)
8248 12:17:48.768785 u2DelayCellOfst[1]=18 cells (5 PI)
8249 12:17:48.771742 u2DelayCellOfst[2]=15 cells (4 PI)
8250 12:17:48.775632 u2DelayCellOfst[3]=18 cells (5 PI)
8251 12:17:48.778930 u2DelayCellOfst[4]=11 cells (3 PI)
8252 12:17:48.781840 u2DelayCellOfst[5]=0 cells (0 PI)
8253 12:17:48.785384 u2DelayCellOfst[6]=18 cells (5 PI)
8254 12:17:48.788355 u2DelayCellOfst[7]=18 cells (5 PI)
8255 12:17:48.792062 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8256 12:17:48.795087 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8257 12:17:48.798636 == TX Byte 1 ==
8258 12:17:48.801755 u2DelayCellOfst[8]=0 cells (0 PI)
8259 12:17:48.804896 u2DelayCellOfst[9]=3 cells (1 PI)
8260 12:17:48.808698 u2DelayCellOfst[10]=7 cells (2 PI)
8261 12:17:48.812286 u2DelayCellOfst[11]=3 cells (1 PI)
8262 12:17:48.815028 u2DelayCellOfst[12]=15 cells (4 PI)
8263 12:17:48.815457 u2DelayCellOfst[13]=11 cells (3 PI)
8264 12:17:48.818254 u2DelayCellOfst[14]=18 cells (5 PI)
8265 12:17:48.822059 u2DelayCellOfst[15]=11 cells (3 PI)
8266 12:17:48.828334 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8267 12:17:48.831395 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8268 12:17:48.831830 DramC Write-DBI on
8269 12:17:48.835233 ==
8270 12:17:48.838359 Dram Type= 6, Freq= 0, CH_0, rank 1
8271 12:17:48.841476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8272 12:17:48.841915 ==
8273 12:17:48.842265
8274 12:17:48.842588
8275 12:17:48.844854 TX Vref Scan disable
8276 12:17:48.845286 == TX Byte 0 ==
8277 12:17:48.851754 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8278 12:17:48.852291 == TX Byte 1 ==
8279 12:17:48.855129 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8280 12:17:48.857979 DramC Write-DBI off
8281 12:17:48.858414
8282 12:17:48.858757 [DATLAT]
8283 12:17:48.861171 Freq=1600, CH0 RK1
8284 12:17:48.861626
8285 12:17:48.861972 DATLAT Default: 0xf
8286 12:17:48.864980 0, 0xFFFF, sum = 0
8287 12:17:48.865422 1, 0xFFFF, sum = 0
8288 12:17:48.868046 2, 0xFFFF, sum = 0
8289 12:17:48.868488 3, 0xFFFF, sum = 0
8290 12:17:48.871079 4, 0xFFFF, sum = 0
8291 12:17:48.874282 5, 0xFFFF, sum = 0
8292 12:17:48.874723 6, 0xFFFF, sum = 0
8293 12:17:48.878155 7, 0xFFFF, sum = 0
8294 12:17:48.878592 8, 0xFFFF, sum = 0
8295 12:17:48.881466 9, 0xFFFF, sum = 0
8296 12:17:48.881927 10, 0xFFFF, sum = 0
8297 12:17:48.884450 11, 0xFFFF, sum = 0
8298 12:17:48.884943 12, 0xFFFF, sum = 0
8299 12:17:48.887652 13, 0xFFFF, sum = 0
8300 12:17:48.888091 14, 0x0, sum = 1
8301 12:17:48.891146 15, 0x0, sum = 2
8302 12:17:48.891588 16, 0x0, sum = 3
8303 12:17:48.894325 17, 0x0, sum = 4
8304 12:17:48.894928 best_step = 15
8305 12:17:48.895410
8306 12:17:48.895744 ==
8307 12:17:48.897679 Dram Type= 6, Freq= 0, CH_0, rank 1
8308 12:17:48.900608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 12:17:48.904279 ==
8310 12:17:48.904898 RX Vref Scan: 0
8311 12:17:48.905392
8312 12:17:48.907398 RX Vref 0 -> 0, step: 1
8313 12:17:48.908015
8314 12:17:48.910514 RX Delay 11 -> 252, step: 4
8315 12:17:48.913883 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8316 12:17:48.917769 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8317 12:17:48.920871 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8318 12:17:48.927594 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8319 12:17:48.930688 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8320 12:17:48.934300 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8321 12:17:48.937374 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8322 12:17:48.940345 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8323 12:17:48.947322 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8324 12:17:48.950565 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8325 12:17:48.953543 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8326 12:17:48.957042 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8327 12:17:48.960863 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8328 12:17:48.967042 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8329 12:17:48.969941 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8330 12:17:48.973735 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8331 12:17:48.974210 ==
8332 12:17:48.976995 Dram Type= 6, Freq= 0, CH_0, rank 1
8333 12:17:48.983161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 12:17:48.983681 ==
8335 12:17:48.984025 DQS Delay:
8336 12:17:48.984386 DQS0 = 0, DQS1 = 0
8337 12:17:48.987236 DQM Delay:
8338 12:17:48.987797 DQM0 = 130, DQM1 = 126
8339 12:17:48.989894 DQ Delay:
8340 12:17:48.992910 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8341 12:17:48.996504 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =140
8342 12:17:48.999504 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8343 12:17:49.003034 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =134
8344 12:17:49.003540
8345 12:17:49.003881
8346 12:17:49.004192
8347 12:17:49.006216 [DramC_TX_OE_Calibration] TA2
8348 12:17:49.009838 Original DQ_B0 (3 6) =30, OEN = 27
8349 12:17:49.013044 Original DQ_B1 (3 6) =30, OEN = 27
8350 12:17:49.016084 24, 0x0, End_B0=24 End_B1=24
8351 12:17:49.016620 25, 0x0, End_B0=25 End_B1=25
8352 12:17:49.019702 26, 0x0, End_B0=26 End_B1=26
8353 12:17:49.023000 27, 0x0, End_B0=27 End_B1=27
8354 12:17:49.026232 28, 0x0, End_B0=28 End_B1=28
8355 12:17:49.029258 29, 0x0, End_B0=29 End_B1=29
8356 12:17:49.029693 30, 0x0, End_B0=30 End_B1=30
8357 12:17:49.032546 31, 0x4545, End_B0=30 End_B1=30
8358 12:17:49.035701 Byte0 end_step=30 best_step=27
8359 12:17:49.039521 Byte1 end_step=30 best_step=27
8360 12:17:49.042436 Byte0 TX OE(2T, 0.5T) = (3, 3)
8361 12:17:49.045572 Byte1 TX OE(2T, 0.5T) = (3, 3)
8362 12:17:49.045662
8363 12:17:49.045734
8364 12:17:49.051951 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d00, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps
8365 12:17:49.055149 CH0 RK1: MR19=303, MR18=1D00
8366 12:17:49.062140 CH0_RK1: MR19=0x303, MR18=0x1D00, DQSOSC=395, MR23=63, INC=23, DEC=15
8367 12:17:49.065286 [RxdqsGatingPostProcess] freq 1600
8368 12:17:49.068493 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8369 12:17:49.071767 best DQS0 dly(2T, 0.5T) = (1, 1)
8370 12:17:49.074919 best DQS1 dly(2T, 0.5T) = (1, 1)
8371 12:17:49.078561 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8372 12:17:49.081786 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8373 12:17:49.084849 best DQS0 dly(2T, 0.5T) = (1, 1)
8374 12:17:49.088619 best DQS1 dly(2T, 0.5T) = (1, 1)
8375 12:17:49.091691 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8376 12:17:49.094895 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8377 12:17:49.098852 Pre-setting of DQS Precalculation
8378 12:17:49.101768 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8379 12:17:49.102182 ==
8380 12:17:49.105265 Dram Type= 6, Freq= 0, CH_1, rank 0
8381 12:17:49.112026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8382 12:17:49.112474 ==
8383 12:17:49.115129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8384 12:17:49.122006 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8385 12:17:49.125102 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8386 12:17:49.131925 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8387 12:17:49.139866 [CA 0] Center 42 (13~72) winsize 60
8388 12:17:49.142603 [CA 1] Center 42 (13~72) winsize 60
8389 12:17:49.146018 [CA 2] Center 38 (9~67) winsize 59
8390 12:17:49.149092 [CA 3] Center 36 (7~66) winsize 60
8391 12:17:49.152129 [CA 4] Center 38 (9~67) winsize 59
8392 12:17:49.155368 [CA 5] Center 37 (8~67) winsize 60
8393 12:17:49.155898
8394 12:17:49.159069 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8395 12:17:49.159483
8396 12:17:49.165282 [CATrainingPosCal] consider 1 rank data
8397 12:17:49.165714 u2DelayCellTimex100 = 258/100 ps
8398 12:17:49.172203 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8399 12:17:49.175259 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8400 12:17:49.178375 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8401 12:17:49.182253 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8402 12:17:49.185182 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8403 12:17:49.188333 CA5 delay=37 (8~67),Diff = 1 PI (3 cell)
8404 12:17:49.188807
8405 12:17:49.192218 CA PerBit enable=1, Macro0, CA PI delay=36
8406 12:17:49.192813
8407 12:17:49.195420 [CBTSetCACLKResult] CA Dly = 36
8408 12:17:49.198445 CS Dly: 9 (0~40)
8409 12:17:49.201995 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8410 12:17:49.205031 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8411 12:17:49.205597 ==
8412 12:17:49.208468 Dram Type= 6, Freq= 0, CH_1, rank 1
8413 12:17:49.214719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 12:17:49.215148 ==
8415 12:17:49.218536 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8416 12:17:49.224731 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8417 12:17:49.227895 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8418 12:17:49.234719 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8419 12:17:49.242310 [CA 0] Center 42 (13~71) winsize 59
8420 12:17:49.245428 [CA 1] Center 43 (13~73) winsize 61
8421 12:17:49.249206 [CA 2] Center 37 (8~67) winsize 60
8422 12:17:49.252311 [CA 3] Center 37 (8~67) winsize 60
8423 12:17:49.255466 [CA 4] Center 38 (9~67) winsize 59
8424 12:17:49.258631 [CA 5] Center 37 (8~67) winsize 60
8425 12:17:49.259079
8426 12:17:49.262319 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8427 12:17:49.262873
8428 12:17:49.265442 [CATrainingPosCal] consider 2 rank data
8429 12:17:49.268657 u2DelayCellTimex100 = 258/100 ps
8430 12:17:49.272285 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8431 12:17:49.278600 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8432 12:17:49.281930 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8433 12:17:49.285368 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8434 12:17:49.288977 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8435 12:17:49.292014 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8436 12:17:49.292614
8437 12:17:49.295769 CA PerBit enable=1, Macro0, CA PI delay=37
8438 12:17:49.296291
8439 12:17:49.298924 [CBTSetCACLKResult] CA Dly = 37
8440 12:17:49.302132 CS Dly: 10 (0~43)
8441 12:17:49.305194 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8442 12:17:49.308408 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8443 12:17:49.308538
8444 12:17:49.311505 ----->DramcWriteLeveling(PI) begin...
8445 12:17:49.311589 ==
8446 12:17:49.314970 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 12:17:49.321442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 12:17:49.321526 ==
8449 12:17:49.324869 Write leveling (Byte 0): 22 => 22
8450 12:17:49.324955 Write leveling (Byte 1): 28 => 28
8451 12:17:49.328003 DramcWriteLeveling(PI) end<-----
8452 12:17:49.328085
8453 12:17:49.331170 ==
8454 12:17:49.331253 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 12:17:49.338293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 12:17:49.338377 ==
8457 12:17:49.341406 [Gating] SW mode calibration
8458 12:17:49.347570 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8459 12:17:49.351303 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8460 12:17:49.357580 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 12:17:49.360839 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 12:17:49.364511 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8463 12:17:49.370888 1 4 12 | B1->B0 | 2b2b 3333 | 1 0 | (1 1) (0 0)
8464 12:17:49.374035 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8465 12:17:49.377839 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8466 12:17:49.384065 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8467 12:17:49.387149 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8468 12:17:49.390933 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8469 12:17:49.397063 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8470 12:17:49.400891 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8471 12:17:49.404006 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (1 0)
8472 12:17:49.410353 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8473 12:17:49.413982 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8474 12:17:49.416880 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 12:17:49.423449 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8476 12:17:49.426711 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8477 12:17:49.430226 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8478 12:17:49.436689 1 6 8 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
8479 12:17:49.439912 1 6 12 | B1->B0 | 3e3d 4545 | 1 0 | (0 0) (0 0)
8480 12:17:49.443687 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8481 12:17:49.449941 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8482 12:17:49.453045 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 12:17:49.456779 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 12:17:49.463034 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8485 12:17:49.466879 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 12:17:49.470100 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 12:17:49.476334 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8488 12:17:49.480166 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8489 12:17:49.483110 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 12:17:49.489979 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 12:17:49.493284 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 12:17:49.496251 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 12:17:49.503035 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 12:17:49.506148 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 12:17:49.509255 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 12:17:49.516059 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 12:17:49.519232 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 12:17:49.522667 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 12:17:49.528961 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 12:17:49.532354 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 12:17:49.535955 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 12:17:49.542390 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 12:17:49.545393 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8504 12:17:49.549181 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8505 12:17:49.552340 Total UI for P1: 0, mck2ui 16
8506 12:17:49.555351 best dqsien dly found for B0: ( 1, 9, 12)
8507 12:17:49.559059 Total UI for P1: 0, mck2ui 16
8508 12:17:49.562274 best dqsien dly found for B1: ( 1, 9, 12)
8509 12:17:49.565420 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8510 12:17:49.568550 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8511 12:17:49.568648
8512 12:17:49.575419 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8513 12:17:49.578687 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8514 12:17:49.581815 [Gating] SW calibration Done
8515 12:17:49.581899 ==
8516 12:17:49.585009 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 12:17:49.588203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 12:17:49.588287 ==
8519 12:17:49.588353 RX Vref Scan: 0
8520 12:17:49.592013
8521 12:17:49.592096 RX Vref 0 -> 0, step: 1
8522 12:17:49.592161
8523 12:17:49.595285 RX Delay 0 -> 252, step: 8
8524 12:17:49.598433 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8525 12:17:49.601862 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8526 12:17:49.608102 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8527 12:17:49.611919 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8528 12:17:49.615025 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8529 12:17:49.618205 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8530 12:17:49.621367 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8531 12:17:49.628152 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8532 12:17:49.631548 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8533 12:17:49.634671 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8534 12:17:49.638081 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8535 12:17:49.641076 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8536 12:17:49.647936 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8537 12:17:49.651382 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8538 12:17:49.654376 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8539 12:17:49.657997 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8540 12:17:49.658081 ==
8541 12:17:49.661241 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 12:17:49.667513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 12:17:49.667597 ==
8544 12:17:49.667663 DQS Delay:
8545 12:17:49.671271 DQS0 = 0, DQS1 = 0
8546 12:17:49.671374 DQM Delay:
8547 12:17:49.674443 DQM0 = 137, DQM1 = 129
8548 12:17:49.674528 DQ Delay:
8549 12:17:49.677601 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8550 12:17:49.680773 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8551 12:17:49.684494 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8552 12:17:49.687685 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8553 12:17:49.687778
8554 12:17:49.687863
8555 12:17:49.687946 ==
8556 12:17:49.690908 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 12:17:49.697520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 12:17:49.697613 ==
8559 12:17:49.697705
8560 12:17:49.697790
8561 12:17:49.697875 TX Vref Scan disable
8562 12:17:49.701437 == TX Byte 0 ==
8563 12:17:49.704621 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8564 12:17:49.710868 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8565 12:17:49.710977 == TX Byte 1 ==
8566 12:17:49.714536 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8567 12:17:49.721372 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8568 12:17:49.721583 ==
8569 12:17:49.724596 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 12:17:49.727928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 12:17:49.728172 ==
8572 12:17:49.740310
8573 12:17:49.743865 TX Vref early break, caculate TX vref
8574 12:17:49.746972 TX Vref=16, minBit 0, minWin=21, winSum=370
8575 12:17:49.750193 TX Vref=18, minBit 5, minWin=22, winSum=375
8576 12:17:49.753838 TX Vref=20, minBit 0, minWin=22, winSum=387
8577 12:17:49.757189 TX Vref=22, minBit 5, minWin=23, winSum=399
8578 12:17:49.760267 TX Vref=24, minBit 5, minWin=23, winSum=406
8579 12:17:49.767383 TX Vref=26, minBit 5, minWin=24, winSum=409
8580 12:17:49.770320 TX Vref=28, minBit 6, minWin=24, winSum=416
8581 12:17:49.774021 TX Vref=30, minBit 0, minWin=23, winSum=410
8582 12:17:49.777222 TX Vref=32, minBit 5, minWin=23, winSum=399
8583 12:17:49.780280 TX Vref=34, minBit 5, minWin=22, winSum=387
8584 12:17:49.787071 [TxChooseVref] Worse bit 6, Min win 24, Win sum 416, Final Vref 28
8585 12:17:49.787636
8586 12:17:49.790509 Final TX Range 0 Vref 28
8587 12:17:49.790956
8588 12:17:49.791398 ==
8589 12:17:49.793474 Dram Type= 6, Freq= 0, CH_1, rank 0
8590 12:17:49.796710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8591 12:17:49.797161 ==
8592 12:17:49.797722
8593 12:17:49.798147
8594 12:17:49.800622 TX Vref Scan disable
8595 12:17:49.806907 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8596 12:17:49.807458 == TX Byte 0 ==
8597 12:17:49.810089 u2DelayCellOfst[0]=18 cells (5 PI)
8598 12:17:49.813506 u2DelayCellOfst[1]=15 cells (4 PI)
8599 12:17:49.816587 u2DelayCellOfst[2]=0 cells (0 PI)
8600 12:17:49.819798 u2DelayCellOfst[3]=7 cells (2 PI)
8601 12:17:49.823508 u2DelayCellOfst[4]=11 cells (3 PI)
8602 12:17:49.826612 u2DelayCellOfst[5]=22 cells (6 PI)
8603 12:17:49.829835 u2DelayCellOfst[6]=22 cells (6 PI)
8604 12:17:49.833060 u2DelayCellOfst[7]=7 cells (2 PI)
8605 12:17:49.836590 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8606 12:17:49.840014 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8607 12:17:49.843160 == TX Byte 1 ==
8608 12:17:49.843627 u2DelayCellOfst[8]=0 cells (0 PI)
8609 12:17:49.846349 u2DelayCellOfst[9]=3 cells (1 PI)
8610 12:17:49.849982 u2DelayCellOfst[10]=11 cells (3 PI)
8611 12:17:49.853147 u2DelayCellOfst[11]=3 cells (1 PI)
8612 12:17:49.856411 u2DelayCellOfst[12]=15 cells (4 PI)
8613 12:17:49.859388 u2DelayCellOfst[13]=18 cells (5 PI)
8614 12:17:49.862889 u2DelayCellOfst[14]=18 cells (5 PI)
8615 12:17:49.866370 u2DelayCellOfst[15]=18 cells (5 PI)
8616 12:17:49.869790 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8617 12:17:49.876355 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8618 12:17:49.876845 DramC Write-DBI on
8619 12:17:49.877192 ==
8620 12:17:49.879862 Dram Type= 6, Freq= 0, CH_1, rank 0
8621 12:17:49.886307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8622 12:17:49.886744 ==
8623 12:17:49.887088
8624 12:17:49.887404
8625 12:17:49.887708 TX Vref Scan disable
8626 12:17:49.889996 == TX Byte 0 ==
8627 12:17:49.893685 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8628 12:17:49.896838 == TX Byte 1 ==
8629 12:17:49.899811 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8630 12:17:49.903532 DramC Write-DBI off
8631 12:17:49.903964
8632 12:17:49.904342 [DATLAT]
8633 12:17:49.904919 Freq=1600, CH1 RK0
8634 12:17:49.905259
8635 12:17:49.906757 DATLAT Default: 0xf
8636 12:17:49.907189 0, 0xFFFF, sum = 0
8637 12:17:49.910017 1, 0xFFFF, sum = 0
8638 12:17:49.913198 2, 0xFFFF, sum = 0
8639 12:17:49.913636 3, 0xFFFF, sum = 0
8640 12:17:49.916318 4, 0xFFFF, sum = 0
8641 12:17:49.916842 5, 0xFFFF, sum = 0
8642 12:17:49.919928 6, 0xFFFF, sum = 0
8643 12:17:49.920460 7, 0xFFFF, sum = 0
8644 12:17:49.923195 8, 0xFFFF, sum = 0
8645 12:17:49.923728 9, 0xFFFF, sum = 0
8646 12:17:49.926271 10, 0xFFFF, sum = 0
8647 12:17:49.926714 11, 0xFFFF, sum = 0
8648 12:17:49.929322 12, 0xFFFF, sum = 0
8649 12:17:49.929784 13, 0xFFFF, sum = 0
8650 12:17:49.933026 14, 0x0, sum = 1
8651 12:17:49.933468 15, 0x0, sum = 2
8652 12:17:49.936173 16, 0x0, sum = 3
8653 12:17:49.936657 17, 0x0, sum = 4
8654 12:17:49.939346 best_step = 15
8655 12:17:49.939780
8656 12:17:49.940119 ==
8657 12:17:49.943070 Dram Type= 6, Freq= 0, CH_1, rank 0
8658 12:17:49.945948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8659 12:17:49.946383 ==
8660 12:17:49.949209 RX Vref Scan: 1
8661 12:17:49.949640
8662 12:17:49.949978 Set Vref Range= 24 -> 127
8663 12:17:49.950299
8664 12:17:49.952415 RX Vref 24 -> 127, step: 1
8665 12:17:49.952890
8666 12:17:49.955900 RX Delay 11 -> 252, step: 4
8667 12:17:49.956329
8668 12:17:49.959467 Set Vref, RX VrefLevel [Byte0]: 24
8669 12:17:49.962481 [Byte1]: 24
8670 12:17:49.962918
8671 12:17:49.966106 Set Vref, RX VrefLevel [Byte0]: 25
8672 12:17:49.969029 [Byte1]: 25
8673 12:17:49.973069
8674 12:17:49.973500 Set Vref, RX VrefLevel [Byte0]: 26
8675 12:17:49.975960 [Byte1]: 26
8676 12:17:49.980620
8677 12:17:49.981051 Set Vref, RX VrefLevel [Byte0]: 27
8678 12:17:49.983714 [Byte1]: 27
8679 12:17:49.987908
8680 12:17:49.988568 Set Vref, RX VrefLevel [Byte0]: 28
8681 12:17:49.991230 [Byte1]: 28
8682 12:17:49.995658
8683 12:17:49.996084 Set Vref, RX VrefLevel [Byte0]: 29
8684 12:17:49.998836 [Byte1]: 29
8685 12:17:50.003398
8686 12:17:50.003822 Set Vref, RX VrefLevel [Byte0]: 30
8687 12:17:50.006444 [Byte1]: 30
8688 12:17:50.011000
8689 12:17:50.011426 Set Vref, RX VrefLevel [Byte0]: 31
8690 12:17:50.014228 [Byte1]: 31
8691 12:17:50.018552
8692 12:17:50.019019 Set Vref, RX VrefLevel [Byte0]: 32
8693 12:17:50.021806 [Byte1]: 32
8694 12:17:50.026159
8695 12:17:50.026591 Set Vref, RX VrefLevel [Byte0]: 33
8696 12:17:50.029378 [Byte1]: 33
8697 12:17:50.033780
8698 12:17:50.034234 Set Vref, RX VrefLevel [Byte0]: 34
8699 12:17:50.036884 [Byte1]: 34
8700 12:17:50.041208
8701 12:17:50.041629 Set Vref, RX VrefLevel [Byte0]: 35
8702 12:17:50.044268 [Byte1]: 35
8703 12:17:50.048975
8704 12:17:50.049433 Set Vref, RX VrefLevel [Byte0]: 36
8705 12:17:50.052071 [Byte1]: 36
8706 12:17:50.056480
8707 12:17:50.056944 Set Vref, RX VrefLevel [Byte0]: 37
8708 12:17:50.059632 [Byte1]: 37
8709 12:17:50.063860
8710 12:17:50.064284 Set Vref, RX VrefLevel [Byte0]: 38
8711 12:17:50.067743 [Byte1]: 38
8712 12:17:50.071874
8713 12:17:50.072308 Set Vref, RX VrefLevel [Byte0]: 39
8714 12:17:50.074775 [Byte1]: 39
8715 12:17:50.079047
8716 12:17:50.079494 Set Vref, RX VrefLevel [Byte0]: 40
8717 12:17:50.082644 [Byte1]: 40
8718 12:17:50.086789
8719 12:17:50.087227 Set Vref, RX VrefLevel [Byte0]: 41
8720 12:17:50.090528 [Byte1]: 41
8721 12:17:50.095190
8722 12:17:50.095734 Set Vref, RX VrefLevel [Byte0]: 42
8723 12:17:50.098358 [Byte1]: 42
8724 12:17:50.102777
8725 12:17:50.103328 Set Vref, RX VrefLevel [Byte0]: 43
8726 12:17:50.105496 [Byte1]: 43
8727 12:17:50.109806
8728 12:17:50.110259 Set Vref, RX VrefLevel [Byte0]: 44
8729 12:17:50.112976 [Byte1]: 44
8730 12:17:50.117450
8731 12:17:50.117896 Set Vref, RX VrefLevel [Byte0]: 45
8732 12:17:50.120440 [Byte1]: 45
8733 12:17:50.124951
8734 12:17:50.125399 Set Vref, RX VrefLevel [Byte0]: 46
8735 12:17:50.128576 [Byte1]: 46
8736 12:17:50.132975
8737 12:17:50.133422 Set Vref, RX VrefLevel [Byte0]: 47
8738 12:17:50.139276 [Byte1]: 47
8739 12:17:50.139729
8740 12:17:50.142383 Set Vref, RX VrefLevel [Byte0]: 48
8741 12:17:50.145505 [Byte1]: 48
8742 12:17:50.145959
8743 12:17:50.148873 Set Vref, RX VrefLevel [Byte0]: 49
8744 12:17:50.152549 [Byte1]: 49
8745 12:17:50.155447
8746 12:17:50.155887 Set Vref, RX VrefLevel [Byte0]: 50
8747 12:17:50.159106 [Byte1]: 50
8748 12:17:50.162928
8749 12:17:50.163388 Set Vref, RX VrefLevel [Byte0]: 51
8750 12:17:50.166925 [Byte1]: 51
8751 12:17:50.170888
8752 12:17:50.171462 Set Vref, RX VrefLevel [Byte0]: 52
8753 12:17:50.173662 [Byte1]: 52
8754 12:17:50.178471
8755 12:17:50.178908 Set Vref, RX VrefLevel [Byte0]: 53
8756 12:17:50.181471 [Byte1]: 53
8757 12:17:50.186099
8758 12:17:50.186537 Set Vref, RX VrefLevel [Byte0]: 54
8759 12:17:50.188900 [Byte1]: 54
8760 12:17:50.193252
8761 12:17:50.193689 Set Vref, RX VrefLevel [Byte0]: 55
8762 12:17:50.196899 [Byte1]: 55
8763 12:17:50.201230
8764 12:17:50.201675 Set Vref, RX VrefLevel [Byte0]: 56
8765 12:17:50.204377 [Byte1]: 56
8766 12:17:50.209162
8767 12:17:50.209728 Set Vref, RX VrefLevel [Byte0]: 57
8768 12:17:50.211965 [Byte1]: 57
8769 12:17:50.216371
8770 12:17:50.216827 Set Vref, RX VrefLevel [Byte0]: 58
8771 12:17:50.219472 [Byte1]: 58
8772 12:17:50.223794
8773 12:17:50.224223 Set Vref, RX VrefLevel [Byte0]: 59
8774 12:17:50.226966 [Byte1]: 59
8775 12:17:50.231290
8776 12:17:50.231723 Set Vref, RX VrefLevel [Byte0]: 60
8777 12:17:50.235027 [Byte1]: 60
8778 12:17:50.239962
8779 12:17:50.240480 Set Vref, RX VrefLevel [Byte0]: 61
8780 12:17:50.242737 [Byte1]: 61
8781 12:17:50.247174
8782 12:17:50.247600 Set Vref, RX VrefLevel [Byte0]: 62
8783 12:17:50.250517 [Byte1]: 62
8784 12:17:50.254801
8785 12:17:50.255503 Set Vref, RX VrefLevel [Byte0]: 63
8786 12:17:50.257800 [Byte1]: 63
8787 12:17:50.261890
8788 12:17:50.262319 Set Vref, RX VrefLevel [Byte0]: 64
8789 12:17:50.265734 [Byte1]: 64
8790 12:17:50.269457
8791 12:17:50.269885 Set Vref, RX VrefLevel [Byte0]: 65
8792 12:17:50.273280 [Byte1]: 65
8793 12:17:50.277097
8794 12:17:50.277523 Set Vref, RX VrefLevel [Byte0]: 66
8795 12:17:50.280831 [Byte1]: 66
8796 12:17:50.285245
8797 12:17:50.285675 Set Vref, RX VrefLevel [Byte0]: 67
8798 12:17:50.288260 [Byte1]: 67
8799 12:17:50.292328
8800 12:17:50.292803 Set Vref, RX VrefLevel [Byte0]: 68
8801 12:17:50.296108 [Byte1]: 68
8802 12:17:50.300229
8803 12:17:50.300697 Set Vref, RX VrefLevel [Byte0]: 69
8804 12:17:50.303279 [Byte1]: 69
8805 12:17:50.307482
8806 12:17:50.307976 Set Vref, RX VrefLevel [Byte0]: 70
8807 12:17:50.310798 [Byte1]: 70
8808 12:17:50.315101
8809 12:17:50.315583 Set Vref, RX VrefLevel [Byte0]: 71
8810 12:17:50.318262 [Byte1]: 71
8811 12:17:50.322768
8812 12:17:50.323330 Set Vref, RX VrefLevel [Byte0]: 72
8813 12:17:50.326484 [Byte1]: 72
8814 12:17:50.330225
8815 12:17:50.330674 Set Vref, RX VrefLevel [Byte0]: 73
8816 12:17:50.336612 [Byte1]: 73
8817 12:17:50.337166
8818 12:17:50.340210 Final RX Vref Byte 0 = 55 to rank0
8819 12:17:50.343424 Final RX Vref Byte 1 = 58 to rank0
8820 12:17:50.346561 Final RX Vref Byte 0 = 55 to rank1
8821 12:17:50.350534 Final RX Vref Byte 1 = 58 to rank1==
8822 12:17:50.353563 Dram Type= 6, Freq= 0, CH_1, rank 0
8823 12:17:50.356845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 12:17:50.357382 ==
8825 12:17:50.357729 DQS Delay:
8826 12:17:50.360438 DQS0 = 0, DQS1 = 0
8827 12:17:50.360902 DQM Delay:
8828 12:17:50.363579 DQM0 = 133, DQM1 = 127
8829 12:17:50.364004 DQ Delay:
8830 12:17:50.366437 DQ0 =140, DQ1 =126, DQ2 =122, DQ3 =130
8831 12:17:50.370081 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8832 12:17:50.373034 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8833 12:17:50.376846 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8834 12:17:50.377274
8835 12:17:50.379692
8836 12:17:50.380116
8837 12:17:50.380450 [DramC_TX_OE_Calibration] TA2
8838 12:17:50.382902 Original DQ_B0 (3 6) =30, OEN = 27
8839 12:17:50.386636 Original DQ_B1 (3 6) =30, OEN = 27
8840 12:17:50.389922 24, 0x0, End_B0=24 End_B1=24
8841 12:17:50.392803 25, 0x0, End_B0=25 End_B1=25
8842 12:17:50.396855 26, 0x0, End_B0=26 End_B1=26
8843 12:17:50.397398 27, 0x0, End_B0=27 End_B1=27
8844 12:17:50.400189 28, 0x0, End_B0=28 End_B1=28
8845 12:17:50.402999 29, 0x0, End_B0=29 End_B1=29
8846 12:17:50.405959 30, 0x0, End_B0=30 End_B1=30
8847 12:17:50.409418 31, 0x4545, End_B0=30 End_B1=30
8848 12:17:50.412503 Byte0 end_step=30 best_step=27
8849 12:17:50.412983 Byte1 end_step=30 best_step=27
8850 12:17:50.415761 Byte0 TX OE(2T, 0.5T) = (3, 3)
8851 12:17:50.419491 Byte1 TX OE(2T, 0.5T) = (3, 3)
8852 12:17:50.419922
8853 12:17:50.420265
8854 12:17:50.429454 [DQSOSCAuto] RK0, (LSB)MR18= 0x170c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8855 12:17:50.429986 CH1 RK0: MR19=303, MR18=170C
8856 12:17:50.435619 CH1_RK0: MR19=0x303, MR18=0x170C, DQSOSC=398, MR23=63, INC=23, DEC=15
8857 12:17:50.436150
8858 12:17:50.438623 ----->DramcWriteLeveling(PI) begin...
8859 12:17:50.442066 ==
8860 12:17:50.442508 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 12:17:50.449071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 12:17:50.449501 ==
8863 12:17:50.452164 Write leveling (Byte 0): 24 => 24
8864 12:17:50.455437 Write leveling (Byte 1): 27 => 27
8865 12:17:50.459221 DramcWriteLeveling(PI) end<-----
8866 12:17:50.459886
8867 12:17:50.460254 ==
8868 12:17:50.462274 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 12:17:50.465515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 12:17:50.465953 ==
8871 12:17:50.468573 [Gating] SW mode calibration
8872 12:17:50.475350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8873 12:17:50.482272 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8874 12:17:50.485313 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8875 12:17:50.488596 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8876 12:17:50.494960 1 4 8 | B1->B0 | 2525 2323 | 1 0 | (1 1) (0 0)
8877 12:17:50.498524 1 4 12 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
8878 12:17:50.501612 1 4 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8879 12:17:50.508295 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8880 12:17:50.511917 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8881 12:17:50.514939 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8882 12:17:50.521604 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8883 12:17:50.524780 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8884 12:17:50.527776 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8885 12:17:50.534756 1 5 12 | B1->B0 | 2c2c 3434 | 0 1 | (1 0) (1 0)
8886 12:17:50.537916 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8887 12:17:50.541017 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8888 12:17:50.547853 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8889 12:17:50.550975 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8890 12:17:50.554635 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8891 12:17:50.561214 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8892 12:17:50.564289 1 6 8 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
8893 12:17:50.567758 1 6 12 | B1->B0 | 4545 2525 | 0 0 | (0 0) (0 0)
8894 12:17:50.574477 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8895 12:17:50.577532 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8896 12:17:50.581077 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 12:17:50.587283 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8898 12:17:50.591205 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8899 12:17:50.594303 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8900 12:17:50.600593 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8901 12:17:50.604159 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8902 12:17:50.607290 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8903 12:17:50.613685 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 12:17:50.616758 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 12:17:50.620326 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 12:17:50.627432 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 12:17:50.630598 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 12:17:50.633593 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 12:17:50.636733 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 12:17:50.643628 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 12:17:50.646795 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 12:17:50.649914 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 12:17:50.656746 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8914 12:17:50.659901 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 12:17:50.663100 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8916 12:17:50.670068 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8917 12:17:50.673036 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8918 12:17:50.676341 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8919 12:17:50.680057 Total UI for P1: 0, mck2ui 16
8920 12:17:50.683008 best dqsien dly found for B0: ( 1, 9, 12)
8921 12:17:50.685992 Total UI for P1: 0, mck2ui 16
8922 12:17:50.689454 best dqsien dly found for B1: ( 1, 9, 10)
8923 12:17:50.696218 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8924 12:17:50.699524 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8925 12:17:50.699952
8926 12:17:50.702347 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8927 12:17:50.705787 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8928 12:17:50.708924 [Gating] SW calibration Done
8929 12:17:50.709353 ==
8930 12:17:50.712389 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 12:17:50.715393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 12:17:50.715823 ==
8933 12:17:50.718994 RX Vref Scan: 0
8934 12:17:50.719421
8935 12:17:50.719761 RX Vref 0 -> 0, step: 1
8936 12:17:50.720077
8937 12:17:50.722334 RX Delay 0 -> 252, step: 8
8938 12:17:50.725350 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8939 12:17:50.732179 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8940 12:17:50.735192 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8941 12:17:50.739076 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8942 12:17:50.742536 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8943 12:17:50.745607 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8944 12:17:50.752040 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8945 12:17:50.755661 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8946 12:17:50.758706 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8947 12:17:50.761974 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8948 12:17:50.765806 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8949 12:17:50.772424 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8950 12:17:50.775118 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8951 12:17:50.778163 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8952 12:17:50.781862 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8953 12:17:50.788196 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8954 12:17:50.788653 ==
8955 12:17:50.791803 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 12:17:50.794864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 12:17:50.795291 ==
8958 12:17:50.795625 DQS Delay:
8959 12:17:50.798777 DQS0 = 0, DQS1 = 0
8960 12:17:50.799311 DQM Delay:
8961 12:17:50.801934 DQM0 = 137, DQM1 = 129
8962 12:17:50.802464 DQ Delay:
8963 12:17:50.804881 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8964 12:17:50.808152 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8965 12:17:50.811245 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8966 12:17:50.814948 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8967 12:17:50.815374
8968 12:17:50.817912
8969 12:17:50.818335 ==
8970 12:17:50.821376 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 12:17:50.824863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 12:17:50.825436 ==
8973 12:17:50.825855
8974 12:17:50.826224
8975 12:17:50.827856 TX Vref Scan disable
8976 12:17:50.828280 == TX Byte 0 ==
8977 12:17:50.834465 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8978 12:17:50.837617 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8979 12:17:50.838045 == TX Byte 1 ==
8980 12:17:50.844614 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8981 12:17:50.847853 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8982 12:17:50.848279 ==
8983 12:17:50.850939 Dram Type= 6, Freq= 0, CH_1, rank 1
8984 12:17:50.853901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8985 12:17:50.854328 ==
8986 12:17:50.867473
8987 12:17:50.871176 TX Vref early break, caculate TX vref
8988 12:17:50.874311 TX Vref=16, minBit 0, minWin=22, winSum=381
8989 12:17:50.877324 TX Vref=18, minBit 0, minWin=23, winSum=395
8990 12:17:50.881103 TX Vref=20, minBit 0, minWin=24, winSum=402
8991 12:17:50.884258 TX Vref=22, minBit 8, minWin=24, winSum=409
8992 12:17:50.887409 TX Vref=24, minBit 3, minWin=25, winSum=417
8993 12:17:50.894429 TX Vref=26, minBit 3, minWin=25, winSum=424
8994 12:17:50.897289 TX Vref=28, minBit 0, minWin=24, winSum=425
8995 12:17:50.901110 TX Vref=30, minBit 0, minWin=24, winSum=416
8996 12:17:50.904357 TX Vref=32, minBit 0, minWin=24, winSum=406
8997 12:17:50.907400 TX Vref=34, minBit 5, minWin=23, winSum=399
8998 12:17:50.914331 [TxChooseVref] Worse bit 3, Min win 25, Win sum 424, Final Vref 26
8999 12:17:50.914761
9000 12:17:50.917516 Final TX Range 0 Vref 26
9001 12:17:50.917943
9002 12:17:50.918275 ==
9003 12:17:50.920565 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 12:17:50.923524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 12:17:50.923960 ==
9006 12:17:50.924292
9007 12:17:50.924647
9008 12:17:50.927260 TX Vref Scan disable
9009 12:17:50.933702 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
9010 12:17:50.934163 == TX Byte 0 ==
9011 12:17:50.937229 u2DelayCellOfst[0]=22 cells (6 PI)
9012 12:17:50.940129 u2DelayCellOfst[1]=15 cells (4 PI)
9013 12:17:50.943608 u2DelayCellOfst[2]=0 cells (0 PI)
9014 12:17:50.946776 u2DelayCellOfst[3]=7 cells (2 PI)
9015 12:17:50.950521 u2DelayCellOfst[4]=7 cells (2 PI)
9016 12:17:50.953910 u2DelayCellOfst[5]=18 cells (5 PI)
9017 12:17:50.956814 u2DelayCellOfst[6]=18 cells (5 PI)
9018 12:17:50.960035 u2DelayCellOfst[7]=3 cells (1 PI)
9019 12:17:50.963842 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9020 12:17:50.967090 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9021 12:17:50.969942 == TX Byte 1 ==
9022 12:17:50.972978 u2DelayCellOfst[8]=0 cells (0 PI)
9023 12:17:50.976758 u2DelayCellOfst[9]=7 cells (2 PI)
9024 12:17:50.979783 u2DelayCellOfst[10]=15 cells (4 PI)
9025 12:17:50.980259 u2DelayCellOfst[11]=7 cells (2 PI)
9026 12:17:50.983009 u2DelayCellOfst[12]=18 cells (5 PI)
9027 12:17:50.986102 u2DelayCellOfst[13]=18 cells (5 PI)
9028 12:17:50.989307 u2DelayCellOfst[14]=18 cells (5 PI)
9029 12:17:50.992620 u2DelayCellOfst[15]=18 cells (5 PI)
9030 12:17:50.999593 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9031 12:17:51.003383 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9032 12:17:51.003813 DramC Write-DBI on
9033 12:17:51.004151 ==
9034 12:17:51.006153 Dram Type= 6, Freq= 0, CH_1, rank 1
9035 12:17:51.012624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9036 12:17:51.013055 ==
9037 12:17:51.013394
9038 12:17:51.013818
9039 12:17:51.016143 TX Vref Scan disable
9040 12:17:51.016596 == TX Byte 0 ==
9041 12:17:51.022604 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9042 12:17:51.023213 == TX Byte 1 ==
9043 12:17:51.025619 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9044 12:17:51.029432 DramC Write-DBI off
9045 12:17:51.029950
9046 12:17:51.030399 [DATLAT]
9047 12:17:51.032381 Freq=1600, CH1 RK1
9048 12:17:51.032849
9049 12:17:51.033192 DATLAT Default: 0xf
9050 12:17:51.036231 0, 0xFFFF, sum = 0
9051 12:17:51.036698 1, 0xFFFF, sum = 0
9052 12:17:51.039376 2, 0xFFFF, sum = 0
9053 12:17:51.039912 3, 0xFFFF, sum = 0
9054 12:17:51.042830 4, 0xFFFF, sum = 0
9055 12:17:51.043264 5, 0xFFFF, sum = 0
9056 12:17:51.045878 6, 0xFFFF, sum = 0
9057 12:17:51.046309 7, 0xFFFF, sum = 0
9058 12:17:51.048895 8, 0xFFFF, sum = 0
9059 12:17:51.049364 9, 0xFFFF, sum = 0
9060 12:17:51.052501 10, 0xFFFF, sum = 0
9061 12:17:51.055698 11, 0xFFFF, sum = 0
9062 12:17:51.056297 12, 0xFFFF, sum = 0
9063 12:17:51.058715 13, 0xFFFF, sum = 0
9064 12:17:51.058993 14, 0x0, sum = 1
9065 12:17:51.062320 15, 0x0, sum = 2
9066 12:17:51.062432 16, 0x0, sum = 3
9067 12:17:51.065387 17, 0x0, sum = 4
9068 12:17:51.065473 best_step = 15
9069 12:17:51.065539
9070 12:17:51.065598 ==
9071 12:17:51.068746 Dram Type= 6, Freq= 0, CH_1, rank 1
9072 12:17:51.071557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9073 12:17:51.071641 ==
9074 12:17:51.074730 RX Vref Scan: 0
9075 12:17:51.074814
9076 12:17:51.078421 RX Vref 0 -> 0, step: 1
9077 12:17:51.078504
9078 12:17:51.078570 RX Delay 11 -> 252, step: 4
9079 12:17:51.085326 iDelay=203, Bit 0, Center 138 (83 ~ 194) 112
9080 12:17:51.089088 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9081 12:17:51.092171 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9082 12:17:51.095432 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9083 12:17:51.102174 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9084 12:17:51.105191 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9085 12:17:51.108790 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9086 12:17:51.111840 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9087 12:17:51.115641 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9088 12:17:51.118826 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9089 12:17:51.124992 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9090 12:17:51.128171 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9091 12:17:51.132065 iDelay=203, Bit 12, Center 138 (83 ~ 194) 112
9092 12:17:51.135262 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9093 12:17:51.141335 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9094 12:17:51.145046 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9095 12:17:51.145192 ==
9096 12:17:51.147932 Dram Type= 6, Freq= 0, CH_1, rank 1
9097 12:17:51.151683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9098 12:17:51.151823 ==
9099 12:17:51.154759 DQS Delay:
9100 12:17:51.154935 DQS0 = 0, DQS1 = 0
9101 12:17:51.155093 DQM Delay:
9102 12:17:51.157980 DQM0 = 134, DQM1 = 127
9103 12:17:51.158165 DQ Delay:
9104 12:17:51.161742 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9105 12:17:51.165034 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9106 12:17:51.171278 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =118
9107 12:17:51.175096 DQ12 =138, DQ13 =136, DQ14 =134, DQ15 =138
9108 12:17:51.175365
9109 12:17:51.175636
9110 12:17:51.175826
9111 12:17:51.178215 [DramC_TX_OE_Calibration] TA2
9112 12:17:51.181311 Original DQ_B0 (3 6) =30, OEN = 27
9113 12:17:51.184777 Original DQ_B1 (3 6) =30, OEN = 27
9114 12:17:51.185559 24, 0x0, End_B0=24 End_B1=24
9115 12:17:51.188164 25, 0x0, End_B0=25 End_B1=25
9116 12:17:51.191231 26, 0x0, End_B0=26 End_B1=26
9117 12:17:51.194486 27, 0x0, End_B0=27 End_B1=27
9118 12:17:51.195763 28, 0x0, End_B0=28 End_B1=28
9119 12:17:51.197607 29, 0x0, End_B0=29 End_B1=29
9120 12:17:51.201216 30, 0x0, End_B0=30 End_B1=30
9121 12:17:51.204450 31, 0x4545, End_B0=30 End_B1=30
9122 12:17:51.207794 Byte0 end_step=30 best_step=27
9123 12:17:51.211430 Byte1 end_step=30 best_step=27
9124 12:17:51.212155 Byte0 TX OE(2T, 0.5T) = (3, 3)
9125 12:17:51.214183 Byte1 TX OE(2T, 0.5T) = (3, 3)
9126 12:17:51.214668
9127 12:17:51.215045
9128 12:17:51.223914 [DQSOSCAuto] RK1, (LSB)MR18= 0xa07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9129 12:17:51.227719 CH1 RK1: MR19=303, MR18=A07
9130 12:17:51.230975 CH1_RK1: MR19=0x303, MR18=0xA07, DQSOSC=404, MR23=63, INC=22, DEC=15
9131 12:17:51.234008 [RxdqsGatingPostProcess] freq 1600
9132 12:17:51.240506 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9133 12:17:51.243623 best DQS0 dly(2T, 0.5T) = (1, 1)
9134 12:17:51.247310 best DQS1 dly(2T, 0.5T) = (1, 1)
9135 12:17:51.250298 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9136 12:17:51.253865 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9137 12:17:51.257269 best DQS0 dly(2T, 0.5T) = (1, 1)
9138 12:17:51.260446 best DQS1 dly(2T, 0.5T) = (1, 1)
9139 12:17:51.263626 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9140 12:17:51.264168 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9141 12:17:51.267480 Pre-setting of DQS Precalculation
9142 12:17:51.273829 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9143 12:17:51.280608 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9144 12:17:51.287208 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9145 12:17:51.287786
9146 12:17:51.288466
9147 12:17:51.290214 [Calibration Summary] 3200 Mbps
9148 12:17:51.293843 CH 0, Rank 0
9149 12:17:51.294325 SW Impedance : PASS
9150 12:17:51.297033 DUTY Scan : NO K
9151 12:17:51.300137 ZQ Calibration : PASS
9152 12:17:51.300682 Jitter Meter : NO K
9153 12:17:51.303822 CBT Training : PASS
9154 12:17:51.307064 Write leveling : PASS
9155 12:17:51.307657 RX DQS gating : PASS
9156 12:17:51.310144 RX DQ/DQS(RDDQC) : PASS
9157 12:17:51.310763 TX DQ/DQS : PASS
9158 12:17:51.313197 RX DATLAT : PASS
9159 12:17:51.316815 RX DQ/DQS(Engine): PASS
9160 12:17:51.317341 TX OE : PASS
9161 12:17:51.319868 All Pass.
9162 12:17:51.320488
9163 12:17:51.320946 CH 0, Rank 1
9164 12:17:51.323381 SW Impedance : PASS
9165 12:17:51.323868 DUTY Scan : NO K
9166 12:17:51.326556 ZQ Calibration : PASS
9167 12:17:51.329694 Jitter Meter : NO K
9168 12:17:51.330291 CBT Training : PASS
9169 12:17:51.333303 Write leveling : PASS
9170 12:17:51.336570 RX DQS gating : PASS
9171 12:17:51.337034 RX DQ/DQS(RDDQC) : PASS
9172 12:17:51.339621 TX DQ/DQS : PASS
9173 12:17:51.342898 RX DATLAT : PASS
9174 12:17:51.343501 RX DQ/DQS(Engine): PASS
9175 12:17:51.346629 TX OE : PASS
9176 12:17:51.347221 All Pass.
9177 12:17:51.347731
9178 12:17:51.349637 CH 1, Rank 0
9179 12:17:51.350306 SW Impedance : PASS
9180 12:17:51.352786 DUTY Scan : NO K
9181 12:17:51.356398 ZQ Calibration : PASS
9182 12:17:51.356982 Jitter Meter : NO K
9183 12:17:51.359929 CBT Training : PASS
9184 12:17:51.362894 Write leveling : PASS
9185 12:17:51.363474 RX DQS gating : PASS
9186 12:17:51.366233 RX DQ/DQS(RDDQC) : PASS
9187 12:17:51.369278 TX DQ/DQS : PASS
9188 12:17:51.369942 RX DATLAT : PASS
9189 12:17:51.372876 RX DQ/DQS(Engine): PASS
9190 12:17:51.376061 TX OE : PASS
9191 12:17:51.376593 All Pass.
9192 12:17:51.376930
9193 12:17:51.377236 CH 1, Rank 1
9194 12:17:51.379355 SW Impedance : PASS
9195 12:17:51.383133 DUTY Scan : NO K
9196 12:17:51.383754 ZQ Calibration : PASS
9197 12:17:51.386216 Jitter Meter : NO K
9198 12:17:51.386794 CBT Training : PASS
9199 12:17:51.389413 Write leveling : PASS
9200 12:17:51.392414 RX DQS gating : PASS
9201 12:17:51.393024 RX DQ/DQS(RDDQC) : PASS
9202 12:17:51.396363 TX DQ/DQS : PASS
9203 12:17:51.399504 RX DATLAT : PASS
9204 12:17:51.399935 RX DQ/DQS(Engine): PASS
9205 12:17:51.402642 TX OE : PASS
9206 12:17:51.403074 All Pass.
9207 12:17:51.403417
9208 12:17:51.405769 DramC Write-DBI on
9209 12:17:51.409463 PER_BANK_REFRESH: Hybrid Mode
9210 12:17:51.409921 TX_TRACKING: ON
9211 12:17:51.419076 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9212 12:17:51.425814 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9213 12:17:51.435556 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9214 12:17:51.438747 [FAST_K] Save calibration result to emmc
9215 12:17:51.439192 sync common calibartion params.
9216 12:17:51.442512 sync cbt_mode0:1, 1:1
9217 12:17:51.445614 dram_init: ddr_geometry: 2
9218 12:17:51.448649 dram_init: ddr_geometry: 2
9219 12:17:51.449333 dram_init: ddr_geometry: 2
9220 12:17:51.451699 0:dram_rank_size:100000000
9221 12:17:51.454887 1:dram_rank_size:100000000
9222 12:17:51.458348 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9223 12:17:51.461335 DFS_SHUFFLE_HW_MODE: ON
9224 12:17:51.465179 dramc_set_vcore_voltage set vcore to 725000
9225 12:17:51.468259 Read voltage for 1600, 0
9226 12:17:51.468731 Vio18 = 0
9227 12:17:51.471435 Vcore = 725000
9228 12:17:51.472104 Vdram = 0
9229 12:17:51.472702 Vddq = 0
9230 12:17:51.475041 Vmddr = 0
9231 12:17:51.475558 switch to 3200 Mbps bootup
9232 12:17:51.478270 [DramcRunTimeConfig]
9233 12:17:51.478741 PHYPLL
9234 12:17:51.481437 DPM_CONTROL_AFTERK: ON
9235 12:17:51.481870 PER_BANK_REFRESH: ON
9236 12:17:51.485101 REFRESH_OVERHEAD_REDUCTION: ON
9237 12:17:51.488303 CMD_PICG_NEW_MODE: OFF
9238 12:17:51.488784 XRTWTW_NEW_MODE: ON
9239 12:17:51.491380 XRTRTR_NEW_MODE: ON
9240 12:17:51.491809 TX_TRACKING: ON
9241 12:17:51.494981 RDSEL_TRACKING: OFF
9242 12:17:51.497901 DQS Precalculation for DVFS: ON
9243 12:17:51.498437 RX_TRACKING: OFF
9244 12:17:51.501668 HW_GATING DBG: ON
9245 12:17:51.502095 ZQCS_ENABLE_LP4: ON
9246 12:17:51.504860 RX_PICG_NEW_MODE: ON
9247 12:17:51.505440 TX_PICG_NEW_MODE: ON
9248 12:17:51.508027 ENABLE_RX_DCM_DPHY: ON
9249 12:17:51.511111 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9250 12:17:51.514281 DUMMY_READ_FOR_TRACKING: OFF
9251 12:17:51.514708 !!! SPM_CONTROL_AFTERK: OFF
9252 12:17:51.518032 !!! SPM could not control APHY
9253 12:17:51.521058 IMPEDANCE_TRACKING: ON
9254 12:17:51.521504 TEMP_SENSOR: ON
9255 12:17:51.524695 HW_SAVE_FOR_SR: OFF
9256 12:17:51.528044 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9257 12:17:51.531258 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9258 12:17:51.531734 Read ODT Tracking: ON
9259 12:17:51.534566 Refresh Rate DeBounce: ON
9260 12:17:51.537674 DFS_NO_QUEUE_FLUSH: ON
9261 12:17:51.541354 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9262 12:17:51.544318 ENABLE_DFS_RUNTIME_MRW: OFF
9263 12:17:51.544915 DDR_RESERVE_NEW_MODE: ON
9264 12:17:51.547422 MR_CBT_SWITCH_FREQ: ON
9265 12:17:51.550562 =========================
9266 12:17:51.568437 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9267 12:17:51.571412 dram_init: ddr_geometry: 2
9268 12:17:51.589762 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9269 12:17:51.593281 dram_init: dram init end (result: 0)
9270 12:17:51.599947 DRAM-K: Full calibration passed in 24650 msecs
9271 12:17:51.602874 MRC: failed to locate region type 0.
9272 12:17:51.603446 DRAM rank0 size:0x100000000,
9273 12:17:51.606335 DRAM rank1 size=0x100000000
9274 12:17:51.616336 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9275 12:17:51.622650 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9276 12:17:51.629492 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9277 12:17:51.639430 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9278 12:17:51.639874 DRAM rank0 size:0x100000000,
9279 12:17:51.642394 DRAM rank1 size=0x100000000
9280 12:17:51.642836 CBMEM:
9281 12:17:51.645520 IMD: root @ 0xfffff000 254 entries.
9282 12:17:51.649338 IMD: root @ 0xffffec00 62 entries.
9283 12:17:51.652708 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9284 12:17:51.658923 WARNING: RO_VPD is uninitialized or empty.
9285 12:17:51.661992 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9286 12:17:51.670142 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9287 12:17:51.682567 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9288 12:17:51.693981 BS: romstage times (exec / console): total (unknown) / 24139 ms
9289 12:17:51.694508
9290 12:17:51.694846
9291 12:17:51.703771 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9292 12:17:51.707342 ARM64: Exception handlers installed.
9293 12:17:51.710476 ARM64: Testing exception
9294 12:17:51.713649 ARM64: Done test exception
9295 12:17:51.714077 Enumerating buses...
9296 12:17:51.717495 Show all devs... Before device enumeration.
9297 12:17:51.720462 Root Device: enabled 1
9298 12:17:51.723640 CPU_CLUSTER: 0: enabled 1
9299 12:17:51.724061 CPU: 00: enabled 1
9300 12:17:51.727364 Compare with tree...
9301 12:17:51.727785 Root Device: enabled 1
9302 12:17:51.730522 CPU_CLUSTER: 0: enabled 1
9303 12:17:51.733681 CPU: 00: enabled 1
9304 12:17:51.734124 Root Device scanning...
9305 12:17:51.736927 scan_static_bus for Root Device
9306 12:17:51.740793 CPU_CLUSTER: 0 enabled
9307 12:17:51.743701 scan_static_bus for Root Device done
9308 12:17:51.746607 scan_bus: bus Root Device finished in 8 msecs
9309 12:17:51.747031 done
9310 12:17:51.753373 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9311 12:17:51.756613 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9312 12:17:51.763417 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9313 12:17:51.766622 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9314 12:17:51.769861 Allocating resources...
9315 12:17:51.773380 Reading resources...
9316 12:17:51.776429 Root Device read_resources bus 0 link: 0
9317 12:17:51.780190 DRAM rank0 size:0x100000000,
9318 12:17:51.780654 DRAM rank1 size=0x100000000
9319 12:17:51.783172 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9320 12:17:51.786163 CPU: 00 missing read_resources
9321 12:17:51.793176 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9322 12:17:51.796413 Root Device read_resources bus 0 link: 0 done
9323 12:17:51.799487 Done reading resources.
9324 12:17:51.802671 Show resources in subtree (Root Device)...After reading.
9325 12:17:51.806512 Root Device child on link 0 CPU_CLUSTER: 0
9326 12:17:51.809391 CPU_CLUSTER: 0 child on link 0 CPU: 00
9327 12:17:51.819743 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9328 12:17:51.820310 CPU: 00
9329 12:17:51.823017 Root Device assign_resources, bus 0 link: 0
9330 12:17:51.826240 CPU_CLUSTER: 0 missing set_resources
9331 12:17:51.832393 Root Device assign_resources, bus 0 link: 0 done
9332 12:17:51.832974 Done setting resources.
9333 12:17:51.839045 Show resources in subtree (Root Device)...After assigning values.
9334 12:17:51.842388 Root Device child on link 0 CPU_CLUSTER: 0
9335 12:17:51.845963 CPU_CLUSTER: 0 child on link 0 CPU: 00
9336 12:17:51.855593 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9337 12:17:51.856033 CPU: 00
9338 12:17:51.859271 Done allocating resources.
9339 12:17:51.865576 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9340 12:17:51.866007 Enabling resources...
9341 12:17:51.866353 done.
9342 12:17:51.871805 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9343 12:17:51.875170 Initializing devices...
9344 12:17:51.875629 Root Device init
9345 12:17:51.878935 init hardware done!
9346 12:17:51.879438 0x00000018: ctrlr->caps
9347 12:17:51.881895 52.000 MHz: ctrlr->f_max
9348 12:17:51.885485 0.400 MHz: ctrlr->f_min
9349 12:17:51.886111 0x40ff8080: ctrlr->voltages
9350 12:17:51.888347 sclk: 390625
9351 12:17:51.888902 Bus Width = 1
9352 12:17:51.892021 sclk: 390625
9353 12:17:51.892548 Bus Width = 1
9354 12:17:51.895264 Early init status = 3
9355 12:17:51.898396 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9356 12:17:51.902344 in-header: 03 fc 00 00 01 00 00 00
9357 12:17:51.905285 in-data: 00
9358 12:17:51.908363 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9359 12:17:51.913467 in-header: 03 fd 00 00 00 00 00 00
9360 12:17:51.916704 in-data:
9361 12:17:51.919619 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9362 12:17:51.923308 in-header: 03 fc 00 00 01 00 00 00
9363 12:17:51.926431 in-data: 00
9364 12:17:51.930065 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9365 12:17:51.934493 in-header: 03 fd 00 00 00 00 00 00
9366 12:17:51.938350 in-data:
9367 12:17:51.941457 [SSUSB] Setting up USB HOST controller...
9368 12:17:51.944626 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9369 12:17:51.948324 [SSUSB] phy power-on done.
9370 12:17:51.951643 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9371 12:17:51.957678 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9372 12:17:51.961333 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9373 12:17:51.968161 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9374 12:17:51.974294 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9375 12:17:51.981326 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9376 12:17:51.987882 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9377 12:17:51.994442 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9378 12:17:51.997651 SPM: binary array size = 0x9dc
9379 12:17:52.000746 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9380 12:17:52.007601 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9381 12:17:52.013902 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9382 12:17:52.020655 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9383 12:17:52.024155 configure_display: Starting display init
9384 12:17:52.057756 anx7625_power_on_init: Init interface.
9385 12:17:52.061286 anx7625_disable_pd_protocol: Disabled PD feature.
9386 12:17:52.064355 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9387 12:17:52.092459 anx7625_start_dp_work: Secure OCM version=00
9388 12:17:52.096074 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9389 12:17:52.110626 sp_tx_get_edid_block: EDID Block = 1
9390 12:17:52.212991 Extracted contents:
9391 12:17:52.216197 header: 00 ff ff ff ff ff ff 00
9392 12:17:52.219321 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9393 12:17:52.222505 version: 01 04
9394 12:17:52.226224 basic params: 95 1f 11 78 0a
9395 12:17:52.229440 chroma info: 76 90 94 55 54 90 27 21 50 54
9396 12:17:52.232586 established: 00 00 00
9397 12:17:52.239074 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9398 12:17:52.242783 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9399 12:17:52.249085 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9400 12:17:52.255302 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9401 12:17:52.262360 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9402 12:17:52.265556 extensions: 00
9403 12:17:52.265641 checksum: fb
9404 12:17:52.265714
9405 12:17:52.268646 Manufacturer: IVO Model 57d Serial Number 0
9406 12:17:52.272265 Made week 0 of 2020
9407 12:17:52.275392 EDID version: 1.4
9408 12:17:52.275472 Digital display
9409 12:17:52.278489 6 bits per primary color channel
9410 12:17:52.278573 DisplayPort interface
9411 12:17:52.281846 Maximum image size: 31 cm x 17 cm
9412 12:17:52.284972 Gamma: 220%
9413 12:17:52.285058 Check DPMS levels
9414 12:17:52.291826 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9415 12:17:52.294941 First detailed timing is preferred timing
9416 12:17:52.295022 Established timings supported:
9417 12:17:52.298183 Standard timings supported:
9418 12:17:52.302041 Detailed timings
9419 12:17:52.304946 Hex of detail: 383680a07038204018303c0035ae10000019
9420 12:17:52.311608 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9421 12:17:52.315134 0780 0798 07c8 0820 hborder 0
9422 12:17:52.318055 0438 043b 0447 0458 vborder 0
9423 12:17:52.321701 -hsync -vsync
9424 12:17:52.321773 Did detailed timing
9425 12:17:52.327989 Hex of detail: 000000000000000000000000000000000000
9426 12:17:52.331152 Manufacturer-specified data, tag 0
9427 12:17:52.334781 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9428 12:17:52.337883 ASCII string: InfoVision
9429 12:17:52.341035 Hex of detail: 000000fe00523134304e574635205248200a
9430 12:17:52.344598 ASCII string: R140NWF5 RH
9431 12:17:52.344711 Checksum
9432 12:17:52.347730 Checksum: 0xfb (valid)
9433 12:17:52.350834 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9434 12:17:52.354607 DSI data_rate: 832800000 bps
9435 12:17:52.360876 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9436 12:17:52.363989 anx7625_parse_edid: pixelclock(138800).
9437 12:17:52.367810 hactive(1920), hsync(48), hfp(24), hbp(88)
9438 12:17:52.371042 vactive(1080), vsync(12), vfp(3), vbp(17)
9439 12:17:52.374290 anx7625_dsi_config: config dsi.
9440 12:17:52.381161 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9441 12:17:52.395298 anx7625_dsi_config: success to config DSI
9442 12:17:52.398499 anx7625_dp_start: MIPI phy setup OK.
9443 12:17:52.401528 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9444 12:17:52.404506 mtk_ddp_mode_set invalid vrefresh 60
9445 12:17:52.408131 main_disp_path_setup
9446 12:17:52.408267 ovl_layer_smi_id_en
9447 12:17:52.411514 ovl_layer_smi_id_en
9448 12:17:52.411677 ccorr_config
9449 12:17:52.411816 aal_config
9450 12:17:52.414478 gamma_config
9451 12:17:52.414663 postmask_config
9452 12:17:52.418075 dither_config
9453 12:17:52.420758 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9454 12:17:52.427787 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9455 12:17:52.430618 Root Device init finished in 552 msecs
9456 12:17:52.434418 CPU_CLUSTER: 0 init
9457 12:17:52.440796 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9458 12:17:52.447582 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9459 12:17:52.447672 APU_MBOX 0x190000b0 = 0x10001
9460 12:17:52.450820 APU_MBOX 0x190001b0 = 0x10001
9461 12:17:52.453914 APU_MBOX 0x190005b0 = 0x10001
9462 12:17:52.457634 APU_MBOX 0x190006b0 = 0x10001
9463 12:17:52.464077 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9464 12:17:52.473588 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9465 12:17:52.486460 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9466 12:17:52.492700 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9467 12:17:52.505063 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9468 12:17:52.513667 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9469 12:17:52.516793 CPU_CLUSTER: 0 init finished in 81 msecs
9470 12:17:52.520639 Devices initialized
9471 12:17:52.523720 Show all devs... After init.
9472 12:17:52.524149 Root Device: enabled 1
9473 12:17:52.526661 CPU_CLUSTER: 0: enabled 1
9474 12:17:52.530122 CPU: 00: enabled 1
9475 12:17:52.533444 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9476 12:17:52.536788 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9477 12:17:52.540305 ELOG: NV offset 0x57f000 size 0x1000
9478 12:17:52.547269 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9479 12:17:52.553641 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9480 12:17:52.556685 ELOG: Event(17) added with size 13 at 2023-06-06 12:17:52 UTC
9481 12:17:52.563515 out: cmd=0x121: 03 db 21 01 00 00 00 00
9482 12:17:52.566690 in-header: 03 a4 00 00 2c 00 00 00
9483 12:17:52.576675 in-data: bb 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9484 12:17:52.583485 ELOG: Event(A1) added with size 10 at 2023-06-06 12:17:52 UTC
9485 12:17:52.589717 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9486 12:17:52.596338 ELOG: Event(A0) added with size 9 at 2023-06-06 12:17:52 UTC
9487 12:17:52.599651 elog_add_boot_reason: Logged dev mode boot
9488 12:17:52.605944 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9489 12:17:52.606028 Finalize devices...
9490 12:17:52.609768 Devices finalized
9491 12:17:52.612978 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9492 12:17:52.616157 Writing coreboot table at 0xffe64000
9493 12:17:52.619288 0. 000000000010a000-0000000000113fff: RAMSTAGE
9494 12:17:52.625579 1. 0000000040000000-00000000400fffff: RAM
9495 12:17:52.629243 2. 0000000040100000-000000004032afff: RAMSTAGE
9496 12:17:52.632419 3. 000000004032b000-00000000545fffff: RAM
9497 12:17:52.635977 4. 0000000054600000-000000005465ffff: BL31
9498 12:17:52.638937 5. 0000000054660000-00000000ffe63fff: RAM
9499 12:17:52.645723 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9500 12:17:52.649064 7. 0000000100000000-000000023fffffff: RAM
9501 12:17:52.652625 Passing 5 GPIOs to payload:
9502 12:17:52.655529 NAME | PORT | POLARITY | VALUE
9503 12:17:52.662434 EC in RW | 0x000000aa | low | undefined
9504 12:17:52.665386 EC interrupt | 0x00000005 | low | undefined
9505 12:17:52.668899 TPM interrupt | 0x000000ab | high | undefined
9506 12:17:52.675707 SD card detect | 0x00000011 | high | undefined
9507 12:17:52.678874 speaker enable | 0x00000093 | high | undefined
9508 12:17:52.682124 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9509 12:17:52.685282 in-header: 03 f9 00 00 02 00 00 00
9510 12:17:52.688924 in-data: 02 00
9511 12:17:52.692004 ADC[4]: Raw value=904509 ID=7
9512 12:17:52.692089 ADC[3]: Raw value=213282 ID=1
9513 12:17:52.695183 RAM Code: 0x71
9514 12:17:52.698946 ADC[6]: Raw value=75036 ID=0
9515 12:17:52.699032 ADC[5]: Raw value=212912 ID=1
9516 12:17:52.702074 SKU Code: 0x1
9517 12:17:52.708473 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9518 12:17:52.708564 coreboot table: 964 bytes.
9519 12:17:52.711581 IMD ROOT 0. 0xfffff000 0x00001000
9520 12:17:52.715385 IMD SMALL 1. 0xffffe000 0x00001000
9521 12:17:52.718512 RO MCACHE 2. 0xffffc000 0x00001104
9522 12:17:52.721693 CONSOLE 3. 0xfff7c000 0x00080000
9523 12:17:52.724931 FMAP 4. 0xfff7b000 0x00000452
9524 12:17:52.728556 TIME STAMP 5. 0xfff7a000 0x00000910
9525 12:17:52.731744 VBOOT WORK 6. 0xfff66000 0x00014000
9526 12:17:52.734963 RAMOOPS 7. 0xffe66000 0x00100000
9527 12:17:52.738026 COREBOOT 8. 0xffe64000 0x00002000
9528 12:17:52.741686 IMD small region:
9529 12:17:52.744529 IMD ROOT 0. 0xffffec00 0x00000400
9530 12:17:52.747833 VPD 1. 0xffffeba0 0x0000004c
9531 12:17:52.751505 MMC STATUS 2. 0xffffeb80 0x00000004
9532 12:17:52.754978 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9533 12:17:52.758110 Probing TPM: done!
9534 12:17:52.761704 Connected to device vid:did:rid of 1ae0:0028:00
9535 12:17:52.772986 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9536 12:17:52.775813 Initialized TPM device CR50 revision 0
9537 12:17:52.779506 Checking cr50 for pending updates
9538 12:17:52.783230 Reading cr50 TPM mode
9539 12:17:52.792139 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9540 12:17:52.798882 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9541 12:17:52.838894 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9542 12:17:52.842052 Checking segment from ROM address 0x40100000
9543 12:17:52.845624 Checking segment from ROM address 0x4010001c
9544 12:17:52.852162 Loading segment from ROM address 0x40100000
9545 12:17:52.852251 code (compression=0)
9546 12:17:52.861970 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9547 12:17:52.868522 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9548 12:17:52.868616 it's not compressed!
9549 12:17:52.875477 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9550 12:17:52.878540 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9551 12:17:52.899024 Loading segment from ROM address 0x4010001c
9552 12:17:52.899126 Entry Point 0x80000000
9553 12:17:52.902688 Loaded segments
9554 12:17:52.905950 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9555 12:17:52.912252 Jumping to boot code at 0x80000000(0xffe64000)
9556 12:17:52.919248 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9557 12:17:52.925411 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9558 12:17:52.933583 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9559 12:17:52.936710 Checking segment from ROM address 0x40100000
9560 12:17:52.939788 Checking segment from ROM address 0x4010001c
9561 12:17:52.946701 Loading segment from ROM address 0x40100000
9562 12:17:52.946835 code (compression=1)
9563 12:17:52.953318 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9564 12:17:52.963045 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9565 12:17:52.963170 using LZMA
9566 12:17:52.972110 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9567 12:17:52.978663 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9568 12:17:52.981528 Loading segment from ROM address 0x4010001c
9569 12:17:52.981642 Entry Point 0x54601000
9570 12:17:52.984982 Loaded segments
9571 12:17:52.988637 NOTICE: MT8192 bl31_setup
9572 12:17:52.995406 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9573 12:17:52.999216 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9574 12:17:53.002353 WARNING: region 0:
9575 12:17:53.005526 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9576 12:17:53.005609 WARNING: region 1:
9577 12:17:53.012489 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9578 12:17:53.015656 WARNING: region 2:
9579 12:17:53.018766 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9580 12:17:53.021874 WARNING: region 3:
9581 12:17:53.025466 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9582 12:17:53.028666 WARNING: region 4:
9583 12:17:53.035728 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9584 12:17:53.035828 WARNING: region 5:
9585 12:17:53.038828 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9586 12:17:53.041951 WARNING: region 6:
9587 12:17:53.045269 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9588 12:17:53.048981 WARNING: region 7:
9589 12:17:53.052198 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9590 12:17:53.058401 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9591 12:17:53.062143 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9592 12:17:53.065114 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9593 12:17:53.072032 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9594 12:17:53.075061 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9595 12:17:53.078744 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9596 12:17:53.085386 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9597 12:17:53.088461 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9598 12:17:53.094985 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9599 12:17:53.098426 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9600 12:17:53.101457 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9601 12:17:53.108301 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9602 12:17:53.111447 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9603 12:17:53.115307 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9604 12:17:53.121602 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9605 12:17:53.124801 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9606 12:17:53.131717 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9607 12:17:53.134736 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9608 12:17:53.137929 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9609 12:17:53.144706 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9610 12:17:53.147776 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9611 12:17:53.154693 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9612 12:17:53.157776 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9613 12:17:53.161528 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9614 12:17:53.167651 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9615 12:17:53.171488 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9616 12:17:53.177807 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9617 12:17:53.180935 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9618 12:17:53.187545 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9619 12:17:53.190936 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9620 12:17:53.194141 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9621 12:17:53.200737 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9622 12:17:53.204363 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9623 12:17:53.207476 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9624 12:17:53.210566 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9625 12:17:53.217369 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9626 12:17:53.220586 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9627 12:17:53.224221 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9628 12:17:53.227278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9629 12:17:53.233677 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9630 12:17:53.237444 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9631 12:17:53.240495 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9632 12:17:53.243609 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9633 12:17:53.250489 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9634 12:17:53.253611 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9635 12:17:53.256881 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9636 12:17:53.263651 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9637 12:17:53.266691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9638 12:17:53.270101 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9639 12:17:53.276967 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9640 12:17:53.280072 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9641 12:17:53.286948 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9642 12:17:53.290086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9643 12:17:53.293481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9644 12:17:53.300014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9645 12:17:53.303729 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9646 12:17:53.309794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9647 12:17:53.313398 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9648 12:17:53.320233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9649 12:17:53.323304 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9650 12:17:53.330106 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9651 12:17:53.333311 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9652 12:17:53.336533 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9653 12:17:53.342842 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9654 12:17:53.346043 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9655 12:17:53.353018 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9656 12:17:53.356245 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9657 12:17:53.362624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9658 12:17:53.366320 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9659 12:17:53.373032 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9660 12:17:53.376079 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9661 12:17:53.379179 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9662 12:17:53.386182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9663 12:17:53.389239 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9664 12:17:53.396092 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9665 12:17:53.399131 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9666 12:17:53.406018 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9667 12:17:53.409500 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9668 12:17:53.416144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9669 12:17:53.419070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9670 12:17:53.422618 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9671 12:17:53.429486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9672 12:17:53.432563 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9673 12:17:53.439016 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9674 12:17:53.442075 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9675 12:17:53.448968 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9676 12:17:53.452202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9677 12:17:53.455293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9678 12:17:53.462027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9679 12:17:53.465178 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9680 12:17:53.472113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9681 12:17:53.475246 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9682 12:17:53.482376 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9683 12:17:53.485679 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9684 12:17:53.491947 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9685 12:17:53.495044 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9686 12:17:53.498875 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9687 12:17:53.505228 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9688 12:17:53.508399 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9689 12:17:53.511944 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9690 12:17:53.514932 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9691 12:17:53.521788 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9692 12:17:53.525035 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9693 12:17:53.531672 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9694 12:17:53.534798 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9695 12:17:53.538693 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9696 12:17:53.544960 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9697 12:17:53.548241 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9698 12:17:53.554605 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9699 12:17:53.558327 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9700 12:17:53.561493 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9701 12:17:53.568413 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9702 12:17:53.571571 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9703 12:17:53.577893 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9704 12:17:53.581570 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9705 12:17:53.584630 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9706 12:17:53.591507 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9707 12:17:53.594586 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9708 12:17:53.597796 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9709 12:17:53.604655 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9710 12:17:53.607772 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9711 12:17:53.610877 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9712 12:17:53.614728 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9713 12:17:53.621004 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9714 12:17:53.624845 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9715 12:17:53.627660 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9716 12:17:53.634587 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9717 12:17:53.637571 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9718 12:17:53.644312 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9719 12:17:53.647464 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9720 12:17:53.650714 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9721 12:17:53.657709 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9722 12:17:53.660675 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9723 12:17:53.667601 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9724 12:17:53.670681 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9725 12:17:53.673793 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9726 12:17:53.680618 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9727 12:17:53.683755 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9728 12:17:53.687332 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9729 12:17:53.694214 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9730 12:17:53.697203 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9731 12:17:53.703926 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9732 12:17:53.707038 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9733 12:17:53.713965 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9734 12:17:53.717091 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9735 12:17:53.720285 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9736 12:17:53.727156 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9737 12:17:53.730258 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9738 12:17:53.733803 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9739 12:17:53.740272 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9740 12:17:53.743591 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9741 12:17:53.750477 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9742 12:17:53.753728 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9743 12:17:53.756884 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9744 12:17:53.763675 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9745 12:17:53.766862 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9746 12:17:53.773836 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9747 12:17:53.777034 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9748 12:17:53.780292 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9749 12:17:53.786581 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9750 12:17:53.790388 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9751 12:17:53.796463 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9752 12:17:53.800209 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9753 12:17:53.803379 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9754 12:17:53.809686 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9755 12:17:53.813465 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9756 12:17:53.819938 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9757 12:17:53.822967 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9758 12:17:53.826203 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9759 12:17:53.832647 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9760 12:17:53.836279 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9761 12:17:53.842746 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9762 12:17:53.846252 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9763 12:17:53.849314 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9764 12:17:53.856077 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9765 12:17:53.859218 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9766 12:17:53.865477 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9767 12:17:53.869269 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9768 12:17:53.872364 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9769 12:17:53.878731 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9770 12:17:53.882413 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9771 12:17:53.888583 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9772 12:17:53.891673 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9773 12:17:53.895406 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9774 12:17:53.902093 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9775 12:17:53.904953 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9776 12:17:53.911954 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9777 12:17:53.915067 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9778 12:17:53.918105 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9779 12:17:53.925212 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9780 12:17:53.928381 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9781 12:17:53.934637 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9782 12:17:53.938279 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9783 12:17:53.944970 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9784 12:17:53.947912 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9785 12:17:53.951204 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9786 12:17:53.957831 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9787 12:17:53.961333 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9788 12:17:53.967554 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9789 12:17:53.970776 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9790 12:17:53.977785 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9791 12:17:53.980986 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9792 12:17:53.984580 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9793 12:17:53.990845 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9794 12:17:53.994606 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9795 12:17:54.001013 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9796 12:17:54.004109 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9797 12:17:54.007555 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9798 12:17:54.014159 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9799 12:17:54.017324 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9800 12:17:54.024257 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9801 12:17:54.027317 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9802 12:17:54.034309 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9803 12:17:54.037410 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9804 12:17:54.040601 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9805 12:17:54.047345 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9806 12:17:54.050452 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9807 12:17:54.056842 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9808 12:17:54.060498 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9809 12:17:54.066956 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9810 12:17:54.070514 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9811 12:17:54.073608 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9812 12:17:54.080032 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9813 12:17:54.083710 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9814 12:17:54.090138 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9815 12:17:54.093225 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9816 12:17:54.099936 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9817 12:17:54.103180 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9818 12:17:54.106406 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9819 12:17:54.112956 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9820 12:17:54.116505 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9821 12:17:54.119799 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9822 12:17:54.123459 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9823 12:17:54.129923 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9824 12:17:54.133208 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9825 12:17:54.136250 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9826 12:17:54.143307 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9827 12:17:54.146472 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9828 12:17:54.149769 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9829 12:17:54.156262 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9830 12:17:54.159681 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9831 12:17:54.166176 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9832 12:17:54.169521 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9833 12:17:54.172941 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9834 12:17:54.179263 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9835 12:17:54.182766 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9836 12:17:54.189051 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9837 12:17:54.192840 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9838 12:17:54.195852 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9839 12:17:54.202119 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9840 12:17:54.205892 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9841 12:17:54.209043 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9842 12:17:54.215911 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9843 12:17:54.219099 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9844 12:17:54.221955 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9845 12:17:54.228721 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9846 12:17:54.231992 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9847 12:17:54.238829 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9848 12:17:54.242108 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9849 12:17:54.245303 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9850 12:17:54.251666 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9851 12:17:54.255336 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9852 12:17:54.262151 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9853 12:17:54.264880 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9854 12:17:54.268769 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9855 12:17:54.275331 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9856 12:17:54.278439 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9857 12:17:54.281916 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9858 12:17:54.288495 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9859 12:17:54.291665 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9860 12:17:54.294865 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9861 12:17:54.297972 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9862 12:17:54.304773 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9863 12:17:54.307997 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9864 12:17:54.311679 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9865 12:17:54.314877 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9866 12:17:54.321151 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9867 12:17:54.324704 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9868 12:17:54.327733 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9869 12:17:54.331578 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9870 12:17:54.337938 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9871 12:17:54.341184 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9872 12:17:54.344240 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9873 12:17:54.351402 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9874 12:17:54.354450 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9875 12:17:54.360748 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9876 12:17:54.364403 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9877 12:17:54.370748 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9878 12:17:54.374509 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9879 12:17:54.377564 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9880 12:17:54.384205 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9881 12:17:54.387178 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9882 12:17:54.394221 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9883 12:17:54.397423 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9884 12:17:54.400820 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9885 12:17:54.407014 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9886 12:17:54.410323 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9887 12:17:54.417093 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9888 12:17:54.420161 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9889 12:17:54.427060 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9890 12:17:54.430079 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9891 12:17:54.433413 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9892 12:17:54.439881 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9893 12:17:54.443603 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9894 12:17:54.449926 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9895 12:17:54.453135 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9896 12:17:54.456290 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9897 12:17:54.463178 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9898 12:17:54.466268 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9899 12:17:54.472919 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9900 12:17:54.476467 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9901 12:17:54.482527 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9902 12:17:54.486108 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9903 12:17:54.489456 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9904 12:17:54.496330 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9905 12:17:54.499107 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9906 12:17:54.505979 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9907 12:17:54.509103 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9908 12:17:54.515319 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9909 12:17:54.519295 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9910 12:17:54.522409 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9911 12:17:54.529354 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9912 12:17:54.532367 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9913 12:17:54.538793 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9914 12:17:54.541901 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9915 12:17:54.545055 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9916 12:17:54.552237 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9917 12:17:54.555367 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9918 12:17:54.561667 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9919 12:17:54.565754 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9920 12:17:54.568891 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9921 12:17:54.574987 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9922 12:17:54.578684 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9923 12:17:54.585102 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9924 12:17:54.588454 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9925 12:17:54.594886 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9926 12:17:54.598553 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9927 12:17:54.601651 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9928 12:17:54.608472 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9929 12:17:54.611571 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9930 12:17:54.618580 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9931 12:17:54.621523 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9932 12:17:54.627823 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9933 12:17:54.631473 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9934 12:17:54.634746 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9935 12:17:54.641804 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9936 12:17:54.644870 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9937 12:17:54.651129 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9938 12:17:54.654392 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9939 12:17:54.658062 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9940 12:17:54.664326 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9941 12:17:54.667564 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9942 12:17:54.674172 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9943 12:17:54.678039 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9944 12:17:54.681072 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9945 12:17:54.687529 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9946 12:17:54.691107 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9947 12:17:54.697238 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9948 12:17:54.700878 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9949 12:17:54.707672 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9950 12:17:54.710455 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9951 12:17:54.717406 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9952 12:17:54.720664 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9953 12:17:54.723761 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9954 12:17:54.730674 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9955 12:17:54.733742 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9956 12:17:54.740750 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9957 12:17:54.743834 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9958 12:17:54.750769 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9959 12:17:54.753240 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9960 12:17:54.760000 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9961 12:17:54.763701 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9962 12:17:54.766877 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9963 12:17:54.773201 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9964 12:17:54.776476 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9965 12:17:54.782590 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9966 12:17:54.786491 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9967 12:17:54.793040 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9968 12:17:54.795934 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9969 12:17:54.802615 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9970 12:17:54.806158 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9971 12:17:54.809645 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9972 12:17:54.816126 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9973 12:17:54.819219 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9974 12:17:54.826095 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9975 12:17:54.829139 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9976 12:17:54.835452 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9977 12:17:54.839521 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9978 12:17:54.845814 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9979 12:17:54.848894 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9980 12:17:54.852608 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9981 12:17:54.858944 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9982 12:17:54.862635 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9983 12:17:54.869034 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9984 12:17:54.872357 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9985 12:17:54.878790 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9986 12:17:54.881674 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9987 12:17:54.888502 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9988 12:17:54.891731 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9989 12:17:54.898251 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9990 12:17:54.901746 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9991 12:17:54.905241 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9992 12:17:54.911795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9993 12:17:54.914950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9994 12:17:54.921415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9995 12:17:54.925224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9996 12:17:54.931415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9997 12:17:54.934469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9998 12:17:54.941562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9999 12:17:54.944777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10000 12:17:54.951119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10001 12:17:54.955020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10002 12:17:54.957653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10003 12:17:54.964880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10004 12:17:54.967987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10005 12:17:54.974359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10006 12:17:54.977481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10007 12:17:54.984357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10008 12:17:54.987472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10009 12:17:54.993923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10010 12:17:54.997057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10011 12:17:55.003929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10012 12:17:55.007214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10013 12:17:55.014052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10014 12:17:55.016995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10015 12:17:55.023987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10016 12:17:55.030187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10017 12:17:55.033966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10018 12:17:55.040240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10019 12:17:55.043437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10020 12:17:55.050253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10021 12:17:55.053306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10022 12:17:55.060056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10023 12:17:55.063111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10024 12:17:55.066692 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10025 12:17:55.069687 INFO: [APUAPC] vio 0
10026 12:17:55.076479 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10027 12:17:55.080269 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10028 12:17:55.083132 INFO: [APUAPC] D0_APC_0: 0x400510
10029 12:17:55.086469 INFO: [APUAPC] D0_APC_1: 0x0
10030 12:17:55.089656 INFO: [APUAPC] D0_APC_2: 0x1540
10031 12:17:55.092984 INFO: [APUAPC] D0_APC_3: 0x0
10032 12:17:55.096008 INFO: [APUAPC] D1_APC_0: 0xffffffff
10033 12:17:55.099254 INFO: [APUAPC] D1_APC_1: 0xffffffff
10034 12:17:55.103218 INFO: [APUAPC] D1_APC_2: 0x3fffff
10035 12:17:55.106266 INFO: [APUAPC] D1_APC_3: 0x0
10036 12:17:55.109196 INFO: [APUAPC] D2_APC_0: 0xffffffff
10037 12:17:55.112718 INFO: [APUAPC] D2_APC_1: 0xffffffff
10038 12:17:55.115578 INFO: [APUAPC] D2_APC_2: 0x3fffff
10039 12:17:55.119389 INFO: [APUAPC] D2_APC_3: 0x0
10040 12:17:55.122851 INFO: [APUAPC] D3_APC_0: 0xffffffff
10041 12:17:55.125858 INFO: [APUAPC] D3_APC_1: 0xffffffff
10042 12:17:55.129426 INFO: [APUAPC] D3_APC_2: 0x3fffff
10043 12:17:55.129984 INFO: [APUAPC] D3_APC_3: 0x0
10044 12:17:55.135838 INFO: [APUAPC] D4_APC_0: 0xffffffff
10045 12:17:55.139066 INFO: [APUAPC] D4_APC_1: 0xffffffff
10046 12:17:55.142280 INFO: [APUAPC] D4_APC_2: 0x3fffff
10047 12:17:55.142786 INFO: [APUAPC] D4_APC_3: 0x0
10048 12:17:55.145902 INFO: [APUAPC] D5_APC_0: 0xffffffff
10049 12:17:55.148882 INFO: [APUAPC] D5_APC_1: 0xffffffff
10050 12:17:55.152077 INFO: [APUAPC] D5_APC_2: 0x3fffff
10051 12:17:55.155215 INFO: [APUAPC] D5_APC_3: 0x0
10052 12:17:55.158608 INFO: [APUAPC] D6_APC_0: 0xffffffff
10053 12:17:55.162385 INFO: [APUAPC] D6_APC_1: 0xffffffff
10054 12:17:55.165510 INFO: [APUAPC] D6_APC_2: 0x3fffff
10055 12:17:55.168410 INFO: [APUAPC] D6_APC_3: 0x0
10056 12:17:55.172187 INFO: [APUAPC] D7_APC_0: 0xffffffff
10057 12:17:55.175702 INFO: [APUAPC] D7_APC_1: 0xffffffff
10058 12:17:55.178468 INFO: [APUAPC] D7_APC_2: 0x3fffff
10059 12:17:55.182072 INFO: [APUAPC] D7_APC_3: 0x0
10060 12:17:55.184956 INFO: [APUAPC] D8_APC_0: 0xffffffff
10061 12:17:55.188735 INFO: [APUAPC] D8_APC_1: 0xffffffff
10062 12:17:55.191859 INFO: [APUAPC] D8_APC_2: 0x3fffff
10063 12:17:55.194997 INFO: [APUAPC] D8_APC_3: 0x0
10064 12:17:55.198235 INFO: [APUAPC] D9_APC_0: 0xffffffff
10065 12:17:55.202059 INFO: [APUAPC] D9_APC_1: 0xffffffff
10066 12:17:55.205234 INFO: [APUAPC] D9_APC_2: 0x3fffff
10067 12:17:55.208483 INFO: [APUAPC] D9_APC_3: 0x0
10068 12:17:55.211313 INFO: [APUAPC] D10_APC_0: 0xffffffff
10069 12:17:55.215018 INFO: [APUAPC] D10_APC_1: 0xffffffff
10070 12:17:55.217899 INFO: [APUAPC] D10_APC_2: 0x3fffff
10071 12:17:55.221652 INFO: [APUAPC] D10_APC_3: 0x0
10072 12:17:55.224739 INFO: [APUAPC] D11_APC_0: 0xffffffff
10073 12:17:55.228433 INFO: [APUAPC] D11_APC_1: 0xffffffff
10074 12:17:55.231440 INFO: [APUAPC] D11_APC_2: 0x3fffff
10075 12:17:55.234527 INFO: [APUAPC] D11_APC_3: 0x0
10076 12:17:55.238268 INFO: [APUAPC] D12_APC_0: 0xffffffff
10077 12:17:55.241513 INFO: [APUAPC] D12_APC_1: 0xffffffff
10078 12:17:55.244826 INFO: [APUAPC] D12_APC_2: 0x3fffff
10079 12:17:55.247716 INFO: [APUAPC] D12_APC_3: 0x0
10080 12:17:55.251625 INFO: [APUAPC] D13_APC_0: 0xffffffff
10081 12:17:55.254802 INFO: [APUAPC] D13_APC_1: 0xffffffff
10082 12:17:55.258188 INFO: [APUAPC] D13_APC_2: 0x3fffff
10083 12:17:55.261102 INFO: [APUAPC] D13_APC_3: 0x0
10084 12:17:55.264298 INFO: [APUAPC] D14_APC_0: 0xffffffff
10085 12:17:55.267478 INFO: [APUAPC] D14_APC_1: 0xffffffff
10086 12:17:55.271095 INFO: [APUAPC] D14_APC_2: 0x3fffff
10087 12:17:55.274552 INFO: [APUAPC] D14_APC_3: 0x0
10088 12:17:55.277363 INFO: [APUAPC] D15_APC_0: 0xffffffff
10089 12:17:55.284313 INFO: [APUAPC] D15_APC_1: 0xffffffff
10090 12:17:55.287379 INFO: [APUAPC] D15_APC_2: 0x3fffff
10091 12:17:55.287883 INFO: [APUAPC] D15_APC_3: 0x0
10092 12:17:55.290688 INFO: [APUAPC] APC_CON: 0x4
10093 12:17:55.294427 INFO: [NOCDAPC] D0_APC_0: 0x0
10094 12:17:55.297765 INFO: [NOCDAPC] D0_APC_1: 0x0
10095 12:17:55.300550 INFO: [NOCDAPC] D1_APC_0: 0x0
10096 12:17:55.304392 INFO: [NOCDAPC] D1_APC_1: 0xfff
10097 12:17:55.307636 INFO: [NOCDAPC] D2_APC_0: 0x0
10098 12:17:55.310670 INFO: [NOCDAPC] D2_APC_1: 0xfff
10099 12:17:55.313777 INFO: [NOCDAPC] D3_APC_0: 0x0
10100 12:17:55.317414 INFO: [NOCDAPC] D3_APC_1: 0xfff
10101 12:17:55.317905 INFO: [NOCDAPC] D4_APC_0: 0x0
10102 12:17:55.320506 INFO: [NOCDAPC] D4_APC_1: 0xfff
10103 12:17:55.324132 INFO: [NOCDAPC] D5_APC_0: 0x0
10104 12:17:55.327049 INFO: [NOCDAPC] D5_APC_1: 0xfff
10105 12:17:55.330343 INFO: [NOCDAPC] D6_APC_0: 0x0
10106 12:17:55.333796 INFO: [NOCDAPC] D6_APC_1: 0xfff
10107 12:17:55.336974 INFO: [NOCDAPC] D7_APC_0: 0x0
10108 12:17:55.340461 INFO: [NOCDAPC] D7_APC_1: 0xfff
10109 12:17:55.343326 INFO: [NOCDAPC] D8_APC_0: 0x0
10110 12:17:55.346992 INFO: [NOCDAPC] D8_APC_1: 0xfff
10111 12:17:55.350171 INFO: [NOCDAPC] D9_APC_0: 0x0
10112 12:17:55.350603 INFO: [NOCDAPC] D9_APC_1: 0xfff
10113 12:17:55.353293 INFO: [NOCDAPC] D10_APC_0: 0x0
10114 12:17:55.357164 INFO: [NOCDAPC] D10_APC_1: 0xfff
10115 12:17:55.360389 INFO: [NOCDAPC] D11_APC_0: 0x0
10116 12:17:55.363504 INFO: [NOCDAPC] D11_APC_1: 0xfff
10117 12:17:55.366883 INFO: [NOCDAPC] D12_APC_0: 0x0
10118 12:17:55.369852 INFO: [NOCDAPC] D12_APC_1: 0xfff
10119 12:17:55.373133 INFO: [NOCDAPC] D13_APC_0: 0x0
10120 12:17:55.376919 INFO: [NOCDAPC] D13_APC_1: 0xfff
10121 12:17:55.380271 INFO: [NOCDAPC] D14_APC_0: 0x0
10122 12:17:55.383257 INFO: [NOCDAPC] D14_APC_1: 0xfff
10123 12:17:55.386816 INFO: [NOCDAPC] D15_APC_0: 0x0
10124 12:17:55.389715 INFO: [NOCDAPC] D15_APC_1: 0xfff
10125 12:17:55.392914 INFO: [NOCDAPC] APC_CON: 0x4
10126 12:17:55.396401 INFO: [APUAPC] set_apusys_apc done
10127 12:17:55.399546 INFO: [DEVAPC] devapc_init done
10128 12:17:55.403319 INFO: GICv3 without legacy support detected.
10129 12:17:55.406424 INFO: ARM GICv3 driver initialized in EL3
10130 12:17:55.409683 INFO: Maximum SPI INTID supported: 639
10131 12:17:55.412690 INFO: BL31: Initializing runtime services
10132 12:17:55.419520 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10133 12:17:55.422441 INFO: SPM: enable CPC mode
10134 12:17:55.429187 INFO: mcdi ready for mcusys-off-idle and system suspend
10135 12:17:55.432866 INFO: BL31: Preparing for EL3 exit to normal world
10136 12:17:55.435984 INFO: Entry point address = 0x80000000
10137 12:17:55.439211 INFO: SPSR = 0x8
10138 12:17:55.443945
10139 12:17:55.444377
10140 12:17:55.444766
10141 12:17:55.447009 Starting depthcharge on Spherion...
10142 12:17:55.447438
10143 12:17:55.447776 Wipe memory regions:
10144 12:17:55.448093
10145 12:17:55.450328 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10146 12:17:55.450840 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10147 12:17:55.451249 Setting prompt string to ['asurada:']
10148 12:17:55.451651 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10149 12:17:55.452343 [0x00000040000000, 0x00000054600000)
10150 12:17:55.572969
10151 12:17:55.573486 [0x00000054660000, 0x00000080000000)
10152 12:17:55.833887
10153 12:17:55.834414 [0x000000821a7280, 0x000000ffe64000)
10154 12:17:56.578291
10155 12:17:56.578849 [0x00000100000000, 0x00000240000000)
10156 12:17:58.468548
10157 12:17:58.472291 Initializing XHCI USB controller at 0x11200000.
10158 12:17:59.453077
10159 12:17:59.453747 R8152: Initializing
10160 12:17:59.454095
10161 12:17:59.456567 Version 9 (ocp_data = 6010)
10162 12:17:59.456996
10163 12:17:59.460238 R8152: Done initializing
10164 12:17:59.460702
10165 12:17:59.461043 Adding net device
10166 12:17:59.981921
10167 12:17:59.984973 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10168 12:17:59.985416
10169 12:17:59.985758
10170 12:17:59.986078
10171 12:17:59.986855 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10173 12:18:00.088042 asurada: tftpboot 192.168.201.1 10605447/tftp-deploy-nuzl_41d/kernel/image.itb 10605447/tftp-deploy-nuzl_41d/kernel/cmdline
10174 12:18:00.088207 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10175 12:18:00.088290 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10176 12:18:00.092643 tftpboot 192.168.201.1 10605447/tftp-deploy-nuzl_41d/kernel/image.itp-deploy-nuzl_41d/kernel/cmdline
10177 12:18:00.092748
10178 12:18:00.092820 Waiting for link
10179 12:18:00.295142
10180 12:18:00.295663 done.
10181 12:18:00.296024
10182 12:18:00.296361 MAC: f4:f5:e8:50:de:0a
10183 12:18:00.296756
10184 12:18:00.298356 Sending DHCP discover... done.
10185 12:18:00.298812
10186 12:18:00.301407 Waiting for reply... done.
10187 12:18:00.301862
10188 12:18:00.305037 Sending DHCP request... done.
10189 12:18:00.305470
10190 12:18:00.305818 Waiting for reply... done.
10191 12:18:00.308139
10192 12:18:00.308727 My ip is 192.168.201.14
10193 12:18:00.309091
10194 12:18:00.311219 The DHCP server ip is 192.168.201.1
10195 12:18:00.311656
10196 12:18:00.314697 TFTP server IP predefined by user: 192.168.201.1
10197 12:18:00.315134
10198 12:18:00.321461 Bootfile predefined by user: 10605447/tftp-deploy-nuzl_41d/kernel/image.itb
10199 12:18:00.321900
10200 12:18:00.324575 Sending tftp read request... done.
10201 12:18:00.325100
10202 12:18:00.332962 Waiting for the transfer...
10203 12:18:00.333604
10204 12:18:00.646380 00000000 ################################################################
10205 12:18:00.646557
10206 12:18:00.871864 00080000 ################################################################
10207 12:18:00.872001
10208 12:18:01.102064 00100000 ################################################################
10209 12:18:01.102202
10210 12:18:01.336267 00180000 ################################################################
10211 12:18:01.336418
10212 12:18:01.565977 00200000 ################################################################
10213 12:18:01.566124
10214 12:18:01.803350 00280000 ################################################################
10215 12:18:01.803503
10216 12:18:02.040796 00300000 ################################################################
10217 12:18:02.040950
10218 12:18:02.288587 00380000 ################################################################
10219 12:18:02.288780
10220 12:18:02.522194 00400000 ################################################################
10221 12:18:02.522348
10222 12:18:02.765141 00480000 ################################################################
10223 12:18:02.765298
10224 12:18:03.001460 00500000 ################################################################
10225 12:18:03.001607
10226 12:18:03.232099 00580000 ################################################################
10227 12:18:03.232248
10228 12:18:03.460151 00600000 ################################################################
10229 12:18:03.460314
10230 12:18:03.703373 00680000 ################################################################
10231 12:18:03.703527
10232 12:18:03.949161 00700000 ################################################################
10233 12:18:03.949340
10234 12:18:04.173594 00780000 ################################################################
10235 12:18:04.173741
10236 12:18:04.397577 00800000 ################################################################
10237 12:18:04.397751
10238 12:18:04.646418 00880000 ################################################################
10239 12:18:04.646568
10240 12:18:04.868026 00900000 ################################################################
10241 12:18:04.868175
10242 12:18:05.091587 00980000 ################################################################
10243 12:18:05.091739
10244 12:18:05.309020 00a00000 ################################################################
10245 12:18:05.309178
10246 12:18:05.530688 00a80000 ################################################################
10247 12:18:05.530844
10248 12:18:05.761440 00b00000 ################################################################
10249 12:18:05.761600
10250 12:18:06.000377 00b80000 ################################################################
10251 12:18:06.000551
10252 12:18:06.242250 00c00000 ################################################################
10253 12:18:06.242399
10254 12:18:06.475006 00c80000 ################################################################
10255 12:18:06.475158
10256 12:18:06.699548 00d00000 ################################################################
10257 12:18:06.699699
10258 12:18:06.933215 00d80000 ################################################################
10259 12:18:06.933393
10260 12:18:07.167858 00e00000 ################################################################
10261 12:18:07.168009
10262 12:18:07.405108 00e80000 ################################################################
10263 12:18:07.405256
10264 12:18:07.636708 00f00000 ################################################################
10265 12:18:07.636858
10266 12:18:07.862868 00f80000 ################################################################
10267 12:18:07.863018
10268 12:18:08.092325 01000000 ################################################################
10269 12:18:08.092473
10270 12:18:08.321168 01080000 ################################################################
10271 12:18:08.321312
10272 12:18:08.545232 01100000 ################################################################
10273 12:18:08.545384
10274 12:18:08.774595 01180000 ################################################################
10275 12:18:08.774748
10276 12:18:09.021083 01200000 ################################################################
10277 12:18:09.021238
10278 12:18:09.278779 01280000 ################################################################
10279 12:18:09.278934
10280 12:18:09.516415 01300000 ################################################################
10281 12:18:09.516622
10282 12:18:09.740471 01380000 ################################################################
10283 12:18:09.740673
10284 12:18:09.970923 01400000 ################################################################
10285 12:18:09.971100
10286 12:18:10.192104 01480000 ################################################################
10287 12:18:10.192285
10288 12:18:10.412103 01500000 ################################################################
10289 12:18:10.412305
10290 12:18:10.642937 01580000 ################################################################
10291 12:18:10.643091
10292 12:18:10.872138 01600000 ################################################################
10293 12:18:10.872335
10294 12:18:11.102953 01680000 ################################################################
10295 12:18:11.103138
10296 12:18:11.336844 01700000 ################################################################
10297 12:18:11.336998
10298 12:18:11.571850 01780000 ################################################################
10299 12:18:11.572001
10300 12:18:11.798873 01800000 ################################################################
10301 12:18:11.799051
10302 12:18:12.026798 01880000 ################################################################
10303 12:18:12.026949
10304 12:18:12.259319 01900000 ################################################################
10305 12:18:12.259483
10306 12:18:12.483638 01980000 ################################################################
10307 12:18:12.483827
10308 12:18:12.706367 01a00000 ################################################################
10309 12:18:12.706527
10310 12:18:12.932006 01a80000 ################################################################
10311 12:18:12.932197
10312 12:18:13.120074 01b00000 ###################################################### done.
10313 12:18:13.120223
10314 12:18:13.123175 The bootfile was 28750666 bytes long.
10315 12:18:13.123263
10316 12:18:13.126631 Sending tftp read request... done.
10317 12:18:13.126778
10318 12:18:13.130025 Waiting for the transfer...
10319 12:18:13.130110
10320 12:18:13.133042 00000000 # done.
10321 12:18:13.133127
10322 12:18:13.139354 Command line loaded dynamically from TFTP file: 10605447/tftp-deploy-nuzl_41d/kernel/cmdline
10323 12:18:13.139447
10324 12:18:13.159447 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605447/extract-nfsrootfs-apxzj0_7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10325 12:18:13.159545
10326 12:18:13.159612 Loading FIT.
10327 12:18:13.159673
10328 12:18:13.162474 Image ramdisk-1 has 18607087 bytes.
10329 12:18:13.162557
10330 12:18:13.165634 Image fdt-1 has 46924 bytes.
10331 12:18:13.165717
10332 12:18:13.169352 Image kernel-1 has 10094623 bytes.
10333 12:18:13.169461
10334 12:18:13.179182 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10335 12:18:13.179325
10336 12:18:13.195393 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10337 12:18:13.195504
10338 12:18:13.202261 Choosing best match conf-1 for compat google,spherion-rev2.
10339 12:18:13.202349
10340 12:18:13.209215 Connected to device vid:did:rid of 1ae0:0028:00
10341 12:18:13.216698
10342 12:18:13.220423 tpm_get_response: command 0x17b, return code 0x0
10343 12:18:13.220551
10344 12:18:13.223681 ec_init: CrosEC protocol v3 supported (256, 248)
10345 12:18:13.227144
10346 12:18:13.230554 tpm_cleanup: add release locality here.
10347 12:18:13.230642
10348 12:18:13.230710 Shutting down all USB controllers.
10349 12:18:13.234029
10350 12:18:13.234115 Removing current net device
10351 12:18:13.234183
10352 12:18:13.240493 Exiting depthcharge with code 4 at timestamp: 47242592
10353 12:18:13.240589
10354 12:18:13.243862 LZMA decompressing kernel-1 to 0x821a6718
10355 12:18:13.243949
10356 12:18:13.246892 LZMA decompressing kernel-1 to 0x40000000
10357 12:18:14.516172
10358 12:18:14.516776 jumping to kernel
10359 12:18:14.518252 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
10360 12:18:14.518789 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10361 12:18:14.519212 Setting prompt string to ['Linux version [0-9]']
10362 12:18:14.519589 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10363 12:18:14.519966 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10364 12:18:14.597685
10365 12:18:14.601304 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10366 12:18:14.604986 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
10367 12:18:14.605452 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10368 12:18:14.605866 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10369 12:18:14.606256 Using line separator: #'\n'#
10370 12:18:14.606579 No login prompt set.
10371 12:18:14.606929 Parsing kernel messages
10372 12:18:14.607227 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10373 12:18:14.607759 [login-action] Waiting for messages, (timeout 00:04:06)
10374 12:18:14.623826 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
10375 12:18:14.627508 [ 0.000000] random: crng init done
10376 12:18:14.633809 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10377 12:18:14.637654 [ 0.000000] efi: UEFI not found.
10378 12:18:14.643556 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10379 12:18:14.650536 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10380 12:18:14.660383 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10381 12:18:14.670222 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10382 12:18:14.677002 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10383 12:18:14.683317 [ 0.000000] printk: bootconsole [mtk8250] enabled
10384 12:18:14.690335 [ 0.000000] NUMA: No NUMA configuration found
10385 12:18:14.696507 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10386 12:18:14.700300 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10387 12:18:14.703406 [ 0.000000] Zone ranges:
10388 12:18:14.709725 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10389 12:18:14.713449 [ 0.000000] DMA32 empty
10390 12:18:14.719836 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10391 12:18:14.723468 [ 0.000000] Movable zone start for each node
10392 12:18:14.726532 [ 0.000000] Early memory node ranges
10393 12:18:14.733344 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10394 12:18:14.739808 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10395 12:18:14.746241 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10396 12:18:14.752634 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10397 12:18:14.759960 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10398 12:18:14.765765 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10399 12:18:14.822308 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10400 12:18:14.828644 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10401 12:18:14.834910 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10402 12:18:14.838693 [ 0.000000] psci: probing for conduit method from DT.
10403 12:18:14.845134 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10404 12:18:14.848838 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10405 12:18:14.854826 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10406 12:18:14.858015 [ 0.000000] psci: SMC Calling Convention v1.2
10407 12:18:14.864712 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10408 12:18:14.868305 [ 0.000000] Detected VIPT I-cache on CPU0
10409 12:18:14.874895 [ 0.000000] CPU features: detected: GIC system register CPU interface
10410 12:18:14.881458 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10411 12:18:14.887715 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10412 12:18:14.894511 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10413 12:18:14.904636 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10414 12:18:14.910683 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10415 12:18:14.913830 [ 0.000000] alternatives: applying boot alternatives
10416 12:18:14.921128 [ 0.000000] Fallback order for Node 0: 0
10417 12:18:14.927057 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10418 12:18:14.930927 [ 0.000000] Policy zone: Normal
10419 12:18:14.950148 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605447/extract-nfsrootfs-apxzj0_7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10420 12:18:14.960207 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10421 12:18:14.972573 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10422 12:18:14.982455 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10423 12:18:14.988870 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10424 12:18:14.992451 <6>[ 0.000000] software IO TLB: area num 8.
10425 12:18:15.049066 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10426 12:18:15.198579 <6>[ 0.000000] Memory: 7954776K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397992K reserved, 32768K cma-reserved)
10427 12:18:15.204640 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10428 12:18:15.211057 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10429 12:18:15.214823 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10430 12:18:15.221810 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10431 12:18:15.227821 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10432 12:18:15.231045 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10433 12:18:15.241385 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10434 12:18:15.247421 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10435 12:18:15.254238 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10436 12:18:15.260471 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10437 12:18:15.263798 <6>[ 0.000000] GICv3: 608 SPIs implemented
10438 12:18:15.266931 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10439 12:18:15.273680 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10440 12:18:15.276880 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10441 12:18:15.283086 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10442 12:18:15.296361 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10443 12:18:15.309835 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10444 12:18:15.316317 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10445 12:18:15.324467 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10446 12:18:15.337455 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10447 12:18:15.343675 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10448 12:18:15.350462 <6>[ 0.009146] Console: colour dummy device 80x25
10449 12:18:15.360413 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10450 12:18:15.367247 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10451 12:18:15.370408 <6>[ 0.029217] LSM: Security Framework initializing
10452 12:18:15.377239 <6>[ 0.034156] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10453 12:18:15.387207 <6>[ 0.041969] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10454 12:18:15.397161 <6>[ 0.051391] cblist_init_generic: Setting adjustable number of callback queues.
10455 12:18:15.400096 <6>[ 0.058845] cblist_init_generic: Setting shift to 3 and lim to 1.
10456 12:18:15.406914 <6>[ 0.065223] cblist_init_generic: Setting shift to 3 and lim to 1.
10457 12:18:15.413337 <6>[ 0.071631] rcu: Hierarchical SRCU implementation.
10458 12:18:15.420116 <6>[ 0.076676] rcu: Max phase no-delay instances is 1000.
10459 12:18:15.426587 <6>[ 0.083692] EFI services will not be available.
10460 12:18:15.429728 <6>[ 0.088664] smp: Bringing up secondary CPUs ...
10461 12:18:15.437898 <6>[ 0.093719] Detected VIPT I-cache on CPU1
10462 12:18:15.444139 <6>[ 0.093790] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10463 12:18:15.450859 <6>[ 0.093820] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10464 12:18:15.453978 <6>[ 0.094156] Detected VIPT I-cache on CPU2
10465 12:18:15.463895 <6>[ 0.094204] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10466 12:18:15.470540 <6>[ 0.094220] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10467 12:18:15.474258 <6>[ 0.094477] Detected VIPT I-cache on CPU3
10468 12:18:15.480427 <6>[ 0.094523] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10469 12:18:15.487450 <6>[ 0.094536] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10470 12:18:15.493692 <6>[ 0.094841] CPU features: detected: Spectre-v4
10471 12:18:15.496705 <6>[ 0.094848] CPU features: detected: Spectre-BHB
10472 12:18:15.500463 <6>[ 0.094853] Detected PIPT I-cache on CPU4
10473 12:18:15.506738 <6>[ 0.094909] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10474 12:18:15.516419 <6>[ 0.094925] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10475 12:18:15.519754 <6>[ 0.095218] Detected PIPT I-cache on CPU5
10476 12:18:15.526499 <6>[ 0.095281] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10477 12:18:15.533523 <6>[ 0.095297] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10478 12:18:15.536385 <6>[ 0.095583] Detected PIPT I-cache on CPU6
10479 12:18:15.546385 <6>[ 0.095649] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10480 12:18:15.552669 <6>[ 0.095665] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10481 12:18:15.556431 <6>[ 0.095963] Detected PIPT I-cache on CPU7
10482 12:18:15.562771 <6>[ 0.096027] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10483 12:18:15.569666 <6>[ 0.096043] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10484 12:18:15.572855 <6>[ 0.096090] smp: Brought up 1 node, 8 CPUs
10485 12:18:15.579075 <6>[ 0.237466] SMP: Total of 8 processors activated.
10486 12:18:15.585860 <6>[ 0.242387] CPU features: detected: 32-bit EL0 Support
10487 12:18:15.592678 <6>[ 0.247750] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10488 12:18:15.598923 <6>[ 0.256550] CPU features: detected: Common not Private translations
10489 12:18:15.605883 <6>[ 0.263026] CPU features: detected: CRC32 instructions
10490 12:18:15.612223 <6>[ 0.268411] CPU features: detected: RCpc load-acquire (LDAPR)
10491 12:18:15.615360 <6>[ 0.274371] CPU features: detected: LSE atomic instructions
10492 12:18:15.621989 <6>[ 0.280188] CPU features: detected: Privileged Access Never
10493 12:18:15.628503 <6>[ 0.285968] CPU features: detected: RAS Extension Support
10494 12:18:15.635428 <6>[ 0.291577] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10495 12:18:15.638869 <6>[ 0.298795] CPU: All CPU(s) started at EL2
10496 12:18:15.645057 <6>[ 0.303111] alternatives: applying system-wide alternatives
10497 12:18:15.655037 <6>[ 0.313763] devtmpfs: initialized
10498 12:18:15.671240 <6>[ 0.322820] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10499 12:18:15.677516 <6>[ 0.332781] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10500 12:18:15.684483 <6>[ 0.340797] pinctrl core: initialized pinctrl subsystem
10501 12:18:15.687591 <6>[ 0.347472] DMI not present or invalid.
10502 12:18:15.693905 <6>[ 0.351881] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10503 12:18:15.704096 <6>[ 0.358760] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10504 12:18:15.710261 <6>[ 0.366344] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10505 12:18:15.720776 <6>[ 0.374558] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10506 12:18:15.723733 <6>[ 0.382799] audit: initializing netlink subsys (disabled)
10507 12:18:15.733856 <5>[ 0.388493] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10508 12:18:15.739997 <6>[ 0.389205] thermal_sys: Registered thermal governor 'step_wise'
10509 12:18:15.747068 <6>[ 0.396456] thermal_sys: Registered thermal governor 'power_allocator'
10510 12:18:15.750021 <6>[ 0.402713] cpuidle: using governor menu
10511 12:18:15.756961 <6>[ 0.413680] NET: Registered PF_QIPCRTR protocol family
10512 12:18:15.763611 <6>[ 0.419172] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10513 12:18:15.769825 <6>[ 0.426272] ASID allocator initialised with 32768 entries
10514 12:18:15.773554 <6>[ 0.432838] Serial: AMBA PL011 UART driver
10515 12:18:15.783648 <4>[ 0.441516] Trying to register duplicate clock ID: 134
10516 12:18:15.837420 <6>[ 0.498687] KASLR enabled
10517 12:18:15.851678 <6>[ 0.506377] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10518 12:18:15.858571 <6>[ 0.513387] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10519 12:18:15.864837 <6>[ 0.519873] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10520 12:18:15.871518 <6>[ 0.526879] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10521 12:18:15.878236 <6>[ 0.533366] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10522 12:18:15.884580 <6>[ 0.540371] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10523 12:18:15.891374 <6>[ 0.546860] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10524 12:18:15.898379 <6>[ 0.553863] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10525 12:18:15.901519 <6>[ 0.561342] ACPI: Interpreter disabled.
10526 12:18:15.909713 <6>[ 0.567772] iommu: Default domain type: Translated
10527 12:18:15.916697 <6>[ 0.572884] iommu: DMA domain TLB invalidation policy: strict mode
10528 12:18:15.920035 <5>[ 0.579546] SCSI subsystem initialized
10529 12:18:15.926164 <6>[ 0.583780] usbcore: registered new interface driver usbfs
10530 12:18:15.933137 <6>[ 0.589513] usbcore: registered new interface driver hub
10531 12:18:15.936064 <6>[ 0.595068] usbcore: registered new device driver usb
10532 12:18:15.942983 <6>[ 0.601175] pps_core: LinuxPPS API ver. 1 registered
10533 12:18:15.952791 <6>[ 0.606370] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10534 12:18:15.956414 <6>[ 0.615713] PTP clock support registered
10535 12:18:15.959651 <6>[ 0.619952] EDAC MC: Ver: 3.0.0
10536 12:18:15.967223 <6>[ 0.625126] FPGA manager framework
10537 12:18:15.973894 <6>[ 0.628800] Advanced Linux Sound Architecture Driver Initialized.
10538 12:18:15.976700 <6>[ 0.635565] vgaarb: loaded
10539 12:18:15.983498 <6>[ 0.638742] clocksource: Switched to clocksource arch_sys_counter
10540 12:18:15.986554 <5>[ 0.645192] VFS: Disk quotas dquot_6.6.0
10541 12:18:15.993325 <6>[ 0.649380] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10542 12:18:15.996212 <6>[ 0.656573] pnp: PnP ACPI: disabled
10543 12:18:16.005551 <6>[ 0.663268] NET: Registered PF_INET protocol family
10544 12:18:16.014853 <6>[ 0.668861] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10545 12:18:16.026148 <6>[ 0.681164] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10546 12:18:16.035782 <6>[ 0.689981] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10547 12:18:16.042797 <6>[ 0.697949] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10548 12:18:16.052709 <6>[ 0.706643] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10549 12:18:16.059495 <6>[ 0.716380] TCP: Hash tables configured (established 65536 bind 65536)
10550 12:18:16.066105 <6>[ 0.723237] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10551 12:18:16.075626 <6>[ 0.730430] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10552 12:18:16.082174 <6>[ 0.738130] NET: Registered PF_UNIX/PF_LOCAL protocol family
10553 12:18:16.088829 <6>[ 0.744289] RPC: Registered named UNIX socket transport module.
10554 12:18:16.092254 <6>[ 0.750444] RPC: Registered udp transport module.
10555 12:18:16.099099 <6>[ 0.755380] RPC: Registered tcp transport module.
10556 12:18:16.105514 <6>[ 0.760310] RPC: Registered tcp NFSv4.1 backchannel transport module.
10557 12:18:16.108453 <6>[ 0.766978] PCI: CLS 0 bytes, default 64
10558 12:18:16.111725 <6>[ 0.771354] Unpacking initramfs...
10559 12:18:16.135751 <6>[ 0.790866] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10560 12:18:16.145913 <6>[ 0.799505] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10561 12:18:16.149050 <6>[ 0.808335] kvm [1]: IPA Size Limit: 40 bits
10562 12:18:16.155846 <6>[ 0.812864] kvm [1]: GICv3: no GICV resource entry
10563 12:18:16.159098 <6>[ 0.817884] kvm [1]: disabling GICv2 emulation
10564 12:18:16.166113 <6>[ 0.822571] kvm [1]: GIC system register CPU interface enabled
10565 12:18:16.168946 <6>[ 0.828734] kvm [1]: vgic interrupt IRQ18
10566 12:18:16.175715 <6>[ 0.833089] kvm [1]: VHE mode initialized successfully
10567 12:18:16.182247 <5>[ 0.839476] Initialise system trusted keyrings
10568 12:18:16.188695 <6>[ 0.844294] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10569 12:18:16.196204 <6>[ 0.854360] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10570 12:18:16.202580 <5>[ 0.860726] NFS: Registering the id_resolver key type
10571 12:18:16.206466 <5>[ 0.866025] Key type id_resolver registered
10572 12:18:16.212798 <5>[ 0.870439] Key type id_legacy registered
10573 12:18:16.219052 <6>[ 0.874713] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10574 12:18:16.226006 <6>[ 0.881635] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10575 12:18:16.232316 <6>[ 0.889349] 9p: Installing v9fs 9p2000 file system support
10576 12:18:16.269045 <5>[ 0.926997] Key type asymmetric registered
10577 12:18:16.272541 <5>[ 0.931332] Asymmetric key parser 'x509' registered
10578 12:18:16.282468 <6>[ 0.936480] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10579 12:18:16.285377 <6>[ 0.944096] io scheduler mq-deadline registered
10580 12:18:16.288390 <6>[ 0.948870] io scheduler kyber registered
10581 12:18:16.308109 <6>[ 0.965689] EINJ: ACPI disabled.
10582 12:18:16.340596 <4>[ 0.991381] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10583 12:18:16.349714 <4>[ 1.002038] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10584 12:18:16.364829 <6>[ 1.022802] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10585 12:18:16.372983 <6>[ 1.030835] printk: console [ttyS0] disabled
10586 12:18:16.401037 <6>[ 1.055485] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10587 12:18:16.407319 <6>[ 1.064948] printk: console [ttyS0] enabled
10588 12:18:16.410678 <6>[ 1.064948] printk: console [ttyS0] enabled
10589 12:18:16.417253 <6>[ 1.073847] printk: bootconsole [mtk8250] disabled
10590 12:18:16.420940 <6>[ 1.073847] printk: bootconsole [mtk8250] disabled
10591 12:18:16.427181 <6>[ 1.085093] SuperH (H)SCI(F) driver initialized
10592 12:18:16.430260 <6>[ 1.090366] msm_serial: driver initialized
10593 12:18:16.444699 <6>[ 1.099201] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10594 12:18:16.454704 <6>[ 1.107747] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10595 12:18:16.461078 <6>[ 1.116291] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10596 12:18:16.470548 <6>[ 1.124920] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10597 12:18:16.481025 <6>[ 1.133631] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10598 12:18:16.487252 <6>[ 1.142344] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10599 12:18:16.497124 <6>[ 1.150884] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10600 12:18:16.503969 <6>[ 1.159696] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10601 12:18:16.513011 <6>[ 1.168242] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10602 12:18:16.525091 <6>[ 1.183503] loop: module loaded
10603 12:18:16.532029 <6>[ 1.189573] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10604 12:18:16.554591 <4>[ 1.212877] mtk-pmic-keys: Failed to locate of_node [id: -1]
10605 12:18:16.561015 <6>[ 1.219634] megasas: 07.719.03.00-rc1
10606 12:18:16.570609 <6>[ 1.229138] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10607 12:18:16.579859 <6>[ 1.238126] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10608 12:18:16.596809 <6>[ 1.254844] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10609 12:18:16.657250 <6>[ 1.308973] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10610 12:18:16.892681 <6>[ 1.550927] Freeing initrd memory: 18164K
10611 12:18:16.904336 <6>[ 1.562602] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10612 12:18:16.915528 <6>[ 1.573457] tun: Universal TUN/TAP device driver, 1.6
10613 12:18:16.918695 <6>[ 1.579507] thunder_xcv, ver 1.0
10614 12:18:16.921759 <6>[ 1.583013] thunder_bgx, ver 1.0
10615 12:18:16.924779 <6>[ 1.586501] nicpf, ver 1.0
10616 12:18:16.936099 <6>[ 1.590511] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10617 12:18:16.939231 <6>[ 1.597987] hns3: Copyright (c) 2017 Huawei Corporation.
10618 12:18:16.945681 <6>[ 1.603573] hclge is initializing
10619 12:18:16.949081 <6>[ 1.607155] e1000: Intel(R) PRO/1000 Network Driver
10620 12:18:16.955900 <6>[ 1.612283] e1000: Copyright (c) 1999-2006 Intel Corporation.
10621 12:18:16.959368 <6>[ 1.618297] e1000e: Intel(R) PRO/1000 Network Driver
10622 12:18:16.965753 <6>[ 1.623513] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10623 12:18:16.972482 <6>[ 1.629699] igb: Intel(R) Gigabit Ethernet Network Driver
10624 12:18:16.978896 <6>[ 1.635348] igb: Copyright (c) 2007-2014 Intel Corporation.
10625 12:18:16.985744 <6>[ 1.641185] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10626 12:18:16.991863 <6>[ 1.647707] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10627 12:18:16.995539 <6>[ 1.654166] sky2: driver version 1.30
10628 12:18:17.001820 <6>[ 1.659152] VFIO - User Level meta-driver version: 0.3
10629 12:18:17.009183 <6>[ 1.667381] usbcore: registered new interface driver usb-storage
10630 12:18:17.016165 <6>[ 1.673823] usbcore: registered new device driver onboard-usb-hub
10631 12:18:17.024910 <6>[ 1.682919] mt6397-rtc mt6359-rtc: registered as rtc0
10632 12:18:17.034687 <6>[ 1.688382] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:18:17 UTC (1686053897)
10633 12:18:17.037850 <6>[ 1.697939] i2c_dev: i2c /dev entries driver
10634 12:18:17.054697 <6>[ 1.709545] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10635 12:18:17.061340 <6>[ 1.719553] sdhci: Secure Digital Host Controller Interface driver
10636 12:18:17.068249 <6>[ 1.725991] sdhci: Copyright(c) Pierre Ossman
10637 12:18:17.074096 <6>[ 1.731393] Synopsys Designware Multimedia Card Interface Driver
10638 12:18:17.077808 <6>[ 1.737991] mmc0: CQHCI version 5.10
10639 12:18:17.084066 <6>[ 1.738540] sdhci-pltfm: SDHCI platform and OF driver helper
10640 12:18:17.091499 <6>[ 1.749928] ledtrig-cpu: registered to indicate activity on CPUs
10641 12:18:17.101949 <6>[ 1.757243] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10642 12:18:17.108466 <6>[ 1.764642] usbcore: registered new interface driver usbhid
10643 12:18:17.112190 <6>[ 1.770474] usbhid: USB HID core driver
10644 12:18:17.118669 <6>[ 1.774725] spi_master spi0: will run message pump with realtime priority
10645 12:18:17.165592 <6>[ 1.817328] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10646 12:18:17.184750 <6>[ 1.832874] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10647 12:18:17.187931 <6>[ 1.846447] mmc0: Command Queue Engine enabled
10648 12:18:17.195131 <6>[ 1.851233] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10649 12:18:17.201678 <6>[ 1.858490] mmcblk0: mmc0:0001 DA4128 116 GiB
10650 12:18:17.204724 <6>[ 1.863442] cros-ec-spi spi0.0: Chrome EC device registered
10651 12:18:17.211466 <6>[ 1.868020] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10652 12:18:17.218859 <6>[ 1.876851] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10653 12:18:17.226034 <6>[ 1.882972] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10654 12:18:17.232132 <6>[ 1.888986] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10655 12:18:17.253124 <6>[ 1.907769] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10656 12:18:17.261260 <6>[ 1.919195] NET: Registered PF_PACKET protocol family
10657 12:18:17.264491 <6>[ 1.924629] 9pnet: Installing 9P2000 support
10658 12:18:17.271114 <5>[ 1.929206] Key type dns_resolver registered
10659 12:18:17.274602 <6>[ 1.934247] registered taskstats version 1
10660 12:18:17.280780 <5>[ 1.938645] Loading compiled-in X.509 certificates
10661 12:18:17.314275 <4>[ 1.966245] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10662 12:18:17.324210 <4>[ 1.976947] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10663 12:18:17.334859 <3>[ 1.989887] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10664 12:18:17.347359 <6>[ 2.005826] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10665 12:18:17.354329 <6>[ 2.012594] xhci-mtk 11200000.usb: xHCI Host Controller
10666 12:18:17.360507 <6>[ 2.018106] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10667 12:18:17.370568 <6>[ 2.025971] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10668 12:18:17.377110 <6>[ 2.035419] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10669 12:18:17.383794 <6>[ 2.041644] xhci-mtk 11200000.usb: xHCI Host Controller
10670 12:18:17.390738 <6>[ 2.047142] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10671 12:18:17.397348 <6>[ 2.054799] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10672 12:18:17.404282 <6>[ 2.062680] hub 1-0:1.0: USB hub found
10673 12:18:17.407392 <6>[ 2.066736] hub 1-0:1.0: 1 port detected
10674 12:18:17.416965 <6>[ 2.071093] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10675 12:18:17.420624 <6>[ 2.079894] hub 2-0:1.0: USB hub found
10676 12:18:17.423728 <6>[ 2.083944] hub 2-0:1.0: 1 port detected
10677 12:18:17.432333 <6>[ 2.091141] mtk-msdc 11f70000.mmc: Got CD GPIO
10678 12:18:17.449517 <6>[ 2.104728] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10679 12:18:17.455730 <6>[ 2.112770] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10680 12:18:17.465844 <4>[ 2.120739] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10681 12:18:17.475874 <6>[ 2.130400] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10682 12:18:17.482634 <6>[ 2.138481] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10683 12:18:17.488898 <6>[ 2.146503] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10684 12:18:17.499382 <6>[ 2.154417] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10685 12:18:17.505967 <6>[ 2.162244] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10686 12:18:17.515789 <6>[ 2.170071] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10687 12:18:17.525754 <6>[ 2.180680] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10688 12:18:17.531858 <6>[ 2.189080] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10689 12:18:17.542155 <6>[ 2.197434] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10690 12:18:17.551972 <6>[ 2.205779] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10691 12:18:17.558779 <6>[ 2.214123] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10692 12:18:17.568737 <6>[ 2.222466] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10693 12:18:17.575093 <6>[ 2.230811] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10694 12:18:17.585554 <6>[ 2.239155] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10695 12:18:17.591697 <6>[ 2.247502] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10696 12:18:17.601655 <6>[ 2.255847] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10697 12:18:17.608353 <6>[ 2.264190] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10698 12:18:17.618929 <6>[ 2.272534] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10699 12:18:17.624960 <6>[ 2.280877] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10700 12:18:17.635628 <6>[ 2.289220] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10701 12:18:17.641859 <6>[ 2.297566] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10702 12:18:17.648506 <6>[ 2.306556] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10703 12:18:17.655572 <6>[ 2.314102] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10704 12:18:17.662698 <6>[ 2.321197] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10705 12:18:17.673513 <6>[ 2.328337] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10706 12:18:17.679788 <6>[ 2.335637] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10707 12:18:17.689711 <6>[ 2.342549] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10708 12:18:17.696461 <6>[ 2.351690] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10709 12:18:17.706150 <6>[ 2.360817] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10710 12:18:17.715941 <6>[ 2.370119] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10711 12:18:17.726201 <6>[ 2.379597] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10712 12:18:17.736134 <6>[ 2.389072] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10713 12:18:17.745995 <6>[ 2.398199] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10714 12:18:17.752639 <6>[ 2.407673] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10715 12:18:17.762498 <6>[ 2.416805] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10716 12:18:17.772561 <6>[ 2.426108] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10717 12:18:17.781710 <6>[ 2.436274] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10718 12:18:17.792677 <6>[ 2.448218] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10719 12:18:17.799757 <6>[ 2.458156] Trying to probe devices needed for running init ...
10720 12:18:17.815436 <6>[ 2.471050] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10721 12:18:17.843374 <6>[ 2.501675] hub 2-1:1.0: USB hub found
10722 12:18:17.846784 <6>[ 2.506103] hub 2-1:1.0: 3 ports detected
10723 12:18:17.968100 <6>[ 2.622922] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10724 12:18:18.122514 <6>[ 2.780523] hub 1-1:1.0: USB hub found
10725 12:18:18.125637 <6>[ 2.784943] hub 1-1:1.0: 4 ports detected
10726 12:18:18.447753 <6>[ 3.103020] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10727 12:18:18.578768 <6>[ 3.236869] hub 1-1.1:1.0: USB hub found
10728 12:18:18.581812 <6>[ 3.241149] hub 1-1.1:1.0: 4 ports detected
10729 12:18:18.696352 <6>[ 3.350796] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10730 12:18:18.828318 <6>[ 3.487295] hub 1-1.4:1.0: USB hub found
10731 12:18:18.831702 <6>[ 3.491944] hub 1-1.4:1.0: 2 ports detected
10732 12:18:18.907497 <6>[ 3.563024] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10733 12:18:19.095719 <6>[ 3.751012] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10734 12:18:19.181011 <3>[ 3.839233] usb 1-1.1.4: device descriptor read/64, error -32
10735 12:18:19.372557 <3>[ 4.031176] usb 1-1.1.4: device descriptor read/64, error -32
10736 12:18:19.567411 <6>[ 4.223015] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10737 12:18:19.755882 <6>[ 4.411019] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10738 12:18:19.840615 <3>[ 4.499226] usb 1-1.1.4: device descriptor read/64, error -32
10739 12:18:20.032621 <3>[ 4.691241] usb 1-1.1.4: device descriptor read/64, error -32
10740 12:18:20.145159 <6>[ 4.803596] usb 1-1.1-port4: attempt power cycle
10741 12:18:20.231784 <6>[ 4.887043] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10742 12:18:20.755974 <6>[ 5.411013] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10743 12:18:20.762030 <4>[ 5.418466] usb 1-1.1.4: Device not responding to setup address.
10744 12:18:20.972490 <4>[ 5.631099] usb 1-1.1.4: Device not responding to setup address.
10745 12:18:21.184077 <3>[ 5.843006] usb 1-1.1.4: device not accepting address 10, error -71
10746 12:18:21.271516 <6>[ 5.927013] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10747 12:18:21.278269 <4>[ 5.934466] usb 1-1.1.4: Device not responding to setup address.
10748 12:18:21.488378 <4>[ 6.147284] usb 1-1.1.4: Device not responding to setup address.
10749 12:18:21.700340 <3>[ 6.359007] usb 1-1.1.4: device not accepting address 11, error -71
10750 12:18:21.707431 <3>[ 6.365955] usb 1-1.1-port4: unable to enumerate USB device
10751 12:18:30.100474 <6>[ 14.763576] ALSA device list:
10752 12:18:30.107134 <6>[ 14.766831] No soundcards found.
10753 12:18:30.119400 <6>[ 14.779250] Freeing unused kernel memory: 8384K
10754 12:18:30.122684 <6>[ 14.784184] Run /init as init process
10755 12:18:30.133211 Loading, please wait...
10756 12:18:30.162097 Starting systemd-udevd version 252.6-1
10757 12:18:30.574121 <6>[ 15.231083] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10758 12:18:30.585432 <6>[ 15.245249] remoteproc remoteproc0: scp is available
10759 12:18:30.595635 <4>[ 15.250984] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10760 12:18:30.601988 <6>[ 15.261024] remoteproc remoteproc0: powering up scp
10761 12:18:30.611612 <4>[ 15.266214] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10762 12:18:30.618324 <3>[ 15.276054] remoteproc remoteproc0: request_firmware failed: -2
10763 12:18:30.624566 <6>[ 15.277753] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10764 12:18:30.634677 <6>[ 15.289985] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10765 12:18:30.641334 <6>[ 15.290272] usbcore: registered new interface driver r8152
10766 12:18:30.647529 <6>[ 15.298706] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10767 12:18:30.654399 <6>[ 15.307041] mc: Linux media interface: v0.10
10768 12:18:30.660792 <6>[ 15.309537] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10769 12:18:30.667577 <3>[ 15.325688] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10770 12:18:30.678822 <3>[ 15.334861] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 12:18:30.685024 <6>[ 15.337244] usbcore: registered new interface driver cdc_ether
10772 12:18:30.691868 <4>[ 15.337527] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10773 12:18:30.698273 <4>[ 15.337664] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10774 12:18:30.709073 <3>[ 15.343012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10775 12:18:30.715411 <4>[ 15.347119] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10776 12:18:30.722114 <4>[ 15.347119] Fallback method does not support PEC.
10777 12:18:30.728413 <3>[ 15.366831] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10778 12:18:30.735537 <6>[ 15.378777] Bluetooth: Core ver 2.22
10779 12:18:30.741362 <3>[ 15.389784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10780 12:18:30.749027 <6>[ 15.390644] videodev: Linux video capture interface: v2.00
10781 12:18:30.752050 <6>[ 15.394365] NET: Registered PF_BLUETOOTH protocol family
10782 12:18:30.758783 <6>[ 15.394533] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10783 12:18:30.768982 <3>[ 15.399199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 12:18:30.775353 <6>[ 15.406297] Bluetooth: HCI device and connection manager initialized
10785 12:18:30.778948 <6>[ 15.406318] Bluetooth: HCI socket layer initialized
10786 12:18:30.788646 <3>[ 15.412172] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10787 12:18:30.795145 <6>[ 15.417609] Bluetooth: L2CAP socket layer initialized
10788 12:18:30.798787 <6>[ 15.417630] Bluetooth: SCO socket layer initialized
10789 12:18:30.808105 <3>[ 15.417672] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10790 12:18:30.815508 <3>[ 15.425484] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10791 12:18:30.821451 <6>[ 15.432251] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10792 12:18:30.828169 <6>[ 15.432259] pci_bus 0000:00: root bus resource [bus 00-ff]
10793 12:18:30.835124 <6>[ 15.432266] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10794 12:18:30.844410 <6>[ 15.432272] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10795 12:18:30.851329 <6>[ 15.432312] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10796 12:18:30.858151 <6>[ 15.432334] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10797 12:18:30.864267 <6>[ 15.432422] pci 0000:00:00.0: supports D1 D2
10798 12:18:30.870968 <6>[ 15.432426] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10799 12:18:30.877730 <6>[ 15.434332] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10800 12:18:30.887438 <3>[ 15.439691] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10801 12:18:30.894100 <3>[ 15.439761] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10802 12:18:30.900580 <6>[ 15.445004] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10803 12:18:30.910926 <6>[ 15.448027] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10804 12:18:30.920608 <6>[ 15.448484] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10805 12:18:30.930661 <6>[ 15.452357] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10806 12:18:30.937230 <3>[ 15.454359] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10807 12:18:30.943410 <6>[ 15.458282] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10808 12:18:30.950422 <6>[ 15.458588] usbcore: registered new interface driver r8153_ecm
10809 12:18:30.960478 <3>[ 15.463728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10810 12:18:30.966738 <6>[ 15.472451] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10811 12:18:30.973718 <3>[ 15.480449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10812 12:18:30.983566 <6>[ 15.487450] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10813 12:18:30.989905 <3>[ 15.493324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10814 12:18:30.996595 <6>[ 15.494674] usbcore: registered new interface driver btusb
10815 12:18:31.006222 <4>[ 15.495132] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10816 12:18:31.013040 <3>[ 15.495143] Bluetooth: hci0: Failed to load firmware file (-2)
10817 12:18:31.019531 <3>[ 15.495147] Bluetooth: hci0: Failed to set up firmware (-2)
10818 12:18:31.029631 <4>[ 15.495152] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10819 12:18:31.033192 <6>[ 15.500441] pci 0000:01:00.0: supports D1 D2
10820 12:18:31.042728 <3>[ 15.510229] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10821 12:18:31.049857 <6>[ 15.511080] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10822 12:18:31.062721 <6>[ 15.513062] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10823 12:18:31.065716 <6>[ 15.513198] usbcore: registered new interface driver uvcvideo
10824 12:18:31.075813 <4>[ 15.515255] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10825 12:18:31.085762 <4>[ 15.515264] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10826 12:18:31.092232 <6>[ 15.516498] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10827 12:18:31.098931 <3>[ 15.523984] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10828 12:18:31.105610 <6>[ 15.524771] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10829 12:18:31.111953 <6>[ 15.538945] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10830 12:18:31.122440 <3>[ 15.543624] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10831 12:18:31.129104 <6>[ 15.551725] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10832 12:18:31.138399 <3>[ 15.559778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10833 12:18:31.145272 <6>[ 15.566035] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10834 12:18:31.148396 <6>[ 15.574962] r8152 1-1.1.1:1.0 eth0: v1.12.13
10835 12:18:31.158231 <3>[ 15.576146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10836 12:18:31.165225 <6>[ 15.584955] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10837 12:18:31.171483 <6>[ 15.585150] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10838 12:18:31.181678 <6>[ 15.836724] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10839 12:18:31.188481 <6>[ 15.844734] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10840 12:18:31.194816 <6>[ 15.852744] pci 0000:00:00.0: PCI bridge to [bus 01]
10841 12:18:31.201552 <6>[ 15.857965] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10842 12:18:31.208125 <6>[ 15.866126] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10843 12:18:31.214372 <6>[ 15.873387] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10844 12:18:31.221188 <6>[ 15.880243] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10845 12:18:31.239436 <5>[ 15.896157] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10846 12:18:31.261822 <5>[ 15.917828] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10847 12:18:31.267870 <4>[ 15.924760] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10848 12:18:31.274517 <6>[ 15.933655] cfg80211: failed to load regulatory.db
10849 12:18:31.318557 <6>[ 15.975051] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10850 12:18:31.324877 <6>[ 15.982582] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10851 12:18:31.349492 <6>[ 16.009290] mt7921e 0000:01:00.0: ASIC revision: 79610010
10852 12:18:31.457078 <4>[ 16.110462] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10853 12:18:31.469819 Begin: Loading essential drivers ... done.
10854 12:18:31.472862 Begin: Running /scripts/init-premount ... done.
10855 12:18:31.482624 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10856 12:18:31.489541 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10857 12:18:31.492618 Device /sys/class/net/enxf4f5e850de0a found
10858 12:18:31.495887 done.
10859 12:18:31.522954 Begin: Waiting up to 180 secs for any network device to become available ... done.
10860 12:18:31.576324 <4>[ 16.229344] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10861 12:18:31.583046 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10862 12:18:31.695264 <4>[ 16.348694] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10863 12:18:31.811255 <4>[ 16.464557] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10864 12:18:31.927688 <4>[ 16.580418] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10865 12:18:32.043443 <4>[ 16.696382] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10866 12:18:32.159178 <4>[ 16.812295] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10867 12:18:32.275023 <4>[ 16.928339] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10868 12:18:32.390634 <4>[ 17.044319] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10869 12:18:32.506337 <4>[ 17.160156] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10870 12:18:32.614054 <3>[ 17.274131] mt7921e 0000:01:00.0: hardware init failed
10871 12:18:32.703684 <6>[ 17.363436] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10872 12:18:33.528399 IP-Config: no response after 2 secs - giving up
10873 12:18:33.558371 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10874 12:18:33.561693 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10875 12:18:33.567887 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10876 12:18:33.578403 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10877 12:18:33.584402 host : mt8192-asurada-spherion-r0-cbg-9
10878 12:18:33.591199 domain : lava-rack
10879 12:18:33.594451 rootserver: 192.168.201.1 rootpath:
10880 12:18:33.594888 filename :
10881 12:18:33.645576 done.
10882 12:18:33.652392 Begin: Running /scripts/nfs-bottom ... done.
10883 12:18:33.673164 Begin: Running /scripts/init-bottom ... done.
10884 12:18:34.888100 <6>[ 19.548313] NET: Registered PF_INET6 protocol family
10885 12:18:34.894733 <6>[ 19.555114] Segment Routing with IPv6
10886 12:18:34.898412 <6>[ 19.559083] In-situ OAM (IOAM) with IPv6
10887 12:18:35.067264 <30>[ 19.701106] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10888 12:18:35.073545 <30>[ 19.733365] systemd[1]: Detected architecture arm64.
10889 12:18:35.081094
10890 12:18:35.084096 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10891 12:18:35.084235
10892 12:18:35.107534 <30>[ 19.768181] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10893 12:18:35.757176 <30>[ 20.414475] systemd[1]: Queued start job for default target graphical.target.
10894 12:18:35.804183 <30>[ 20.461174] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10895 12:18:35.810533 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10896 12:18:35.830841 <30>[ 20.487856] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10897 12:18:35.840482 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10898 12:18:35.859293 <30>[ 20.516458] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10899 12:18:35.869105 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10900 12:18:35.886443 <30>[ 20.543647] systemd[1]: Created slice user.slice - User and Session Slice.
10901 12:18:35.893312 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10902 12:18:35.913429 <30>[ 20.567263] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10903 12:18:35.920265 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10904 12:18:35.941722 <30>[ 20.595157] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10905 12:18:35.948068 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10906 12:18:35.976432 <30>[ 20.623471] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10907 12:18:35.986209 <30>[ 20.643320] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10908 12:18:35.993153 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10909 12:18:36.010249 <30>[ 20.667354] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10910 12:18:36.020125 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10911 12:18:36.035460 <30>[ 20.695392] systemd[1]: Reached target paths.target - Path Units.
10912 12:18:36.041672 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10913 12:18:36.062654 <30>[ 20.719336] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10914 12:18:36.068811 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10915 12:18:36.082882 <30>[ 20.743094] systemd[1]: Reached target slices.target - Slice Units.
10916 12:18:36.092964 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10917 12:18:36.107697 <30>[ 20.767376] systemd[1]: Reached target swap.target - Swaps.
10918 12:18:36.114023 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10919 12:18:36.134267 <30>[ 20.791118] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10920 12:18:36.143863 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10921 12:18:36.162097 <30>[ 20.819320] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10922 12:18:36.171808 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10923 12:18:36.191939 <30>[ 20.848835] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10924 12:18:36.201867 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10925 12:18:36.219247 <30>[ 20.876237] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10926 12:18:36.228847 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10927 12:18:36.246657 <30>[ 20.903406] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10928 12:18:36.253214 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10929 12:18:36.270952 <30>[ 20.928281] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10930 12:18:36.280768 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10931 12:18:36.300126 <30>[ 20.957372] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10932 12:18:36.310167 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10933 12:18:36.326549 <30>[ 20.983323] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10934 12:18:36.335888 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10935 12:18:36.370428 <30>[ 21.027492] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10936 12:18:36.376987 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10937 12:18:36.396263 <30>[ 21.053579] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10938 12:18:36.402636 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10939 12:18:36.424736 <30>[ 21.081725] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10940 12:18:36.431071 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10941 12:18:36.456762 <30>[ 21.107348] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10942 12:18:36.469532 <30>[ 21.126390] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10943 12:18:36.479108 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10944 12:18:36.501376 <30>[ 21.158155] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10945 12:18:36.507206 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10946 12:18:36.528752 <30>[ 21.186043] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10947 12:18:36.535480 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10948 12:18:36.557566 <30>[ 21.214689] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10949 12:18:36.567466 Startin<6>[ 21.223995] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10950 12:18:36.574039 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10951 12:18:36.592892 <30>[ 21.250185] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10952 12:18:36.602965 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10953 12:18:36.620717 <30>[ 21.278020] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10954 12:18:36.627103 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10955 12:18:36.648968 <30>[ 21.306240] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10956 12:18:36.655714 Startin<6>[ 21.315337] fuse: init (API version 7.37)
10957 12:18:36.658765 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10958 12:18:36.683747 <30>[ 21.340466] systemd[1]: Starting systemd-journald.service - Journal Service...
10959 12:18:36.690070 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10960 12:18:36.714356 <30>[ 21.371302] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10961 12:18:36.720644 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10962 12:18:36.765813 <30>[ 21.419790] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10963 12:18:36.772497 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10964 12:18:36.793312 <30>[ 21.450246] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10965 12:18:36.803060 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10966 12:18:36.825261 <30>[ 21.482473] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10967 12:18:36.832094 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10968 12:18:36.842267 <3>[ 21.499333] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 12:18:36.855389 <30>[ 21.512371] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10970 12:18:36.862286 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10971 12:18:36.873358 <3>[ 21.530224] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 12:18:36.883247 <30>[ 21.539756] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10973 12:18:36.889406 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10974 12:18:36.910967 <30>[ 21.567429] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10975 12:18:36.921157 [[0;32m OK [0m] Mounted [0;<3>[ 21.577024] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 12:18:36.927372 1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10977 12:18:36.946779 <30>[ 21.603872] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10978 12:18:36.956823 <3>[ 21.608136] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 12:18:36.963265 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10980 12:18:36.983208 <30>[ 21.640183] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10981 12:18:36.989991 <3>[ 21.641844] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 12:18:36.999675 <30>[ 21.648018] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10983 12:18:37.006156 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10984 12:18:37.023358 <3>[ 21.680626] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 12:18:37.033301 <30>[ 21.690689] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10986 12:18:37.040310 <30>[ 21.698406] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10987 12:18:37.050447 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10988 12:18:37.060543 <3>[ 21.717208] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 12:18:37.070286 <30>[ 21.727348] systemd[1]: modprobe@drm.service: Deactivated successfully.
10990 12:18:37.076794 <30>[ 21.734724] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10991 12:18:37.083792 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10992 12:18:37.094230 <3>[ 21.751318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10993 12:18:37.104162 <30>[ 21.761332] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10994 12:18:37.114474 <30>[ 21.769343] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10995 12:18:37.127884 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module<3>[ 21.784516] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 12:18:37.130870 efi_pstore.
10997 12:18:37.146964 <30>[ 21.803982] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10998 12:18:37.153727 <30>[ 21.811536] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10999 12:18:37.163649 [[0;32m OK [<3>[ 21.820505] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 12:18:37.170505 0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11001 12:18:37.191192 <30>[ 21.848356] systemd[1]: modprobe@loop.service: Deactivated successfully.
11002 12:18:37.198007 <30>[ 21.855936] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11003 12:18:37.207710 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11004 12:18:37.226556 <30>[ 21.883584] systemd[1]: Started systemd-journald.service - Journal Service.
11005 12:18:37.232827 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11006 12:18:37.252388 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11007 12:18:37.271095 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11008 12:18:37.291134 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11009 12:18:37.311723 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11010 12:18:37.358796 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11011 12:18:37.385448 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11012 12:18:37.410277 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11013 12:18:37.430090 <4>[ 22.080786] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11014 12:18:37.439875 <3>[ 22.096476] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11015 12:18:37.446765 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11016 12:18:37.473986 <46>[ 22.131104] systemd-journald[299]: Received client request to flush runtime journal.
11017 12:18:37.480719 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11018 12:18:37.504563 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11019 12:18:37.525399 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11020 12:18:37.542690 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11021 12:18:37.558574 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11022 12:18:37.574431 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11023 12:18:38.247726 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11024 12:18:38.851585 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11025 12:18:38.870602 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11026 12:18:38.910628 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11027 12:18:38.981978 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11028 12:18:38.998484 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11029 12:18:39.013565 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11030 12:18:39.062078 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
11031 12:18:39.084752 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11032 12:18:39.107735 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11033 12:18:39.131303 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
11034 12:18:39.146738 See 'systemctl status systemd-binfmt.service' for details.
11035 12:18:39.347446 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11036 12:18:39.411240 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11037 12:18:39.436357 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11038 12:18:39.575458 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11039 12:18:39.610643 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11040 12:18:39.639415 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11041 12:18:39.807883 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11042 12:18:39.872421 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11043 12:18:39.918889 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11044 12:18:39.969855 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11045 12:18:39.976896 <6>[ 24.637197] remoteproc remoteproc0: powering up scp
11046 12:18:39.995859 <4>[ 24.653665] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11047 12:18:40.003289 <3>[ 24.664314] remoteproc remoteproc0: request_firmware failed: -2
11048 12:18:40.014591 [[0;32m OK [<3>[ 24.672805] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11049 12:18:40.020857 0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11050 12:18:40.042285 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11051 12:18:40.048730 <46>[ 24.709476] systemd-journald[299]: Time jumped backwards, rotating.
11052 12:18:40.062653 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11053 12:18:40.104378 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11054 12:18:40.129729 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11055 12:18:40.145799 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11056 12:18:40.162039 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11057 12:18:40.834429 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11058 12:18:41.163650 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11059 12:18:41.181380 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11060 12:18:41.523602 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11061 12:18:41.544113 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11062 12:18:41.561394 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11063 12:18:41.824895 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11064 12:18:41.845313 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11065 12:18:41.861434 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11066 12:18:41.876992 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11067 12:18:41.938403 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11068 12:18:41.968191 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11069 12:18:42.033774 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11070 12:18:42.057036 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11071 12:18:42.082124 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11072 12:18:42.234943 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11073 12:18:42.277697 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11074 12:18:42.325954 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11075 12:18:42.349954 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11076 12:18:42.366330 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11077 12:18:42.389996 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11078 12:18:42.417001 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11079 12:18:42.436075 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11080 12:18:42.460413 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11081 12:18:42.481528 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11082 12:18:42.535170 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11083 12:18:42.553835 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11084 12:18:42.624826 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11085 12:18:42.677558 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11086 12:18:42.737156
11087 12:18:42.737640
11088 12:18:42.740921 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11089 12:18:42.741354
11090 12:18:42.743801 debian-bookworm-arm64 login: root (automatic login)
11091 12:18:42.744266
11092 12:18:42.744756
11093 12:18:42.981603 Linux debian-bookworm-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023 aarch64
11094 12:18:42.981751
11095 12:18:42.988163 The programs included with the Debian GNU/Linux system are free software;
11096 12:18:42.994534 the exact distribution terms for each program are described in the
11097 12:18:42.997969 individual files in /usr/share/doc/*/copyright.
11098 12:18:42.998053
11099 12:18:43.004304 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11100 12:18:43.007757 permitted by applicable law.
11101 12:18:43.904410 Matched prompt #10: / #
11103 12:18:43.904762 Setting prompt string to ['/ #']
11104 12:18:43.904879 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11106 12:18:43.905122 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11107 12:18:43.905228 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
11108 12:18:43.905315 Setting prompt string to ['/ #']
11109 12:18:43.905391 Forcing a shell prompt, looking for ['/ #']
11111 12:18:43.955737 / #
11112 12:18:43.956418 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11113 12:18:43.956955 Waiting using forced prompt support (timeout 00:02:30)
11114 12:18:43.961463
11115 12:18:43.962291 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11116 12:18:43.962821 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
11118 12:18:44.064062 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605447/extract-nfsrootfs-apxzj0_7'
11119 12:18:44.069947 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605447/extract-nfsrootfs-apxzj0_7'
11121 12:18:44.171484 / # export NFS_SERVER_IP='192.168.201.1'
11122 12:18:44.178070 export NFS_SERVER_IP='192.168.201.1'
11123 12:18:44.178843 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11124 12:18:44.179354 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11125 12:18:44.179816 end: 2 depthcharge-action (duration 00:01:24) [common]
11126 12:18:44.180272 start: 3 lava-test-retry (timeout 00:07:53) [common]
11127 12:18:44.180743 start: 3.1 lava-test-shell (timeout 00:07:53) [common]
11128 12:18:44.181136 Using namespace: common
11130 12:18:44.282185 / # #
11131 12:18:44.282745 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11132 12:18:44.288246 #
11133 12:18:44.289016 Using /lava-10605447
11135 12:18:44.390234 / # export SHELL=/bin/bash
11136 12:18:44.396566 export SHELL=/bin/bash
11138 12:18:44.498171 / # . /lava-10605447/environment
11139 12:18:44.504063 . /lava-10605447/environment
11141 12:18:44.609540 / # /lava-10605447/bin/lava-test-runner /lava-10605447/0
11142 12:18:44.610154 Test shell timeout: 10s (minimum of the action and connection timeout)
11143 12:18:44.615597 /lava-10605447/bin/lava-test-runner /lava-10605447/0
11144 12:18:44.820173 + export TESTRUN_ID=0_timesync-off
11145 12:18:44.823119 + TESTRUN_ID=0_timesync-off
11146 12:18:44.826285 + cd /lava-10605447/0/tests/0_timesync-off
11147 12:18:44.830178 ++ cat uuid
11148 12:18:44.830282 + UUID=10605447_1.6.2.3.1
11149 12:18:44.833213 + set +x
11150 12:18:44.836360 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10605447_1.6.2.3.1>
11151 12:18:44.836728 Received signal: <STARTRUN> 0_timesync-off 10605447_1.6.2.3.1
11152 12:18:44.836843 Starting test lava.0_timesync-off (10605447_1.6.2.3.1)
11153 12:18:44.836982 Skipping test definition patterns.
11154 12:18:44.840037 + systemctl stop systemd-timesyncd
11155 12:18:44.873802 + set +x
11156 12:18:44.876803 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10605447_1.6.2.3.1>
11157 12:18:44.877479 Received signal: <ENDRUN> 0_timesync-off 10605447_1.6.2.3.1
11158 12:18:44.877897 Ending use of test pattern.
11159 12:18:44.878215 Ending test lava.0_timesync-off (10605447_1.6.2.3.1), duration 0.04
11161 12:18:44.938712 + export TESTRUN_ID=1_kselftest-alsa
11162 12:18:44.941836 + TESTRUN_ID=1_kselftest-alsa
11163 12:18:44.948513 + cd /lava-10605447/0/tests/1_kselftest-alsa
11164 12:18:44.948635 ++ cat uuid
11165 12:18:44.951545 + UUID=10605447_1.6.2.3.5
11166 12:18:44.951629 + set +x
11167 12:18:44.955201 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 10605447_1.6.2.3.5>
11168 12:18:44.955456 Received signal: <STARTRUN> 1_kselftest-alsa 10605447_1.6.2.3.5
11169 12:18:44.955530 Starting test lava.1_kselftest-alsa (10605447_1.6.2.3.5)
11170 12:18:44.955610 Skipping test definition patterns.
11171 12:18:44.958502 + cd ./automated/linux/kselftest/
11172 12:18:44.988304 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11173 12:18:45.004808 INFO: install_deps skipped
11174 12:18:45.466569 --2023-06-06 12:18:45-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11175 12:18:45.473737 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11176 12:18:45.604310 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11177 12:18:45.745804 HTTP request sent, awaiting response... 200 OK
11178 12:18:45.748592 Length: 2704052 (2.6M) [application/octet-stream]
11179 12:18:45.752320 Saving to: 'kselftest.tar.xz'
11180 12:18:45.752404
11181 12:18:45.752469
11182 12:18:46.028736 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11183 12:18:46.314065 kselftest.tar.xz 1%[ ] 46.39K 165KB/s
11184 12:18:46.642685 kselftest.tar.xz 8%[> ] 217.50K 384KB/s
11185 12:18:46.932690 kselftest.tar.xz 29%[====> ] 770.39K 860KB/s
11186 12:18:47.069130 kselftest.tar.xz 68%[============> ] 1.77M 1.50MB/s
11187 12:18:47.075377 kselftest.tar.xz 100%[===================>] 2.58M 1.95MB/s in 1.3s
11188 12:18:47.075464
11189 12:18:47.309727 2023-06-06 12:18:47 (1.95 MB/s) - 'kselftest.tar.xz' saved [2704052/2704052]
11190 12:18:47.309876
11191 12:18:52.076998 skiplist:
11192 12:18:52.080646 ========================================
11193 12:18:52.083487 ========================================
11194 12:18:52.125683 alsa:mixer-test
11195 12:18:52.145682 ============== Tests to run ===============
11196 12:18:52.146330 alsa:mixer-test
11197 12:18:52.148809 ===========End Tests to run ===============
11198 12:18:52.245218 <12>[ 36.907503] kselftest: Running tests in alsa
11199 12:18:52.253948 TAP version 13
11200 12:18:52.268608 1..1
11201 12:18:52.282499 # selftests: alsa: mixer-test
11202 12:18:52.707210 # TAP version 13
11203 12:18:52.707378 # 1..0
11204 12:18:52.713775 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11205 12:18:52.716492 ok 1 selftests: alsa: mixer-test
11206 12:18:53.325419 alsa_mixer-test pass
11207 12:18:53.357257 + ../../utils/send-to-lava.sh ./output/result.txt
11208 12:18:53.406231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11209 12:18:53.406360 + set +x
11210 12:18:53.406607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11212 12:18:53.413331 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 10605447_1.6.2.3.5>
11213 12:18:53.413692 Received signal: <ENDRUN> 1_kselftest-alsa 10605447_1.6.2.3.5
11214 12:18:53.413800 Ending use of test pattern.
11215 12:18:53.413882 Ending test lava.1_kselftest-alsa (10605447_1.6.2.3.5), duration 8.46
11217 12:18:53.416475 <LAVA_TEST_RUNNER EXIT>
11218 12:18:53.416767 ok: lava_test_shell seems to have completed
11219 12:18:53.416901 alsa_mixer-test: pass
11220 12:18:53.417020 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11221 12:18:53.417128 end: 3 lava-test-retry (duration 00:00:09) [common]
11222 12:18:53.417243 start: 4 finalize (timeout 00:07:44) [common]
11223 12:18:53.417359 start: 4.1 power-off (timeout 00:00:30) [common]
11224 12:18:53.417552 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11225 12:18:53.497938 >> Command sent successfully.
11226 12:18:53.504905 Returned 0 in 0 seconds
11227 12:18:53.605593 end: 4.1 power-off (duration 00:00:00) [common]
11229 12:18:53.607003 start: 4.2 read-feedback (timeout 00:07:44) [common]
11230 12:18:53.608166 Listened to connection for namespace 'common' for up to 1s
11231 12:18:54.608724 Finalising connection for namespace 'common'
11232 12:18:54.609373 Disconnecting from shell: Finalise
11233 12:18:54.609784 / #
11234 12:18:54.710715 end: 4.2 read-feedback (duration 00:00:01) [common]
11235 12:18:54.711360 end: 4 finalize (duration 00:00:01) [common]
11236 12:18:54.711913 Cleaning after the job
11237 12:18:54.712395 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/ramdisk
11238 12:18:54.722847 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/kernel
11239 12:18:54.750730 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/dtb
11240 12:18:54.751140 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/nfsrootfs
11241 12:18:54.831498 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605447/tftp-deploy-nuzl_41d/modules
11242 12:18:54.836877 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605447
11243 12:18:55.404135 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605447
11244 12:18:55.404344 Job finished correctly