Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 48
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 12:16:21.842006 lava-dispatcher, installed at version: 2023.05.1
2 12:16:21.842210 start: 0 validate
3 12:16:21.842351 Start time: 2023-06-06 12:16:21.842343+00:00 (UTC)
4 12:16:21.842482 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:16:21.842616 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 12:16:22.124428 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:16:22.124608 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:16:22.425945 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:16:22.426180 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:16:22.728547 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:16:22.728777 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:16:23.025742 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:16:23.025951 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:16:23.313407 validate duration: 1.47
16 12:16:23.313766 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:16:23.313907 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:16:23.314040 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:16:23.314202 Not decompressing ramdisk as can be used compressed.
20 12:16:23.314332 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 12:16:23.314436 saving as /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/ramdisk/initrd.cpio.gz
22 12:16:23.314534 total size: 4665601 (4MB)
23 12:16:23.316118 progress 0% (0MB)
24 12:16:23.317799 progress 5% (0MB)
25 12:16:23.319143 progress 10% (0MB)
26 12:16:23.320476 progress 15% (0MB)
27 12:16:23.321820 progress 20% (0MB)
28 12:16:23.323163 progress 25% (1MB)
29 12:16:23.324485 progress 30% (1MB)
30 12:16:23.325829 progress 35% (1MB)
31 12:16:23.327163 progress 40% (1MB)
32 12:16:23.328664 progress 45% (2MB)
33 12:16:23.329993 progress 50% (2MB)
34 12:16:23.331316 progress 55% (2MB)
35 12:16:23.332630 progress 60% (2MB)
36 12:16:23.333959 progress 65% (2MB)
37 12:16:23.335255 progress 70% (3MB)
38 12:16:23.336545 progress 75% (3MB)
39 12:16:23.337801 progress 80% (3MB)
40 12:16:23.339192 progress 85% (3MB)
41 12:16:23.340409 progress 90% (4MB)
42 12:16:23.341644 progress 95% (4MB)
43 12:16:23.342886 progress 100% (4MB)
44 12:16:23.343047 4MB downloaded in 0.03s (156.07MB/s)
45 12:16:23.343204 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:16:23.343466 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:16:23.343581 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:16:23.343706 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:16:23.343866 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:16:23.343969 saving as /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/kernel/Image
52 12:16:23.344062 total size: 45746688 (43MB)
53 12:16:23.344157 No compression specified
54 12:16:23.345857 progress 0% (0MB)
55 12:16:23.357857 progress 5% (2MB)
56 12:16:23.370346 progress 10% (4MB)
57 12:16:23.382395 progress 15% (6MB)
58 12:16:23.394950 progress 20% (8MB)
59 12:16:23.407272 progress 25% (10MB)
60 12:16:23.419700 progress 30% (13MB)
61 12:16:23.432413 progress 35% (15MB)
62 12:16:23.445045 progress 40% (17MB)
63 12:16:23.457640 progress 45% (19MB)
64 12:16:23.469895 progress 50% (21MB)
65 12:16:23.481818 progress 55% (24MB)
66 12:16:23.494833 progress 60% (26MB)
67 12:16:23.507268 progress 65% (28MB)
68 12:16:23.519104 progress 70% (30MB)
69 12:16:23.531072 progress 75% (32MB)
70 12:16:23.543289 progress 80% (34MB)
71 12:16:23.555807 progress 85% (37MB)
72 12:16:23.568122 progress 90% (39MB)
73 12:16:23.580473 progress 95% (41MB)
74 12:16:23.592949 progress 100% (43MB)
75 12:16:23.593128 43MB downloaded in 0.25s (175.17MB/s)
76 12:16:23.593336 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:16:23.593727 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:16:23.593858 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:16:23.593981 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:16:23.594146 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:16:23.594250 saving as /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/dtb/mt8192-asurada-spherion-r0.dtb
83 12:16:23.594346 total size: 46924 (0MB)
84 12:16:23.594437 No compression specified
85 12:16:23.596156 progress 69% (0MB)
86 12:16:23.596474 progress 100% (0MB)
87 12:16:23.596663 0MB downloaded in 0.00s (19.34MB/s)
88 12:16:23.596845 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:16:23.597218 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:16:23.597345 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:16:23.597474 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:16:23.597633 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 12:16:23.597742 saving as /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/nfsrootfs/full.rootfs.tar
95 12:16:23.597840 total size: 200770336 (191MB)
96 12:16:23.597942 Using unxz to decompress xz
97 12:16:23.602169 progress 0% (0MB)
98 12:16:24.130666 progress 5% (9MB)
99 12:16:24.646295 progress 10% (19MB)
100 12:16:25.229661 progress 15% (28MB)
101 12:16:25.600806 progress 20% (38MB)
102 12:16:25.925837 progress 25% (47MB)
103 12:16:26.524252 progress 30% (57MB)
104 12:16:27.082012 progress 35% (67MB)
105 12:16:27.676703 progress 40% (76MB)
106 12:16:28.256377 progress 45% (86MB)
107 12:16:28.861064 progress 50% (95MB)
108 12:16:29.488936 progress 55% (105MB)
109 12:16:30.147213 progress 60% (114MB)
110 12:16:30.270037 progress 65% (124MB)
111 12:16:30.414146 progress 70% (134MB)
112 12:16:30.517972 progress 75% (143MB)
113 12:16:30.597197 progress 80% (153MB)
114 12:16:30.668716 progress 85% (162MB)
115 12:16:30.770729 progress 90% (172MB)
116 12:16:31.082734 progress 95% (181MB)
117 12:16:31.687037 progress 100% (191MB)
118 12:16:31.691748 191MB downloaded in 8.09s (23.66MB/s)
119 12:16:31.692075 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:16:31.692506 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:16:31.692646 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:16:31.692785 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:16:31.692972 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:16:31.693062 saving as /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/modules/modules.tar
126 12:16:31.693146 total size: 8553528 (8MB)
127 12:16:31.693249 Using unxz to decompress xz
128 12:16:31.697074 progress 0% (0MB)
129 12:16:31.718348 progress 5% (0MB)
130 12:16:31.742279 progress 10% (0MB)
131 12:16:31.773767 progress 15% (1MB)
132 12:16:31.799809 progress 20% (1MB)
133 12:16:31.825513 progress 25% (2MB)
134 12:16:31.850344 progress 30% (2MB)
135 12:16:31.877305 progress 35% (2MB)
136 12:16:31.902451 progress 40% (3MB)
137 12:16:31.930265 progress 45% (3MB)
138 12:16:31.957515 progress 50% (4MB)
139 12:16:31.984577 progress 55% (4MB)
140 12:16:32.010133 progress 60% (4MB)
141 12:16:32.034485 progress 65% (5MB)
142 12:16:32.059728 progress 70% (5MB)
143 12:16:32.084682 progress 75% (6MB)
144 12:16:32.112190 progress 80% (6MB)
145 12:16:32.138081 progress 85% (6MB)
146 12:16:32.164413 progress 90% (7MB)
147 12:16:32.188856 progress 95% (7MB)
148 12:16:32.216884 progress 100% (8MB)
149 12:16:32.221684 8MB downloaded in 0.53s (15.43MB/s)
150 12:16:32.221973 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:16:32.222247 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:16:32.222346 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:16:32.222445 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:16:36.060443 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10605441/extract-nfsrootfs-oz4520mr
156 12:16:36.060681 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:16:36.060826 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:16:36.061012 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb
159 12:16:36.061155 makedir: /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin
160 12:16:36.061265 makedir: /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/tests
161 12:16:36.061375 makedir: /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/results
162 12:16:36.061483 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-add-keys
163 12:16:36.061628 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-add-sources
164 12:16:36.061759 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-background-process-start
165 12:16:36.061888 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-background-process-stop
166 12:16:36.062017 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-common-functions
167 12:16:36.062144 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-echo-ipv4
168 12:16:36.062271 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-install-packages
169 12:16:36.062396 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-installed-packages
170 12:16:36.062520 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-os-build
171 12:16:36.062645 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-probe-channel
172 12:16:36.062771 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-probe-ip
173 12:16:36.062898 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-target-ip
174 12:16:36.063022 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-target-mac
175 12:16:36.063147 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-target-storage
176 12:16:36.063274 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-test-case
177 12:16:36.063399 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-test-event
178 12:16:36.063523 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-test-feedback
179 12:16:36.063659 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-test-raise
180 12:16:36.063784 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-test-reference
181 12:16:36.063916 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-test-runner
182 12:16:36.064042 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-test-set
183 12:16:36.064173 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-test-shell
184 12:16:36.064312 Updating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-add-keys (debian)
185 12:16:36.066186 Updating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-add-sources (debian)
186 12:16:36.067201 Updating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-install-packages (debian)
187 12:16:36.067520 Updating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-installed-packages (debian)
188 12:16:36.067858 Updating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/bin/lava-os-build (debian)
189 12:16:36.068068 Creating /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/environment
190 12:16:36.068179 LAVA metadata
191 12:16:36.068253 - LAVA_JOB_ID=10605441
192 12:16:36.068319 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:16:36.068424 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:16:36.068494 skipped lava-vland-overlay
195 12:16:36.068573 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:16:36.068656 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:16:36.068720 skipped lava-multinode-overlay
198 12:16:36.068804 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:16:36.068890 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:16:36.068967 Loading test definitions
201 12:16:36.069063 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:16:36.069138 Using /lava-10605441 at stage 0
203 12:16:36.069427 uuid=10605441_1.6.2.3.1 testdef=None
204 12:16:36.069520 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:16:36.069611 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:16:36.070069 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:16:36.070305 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:16:36.070881 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:16:36.071121 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:16:36.071664 runner path: /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/0/tests/0_timesync-off test_uuid 10605441_1.6.2.3.1
213 12:16:36.071823 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:16:36.072056 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:16:36.072131 Using /lava-10605441 at stage 0
217 12:16:36.072233 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:16:36.072314 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/0/tests/1_kselftest-rtc'
219 12:16:40.108212 Running '/usr/bin/git checkout kernelci.org
220 12:16:40.210282 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 12:16:40.211003 uuid=10605441_1.6.2.3.5 testdef=None
222 12:16:40.211165 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 12:16:40.211426 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 12:16:40.212175 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:16:40.212414 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 12:16:40.213404 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:16:40.213646 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 12:16:40.214610 runner path: /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/0/tests/1_kselftest-rtc test_uuid 10605441_1.6.2.3.5
232 12:16:40.214711 BOARD='mt8192-asurada-spherion-r0'
233 12:16:40.214781 BRANCH='cip-gitlab'
234 12:16:40.214846 SKIPFILE='/dev/null'
235 12:16:40.214906 SKIP_INSTALL='True'
236 12:16:40.214969 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:16:40.215031 TST_CASENAME=''
238 12:16:40.215103 TST_CMDFILES='rtc'
239 12:16:40.215253 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:16:40.215474 Creating lava-test-runner.conf files
242 12:16:40.215544 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605441/lava-overlay-5j974tvb/lava-10605441/0 for stage 0
243 12:16:40.215646 - 0_timesync-off
244 12:16:40.215721 - 1_kselftest-rtc
245 12:16:40.215822 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 12:16:40.215918 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 12:16:48.159552 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:16:48.159716 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 12:16:48.159812 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:16:48.159916 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 12:16:48.160008 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 12:16:48.271602 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:16:48.271955 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 12:16:48.272076 extracting modules file /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605441/extract-nfsrootfs-oz4520mr
255 12:16:48.481488 extracting modules file /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605441/extract-overlay-ramdisk-1n7vutpg/ramdisk
256 12:16:48.681549 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:16:48.681726 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 12:16:48.681825 [common] Applying overlay to NFS
259 12:16:48.681899 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605441/compress-overlay-nvd2h64q/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605441/extract-nfsrootfs-oz4520mr
260 12:16:49.572156 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:16:49.572337 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 12:16:49.572438 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:16:49.572536 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 12:16:49.572621 Building ramdisk /var/lib/lava/dispatcher/tmp/10605441/extract-overlay-ramdisk-1n7vutpg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605441/extract-overlay-ramdisk-1n7vutpg/ramdisk
265 12:16:50.315160 >> 117807 blocks
266 12:16:52.265049 rename /var/lib/lava/dispatcher/tmp/10605441/extract-overlay-ramdisk-1n7vutpg/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/ramdisk/ramdisk.cpio.gz
267 12:16:52.265477 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 12:16:52.265603 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 12:16:52.265702 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 12:16:52.265807 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/kernel/Image'
271 12:17:03.986116 Returned 0 in 11 seconds
272 12:17:04.087116 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/kernel/image.itb
273 12:17:04.462671 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:17:04.463032 output: Created: Tue Jun 6 13:17:04 2023
275 12:17:04.463128 output: Image 0 (kernel-1)
276 12:17:04.463208 output: Description:
277 12:17:04.463271 output: Created: Tue Jun 6 13:17:04 2023
278 12:17:04.463334 output: Type: Kernel Image
279 12:17:04.463395 output: Compression: lzma compressed
280 12:17:04.463454 output: Data Size: 10094623 Bytes = 9858.03 KiB = 9.63 MiB
281 12:17:04.463512 output: Architecture: AArch64
282 12:17:04.463569 output: OS: Linux
283 12:17:04.463628 output: Load Address: 0x00000000
284 12:17:04.463685 output: Entry Point: 0x00000000
285 12:17:04.463740 output: Hash algo: crc32
286 12:17:04.463793 output: Hash value: fd97082e
287 12:17:04.463845 output: Image 1 (fdt-1)
288 12:17:04.463898 output: Description: mt8192-asurada-spherion-r0
289 12:17:04.463951 output: Created: Tue Jun 6 13:17:04 2023
290 12:17:04.464004 output: Type: Flat Device Tree
291 12:17:04.464057 output: Compression: uncompressed
292 12:17:04.464110 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 12:17:04.464163 output: Architecture: AArch64
294 12:17:04.464215 output: Hash algo: crc32
295 12:17:04.464267 output: Hash value: 1df858fa
296 12:17:04.464319 output: Image 2 (ramdisk-1)
297 12:17:04.464371 output: Description: unavailable
298 12:17:04.464423 output: Created: Tue Jun 6 13:17:04 2023
299 12:17:04.464503 output: Type: RAMDisk Image
300 12:17:04.464555 output: Compression: Unknown Compression
301 12:17:04.464608 output: Data Size: 17643869 Bytes = 17230.34 KiB = 16.83 MiB
302 12:17:04.464683 output: Architecture: AArch64
303 12:17:04.464737 output: OS: Linux
304 12:17:04.464812 output: Load Address: unavailable
305 12:17:04.464865 output: Entry Point: unavailable
306 12:17:04.464918 output: Hash algo: crc32
307 12:17:04.464969 output: Hash value: f595e2ae
308 12:17:04.465022 output: Default Configuration: 'conf-1'
309 12:17:04.465074 output: Configuration 0 (conf-1)
310 12:17:04.465126 output: Description: mt8192-asurada-spherion-r0
311 12:17:04.465181 output: Kernel: kernel-1
312 12:17:04.465238 output: Init Ramdisk: ramdisk-1
313 12:17:04.465291 output: FDT: fdt-1
314 12:17:04.465344 output: Loadables: kernel-1
315 12:17:04.465401 output:
316 12:17:04.465592 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 12:17:04.465693 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 12:17:04.465799 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 12:17:04.465897 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 12:17:04.465979 No LXC device requested
321 12:17:04.466058 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:17:04.466144 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 12:17:04.466224 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:17:04.466295 Checking files for TFTP limit of 4294967296 bytes.
325 12:17:04.466775 end: 1 tftp-deploy (duration 00:00:41) [common]
326 12:17:04.466884 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:17:04.466977 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:17:04.467104 substitutions:
329 12:17:04.467174 - {DTB}: 10605441/tftp-deploy-gxdu5qj5/dtb/mt8192-asurada-spherion-r0.dtb
330 12:17:04.467238 - {INITRD}: 10605441/tftp-deploy-gxdu5qj5/ramdisk/ramdisk.cpio.gz
331 12:17:04.467297 - {KERNEL}: 10605441/tftp-deploy-gxdu5qj5/kernel/Image
332 12:17:04.467355 - {LAVA_MAC}: None
333 12:17:04.467411 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10605441/extract-nfsrootfs-oz4520mr
334 12:17:04.467468 - {NFS_SERVER_IP}: 192.168.201.1
335 12:17:04.467522 - {PRESEED_CONFIG}: None
336 12:17:04.467576 - {PRESEED_LOCAL}: None
337 12:17:04.467638 - {RAMDISK}: 10605441/tftp-deploy-gxdu5qj5/ramdisk/ramdisk.cpio.gz
338 12:17:04.467693 - {ROOT_PART}: None
339 12:17:04.467747 - {ROOT}: None
340 12:17:04.467800 - {SERVER_IP}: 192.168.201.1
341 12:17:04.467854 - {TEE}: None
342 12:17:04.467907 Parsed boot commands:
343 12:17:04.467962 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:17:04.468129 Parsed boot commands: tftpboot 192.168.201.1 10605441/tftp-deploy-gxdu5qj5/kernel/image.itb 10605441/tftp-deploy-gxdu5qj5/kernel/cmdline
345 12:17:04.468218 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:17:04.468301 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:17:04.468395 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:17:04.468480 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:17:04.468551 Not connected, no need to disconnect.
350 12:17:04.468625 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:17:04.468706 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:17:04.468798 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
353 12:17:04.471915 Setting prompt string to ['lava-test: # ']
354 12:17:04.472251 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:17:04.472391 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:17:04.472526 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:17:04.472647 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:17:04.472927 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 12:17:09.619241 >> Command sent successfully.
360 12:17:09.621679 Returned 0 in 5 seconds
361 12:17:09.722065 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:17:09.722387 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:17:09.722492 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:17:09.722607 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:17:09.722676 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:17:09.722746 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:17:09.723004 [Enter `^Ec?' for help]
369 12:17:09.897709
370 12:17:09.897874
371 12:17:09.897946 F0: 102B 0000
372 12:17:09.898010
373 12:17:09.898070 F3: 1001 0000 [0200]
374 12:17:09.901100
375 12:17:09.901184 F3: 1001 0000
376 12:17:09.901251
377 12:17:09.901313 F7: 102D 0000
378 12:17:09.901374
379 12:17:09.904216 F1: 0000 0000
380 12:17:09.904300
381 12:17:09.904367 V0: 0000 0000 [0001]
382 12:17:09.904429
383 12:17:09.907884 00: 0007 8000
384 12:17:09.907973
385 12:17:09.908040 01: 0000 0000
386 12:17:09.908104
387 12:17:09.910887 BP: 0C00 0209 [0000]
388 12:17:09.910970
389 12:17:09.911037 G0: 1182 0000
390 12:17:09.911099
391 12:17:09.914471 EC: 0000 0021 [4000]
392 12:17:09.914555
393 12:17:09.914621 S7: 0000 0000 [0000]
394 12:17:09.914683
395 12:17:09.918801 CC: 0000 0000 [0001]
396 12:17:09.918971
397 12:17:09.919053 T0: 0000 0040 [010F]
398 12:17:09.919129
399 12:17:09.919198 Jump to BL
400 12:17:09.919267
401 12:17:09.944687
402 12:17:09.944863
403 12:17:09.944934
404 12:17:09.951632 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:17:09.955025 ARM64: Exception handlers installed.
406 12:17:09.959043 ARM64: Testing exception
407 12:17:09.962015 ARM64: Done test exception
408 12:17:09.968757 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:17:09.979345 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:17:09.985777 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:17:09.995647 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:17:10.002125 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:17:10.012516 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:17:10.022674 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:17:10.029311 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:17:10.047834 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:17:10.050815 WDT: Last reset was cold boot
418 12:17:10.054192 SPI1(PAD0) initialized at 2873684 Hz
419 12:17:10.057599 SPI5(PAD0) initialized at 992727 Hz
420 12:17:10.060720 VBOOT: Loading verstage.
421 12:17:10.067221 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:17:10.070338 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:17:10.073864 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:17:10.080395 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:17:10.087285 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:17:10.093331 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:17:10.102844 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:17:10.103060
429 12:17:10.103226
430 12:17:10.112541 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:17:10.116004 ARM64: Exception handlers installed.
432 12:17:10.119076 ARM64: Testing exception
433 12:17:10.119185 ARM64: Done test exception
434 12:17:10.126034 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:17:10.129439 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:17:10.143721 Probing TPM: . done!
437 12:17:10.143875 TPM ready after 0 ms
438 12:17:10.150131 Connected to device vid:did:rid of 1ae0:0028:00
439 12:17:10.157531 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 12:17:10.160851 Initialized TPM device CR50 revision 0
441 12:17:10.226745 tlcl_send_startup: Startup return code is 0
442 12:17:10.227272 TPM: setup succeeded
443 12:17:10.238359 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:17:10.247234 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:17:10.253537 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:17:10.266428 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:17:10.269584 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:17:10.277714 in-header: 03 07 00 00 08 00 00 00
449 12:17:10.281208 in-data: aa e4 47 04 13 02 00 00
450 12:17:10.284670 Chrome EC: UHEPI supported
451 12:17:10.291971 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:17:10.295525 in-header: 03 ad 00 00 08 00 00 00
453 12:17:10.299045 in-data: 00 20 20 08 00 00 00 00
454 12:17:10.299553 Phase 1
455 12:17:10.302852 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:17:10.310151 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:17:10.313775 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:17:10.316869 Recovery requested (1009000e)
459 12:17:10.327488 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:17:10.333540 tlcl_extend: response is 0
461 12:17:10.343669 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:17:10.349494 tlcl_extend: response is 0
463 12:17:10.356599 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:17:10.376854 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 12:17:10.383423 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:17:10.383872
467 12:17:10.384218
468 12:17:10.393232 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:17:10.396902 ARM64: Exception handlers installed.
470 12:17:10.400462 ARM64: Testing exception
471 12:17:10.400955 ARM64: Done test exception
472 12:17:10.421896 pmic_efuse_setting: Set efuses in 11 msecs
473 12:17:10.425492 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:17:10.432043 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:17:10.435184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:17:10.441949 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:17:10.445590 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:17:10.448948 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:17:10.456273 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:17:10.459792 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:17:10.463797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:17:10.467850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:17:10.474639 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:17:10.478729 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:17:10.481941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:17:10.488410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:17:10.495500 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:17:10.498474 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:17:10.505469 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:17:10.512901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:17:10.516394 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:17:10.522792 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:17:10.529903 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:17:10.533507 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:17:10.540225 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:17:10.543713 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:17:10.549878 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:17:10.556525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:17:10.560172 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:17:10.566771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:17:10.569793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:17:10.576662 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:17:10.580082 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:17:10.587022 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:17:10.590245 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:17:10.596882 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:17:10.599955 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:17:10.606528 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:17:10.610065 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:17:10.616442 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:17:10.619472 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:17:10.626248 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:17:10.630229 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:17:10.634147 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:17:10.637627 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:17:10.644357 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:17:10.647490 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:17:10.650901 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:17:10.657238 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:17:10.660702 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:17:10.663738 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:17:10.667107 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:17:10.674142 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:17:10.677403 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:17:10.684037 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:17:10.694189 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:17:10.697028 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:17:10.707098 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:17:10.713654 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:17:10.720423 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:17:10.723998 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:17:10.727121 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:17:10.735028 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
534 12:17:10.741396 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:17:10.744488 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 12:17:10.747798 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:17:10.759253 [RTC]rtc_get_frequency_meter,154: input=15, output=773
538 12:17:10.768729 [RTC]rtc_get_frequency_meter,154: input=23, output=958
539 12:17:10.778189 [RTC]rtc_get_frequency_meter,154: input=19, output=864
540 12:17:10.787519 [RTC]rtc_get_frequency_meter,154: input=17, output=819
541 12:17:10.797525 [RTC]rtc_get_frequency_meter,154: input=16, output=795
542 12:17:10.800491 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 12:17:10.807162 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 12:17:10.810427 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 12:17:10.813942 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 12:17:10.817432 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 12:17:10.820440 ADC[4]: Raw value=903245 ID=7
548 12:17:10.823735 ADC[3]: Raw value=213179 ID=1
549 12:17:10.827371 RAM Code: 0x71
550 12:17:10.830304 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 12:17:10.833810 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 12:17:10.843989 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 12:17:10.850555 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 12:17:10.853613 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 12:17:10.856841 in-header: 03 07 00 00 08 00 00 00
556 12:17:10.860605 in-data: aa e4 47 04 13 02 00 00
557 12:17:10.863663 Chrome EC: UHEPI supported
558 12:17:10.870529 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 12:17:10.873489 in-header: 03 ed 00 00 08 00 00 00
560 12:17:10.876907 in-data: 80 20 60 08 00 00 00 00
561 12:17:10.880041 MRC: failed to locate region type 0.
562 12:17:10.886901 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 12:17:10.890295 DRAM-K: Running full calibration
564 12:17:10.893659 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 12:17:10.896627 header.status = 0x0
566 12:17:10.900126 header.version = 0x6 (expected: 0x6)
567 12:17:10.903551 header.size = 0xd00 (expected: 0xd00)
568 12:17:10.906660 header.flags = 0x0
569 12:17:10.910284 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 12:17:10.928990 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
571 12:17:10.935465 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 12:17:10.938928 dram_init: ddr_geometry: 2
573 12:17:10.942221 [EMI] MDL number = 2
574 12:17:10.942684 [EMI] Get MDL freq = 0
575 12:17:10.945748 dram_init: ddr_type: 0
576 12:17:10.946268 is_discrete_lpddr4: 1
577 12:17:10.949281 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 12:17:10.949714
579 12:17:10.950053
580 12:17:10.952888 [Bian_co] ETT version 0.0.0.1
581 12:17:10.956385 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 12:17:10.956850
583 12:17:10.963560 dramc_set_vcore_voltage set vcore to 650000
584 12:17:10.963994 Read voltage for 800, 4
585 12:17:10.964341 Vio18 = 0
586 12:17:10.967487 Vcore = 650000
587 12:17:10.967922 Vdram = 0
588 12:17:10.968286 Vddq = 0
589 12:17:10.968641 Vmddr = 0
590 12:17:10.971485 dram_init: config_dvfs: 1
591 12:17:10.975178 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 12:17:10.981802 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 12:17:10.985911 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 12:17:10.989229 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 12:17:10.993022 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 12:17:10.996899 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 12:17:11.000347 MEM_TYPE=3, freq_sel=18
598 12:17:11.004364 sv_algorithm_assistance_LP4_1600
599 12:17:11.007926 ============ PULL DRAM RESETB DOWN ============
600 12:17:11.011482 ========== PULL DRAM RESETB DOWN end =========
601 12:17:11.014576 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 12:17:11.018016 ===================================
603 12:17:11.021604 LPDDR4 DRAM CONFIGURATION
604 12:17:11.024499 ===================================
605 12:17:11.024967 EX_ROW_EN[0] = 0x0
606 12:17:11.027966 EX_ROW_EN[1] = 0x0
607 12:17:11.031375 LP4Y_EN = 0x0
608 12:17:11.031808 WORK_FSP = 0x0
609 12:17:11.034840 WL = 0x2
610 12:17:11.035272 RL = 0x2
611 12:17:11.037996 BL = 0x2
612 12:17:11.038429 RPST = 0x0
613 12:17:11.041457 RD_PRE = 0x0
614 12:17:11.041890 WR_PRE = 0x1
615 12:17:11.044798 WR_PST = 0x0
616 12:17:11.045229 DBI_WR = 0x0
617 12:17:11.047949 DBI_RD = 0x0
618 12:17:11.048385 OTF = 0x1
619 12:17:11.051430 ===================================
620 12:17:11.054370 ===================================
621 12:17:11.057810 ANA top config
622 12:17:11.061437 ===================================
623 12:17:11.061870 DLL_ASYNC_EN = 0
624 12:17:11.064869 ALL_SLAVE_EN = 1
625 12:17:11.068229 NEW_RANK_MODE = 1
626 12:17:11.071231 DLL_IDLE_MODE = 1
627 12:17:11.071666 LP45_APHY_COMB_EN = 1
628 12:17:11.075022 TX_ODT_DIS = 1
629 12:17:11.078806 NEW_8X_MODE = 1
630 12:17:11.081967 ===================================
631 12:17:11.086179 ===================================
632 12:17:11.089114 data_rate = 1600
633 12:17:11.089591 CKR = 1
634 12:17:11.092535 DQ_P2S_RATIO = 8
635 12:17:11.096331 ===================================
636 12:17:11.099090 CA_P2S_RATIO = 8
637 12:17:11.102608 DQ_CA_OPEN = 0
638 12:17:11.106041 DQ_SEMI_OPEN = 0
639 12:17:11.106503 CA_SEMI_OPEN = 0
640 12:17:11.109141 CA_FULL_RATE = 0
641 12:17:11.112755 DQ_CKDIV4_EN = 1
642 12:17:11.115716 CA_CKDIV4_EN = 1
643 12:17:11.119141 CA_PREDIV_EN = 0
644 12:17:11.122499 PH8_DLY = 0
645 12:17:11.123154 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 12:17:11.125990 DQ_AAMCK_DIV = 4
647 12:17:11.128989 CA_AAMCK_DIV = 4
648 12:17:11.132072 CA_ADMCK_DIV = 4
649 12:17:11.135333 DQ_TRACK_CA_EN = 0
650 12:17:11.138747 CA_PICK = 800
651 12:17:11.142178 CA_MCKIO = 800
652 12:17:11.142295 MCKIO_SEMI = 0
653 12:17:11.145126 PLL_FREQ = 3068
654 12:17:11.148752 DQ_UI_PI_RATIO = 32
655 12:17:11.152206 CA_UI_PI_RATIO = 0
656 12:17:11.155286 ===================================
657 12:17:11.158795 ===================================
658 12:17:11.161861 memory_type:LPDDR4
659 12:17:11.161989 GP_NUM : 10
660 12:17:11.165224 SRAM_EN : 1
661 12:17:11.168758 MD32_EN : 0
662 12:17:11.168859 ===================================
663 12:17:11.172420 [ANA_INIT] >>>>>>>>>>>>>>
664 12:17:11.176064 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 12:17:11.179622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 12:17:11.183203 ===================================
667 12:17:11.187007 data_rate = 1600,PCW = 0X7600
668 12:17:11.187127 ===================================
669 12:17:11.190904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 12:17:11.198058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 12:17:11.201576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 12:17:11.208058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 12:17:11.211602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 12:17:11.214725 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 12:17:11.214847 [ANA_INIT] flow start
676 12:17:11.218222 [ANA_INIT] PLL >>>>>>>>
677 12:17:11.221158 [ANA_INIT] PLL <<<<<<<<
678 12:17:11.224746 [ANA_INIT] MIDPI >>>>>>>>
679 12:17:11.224943 [ANA_INIT] MIDPI <<<<<<<<
680 12:17:11.228119 [ANA_INIT] DLL >>>>>>>>
681 12:17:11.231145 [ANA_INIT] flow end
682 12:17:11.234762 ============ LP4 DIFF to SE enter ============
683 12:17:11.238220 ============ LP4 DIFF to SE exit ============
684 12:17:11.241659 [ANA_INIT] <<<<<<<<<<<<<
685 12:17:11.245041 [Flow] Enable top DCM control >>>>>
686 12:17:11.248050 [Flow] Enable top DCM control <<<<<
687 12:17:11.251491 Enable DLL master slave shuffle
688 12:17:11.255051 ==============================================================
689 12:17:11.258116 Gating Mode config
690 12:17:11.261269 ==============================================================
691 12:17:11.264746 Config description:
692 12:17:11.274657 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 12:17:11.281106 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 12:17:11.284793 SELPH_MODE 0: By rank 1: By Phase
695 12:17:11.291199 ==============================================================
696 12:17:11.294549 GAT_TRACK_EN = 1
697 12:17:11.297950 RX_GATING_MODE = 2
698 12:17:11.301229 RX_GATING_TRACK_MODE = 2
699 12:17:11.304614 SELPH_MODE = 1
700 12:17:11.307865 PICG_EARLY_EN = 1
701 12:17:11.307974 VALID_LAT_VALUE = 1
702 12:17:11.314567 ==============================================================
703 12:17:11.317886 Enter into Gating configuration >>>>
704 12:17:11.321359 Exit from Gating configuration <<<<
705 12:17:11.324295 Enter into DVFS_PRE_config >>>>>
706 12:17:11.334280 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 12:17:11.337576 Exit from DVFS_PRE_config <<<<<
708 12:17:11.341052 Enter into PICG configuration >>>>
709 12:17:11.344350 Exit from PICG configuration <<<<
710 12:17:11.347663 [RX_INPUT] configuration >>>>>
711 12:17:11.351040 [RX_INPUT] configuration <<<<<
712 12:17:11.354427 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 12:17:11.361090 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 12:17:11.367599 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 12:17:11.374424 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 12:17:11.380783 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 12:17:11.387647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 12:17:11.391083 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 12:17:11.394009 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 12:17:11.397985 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 12:17:11.401769 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 12:17:11.405240 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 12:17:11.412125 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 12:17:11.415277 ===================================
725 12:17:11.415370 LPDDR4 DRAM CONFIGURATION
726 12:17:11.418497 ===================================
727 12:17:11.421953 EX_ROW_EN[0] = 0x0
728 12:17:11.425336 EX_ROW_EN[1] = 0x0
729 12:17:11.425417 LP4Y_EN = 0x0
730 12:17:11.428664 WORK_FSP = 0x0
731 12:17:11.428745 WL = 0x2
732 12:17:11.432313 RL = 0x2
733 12:17:11.432419 BL = 0x2
734 12:17:11.435600 RPST = 0x0
735 12:17:11.435707 RD_PRE = 0x0
736 12:17:11.439584 WR_PRE = 0x1
737 12:17:11.439695 WR_PST = 0x0
738 12:17:11.439804 DBI_WR = 0x0
739 12:17:11.443014 DBI_RD = 0x0
740 12:17:11.443128 OTF = 0x1
741 12:17:11.446543 ===================================
742 12:17:11.453444 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 12:17:11.457395 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 12:17:11.460758 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 12:17:11.464535 ===================================
746 12:17:11.464656 LPDDR4 DRAM CONFIGURATION
747 12:17:11.468490 ===================================
748 12:17:11.472021 EX_ROW_EN[0] = 0x10
749 12:17:11.472096 EX_ROW_EN[1] = 0x0
750 12:17:11.476004 LP4Y_EN = 0x0
751 12:17:11.476103 WORK_FSP = 0x0
752 12:17:11.479551 WL = 0x2
753 12:17:11.479624 RL = 0x2
754 12:17:11.482867 BL = 0x2
755 12:17:11.483045 RPST = 0x0
756 12:17:11.486534 RD_PRE = 0x0
757 12:17:11.486631 WR_PRE = 0x1
758 12:17:11.490456 WR_PST = 0x0
759 12:17:11.490552 DBI_WR = 0x0
760 12:17:11.493525 DBI_RD = 0x0
761 12:17:11.493596 OTF = 0x1
762 12:17:11.496965 ===================================
763 12:17:11.504424 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 12:17:11.508047 nWR fixed to 40
765 12:17:11.508125 [ModeRegInit_LP4] CH0 RK0
766 12:17:11.511454 [ModeRegInit_LP4] CH0 RK1
767 12:17:11.515213 [ModeRegInit_LP4] CH1 RK0
768 12:17:11.515287 [ModeRegInit_LP4] CH1 RK1
769 12:17:11.519012 match AC timing 13
770 12:17:11.522764 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 12:17:11.526419 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 12:17:11.529885 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 12:17:11.537884 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 12:17:11.541269 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 12:17:11.541357 [EMI DOE] emi_dcm 0
776 12:17:11.545132 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 12:17:11.545222 ==
778 12:17:11.549224 Dram Type= 6, Freq= 0, CH_0, rank 0
779 12:17:11.552930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 12:17:11.556669 ==
781 12:17:11.560128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 12:17:11.566952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 12:17:11.574851 [CA 0] Center 38 (7~69) winsize 63
784 12:17:11.578328 [CA 1] Center 38 (7~69) winsize 63
785 12:17:11.581849 [CA 2] Center 35 (5~66) winsize 62
786 12:17:11.585707 [CA 3] Center 35 (5~66) winsize 62
787 12:17:11.589449 [CA 4] Center 34 (4~65) winsize 62
788 12:17:11.593394 [CA 5] Center 34 (3~65) winsize 63
789 12:17:11.593518
790 12:17:11.596852 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 12:17:11.596941
792 12:17:11.600447 [CATrainingPosCal] consider 1 rank data
793 12:17:11.604255 u2DelayCellTimex100 = 270/100 ps
794 12:17:11.608203 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
795 12:17:11.611440 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
796 12:17:11.611553 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
797 12:17:11.615129 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
798 12:17:11.618984 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
799 12:17:11.622802 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
800 12:17:11.622945
801 12:17:11.626560 CA PerBit enable=1, Macro0, CA PI delay=34
802 12:17:11.630188
803 12:17:11.630380 [CBTSetCACLKResult] CA Dly = 34
804 12:17:11.634142 CS Dly: 6 (0~37)
805 12:17:11.634302 ==
806 12:17:11.637500 Dram Type= 6, Freq= 0, CH_0, rank 1
807 12:17:11.641037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 12:17:11.641122 ==
809 12:17:11.644978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 12:17:11.652350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 12:17:11.661486 [CA 0] Center 38 (7~69) winsize 63
812 12:17:11.664886 [CA 1] Center 38 (7~69) winsize 63
813 12:17:11.668837 [CA 2] Center 36 (6~67) winsize 62
814 12:17:11.672178 [CA 3] Center 35 (5~66) winsize 62
815 12:17:11.676129 [CA 4] Center 35 (4~66) winsize 63
816 12:17:11.679545 [CA 5] Center 34 (4~65) winsize 62
817 12:17:11.679633
818 12:17:11.683581 [CmdBusTrainingLP45] Vref(ca) range 1: 34
819 12:17:11.683695
820 12:17:11.687549 [CATrainingPosCal] consider 2 rank data
821 12:17:11.687672 u2DelayCellTimex100 = 270/100 ps
822 12:17:11.691089 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 12:17:11.695116 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 12:17:11.698621 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 12:17:11.702575 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 12:17:11.706069 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 12:17:11.710039 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
828 12:17:11.710129
829 12:17:11.713600 CA PerBit enable=1, Macro0, CA PI delay=34
830 12:17:11.713683
831 12:17:11.716924 [CBTSetCACLKResult] CA Dly = 34
832 12:17:11.721182 CS Dly: 6 (0~38)
833 12:17:11.721293
834 12:17:11.721365 ----->DramcWriteLeveling(PI) begin...
835 12:17:11.724465 ==
836 12:17:11.724573 Dram Type= 6, Freq= 0, CH_0, rank 0
837 12:17:11.732103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 12:17:11.732220 ==
839 12:17:11.735345 Write leveling (Byte 0): 30 => 30
840 12:17:11.735457 Write leveling (Byte 1): 30 => 30
841 12:17:11.739051 DramcWriteLeveling(PI) end<-----
842 12:17:11.739160
843 12:17:11.739260 ==
844 12:17:11.742045 Dram Type= 6, Freq= 0, CH_0, rank 0
845 12:17:11.748646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 12:17:11.748767 ==
847 12:17:11.748841 [Gating] SW mode calibration
848 12:17:11.756148 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 12:17:11.763921 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 12:17:11.767244 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 12:17:11.770785 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
852 12:17:11.774113 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 12:17:11.780492 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:17:11.784986 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:17:11.787898 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:17:11.794772 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:17:11.798033 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:17:11.801573 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:17:11.808089 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:17:11.811303 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:17:11.814294 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:17:11.821222 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:17:11.824448 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:17:11.827606 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:17:11.834515 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:17:11.837849 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 12:17:11.841070 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
868 12:17:11.844540 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
869 12:17:11.850818 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:17:11.854224 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:17:11.857615 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 12:17:11.864353 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:17:11.867646 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:17:11.870950 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:17:11.877423 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
876 12:17:11.880657 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
877 12:17:11.884151 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
878 12:17:11.890452 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 12:17:11.894241 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 12:17:11.897158 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 12:17:11.904019 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:17:11.907371 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:17:11.910909 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
884 12:17:11.917397 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
885 12:17:11.920390 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
886 12:17:11.923916 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 12:17:11.930588 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 12:17:11.933818 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 12:17:11.936985 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:17:11.943596 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:17:11.946852 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
892 12:17:11.950065 0 11 8 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
893 12:17:11.957235 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
894 12:17:11.960107 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 12:17:11.963434 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 12:17:11.970234 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 12:17:11.973514 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:17:11.976956 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:17:11.983351 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
900 12:17:11.986329 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
901 12:17:11.989635 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:17:11.996860 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:17:11.999795 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:17:12.003293 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:17:12.010027 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:17:12.013037 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:17:12.016625 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:17:12.023028 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:17:12.026487 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:17:12.029469 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:17:12.036355 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:17:12.039739 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:17:12.043041 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:17:12.049470 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:17:12.052572 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 12:17:12.055813 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
917 12:17:12.059167 Total UI for P1: 0, mck2ui 16
918 12:17:12.062439 best dqsien dly found for B0: ( 0, 14, 4)
919 12:17:12.069231 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 12:17:12.069327 Total UI for P1: 0, mck2ui 16
921 12:17:12.075963 best dqsien dly found for B1: ( 0, 14, 10)
922 12:17:12.079304 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
923 12:17:12.082792 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
924 12:17:12.082880
925 12:17:12.085683 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
926 12:17:12.089413 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
927 12:17:12.092623 [Gating] SW calibration Done
928 12:17:12.092712 ==
929 12:17:12.096000 Dram Type= 6, Freq= 0, CH_0, rank 0
930 12:17:12.098999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 12:17:12.099088 ==
932 12:17:12.102404 RX Vref Scan: 0
933 12:17:12.102501
934 12:17:12.102578 RX Vref 0 -> 0, step: 1
935 12:17:12.102647
936 12:17:12.105690 RX Delay -130 -> 252, step: 16
937 12:17:12.109079 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
938 12:17:12.115384 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 12:17:12.118905 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
940 12:17:12.122252 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
941 12:17:12.125731 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 12:17:12.129086 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 12:17:12.135504 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 12:17:12.138873 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 12:17:12.142365 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 12:17:12.145624 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 12:17:12.148863 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
948 12:17:12.155431 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 12:17:12.158916 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
950 12:17:12.162063 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 12:17:12.165524 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 12:17:12.172191 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 12:17:12.172322 ==
954 12:17:12.175146 Dram Type= 6, Freq= 0, CH_0, rank 0
955 12:17:12.178500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 12:17:12.178617 ==
957 12:17:12.178715 DQS Delay:
958 12:17:12.182240 DQS0 = 0, DQS1 = 0
959 12:17:12.182363 DQM Delay:
960 12:17:12.185183 DQM0 = 90, DQM1 = 80
961 12:17:12.185300 DQ Delay:
962 12:17:12.188700 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
963 12:17:12.191920 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
964 12:17:12.195259 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
965 12:17:12.198749 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
966 12:17:12.198864
967 12:17:12.199007
968 12:17:12.199111 ==
969 12:17:12.202140 Dram Type= 6, Freq= 0, CH_0, rank 0
970 12:17:12.205125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 12:17:12.205240 ==
972 12:17:12.205338
973 12:17:12.208487
974 12:17:12.208589 TX Vref Scan disable
975 12:17:12.211892 == TX Byte 0 ==
976 12:17:12.215168 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
977 12:17:12.218564 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
978 12:17:12.222142 == TX Byte 1 ==
979 12:17:12.225146 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 12:17:12.228515 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 12:17:12.228628 ==
982 12:17:12.231960 Dram Type= 6, Freq= 0, CH_0, rank 0
983 12:17:12.238366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 12:17:12.238475 ==
985 12:17:12.249937 TX Vref=22, minBit 13, minWin=26, winSum=441
986 12:17:12.253271 TX Vref=24, minBit 6, minWin=27, winSum=442
987 12:17:12.256599 TX Vref=26, minBit 10, minWin=27, winSum=449
988 12:17:12.260392 TX Vref=28, minBit 8, minWin=27, winSum=450
989 12:17:12.263548 TX Vref=30, minBit 5, minWin=28, winSum=456
990 12:17:12.269907 TX Vref=32, minBit 10, minWin=27, winSum=456
991 12:17:12.273463 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 30
992 12:17:12.273556
993 12:17:12.277014 Final TX Range 1 Vref 30
994 12:17:12.277101
995 12:17:12.277169 ==
996 12:17:12.280217 Dram Type= 6, Freq= 0, CH_0, rank 0
997 12:17:12.283478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 12:17:12.283564 ==
999 12:17:12.286692
1000 12:17:12.286776
1001 12:17:12.286864 TX Vref Scan disable
1002 12:17:12.290129 == TX Byte 0 ==
1003 12:17:12.293497 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1004 12:17:12.300478 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1005 12:17:12.300599 == TX Byte 1 ==
1006 12:17:12.303471 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1007 12:17:12.310279 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1008 12:17:12.310370
1009 12:17:12.310438 [DATLAT]
1010 12:17:12.310500 Freq=800, CH0 RK0
1011 12:17:12.310565
1012 12:17:12.313713 DATLAT Default: 0xa
1013 12:17:12.313798 0, 0xFFFF, sum = 0
1014 12:17:12.317148 1, 0xFFFF, sum = 0
1015 12:17:12.317271 2, 0xFFFF, sum = 0
1016 12:17:12.320071 3, 0xFFFF, sum = 0
1017 12:17:12.320190 4, 0xFFFF, sum = 0
1018 12:17:12.323489 5, 0xFFFF, sum = 0
1019 12:17:12.327009 6, 0xFFFF, sum = 0
1020 12:17:12.327092 7, 0xFFFF, sum = 0
1021 12:17:12.330382 8, 0xFFFF, sum = 0
1022 12:17:12.330459 9, 0x0, sum = 1
1023 12:17:12.330524 10, 0x0, sum = 2
1024 12:17:12.333773 11, 0x0, sum = 3
1025 12:17:12.333872 12, 0x0, sum = 4
1026 12:17:12.336620 best_step = 10
1027 12:17:12.336730
1028 12:17:12.336851 ==
1029 12:17:12.340173 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 12:17:12.343147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 12:17:12.343236 ==
1032 12:17:12.346636 RX Vref Scan: 1
1033 12:17:12.346761
1034 12:17:12.349946 Set Vref Range= 32 -> 127
1035 12:17:12.350070
1036 12:17:12.350195 RX Vref 32 -> 127, step: 1
1037 12:17:12.350295
1038 12:17:12.353227 RX Delay -95 -> 252, step: 8
1039 12:17:12.353342
1040 12:17:12.356526 Set Vref, RX VrefLevel [Byte0]: 32
1041 12:17:12.359992 [Byte1]: 32
1042 12:17:12.360077
1043 12:17:12.363228 Set Vref, RX VrefLevel [Byte0]: 33
1044 12:17:12.366631 [Byte1]: 33
1045 12:17:12.370498
1046 12:17:12.370602 Set Vref, RX VrefLevel [Byte0]: 34
1047 12:17:12.373667 [Byte1]: 34
1048 12:17:12.378271
1049 12:17:12.378352 Set Vref, RX VrefLevel [Byte0]: 35
1050 12:17:12.381290 [Byte1]: 35
1051 12:17:12.385824
1052 12:17:12.385910 Set Vref, RX VrefLevel [Byte0]: 36
1053 12:17:12.388987 [Byte1]: 36
1054 12:17:12.393361
1055 12:17:12.393446 Set Vref, RX VrefLevel [Byte0]: 37
1056 12:17:12.396726 [Byte1]: 37
1057 12:17:12.401470
1058 12:17:12.401556 Set Vref, RX VrefLevel [Byte0]: 38
1059 12:17:12.404727 [Byte1]: 38
1060 12:17:12.408625
1061 12:17:12.408710 Set Vref, RX VrefLevel [Byte0]: 39
1062 12:17:12.412114 [Byte1]: 39
1063 12:17:12.415966
1064 12:17:12.416054 Set Vref, RX VrefLevel [Byte0]: 40
1065 12:17:12.419839 [Byte1]: 40
1066 12:17:12.423655
1067 12:17:12.423751 Set Vref, RX VrefLevel [Byte0]: 41
1068 12:17:12.427159 [Byte1]: 41
1069 12:17:12.431587
1070 12:17:12.431682 Set Vref, RX VrefLevel [Byte0]: 42
1071 12:17:12.434826 [Byte1]: 42
1072 12:17:12.439102
1073 12:17:12.439201 Set Vref, RX VrefLevel [Byte0]: 43
1074 12:17:12.442522 [Byte1]: 43
1075 12:17:12.446916
1076 12:17:12.447005 Set Vref, RX VrefLevel [Byte0]: 44
1077 12:17:12.449959 [Byte1]: 44
1078 12:17:12.454532
1079 12:17:12.454619 Set Vref, RX VrefLevel [Byte0]: 45
1080 12:17:12.457795 [Byte1]: 45
1081 12:17:12.461522
1082 12:17:12.461609 Set Vref, RX VrefLevel [Byte0]: 46
1083 12:17:12.464781 [Byte1]: 46
1084 12:17:12.469545
1085 12:17:12.469647 Set Vref, RX VrefLevel [Byte0]: 47
1086 12:17:12.472495 [Byte1]: 47
1087 12:17:12.476858
1088 12:17:12.477016 Set Vref, RX VrefLevel [Byte0]: 48
1089 12:17:12.480151 [Byte1]: 48
1090 12:17:12.484461
1091 12:17:12.484541 Set Vref, RX VrefLevel [Byte0]: 49
1092 12:17:12.487603 [Byte1]: 49
1093 12:17:12.492282
1094 12:17:12.492402 Set Vref, RX VrefLevel [Byte0]: 50
1095 12:17:12.495365 [Byte1]: 50
1096 12:17:12.499763
1097 12:17:12.499848 Set Vref, RX VrefLevel [Byte0]: 51
1098 12:17:12.503133 [Byte1]: 51
1099 12:17:12.507154
1100 12:17:12.507240 Set Vref, RX VrefLevel [Byte0]: 52
1101 12:17:12.510540 [Byte1]: 52
1102 12:17:12.515055
1103 12:17:12.515189 Set Vref, RX VrefLevel [Byte0]: 53
1104 12:17:12.518028 [Byte1]: 53
1105 12:17:12.522387
1106 12:17:12.522487 Set Vref, RX VrefLevel [Byte0]: 54
1107 12:17:12.525810 [Byte1]: 54
1108 12:17:12.530178
1109 12:17:12.530262 Set Vref, RX VrefLevel [Byte0]: 55
1110 12:17:12.533140 [Byte1]: 55
1111 12:17:12.537463
1112 12:17:12.537548 Set Vref, RX VrefLevel [Byte0]: 56
1113 12:17:12.540898 [Byte1]: 56
1114 12:17:12.545212
1115 12:17:12.545295 Set Vref, RX VrefLevel [Byte0]: 57
1116 12:17:12.548591 [Byte1]: 57
1117 12:17:12.553088
1118 12:17:12.553170 Set Vref, RX VrefLevel [Byte0]: 58
1119 12:17:12.556405 [Byte1]: 58
1120 12:17:12.560739
1121 12:17:12.560856 Set Vref, RX VrefLevel [Byte0]: 59
1122 12:17:12.563934 [Byte1]: 59
1123 12:17:12.568198
1124 12:17:12.568281 Set Vref, RX VrefLevel [Byte0]: 60
1125 12:17:12.571512 [Byte1]: 60
1126 12:17:12.575507
1127 12:17:12.575626 Set Vref, RX VrefLevel [Byte0]: 61
1128 12:17:12.579059 [Byte1]: 61
1129 12:17:12.583288
1130 12:17:12.583443 Set Vref, RX VrefLevel [Byte0]: 62
1131 12:17:12.586662 [Byte1]: 62
1132 12:17:12.590941
1133 12:17:12.591017 Set Vref, RX VrefLevel [Byte0]: 63
1134 12:17:12.594223 [Byte1]: 63
1135 12:17:12.598294
1136 12:17:12.598376 Set Vref, RX VrefLevel [Byte0]: 64
1137 12:17:12.601954 [Byte1]: 64
1138 12:17:12.605844
1139 12:17:12.605949 Set Vref, RX VrefLevel [Byte0]: 65
1140 12:17:12.612559 [Byte1]: 65
1141 12:17:12.612663
1142 12:17:12.615977 Set Vref, RX VrefLevel [Byte0]: 66
1143 12:17:12.618981 [Byte1]: 66
1144 12:17:12.619080
1145 12:17:12.622375 Set Vref, RX VrefLevel [Byte0]: 67
1146 12:17:12.625823 [Byte1]: 67
1147 12:17:12.625922
1148 12:17:12.629279 Set Vref, RX VrefLevel [Byte0]: 68
1149 12:17:12.632614 [Byte1]: 68
1150 12:17:12.636529
1151 12:17:12.636628 Set Vref, RX VrefLevel [Byte0]: 69
1152 12:17:12.640001 [Byte1]: 69
1153 12:17:12.644197
1154 12:17:12.644311 Set Vref, RX VrefLevel [Byte0]: 70
1155 12:17:12.647175 [Byte1]: 70
1156 12:17:12.651542
1157 12:17:12.651642 Set Vref, RX VrefLevel [Byte0]: 71
1158 12:17:12.654951 [Byte1]: 71
1159 12:17:12.659341
1160 12:17:12.659454 Set Vref, RX VrefLevel [Byte0]: 72
1161 12:17:12.662811 [Byte1]: 72
1162 12:17:12.667101
1163 12:17:12.667217 Set Vref, RX VrefLevel [Byte0]: 73
1164 12:17:12.670321 [Byte1]: 73
1165 12:17:12.674507
1166 12:17:12.674594 Set Vref, RX VrefLevel [Byte0]: 74
1167 12:17:12.677911 [Byte1]: 74
1168 12:17:12.681829
1169 12:17:12.681916 Final RX Vref Byte 0 = 61 to rank0
1170 12:17:12.685242 Final RX Vref Byte 1 = 60 to rank0
1171 12:17:12.688646 Final RX Vref Byte 0 = 61 to rank1
1172 12:17:12.692068 Final RX Vref Byte 1 = 60 to rank1==
1173 12:17:12.695400 Dram Type= 6, Freq= 0, CH_0, rank 0
1174 12:17:12.702075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1175 12:17:12.702164 ==
1176 12:17:12.702231 DQS Delay:
1177 12:17:12.702294 DQS0 = 0, DQS1 = 0
1178 12:17:12.705239 DQM Delay:
1179 12:17:12.705339 DQM0 = 93, DQM1 = 81
1180 12:17:12.708445 DQ Delay:
1181 12:17:12.712119 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1182 12:17:12.715180 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1183 12:17:12.718653 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1184 12:17:12.722255 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1185 12:17:12.722365
1186 12:17:12.722459
1187 12:17:12.728651 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
1188 12:17:12.732062 CH0 RK0: MR19=606, MR18=3C36
1189 12:17:12.738780 CH0_RK0: MR19=0x606, MR18=0x3C36, DQSOSC=394, MR23=63, INC=95, DEC=63
1190 12:17:12.738867
1191 12:17:12.741691 ----->DramcWriteLeveling(PI) begin...
1192 12:17:12.741780 ==
1193 12:17:12.745078 Dram Type= 6, Freq= 0, CH_0, rank 1
1194 12:17:12.748396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1195 12:17:12.748502 ==
1196 12:17:12.751876 Write leveling (Byte 0): 32 => 32
1197 12:17:12.755322 Write leveling (Byte 1): 32 => 32
1198 12:17:12.758198 DramcWriteLeveling(PI) end<-----
1199 12:17:12.758302
1200 12:17:12.758398 ==
1201 12:17:12.761673 Dram Type= 6, Freq= 0, CH_0, rank 1
1202 12:17:12.765125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1203 12:17:12.765228 ==
1204 12:17:12.768525 [Gating] SW mode calibration
1205 12:17:12.775072 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1206 12:17:12.781723 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1207 12:17:12.785039 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1208 12:17:12.791333 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1209 12:17:12.794773 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 12:17:12.798251 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 12:17:12.804811 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 12:17:12.808169 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 12:17:12.811451 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 12:17:12.814658 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 12:17:12.821357 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 12:17:12.865737 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:17:12.865886 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:17:12.866018 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:17:12.866308 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:17:12.866381 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:17:12.866446 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:17:12.866505 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:17:12.866563 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:17:12.866619 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1225 12:17:12.866675 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:17:12.909499 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:17:12.910056 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:17:12.910149 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:17:12.910396 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:17:12.910464 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:17:12.910526 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:17:12.910597 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1233 12:17:12.910659 0 9 8 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (0 0)
1234 12:17:12.911057 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 12:17:12.911321 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 12:17:12.945138 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 12:17:12.945461 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 12:17:12.945575 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 12:17:12.945639 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 12:17:12.945713 0 10 4 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
1241 12:17:12.945774 0 10 8 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
1242 12:17:12.945833 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:17:12.945890 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:17:12.949065 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:17:12.952466 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:17:12.955723 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:17:12.962080 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:17:12.965463 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1249 12:17:12.969033 0 11 8 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
1250 12:17:12.975677 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 12:17:12.979027 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 12:17:12.982189 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 12:17:12.989012 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 12:17:12.992593 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 12:17:12.996066 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 12:17:13.002283 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1257 12:17:13.006299 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1258 12:17:13.010072 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 12:17:13.013317 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 12:17:13.020455 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 12:17:13.023641 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 12:17:13.026678 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 12:17:13.030109 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 12:17:13.037317 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 12:17:13.040670 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 12:17:13.044247 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 12:17:13.050515 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 12:17:13.054435 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:17:13.057190 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:17:13.063804 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:17:13.067426 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:17:13.070972 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1273 12:17:13.077216 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1274 12:17:13.077344 Total UI for P1: 0, mck2ui 16
1275 12:17:13.080675 best dqsien dly found for B1: ( 0, 14, 6)
1276 12:17:13.087307 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 12:17:13.090308 Total UI for P1: 0, mck2ui 16
1278 12:17:13.093832 best dqsien dly found for B0: ( 0, 14, 6)
1279 12:17:13.097132 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1280 12:17:13.100648 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1281 12:17:13.100863
1282 12:17:13.104156 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1283 12:17:13.107077 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1284 12:17:13.110289 [Gating] SW calibration Done
1285 12:17:13.110516 ==
1286 12:17:13.113792 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 12:17:13.116912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 12:17:13.117102 ==
1289 12:17:13.120274 RX Vref Scan: 0
1290 12:17:13.120373
1291 12:17:13.123600 RX Vref 0 -> 0, step: 1
1292 12:17:13.123698
1293 12:17:13.123788 RX Delay -130 -> 252, step: 16
1294 12:17:13.129918 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1295 12:17:13.133503 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1296 12:17:13.136637 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1297 12:17:13.140547 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1298 12:17:13.143441 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1299 12:17:13.150242 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1300 12:17:13.153660 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1301 12:17:13.156932 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1302 12:17:13.159968 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1303 12:17:13.163351 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1304 12:17:13.170312 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1305 12:17:13.173603 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1306 12:17:13.176546 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1307 12:17:13.179941 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1308 12:17:13.186764 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1309 12:17:13.190090 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1310 12:17:13.190215 ==
1311 12:17:13.193500 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 12:17:13.196716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 12:17:13.196872 ==
1314 12:17:13.196983 DQS Delay:
1315 12:17:13.200078 DQS0 = 0, DQS1 = 0
1316 12:17:13.200280 DQM Delay:
1317 12:17:13.203648 DQM0 = 90, DQM1 = 81
1318 12:17:13.203803 DQ Delay:
1319 12:17:13.206592 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1320 12:17:13.210258 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1321 12:17:13.213084 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1322 12:17:13.216701 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1323 12:17:13.216994
1324 12:17:13.217220
1325 12:17:13.217409 ==
1326 12:17:13.219912 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 12:17:13.223347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 12:17:13.226885 ==
1329 12:17:13.227280
1330 12:17:13.227690
1331 12:17:13.228142 TX Vref Scan disable
1332 12:17:13.230338 == TX Byte 0 ==
1333 12:17:13.233339 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1334 12:17:13.237057 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1335 12:17:13.240194 == TX Byte 1 ==
1336 12:17:13.243421 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1337 12:17:13.246823 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1338 12:17:13.250014 ==
1339 12:17:13.253228 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 12:17:13.256568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 12:17:13.257237 ==
1342 12:17:13.268834 TX Vref=22, minBit 8, minWin=27, winSum=450
1343 12:17:13.272147 TX Vref=24, minBit 1, minWin=27, winSum=447
1344 12:17:13.275613 TX Vref=26, minBit 1, minWin=28, winSum=454
1345 12:17:13.279073 TX Vref=28, minBit 4, minWin=28, winSum=456
1346 12:17:13.282519 TX Vref=30, minBit 14, minWin=27, winSum=456
1347 12:17:13.285789 TX Vref=32, minBit 8, minWin=28, winSum=457
1348 12:17:13.292602 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 32
1349 12:17:13.293182
1350 12:17:13.295778 Final TX Range 1 Vref 32
1351 12:17:13.296363
1352 12:17:13.296914 ==
1353 12:17:13.299055 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 12:17:13.302384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 12:17:13.302967 ==
1356 12:17:13.305387
1357 12:17:13.306026
1358 12:17:13.306592 TX Vref Scan disable
1359 12:17:13.308872 == TX Byte 0 ==
1360 12:17:13.312372 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1361 12:17:13.318978 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1362 12:17:13.319626 == TX Byte 1 ==
1363 12:17:13.322472 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1364 12:17:13.328876 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1365 12:17:13.329517
1366 12:17:13.330096 [DATLAT]
1367 12:17:13.330698 Freq=800, CH0 RK1
1368 12:17:13.331277
1369 12:17:13.332433 DATLAT Default: 0xa
1370 12:17:13.333029 0, 0xFFFF, sum = 0
1371 12:17:13.335285 1, 0xFFFF, sum = 0
1372 12:17:13.335700 2, 0xFFFF, sum = 0
1373 12:17:13.338689 3, 0xFFFF, sum = 0
1374 12:17:13.342183 4, 0xFFFF, sum = 0
1375 12:17:13.342568 5, 0xFFFF, sum = 0
1376 12:17:13.345535 6, 0xFFFF, sum = 0
1377 12:17:13.345904 7, 0xFFFF, sum = 0
1378 12:17:13.348973 8, 0xFFFF, sum = 0
1379 12:17:13.349382 9, 0x0, sum = 1
1380 12:17:13.352124 10, 0x0, sum = 2
1381 12:17:13.352506 11, 0x0, sum = 3
1382 12:17:13.352868 12, 0x0, sum = 4
1383 12:17:13.355329 best_step = 10
1384 12:17:13.355724
1385 12:17:13.356086 ==
1386 12:17:13.358386 Dram Type= 6, Freq= 0, CH_0, rank 1
1387 12:17:13.362141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 12:17:13.362467 ==
1389 12:17:13.365446 RX Vref Scan: 0
1390 12:17:13.365755
1391 12:17:13.366002 RX Vref 0 -> 0, step: 1
1392 12:17:13.368426
1393 12:17:13.368861 RX Delay -79 -> 252, step: 8
1394 12:17:13.375185 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1395 12:17:13.378588 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1396 12:17:13.382121 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1397 12:17:13.385551 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1398 12:17:13.388868 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1399 12:17:13.395216 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1400 12:17:13.398633 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1401 12:17:13.402020 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1402 12:17:13.405185 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1403 12:17:13.408570 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1404 12:17:13.415435 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1405 12:17:13.418813 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1406 12:17:13.421846 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1407 12:17:13.425220 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1408 12:17:13.432022 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1409 12:17:13.435411 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1410 12:17:13.435833 ==
1411 12:17:13.438874 Dram Type= 6, Freq= 0, CH_0, rank 1
1412 12:17:13.441867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 12:17:13.442471 ==
1414 12:17:13.442981 DQS Delay:
1415 12:17:13.445275 DQS0 = 0, DQS1 = 0
1416 12:17:13.445814 DQM Delay:
1417 12:17:13.449002 DQM0 = 90, DQM1 = 82
1418 12:17:13.449688 DQ Delay:
1419 12:17:13.452227 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1420 12:17:13.455244 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1421 12:17:13.458694 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1422 12:17:13.462103 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1423 12:17:13.462514
1424 12:17:13.462849
1425 12:17:13.472054 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f1a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1426 12:17:13.472485 CH0 RK1: MR19=606, MR18=3F1A
1427 12:17:13.478897 CH0_RK1: MR19=0x606, MR18=0x3F1A, DQSOSC=393, MR23=63, INC=95, DEC=63
1428 12:17:13.482394 [RxdqsGatingPostProcess] freq 800
1429 12:17:13.488878 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1430 12:17:13.491756 Pre-setting of DQS Precalculation
1431 12:17:13.495295 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1432 12:17:13.495713 ==
1433 12:17:13.498789 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 12:17:13.504938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 12:17:13.505395 ==
1436 12:17:13.508235 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1437 12:17:13.514828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1438 12:17:13.524212 [CA 0] Center 36 (6~67) winsize 62
1439 12:17:13.527555 [CA 1] Center 36 (6~67) winsize 62
1440 12:17:13.530972 [CA 2] Center 35 (5~65) winsize 61
1441 12:17:13.534149 [CA 3] Center 34 (4~65) winsize 62
1442 12:17:13.537656 [CA 4] Center 34 (4~65) winsize 62
1443 12:17:13.540618 [CA 5] Center 34 (4~64) winsize 61
1444 12:17:13.541089
1445 12:17:13.544028 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1446 12:17:13.544446
1447 12:17:13.547291 [CATrainingPosCal] consider 1 rank data
1448 12:17:13.550747 u2DelayCellTimex100 = 270/100 ps
1449 12:17:13.554035 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1450 12:17:13.560560 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1451 12:17:13.563750 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1452 12:17:13.567226 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1453 12:17:13.570344 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 12:17:13.573403 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1455 12:17:13.573485
1456 12:17:13.576651 CA PerBit enable=1, Macro0, CA PI delay=34
1457 12:17:13.576750
1458 12:17:13.579906 [CBTSetCACLKResult] CA Dly = 34
1459 12:17:13.579989 CS Dly: 5 (0~36)
1460 12:17:13.583257 ==
1461 12:17:13.586877 Dram Type= 6, Freq= 0, CH_1, rank 1
1462 12:17:13.590341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 12:17:13.590426 ==
1464 12:17:13.593204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1465 12:17:13.599941 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1466 12:17:13.609997 [CA 0] Center 37 (7~67) winsize 61
1467 12:17:13.613222 [CA 1] Center 37 (6~68) winsize 63
1468 12:17:13.616505 [CA 2] Center 35 (5~66) winsize 62
1469 12:17:13.619864 [CA 3] Center 34 (4~65) winsize 62
1470 12:17:13.623343 [CA 4] Center 35 (5~65) winsize 61
1471 12:17:13.626355 [CA 5] Center 34 (4~65) winsize 62
1472 12:17:13.626427
1473 12:17:13.629732 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1474 12:17:13.629825
1475 12:17:13.633033 [CATrainingPosCal] consider 2 rank data
1476 12:17:13.636305 u2DelayCellTimex100 = 270/100 ps
1477 12:17:13.639703 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1478 12:17:13.646418 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1479 12:17:13.649845 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1480 12:17:13.652929 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1481 12:17:13.656189 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1482 12:17:13.659469 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1483 12:17:13.659542
1484 12:17:13.663056 CA PerBit enable=1, Macro0, CA PI delay=34
1485 12:17:13.663137
1486 12:17:13.666775 [CBTSetCACLKResult] CA Dly = 34
1487 12:17:13.666853 CS Dly: 5 (0~37)
1488 12:17:13.666916
1489 12:17:13.669750 ----->DramcWriteLeveling(PI) begin...
1490 12:17:13.673563 ==
1491 12:17:13.673666 Dram Type= 6, Freq= 0, CH_1, rank 0
1492 12:17:13.680573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 12:17:13.680681 ==
1494 12:17:13.683858 Write leveling (Byte 0): 27 => 27
1495 12:17:13.683944 Write leveling (Byte 1): 31 => 31
1496 12:17:13.687519 DramcWriteLeveling(PI) end<-----
1497 12:17:13.687591
1498 12:17:13.687652 ==
1499 12:17:13.691236 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 12:17:13.695284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 12:17:13.695399 ==
1502 12:17:13.698691 [Gating] SW mode calibration
1503 12:17:13.705628 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1504 12:17:13.712221 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1505 12:17:13.715605 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1506 12:17:13.719003 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1507 12:17:13.725396 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 12:17:13.728871 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 12:17:13.732250 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 12:17:13.738657 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 12:17:13.742252 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 12:17:13.745644 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 12:17:13.752252 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:17:13.755631 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:17:13.758633 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:17:13.765284 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:17:13.768671 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:17:13.772127 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:17:13.778899 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:17:13.782220 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:17:13.785439 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1522 12:17:13.791759 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1523 12:17:13.795189 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:17:13.798786 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:17:13.802064 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:17:13.808798 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:17:13.811806 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:17:13.815287 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:17:13.821961 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:17:13.825289 0 9 4 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
1531 12:17:13.828783 0 9 8 | B1->B0 | 3131 3333 | 1 1 | (1 1) (1 1)
1532 12:17:13.835083 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 12:17:13.838519 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 12:17:13.841877 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 12:17:13.848692 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 12:17:13.852184 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 12:17:13.855257 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 12:17:13.862063 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
1539 12:17:13.865451 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:17:13.868504 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:17:13.875160 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:17:13.878954 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:17:13.882188 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:17:13.888995 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:17:13.892274 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:17:13.895580 0 11 4 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 0)
1547 12:17:13.902228 0 11 8 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
1548 12:17:13.905447 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 12:17:13.908663 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 12:17:13.915272 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 12:17:13.918698 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 12:17:13.921930 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 12:17:13.925308 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 12:17:13.931872 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1555 12:17:13.935400 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 12:17:13.938910 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 12:17:13.945281 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 12:17:13.948671 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 12:17:13.951942 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 12:17:13.958339 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 12:17:13.961816 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 12:17:13.965299 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 12:17:13.971870 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 12:17:13.975131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 12:17:13.978557 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:17:13.984952 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:17:13.988408 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:17:13.991654 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:17:13.998399 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1570 12:17:14.001774 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1571 12:17:14.004959 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 12:17:14.008564 Total UI for P1: 0, mck2ui 16
1573 12:17:14.011805 best dqsien dly found for B0: ( 0, 14, 2)
1574 12:17:14.014992 Total UI for P1: 0, mck2ui 16
1575 12:17:14.018437 best dqsien dly found for B1: ( 0, 14, 6)
1576 12:17:14.021394 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1577 12:17:14.025131 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1578 12:17:14.025734
1579 12:17:14.031184 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1580 12:17:14.034623 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1581 12:17:14.035068 [Gating] SW calibration Done
1582 12:17:14.037964 ==
1583 12:17:14.041354 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 12:17:14.044870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 12:17:14.045325 ==
1586 12:17:14.045696 RX Vref Scan: 0
1587 12:17:14.046130
1588 12:17:14.047820 RX Vref 0 -> 0, step: 1
1589 12:17:14.048309
1590 12:17:14.051250 RX Delay -130 -> 252, step: 16
1591 12:17:14.054567 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1592 12:17:14.057885 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1593 12:17:14.064528 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1594 12:17:14.067954 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1595 12:17:14.071024 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1596 12:17:14.074435 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1597 12:17:14.077702 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1598 12:17:14.084008 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1599 12:17:14.087601 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1600 12:17:14.091209 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1601 12:17:14.094168 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1602 12:17:14.097206 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1603 12:17:14.104138 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1604 12:17:14.107114 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1605 12:17:14.110628 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1606 12:17:14.113953 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1607 12:17:14.114092 ==
1608 12:17:14.117128 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 12:17:14.123945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 12:17:14.124092 ==
1611 12:17:14.124190 DQS Delay:
1612 12:17:14.124250 DQS0 = 0, DQS1 = 0
1613 12:17:14.127208 DQM Delay:
1614 12:17:14.127291 DQM0 = 91, DQM1 = 82
1615 12:17:14.130384 DQ Delay:
1616 12:17:14.133938 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1617 12:17:14.137244 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =93
1618 12:17:14.140653 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1619 12:17:14.143651 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1620 12:17:14.143734
1621 12:17:14.143798
1622 12:17:14.143859 ==
1623 12:17:14.147458 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 12:17:14.150910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 12:17:14.151333 ==
1626 12:17:14.151672
1627 12:17:14.151976
1628 12:17:14.153952 TX Vref Scan disable
1629 12:17:14.154373 == TX Byte 0 ==
1630 12:17:14.160652 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1631 12:17:14.164055 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1632 12:17:14.164639 == TX Byte 1 ==
1633 12:17:14.170506 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1634 12:17:14.174128 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1635 12:17:14.174548 ==
1636 12:17:14.176955 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 12:17:14.180266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 12:17:14.180688 ==
1639 12:17:14.194958 TX Vref=22, minBit 8, minWin=27, winSum=447
1640 12:17:14.198267 TX Vref=24, minBit 8, minWin=27, winSum=449
1641 12:17:14.201821 TX Vref=26, minBit 8, minWin=27, winSum=453
1642 12:17:14.204520 TX Vref=28, minBit 15, minWin=27, winSum=458
1643 12:17:14.207983 TX Vref=30, minBit 8, minWin=27, winSum=457
1644 12:17:14.214683 TX Vref=32, minBit 8, minWin=27, winSum=455
1645 12:17:14.218054 [TxChooseVref] Worse bit 15, Min win 27, Win sum 458, Final Vref 28
1646 12:17:14.218149
1647 12:17:14.221672 Final TX Range 1 Vref 28
1648 12:17:14.221877
1649 12:17:14.222007 ==
1650 12:17:14.224746 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 12:17:14.227813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 12:17:14.230902 ==
1653 12:17:14.231062
1654 12:17:14.231200
1655 12:17:14.231325 TX Vref Scan disable
1656 12:17:14.234606 == TX Byte 0 ==
1657 12:17:14.237995 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1658 12:17:14.244638 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1659 12:17:14.244819 == TX Byte 1 ==
1660 12:17:14.248036 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1661 12:17:14.251926 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1662 12:17:14.252132
1663 12:17:14.255359 [DATLAT]
1664 12:17:14.255449 Freq=800, CH1 RK0
1665 12:17:14.255520
1666 12:17:14.258598 DATLAT Default: 0xa
1667 12:17:14.258727 0, 0xFFFF, sum = 0
1668 12:17:14.261991 1, 0xFFFF, sum = 0
1669 12:17:14.262067 2, 0xFFFF, sum = 0
1670 12:17:14.265217 3, 0xFFFF, sum = 0
1671 12:17:14.265306 4, 0xFFFF, sum = 0
1672 12:17:14.268657 5, 0xFFFF, sum = 0
1673 12:17:14.268755 6, 0xFFFF, sum = 0
1674 12:17:14.271613 7, 0xFFFF, sum = 0
1675 12:17:14.271724 8, 0xFFFF, sum = 0
1676 12:17:14.275152 9, 0x0, sum = 1
1677 12:17:14.275266 10, 0x0, sum = 2
1678 12:17:14.278516 11, 0x0, sum = 3
1679 12:17:14.278618 12, 0x0, sum = 4
1680 12:17:14.281864 best_step = 10
1681 12:17:14.281936
1682 12:17:14.282005 ==
1683 12:17:14.285203 Dram Type= 6, Freq= 0, CH_1, rank 0
1684 12:17:14.288477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1685 12:17:14.288547 ==
1686 12:17:14.291425 RX Vref Scan: 1
1687 12:17:14.291495
1688 12:17:14.291554 Set Vref Range= 32 -> 127
1689 12:17:14.291612
1690 12:17:14.294967 RX Vref 32 -> 127, step: 1
1691 12:17:14.295035
1692 12:17:14.298270 RX Delay -95 -> 252, step: 8
1693 12:17:14.298347
1694 12:17:14.301636 Set Vref, RX VrefLevel [Byte0]: 32
1695 12:17:14.304808 [Byte1]: 32
1696 12:17:14.304878
1697 12:17:14.308153 Set Vref, RX VrefLevel [Byte0]: 33
1698 12:17:14.311623 [Byte1]: 33
1699 12:17:14.315277
1700 12:17:14.315354 Set Vref, RX VrefLevel [Byte0]: 34
1701 12:17:14.318386 [Byte1]: 34
1702 12:17:14.322641
1703 12:17:14.322747 Set Vref, RX VrefLevel [Byte0]: 35
1704 12:17:14.325925 [Byte1]: 35
1705 12:17:14.330215
1706 12:17:14.330291 Set Vref, RX VrefLevel [Byte0]: 36
1707 12:17:14.333521 [Byte1]: 36
1708 12:17:14.337879
1709 12:17:14.337966 Set Vref, RX VrefLevel [Byte0]: 37
1710 12:17:14.341044 [Byte1]: 37
1711 12:17:14.345345
1712 12:17:14.345434 Set Vref, RX VrefLevel [Byte0]: 38
1713 12:17:14.348631 [Byte1]: 38
1714 12:17:14.352972
1715 12:17:14.353071 Set Vref, RX VrefLevel [Byte0]: 39
1716 12:17:14.356470 [Byte1]: 39
1717 12:17:14.360712
1718 12:17:14.360847 Set Vref, RX VrefLevel [Byte0]: 40
1719 12:17:14.364252 [Byte1]: 40
1720 12:17:14.368102
1721 12:17:14.368218 Set Vref, RX VrefLevel [Byte0]: 41
1722 12:17:14.371495 [Byte1]: 41
1723 12:17:14.376035
1724 12:17:14.376207 Set Vref, RX VrefLevel [Byte0]: 42
1725 12:17:14.379459 [Byte1]: 42
1726 12:17:14.383759
1727 12:17:14.383941 Set Vref, RX VrefLevel [Byte0]: 43
1728 12:17:14.386736 [Byte1]: 43
1729 12:17:14.391197
1730 12:17:14.391423 Set Vref, RX VrefLevel [Byte0]: 44
1731 12:17:14.394653 [Byte1]: 44
1732 12:17:14.399062
1733 12:17:14.399397 Set Vref, RX VrefLevel [Byte0]: 45
1734 12:17:14.405501 [Byte1]: 45
1735 12:17:14.406024
1736 12:17:14.408543 Set Vref, RX VrefLevel [Byte0]: 46
1737 12:17:14.412019 [Byte1]: 46
1738 12:17:14.412559
1739 12:17:14.415470 Set Vref, RX VrefLevel [Byte0]: 47
1740 12:17:14.418869 [Byte1]: 47
1741 12:17:14.419330
1742 12:17:14.421890 Set Vref, RX VrefLevel [Byte0]: 48
1743 12:17:14.425194 [Byte1]: 48
1744 12:17:14.429383
1745 12:17:14.429818 Set Vref, RX VrefLevel [Byte0]: 49
1746 12:17:14.432467 [Byte1]: 49
1747 12:17:14.437025
1748 12:17:14.437513 Set Vref, RX VrefLevel [Byte0]: 50
1749 12:17:14.440550 [Byte1]: 50
1750 12:17:14.444446
1751 12:17:14.444919 Set Vref, RX VrefLevel [Byte0]: 51
1752 12:17:14.448190 [Byte1]: 51
1753 12:17:14.452339
1754 12:17:14.452800 Set Vref, RX VrefLevel [Byte0]: 52
1755 12:17:14.455718 [Byte1]: 52
1756 12:17:14.459702
1757 12:17:14.460117 Set Vref, RX VrefLevel [Byte0]: 53
1758 12:17:14.463150 [Byte1]: 53
1759 12:17:14.467618
1760 12:17:14.468039 Set Vref, RX VrefLevel [Byte0]: 54
1761 12:17:14.470591 [Byte1]: 54
1762 12:17:14.475105
1763 12:17:14.475527 Set Vref, RX VrefLevel [Byte0]: 55
1764 12:17:14.478527 [Byte1]: 55
1765 12:17:14.482369
1766 12:17:14.482789 Set Vref, RX VrefLevel [Byte0]: 56
1767 12:17:14.485642 [Byte1]: 56
1768 12:17:14.490077
1769 12:17:14.490500 Set Vref, RX VrefLevel [Byte0]: 57
1770 12:17:14.493420 [Byte1]: 57
1771 12:17:14.497443
1772 12:17:14.497862 Set Vref, RX VrefLevel [Byte0]: 58
1773 12:17:14.500742 [Byte1]: 58
1774 12:17:14.505260
1775 12:17:14.505690 Set Vref, RX VrefLevel [Byte0]: 59
1776 12:17:14.508974 [Byte1]: 59
1777 12:17:14.513308
1778 12:17:14.513729 Set Vref, RX VrefLevel [Byte0]: 60
1779 12:17:14.516506 [Byte1]: 60
1780 12:17:14.520548
1781 12:17:14.521013 Set Vref, RX VrefLevel [Byte0]: 61
1782 12:17:14.523727 [Byte1]: 61
1783 12:17:14.528028
1784 12:17:14.528448 Set Vref, RX VrefLevel [Byte0]: 62
1785 12:17:14.531479 [Byte1]: 62
1786 12:17:14.535928
1787 12:17:14.536350 Set Vref, RX VrefLevel [Byte0]: 63
1788 12:17:14.539222 [Byte1]: 63
1789 12:17:14.543399
1790 12:17:14.543833 Set Vref, RX VrefLevel [Byte0]: 64
1791 12:17:14.546576 [Byte1]: 64
1792 12:17:14.551004
1793 12:17:14.551436 Set Vref, RX VrefLevel [Byte0]: 65
1794 12:17:14.553950 [Byte1]: 65
1795 12:17:14.558612
1796 12:17:14.559041 Set Vref, RX VrefLevel [Byte0]: 66
1797 12:17:14.561606 [Byte1]: 66
1798 12:17:14.565855
1799 12:17:14.566366 Set Vref, RX VrefLevel [Byte0]: 67
1800 12:17:14.569328 [Byte1]: 67
1801 12:17:14.573727
1802 12:17:14.574170 Set Vref, RX VrefLevel [Byte0]: 68
1803 12:17:14.576956 [Byte1]: 68
1804 12:17:14.581283
1805 12:17:14.581704 Set Vref, RX VrefLevel [Byte0]: 69
1806 12:17:14.584703 [Byte1]: 69
1807 12:17:14.589017
1808 12:17:14.589441 Set Vref, RX VrefLevel [Byte0]: 70
1809 12:17:14.592378 [Byte1]: 70
1810 12:17:14.596396
1811 12:17:14.596929 Set Vref, RX VrefLevel [Byte0]: 71
1812 12:17:14.599671 [Byte1]: 71
1813 12:17:14.604470
1814 12:17:14.604989 Set Vref, RX VrefLevel [Byte0]: 72
1815 12:17:14.607420 [Byte1]: 72
1816 12:17:14.611784
1817 12:17:14.612274 Set Vref, RX VrefLevel [Byte0]: 73
1818 12:17:14.614990 [Byte1]: 73
1819 12:17:14.619359
1820 12:17:14.619784 Set Vref, RX VrefLevel [Byte0]: 74
1821 12:17:14.622739 [Byte1]: 74
1822 12:17:14.627140
1823 12:17:14.627614 Final RX Vref Byte 0 = 51 to rank0
1824 12:17:14.630614 Final RX Vref Byte 1 = 63 to rank0
1825 12:17:14.633493 Final RX Vref Byte 0 = 51 to rank1
1826 12:17:14.636881 Final RX Vref Byte 1 = 63 to rank1==
1827 12:17:14.640229 Dram Type= 6, Freq= 0, CH_1, rank 0
1828 12:17:14.647032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1829 12:17:14.647463 ==
1830 12:17:14.647847 DQS Delay:
1831 12:17:14.648172 DQS0 = 0, DQS1 = 0
1832 12:17:14.650486 DQM Delay:
1833 12:17:14.650911 DQM0 = 92, DQM1 = 83
1834 12:17:14.653800 DQ Delay:
1835 12:17:14.657067 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1836 12:17:14.660069 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1837 12:17:14.663530 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1838 12:17:14.666776 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1839 12:17:14.667204
1840 12:17:14.667542
1841 12:17:14.673695 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1842 12:17:14.676587 CH1 RK0: MR19=606, MR18=2B48
1843 12:17:14.683449 CH1_RK0: MR19=0x606, MR18=0x2B48, DQSOSC=391, MR23=63, INC=96, DEC=64
1844 12:17:14.683937
1845 12:17:14.686842 ----->DramcWriteLeveling(PI) begin...
1846 12:17:14.687267 ==
1847 12:17:14.689953 Dram Type= 6, Freq= 0, CH_1, rank 1
1848 12:17:14.692789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 12:17:14.692888 ==
1850 12:17:14.696201 Write leveling (Byte 0): 29 => 29
1851 12:17:14.699813 Write leveling (Byte 1): 30 => 30
1852 12:17:14.703020 DramcWriteLeveling(PI) end<-----
1853 12:17:14.703116
1854 12:17:14.703192 ==
1855 12:17:14.706169 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 12:17:14.709624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 12:17:14.709733 ==
1858 12:17:14.713048 [Gating] SW mode calibration
1859 12:17:14.719486 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1860 12:17:14.725970 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1861 12:17:14.729419 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1862 12:17:14.735823 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1863 12:17:14.739194 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1864 12:17:14.742901 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 12:17:14.749548 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 12:17:14.752819 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 12:17:14.756014 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 12:17:14.762635 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 12:17:14.765763 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 12:17:14.768901 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:17:14.775507 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:17:14.778956 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:17:14.782691 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:17:14.789268 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:17:14.792628 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:17:14.796020 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:17:14.802451 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1878 12:17:14.805393 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1879 12:17:14.808902 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1880 12:17:14.815516 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:17:14.818955 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:17:14.822406 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:17:14.825357 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:17:14.831636 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:17:14.835006 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:17:14.838390 0 9 4 | B1->B0 | 2525 2424 | 1 1 | (0 0) (1 1)
1887 12:17:14.845238 0 9 8 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
1888 12:17:14.848195 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 12:17:14.851605 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 12:17:14.858396 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 12:17:14.861781 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 12:17:14.864969 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 12:17:14.871279 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 12:17:14.874824 0 10 4 | B1->B0 | 2f2f 3232 | 0 0 | (1 1) (1 1)
1895 12:17:14.877923 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1896 12:17:14.884688 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:17:14.888344 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:17:14.891886 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:17:14.898182 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:17:14.901567 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:17:14.904903 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:17:14.911300 0 11 4 | B1->B0 | 3232 2929 | 0 1 | (0 0) (0 0)
1903 12:17:14.915028 0 11 8 | B1->B0 | 4545 4040 | 0 1 | (0 0) (0 0)
1904 12:17:14.917925 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 12:17:14.925160 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 12:17:14.928411 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 12:17:14.931195 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 12:17:14.937817 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 12:17:14.941201 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 12:17:14.944654 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1911 12:17:14.951130 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 12:17:14.954558 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 12:17:14.957925 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 12:17:14.964870 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 12:17:14.967997 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 12:17:14.971268 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 12:17:14.977640 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 12:17:14.981360 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 12:17:14.984330 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 12:17:14.991083 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 12:17:14.994338 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 12:17:14.997646 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 12:17:15.003998 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 12:17:15.007324 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 12:17:15.010815 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 12:17:15.017589 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1927 12:17:15.020830 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 12:17:15.024181 Total UI for P1: 0, mck2ui 16
1929 12:17:15.027146 best dqsien dly found for B0: ( 0, 14, 4)
1930 12:17:15.030716 Total UI for P1: 0, mck2ui 16
1931 12:17:15.034038 best dqsien dly found for B1: ( 0, 14, 4)
1932 12:17:15.037177 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1933 12:17:15.040522 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1934 12:17:15.040980
1935 12:17:15.044062 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1936 12:17:15.047020 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1937 12:17:15.050342 [Gating] SW calibration Done
1938 12:17:15.050763 ==
1939 12:17:15.053806 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 12:17:15.056990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 12:17:15.057072 ==
1942 12:17:15.060279 RX Vref Scan: 0
1943 12:17:15.060361
1944 12:17:15.063294 RX Vref 0 -> 0, step: 1
1945 12:17:15.063393
1946 12:17:15.066697 RX Delay -130 -> 252, step: 16
1947 12:17:15.069991 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1948 12:17:15.073324 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1949 12:17:15.076428 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1950 12:17:15.080136 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1951 12:17:15.083166 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1952 12:17:15.090028 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1953 12:17:15.093631 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1954 12:17:15.096526 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1955 12:17:15.099801 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1956 12:17:15.103049 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1957 12:17:15.109724 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1958 12:17:15.113372 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1959 12:17:15.116361 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1960 12:17:15.119885 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1961 12:17:15.126495 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1962 12:17:15.130087 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1963 12:17:15.130492 ==
1964 12:17:15.133584 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 12:17:15.136683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 12:17:15.137296 ==
1967 12:17:15.140237 DQS Delay:
1968 12:17:15.140664 DQS0 = 0, DQS1 = 0
1969 12:17:15.141060 DQM Delay:
1970 12:17:15.143371 DQM0 = 90, DQM1 = 83
1971 12:17:15.143798 DQ Delay:
1972 12:17:15.146760 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1973 12:17:15.150429 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1974 12:17:15.153242 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1975 12:17:15.156685 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1976 12:17:15.157219
1977 12:17:15.157556
1978 12:17:15.157866 ==
1979 12:17:15.160124 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 12:17:15.166170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 12:17:15.166254 ==
1982 12:17:15.166321
1983 12:17:15.166382
1984 12:17:15.166442 TX Vref Scan disable
1985 12:17:15.169672 == TX Byte 0 ==
1986 12:17:15.173113 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1987 12:17:15.176199 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1988 12:17:15.179563 == TX Byte 1 ==
1989 12:17:15.182782 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1990 12:17:15.189564 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1991 12:17:15.189643 ==
1992 12:17:15.192563 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 12:17:15.196191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 12:17:15.196292 ==
1995 12:17:15.208688 TX Vref=22, minBit 13, minWin=27, winSum=452
1996 12:17:15.212193 TX Vref=24, minBit 8, minWin=27, winSum=454
1997 12:17:15.215645 TX Vref=26, minBit 13, minWin=27, winSum=456
1998 12:17:15.218561 TX Vref=28, minBit 8, minWin=28, winSum=460
1999 12:17:15.222047 TX Vref=30, minBit 8, minWin=28, winSum=463
2000 12:17:15.228678 TX Vref=32, minBit 8, minWin=28, winSum=460
2001 12:17:15.231975 [TxChooseVref] Worse bit 8, Min win 28, Win sum 463, Final Vref 30
2002 12:17:15.232068
2003 12:17:15.235328 Final TX Range 1 Vref 30
2004 12:17:15.235428
2005 12:17:15.235511 ==
2006 12:17:15.238407 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 12:17:15.241969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 12:17:15.245143 ==
2009 12:17:15.245280
2010 12:17:15.245388
2011 12:17:15.245489 TX Vref Scan disable
2012 12:17:15.248947 == TX Byte 0 ==
2013 12:17:15.251837 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2014 12:17:15.258759 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2015 12:17:15.258842 == TX Byte 1 ==
2016 12:17:15.261716 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2017 12:17:15.268653 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2018 12:17:15.268737
2019 12:17:15.268841 [DATLAT]
2020 12:17:15.268903 Freq=800, CH1 RK1
2021 12:17:15.268963
2022 12:17:15.271675 DATLAT Default: 0xa
2023 12:17:15.271758 0, 0xFFFF, sum = 0
2024 12:17:15.275154 1, 0xFFFF, sum = 0
2025 12:17:15.275249 2, 0xFFFF, sum = 0
2026 12:17:15.278350 3, 0xFFFF, sum = 0
2027 12:17:15.282018 4, 0xFFFF, sum = 0
2028 12:17:15.282108 5, 0xFFFF, sum = 0
2029 12:17:15.285346 6, 0xFFFF, sum = 0
2030 12:17:15.285430 7, 0xFFFF, sum = 0
2031 12:17:15.288635 8, 0xFFFF, sum = 0
2032 12:17:15.288730 9, 0x0, sum = 1
2033 12:17:15.291801 10, 0x0, sum = 2
2034 12:17:15.291895 11, 0x0, sum = 3
2035 12:17:15.291963 12, 0x0, sum = 4
2036 12:17:15.295059 best_step = 10
2037 12:17:15.295152
2038 12:17:15.295219 ==
2039 12:17:15.298237 Dram Type= 6, Freq= 0, CH_1, rank 1
2040 12:17:15.301291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2041 12:17:15.301386 ==
2042 12:17:15.304619 RX Vref Scan: 0
2043 12:17:15.304702
2044 12:17:15.308080 RX Vref 0 -> 0, step: 1
2045 12:17:15.308207
2046 12:17:15.308273 RX Delay -95 -> 252, step: 8
2047 12:17:15.315199 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2048 12:17:15.318629 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2049 12:17:15.321635 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2050 12:17:15.325146 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2051 12:17:15.328508 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2052 12:17:15.334998 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2053 12:17:15.338446 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2054 12:17:15.341980 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2055 12:17:15.345005 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2056 12:17:15.348359 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2057 12:17:15.354983 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2058 12:17:15.357981 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2059 12:17:15.361365 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2060 12:17:15.364699 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2061 12:17:15.368094 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2062 12:17:15.374866 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2063 12:17:15.374950 ==
2064 12:17:15.378334 Dram Type= 6, Freq= 0, CH_1, rank 1
2065 12:17:15.381302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2066 12:17:15.381385 ==
2067 12:17:15.381451 DQS Delay:
2068 12:17:15.384638 DQS0 = 0, DQS1 = 0
2069 12:17:15.384722 DQM Delay:
2070 12:17:15.387788 DQM0 = 92, DQM1 = 84
2071 12:17:15.387871 DQ Delay:
2072 12:17:15.391374 DQ0 =92, DQ1 =84, DQ2 =84, DQ3 =88
2073 12:17:15.394596 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2074 12:17:15.398090 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2075 12:17:15.401394 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =92
2076 12:17:15.401478
2077 12:17:15.401543
2078 12:17:15.411243 [DQSOSCAuto] RK1, (LSB)MR18= 0x350a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
2079 12:17:15.411329 CH1 RK1: MR19=606, MR18=350A
2080 12:17:15.417738 CH1_RK1: MR19=0x606, MR18=0x350A, DQSOSC=396, MR23=63, INC=94, DEC=62
2081 12:17:15.421141 [RxdqsGatingPostProcess] freq 800
2082 12:17:15.427892 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2083 12:17:15.430789 Pre-setting of DQS Precalculation
2084 12:17:15.434277 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2085 12:17:15.440926 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2086 12:17:15.451164 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2087 12:17:15.451239
2088 12:17:15.451303
2089 12:17:15.454336 [Calibration Summary] 1600 Mbps
2090 12:17:15.454406 CH 0, Rank 0
2091 12:17:15.457420 SW Impedance : PASS
2092 12:17:15.457491 DUTY Scan : NO K
2093 12:17:15.460954 ZQ Calibration : PASS
2094 12:17:15.461019 Jitter Meter : NO K
2095 12:17:15.464390 CBT Training : PASS
2096 12:17:15.467847 Write leveling : PASS
2097 12:17:15.467920 RX DQS gating : PASS
2098 12:17:15.471127 RX DQ/DQS(RDDQC) : PASS
2099 12:17:15.474317 TX DQ/DQS : PASS
2100 12:17:15.474417 RX DATLAT : PASS
2101 12:17:15.477769 RX DQ/DQS(Engine): PASS
2102 12:17:15.480635 TX OE : NO K
2103 12:17:15.480705 All Pass.
2104 12:17:15.480789
2105 12:17:15.480866 CH 0, Rank 1
2106 12:17:15.484160 SW Impedance : PASS
2107 12:17:15.487390 DUTY Scan : NO K
2108 12:17:15.487459 ZQ Calibration : PASS
2109 12:17:15.490962 Jitter Meter : NO K
2110 12:17:15.494212 CBT Training : PASS
2111 12:17:15.494295 Write leveling : PASS
2112 12:17:15.497379 RX DQS gating : PASS
2113 12:17:15.500674 RX DQ/DQS(RDDQC) : PASS
2114 12:17:15.500757 TX DQ/DQS : PASS
2115 12:17:15.504321 RX DATLAT : PASS
2116 12:17:15.507473 RX DQ/DQS(Engine): PASS
2117 12:17:15.507551 TX OE : NO K
2118 12:17:15.507618 All Pass.
2119 12:17:15.510774
2120 12:17:15.510845 CH 1, Rank 0
2121 12:17:15.513833 SW Impedance : PASS
2122 12:17:15.513909 DUTY Scan : NO K
2123 12:17:15.517185 ZQ Calibration : PASS
2124 12:17:15.520311 Jitter Meter : NO K
2125 12:17:15.520380 CBT Training : PASS
2126 12:17:15.523908 Write leveling : PASS
2127 12:17:15.523991 RX DQS gating : PASS
2128 12:17:15.527245 RX DQ/DQS(RDDQC) : PASS
2129 12:17:15.530655 TX DQ/DQS : PASS
2130 12:17:15.530738 RX DATLAT : PASS
2131 12:17:15.534156 RX DQ/DQS(Engine): PASS
2132 12:17:15.537086 TX OE : NO K
2133 12:17:15.537170 All Pass.
2134 12:17:15.537236
2135 12:17:15.537298 CH 1, Rank 1
2136 12:17:15.540491 SW Impedance : PASS
2137 12:17:15.543786 DUTY Scan : NO K
2138 12:17:15.543870 ZQ Calibration : PASS
2139 12:17:15.547329 Jitter Meter : NO K
2140 12:17:15.550712 CBT Training : PASS
2141 12:17:15.550795 Write leveling : PASS
2142 12:17:15.553691 RX DQS gating : PASS
2143 12:17:15.556998 RX DQ/DQS(RDDQC) : PASS
2144 12:17:15.557082 TX DQ/DQS : PASS
2145 12:17:15.560381 RX DATLAT : PASS
2146 12:17:15.560468 RX DQ/DQS(Engine): PASS
2147 12:17:15.563700 TX OE : NO K
2148 12:17:15.563775 All Pass.
2149 12:17:15.563838
2150 12:17:15.567113 DramC Write-DBI off
2151 12:17:15.570591 PER_BANK_REFRESH: Hybrid Mode
2152 12:17:15.570682 TX_TRACKING: ON
2153 12:17:15.573945 [GetDramInforAfterCalByMRR] Vendor 6.
2154 12:17:15.576916 [GetDramInforAfterCalByMRR] Revision 606.
2155 12:17:15.583768 [GetDramInforAfterCalByMRR] Revision 2 0.
2156 12:17:15.583874 MR0 0x3b3b
2157 12:17:15.583940 MR8 0x5151
2158 12:17:15.587209 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2159 12:17:15.587291
2160 12:17:15.590589 MR0 0x3b3b
2161 12:17:15.590670 MR8 0x5151
2162 12:17:15.593923 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2163 12:17:15.594005
2164 12:17:15.603923 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2165 12:17:15.607140 [FAST_K] Save calibration result to emmc
2166 12:17:15.610420 [FAST_K] Save calibration result to emmc
2167 12:17:15.613911 dram_init: config_dvfs: 1
2168 12:17:15.617332 dramc_set_vcore_voltage set vcore to 662500
2169 12:17:15.617411 Read voltage for 1200, 2
2170 12:17:15.620390 Vio18 = 0
2171 12:17:15.620462 Vcore = 662500
2172 12:17:15.620526 Vdram = 0
2173 12:17:15.623951 Vddq = 0
2174 12:17:15.624034 Vmddr = 0
2175 12:17:15.630127 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2176 12:17:15.633825 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2177 12:17:15.637127 MEM_TYPE=3, freq_sel=15
2178 12:17:15.640005 sv_algorithm_assistance_LP4_1600
2179 12:17:15.643517 ============ PULL DRAM RESETB DOWN ============
2180 12:17:15.646794 ========== PULL DRAM RESETB DOWN end =========
2181 12:17:15.653653 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2182 12:17:15.656576 ===================================
2183 12:17:15.656659 LPDDR4 DRAM CONFIGURATION
2184 12:17:15.659858 ===================================
2185 12:17:15.663213 EX_ROW_EN[0] = 0x0
2186 12:17:15.666677 EX_ROW_EN[1] = 0x0
2187 12:17:15.666760 LP4Y_EN = 0x0
2188 12:17:15.670095 WORK_FSP = 0x0
2189 12:17:15.670178 WL = 0x4
2190 12:17:15.672993 RL = 0x4
2191 12:17:15.673075 BL = 0x2
2192 12:17:15.676400 RPST = 0x0
2193 12:17:15.676482 RD_PRE = 0x0
2194 12:17:15.679743 WR_PRE = 0x1
2195 12:17:15.679826 WR_PST = 0x0
2196 12:17:15.683138 DBI_WR = 0x0
2197 12:17:15.683221 DBI_RD = 0x0
2198 12:17:15.686481 OTF = 0x1
2199 12:17:15.689895 ===================================
2200 12:17:15.693296 ===================================
2201 12:17:15.693379 ANA top config
2202 12:17:15.696613 ===================================
2203 12:17:15.699735 DLL_ASYNC_EN = 0
2204 12:17:15.703121 ALL_SLAVE_EN = 0
2205 12:17:15.706399 NEW_RANK_MODE = 1
2206 12:17:15.706483 DLL_IDLE_MODE = 1
2207 12:17:15.709633 LP45_APHY_COMB_EN = 1
2208 12:17:15.713108 TX_ODT_DIS = 1
2209 12:17:15.716582 NEW_8X_MODE = 1
2210 12:17:15.719818 ===================================
2211 12:17:15.722879 ===================================
2212 12:17:15.726186 data_rate = 2400
2213 12:17:15.726269 CKR = 1
2214 12:17:15.729794 DQ_P2S_RATIO = 8
2215 12:17:15.733056 ===================================
2216 12:17:15.736230 CA_P2S_RATIO = 8
2217 12:17:15.739669 DQ_CA_OPEN = 0
2218 12:17:15.742872 DQ_SEMI_OPEN = 0
2219 12:17:15.742955 CA_SEMI_OPEN = 0
2220 12:17:15.746241 CA_FULL_RATE = 0
2221 12:17:15.749536 DQ_CKDIV4_EN = 0
2222 12:17:15.752733 CA_CKDIV4_EN = 0
2223 12:17:15.756296 CA_PREDIV_EN = 0
2224 12:17:15.759215 PH8_DLY = 17
2225 12:17:15.762601 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2226 12:17:15.762684 DQ_AAMCK_DIV = 4
2227 12:17:15.765936 CA_AAMCK_DIV = 4
2228 12:17:15.769301 CA_ADMCK_DIV = 4
2229 12:17:15.772782 DQ_TRACK_CA_EN = 0
2230 12:17:15.776130 CA_PICK = 1200
2231 12:17:15.779078 CA_MCKIO = 1200
2232 12:17:15.779160 MCKIO_SEMI = 0
2233 12:17:15.782483 PLL_FREQ = 2366
2234 12:17:15.786004 DQ_UI_PI_RATIO = 32
2235 12:17:15.788922 CA_UI_PI_RATIO = 0
2236 12:17:15.792267 ===================================
2237 12:17:15.795747 ===================================
2238 12:17:15.799094 memory_type:LPDDR4
2239 12:17:15.799177 GP_NUM : 10
2240 12:17:15.802564 SRAM_EN : 1
2241 12:17:15.805568 MD32_EN : 0
2242 12:17:15.808943 ===================================
2243 12:17:15.809043 [ANA_INIT] >>>>>>>>>>>>>>
2244 12:17:15.812604 <<<<<< [CONFIGURE PHASE]: ANA_TX
2245 12:17:15.815834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2246 12:17:15.819203 ===================================
2247 12:17:15.822530 data_rate = 2400,PCW = 0X5b00
2248 12:17:15.825760 ===================================
2249 12:17:15.828998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2250 12:17:15.835756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2251 12:17:15.838978 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2252 12:17:15.845465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2253 12:17:15.849078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2254 12:17:15.852191 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2255 12:17:15.855454 [ANA_INIT] flow start
2256 12:17:15.855537 [ANA_INIT] PLL >>>>>>>>
2257 12:17:15.858952 [ANA_INIT] PLL <<<<<<<<
2258 12:17:15.862291 [ANA_INIT] MIDPI >>>>>>>>
2259 12:17:15.862400 [ANA_INIT] MIDPI <<<<<<<<
2260 12:17:15.865739 [ANA_INIT] DLL >>>>>>>>
2261 12:17:15.868633 [ANA_INIT] DLL <<<<<<<<
2262 12:17:15.868706 [ANA_INIT] flow end
2263 12:17:15.875354 ============ LP4 DIFF to SE enter ============
2264 12:17:15.878824 ============ LP4 DIFF to SE exit ============
2265 12:17:15.878908 [ANA_INIT] <<<<<<<<<<<<<
2266 12:17:15.881783 [Flow] Enable top DCM control >>>>>
2267 12:17:15.885199 [Flow] Enable top DCM control <<<<<
2268 12:17:15.888633 Enable DLL master slave shuffle
2269 12:17:15.895527 ==============================================================
2270 12:17:15.895611 Gating Mode config
2271 12:17:15.901923 ==============================================================
2272 12:17:15.905473 Config description:
2273 12:17:15.915173 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2274 12:17:15.921737 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2275 12:17:15.925125 SELPH_MODE 0: By rank 1: By Phase
2276 12:17:15.931825 ==============================================================
2277 12:17:15.935198 GAT_TRACK_EN = 1
2278 12:17:15.938134 RX_GATING_MODE = 2
2279 12:17:15.941988 RX_GATING_TRACK_MODE = 2
2280 12:17:15.942179 SELPH_MODE = 1
2281 12:17:15.945270 PICG_EARLY_EN = 1
2282 12:17:15.948642 VALID_LAT_VALUE = 1
2283 12:17:15.955240 ==============================================================
2284 12:17:15.958510 Enter into Gating configuration >>>>
2285 12:17:15.962024 Exit from Gating configuration <<<<
2286 12:17:15.965179 Enter into DVFS_PRE_config >>>>>
2287 12:17:15.975322 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2288 12:17:15.978614 Exit from DVFS_PRE_config <<<<<
2289 12:17:15.982135 Enter into PICG configuration >>>>
2290 12:17:15.985051 Exit from PICG configuration <<<<
2291 12:17:15.988466 [RX_INPUT] configuration >>>>>
2292 12:17:15.992011 [RX_INPUT] configuration <<<<<
2293 12:17:15.995455 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2294 12:17:16.001783 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2295 12:17:16.008621 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2296 12:17:16.015404 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2297 12:17:16.018623 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2298 12:17:16.025467 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2299 12:17:16.028936 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2300 12:17:16.035425 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2301 12:17:16.038393 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2302 12:17:16.041849 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2303 12:17:16.045595 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2304 12:17:16.051788 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2305 12:17:16.055338 ===================================
2306 12:17:16.055421 LPDDR4 DRAM CONFIGURATION
2307 12:17:16.058058 ===================================
2308 12:17:16.061729 EX_ROW_EN[0] = 0x0
2309 12:17:16.064946 EX_ROW_EN[1] = 0x0
2310 12:17:16.065035 LP4Y_EN = 0x0
2311 12:17:16.068395 WORK_FSP = 0x0
2312 12:17:16.068490 WL = 0x4
2313 12:17:16.071564 RL = 0x4
2314 12:17:16.071659 BL = 0x2
2315 12:17:16.074962 RPST = 0x0
2316 12:17:16.075066 RD_PRE = 0x0
2317 12:17:16.078192 WR_PRE = 0x1
2318 12:17:16.078305 WR_PST = 0x0
2319 12:17:16.081621 DBI_WR = 0x0
2320 12:17:16.081769 DBI_RD = 0x0
2321 12:17:16.084956 OTF = 0x1
2322 12:17:16.088462 ===================================
2323 12:17:16.091840 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2324 12:17:16.094879 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2325 12:17:16.101683 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2326 12:17:16.105079 ===================================
2327 12:17:16.105285 LPDDR4 DRAM CONFIGURATION
2328 12:17:16.108869 ===================================
2329 12:17:16.112169 EX_ROW_EN[0] = 0x10
2330 12:17:16.112594 EX_ROW_EN[1] = 0x0
2331 12:17:16.115021 LP4Y_EN = 0x0
2332 12:17:16.118277 WORK_FSP = 0x0
2333 12:17:16.118702 WL = 0x4
2334 12:17:16.121790 RL = 0x4
2335 12:17:16.122257 BL = 0x2
2336 12:17:16.125278 RPST = 0x0
2337 12:17:16.125865 RD_PRE = 0x0
2338 12:17:16.128584 WR_PRE = 0x1
2339 12:17:16.129114 WR_PST = 0x0
2340 12:17:16.132021 DBI_WR = 0x0
2341 12:17:16.132467 DBI_RD = 0x0
2342 12:17:16.135394 OTF = 0x1
2343 12:17:16.138722 ===================================
2344 12:17:16.142172 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2345 12:17:16.144950 ==
2346 12:17:16.148278 Dram Type= 6, Freq= 0, CH_0, rank 0
2347 12:17:16.151592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2348 12:17:16.152101 ==
2349 12:17:16.155256 [Duty_Offset_Calibration]
2350 12:17:16.155708 B0:2 B1:0 CA:1
2351 12:17:16.156211
2352 12:17:16.158458 [DutyScan_Calibration_Flow] k_type=0
2353 12:17:16.167430
2354 12:17:16.167855 ==CLK 0==
2355 12:17:16.170428 Final CLK duty delay cell = -4
2356 12:17:16.173948 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2357 12:17:16.177029 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2358 12:17:16.180472 [-4] AVG Duty = 4953%(X100)
2359 12:17:16.181021
2360 12:17:16.183723 CH0 CLK Duty spec in!! Max-Min= 156%
2361 12:17:16.187355 [DutyScan_Calibration_Flow] ====Done====
2362 12:17:16.187769
2363 12:17:16.190228 [DutyScan_Calibration_Flow] k_type=1
2364 12:17:16.205800
2365 12:17:16.206219 ==DQS 0 ==
2366 12:17:16.209274 Final DQS duty delay cell = 0
2367 12:17:16.212835 [0] MAX Duty = 5187%(X100), DQS PI = 30
2368 12:17:16.216185 [0] MIN Duty = 4938%(X100), DQS PI = 2
2369 12:17:16.216735 [0] AVG Duty = 5062%(X100)
2370 12:17:16.219194
2371 12:17:16.219775 ==DQS 1 ==
2372 12:17:16.222993 Final DQS duty delay cell = -4
2373 12:17:16.226026 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2374 12:17:16.229249 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2375 12:17:16.232590 [-4] AVG Duty = 5031%(X100)
2376 12:17:16.233209
2377 12:17:16.235936 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2378 12:17:16.236476
2379 12:17:16.239247 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2380 12:17:16.242402 [DutyScan_Calibration_Flow] ====Done====
2381 12:17:16.242820
2382 12:17:16.246033 [DutyScan_Calibration_Flow] k_type=3
2383 12:17:16.261908
2384 12:17:16.262465 ==DQM 0 ==
2385 12:17:16.265247 Final DQM duty delay cell = 0
2386 12:17:16.268435 [0] MAX Duty = 5062%(X100), DQS PI = 24
2387 12:17:16.271882 [0] MIN Duty = 4813%(X100), DQS PI = 2
2388 12:17:16.275201 [0] AVG Duty = 4937%(X100)
2389 12:17:16.275725
2390 12:17:16.276226 ==DQM 1 ==
2391 12:17:16.278819 Final DQM duty delay cell = -4
2392 12:17:16.282056 [-4] MAX Duty = 5000%(X100), DQS PI = 48
2393 12:17:16.285202 [-4] MIN Duty = 4813%(X100), DQS PI = 12
2394 12:17:16.288762 [-4] AVG Duty = 4906%(X100)
2395 12:17:16.289228
2396 12:17:16.291730 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2397 12:17:16.292185
2398 12:17:16.295006 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2399 12:17:16.298326 [DutyScan_Calibration_Flow] ====Done====
2400 12:17:16.298740
2401 12:17:16.301799 [DutyScan_Calibration_Flow] k_type=2
2402 12:17:16.318660
2403 12:17:16.319100 ==DQ 0 ==
2404 12:17:16.322105 Final DQ duty delay cell = -4
2405 12:17:16.325515 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2406 12:17:16.328881 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2407 12:17:16.332185 [-4] AVG Duty = 4953%(X100)
2408 12:17:16.332740
2409 12:17:16.333190 ==DQ 1 ==
2410 12:17:16.335455 Final DQ duty delay cell = 4
2411 12:17:16.338884 [4] MAX Duty = 5093%(X100), DQS PI = 4
2412 12:17:16.342169 [4] MIN Duty = 5031%(X100), DQS PI = 0
2413 12:17:16.342635 [4] AVG Duty = 5062%(X100)
2414 12:17:16.345697
2415 12:17:16.348900 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2416 12:17:16.349360
2417 12:17:16.352245 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2418 12:17:16.355080 [DutyScan_Calibration_Flow] ====Done====
2419 12:17:16.355528 ==
2420 12:17:16.358894 Dram Type= 6, Freq= 0, CH_1, rank 0
2421 12:17:16.361824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2422 12:17:16.362238 ==
2423 12:17:16.365245 [Duty_Offset_Calibration]
2424 12:17:16.365660 B0:0 B1:-1 CA:2
2425 12:17:16.365988
2426 12:17:16.368715 [DutyScan_Calibration_Flow] k_type=0
2427 12:17:16.379420
2428 12:17:16.379926 ==CLK 0==
2429 12:17:16.382248 Final CLK duty delay cell = 0
2430 12:17:16.385937 [0] MAX Duty = 5156%(X100), DQS PI = 16
2431 12:17:16.389106 [0] MIN Duty = 4938%(X100), DQS PI = 44
2432 12:17:16.389568 [0] AVG Duty = 5047%(X100)
2433 12:17:16.392728
2434 12:17:16.395752 CH1 CLK Duty spec in!! Max-Min= 218%
2435 12:17:16.398886 [DutyScan_Calibration_Flow] ====Done====
2436 12:17:16.399300
2437 12:17:16.402448 [DutyScan_Calibration_Flow] k_type=1
2438 12:17:16.418597
2439 12:17:16.419218 ==DQS 0 ==
2440 12:17:16.422040 Final DQS duty delay cell = 0
2441 12:17:16.425251 [0] MAX Duty = 5093%(X100), DQS PI = 24
2442 12:17:16.428735 [0] MIN Duty = 4969%(X100), DQS PI = 0
2443 12:17:16.429222 [0] AVG Duty = 5031%(X100)
2444 12:17:16.431940
2445 12:17:16.432423 ==DQS 1 ==
2446 12:17:16.435076 Final DQS duty delay cell = 0
2447 12:17:16.438561 [0] MAX Duty = 5156%(X100), DQS PI = 0
2448 12:17:16.441692 [0] MIN Duty = 4875%(X100), DQS PI = 34
2449 12:17:16.445142 [0] AVG Duty = 5015%(X100)
2450 12:17:16.445632
2451 12:17:16.448332 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2452 12:17:16.448896
2453 12:17:16.451707 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2454 12:17:16.455226 [DutyScan_Calibration_Flow] ====Done====
2455 12:17:16.455659
2456 12:17:16.458123 [DutyScan_Calibration_Flow] k_type=3
2457 12:17:16.474851
2458 12:17:16.475340 ==DQM 0 ==
2459 12:17:16.478199 Final DQM duty delay cell = 4
2460 12:17:16.481658 [4] MAX Duty = 5093%(X100), DQS PI = 6
2461 12:17:16.484937 [4] MIN Duty = 4969%(X100), DQS PI = 28
2462 12:17:16.488325 [4] AVG Duty = 5031%(X100)
2463 12:17:16.488703
2464 12:17:16.489071 ==DQM 1 ==
2465 12:17:16.491642 Final DQM duty delay cell = -4
2466 12:17:16.494758 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2467 12:17:16.498214 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2468 12:17:16.501361 [-4] AVG Duty = 4875%(X100)
2469 12:17:16.501789
2470 12:17:16.504910 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2471 12:17:16.505471
2472 12:17:16.508116 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2473 12:17:16.511106 [DutyScan_Calibration_Flow] ====Done====
2474 12:17:16.511528
2475 12:17:16.514374 [DutyScan_Calibration_Flow] k_type=2
2476 12:17:16.531594
2477 12:17:16.532018 ==DQ 0 ==
2478 12:17:16.534960 Final DQ duty delay cell = 0
2479 12:17:16.538402 [0] MAX Duty = 5062%(X100), DQS PI = 18
2480 12:17:16.541784 [0] MIN Duty = 4938%(X100), DQS PI = 44
2481 12:17:16.542266 [0] AVG Duty = 5000%(X100)
2482 12:17:16.545090
2483 12:17:16.545614 ==DQ 1 ==
2484 12:17:16.548334 Final DQ duty delay cell = 0
2485 12:17:16.551715 [0] MAX Duty = 5031%(X100), DQS PI = 0
2486 12:17:16.555310 [0] MIN Duty = 4813%(X100), DQS PI = 36
2487 12:17:16.555686 [0] AVG Duty = 4922%(X100)
2488 12:17:16.556010
2489 12:17:16.558255 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2490 12:17:16.561530
2491 12:17:16.564897 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2492 12:17:16.568161 [DutyScan_Calibration_Flow] ====Done====
2493 12:17:16.571572 nWR fixed to 30
2494 12:17:16.572001 [ModeRegInit_LP4] CH0 RK0
2495 12:17:16.575029 [ModeRegInit_LP4] CH0 RK1
2496 12:17:16.578299 [ModeRegInit_LP4] CH1 RK0
2497 12:17:16.578721 [ModeRegInit_LP4] CH1 RK1
2498 12:17:16.581426 match AC timing 7
2499 12:17:16.584826 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2500 12:17:16.591407 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2501 12:17:16.594770 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2502 12:17:16.601210 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2503 12:17:16.604620 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2504 12:17:16.605120 ==
2505 12:17:16.607726 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 12:17:16.611407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 12:17:16.611832 ==
2508 12:17:16.617630 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2509 12:17:16.624210 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2510 12:17:16.631619 [CA 0] Center 38 (8~69) winsize 62
2511 12:17:16.635008 [CA 1] Center 38 (8~69) winsize 62
2512 12:17:16.638383 [CA 2] Center 35 (4~66) winsize 63
2513 12:17:16.641738 [CA 3] Center 34 (4~65) winsize 62
2514 12:17:16.645107 [CA 4] Center 34 (4~64) winsize 61
2515 12:17:16.648547 [CA 5] Center 33 (3~64) winsize 62
2516 12:17:16.649009
2517 12:17:16.651361 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2518 12:17:16.651781
2519 12:17:16.654778 [CATrainingPosCal] consider 1 rank data
2520 12:17:16.658278 u2DelayCellTimex100 = 270/100 ps
2521 12:17:16.661152 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2522 12:17:16.667947 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2523 12:17:16.671212 CA2 delay=35 (4~66),Diff = 2 PI (9 cell)
2524 12:17:16.674388 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2525 12:17:16.677772 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2526 12:17:16.681303 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2527 12:17:16.681876
2528 12:17:16.684410 CA PerBit enable=1, Macro0, CA PI delay=33
2529 12:17:16.685059
2530 12:17:16.687730 [CBTSetCACLKResult] CA Dly = 33
2531 12:17:16.691232 CS Dly: 6 (0~37)
2532 12:17:16.691853 ==
2533 12:17:16.694095 Dram Type= 6, Freq= 0, CH_0, rank 1
2534 12:17:16.697527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 12:17:16.698156 ==
2536 12:17:16.704146 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2537 12:17:16.707580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2538 12:17:16.717187 [CA 0] Center 39 (8~70) winsize 63
2539 12:17:16.720381 [CA 1] Center 38 (8~69) winsize 62
2540 12:17:16.723576 [CA 2] Center 35 (5~66) winsize 62
2541 12:17:16.727111 [CA 3] Center 35 (5~66) winsize 62
2542 12:17:16.730480 [CA 4] Center 34 (4~65) winsize 62
2543 12:17:16.733868 [CA 5] Center 34 (4~64) winsize 61
2544 12:17:16.734511
2545 12:17:16.736709 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2546 12:17:16.737303
2547 12:17:16.740143 [CATrainingPosCal] consider 2 rank data
2548 12:17:16.743508 u2DelayCellTimex100 = 270/100 ps
2549 12:17:16.746866 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2550 12:17:16.753637 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2551 12:17:16.756835 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2552 12:17:16.760425 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
2553 12:17:16.763789 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
2554 12:17:16.767181 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2555 12:17:16.767603
2556 12:17:16.770123 CA PerBit enable=1, Macro0, CA PI delay=34
2557 12:17:16.770547
2558 12:17:16.773675 [CBTSetCACLKResult] CA Dly = 34
2559 12:17:16.777012 CS Dly: 7 (0~39)
2560 12:17:16.777658
2561 12:17:16.780064 ----->DramcWriteLeveling(PI) begin...
2562 12:17:16.780492 ==
2563 12:17:16.783508 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 12:17:16.786792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 12:17:16.787223 ==
2566 12:17:16.790029 Write leveling (Byte 0): 33 => 33
2567 12:17:16.793270 Write leveling (Byte 1): 30 => 30
2568 12:17:16.796751 DramcWriteLeveling(PI) end<-----
2569 12:17:16.797214
2570 12:17:16.797548 ==
2571 12:17:16.799506 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 12:17:16.802794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 12:17:16.802877 ==
2574 12:17:16.806390 [Gating] SW mode calibration
2575 12:17:16.812932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2576 12:17:16.819552 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2577 12:17:16.822651 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2578 12:17:16.826317 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
2579 12:17:16.832820 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 12:17:16.835903 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 12:17:16.839558 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 12:17:16.845809 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 12:17:16.849179 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2584 12:17:16.852530 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
2585 12:17:16.859186 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2586 12:17:16.862556 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 12:17:16.865956 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 12:17:16.872745 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 12:17:16.875790 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 12:17:16.879180 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 12:17:16.885851 1 0 24 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
2592 12:17:16.889243 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2593 12:17:16.892563 1 1 0 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
2594 12:17:16.899288 1 1 4 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
2595 12:17:16.902704 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 12:17:16.905679 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 12:17:16.909183 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 12:17:16.915841 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 12:17:16.919305 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2600 12:17:16.922671 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2601 12:17:16.928967 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2602 12:17:16.932318 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 12:17:16.935896 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 12:17:16.942551 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 12:17:16.945657 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 12:17:16.949100 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 12:17:16.956018 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 12:17:16.959425 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 12:17:16.962421 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 12:17:16.969273 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 12:17:16.972536 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 12:17:16.976031 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 12:17:16.982496 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 12:17:16.985752 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 12:17:16.989177 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 12:17:16.995600 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2617 12:17:16.998876 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2618 12:17:17.002203 Total UI for P1: 0, mck2ui 16
2619 12:17:17.005625 best dqsien dly found for B0: ( 1, 3, 28)
2620 12:17:17.009047 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 12:17:17.012107 Total UI for P1: 0, mck2ui 16
2622 12:17:17.015471 best dqsien dly found for B1: ( 1, 4, 0)
2623 12:17:17.018890 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2624 12:17:17.022490 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2625 12:17:17.022579
2626 12:17:17.025740 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2627 12:17:17.031994 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2628 12:17:17.032099 [Gating] SW calibration Done
2629 12:17:17.032182 ==
2630 12:17:17.035468 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 12:17:17.042179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 12:17:17.042391 ==
2633 12:17:17.042513 RX Vref Scan: 0
2634 12:17:17.042625
2635 12:17:17.045838 RX Vref 0 -> 0, step: 1
2636 12:17:17.046022
2637 12:17:17.048994 RX Delay -40 -> 252, step: 8
2638 12:17:17.051777 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2639 12:17:17.055301 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2640 12:17:17.058784 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2641 12:17:17.065553 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2642 12:17:17.068730 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2643 12:17:17.071796 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2644 12:17:17.075366 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2645 12:17:17.078716 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2646 12:17:17.085213 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2647 12:17:17.088548 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2648 12:17:17.091681 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2649 12:17:17.095297 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2650 12:17:17.098574 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2651 12:17:17.105176 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2652 12:17:17.108577 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2653 12:17:17.112167 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2654 12:17:17.112587 ==
2655 12:17:17.114975 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 12:17:17.118369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 12:17:17.118956 ==
2658 12:17:17.121567 DQS Delay:
2659 12:17:17.122103 DQS0 = 0, DQS1 = 0
2660 12:17:17.124979 DQM Delay:
2661 12:17:17.125462 DQM0 = 123, DQM1 = 110
2662 12:17:17.128400 DQ Delay:
2663 12:17:17.131930 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2664 12:17:17.135261 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2665 12:17:17.138571 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2666 12:17:17.141960 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2667 12:17:17.142385
2668 12:17:17.142717
2669 12:17:17.143030 ==
2670 12:17:17.144850 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 12:17:17.148327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 12:17:17.148754 ==
2673 12:17:17.149151
2674 12:17:17.149466
2675 12:17:17.151646 TX Vref Scan disable
2676 12:17:17.155045 == TX Byte 0 ==
2677 12:17:17.158477 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2678 12:17:17.161660 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2679 12:17:17.165233 == TX Byte 1 ==
2680 12:17:17.168209 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2681 12:17:17.171677 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2682 12:17:17.172217 ==
2683 12:17:17.175073 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 12:17:17.178451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 12:17:17.181302 ==
2686 12:17:17.191674 TX Vref=22, minBit 4, minWin=24, winSum=408
2687 12:17:17.194916 TX Vref=24, minBit 0, minWin=25, winSum=415
2688 12:17:17.198280 TX Vref=26, minBit 0, minWin=25, winSum=420
2689 12:17:17.201844 TX Vref=28, minBit 3, minWin=25, winSum=423
2690 12:17:17.205319 TX Vref=30, minBit 0, minWin=26, winSum=426
2691 12:17:17.208476 TX Vref=32, minBit 3, minWin=25, winSum=421
2692 12:17:17.214887 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
2693 12:17:17.215501
2694 12:17:17.218371 Final TX Range 1 Vref 30
2695 12:17:17.218920
2696 12:17:17.219412 ==
2697 12:17:17.221399 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 12:17:17.224724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 12:17:17.228103 ==
2700 12:17:17.228669
2701 12:17:17.229146
2702 12:17:17.229474 TX Vref Scan disable
2703 12:17:17.231561 == TX Byte 0 ==
2704 12:17:17.235016 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2705 12:17:17.237970 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2706 12:17:17.241362 == TX Byte 1 ==
2707 12:17:17.244693 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2708 12:17:17.248184 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2709 12:17:17.251609
2710 12:17:17.252052 [DATLAT]
2711 12:17:17.252475 Freq=1200, CH0 RK0
2712 12:17:17.252980
2713 12:17:17.254490 DATLAT Default: 0xd
2714 12:17:17.254925 0, 0xFFFF, sum = 0
2715 12:17:17.257928 1, 0xFFFF, sum = 0
2716 12:17:17.258434 2, 0xFFFF, sum = 0
2717 12:17:17.261215 3, 0xFFFF, sum = 0
2718 12:17:17.264850 4, 0xFFFF, sum = 0
2719 12:17:17.265234 5, 0xFFFF, sum = 0
2720 12:17:17.268313 6, 0xFFFF, sum = 0
2721 12:17:17.268913 7, 0xFFFF, sum = 0
2722 12:17:17.271457 8, 0xFFFF, sum = 0
2723 12:17:17.271885 9, 0xFFFF, sum = 0
2724 12:17:17.274729 10, 0xFFFF, sum = 0
2725 12:17:17.275185 11, 0xFFFF, sum = 0
2726 12:17:17.277935 12, 0x0, sum = 1
2727 12:17:17.278394 13, 0x0, sum = 2
2728 12:17:17.281467 14, 0x0, sum = 3
2729 12:17:17.281899 15, 0x0, sum = 4
2730 12:17:17.284365 best_step = 13
2731 12:17:17.284961
2732 12:17:17.285449 ==
2733 12:17:17.287849 Dram Type= 6, Freq= 0, CH_0, rank 0
2734 12:17:17.291128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2735 12:17:17.291742 ==
2736 12:17:17.292206 RX Vref Scan: 1
2737 12:17:17.292692
2738 12:17:17.294421 Set Vref Range= 32 -> 127
2739 12:17:17.294934
2740 12:17:17.297767 RX Vref 32 -> 127, step: 1
2741 12:17:17.298354
2742 12:17:17.301448 RX Delay -13 -> 252, step: 4
2743 12:17:17.301990
2744 12:17:17.304353 Set Vref, RX VrefLevel [Byte0]: 32
2745 12:17:17.307606 [Byte1]: 32
2746 12:17:17.308152
2747 12:17:17.310968 Set Vref, RX VrefLevel [Byte0]: 33
2748 12:17:17.314441 [Byte1]: 33
2749 12:17:17.317761
2750 12:17:17.318243 Set Vref, RX VrefLevel [Byte0]: 34
2751 12:17:17.321225 [Byte1]: 34
2752 12:17:17.325955
2753 12:17:17.326373 Set Vref, RX VrefLevel [Byte0]: 35
2754 12:17:17.329153 [Byte1]: 35
2755 12:17:17.333499
2756 12:17:17.333915 Set Vref, RX VrefLevel [Byte0]: 36
2757 12:17:17.336993 [Byte1]: 36
2758 12:17:17.341477
2759 12:17:17.341892 Set Vref, RX VrefLevel [Byte0]: 37
2760 12:17:17.344756 [Byte1]: 37
2761 12:17:17.349592
2762 12:17:17.350006 Set Vref, RX VrefLevel [Byte0]: 38
2763 12:17:17.352609 [Byte1]: 38
2764 12:17:17.357388
2765 12:17:17.357805 Set Vref, RX VrefLevel [Byte0]: 39
2766 12:17:17.360851 [Byte1]: 39
2767 12:17:17.365173
2768 12:17:17.365588 Set Vref, RX VrefLevel [Byte0]: 40
2769 12:17:17.368638 [Byte1]: 40
2770 12:17:17.373440
2771 12:17:17.373964 Set Vref, RX VrefLevel [Byte0]: 41
2772 12:17:17.376323 [Byte1]: 41
2773 12:17:17.380881
2774 12:17:17.381364 Set Vref, RX VrefLevel [Byte0]: 42
2775 12:17:17.384541 [Byte1]: 42
2776 12:17:17.388873
2777 12:17:17.389376 Set Vref, RX VrefLevel [Byte0]: 43
2778 12:17:17.392210 [Byte1]: 43
2779 12:17:17.396506
2780 12:17:17.397042 Set Vref, RX VrefLevel [Byte0]: 44
2781 12:17:17.399976 [Byte1]: 44
2782 12:17:17.404574
2783 12:17:17.405051 Set Vref, RX VrefLevel [Byte0]: 45
2784 12:17:17.407834 [Byte1]: 45
2785 12:17:17.412335
2786 12:17:17.412963 Set Vref, RX VrefLevel [Byte0]: 46
2787 12:17:17.415675 [Byte1]: 46
2788 12:17:17.420561
2789 12:17:17.421117 Set Vref, RX VrefLevel [Byte0]: 47
2790 12:17:17.423775 [Byte1]: 47
2791 12:17:17.428119
2792 12:17:17.428540 Set Vref, RX VrefLevel [Byte0]: 48
2793 12:17:17.431536 [Byte1]: 48
2794 12:17:17.436249
2795 12:17:17.436869 Set Vref, RX VrefLevel [Byte0]: 49
2796 12:17:17.439325 [Byte1]: 49
2797 12:17:17.444202
2798 12:17:17.444693 Set Vref, RX VrefLevel [Byte0]: 50
2799 12:17:17.447315 [Byte1]: 50
2800 12:17:17.451973
2801 12:17:17.452472 Set Vref, RX VrefLevel [Byte0]: 51
2802 12:17:17.455357 [Byte1]: 51
2803 12:17:17.459868
2804 12:17:17.460284 Set Vref, RX VrefLevel [Byte0]: 52
2805 12:17:17.463631 [Byte1]: 52
2806 12:17:17.467741
2807 12:17:17.468203 Set Vref, RX VrefLevel [Byte0]: 53
2808 12:17:17.471192 [Byte1]: 53
2809 12:17:17.475451
2810 12:17:17.476012 Set Vref, RX VrefLevel [Byte0]: 54
2811 12:17:17.478899 [Byte1]: 54
2812 12:17:17.483587
2813 12:17:17.484038 Set Vref, RX VrefLevel [Byte0]: 55
2814 12:17:17.486798 [Byte1]: 55
2815 12:17:17.491347
2816 12:17:17.492010 Set Vref, RX VrefLevel [Byte0]: 56
2817 12:17:17.494905 [Byte1]: 56
2818 12:17:17.499315
2819 12:17:17.499733 Set Vref, RX VrefLevel [Byte0]: 57
2820 12:17:17.502716 [Byte1]: 57
2821 12:17:17.507607
2822 12:17:17.508021 Set Vref, RX VrefLevel [Byte0]: 58
2823 12:17:17.510438 [Byte1]: 58
2824 12:17:17.515383
2825 12:17:17.515856 Set Vref, RX VrefLevel [Byte0]: 59
2826 12:17:17.518419 [Byte1]: 59
2827 12:17:17.523000
2828 12:17:17.523418 Set Vref, RX VrefLevel [Byte0]: 60
2829 12:17:17.526334 [Byte1]: 60
2830 12:17:17.530830
2831 12:17:17.531289 Set Vref, RX VrefLevel [Byte0]: 61
2832 12:17:17.534330 [Byte1]: 61
2833 12:17:17.538481
2834 12:17:17.538897 Set Vref, RX VrefLevel [Byte0]: 62
2835 12:17:17.541953 [Byte1]: 62
2836 12:17:17.546671
2837 12:17:17.547086 Set Vref, RX VrefLevel [Byte0]: 63
2838 12:17:17.550153 [Byte1]: 63
2839 12:17:17.554269
2840 12:17:17.554791 Set Vref, RX VrefLevel [Byte0]: 64
2841 12:17:17.557749 [Byte1]: 64
2842 12:17:17.562457
2843 12:17:17.562940 Set Vref, RX VrefLevel [Byte0]: 65
2844 12:17:17.565537 [Byte1]: 65
2845 12:17:17.570470
2846 12:17:17.570885 Set Vref, RX VrefLevel [Byte0]: 66
2847 12:17:17.573837 [Byte1]: 66
2848 12:17:17.578521
2849 12:17:17.581599 Set Vref, RX VrefLevel [Byte0]: 67
2850 12:17:17.584511 [Byte1]: 67
2851 12:17:17.584978
2852 12:17:17.587948 Set Vref, RX VrefLevel [Byte0]: 68
2853 12:17:17.591158 [Byte1]: 68
2854 12:17:17.591574
2855 12:17:17.594626 Set Vref, RX VrefLevel [Byte0]: 69
2856 12:17:17.597823 [Byte1]: 69
2857 12:17:17.601741
2858 12:17:17.602157 Set Vref, RX VrefLevel [Byte0]: 70
2859 12:17:17.604973 [Byte1]: 70
2860 12:17:17.609831
2861 12:17:17.610249 Set Vref, RX VrefLevel [Byte0]: 71
2862 12:17:17.613068 [Byte1]: 71
2863 12:17:17.617618
2864 12:17:17.618052 Final RX Vref Byte 0 = 59 to rank0
2865 12:17:17.621068 Final RX Vref Byte 1 = 49 to rank0
2866 12:17:17.624367 Final RX Vref Byte 0 = 59 to rank1
2867 12:17:17.627529 Final RX Vref Byte 1 = 49 to rank1==
2868 12:17:17.630879 Dram Type= 6, Freq= 0, CH_0, rank 0
2869 12:17:17.637686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2870 12:17:17.638110 ==
2871 12:17:17.638438 DQS Delay:
2872 12:17:17.638743 DQS0 = 0, DQS1 = 0
2873 12:17:17.641242 DQM Delay:
2874 12:17:17.641661 DQM0 = 123, DQM1 = 109
2875 12:17:17.644445 DQ Delay:
2876 12:17:17.647705 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2877 12:17:17.650717 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2878 12:17:17.654142 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2879 12:17:17.657553 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2880 12:17:17.657971
2881 12:17:17.658299
2882 12:17:17.664083 [DQSOSCAuto] RK0, (LSB)MR18= 0x905, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2883 12:17:17.667438 CH0 RK0: MR19=404, MR18=905
2884 12:17:17.674300 CH0_RK0: MR19=0x404, MR18=0x905, DQSOSC=406, MR23=63, INC=39, DEC=26
2885 12:17:17.674731
2886 12:17:17.677762 ----->DramcWriteLeveling(PI) begin...
2887 12:17:17.678194 ==
2888 12:17:17.680626 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 12:17:17.684100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 12:17:17.687587 ==
2891 12:17:17.688034 Write leveling (Byte 0): 35 => 35
2892 12:17:17.690820 Write leveling (Byte 1): 31 => 31
2893 12:17:17.694225 DramcWriteLeveling(PI) end<-----
2894 12:17:17.694671
2895 12:17:17.695016 ==
2896 12:17:17.696992 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 12:17:17.703858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 12:17:17.704291 ==
2899 12:17:17.707166 [Gating] SW mode calibration
2900 12:17:17.713618 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2901 12:17:17.717381 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2902 12:17:17.724141 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2903 12:17:17.727448 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 12:17:17.730578 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 12:17:17.737361 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 12:17:17.740224 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 12:17:17.743823 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 12:17:17.747243 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2909 12:17:17.753803 0 15 28 | B1->B0 | 3232 2b2b | 0 1 | (0 0) (1 0)
2910 12:17:17.757234 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 12:17:17.760484 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 12:17:17.767080 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 12:17:17.770607 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 12:17:17.773864 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 12:17:17.780282 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 12:17:17.783633 1 0 24 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
2917 12:17:17.787031 1 0 28 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
2918 12:17:17.793821 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 12:17:17.797117 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 12:17:17.800525 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 12:17:17.807004 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 12:17:17.810258 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 12:17:17.813528 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 12:17:17.819869 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 12:17:17.823255 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2926 12:17:17.826564 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2927 12:17:17.833434 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 12:17:17.836626 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 12:17:17.839981 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 12:17:17.846901 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 12:17:17.849861 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 12:17:17.853392 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 12:17:17.860149 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 12:17:17.862972 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 12:17:17.866518 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 12:17:17.873255 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 12:17:17.876655 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 12:17:17.879673 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 12:17:17.886814 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 12:17:17.889992 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 12:17:17.892927 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2942 12:17:17.896508 Total UI for P1: 0, mck2ui 16
2943 12:17:17.899644 best dqsien dly found for B0: ( 1, 3, 26)
2944 12:17:17.902968 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2945 12:17:17.906403 Total UI for P1: 0, mck2ui 16
2946 12:17:17.909270 best dqsien dly found for B1: ( 1, 3, 28)
2947 12:17:17.912808 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2948 12:17:17.919396 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2949 12:17:17.919951
2950 12:17:17.922665 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2951 12:17:17.926040 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2952 12:17:17.929691 [Gating] SW calibration Done
2953 12:17:17.930114 ==
2954 12:17:17.933076 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 12:17:17.936019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 12:17:17.936557 ==
2957 12:17:17.937015 RX Vref Scan: 0
2958 12:17:17.939724
2959 12:17:17.940278 RX Vref 0 -> 0, step: 1
2960 12:17:17.940751
2961 12:17:17.942477 RX Delay -40 -> 252, step: 8
2962 12:17:17.945964 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2963 12:17:17.949367 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2964 12:17:17.956030 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2965 12:17:17.959301 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2966 12:17:17.962818 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2967 12:17:17.965902 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2968 12:17:17.969550 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2969 12:17:17.976027 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2970 12:17:17.979276 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2971 12:17:17.982635 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2972 12:17:17.986014 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2973 12:17:17.989474 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2974 12:17:17.995693 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2975 12:17:17.999391 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2976 12:17:18.002240 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2977 12:17:18.005591 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2978 12:17:18.005968 ==
2979 12:17:18.009013 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 12:17:18.015575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 12:17:18.016056 ==
2982 12:17:18.016413 DQS Delay:
2983 12:17:18.018890 DQS0 = 0, DQS1 = 0
2984 12:17:18.019260 DQM Delay:
2985 12:17:18.022136 DQM0 = 120, DQM1 = 108
2986 12:17:18.022584 DQ Delay:
2987 12:17:18.025623 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2988 12:17:18.029064 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2989 12:17:18.032265 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2990 12:17:18.035418 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2991 12:17:18.035863
2992 12:17:18.036199
2993 12:17:18.036530 ==
2994 12:17:18.038930 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 12:17:18.045257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 12:17:18.045680 ==
2997 12:17:18.046012
2998 12:17:18.046318
2999 12:17:18.046641 TX Vref Scan disable
3000 12:17:18.048651 == TX Byte 0 ==
3001 12:17:18.052145 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3002 12:17:18.055643 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3003 12:17:18.058623 == TX Byte 1 ==
3004 12:17:18.061906 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3005 12:17:18.065673 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3006 12:17:18.068629 ==
3007 12:17:18.071950 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 12:17:18.075585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 12:17:18.076011 ==
3010 12:17:18.087332 TX Vref=22, minBit 7, minWin=24, winSum=412
3011 12:17:18.090471 TX Vref=24, minBit 3, minWin=24, winSum=414
3012 12:17:18.093482 TX Vref=26, minBit 1, minWin=25, winSum=417
3013 12:17:18.096659 TX Vref=28, minBit 1, minWin=25, winSum=419
3014 12:17:18.100094 TX Vref=30, minBit 5, minWin=25, winSum=426
3015 12:17:18.106775 TX Vref=32, minBit 2, minWin=25, winSum=422
3016 12:17:18.110155 [TxChooseVref] Worse bit 5, Min win 25, Win sum 426, Final Vref 30
3017 12:17:18.110785
3018 12:17:18.113468 Final TX Range 1 Vref 30
3019 12:17:18.114068
3020 12:17:18.114629 ==
3021 12:17:18.116466 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 12:17:18.119918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 12:17:18.120454 ==
3024 12:17:18.123367
3025 12:17:18.124008
3026 12:17:18.124516 TX Vref Scan disable
3027 12:17:18.126823 == TX Byte 0 ==
3028 12:17:18.130096 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3029 12:17:18.136655 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3030 12:17:18.137120 == TX Byte 1 ==
3031 12:17:18.139944 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3032 12:17:18.146562 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3033 12:17:18.146987
3034 12:17:18.147320 [DATLAT]
3035 12:17:18.147633 Freq=1200, CH0 RK1
3036 12:17:18.147939
3037 12:17:18.149741 DATLAT Default: 0xd
3038 12:17:18.150168 0, 0xFFFF, sum = 0
3039 12:17:18.153151 1, 0xFFFF, sum = 0
3040 12:17:18.156460 2, 0xFFFF, sum = 0
3041 12:17:18.157041 3, 0xFFFF, sum = 0
3042 12:17:18.159385 4, 0xFFFF, sum = 0
3043 12:17:18.159893 5, 0xFFFF, sum = 0
3044 12:17:18.162802 6, 0xFFFF, sum = 0
3045 12:17:18.163362 7, 0xFFFF, sum = 0
3046 12:17:18.166229 8, 0xFFFF, sum = 0
3047 12:17:18.166922 9, 0xFFFF, sum = 0
3048 12:17:18.169683 10, 0xFFFF, sum = 0
3049 12:17:18.170185 11, 0xFFFF, sum = 0
3050 12:17:18.173088 12, 0x0, sum = 1
3051 12:17:18.173759 13, 0x0, sum = 2
3052 12:17:18.176352 14, 0x0, sum = 3
3053 12:17:18.177023 15, 0x0, sum = 4
3054 12:17:18.179347 best_step = 13
3055 12:17:18.179931
3056 12:17:18.180471 ==
3057 12:17:18.182761 Dram Type= 6, Freq= 0, CH_0, rank 1
3058 12:17:18.186323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 12:17:18.186975 ==
3060 12:17:18.187545 RX Vref Scan: 0
3061 12:17:18.189661
3062 12:17:18.190263 RX Vref 0 -> 0, step: 1
3063 12:17:18.190772
3064 12:17:18.192551 RX Delay -21 -> 252, step: 4
3065 12:17:18.195918 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3066 12:17:18.202732 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3067 12:17:18.206147 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3068 12:17:18.209519 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3069 12:17:18.212737 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3070 12:17:18.216060 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3071 12:17:18.222453 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3072 12:17:18.225952 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3073 12:17:18.229308 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3074 12:17:18.232656 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3075 12:17:18.235866 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3076 12:17:18.242810 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3077 12:17:18.245961 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3078 12:17:18.249503 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3079 12:17:18.252613 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3080 12:17:18.255676 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3081 12:17:18.259436 ==
3082 12:17:18.262564 Dram Type= 6, Freq= 0, CH_0, rank 1
3083 12:17:18.266031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3084 12:17:18.266630 ==
3085 12:17:18.267118 DQS Delay:
3086 12:17:18.269467 DQS0 = 0, DQS1 = 0
3087 12:17:18.269977 DQM Delay:
3088 12:17:18.272834 DQM0 = 119, DQM1 = 107
3089 12:17:18.273273 DQ Delay:
3090 12:17:18.275856 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3091 12:17:18.279140 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3092 12:17:18.282532 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3093 12:17:18.285932 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3094 12:17:18.286508
3095 12:17:18.287054
3096 12:17:18.295866 [DQSOSCAuto] RK1, (LSB)MR18= 0xff7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 404 ps
3097 12:17:18.296399 CH0 RK1: MR19=403, MR18=FF7
3098 12:17:18.302817 CH0_RK1: MR19=0x403, MR18=0xFF7, DQSOSC=404, MR23=63, INC=40, DEC=26
3099 12:17:18.306190 [RxdqsGatingPostProcess] freq 1200
3100 12:17:18.312484 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3101 12:17:18.315761 best DQS0 dly(2T, 0.5T) = (0, 11)
3102 12:17:18.319131 best DQS1 dly(2T, 0.5T) = (0, 12)
3103 12:17:18.322461 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3104 12:17:18.325945 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3105 12:17:18.329313 best DQS0 dly(2T, 0.5T) = (0, 11)
3106 12:17:18.329750 best DQS1 dly(2T, 0.5T) = (0, 11)
3107 12:17:18.332813 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3108 12:17:18.335585 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3109 12:17:18.338945 Pre-setting of DQS Precalculation
3110 12:17:18.345751 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3111 12:17:18.346194 ==
3112 12:17:18.349103 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 12:17:18.352420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 12:17:18.352994 ==
3115 12:17:18.358917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3116 12:17:18.365723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3117 12:17:18.372583 [CA 0] Center 37 (7~68) winsize 62
3118 12:17:18.376250 [CA 1] Center 37 (7~68) winsize 62
3119 12:17:18.379680 [CA 2] Center 35 (5~65) winsize 61
3120 12:17:18.382712 [CA 3] Center 34 (4~65) winsize 62
3121 12:17:18.386186 [CA 4] Center 34 (4~64) winsize 61
3122 12:17:18.389480 [CA 5] Center 33 (3~64) winsize 62
3123 12:17:18.389920
3124 12:17:18.392849 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3125 12:17:18.393324
3126 12:17:18.395915 [CATrainingPosCal] consider 1 rank data
3127 12:17:18.399398 u2DelayCellTimex100 = 270/100 ps
3128 12:17:18.402826 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3129 12:17:18.405832 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3130 12:17:18.412656 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3131 12:17:18.415652 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3132 12:17:18.419211 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3133 12:17:18.422606 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3134 12:17:18.423033
3135 12:17:18.425901 CA PerBit enable=1, Macro0, CA PI delay=33
3136 12:17:18.426328
3137 12:17:18.429259 [CBTSetCACLKResult] CA Dly = 33
3138 12:17:18.429725 CS Dly: 5 (0~36)
3139 12:17:18.432226 ==
3140 12:17:18.432675 Dram Type= 6, Freq= 0, CH_1, rank 1
3141 12:17:18.439186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 12:17:18.439617 ==
3143 12:17:18.442591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3144 12:17:18.449393 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3145 12:17:18.458446 [CA 0] Center 38 (8~68) winsize 61
3146 12:17:18.461904 [CA 1] Center 38 (7~69) winsize 63
3147 12:17:18.465163 [CA 2] Center 35 (5~66) winsize 62
3148 12:17:18.468423 [CA 3] Center 35 (5~65) winsize 61
3149 12:17:18.471557 [CA 4] Center 35 (5~65) winsize 61
3150 12:17:18.475152 [CA 5] Center 34 (4~64) winsize 61
3151 12:17:18.475593
3152 12:17:18.478250 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3153 12:17:18.478677
3154 12:17:18.481537 [CATrainingPosCal] consider 2 rank data
3155 12:17:18.484923 u2DelayCellTimex100 = 270/100 ps
3156 12:17:18.488408 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3157 12:17:18.495163 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3158 12:17:18.498543 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3159 12:17:18.501951 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3160 12:17:18.504915 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3161 12:17:18.508299 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3162 12:17:18.508797
3163 12:17:18.511238 CA PerBit enable=1, Macro0, CA PI delay=34
3164 12:17:18.511681
3165 12:17:18.514736 [CBTSetCACLKResult] CA Dly = 34
3166 12:17:18.515282 CS Dly: 6 (0~39)
3167 12:17:18.515815
3168 12:17:18.521091 ----->DramcWriteLeveling(PI) begin...
3169 12:17:18.521720 ==
3170 12:17:18.524577 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 12:17:18.527874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 12:17:18.528293 ==
3173 12:17:18.531276 Write leveling (Byte 0): 26 => 26
3174 12:17:18.534604 Write leveling (Byte 1): 27 => 27
3175 12:17:18.537948 DramcWriteLeveling(PI) end<-----
3176 12:17:18.538365
3177 12:17:18.538691 ==
3178 12:17:18.541371 Dram Type= 6, Freq= 0, CH_1, rank 0
3179 12:17:18.544833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3180 12:17:18.545343 ==
3181 12:17:18.547716 [Gating] SW mode calibration
3182 12:17:18.554530 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3183 12:17:18.560827 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3184 12:17:18.564450 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 12:17:18.567806 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 12:17:18.574310 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 12:17:18.577987 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 12:17:18.581070 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 12:17:18.587662 0 15 20 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 0)
3190 12:17:18.590907 0 15 24 | B1->B0 | 2b2b 2828 | 1 0 | (1 1) (1 0)
3191 12:17:18.594407 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3192 12:17:18.601031 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 12:17:18.604271 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 12:17:18.607530 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 12:17:18.613837 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 12:17:18.617413 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 12:17:18.620859 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 12:17:18.627391 1 0 24 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (0 0)
3199 12:17:18.630834 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 12:17:18.634104 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 12:17:18.637207 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 12:17:18.644031 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 12:17:18.647583 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 12:17:18.650628 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 12:17:18.657582 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3206 12:17:18.660874 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3207 12:17:18.663847 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 12:17:18.670350 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 12:17:18.673748 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 12:17:18.677141 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 12:17:18.683970 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 12:17:18.687366 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 12:17:18.690553 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 12:17:18.697055 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 12:17:18.700268 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 12:17:18.703745 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 12:17:18.710140 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 12:17:18.713567 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 12:17:18.717150 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 12:17:18.723687 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 12:17:18.726730 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3222 12:17:18.730017 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3223 12:17:18.736748 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 12:17:18.737216 Total UI for P1: 0, mck2ui 16
3225 12:17:18.743473 best dqsien dly found for B0: ( 1, 3, 22)
3226 12:17:18.743891 Total UI for P1: 0, mck2ui 16
3227 12:17:18.749762 best dqsien dly found for B1: ( 1, 3, 24)
3228 12:17:18.753189 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3229 12:17:18.756523 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3230 12:17:18.756617
3231 12:17:18.760162 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3232 12:17:18.763019 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3233 12:17:18.766490 [Gating] SW calibration Done
3234 12:17:18.766571 ==
3235 12:17:18.769758 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 12:17:18.773239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 12:17:18.773327 ==
3238 12:17:18.776724 RX Vref Scan: 0
3239 12:17:18.776829
3240 12:17:18.776899 RX Vref 0 -> 0, step: 1
3241 12:17:18.776964
3242 12:17:18.779598 RX Delay -40 -> 252, step: 8
3243 12:17:18.782981 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3244 12:17:18.789658 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3245 12:17:18.793189 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3246 12:17:18.796229 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3247 12:17:18.799715 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3248 12:17:18.802831 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3249 12:17:18.809506 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3250 12:17:18.812713 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3251 12:17:18.816281 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3252 12:17:18.819676 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3253 12:17:18.822553 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3254 12:17:18.829394 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3255 12:17:18.832747 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3256 12:17:18.835724 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3257 12:17:18.839041 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3258 12:17:18.842360 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3259 12:17:18.845825 ==
3260 12:17:18.849247 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 12:17:18.852654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 12:17:18.852761 ==
3263 12:17:18.852836 DQS Delay:
3264 12:17:18.855630 DQS0 = 0, DQS1 = 0
3265 12:17:18.855712 DQM Delay:
3266 12:17:18.859285 DQM0 = 119, DQM1 = 112
3267 12:17:18.859367 DQ Delay:
3268 12:17:18.862581 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3269 12:17:18.866257 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3270 12:17:18.868941 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3271 12:17:18.872418 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3272 12:17:18.872505
3273 12:17:18.872616
3274 12:17:18.872715 ==
3275 12:17:18.875710 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 12:17:18.882132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 12:17:18.882233 ==
3278 12:17:18.882312
3279 12:17:18.882386
3280 12:17:18.882473 TX Vref Scan disable
3281 12:17:18.886178 == TX Byte 0 ==
3282 12:17:18.889520 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3283 12:17:18.896108 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3284 12:17:18.896555 == TX Byte 1 ==
3285 12:17:18.899498 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3286 12:17:18.905740 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3287 12:17:18.906238 ==
3288 12:17:18.909446 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 12:17:18.912451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 12:17:18.913046 ==
3291 12:17:18.923855 TX Vref=22, minBit 1, minWin=24, winSum=404
3292 12:17:18.927080 TX Vref=24, minBit 10, minWin=24, winSum=409
3293 12:17:18.930587 TX Vref=26, minBit 3, minWin=25, winSum=417
3294 12:17:18.934420 TX Vref=28, minBit 3, minWin=25, winSum=420
3295 12:17:18.937494 TX Vref=30, minBit 10, minWin=25, winSum=423
3296 12:17:18.943638 TX Vref=32, minBit 1, minWin=26, winSum=426
3297 12:17:18.947304 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 32
3298 12:17:18.947730
3299 12:17:18.950635 Final TX Range 1 Vref 32
3300 12:17:18.951057
3301 12:17:18.951388 ==
3302 12:17:18.953592 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 12:17:18.957109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 12:17:18.957535 ==
3305 12:17:18.960506
3306 12:17:18.960969
3307 12:17:18.961311 TX Vref Scan disable
3308 12:17:18.963875 == TX Byte 0 ==
3309 12:17:18.967240 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3310 12:17:18.973887 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3311 12:17:18.974312 == TX Byte 1 ==
3312 12:17:18.977266 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3313 12:17:18.983415 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3314 12:17:18.983840
3315 12:17:18.984175 [DATLAT]
3316 12:17:18.984487 Freq=1200, CH1 RK0
3317 12:17:18.984822
3318 12:17:18.986824 DATLAT Default: 0xd
3319 12:17:18.987256 0, 0xFFFF, sum = 0
3320 12:17:18.990163 1, 0xFFFF, sum = 0
3321 12:17:18.993694 2, 0xFFFF, sum = 0
3322 12:17:18.994182 3, 0xFFFF, sum = 0
3323 12:17:18.996869 4, 0xFFFF, sum = 0
3324 12:17:18.997372 5, 0xFFFF, sum = 0
3325 12:17:19.000210 6, 0xFFFF, sum = 0
3326 12:17:19.000737 7, 0xFFFF, sum = 0
3327 12:17:19.003642 8, 0xFFFF, sum = 0
3328 12:17:19.004144 9, 0xFFFF, sum = 0
3329 12:17:19.006621 10, 0xFFFF, sum = 0
3330 12:17:19.007058 11, 0xFFFF, sum = 0
3331 12:17:19.010050 12, 0x0, sum = 1
3332 12:17:19.010498 13, 0x0, sum = 2
3333 12:17:19.013424 14, 0x0, sum = 3
3334 12:17:19.013856 15, 0x0, sum = 4
3335 12:17:19.016651 best_step = 13
3336 12:17:19.017233
3337 12:17:19.017573 ==
3338 12:17:19.019887 Dram Type= 6, Freq= 0, CH_1, rank 0
3339 12:17:19.023645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3340 12:17:19.024077 ==
3341 12:17:19.024416 RX Vref Scan: 1
3342 12:17:19.024730
3343 12:17:19.026763 Set Vref Range= 32 -> 127
3344 12:17:19.027189
3345 12:17:19.030483 RX Vref 32 -> 127, step: 1
3346 12:17:19.030927
3347 12:17:19.033795 RX Delay -13 -> 252, step: 4
3348 12:17:19.034243
3349 12:17:19.036747 Set Vref, RX VrefLevel [Byte0]: 32
3350 12:17:19.040135 [Byte1]: 32
3351 12:17:19.040582
3352 12:17:19.043622 Set Vref, RX VrefLevel [Byte0]: 33
3353 12:17:19.047016 [Byte1]: 33
3354 12:17:19.050383
3355 12:17:19.050918 Set Vref, RX VrefLevel [Byte0]: 34
3356 12:17:19.053527 [Byte1]: 34
3357 12:17:19.057908
3358 12:17:19.058297 Set Vref, RX VrefLevel [Byte0]: 35
3359 12:17:19.061287 [Byte1]: 35
3360 12:17:19.066104
3361 12:17:19.066543 Set Vref, RX VrefLevel [Byte0]: 36
3362 12:17:19.069144 [Byte1]: 36
3363 12:17:19.073759
3364 12:17:19.074216 Set Vref, RX VrefLevel [Byte0]: 37
3365 12:17:19.077057 [Byte1]: 37
3366 12:17:19.081486
3367 12:17:19.081921 Set Vref, RX VrefLevel [Byte0]: 38
3368 12:17:19.084761 [Byte1]: 38
3369 12:17:19.089580
3370 12:17:19.089910 Set Vref, RX VrefLevel [Byte0]: 39
3371 12:17:19.092709 [Byte1]: 39
3372 12:17:19.097230
3373 12:17:19.097452 Set Vref, RX VrefLevel [Byte0]: 40
3374 12:17:19.100391 [Byte1]: 40
3375 12:17:19.105293
3376 12:17:19.105516 Set Vref, RX VrefLevel [Byte0]: 41
3377 12:17:19.108292 [Byte1]: 41
3378 12:17:19.113081
3379 12:17:19.113311 Set Vref, RX VrefLevel [Byte0]: 42
3380 12:17:19.116664 [Byte1]: 42
3381 12:17:19.121056
3382 12:17:19.121493 Set Vref, RX VrefLevel [Byte0]: 43
3383 12:17:19.124426 [Byte1]: 43
3384 12:17:19.128826
3385 12:17:19.129244 Set Vref, RX VrefLevel [Byte0]: 44
3386 12:17:19.132297 [Byte1]: 44
3387 12:17:19.136669
3388 12:17:19.137219 Set Vref, RX VrefLevel [Byte0]: 45
3389 12:17:19.140394 [Byte1]: 45
3390 12:17:19.144851
3391 12:17:19.145258 Set Vref, RX VrefLevel [Byte0]: 46
3392 12:17:19.148336 [Byte1]: 46
3393 12:17:19.152474
3394 12:17:19.152927 Set Vref, RX VrefLevel [Byte0]: 47
3395 12:17:19.155682 [Byte1]: 47
3396 12:17:19.160638
3397 12:17:19.161089 Set Vref, RX VrefLevel [Byte0]: 48
3398 12:17:19.164059 [Byte1]: 48
3399 12:17:19.168295
3400 12:17:19.168701 Set Vref, RX VrefLevel [Byte0]: 49
3401 12:17:19.171765 [Byte1]: 49
3402 12:17:19.176544
3403 12:17:19.176977 Set Vref, RX VrefLevel [Byte0]: 50
3404 12:17:19.179851 [Byte1]: 50
3405 12:17:19.184244
3406 12:17:19.184645 Set Vref, RX VrefLevel [Byte0]: 51
3407 12:17:19.187552 [Byte1]: 51
3408 12:17:19.192005
3409 12:17:19.192470 Set Vref, RX VrefLevel [Byte0]: 52
3410 12:17:19.195420 [Byte1]: 52
3411 12:17:19.199896
3412 12:17:19.203287 Set Vref, RX VrefLevel [Byte0]: 53
3413 12:17:19.206520 [Byte1]: 53
3414 12:17:19.206974
3415 12:17:19.209508 Set Vref, RX VrefLevel [Byte0]: 54
3416 12:17:19.212868 [Byte1]: 54
3417 12:17:19.213295
3418 12:17:19.216245 Set Vref, RX VrefLevel [Byte0]: 55
3419 12:17:19.219602 [Byte1]: 55
3420 12:17:19.223704
3421 12:17:19.224161 Set Vref, RX VrefLevel [Byte0]: 56
3422 12:17:19.227060 [Byte1]: 56
3423 12:17:19.231593
3424 12:17:19.232019 Set Vref, RX VrefLevel [Byte0]: 57
3425 12:17:19.234566 [Byte1]: 57
3426 12:17:19.239079
3427 12:17:19.239505 Set Vref, RX VrefLevel [Byte0]: 58
3428 12:17:19.242642 [Byte1]: 58
3429 12:17:19.247363
3430 12:17:19.247790 Set Vref, RX VrefLevel [Byte0]: 59
3431 12:17:19.250654 [Byte1]: 59
3432 12:17:19.255439
3433 12:17:19.255862 Set Vref, RX VrefLevel [Byte0]: 60
3434 12:17:19.258953 [Byte1]: 60
3435 12:17:19.263463
3436 12:17:19.264025 Set Vref, RX VrefLevel [Byte0]: 61
3437 12:17:19.269306 [Byte1]: 61
3438 12:17:19.269759
3439 12:17:19.272716 Set Vref, RX VrefLevel [Byte0]: 62
3440 12:17:19.276325 [Byte1]: 62
3441 12:17:19.276888
3442 12:17:19.279340 Set Vref, RX VrefLevel [Byte0]: 63
3443 12:17:19.282952 [Byte1]: 63
3444 12:17:19.286906
3445 12:17:19.287338 Set Vref, RX VrefLevel [Byte0]: 64
3446 12:17:19.290403 [Byte1]: 64
3447 12:17:19.295068
3448 12:17:19.295666 Set Vref, RX VrefLevel [Byte0]: 65
3449 12:17:19.298151 [Byte1]: 65
3450 12:17:19.302553
3451 12:17:19.303029 Set Vref, RX VrefLevel [Byte0]: 66
3452 12:17:19.306220 [Byte1]: 66
3453 12:17:19.310496
3454 12:17:19.311074 Set Vref, RX VrefLevel [Byte0]: 67
3455 12:17:19.313932 [Byte1]: 67
3456 12:17:19.318744
3457 12:17:19.319347 Final RX Vref Byte 0 = 51 to rank0
3458 12:17:19.321582 Final RX Vref Byte 1 = 52 to rank0
3459 12:17:19.324941 Final RX Vref Byte 0 = 51 to rank1
3460 12:17:19.328483 Final RX Vref Byte 1 = 52 to rank1==
3461 12:17:19.331884 Dram Type= 6, Freq= 0, CH_1, rank 0
3462 12:17:19.338138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3463 12:17:19.338645 ==
3464 12:17:19.339141 DQS Delay:
3465 12:17:19.339705 DQS0 = 0, DQS1 = 0
3466 12:17:19.341602 DQM Delay:
3467 12:17:19.342225 DQM0 = 119, DQM1 = 112
3468 12:17:19.344879 DQ Delay:
3469 12:17:19.348112 DQ0 =122, DQ1 =112, DQ2 =112, DQ3 =118
3470 12:17:19.351571 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3471 12:17:19.354764 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3472 12:17:19.358377 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3473 12:17:19.358881
3474 12:17:19.359414
3475 12:17:19.368051 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3476 12:17:19.368636 CH1 RK0: MR19=404, MR18=417
3477 12:17:19.374431 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3478 12:17:19.375034
3479 12:17:19.377847 ----->DramcWriteLeveling(PI) begin...
3480 12:17:19.378435 ==
3481 12:17:19.381328 Dram Type= 6, Freq= 0, CH_1, rank 1
3482 12:17:19.384645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3483 12:17:19.387916 ==
3484 12:17:19.388509 Write leveling (Byte 0): 25 => 25
3485 12:17:19.391364 Write leveling (Byte 1): 30 => 30
3486 12:17:19.394774 DramcWriteLeveling(PI) end<-----
3487 12:17:19.395206
3488 12:17:19.395629 ==
3489 12:17:19.398258 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 12:17:19.404591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 12:17:19.405175 ==
3492 12:17:19.405711 [Gating] SW mode calibration
3493 12:17:19.414598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3494 12:17:19.417822 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3495 12:17:19.424339 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 12:17:19.427807 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 12:17:19.431020 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 12:17:19.437972 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 12:17:19.441362 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 12:17:19.444658 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 12:17:19.448058 0 15 24 | B1->B0 | 2828 3333 | 0 1 | (0 1) (1 0)
3502 12:17:19.454422 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3503 12:17:19.457958 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 12:17:19.461193 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 12:17:19.467710 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 12:17:19.471296 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 12:17:19.474708 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 12:17:19.481124 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 12:17:19.484509 1 0 24 | B1->B0 | 3737 2828 | 0 0 | (1 1) (0 0)
3510 12:17:19.487408 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3511 12:17:19.494331 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 12:17:19.497870 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 12:17:19.501249 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 12:17:19.507518 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 12:17:19.510871 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 12:17:19.514313 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 12:17:19.521060 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3518 12:17:19.524439 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3519 12:17:19.527401 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 12:17:19.534457 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 12:17:19.537448 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 12:17:19.540676 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 12:17:19.547164 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 12:17:19.550551 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 12:17:19.553493 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 12:17:19.560460 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 12:17:19.563850 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 12:17:19.566719 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 12:17:19.573513 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 12:17:19.577043 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 12:17:19.579983 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 12:17:19.586615 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 12:17:19.590068 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3534 12:17:19.592967 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3535 12:17:19.596581 Total UI for P1: 0, mck2ui 16
3536 12:17:19.599503 best dqsien dly found for B0: ( 1, 3, 24)
3537 12:17:19.606399 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 12:17:19.606496 Total UI for P1: 0, mck2ui 16
3539 12:17:19.613233 best dqsien dly found for B1: ( 1, 3, 26)
3540 12:17:19.616231 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3541 12:17:19.619525 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3542 12:17:19.619638
3543 12:17:19.622979 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3544 12:17:19.626169 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3545 12:17:19.629598 [Gating] SW calibration Done
3546 12:17:19.629736 ==
3547 12:17:19.633004 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 12:17:19.636517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 12:17:19.636673 ==
3550 12:17:19.639463 RX Vref Scan: 0
3551 12:17:19.639637
3552 12:17:19.639774 RX Vref 0 -> 0, step: 1
3553 12:17:19.639905
3554 12:17:19.642655 RX Delay -40 -> 252, step: 8
3555 12:17:19.645978 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3556 12:17:19.652620 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3557 12:17:19.656124 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3558 12:17:19.659559 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3559 12:17:19.663090 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3560 12:17:19.666221 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3561 12:17:19.672804 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3562 12:17:19.676212 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3563 12:17:19.679535 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3564 12:17:19.682406 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3565 12:17:19.685677 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3566 12:17:19.692347 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3567 12:17:19.695874 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3568 12:17:19.698993 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3569 12:17:19.702462 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3570 12:17:19.708855 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3571 12:17:19.709336 ==
3572 12:17:19.712144 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 12:17:19.715469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 12:17:19.715936 ==
3575 12:17:19.716311 DQS Delay:
3576 12:17:19.718812 DQS0 = 0, DQS1 = 0
3577 12:17:19.719236 DQM Delay:
3578 12:17:19.721665 DQM0 = 120, DQM1 = 113
3579 12:17:19.722229 DQ Delay:
3580 12:17:19.725171 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =123
3581 12:17:19.728387 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3582 12:17:19.731814 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3583 12:17:19.735414 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3584 12:17:19.738378
3585 12:17:19.738732
3586 12:17:19.739038 ==
3587 12:17:19.741821 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 12:17:19.745129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 12:17:19.745553 ==
3590 12:17:19.745885
3591 12:17:19.746196
3592 12:17:19.748549 TX Vref Scan disable
3593 12:17:19.749077 == TX Byte 0 ==
3594 12:17:19.754612 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3595 12:17:19.758018 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3596 12:17:19.758862 == TX Byte 1 ==
3597 12:17:19.764569 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3598 12:17:19.767863 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3599 12:17:19.768407 ==
3600 12:17:19.771095 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 12:17:19.774378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 12:17:19.775081 ==
3603 12:17:19.787382 TX Vref=22, minBit 3, minWin=25, winSum=421
3604 12:17:19.790878 TX Vref=24, minBit 0, minWin=26, winSum=421
3605 12:17:19.794145 TX Vref=26, minBit 1, minWin=26, winSum=427
3606 12:17:19.797286 TX Vref=28, minBit 7, minWin=26, winSum=430
3607 12:17:19.800726 TX Vref=30, minBit 1, minWin=26, winSum=431
3608 12:17:19.807381 TX Vref=32, minBit 1, minWin=26, winSum=426
3609 12:17:19.810801 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3610 12:17:19.811297
3611 12:17:19.814233 Final TX Range 1 Vref 30
3612 12:17:19.814791
3613 12:17:19.815132 ==
3614 12:17:19.817551 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 12:17:19.820561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 12:17:19.823986 ==
3617 12:17:19.824585
3618 12:17:19.825108
3619 12:17:19.825433 TX Vref Scan disable
3620 12:17:19.827360 == TX Byte 0 ==
3621 12:17:19.830723 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3622 12:17:19.837103 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3623 12:17:19.837586 == TX Byte 1 ==
3624 12:17:19.840612 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3625 12:17:19.846892 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3626 12:17:19.847308
3627 12:17:19.847635 [DATLAT]
3628 12:17:19.847942 Freq=1200, CH1 RK1
3629 12:17:19.848243
3630 12:17:19.850392 DATLAT Default: 0xd
3631 12:17:19.853751 0, 0xFFFF, sum = 0
3632 12:17:19.854196 1, 0xFFFF, sum = 0
3633 12:17:19.857023 2, 0xFFFF, sum = 0
3634 12:17:19.857591 3, 0xFFFF, sum = 0
3635 12:17:19.860434 4, 0xFFFF, sum = 0
3636 12:17:19.861071 5, 0xFFFF, sum = 0
3637 12:17:19.863323 6, 0xFFFF, sum = 0
3638 12:17:19.863800 7, 0xFFFF, sum = 0
3639 12:17:19.866844 8, 0xFFFF, sum = 0
3640 12:17:19.867374 9, 0xFFFF, sum = 0
3641 12:17:19.870195 10, 0xFFFF, sum = 0
3642 12:17:19.870627 11, 0xFFFF, sum = 0
3643 12:17:19.873724 12, 0x0, sum = 1
3644 12:17:19.874181 13, 0x0, sum = 2
3645 12:17:19.876994 14, 0x0, sum = 3
3646 12:17:19.877443 15, 0x0, sum = 4
3647 12:17:19.880414 best_step = 13
3648 12:17:19.880985
3649 12:17:19.881397 ==
3650 12:17:19.883364 Dram Type= 6, Freq= 0, CH_1, rank 1
3651 12:17:19.886781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3652 12:17:19.887204 ==
3653 12:17:19.890145 RX Vref Scan: 0
3654 12:17:19.890559
3655 12:17:19.890977 RX Vref 0 -> 0, step: 1
3656 12:17:19.891565
3657 12:17:19.893400 RX Delay -13 -> 252, step: 4
3658 12:17:19.900038 iDelay=191, Bit 0, Center 122 (63 ~ 182) 120
3659 12:17:19.903369 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3660 12:17:19.906493 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3661 12:17:19.910008 iDelay=191, Bit 3, Center 118 (59 ~ 178) 120
3662 12:17:19.913208 iDelay=191, Bit 4, Center 122 (63 ~ 182) 120
3663 12:17:19.919694 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3664 12:17:19.923102 iDelay=191, Bit 6, Center 126 (67 ~ 186) 120
3665 12:17:19.926322 iDelay=191, Bit 7, Center 116 (55 ~ 178) 124
3666 12:17:19.929601 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3667 12:17:19.932996 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3668 12:17:19.939875 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3669 12:17:19.942633 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3670 12:17:19.946217 iDelay=191, Bit 12, Center 122 (59 ~ 186) 128
3671 12:17:19.949544 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3672 12:17:19.956292 iDelay=191, Bit 14, Center 122 (59 ~ 186) 128
3673 12:17:19.959427 iDelay=191, Bit 15, Center 124 (59 ~ 190) 132
3674 12:17:19.959962 ==
3675 12:17:19.962605 Dram Type= 6, Freq= 0, CH_1, rank 1
3676 12:17:19.965578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3677 12:17:19.965661 ==
3678 12:17:19.965725 DQS Delay:
3679 12:17:19.969050 DQS0 = 0, DQS1 = 0
3680 12:17:19.969131 DQM Delay:
3681 12:17:19.972297 DQM0 = 119, DQM1 = 113
3682 12:17:19.972378 DQ Delay:
3683 12:17:19.975702 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3684 12:17:19.979002 DQ4 =122, DQ5 =128, DQ6 =126, DQ7 =116
3685 12:17:19.982299 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3686 12:17:19.988650 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3687 12:17:19.988770
3688 12:17:19.988878
3689 12:17:19.995455 [DQSOSCAuto] RK1, (LSB)MR18= 0x9ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3690 12:17:19.998559 CH1 RK1: MR19=403, MR18=9ED
3691 12:17:20.005213 CH1_RK1: MR19=0x403, MR18=0x9ED, DQSOSC=406, MR23=63, INC=39, DEC=26
3692 12:17:20.008415 [RxdqsGatingPostProcess] freq 1200
3693 12:17:20.011492 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3694 12:17:20.015096 best DQS0 dly(2T, 0.5T) = (0, 11)
3695 12:17:20.018194 best DQS1 dly(2T, 0.5T) = (0, 11)
3696 12:17:20.021831 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3697 12:17:20.024934 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3698 12:17:20.028485 best DQS0 dly(2T, 0.5T) = (0, 11)
3699 12:17:20.031991 best DQS1 dly(2T, 0.5T) = (0, 11)
3700 12:17:20.035287 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3701 12:17:20.038810 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3702 12:17:20.041776 Pre-setting of DQS Precalculation
3703 12:17:20.045164 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3704 12:17:20.054949 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3705 12:17:20.061325 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3706 12:17:20.061409
3707 12:17:20.061474
3708 12:17:20.064616 [Calibration Summary] 2400 Mbps
3709 12:17:20.064700 CH 0, Rank 0
3710 12:17:20.067990 SW Impedance : PASS
3711 12:17:20.068073 DUTY Scan : NO K
3712 12:17:20.071301 ZQ Calibration : PASS
3713 12:17:20.074693 Jitter Meter : NO K
3714 12:17:20.074777 CBT Training : PASS
3715 12:17:20.078127 Write leveling : PASS
3716 12:17:20.081518 RX DQS gating : PASS
3717 12:17:20.081607 RX DQ/DQS(RDDQC) : PASS
3718 12:17:20.084301 TX DQ/DQS : PASS
3719 12:17:20.087735 RX DATLAT : PASS
3720 12:17:20.087819 RX DQ/DQS(Engine): PASS
3721 12:17:20.091161 TX OE : NO K
3722 12:17:20.091245 All Pass.
3723 12:17:20.091311
3724 12:17:20.094634 CH 0, Rank 1
3725 12:17:20.094717 SW Impedance : PASS
3726 12:17:20.097636 DUTY Scan : NO K
3727 12:17:20.100879 ZQ Calibration : PASS
3728 12:17:20.100962 Jitter Meter : NO K
3729 12:17:20.104211 CBT Training : PASS
3730 12:17:20.107725 Write leveling : PASS
3731 12:17:20.107814 RX DQS gating : PASS
3732 12:17:20.111237 RX DQ/DQS(RDDQC) : PASS
3733 12:17:20.111325 TX DQ/DQS : PASS
3734 12:17:20.114180 RX DATLAT : PASS
3735 12:17:20.117447 RX DQ/DQS(Engine): PASS
3736 12:17:20.117543 TX OE : NO K
3737 12:17:20.121091 All Pass.
3738 12:17:20.121195
3739 12:17:20.121277 CH 1, Rank 0
3740 12:17:20.124113 SW Impedance : PASS
3741 12:17:20.124226 DUTY Scan : NO K
3742 12:17:20.127274 ZQ Calibration : PASS
3743 12:17:20.130846 Jitter Meter : NO K
3744 12:17:20.130969 CBT Training : PASS
3745 12:17:20.133948 Write leveling : PASS
3746 12:17:20.136881 RX DQS gating : PASS
3747 12:17:20.137020 RX DQ/DQS(RDDQC) : PASS
3748 12:17:20.140424 TX DQ/DQS : PASS
3749 12:17:20.143877 RX DATLAT : PASS
3750 12:17:20.144032 RX DQ/DQS(Engine): PASS
3751 12:17:20.147261 TX OE : NO K
3752 12:17:20.147438 All Pass.
3753 12:17:20.147578
3754 12:17:20.150007 CH 1, Rank 1
3755 12:17:20.150090 SW Impedance : PASS
3756 12:17:20.153547 DUTY Scan : NO K
3757 12:17:20.157033 ZQ Calibration : PASS
3758 12:17:20.157116 Jitter Meter : NO K
3759 12:17:20.160411 CBT Training : PASS
3760 12:17:20.163718 Write leveling : PASS
3761 12:17:20.163801 RX DQS gating : PASS
3762 12:17:20.166709 RX DQ/DQS(RDDQC) : PASS
3763 12:17:20.170123 TX DQ/DQS : PASS
3764 12:17:20.170212 RX DATLAT : PASS
3765 12:17:20.173384 RX DQ/DQS(Engine): PASS
3766 12:17:20.176759 TX OE : NO K
3767 12:17:20.176868 All Pass.
3768 12:17:20.176944
3769 12:17:20.177015 DramC Write-DBI off
3770 12:17:20.180103 PER_BANK_REFRESH: Hybrid Mode
3771 12:17:20.183035 TX_TRACKING: ON
3772 12:17:20.189767 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3773 12:17:20.196144 [FAST_K] Save calibration result to emmc
3774 12:17:20.199458 dramc_set_vcore_voltage set vcore to 650000
3775 12:17:20.199567 Read voltage for 600, 5
3776 12:17:20.202882 Vio18 = 0
3777 12:17:20.202982 Vcore = 650000
3778 12:17:20.203072 Vdram = 0
3779 12:17:20.206310 Vddq = 0
3780 12:17:20.206407 Vmddr = 0
3781 12:17:20.209640 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3782 12:17:20.216432 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3783 12:17:20.219746 MEM_TYPE=3, freq_sel=19
3784 12:17:20.222598 sv_algorithm_assistance_LP4_1600
3785 12:17:20.226292 ============ PULL DRAM RESETB DOWN ============
3786 12:17:20.229394 ========== PULL DRAM RESETB DOWN end =========
3787 12:17:20.235944 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3788 12:17:20.239130 ===================================
3789 12:17:20.239271 LPDDR4 DRAM CONFIGURATION
3790 12:17:20.242745 ===================================
3791 12:17:20.246070 EX_ROW_EN[0] = 0x0
3792 12:17:20.246184 EX_ROW_EN[1] = 0x0
3793 12:17:20.249456 LP4Y_EN = 0x0
3794 12:17:20.252304 WORK_FSP = 0x0
3795 12:17:20.252416 WL = 0x2
3796 12:17:20.255741 RL = 0x2
3797 12:17:20.255824 BL = 0x2
3798 12:17:20.259279 RPST = 0x0
3799 12:17:20.259368 RD_PRE = 0x0
3800 12:17:20.262676 WR_PRE = 0x1
3801 12:17:20.262764 WR_PST = 0x0
3802 12:17:20.265854 DBI_WR = 0x0
3803 12:17:20.266034 DBI_RD = 0x0
3804 12:17:20.269136 OTF = 0x1
3805 12:17:20.272282 ===================================
3806 12:17:20.275653 ===================================
3807 12:17:20.275759 ANA top config
3808 12:17:20.278980 ===================================
3809 12:17:20.282474 DLL_ASYNC_EN = 0
3810 12:17:20.285332 ALL_SLAVE_EN = 1
3811 12:17:20.285421 NEW_RANK_MODE = 1
3812 12:17:20.289094 DLL_IDLE_MODE = 1
3813 12:17:20.292164 LP45_APHY_COMB_EN = 1
3814 12:17:20.295522 TX_ODT_DIS = 1
3815 12:17:20.298455 NEW_8X_MODE = 1
3816 12:17:20.301927 ===================================
3817 12:17:20.305391 ===================================
3818 12:17:20.308670 data_rate = 1200
3819 12:17:20.308823 CKR = 1
3820 12:17:20.311987 DQ_P2S_RATIO = 8
3821 12:17:20.315297 ===================================
3822 12:17:20.318289 CA_P2S_RATIO = 8
3823 12:17:20.321789 DQ_CA_OPEN = 0
3824 12:17:20.325174 DQ_SEMI_OPEN = 0
3825 12:17:20.328065 CA_SEMI_OPEN = 0
3826 12:17:20.328141 CA_FULL_RATE = 0
3827 12:17:20.331370 DQ_CKDIV4_EN = 1
3828 12:17:20.334706 CA_CKDIV4_EN = 1
3829 12:17:20.338281 CA_PREDIV_EN = 0
3830 12:17:20.341615 PH8_DLY = 0
3831 12:17:20.344586 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3832 12:17:20.344681 DQ_AAMCK_DIV = 4
3833 12:17:20.348128 CA_AAMCK_DIV = 4
3834 12:17:20.351316 CA_ADMCK_DIV = 4
3835 12:17:20.354463 DQ_TRACK_CA_EN = 0
3836 12:17:20.357745 CA_PICK = 600
3837 12:17:20.361114 CA_MCKIO = 600
3838 12:17:20.361190 MCKIO_SEMI = 0
3839 12:17:20.364497 PLL_FREQ = 2288
3840 12:17:20.367834 DQ_UI_PI_RATIO = 32
3841 12:17:20.371309 CA_UI_PI_RATIO = 0
3842 12:17:20.374344 ===================================
3843 12:17:20.377972 ===================================
3844 12:17:20.381190 memory_type:LPDDR4
3845 12:17:20.384469 GP_NUM : 10
3846 12:17:20.384557 SRAM_EN : 1
3847 12:17:20.387586 MD32_EN : 0
3848 12:17:20.390641 ===================================
3849 12:17:20.390827 [ANA_INIT] >>>>>>>>>>>>>>
3850 12:17:20.394085 <<<<<< [CONFIGURE PHASE]: ANA_TX
3851 12:17:20.397404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3852 12:17:20.400596 ===================================
3853 12:17:20.404037 data_rate = 1200,PCW = 0X5800
3854 12:17:20.406823 ===================================
3855 12:17:20.410455 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3856 12:17:20.416992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3857 12:17:20.423719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3858 12:17:20.426618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3859 12:17:20.430129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3860 12:17:20.433748 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3861 12:17:20.436685 [ANA_INIT] flow start
3862 12:17:20.436788 [ANA_INIT] PLL >>>>>>>>
3863 12:17:20.440083 [ANA_INIT] PLL <<<<<<<<
3864 12:17:20.443338 [ANA_INIT] MIDPI >>>>>>>>
3865 12:17:20.446965 [ANA_INIT] MIDPI <<<<<<<<
3866 12:17:20.447066 [ANA_INIT] DLL >>>>>>>>
3867 12:17:20.450175 [ANA_INIT] flow end
3868 12:17:20.453137 ============ LP4 DIFF to SE enter ============
3869 12:17:20.456218 ============ LP4 DIFF to SE exit ============
3870 12:17:20.459840 [ANA_INIT] <<<<<<<<<<<<<
3871 12:17:20.463061 [Flow] Enable top DCM control >>>>>
3872 12:17:20.466291 [Flow] Enable top DCM control <<<<<
3873 12:17:20.469632 Enable DLL master slave shuffle
3874 12:17:20.476400 ==============================================================
3875 12:17:20.476484 Gating Mode config
3876 12:17:20.482845 ==============================================================
3877 12:17:20.482961 Config description:
3878 12:17:20.492695 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3879 12:17:20.499092 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3880 12:17:20.505922 SELPH_MODE 0: By rank 1: By Phase
3881 12:17:20.512492 ==============================================================
3882 12:17:20.512584 GAT_TRACK_EN = 1
3883 12:17:20.515493 RX_GATING_MODE = 2
3884 12:17:20.518869 RX_GATING_TRACK_MODE = 2
3885 12:17:20.522208 SELPH_MODE = 1
3886 12:17:20.525764 PICG_EARLY_EN = 1
3887 12:17:20.528585 VALID_LAT_VALUE = 1
3888 12:17:20.535527 ==============================================================
3889 12:17:20.538759 Enter into Gating configuration >>>>
3890 12:17:20.542056 Exit from Gating configuration <<<<
3891 12:17:20.545069 Enter into DVFS_PRE_config >>>>>
3892 12:17:20.555048 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3893 12:17:20.558213 Exit from DVFS_PRE_config <<<<<
3894 12:17:20.561977 Enter into PICG configuration >>>>
3895 12:17:20.565095 Exit from PICG configuration <<<<
3896 12:17:20.568275 [RX_INPUT] configuration >>>>>
3897 12:17:20.571951 [RX_INPUT] configuration <<<<<
3898 12:17:20.574994 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3899 12:17:20.581947 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3900 12:17:20.588325 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3901 12:17:20.591404 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3902 12:17:20.597935 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3903 12:17:20.605061 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3904 12:17:20.608372 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3905 12:17:20.615125 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3906 12:17:20.618572 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3907 12:17:20.621678 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3908 12:17:20.625260 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3909 12:17:20.631819 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3910 12:17:20.635248 ===================================
3911 12:17:20.635848 LPDDR4 DRAM CONFIGURATION
3912 12:17:20.638275 ===================================
3913 12:17:20.641640 EX_ROW_EN[0] = 0x0
3914 12:17:20.645008 EX_ROW_EN[1] = 0x0
3915 12:17:20.645492 LP4Y_EN = 0x0
3916 12:17:20.648342 WORK_FSP = 0x0
3917 12:17:20.648899 WL = 0x2
3918 12:17:20.651718 RL = 0x2
3919 12:17:20.652238 BL = 0x2
3920 12:17:20.655018 RPST = 0x0
3921 12:17:20.655517 RD_PRE = 0x0
3922 12:17:20.658191 WR_PRE = 0x1
3923 12:17:20.658816 WR_PST = 0x0
3924 12:17:20.661447 DBI_WR = 0x0
3925 12:17:20.661970 DBI_RD = 0x0
3926 12:17:20.664617 OTF = 0x1
3927 12:17:20.668147 ===================================
3928 12:17:20.671653 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3929 12:17:20.674899 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3930 12:17:20.681428 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3931 12:17:20.684655 ===================================
3932 12:17:20.685355 LPDDR4 DRAM CONFIGURATION
3933 12:17:20.688078 ===================================
3934 12:17:20.690987 EX_ROW_EN[0] = 0x10
3935 12:17:20.694641 EX_ROW_EN[1] = 0x0
3936 12:17:20.695033 LP4Y_EN = 0x0
3937 12:17:20.698110 WORK_FSP = 0x0
3938 12:17:20.698396 WL = 0x2
3939 12:17:20.701065 RL = 0x2
3940 12:17:20.701323 BL = 0x2
3941 12:17:20.704524 RPST = 0x0
3942 12:17:20.704919 RD_PRE = 0x0
3943 12:17:20.707858 WR_PRE = 0x1
3944 12:17:20.708229 WR_PST = 0x0
3945 12:17:20.710975 DBI_WR = 0x0
3946 12:17:20.711398 DBI_RD = 0x0
3947 12:17:20.714352 OTF = 0x1
3948 12:17:20.717727 ===================================
3949 12:17:20.724098 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3950 12:17:20.727550 nWR fixed to 30
3951 12:17:20.727634 [ModeRegInit_LP4] CH0 RK0
3952 12:17:20.730736 [ModeRegInit_LP4] CH0 RK1
3953 12:17:20.734194 [ModeRegInit_LP4] CH1 RK0
3954 12:17:20.737226 [ModeRegInit_LP4] CH1 RK1
3955 12:17:20.737309 match AC timing 17
3956 12:17:20.744025 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3957 12:17:20.747377 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3958 12:17:20.750422 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3959 12:17:20.757241 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3960 12:17:20.760538 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3961 12:17:20.760640 ==
3962 12:17:20.763935 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 12:17:20.766748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 12:17:20.766848 ==
3965 12:17:20.773542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3966 12:17:20.780483 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3967 12:17:20.783728 [CA 0] Center 36 (6~67) winsize 62
3968 12:17:20.786910 [CA 1] Center 36 (6~67) winsize 62
3969 12:17:20.790204 [CA 2] Center 34 (4~65) winsize 62
3970 12:17:20.793593 [CA 3] Center 34 (4~65) winsize 62
3971 12:17:20.796815 [CA 4] Center 33 (3~64) winsize 62
3972 12:17:20.800141 [CA 5] Center 33 (3~64) winsize 62
3973 12:17:20.800303
3974 12:17:20.803496 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3975 12:17:20.803631
3976 12:17:20.806495 [CATrainingPosCal] consider 1 rank data
3977 12:17:20.809897 u2DelayCellTimex100 = 270/100 ps
3978 12:17:20.813269 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3979 12:17:20.816576 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3980 12:17:20.820116 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3981 12:17:20.823395 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3982 12:17:20.826780 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3983 12:17:20.829776 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3984 12:17:20.829852
3985 12:17:20.836725 CA PerBit enable=1, Macro0, CA PI delay=33
3986 12:17:20.836847
3987 12:17:20.839625 [CBTSetCACLKResult] CA Dly = 33
3988 12:17:20.839725 CS Dly: 5 (0~36)
3989 12:17:20.839815 ==
3990 12:17:20.843297 Dram Type= 6, Freq= 0, CH_0, rank 1
3991 12:17:20.846627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 12:17:20.846746 ==
3993 12:17:20.852912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3994 12:17:20.859933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3995 12:17:20.863159 [CA 0] Center 36 (6~67) winsize 62
3996 12:17:20.866423 [CA 1] Center 36 (6~67) winsize 62
3997 12:17:20.869682 [CA 2] Center 35 (4~66) winsize 63
3998 12:17:20.873229 [CA 3] Center 35 (4~66) winsize 63
3999 12:17:20.876561 [CA 4] Center 34 (3~65) winsize 63
4000 12:17:20.879887 [CA 5] Center 34 (3~65) winsize 63
4001 12:17:20.880414
4002 12:17:20.883028 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4003 12:17:20.883481
4004 12:17:20.886510 [CATrainingPosCal] consider 2 rank data
4005 12:17:20.889957 u2DelayCellTimex100 = 270/100 ps
4006 12:17:20.893223 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4007 12:17:20.896115 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4008 12:17:20.899583 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4009 12:17:20.906199 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4010 12:17:20.909528 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4011 12:17:20.912931 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4012 12:17:20.913385
4013 12:17:20.916255 CA PerBit enable=1, Macro0, CA PI delay=33
4014 12:17:20.916648
4015 12:17:20.919459 [CBTSetCACLKResult] CA Dly = 33
4016 12:17:20.919994 CS Dly: 5 (0~37)
4017 12:17:20.920428
4018 12:17:20.922833 ----->DramcWriteLeveling(PI) begin...
4019 12:17:20.923224 ==
4020 12:17:20.926336 Dram Type= 6, Freq= 0, CH_0, rank 0
4021 12:17:20.932565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4022 12:17:20.933037 ==
4023 12:17:20.936139 Write leveling (Byte 0): 31 => 31
4024 12:17:20.939314 Write leveling (Byte 1): 30 => 30
4025 12:17:20.939759 DramcWriteLeveling(PI) end<-----
4026 12:17:20.942730
4027 12:17:20.943297 ==
4028 12:17:20.945837 Dram Type= 6, Freq= 0, CH_0, rank 0
4029 12:17:20.949316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4030 12:17:20.949747 ==
4031 12:17:20.953030 [Gating] SW mode calibration
4032 12:17:20.959041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4033 12:17:20.962585 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4034 12:17:20.969226 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4035 12:17:20.972388 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 12:17:20.975303 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 12:17:20.982541 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4038 12:17:20.985772 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4039 12:17:20.988910 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 12:17:20.995472 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 12:17:20.998736 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 12:17:21.001951 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 12:17:21.008393 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 12:17:21.011539 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 12:17:21.015018 0 10 12 | B1->B0 | 2727 3b3b | 0 0 | (0 0) (0 0)
4046 12:17:21.021407 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4047 12:17:21.024648 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 12:17:21.028128 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 12:17:21.034470 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 12:17:21.037907 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 12:17:21.041269 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 12:17:21.047843 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 12:17:21.051277 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4054 12:17:21.054597 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4055 12:17:21.061136 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 12:17:21.064595 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 12:17:21.067993 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 12:17:21.074277 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 12:17:21.077678 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 12:17:21.081182 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 12:17:21.087668 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 12:17:21.091523 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 12:17:21.094550 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 12:17:21.101080 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 12:17:21.104524 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 12:17:21.107627 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 12:17:21.114252 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:17:21.117679 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:17:21.121103 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4070 12:17:21.127550 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 12:17:21.127976 Total UI for P1: 0, mck2ui 16
4072 12:17:21.134273 best dqsien dly found for B0: ( 0, 13, 12)
4073 12:17:21.134845 Total UI for P1: 0, mck2ui 16
4074 12:17:21.141018 best dqsien dly found for B1: ( 0, 13, 12)
4075 12:17:21.144041 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4076 12:17:21.147508 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4077 12:17:21.148221
4078 12:17:21.150635 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4079 12:17:21.153985 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4080 12:17:21.157510 [Gating] SW calibration Done
4081 12:17:21.157935 ==
4082 12:17:21.160353 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 12:17:21.163786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 12:17:21.164315 ==
4085 12:17:21.167213 RX Vref Scan: 0
4086 12:17:21.167757
4087 12:17:21.168231 RX Vref 0 -> 0, step: 1
4088 12:17:21.170860
4089 12:17:21.171321 RX Delay -230 -> 252, step: 16
4090 12:17:21.176997 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4091 12:17:21.180409 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4092 12:17:21.183729 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4093 12:17:21.187061 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4094 12:17:21.193699 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4095 12:17:21.196758 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4096 12:17:21.199911 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4097 12:17:21.203705 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4098 12:17:21.206897 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4099 12:17:21.213166 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4100 12:17:21.216809 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4101 12:17:21.219907 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4102 12:17:21.223340 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4103 12:17:21.229830 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4104 12:17:21.232970 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4105 12:17:21.236284 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4106 12:17:21.236753 ==
4107 12:17:21.239744 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 12:17:21.246193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 12:17:21.246776 ==
4110 12:17:21.247284 DQS Delay:
4111 12:17:21.247765 DQS0 = 0, DQS1 = 0
4112 12:17:21.249619 DQM Delay:
4113 12:17:21.250134 DQM0 = 51, DQM1 = 41
4114 12:17:21.252862 DQ Delay:
4115 12:17:21.256232 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4116 12:17:21.259601 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =57
4117 12:17:21.260087 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4118 12:17:21.265981 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4119 12:17:21.266405
4120 12:17:21.266740
4121 12:17:21.267051 ==
4122 12:17:21.269597 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 12:17:21.273035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 12:17:21.273488 ==
4125 12:17:21.273822
4126 12:17:21.274131
4127 12:17:21.276399 TX Vref Scan disable
4128 12:17:21.276846 == TX Byte 0 ==
4129 12:17:21.282658 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4130 12:17:21.286100 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4131 12:17:21.286540 == TX Byte 1 ==
4132 12:17:21.292875 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4133 12:17:21.295921 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4134 12:17:21.296347 ==
4135 12:17:21.299169 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 12:17:21.302674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 12:17:21.303103 ==
4138 12:17:21.303440
4139 12:17:21.305726
4140 12:17:21.306169 TX Vref Scan disable
4141 12:17:21.309417 == TX Byte 0 ==
4142 12:17:21.312827 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4143 12:17:21.319136 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4144 12:17:21.319585 == TX Byte 1 ==
4145 12:17:21.322689 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4146 12:17:21.329256 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4147 12:17:21.329708
4148 12:17:21.330045 [DATLAT]
4149 12:17:21.330359 Freq=600, CH0 RK0
4150 12:17:21.330663
4151 12:17:21.332327 DATLAT Default: 0x9
4152 12:17:21.332677 0, 0xFFFF, sum = 0
4153 12:17:21.335704 1, 0xFFFF, sum = 0
4154 12:17:21.338561 2, 0xFFFF, sum = 0
4155 12:17:21.338645 3, 0xFFFF, sum = 0
4156 12:17:21.341959 4, 0xFFFF, sum = 0
4157 12:17:21.342043 5, 0xFFFF, sum = 0
4158 12:17:21.345324 6, 0xFFFF, sum = 0
4159 12:17:21.345409 7, 0xFFFF, sum = 0
4160 12:17:21.348210 8, 0x0, sum = 1
4161 12:17:21.348294 9, 0x0, sum = 2
4162 12:17:21.351576 10, 0x0, sum = 3
4163 12:17:21.351661 11, 0x0, sum = 4
4164 12:17:21.351727 best_step = 9
4165 12:17:21.351789
4166 12:17:21.355025 ==
4167 12:17:21.358446 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 12:17:21.361969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 12:17:21.362052 ==
4170 12:17:21.362118 RX Vref Scan: 1
4171 12:17:21.362180
4172 12:17:21.364886 RX Vref 0 -> 0, step: 1
4173 12:17:21.364969
4174 12:17:21.368433 RX Delay -179 -> 252, step: 8
4175 12:17:21.368518
4176 12:17:21.371794 Set Vref, RX VrefLevel [Byte0]: 59
4177 12:17:21.375109 [Byte1]: 49
4178 12:17:21.375196
4179 12:17:21.377996 Final RX Vref Byte 0 = 59 to rank0
4180 12:17:21.381480 Final RX Vref Byte 1 = 49 to rank0
4181 12:17:21.384755 Final RX Vref Byte 0 = 59 to rank1
4182 12:17:21.388267 Final RX Vref Byte 1 = 49 to rank1==
4183 12:17:21.391640 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 12:17:21.394921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 12:17:21.395001 ==
4186 12:17:21.398002 DQS Delay:
4187 12:17:21.398074 DQS0 = 0, DQS1 = 0
4188 12:17:21.401340 DQM Delay:
4189 12:17:21.401423 DQM0 = 48, DQM1 = 39
4190 12:17:21.401488 DQ Delay:
4191 12:17:21.404708 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4192 12:17:21.407866 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4193 12:17:21.411479 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4194 12:17:21.414481 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4195 12:17:21.414566
4196 12:17:21.417697
4197 12:17:21.424464 [DQSOSCAuto] RK0, (LSB)MR18= 0x5a55, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4198 12:17:21.427779 CH0 RK0: MR19=808, MR18=5A55
4199 12:17:21.434441 CH0_RK0: MR19=0x808, MR18=0x5A55, DQSOSC=392, MR23=63, INC=170, DEC=113
4200 12:17:21.434531
4201 12:17:21.437530 ----->DramcWriteLeveling(PI) begin...
4202 12:17:21.437613 ==
4203 12:17:21.440870 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 12:17:21.444217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 12:17:21.444294 ==
4206 12:17:21.448125 Write leveling (Byte 0): 32 => 32
4207 12:17:21.451141 Write leveling (Byte 1): 32 => 32
4208 12:17:21.454503 DramcWriteLeveling(PI) end<-----
4209 12:17:21.454925
4210 12:17:21.455284 ==
4211 12:17:21.457888 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 12:17:21.461148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 12:17:21.461600 ==
4214 12:17:21.464543 [Gating] SW mode calibration
4215 12:17:21.470797 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4216 12:17:21.477845 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4217 12:17:21.481323 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 12:17:21.484355 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4219 12:17:21.490906 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 12:17:21.493991 0 9 12 | B1->B0 | 3333 3232 | 0 1 | (0 1) (1 0)
4221 12:17:21.497337 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4222 12:17:21.503764 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 12:17:21.507248 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 12:17:21.510129 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 12:17:21.517049 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 12:17:21.520138 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 12:17:21.523583 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 12:17:21.530123 0 10 12 | B1->B0 | 2c2c 3030 | 0 1 | (0 0) (0 0)
4229 12:17:21.533659 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4230 12:17:21.536643 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 12:17:21.543417 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 12:17:21.546542 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 12:17:21.550409 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 12:17:21.556993 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 12:17:21.560289 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 12:17:21.563662 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 12:17:21.570836 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4238 12:17:21.573327 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 12:17:21.577090 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 12:17:21.583621 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 12:17:21.587275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 12:17:21.589971 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 12:17:21.596835 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 12:17:21.599963 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 12:17:21.603296 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 12:17:21.609449 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 12:17:21.612696 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 12:17:21.616142 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 12:17:21.622732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 12:17:21.625892 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:17:21.629419 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:17:21.635904 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 12:17:21.639199 Total UI for P1: 0, mck2ui 16
4254 12:17:21.642342 best dqsien dly found for B0: ( 0, 13, 10)
4255 12:17:21.645862 Total UI for P1: 0, mck2ui 16
4256 12:17:21.648988 best dqsien dly found for B1: ( 0, 13, 10)
4257 12:17:21.652102 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4258 12:17:21.655545 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4259 12:17:21.655672
4260 12:17:21.659123 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4261 12:17:21.662503 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4262 12:17:21.665425 [Gating] SW calibration Done
4263 12:17:21.665513 ==
4264 12:17:21.668726 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 12:17:21.671982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 12:17:21.672074 ==
4267 12:17:21.675503 RX Vref Scan: 0
4268 12:17:21.675612
4269 12:17:21.678899 RX Vref 0 -> 0, step: 1
4270 12:17:21.678973
4271 12:17:21.679036 RX Delay -230 -> 252, step: 16
4272 12:17:21.685232 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4273 12:17:21.688589 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4274 12:17:21.692024 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4275 12:17:21.695466 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4276 12:17:21.702167 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4277 12:17:21.705034 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4278 12:17:21.708419 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4279 12:17:21.711875 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4280 12:17:21.715283 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4281 12:17:21.721719 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4282 12:17:21.725027 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4283 12:17:21.728396 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4284 12:17:21.731844 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4285 12:17:21.738241 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4286 12:17:21.741634 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4287 12:17:21.744698 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4288 12:17:21.744802 ==
4289 12:17:21.748309 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 12:17:21.754738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 12:17:21.754848 ==
4292 12:17:21.754917 DQS Delay:
4293 12:17:21.754979 DQS0 = 0, DQS1 = 0
4294 12:17:21.758272 DQM Delay:
4295 12:17:21.758363 DQM0 = 48, DQM1 = 40
4296 12:17:21.761513 DQ Delay:
4297 12:17:21.764958 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4298 12:17:21.765059 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4299 12:17:21.767962 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4300 12:17:21.774843 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4301 12:17:21.774955
4302 12:17:21.775049
4303 12:17:21.775148 ==
4304 12:17:21.777802 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 12:17:21.781209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 12:17:21.781297 ==
4307 12:17:21.781364
4308 12:17:21.781424
4309 12:17:21.784562 TX Vref Scan disable
4310 12:17:21.784678 == TX Byte 0 ==
4311 12:17:21.790904 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4312 12:17:21.794334 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4313 12:17:21.797649 == TX Byte 1 ==
4314 12:17:21.801083 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4315 12:17:21.804343 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4316 12:17:21.804448 ==
4317 12:17:21.807822 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 12:17:21.810800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 12:17:21.810903 ==
4320 12:17:21.814297
4321 12:17:21.814393
4322 12:17:21.814458 TX Vref Scan disable
4323 12:17:21.817583 == TX Byte 0 ==
4324 12:17:21.820994 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4325 12:17:21.827367 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4326 12:17:21.827494 == TX Byte 1 ==
4327 12:17:21.830773 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4328 12:17:21.837695 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4329 12:17:21.837850
4330 12:17:21.837948 [DATLAT]
4331 12:17:21.838038 Freq=600, CH0 RK1
4332 12:17:21.838126
4333 12:17:21.841125 DATLAT Default: 0x9
4334 12:17:21.841235 0, 0xFFFF, sum = 0
4335 12:17:21.844208 1, 0xFFFF, sum = 0
4336 12:17:21.844320 2, 0xFFFF, sum = 0
4337 12:17:21.847474 3, 0xFFFF, sum = 0
4338 12:17:21.850676 4, 0xFFFF, sum = 0
4339 12:17:21.850761 5, 0xFFFF, sum = 0
4340 12:17:21.854235 6, 0xFFFF, sum = 0
4341 12:17:21.854318 7, 0xFFFF, sum = 0
4342 12:17:21.857310 8, 0x0, sum = 1
4343 12:17:21.857395 9, 0x0, sum = 2
4344 12:17:21.857461 10, 0x0, sum = 3
4345 12:17:21.860983 11, 0x0, sum = 4
4346 12:17:21.861073 best_step = 9
4347 12:17:21.861139
4348 12:17:21.861198 ==
4349 12:17:21.864151 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 12:17:21.870791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 12:17:21.870956 ==
4352 12:17:21.871034 RX Vref Scan: 0
4353 12:17:21.871103
4354 12:17:21.874224 RX Vref 0 -> 0, step: 1
4355 12:17:21.874381
4356 12:17:21.877313 RX Delay -179 -> 252, step: 8
4357 12:17:21.880445 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4358 12:17:21.886932 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4359 12:17:21.890302 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4360 12:17:21.893675 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4361 12:17:21.897360 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4362 12:17:21.903421 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4363 12:17:21.906942 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4364 12:17:21.910278 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4365 12:17:21.913373 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4366 12:17:21.916704 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4367 12:17:21.924082 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4368 12:17:21.926792 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4369 12:17:21.930400 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4370 12:17:21.933673 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4371 12:17:21.939940 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4372 12:17:21.943449 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4373 12:17:21.943900 ==
4374 12:17:21.946738 Dram Type= 6, Freq= 0, CH_0, rank 1
4375 12:17:21.949743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 12:17:21.950197 ==
4377 12:17:21.953436 DQS Delay:
4378 12:17:21.953844 DQS0 = 0, DQS1 = 0
4379 12:17:21.954226 DQM Delay:
4380 12:17:21.956667 DQM0 = 48, DQM1 = 39
4381 12:17:21.957175 DQ Delay:
4382 12:17:21.959714 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4383 12:17:21.962841 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4384 12:17:21.966236 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4385 12:17:21.969775 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4386 12:17:21.970273
4387 12:17:21.970700
4388 12:17:21.979555 [DQSOSCAuto] RK1, (LSB)MR18= 0x6230, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4389 12:17:21.982758 CH0 RK1: MR19=808, MR18=6230
4390 12:17:21.986156 CH0_RK1: MR19=0x808, MR18=0x6230, DQSOSC=391, MR23=63, INC=171, DEC=114
4391 12:17:21.989487 [RxdqsGatingPostProcess] freq 600
4392 12:17:21.995913 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4393 12:17:21.999408 Pre-setting of DQS Precalculation
4394 12:17:22.002343 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4395 12:17:22.002762 ==
4396 12:17:22.005772 Dram Type= 6, Freq= 0, CH_1, rank 0
4397 12:17:22.012518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 12:17:22.013170 ==
4399 12:17:22.015994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4400 12:17:22.022353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4401 12:17:22.025754 [CA 0] Center 35 (5~66) winsize 62
4402 12:17:22.029242 [CA 1] Center 35 (5~66) winsize 62
4403 12:17:22.032644 [CA 2] Center 34 (4~65) winsize 62
4404 12:17:22.036019 [CA 3] Center 33 (3~64) winsize 62
4405 12:17:22.039276 [CA 4] Center 33 (3~64) winsize 62
4406 12:17:22.042770 [CA 5] Center 33 (3~64) winsize 62
4407 12:17:22.043201
4408 12:17:22.045828 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4409 12:17:22.046256
4410 12:17:22.049290 [CATrainingPosCal] consider 1 rank data
4411 12:17:22.052542 u2DelayCellTimex100 = 270/100 ps
4412 12:17:22.055846 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4413 12:17:22.062673 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4414 12:17:22.065601 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 12:17:22.069002 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 12:17:22.072073 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 12:17:22.075356 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 12:17:22.075807
4419 12:17:22.078827 CA PerBit enable=1, Macro0, CA PI delay=33
4420 12:17:22.079260
4421 12:17:22.082256 [CBTSetCACLKResult] CA Dly = 33
4422 12:17:22.085558 CS Dly: 5 (0~36)
4423 12:17:22.086022 ==
4424 12:17:22.088807 Dram Type= 6, Freq= 0, CH_1, rank 1
4425 12:17:22.092169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 12:17:22.092635 ==
4427 12:17:22.098441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4428 12:17:22.101972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4429 12:17:22.105824 [CA 0] Center 36 (6~66) winsize 61
4430 12:17:22.109381 [CA 1] Center 35 (5~66) winsize 62
4431 12:17:22.112743 [CA 2] Center 34 (4~65) winsize 62
4432 12:17:22.116276 [CA 3] Center 34 (4~65) winsize 62
4433 12:17:22.119195 [CA 4] Center 34 (4~65) winsize 62
4434 12:17:22.122582 [CA 5] Center 33 (3~64) winsize 62
4435 12:17:22.123011
4436 12:17:22.125937 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4437 12:17:22.126366
4438 12:17:22.129479 [CATrainingPosCal] consider 2 rank data
4439 12:17:22.132713 u2DelayCellTimex100 = 270/100 ps
4440 12:17:22.135750 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4441 12:17:22.142217 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4442 12:17:22.145494 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4443 12:17:22.149020 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4444 12:17:22.152469 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4445 12:17:22.155517 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4446 12:17:22.155939
4447 12:17:22.158859 CA PerBit enable=1, Macro0, CA PI delay=33
4448 12:17:22.159287
4449 12:17:22.162188 [CBTSetCACLKResult] CA Dly = 33
4450 12:17:22.165359 CS Dly: 5 (0~36)
4451 12:17:22.165784
4452 12:17:22.168861 ----->DramcWriteLeveling(PI) begin...
4453 12:17:22.169292 ==
4454 12:17:22.172151 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 12:17:22.175162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 12:17:22.175588 ==
4457 12:17:22.178499 Write leveling (Byte 0): 28 => 28
4458 12:17:22.182153 Write leveling (Byte 1): 30 => 30
4459 12:17:22.185300 DramcWriteLeveling(PI) end<-----
4460 12:17:22.185724
4461 12:17:22.186056 ==
4462 12:17:22.188539 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 12:17:22.192128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 12:17:22.192550 ==
4465 12:17:22.195521 [Gating] SW mode calibration
4466 12:17:22.202037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4467 12:17:22.208470 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4468 12:17:22.211723 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 12:17:22.215258 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 12:17:22.221413 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4471 12:17:22.224904 0 9 12 | B1->B0 | 3030 2c2c | 1 1 | (1 0) (0 0)
4472 12:17:22.228181 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 12:17:22.234652 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 12:17:22.237895 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 12:17:22.241404 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 12:17:22.248151 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 12:17:22.251514 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 12:17:22.254867 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4479 12:17:22.261204 0 10 12 | B1->B0 | 3c3c 3b3b | 0 1 | (0 0) (0 0)
4480 12:17:22.264570 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 12:17:22.267634 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 12:17:22.274324 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 12:17:22.277789 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 12:17:22.280913 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 12:17:22.287727 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 12:17:22.290719 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 12:17:22.294187 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4488 12:17:22.300660 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 12:17:22.304038 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 12:17:22.306932 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 12:17:22.313850 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 12:17:22.317459 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 12:17:22.320137 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 12:17:22.326824 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 12:17:22.330277 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 12:17:22.333892 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 12:17:22.340157 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 12:17:22.343337 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 12:17:22.346693 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 12:17:22.353353 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 12:17:22.356296 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 12:17:22.359701 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4503 12:17:22.366311 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4504 12:17:22.369726 Total UI for P1: 0, mck2ui 16
4505 12:17:22.373018 best dqsien dly found for B0: ( 0, 13, 8)
4506 12:17:22.376340 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 12:17:22.379590 Total UI for P1: 0, mck2ui 16
4508 12:17:22.382835 best dqsien dly found for B1: ( 0, 13, 12)
4509 12:17:22.385943 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4510 12:17:22.389593 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4511 12:17:22.389662
4512 12:17:22.392618 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4513 12:17:22.395928 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4514 12:17:22.399083 [Gating] SW calibration Done
4515 12:17:22.399193 ==
4516 12:17:22.402713 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 12:17:22.409392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 12:17:22.409476 ==
4519 12:17:22.409542 RX Vref Scan: 0
4520 12:17:22.409604
4521 12:17:22.412365 RX Vref 0 -> 0, step: 1
4522 12:17:22.412447
4523 12:17:22.415827 RX Delay -230 -> 252, step: 16
4524 12:17:22.419255 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4525 12:17:22.422450 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4526 12:17:22.425774 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4527 12:17:22.432215 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4528 12:17:22.435666 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4529 12:17:22.438970 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4530 12:17:22.441938 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4531 12:17:22.448798 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4532 12:17:22.452217 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4533 12:17:22.455203 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4534 12:17:22.458650 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4535 12:17:22.462162 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4536 12:17:22.468580 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4537 12:17:22.471972 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4538 12:17:22.474933 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4539 12:17:22.481807 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4540 12:17:22.481893 ==
4541 12:17:22.485057 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 12:17:22.488042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 12:17:22.488151 ==
4544 12:17:22.488244 DQS Delay:
4545 12:17:22.491353 DQS0 = 0, DQS1 = 0
4546 12:17:22.491425 DQM Delay:
4547 12:17:22.494939 DQM0 = 53, DQM1 = 44
4548 12:17:22.495023 DQ Delay:
4549 12:17:22.498160 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4550 12:17:22.501722 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4551 12:17:22.504867 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4552 12:17:22.508125 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =57
4553 12:17:22.508233
4554 12:17:22.508332
4555 12:17:22.508429 ==
4556 12:17:22.511146 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 12:17:22.514384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 12:17:22.514510 ==
4559 12:17:22.514621
4560 12:17:22.517981
4561 12:17:22.518116 TX Vref Scan disable
4562 12:17:22.521419 == TX Byte 0 ==
4563 12:17:22.524367 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4564 12:17:22.527867 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4565 12:17:22.531229 == TX Byte 1 ==
4566 12:17:22.534550 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4567 12:17:22.537842 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4568 12:17:22.537955 ==
4569 12:17:22.541337 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 12:17:22.547782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 12:17:22.547866 ==
4572 12:17:22.547931
4573 12:17:22.547993
4574 12:17:22.548052 TX Vref Scan disable
4575 12:17:22.552325 == TX Byte 0 ==
4576 12:17:22.555970 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4577 12:17:22.562585 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4578 12:17:22.563012 == TX Byte 1 ==
4579 12:17:22.565918 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4580 12:17:22.572228 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4581 12:17:22.572803
4582 12:17:22.573159 [DATLAT]
4583 12:17:22.573503 Freq=600, CH1 RK0
4584 12:17:22.573912
4585 12:17:22.575667 DATLAT Default: 0x9
4586 12:17:22.576206 0, 0xFFFF, sum = 0
4587 12:17:22.579214 1, 0xFFFF, sum = 0
4588 12:17:22.582267 2, 0xFFFF, sum = 0
4589 12:17:22.582855 3, 0xFFFF, sum = 0
4590 12:17:22.585721 4, 0xFFFF, sum = 0
4591 12:17:22.586297 5, 0xFFFF, sum = 0
4592 12:17:22.588898 6, 0xFFFF, sum = 0
4593 12:17:22.589389 7, 0xFFFF, sum = 0
4594 12:17:22.592212 8, 0x0, sum = 1
4595 12:17:22.592818 9, 0x0, sum = 2
4596 12:17:22.593184 10, 0x0, sum = 3
4597 12:17:22.595584 11, 0x0, sum = 4
4598 12:17:22.596153 best_step = 9
4599 12:17:22.596323
4600 12:17:22.596412 ==
4601 12:17:22.598596 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 12:17:22.605040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 12:17:22.605137 ==
4604 12:17:22.605204 RX Vref Scan: 1
4605 12:17:22.605266
4606 12:17:22.608331 RX Vref 0 -> 0, step: 1
4607 12:17:22.608421
4608 12:17:22.611547 RX Delay -163 -> 252, step: 8
4609 12:17:22.611663
4610 12:17:22.614758 Set Vref, RX VrefLevel [Byte0]: 51
4611 12:17:22.618458 [Byte1]: 52
4612 12:17:22.618578
4613 12:17:22.621757 Final RX Vref Byte 0 = 51 to rank0
4614 12:17:22.625129 Final RX Vref Byte 1 = 52 to rank0
4615 12:17:22.628417 Final RX Vref Byte 0 = 51 to rank1
4616 12:17:22.631474 Final RX Vref Byte 1 = 52 to rank1==
4617 12:17:22.634931 Dram Type= 6, Freq= 0, CH_1, rank 0
4618 12:17:22.638156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 12:17:22.638332 ==
4620 12:17:22.641675 DQS Delay:
4621 12:17:22.641866 DQS0 = 0, DQS1 = 0
4622 12:17:22.644927 DQM Delay:
4623 12:17:22.645137 DQM0 = 49, DQM1 = 41
4624 12:17:22.645285 DQ Delay:
4625 12:17:22.647878 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4626 12:17:22.651472 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4627 12:17:22.654783 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4628 12:17:22.658270 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4629 12:17:22.658608
4630 12:17:22.661675
4631 12:17:22.668481 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4632 12:17:22.671442 CH1 RK0: MR19=808, MR18=4D73
4633 12:17:22.678409 CH1_RK0: MR19=0x808, MR18=0x4D73, DQSOSC=388, MR23=63, INC=174, DEC=116
4634 12:17:22.679033
4635 12:17:22.681291 ----->DramcWriteLeveling(PI) begin...
4636 12:17:22.681921 ==
4637 12:17:22.684748 Dram Type= 6, Freq= 0, CH_1, rank 1
4638 12:17:22.688331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 12:17:22.689027 ==
4640 12:17:22.691516 Write leveling (Byte 0): 31 => 31
4641 12:17:22.694407 Write leveling (Byte 1): 31 => 31
4642 12:17:22.698050 DramcWriteLeveling(PI) end<-----
4643 12:17:22.698630
4644 12:17:22.699168 ==
4645 12:17:22.701411 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 12:17:22.704604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 12:17:22.705144 ==
4648 12:17:22.707922 [Gating] SW mode calibration
4649 12:17:22.714719 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4650 12:17:22.720931 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4651 12:17:22.724231 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 12:17:22.727865 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 12:17:22.734502 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
4654 12:17:22.737610 0 9 12 | B1->B0 | 2d2d 3232 | 0 0 | (1 0) (0 1)
4655 12:17:22.740863 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 12:17:22.747554 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 12:17:22.751066 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 12:17:22.753917 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 12:17:22.760725 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 12:17:22.763758 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 12:17:22.767058 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4662 12:17:22.773677 0 10 12 | B1->B0 | 4444 3030 | 0 1 | (0 0) (0 0)
4663 12:17:22.777184 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4664 12:17:22.780166 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 12:17:22.787008 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 12:17:22.790137 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 12:17:22.793090 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 12:17:22.800065 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 12:17:22.803077 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 12:17:22.806476 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4671 12:17:22.812922 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 12:17:22.816606 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 12:17:22.819593 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 12:17:22.826245 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 12:17:22.829375 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 12:17:22.833168 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 12:17:22.839334 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 12:17:22.842827 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 12:17:22.846153 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 12:17:22.852917 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 12:17:22.855943 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 12:17:22.859344 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 12:17:22.865669 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 12:17:22.869153 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 12:17:22.872413 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 12:17:22.878933 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 12:17:22.882478 Total UI for P1: 0, mck2ui 16
4688 12:17:22.886005 best dqsien dly found for B0: ( 0, 13, 10)
4689 12:17:22.888890 Total UI for P1: 0, mck2ui 16
4690 12:17:22.892321 best dqsien dly found for B1: ( 0, 13, 10)
4691 12:17:22.895597 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4692 12:17:22.898992 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4693 12:17:22.899077
4694 12:17:22.901818 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4695 12:17:22.905097 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4696 12:17:22.908466 [Gating] SW calibration Done
4697 12:17:22.908548 ==
4698 12:17:22.911920 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 12:17:22.915281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 12:17:22.915364 ==
4701 12:17:22.918563 RX Vref Scan: 0
4702 12:17:22.918645
4703 12:17:22.921907 RX Vref 0 -> 0, step: 1
4704 12:17:22.921990
4705 12:17:22.925036 RX Delay -230 -> 252, step: 16
4706 12:17:22.928316 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4707 12:17:22.931570 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4708 12:17:22.934872 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4709 12:17:22.941424 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4710 12:17:22.944861 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4711 12:17:22.947954 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4712 12:17:22.951312 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4713 12:17:22.954526 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4714 12:17:22.960879 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4715 12:17:22.964279 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4716 12:17:22.967640 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4717 12:17:22.971061 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4718 12:17:22.977839 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4719 12:17:22.981031 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4720 12:17:22.984033 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4721 12:17:22.987339 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4722 12:17:22.990768 ==
4723 12:17:22.990850 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 12:17:22.997538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 12:17:22.997621 ==
4726 12:17:22.997686 DQS Delay:
4727 12:17:23.000502 DQS0 = 0, DQS1 = 0
4728 12:17:23.000583 DQM Delay:
4729 12:17:23.003946 DQM0 = 51, DQM1 = 48
4730 12:17:23.004029 DQ Delay:
4731 12:17:23.007369 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4732 12:17:23.010638 DQ4 =49, DQ5 =65, DQ6 =49, DQ7 =49
4733 12:17:23.013901 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4734 12:17:23.017275 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4735 12:17:23.017377
4736 12:17:23.017457
4737 12:17:23.017531 ==
4738 12:17:23.020669 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 12:17:23.023938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 12:17:23.024029 ==
4741 12:17:23.024108
4742 12:17:23.024206
4743 12:17:23.027068 TX Vref Scan disable
4744 12:17:23.030284 == TX Byte 0 ==
4745 12:17:23.033705 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4746 12:17:23.037057 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4747 12:17:23.040276 == TX Byte 1 ==
4748 12:17:23.043298 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4749 12:17:23.046950 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4750 12:17:23.047033 ==
4751 12:17:23.050310 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 12:17:23.056896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 12:17:23.056979 ==
4754 12:17:23.057043
4755 12:17:23.057102
4756 12:17:23.057159 TX Vref Scan disable
4757 12:17:23.060759 == TX Byte 0 ==
4758 12:17:23.064161 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4759 12:17:23.070675 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4760 12:17:23.070759 == TX Byte 1 ==
4761 12:17:23.074080 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4762 12:17:23.080502 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4763 12:17:23.080585
4764 12:17:23.080650 [DATLAT]
4765 12:17:23.080710 Freq=600, CH1 RK1
4766 12:17:23.080790
4767 12:17:23.084255 DATLAT Default: 0x9
4768 12:17:23.084338 0, 0xFFFF, sum = 0
4769 12:17:23.087248 1, 0xFFFF, sum = 0
4770 12:17:23.090621 2, 0xFFFF, sum = 0
4771 12:17:23.090706 3, 0xFFFF, sum = 0
4772 12:17:23.094116 4, 0xFFFF, sum = 0
4773 12:17:23.094200 5, 0xFFFF, sum = 0
4774 12:17:23.097409 6, 0xFFFF, sum = 0
4775 12:17:23.097493 7, 0xFFFF, sum = 0
4776 12:17:23.100471 8, 0x0, sum = 1
4777 12:17:23.100555 9, 0x0, sum = 2
4778 12:17:23.103855 10, 0x0, sum = 3
4779 12:17:23.103940 11, 0x0, sum = 4
4780 12:17:23.104007 best_step = 9
4781 12:17:23.104068
4782 12:17:23.106959 ==
4783 12:17:23.110352 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 12:17:23.113444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 12:17:23.113528 ==
4786 12:17:23.113593 RX Vref Scan: 0
4787 12:17:23.113654
4788 12:17:23.116881 RX Vref 0 -> 0, step: 1
4789 12:17:23.116964
4790 12:17:23.120285 RX Delay -163 -> 252, step: 8
4791 12:17:23.126520 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4792 12:17:23.130136 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4793 12:17:23.132915 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4794 12:17:23.136543 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4795 12:17:23.139601 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4796 12:17:23.146312 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4797 12:17:23.149911 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4798 12:17:23.152957 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4799 12:17:23.156268 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4800 12:17:23.159453 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4801 12:17:23.166498 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4802 12:17:23.169894 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4803 12:17:23.172656 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4804 12:17:23.176087 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4805 12:17:23.182935 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4806 12:17:23.185990 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4807 12:17:23.186079 ==
4808 12:17:23.189185 Dram Type= 6, Freq= 0, CH_1, rank 1
4809 12:17:23.192523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4810 12:17:23.192620 ==
4811 12:17:23.195915 DQS Delay:
4812 12:17:23.196024 DQS0 = 0, DQS1 = 0
4813 12:17:23.196106 DQM Delay:
4814 12:17:23.199539 DQM0 = 48, DQM1 = 43
4815 12:17:23.199650 DQ Delay:
4816 12:17:23.202376 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4817 12:17:23.205754 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4818 12:17:23.209187 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4819 12:17:23.212644 DQ12 =48, DQ13 =52, DQ14 =48, DQ15 =52
4820 12:17:23.212791
4821 12:17:23.212897
4822 12:17:23.223080 [DQSOSCAuto] RK1, (LSB)MR18= 0x571d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4823 12:17:23.225997 CH1 RK1: MR19=808, MR18=571D
4824 12:17:23.229390 CH1_RK1: MR19=0x808, MR18=0x571D, DQSOSC=393, MR23=63, INC=169, DEC=113
4825 12:17:23.232832 [RxdqsGatingPostProcess] freq 600
4826 12:17:23.239332 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4827 12:17:23.242361 Pre-setting of DQS Precalculation
4828 12:17:23.246023 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4829 12:17:23.255970 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4830 12:17:23.262677 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4831 12:17:23.263120
4832 12:17:23.263621
4833 12:17:23.265850 [Calibration Summary] 1200 Mbps
4834 12:17:23.266385 CH 0, Rank 0
4835 12:17:23.269402 SW Impedance : PASS
4836 12:17:23.269821 DUTY Scan : NO K
4837 12:17:23.272256 ZQ Calibration : PASS
4838 12:17:23.275763 Jitter Meter : NO K
4839 12:17:23.276291 CBT Training : PASS
4840 12:17:23.279322 Write leveling : PASS
4841 12:17:23.282137 RX DQS gating : PASS
4842 12:17:23.282659 RX DQ/DQS(RDDQC) : PASS
4843 12:17:23.285645 TX DQ/DQS : PASS
4844 12:17:23.288996 RX DATLAT : PASS
4845 12:17:23.289532 RX DQ/DQS(Engine): PASS
4846 12:17:23.292189 TX OE : NO K
4847 12:17:23.292682 All Pass.
4848 12:17:23.293187
4849 12:17:23.293514 CH 0, Rank 1
4850 12:17:23.295614 SW Impedance : PASS
4851 12:17:23.298901 DUTY Scan : NO K
4852 12:17:23.299392 ZQ Calibration : PASS
4853 12:17:23.302460 Jitter Meter : NO K
4854 12:17:23.305265 CBT Training : PASS
4855 12:17:23.305702 Write leveling : PASS
4856 12:17:23.308631 RX DQS gating : PASS
4857 12:17:23.312009 RX DQ/DQS(RDDQC) : PASS
4858 12:17:23.312429 TX DQ/DQS : PASS
4859 12:17:23.315548 RX DATLAT : PASS
4860 12:17:23.318844 RX DQ/DQS(Engine): PASS
4861 12:17:23.319340 TX OE : NO K
4862 12:17:23.321995 All Pass.
4863 12:17:23.322426
4864 12:17:23.322868 CH 1, Rank 0
4865 12:17:23.325266 SW Impedance : PASS
4866 12:17:23.325561 DUTY Scan : NO K
4867 12:17:23.328191 ZQ Calibration : PASS
4868 12:17:23.331534 Jitter Meter : NO K
4869 12:17:23.331789 CBT Training : PASS
4870 12:17:23.334841 Write leveling : PASS
4871 12:17:23.338261 RX DQS gating : PASS
4872 12:17:23.338484 RX DQ/DQS(RDDQC) : PASS
4873 12:17:23.341512 TX DQ/DQS : PASS
4874 12:17:23.344707 RX DATLAT : PASS
4875 12:17:23.344855 RX DQ/DQS(Engine): PASS
4876 12:17:23.348124 TX OE : NO K
4877 12:17:23.348291 All Pass.
4878 12:17:23.348423
4879 12:17:23.351790 CH 1, Rank 1
4880 12:17:23.351897 SW Impedance : PASS
4881 12:17:23.354896 DUTY Scan : NO K
4882 12:17:23.357800 ZQ Calibration : PASS
4883 12:17:23.357922 Jitter Meter : NO K
4884 12:17:23.361407 CBT Training : PASS
4885 12:17:23.361489 Write leveling : PASS
4886 12:17:23.364400 RX DQS gating : PASS
4887 12:17:23.367670 RX DQ/DQS(RDDQC) : PASS
4888 12:17:23.367780 TX DQ/DQS : PASS
4889 12:17:23.371320 RX DATLAT : PASS
4890 12:17:23.374640 RX DQ/DQS(Engine): PASS
4891 12:17:23.374749 TX OE : NO K
4892 12:17:23.377582 All Pass.
4893 12:17:23.377665
4894 12:17:23.377731 DramC Write-DBI off
4895 12:17:23.381030 PER_BANK_REFRESH: Hybrid Mode
4896 12:17:23.384296 TX_TRACKING: ON
4897 12:17:23.391206 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4898 12:17:23.394624 [FAST_K] Save calibration result to emmc
4899 12:17:23.397911 dramc_set_vcore_voltage set vcore to 662500
4900 12:17:23.400724 Read voltage for 933, 3
4901 12:17:23.400849 Vio18 = 0
4902 12:17:23.404178 Vcore = 662500
4903 12:17:23.404288 Vdram = 0
4904 12:17:23.404387 Vddq = 0
4905 12:17:23.407442 Vmddr = 0
4906 12:17:23.410910 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4907 12:17:23.417223 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4908 12:17:23.417308 MEM_TYPE=3, freq_sel=17
4909 12:17:23.420591 sv_algorithm_assistance_LP4_1600
4910 12:17:23.427265 ============ PULL DRAM RESETB DOWN ============
4911 12:17:23.430690 ========== PULL DRAM RESETB DOWN end =========
4912 12:17:23.434141 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4913 12:17:23.437531 ===================================
4914 12:17:23.440354 LPDDR4 DRAM CONFIGURATION
4915 12:17:23.443810 ===================================
4916 12:17:23.447235 EX_ROW_EN[0] = 0x0
4917 12:17:23.447313 EX_ROW_EN[1] = 0x0
4918 12:17:23.450421 LP4Y_EN = 0x0
4919 12:17:23.450504 WORK_FSP = 0x0
4920 12:17:23.453811 WL = 0x3
4921 12:17:23.453894 RL = 0x3
4922 12:17:23.456895 BL = 0x2
4923 12:17:23.456991 RPST = 0x0
4924 12:17:23.460554 RD_PRE = 0x0
4925 12:17:23.460654 WR_PRE = 0x1
4926 12:17:23.463955 WR_PST = 0x0
4927 12:17:23.464058 DBI_WR = 0x0
4928 12:17:23.467264 DBI_RD = 0x0
4929 12:17:23.467373 OTF = 0x1
4930 12:17:23.470348 ===================================
4931 12:17:23.473545 ===================================
4932 12:17:23.477083 ANA top config
4933 12:17:23.480417 ===================================
4934 12:17:23.483494 DLL_ASYNC_EN = 0
4935 12:17:23.483580 ALL_SLAVE_EN = 1
4936 12:17:23.486919 NEW_RANK_MODE = 1
4937 12:17:23.490295 DLL_IDLE_MODE = 1
4938 12:17:23.493585 LP45_APHY_COMB_EN = 1
4939 12:17:23.496452 TX_ODT_DIS = 1
4940 12:17:23.496560 NEW_8X_MODE = 1
4941 12:17:23.499833 ===================================
4942 12:17:23.503093 ===================================
4943 12:17:23.506596 data_rate = 1866
4944 12:17:23.510042 CKR = 1
4945 12:17:23.512984 DQ_P2S_RATIO = 8
4946 12:17:23.516374 ===================================
4947 12:17:23.519809 CA_P2S_RATIO = 8
4948 12:17:23.523133 DQ_CA_OPEN = 0
4949 12:17:23.523256 DQ_SEMI_OPEN = 0
4950 12:17:23.526562 CA_SEMI_OPEN = 0
4951 12:17:23.529890 CA_FULL_RATE = 0
4952 12:17:23.533257 DQ_CKDIV4_EN = 1
4953 12:17:23.536232 CA_CKDIV4_EN = 1
4954 12:17:23.539748 CA_PREDIV_EN = 0
4955 12:17:23.539831 PH8_DLY = 0
4956 12:17:23.543089 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4957 12:17:23.546168 DQ_AAMCK_DIV = 4
4958 12:17:23.549487 CA_AAMCK_DIV = 4
4959 12:17:23.552865 CA_ADMCK_DIV = 4
4960 12:17:23.556036 DQ_TRACK_CA_EN = 0
4961 12:17:23.556144 CA_PICK = 933
4962 12:17:23.559215 CA_MCKIO = 933
4963 12:17:23.562852 MCKIO_SEMI = 0
4964 12:17:23.565687 PLL_FREQ = 3732
4965 12:17:23.569398 DQ_UI_PI_RATIO = 32
4966 12:17:23.572637 CA_UI_PI_RATIO = 0
4967 12:17:23.575782 ===================================
4968 12:17:23.579088 ===================================
4969 12:17:23.582146 memory_type:LPDDR4
4970 12:17:23.582271 GP_NUM : 10
4971 12:17:23.585542 SRAM_EN : 1
4972 12:17:23.585666 MD32_EN : 0
4973 12:17:23.589111 ===================================
4974 12:17:23.592410 [ANA_INIT] >>>>>>>>>>>>>>
4975 12:17:23.595399 <<<<<< [CONFIGURE PHASE]: ANA_TX
4976 12:17:23.598955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4977 12:17:23.602402 ===================================
4978 12:17:23.605578 data_rate = 1866,PCW = 0X8f00
4979 12:17:23.608535 ===================================
4980 12:17:23.612053 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4981 12:17:23.618323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 12:17:23.621857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4983 12:17:23.628307 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4984 12:17:23.631739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4985 12:17:23.635066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4986 12:17:23.635160 [ANA_INIT] flow start
4987 12:17:23.638490 [ANA_INIT] PLL >>>>>>>>
4988 12:17:23.641940 [ANA_INIT] PLL <<<<<<<<
4989 12:17:23.642031 [ANA_INIT] MIDPI >>>>>>>>
4990 12:17:23.645302 [ANA_INIT] MIDPI <<<<<<<<
4991 12:17:23.648648 [ANA_INIT] DLL >>>>>>>>
4992 12:17:23.648757 [ANA_INIT] flow end
4993 12:17:23.655123 ============ LP4 DIFF to SE enter ============
4994 12:17:23.658530 ============ LP4 DIFF to SE exit ============
4995 12:17:23.661814 [ANA_INIT] <<<<<<<<<<<<<
4996 12:17:23.664929 [Flow] Enable top DCM control >>>>>
4997 12:17:23.668624 [Flow] Enable top DCM control <<<<<
4998 12:17:23.668738 Enable DLL master slave shuffle
4999 12:17:23.674873 ==============================================================
5000 12:17:23.678031 Gating Mode config
5001 12:17:23.681529 ==============================================================
5002 12:17:23.684992 Config description:
5003 12:17:23.694599 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5004 12:17:23.701358 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5005 12:17:23.704890 SELPH_MODE 0: By rank 1: By Phase
5006 12:17:23.711456 ==============================================================
5007 12:17:23.714456 GAT_TRACK_EN = 1
5008 12:17:23.717832 RX_GATING_MODE = 2
5009 12:17:23.721289 RX_GATING_TRACK_MODE = 2
5010 12:17:23.724335 SELPH_MODE = 1
5011 12:17:23.727711 PICG_EARLY_EN = 1
5012 12:17:23.727853 VALID_LAT_VALUE = 1
5013 12:17:23.734435 ==============================================================
5014 12:17:23.737746 Enter into Gating configuration >>>>
5015 12:17:23.741113 Exit from Gating configuration <<<<
5016 12:17:23.743985 Enter into DVFS_PRE_config >>>>>
5017 12:17:23.757268 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5018 12:17:23.757373 Exit from DVFS_PRE_config <<<<<
5019 12:17:23.760699 Enter into PICG configuration >>>>
5020 12:17:23.764221 Exit from PICG configuration <<<<
5021 12:17:23.767183 [RX_INPUT] configuration >>>>>
5022 12:17:23.770512 [RX_INPUT] configuration <<<<<
5023 12:17:23.777261 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5024 12:17:23.780325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5025 12:17:23.786880 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5026 12:17:23.793937 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5027 12:17:23.800089 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5028 12:17:23.806905 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5029 12:17:23.810280 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5030 12:17:23.813456 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5031 12:17:23.816899 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5032 12:17:23.823486 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5033 12:17:23.826399 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5034 12:17:23.830067 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5035 12:17:23.833348 ===================================
5036 12:17:23.836321 LPDDR4 DRAM CONFIGURATION
5037 12:17:23.840076 ===================================
5038 12:17:23.842966 EX_ROW_EN[0] = 0x0
5039 12:17:23.843050 EX_ROW_EN[1] = 0x0
5040 12:17:23.846379 LP4Y_EN = 0x0
5041 12:17:23.846462 WORK_FSP = 0x0
5042 12:17:23.849959 WL = 0x3
5043 12:17:23.850042 RL = 0x3
5044 12:17:23.852906 BL = 0x2
5045 12:17:23.852990 RPST = 0x0
5046 12:17:23.856254 RD_PRE = 0x0
5047 12:17:23.856337 WR_PRE = 0x1
5048 12:17:23.859746 WR_PST = 0x0
5049 12:17:23.859853 DBI_WR = 0x0
5050 12:17:23.863103 DBI_RD = 0x0
5051 12:17:23.863177 OTF = 0x1
5052 12:17:23.866086 ===================================
5053 12:17:23.872870 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5054 12:17:23.876216 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5055 12:17:23.879581 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5056 12:17:23.882937 ===================================
5057 12:17:23.885901 LPDDR4 DRAM CONFIGURATION
5058 12:17:23.889449 ===================================
5059 12:17:23.892741 EX_ROW_EN[0] = 0x10
5060 12:17:23.892878 EX_ROW_EN[1] = 0x0
5061 12:17:23.896038 LP4Y_EN = 0x0
5062 12:17:23.896148 WORK_FSP = 0x0
5063 12:17:23.899186 WL = 0x3
5064 12:17:23.899264 RL = 0x3
5065 12:17:23.902272 BL = 0x2
5066 12:17:23.902378 RPST = 0x0
5067 12:17:23.905930 RD_PRE = 0x0
5068 12:17:23.906005 WR_PRE = 0x1
5069 12:17:23.909119 WR_PST = 0x0
5070 12:17:23.909203 DBI_WR = 0x0
5071 12:17:23.912474 DBI_RD = 0x0
5072 12:17:23.912556 OTF = 0x1
5073 12:17:23.915859 ===================================
5074 12:17:23.922498 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5075 12:17:23.927361 nWR fixed to 30
5076 12:17:23.930343 [ModeRegInit_LP4] CH0 RK0
5077 12:17:23.930423 [ModeRegInit_LP4] CH0 RK1
5078 12:17:23.933935 [ModeRegInit_LP4] CH1 RK0
5079 12:17:23.937355 [ModeRegInit_LP4] CH1 RK1
5080 12:17:23.937440 match AC timing 9
5081 12:17:23.943780 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5082 12:17:23.946963 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5083 12:17:23.950253 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5084 12:17:23.957126 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5085 12:17:23.960030 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5086 12:17:23.960147 ==
5087 12:17:23.963426 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 12:17:23.966873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 12:17:23.966951 ==
5090 12:17:23.973262 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5091 12:17:23.979993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5092 12:17:23.983336 [CA 0] Center 37 (7~68) winsize 62
5093 12:17:23.986672 [CA 1] Center 38 (8~68) winsize 61
5094 12:17:23.989967 [CA 2] Center 35 (5~65) winsize 61
5095 12:17:23.993283 [CA 3] Center 35 (5~65) winsize 61
5096 12:17:23.996501 [CA 4] Center 34 (4~64) winsize 61
5097 12:17:23.999706 [CA 5] Center 33 (3~64) winsize 62
5098 12:17:23.999820
5099 12:17:24.003033 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5100 12:17:24.003115
5101 12:17:24.006509 [CATrainingPosCal] consider 1 rank data
5102 12:17:24.010016 u2DelayCellTimex100 = 270/100 ps
5103 12:17:24.013232 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5104 12:17:24.016283 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5105 12:17:24.019998 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5106 12:17:24.023119 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5107 12:17:24.029466 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5108 12:17:24.032867 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5109 12:17:24.032966
5110 12:17:24.036452 CA PerBit enable=1, Macro0, CA PI delay=33
5111 12:17:24.036523
5112 12:17:24.039828 [CBTSetCACLKResult] CA Dly = 33
5113 12:17:24.039909 CS Dly: 6 (0~37)
5114 12:17:24.040009 ==
5115 12:17:24.042803 Dram Type= 6, Freq= 0, CH_0, rank 1
5116 12:17:24.049389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 12:17:24.049467 ==
5118 12:17:24.052798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5119 12:17:24.059241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5120 12:17:24.062698 [CA 0] Center 38 (7~69) winsize 63
5121 12:17:24.065646 [CA 1] Center 38 (8~69) winsize 62
5122 12:17:24.069112 [CA 2] Center 36 (6~66) winsize 61
5123 12:17:24.072467 [CA 3] Center 35 (5~66) winsize 62
5124 12:17:24.075930 [CA 4] Center 34 (4~65) winsize 62
5125 12:17:24.079335 [CA 5] Center 34 (4~65) winsize 62
5126 12:17:24.079448
5127 12:17:24.082623 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5128 12:17:24.082705
5129 12:17:24.085980 [CATrainingPosCal] consider 2 rank data
5130 12:17:24.088977 u2DelayCellTimex100 = 270/100 ps
5131 12:17:24.092350 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5132 12:17:24.095663 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5133 12:17:24.102163 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5134 12:17:24.105318 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5135 12:17:24.108974 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5136 12:17:24.112172 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5137 12:17:24.112256
5138 12:17:24.115262 CA PerBit enable=1, Macro0, CA PI delay=34
5139 12:17:24.115375
5140 12:17:24.118895 [CBTSetCACLKResult] CA Dly = 34
5141 12:17:24.119008 CS Dly: 7 (0~39)
5142 12:17:24.121976
5143 12:17:24.125221 ----->DramcWriteLeveling(PI) begin...
5144 12:17:24.125304 ==
5145 12:17:24.128835 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 12:17:24.131818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 12:17:24.131905 ==
5148 12:17:24.135206 Write leveling (Byte 0): 32 => 32
5149 12:17:24.138656 Write leveling (Byte 1): 30 => 30
5150 12:17:24.141710 DramcWriteLeveling(PI) end<-----
5151 12:17:24.141806
5152 12:17:24.141898 ==
5153 12:17:24.145117 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 12:17:24.148563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 12:17:24.148661 ==
5156 12:17:24.151951 [Gating] SW mode calibration
5157 12:17:24.158186 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5158 12:17:24.165072 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5159 12:17:24.168421 0 14 0 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 1)
5160 12:17:24.171277 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 12:17:24.178158 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 12:17:24.181527 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 12:17:24.184916 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 12:17:24.191503 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 12:17:24.194466 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5166 12:17:24.197825 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5167 12:17:24.204523 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5168 12:17:24.207930 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 12:17:24.211220 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 12:17:24.218066 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 12:17:24.221142 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 12:17:24.224257 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 12:17:24.230925 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5174 12:17:24.234260 0 15 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
5175 12:17:24.237782 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5176 12:17:24.244211 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 12:17:24.247600 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 12:17:24.250616 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 12:17:24.257013 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 12:17:24.260701 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 12:17:24.263581 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5182 12:17:24.270543 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5183 12:17:24.273547 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5184 12:17:24.276957 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 12:17:24.283723 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 12:17:24.287092 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 12:17:24.290059 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 12:17:24.296677 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 12:17:24.299982 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 12:17:24.303208 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 12:17:24.310012 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 12:17:24.313396 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 12:17:24.316468 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 12:17:24.323246 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 12:17:24.326423 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 12:17:24.329891 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 12:17:24.336441 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5198 12:17:24.339518 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5199 12:17:24.342840 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 12:17:24.346283 Total UI for P1: 0, mck2ui 16
5201 12:17:24.349489 best dqsien dly found for B0: ( 1, 2, 26)
5202 12:17:24.352963 Total UI for P1: 0, mck2ui 16
5203 12:17:24.356301 best dqsien dly found for B1: ( 1, 2, 30)
5204 12:17:24.359413 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5205 12:17:24.362734 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5206 12:17:24.362853
5207 12:17:24.369319 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5208 12:17:24.372729 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5209 12:17:24.376213 [Gating] SW calibration Done
5210 12:17:24.376297 ==
5211 12:17:24.379093 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 12:17:24.382430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 12:17:24.382530 ==
5214 12:17:24.382603 RX Vref Scan: 0
5215 12:17:24.382699
5216 12:17:24.385955 RX Vref 0 -> 0, step: 1
5217 12:17:24.386059
5218 12:17:24.388976 RX Delay -80 -> 252, step: 8
5219 12:17:24.392419 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5220 12:17:24.395790 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5221 12:17:24.402362 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5222 12:17:24.405737 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5223 12:17:24.409075 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5224 12:17:24.412092 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5225 12:17:24.415531 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5226 12:17:24.418914 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5227 12:17:24.425505 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5228 12:17:24.428461 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5229 12:17:24.431712 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5230 12:17:24.435379 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5231 12:17:24.438447 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5232 12:17:24.445225 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5233 12:17:24.448346 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5234 12:17:24.451591 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5235 12:17:24.451677 ==
5236 12:17:24.454873 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 12:17:24.458575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 12:17:24.458661 ==
5239 12:17:24.461495 DQS Delay:
5240 12:17:24.461582 DQS0 = 0, DQS1 = 0
5241 12:17:24.461649 DQM Delay:
5242 12:17:24.464743 DQM0 = 105, DQM1 = 90
5243 12:17:24.464869 DQ Delay:
5244 12:17:24.468425 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5245 12:17:24.471434 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5246 12:17:24.474958 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5247 12:17:24.478424 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5248 12:17:24.478509
5249 12:17:24.478575
5250 12:17:24.481914 ==
5251 12:17:24.484729 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 12:17:24.488332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 12:17:24.488417 ==
5254 12:17:24.488484
5255 12:17:24.488544
5256 12:17:24.491694 TX Vref Scan disable
5257 12:17:24.491778 == TX Byte 0 ==
5258 12:17:24.497948 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5259 12:17:24.501261 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5260 12:17:24.501350 == TX Byte 1 ==
5261 12:17:24.508219 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5262 12:17:24.511479 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5263 12:17:24.511559 ==
5264 12:17:24.514468 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 12:17:24.517966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 12:17:24.518042 ==
5267 12:17:24.518104
5268 12:17:24.518162
5269 12:17:24.521844 TX Vref Scan disable
5270 12:17:24.524533 == TX Byte 0 ==
5271 12:17:24.527935 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5272 12:17:24.531408 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5273 12:17:24.534214 == TX Byte 1 ==
5274 12:17:24.537627 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5275 12:17:24.540832 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5276 12:17:24.540916
5277 12:17:24.544439 [DATLAT]
5278 12:17:24.544535 Freq=933, CH0 RK0
5279 12:17:24.544629
5280 12:17:24.547422 DATLAT Default: 0xd
5281 12:17:24.547505 0, 0xFFFF, sum = 0
5282 12:17:24.550915 1, 0xFFFF, sum = 0
5283 12:17:24.551027 2, 0xFFFF, sum = 0
5284 12:17:24.554084 3, 0xFFFF, sum = 0
5285 12:17:24.554168 4, 0xFFFF, sum = 0
5286 12:17:24.557650 5, 0xFFFF, sum = 0
5287 12:17:24.557734 6, 0xFFFF, sum = 0
5288 12:17:24.560984 7, 0xFFFF, sum = 0
5289 12:17:24.561068 8, 0xFFFF, sum = 0
5290 12:17:24.564016 9, 0xFFFF, sum = 0
5291 12:17:24.564099 10, 0x0, sum = 1
5292 12:17:24.567153 11, 0x0, sum = 2
5293 12:17:24.567238 12, 0x0, sum = 3
5294 12:17:24.570823 13, 0x0, sum = 4
5295 12:17:24.570909 best_step = 11
5296 12:17:24.570975
5297 12:17:24.571037 ==
5298 12:17:24.573728 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 12:17:24.580659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 12:17:24.580759 ==
5301 12:17:24.580846 RX Vref Scan: 1
5302 12:17:24.580908
5303 12:17:24.583518 RX Vref 0 -> 0, step: 1
5304 12:17:24.583665
5305 12:17:24.587061 RX Delay -53 -> 252, step: 4
5306 12:17:24.587143
5307 12:17:24.590447 Set Vref, RX VrefLevel [Byte0]: 59
5308 12:17:24.593412 [Byte1]: 49
5309 12:17:24.593497
5310 12:17:24.596783 Final RX Vref Byte 0 = 59 to rank0
5311 12:17:24.600103 Final RX Vref Byte 1 = 49 to rank0
5312 12:17:24.603586 Final RX Vref Byte 0 = 59 to rank1
5313 12:17:24.607106 Final RX Vref Byte 1 = 49 to rank1==
5314 12:17:24.610087 Dram Type= 6, Freq= 0, CH_0, rank 0
5315 12:17:24.613435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 12:17:24.613547 ==
5317 12:17:24.616624 DQS Delay:
5318 12:17:24.616708 DQS0 = 0, DQS1 = 0
5319 12:17:24.620017 DQM Delay:
5320 12:17:24.620105 DQM0 = 107, DQM1 = 92
5321 12:17:24.623458 DQ Delay:
5322 12:17:24.626869 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =106
5323 12:17:24.630189 DQ4 =108, DQ5 =100, DQ6 =120, DQ7 =114
5324 12:17:24.633060 DQ8 =86, DQ9 =78, DQ10 =90, DQ11 =90
5325 12:17:24.636544 DQ12 =96, DQ13 =96, DQ14 =102, DQ15 =100
5326 12:17:24.636617
5327 12:17:24.636680
5328 12:17:24.642900 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5329 12:17:24.646164 CH0 RK0: MR19=505, MR18=2420
5330 12:17:24.652745 CH0_RK0: MR19=0x505, MR18=0x2420, DQSOSC=410, MR23=63, INC=64, DEC=42
5331 12:17:24.652867
5332 12:17:24.656040 ----->DramcWriteLeveling(PI) begin...
5333 12:17:24.656129 ==
5334 12:17:24.659354 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 12:17:24.662930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 12:17:24.663015 ==
5337 12:17:24.665933 Write leveling (Byte 0): 33 => 33
5338 12:17:24.669544 Write leveling (Byte 1): 29 => 29
5339 12:17:24.672594 DramcWriteLeveling(PI) end<-----
5340 12:17:24.672680
5341 12:17:24.672745 ==
5342 12:17:24.676191 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 12:17:24.682384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 12:17:24.682468 ==
5345 12:17:24.682539 [Gating] SW mode calibration
5346 12:17:24.692530 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5347 12:17:24.695432 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5348 12:17:24.698866 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 12:17:24.705675 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 12:17:24.709099 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 12:17:24.712058 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 12:17:24.718883 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 12:17:24.722265 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 12:17:24.725629 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
5355 12:17:24.732294 0 14 28 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
5356 12:17:24.735160 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5357 12:17:24.738540 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 12:17:24.745361 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 12:17:24.748784 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 12:17:24.751751 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 12:17:24.758760 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 12:17:24.761739 0 15 24 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
5363 12:17:24.765010 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5364 12:17:24.771713 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 12:17:24.775185 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 12:17:24.778505 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 12:17:24.785005 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 12:17:24.788372 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 12:17:24.791894 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 12:17:24.798237 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5371 12:17:24.801685 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5372 12:17:24.805045 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5373 12:17:24.811827 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 12:17:24.814773 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 12:17:24.818251 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 12:17:24.824730 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 12:17:24.828193 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 12:17:24.831666 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 12:17:24.837976 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 12:17:24.841395 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 12:17:24.844775 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 12:17:24.851076 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 12:17:24.854652 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 12:17:24.858042 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 12:17:24.864315 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 12:17:24.867654 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:17:24.871059 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 12:17:24.874331 Total UI for P1: 0, mck2ui 16
5389 12:17:24.877417 best dqsien dly found for B0: ( 1, 2, 26)
5390 12:17:24.880975 Total UI for P1: 0, mck2ui 16
5391 12:17:24.884198 best dqsien dly found for B1: ( 1, 2, 26)
5392 12:17:24.887492 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5393 12:17:24.890978 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5394 12:17:24.891080
5395 12:17:24.897288 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5396 12:17:24.900722 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5397 12:17:24.900871 [Gating] SW calibration Done
5398 12:17:24.904114 ==
5399 12:17:24.907417 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 12:17:24.910849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 12:17:24.910970 ==
5402 12:17:24.911067 RX Vref Scan: 0
5403 12:17:24.911157
5404 12:17:24.913785 RX Vref 0 -> 0, step: 1
5405 12:17:24.913885
5406 12:17:24.917235 RX Delay -80 -> 252, step: 8
5407 12:17:24.920702 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5408 12:17:24.924050 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5409 12:17:24.927312 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5410 12:17:24.933548 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5411 12:17:24.937111 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5412 12:17:24.940662 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5413 12:17:24.943578 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5414 12:17:24.947047 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5415 12:17:24.953379 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5416 12:17:24.956744 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5417 12:17:24.960236 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5418 12:17:24.963540 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5419 12:17:24.966879 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5420 12:17:24.969805 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5421 12:17:24.976737 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5422 12:17:24.979987 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5423 12:17:24.980070 ==
5424 12:17:24.983317 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 12:17:24.986817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 12:17:24.986916 ==
5427 12:17:24.989899 DQS Delay:
5428 12:17:24.989981 DQS0 = 0, DQS1 = 0
5429 12:17:24.990045 DQM Delay:
5430 12:17:24.993108 DQM0 = 104, DQM1 = 90
5431 12:17:24.993190 DQ Delay:
5432 12:17:24.996416 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5433 12:17:24.999578 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5434 12:17:25.002929 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5435 12:17:25.006393 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5436 12:17:25.006480
5437 12:17:25.006546
5438 12:17:25.009732 ==
5439 12:17:25.009816 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 12:17:25.016069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 12:17:25.016158 ==
5442 12:17:25.016223
5443 12:17:25.016281
5444 12:17:25.019432 TX Vref Scan disable
5445 12:17:25.019515 == TX Byte 0 ==
5446 12:17:25.022910 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5447 12:17:25.029649 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5448 12:17:25.029733 == TX Byte 1 ==
5449 12:17:25.032901 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5450 12:17:25.039606 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5451 12:17:25.039692 ==
5452 12:17:25.042582 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 12:17:25.045922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 12:17:25.046008 ==
5455 12:17:25.046113
5456 12:17:25.046176
5457 12:17:25.049312 TX Vref Scan disable
5458 12:17:25.052672 == TX Byte 0 ==
5459 12:17:25.056081 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5460 12:17:25.058936 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5461 12:17:25.062457 == TX Byte 1 ==
5462 12:17:25.065973 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5463 12:17:25.069141 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5464 12:17:25.069247
5465 12:17:25.072464 [DATLAT]
5466 12:17:25.072560 Freq=933, CH0 RK1
5467 12:17:25.072652
5468 12:17:25.075568 DATLAT Default: 0xb
5469 12:17:25.075639 0, 0xFFFF, sum = 0
5470 12:17:25.078971 1, 0xFFFF, sum = 0
5471 12:17:25.079040 2, 0xFFFF, sum = 0
5472 12:17:25.082443 3, 0xFFFF, sum = 0
5473 12:17:25.082528 4, 0xFFFF, sum = 0
5474 12:17:25.085875 5, 0xFFFF, sum = 0
5475 12:17:25.085960 6, 0xFFFF, sum = 0
5476 12:17:25.088734 7, 0xFFFF, sum = 0
5477 12:17:25.088841 8, 0xFFFF, sum = 0
5478 12:17:25.092398 9, 0xFFFF, sum = 0
5479 12:17:25.092483 10, 0x0, sum = 1
5480 12:17:25.095566 11, 0x0, sum = 2
5481 12:17:25.095651 12, 0x0, sum = 3
5482 12:17:25.098953 13, 0x0, sum = 4
5483 12:17:25.099038 best_step = 11
5484 12:17:25.099146
5485 12:17:25.099209 ==
5486 12:17:25.102136 Dram Type= 6, Freq= 0, CH_0, rank 1
5487 12:17:25.108742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 12:17:25.108870 ==
5489 12:17:25.108954 RX Vref Scan: 0
5490 12:17:25.109018
5491 12:17:25.112236 RX Vref 0 -> 0, step: 1
5492 12:17:25.112321
5493 12:17:25.115620 RX Delay -53 -> 252, step: 4
5494 12:17:25.118627 iDelay=203, Bit 0, Center 104 (19 ~ 190) 172
5495 12:17:25.122083 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5496 12:17:25.128810 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5497 12:17:25.131722 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5498 12:17:25.135361 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5499 12:17:25.138523 iDelay=203, Bit 5, Center 98 (11 ~ 186) 176
5500 12:17:25.141575 iDelay=203, Bit 6, Center 112 (23 ~ 202) 180
5501 12:17:25.148356 iDelay=203, Bit 7, Center 110 (23 ~ 198) 176
5502 12:17:25.151763 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5503 12:17:25.154693 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5504 12:17:25.158050 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5505 12:17:25.161533 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5506 12:17:25.167829 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5507 12:17:25.171231 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5508 12:17:25.174482 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5509 12:17:25.177904 iDelay=203, Bit 15, Center 100 (19 ~ 182) 164
5510 12:17:25.178008 ==
5511 12:17:25.181291 Dram Type= 6, Freq= 0, CH_0, rank 1
5512 12:17:25.187679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 12:17:25.187784 ==
5514 12:17:25.187861 DQS Delay:
5515 12:17:25.191023 DQS0 = 0, DQS1 = 0
5516 12:17:25.191096 DQM Delay:
5517 12:17:25.191157 DQM0 = 104, DQM1 = 92
5518 12:17:25.194322 DQ Delay:
5519 12:17:25.197663 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5520 12:17:25.200940 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =110
5521 12:17:25.204288 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5522 12:17:25.207468 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =100
5523 12:17:25.207549
5524 12:17:25.207614
5525 12:17:25.214223 [DQSOSCAuto] RK1, (LSB)MR18= 0x2607, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5526 12:17:25.217364 CH0 RK1: MR19=505, MR18=2607
5527 12:17:25.224350 CH0_RK1: MR19=0x505, MR18=0x2607, DQSOSC=409, MR23=63, INC=64, DEC=43
5528 12:17:25.227117 [RxdqsGatingPostProcess] freq 933
5529 12:17:25.234079 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5530 12:17:25.237501 best DQS0 dly(2T, 0.5T) = (0, 10)
5531 12:17:25.240719 best DQS1 dly(2T, 0.5T) = (0, 10)
5532 12:17:25.243950 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5533 12:17:25.247495 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5534 12:17:25.247581 best DQS0 dly(2T, 0.5T) = (0, 10)
5535 12:17:25.250514 best DQS1 dly(2T, 0.5T) = (0, 10)
5536 12:17:25.254177 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5537 12:17:25.257097 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5538 12:17:25.260467 Pre-setting of DQS Precalculation
5539 12:17:25.267375 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5540 12:17:25.267463 ==
5541 12:17:25.270451 Dram Type= 6, Freq= 0, CH_1, rank 0
5542 12:17:25.273917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 12:17:25.274027 ==
5544 12:17:25.280091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5545 12:17:25.287100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5546 12:17:25.289974 [CA 0] Center 37 (7~68) winsize 62
5547 12:17:25.293430 [CA 1] Center 37 (7~68) winsize 62
5548 12:17:25.296922 [CA 2] Center 36 (6~66) winsize 61
5549 12:17:25.300101 [CA 3] Center 35 (5~65) winsize 61
5550 12:17:25.303537 [CA 4] Center 35 (5~66) winsize 62
5551 12:17:25.303623 [CA 5] Center 34 (4~64) winsize 61
5552 12:17:25.306962
5553 12:17:25.310028 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5554 12:17:25.310116
5555 12:17:25.313345 [CATrainingPosCal] consider 1 rank data
5556 12:17:25.316775 u2DelayCellTimex100 = 270/100 ps
5557 12:17:25.319914 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5558 12:17:25.323145 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5559 12:17:25.326305 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5560 12:17:25.329540 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5561 12:17:25.332994 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5562 12:17:25.336471 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5563 12:17:25.336546
5564 12:17:25.342858 CA PerBit enable=1, Macro0, CA PI delay=34
5565 12:17:25.342939
5566 12:17:25.343006 [CBTSetCACLKResult] CA Dly = 34
5567 12:17:25.346149 CS Dly: 6 (0~37)
5568 12:17:25.346229 ==
5569 12:17:25.349536 Dram Type= 6, Freq= 0, CH_1, rank 1
5570 12:17:25.353087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 12:17:25.353172 ==
5572 12:17:25.359845 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5573 12:17:25.366181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5574 12:17:25.369604 [CA 0] Center 38 (8~69) winsize 62
5575 12:17:25.372681 [CA 1] Center 38 (8~69) winsize 62
5576 12:17:25.376079 [CA 2] Center 36 (5~67) winsize 63
5577 12:17:25.379300 [CA 3] Center 35 (5~65) winsize 61
5578 12:17:25.382585 [CA 4] Center 35 (5~65) winsize 61
5579 12:17:25.386001 [CA 5] Center 34 (5~64) winsize 60
5580 12:17:25.386086
5581 12:17:25.389443 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5582 12:17:25.389517
5583 12:17:25.392894 [CATrainingPosCal] consider 2 rank data
5584 12:17:25.395794 u2DelayCellTimex100 = 270/100 ps
5585 12:17:25.399236 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5586 12:17:25.402830 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5587 12:17:25.405806 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5588 12:17:25.409092 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5589 12:17:25.412287 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5590 12:17:25.419079 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5591 12:17:25.419167
5592 12:17:25.422347 CA PerBit enable=1, Macro0, CA PI delay=34
5593 12:17:25.422432
5594 12:17:25.425361 [CBTSetCACLKResult] CA Dly = 34
5595 12:17:25.425483 CS Dly: 7 (0~39)
5596 12:17:25.425548
5597 12:17:25.428949 ----->DramcWriteLeveling(PI) begin...
5598 12:17:25.429035 ==
5599 12:17:25.432217 Dram Type= 6, Freq= 0, CH_1, rank 0
5600 12:17:25.438738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 12:17:25.438829 ==
5602 12:17:25.442186 Write leveling (Byte 0): 26 => 26
5603 12:17:25.442261 Write leveling (Byte 1): 28 => 28
5604 12:17:25.445626 DramcWriteLeveling(PI) end<-----
5605 12:17:25.445710
5606 12:17:25.448969 ==
5607 12:17:25.449052 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 12:17:25.455591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 12:17:25.455677 ==
5610 12:17:25.458587 [Gating] SW mode calibration
5611 12:17:25.465188 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5612 12:17:25.468547 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5613 12:17:25.474958 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 12:17:25.478427 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 12:17:25.481473 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 12:17:25.488034 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 12:17:25.491352 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 12:17:25.494832 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 12:17:25.501529 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
5620 12:17:25.504865 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5621 12:17:25.508030 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 12:17:25.514549 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 12:17:25.517894 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 12:17:25.521304 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 12:17:25.527756 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 12:17:25.531262 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 12:17:25.534261 0 15 24 | B1->B0 | 2d2d 3030 | 0 0 | (0 0) (0 0)
5628 12:17:25.541248 0 15 28 | B1->B0 | 3e3e 4545 | 0 1 | (0 0) (0 0)
5629 12:17:25.544279 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 12:17:25.547629 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 12:17:25.554042 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 12:17:25.557364 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 12:17:25.561108 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 12:17:25.567806 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 12:17:25.570953 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5636 12:17:25.574311 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5637 12:17:25.580996 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 12:17:25.584149 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 12:17:25.587433 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 12:17:25.593876 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 12:17:25.597160 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 12:17:25.600484 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 12:17:25.607061 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 12:17:25.610609 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 12:17:25.613903 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 12:17:25.620210 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 12:17:25.623504 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 12:17:25.626847 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 12:17:25.633373 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 12:17:25.636611 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5651 12:17:25.640155 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5652 12:17:25.646576 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5653 12:17:25.646673 Total UI for P1: 0, mck2ui 16
5654 12:17:25.653425 best dqsien dly found for B0: ( 1, 2, 22)
5655 12:17:25.656520 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 12:17:25.659670 Total UI for P1: 0, mck2ui 16
5657 12:17:25.663008 best dqsien dly found for B1: ( 1, 2, 28)
5658 12:17:25.666260 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5659 12:17:25.669652 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5660 12:17:25.669740
5661 12:17:25.672966 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5662 12:17:25.676287 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5663 12:17:25.679547 [Gating] SW calibration Done
5664 12:17:25.679635 ==
5665 12:17:25.682886 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 12:17:25.686163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 12:17:25.689552 ==
5668 12:17:25.689648 RX Vref Scan: 0
5669 12:17:25.689718
5670 12:17:25.692826 RX Vref 0 -> 0, step: 1
5671 12:17:25.692934
5672 12:17:25.696170 RX Delay -80 -> 252, step: 8
5673 12:17:25.699382 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5674 12:17:25.702837 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5675 12:17:25.706238 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5676 12:17:25.709508 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5677 12:17:25.712786 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5678 12:17:25.719240 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5679 12:17:25.722807 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5680 12:17:25.726005 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5681 12:17:25.729404 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5682 12:17:25.732709 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5683 12:17:25.736049 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5684 12:17:25.742297 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5685 12:17:25.745502 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5686 12:17:25.749036 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5687 12:17:25.751971 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5688 12:17:25.755517 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5689 12:17:25.759034 ==
5690 12:17:25.762281 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 12:17:25.765506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 12:17:25.765594 ==
5693 12:17:25.765662 DQS Delay:
5694 12:17:25.768711 DQS0 = 0, DQS1 = 0
5695 12:17:25.768805 DQM Delay:
5696 12:17:25.771994 DQM0 = 101, DQM1 = 94
5697 12:17:25.772081 DQ Delay:
5698 12:17:25.775364 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5699 12:17:25.778586 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5700 12:17:25.782124 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5701 12:17:25.785429 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5702 12:17:25.785515
5703 12:17:25.785582
5704 12:17:25.785661 ==
5705 12:17:25.788649 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 12:17:25.791972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 12:17:25.792063 ==
5708 12:17:25.795217
5709 12:17:25.795297
5710 12:17:25.795363 TX Vref Scan disable
5711 12:17:25.798426 == TX Byte 0 ==
5712 12:17:25.802010 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5713 12:17:25.804884 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5714 12:17:25.808625 == TX Byte 1 ==
5715 12:17:25.812043 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5716 12:17:25.814875 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5717 12:17:25.814965 ==
5718 12:17:25.818582 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 12:17:25.824729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 12:17:25.824835 ==
5721 12:17:25.824906
5722 12:17:25.824969
5723 12:17:25.825029 TX Vref Scan disable
5724 12:17:25.828999 == TX Byte 0 ==
5725 12:17:25.832603 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5726 12:17:25.839252 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5727 12:17:25.839345 == TX Byte 1 ==
5728 12:17:25.842617 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5729 12:17:25.848693 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5730 12:17:25.848788
5731 12:17:25.848858 [DATLAT]
5732 12:17:25.848924 Freq=933, CH1 RK0
5733 12:17:25.848985
5734 12:17:25.852154 DATLAT Default: 0xd
5735 12:17:25.855415 0, 0xFFFF, sum = 0
5736 12:17:25.855503 1, 0xFFFF, sum = 0
5737 12:17:25.858707 2, 0xFFFF, sum = 0
5738 12:17:25.858794 3, 0xFFFF, sum = 0
5739 12:17:25.862033 4, 0xFFFF, sum = 0
5740 12:17:25.862148 5, 0xFFFF, sum = 0
5741 12:17:25.865663 6, 0xFFFF, sum = 0
5742 12:17:25.865750 7, 0xFFFF, sum = 0
5743 12:17:25.868733 8, 0xFFFF, sum = 0
5744 12:17:25.868831 9, 0xFFFF, sum = 0
5745 12:17:25.872141 10, 0x0, sum = 1
5746 12:17:25.872228 11, 0x0, sum = 2
5747 12:17:25.875207 12, 0x0, sum = 3
5748 12:17:25.875287 13, 0x0, sum = 4
5749 12:17:25.878533 best_step = 11
5750 12:17:25.878621
5751 12:17:25.878688 ==
5752 12:17:25.881806 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 12:17:25.885119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 12:17:25.885209 ==
5755 12:17:25.885279 RX Vref Scan: 1
5756 12:17:25.885346
5757 12:17:25.888436 RX Vref 0 -> 0, step: 1
5758 12:17:25.888510
5759 12:17:25.891801 RX Delay -53 -> 252, step: 4
5760 12:17:25.891886
5761 12:17:25.895269 Set Vref, RX VrefLevel [Byte0]: 51
5762 12:17:25.898604 [Byte1]: 52
5763 12:17:25.901791
5764 12:17:25.901878 Final RX Vref Byte 0 = 51 to rank0
5765 12:17:25.905028 Final RX Vref Byte 1 = 52 to rank0
5766 12:17:25.908347 Final RX Vref Byte 0 = 51 to rank1
5767 12:17:25.911522 Final RX Vref Byte 1 = 52 to rank1==
5768 12:17:25.914945 Dram Type= 6, Freq= 0, CH_1, rank 0
5769 12:17:25.921553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 12:17:25.921660 ==
5771 12:17:25.921732 DQS Delay:
5772 12:17:25.924947 DQS0 = 0, DQS1 = 0
5773 12:17:25.925027 DQM Delay:
5774 12:17:25.925091 DQM0 = 104, DQM1 = 97
5775 12:17:25.928176 DQ Delay:
5776 12:17:25.931344 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5777 12:17:25.934520 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5778 12:17:25.937839 DQ8 =88, DQ9 =86, DQ10 =102, DQ11 =90
5779 12:17:25.941088 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =102
5780 12:17:25.941181
5781 12:17:25.941252
5782 12:17:25.951203 [DQSOSCAuto] RK0, (LSB)MR18= 0x172f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5783 12:17:25.951313 CH1 RK0: MR19=505, MR18=172F
5784 12:17:25.957872 CH1_RK0: MR19=0x505, MR18=0x172F, DQSOSC=407, MR23=63, INC=65, DEC=43
5785 12:17:25.957965
5786 12:17:25.961251 ----->DramcWriteLeveling(PI) begin...
5787 12:17:25.961340 ==
5788 12:17:25.964287 Dram Type= 6, Freq= 0, CH_1, rank 1
5789 12:17:25.971152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 12:17:25.971279 ==
5791 12:17:25.974188 Write leveling (Byte 0): 27 => 27
5792 12:17:25.974295 Write leveling (Byte 1): 28 => 28
5793 12:17:25.977719 DramcWriteLeveling(PI) end<-----
5794 12:17:25.977799
5795 12:17:25.977865 ==
5796 12:17:25.980675 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 12:17:25.987289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 12:17:25.987384 ==
5799 12:17:25.990592 [Gating] SW mode calibration
5800 12:17:25.997274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5801 12:17:26.000567 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5802 12:17:26.007100 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 12:17:26.010525 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 12:17:26.013869 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 12:17:26.020419 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 12:17:26.023779 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 12:17:26.027243 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5808 12:17:26.033731 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
5809 12:17:26.037272 0 14 28 | B1->B0 | 2323 2727 | 0 0 | (1 0) (1 1)
5810 12:17:26.040544 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5811 12:17:26.047289 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 12:17:26.050112 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 12:17:26.053418 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 12:17:26.060038 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 12:17:26.063385 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 12:17:26.067121 0 15 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
5817 12:17:26.073542 0 15 28 | B1->B0 | 3d3d 3535 | 0 0 | (0 0) (0 0)
5818 12:17:26.076676 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 12:17:26.079741 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 12:17:26.086582 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 12:17:26.089901 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 12:17:26.093017 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 12:17:26.099948 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 12:17:26.103232 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5825 12:17:26.106500 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 12:17:26.113005 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 12:17:26.116292 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 12:17:26.119581 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 12:17:26.125831 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 12:17:26.129225 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 12:17:26.132823 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 12:17:26.139090 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 12:17:26.142803 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 12:17:26.146106 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 12:17:26.152371 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 12:17:26.155643 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 12:17:26.159020 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 12:17:26.165700 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 12:17:26.169054 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 12:17:26.172490 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5841 12:17:26.179072 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 12:17:26.179211 Total UI for P1: 0, mck2ui 16
5843 12:17:26.185356 best dqsien dly found for B0: ( 1, 2, 24)
5844 12:17:26.185575 Total UI for P1: 0, mck2ui 16
5845 12:17:26.188758 best dqsien dly found for B1: ( 1, 2, 24)
5846 12:17:26.195394 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5847 12:17:26.198749 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5848 12:17:26.198878
5849 12:17:26.201874 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5850 12:17:26.205243 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5851 12:17:26.208462 [Gating] SW calibration Done
5852 12:17:26.208578 ==
5853 12:17:26.211716 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 12:17:26.215403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 12:17:26.215519 ==
5856 12:17:26.218771 RX Vref Scan: 0
5857 12:17:26.218862
5858 12:17:26.218952 RX Vref 0 -> 0, step: 1
5859 12:17:26.219035
5860 12:17:26.221765 RX Delay -80 -> 252, step: 8
5861 12:17:26.225091 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5862 12:17:26.231682 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5863 12:17:26.234849 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5864 12:17:26.238220 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5865 12:17:26.241444 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5866 12:17:26.244940 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5867 12:17:26.251222 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5868 12:17:26.254664 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5869 12:17:26.258057 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5870 12:17:26.261337 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5871 12:17:26.264651 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5872 12:17:26.271484 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5873 12:17:26.274424 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5874 12:17:26.277577 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5875 12:17:26.280963 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5876 12:17:26.284234 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5877 12:17:26.284324 ==
5878 12:17:26.287368 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 12:17:26.294063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 12:17:26.294163 ==
5881 12:17:26.294234 DQS Delay:
5882 12:17:26.297547 DQS0 = 0, DQS1 = 0
5883 12:17:26.297634 DQM Delay:
5884 12:17:26.300783 DQM0 = 103, DQM1 = 96
5885 12:17:26.300870 DQ Delay:
5886 12:17:26.304027 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5887 12:17:26.307069 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5888 12:17:26.310368 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5889 12:17:26.313691 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =107
5890 12:17:26.313777
5891 12:17:26.313844
5892 12:17:26.313904 ==
5893 12:17:26.317059 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 12:17:26.320185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 12:17:26.323419 ==
5896 12:17:26.323510
5897 12:17:26.323579
5898 12:17:26.323643 TX Vref Scan disable
5899 12:17:26.326840 == TX Byte 0 ==
5900 12:17:26.330213 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5901 12:17:26.333594 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5902 12:17:26.336755 == TX Byte 1 ==
5903 12:17:26.340014 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5904 12:17:26.346523 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5905 12:17:26.346626 ==
5906 12:17:26.350154 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 12:17:26.353406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 12:17:26.353497 ==
5909 12:17:26.353586
5910 12:17:26.353668
5911 12:17:26.356641 TX Vref Scan disable
5912 12:17:26.356772 == TX Byte 0 ==
5913 12:17:26.362919 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5914 12:17:26.366205 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5915 12:17:26.366318 == TX Byte 1 ==
5916 12:17:26.372923 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5917 12:17:26.376323 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5918 12:17:26.376408
5919 12:17:26.376473 [DATLAT]
5920 12:17:26.379725 Freq=933, CH1 RK1
5921 12:17:26.379809
5922 12:17:26.379874 DATLAT Default: 0xb
5923 12:17:26.382929 0, 0xFFFF, sum = 0
5924 12:17:26.383015 1, 0xFFFF, sum = 0
5925 12:17:26.386192 2, 0xFFFF, sum = 0
5926 12:17:26.386276 3, 0xFFFF, sum = 0
5927 12:17:26.389561 4, 0xFFFF, sum = 0
5928 12:17:26.393158 5, 0xFFFF, sum = 0
5929 12:17:26.393242 6, 0xFFFF, sum = 0
5930 12:17:26.396258 7, 0xFFFF, sum = 0
5931 12:17:26.396342 8, 0xFFFF, sum = 0
5932 12:17:26.399516 9, 0xFFFF, sum = 0
5933 12:17:26.399600 10, 0x0, sum = 1
5934 12:17:26.403055 11, 0x0, sum = 2
5935 12:17:26.403140 12, 0x0, sum = 3
5936 12:17:26.403207 13, 0x0, sum = 4
5937 12:17:26.406215 best_step = 11
5938 12:17:26.406298
5939 12:17:26.406363 ==
5940 12:17:26.409462 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 12:17:26.413020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 12:17:26.413104 ==
5943 12:17:26.416146 RX Vref Scan: 0
5944 12:17:26.416230
5945 12:17:26.419493 RX Vref 0 -> 0, step: 1
5946 12:17:26.419577
5947 12:17:26.419643 RX Delay -53 -> 252, step: 4
5948 12:17:26.426894 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5949 12:17:26.430240 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5950 12:17:26.433697 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5951 12:17:26.437078 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5952 12:17:26.440019 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5953 12:17:26.446617 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5954 12:17:26.449853 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5955 12:17:26.453316 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5956 12:17:26.456700 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5957 12:17:26.460020 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5958 12:17:26.466658 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5959 12:17:26.469560 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5960 12:17:26.473005 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5961 12:17:26.476222 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5962 12:17:26.479621 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5963 12:17:26.486213 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5964 12:17:26.486404 ==
5965 12:17:26.489550 Dram Type= 6, Freq= 0, CH_1, rank 1
5966 12:17:26.492787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5967 12:17:26.492940 ==
5968 12:17:26.493026 DQS Delay:
5969 12:17:26.496192 DQS0 = 0, DQS1 = 0
5970 12:17:26.496340 DQM Delay:
5971 12:17:26.499485 DQM0 = 105, DQM1 = 98
5972 12:17:26.499681 DQ Delay:
5973 12:17:26.502638 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =104
5974 12:17:26.506091 DQ4 =106, DQ5 =114, DQ6 =114, DQ7 =102
5975 12:17:26.509279 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
5976 12:17:26.512665 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5977 12:17:26.512865
5978 12:17:26.515783
5979 12:17:26.522638 [DQSOSCAuto] RK1, (LSB)MR18= 0x22ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5980 12:17:26.525931 CH1 RK1: MR19=504, MR18=22FF
5981 12:17:26.532380 CH1_RK1: MR19=0x504, MR18=0x22FF, DQSOSC=411, MR23=63, INC=64, DEC=42
5982 12:17:26.532555 [RxdqsGatingPostProcess] freq 933
5983 12:17:26.538971 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5984 12:17:26.542377 best DQS0 dly(2T, 0.5T) = (0, 10)
5985 12:17:26.545711 best DQS1 dly(2T, 0.5T) = (0, 10)
5986 12:17:26.548723 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5987 12:17:26.551901 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5988 12:17:26.555602 best DQS0 dly(2T, 0.5T) = (0, 10)
5989 12:17:26.558696 best DQS1 dly(2T, 0.5T) = (0, 10)
5990 12:17:26.562083 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5991 12:17:26.565446 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5992 12:17:26.568923 Pre-setting of DQS Precalculation
5993 12:17:26.572128 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5994 12:17:26.578716 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5995 12:17:26.588532 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5996 12:17:26.588711
5997 12:17:26.588800
5998 12:17:26.591681 [Calibration Summary] 1866 Mbps
5999 12:17:26.591820 CH 0, Rank 0
6000 12:17:26.594994 SW Impedance : PASS
6001 12:17:26.595144 DUTY Scan : NO K
6002 12:17:26.598486 ZQ Calibration : PASS
6003 12:17:26.601726 Jitter Meter : NO K
6004 12:17:26.601890 CBT Training : PASS
6005 12:17:26.604916 Write leveling : PASS
6006 12:17:26.608272 RX DQS gating : PASS
6007 12:17:26.608457 RX DQ/DQS(RDDQC) : PASS
6008 12:17:26.611323 TX DQ/DQS : PASS
6009 12:17:26.614827 RX DATLAT : PASS
6010 12:17:26.615022 RX DQ/DQS(Engine): PASS
6011 12:17:26.618242 TX OE : NO K
6012 12:17:26.618391 All Pass.
6013 12:17:26.618467
6014 12:17:26.621339 CH 0, Rank 1
6015 12:17:26.621493 SW Impedance : PASS
6016 12:17:26.624720 DUTY Scan : NO K
6017 12:17:26.624917 ZQ Calibration : PASS
6018 12:17:26.627790 Jitter Meter : NO K
6019 12:17:26.631048 CBT Training : PASS
6020 12:17:26.631226 Write leveling : PASS
6021 12:17:26.634637 RX DQS gating : PASS
6022 12:17:26.638057 RX DQ/DQS(RDDQC) : PASS
6023 12:17:26.638209 TX DQ/DQS : PASS
6024 12:17:26.641425 RX DATLAT : PASS
6025 12:17:26.644234 RX DQ/DQS(Engine): PASS
6026 12:17:26.644375 TX OE : NO K
6027 12:17:26.647967 All Pass.
6028 12:17:26.648141
6029 12:17:26.648223 CH 1, Rank 0
6030 12:17:26.651190 SW Impedance : PASS
6031 12:17:26.651358 DUTY Scan : NO K
6032 12:17:26.654459 ZQ Calibration : PASS
6033 12:17:26.657737 Jitter Meter : NO K
6034 12:17:26.657887 CBT Training : PASS
6035 12:17:26.660876 Write leveling : PASS
6036 12:17:26.664205 RX DQS gating : PASS
6037 12:17:26.664362 RX DQ/DQS(RDDQC) : PASS
6038 12:17:26.667522 TX DQ/DQS : PASS
6039 12:17:26.670854 RX DATLAT : PASS
6040 12:17:26.671011 RX DQ/DQS(Engine): PASS
6041 12:17:26.674199 TX OE : NO K
6042 12:17:26.674318 All Pass.
6043 12:17:26.674387
6044 12:17:26.677554 CH 1, Rank 1
6045 12:17:26.677640 SW Impedance : PASS
6046 12:17:26.680885 DUTY Scan : NO K
6047 12:17:26.680972 ZQ Calibration : PASS
6048 12:17:26.684199 Jitter Meter : NO K
6049 12:17:26.687557 CBT Training : PASS
6050 12:17:26.687665 Write leveling : PASS
6051 12:17:26.690831 RX DQS gating : PASS
6052 12:17:26.693991 RX DQ/DQS(RDDQC) : PASS
6053 12:17:26.694097 TX DQ/DQS : PASS
6054 12:17:26.697336 RX DATLAT : PASS
6055 12:17:26.700559 RX DQ/DQS(Engine): PASS
6056 12:17:26.700669 TX OE : NO K
6057 12:17:26.703913 All Pass.
6058 12:17:26.703997
6059 12:17:26.704064 DramC Write-DBI off
6060 12:17:26.707145 PER_BANK_REFRESH: Hybrid Mode
6061 12:17:26.710395 TX_TRACKING: ON
6062 12:17:26.717003 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6063 12:17:26.720522 [FAST_K] Save calibration result to emmc
6064 12:17:26.723487 dramc_set_vcore_voltage set vcore to 650000
6065 12:17:26.726895 Read voltage for 400, 6
6066 12:17:26.727014 Vio18 = 0
6067 12:17:26.730584 Vcore = 650000
6068 12:17:26.730668 Vdram = 0
6069 12:17:26.730730 Vddq = 0
6070 12:17:26.733512 Vmddr = 0
6071 12:17:26.737044 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6072 12:17:26.743566 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6073 12:17:26.743652 MEM_TYPE=3, freq_sel=20
6074 12:17:26.746913 sv_algorithm_assistance_LP4_800
6075 12:17:26.753544 ============ PULL DRAM RESETB DOWN ============
6076 12:17:26.757055 ========== PULL DRAM RESETB DOWN end =========
6077 12:17:26.760050 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6078 12:17:26.763247 ===================================
6079 12:17:26.766486 LPDDR4 DRAM CONFIGURATION
6080 12:17:26.769868 ===================================
6081 12:17:26.773308 EX_ROW_EN[0] = 0x0
6082 12:17:26.773387 EX_ROW_EN[1] = 0x0
6083 12:17:26.776502 LP4Y_EN = 0x0
6084 12:17:26.776577 WORK_FSP = 0x0
6085 12:17:26.779745 WL = 0x2
6086 12:17:26.779820 RL = 0x2
6087 12:17:26.783105 BL = 0x2
6088 12:17:26.783184 RPST = 0x0
6089 12:17:26.786401 RD_PRE = 0x0
6090 12:17:26.786475 WR_PRE = 0x1
6091 12:17:26.789731 WR_PST = 0x0
6092 12:17:26.789838 DBI_WR = 0x0
6093 12:17:26.793074 DBI_RD = 0x0
6094 12:17:26.793147 OTF = 0x1
6095 12:17:26.796255 ===================================
6096 12:17:26.799898 ===================================
6097 12:17:26.803271 ANA top config
6098 12:17:26.806577 ===================================
6099 12:17:26.810022 DLL_ASYNC_EN = 0
6100 12:17:26.810102 ALL_SLAVE_EN = 1
6101 12:17:26.812996 NEW_RANK_MODE = 1
6102 12:17:26.816291 DLL_IDLE_MODE = 1
6103 12:17:26.819513 LP45_APHY_COMB_EN = 1
6104 12:17:26.819614 TX_ODT_DIS = 1
6105 12:17:26.823208 NEW_8X_MODE = 1
6106 12:17:26.826394 ===================================
6107 12:17:26.829546 ===================================
6108 12:17:26.833139 data_rate = 800
6109 12:17:26.836239 CKR = 1
6110 12:17:26.839475 DQ_P2S_RATIO = 4
6111 12:17:26.842606 ===================================
6112 12:17:26.846191 CA_P2S_RATIO = 4
6113 12:17:26.846299 DQ_CA_OPEN = 0
6114 12:17:26.849369 DQ_SEMI_OPEN = 1
6115 12:17:26.852655 CA_SEMI_OPEN = 1
6116 12:17:26.856065 CA_FULL_RATE = 0
6117 12:17:26.859152 DQ_CKDIV4_EN = 0
6118 12:17:26.862681 CA_CKDIV4_EN = 1
6119 12:17:26.862755 CA_PREDIV_EN = 0
6120 12:17:26.866022 PH8_DLY = 0
6121 12:17:26.869277 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6122 12:17:26.872488 DQ_AAMCK_DIV = 0
6123 12:17:26.875824 CA_AAMCK_DIV = 0
6124 12:17:26.879125 CA_ADMCK_DIV = 4
6125 12:17:26.879206 DQ_TRACK_CA_EN = 0
6126 12:17:26.882426 CA_PICK = 800
6127 12:17:26.885840 CA_MCKIO = 400
6128 12:17:26.889124 MCKIO_SEMI = 400
6129 12:17:26.892492 PLL_FREQ = 3016
6130 12:17:26.895936 DQ_UI_PI_RATIO = 32
6131 12:17:26.898838 CA_UI_PI_RATIO = 32
6132 12:17:26.902352 ===================================
6133 12:17:26.905730 ===================================
6134 12:17:26.909055 memory_type:LPDDR4
6135 12:17:26.909138 GP_NUM : 10
6136 12:17:26.912420 SRAM_EN : 1
6137 12:17:26.912530 MD32_EN : 0
6138 12:17:26.915774 ===================================
6139 12:17:26.919036 [ANA_INIT] >>>>>>>>>>>>>>
6140 12:17:26.921885 <<<<<< [CONFIGURE PHASE]: ANA_TX
6141 12:17:26.925611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6142 12:17:26.928632 ===================================
6143 12:17:26.931914 data_rate = 800,PCW = 0X7400
6144 12:17:26.935555 ===================================
6145 12:17:26.938658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6146 12:17:26.942202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6147 12:17:26.955185 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6148 12:17:26.958508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6149 12:17:26.961826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6150 12:17:26.965020 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6151 12:17:26.968292 [ANA_INIT] flow start
6152 12:17:26.971517 [ANA_INIT] PLL >>>>>>>>
6153 12:17:26.971633 [ANA_INIT] PLL <<<<<<<<
6154 12:17:26.974693 [ANA_INIT] MIDPI >>>>>>>>
6155 12:17:26.978437 [ANA_INIT] MIDPI <<<<<<<<
6156 12:17:26.981728 [ANA_INIT] DLL >>>>>>>>
6157 12:17:26.981812 [ANA_INIT] flow end
6158 12:17:26.985083 ============ LP4 DIFF to SE enter ============
6159 12:17:26.991641 ============ LP4 DIFF to SE exit ============
6160 12:17:26.991749 [ANA_INIT] <<<<<<<<<<<<<
6161 12:17:26.994848 [Flow] Enable top DCM control >>>>>
6162 12:17:26.998153 [Flow] Enable top DCM control <<<<<
6163 12:17:27.001410 Enable DLL master slave shuffle
6164 12:17:27.008251 ==============================================================
6165 12:17:27.008392 Gating Mode config
6166 12:17:27.014869 ==============================================================
6167 12:17:27.018232 Config description:
6168 12:17:27.024916 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6169 12:17:27.034670 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6170 12:17:27.038070 SELPH_MODE 0: By rank 1: By Phase
6171 12:17:27.044854 ==============================================================
6172 12:17:27.047810 GAT_TRACK_EN = 0
6173 12:17:27.047920 RX_GATING_MODE = 2
6174 12:17:27.051370 RX_GATING_TRACK_MODE = 2
6175 12:17:27.054583 SELPH_MODE = 1
6176 12:17:27.058030 PICG_EARLY_EN = 1
6177 12:17:27.061167 VALID_LAT_VALUE = 1
6178 12:17:27.067778 ==============================================================
6179 12:17:27.071440 Enter into Gating configuration >>>>
6180 12:17:27.074803 Exit from Gating configuration <<<<
6181 12:17:27.077923 Enter into DVFS_PRE_config >>>>>
6182 12:17:27.087843 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6183 12:17:27.091159 Exit from DVFS_PRE_config <<<<<
6184 12:17:27.094460 Enter into PICG configuration >>>>
6185 12:17:27.097767 Exit from PICG configuration <<<<
6186 12:17:27.101099 [RX_INPUT] configuration >>>>>
6187 12:17:27.104384 [RX_INPUT] configuration <<<<<
6188 12:17:27.107703 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6189 12:17:27.114180 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6190 12:17:27.120715 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6191 12:17:27.127421 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6192 12:17:27.130724 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6193 12:17:27.137084 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6194 12:17:27.140462 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6195 12:17:27.147157 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6196 12:17:27.150311 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6197 12:17:27.153698 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6198 12:17:27.156694 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6199 12:17:27.163454 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6200 12:17:27.166974 ===================================
6201 12:17:27.170393 LPDDR4 DRAM CONFIGURATION
6202 12:17:27.173640 ===================================
6203 12:17:27.173725 EX_ROW_EN[0] = 0x0
6204 12:17:27.176962 EX_ROW_EN[1] = 0x0
6205 12:17:27.177046 LP4Y_EN = 0x0
6206 12:17:27.180191 WORK_FSP = 0x0
6207 12:17:27.180274 WL = 0x2
6208 12:17:27.183243 RL = 0x2
6209 12:17:27.183353 BL = 0x2
6210 12:17:27.186540 RPST = 0x0
6211 12:17:27.186640 RD_PRE = 0x0
6212 12:17:27.189830 WR_PRE = 0x1
6213 12:17:27.189931 WR_PST = 0x0
6214 12:17:27.193193 DBI_WR = 0x0
6215 12:17:27.193276 DBI_RD = 0x0
6216 12:17:27.196472 OTF = 0x1
6217 12:17:27.199850 ===================================
6218 12:17:27.203174 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6219 12:17:27.206608 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6220 12:17:27.213357 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6221 12:17:27.216602 ===================================
6222 12:17:27.216720 LPDDR4 DRAM CONFIGURATION
6223 12:17:27.219947 ===================================
6224 12:17:27.223117 EX_ROW_EN[0] = 0x10
6225 12:17:27.226433 EX_ROW_EN[1] = 0x0
6226 12:17:27.226533 LP4Y_EN = 0x0
6227 12:17:27.229808 WORK_FSP = 0x0
6228 12:17:27.229908 WL = 0x2
6229 12:17:27.233107 RL = 0x2
6230 12:17:27.233212 BL = 0x2
6231 12:17:27.235999 RPST = 0x0
6232 12:17:27.236096 RD_PRE = 0x0
6233 12:17:27.239665 WR_PRE = 0x1
6234 12:17:27.239766 WR_PST = 0x0
6235 12:17:27.242741 DBI_WR = 0x0
6236 12:17:27.242841 DBI_RD = 0x0
6237 12:17:27.246083 OTF = 0x1
6238 12:17:27.249398 ===================================
6239 12:17:27.255773 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6240 12:17:27.259443 nWR fixed to 30
6241 12:17:27.262772 [ModeRegInit_LP4] CH0 RK0
6242 12:17:27.262893 [ModeRegInit_LP4] CH0 RK1
6243 12:17:27.265761 [ModeRegInit_LP4] CH1 RK0
6244 12:17:27.269192 [ModeRegInit_LP4] CH1 RK1
6245 12:17:27.269316 match AC timing 19
6246 12:17:27.275737 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6247 12:17:27.279206 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6248 12:17:27.282658 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6249 12:17:27.288972 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6250 12:17:27.292347 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6251 12:17:27.292451 ==
6252 12:17:27.295538 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 12:17:27.298955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 12:17:27.299028 ==
6255 12:17:27.305570 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6256 12:17:27.312159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6257 12:17:27.315375 [CA 0] Center 36 (8~64) winsize 57
6258 12:17:27.318988 [CA 1] Center 36 (8~64) winsize 57
6259 12:17:27.322171 [CA 2] Center 36 (8~64) winsize 57
6260 12:17:27.325431 [CA 3] Center 36 (8~64) winsize 57
6261 12:17:27.328685 [CA 4] Center 36 (8~64) winsize 57
6262 12:17:27.328813 [CA 5] Center 36 (8~64) winsize 57
6263 12:17:27.332190
6264 12:17:27.335537 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6265 12:17:27.335623
6266 12:17:27.338896 [CATrainingPosCal] consider 1 rank data
6267 12:17:27.342194 u2DelayCellTimex100 = 270/100 ps
6268 12:17:27.345415 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 12:17:27.348602 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 12:17:27.351966 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 12:17:27.355358 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 12:17:27.358660 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 12:17:27.361729 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 12:17:27.361837
6275 12:17:27.365127 CA PerBit enable=1, Macro0, CA PI delay=36
6276 12:17:27.365212
6277 12:17:27.368420 [CBTSetCACLKResult] CA Dly = 36
6278 12:17:27.371643 CS Dly: 1 (0~32)
6279 12:17:27.371726 ==
6280 12:17:27.375052 Dram Type= 6, Freq= 0, CH_0, rank 1
6281 12:17:27.378134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 12:17:27.378218 ==
6283 12:17:27.385070 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6284 12:17:27.391433 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6285 12:17:27.394781 [CA 0] Center 36 (8~64) winsize 57
6286 12:17:27.398044 [CA 1] Center 36 (8~64) winsize 57
6287 12:17:27.398128 [CA 2] Center 36 (8~64) winsize 57
6288 12:17:27.401355 [CA 3] Center 36 (8~64) winsize 57
6289 12:17:27.404555 [CA 4] Center 36 (8~64) winsize 57
6290 12:17:27.408002 [CA 5] Center 36 (8~64) winsize 57
6291 12:17:27.408085
6292 12:17:27.411348 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6293 12:17:27.414688
6294 12:17:27.417963 [CATrainingPosCal] consider 2 rank data
6295 12:17:27.418050 u2DelayCellTimex100 = 270/100 ps
6296 12:17:27.424673 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 12:17:27.427933 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 12:17:27.431325 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 12:17:27.434601 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 12:17:27.437915 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 12:17:27.441186 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 12:17:27.441277
6303 12:17:27.444614 CA PerBit enable=1, Macro0, CA PI delay=36
6304 12:17:27.444697
6305 12:17:27.447848 [CBTSetCACLKResult] CA Dly = 36
6306 12:17:27.451016 CS Dly: 1 (0~32)
6307 12:17:27.451102
6308 12:17:27.454211 ----->DramcWriteLeveling(PI) begin...
6309 12:17:27.454324 ==
6310 12:17:27.457630 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 12:17:27.460991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 12:17:27.461094 ==
6313 12:17:27.463777 Write leveling (Byte 0): 40 => 8
6314 12:17:27.467539 Write leveling (Byte 1): 32 => 0
6315 12:17:27.470778 DramcWriteLeveling(PI) end<-----
6316 12:17:27.470881
6317 12:17:27.470971 ==
6318 12:17:27.474021 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 12:17:27.477276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 12:17:27.477361 ==
6321 12:17:27.480549 [Gating] SW mode calibration
6322 12:17:27.487132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6323 12:17:27.493838 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6324 12:17:27.496963 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6325 12:17:27.500385 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6326 12:17:27.507069 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 12:17:27.510074 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6328 12:17:27.513383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 12:17:27.520255 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 12:17:27.523556 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 12:17:27.526859 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 12:17:27.533377 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 12:17:27.536733 Total UI for P1: 0, mck2ui 16
6334 12:17:27.540038 best dqsien dly found for B0: ( 0, 14, 24)
6335 12:17:27.543309 Total UI for P1: 0, mck2ui 16
6336 12:17:27.546604 best dqsien dly found for B1: ( 0, 14, 24)
6337 12:17:27.549924 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6338 12:17:27.553253 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6339 12:17:27.553395
6340 12:17:27.556336 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6341 12:17:27.559702 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6342 12:17:27.563050 [Gating] SW calibration Done
6343 12:17:27.563161 ==
6344 12:17:27.566425 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 12:17:27.569650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 12:17:27.569752 ==
6347 12:17:27.573027 RX Vref Scan: 0
6348 12:17:27.573111
6349 12:17:27.576361 RX Vref 0 -> 0, step: 1
6350 12:17:27.576447
6351 12:17:27.576516 RX Delay -410 -> 252, step: 16
6352 12:17:27.583085 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6353 12:17:27.586380 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6354 12:17:27.589977 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6355 12:17:27.596177 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6356 12:17:27.599589 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6357 12:17:27.602729 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6358 12:17:27.606196 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6359 12:17:27.613041 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6360 12:17:27.616322 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6361 12:17:27.619654 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6362 12:17:27.622956 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6363 12:17:27.629555 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6364 12:17:27.632698 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6365 12:17:27.636127 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6366 12:17:27.639406 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6367 12:17:27.646043 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6368 12:17:27.646120 ==
6369 12:17:27.649269 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 12:17:27.652616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 12:17:27.652691 ==
6372 12:17:27.652778 DQS Delay:
6373 12:17:27.655939 DQS0 = 27, DQS1 = 43
6374 12:17:27.656009 DQM Delay:
6375 12:17:27.659506 DQM0 = 12, DQM1 = 12
6376 12:17:27.659583 DQ Delay:
6377 12:17:27.662873 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6378 12:17:27.665739 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6379 12:17:27.669114 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6380 12:17:27.672322 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6381 12:17:27.672397
6382 12:17:27.672457
6383 12:17:27.672515 ==
6384 12:17:27.676078 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 12:17:27.679313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 12:17:27.679400 ==
6387 12:17:27.679461
6388 12:17:27.679518
6389 12:17:27.682509 TX Vref Scan disable
6390 12:17:27.685810 == TX Byte 0 ==
6391 12:17:27.689111 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 12:17:27.692628 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 12:17:27.695543 == TX Byte 1 ==
6394 12:17:27.698760 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6395 12:17:27.702438 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6396 12:17:27.702549 ==
6397 12:17:27.705527 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 12:17:27.708594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 12:17:27.711974 ==
6400 12:17:27.712053
6401 12:17:27.712122
6402 12:17:27.712213 TX Vref Scan disable
6403 12:17:27.715463 == TX Byte 0 ==
6404 12:17:27.718842 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 12:17:27.722215 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 12:17:27.725533 == TX Byte 1 ==
6407 12:17:27.728897 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6408 12:17:27.731767 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6409 12:17:27.731849
6410 12:17:27.735035 [DATLAT]
6411 12:17:27.735116 Freq=400, CH0 RK0
6412 12:17:27.735181
6413 12:17:27.738708 DATLAT Default: 0xf
6414 12:17:27.738789 0, 0xFFFF, sum = 0
6415 12:17:27.741968 1, 0xFFFF, sum = 0
6416 12:17:27.742050 2, 0xFFFF, sum = 0
6417 12:17:27.745354 3, 0xFFFF, sum = 0
6418 12:17:27.745436 4, 0xFFFF, sum = 0
6419 12:17:27.748120 5, 0xFFFF, sum = 0
6420 12:17:27.748202 6, 0xFFFF, sum = 0
6421 12:17:27.751936 7, 0xFFFF, sum = 0
6422 12:17:27.752018 8, 0xFFFF, sum = 0
6423 12:17:27.755236 9, 0xFFFF, sum = 0
6424 12:17:27.755318 10, 0xFFFF, sum = 0
6425 12:17:27.758420 11, 0xFFFF, sum = 0
6426 12:17:27.761537 12, 0xFFFF, sum = 0
6427 12:17:27.761619 13, 0x0, sum = 1
6428 12:17:27.764877 14, 0x0, sum = 2
6429 12:17:27.764959 15, 0x0, sum = 3
6430 12:17:27.765024 16, 0x0, sum = 4
6431 12:17:27.768178 best_step = 14
6432 12:17:27.768259
6433 12:17:27.768322 ==
6434 12:17:27.771493 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 12:17:27.774828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 12:17:27.774910 ==
6437 12:17:27.778050 RX Vref Scan: 1
6438 12:17:27.778132
6439 12:17:27.781225 RX Vref 0 -> 0, step: 1
6440 12:17:27.781306
6441 12:17:27.781369 RX Delay -327 -> 252, step: 8
6442 12:17:27.781428
6443 12:17:27.784542 Set Vref, RX VrefLevel [Byte0]: 59
6444 12:17:27.787691 [Byte1]: 49
6445 12:17:27.793167
6446 12:17:27.793251 Final RX Vref Byte 0 = 59 to rank0
6447 12:17:27.796437 Final RX Vref Byte 1 = 49 to rank0
6448 12:17:27.799847 Final RX Vref Byte 0 = 59 to rank1
6449 12:17:27.803148 Final RX Vref Byte 1 = 49 to rank1==
6450 12:17:27.806332 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 12:17:27.813160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 12:17:27.813246 ==
6453 12:17:27.813310 DQS Delay:
6454 12:17:27.816249 DQS0 = 28, DQS1 = 48
6455 12:17:27.816330 DQM Delay:
6456 12:17:27.816394 DQM0 = 12, DQM1 = 14
6457 12:17:27.819438 DQ Delay:
6458 12:17:27.822871 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6459 12:17:27.825928 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6460 12:17:27.826010 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6461 12:17:27.829685 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6462 12:17:27.832611
6463 12:17:27.832722
6464 12:17:27.839207 [DQSOSCAuto] RK0, (LSB)MR18= 0xada4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6465 12:17:27.842902 CH0 RK0: MR19=C0C, MR18=ADA4
6466 12:17:27.849210 CH0_RK0: MR19=0xC0C, MR18=0xADA4, DQSOSC=388, MR23=63, INC=392, DEC=261
6467 12:17:27.849318 ==
6468 12:17:27.852448 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 12:17:27.855868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 12:17:27.855943 ==
6471 12:17:27.859204 [Gating] SW mode calibration
6472 12:17:27.865773 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6473 12:17:27.872368 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6474 12:17:27.875679 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6475 12:17:27.878896 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6476 12:17:27.885785 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 12:17:27.889097 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6478 12:17:27.892440 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 12:17:27.898954 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 12:17:27.902394 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 12:17:27.905285 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 12:17:27.911785 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 12:17:27.911905 Total UI for P1: 0, mck2ui 16
6484 12:17:27.918486 best dqsien dly found for B0: ( 0, 14, 24)
6485 12:17:27.918570 Total UI for P1: 0, mck2ui 16
6486 12:17:27.925156 best dqsien dly found for B1: ( 0, 14, 24)
6487 12:17:27.928520 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6488 12:17:27.932154 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6489 12:17:27.932237
6490 12:17:27.934929 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6491 12:17:27.938335 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6492 12:17:27.941754 [Gating] SW calibration Done
6493 12:17:27.941836 ==
6494 12:17:27.944754 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 12:17:27.948050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 12:17:27.948137 ==
6497 12:17:27.951397 RX Vref Scan: 0
6498 12:17:27.951470
6499 12:17:27.951532 RX Vref 0 -> 0, step: 1
6500 12:17:27.954783
6501 12:17:27.954866 RX Delay -410 -> 252, step: 16
6502 12:17:27.961475 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6503 12:17:27.964786 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6504 12:17:27.968217 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6505 12:17:27.971282 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6506 12:17:27.977979 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6507 12:17:27.981305 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6508 12:17:27.984533 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6509 12:17:27.988244 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6510 12:17:27.994312 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6511 12:17:27.998090 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6512 12:17:28.001261 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6513 12:17:28.004601 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6514 12:17:28.011011 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6515 12:17:28.014269 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6516 12:17:28.017982 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6517 12:17:28.024192 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6518 12:17:28.024280 ==
6519 12:17:28.027775 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 12:17:28.030974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 12:17:28.031072 ==
6522 12:17:28.031168 DQS Delay:
6523 12:17:28.034472 DQS0 = 19, DQS1 = 35
6524 12:17:28.034555 DQM Delay:
6525 12:17:28.037542 DQM0 = 3, DQM1 = 10
6526 12:17:28.037623 DQ Delay:
6527 12:17:28.040686 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6528 12:17:28.044098 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =8
6529 12:17:28.047384 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6530 12:17:28.050539 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6531 12:17:28.050623
6532 12:17:28.050688
6533 12:17:28.050749 ==
6534 12:17:28.053922 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 12:17:28.057147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 12:17:28.057257 ==
6537 12:17:28.057350
6538 12:17:28.057441
6539 12:17:28.060472 TX Vref Scan disable
6540 12:17:28.060555 == TX Byte 0 ==
6541 12:17:28.067150 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6542 12:17:28.070447 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6543 12:17:28.070531 == TX Byte 1 ==
6544 12:17:28.077361 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6545 12:17:28.080165 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6546 12:17:28.080264 ==
6547 12:17:28.083484 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 12:17:28.086784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 12:17:28.086876 ==
6550 12:17:28.086945
6551 12:17:28.087007
6552 12:17:28.090423 TX Vref Scan disable
6553 12:17:28.093454 == TX Byte 0 ==
6554 12:17:28.096744 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6555 12:17:28.099989 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6556 12:17:28.100064 == TX Byte 1 ==
6557 12:17:28.106940 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6558 12:17:28.109889 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6559 12:17:28.109967
6560 12:17:28.110031 [DATLAT]
6561 12:17:28.113183 Freq=400, CH0 RK1
6562 12:17:28.113261
6563 12:17:28.113324 DATLAT Default: 0xe
6564 12:17:28.116554 0, 0xFFFF, sum = 0
6565 12:17:28.116673 1, 0xFFFF, sum = 0
6566 12:17:28.119885 2, 0xFFFF, sum = 0
6567 12:17:28.123238 3, 0xFFFF, sum = 0
6568 12:17:28.123354 4, 0xFFFF, sum = 0
6569 12:17:28.126419 5, 0xFFFF, sum = 0
6570 12:17:28.126504 6, 0xFFFF, sum = 0
6571 12:17:28.129697 7, 0xFFFF, sum = 0
6572 12:17:28.129784 8, 0xFFFF, sum = 0
6573 12:17:28.133161 9, 0xFFFF, sum = 0
6574 12:17:28.133281 10, 0xFFFF, sum = 0
6575 12:17:28.136146 11, 0xFFFF, sum = 0
6576 12:17:28.136221 12, 0xFFFF, sum = 0
6577 12:17:28.139768 13, 0x0, sum = 1
6578 12:17:28.139871 14, 0x0, sum = 2
6579 12:17:28.142818 15, 0x0, sum = 3
6580 12:17:28.142929 16, 0x0, sum = 4
6581 12:17:28.146507 best_step = 14
6582 12:17:28.146609
6583 12:17:28.146699 ==
6584 12:17:28.149811 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 12:17:28.152983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 12:17:28.153054 ==
6587 12:17:28.153121 RX Vref Scan: 0
6588 12:17:28.156278
6589 12:17:28.156371 RX Vref 0 -> 0, step: 1
6590 12:17:28.156458
6591 12:17:28.159677 RX Delay -311 -> 252, step: 8
6592 12:17:28.166826 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6593 12:17:28.170178 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6594 12:17:28.173433 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6595 12:17:28.179842 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6596 12:17:28.183202 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6597 12:17:28.186508 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6598 12:17:28.189799 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6599 12:17:28.193005 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6600 12:17:28.199861 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6601 12:17:28.203243 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6602 12:17:28.206400 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6603 12:17:28.213087 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6604 12:17:28.216426 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6605 12:17:28.219806 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6606 12:17:28.223163 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6607 12:17:28.229637 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6608 12:17:28.229749 ==
6609 12:17:28.232668 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 12:17:28.236433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 12:17:28.236544 ==
6612 12:17:28.236639 DQS Delay:
6613 12:17:28.239510 DQS0 = 28, DQS1 = 40
6614 12:17:28.239618 DQM Delay:
6615 12:17:28.242675 DQM0 = 10, DQM1 = 11
6616 12:17:28.242748 DQ Delay:
6617 12:17:28.246162 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6618 12:17:28.249312 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6619 12:17:28.252709 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6620 12:17:28.255983 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6621 12:17:28.256092
6622 12:17:28.256180
6623 12:17:28.265747 [DQSOSCAuto] RK1, (LSB)MR18= 0xb468, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6624 12:17:28.265831 CH0 RK1: MR19=C0C, MR18=B468
6625 12:17:28.272347 CH0_RK1: MR19=0xC0C, MR18=0xB468, DQSOSC=387, MR23=63, INC=394, DEC=262
6626 12:17:28.275730 [RxdqsGatingPostProcess] freq 400
6627 12:17:28.282293 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6628 12:17:28.285423 best DQS0 dly(2T, 0.5T) = (0, 10)
6629 12:17:28.288708 best DQS1 dly(2T, 0.5T) = (0, 10)
6630 12:17:28.291969 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6631 12:17:28.295320 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6632 12:17:28.298934 best DQS0 dly(2T, 0.5T) = (0, 10)
6633 12:17:28.299019 best DQS1 dly(2T, 0.5T) = (0, 10)
6634 12:17:28.302107 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6635 12:17:28.305327 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6636 12:17:28.308612 Pre-setting of DQS Precalculation
6637 12:17:28.315246 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6638 12:17:28.315331 ==
6639 12:17:28.318623 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 12:17:28.321988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 12:17:28.322074 ==
6642 12:17:28.328695 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6643 12:17:28.335000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6644 12:17:28.338642 [CA 0] Center 36 (8~64) winsize 57
6645 12:17:28.341636 [CA 1] Center 36 (8~64) winsize 57
6646 12:17:28.344792 [CA 2] Center 36 (8~64) winsize 57
6647 12:17:28.344884 [CA 3] Center 36 (8~64) winsize 57
6648 12:17:28.348296 [CA 4] Center 36 (8~64) winsize 57
6649 12:17:28.351492 [CA 5] Center 36 (8~64) winsize 57
6650 12:17:28.351596
6651 12:17:28.358071 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6652 12:17:28.358159
6653 12:17:28.361259 [CATrainingPosCal] consider 1 rank data
6654 12:17:28.364803 u2DelayCellTimex100 = 270/100 ps
6655 12:17:28.368120 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 12:17:28.371295 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 12:17:28.374647 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 12:17:28.378107 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 12:17:28.381380 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 12:17:28.384653 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 12:17:28.384737
6662 12:17:28.387953 CA PerBit enable=1, Macro0, CA PI delay=36
6663 12:17:28.388035
6664 12:17:28.391228 [CBTSetCACLKResult] CA Dly = 36
6665 12:17:28.394539 CS Dly: 1 (0~32)
6666 12:17:28.394621 ==
6667 12:17:28.397858 Dram Type= 6, Freq= 0, CH_1, rank 1
6668 12:17:28.401318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 12:17:28.401402 ==
6670 12:17:28.407761 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6671 12:17:28.414301 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6672 12:17:28.417465 [CA 0] Center 36 (8~64) winsize 57
6673 12:17:28.417549 [CA 1] Center 36 (8~64) winsize 57
6674 12:17:28.420987 [CA 2] Center 36 (8~64) winsize 57
6675 12:17:28.424169 [CA 3] Center 36 (8~64) winsize 57
6676 12:17:28.427527 [CA 4] Center 36 (8~64) winsize 57
6677 12:17:28.430886 [CA 5] Center 36 (8~64) winsize 57
6678 12:17:28.430964
6679 12:17:28.434131 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6680 12:17:28.434292
6681 12:17:28.440709 [CATrainingPosCal] consider 2 rank data
6682 12:17:28.440861 u2DelayCellTimex100 = 270/100 ps
6683 12:17:28.444018 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 12:17:28.450483 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 12:17:28.453893 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 12:17:28.457016 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 12:17:28.460450 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 12:17:28.463803 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 12:17:28.463888
6690 12:17:28.467322 CA PerBit enable=1, Macro0, CA PI delay=36
6691 12:17:28.467431
6692 12:17:28.470319 [CBTSetCACLKResult] CA Dly = 36
6693 12:17:28.473506 CS Dly: 1 (0~32)
6694 12:17:28.473599
6695 12:17:28.476871 ----->DramcWriteLeveling(PI) begin...
6696 12:17:28.476977 ==
6697 12:17:28.480230 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 12:17:28.483579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 12:17:28.483664 ==
6700 12:17:28.486849 Write leveling (Byte 0): 40 => 8
6701 12:17:28.490082 Write leveling (Byte 1): 32 => 0
6702 12:17:28.493473 DramcWriteLeveling(PI) end<-----
6703 12:17:28.493557
6704 12:17:28.493622 ==
6705 12:17:28.496810 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 12:17:28.500169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 12:17:28.500253 ==
6708 12:17:28.503296 [Gating] SW mode calibration
6709 12:17:28.509739 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6710 12:17:28.516191 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6711 12:17:28.519869 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6712 12:17:28.523151 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6713 12:17:28.529288 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 12:17:28.533063 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6715 12:17:28.535916 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 12:17:28.542417 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 12:17:28.545855 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 12:17:28.549256 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 12:17:28.555743 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 12:17:28.559015 Total UI for P1: 0, mck2ui 16
6721 12:17:28.562594 best dqsien dly found for B0: ( 0, 14, 24)
6722 12:17:28.565777 Total UI for P1: 0, mck2ui 16
6723 12:17:28.569257 best dqsien dly found for B1: ( 0, 14, 24)
6724 12:17:28.572305 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6725 12:17:28.575747 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6726 12:17:28.575829
6727 12:17:28.578870 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6728 12:17:28.582219 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6729 12:17:28.585615 [Gating] SW calibration Done
6730 12:17:28.585696 ==
6731 12:17:28.588887 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 12:17:28.592214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 12:17:28.595365 ==
6734 12:17:28.595460 RX Vref Scan: 0
6735 12:17:28.595637
6736 12:17:28.598580 RX Vref 0 -> 0, step: 1
6737 12:17:28.598662
6738 12:17:28.601919 RX Delay -410 -> 252, step: 16
6739 12:17:28.605040 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6740 12:17:28.608317 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6741 12:17:28.611672 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6742 12:17:28.618160 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6743 12:17:28.621415 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6744 12:17:28.624630 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6745 12:17:28.627984 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6746 12:17:28.634634 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6747 12:17:28.637922 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6748 12:17:28.641191 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6749 12:17:28.647942 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6750 12:17:28.650906 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6751 12:17:28.654160 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6752 12:17:28.657522 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6753 12:17:28.664064 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6754 12:17:28.667570 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6755 12:17:28.667664 ==
6756 12:17:28.670514 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 12:17:28.674112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 12:17:28.674199 ==
6759 12:17:28.677356 DQS Delay:
6760 12:17:28.677438 DQS0 = 27, DQS1 = 43
6761 12:17:28.680755 DQM Delay:
6762 12:17:28.680859 DQM0 = 6, DQM1 = 15
6763 12:17:28.680924 DQ Delay:
6764 12:17:28.683814 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6765 12:17:28.686927 DQ4 =0, DQ5 =24, DQ6 =16, DQ7 =0
6766 12:17:28.690826 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6767 12:17:28.694083 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6768 12:17:28.694166
6769 12:17:28.694231
6770 12:17:28.694290 ==
6771 12:17:28.697285 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 12:17:28.703775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 12:17:28.703889 ==
6774 12:17:28.703954
6775 12:17:28.704014
6776 12:17:28.704070 TX Vref Scan disable
6777 12:17:28.707199 == TX Byte 0 ==
6778 12:17:28.710497 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 12:17:28.713857 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 12:17:28.716981 == TX Byte 1 ==
6781 12:17:28.720313 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6782 12:17:28.723695 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6783 12:17:28.723778 ==
6784 12:17:28.726882 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 12:17:28.733387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 12:17:28.733471 ==
6787 12:17:28.733535
6788 12:17:28.733595
6789 12:17:28.736686 TX Vref Scan disable
6790 12:17:28.736789 == TX Byte 0 ==
6791 12:17:28.740113 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 12:17:28.746731 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 12:17:28.746814 == TX Byte 1 ==
6794 12:17:28.750054 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6795 12:17:28.756663 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6796 12:17:28.756747
6797 12:17:28.756841 [DATLAT]
6798 12:17:28.756902 Freq=400, CH1 RK0
6799 12:17:28.756961
6800 12:17:28.760036 DATLAT Default: 0xf
6801 12:17:28.760119 0, 0xFFFF, sum = 0
6802 12:17:28.763299 1, 0xFFFF, sum = 0
6803 12:17:28.763411 2, 0xFFFF, sum = 0
6804 12:17:28.766564 3, 0xFFFF, sum = 0
6805 12:17:28.770056 4, 0xFFFF, sum = 0
6806 12:17:28.770161 5, 0xFFFF, sum = 0
6807 12:17:28.773525 6, 0xFFFF, sum = 0
6808 12:17:28.773600 7, 0xFFFF, sum = 0
6809 12:17:28.776598 8, 0xFFFF, sum = 0
6810 12:17:28.776705 9, 0xFFFF, sum = 0
6811 12:17:28.779774 10, 0xFFFF, sum = 0
6812 12:17:28.779883 11, 0xFFFF, sum = 0
6813 12:17:28.783230 12, 0xFFFF, sum = 0
6814 12:17:28.783334 13, 0x0, sum = 1
6815 12:17:28.786451 14, 0x0, sum = 2
6816 12:17:28.786555 15, 0x0, sum = 3
6817 12:17:28.789765 16, 0x0, sum = 4
6818 12:17:28.789867 best_step = 14
6819 12:17:28.789964
6820 12:17:28.790063 ==
6821 12:17:28.792895 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 12:17:28.796176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 12:17:28.799553 ==
6824 12:17:28.799649 RX Vref Scan: 1
6825 12:17:28.799737
6826 12:17:28.802813 RX Vref 0 -> 0, step: 1
6827 12:17:28.802882
6828 12:17:28.806175 RX Delay -327 -> 252, step: 8
6829 12:17:28.806259
6830 12:17:28.809914 Set Vref, RX VrefLevel [Byte0]: 51
6831 12:17:28.812748 [Byte1]: 52
6832 12:17:28.812867
6833 12:17:28.816116 Final RX Vref Byte 0 = 51 to rank0
6834 12:17:28.819387 Final RX Vref Byte 1 = 52 to rank0
6835 12:17:28.822603 Final RX Vref Byte 0 = 51 to rank1
6836 12:17:28.826005 Final RX Vref Byte 1 = 52 to rank1==
6837 12:17:28.829315 Dram Type= 6, Freq= 0, CH_1, rank 0
6838 12:17:28.832709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 12:17:28.832855 ==
6840 12:17:28.836096 DQS Delay:
6841 12:17:28.836180 DQS0 = 32, DQS1 = 40
6842 12:17:28.838997 DQM Delay:
6843 12:17:28.839084 DQM0 = 12, DQM1 = 13
6844 12:17:28.842405 DQ Delay:
6845 12:17:28.842525 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
6846 12:17:28.845685 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6847 12:17:28.849000 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6848 12:17:28.852393 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6849 12:17:28.852467
6850 12:17:28.852530
6851 12:17:28.862347 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6852 12:17:28.865858 CH1 RK0: MR19=C0C, MR18=8FC9
6853 12:17:28.868996 CH1_RK0: MR19=0xC0C, MR18=0x8FC9, DQSOSC=384, MR23=63, INC=400, DEC=267
6854 12:17:28.872274 ==
6855 12:17:28.875531 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 12:17:28.878844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 12:17:28.878921 ==
6858 12:17:28.881963 [Gating] SW mode calibration
6859 12:17:28.888671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6860 12:17:28.892213 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6861 12:17:28.898663 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6862 12:17:28.901956 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6863 12:17:28.905208 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 12:17:28.912067 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6865 12:17:28.914945 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 12:17:28.918181 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 12:17:28.925157 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 12:17:28.928494 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 12:17:28.931323 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 12:17:28.935045 Total UI for P1: 0, mck2ui 16
6871 12:17:28.938160 best dqsien dly found for B0: ( 0, 14, 24)
6872 12:17:28.941517 Total UI for P1: 0, mck2ui 16
6873 12:17:28.944957 best dqsien dly found for B1: ( 0, 14, 24)
6874 12:17:28.948216 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6875 12:17:28.954917 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6876 12:17:28.955003
6877 12:17:28.958153 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6878 12:17:28.961496 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6879 12:17:28.964728 [Gating] SW calibration Done
6880 12:17:28.964839 ==
6881 12:17:28.968146 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 12:17:28.971341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 12:17:28.971427 ==
6884 12:17:28.974524 RX Vref Scan: 0
6885 12:17:28.974608
6886 12:17:28.974696 RX Vref 0 -> 0, step: 1
6887 12:17:28.974807
6888 12:17:28.978005 RX Delay -410 -> 252, step: 16
6889 12:17:28.981361 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6890 12:17:28.987924 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6891 12:17:28.990936 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6892 12:17:28.994388 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6893 12:17:28.997923 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6894 12:17:29.004412 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6895 12:17:29.007746 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6896 12:17:29.011016 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6897 12:17:29.014145 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6898 12:17:29.020672 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6899 12:17:29.024097 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6900 12:17:29.027503 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6901 12:17:29.034043 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6902 12:17:29.037438 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6903 12:17:29.040573 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6904 12:17:29.043934 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6905 12:17:29.047213 ==
6906 12:17:29.047298 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 12:17:29.053912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 12:17:29.053998 ==
6909 12:17:29.054082 DQS Delay:
6910 12:17:29.057205 DQS0 = 35, DQS1 = 43
6911 12:17:29.057290 DQM Delay:
6912 12:17:29.060034 DQM0 = 18, DQM1 = 20
6913 12:17:29.060119 DQ Delay:
6914 12:17:29.063337 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6915 12:17:29.067084 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6916 12:17:29.070388 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6917 12:17:29.073261 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6918 12:17:29.073337
6919 12:17:29.073437
6920 12:17:29.073496 ==
6921 12:17:29.076577 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 12:17:29.079886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 12:17:29.079968 ==
6924 12:17:29.080028
6925 12:17:29.080085
6926 12:17:29.083285 TX Vref Scan disable
6927 12:17:29.083366 == TX Byte 0 ==
6928 12:17:29.090184 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6929 12:17:29.093365 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6930 12:17:29.093448 == TX Byte 1 ==
6931 12:17:29.099797 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6932 12:17:29.103033 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6933 12:17:29.103115 ==
6934 12:17:29.106382 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 12:17:29.109891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 12:17:29.109974 ==
6937 12:17:29.110039
6938 12:17:29.110098
6939 12:17:29.112834 TX Vref Scan disable
6940 12:17:29.116410 == TX Byte 0 ==
6941 12:17:29.119632 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6942 12:17:29.123005 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6943 12:17:29.126334 == TX Byte 1 ==
6944 12:17:29.129650 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6945 12:17:29.133040 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6946 12:17:29.133122
6947 12:17:29.133186 [DATLAT]
6948 12:17:29.136156 Freq=400, CH1 RK1
6949 12:17:29.136238
6950 12:17:29.136302 DATLAT Default: 0xe
6951 12:17:29.139560 0, 0xFFFF, sum = 0
6952 12:17:29.139646 1, 0xFFFF, sum = 0
6953 12:17:29.142871 2, 0xFFFF, sum = 0
6954 12:17:29.142954 3, 0xFFFF, sum = 0
6955 12:17:29.146443 4, 0xFFFF, sum = 0
6956 12:17:29.149793 5, 0xFFFF, sum = 0
6957 12:17:29.149881 6, 0xFFFF, sum = 0
6958 12:17:29.153059 7, 0xFFFF, sum = 0
6959 12:17:29.153147 8, 0xFFFF, sum = 0
6960 12:17:29.156364 9, 0xFFFF, sum = 0
6961 12:17:29.156447 10, 0xFFFF, sum = 0
6962 12:17:29.159708 11, 0xFFFF, sum = 0
6963 12:17:29.159791 12, 0xFFFF, sum = 0
6964 12:17:29.163056 13, 0x0, sum = 1
6965 12:17:29.163138 14, 0x0, sum = 2
6966 12:17:29.166234 15, 0x0, sum = 3
6967 12:17:29.166331 16, 0x0, sum = 4
6968 12:17:29.169679 best_step = 14
6969 12:17:29.169774
6970 12:17:29.169868 ==
6971 12:17:29.172864 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 12:17:29.176210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 12:17:29.176295 ==
6974 12:17:29.176361 RX Vref Scan: 0
6975 12:17:29.179549
6976 12:17:29.179632 RX Vref 0 -> 0, step: 1
6977 12:17:29.179698
6978 12:17:29.182376 RX Delay -327 -> 252, step: 8
6979 12:17:29.190034 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6980 12:17:29.193358 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6981 12:17:29.196610 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6982 12:17:29.203012 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6983 12:17:29.206524 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6984 12:17:29.209630 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6985 12:17:29.213091 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6986 12:17:29.216124 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6987 12:17:29.223162 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6988 12:17:29.226463 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6989 12:17:29.229749 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6990 12:17:29.236389 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6991 12:17:29.239590 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6992 12:17:29.242822 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6993 12:17:29.246180 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6994 12:17:29.252542 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6995 12:17:29.252624 ==
6996 12:17:29.255927 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 12:17:29.259145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 12:17:29.259231 ==
6999 12:17:29.259297 DQS Delay:
7000 12:17:29.262534 DQS0 = 28, DQS1 = 36
7001 12:17:29.262616 DQM Delay:
7002 12:17:29.265951 DQM0 = 8, DQM1 = 10
7003 12:17:29.266033 DQ Delay:
7004 12:17:29.268755 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
7005 12:17:29.272584 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =4
7006 12:17:29.275966 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7007 12:17:29.279244 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7008 12:17:29.279326
7009 12:17:29.279390
7010 12:17:29.285899 [DQSOSCAuto] RK1, (LSB)MR18= 0xa44d, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
7011 12:17:29.289157 CH1 RK1: MR19=C0C, MR18=A44D
7012 12:17:29.295381 CH1_RK1: MR19=0xC0C, MR18=0xA44D, DQSOSC=389, MR23=63, INC=390, DEC=260
7013 12:17:29.298716 [RxdqsGatingPostProcess] freq 400
7014 12:17:29.305685 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7015 12:17:29.308692 best DQS0 dly(2T, 0.5T) = (0, 10)
7016 12:17:29.312170 best DQS1 dly(2T, 0.5T) = (0, 10)
7017 12:17:29.315239 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7018 12:17:29.318828 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7019 12:17:29.318911 best DQS0 dly(2T, 0.5T) = (0, 10)
7020 12:17:29.321969 best DQS1 dly(2T, 0.5T) = (0, 10)
7021 12:17:29.324990 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7022 12:17:29.328463 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7023 12:17:29.332097 Pre-setting of DQS Precalculation
7024 12:17:29.338699 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7025 12:17:29.345128 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7026 12:17:29.351647 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7027 12:17:29.351730
7028 12:17:29.351794
7029 12:17:29.354931 [Calibration Summary] 800 Mbps
7030 12:17:29.355012 CH 0, Rank 0
7031 12:17:29.358170 SW Impedance : PASS
7032 12:17:29.361534 DUTY Scan : NO K
7033 12:17:29.361615 ZQ Calibration : PASS
7034 12:17:29.364762 Jitter Meter : NO K
7035 12:17:29.368114 CBT Training : PASS
7036 12:17:29.368196 Write leveling : PASS
7037 12:17:29.371011 RX DQS gating : PASS
7038 12:17:29.374488 RX DQ/DQS(RDDQC) : PASS
7039 12:17:29.374570 TX DQ/DQS : PASS
7040 12:17:29.377849 RX DATLAT : PASS
7041 12:17:29.381241 RX DQ/DQS(Engine): PASS
7042 12:17:29.381326 TX OE : NO K
7043 12:17:29.384619 All Pass.
7044 12:17:29.384693
7045 12:17:29.384758 CH 0, Rank 1
7046 12:17:29.387850 SW Impedance : PASS
7047 12:17:29.387922 DUTY Scan : NO K
7048 12:17:29.391110 ZQ Calibration : PASS
7049 12:17:29.394414 Jitter Meter : NO K
7050 12:17:29.394489 CBT Training : PASS
7051 12:17:29.397877 Write leveling : NO K
7052 12:17:29.401015 RX DQS gating : PASS
7053 12:17:29.401099 RX DQ/DQS(RDDQC) : PASS
7054 12:17:29.404354 TX DQ/DQS : PASS
7055 12:17:29.407713 RX DATLAT : PASS
7056 12:17:29.407797 RX DQ/DQS(Engine): PASS
7057 12:17:29.411088 TX OE : NO K
7058 12:17:29.411172 All Pass.
7059 12:17:29.411237
7060 12:17:29.414153 CH 1, Rank 0
7061 12:17:29.414236 SW Impedance : PASS
7062 12:17:29.417685 DUTY Scan : NO K
7063 12:17:29.420881 ZQ Calibration : PASS
7064 12:17:29.420963 Jitter Meter : NO K
7065 12:17:29.424064 CBT Training : PASS
7066 12:17:29.424149 Write leveling : PASS
7067 12:17:29.427146 RX DQS gating : PASS
7068 12:17:29.430717 RX DQ/DQS(RDDQC) : PASS
7069 12:17:29.430800 TX DQ/DQS : PASS
7070 12:17:29.433796 RX DATLAT : PASS
7071 12:17:29.437375 RX DQ/DQS(Engine): PASS
7072 12:17:29.437460 TX OE : NO K
7073 12:17:29.440218 All Pass.
7074 12:17:29.440302
7075 12:17:29.440368 CH 1, Rank 1
7076 12:17:29.443933 SW Impedance : PASS
7077 12:17:29.444017 DUTY Scan : NO K
7078 12:17:29.447225 ZQ Calibration : PASS
7079 12:17:29.450665 Jitter Meter : NO K
7080 12:17:29.450740 CBT Training : PASS
7081 12:17:29.453510 Write leveling : NO K
7082 12:17:29.457069 RX DQS gating : PASS
7083 12:17:29.457141 RX DQ/DQS(RDDQC) : PASS
7084 12:17:29.460507 TX DQ/DQS : PASS
7085 12:17:29.463892 RX DATLAT : PASS
7086 12:17:29.463965 RX DQ/DQS(Engine): PASS
7087 12:17:29.466703 TX OE : NO K
7088 12:17:29.466787 All Pass.
7089 12:17:29.466854
7090 12:17:29.470436 DramC Write-DBI off
7091 12:17:29.473826 PER_BANK_REFRESH: Hybrid Mode
7092 12:17:29.473910 TX_TRACKING: ON
7093 12:17:29.483370 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7094 12:17:29.486656 [FAST_K] Save calibration result to emmc
7095 12:17:29.490040 dramc_set_vcore_voltage set vcore to 725000
7096 12:17:29.493256 Read voltage for 1600, 0
7097 12:17:29.493359 Vio18 = 0
7098 12:17:29.493426 Vcore = 725000
7099 12:17:29.496556 Vdram = 0
7100 12:17:29.496665 Vddq = 0
7101 12:17:29.496759 Vmddr = 0
7102 12:17:29.503140 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7103 12:17:29.506416 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7104 12:17:29.509859 MEM_TYPE=3, freq_sel=13
7105 12:17:29.513233 sv_algorithm_assistance_LP4_3733
7106 12:17:29.516139 ============ PULL DRAM RESETB DOWN ============
7107 12:17:29.522881 ========== PULL DRAM RESETB DOWN end =========
7108 12:17:29.526305 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7109 12:17:29.529487 ===================================
7110 12:17:29.533013 LPDDR4 DRAM CONFIGURATION
7111 12:17:29.536003 ===================================
7112 12:17:29.536088 EX_ROW_EN[0] = 0x0
7113 12:17:29.539266 EX_ROW_EN[1] = 0x0
7114 12:17:29.539351 LP4Y_EN = 0x0
7115 12:17:29.542859 WORK_FSP = 0x1
7116 12:17:29.542943 WL = 0x5
7117 12:17:29.546191 RL = 0x5
7118 12:17:29.546274 BL = 0x2
7119 12:17:29.549411 RPST = 0x0
7120 12:17:29.552610 RD_PRE = 0x0
7121 12:17:29.552720 WR_PRE = 0x1
7122 12:17:29.555869 WR_PST = 0x1
7123 12:17:29.555954 DBI_WR = 0x0
7124 12:17:29.559096 DBI_RD = 0x0
7125 12:17:29.559180 OTF = 0x1
7126 12:17:29.562208 ===================================
7127 12:17:29.565500 ===================================
7128 12:17:29.569245 ANA top config
7129 12:17:29.572077 ===================================
7130 12:17:29.572160 DLL_ASYNC_EN = 0
7131 12:17:29.575300 ALL_SLAVE_EN = 0
7132 12:17:29.578602 NEW_RANK_MODE = 1
7133 12:17:29.581911 DLL_IDLE_MODE = 1
7134 12:17:29.585220 LP45_APHY_COMB_EN = 1
7135 12:17:29.585304 TX_ODT_DIS = 0
7136 12:17:29.588489 NEW_8X_MODE = 1
7137 12:17:29.591830 ===================================
7138 12:17:29.595183 ===================================
7139 12:17:29.598502 data_rate = 3200
7140 12:17:29.601866 CKR = 1
7141 12:17:29.605148 DQ_P2S_RATIO = 8
7142 12:17:29.608486 ===================================
7143 12:17:29.608580 CA_P2S_RATIO = 8
7144 12:17:29.611812 DQ_CA_OPEN = 0
7145 12:17:29.615084 DQ_SEMI_OPEN = 0
7146 12:17:29.618387 CA_SEMI_OPEN = 0
7147 12:17:29.621264 CA_FULL_RATE = 0
7148 12:17:29.624659 DQ_CKDIV4_EN = 0
7149 12:17:29.628363 CA_CKDIV4_EN = 0
7150 12:17:29.628447 CA_PREDIV_EN = 0
7151 12:17:29.631280 PH8_DLY = 12
7152 12:17:29.634788 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7153 12:17:29.637895 DQ_AAMCK_DIV = 4
7154 12:17:29.641381 CA_AAMCK_DIV = 4
7155 12:17:29.644426 CA_ADMCK_DIV = 4
7156 12:17:29.644532 DQ_TRACK_CA_EN = 0
7157 12:17:29.647664 CA_PICK = 1600
7158 12:17:29.650964 CA_MCKIO = 1600
7159 12:17:29.654195 MCKIO_SEMI = 0
7160 12:17:29.657936 PLL_FREQ = 3068
7161 12:17:29.660754 DQ_UI_PI_RATIO = 32
7162 12:17:29.664357 CA_UI_PI_RATIO = 0
7163 12:17:29.667580 ===================================
7164 12:17:29.670965 ===================================
7165 12:17:29.671049 memory_type:LPDDR4
7166 12:17:29.674355 GP_NUM : 10
7167 12:17:29.677733 SRAM_EN : 1
7168 12:17:29.677817 MD32_EN : 0
7169 12:17:29.681035 ===================================
7170 12:17:29.683912 [ANA_INIT] >>>>>>>>>>>>>>
7171 12:17:29.687223 <<<<<< [CONFIGURE PHASE]: ANA_TX
7172 12:17:29.690745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7173 12:17:29.694021 ===================================
7174 12:17:29.697265 data_rate = 3200,PCW = 0X7600
7175 12:17:29.700656 ===================================
7176 12:17:29.703856 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7177 12:17:29.707015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7178 12:17:29.713745 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7179 12:17:29.717190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7180 12:17:29.723718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7181 12:17:29.727143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7182 12:17:29.727230 [ANA_INIT] flow start
7183 12:17:29.730355 [ANA_INIT] PLL >>>>>>>>
7184 12:17:29.733673 [ANA_INIT] PLL <<<<<<<<
7185 12:17:29.733757 [ANA_INIT] MIDPI >>>>>>>>
7186 12:17:29.737129 [ANA_INIT] MIDPI <<<<<<<<
7187 12:17:29.740192 [ANA_INIT] DLL >>>>>>>>
7188 12:17:29.740276 [ANA_INIT] DLL <<<<<<<<
7189 12:17:29.743358 [ANA_INIT] flow end
7190 12:17:29.747026 ============ LP4 DIFF to SE enter ============
7191 12:17:29.750032 ============ LP4 DIFF to SE exit ============
7192 12:17:29.753594 [ANA_INIT] <<<<<<<<<<<<<
7193 12:17:29.756661 [Flow] Enable top DCM control >>>>>
7194 12:17:29.759886 [Flow] Enable top DCM control <<<<<
7195 12:17:29.763305 Enable DLL master slave shuffle
7196 12:17:29.770084 ==============================================================
7197 12:17:29.770172 Gating Mode config
7198 12:17:29.776394 ==============================================================
7199 12:17:29.779718 Config description:
7200 12:17:29.786346 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7201 12:17:29.793038 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7202 12:17:29.799614 SELPH_MODE 0: By rank 1: By Phase
7203 12:17:29.806173 ==============================================================
7204 12:17:29.806263 GAT_TRACK_EN = 1
7205 12:17:29.809882 RX_GATING_MODE = 2
7206 12:17:29.812996 RX_GATING_TRACK_MODE = 2
7207 12:17:29.816337 SELPH_MODE = 1
7208 12:17:29.819605 PICG_EARLY_EN = 1
7209 12:17:29.823030 VALID_LAT_VALUE = 1
7210 12:17:29.829299 ==============================================================
7211 12:17:29.832625 Enter into Gating configuration >>>>
7212 12:17:29.836042 Exit from Gating configuration <<<<
7213 12:17:29.839308 Enter into DVFS_PRE_config >>>>>
7214 12:17:29.849256 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7215 12:17:29.852695 Exit from DVFS_PRE_config <<<<<
7216 12:17:29.856016 Enter into PICG configuration >>>>
7217 12:17:29.859296 Exit from PICG configuration <<<<
7218 12:17:29.862378 [RX_INPUT] configuration >>>>>
7219 12:17:29.865966 [RX_INPUT] configuration <<<<<
7220 12:17:29.869172 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7221 12:17:29.875785 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7222 12:17:29.882125 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7223 12:17:29.888698 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7224 12:17:29.892074 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7225 12:17:29.898650 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7226 12:17:29.902147 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7227 12:17:29.908301 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7228 12:17:29.911914 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7229 12:17:29.915208 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7230 12:17:29.918602 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7231 12:17:29.925233 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7232 12:17:29.928564 ===================================
7233 12:17:29.931889 LPDDR4 DRAM CONFIGURATION
7234 12:17:29.935125 ===================================
7235 12:17:29.935210 EX_ROW_EN[0] = 0x0
7236 12:17:29.938336 EX_ROW_EN[1] = 0x0
7237 12:17:29.938420 LP4Y_EN = 0x0
7238 12:17:29.941594 WORK_FSP = 0x1
7239 12:17:29.941703 WL = 0x5
7240 12:17:29.944789 RL = 0x5
7241 12:17:29.944886 BL = 0x2
7242 12:17:29.948179 RPST = 0x0
7243 12:17:29.948270 RD_PRE = 0x0
7244 12:17:29.951375 WR_PRE = 0x1
7245 12:17:29.951487 WR_PST = 0x1
7246 12:17:29.954722 DBI_WR = 0x0
7247 12:17:29.954804 DBI_RD = 0x0
7248 12:17:29.958070 OTF = 0x1
7249 12:17:29.961529 ===================================
7250 12:17:29.964992 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7251 12:17:29.968067 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7252 12:17:29.974650 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7253 12:17:29.978093 ===================================
7254 12:17:29.978200 LPDDR4 DRAM CONFIGURATION
7255 12:17:29.981010 ===================================
7256 12:17:29.984509 EX_ROW_EN[0] = 0x10
7257 12:17:29.987589 EX_ROW_EN[1] = 0x0
7258 12:17:29.987662 LP4Y_EN = 0x0
7259 12:17:29.990895 WORK_FSP = 0x1
7260 12:17:29.990967 WL = 0x5
7261 12:17:29.994202 RL = 0x5
7262 12:17:29.994272 BL = 0x2
7263 12:17:29.997478 RPST = 0x0
7264 12:17:29.997571 RD_PRE = 0x0
7265 12:17:30.000974 WR_PRE = 0x1
7266 12:17:30.001056 WR_PST = 0x1
7267 12:17:30.004277 DBI_WR = 0x0
7268 12:17:30.004385 DBI_RD = 0x0
7269 12:17:30.007536 OTF = 0x1
7270 12:17:30.010846 ===================================
7271 12:17:30.017334 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7272 12:17:30.017420 ==
7273 12:17:30.020632 Dram Type= 6, Freq= 0, CH_0, rank 0
7274 12:17:30.023960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7275 12:17:30.024044 ==
7276 12:17:30.027318 [Duty_Offset_Calibration]
7277 12:17:30.027401 B0:2 B1:0 CA:1
7278 12:17:30.030642
7279 12:17:30.033899 [DutyScan_Calibration_Flow] k_type=0
7280 12:17:30.041292
7281 12:17:30.041376 ==CLK 0==
7282 12:17:30.044197 Final CLK duty delay cell = -4
7283 12:17:30.047975 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7284 12:17:30.050878 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7285 12:17:30.054192 [-4] AVG Duty = 4937%(X100)
7286 12:17:30.054278
7287 12:17:30.057924 CH0 CLK Duty spec in!! Max-Min= 187%
7288 12:17:30.061131 [DutyScan_Calibration_Flow] ====Done====
7289 12:17:30.061207
7290 12:17:30.064347 [DutyScan_Calibration_Flow] k_type=1
7291 12:17:30.080723
7292 12:17:30.080846 ==DQS 0 ==
7293 12:17:30.083914 Final DQS duty delay cell = 0
7294 12:17:30.087345 [0] MAX Duty = 5249%(X100), DQS PI = 32
7295 12:17:30.090454 [0] MIN Duty = 4938%(X100), DQS PI = 62
7296 12:17:30.094015 [0] AVG Duty = 5093%(X100)
7297 12:17:30.094087
7298 12:17:30.094149 ==DQS 1 ==
7299 12:17:30.097259 Final DQS duty delay cell = -4
7300 12:17:30.100176 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7301 12:17:30.103481 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7302 12:17:30.106766 [-4] AVG Duty = 5000%(X100)
7303 12:17:30.106849
7304 12:17:30.110157 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7305 12:17:30.110247
7306 12:17:30.113431 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7307 12:17:30.116696 [DutyScan_Calibration_Flow] ====Done====
7308 12:17:30.116824
7309 12:17:30.119842 [DutyScan_Calibration_Flow] k_type=3
7310 12:17:30.137895
7311 12:17:30.138008 ==DQM 0 ==
7312 12:17:30.141700 Final DQM duty delay cell = 0
7313 12:17:30.144562 [0] MAX Duty = 5093%(X100), DQS PI = 24
7314 12:17:30.147929 [0] MIN Duty = 4813%(X100), DQS PI = 50
7315 12:17:30.151121 [0] AVG Duty = 4953%(X100)
7316 12:17:30.151196
7317 12:17:30.151276 ==DQM 1 ==
7318 12:17:30.154554 Final DQM duty delay cell = 0
7319 12:17:30.157867 [0] MAX Duty = 5249%(X100), DQS PI = 44
7320 12:17:30.161529 [0] MIN Duty = 5031%(X100), DQS PI = 20
7321 12:17:30.164438 [0] AVG Duty = 5140%(X100)
7322 12:17:30.164511
7323 12:17:30.167726 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7324 12:17:30.167800
7325 12:17:30.171371 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7326 12:17:30.174616 [DutyScan_Calibration_Flow] ====Done====
7327 12:17:30.174701
7328 12:17:30.177825 [DutyScan_Calibration_Flow] k_type=2
7329 12:17:30.196165
7330 12:17:30.196264 ==DQ 0 ==
7331 12:17:30.199642 Final DQ duty delay cell = 0
7332 12:17:30.202813 [0] MAX Duty = 5124%(X100), DQS PI = 34
7333 12:17:30.206069 [0] MIN Duty = 5000%(X100), DQS PI = 16
7334 12:17:30.206152 [0] AVG Duty = 5062%(X100)
7335 12:17:30.209398
7336 12:17:30.209481 ==DQ 1 ==
7337 12:17:30.212733 Final DQ duty delay cell = 4
7338 12:17:30.216064 [4] MAX Duty = 5125%(X100), DQS PI = 2
7339 12:17:30.219277 [4] MIN Duty = 5062%(X100), DQS PI = 0
7340 12:17:30.219390 [4] AVG Duty = 5093%(X100)
7341 12:17:30.222531
7342 12:17:30.225903 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7343 12:17:30.226019
7344 12:17:30.229184 CH0 DQ 1 Duty spec in!! Max-Min= 63%
7345 12:17:30.232524 [DutyScan_Calibration_Flow] ====Done====
7346 12:17:30.232634 ==
7347 12:17:30.235861 Dram Type= 6, Freq= 0, CH_1, rank 0
7348 12:17:30.239119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7349 12:17:30.239230 ==
7350 12:17:30.242496 [Duty_Offset_Calibration]
7351 12:17:30.242579 B0:0 B1:-1 CA:2
7352 12:17:30.242646
7353 12:17:30.245882 [DutyScan_Calibration_Flow] k_type=0
7354 12:17:30.256146
7355 12:17:30.256257 ==CLK 0==
7356 12:17:30.259522 Final CLK duty delay cell = 0
7357 12:17:30.262846 [0] MAX Duty = 5156%(X100), DQS PI = 10
7358 12:17:30.266108 [0] MIN Duty = 4938%(X100), DQS PI = 44
7359 12:17:30.269368 [0] AVG Duty = 5047%(X100)
7360 12:17:30.269450
7361 12:17:30.272722 CH1 CLK Duty spec in!! Max-Min= 218%
7362 12:17:30.276185 [DutyScan_Calibration_Flow] ====Done====
7363 12:17:30.276292
7364 12:17:30.279537 [DutyScan_Calibration_Flow] k_type=1
7365 12:17:30.296057
7366 12:17:30.296154 ==DQS 0 ==
7367 12:17:30.299169 Final DQS duty delay cell = 0
7368 12:17:30.302680 [0] MAX Duty = 5124%(X100), DQS PI = 24
7369 12:17:30.305883 [0] MIN Duty = 4969%(X100), DQS PI = 0
7370 12:17:30.308890 [0] AVG Duty = 5046%(X100)
7371 12:17:30.308997
7372 12:17:30.309096 ==DQS 1 ==
7373 12:17:30.312328 Final DQS duty delay cell = 0
7374 12:17:30.315733 [0] MAX Duty = 5187%(X100), DQS PI = 0
7375 12:17:30.319059 [0] MIN Duty = 4844%(X100), DQS PI = 34
7376 12:17:30.322359 [0] AVG Duty = 5015%(X100)
7377 12:17:30.322441
7378 12:17:30.325749 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7379 12:17:30.325831
7380 12:17:30.329014 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7381 12:17:30.332266 [DutyScan_Calibration_Flow] ====Done====
7382 12:17:30.332347
7383 12:17:30.335487 [DutyScan_Calibration_Flow] k_type=3
7384 12:17:30.353746
7385 12:17:30.353839 ==DQM 0 ==
7386 12:17:30.356954 Final DQM duty delay cell = 4
7387 12:17:30.360337 [4] MAX Duty = 5125%(X100), DQS PI = 8
7388 12:17:30.363516 [4] MIN Duty = 5000%(X100), DQS PI = 32
7389 12:17:30.363629 [4] AVG Duty = 5062%(X100)
7390 12:17:30.366728
7391 12:17:30.366809 ==DQM 1 ==
7392 12:17:30.370040 Final DQM duty delay cell = 0
7393 12:17:30.373416 [0] MAX Duty = 5281%(X100), DQS PI = 58
7394 12:17:30.376873 [0] MIN Duty = 4876%(X100), DQS PI = 34
7395 12:17:30.380030 [0] AVG Duty = 5078%(X100)
7396 12:17:30.380112
7397 12:17:30.383270 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7398 12:17:30.383352
7399 12:17:30.386679 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7400 12:17:30.389668 [DutyScan_Calibration_Flow] ====Done====
7401 12:17:30.389750
7402 12:17:30.393253 [DutyScan_Calibration_Flow] k_type=2
7403 12:17:30.410178
7404 12:17:30.410274 ==DQ 0 ==
7405 12:17:30.413802 Final DQ duty delay cell = 0
7406 12:17:30.416745 [0] MAX Duty = 5093%(X100), DQS PI = 20
7407 12:17:30.420248 [0] MIN Duty = 4969%(X100), DQS PI = 48
7408 12:17:30.423491 [0] AVG Duty = 5031%(X100)
7409 12:17:30.423619
7410 12:17:30.423685 ==DQ 1 ==
7411 12:17:30.426830 Final DQ duty delay cell = 0
7412 12:17:30.430269 [0] MAX Duty = 5062%(X100), DQS PI = 2
7413 12:17:30.433402 [0] MIN Duty = 4844%(X100), DQS PI = 32
7414 12:17:30.433516 [0] AVG Duty = 4953%(X100)
7415 12:17:30.436745
7416 12:17:30.440167 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7417 12:17:30.440254
7418 12:17:30.443520 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7419 12:17:30.446455 [DutyScan_Calibration_Flow] ====Done====
7420 12:17:30.450098 nWR fixed to 30
7421 12:17:30.450176 [ModeRegInit_LP4] CH0 RK0
7422 12:17:30.452937 [ModeRegInit_LP4] CH0 RK1
7423 12:17:30.456309 [ModeRegInit_LP4] CH1 RK0
7424 12:17:30.459543 [ModeRegInit_LP4] CH1 RK1
7425 12:17:30.459641 match AC timing 5
7426 12:17:30.466215 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7427 12:17:30.469556 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7428 12:17:30.472727 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7429 12:17:30.479523 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7430 12:17:30.482898 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7431 12:17:30.482986 [MiockJmeterHQA]
7432 12:17:30.483053
7433 12:17:30.485945 [DramcMiockJmeter] u1RxGatingPI = 0
7434 12:17:30.489233 0 : 4363, 4137
7435 12:17:30.489319 4 : 4257, 4029
7436 12:17:30.492561 8 : 4363, 4138
7437 12:17:30.492648 12 : 4253, 4027
7438 12:17:30.495898 16 : 4252, 4027
7439 12:17:30.495988 20 : 4363, 4138
7440 12:17:30.496056 24 : 4363, 4137
7441 12:17:30.499383 28 : 4252, 4027
7442 12:17:30.499494 32 : 4253, 4026
7443 12:17:30.502794 36 : 4253, 4029
7444 12:17:30.502880 40 : 4363, 4137
7445 12:17:30.506040 44 : 4250, 4026
7446 12:17:30.506123 48 : 4360, 4138
7447 12:17:30.509193 52 : 4250, 4027
7448 12:17:30.509276 56 : 4250, 4027
7449 12:17:30.509343 60 : 4250, 4027
7450 12:17:30.512279 64 : 4250, 4026
7451 12:17:30.512365 68 : 4360, 4138
7452 12:17:30.515919 72 : 4250, 4027
7453 12:17:30.515999 76 : 4361, 4137
7454 12:17:30.519048 80 : 4250, 4027
7455 12:17:30.519120 84 : 4250, 4026
7456 12:17:30.522571 88 : 4250, 3781
7457 12:17:30.522643 92 : 4361, 0
7458 12:17:30.522705 96 : 4250, 0
7459 12:17:30.525699 100 : 4250, 0
7460 12:17:30.525768 104 : 4252, 0
7461 12:17:30.525829 108 : 4250, 0
7462 12:17:30.529103 112 : 4361, 0
7463 12:17:30.529187 116 : 4361, 0
7464 12:17:30.532399 120 : 4250, 0
7465 12:17:30.532483 124 : 4250, 0
7466 12:17:30.532548 128 : 4250, 0
7467 12:17:30.535650 132 : 4250, 0
7468 12:17:30.535733 136 : 4250, 0
7469 12:17:30.538949 140 : 4250, 0
7470 12:17:30.539034 144 : 4250, 0
7471 12:17:30.539100 148 : 4250, 0
7472 12:17:30.542321 152 : 4250, 0
7473 12:17:30.542406 156 : 4252, 0
7474 12:17:30.542473 160 : 4250, 0
7475 12:17:30.545649 164 : 4360, 0
7476 12:17:30.545733 168 : 4361, 0
7477 12:17:30.548997 172 : 4250, 0
7478 12:17:30.549081 176 : 4250, 0
7479 12:17:30.549147 180 : 4250, 0
7480 12:17:30.552378 184 : 4250, 0
7481 12:17:30.552461 188 : 4250, 0
7482 12:17:30.555679 192 : 4250, 0
7483 12:17:30.555762 196 : 4250, 0
7484 12:17:30.555828 200 : 4361, 2
7485 12:17:30.559059 204 : 4360, 2578
7486 12:17:30.559143 208 : 4253, 4029
7487 12:17:30.561985 212 : 4250, 4027
7488 12:17:30.562068 216 : 4252, 4030
7489 12:17:30.565284 220 : 4250, 4027
7490 12:17:30.565368 224 : 4250, 4027
7491 12:17:30.569075 228 : 4250, 4027
7492 12:17:30.569158 232 : 4250, 4026
7493 12:17:30.572054 236 : 4250, 4027
7494 12:17:30.572137 240 : 4360, 4137
7495 12:17:30.575281 244 : 4361, 4137
7496 12:17:30.575365 248 : 4248, 4024
7497 12:17:30.578935 252 : 4361, 4137
7498 12:17:30.579018 256 : 4360, 4138
7499 12:17:30.579084 260 : 4250, 4026
7500 12:17:30.582296 264 : 4250, 4027
7501 12:17:30.582380 268 : 4250, 4026
7502 12:17:30.585625 272 : 4250, 4027
7503 12:17:30.585709 276 : 4250, 4027
7504 12:17:30.588798 280 : 4250, 4027
7505 12:17:30.588882 284 : 4250, 4026
7506 12:17:30.592104 288 : 4250, 4027
7507 12:17:30.592189 292 : 4360, 4138
7508 12:17:30.595002 296 : 4361, 4137
7509 12:17:30.595086 300 : 4248, 4024
7510 12:17:30.598658 304 : 4361, 4137
7511 12:17:30.598742 308 : 4360, 4138
7512 12:17:30.601804 312 : 4250, 3983
7513 12:17:30.601888 316 : 4250, 2229
7514 12:17:30.601955 320 : 4250, 6
7515 12:17:30.602015
7516 12:17:30.605009 MIOCK jitter meter ch=0
7517 12:17:30.605092
7518 12:17:30.608235 1T = (320-92) = 228 dly cells
7519 12:17:30.615143 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7520 12:17:30.615230 ==
7521 12:17:30.618349 Dram Type= 6, Freq= 0, CH_0, rank 0
7522 12:17:30.621352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7523 12:17:30.621438 ==
7524 12:17:30.628117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7525 12:17:30.631567 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7526 12:17:30.634917 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7527 12:17:30.641403 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7528 12:17:30.650291 [CA 0] Center 42 (12~73) winsize 62
7529 12:17:30.654074 [CA 1] Center 42 (12~72) winsize 61
7530 12:17:30.657378 [CA 2] Center 37 (7~67) winsize 61
7531 12:17:30.660381 [CA 3] Center 37 (7~67) winsize 61
7532 12:17:30.663668 [CA 4] Center 36 (6~66) winsize 61
7533 12:17:30.666972 [CA 5] Center 35 (5~65) winsize 61
7534 12:17:30.667056
7535 12:17:30.670251 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7536 12:17:30.670337
7537 12:17:30.677001 [CATrainingPosCal] consider 1 rank data
7538 12:17:30.677087 u2DelayCellTimex100 = 285/100 ps
7539 12:17:30.683318 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7540 12:17:30.686633 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7541 12:17:30.689937 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7542 12:17:30.693318 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7543 12:17:30.696606 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7544 12:17:30.700006 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7545 12:17:30.700091
7546 12:17:30.703280 CA PerBit enable=1, Macro0, CA PI delay=35
7547 12:17:30.703368
7548 12:17:30.706517 [CBTSetCACLKResult] CA Dly = 35
7549 12:17:30.709899 CS Dly: 10 (0~41)
7550 12:17:30.713146 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7551 12:17:30.716371 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7552 12:17:30.716457 ==
7553 12:17:30.719688 Dram Type= 6, Freq= 0, CH_0, rank 1
7554 12:17:30.726316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 12:17:30.726411 ==
7556 12:17:30.729391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7557 12:17:30.736246 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7558 12:17:30.739347 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7559 12:17:30.745836 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7560 12:17:30.753992 [CA 0] Center 43 (13~73) winsize 61
7561 12:17:30.757330 [CA 1] Center 43 (13~73) winsize 61
7562 12:17:30.760597 [CA 2] Center 38 (9~68) winsize 60
7563 12:17:30.763807 [CA 3] Center 38 (8~68) winsize 61
7564 12:17:30.767168 [CA 4] Center 37 (7~67) winsize 61
7565 12:17:30.770049 [CA 5] Center 36 (6~66) winsize 61
7566 12:17:30.770138
7567 12:17:30.773822 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7568 12:17:30.773901
7569 12:17:30.776638 [CATrainingPosCal] consider 2 rank data
7570 12:17:30.780012 u2DelayCellTimex100 = 285/100 ps
7571 12:17:30.787031 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7572 12:17:30.789909 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7573 12:17:30.793342 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7574 12:17:30.796965 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7575 12:17:30.800046 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7576 12:17:30.803416 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7577 12:17:30.803505
7578 12:17:30.806670 CA PerBit enable=1, Macro0, CA PI delay=35
7579 12:17:30.806746
7580 12:17:30.809837 [CBTSetCACLKResult] CA Dly = 35
7581 12:17:30.813140 CS Dly: 11 (0~43)
7582 12:17:30.816392 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7583 12:17:30.819649 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7584 12:17:30.819755
7585 12:17:30.823401 ----->DramcWriteLeveling(PI) begin...
7586 12:17:30.823503 ==
7587 12:17:30.826817 Dram Type= 6, Freq= 0, CH_0, rank 0
7588 12:17:30.833166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 12:17:30.833243 ==
7590 12:17:30.836552 Write leveling (Byte 0): 37 => 37
7591 12:17:30.839907 Write leveling (Byte 1): 31 => 31
7592 12:17:30.840017 DramcWriteLeveling(PI) end<-----
7593 12:17:30.840112
7594 12:17:30.843247 ==
7595 12:17:30.846465 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 12:17:30.849773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 12:17:30.849859 ==
7598 12:17:30.853232 [Gating] SW mode calibration
7599 12:17:30.859543 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7600 12:17:30.862795 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7601 12:17:30.869861 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 12:17:30.872707 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 12:17:30.876045 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7604 12:17:30.882794 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7605 12:17:30.886068 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7606 12:17:30.889180 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (1 0) (1 1)
7607 12:17:30.895919 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 12:17:30.899272 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 12:17:30.902426 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 12:17:30.909036 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 12:17:30.912422 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7612 12:17:30.916053 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7613 12:17:30.922612 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
7614 12:17:30.925913 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7615 12:17:30.929279 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 12:17:30.935593 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 12:17:30.938852 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 12:17:30.942244 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 12:17:30.948746 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7620 12:17:30.952306 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7621 12:17:30.955402 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7622 12:17:30.962368 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7623 12:17:30.965353 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 12:17:30.968663 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 12:17:30.975408 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 12:17:30.978758 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 12:17:30.982143 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 12:17:30.988445 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7629 12:17:30.991625 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7630 12:17:30.994891 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7631 12:17:31.001478 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7632 12:17:31.004627 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 12:17:31.007879 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 12:17:31.014538 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 12:17:31.018239 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 12:17:31.021427 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 12:17:31.027844 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 12:17:31.031212 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 12:17:31.034381 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 12:17:31.041092 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 12:17:31.044464 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 12:17:31.047769 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 12:17:31.054431 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 12:17:31.057882 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7645 12:17:31.061045 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7646 12:17:31.064436 Total UI for P1: 0, mck2ui 16
7647 12:17:31.067551 best dqsien dly found for B0: ( 1, 9, 12)
7648 12:17:31.074453 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7649 12:17:31.077324 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 12:17:31.080565 Total UI for P1: 0, mck2ui 16
7651 12:17:31.083915 best dqsien dly found for B1: ( 1, 9, 18)
7652 12:17:31.087195 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7653 12:17:31.090491 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7654 12:17:31.090575
7655 12:17:31.093833 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7656 12:17:31.097075 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7657 12:17:31.100341 [Gating] SW calibration Done
7658 12:17:31.100425 ==
7659 12:17:31.104026 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 12:17:31.110514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 12:17:31.110598 ==
7662 12:17:31.110665 RX Vref Scan: 0
7663 12:17:31.110727
7664 12:17:31.113912 RX Vref 0 -> 0, step: 1
7665 12:17:31.113996
7666 12:17:31.116741 RX Delay 0 -> 252, step: 8
7667 12:17:31.120472 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7668 12:17:31.123568 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7669 12:17:31.127085 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7670 12:17:31.130224 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7671 12:17:31.136759 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7672 12:17:31.140084 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7673 12:17:31.143365 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7674 12:17:31.146268 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7675 12:17:31.149614 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7676 12:17:31.156500 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7677 12:17:31.159551 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7678 12:17:31.163013 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7679 12:17:31.166070 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7680 12:17:31.173005 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7681 12:17:31.176042 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7682 12:17:31.179457 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7683 12:17:31.179541 ==
7684 12:17:31.182576 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 12:17:31.185877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 12:17:31.185961 ==
7687 12:17:31.189286 DQS Delay:
7688 12:17:31.189370 DQS0 = 0, DQS1 = 0
7689 12:17:31.192575 DQM Delay:
7690 12:17:31.192658 DQM0 = 138, DQM1 = 127
7691 12:17:31.192723 DQ Delay:
7692 12:17:31.195828 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7693 12:17:31.202355 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7694 12:17:31.205594 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7695 12:17:31.208970 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7696 12:17:31.209066
7697 12:17:31.209162
7698 12:17:31.209223 ==
7699 12:17:31.212219 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 12:17:31.215426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 12:17:31.215509 ==
7702 12:17:31.215580
7703 12:17:31.215672
7704 12:17:31.218879 TX Vref Scan disable
7705 12:17:31.222245 == TX Byte 0 ==
7706 12:17:31.225414 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7707 12:17:31.228587 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7708 12:17:31.231947 == TX Byte 1 ==
7709 12:17:31.235431 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7710 12:17:31.238769 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7711 12:17:31.238853 ==
7712 12:17:31.242020 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 12:17:31.248309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 12:17:31.248417 ==
7715 12:17:31.260433
7716 12:17:31.263729 TX Vref early break, caculate TX vref
7717 12:17:31.266956 TX Vref=16, minBit 0, minWin=23, winSum=379
7718 12:17:31.270236 TX Vref=18, minBit 6, minWin=23, winSum=387
7719 12:17:31.273848 TX Vref=20, minBit 0, minWin=24, winSum=397
7720 12:17:31.276960 TX Vref=22, minBit 0, minWin=25, winSum=409
7721 12:17:31.280355 TX Vref=24, minBit 4, minWin=25, winSum=420
7722 12:17:31.287089 TX Vref=26, minBit 0, minWin=26, winSum=430
7723 12:17:31.290225 TX Vref=28, minBit 0, minWin=25, winSum=429
7724 12:17:31.293117 TX Vref=30, minBit 0, minWin=25, winSum=426
7725 12:17:31.296967 TX Vref=32, minBit 0, minWin=25, winSum=413
7726 12:17:31.299822 TX Vref=34, minBit 0, minWin=24, winSum=404
7727 12:17:31.306787 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 26
7728 12:17:31.306872
7729 12:17:31.310136 Final TX Range 0 Vref 26
7730 12:17:31.310220
7731 12:17:31.310290 ==
7732 12:17:31.313054 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 12:17:31.316768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 12:17:31.316868 ==
7735 12:17:31.316939
7736 12:17:31.317004
7737 12:17:31.319999 TX Vref Scan disable
7738 12:17:31.326732 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7739 12:17:31.326817 == TX Byte 0 ==
7740 12:17:31.329892 u2DelayCellOfst[0]=10 cells (3 PI)
7741 12:17:31.333116 u2DelayCellOfst[1]=17 cells (5 PI)
7742 12:17:31.336513 u2DelayCellOfst[2]=10 cells (3 PI)
7743 12:17:31.339716 u2DelayCellOfst[3]=10 cells (3 PI)
7744 12:17:31.342999 u2DelayCellOfst[4]=3 cells (1 PI)
7745 12:17:31.346240 u2DelayCellOfst[5]=0 cells (0 PI)
7746 12:17:31.349642 u2DelayCellOfst[6]=17 cells (5 PI)
7747 12:17:31.353077 u2DelayCellOfst[7]=17 cells (5 PI)
7748 12:17:31.355990 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7749 12:17:31.359323 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7750 12:17:31.362695 == TX Byte 1 ==
7751 12:17:31.366052 u2DelayCellOfst[8]=0 cells (0 PI)
7752 12:17:31.369383 u2DelayCellOfst[9]=0 cells (0 PI)
7753 12:17:31.372620 u2DelayCellOfst[10]=10 cells (3 PI)
7754 12:17:31.372752 u2DelayCellOfst[11]=3 cells (1 PI)
7755 12:17:31.375772 u2DelayCellOfst[12]=13 cells (4 PI)
7756 12:17:31.379044 u2DelayCellOfst[13]=13 cells (4 PI)
7757 12:17:31.382565 u2DelayCellOfst[14]=17 cells (5 PI)
7758 12:17:31.385615 u2DelayCellOfst[15]=10 cells (3 PI)
7759 12:17:31.392259 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7760 12:17:31.395383 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7761 12:17:31.395487 DramC Write-DBI on
7762 12:17:31.398691 ==
7763 12:17:31.398794 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 12:17:31.405399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 12:17:31.405508 ==
7766 12:17:31.405576
7767 12:17:31.405666
7768 12:17:31.408689 TX Vref Scan disable
7769 12:17:31.408821 == TX Byte 0 ==
7770 12:17:31.415283 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7771 12:17:31.415395 == TX Byte 1 ==
7772 12:17:31.418583 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7773 12:17:31.422328 DramC Write-DBI off
7774 12:17:31.422411
7775 12:17:31.422476 [DATLAT]
7776 12:17:31.425524 Freq=1600, CH0 RK0
7777 12:17:31.425607
7778 12:17:31.425672 DATLAT Default: 0xf
7779 12:17:31.428905 0, 0xFFFF, sum = 0
7780 12:17:31.428989 1, 0xFFFF, sum = 0
7781 12:17:31.432298 2, 0xFFFF, sum = 0
7782 12:17:31.432381 3, 0xFFFF, sum = 0
7783 12:17:31.435385 4, 0xFFFF, sum = 0
7784 12:17:31.435469 5, 0xFFFF, sum = 0
7785 12:17:31.438737 6, 0xFFFF, sum = 0
7786 12:17:31.438849 7, 0xFFFF, sum = 0
7787 12:17:31.441970 8, 0xFFFF, sum = 0
7788 12:17:31.445079 9, 0xFFFF, sum = 0
7789 12:17:31.445163 10, 0xFFFF, sum = 0
7790 12:17:31.448473 11, 0xFFFF, sum = 0
7791 12:17:31.448556 12, 0xFFFF, sum = 0
7792 12:17:31.451813 13, 0xFFFF, sum = 0
7793 12:17:31.451897 14, 0x0, sum = 1
7794 12:17:31.455080 15, 0x0, sum = 2
7795 12:17:31.455164 16, 0x0, sum = 3
7796 12:17:31.458314 17, 0x0, sum = 4
7797 12:17:31.458398 best_step = 15
7798 12:17:31.458463
7799 12:17:31.458526 ==
7800 12:17:31.461597 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 12:17:31.465418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 12:17:31.465501 ==
7803 12:17:31.468689 RX Vref Scan: 1
7804 12:17:31.468809
7805 12:17:31.471690 Set Vref Range= 24 -> 127
7806 12:17:31.471772
7807 12:17:31.471837 RX Vref 24 -> 127, step: 1
7808 12:17:31.471897
7809 12:17:31.474972 RX Delay 19 -> 252, step: 4
7810 12:17:31.475056
7811 12:17:31.478187 Set Vref, RX VrefLevel [Byte0]: 24
7812 12:17:31.481455 [Byte1]: 24
7813 12:17:31.485197
7814 12:17:31.485279 Set Vref, RX VrefLevel [Byte0]: 25
7815 12:17:31.488283 [Byte1]: 25
7816 12:17:31.492407
7817 12:17:31.492491 Set Vref, RX VrefLevel [Byte0]: 26
7818 12:17:31.496060 [Byte1]: 26
7819 12:17:31.500171
7820 12:17:31.500253 Set Vref, RX VrefLevel [Byte0]: 27
7821 12:17:31.503315 [Byte1]: 27
7822 12:17:31.507893
7823 12:17:31.507998 Set Vref, RX VrefLevel [Byte0]: 28
7824 12:17:31.511194 [Byte1]: 28
7825 12:17:31.515200
7826 12:17:31.515283 Set Vref, RX VrefLevel [Byte0]: 29
7827 12:17:31.518631 [Byte1]: 29
7828 12:17:31.523022
7829 12:17:31.523105 Set Vref, RX VrefLevel [Byte0]: 30
7830 12:17:31.526149 [Byte1]: 30
7831 12:17:31.530457
7832 12:17:31.530539 Set Vref, RX VrefLevel [Byte0]: 31
7833 12:17:31.533889 [Byte1]: 31
7834 12:17:31.537998
7835 12:17:31.538080 Set Vref, RX VrefLevel [Byte0]: 32
7836 12:17:31.541190 [Byte1]: 32
7837 12:17:31.545841
7838 12:17:31.545923 Set Vref, RX VrefLevel [Byte0]: 33
7839 12:17:31.548998 [Byte1]: 33
7840 12:17:31.553218
7841 12:17:31.553300 Set Vref, RX VrefLevel [Byte0]: 34
7842 12:17:31.556585 [Byte1]: 34
7843 12:17:31.560980
7844 12:17:31.561063 Set Vref, RX VrefLevel [Byte0]: 35
7845 12:17:31.564265 [Byte1]: 35
7846 12:17:31.568570
7847 12:17:31.568655 Set Vref, RX VrefLevel [Byte0]: 36
7848 12:17:31.571863 [Byte1]: 36
7849 12:17:31.576105
7850 12:17:31.576189 Set Vref, RX VrefLevel [Byte0]: 37
7851 12:17:31.579366 [Byte1]: 37
7852 12:17:31.583519
7853 12:17:31.583647 Set Vref, RX VrefLevel [Byte0]: 38
7854 12:17:31.586818 [Byte1]: 38
7855 12:17:31.591008
7856 12:17:31.591091 Set Vref, RX VrefLevel [Byte0]: 39
7857 12:17:31.594302 [Byte1]: 39
7858 12:17:31.598634
7859 12:17:31.598717 Set Vref, RX VrefLevel [Byte0]: 40
7860 12:17:31.602096 [Byte1]: 40
7861 12:17:31.606120
7862 12:17:31.606202 Set Vref, RX VrefLevel [Byte0]: 41
7863 12:17:31.609574 [Byte1]: 41
7864 12:17:31.614015
7865 12:17:31.614097 Set Vref, RX VrefLevel [Byte0]: 42
7866 12:17:31.617251 [Byte1]: 42
7867 12:17:31.621351
7868 12:17:31.621434 Set Vref, RX VrefLevel [Byte0]: 43
7869 12:17:31.624714 [Byte1]: 43
7870 12:17:31.628959
7871 12:17:31.632266 Set Vref, RX VrefLevel [Byte0]: 44
7872 12:17:31.635589 [Byte1]: 44
7873 12:17:31.635749
7874 12:17:31.638880 Set Vref, RX VrefLevel [Byte0]: 45
7875 12:17:31.642167 [Byte1]: 45
7876 12:17:31.642249
7877 12:17:31.645367 Set Vref, RX VrefLevel [Byte0]: 46
7878 12:17:31.648694 [Byte1]: 46
7879 12:17:31.648808
7880 12:17:31.651820 Set Vref, RX VrefLevel [Byte0]: 47
7881 12:17:31.655264 [Byte1]: 47
7882 12:17:31.659454
7883 12:17:31.659537 Set Vref, RX VrefLevel [Byte0]: 48
7884 12:17:31.665639 [Byte1]: 48
7885 12:17:31.665749
7886 12:17:31.668959 Set Vref, RX VrefLevel [Byte0]: 49
7887 12:17:31.672239 [Byte1]: 49
7888 12:17:31.672325
7889 12:17:31.675569 Set Vref, RX VrefLevel [Byte0]: 50
7890 12:17:31.678919 [Byte1]: 50
7891 12:17:31.679002
7892 12:17:31.682193 Set Vref, RX VrefLevel [Byte0]: 51
7893 12:17:31.685534 [Byte1]: 51
7894 12:17:31.689612
7895 12:17:31.689695 Set Vref, RX VrefLevel [Byte0]: 52
7896 12:17:31.692759 [Byte1]: 52
7897 12:17:31.697128
7898 12:17:31.697210 Set Vref, RX VrefLevel [Byte0]: 53
7899 12:17:31.700397 [Byte1]: 53
7900 12:17:31.704889
7901 12:17:31.704972 Set Vref, RX VrefLevel [Byte0]: 54
7902 12:17:31.707910 [Byte1]: 54
7903 12:17:31.712235
7904 12:17:31.712316 Set Vref, RX VrefLevel [Byte0]: 55
7905 12:17:31.715523 [Byte1]: 55
7906 12:17:31.719878
7907 12:17:31.719987 Set Vref, RX VrefLevel [Byte0]: 56
7908 12:17:31.722987 [Byte1]: 56
7909 12:17:31.727380
7910 12:17:31.727462 Set Vref, RX VrefLevel [Byte0]: 57
7911 12:17:31.730595 [Byte1]: 57
7912 12:17:31.735268
7913 12:17:31.735351 Set Vref, RX VrefLevel [Byte0]: 58
7914 12:17:31.738135 [Byte1]: 58
7915 12:17:31.742443
7916 12:17:31.742526 Set Vref, RX VrefLevel [Byte0]: 59
7917 12:17:31.745758 [Byte1]: 59
7918 12:17:31.750346
7919 12:17:31.750428 Set Vref, RX VrefLevel [Byte0]: 60
7920 12:17:31.753622 [Byte1]: 60
7921 12:17:31.757735
7922 12:17:31.757818 Set Vref, RX VrefLevel [Byte0]: 61
7923 12:17:31.761095 [Byte1]: 61
7924 12:17:31.765303
7925 12:17:31.765385 Set Vref, RX VrefLevel [Byte0]: 62
7926 12:17:31.768513 [Byte1]: 62
7927 12:17:31.772648
7928 12:17:31.772725 Set Vref, RX VrefLevel [Byte0]: 63
7929 12:17:31.776137 [Byte1]: 63
7930 12:17:31.780385
7931 12:17:31.780503 Set Vref, RX VrefLevel [Byte0]: 64
7932 12:17:31.783591 [Byte1]: 64
7933 12:17:31.787880
7934 12:17:31.787962 Set Vref, RX VrefLevel [Byte0]: 65
7935 12:17:31.791109 [Byte1]: 65
7936 12:17:31.795593
7937 12:17:31.795677 Set Vref, RX VrefLevel [Byte0]: 66
7938 12:17:31.799038 [Byte1]: 66
7939 12:17:31.803117
7940 12:17:31.803200 Set Vref, RX VrefLevel [Byte0]: 67
7941 12:17:31.806404 [Byte1]: 67
7942 12:17:31.810965
7943 12:17:31.811049 Set Vref, RX VrefLevel [Byte0]: 68
7944 12:17:31.814237 [Byte1]: 68
7945 12:17:31.818358
7946 12:17:31.818441 Set Vref, RX VrefLevel [Byte0]: 69
7947 12:17:31.821340 [Byte1]: 69
7948 12:17:31.826017
7949 12:17:31.826101 Set Vref, RX VrefLevel [Byte0]: 70
7950 12:17:31.829101 [Byte1]: 70
7951 12:17:31.833401
7952 12:17:31.833484 Set Vref, RX VrefLevel [Byte0]: 71
7953 12:17:31.836536 [Byte1]: 71
7954 12:17:31.841049
7955 12:17:31.841132 Set Vref, RX VrefLevel [Byte0]: 72
7956 12:17:31.844508 [Byte1]: 72
7957 12:17:31.848745
7958 12:17:31.848864 Set Vref, RX VrefLevel [Byte0]: 73
7959 12:17:31.851876 [Byte1]: 73
7960 12:17:31.856126
7961 12:17:31.856208 Set Vref, RX VrefLevel [Byte0]: 74
7962 12:17:31.859779 [Byte1]: 74
7963 12:17:31.863935
7964 12:17:31.864018 Set Vref, RX VrefLevel [Byte0]: 75
7965 12:17:31.866852 [Byte1]: 75
7966 12:17:31.871525
7967 12:17:31.871609 Set Vref, RX VrefLevel [Byte0]: 76
7968 12:17:31.874815 [Byte1]: 76
7969 12:17:31.879084
7970 12:17:31.879167 Set Vref, RX VrefLevel [Byte0]: 77
7971 12:17:31.881920 [Byte1]: 77
7972 12:17:31.886579
7973 12:17:31.886679 Set Vref, RX VrefLevel [Byte0]: 78
7974 12:17:31.889913 [Byte1]: 78
7975 12:17:31.894093
7976 12:17:31.894193 Set Vref, RX VrefLevel [Byte0]: 79
7977 12:17:31.897309 [Byte1]: 79
7978 12:17:31.901529
7979 12:17:31.901634 Set Vref, RX VrefLevel [Byte0]: 80
7980 12:17:31.904990 [Byte1]: 80
7981 12:17:31.909270
7982 12:17:31.909381 Set Vref, RX VrefLevel [Byte0]: 81
7983 12:17:31.912544 [Byte1]: 81
7984 12:17:31.916729
7985 12:17:31.916854 Final RX Vref Byte 0 = 58 to rank0
7986 12:17:31.920052 Final RX Vref Byte 1 = 61 to rank0
7987 12:17:31.923197 Final RX Vref Byte 0 = 58 to rank1
7988 12:17:31.926568 Final RX Vref Byte 1 = 61 to rank1==
7989 12:17:31.929869 Dram Type= 6, Freq= 0, CH_0, rank 0
7990 12:17:31.936693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7991 12:17:31.936821 ==
7992 12:17:31.936890 DQS Delay:
7993 12:17:31.939629 DQS0 = 0, DQS1 = 0
7994 12:17:31.939729 DQM Delay:
7995 12:17:31.939798 DQM0 = 136, DQM1 = 124
7996 12:17:31.942986 DQ Delay:
7997 12:17:31.946076 DQ0 =136, DQ1 =140, DQ2 =132, DQ3 =132
7998 12:17:31.949446 DQ4 =140, DQ5 =124, DQ6 =142, DQ7 =144
7999 12:17:31.952693 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
8000 12:17:31.956476 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
8001 12:17:31.956564
8002 12:17:31.956630
8003 12:17:31.956710
8004 12:17:31.959318 [DramC_TX_OE_Calibration] TA2
8005 12:17:31.962513 Original DQ_B0 (3 6) =30, OEN = 27
8006 12:17:31.965863 Original DQ_B1 (3 6) =30, OEN = 27
8007 12:17:31.969288 24, 0x0, End_B0=24 End_B1=24
8008 12:17:31.972433 25, 0x0, End_B0=25 End_B1=25
8009 12:17:31.972546 26, 0x0, End_B0=26 End_B1=26
8010 12:17:31.975738 27, 0x0, End_B0=27 End_B1=27
8011 12:17:31.979159 28, 0x0, End_B0=28 End_B1=28
8012 12:17:31.982434 29, 0x0, End_B0=29 End_B1=29
8013 12:17:31.982541 30, 0x0, End_B0=30 End_B1=30
8014 12:17:31.985740 31, 0x4141, End_B0=30 End_B1=30
8015 12:17:31.989031 Byte0 end_step=30 best_step=27
8016 12:17:31.992369 Byte1 end_step=30 best_step=27
8017 12:17:31.995713 Byte0 TX OE(2T, 0.5T) = (3, 3)
8018 12:17:31.999005 Byte1 TX OE(2T, 0.5T) = (3, 3)
8019 12:17:31.999111
8020 12:17:31.999208
8021 12:17:32.005553 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8022 12:17:32.008876 CH0 RK0: MR19=303, MR18=1E1D
8023 12:17:32.015401 CH0_RK0: MR19=0x303, MR18=0x1E1D, DQSOSC=394, MR23=63, INC=23, DEC=15
8024 12:17:32.015484
8025 12:17:32.018573 ----->DramcWriteLeveling(PI) begin...
8026 12:17:32.018659 ==
8027 12:17:32.022024 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 12:17:32.025254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 12:17:32.025339 ==
8030 12:17:32.028441 Write leveling (Byte 0): 37 => 37
8031 12:17:32.031887 Write leveling (Byte 1): 28 => 28
8032 12:17:32.035181 DramcWriteLeveling(PI) end<-----
8033 12:17:32.035265
8034 12:17:32.035330 ==
8035 12:17:32.038744 Dram Type= 6, Freq= 0, CH_0, rank 1
8036 12:17:32.045168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8037 12:17:32.045252 ==
8038 12:17:32.045319 [Gating] SW mode calibration
8039 12:17:32.054836 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8040 12:17:32.058556 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8041 12:17:32.061798 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 12:17:32.068345 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 12:17:32.071612 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 12:17:32.074870 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8045 12:17:32.081472 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 12:17:32.084734 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 12:17:32.088219 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 12:17:32.094565 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 12:17:32.097901 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 12:17:32.101199 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8051 12:17:32.107950 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8052 12:17:32.111331 1 5 12 | B1->B0 | 3434 2727 | 0 0 | (0 1) (0 0)
8053 12:17:32.114595 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8054 12:17:32.121163 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 12:17:32.124451 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 12:17:32.127786 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 12:17:32.134414 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 12:17:32.137822 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 12:17:32.141145 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8060 12:17:32.147313 1 6 12 | B1->B0 | 2e2e 3f3f | 0 0 | (0 0) (1 1)
8061 12:17:32.150906 1 6 16 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
8062 12:17:32.154260 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 12:17:32.160912 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 12:17:32.163893 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 12:17:32.167438 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 12:17:32.174123 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 12:17:32.177306 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 12:17:32.180648 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8069 12:17:32.187017 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8070 12:17:32.190153 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 12:17:32.193532 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 12:17:32.200082 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 12:17:32.203397 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 12:17:32.206623 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 12:17:32.213378 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 12:17:32.216923 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 12:17:32.220111 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 12:17:32.226393 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 12:17:32.229669 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 12:17:32.233028 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 12:17:32.239611 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 12:17:32.243015 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 12:17:32.246378 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8084 12:17:32.253028 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8085 12:17:32.256119 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8086 12:17:32.259792 Total UI for P1: 0, mck2ui 16
8087 12:17:32.262908 best dqsien dly found for B0: ( 1, 9, 10)
8088 12:17:32.266397 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8089 12:17:32.272698 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 12:17:32.276252 Total UI for P1: 0, mck2ui 16
8091 12:17:32.279286 best dqsien dly found for B1: ( 1, 9, 16)
8092 12:17:32.282662 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8093 12:17:32.286021 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8094 12:17:32.286110
8095 12:17:32.289325 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8096 12:17:32.292678 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8097 12:17:32.296035 [Gating] SW calibration Done
8098 12:17:32.296121 ==
8099 12:17:32.299319 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 12:17:32.302522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 12:17:32.302660 ==
8102 12:17:32.305593 RX Vref Scan: 0
8103 12:17:32.305679
8104 12:17:32.309023 RX Vref 0 -> 0, step: 1
8105 12:17:32.309109
8106 12:17:32.309175 RX Delay 0 -> 252, step: 8
8107 12:17:32.315484 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8108 12:17:32.318925 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8109 12:17:32.322274 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8110 12:17:32.325480 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8111 12:17:32.328751 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8112 12:17:32.335233 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8113 12:17:32.338574 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8114 12:17:32.341770 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8115 12:17:32.345025 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8116 12:17:32.348341 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8117 12:17:32.354893 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8118 12:17:32.358253 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8119 12:17:32.361874 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8120 12:17:32.364785 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8121 12:17:32.371537 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8122 12:17:32.374755 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8123 12:17:32.374858 ==
8124 12:17:32.378051 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 12:17:32.381320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 12:17:32.381419 ==
8127 12:17:32.384752 DQS Delay:
8128 12:17:32.384910 DQS0 = 0, DQS1 = 0
8129 12:17:32.384977 DQM Delay:
8130 12:17:32.388229 DQM0 = 136, DQM1 = 125
8131 12:17:32.388322 DQ Delay:
8132 12:17:32.391542 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8133 12:17:32.395028 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8134 12:17:32.397740 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8135 12:17:32.404738 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8136 12:17:32.404899
8137 12:17:32.404970
8138 12:17:32.405032 ==
8139 12:17:32.408127 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 12:17:32.411346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 12:17:32.411440 ==
8142 12:17:32.411507
8143 12:17:32.411568
8144 12:17:32.414683 TX Vref Scan disable
8145 12:17:32.414771 == TX Byte 0 ==
8146 12:17:32.421217 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8147 12:17:32.424520 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8148 12:17:32.427816 == TX Byte 1 ==
8149 12:17:32.431130 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8150 12:17:32.434382 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8151 12:17:32.434482 ==
8152 12:17:32.437643 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 12:17:32.440966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 12:17:32.441064 ==
8155 12:17:32.456087
8156 12:17:32.459325 TX Vref early break, caculate TX vref
8157 12:17:32.462586 TX Vref=16, minBit 0, minWin=23, winSum=389
8158 12:17:32.465918 TX Vref=18, minBit 0, minWin=24, winSum=399
8159 12:17:32.469138 TX Vref=20, minBit 0, minWin=25, winSum=410
8160 12:17:32.472647 TX Vref=22, minBit 0, minWin=25, winSum=417
8161 12:17:32.476106 TX Vref=24, minBit 0, minWin=25, winSum=421
8162 12:17:32.482375 TX Vref=26, minBit 0, minWin=25, winSum=430
8163 12:17:32.485726 TX Vref=28, minBit 0, minWin=26, winSum=433
8164 12:17:32.489291 TX Vref=30, minBit 0, minWin=26, winSum=429
8165 12:17:32.492276 TX Vref=32, minBit 0, minWin=25, winSum=421
8166 12:17:32.495716 TX Vref=34, minBit 0, minWin=24, winSum=406
8167 12:17:32.502341 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 28
8168 12:17:32.502461
8169 12:17:32.505634 Final TX Range 0 Vref 28
8170 12:17:32.505716
8171 12:17:32.505779 ==
8172 12:17:32.508880 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 12:17:32.512079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 12:17:32.512162 ==
8175 12:17:32.512237
8176 12:17:32.512324
8177 12:17:32.515419 TX Vref Scan disable
8178 12:17:32.521723 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8179 12:17:32.521838 == TX Byte 0 ==
8180 12:17:32.525346 u2DelayCellOfst[0]=10 cells (3 PI)
8181 12:17:32.528683 u2DelayCellOfst[1]=17 cells (5 PI)
8182 12:17:32.531627 u2DelayCellOfst[2]=10 cells (3 PI)
8183 12:17:32.535368 u2DelayCellOfst[3]=10 cells (3 PI)
8184 12:17:32.538536 u2DelayCellOfst[4]=6 cells (2 PI)
8185 12:17:32.541973 u2DelayCellOfst[5]=0 cells (0 PI)
8186 12:17:32.544898 u2DelayCellOfst[6]=17 cells (5 PI)
8187 12:17:32.548529 u2DelayCellOfst[7]=13 cells (4 PI)
8188 12:17:32.551855 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8189 12:17:32.555205 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8190 12:17:32.558410 == TX Byte 1 ==
8191 12:17:32.561849 u2DelayCellOfst[8]=0 cells (0 PI)
8192 12:17:32.565188 u2DelayCellOfst[9]=0 cells (0 PI)
8193 12:17:32.568036 u2DelayCellOfst[10]=6 cells (2 PI)
8194 12:17:32.568134 u2DelayCellOfst[11]=0 cells (0 PI)
8195 12:17:32.571396 u2DelayCellOfst[12]=10 cells (3 PI)
8196 12:17:32.574907 u2DelayCellOfst[13]=10 cells (3 PI)
8197 12:17:32.578276 u2DelayCellOfst[14]=13 cells (4 PI)
8198 12:17:32.581563 u2DelayCellOfst[15]=10 cells (3 PI)
8199 12:17:32.588053 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8200 12:17:32.591279 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8201 12:17:32.591400 DramC Write-DBI on
8202 12:17:32.594641 ==
8203 12:17:32.597931 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 12:17:32.601200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 12:17:32.601306 ==
8206 12:17:32.601375
8207 12:17:32.601437
8208 12:17:32.604247 TX Vref Scan disable
8209 12:17:32.604338 == TX Byte 0 ==
8210 12:17:32.611068 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8211 12:17:32.611188 == TX Byte 1 ==
8212 12:17:32.614432 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8213 12:17:32.617304 DramC Write-DBI off
8214 12:17:32.617390
8215 12:17:32.617465 [DATLAT]
8216 12:17:32.620645 Freq=1600, CH0 RK1
8217 12:17:32.620777
8218 12:17:32.620879 DATLAT Default: 0xf
8219 12:17:32.623892 0, 0xFFFF, sum = 0
8220 12:17:32.623972 1, 0xFFFF, sum = 0
8221 12:17:32.627603 2, 0xFFFF, sum = 0
8222 12:17:32.627721 3, 0xFFFF, sum = 0
8223 12:17:32.630472 4, 0xFFFF, sum = 0
8224 12:17:32.633799 5, 0xFFFF, sum = 0
8225 12:17:32.633887 6, 0xFFFF, sum = 0
8226 12:17:32.637106 7, 0xFFFF, sum = 0
8227 12:17:32.637187 8, 0xFFFF, sum = 0
8228 12:17:32.640409 9, 0xFFFF, sum = 0
8229 12:17:32.640486 10, 0xFFFF, sum = 0
8230 12:17:32.644159 11, 0xFFFF, sum = 0
8231 12:17:32.644254 12, 0xFFFF, sum = 0
8232 12:17:32.647036 13, 0xFFFF, sum = 0
8233 12:17:32.647127 14, 0x0, sum = 1
8234 12:17:32.650442 15, 0x0, sum = 2
8235 12:17:32.650531 16, 0x0, sum = 3
8236 12:17:32.653711 17, 0x0, sum = 4
8237 12:17:32.653802 best_step = 15
8238 12:17:32.653874
8239 12:17:32.653939 ==
8240 12:17:32.657001 Dram Type= 6, Freq= 0, CH_0, rank 1
8241 12:17:32.660375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 12:17:32.663747 ==
8243 12:17:32.663841 RX Vref Scan: 0
8244 12:17:32.663910
8245 12:17:32.667086 RX Vref 0 -> 0, step: 1
8246 12:17:32.667162
8247 12:17:32.670380 RX Delay 11 -> 252, step: 4
8248 12:17:32.673702 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8249 12:17:32.677005 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8250 12:17:32.680601 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8251 12:17:32.686826 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8252 12:17:32.690043 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8253 12:17:32.693506 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8254 12:17:32.696940 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8255 12:17:32.699967 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8256 12:17:32.706872 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8257 12:17:32.710057 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8258 12:17:32.713463 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8259 12:17:32.716650 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8260 12:17:32.720046 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8261 12:17:32.726742 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8262 12:17:32.729962 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8263 12:17:32.733243 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8264 12:17:32.733327 ==
8265 12:17:32.736548 Dram Type= 6, Freq= 0, CH_0, rank 1
8266 12:17:32.739455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8267 12:17:32.742822 ==
8268 12:17:32.742905 DQS Delay:
8269 12:17:32.742971 DQS0 = 0, DQS1 = 0
8270 12:17:32.746065 DQM Delay:
8271 12:17:32.746148 DQM0 = 133, DQM1 = 123
8272 12:17:32.749640 DQ Delay:
8273 12:17:32.752565 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8274 12:17:32.755884 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8275 12:17:32.759516 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8276 12:17:32.762780 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8277 12:17:32.762867
8278 12:17:32.762952
8279 12:17:32.763033
8280 12:17:32.765999 [DramC_TX_OE_Calibration] TA2
8281 12:17:32.769272 Original DQ_B0 (3 6) =30, OEN = 27
8282 12:17:32.772525 Original DQ_B1 (3 6) =30, OEN = 27
8283 12:17:32.775932 24, 0x0, End_B0=24 End_B1=24
8284 12:17:32.776020 25, 0x0, End_B0=25 End_B1=25
8285 12:17:32.778895 26, 0x0, End_B0=26 End_B1=26
8286 12:17:32.782562 27, 0x0, End_B0=27 End_B1=27
8287 12:17:32.785348 28, 0x0, End_B0=28 End_B1=28
8288 12:17:32.788694 29, 0x0, End_B0=29 End_B1=29
8289 12:17:32.788802 30, 0x0, End_B0=30 End_B1=30
8290 12:17:32.791988 31, 0x4545, End_B0=30 End_B1=30
8291 12:17:32.795268 Byte0 end_step=30 best_step=27
8292 12:17:32.799019 Byte1 end_step=30 best_step=27
8293 12:17:32.802231 Byte0 TX OE(2T, 0.5T) = (3, 3)
8294 12:17:32.805274 Byte1 TX OE(2T, 0.5T) = (3, 3)
8295 12:17:32.805390
8296 12:17:32.805456
8297 12:17:32.811726 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8298 12:17:32.815283 CH0 RK1: MR19=303, MR18=210E
8299 12:17:32.821992 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8300 12:17:32.825137 [RxdqsGatingPostProcess] freq 1600
8301 12:17:32.828500 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8302 12:17:32.831761 best DQS0 dly(2T, 0.5T) = (1, 1)
8303 12:17:32.834994 best DQS1 dly(2T, 0.5T) = (1, 1)
8304 12:17:32.838229 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8305 12:17:32.841574 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8306 12:17:32.844893 best DQS0 dly(2T, 0.5T) = (1, 1)
8307 12:17:32.848171 best DQS1 dly(2T, 0.5T) = (1, 1)
8308 12:17:32.851382 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8309 12:17:32.854744 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8310 12:17:32.858042 Pre-setting of DQS Precalculation
8311 12:17:32.861349 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8312 12:17:32.861435 ==
8313 12:17:32.864667 Dram Type= 6, Freq= 0, CH_1, rank 0
8314 12:17:32.871213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 12:17:32.871305 ==
8316 12:17:32.874523 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8317 12:17:32.881247 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8318 12:17:32.884492 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8319 12:17:32.891002 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8320 12:17:32.898676 [CA 0] Center 40 (11~70) winsize 60
8321 12:17:32.901943 [CA 1] Center 41 (11~71) winsize 61
8322 12:17:32.905319 [CA 2] Center 37 (8~67) winsize 60
8323 12:17:32.908499 [CA 3] Center 36 (7~66) winsize 60
8324 12:17:32.911975 [CA 4] Center 36 (6~66) winsize 61
8325 12:17:32.914981 [CA 5] Center 36 (6~66) winsize 61
8326 12:17:32.915066
8327 12:17:32.918405 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8328 12:17:32.918490
8329 12:17:32.924967 [CATrainingPosCal] consider 1 rank data
8330 12:17:32.925054 u2DelayCellTimex100 = 285/100 ps
8331 12:17:32.931821 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8332 12:17:32.935149 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8333 12:17:32.938470 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8334 12:17:32.941686 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8335 12:17:32.945038 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
8336 12:17:32.948299 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8337 12:17:32.948394
8338 12:17:32.951147 CA PerBit enable=1, Macro0, CA PI delay=36
8339 12:17:32.951231
8340 12:17:32.954785 [CBTSetCACLKResult] CA Dly = 36
8341 12:17:32.958153 CS Dly: 8 (0~39)
8342 12:17:32.961079 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8343 12:17:32.964335 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8344 12:17:32.964420 ==
8345 12:17:32.967756 Dram Type= 6, Freq= 0, CH_1, rank 1
8346 12:17:32.974418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8347 12:17:32.974504 ==
8348 12:17:32.977711 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8349 12:17:32.984267 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8350 12:17:32.987589 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8351 12:17:32.993904 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8352 12:17:33.001862 [CA 0] Center 41 (12~71) winsize 60
8353 12:17:33.005080 [CA 1] Center 41 (12~71) winsize 60
8354 12:17:33.008381 [CA 2] Center 37 (8~67) winsize 60
8355 12:17:33.011661 [CA 3] Center 37 (8~67) winsize 60
8356 12:17:33.015062 [CA 4] Center 37 (8~67) winsize 60
8357 12:17:33.018349 [CA 5] Center 37 (7~67) winsize 61
8358 12:17:33.018431
8359 12:17:33.021720 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8360 12:17:33.021802
8361 12:17:33.025016 [CATrainingPosCal] consider 2 rank data
8362 12:17:33.028274 u2DelayCellTimex100 = 285/100 ps
8363 12:17:33.034636 CA0 delay=41 (12~70),Diff = 5 PI (17 cell)
8364 12:17:33.037961 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8365 12:17:33.041564 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8366 12:17:33.044660 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8367 12:17:33.047907 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8368 12:17:33.051234 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8369 12:17:33.051314
8370 12:17:33.054575 CA PerBit enable=1, Macro0, CA PI delay=36
8371 12:17:33.054655
8372 12:17:33.057914 [CBTSetCACLKResult] CA Dly = 36
8373 12:17:33.061042 CS Dly: 9 (0~42)
8374 12:17:33.064310 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8375 12:17:33.067613 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8376 12:17:33.067693
8377 12:17:33.070954 ----->DramcWriteLeveling(PI) begin...
8378 12:17:33.071036 ==
8379 12:17:33.074326 Dram Type= 6, Freq= 0, CH_1, rank 0
8380 12:17:33.080917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 12:17:33.081003 ==
8382 12:17:33.084275 Write leveling (Byte 0): 24 => 24
8383 12:17:33.087681 Write leveling (Byte 1): 30 => 30
8384 12:17:33.087766 DramcWriteLeveling(PI) end<-----
8385 12:17:33.087830
8386 12:17:33.091005 ==
8387 12:17:33.094270 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 12:17:33.097442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 12:17:33.097525 ==
8390 12:17:33.100737 [Gating] SW mode calibration
8391 12:17:33.107509 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8392 12:17:33.110699 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8393 12:17:33.117385 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 12:17:33.120675 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 12:17:33.123940 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8396 12:17:33.130429 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8397 12:17:33.133615 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 12:17:33.137192 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 12:17:33.143659 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 12:17:33.147036 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 12:17:33.150385 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 12:17:33.157125 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8403 12:17:33.160430 1 5 8 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (0 1)
8404 12:17:33.163721 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8405 12:17:33.170366 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8406 12:17:33.173656 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 12:17:33.176921 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 12:17:33.183523 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 12:17:33.186789 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 12:17:33.190040 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 12:17:33.196732 1 6 8 | B1->B0 | 3030 4040 | 0 0 | (0 0) (0 0)
8412 12:17:33.199863 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8413 12:17:33.203189 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 12:17:33.209863 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 12:17:33.213033 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 12:17:33.216241 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 12:17:33.222777 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 12:17:33.226291 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 12:17:33.229699 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8420 12:17:33.236157 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8421 12:17:33.239268 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 12:17:33.242628 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 12:17:33.249476 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 12:17:33.252633 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 12:17:33.256090 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 12:17:33.262475 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 12:17:33.265845 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 12:17:33.269084 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 12:17:33.275760 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 12:17:33.279180 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 12:17:33.282478 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 12:17:33.288689 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 12:17:33.292125 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 12:17:33.295393 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8435 12:17:33.301948 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8436 12:17:33.305506 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8437 12:17:33.308693 Total UI for P1: 0, mck2ui 16
8438 12:17:33.312070 best dqsien dly found for B0: ( 1, 9, 6)
8439 12:17:33.314859 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 12:17:33.318665 Total UI for P1: 0, mck2ui 16
8441 12:17:33.321594 best dqsien dly found for B1: ( 1, 9, 12)
8442 12:17:33.325013 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8443 12:17:33.328253 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8444 12:17:33.328347
8445 12:17:33.334881 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8446 12:17:33.338124 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8447 12:17:33.341352 [Gating] SW calibration Done
8448 12:17:33.341439 ==
8449 12:17:33.344496 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 12:17:33.347829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 12:17:33.347920 ==
8452 12:17:33.351046 RX Vref Scan: 0
8453 12:17:33.351179
8454 12:17:33.351245 RX Vref 0 -> 0, step: 1
8455 12:17:33.351309
8456 12:17:33.354514 RX Delay 0 -> 252, step: 8
8457 12:17:33.357714 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8458 12:17:33.361025 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8459 12:17:33.367660 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8460 12:17:33.370857 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8461 12:17:33.374314 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8462 12:17:33.377611 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8463 12:17:33.380889 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8464 12:17:33.387452 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8465 12:17:33.390854 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8466 12:17:33.394215 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8467 12:17:33.397579 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8468 12:17:33.400799 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8469 12:17:33.407273 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8470 12:17:33.410462 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8471 12:17:33.413875 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8472 12:17:33.417162 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8473 12:17:33.417260 ==
8474 12:17:33.419968 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 12:17:33.426901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 12:17:33.427010 ==
8477 12:17:33.427080 DQS Delay:
8478 12:17:33.430152 DQS0 = 0, DQS1 = 0
8479 12:17:33.430238 DQM Delay:
8480 12:17:33.433368 DQM0 = 138, DQM1 = 131
8481 12:17:33.433456 DQ Delay:
8482 12:17:33.436554 DQ0 =139, DQ1 =135, DQ2 =127, DQ3 =139
8483 12:17:33.440259 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8484 12:17:33.443453 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
8485 12:17:33.446659 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8486 12:17:33.446749
8487 12:17:33.446816
8488 12:17:33.446878 ==
8489 12:17:33.449982 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 12:17:33.456549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 12:17:33.456649 ==
8492 12:17:33.456719
8493 12:17:33.456787
8494 12:17:33.456847 TX Vref Scan disable
8495 12:17:33.460115 == TX Byte 0 ==
8496 12:17:33.463328 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8497 12:17:33.469867 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8498 12:17:33.469999 == TX Byte 1 ==
8499 12:17:33.472967 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8500 12:17:33.479797 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8501 12:17:33.479924 ==
8502 12:17:33.483156 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 12:17:33.486423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 12:17:33.486526 ==
8505 12:17:33.499122
8506 12:17:33.502388 TX Vref early break, caculate TX vref
8507 12:17:33.505742 TX Vref=16, minBit 15, minWin=20, winSum=368
8508 12:17:33.509043 TX Vref=18, minBit 15, minWin=21, winSum=375
8509 12:17:33.512218 TX Vref=20, minBit 13, minWin=22, winSum=382
8510 12:17:33.515484 TX Vref=22, minBit 15, minWin=23, winSum=400
8511 12:17:33.522119 TX Vref=24, minBit 13, minWin=24, winSum=411
8512 12:17:33.525500 TX Vref=26, minBit 12, minWin=24, winSum=413
8513 12:17:33.528688 TX Vref=28, minBit 15, minWin=24, winSum=419
8514 12:17:33.532179 TX Vref=30, minBit 9, minWin=24, winSum=414
8515 12:17:33.535323 TX Vref=32, minBit 10, minWin=24, winSum=407
8516 12:17:33.541830 TX Vref=34, minBit 10, minWin=23, winSum=396
8517 12:17:33.544976 [TxChooseVref] Worse bit 15, Min win 24, Win sum 419, Final Vref 28
8518 12:17:33.545110
8519 12:17:33.548346 Final TX Range 0 Vref 28
8520 12:17:33.548476
8521 12:17:33.548597 ==
8522 12:17:33.552081 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 12:17:33.555386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 12:17:33.558654 ==
8525 12:17:33.558805
8526 12:17:33.558939
8527 12:17:33.559064 TX Vref Scan disable
8528 12:17:33.565253 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8529 12:17:33.565434 == TX Byte 0 ==
8530 12:17:33.568757 u2DelayCellOfst[0]=17 cells (5 PI)
8531 12:17:33.572027 u2DelayCellOfst[1]=10 cells (3 PI)
8532 12:17:33.575153 u2DelayCellOfst[2]=0 cells (0 PI)
8533 12:17:33.578375 u2DelayCellOfst[3]=6 cells (2 PI)
8534 12:17:33.581949 u2DelayCellOfst[4]=6 cells (2 PI)
8535 12:17:33.585130 u2DelayCellOfst[5]=17 cells (5 PI)
8536 12:17:33.588489 u2DelayCellOfst[6]=17 cells (5 PI)
8537 12:17:33.591368 u2DelayCellOfst[7]=6 cells (2 PI)
8538 12:17:33.594712 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8539 12:17:33.598033 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8540 12:17:33.601414 == TX Byte 1 ==
8541 12:17:33.604906 u2DelayCellOfst[8]=0 cells (0 PI)
8542 12:17:33.608138 u2DelayCellOfst[9]=3 cells (1 PI)
8543 12:17:33.611337 u2DelayCellOfst[10]=10 cells (3 PI)
8544 12:17:33.614571 u2DelayCellOfst[11]=3 cells (1 PI)
8545 12:17:33.618262 u2DelayCellOfst[12]=13 cells (4 PI)
8546 12:17:33.618393 u2DelayCellOfst[13]=13 cells (4 PI)
8547 12:17:33.621648 u2DelayCellOfst[14]=17 cells (5 PI)
8548 12:17:33.624904 u2DelayCellOfst[15]=13 cells (4 PI)
8549 12:17:33.630965 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8550 12:17:33.634352 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8551 12:17:33.637627 DramC Write-DBI on
8552 12:17:33.637794 ==
8553 12:17:33.640879 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 12:17:33.644463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 12:17:33.644586 ==
8556 12:17:33.644688
8557 12:17:33.644835
8558 12:17:33.647431 TX Vref Scan disable
8559 12:17:33.647521 == TX Byte 0 ==
8560 12:17:33.654174 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8561 12:17:33.654281 == TX Byte 1 ==
8562 12:17:33.657410 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8563 12:17:33.660728 DramC Write-DBI off
8564 12:17:33.660818
8565 12:17:33.660884 [DATLAT]
8566 12:17:33.664087 Freq=1600, CH1 RK0
8567 12:17:33.664250
8568 12:17:33.664317 DATLAT Default: 0xf
8569 12:17:33.667432 0, 0xFFFF, sum = 0
8570 12:17:33.670775 1, 0xFFFF, sum = 0
8571 12:17:33.670861 2, 0xFFFF, sum = 0
8572 12:17:33.674491 3, 0xFFFF, sum = 0
8573 12:17:33.674861 4, 0xFFFF, sum = 0
8574 12:17:33.677472 5, 0xFFFF, sum = 0
8575 12:17:33.677842 6, 0xFFFF, sum = 0
8576 12:17:33.681185 7, 0xFFFF, sum = 0
8577 12:17:33.681271 8, 0xFFFF, sum = 0
8578 12:17:33.684042 9, 0xFFFF, sum = 0
8579 12:17:33.684127 10, 0xFFFF, sum = 0
8580 12:17:33.687132 11, 0xFFFF, sum = 0
8581 12:17:33.687217 12, 0xFFFF, sum = 0
8582 12:17:33.690622 13, 0xFFFF, sum = 0
8583 12:17:33.690708 14, 0x0, sum = 1
8584 12:17:33.693952 15, 0x0, sum = 2
8585 12:17:33.694037 16, 0x0, sum = 3
8586 12:17:33.697353 17, 0x0, sum = 4
8587 12:17:33.697439 best_step = 15
8588 12:17:33.697506
8589 12:17:33.697567 ==
8590 12:17:33.700676 Dram Type= 6, Freq= 0, CH_1, rank 0
8591 12:17:33.707479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8592 12:17:33.707564 ==
8593 12:17:33.707629 RX Vref Scan: 1
8594 12:17:33.707691
8595 12:17:33.710592 Set Vref Range= 24 -> 127
8596 12:17:33.710676
8597 12:17:33.713659 RX Vref 24 -> 127, step: 1
8598 12:17:33.713743
8599 12:17:33.713809 RX Delay 19 -> 252, step: 4
8600 12:17:33.713872
8601 12:17:33.717057 Set Vref, RX VrefLevel [Byte0]: 24
8602 12:17:33.720038 [Byte1]: 24
8603 12:17:33.724362
8604 12:17:33.724443 Set Vref, RX VrefLevel [Byte0]: 25
8605 12:17:33.727544 [Byte1]: 25
8606 12:17:33.731713
8607 12:17:33.731824 Set Vref, RX VrefLevel [Byte0]: 26
8608 12:17:33.734982 [Byte1]: 26
8609 12:17:33.739489
8610 12:17:33.739599 Set Vref, RX VrefLevel [Byte0]: 27
8611 12:17:33.742856 [Byte1]: 27
8612 12:17:33.746927
8613 12:17:33.747035 Set Vref, RX VrefLevel [Byte0]: 28
8614 12:17:33.750718 [Byte1]: 28
8615 12:17:33.754590
8616 12:17:33.754697 Set Vref, RX VrefLevel [Byte0]: 29
8617 12:17:33.757797 [Byte1]: 29
8618 12:17:33.762300
8619 12:17:33.762375 Set Vref, RX VrefLevel [Byte0]: 30
8620 12:17:33.765519 [Byte1]: 30
8621 12:17:33.769808
8622 12:17:33.769878 Set Vref, RX VrefLevel [Byte0]: 31
8623 12:17:33.773207 [Byte1]: 31
8624 12:17:33.777440
8625 12:17:33.777521 Set Vref, RX VrefLevel [Byte0]: 32
8626 12:17:33.780739 [Byte1]: 32
8627 12:17:33.785237
8628 12:17:33.785324 Set Vref, RX VrefLevel [Byte0]: 33
8629 12:17:33.788278 [Byte1]: 33
8630 12:17:33.792357
8631 12:17:33.792433 Set Vref, RX VrefLevel [Byte0]: 34
8632 12:17:33.795804 [Byte1]: 34
8633 12:17:33.800519
8634 12:17:33.800719 Set Vref, RX VrefLevel [Byte0]: 35
8635 12:17:33.803422 [Byte1]: 35
8636 12:17:33.807860
8637 12:17:33.807967 Set Vref, RX VrefLevel [Byte0]: 36
8638 12:17:33.811081 [Byte1]: 36
8639 12:17:33.815380
8640 12:17:33.815511 Set Vref, RX VrefLevel [Byte0]: 37
8641 12:17:33.818777 [Byte1]: 37
8642 12:17:33.823008
8643 12:17:33.823197 Set Vref, RX VrefLevel [Byte0]: 38
8644 12:17:33.826081 [Byte1]: 38
8645 12:17:33.830333
8646 12:17:33.830439 Set Vref, RX VrefLevel [Byte0]: 39
8647 12:17:33.833812 [Byte1]: 39
8648 12:17:33.838040
8649 12:17:33.838134 Set Vref, RX VrefLevel [Byte0]: 40
8650 12:17:33.841248 [Byte1]: 40
8651 12:17:33.845421
8652 12:17:33.845574 Set Vref, RX VrefLevel [Byte0]: 41
8653 12:17:33.848667 [Byte1]: 41
8654 12:17:33.853215
8655 12:17:33.853335 Set Vref, RX VrefLevel [Byte0]: 42
8656 12:17:33.856489 [Byte1]: 42
8657 12:17:33.860878
8658 12:17:33.861058 Set Vref, RX VrefLevel [Byte0]: 43
8659 12:17:33.864147 [Byte1]: 43
8660 12:17:33.868315
8661 12:17:33.868548 Set Vref, RX VrefLevel [Byte0]: 44
8662 12:17:33.871586 [Byte1]: 44
8663 12:17:33.875939
8664 12:17:33.876252 Set Vref, RX VrefLevel [Byte0]: 45
8665 12:17:33.879474 [Byte1]: 45
8666 12:17:33.883646
8667 12:17:33.884100 Set Vref, RX VrefLevel [Byte0]: 46
8668 12:17:33.886935 [Byte1]: 46
8669 12:17:33.891392
8670 12:17:33.891873 Set Vref, RX VrefLevel [Byte0]: 47
8671 12:17:33.894642 [Byte1]: 47
8672 12:17:33.899051
8673 12:17:33.899577 Set Vref, RX VrefLevel [Byte0]: 48
8674 12:17:33.902161 [Byte1]: 48
8675 12:17:33.906476
8676 12:17:33.906927 Set Vref, RX VrefLevel [Byte0]: 49
8677 12:17:33.909543 [Byte1]: 49
8678 12:17:33.913840
8679 12:17:33.914234 Set Vref, RX VrefLevel [Byte0]: 50
8680 12:17:33.917123 [Byte1]: 50
8681 12:17:33.921375
8682 12:17:33.921836 Set Vref, RX VrefLevel [Byte0]: 51
8683 12:17:33.924792 [Byte1]: 51
8684 12:17:33.929046
8685 12:17:33.929532 Set Vref, RX VrefLevel [Byte0]: 52
8686 12:17:33.932601 [Byte1]: 52
8687 12:17:33.937301
8688 12:17:33.937764 Set Vref, RX VrefLevel [Byte0]: 53
8689 12:17:33.940262 [Byte1]: 53
8690 12:17:33.944366
8691 12:17:33.944720 Set Vref, RX VrefLevel [Byte0]: 54
8692 12:17:33.947758 [Byte1]: 54
8693 12:17:33.951748
8694 12:17:33.952208 Set Vref, RX VrefLevel [Byte0]: 55
8695 12:17:33.955212 [Byte1]: 55
8696 12:17:33.959571
8697 12:17:33.959924 Set Vref, RX VrefLevel [Byte0]: 56
8698 12:17:33.962496 [Byte1]: 56
8699 12:17:33.967178
8700 12:17:33.967529 Set Vref, RX VrefLevel [Byte0]: 57
8701 12:17:33.970332 [Byte1]: 57
8702 12:17:33.974642
8703 12:17:33.975006 Set Vref, RX VrefLevel [Byte0]: 58
8704 12:17:33.977927 [Byte1]: 58
8705 12:17:33.982201
8706 12:17:33.982676 Set Vref, RX VrefLevel [Byte0]: 59
8707 12:17:33.985613 [Byte1]: 59
8708 12:17:33.989605
8709 12:17:33.989959 Set Vref, RX VrefLevel [Byte0]: 60
8710 12:17:33.992800 [Byte1]: 60
8711 12:17:33.997487
8712 12:17:33.997841 Set Vref, RX VrefLevel [Byte0]: 61
8713 12:17:34.000788 [Byte1]: 61
8714 12:17:34.004869
8715 12:17:34.005224 Set Vref, RX VrefLevel [Byte0]: 62
8716 12:17:34.008189 [Byte1]: 62
8717 12:17:34.012568
8718 12:17:34.013095 Set Vref, RX VrefLevel [Byte0]: 63
8719 12:17:34.015632 [Byte1]: 63
8720 12:17:34.019963
8721 12:17:34.020389 Set Vref, RX VrefLevel [Byte0]: 64
8722 12:17:34.023197 [Byte1]: 64
8723 12:17:34.027477
8724 12:17:34.027912 Set Vref, RX VrefLevel [Byte0]: 65
8725 12:17:34.030805 [Byte1]: 65
8726 12:17:34.035127
8727 12:17:34.035479 Set Vref, RX VrefLevel [Byte0]: 66
8728 12:17:34.038803 [Byte1]: 66
8729 12:17:34.042584
8730 12:17:34.042936 Set Vref, RX VrefLevel [Byte0]: 67
8731 12:17:34.045801 [Byte1]: 67
8732 12:17:34.050504
8733 12:17:34.050856 Set Vref, RX VrefLevel [Byte0]: 68
8734 12:17:34.053380 [Byte1]: 68
8735 12:17:34.057570
8736 12:17:34.057930 Set Vref, RX VrefLevel [Byte0]: 69
8737 12:17:34.060897 [Byte1]: 69
8738 12:17:34.065318
8739 12:17:34.065676 Set Vref, RX VrefLevel [Byte0]: 70
8740 12:17:34.068597 [Byte1]: 70
8741 12:17:34.072831
8742 12:17:34.073188 Set Vref, RX VrefLevel [Byte0]: 71
8743 12:17:34.076465 [Byte1]: 71
8744 12:17:34.080753
8745 12:17:34.081137 Set Vref, RX VrefLevel [Byte0]: 72
8746 12:17:34.083655 [Byte1]: 72
8747 12:17:34.088450
8748 12:17:34.088826 Final RX Vref Byte 0 = 52 to rank0
8749 12:17:34.091324 Final RX Vref Byte 1 = 63 to rank0
8750 12:17:34.094460 Final RX Vref Byte 0 = 52 to rank1
8751 12:17:34.098118 Final RX Vref Byte 1 = 63 to rank1==
8752 12:17:34.101387 Dram Type= 6, Freq= 0, CH_1, rank 0
8753 12:17:34.107731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 12:17:34.108094 ==
8755 12:17:34.108381 DQS Delay:
8756 12:17:34.110913 DQS0 = 0, DQS1 = 0
8757 12:17:34.111270 DQM Delay:
8758 12:17:34.114434 DQM0 = 133, DQM1 = 128
8759 12:17:34.114794 DQ Delay:
8760 12:17:34.117194 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8761 12:17:34.120535 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8762 12:17:34.124033 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8763 12:17:34.127370 DQ12 =140, DQ13 =134, DQ14 =134, DQ15 =134
8764 12:17:34.127452
8765 12:17:34.127517
8766 12:17:34.127575
8767 12:17:34.130675 [DramC_TX_OE_Calibration] TA2
8768 12:17:34.134106 Original DQ_B0 (3 6) =30, OEN = 27
8769 12:17:34.137148 Original DQ_B1 (3 6) =30, OEN = 27
8770 12:17:34.140305 24, 0x0, End_B0=24 End_B1=24
8771 12:17:34.143661 25, 0x0, End_B0=25 End_B1=25
8772 12:17:34.143745 26, 0x0, End_B0=26 End_B1=26
8773 12:17:34.147031 27, 0x0, End_B0=27 End_B1=27
8774 12:17:34.150463 28, 0x0, End_B0=28 End_B1=28
8775 12:17:34.153415 29, 0x0, End_B0=29 End_B1=29
8776 12:17:34.153512 30, 0x0, End_B0=30 End_B1=30
8777 12:17:34.156670 31, 0x4141, End_B0=30 End_B1=30
8778 12:17:34.160230 Byte0 end_step=30 best_step=27
8779 12:17:34.163532 Byte1 end_step=30 best_step=27
8780 12:17:34.166843 Byte0 TX OE(2T, 0.5T) = (3, 3)
8781 12:17:34.170179 Byte1 TX OE(2T, 0.5T) = (3, 3)
8782 12:17:34.170303
8783 12:17:34.170400
8784 12:17:34.176760 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8785 12:17:34.180059 CH1 RK0: MR19=303, MR18=1725
8786 12:17:34.186875 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8787 12:17:34.187360
8788 12:17:34.189802 ----->DramcWriteLeveling(PI) begin...
8789 12:17:34.189886 ==
8790 12:17:34.193157 Dram Type= 6, Freq= 0, CH_1, rank 1
8791 12:17:34.196535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8792 12:17:34.196619 ==
8793 12:17:34.199882 Write leveling (Byte 0): 23 => 23
8794 12:17:34.203563 Write leveling (Byte 1): 30 => 30
8795 12:17:34.206742 DramcWriteLeveling(PI) end<-----
8796 12:17:34.206895
8797 12:17:34.206970 ==
8798 12:17:34.210042 Dram Type= 6, Freq= 0, CH_1, rank 1
8799 12:17:34.213446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 12:17:34.216700 ==
8801 12:17:34.216823 [Gating] SW mode calibration
8802 12:17:34.226299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8803 12:17:34.229769 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8804 12:17:34.233157 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 12:17:34.239638 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 12:17:34.242916 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 12:17:34.246034 1 4 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
8808 12:17:34.252651 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 12:17:34.255966 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 12:17:34.259214 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 12:17:34.265836 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 12:17:34.269220 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 12:17:34.272243 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8814 12:17:34.278842 1 5 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 0) (1 0)
8815 12:17:34.282104 1 5 12 | B1->B0 | 2323 2f2f | 0 1 | (1 0) (1 0)
8816 12:17:34.285353 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 12:17:34.292176 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 12:17:34.295399 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 12:17:34.298799 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 12:17:34.305197 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 12:17:34.308482 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 12:17:34.311941 1 6 8 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8823 12:17:34.318575 1 6 12 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
8824 12:17:34.322185 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 12:17:34.325146 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 12:17:34.332022 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 12:17:34.334995 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 12:17:34.338353 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 12:17:34.345132 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 12:17:34.348229 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8831 12:17:34.351449 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8832 12:17:34.358091 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 12:17:34.361314 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 12:17:34.364585 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 12:17:34.371211 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 12:17:34.374388 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 12:17:34.378024 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 12:17:34.384690 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 12:17:34.387826 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 12:17:34.391146 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 12:17:34.397844 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 12:17:34.401244 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 12:17:34.404471 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 12:17:34.410980 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 12:17:34.414297 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 12:17:34.417687 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8847 12:17:34.424495 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8848 12:17:34.427746 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 12:17:34.431059 Total UI for P1: 0, mck2ui 16
8850 12:17:34.434526 best dqsien dly found for B0: ( 1, 9, 10)
8851 12:17:34.437790 Total UI for P1: 0, mck2ui 16
8852 12:17:34.441244 best dqsien dly found for B1: ( 1, 9, 10)
8853 12:17:34.444645 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8854 12:17:34.447630 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8855 12:17:34.448319
8856 12:17:34.450867 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8857 12:17:34.454304 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8858 12:17:34.457412 [Gating] SW calibration Done
8859 12:17:34.457497 ==
8860 12:17:34.460667 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 12:17:34.467058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 12:17:34.467176 ==
8863 12:17:34.467298 RX Vref Scan: 0
8864 12:17:34.467406
8865 12:17:34.470491 RX Vref 0 -> 0, step: 1
8866 12:17:34.470613
8867 12:17:34.473854 RX Delay 0 -> 252, step: 8
8868 12:17:34.477108 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8869 12:17:34.480559 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8870 12:17:34.483812 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8871 12:17:34.487148 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8872 12:17:34.493898 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8873 12:17:34.497100 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8874 12:17:34.500352 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8875 12:17:34.503675 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8876 12:17:34.506836 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8877 12:17:34.510226 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8878 12:17:34.517165 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8879 12:17:34.520499 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8880 12:17:34.523854 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8881 12:17:34.527183 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8882 12:17:34.533659 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8883 12:17:34.537051 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8884 12:17:34.537135 ==
8885 12:17:34.540409 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 12:17:34.543710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 12:17:34.543797 ==
8888 12:17:34.546975 DQS Delay:
8889 12:17:34.547063 DQS0 = 0, DQS1 = 0
8890 12:17:34.547133 DQM Delay:
8891 12:17:34.550062 DQM0 = 138, DQM1 = 131
8892 12:17:34.550145 DQ Delay:
8893 12:17:34.553506 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8894 12:17:34.556957 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =139
8895 12:17:34.559898 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8896 12:17:34.566502 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =139
8897 12:17:34.566586
8898 12:17:34.566651
8899 12:17:34.566712 ==
8900 12:17:34.569891 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 12:17:34.573190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 12:17:34.573274 ==
8903 12:17:34.573340
8904 12:17:34.573400
8905 12:17:34.576616 TX Vref Scan disable
8906 12:17:34.576699 == TX Byte 0 ==
8907 12:17:34.582989 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8908 12:17:34.586688 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8909 12:17:34.586772 == TX Byte 1 ==
8910 12:17:34.592925 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8911 12:17:34.596695 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8912 12:17:34.596806 ==
8913 12:17:34.600017 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 12:17:34.603236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 12:17:34.603326 ==
8916 12:17:34.617814
8917 12:17:34.620961 TX Vref early break, caculate TX vref
8918 12:17:34.624386 TX Vref=16, minBit 9, minWin=22, winSum=380
8919 12:17:34.627706 TX Vref=18, minBit 9, minWin=23, winSum=391
8920 12:17:34.630671 TX Vref=20, minBit 15, minWin=23, winSum=398
8921 12:17:34.634132 TX Vref=22, minBit 9, minWin=24, winSum=407
8922 12:17:34.637528 TX Vref=24, minBit 13, minWin=23, winSum=412
8923 12:17:34.644179 TX Vref=26, minBit 13, minWin=25, winSum=422
8924 12:17:34.647381 TX Vref=28, minBit 15, minWin=25, winSum=425
8925 12:17:34.650652 TX Vref=30, minBit 10, minWin=24, winSum=412
8926 12:17:34.653989 TX Vref=32, minBit 9, minWin=24, winSum=405
8927 12:17:34.657179 TX Vref=34, minBit 10, minWin=23, winSum=400
8928 12:17:34.663681 [TxChooseVref] Worse bit 15, Min win 25, Win sum 425, Final Vref 28
8929 12:17:34.663759
8930 12:17:34.667053 Final TX Range 0 Vref 28
8931 12:17:34.667137
8932 12:17:34.667200 ==
8933 12:17:34.670512 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 12:17:34.673709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 12:17:34.673792 ==
8936 12:17:34.677001
8937 12:17:34.677079
8938 12:17:34.677145 TX Vref Scan disable
8939 12:17:34.683550 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8940 12:17:34.683639 == TX Byte 0 ==
8941 12:17:34.686830 u2DelayCellOfst[0]=13 cells (4 PI)
8942 12:17:34.690407 u2DelayCellOfst[1]=10 cells (3 PI)
8943 12:17:34.693745 u2DelayCellOfst[2]=0 cells (0 PI)
8944 12:17:34.696937 u2DelayCellOfst[3]=3 cells (1 PI)
8945 12:17:34.700085 u2DelayCellOfst[4]=6 cells (2 PI)
8946 12:17:34.703358 u2DelayCellOfst[5]=17 cells (5 PI)
8947 12:17:34.706692 u2DelayCellOfst[6]=13 cells (4 PI)
8948 12:17:34.710268 u2DelayCellOfst[7]=3 cells (1 PI)
8949 12:17:34.713674 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8950 12:17:34.717000 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8951 12:17:34.720374 == TX Byte 1 ==
8952 12:17:34.723484 u2DelayCellOfst[8]=0 cells (0 PI)
8953 12:17:34.726719 u2DelayCellOfst[9]=3 cells (1 PI)
8954 12:17:34.730041 u2DelayCellOfst[10]=10 cells (3 PI)
8955 12:17:34.733432 u2DelayCellOfst[11]=3 cells (1 PI)
8956 12:17:34.733715 u2DelayCellOfst[12]=13 cells (4 PI)
8957 12:17:34.736534 u2DelayCellOfst[13]=17 cells (5 PI)
8958 12:17:34.739748 u2DelayCellOfst[14]=13 cells (4 PI)
8959 12:17:34.743155 u2DelayCellOfst[15]=17 cells (5 PI)
8960 12:17:34.749802 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8961 12:17:34.753118 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8962 12:17:34.753255 DramC Write-DBI on
8963 12:17:34.756473 ==
8964 12:17:34.759810 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 12:17:34.763041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 12:17:34.763133 ==
8967 12:17:34.763234
8968 12:17:34.763325
8969 12:17:34.766158 TX Vref Scan disable
8970 12:17:34.766232 == TX Byte 0 ==
8971 12:17:34.772628 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8972 12:17:34.772748 == TX Byte 1 ==
8973 12:17:34.776190 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8974 12:17:34.779206 DramC Write-DBI off
8975 12:17:34.779279
8976 12:17:34.779343 [DATLAT]
8977 12:17:34.782642 Freq=1600, CH1 RK1
8978 12:17:34.782720
8979 12:17:34.782792 DATLAT Default: 0xf
8980 12:17:34.785966 0, 0xFFFF, sum = 0
8981 12:17:34.786049 1, 0xFFFF, sum = 0
8982 12:17:34.789088 2, 0xFFFF, sum = 0
8983 12:17:34.789171 3, 0xFFFF, sum = 0
8984 12:17:34.792744 4, 0xFFFF, sum = 0
8985 12:17:34.796108 5, 0xFFFF, sum = 0
8986 12:17:34.796180 6, 0xFFFF, sum = 0
8987 12:17:34.798868 7, 0xFFFF, sum = 0
8988 12:17:34.798952 8, 0xFFFF, sum = 0
8989 12:17:34.802592 9, 0xFFFF, sum = 0
8990 12:17:34.802675 10, 0xFFFF, sum = 0
8991 12:17:34.805878 11, 0xFFFF, sum = 0
8992 12:17:34.805964 12, 0xFFFF, sum = 0
8993 12:17:34.809236 13, 0xFFFF, sum = 0
8994 12:17:34.809322 14, 0x0, sum = 1
8995 12:17:34.812585 15, 0x0, sum = 2
8996 12:17:34.812671 16, 0x0, sum = 3
8997 12:17:34.815904 17, 0x0, sum = 4
8998 12:17:34.815990 best_step = 15
8999 12:17:34.816057
9000 12:17:34.816119 ==
9001 12:17:34.819251 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 12:17:34.822518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 12:17:34.825746 ==
9004 12:17:34.825828 RX Vref Scan: 0
9005 12:17:34.825892
9006 12:17:34.828864 RX Vref 0 -> 0, step: 1
9007 12:17:34.828937
9008 12:17:34.832125 RX Delay 19 -> 252, step: 4
9009 12:17:34.835469 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
9010 12:17:34.838706 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
9011 12:17:34.841961 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
9012 12:17:34.845292 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9013 12:17:34.851987 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9014 12:17:34.855412 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9015 12:17:34.858685 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9016 12:17:34.861979 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
9017 12:17:34.865413 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9018 12:17:34.871961 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9019 12:17:34.875084 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9020 12:17:34.878328 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9021 12:17:34.881774 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9022 12:17:34.888014 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9023 12:17:34.891361 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9024 12:17:34.895059 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9025 12:17:34.895145 ==
9026 12:17:34.898102 Dram Type= 6, Freq= 0, CH_1, rank 1
9027 12:17:34.901275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9028 12:17:34.901363 ==
9029 12:17:34.905034 DQS Delay:
9030 12:17:34.905114 DQS0 = 0, DQS1 = 0
9031 12:17:34.905192 DQM Delay:
9032 12:17:34.908146 DQM0 = 134, DQM1 = 129
9033 12:17:34.908219 DQ Delay:
9034 12:17:34.911316 DQ0 =136, DQ1 =132, DQ2 =122, DQ3 =130
9035 12:17:34.914777 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
9036 12:17:34.921412 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9037 12:17:34.924645 DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =140
9038 12:17:34.924757
9039 12:17:34.924837
9040 12:17:34.924901
9041 12:17:34.927993 [DramC_TX_OE_Calibration] TA2
9042 12:17:34.931201 Original DQ_B0 (3 6) =30, OEN = 27
9043 12:17:34.934447 Original DQ_B1 (3 6) =30, OEN = 27
9044 12:17:34.934532 24, 0x0, End_B0=24 End_B1=24
9045 12:17:34.937849 25, 0x0, End_B0=25 End_B1=25
9046 12:17:34.941162 26, 0x0, End_B0=26 End_B1=26
9047 12:17:34.944448 27, 0x0, End_B0=27 End_B1=27
9048 12:17:34.944535 28, 0x0, End_B0=28 End_B1=28
9049 12:17:34.948090 29, 0x0, End_B0=29 End_B1=29
9050 12:17:34.950876 30, 0x0, End_B0=30 End_B1=30
9051 12:17:34.954442 31, 0x4141, End_B0=30 End_B1=30
9052 12:17:34.957924 Byte0 end_step=30 best_step=27
9053 12:17:34.960718 Byte1 end_step=30 best_step=27
9054 12:17:34.960815 Byte0 TX OE(2T, 0.5T) = (3, 3)
9055 12:17:34.964102 Byte1 TX OE(2T, 0.5T) = (3, 3)
9056 12:17:34.964179
9057 12:17:34.964243
9058 12:17:34.973962 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9059 12:17:34.977794 CH1 RK1: MR19=303, MR18=1E08
9060 12:17:34.984228 CH1_RK1: MR19=0x303, MR18=0x1E08, DQSOSC=394, MR23=63, INC=23, DEC=15
9061 12:17:34.984314 [RxdqsGatingPostProcess] freq 1600
9062 12:17:34.990473 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9063 12:17:34.994134 best DQS0 dly(2T, 0.5T) = (1, 1)
9064 12:17:34.997342 best DQS1 dly(2T, 0.5T) = (1, 1)
9065 12:17:35.000361 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9066 12:17:35.003682 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9067 12:17:35.007227 best DQS0 dly(2T, 0.5T) = (1, 1)
9068 12:17:35.010429 best DQS1 dly(2T, 0.5T) = (1, 1)
9069 12:17:35.013745 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9070 12:17:35.017043 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9071 12:17:35.020363 Pre-setting of DQS Precalculation
9072 12:17:35.023630 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9073 12:17:35.029911 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9074 12:17:35.036641 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9075 12:17:35.040040
9076 12:17:35.040143
9077 12:17:35.040210 [Calibration Summary] 3200 Mbps
9078 12:17:35.043223 CH 0, Rank 0
9079 12:17:35.043306 SW Impedance : PASS
9080 12:17:35.046455 DUTY Scan : NO K
9081 12:17:35.049609 ZQ Calibration : PASS
9082 12:17:35.049692 Jitter Meter : NO K
9083 12:17:35.052917 CBT Training : PASS
9084 12:17:35.056618 Write leveling : PASS
9085 12:17:35.056735 RX DQS gating : PASS
9086 12:17:35.059551 RX DQ/DQS(RDDQC) : PASS
9087 12:17:35.062996 TX DQ/DQS : PASS
9088 12:17:35.063092 RX DATLAT : PASS
9089 12:17:35.066229 RX DQ/DQS(Engine): PASS
9090 12:17:35.069403 TX OE : PASS
9091 12:17:35.069486 All Pass.
9092 12:17:35.069551
9093 12:17:35.069611 CH 0, Rank 1
9094 12:17:35.073109 SW Impedance : PASS
9095 12:17:35.075966 DUTY Scan : NO K
9096 12:17:35.076048 ZQ Calibration : PASS
9097 12:17:35.079326 Jitter Meter : NO K
9098 12:17:35.082964 CBT Training : PASS
9099 12:17:35.083047 Write leveling : PASS
9100 12:17:35.086239 RX DQS gating : PASS
9101 12:17:35.089666 RX DQ/DQS(RDDQC) : PASS
9102 12:17:35.089755 TX DQ/DQS : PASS
9103 12:17:35.092774 RX DATLAT : PASS
9104 12:17:35.092896 RX DQ/DQS(Engine): PASS
9105 12:17:35.095806 TX OE : PASS
9106 12:17:35.095923 All Pass.
9107 12:17:35.095996
9108 12:17:35.099225 CH 1, Rank 0
9109 12:17:35.102828 SW Impedance : PASS
9110 12:17:35.102923 DUTY Scan : NO K
9111 12:17:35.105980 ZQ Calibration : PASS
9112 12:17:35.106097 Jitter Meter : NO K
9113 12:17:35.109016 CBT Training : PASS
9114 12:17:35.112488 Write leveling : PASS
9115 12:17:35.112640 RX DQS gating : PASS
9116 12:17:35.115612 RX DQ/DQS(RDDQC) : PASS
9117 12:17:35.119177 TX DQ/DQS : PASS
9118 12:17:35.119332 RX DATLAT : PASS
9119 12:17:35.122400 RX DQ/DQS(Engine): PASS
9120 12:17:35.125776 TX OE : PASS
9121 12:17:35.125885 All Pass.
9122 12:17:35.125979
9123 12:17:35.126069 CH 1, Rank 1
9124 12:17:35.129102 SW Impedance : PASS
9125 12:17:35.132044 DUTY Scan : NO K
9126 12:17:35.132143 ZQ Calibration : PASS
9127 12:17:35.135361 Jitter Meter : NO K
9128 12:17:35.138577 CBT Training : PASS
9129 12:17:35.138692 Write leveling : PASS
9130 12:17:35.141844 RX DQS gating : PASS
9131 12:17:35.145223 RX DQ/DQS(RDDQC) : PASS
9132 12:17:35.145306 TX DQ/DQS : PASS
9133 12:17:35.148547 RX DATLAT : PASS
9134 12:17:35.151857 RX DQ/DQS(Engine): PASS
9135 12:17:35.151965 TX OE : PASS
9136 12:17:35.155072 All Pass.
9137 12:17:35.155196
9138 12:17:35.155301 DramC Write-DBI on
9139 12:17:35.158419 PER_BANK_REFRESH: Hybrid Mode
9140 12:17:35.158514 TX_TRACKING: ON
9141 12:17:35.168423 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9142 12:17:35.178334 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9143 12:17:35.184987 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9144 12:17:35.188360 [FAST_K] Save calibration result to emmc
9145 12:17:35.191672 sync common calibartion params.
9146 12:17:35.191791 sync cbt_mode0:1, 1:1
9147 12:17:35.195043 dram_init: ddr_geometry: 2
9148 12:17:35.198195 dram_init: ddr_geometry: 2
9149 12:17:35.198285 dram_init: ddr_geometry: 2
9150 12:17:35.201296 0:dram_rank_size:100000000
9151 12:17:35.205010 1:dram_rank_size:100000000
9152 12:17:35.211206 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9153 12:17:35.211299 DFS_SHUFFLE_HW_MODE: ON
9154 12:17:35.214721 dramc_set_vcore_voltage set vcore to 725000
9155 12:17:35.217801 Read voltage for 1600, 0
9156 12:17:35.217883 Vio18 = 0
9157 12:17:35.221251 Vcore = 725000
9158 12:17:35.221333 Vdram = 0
9159 12:17:35.221399 Vddq = 0
9160 12:17:35.224265 Vmddr = 0
9161 12:17:35.224388 switch to 3200 Mbps bootup
9162 12:17:35.228043 [DramcRunTimeConfig]
9163 12:17:35.228126 PHYPLL
9164 12:17:35.231249 DPM_CONTROL_AFTERK: ON
9165 12:17:35.231358 PER_BANK_REFRESH: ON
9166 12:17:35.234819 REFRESH_OVERHEAD_REDUCTION: ON
9167 12:17:35.237492 CMD_PICG_NEW_MODE: OFF
9168 12:17:35.237574 XRTWTW_NEW_MODE: ON
9169 12:17:35.240886 XRTRTR_NEW_MODE: ON
9170 12:17:35.240968 TX_TRACKING: ON
9171 12:17:35.244503 RDSEL_TRACKING: OFF
9172 12:17:35.247746 DQS Precalculation for DVFS: ON
9173 12:17:35.247863 RX_TRACKING: OFF
9174 12:17:35.251108 HW_GATING DBG: ON
9175 12:17:35.251190 ZQCS_ENABLE_LP4: ON
9176 12:17:35.254401 RX_PICG_NEW_MODE: ON
9177 12:17:35.254494 TX_PICG_NEW_MODE: ON
9178 12:17:35.257590 ENABLE_RX_DCM_DPHY: ON
9179 12:17:35.260899 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9180 12:17:35.264173 DUMMY_READ_FOR_TRACKING: OFF
9181 12:17:35.267602 !!! SPM_CONTROL_AFTERK: OFF
9182 12:17:35.267685 !!! SPM could not control APHY
9183 12:17:35.270735 IMPEDANCE_TRACKING: ON
9184 12:17:35.270838 TEMP_SENSOR: ON
9185 12:17:35.274004 HW_SAVE_FOR_SR: OFF
9186 12:17:35.277430 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9187 12:17:35.280684 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9188 12:17:35.283998 Read ODT Tracking: ON
9189 12:17:35.284080 Refresh Rate DeBounce: ON
9190 12:17:35.286935 DFS_NO_QUEUE_FLUSH: ON
9191 12:17:35.290645 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9192 12:17:35.293834 ENABLE_DFS_RUNTIME_MRW: OFF
9193 12:17:35.293917 DDR_RESERVE_NEW_MODE: ON
9194 12:17:35.297287 MR_CBT_SWITCH_FREQ: ON
9195 12:17:35.300105 =========================
9196 12:17:35.318174 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9197 12:17:35.321397 dram_init: ddr_geometry: 2
9198 12:17:35.339881 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9199 12:17:35.343294 dram_init: dram init end (result: 0)
9200 12:17:35.349973 DRAM-K: Full calibration passed in 24449 msecs
9201 12:17:35.353047 MRC: failed to locate region type 0.
9202 12:17:35.353124 DRAM rank0 size:0x100000000,
9203 12:17:35.356217 DRAM rank1 size=0x100000000
9204 12:17:35.366585 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9205 12:17:35.373114 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9206 12:17:35.379691 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9207 12:17:35.385901 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9208 12:17:35.389171 DRAM rank0 size:0x100000000,
9209 12:17:35.392945 DRAM rank1 size=0x100000000
9210 12:17:35.393060 CBMEM:
9211 12:17:35.396038 IMD: root @ 0xfffff000 254 entries.
9212 12:17:35.399237 IMD: root @ 0xffffec00 62 entries.
9213 12:17:35.402470 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9214 12:17:35.409205 WARNING: RO_VPD is uninitialized or empty.
9215 12:17:35.412395 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9216 12:17:35.420128 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9217 12:17:35.432537 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9218 12:17:35.443871 BS: romstage times (exec / console): total (unknown) / 23954 ms
9219 12:17:35.443985
9220 12:17:35.444062
9221 12:17:35.453737 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9222 12:17:35.457042 ARM64: Exception handlers installed.
9223 12:17:35.460516 ARM64: Testing exception
9224 12:17:35.463706 ARM64: Done test exception
9225 12:17:35.463817 Enumerating buses...
9226 12:17:35.466938 Show all devs... Before device enumeration.
9227 12:17:35.470337 Root Device: enabled 1
9228 12:17:35.473681 CPU_CLUSTER: 0: enabled 1
9229 12:17:35.473765 CPU: 00: enabled 1
9230 12:17:35.477129 Compare with tree...
9231 12:17:35.477214 Root Device: enabled 1
9232 12:17:35.480369 CPU_CLUSTER: 0: enabled 1
9233 12:17:35.483828 CPU: 00: enabled 1
9234 12:17:35.483912 Root Device scanning...
9235 12:17:35.487130 scan_static_bus for Root Device
9236 12:17:35.490403 CPU_CLUSTER: 0 enabled
9237 12:17:35.493925 scan_static_bus for Root Device done
9238 12:17:35.496973 scan_bus: bus Root Device finished in 8 msecs
9239 12:17:35.497058 done
9240 12:17:35.503375 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9241 12:17:35.506741 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9242 12:17:35.513407 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9243 12:17:35.516636 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9244 12:17:35.520038 Allocating resources...
9245 12:17:35.523452 Reading resources...
9246 12:17:35.526677 Root Device read_resources bus 0 link: 0
9247 12:17:35.529976 DRAM rank0 size:0x100000000,
9248 12:17:35.530052 DRAM rank1 size=0x100000000
9249 12:17:35.533307 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9250 12:17:35.536724 CPU: 00 missing read_resources
9251 12:17:35.543213 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9252 12:17:35.546472 Root Device read_resources bus 0 link: 0 done
9253 12:17:35.546582 Done reading resources.
9254 12:17:35.552863 Show resources in subtree (Root Device)...After reading.
9255 12:17:35.556474 Root Device child on link 0 CPU_CLUSTER: 0
9256 12:17:35.559752 CPU_CLUSTER: 0 child on link 0 CPU: 00
9257 12:17:35.569374 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9258 12:17:35.569479 CPU: 00
9259 12:17:35.572688 Root Device assign_resources, bus 0 link: 0
9260 12:17:35.575845 CPU_CLUSTER: 0 missing set_resources
9261 12:17:35.582693 Root Device assign_resources, bus 0 link: 0 done
9262 12:17:35.582810 Done setting resources.
9263 12:17:35.589358 Show resources in subtree (Root Device)...After assigning values.
9264 12:17:35.592624 Root Device child on link 0 CPU_CLUSTER: 0
9265 12:17:35.595878 CPU_CLUSTER: 0 child on link 0 CPU: 00
9266 12:17:35.605894 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9267 12:17:35.606005 CPU: 00
9268 12:17:35.609073 Done allocating resources.
9269 12:17:35.615675 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9270 12:17:35.615794 Enabling resources...
9271 12:17:35.615915 done.
9272 12:17:35.622341 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9273 12:17:35.625623 Initializing devices...
9274 12:17:35.625762 Root Device init
9275 12:17:35.628699 init hardware done!
9276 12:17:35.628785 0x00000018: ctrlr->caps
9277 12:17:35.632373 52.000 MHz: ctrlr->f_max
9278 12:17:35.635412 0.400 MHz: ctrlr->f_min
9279 12:17:35.635566 0x40ff8080: ctrlr->voltages
9280 12:17:35.638611 sclk: 390625
9281 12:17:35.638681 Bus Width = 1
9282 12:17:35.638747 sclk: 390625
9283 12:17:35.641833 Bus Width = 1
9284 12:17:35.645360 Early init status = 3
9285 12:17:35.648561 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9286 12:17:35.651673 in-header: 03 fc 00 00 01 00 00 00
9287 12:17:35.655107 in-data: 00
9288 12:17:35.658498 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9289 12:17:35.663084 in-header: 03 fd 00 00 00 00 00 00
9290 12:17:35.666422 in-data:
9291 12:17:35.669671 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9292 12:17:35.674322 in-header: 03 fc 00 00 01 00 00 00
9293 12:17:35.677408 in-data: 00
9294 12:17:35.680851 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9295 12:17:35.686390 in-header: 03 fd 00 00 00 00 00 00
9296 12:17:35.689798 in-data:
9297 12:17:35.693148 [SSUSB] Setting up USB HOST controller...
9298 12:17:35.696419 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9299 12:17:35.699729 [SSUSB] phy power-on done.
9300 12:17:35.703115 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9301 12:17:35.709597 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9302 12:17:35.712839 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9303 12:17:35.719483 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9304 12:17:35.726170 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9305 12:17:35.732657 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9306 12:17:35.739614 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9307 12:17:35.745614 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9308 12:17:35.749144 SPM: binary array size = 0x9dc
9309 12:17:35.752636 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9310 12:17:35.759117 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9311 12:17:35.765577 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9312 12:17:35.772317 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9313 12:17:35.775684 configure_display: Starting display init
9314 12:17:35.809768 anx7625_power_on_init: Init interface.
9315 12:17:35.812867 anx7625_disable_pd_protocol: Disabled PD feature.
9316 12:17:35.816410 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9317 12:17:35.844062 anx7625_start_dp_work: Secure OCM version=00
9318 12:17:35.847409 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9319 12:17:35.862309 sp_tx_get_edid_block: EDID Block = 1
9320 12:17:35.964962 Extracted contents:
9321 12:17:35.968052 header: 00 ff ff ff ff ff ff 00
9322 12:17:35.971159 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9323 12:17:35.974810 version: 01 04
9324 12:17:35.978041 basic params: 95 1f 11 78 0a
9325 12:17:35.981331 chroma info: 76 90 94 55 54 90 27 21 50 54
9326 12:17:35.984558 established: 00 00 00
9327 12:17:35.990970 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9328 12:17:35.997693 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9329 12:17:36.000930 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9330 12:17:36.007423 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9331 12:17:36.014206 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9332 12:17:36.017885 extensions: 00
9333 12:17:36.017978 checksum: fb
9334 12:17:36.018047
9335 12:17:36.023951 Manufacturer: IVO Model 57d Serial Number 0
9336 12:17:36.024086 Made week 0 of 2020
9337 12:17:36.027297 EDID version: 1.4
9338 12:17:36.027393 Digital display
9339 12:17:36.030661 6 bits per primary color channel
9340 12:17:36.033911 DisplayPort interface
9341 12:17:36.034006 Maximum image size: 31 cm x 17 cm
9342 12:17:36.037271 Gamma: 220%
9343 12:17:36.037358 Check DPMS levels
9344 12:17:36.043458 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9345 12:17:36.046797 First detailed timing is preferred timing
9346 12:17:36.050440 Established timings supported:
9347 12:17:36.050532 Standard timings supported:
9348 12:17:36.053489 Detailed timings
9349 12:17:36.056739 Hex of detail: 383680a07038204018303c0035ae10000019
9350 12:17:36.063370 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9351 12:17:36.066398 0780 0798 07c8 0820 hborder 0
9352 12:17:36.069946 0438 043b 0447 0458 vborder 0
9353 12:17:36.072993 -hsync -vsync
9354 12:17:36.073090 Did detailed timing
9355 12:17:36.079765 Hex of detail: 000000000000000000000000000000000000
9356 12:17:36.083019 Manufacturer-specified data, tag 0
9357 12:17:36.086371 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9358 12:17:36.089770 ASCII string: InfoVision
9359 12:17:36.092936 Hex of detail: 000000fe00523134304e574635205248200a
9360 12:17:36.096113 ASCII string: R140NWF5 RH
9361 12:17:36.096212 Checksum
9362 12:17:36.099469 Checksum: 0xfb (valid)
9363 12:17:36.102809 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9364 12:17:36.106050 DSI data_rate: 832800000 bps
9365 12:17:36.112573 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9366 12:17:36.115922 anx7625_parse_edid: pixelclock(138800).
9367 12:17:36.119244 hactive(1920), hsync(48), hfp(24), hbp(88)
9368 12:17:36.122676 vactive(1080), vsync(12), vfp(3), vbp(17)
9369 12:17:36.125961 anx7625_dsi_config: config dsi.
9370 12:17:36.132417 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9371 12:17:36.146690 anx7625_dsi_config: success to config DSI
9372 12:17:36.149982 anx7625_dp_start: MIPI phy setup OK.
9373 12:17:36.153343 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9374 12:17:36.156701 mtk_ddp_mode_set invalid vrefresh 60
9375 12:17:36.159973 main_disp_path_setup
9376 12:17:36.160067 ovl_layer_smi_id_en
9377 12:17:36.163414 ovl_layer_smi_id_en
9378 12:17:36.163494 ccorr_config
9379 12:17:36.163559 aal_config
9380 12:17:36.166439 gamma_config
9381 12:17:36.166518 postmask_config
9382 12:17:36.169694 dither_config
9383 12:17:36.173270 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9384 12:17:36.179855 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9385 12:17:36.183257 Root Device init finished in 554 msecs
9386 12:17:36.186368 CPU_CLUSTER: 0 init
9387 12:17:36.192936 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9388 12:17:36.199408 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9389 12:17:36.199491 APU_MBOX 0x190000b0 = 0x10001
9390 12:17:36.202723 APU_MBOX 0x190001b0 = 0x10001
9391 12:17:36.205959 APU_MBOX 0x190005b0 = 0x10001
9392 12:17:36.209306 APU_MBOX 0x190006b0 = 0x10001
9393 12:17:36.215900 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9394 12:17:36.225815 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9395 12:17:36.237954 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9396 12:17:36.244539 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9397 12:17:36.256255 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9398 12:17:36.265866 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9399 12:17:36.269032 CPU_CLUSTER: 0 init finished in 81 msecs
9400 12:17:36.272099 Devices initialized
9401 12:17:36.275338 Show all devs... After init.
9402 12:17:36.275419 Root Device: enabled 1
9403 12:17:36.278641 CPU_CLUSTER: 0: enabled 1
9404 12:17:36.282196 CPU: 00: enabled 1
9405 12:17:36.285220 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9406 12:17:36.288709 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9407 12:17:36.291640 ELOG: NV offset 0x57f000 size 0x1000
9408 12:17:36.298725 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9409 12:17:36.305129 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9410 12:17:36.308427 ELOG: Event(17) added with size 13 at 2023-06-06 12:17:39 UTC
9411 12:17:36.315099 out: cmd=0x121: 03 db 21 01 00 00 00 00
9412 12:17:36.318432 in-header: 03 63 00 00 2c 00 00 00
9413 12:17:36.331649 in-data: fd 67 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9414 12:17:36.334786 ELOG: Event(A1) added with size 10 at 2023-06-06 12:17:39 UTC
9415 12:17:36.344612 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9416 12:17:36.347908 ELOG: Event(A0) added with size 9 at 2023-06-06 12:17:39 UTC
9417 12:17:36.351273 elog_add_boot_reason: Logged dev mode boot
9418 12:17:36.357946 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9419 12:17:36.360791 Finalize devices...
9420 12:17:36.360890 Devices finalized
9421 12:17:36.367442 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9422 12:17:36.370755 Writing coreboot table at 0xffe64000
9423 12:17:36.374308 0. 000000000010a000-0000000000113fff: RAMSTAGE
9424 12:17:36.377489 1. 0000000040000000-00000000400fffff: RAM
9425 12:17:36.380638 2. 0000000040100000-000000004032afff: RAMSTAGE
9426 12:17:36.384429 3. 000000004032b000-00000000545fffff: RAM
9427 12:17:36.390453 4. 0000000054600000-000000005465ffff: BL31
9428 12:17:36.393989 5. 0000000054660000-00000000ffe63fff: RAM
9429 12:17:36.397166 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9430 12:17:36.400540 7. 0000000100000000-000000023fffffff: RAM
9431 12:17:36.403531 Passing 5 GPIOs to payload:
9432 12:17:36.410341 NAME | PORT | POLARITY | VALUE
9433 12:17:36.413635 EC in RW | 0x000000aa | low | undefined
9434 12:17:36.416879 EC interrupt | 0x00000005 | low | undefined
9435 12:17:36.423592 TPM interrupt | 0x000000ab | high | undefined
9436 12:17:36.427035 SD card detect | 0x00000011 | high | undefined
9437 12:17:36.433663 speaker enable | 0x00000093 | high | undefined
9438 12:17:36.436965 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9439 12:17:36.440172 in-header: 03 f9 00 00 02 00 00 00
9440 12:17:36.440256 in-data: 02 00
9441 12:17:36.443439 ADC[4]: Raw value=901032 ID=7
9442 12:17:36.446798 ADC[3]: Raw value=213179 ID=1
9443 12:17:36.446876 RAM Code: 0x71
9444 12:17:36.450100 ADC[6]: Raw value=74502 ID=0
9445 12:17:36.453452 ADC[5]: Raw value=212441 ID=1
9446 12:17:36.453538 SKU Code: 0x1
9447 12:17:36.460019 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9448 12:17:36.463273 coreboot table: 964 bytes.
9449 12:17:36.466494 IMD ROOT 0. 0xfffff000 0x00001000
9450 12:17:36.469793 IMD SMALL 1. 0xffffe000 0x00001000
9451 12:17:36.473044 RO MCACHE 2. 0xffffc000 0x00001104
9452 12:17:36.476308 CONSOLE 3. 0xfff7c000 0x00080000
9453 12:17:36.479628 FMAP 4. 0xfff7b000 0x00000452
9454 12:17:36.482865 TIME STAMP 5. 0xfff7a000 0x00000910
9455 12:17:36.486430 VBOOT WORK 6. 0xfff66000 0x00014000
9456 12:17:36.489698 RAMOOPS 7. 0xffe66000 0x00100000
9457 12:17:36.493360 COREBOOT 8. 0xffe64000 0x00002000
9458 12:17:36.493446 IMD small region:
9459 12:17:36.496466 IMD ROOT 0. 0xffffec00 0x00000400
9460 12:17:36.499678 VPD 1. 0xffffeba0 0x0000004c
9461 12:17:36.502974 MMC STATUS 2. 0xffffeb80 0x00000004
9462 12:17:36.510032 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9463 12:17:36.510143 Probing TPM: done!
9464 12:17:36.516373 Connected to device vid:did:rid of 1ae0:0028:00
9465 12:17:36.526341 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9466 12:17:36.530081 Initialized TPM device CR50 revision 0
9467 12:17:36.530190 Checking cr50 for pending updates
9468 12:17:36.536374 Reading cr50 TPM mode
9469 12:17:36.544752 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9470 12:17:36.551449 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9471 12:17:36.591601 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9472 12:17:36.595087 Checking segment from ROM address 0x40100000
9473 12:17:36.598395 Checking segment from ROM address 0x4010001c
9474 12:17:36.604899 Loading segment from ROM address 0x40100000
9475 12:17:36.604986 code (compression=0)
9476 12:17:36.614796 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9477 12:17:36.621445 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9478 12:17:36.621530 it's not compressed!
9479 12:17:36.628017 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9480 12:17:36.634726 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9481 12:17:36.652070 Loading segment from ROM address 0x4010001c
9482 12:17:36.652165 Entry Point 0x80000000
9483 12:17:36.655446 Loaded segments
9484 12:17:36.658306 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9485 12:17:36.664886 Jumping to boot code at 0x80000000(0xffe64000)
9486 12:17:36.671580 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9487 12:17:36.678330 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9488 12:17:36.686296 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9489 12:17:36.689545 Checking segment from ROM address 0x40100000
9490 12:17:36.692712 Checking segment from ROM address 0x4010001c
9491 12:17:36.699527 Loading segment from ROM address 0x40100000
9492 12:17:36.699611 code (compression=1)
9493 12:17:36.706087 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9494 12:17:36.716074 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9495 12:17:36.716159 using LZMA
9496 12:17:36.724649 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9497 12:17:36.731299 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9498 12:17:36.734567 Loading segment from ROM address 0x4010001c
9499 12:17:36.734677 Entry Point 0x54601000
9500 12:17:36.737921 Loaded segments
9501 12:17:36.741281 NOTICE: MT8192 bl31_setup
9502 12:17:36.748384 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9503 12:17:36.751539 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9504 12:17:36.754819 WARNING: region 0:
9505 12:17:36.758190 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 12:17:36.758297 WARNING: region 1:
9507 12:17:36.764723 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9508 12:17:36.768158 WARNING: region 2:
9509 12:17:36.771433 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9510 12:17:36.774810 WARNING: region 3:
9511 12:17:36.778067 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9512 12:17:36.781483 WARNING: region 4:
9513 12:17:36.788114 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9514 12:17:36.788222 WARNING: region 5:
9515 12:17:36.791374 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9516 12:17:36.794630 WARNING: region 6:
9517 12:17:36.798065 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 12:17:36.801344 WARNING: region 7:
9519 12:17:36.804709 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9520 12:17:36.811477 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9521 12:17:36.814621 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9522 12:17:36.817709 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9523 12:17:36.824319 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9524 12:17:36.827732 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9525 12:17:36.834518 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9526 12:17:36.837722 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9527 12:17:36.841010 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9528 12:17:36.847538 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9529 12:17:36.851022 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9530 12:17:36.854275 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9531 12:17:36.861086 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9532 12:17:36.864353 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9533 12:17:36.870951 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9534 12:17:36.874219 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9535 12:17:36.877591 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9536 12:17:36.884190 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9537 12:17:36.887484 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9538 12:17:36.894036 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9539 12:17:36.897392 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9540 12:17:36.900728 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9541 12:17:36.907409 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9542 12:17:36.910465 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9543 12:17:36.913935 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9544 12:17:36.920637 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9545 12:17:36.923609 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9546 12:17:36.930164 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9547 12:17:36.933652 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9548 12:17:36.940617 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9549 12:17:36.943741 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9550 12:17:36.947201 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9551 12:17:36.953499 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9552 12:17:36.956716 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9553 12:17:36.960433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9554 12:17:36.963788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9555 12:17:36.970398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9556 12:17:36.973796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9557 12:17:36.977170 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9558 12:17:36.979927 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9559 12:17:36.986517 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9560 12:17:36.989818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9561 12:17:36.993176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9562 12:17:36.999676 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9563 12:17:37.002880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9564 12:17:37.006317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9565 12:17:37.009732 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9566 12:17:37.016307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9567 12:17:37.019602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9568 12:17:37.022989 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9569 12:17:37.029434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9570 12:17:37.032951 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9571 12:17:37.039599 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9572 12:17:37.042719 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9573 12:17:37.046118 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9574 12:17:37.052605 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9575 12:17:37.056152 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9576 12:17:37.062761 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9577 12:17:37.065925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9578 12:17:37.072620 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9579 12:17:37.075999 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9580 12:17:37.082207 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9581 12:17:37.085525 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9582 12:17:37.092118 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9583 12:17:37.095919 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9584 12:17:37.098801 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9585 12:17:37.105736 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9586 12:17:37.109025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9587 12:17:37.115634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9588 12:17:37.118979 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9589 12:17:37.125361 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9590 12:17:37.128609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9591 12:17:37.131922 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9592 12:17:37.138977 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9593 12:17:37.142085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9594 12:17:37.148581 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9595 12:17:37.151640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9596 12:17:37.158146 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9597 12:17:37.161759 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9598 12:17:37.168190 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9599 12:17:37.171881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9600 12:17:37.178550 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9601 12:17:37.181983 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9602 12:17:37.185277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9603 12:17:37.191846 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9604 12:17:37.195147 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9605 12:17:37.201936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9606 12:17:37.205229 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9607 12:17:37.208529 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9608 12:17:37.214792 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9609 12:17:37.218030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9610 12:17:37.224869 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9611 12:17:37.228215 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9612 12:17:37.234495 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9613 12:17:37.237760 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9614 12:17:37.244525 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9615 12:17:37.248248 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9616 12:17:37.251216 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9617 12:17:37.257855 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9618 12:17:37.261222 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9619 12:17:37.264830 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9620 12:17:37.267912 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9621 12:17:37.274519 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9622 12:17:37.278271 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9623 12:17:37.284875 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9624 12:17:37.287798 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9625 12:17:37.291251 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9626 12:17:37.297951 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9627 12:17:37.301262 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9628 12:17:37.307908 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9629 12:17:37.311097 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9630 12:17:37.314310 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9631 12:17:37.321005 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9632 12:17:37.324421 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9633 12:17:37.330885 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9634 12:17:37.334196 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9635 12:17:37.337984 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9636 12:17:37.341278 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9637 12:17:37.347781 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9638 12:17:37.351151 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9639 12:17:37.354346 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9640 12:17:37.361043 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9641 12:17:37.364579 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9642 12:17:37.367707 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9643 12:17:37.371241 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9644 12:17:37.377564 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9645 12:17:37.381323 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9646 12:17:37.387471 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9647 12:17:37.391209 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9648 12:17:37.394499 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9649 12:17:37.401109 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9650 12:17:37.404478 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9651 12:17:37.410622 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9652 12:17:37.413889 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9653 12:17:37.417635 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9654 12:17:37.424150 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9655 12:17:37.427531 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9656 12:17:37.434077 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9657 12:17:37.437385 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9658 12:17:37.440637 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9659 12:17:37.447096 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9660 12:17:37.450464 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9661 12:17:37.457146 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9662 12:17:37.460422 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9663 12:17:37.463916 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9664 12:17:37.470415 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9665 12:17:37.473918 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9666 12:17:37.477392 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9667 12:17:37.484015 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9668 12:17:37.487080 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9669 12:17:37.493899 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9670 12:17:37.497263 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9671 12:17:37.500485 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9672 12:17:37.507155 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9673 12:17:37.510530 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9674 12:17:37.517235 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9675 12:17:37.520333 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9676 12:17:37.523666 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9677 12:17:37.530263 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9678 12:17:37.533528 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9679 12:17:37.540472 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9680 12:17:37.543772 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9681 12:17:37.546970 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9682 12:17:37.553549 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9683 12:17:37.556893 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9684 12:17:37.563113 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9685 12:17:37.566439 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9686 12:17:37.569993 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9687 12:17:37.576685 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9688 12:17:37.579824 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9689 12:17:37.586560 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9690 12:17:37.589641 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9691 12:17:37.593231 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9692 12:17:37.599956 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9693 12:17:37.603331 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9694 12:17:37.606667 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9695 12:17:37.612975 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9696 12:17:37.616225 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9697 12:17:37.623060 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9698 12:17:37.626228 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9699 12:17:37.629569 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9700 12:17:37.636156 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9701 12:17:37.639459 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9702 12:17:37.645949 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9703 12:17:37.649167 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9704 12:17:37.652969 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9705 12:17:37.659553 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9706 12:17:37.662855 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9707 12:17:37.669497 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9708 12:17:37.672672 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9709 12:17:37.675855 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9710 12:17:37.682376 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9711 12:17:37.685856 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9712 12:17:37.692604 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9713 12:17:37.695673 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9714 12:17:37.702499 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9715 12:17:37.705850 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9716 12:17:37.709234 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9717 12:17:37.715886 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9718 12:17:37.719231 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9719 12:17:37.725832 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9720 12:17:37.728996 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9721 12:17:37.732332 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9722 12:17:37.739066 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9723 12:17:37.741890 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9724 12:17:37.748629 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9725 12:17:37.751918 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9726 12:17:37.758591 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9727 12:17:37.761878 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9728 12:17:37.765121 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9729 12:17:37.771671 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9730 12:17:37.775009 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9731 12:17:37.781845 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9732 12:17:37.785028 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9733 12:17:37.791495 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9734 12:17:37.794994 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9735 12:17:37.798182 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9736 12:17:37.804998 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9737 12:17:37.808409 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9738 12:17:37.814585 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9739 12:17:37.817933 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9740 12:17:37.824705 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9741 12:17:37.827965 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9742 12:17:37.831536 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9743 12:17:37.837997 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9744 12:17:37.841343 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9745 12:17:37.848008 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9746 12:17:37.851077 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9747 12:17:37.857627 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9748 12:17:37.860923 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9749 12:17:37.864257 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9750 12:17:37.867340 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9751 12:17:37.874096 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9752 12:17:37.877400 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9753 12:17:37.880732 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9754 12:17:37.884039 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9755 12:17:37.890798 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9756 12:17:37.893972 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9757 12:17:37.900881 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9758 12:17:37.903980 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9759 12:17:37.907133 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9760 12:17:37.913898 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9761 12:17:37.917163 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9762 12:17:37.923954 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9763 12:17:37.927235 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9764 12:17:37.930540 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9765 12:17:37.936913 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9766 12:17:37.940458 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9767 12:17:37.943801 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9768 12:17:37.949980 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9769 12:17:37.953664 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9770 12:17:37.956672 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9771 12:17:37.963364 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9772 12:17:37.966687 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9773 12:17:37.970014 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9774 12:17:37.976672 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9775 12:17:37.979992 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9776 12:17:37.986776 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9777 12:17:37.990184 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9778 12:17:37.993305 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9779 12:17:38.000066 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9780 12:17:38.003055 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9781 12:17:38.009712 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9782 12:17:38.013312 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9783 12:17:38.016330 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9784 12:17:38.023019 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9785 12:17:38.026317 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9786 12:17:38.029632 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9787 12:17:38.036321 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9788 12:17:38.039488 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9789 12:17:38.042746 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9790 12:17:38.046093 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9791 12:17:38.052700 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9792 12:17:38.055980 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9793 12:17:38.059142 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9794 12:17:38.062848 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9795 12:17:38.069379 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9796 12:17:38.072770 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9797 12:17:38.075934 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9798 12:17:38.079270 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9799 12:17:38.085890 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9800 12:17:38.089158 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9801 12:17:38.092468 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9802 12:17:38.099060 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9803 12:17:38.102163 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9804 12:17:38.109021 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9805 12:17:38.112149 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9806 12:17:38.118996 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9807 12:17:38.121924 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9808 12:17:38.125260 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9809 12:17:38.131997 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9810 12:17:38.135321 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9811 12:17:38.138541 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9812 12:17:38.145456 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9813 12:17:38.148743 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9814 12:17:38.155078 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9815 12:17:38.158345 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9816 12:17:38.165156 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9817 12:17:38.168577 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9818 12:17:38.171792 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9819 12:17:38.178305 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9820 12:17:38.181897 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9821 12:17:38.188185 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9822 12:17:38.191421 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9823 12:17:38.198248 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9824 12:17:38.201546 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9825 12:17:38.204690 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9826 12:17:38.211227 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9827 12:17:38.214357 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9828 12:17:38.221332 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9829 12:17:38.224609 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9830 12:17:38.227684 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9831 12:17:38.234144 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9832 12:17:38.237896 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9833 12:17:38.244344 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9834 12:17:38.247794 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9835 12:17:38.251011 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9836 12:17:38.257737 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9837 12:17:38.261029 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9838 12:17:38.267534 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9839 12:17:38.270743 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9840 12:17:38.277402 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9841 12:17:38.280717 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9842 12:17:38.284130 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9843 12:17:38.290548 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9844 12:17:38.293860 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9845 12:17:38.300398 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9846 12:17:38.303763 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9847 12:17:38.307087 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9848 12:17:38.313778 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9849 12:17:38.316984 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9850 12:17:38.323942 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9851 12:17:38.326914 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9852 12:17:38.333458 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9853 12:17:38.337056 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9854 12:17:38.340367 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9855 12:17:38.347083 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9856 12:17:38.350360 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9857 12:17:38.356952 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9858 12:17:38.360240 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9859 12:17:38.363545 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9860 12:17:38.370139 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9861 12:17:38.373294 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9862 12:17:38.379876 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9863 12:17:38.383248 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9864 12:17:38.389804 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9865 12:17:38.393231 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9866 12:17:38.396421 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9867 12:17:38.403068 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9868 12:17:38.406339 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9869 12:17:38.412964 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9870 12:17:38.416271 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9871 12:17:38.419562 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9872 12:17:38.425934 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9873 12:17:38.429204 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9874 12:17:38.435838 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9875 12:17:38.438959 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9876 12:17:38.445552 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9877 12:17:38.449281 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9878 12:17:38.455570 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9879 12:17:38.459028 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9880 12:17:38.462360 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9881 12:17:38.469023 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9882 12:17:38.472246 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9883 12:17:38.478700 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9884 12:17:38.482048 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9885 12:17:38.488810 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9886 12:17:38.492189 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9887 12:17:38.498357 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9888 12:17:38.501654 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9889 12:17:38.504966 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9890 12:17:38.511416 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9891 12:17:38.514867 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9892 12:17:38.521540 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9893 12:17:38.524807 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9894 12:17:38.531484 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9895 12:17:38.534553 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9896 12:17:38.541485 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9897 12:17:38.544951 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9898 12:17:38.548067 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9899 12:17:38.554440 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9900 12:17:38.558077 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9901 12:17:38.564587 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9902 12:17:38.567763 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9903 12:17:38.574384 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9904 12:17:38.577805 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9905 12:17:38.580954 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9906 12:17:38.587602 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9907 12:17:38.590858 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9908 12:17:38.597445 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9909 12:17:38.600724 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9910 12:17:38.607284 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9911 12:17:38.610746 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9912 12:17:38.617387 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9913 12:17:38.620605 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9914 12:17:38.623874 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9915 12:17:38.630626 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9916 12:17:38.633885 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9917 12:17:38.640441 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9918 12:17:38.643984 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9919 12:17:38.650371 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9920 12:17:38.653509 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9921 12:17:38.657055 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9922 12:17:38.663509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9923 12:17:38.666909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9924 12:17:38.673398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9925 12:17:38.677057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9926 12:17:38.683180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9927 12:17:38.686767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9928 12:17:38.693054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9929 12:17:38.696310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9930 12:17:38.702945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9931 12:17:38.706337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9932 12:17:38.712886 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9933 12:17:38.716124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9934 12:17:38.722721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9935 12:17:38.725967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9936 12:17:38.732457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9937 12:17:38.735777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9938 12:17:38.742621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9939 12:17:38.746037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9940 12:17:38.752460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9941 12:17:38.756017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9942 12:17:38.762663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9943 12:17:38.765910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9944 12:17:38.772408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9945 12:17:38.775731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9946 12:17:38.782272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9947 12:17:38.785744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9948 12:17:38.792380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9949 12:17:38.795692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9950 12:17:38.802031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9951 12:17:38.805279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9952 12:17:38.811913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9953 12:17:38.815323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9954 12:17:38.818565 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9955 12:17:38.821940 INFO: [APUAPC] vio 0
9956 12:17:38.828600 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9957 12:17:38.831982 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9958 12:17:38.835364 INFO: [APUAPC] D0_APC_0: 0x400510
9959 12:17:38.838260 INFO: [APUAPC] D0_APC_1: 0x0
9960 12:17:38.841612 INFO: [APUAPC] D0_APC_2: 0x1540
9961 12:17:38.845023 INFO: [APUAPC] D0_APC_3: 0x0
9962 12:17:38.848199 INFO: [APUAPC] D1_APC_0: 0xffffffff
9963 12:17:38.851845 INFO: [APUAPC] D1_APC_1: 0xffffffff
9964 12:17:38.854702 INFO: [APUAPC] D1_APC_2: 0x3fffff
9965 12:17:38.858174 INFO: [APUAPC] D1_APC_3: 0x0
9966 12:17:38.861230 INFO: [APUAPC] D2_APC_0: 0xffffffff
9967 12:17:38.864819 INFO: [APUAPC] D2_APC_1: 0xffffffff
9968 12:17:38.868255 INFO: [APUAPC] D2_APC_2: 0x3fffff
9969 12:17:38.871366 INFO: [APUAPC] D2_APC_3: 0x0
9970 12:17:38.874498 INFO: [APUAPC] D3_APC_0: 0xffffffff
9971 12:17:38.877889 INFO: [APUAPC] D3_APC_1: 0xffffffff
9972 12:17:38.881161 INFO: [APUAPC] D3_APC_2: 0x3fffff
9973 12:17:38.881245 INFO: [APUAPC] D3_APC_3: 0x0
9974 12:17:38.887695 INFO: [APUAPC] D4_APC_0: 0xffffffff
9975 12:17:38.891001 INFO: [APUAPC] D4_APC_1: 0xffffffff
9976 12:17:38.894638 INFO: [APUAPC] D4_APC_2: 0x3fffff
9977 12:17:38.894722 INFO: [APUAPC] D4_APC_3: 0x0
9978 12:17:38.897871 INFO: [APUAPC] D5_APC_0: 0xffffffff
9979 12:17:38.904554 INFO: [APUAPC] D5_APC_1: 0xffffffff
9980 12:17:38.907956 INFO: [APUAPC] D5_APC_2: 0x3fffff
9981 12:17:38.908040 INFO: [APUAPC] D5_APC_3: 0x0
9982 12:17:38.911217 INFO: [APUAPC] D6_APC_0: 0xffffffff
9983 12:17:38.914456 INFO: [APUAPC] D6_APC_1: 0xffffffff
9984 12:17:38.917772 INFO: [APUAPC] D6_APC_2: 0x3fffff
9985 12:17:38.921085 INFO: [APUAPC] D6_APC_3: 0x0
9986 12:17:38.924475 INFO: [APUAPC] D7_APC_0: 0xffffffff
9987 12:17:38.927363 INFO: [APUAPC] D7_APC_1: 0xffffffff
9988 12:17:38.930583 INFO: [APUAPC] D7_APC_2: 0x3fffff
9989 12:17:38.933967 INFO: [APUAPC] D7_APC_3: 0x0
9990 12:17:38.937282 INFO: [APUAPC] D8_APC_0: 0xffffffff
9991 12:17:38.940483 INFO: [APUAPC] D8_APC_1: 0xffffffff
9992 12:17:38.943819 INFO: [APUAPC] D8_APC_2: 0x3fffff
9993 12:17:38.947216 INFO: [APUAPC] D8_APC_3: 0x0
9994 12:17:38.950586 INFO: [APUAPC] D9_APC_0: 0xffffffff
9995 12:17:38.953793 INFO: [APUAPC] D9_APC_1: 0xffffffff
9996 12:17:38.957136 INFO: [APUAPC] D9_APC_2: 0x3fffff
9997 12:17:38.960429 INFO: [APUAPC] D9_APC_3: 0x0
9998 12:17:38.963627 INFO: [APUAPC] D10_APC_0: 0xffffffff
9999 12:17:38.966875 INFO: [APUAPC] D10_APC_1: 0xffffffff
10000 12:17:38.970485 INFO: [APUAPC] D10_APC_2: 0x3fffff
10001 12:17:38.973672 INFO: [APUAPC] D10_APC_3: 0x0
10002 12:17:38.977194 INFO: [APUAPC] D11_APC_0: 0xffffffff
10003 12:17:38.980220 INFO: [APUAPC] D11_APC_1: 0xffffffff
10004 12:17:38.983308 INFO: [APUAPC] D11_APC_2: 0x3fffff
10005 12:17:38.986907 INFO: [APUAPC] D11_APC_3: 0x0
10006 12:17:38.990133 INFO: [APUAPC] D12_APC_0: 0xffffffff
10007 12:17:38.993499 INFO: [APUAPC] D12_APC_1: 0xffffffff
10008 12:17:38.996683 INFO: [APUAPC] D12_APC_2: 0x3fffff
10009 12:17:39.000074 INFO: [APUAPC] D12_APC_3: 0x0
10010 12:17:39.002921 INFO: [APUAPC] D13_APC_0: 0xffffffff
10011 12:17:39.009488 INFO: [APUAPC] D13_APC_1: 0xffffffff
10012 12:17:39.012710 INFO: [APUAPC] D13_APC_2: 0x3fffff
10013 12:17:39.012805 INFO: [APUAPC] D13_APC_3: 0x0
10014 12:17:39.016039 INFO: [APUAPC] D14_APC_0: 0xffffffff
10015 12:17:39.022734 INFO: [APUAPC] D14_APC_1: 0xffffffff
10016 12:17:39.025970 INFO: [APUAPC] D14_APC_2: 0x3fffff
10017 12:17:39.026054 INFO: [APUAPC] D14_APC_3: 0x0
10018 12:17:39.032591 INFO: [APUAPC] D15_APC_0: 0xffffffff
10019 12:17:39.035999 INFO: [APUAPC] D15_APC_1: 0xffffffff
10020 12:17:39.039309 INFO: [APUAPC] D15_APC_2: 0x3fffff
10021 12:17:39.042744 INFO: [APUAPC] D15_APC_3: 0x0
10022 12:17:39.042817 INFO: [APUAPC] APC_CON: 0x4
10023 12:17:39.046197 INFO: [NOCDAPC] D0_APC_0: 0x0
10024 12:17:39.049481 INFO: [NOCDAPC] D0_APC_1: 0x0
10025 12:17:39.052759 INFO: [NOCDAPC] D1_APC_0: 0x0
10026 12:17:39.056066 INFO: [NOCDAPC] D1_APC_1: 0xfff
10027 12:17:39.059291 INFO: [NOCDAPC] D2_APC_0: 0x0
10028 12:17:39.062661 INFO: [NOCDAPC] D2_APC_1: 0xfff
10029 12:17:39.065504 INFO: [NOCDAPC] D3_APC_0: 0x0
10030 12:17:39.068984 INFO: [NOCDAPC] D3_APC_1: 0xfff
10031 12:17:39.072278 INFO: [NOCDAPC] D4_APC_0: 0x0
10032 12:17:39.072364 INFO: [NOCDAPC] D4_APC_1: 0xfff
10033 12:17:39.075624 INFO: [NOCDAPC] D5_APC_0: 0x0
10034 12:17:39.078730 INFO: [NOCDAPC] D5_APC_1: 0xfff
10035 12:17:39.082168 INFO: [NOCDAPC] D6_APC_0: 0x0
10036 12:17:39.085476 INFO: [NOCDAPC] D6_APC_1: 0xfff
10037 12:17:39.088526 INFO: [NOCDAPC] D7_APC_0: 0x0
10038 12:17:39.092063 INFO: [NOCDAPC] D7_APC_1: 0xfff
10039 12:17:39.095237 INFO: [NOCDAPC] D8_APC_0: 0x0
10040 12:17:39.098580 INFO: [NOCDAPC] D8_APC_1: 0xfff
10041 12:17:39.101875 INFO: [NOCDAPC] D9_APC_0: 0x0
10042 12:17:39.105012 INFO: [NOCDAPC] D9_APC_1: 0xfff
10043 12:17:39.108348 INFO: [NOCDAPC] D10_APC_0: 0x0
10044 12:17:39.111836 INFO: [NOCDAPC] D10_APC_1: 0xfff
10045 12:17:39.111913 INFO: [NOCDAPC] D11_APC_0: 0x0
10046 12:17:39.115260 INFO: [NOCDAPC] D11_APC_1: 0xfff
10047 12:17:39.118507 INFO: [NOCDAPC] D12_APC_0: 0x0
10048 12:17:39.121891 INFO: [NOCDAPC] D12_APC_1: 0xfff
10049 12:17:39.125279 INFO: [NOCDAPC] D13_APC_0: 0x0
10050 12:17:39.128627 INFO: [NOCDAPC] D13_APC_1: 0xfff
10051 12:17:39.131514 INFO: [NOCDAPC] D14_APC_0: 0x0
10052 12:17:39.134855 INFO: [NOCDAPC] D14_APC_1: 0xfff
10053 12:17:39.138543 INFO: [NOCDAPC] D15_APC_0: 0x0
10054 12:17:39.141337 INFO: [NOCDAPC] D15_APC_1: 0xfff
10055 12:17:39.144672 INFO: [NOCDAPC] APC_CON: 0x4
10056 12:17:39.148104 INFO: [APUAPC] set_apusys_apc done
10057 12:17:39.151369 INFO: [DEVAPC] devapc_init done
10058 12:17:39.154660 INFO: GICv3 without legacy support detected.
10059 12:17:39.158039 INFO: ARM GICv3 driver initialized in EL3
10060 12:17:39.161728 INFO: Maximum SPI INTID supported: 639
10061 12:17:39.167854 INFO: BL31: Initializing runtime services
10062 12:17:39.171197 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10063 12:17:39.174850 INFO: SPM: enable CPC mode
10064 12:17:39.181321 INFO: mcdi ready for mcusys-off-idle and system suspend
10065 12:17:39.184365 INFO: BL31: Preparing for EL3 exit to normal world
10066 12:17:39.187907 INFO: Entry point address = 0x80000000
10067 12:17:39.191034 INFO: SPSR = 0x8
10068 12:17:39.196350
10069 12:17:39.196426
10070 12:17:39.196506
10071 12:17:39.199392 Starting depthcharge on Spherion...
10072 12:17:39.199480
10073 12:17:39.199564 Wipe memory regions:
10074 12:17:39.199642
10075 12:17:39.200453 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10076 12:17:39.200593 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10077 12:17:39.200719 Setting prompt string to ['asurada:']
10078 12:17:39.200878 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10079 12:17:39.202687 [0x00000040000000, 0x00000054600000)
10080 12:17:39.325007
10081 12:17:39.325149 [0x00000054660000, 0x00000080000000)
10082 12:17:39.586050
10083 12:17:39.586199 [0x000000821a7280, 0x000000ffe64000)
10084 12:17:40.330454
10085 12:17:40.330632 [0x00000100000000, 0x00000240000000)
10086 12:17:42.221151
10087 12:17:42.223996 Initializing XHCI USB controller at 0x11200000.
10088 12:17:43.262270
10089 12:17:43.265115 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10090 12:17:43.265208
10091 12:17:43.265274
10092 12:17:43.265333
10093 12:17:43.265612 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10095 12:17:43.365985 asurada: tftpboot 192.168.201.1 10605441/tftp-deploy-gxdu5qj5/kernel/image.itb 10605441/tftp-deploy-gxdu5qj5/kernel/cmdline
10096 12:17:43.366135 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10097 12:17:43.366239 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10098 12:17:43.370237 tftpboot 192.168.201.1 10605441/tftp-deploy-gxdu5qj5/kernel/image.itp-deploy-gxdu5qj5/kernel/cmdline
10099 12:17:43.370323
10100 12:17:43.370389 Waiting for link
10101 12:17:43.530847
10102 12:17:43.530984 R8152: Initializing
10103 12:17:43.531052
10104 12:17:43.533851 Version 9 (ocp_data = 6010)
10105 12:17:43.533935
10106 12:17:43.537003 R8152: Done initializing
10107 12:17:43.537085
10108 12:17:43.537148 Adding net device
10109 12:17:45.483220
10110 12:17:45.483390 done.
10111 12:17:45.483462
10112 12:17:45.483523 MAC: 00:e0:4c:72:2d:d6
10113 12:17:45.483583
10114 12:17:45.486537 Sending DHCP discover... done.
10115 12:17:45.486617
10116 12:17:45.489918 Waiting for reply... done.
10117 12:17:45.490030
10118 12:17:45.493112 Sending DHCP request... done.
10119 12:17:45.493189
10120 12:17:45.498979 Waiting for reply... done.
10121 12:17:45.499081
10122 12:17:45.499180 My ip is 192.168.201.21
10123 12:17:45.499270
10124 12:17:45.502307 The DHCP server ip is 192.168.201.1
10125 12:17:45.502402
10126 12:17:45.509048 TFTP server IP predefined by user: 192.168.201.1
10127 12:17:45.509127
10128 12:17:45.515267 Bootfile predefined by user: 10605441/tftp-deploy-gxdu5qj5/kernel/image.itb
10129 12:17:45.515344
10130 12:17:45.515410 Sending tftp read request... done.
10131 12:17:45.518727
10132 12:17:45.518862 Waiting for the transfer...
10133 12:17:45.522030
10134 12:17:45.784865 00000000 ################################################################
10135 12:17:45.785021
10136 12:17:46.068455 00080000 ################################################################
10137 12:17:46.068604
10138 12:17:46.326622 00100000 ################################################################
10139 12:17:46.326777
10140 12:17:46.598563 00180000 ################################################################
10141 12:17:46.598739
10142 12:17:46.858868 00200000 ################################################################
10143 12:17:46.859044
10144 12:17:47.130166 00280000 ################################################################
10145 12:17:47.130359
10146 12:17:47.379788 00300000 ################################################################
10147 12:17:47.379940
10148 12:17:47.645026 00380000 ################################################################
10149 12:17:47.645179
10150 12:17:47.904586 00400000 ################################################################
10151 12:17:47.904812
10152 12:17:48.159279 00480000 ################################################################
10153 12:17:48.159465
10154 12:17:48.422981 00500000 ################################################################
10155 12:17:48.423140
10156 12:17:48.706217 00580000 ################################################################
10157 12:17:48.706376
10158 12:17:48.987581 00600000 ################################################################
10159 12:17:48.987737
10160 12:17:49.241226 00680000 ################################################################
10161 12:17:49.241411
10162 12:17:49.502341 00700000 ################################################################
10163 12:17:49.502499
10164 12:17:49.771302 00780000 ################################################################
10165 12:17:49.771464
10166 12:17:50.046693 00800000 ################################################################
10167 12:17:50.046906
10168 12:17:50.312758 00880000 ################################################################
10169 12:17:50.312952
10170 12:17:50.577723 00900000 ################################################################
10171 12:17:50.577882
10172 12:17:50.864659 00980000 ################################################################
10173 12:17:50.864872
10174 12:17:51.136515 00a00000 ################################################################
10175 12:17:51.136673
10176 12:17:51.391491 00a80000 ################################################################
10177 12:17:51.391649
10178 12:17:51.651486 00b00000 ################################################################
10179 12:17:51.651669
10180 12:17:51.909746 00b80000 ################################################################
10181 12:17:51.909954
10182 12:17:52.168529 00c00000 ################################################################
10183 12:17:52.168715
10184 12:17:52.419650 00c80000 ################################################################
10185 12:17:52.419806
10186 12:17:52.692928 00d00000 ################################################################
10187 12:17:52.693094
10188 12:17:52.939709 00d80000 ################################################################
10189 12:17:52.939890
10190 12:17:53.207440 00e00000 ################################################################
10191 12:17:53.207604
10192 12:17:53.473239 00e80000 ################################################################
10193 12:17:53.473399
10194 12:17:53.731247 00f00000 ################################################################
10195 12:17:53.731400
10196 12:17:53.984116 00f80000 ################################################################
10197 12:17:53.984314
10198 12:17:54.246421 01000000 ################################################################
10199 12:17:54.246580
10200 12:17:54.511106 01080000 ################################################################
10201 12:17:54.511259
10202 12:17:54.803731 01100000 ################################################################
10203 12:17:54.803918
10204 12:17:55.098612 01180000 ################################################################
10205 12:17:55.098792
10206 12:17:55.369055 01200000 ################################################################
10207 12:17:55.369210
10208 12:17:55.638496 01280000 ################################################################
10209 12:17:55.638648
10210 12:17:55.900278 01300000 ################################################################
10211 12:17:55.900472
10212 12:17:56.162170 01380000 ################################################################
10213 12:17:56.162327
10214 12:17:56.428697 01400000 ################################################################
10215 12:17:56.428864
10216 12:17:56.709115 01480000 ################################################################
10217 12:17:56.709268
10218 12:17:56.957865 01500000 ################################################################
10219 12:17:56.958069
10220 12:17:57.208291 01580000 ################################################################
10221 12:17:57.208470
10222 12:17:57.465642 01600000 ################################################################
10223 12:17:57.465800
10224 12:17:57.724668 01680000 ################################################################
10225 12:17:57.724844
10226 12:17:57.988439 01700000 ################################################################
10227 12:17:57.988600
10228 12:17:58.249253 01780000 ################################################################
10229 12:17:58.249410
10230 12:17:58.514243 01800000 ################################################################
10231 12:17:58.514409
10232 12:17:58.786775 01880000 ################################################################
10233 12:17:58.786935
10234 12:17:59.071733 01900000 ################################################################
10235 12:17:59.071926
10236 12:17:59.330948 01980000 ################################################################
10237 12:17:59.331103
10238 12:17:59.586126 01a00000 ################################################################
10239 12:17:59.586260
10240 12:17:59.586335 01a80000 # done.
10241 12:17:59.586397
10242 12:17:59.589308 The bootfile was 27787450 bytes long.
10243 12:17:59.589393
10244 12:17:59.592724 Sending tftp read request... done.
10245 12:17:59.592869
10246 12:17:59.595874 Waiting for the transfer...
10247 12:17:59.595981
10248 12:17:59.596049 00000000 # done.
10249 12:17:59.596112
10250 12:17:59.606118 Command line loaded dynamically from TFTP file: 10605441/tftp-deploy-gxdu5qj5/kernel/cmdline
10251 12:17:59.606240
10252 12:17:59.625391 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605441/extract-nfsrootfs-oz4520mr,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10253 12:17:59.625526
10254 12:17:59.625594 Loading FIT.
10255 12:17:59.625655
10256 12:17:59.629131 Image ramdisk-1 has 17643869 bytes.
10257 12:17:59.629214
10258 12:17:59.632361 Image fdt-1 has 46924 bytes.
10259 12:17:59.632444
10260 12:17:59.635208 Image kernel-1 has 10094623 bytes.
10261 12:17:59.635291
10262 12:17:59.642147 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10263 12:17:59.645160
10264 12:17:59.661931 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10265 12:17:59.662113
10266 12:17:59.664986 Choosing best match conf-1 for compat google,spherion-rev2.
10267 12:17:59.671005
10268 12:17:59.675117 Connected to device vid:did:rid of 1ae0:0028:00
10269 12:17:59.681890
10270 12:17:59.685533 tpm_get_response: command 0x17b, return code 0x0
10271 12:17:59.685750
10272 12:17:59.688521 ec_init: CrosEC protocol v3 supported (256, 248)
10273 12:17:59.692812
10274 12:17:59.696058 tpm_cleanup: add release locality here.
10275 12:17:59.696263
10276 12:17:59.696425 Shutting down all USB controllers.
10277 12:17:59.699735
10278 12:17:59.699979 Removing current net device
10279 12:17:59.700173
10280 12:17:59.706403 Exiting depthcharge with code 4 at timestamp: 49757795
10281 12:17:59.706803
10282 12:17:59.709496 LZMA decompressing kernel-1 to 0x821a6718
10283 12:17:59.709889
10284 12:17:59.712589 LZMA decompressing kernel-1 to 0x40000000
10285 12:18:00.981116
10286 12:18:00.981815 jumping to kernel
10287 12:18:00.983599 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10288 12:18:00.984294 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10289 12:18:00.984698 Setting prompt string to ['Linux version [0-9]']
10290 12:18:00.985094 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10291 12:18:00.985450 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10292 12:18:01.062819
10293 12:18:01.066333 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10294 12:18:01.069662 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10295 12:18:01.070168 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10296 12:18:01.070640 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10297 12:18:01.071013 Using line separator: #'\n'#
10298 12:18:01.071420 No login prompt set.
10299 12:18:01.071764 Parsing kernel messages
10300 12:18:01.072139 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10301 12:18:01.072882 [login-action] Waiting for messages, (timeout 00:04:03)
10302 12:18:01.088656 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
10303 12:18:01.091717 [ 0.000000] random: crng init done
10304 12:18:01.095019 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10305 12:18:01.098291 [ 0.000000] efi: UEFI not found.
10306 12:18:01.108253 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10307 12:18:01.114553 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10308 12:18:01.124414 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10309 12:18:01.134209 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10310 12:18:01.141156 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10311 12:18:01.147680 [ 0.000000] printk: bootconsole [mtk8250] enabled
10312 12:18:01.154179 [ 0.000000] NUMA: No NUMA configuration found
10313 12:18:01.160666 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10314 12:18:01.164090 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10315 12:18:01.167268 [ 0.000000] Zone ranges:
10316 12:18:01.173894 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10317 12:18:01.177404 [ 0.000000] DMA32 empty
10318 12:18:01.183936 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10319 12:18:01.186882 [ 0.000000] Movable zone start for each node
10320 12:18:01.190367 [ 0.000000] Early memory node ranges
10321 12:18:01.196959 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10322 12:18:01.203533 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10323 12:18:01.210103 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10324 12:18:01.216459 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10325 12:18:01.223279 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10326 12:18:01.230099 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10327 12:18:01.286032 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10328 12:18:01.292552 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10329 12:18:01.299092 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10330 12:18:01.302555 [ 0.000000] psci: probing for conduit method from DT.
10331 12:18:01.308910 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10332 12:18:01.312124 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10333 12:18:01.318713 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10334 12:18:01.322256 [ 0.000000] psci: SMC Calling Convention v1.2
10335 12:18:01.328459 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10336 12:18:01.331835 [ 0.000000] Detected VIPT I-cache on CPU0
10337 12:18:01.338386 [ 0.000000] CPU features: detected: GIC system register CPU interface
10338 12:18:01.345152 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10339 12:18:01.351535 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10340 12:18:01.358403 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10341 12:18:01.368042 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10342 12:18:01.374751 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10343 12:18:01.377642 [ 0.000000] alternatives: applying boot alternatives
10344 12:18:01.384965 [ 0.000000] Fallback order for Node 0: 0
10345 12:18:01.391254 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10346 12:18:01.394716 [ 0.000000] Policy zone: Normal
10347 12:18:01.414418 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605441/extract-nfsrootfs-oz4520mr,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10348 12:18:01.424353 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10349 12:18:01.435714 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10350 12:18:01.445759 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10351 12:18:01.452404 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10352 12:18:01.455138 <6>[ 0.000000] software IO TLB: area num 8.
10353 12:18:01.511837 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10354 12:18:01.661652 <6>[ 0.000000] Memory: 7955716K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397052K reserved, 32768K cma-reserved)
10355 12:18:01.668114 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10356 12:18:01.674881 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10357 12:18:01.678276 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10358 12:18:01.684729 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10359 12:18:01.691251 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10360 12:18:01.694691 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10361 12:18:01.704480 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10362 12:18:01.711455 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10363 12:18:01.717860 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10364 12:18:01.724233 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10365 12:18:01.727717 <6>[ 0.000000] GICv3: 608 SPIs implemented
10366 12:18:01.730688 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10367 12:18:01.737136 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10368 12:18:01.740600 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10369 12:18:01.747145 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10370 12:18:01.760364 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10371 12:18:01.773762 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10372 12:18:01.780113 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10373 12:18:01.787569 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10374 12:18:01.800918 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10375 12:18:01.807485 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10376 12:18:01.813925 <6>[ 0.009179] Console: colour dummy device 80x25
10377 12:18:01.824205 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10378 12:18:01.830953 <6>[ 0.024413] pid_max: default: 32768 minimum: 301
10379 12:18:01.833926 <6>[ 0.029280] LSM: Security Framework initializing
10380 12:18:01.840711 <6>[ 0.034220] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10381 12:18:01.850684 <6>[ 0.042034] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10382 12:18:01.857217 <6>[ 0.051469] cblist_init_generic: Setting adjustable number of callback queues.
10383 12:18:01.863763 <6>[ 0.058923] cblist_init_generic: Setting shift to 3 and lim to 1.
10384 12:18:01.870612 <6>[ 0.065299] cblist_init_generic: Setting shift to 3 and lim to 1.
10385 12:18:01.877255 <6>[ 0.071707] rcu: Hierarchical SRCU implementation.
10386 12:18:01.883292 <6>[ 0.076721] rcu: Max phase no-delay instances is 1000.
10387 12:18:01.890114 <6>[ 0.083738] EFI services will not be available.
10388 12:18:01.893066 <6>[ 0.088704] smp: Bringing up secondary CPUs ...
10389 12:18:01.901203 <6>[ 0.093784] Detected VIPT I-cache on CPU1
10390 12:18:01.907647 <6>[ 0.093855] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10391 12:18:01.914105 <6>[ 0.093887] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10392 12:18:01.917390 <6>[ 0.094225] Detected VIPT I-cache on CPU2
10393 12:18:01.927308 <6>[ 0.094274] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10394 12:18:01.933765 <6>[ 0.094288] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10395 12:18:01.937192 <6>[ 0.094548] Detected VIPT I-cache on CPU3
10396 12:18:01.943556 <6>[ 0.094596] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10397 12:18:01.950241 <6>[ 0.094610] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10398 12:18:01.957082 <6>[ 0.094913] CPU features: detected: Spectre-v4
10399 12:18:01.960259 <6>[ 0.094919] CPU features: detected: Spectre-BHB
10400 12:18:01.963447 <6>[ 0.094925] Detected PIPT I-cache on CPU4
10401 12:18:01.969971 <6>[ 0.094982] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10402 12:18:01.976694 <6>[ 0.094998] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10403 12:18:01.983479 <6>[ 0.095294] Detected PIPT I-cache on CPU5
10404 12:18:01.990458 <6>[ 0.095357] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10405 12:18:01.996904 <6>[ 0.095373] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10406 12:18:02.000212 <6>[ 0.095657] Detected PIPT I-cache on CPU6
10407 12:18:02.006462 <6>[ 0.095722] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10408 12:18:02.013423 <6>[ 0.095738] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10409 12:18:02.019761 <6>[ 0.096036] Detected PIPT I-cache on CPU7
10410 12:18:02.026269 <6>[ 0.096094] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10411 12:18:02.033065 <6>[ 0.096110] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10412 12:18:02.036460 <6>[ 0.096156] smp: Brought up 1 node, 8 CPUs
10413 12:18:02.042730 <6>[ 0.237579] SMP: Total of 8 processors activated.
10414 12:18:02.046218 <6>[ 0.242500] CPU features: detected: 32-bit EL0 Support
10415 12:18:02.056125 <6>[ 0.247863] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10416 12:18:02.062638 <6>[ 0.256663] CPU features: detected: Common not Private translations
10417 12:18:02.069359 <6>[ 0.263138] CPU features: detected: CRC32 instructions
10418 12:18:02.075673 <6>[ 0.268489] CPU features: detected: RCpc load-acquire (LDAPR)
10419 12:18:02.078898 <6>[ 0.274486] CPU features: detected: LSE atomic instructions
10420 12:18:02.085758 <6>[ 0.280268] CPU features: detected: Privileged Access Never
10421 12:18:02.092344 <6>[ 0.286047] CPU features: detected: RAS Extension Support
10422 12:18:02.098804 <6>[ 0.291656] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10423 12:18:02.102303 <6>[ 0.298920] CPU: All CPU(s) started at EL2
10424 12:18:02.108524 <6>[ 0.303237] alternatives: applying system-wide alternatives
10425 12:18:02.118892 <6>[ 0.313946] devtmpfs: initialized
10426 12:18:02.134178 <6>[ 0.322806] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10427 12:18:02.141193 <6>[ 0.332764] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10428 12:18:02.147793 <6>[ 0.340791] pinctrl core: initialized pinctrl subsystem
10429 12:18:02.150979 <6>[ 0.347457] DMI not present or invalid.
10430 12:18:02.157736 <6>[ 0.351860] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10431 12:18:02.167968 <6>[ 0.358732] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10432 12:18:02.174125 <6>[ 0.366315] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10433 12:18:02.184075 <6>[ 0.374528] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10434 12:18:02.187444 <6>[ 0.382768] audit: initializing netlink subsys (disabled)
10435 12:18:02.197379 <5>[ 0.388463] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10436 12:18:02.204081 <6>[ 0.389176] thermal_sys: Registered thermal governor 'step_wise'
10437 12:18:02.210474 <6>[ 0.396434] thermal_sys: Registered thermal governor 'power_allocator'
10438 12:18:02.213935 <6>[ 0.402691] cpuidle: using governor menu
10439 12:18:02.220285 <6>[ 0.413651] NET: Registered PF_QIPCRTR protocol family
10440 12:18:02.226915 <6>[ 0.419145] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10441 12:18:02.233883 <6>[ 0.426251] ASID allocator initialised with 32768 entries
10442 12:18:02.236762 <6>[ 0.432825] Serial: AMBA PL011 UART driver
10443 12:18:02.246704 <4>[ 0.441532] Trying to register duplicate clock ID: 134
10444 12:18:02.300735 <6>[ 0.498650] KASLR enabled
10445 12:18:02.314905 <6>[ 0.506343] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10446 12:18:02.321609 <6>[ 0.513358] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10447 12:18:02.327919 <6>[ 0.519844] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10448 12:18:02.334687 <6>[ 0.526846] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10449 12:18:02.341476 <6>[ 0.533332] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10450 12:18:02.347839 <6>[ 0.540334] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10451 12:18:02.354251 <6>[ 0.546821] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10452 12:18:02.361236 <6>[ 0.553821] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10453 12:18:02.364368 <6>[ 0.561299] ACPI: Interpreter disabled.
10454 12:18:02.373175 <6>[ 0.567707] iommu: Default domain type: Translated
10455 12:18:02.379866 <6>[ 0.572817] iommu: DMA domain TLB invalidation policy: strict mode
10456 12:18:02.382744 <5>[ 0.579478] SCSI subsystem initialized
10457 12:18:02.389473 <6>[ 0.583713] usbcore: registered new interface driver usbfs
10458 12:18:02.396094 <6>[ 0.589447] usbcore: registered new interface driver hub
10459 12:18:02.399229 <6>[ 0.595000] usbcore: registered new device driver usb
10460 12:18:02.406207 <6>[ 0.601108] pps_core: LinuxPPS API ver. 1 registered
10461 12:18:02.416269 <6>[ 0.606303] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10462 12:18:02.419899 <6>[ 0.615642] PTP clock support registered
10463 12:18:02.422861 <6>[ 0.619882] EDAC MC: Ver: 3.0.0
10464 12:18:02.430380 <6>[ 0.625081] FPGA manager framework
10465 12:18:02.436699 <6>[ 0.628760] Advanced Linux Sound Architecture Driver Initialized.
10466 12:18:02.440124 <6>[ 0.635532] vgaarb: loaded
10467 12:18:02.446632 <6>[ 0.638701] clocksource: Switched to clocksource arch_sys_counter
10468 12:18:02.450078 <5>[ 0.645149] VFS: Disk quotas dquot_6.6.0
10469 12:18:02.456340 <6>[ 0.649334] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10470 12:18:02.459786 <6>[ 0.656525] pnp: PnP ACPI: disabled
10471 12:18:02.468326 <6>[ 0.663183] NET: Registered PF_INET protocol family
10472 12:18:02.478050 <6>[ 0.668770] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10473 12:18:02.489386 <6>[ 0.681063] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10474 12:18:02.499386 <6>[ 0.689879] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10475 12:18:02.506086 <6>[ 0.697844] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10476 12:18:02.516041 <6>[ 0.706545] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10477 12:18:02.522606 <6>[ 0.716281] TCP: Hash tables configured (established 65536 bind 65536)
10478 12:18:02.528939 <6>[ 0.723141] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10479 12:18:02.538757 <6>[ 0.730340] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10480 12:18:02.545226 <6>[ 0.738044] NET: Registered PF_UNIX/PF_LOCAL protocol family
10481 12:18:02.552177 <6>[ 0.744209] RPC: Registered named UNIX socket transport module.
10482 12:18:02.555064 <6>[ 0.750361] RPC: Registered udp transport module.
10483 12:18:02.561997 <6>[ 0.755293] RPC: Registered tcp transport module.
10484 12:18:02.568276 <6>[ 0.760227] RPC: Registered tcp NFSv4.1 backchannel transport module.
10485 12:18:02.571846 <6>[ 0.766895] PCI: CLS 0 bytes, default 64
10486 12:18:02.575226 <6>[ 0.771267] Unpacking initramfs...
10487 12:18:02.591735 <6>[ 0.783265] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10488 12:18:02.601593 <6>[ 0.791914] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10489 12:18:02.605042 <6>[ 0.800733] kvm [1]: IPA Size Limit: 40 bits
10490 12:18:02.611659 <6>[ 0.805258] kvm [1]: GICv3: no GICV resource entry
10491 12:18:02.615006 <6>[ 0.810276] kvm [1]: disabling GICv2 emulation
10492 12:18:02.621610 <6>[ 0.814959] kvm [1]: GIC system register CPU interface enabled
10493 12:18:02.624856 <6>[ 0.821127] kvm [1]: vgic interrupt IRQ18
10494 12:18:02.631351 <6>[ 0.825484] kvm [1]: VHE mode initialized successfully
10495 12:18:02.638078 <5>[ 0.832019] Initialise system trusted keyrings
10496 12:18:02.644828 <6>[ 0.836829] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10497 12:18:02.652314 <6>[ 0.846874] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10498 12:18:02.658894 <5>[ 0.853254] NFS: Registering the id_resolver key type
10499 12:18:02.661857 <5>[ 0.858559] Key type id_resolver registered
10500 12:18:02.668595 <5>[ 0.862971] Key type id_legacy registered
10501 12:18:02.675160 <6>[ 0.867247] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10502 12:18:02.681824 <6>[ 0.874169] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10503 12:18:02.688412 <6>[ 0.881881] 9p: Installing v9fs 9p2000 file system support
10504 12:18:02.725078 <5>[ 0.919815] Key type asymmetric registered
10505 12:18:02.728334 <5>[ 0.924147] Asymmetric key parser 'x509' registered
10506 12:18:02.738333 <6>[ 0.929290] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10507 12:18:02.741700 <6>[ 0.936907] io scheduler mq-deadline registered
10508 12:18:02.744885 <6>[ 0.941688] io scheduler kyber registered
10509 12:18:02.763125 <6>[ 0.958455] EINJ: ACPI disabled.
10510 12:18:02.794888 <4>[ 0.983769] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10511 12:18:02.804725 <4>[ 0.994386] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10512 12:18:02.819541 <6>[ 1.014867] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10513 12:18:02.827557 <6>[ 1.022733] printk: console [ttyS0] disabled
10514 12:18:02.855415 <6>[ 1.047385] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10515 12:18:02.862170 <6>[ 1.056870] printk: console [ttyS0] enabled
10516 12:18:02.865467 <6>[ 1.056870] printk: console [ttyS0] enabled
10517 12:18:02.872193 <6>[ 1.065763] printk: bootconsole [mtk8250] disabled
10518 12:18:02.875535 <6>[ 1.065763] printk: bootconsole [mtk8250] disabled
10519 12:18:02.881854 <6>[ 1.076816] SuperH (H)SCI(F) driver initialized
10520 12:18:02.885047 <6>[ 1.082089] msm_serial: driver initialized
10521 12:18:02.899220 <6>[ 1.090934] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10522 12:18:02.908811 <6>[ 1.099482] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10523 12:18:02.915835 <6>[ 1.108025] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10524 12:18:02.925311 <6>[ 1.116652] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10525 12:18:02.935459 <6>[ 1.125359] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10526 12:18:02.942101 <6>[ 1.134079] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10527 12:18:02.952027 <6>[ 1.142619] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10528 12:18:02.958933 <6>[ 1.151420] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10529 12:18:02.968366 <6>[ 1.159963] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10530 12:18:02.980401 <6>[ 1.175448] loop: module loaded
10531 12:18:02.986649 <6>[ 1.181390] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10532 12:18:03.009501 <4>[ 1.204688] mtk-pmic-keys: Failed to locate of_node [id: -1]
10533 12:18:03.016114 <6>[ 1.211387] megasas: 07.719.03.00-rc1
10534 12:18:03.025532 <6>[ 1.220818] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10535 12:18:03.034693 <6>[ 1.230084] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10536 12:18:03.051619 <6>[ 1.246750] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10537 12:18:03.111717 <6>[ 1.300658] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10538 12:18:03.303308 <6>[ 1.498651] Freeing initrd memory: 17224K
10539 12:18:03.313366 <6>[ 1.508843] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10540 12:18:03.324824 <6>[ 1.519734] tun: Universal TUN/TAP device driver, 1.6
10541 12:18:03.328104 <6>[ 1.525771] thunder_xcv, ver 1.0
10542 12:18:03.331267 <6>[ 1.529277] thunder_bgx, ver 1.0
10543 12:18:03.334614 <6>[ 1.532772] nicpf, ver 1.0
10544 12:18:03.345214 <6>[ 1.536768] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10545 12:18:03.348214 <6>[ 1.544244] hns3: Copyright (c) 2017 Huawei Corporation.
10546 12:18:03.354800 <6>[ 1.549833] hclge is initializing
10547 12:18:03.358135 <6>[ 1.553414] e1000: Intel(R) PRO/1000 Network Driver
10548 12:18:03.364945 <6>[ 1.558543] e1000: Copyright (c) 1999-2006 Intel Corporation.
10549 12:18:03.368323 <6>[ 1.564556] e1000e: Intel(R) PRO/1000 Network Driver
10550 12:18:03.374624 <6>[ 1.569771] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10551 12:18:03.381216 <6>[ 1.575955] igb: Intel(R) Gigabit Ethernet Network Driver
10552 12:18:03.388236 <6>[ 1.581605] igb: Copyright (c) 2007-2014 Intel Corporation.
10553 12:18:03.394779 <6>[ 1.587444] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10554 12:18:03.401222 <6>[ 1.593961] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10555 12:18:03.404557 <6>[ 1.600417] sky2: driver version 1.30
10556 12:18:03.411031 <6>[ 1.605383] VFIO - User Level meta-driver version: 0.3
10557 12:18:03.418719 <6>[ 1.613568] usbcore: registered new interface driver usb-storage
10558 12:18:03.424748 <6>[ 1.620016] usbcore: registered new device driver onboard-usb-hub
10559 12:18:03.434138 <6>[ 1.629103] mt6397-rtc mt6359-rtc: registered as rtc0
10560 12:18:03.444091 <6>[ 1.634568] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:18:06 UTC (1686053886)
10561 12:18:03.447320 <6>[ 1.644123] i2c_dev: i2c /dev entries driver
10562 12:18:03.463640 <6>[ 1.655738] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10563 12:18:03.470913 <6>[ 1.665913] sdhci: Secure Digital Host Controller Interface driver
10564 12:18:03.477071 <6>[ 1.672351] sdhci: Copyright(c) Pierre Ossman
10565 12:18:03.483768 <6>[ 1.677740] Synopsys Designware Multimedia Card Interface Driver
10566 12:18:03.487105 <6>[ 1.684359] mmc0: CQHCI version 5.10
10567 12:18:03.493885 <6>[ 1.684889] sdhci-pltfm: SDHCI platform and OF driver helper
10568 12:18:03.500954 <6>[ 1.696230] ledtrig-cpu: registered to indicate activity on CPUs
10569 12:18:03.511438 <6>[ 1.703581] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10570 12:18:03.515241 <6>[ 1.710982] usbcore: registered new interface driver usbhid
10571 12:18:03.521741 <6>[ 1.716811] usbhid: USB HID core driver
10572 12:18:03.528464 <6>[ 1.721056] spi_master spi0: will run message pump with realtime priority
10573 12:18:03.576876 <6>[ 1.765724] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10574 12:18:03.595972 <6>[ 1.780950] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10575 12:18:03.599276 <6>[ 1.794545] mmc0: Command Queue Engine enabled
10576 12:18:03.606000 <6>[ 1.796672] cros-ec-spi spi0.0: Chrome EC device registered
10577 12:18:03.612464 <6>[ 1.799276] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10578 12:18:03.615581 <6>[ 1.812589] mmcblk0: mmc0:0001 DA4128 116 GiB
10579 12:18:03.630723 <6>[ 1.822555] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10580 12:18:03.637292 <6>[ 1.824611] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10581 12:18:03.643880 <6>[ 1.834072] NET: Registered PF_PACKET protocol family
10582 12:18:03.647108 <6>[ 1.838838] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10583 12:18:03.653687 <6>[ 1.843230] 9pnet: Installing 9P2000 support
10584 12:18:03.657135 <6>[ 1.849025] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10585 12:18:03.663655 <5>[ 1.852892] Key type dns_resolver registered
10586 12:18:03.670518 <6>[ 1.858744] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10587 12:18:03.673731 <6>[ 1.863182] registered taskstats version 1
10588 12:18:03.676693 <5>[ 1.873520] Loading compiled-in X.509 certificates
10589 12:18:03.712860 <4>[ 1.901345] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10590 12:18:03.722490 <4>[ 1.912053] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10591 12:18:03.732875 <3>[ 1.924898] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10592 12:18:03.745130 <6>[ 1.940378] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10593 12:18:03.752206 <6>[ 1.947261] xhci-mtk 11200000.usb: xHCI Host Controller
10594 12:18:03.758786 <6>[ 1.952767] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10595 12:18:03.768561 <6>[ 1.960620] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10596 12:18:03.775349 <6>[ 1.970050] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10597 12:18:03.781769 <6>[ 1.976228] xhci-mtk 11200000.usb: xHCI Host Controller
10598 12:18:03.788755 <6>[ 1.981721] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10599 12:18:03.795406 <6>[ 1.989384] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10600 12:18:03.801890 <6>[ 1.997277] hub 1-0:1.0: USB hub found
10601 12:18:03.805439 <6>[ 2.001310] hub 1-0:1.0: 1 port detected
10602 12:18:03.815483 <6>[ 2.005661] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10603 12:18:03.818667 <6>[ 2.014468] hub 2-0:1.0: USB hub found
10604 12:18:03.821862 <6>[ 2.018501] hub 2-0:1.0: 1 port detected
10605 12:18:03.830025 <6>[ 2.025362] mtk-msdc 11f70000.mmc: Got CD GPIO
10606 12:18:03.848185 <6>[ 2.039983] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10607 12:18:03.854885 <6>[ 2.048012] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10608 12:18:03.864484 <4>[ 2.055991] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10609 12:18:03.874760 <6>[ 2.065642] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10610 12:18:03.881466 <6>[ 2.073722] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10611 12:18:03.888054 <6>[ 2.081761] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10612 12:18:03.897807 <6>[ 2.089675] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10613 12:18:03.904436 <6>[ 2.097496] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10614 12:18:03.914487 <6>[ 2.105317] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10615 12:18:03.924316 <6>[ 2.116066] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10616 12:18:03.931120 <6>[ 2.124438] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10617 12:18:03.941248 <6>[ 2.132783] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10618 12:18:03.947846 <6>[ 2.141126] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10619 12:18:03.957933 <6>[ 2.149469] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10620 12:18:03.964362 <6>[ 2.157812] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10621 12:18:03.974422 <6>[ 2.166154] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10622 12:18:03.980744 <6>[ 2.174497] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10623 12:18:03.990872 <6>[ 2.182840] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10624 12:18:03.997529 <6>[ 2.191183] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10625 12:18:04.007520 <6>[ 2.199526] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10626 12:18:04.017676 <6>[ 2.207869] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10627 12:18:04.024224 <6>[ 2.216213] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10628 12:18:04.034265 <6>[ 2.224557] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10629 12:18:04.040694 <6>[ 2.232924] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10630 12:18:04.047041 <6>[ 2.241783] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10631 12:18:04.053766 <6>[ 2.249239] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10632 12:18:04.061078 <6>[ 2.256255] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10633 12:18:04.071140 <6>[ 2.263376] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10634 12:18:04.077752 <6>[ 2.270658] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10635 12:18:04.087960 <6>[ 2.277599] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10636 12:18:04.094418 <6>[ 2.286739] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10637 12:18:04.104110 <6>[ 2.295865] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10638 12:18:04.114054 <6>[ 2.305166] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10639 12:18:04.123941 <6>[ 2.314641] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10640 12:18:04.133571 <6>[ 2.324115] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10641 12:18:04.143614 <6>[ 2.333241] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10642 12:18:04.150150 <6>[ 2.342718] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10643 12:18:04.160184 <6>[ 2.351844] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10644 12:18:04.170013 <6>[ 2.361146] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10645 12:18:04.179706 <6>[ 2.371311] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10646 12:18:04.191104 <6>[ 2.383237] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10647 12:18:04.197732 <6>[ 2.393192] Trying to probe devices needed for running init ...
10648 12:18:04.230763 <6>[ 2.422949] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10649 12:18:04.383405 <6>[ 2.578835] hub 1-1:1.0: USB hub found
10650 12:18:04.386626 <6>[ 2.583189] hub 1-1:1.0: 4 ports detected
10651 12:18:04.511183 <6>[ 2.703311] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10652 12:18:04.538169 <6>[ 2.733308] hub 2-1:1.0: USB hub found
10653 12:18:04.541272 <6>[ 2.737843] hub 2-1:1.0: 3 ports detected
10654 12:18:04.706869 <6>[ 2.898997] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10655 12:18:04.839484 <6>[ 3.034955] hub 1-1.4:1.0: USB hub found
10656 12:18:04.843011 <6>[ 3.039617] hub 1-1.4:1.0: 2 ports detected
10657 12:18:04.922838 <6>[ 3.115224] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10658 12:18:05.138761 <6>[ 3.330866] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10659 12:18:05.330665 <6>[ 3.522971] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10660 12:18:16.499650 <6>[ 14.699523] ALSA device list:
10661 12:18:16.506084 <6>[ 14.702780] No soundcards found.
10662 12:18:16.518264 <6>[ 14.715171] Freeing unused kernel memory: 8384K
10663 12:18:16.521435 <6>[ 14.720105] Run /init as init process
10664 12:18:16.532568 Loading, please wait...
10665 12:18:16.552583 Starting version 247.3-7+deb11u2
10666 12:18:16.872430 <6>[ 15.065981] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10667 12:18:16.883933 <6>[ 15.080719] remoteproc remoteproc0: scp is available
10668 12:18:16.893804 <4>[ 15.086420] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10669 12:18:16.900531 <6>[ 15.096496] remoteproc remoteproc0: powering up scp
10670 12:18:16.910437 <4>[ 15.101692] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10671 12:18:16.917052 <3>[ 15.104402] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 12:18:16.923599 <3>[ 15.111525] remoteproc remoteproc0: request_firmware failed: -2
10673 12:18:16.933702 <3>[ 15.125808] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 12:18:16.939988 <3>[ 15.133901] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 12:18:16.950185 <3>[ 15.143076] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 12:18:16.956516 <6>[ 15.149882] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10677 12:18:16.966745 <3>[ 15.158821] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 12:18:16.973251 <6>[ 15.158843] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10679 12:18:16.979645 <6>[ 15.164913] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10680 12:18:16.989871 <3>[ 15.166927] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 12:18:16.999670 <6>[ 15.175654] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10682 12:18:17.006459 <3>[ 15.183280] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 12:18:17.010092 <6>[ 15.184789] mc: Linux media interface: v0.10
10684 12:18:17.016337 <4>[ 15.185514] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10685 12:18:17.026266 <4>[ 15.185715] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10686 12:18:17.033703 <4>[ 15.188910] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10687 12:18:17.040437 <4>[ 15.188910] Fallback method does not support PEC.
10688 12:18:17.046597 <3>[ 15.206040] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10689 12:18:17.053510 <6>[ 15.206369] usbcore: registered new interface driver r8152
10690 12:18:17.060093 <3>[ 15.208177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 12:18:17.069868 <3>[ 15.208302] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 12:18:17.076489 <6>[ 15.209320] videodev: Linux video capture interface: v2.00
10693 12:18:17.083164 <3>[ 15.235624] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 12:18:17.093070 <3>[ 15.241025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 12:18:17.099816 <3>[ 15.294236] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 12:18:17.106253 <3>[ 15.295010] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10697 12:18:17.116076 <3>[ 15.302328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 12:18:17.122606 <6>[ 15.311001] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10699 12:18:17.132775 <6>[ 15.311689] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10700 12:18:17.142635 <6>[ 15.312155] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10701 12:18:17.149205 <6>[ 15.316106] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10702 12:18:17.152640 <6>[ 15.316113] pci_bus 0000:00: root bus resource [bus 00-ff]
10703 12:18:17.162622 <6>[ 15.316120] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10704 12:18:17.172498 <6>[ 15.316125] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10705 12:18:17.175384 <6>[ 15.316158] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10706 12:18:17.185467 <6>[ 15.316179] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10707 12:18:17.188970 <6>[ 15.316271] pci 0000:00:00.0: supports D1 D2
10708 12:18:17.195575 <6>[ 15.316275] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10709 12:18:17.205356 <3>[ 15.316978] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 12:18:17.212285 <6>[ 15.317953] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10711 12:18:17.218933 <6>[ 15.318062] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10712 12:18:17.225379 <6>[ 15.318092] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10713 12:18:17.232072 <6>[ 15.318112] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10714 12:18:17.241544 <6>[ 15.318131] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10715 12:18:17.244888 <6>[ 15.318246] pci 0000:01:00.0: supports D1 D2
10716 12:18:17.251863 <6>[ 15.318249] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10717 12:18:17.258043 <6>[ 15.334833] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10718 12:18:17.268046 <3>[ 15.343088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 12:18:17.274902 <6>[ 15.349981] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10720 12:18:17.284600 <4>[ 15.350817] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10721 12:18:17.291160 <4>[ 15.350828] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10722 12:18:17.300967 <3>[ 15.355693] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 12:18:17.308048 <6>[ 15.362817] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10724 12:18:17.317645 <3>[ 15.372718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 12:18:17.324372 <6>[ 15.378981] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10726 12:18:17.333994 <3>[ 15.386444] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 12:18:17.340995 <6>[ 15.391064] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10728 12:18:17.347568 <3>[ 15.397864] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 12:18:17.357368 <6>[ 15.405961] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10730 12:18:17.364135 <3>[ 15.414927] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10731 12:18:17.367524 <6>[ 15.420552] r8152 2-1.3:1.0 eth0: v1.12.13
10732 12:18:17.373649 <6>[ 15.422849] pci 0000:00:00.0: PCI bridge to [bus 01]
10733 12:18:17.380261 <6>[ 15.422860] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10734 12:18:17.387014 <6>[ 15.423008] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10735 12:18:17.393511 <6>[ 15.423851] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10736 12:18:17.400345 <6>[ 15.424321] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10737 12:18:17.406734 <3>[ 15.526990] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10738 12:18:17.413234 <3>[ 15.607982] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10739 12:18:17.423308 <6>[ 15.614957] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10740 12:18:17.434426 <6>[ 15.631811] usbcore: registered new interface driver cdc_ether
10741 12:18:17.446193 <6>[ 15.643387] usbcore: registered new interface driver r8153_ecm
10742 12:18:17.455244 <6>[ 15.652076] Bluetooth: Core ver 2.22
10743 12:18:17.461600 <6>[ 15.653627] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10744 12:18:17.468472 <5>[ 15.653671] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10745 12:18:17.474714 <6>[ 15.656089] NET: Registered PF_BLUETOOTH protocol family
10746 12:18:17.481376 <6>[ 15.660573] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10747 12:18:17.487974 <6>[ 15.664068] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10748 12:18:17.501317 <6>[ 15.664523] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10749 12:18:17.504517 <6>[ 15.664740] usbcore: registered new interface driver uvcvideo
10750 12:18:17.511219 <5>[ 15.665203] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10751 12:18:17.517776 <6>[ 15.671035] Bluetooth: HCI device and connection manager initialized
10752 12:18:17.524309 <6>[ 15.671057] Bluetooth: HCI socket layer initialized
10753 12:18:17.531195 <6>[ 15.726127] Bluetooth: L2CAP socket layer initialized
10754 12:18:17.534373 <6>[ 15.731438] Bluetooth: SCO socket layer initialized
10755 12:18:17.544655 <6>[ 15.741537] usbcore: registered new interface driver btusb
10756 12:18:17.554367 <4>[ 15.742096] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10757 12:18:17.560924 <3>[ 15.757896] Bluetooth: hci0: Failed to load firmware file (-2)
10758 12:18:17.570756 <4>[ 15.759190] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10759 12:18:17.577292 <3>[ 15.763994] Bluetooth: hci0: Failed to set up firmware (-2)
10760 12:18:17.580598 <6>[ 15.772864] cfg80211: failed to load regulatory.db
10761 12:18:17.590457 <4>[ 15.778691] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10762 12:18:17.628725 <6>[ 15.822584] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10763 12:18:17.635525 <6>[ 15.830130] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10764 12:18:17.659778 <6>[ 15.856906] mt7921e 0000:01:00.0: ASIC revision: 79610010
10765 12:18:17.764546 <4>[ 15.954946] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10766 12:18:17.777977 Begin: Loading essential drivers ... done.
10767 12:18:17.784532 Begin: Running /scripts/init-premount ... done.
10768 12:18:17.790939 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10769 12:18:17.797666 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10770 12:18:17.804157 Device /sys/class/net/enx00e04c722dd6 found
10771 12:18:17.804272 done.
10772 12:18:17.832982 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10773 12:18:17.887032 <4>[ 16.077252] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 12:18:18.005936 <4>[ 16.196627] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 12:18:18.121840 <4>[ 16.312400] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 12:18:18.237756 <4>[ 16.428322] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 12:18:18.353759 <4>[ 16.544291] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 12:18:18.469414 <4>[ 16.660201] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 12:18:18.585480 <4>[ 16.776152] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 12:18:18.701567 <4>[ 16.892134] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 12:18:18.817884 <4>[ 17.008339] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 12:18:18.829852 <6>[ 17.027024] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10783 12:18:18.924754 <3>[ 17.122006] mt7921e 0000:01:00.0: hardware init failed
10784 12:18:18.937588 IP-Config: no response after 2 secs - giving up
10785 12:18:18.985007 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10786 12:18:18.988334 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10787 12:18:18.994941 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10788 12:18:19.004779 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10789 12:18:19.011456 host : mt8192-asurada-spherion-r0-cbg-1
10790 12:18:19.017984 domain : lava-rack
10791 12:18:19.021252 rootserver: 192.168.201.1 rootpath:
10792 12:18:19.021379 filename :
10793 12:18:19.038717 done.
10794 12:18:19.045394 Begin: Running /scripts/nfs-bottom ... done.
10795 12:18:19.062572 Begin: Running /scripts/init-bottom ... done.
10796 12:18:20.151443 <6>[ 18.348852] NET: Registered PF_INET6 protocol family
10797 12:18:20.158069 <6>[ 18.355614] Segment Routing with IPv6
10798 12:18:20.161668 <6>[ 18.359601] In-situ OAM (IOAM) with IPv6
10799 12:18:20.261825 <30>[ 18.439538] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10800 12:18:20.264975 <30>[ 18.463341] systemd[1]: Detected architecture arm64.
10801 12:18:20.282188
10802 12:18:20.285495 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10803 12:18:20.285586
10804 12:18:20.303528 <30>[ 18.500595] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10805 12:18:20.764817 <30>[ 18.958958] systemd[1]: Queued start job for default target Graphical Interface.
10806 12:18:20.791067 <30>[ 18.988206] systemd[1]: Created slice system-getty.slice.
10807 12:18:20.797604 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10808 12:18:20.814766 <30>[ 19.011698] systemd[1]: Created slice system-modprobe.slice.
10809 12:18:20.820860 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10810 12:18:20.838257 <30>[ 19.035518] systemd[1]: Created slice system-serial\x2dgetty.slice.
10811 12:18:20.848082 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10812 12:18:20.862510 <30>[ 19.059999] systemd[1]: Created slice User and Session Slice.
10813 12:18:20.868895 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10814 12:18:20.889002 <30>[ 19.083127] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10815 12:18:20.898935 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10816 12:18:20.912921 <30>[ 19.107070] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10817 12:18:20.919393 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10818 12:18:20.940244 <30>[ 19.131094] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10819 12:18:20.946743 <30>[ 19.143121] systemd[1]: Reached target Local Encrypted Volumes.
10820 12:18:20.953327 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10821 12:18:20.970098 <30>[ 19.167383] systemd[1]: Reached target Paths.
10822 12:18:20.973370 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10823 12:18:20.989457 <30>[ 19.187017] systemd[1]: Reached target Remote File Systems.
10824 12:18:20.996002 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10825 12:18:21.009762 <30>[ 19.206994] systemd[1]: Reached target Slices.
10826 12:18:21.013153 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10827 12:18:21.029780 <30>[ 19.227010] systemd[1]: Reached target Swap.
10828 12:18:21.033259 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10829 12:18:21.053267 <30>[ 19.247318] systemd[1]: Listening on initctl Compatibility Named Pipe.
10830 12:18:21.059934 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10831 12:18:21.066511 <30>[ 19.262574] systemd[1]: Listening on Journal Audit Socket.
10832 12:18:21.072945 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10833 12:18:21.086365 <30>[ 19.283806] systemd[1]: Listening on Journal Socket (/dev/log).
10834 12:18:21.093239 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10835 12:18:21.110429 <30>[ 19.307796] systemd[1]: Listening on Journal Socket.
10836 12:18:21.117170 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10837 12:18:21.134066 <30>[ 19.328133] systemd[1]: Listening on Network Service Netlink Socket.
10838 12:18:21.140567 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10839 12:18:21.155610 <30>[ 19.352952] systemd[1]: Listening on udev Control Socket.
10840 12:18:21.162238 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10841 12:18:21.178138 <30>[ 19.375249] systemd[1]: Listening on udev Kernel Socket.
10842 12:18:21.184534 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10843 12:18:21.221949 <30>[ 19.419216] systemd[1]: Mounting Huge Pages File System...
10844 12:18:21.228603 Mounting [0;1;39mHuge Pages File System[0m...
10845 12:18:21.244122 <30>[ 19.441316] systemd[1]: Mounting POSIX Message Queue File System...
10846 12:18:21.250874 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10847 12:18:21.268225 <30>[ 19.465362] systemd[1]: Mounting Kernel Debug File System...
10848 12:18:21.274270 Mounting [0;1;39mKernel Debug File System[0m...
10849 12:18:21.293128 <30>[ 19.487209] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10850 12:18:21.311769 <30>[ 19.505839] systemd[1]: Starting Create list of static device nodes for the current kernel...
10851 12:18:21.318162 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10852 12:18:21.335987 <30>[ 19.533479] systemd[1]: Starting Load Kernel Module configfs...
10853 12:18:21.342455 Starting [0;1;39mLoad Kernel Module configfs[0m...
10854 12:18:21.359921 <30>[ 19.557437] systemd[1]: Starting Load Kernel Module drm...
10855 12:18:21.366439 Starting [0;1;39mLoad Kernel Module drm[0m...
10856 12:18:21.383970 <30>[ 19.581387] systemd[1]: Starting Load Kernel Module fuse...
10857 12:18:21.390703 Starting [0;1;39mLoad Kernel Module fuse[0m...
10858 12:18:21.416192 <6>[ 19.613527] fuse: init (API version 7.37)
10859 12:18:21.425732 <30>[ 19.613940] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10860 12:18:21.434541 <30>[ 19.631821] systemd[1]: Starting Journal Service...
10861 12:18:21.437743 Starting [0;1;39mJournal Service[0m...
10862 12:18:21.459470 <30>[ 19.656952] systemd[1]: Starting Load Kernel Modules...
10863 12:18:21.465931 Starting [0;1;39mLoad Kernel Modules[0m...
10864 12:18:21.488378 <30>[ 19.682404] systemd[1]: Starting Remount Root and Kernel File Systems...
10865 12:18:21.494778 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10866 12:18:21.512513 <30>[ 19.710099] systemd[1]: Starting Coldplug All udev Devices...
10867 12:18:21.519340 Starting [0;1;39mColdplug All udev Devices[0m...
10868 12:18:21.536342 <30>[ 19.733916] systemd[1]: Mounted Huge Pages File System.
10869 12:18:21.543138 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10870 12:18:21.557812 <30>[ 19.755415] systemd[1]: Mounted POSIX Message Queue File System.
10871 12:18:21.564552 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10872 12:18:21.582392 <3>[ 19.776531] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10873 12:18:21.588883 <30>[ 19.785851] systemd[1]: Mounted Kernel Debug File System.
10874 12:18:21.595545 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10875 12:18:21.613363 <3>[ 19.807267] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 12:18:21.623096 <30>[ 19.807827] systemd[1]: Finished Create list of static device nodes for the current kernel.
10877 12:18:21.630730 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10878 12:18:21.646535 <30>[ 19.844249] systemd[1]: modprobe@configfs.service: Succeeded.
10879 12:18:21.653910 <30>[ 19.850998] systemd[1]: Finished Load Kernel Module configfs.
10880 12:18:21.663736 <3>[ 19.856839] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 12:18:21.670493 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10882 12:18:21.686544 <30>[ 19.883907] systemd[1]: modprobe@drm.service: Succeeded.
10883 12:18:21.696371 <3>[ 19.887833] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 12:18:21.703118 <30>[ 19.890130] systemd[1]: Finished Load Kernel Module drm.
10885 12:18:21.709157 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10886 12:18:21.722862 <30>[ 19.920123] systemd[1]: modprobe@fuse.service: Succeeded.
10887 12:18:21.732389 <3>[ 19.921014] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 12:18:21.739067 <30>[ 19.926428] systemd[1]: Finished Load Kernel Module fuse.
10889 12:18:21.745787 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10890 12:18:21.759067 <30>[ 19.956334] systemd[1]: Finished Load Kernel Modules.
10891 12:18:21.768696 <3>[ 19.958081] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 12:18:21.775479 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10893 12:18:21.792006 <30>[ 19.989134] systemd[1]: Finished Remount Root and Kernel File Systems.
10894 12:18:21.802097 <3>[ 19.995043] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 12:18:21.808680 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10896 12:18:21.836227 <3>[ 20.030144] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 12:18:21.857848 <30>[ 20.055488] systemd[1]: Mounting FUSE Control File System...
10898 12:18:21.864908 Mounting [0;1;39mFUSE Control File System[0m...
10899 12:18:21.887447 <30>[ 20.081608] systemd[1]: Mounting Kernel Configuration File System...
10900 12:18:21.890956 Mounting [0;1;39mKernel Configuration File System[0m...
10901 12:18:21.915097 <30>[ 20.109571] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10902 12:18:21.925063 <30>[ 20.119308] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10903 12:18:21.935101 <30>[ 20.132259] systemd[1]: Starting Load/Save Random Seed...
10904 12:18:21.941205 Starting [0;1;39mLoad/Save Random Seed[0m...
10905 12:18:21.956647 <30>[ 20.154114] systemd[1]: Starting Apply Kernel Variables...
10906 12:18:21.963228 Starting [0;1;39mApply Kernel Variables[0m...
10907 12:18:21.981496 <30>[ 20.179108] systemd[1]: Starting Create System Users...
10908 12:18:21.988127 Starting [0;1;39mCreate System Users[0m...
10909 12:18:22.004260 <30>[ 20.201117] systemd[1]: Started Journal Service.
10910 12:18:22.014430 [[0;32m OK [0m] Started [0;1;39mJournal Ser<4>[ 20.209412] power_supply_show_property: 2 callbacks suppressed
10911 12:18:22.014526 vice[0m.
10912 12:18:22.024387 <3>[ 20.209424] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 12:18:22.031046 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10914 12:18:22.047295 <3>[ 20.241546] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 12:18:22.054258 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10916 12:18:22.070325 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10917 12:18:22.091040 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10918 12:18:22.102724 <3>[ 20.297306] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 12:18:22.113044 <3>[ 20.298074] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10920 12:18:22.129513 <4>[ 20.306136] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10921 12:18:22.136516 <3>[ 20.330541] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10922 12:18:22.143169 <3>[ 20.336847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 12:18:22.149706 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10924 12:18:22.177462 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev<3>[ 20.370147] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 12:18:22.177569 Devices[0m.
10926 12:18:22.193395 See 'systemctl status systemd-udev-trigger.service' for details.
10927 12:18:22.210176 <3>[ 20.404282] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 12:18:22.243213 <3>[ 20.437638] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 12:18:22.250331 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10930 12:18:22.275835 Starting [0;1;39mCreate Static Device <3>[ 20.468808] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 12:18:22.278968 Nodes in /dev[0m...
10932 12:18:22.308848 <3>[ 20.503218] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 12:18:22.323642 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10934 12:18:22.341633 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10935 12:18:22.357672 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10936 12:18:22.385471 <46>[ 20.579620] systemd-journald[295]: Received client request to flush runtime journal.
10937 12:18:22.418318 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10938 12:18:23.750882 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10939 12:18:23.789962 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10940 12:18:23.811475 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10941 12:18:23.834923 Starting [0;1;39mNetwork Service[0m...
10942 12:18:24.158194 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10943 12:18:24.184371 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10944 12:18:24.245484 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10945 12:18:24.393480 <6>[ 22.591243] remoteproc remoteproc0: powering up scp
10946 12:18:24.409179 <4>[ 22.603828] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10947 12:18:24.415720 <3>[ 22.613707] remoteproc remoteproc0: request_firmware failed: -2
10948 12:18:24.425580 <3>[ 22.619900] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10949 12:18:24.515221 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10950 12:18:24.532731 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10951 12:18:24.570012 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10952 12:18:24.585913 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10953 12:18:24.605877 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10954 12:18:24.626941 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10955 12:18:24.645850 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10956 12:18:24.697774 Starting [0;1;39mNetwork Name Resolution[0m...
10957 12:18:24.721383 Starting [0;1;39mNetwork Time Synchronization[0m...
10958 12:18:24.739932 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10959 12:18:24.778570 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10960 12:18:24.962665 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10961 12:18:24.981811 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10962 12:18:25.000615 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10963 12:18:25.013119 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10964 12:18:25.029363 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10965 12:18:25.132126 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10966 12:18:25.182003 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10967 12:18:25.210104 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10968 12:18:25.761392 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10969 12:18:25.773082 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10970 12:18:25.940554 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10971 12:18:25.957327 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10972 12:18:25.977207 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10973 12:18:26.025457 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10974 12:18:26.341065 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10975 12:18:26.377628 Starting [0;1;39mUser Login Management[0m...
10976 12:18:26.393986 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10977 12:18:26.410443 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10978 12:18:26.428363 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10979 12:18:26.481680 Starting [0;1;39mPermit User Sessions[0m...
10980 12:18:26.599501 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10981 12:18:26.658314 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10982 12:18:26.677752 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10983 12:18:26.693578 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10984 12:18:26.718151 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10985 12:18:26.738901 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10986 12:18:26.746581 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10987 12:18:26.765516 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10988 12:18:26.805216 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10989 12:18:26.838406 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10990 12:18:26.904289
10991 12:18:26.904416
10992 12:18:26.907837 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10993 12:18:26.907964
10994 12:18:26.943162 debian-bullseye-arm64 login: root (automatic login)
10995 12:18:26.943282
10996 12:18:26.943367
10997 12:18:27.221016 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023 aarch64
10998 12:18:27.221158
10999 12:18:27.227920 The programs included with the Debian GNU/Linux system are free software;
11000 12:18:27.234156 the exact distribution terms for each program are described in the
11001 12:18:27.237774 individual files in /usr/share/doc/*/copyright.
11002 12:18:27.237898
11003 12:18:27.244173 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11004 12:18:27.247231 permitted by applicable law.
11005 12:18:27.969360 Matched prompt #10: / #
11007 12:18:27.969663 Setting prompt string to ['/ #']
11008 12:18:27.969769 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11010 12:18:27.970111 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11011 12:18:27.970242 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11012 12:18:27.970357 Setting prompt string to ['/ #']
11013 12:18:27.970467 Forcing a shell prompt, looking for ['/ #']
11015 12:18:28.020734 / #
11016 12:18:28.020926 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11017 12:18:28.021008 Waiting using forced prompt support (timeout 00:02:30)
11018 12:18:28.025719
11019 12:18:28.026019 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11020 12:18:28.026125 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11022 12:18:28.126450 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605441/extract-nfsrootfs-oz4520mr'
11023 12:18:28.131307 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605441/extract-nfsrootfs-oz4520mr'
11025 12:18:28.231868 / # export NFS_SERVER_IP='192.168.201.1'
11026 12:18:28.236739 export NFS_SERVER_IP='192.168.201.1'
11027 12:18:28.237081 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11028 12:18:28.237238 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11029 12:18:28.237373 end: 2 depthcharge-action (duration 00:01:24) [common]
11030 12:18:28.237520 start: 3 lava-test-retry (timeout 00:07:55) [common]
11031 12:18:28.237673 start: 3.1 lava-test-shell (timeout 00:07:55) [common]
11032 12:18:28.237757 Using namespace: common
11034 12:18:28.338086 / # #
11035 12:18:28.338260 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11036 12:18:28.343074 #
11037 12:18:28.343340 Using /lava-10605441
11039 12:18:28.443666 / # export SHELL=/bin/bash
11040 12:18:28.448879 export SHELL=/bin/bash
11042 12:18:28.549557 / # . /lava-10605441/environment
11043 12:18:28.554154 . /lava-10605441/environment
11045 12:18:28.657866 / # /lava-10605441/bin/lava-test-runner /lava-10605441/0
11046 12:18:28.658023 Test shell timeout: 10s (minimum of the action and connection timeout)
11047 12:18:28.662732 /lava-10605441/bin/lava-test-runner /lava-10605441/0
11048 12:18:28.869924 + export TESTRUN_ID=0_timesync-off
11049 12:18:28.873315 + TESTRUN_ID=0_timesync-off
11050 12:18:28.876402 + cd /lava-10605441/0/tests/0_timesync-off
11051 12:18:28.879686 ++ cat uuid
11052 12:18:28.879770 + UUID=10605441_1.6.2.3.1
11053 12:18:28.882934 + set +x
11054 12:18:28.886539 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10605441_1.6.2.3.1>
11055 12:18:28.886802 Received signal: <STARTRUN> 0_timesync-off 10605441_1.6.2.3.1
11056 12:18:28.886880 Starting test lava.0_timesync-off (10605441_1.6.2.3.1)
11057 12:18:28.886969 Skipping test definition patterns.
11058 12:18:28.889958 + systemctl stop systemd-timesyncd
11059 12:18:28.911478 + set +x
11060 12:18:28.914746 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10605441_1.6.2.3.1>
11061 12:18:28.915018 Received signal: <ENDRUN> 0_timesync-off 10605441_1.6.2.3.1
11062 12:18:28.915124 Ending use of test pattern.
11063 12:18:28.915214 Ending test lava.0_timesync-off (10605441_1.6.2.3.1), duration 0.03
11065 12:18:28.955362 + export TESTRUN_ID=1_kselftest-rtc
11066 12:18:28.958523 + TESTRUN_ID=1_kselftest-rtc
11067 12:18:28.961947 + cd /lava-10605441/0/tests/1_kselftest-rtc
11068 12:18:28.964781 ++ cat uuid
11069 12:18:28.968248 + UUID=10605441_1.6.2.3.5
11070 12:18:28.968349 + set +x
11071 12:18:28.971536 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 10605441_1.6.2.3.5>
11072 12:18:28.971807 Received signal: <STARTRUN> 1_kselftest-rtc 10605441_1.6.2.3.5
11073 12:18:28.971880 Starting test lava.1_kselftest-rtc (10605441_1.6.2.3.5)
11074 12:18:28.971962 Skipping test definition patterns.
11075 12:18:28.974846 + cd ./automated/linux/kselftest/
11076 12:18:29.004336 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11077 12:18:29.012726 INFO: install_deps skipped
11078 12:18:29.114310 --2023-06-06 12:18:26-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11079 12:18:29.134600 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11080 12:18:29.282140 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11081 12:18:29.428984 HTTP request sent, awaiting response... 200 OK
11082 12:18:29.432073 Length: 2704052 (2.6M) [application/octet-stream]
11083 12:18:29.435352 Saving to: 'kselftest.tar.xz'
11084 12:18:29.435762
11085 12:18:29.436070
11086 12:18:29.721632 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11087 12:18:30.015583 kselftest.tar.xz 1%[ ] 46.39K 159KB/s
11088 12:18:30.358373 kselftest.tar.xz 8%[> ] 218.91K 374KB/s
11089 12:18:30.664085 kselftest.tar.xz 30%[=====> ] 817.06K 880KB/s
11090 12:18:30.757776 kselftest.tar.xz 76%[==============> ] 1.97M 1.60MB/s
11091 12:18:30.763757 kselftest.tar.xz 100%[===================>] 2.58M 1.94MB/s in 1.3s
11092 12:18:30.763853
11093 12:18:30.998440 2023-06-06 12:18:28 (1.94 MB/s) - 'kselftest.tar.xz' saved [2704052/2704052]
11094 12:18:30.998592
11095 12:18:36.341090 skiplist:
11096 12:18:36.344353 ========================================
11097 12:18:36.347596 ========================================
11098 12:18:36.376184 rtc:rtctest
11099 12:18:36.390405 ============== Tests to run ===============
11100 12:18:36.390532 rtc:rtctest
11101 12:18:36.393358 ===========End Tests to run ===============
11102 12:18:36.464584 <12>[ 34.663786] kselftest: Running tests in rtc
11103 12:18:36.472426 TAP version 13
11104 12:18:36.483324 1..1
11105 12:18:36.505223 # selftests: rtc: rtctest
11106 12:18:36.849637 # TAP version 13
11107 12:18:36.849779 # 1..8
11108 12:18:36.852471 # # Starting 8 tests from 2 test cases.
11109 12:18:36.855837 # # RUN rtc.date_read ...
11110 12:18:36.862591 # # rtctest.c:49:date_read:Current RTC date/time is 06/06/2023 12:18:33.
11111 12:18:36.865904 # # OK rtc.date_read
11112 12:18:36.869326 # ok 1 rtc.date_read
11113 12:18:36.872256 # # RUN rtc.date_read_loop ...
11114 12:18:36.882337 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11115 12:18:47.951069 <6>[ 46.154919] vpu: disabling
11116 12:18:47.954253 <6>[ 46.157968] vproc2: disabling
11117 12:18:47.957829 <6>[ 46.161239] vproc1: disabling
11118 12:18:47.961220 <6>[ 46.164500] vaud18: disabling
11119 12:18:47.967618 <6>[ 46.167905] vsram_others: disabling
11120 12:18:47.970906 <6>[ 46.171775] va09: disabling
11121 12:18:47.974574 <6>[ 46.174876] vsram_md: disabling
11122 12:18:47.974658 <6>[ 46.178359] Vgpu: disabling
11123 12:19:06.752174 # # rtctest.c:115:date_read_loop:Performed 2661 RTC time reads.
11124 12:19:06.755558 # # OK rtc.date_read_loop
11125 12:19:06.758817 # ok 2 rtc.date_read_loop
11126 12:19:06.762204 # # RUN rtc.uie_read ...
11127 12:19:09.731648 # # OK rtc.uie_read
11128 12:19:09.734961 # ok 3 rtc.uie_read
11129 12:19:09.737928 # # RUN rtc.uie_select ...
11130 12:19:12.731304 # # OK rtc.uie_select
11131 12:19:12.734763 # ok 4 rtc.uie_select
11132 12:19:12.737996 # # RUN rtc.alarm_alm_set ...
11133 12:19:12.744323 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 12:19:13.
11134 12:19:12.747895 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11135 12:19:12.754038 # # alarm_alm_set: Test terminated by assertion
11136 12:19:12.757623 # # FAIL rtc.alarm_alm_set
11137 12:19:12.760562 # not ok 5 rtc.alarm_alm_set
11138 12:19:12.763841 # # RUN rtc.alarm_wkalm_set ...
11139 12:19:12.770423 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 06/06/2023 12:19:13.
11140 12:19:15.733778 # # OK rtc.alarm_wkalm_set
11141 12:19:15.733931 # ok 6 rtc.alarm_wkalm_set
11142 12:19:15.740020 # # RUN rtc.alarm_alm_set_minute ...
11143 12:19:15.743297 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 12:20:00.
11144 12:19:15.749981 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11145 12:19:15.756572 # # alarm_alm_set_minute: Test terminated by assertion
11146 12:19:15.760024 # # FAIL rtc.alarm_alm_set_minute
11147 12:19:15.763496 # not ok 7 rtc.alarm_alm_set_minute
11148 12:19:15.766384 # # RUN rtc.alarm_wkalm_set_minute ...
11149 12:19:15.773080 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 06/06/2023 12:20:00.
11150 12:20:02.728437 # # OK rtc.alarm_wkalm_set_minute
11151 12:20:02.731300 # ok 8 rtc.alarm_wkalm_set_minute
11152 12:20:02.734720 # # FAILED: 6 / 8 tests passed.
11153 12:20:02.738403 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11154 12:20:02.741692 not ok 1 selftests: rtc: rtctest # exit=1
11155 12:20:03.249387 rtc_rtctest_rtc_date_read pass
11156 12:20:03.252705 rtc_rtctest_rtc_date_read_loop pass
11157 12:20:03.255873 rtc_rtctest_rtc_uie_read pass
11158 12:20:03.259536 rtc_rtctest_rtc_uie_select pass
11159 12:20:03.262940 rtc_rtctest_rtc_alarm_alm_set fail
11160 12:20:03.265830 rtc_rtctest_rtc_alarm_wkalm_set pass
11161 12:20:03.269177 rtc_rtctest_rtc_alarm_alm_set_minute fail
11162 12:20:03.272567 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11163 12:20:03.275620 rtc_rtctest fail
11164 12:20:03.278674 + ../../utils/send-to-lava.sh ./output/result.txt
11165 12:20:03.327562 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11167 12:20:03.330495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11168 12:20:03.382486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11169 12:20:03.383196 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11171 12:20:03.425135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11172 12:20:03.425834 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11174 12:20:03.472986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11175 12:20:03.473706 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11177 12:20:03.512050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11178 12:20:03.512325 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11180 12:20:03.548654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11181 12:20:03.548933 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11183 12:20:03.588226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11184 12:20:03.588957 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11186 12:20:03.641929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11187 12:20:03.642632 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11189 12:20:03.673818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11190 12:20:03.673927 + set +x
11191 12:20:03.674204 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11193 12:20:03.680457 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 10605441_1.6.2.3.5>
11194 12:20:03.680715 Received signal: <ENDRUN> 1_kselftest-rtc 10605441_1.6.2.3.5
11195 12:20:03.680831 Ending use of test pattern.
11196 12:20:03.680908 Ending test lava.1_kselftest-rtc (10605441_1.6.2.3.5), duration 94.71
11198 12:20:03.681171 ok: lava_test_shell seems to have completed
11199 12:20:03.681323 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
11200 12:20:03.681432 end: 3.1 lava-test-shell (duration 00:01:35) [common]
11201 12:20:03.681559 end: 3 lava-test-retry (duration 00:01:35) [common]
11202 12:20:03.681662 start: 4 finalize (timeout 00:06:20) [common]
11203 12:20:03.681792 start: 4.1 power-off (timeout 00:00:30) [common]
11204 12:20:03.682085 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11205 12:20:03.758017 >> Command sent successfully.
11206 12:20:03.762841 Returned 0 in 0 seconds
11207 12:20:03.863431 end: 4.1 power-off (duration 00:00:00) [common]
11209 12:20:03.863795 start: 4.2 read-feedback (timeout 00:06:19) [common]
11211 12:20:03.864362 Listened to connection for namespace 'common' for up to 1s
11212 12:20:04.865023 Finalising connection for namespace 'common'
11213 12:20:04.865712 Disconnecting from shell: Finalise
11214 12:20:04.866170 / #
11215 12:20:04.967189 end: 4.2 read-feedback (duration 00:00:01) [common]
11216 12:20:04.967905 end: 4 finalize (duration 00:00:01) [common]
11217 12:20:04.968558 Cleaning after the job
11218 12:20:04.969118 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/ramdisk
11219 12:20:04.979134 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/kernel
11220 12:20:05.009501 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/dtb
11221 12:20:05.009868 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/nfsrootfs
11222 12:20:05.081449 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605441/tftp-deploy-gxdu5qj5/modules
11223 12:20:05.086639 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605441
11224 12:20:05.600908 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605441
11225 12:20:05.601095 Job finished correctly