Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 31
1 12:13:58.872350 lava-dispatcher, installed at version: 2023.05.1
2 12:13:58.872592 start: 0 validate
3 12:13:58.872759 Start time: 2023-06-06 12:13:58.872751+00:00 (UTC)
4 12:13:58.872904 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:13:58.873036 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 12:13:59.159830 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:13:59.160011 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:13:59.445503 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:13:59.445737 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:13:59.725550 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:13:59.725766 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:14:00.011216 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:14:00.011405 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:14:00.304445 validate duration: 1.43
16 12:14:00.304704 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:14:00.304801 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:14:00.304892 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:14:00.305015 Not decompressing ramdisk as can be used compressed.
20 12:14:00.305098 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 12:14:00.305163 saving as /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/ramdisk/initrd.cpio.gz
22 12:14:00.305226 total size: 4665601 (4MB)
23 12:14:00.306305 progress 0% (0MB)
24 12:14:00.307806 progress 5% (0MB)
25 12:14:00.309058 progress 10% (0MB)
26 12:14:00.310313 progress 15% (0MB)
27 12:14:00.311657 progress 20% (0MB)
28 12:14:00.312885 progress 25% (1MB)
29 12:14:00.314102 progress 30% (1MB)
30 12:14:00.315412 progress 35% (1MB)
31 12:14:00.316646 progress 40% (1MB)
32 12:14:00.318023 progress 45% (2MB)
33 12:14:00.319391 progress 50% (2MB)
34 12:14:00.320615 progress 55% (2MB)
35 12:14:00.321830 progress 60% (2MB)
36 12:14:00.323178 progress 65% (2MB)
37 12:14:00.324419 progress 70% (3MB)
38 12:14:00.325638 progress 75% (3MB)
39 12:14:00.326974 progress 80% (3MB)
40 12:14:00.328389 progress 85% (3MB)
41 12:14:00.329607 progress 90% (4MB)
42 12:14:00.330918 progress 95% (4MB)
43 12:14:00.332169 progress 100% (4MB)
44 12:14:00.332326 4MB downloaded in 0.03s (164.20MB/s)
45 12:14:00.332475 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:14:00.332720 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:14:00.332807 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:14:00.332891 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:14:00.333021 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:14:00.333095 saving as /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/kernel/Image
52 12:14:00.333157 total size: 45746688 (43MB)
53 12:14:00.333218 No compression specified
54 12:14:00.334312 progress 0% (0MB)
55 12:14:00.345942 progress 5% (2MB)
56 12:14:00.358169 progress 10% (4MB)
57 12:14:00.370237 progress 15% (6MB)
58 12:14:00.382113 progress 20% (8MB)
59 12:14:00.393933 progress 25% (10MB)
60 12:14:00.405700 progress 30% (13MB)
61 12:14:00.418055 progress 35% (15MB)
62 12:14:00.430005 progress 40% (17MB)
63 12:14:00.441490 progress 45% (19MB)
64 12:14:00.452974 progress 50% (21MB)
65 12:14:00.464536 progress 55% (24MB)
66 12:14:00.476599 progress 60% (26MB)
67 12:14:00.488294 progress 65% (28MB)
68 12:14:00.500220 progress 70% (30MB)
69 12:14:00.511807 progress 75% (32MB)
70 12:14:00.523162 progress 80% (34MB)
71 12:14:00.535135 progress 85% (37MB)
72 12:14:00.546798 progress 90% (39MB)
73 12:14:00.558189 progress 95% (41MB)
74 12:14:00.569695 progress 100% (43MB)
75 12:14:00.569850 43MB downloaded in 0.24s (184.32MB/s)
76 12:14:00.570042 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:14:00.570414 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:14:00.570543 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:14:00.570705 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:14:00.570872 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:14:00.570975 saving as /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/dtb/mt8192-asurada-spherion-r0.dtb
83 12:14:00.571068 total size: 46924 (0MB)
84 12:14:00.571155 No compression specified
85 12:14:00.572311 progress 69% (0MB)
86 12:14:00.572582 progress 100% (0MB)
87 12:14:00.572733 0MB downloaded in 0.00s (26.90MB/s)
88 12:14:00.572851 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:14:00.573070 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:14:00.573154 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:14:00.573236 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:14:00.573349 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 12:14:00.573418 saving as /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/nfsrootfs/full.rootfs.tar
95 12:14:00.573478 total size: 200770336 (191MB)
96 12:14:00.573538 Using unxz to decompress xz
97 12:14:00.576836 progress 0% (0MB)
98 12:14:01.120392 progress 5% (9MB)
99 12:14:01.658249 progress 10% (19MB)
100 12:14:02.296791 progress 15% (28MB)
101 12:14:02.680728 progress 20% (38MB)
102 12:14:03.011322 progress 25% (47MB)
103 12:14:03.642774 progress 30% (57MB)
104 12:14:04.235148 progress 35% (67MB)
105 12:14:04.882758 progress 40% (76MB)
106 12:14:05.505734 progress 45% (86MB)
107 12:14:06.121366 progress 50% (95MB)
108 12:14:06.765254 progress 55% (105MB)
109 12:14:07.429309 progress 60% (114MB)
110 12:14:07.550183 progress 65% (124MB)
111 12:14:07.697919 progress 70% (134MB)
112 12:14:07.802293 progress 75% (143MB)
113 12:14:07.878571 progress 80% (153MB)
114 12:14:07.947925 progress 85% (162MB)
115 12:14:08.047857 progress 90% (172MB)
116 12:14:08.333242 progress 95% (181MB)
117 12:14:08.932806 progress 100% (191MB)
118 12:14:08.937606 191MB downloaded in 8.36s (22.89MB/s)
119 12:14:08.937935 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:14:08.938337 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:14:08.938459 start: 1.5 download-retry (timeout 00:09:51) [common]
123 12:14:08.938577 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 12:14:08.938756 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:14:08.938857 saving as /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/modules/modules.tar
126 12:14:08.938947 total size: 8553528 (8MB)
127 12:14:08.939039 Using unxz to decompress xz
128 12:14:08.942399 progress 0% (0MB)
129 12:14:08.963971 progress 5% (0MB)
130 12:14:08.988192 progress 10% (0MB)
131 12:14:09.020577 progress 15% (1MB)
132 12:14:09.047762 progress 20% (1MB)
133 12:14:09.072890 progress 25% (2MB)
134 12:14:09.098423 progress 30% (2MB)
135 12:14:09.124468 progress 35% (2MB)
136 12:14:09.150723 progress 40% (3MB)
137 12:14:09.176811 progress 45% (3MB)
138 12:14:09.201872 progress 50% (4MB)
139 12:14:09.226356 progress 55% (4MB)
140 12:14:09.253559 progress 60% (4MB)
141 12:14:09.282666 progress 65% (5MB)
142 12:14:09.310061 progress 70% (5MB)
143 12:14:09.336596 progress 75% (6MB)
144 12:14:09.365922 progress 80% (6MB)
145 12:14:09.392993 progress 85% (6MB)
146 12:14:09.419213 progress 90% (7MB)
147 12:14:09.443809 progress 95% (7MB)
148 12:14:09.470530 progress 100% (8MB)
149 12:14:09.475286 8MB downloaded in 0.54s (15.21MB/s)
150 12:14:09.475550 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:14:09.475817 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:14:09.475913 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:14:09.476007 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:14:12.886158 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10605418/extract-nfsrootfs-xjdocy5u
156 12:14:12.886368 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 12:14:12.886489 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:14:12.886668 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig
159 12:14:12.886821 makedir: /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin
160 12:14:12.886936 makedir: /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/tests
161 12:14:12.887048 makedir: /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/results
162 12:14:12.887164 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-add-keys
163 12:14:12.887384 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-add-sources
164 12:14:12.887569 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-background-process-start
165 12:14:12.887712 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-background-process-stop
166 12:14:12.887862 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-common-functions
167 12:14:12.888040 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-echo-ipv4
168 12:14:12.888180 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-install-packages
169 12:14:12.888318 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-installed-packages
170 12:14:12.888464 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-os-build
171 12:14:12.888610 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-probe-channel
172 12:14:12.888776 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-probe-ip
173 12:14:12.888937 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-target-ip
174 12:14:12.889083 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-target-mac
175 12:14:12.889224 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-target-storage
176 12:14:12.889390 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-test-case
177 12:14:12.889527 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-test-event
178 12:14:12.889664 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-test-feedback
179 12:14:12.889812 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-test-raise
180 12:14:12.889952 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-test-reference
181 12:14:12.890119 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-test-runner
182 12:14:12.890287 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-test-set
183 12:14:12.890460 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-test-shell
184 12:14:12.890601 Updating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-add-keys (debian)
185 12:14:12.890759 Updating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-add-sources (debian)
186 12:14:12.890928 Updating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-install-packages (debian)
187 12:14:12.891085 Updating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-installed-packages (debian)
188 12:14:12.891244 Updating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/bin/lava-os-build (debian)
189 12:14:12.891449 Creating /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/environment
190 12:14:12.891587 LAVA metadata
191 12:14:12.891691 - LAVA_JOB_ID=10605418
192 12:14:12.891792 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:14:12.891947 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:14:12.892046 skipped lava-vland-overlay
195 12:14:12.892144 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:14:12.892241 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:14:12.892319 skipped lava-multinode-overlay
198 12:14:12.892419 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:14:12.892540 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:14:12.892651 Loading test definitions
201 12:14:12.892764 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:14:12.892875 Using /lava-10605418 at stage 0
203 12:14:12.893204 uuid=10605418_1.6.2.3.1 testdef=None
204 12:14:12.893301 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:14:12.893403 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:14:12.893868 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:14:12.894119 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:14:12.894680 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:14:12.894948 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:14:12.895586 runner path: /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/0/tests/0_timesync-off test_uuid 10605418_1.6.2.3.1
213 12:14:12.895758 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:14:12.896013 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:14:12.896105 Using /lava-10605418 at stage 0
217 12:14:12.896232 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:14:12.896346 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/0/tests/1_kselftest-tpm2'
219 12:14:20.591138 Running '/usr/bin/git checkout kernelci.org
220 12:14:20.741849 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 12:14:20.742800 uuid=10605418_1.6.2.3.5 testdef=None
222 12:14:20.743027 end: 1.6.2.3.5 git-repo-action (duration 00:00:08) [common]
224 12:14:20.743441 start: 1.6.2.3.6 test-overlay (timeout 00:09:40) [common]
225 12:14:20.744672 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:14:20.745050 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:40) [common]
228 12:14:20.746696 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:14:20.747092 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:40) [common]
231 12:14:20.748135 runner path: /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/0/tests/1_kselftest-tpm2 test_uuid 10605418_1.6.2.3.5
232 12:14:20.748232 BOARD='mt8192-asurada-spherion-r0'
233 12:14:20.748298 BRANCH='cip-gitlab'
234 12:14:20.748361 SKIPFILE='/dev/null'
235 12:14:20.748421 SKIP_INSTALL='True'
236 12:14:20.748478 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:14:20.748535 TST_CASENAME=''
238 12:14:20.748591 TST_CMDFILES='tpm2'
239 12:14:20.748735 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:14:20.748997 Creating lava-test-runner.conf files
242 12:14:20.749088 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605418/lava-overlay-vjbqdmig/lava-10605418/0 for stage 0
243 12:14:20.749190 - 0_timesync-off
244 12:14:20.749268 - 1_kselftest-tpm2
245 12:14:20.749365 end: 1.6.2.3 test-definition (duration 00:00:08) [common]
246 12:14:20.749459 start: 1.6.2.4 compress-overlay (timeout 00:09:40) [common]
247 12:14:28.599830 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:14:28.599992 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:32) [common]
249 12:14:28.600084 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:14:28.600186 end: 1.6.2 lava-overlay (duration 00:00:16) [common]
251 12:14:28.600277 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
252 12:14:28.755960 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:14:28.756313 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
254 12:14:28.756432 extracting modules file /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605418/extract-nfsrootfs-xjdocy5u
255 12:14:28.959550 extracting modules file /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605418/extract-overlay-ramdisk-sfz5vbw_/ramdisk
256 12:14:29.166165 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:14:29.166328 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
258 12:14:29.166425 [common] Applying overlay to NFS
259 12:14:29.166495 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605418/compress-overlay-6k1fpwzm/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605418/extract-nfsrootfs-xjdocy5u
260 12:14:30.074952 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:14:30.075144 start: 1.6.6 configure-preseed-file (timeout 00:09:30) [common]
262 12:14:30.075257 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:14:30.075415 start: 1.6.7 compress-ramdisk (timeout 00:09:30) [common]
264 12:14:30.075499 Building ramdisk /var/lib/lava/dispatcher/tmp/10605418/extract-overlay-ramdisk-sfz5vbw_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605418/extract-overlay-ramdisk-sfz5vbw_/ramdisk
265 12:14:30.350889 >> 117807 blocks
266 12:14:32.303817 rename /var/lib/lava/dispatcher/tmp/10605418/extract-overlay-ramdisk-sfz5vbw_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/ramdisk/ramdisk.cpio.gz
267 12:14:32.304271 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:14:32.304396 start: 1.6.8 prepare-kernel (timeout 00:09:28) [common]
269 12:14:32.304498 start: 1.6.8.1 prepare-fit (timeout 00:09:28) [common]
270 12:14:32.304603 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/kernel/Image'
271 12:14:44.581906 Returned 0 in 12 seconds
272 12:14:44.682515 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/kernel/image.itb
273 12:14:45.003686 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:14:45.004037 output: Created: Tue Jun 6 13:14:44 2023
275 12:14:45.004117 output: Image 0 (kernel-1)
276 12:14:45.004184 output: Description:
277 12:14:45.004250 output: Created: Tue Jun 6 13:14:44 2023
278 12:14:45.004313 output: Type: Kernel Image
279 12:14:45.004376 output: Compression: lzma compressed
280 12:14:45.004439 output: Data Size: 10094623 Bytes = 9858.03 KiB = 9.63 MiB
281 12:14:45.004501 output: Architecture: AArch64
282 12:14:45.004558 output: OS: Linux
283 12:14:45.004616 output: Load Address: 0x00000000
284 12:14:45.004673 output: Entry Point: 0x00000000
285 12:14:45.004729 output: Hash algo: crc32
286 12:14:45.004785 output: Hash value: fd97082e
287 12:14:45.004839 output: Image 1 (fdt-1)
288 12:14:45.004893 output: Description: mt8192-asurada-spherion-r0
289 12:14:45.004947 output: Created: Tue Jun 6 13:14:44 2023
290 12:14:45.005001 output: Type: Flat Device Tree
291 12:14:45.005055 output: Compression: uncompressed
292 12:14:45.005109 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 12:14:45.005162 output: Architecture: AArch64
294 12:14:45.005216 output: Hash algo: crc32
295 12:14:45.005269 output: Hash value: 1df858fa
296 12:14:45.005323 output: Image 2 (ramdisk-1)
297 12:14:45.005375 output: Description: unavailable
298 12:14:45.005428 output: Created: Tue Jun 6 13:14:44 2023
299 12:14:45.005482 output: Type: RAMDisk Image
300 12:14:45.005535 output: Compression: Unknown Compression
301 12:14:45.005588 output: Data Size: 17641531 Bytes = 17228.06 KiB = 16.82 MiB
302 12:14:45.005642 output: Architecture: AArch64
303 12:14:45.005695 output: OS: Linux
304 12:14:45.005748 output: Load Address: unavailable
305 12:14:45.005801 output: Entry Point: unavailable
306 12:14:45.005855 output: Hash algo: crc32
307 12:14:45.005908 output: Hash value: edf35ae7
308 12:14:45.005961 output: Default Configuration: 'conf-1'
309 12:14:45.006014 output: Configuration 0 (conf-1)
310 12:14:45.006067 output: Description: mt8192-asurada-spherion-r0
311 12:14:45.006120 output: Kernel: kernel-1
312 12:14:45.006172 output: Init Ramdisk: ramdisk-1
313 12:14:45.006225 output: FDT: fdt-1
314 12:14:45.006278 output: Loadables: kernel-1
315 12:14:45.006331 output:
316 12:14:45.006526 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:14:45.006622 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:14:45.006724 end: 1.6 prepare-tftp-overlay (duration 00:00:36) [common]
319 12:14:45.006820 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:15) [common]
320 12:14:45.006899 No LXC device requested
321 12:14:45.006976 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:14:45.007059 start: 1.8 deploy-device-env (timeout 00:09:15) [common]
323 12:14:45.007137 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:14:45.007208 Checking files for TFTP limit of 4294967296 bytes.
325 12:14:45.007795 end: 1 tftp-deploy (duration 00:00:45) [common]
326 12:14:45.007933 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:14:45.008025 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:14:45.008147 substitutions:
329 12:14:45.008215 - {DTB}: 10605418/tftp-deploy-2hk8o711/dtb/mt8192-asurada-spherion-r0.dtb
330 12:14:45.008311 - {INITRD}: 10605418/tftp-deploy-2hk8o711/ramdisk/ramdisk.cpio.gz
331 12:14:45.008388 - {KERNEL}: 10605418/tftp-deploy-2hk8o711/kernel/Image
332 12:14:45.008463 - {LAVA_MAC}: None
333 12:14:45.008551 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10605418/extract-nfsrootfs-xjdocy5u
334 12:14:45.008607 - {NFS_SERVER_IP}: 192.168.201.1
335 12:14:45.008663 - {PRESEED_CONFIG}: None
336 12:14:45.008718 - {PRESEED_LOCAL}: None
337 12:14:45.008773 - {RAMDISK}: 10605418/tftp-deploy-2hk8o711/ramdisk/ramdisk.cpio.gz
338 12:14:45.008828 - {ROOT_PART}: None
339 12:14:45.008882 - {ROOT}: None
340 12:14:45.008935 - {SERVER_IP}: 192.168.201.1
341 12:14:45.008989 - {TEE}: None
342 12:14:45.009042 Parsed boot commands:
343 12:14:45.009095 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:14:45.009266 Parsed boot commands: tftpboot 192.168.201.1 10605418/tftp-deploy-2hk8o711/kernel/image.itb 10605418/tftp-deploy-2hk8o711/kernel/cmdline
345 12:14:45.009355 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:14:45.009437 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:14:45.009528 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:14:45.009614 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:14:45.009683 Not connected, no need to disconnect.
350 12:14:45.009757 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:14:45.009839 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:14:45.009912 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
353 12:14:45.013201 Setting prompt string to ['lava-test: # ']
354 12:14:45.013551 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:14:45.013689 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:14:45.013790 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:14:45.013886 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:14:45.014078 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 12:14:50.147383 >> Command sent successfully.
360 12:14:50.150458 Returned 0 in 5 seconds
361 12:14:50.250871 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:14:50.251208 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:14:50.251311 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:14:50.251455 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:14:50.251526 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:14:50.251597 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:14:50.251946 [Enter `^Ec?' for help]
369 12:14:50.423036
370 12:14:50.423223
371 12:14:50.423320 F0: 102B 0000
372 12:14:50.423428
373 12:14:50.423491 F3: 1001 0000 [0200]
374 12:14:50.426405
375 12:14:50.426474 F3: 1001 0000
376 12:14:50.426536
377 12:14:50.426594 F7: 102D 0000
378 12:14:50.426653
379 12:14:50.429827 F1: 0000 0000
380 12:14:50.429912
381 12:14:50.429979 V0: 0000 0000 [0001]
382 12:14:50.430044
383 12:14:50.433190 00: 0007 8000
384 12:14:50.433277
385 12:14:50.433344 01: 0000 0000
386 12:14:50.433409
387 12:14:50.436016 BP: 0C00 0209 [0000]
388 12:14:50.436100
389 12:14:50.436167 G0: 1182 0000
390 12:14:50.436229
391 12:14:50.440207 EC: 0000 0021 [4000]
392 12:14:50.440291
393 12:14:50.440358 S7: 0000 0000 [0000]
394 12:14:50.440453
395 12:14:50.443609 CC: 0000 0000 [0001]
396 12:14:50.443693
397 12:14:50.443759 T0: 0000 0040 [010F]
398 12:14:50.443850
399 12:14:50.443909 Jump to BL
400 12:14:50.443984
401 12:14:50.470289
402 12:14:50.470442
403 12:14:50.470572
404 12:14:50.477479 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:14:50.480807 ARM64: Exception handlers installed.
406 12:14:50.484858 ARM64: Testing exception
407 12:14:50.488204 ARM64: Done test exception
408 12:14:50.495010 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:14:50.504843 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:14:50.511765 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:14:50.521273 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:14:50.527917 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:14:50.534709 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:14:50.547621 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:14:50.553804 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:14:50.573075 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:14:50.576296 WDT: Last reset was cold boot
418 12:14:50.579641 SPI1(PAD0) initialized at 2873684 Hz
419 12:14:50.582967 SPI5(PAD0) initialized at 992727 Hz
420 12:14:50.586295 VBOOT: Loading verstage.
421 12:14:50.592856 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:14:50.596343 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:14:50.599888 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:14:50.603131 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:14:50.610389 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:14:50.617277 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:14:50.628163 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:14:50.628249
429 12:14:50.628316
430 12:14:50.638487 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:14:50.641955 ARM64: Exception handlers installed.
432 12:14:50.645355 ARM64: Testing exception
433 12:14:50.645440 ARM64: Done test exception
434 12:14:50.652004 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:14:50.654728 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:14:50.668666 Probing TPM: . done!
437 12:14:50.668759 TPM ready after 0 ms
438 12:14:50.676398 Connected to device vid:did:rid of 1ae0:0028:00
439 12:14:50.683069 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 12:14:50.743144 Initialized TPM device CR50 revision 0
441 12:14:50.755641 tlcl_send_startup: Startup return code is 0
442 12:14:50.755743 TPM: setup succeeded
443 12:14:50.766609 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:14:50.775606 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:14:50.790077 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:14:50.797157 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:14:50.800974 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:14:50.804802 in-header: 03 07 00 00 08 00 00 00
449 12:14:50.808069 in-data: aa e4 47 04 13 02 00 00
450 12:14:50.808155 Chrome EC: UHEPI supported
451 12:14:50.815579 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:14:50.819746 in-header: 03 95 00 00 08 00 00 00
453 12:14:50.823094 in-data: 18 20 20 08 00 00 00 00
454 12:14:50.823187 Phase 1
455 12:14:50.830629 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:14:50.834717 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:14:50.842085 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:14:50.842167 Recovery requested (1009000e)
459 12:14:50.854916 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:14:50.859042 tlcl_extend: response is 0
461 12:14:50.867188 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:14:50.873232 tlcl_extend: response is 0
463 12:14:50.879983 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:14:50.900024 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 12:14:50.906437 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:14:50.906588
467 12:14:50.906665
468 12:14:50.916579 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:14:50.919858 ARM64: Exception handlers installed.
470 12:14:50.923062 ARM64: Testing exception
471 12:14:50.923205 ARM64: Done test exception
472 12:14:50.945124 pmic_efuse_setting: Set efuses in 11 msecs
473 12:14:50.949151 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:14:50.955322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:14:50.958835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:14:50.962914 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:14:50.969905 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:14:50.973399 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:14:50.977615 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:14:50.984948 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:14:50.988342 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:14:50.991706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:14:50.999600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:14:51.003137 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:14:51.007293 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:14:51.009990 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:14:51.017665 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:14:51.025484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:14:51.028789 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:14:51.036761 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:14:51.040220 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:14:51.047805 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:14:51.051307 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:14:51.058578 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:14:51.062706 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:14:51.070145 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:14:51.073654 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:14:51.077850 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:14:51.085272 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:14:51.088593 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:14:51.095856 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:14:51.099813 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:14:51.103060 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:14:51.110440 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:14:51.113841 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:14:51.118026 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:14:51.125238 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:14:51.128387 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:14:51.135595 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:14:51.139991 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:14:51.143798 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:14:51.147832 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:14:51.154681 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:14:51.158750 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:14:51.162094 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:14:51.165506 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:14:51.169526 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:14:51.176578 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:14:51.179980 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:14:51.183951 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:14:51.187537 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:14:51.190907 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:14:51.194464 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:14:51.202286 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:14:51.209468 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:14:51.216879 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:14:51.220989 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:14:51.231264 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:14:51.239045 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:14:51.243062 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:14:51.246938 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:14:51.249844 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:14:51.258923 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 12:14:51.262213 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:14:51.270841 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 12:14:51.274260 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:14:51.282686 [RTC]rtc_get_frequency_meter,154: input=15, output=758
538 12:14:51.293082 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 12:14:51.301923 [RTC]rtc_get_frequency_meter,154: input=19, output=851
540 12:14:51.311786 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 12:14:51.320945 [RTC]rtc_get_frequency_meter,154: input=16, output=783
542 12:14:51.330463 [RTC]rtc_get_frequency_meter,154: input=16, output=782
543 12:14:51.339988 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 12:14:51.343479 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 12:14:51.350793 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 12:14:51.354595 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:14:51.357687 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:14:51.361519 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:14:51.365443 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:14:51.368814 ADC[4]: Raw value=906203 ID=7
551 12:14:51.372685 ADC[3]: Raw value=213810 ID=1
552 12:14:51.372776 RAM Code: 0x71
553 12:14:51.376074 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:14:51.383682 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:14:51.391233 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:14:51.398754 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:14:51.402224 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:14:51.406332 in-header: 03 07 00 00 08 00 00 00
559 12:14:51.409728 in-data: aa e4 47 04 13 02 00 00
560 12:14:51.409814 Chrome EC: UHEPI supported
561 12:14:51.416859 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:14:51.420955 in-header: 03 95 00 00 08 00 00 00
563 12:14:51.423984 in-data: 18 20 20 08 00 00 00 00
564 12:14:51.428017 MRC: failed to locate region type 0.
565 12:14:51.431608 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:14:51.435643 DRAM-K: Running full calibration
567 12:14:51.442875 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:14:51.446253 header.status = 0x0
569 12:14:51.446337 header.version = 0x6 (expected: 0x6)
570 12:14:51.450354 header.size = 0xd00 (expected: 0xd00)
571 12:14:51.454212 header.flags = 0x0
572 12:14:51.457544 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:14:51.478454 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 12:14:51.485446 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:14:51.485544 dram_init: ddr_geometry: 2
576 12:14:51.489738 [EMI] MDL number = 2
577 12:14:51.489825 [EMI] Get MDL freq = 0
578 12:14:51.493107 dram_init: ddr_type: 0
579 12:14:51.493193 is_discrete_lpddr4: 1
580 12:14:51.496553 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:14:51.496639
582 12:14:51.496707
583 12:14:51.500597 [Bian_co] ETT version 0.0.0.1
584 12:14:51.503987 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:14:51.504075
586 12:14:51.508065 dramc_set_vcore_voltage set vcore to 650000
587 12:14:51.511484 Read voltage for 800, 4
588 12:14:51.511569 Vio18 = 0
589 12:14:51.514883 Vcore = 650000
590 12:14:51.514987 Vdram = 0
591 12:14:51.515056 Vddq = 0
592 12:14:51.518919 Vmddr = 0
593 12:14:51.519005 dram_init: config_dvfs: 1
594 12:14:51.522222 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:14:51.529643 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:14:51.533677 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 12:14:51.537049 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 12:14:51.540536 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 12:14:51.544469 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 12:14:51.548532 MEM_TYPE=3, freq_sel=18
601 12:14:51.548646 sv_algorithm_assistance_LP4_1600
602 12:14:51.555554 ============ PULL DRAM RESETB DOWN ============
603 12:14:51.558823 ========== PULL DRAM RESETB DOWN end =========
604 12:14:51.562088 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:14:51.565277 ===================================
606 12:14:51.569082 LPDDR4 DRAM CONFIGURATION
607 12:14:51.572540 ===================================
608 12:14:51.572630 EX_ROW_EN[0] = 0x0
609 12:14:51.575876 EX_ROW_EN[1] = 0x0
610 12:14:51.575963 LP4Y_EN = 0x0
611 12:14:51.579844 WORK_FSP = 0x0
612 12:14:51.579931 WL = 0x2
613 12:14:51.583940 RL = 0x2
614 12:14:51.584029 BL = 0x2
615 12:14:51.587258 RPST = 0x0
616 12:14:51.587366 RD_PRE = 0x0
617 12:14:51.590870 WR_PRE = 0x1
618 12:14:51.590982 WR_PST = 0x0
619 12:14:51.594163 DBI_WR = 0x0
620 12:14:51.594249 DBI_RD = 0x0
621 12:14:51.597422 OTF = 0x1
622 12:14:51.600808 ===================================
623 12:14:51.604199 ===================================
624 12:14:51.604287 ANA top config
625 12:14:51.607738 ===================================
626 12:14:51.611084 DLL_ASYNC_EN = 0
627 12:14:51.614540 ALL_SLAVE_EN = 1
628 12:14:51.614627 NEW_RANK_MODE = 1
629 12:14:51.617248 DLL_IDLE_MODE = 1
630 12:14:51.620638 LP45_APHY_COMB_EN = 1
631 12:14:51.624062 TX_ODT_DIS = 1
632 12:14:51.624150 NEW_8X_MODE = 1
633 12:14:51.628603 ===================================
634 12:14:51.631917 ===================================
635 12:14:51.635241 data_rate = 1600
636 12:14:51.638431 CKR = 1
637 12:14:51.641763 DQ_P2S_RATIO = 8
638 12:14:51.645263 ===================================
639 12:14:51.648553 CA_P2S_RATIO = 8
640 12:14:51.648667 DQ_CA_OPEN = 0
641 12:14:51.651908 DQ_SEMI_OPEN = 0
642 12:14:51.655340 CA_SEMI_OPEN = 0
643 12:14:51.658830 CA_FULL_RATE = 0
644 12:14:51.661523 DQ_CKDIV4_EN = 1
645 12:14:51.661639 CA_CKDIV4_EN = 1
646 12:14:51.664900 CA_PREDIV_EN = 0
647 12:14:51.668736 PH8_DLY = 0
648 12:14:51.671874 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:14:51.675085 DQ_AAMCK_DIV = 4
650 12:14:51.678396 CA_AAMCK_DIV = 4
651 12:14:51.678513 CA_ADMCK_DIV = 4
652 12:14:51.681803 DQ_TRACK_CA_EN = 0
653 12:14:51.685091 CA_PICK = 800
654 12:14:51.688839 CA_MCKIO = 800
655 12:14:51.692227 MCKIO_SEMI = 0
656 12:14:51.695777 PLL_FREQ = 3068
657 12:14:51.695887 DQ_UI_PI_RATIO = 32
658 12:14:51.699173 CA_UI_PI_RATIO = 0
659 12:14:51.703415 ===================================
660 12:14:51.706835 ===================================
661 12:14:51.710349 memory_type:LPDDR4
662 12:14:51.710474 GP_NUM : 10
663 12:14:51.714447 SRAM_EN : 1
664 12:14:51.714529 MD32_EN : 0
665 12:14:51.717811 ===================================
666 12:14:51.721846 [ANA_INIT] >>>>>>>>>>>>>>
667 12:14:51.725313 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:14:51.728674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:14:51.731970 ===================================
670 12:14:51.732076 data_rate = 1600,PCW = 0X7600
671 12:14:51.735205 ===================================
672 12:14:51.738552 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:14:51.745408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:14:51.752109 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:14:51.755465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:14:51.758842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:14:51.762272 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:14:51.765665 [ANA_INIT] flow start
679 12:14:51.765807 [ANA_INIT] PLL >>>>>>>>
680 12:14:51.768391 [ANA_INIT] PLL <<<<<<<<
681 12:14:51.771817 [ANA_INIT] MIDPI >>>>>>>>
682 12:14:51.771903 [ANA_INIT] MIDPI <<<<<<<<
683 12:14:51.775132 [ANA_INIT] DLL >>>>>>>>
684 12:14:51.778939 [ANA_INIT] flow end
685 12:14:51.782180 ============ LP4 DIFF to SE enter ============
686 12:14:51.785384 ============ LP4 DIFF to SE exit ============
687 12:14:51.788692 [ANA_INIT] <<<<<<<<<<<<<
688 12:14:51.791959 [Flow] Enable top DCM control >>>>>
689 12:14:51.795235 [Flow] Enable top DCM control <<<<<
690 12:14:51.798502 Enable DLL master slave shuffle
691 12:14:51.801883 ==============================================================
692 12:14:51.805209 Gating Mode config
693 12:14:51.812174 ==============================================================
694 12:14:51.812260 Config description:
695 12:14:51.822219 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:14:51.828583 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:14:51.832517 SELPH_MODE 0: By rank 1: By Phase
698 12:14:51.838688 ==============================================================
699 12:14:51.842493 GAT_TRACK_EN = 1
700 12:14:51.845816 RX_GATING_MODE = 2
701 12:14:51.849174 RX_GATING_TRACK_MODE = 2
702 12:14:51.852339 SELPH_MODE = 1
703 12:14:51.855543 PICG_EARLY_EN = 1
704 12:14:51.855634 VALID_LAT_VALUE = 1
705 12:14:51.862217 ==============================================================
706 12:14:51.865714 Enter into Gating configuration >>>>
707 12:14:51.869151 Exit from Gating configuration <<<<
708 12:14:51.872587 Enter into DVFS_PRE_config >>>>>
709 12:14:51.882157 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:14:51.886031 Exit from DVFS_PRE_config <<<<<
711 12:14:51.889168 Enter into PICG configuration >>>>
712 12:14:51.892452 Exit from PICG configuration <<<<
713 12:14:51.895820 [RX_INPUT] configuration >>>>>
714 12:14:51.898928 [RX_INPUT] configuration <<<<<
715 12:14:51.902246 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:14:51.908855 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:14:51.915643 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:14:51.922510 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:14:51.929437 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:14:51.932123 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:14:51.938899 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:14:51.942282 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:14:51.946170 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:14:51.949403 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:14:51.952756 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:14:51.959373 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:14:51.962555 ===================================
728 12:14:51.965874 LPDDR4 DRAM CONFIGURATION
729 12:14:51.969196 ===================================
730 12:14:51.969281 EX_ROW_EN[0] = 0x0
731 12:14:51.972626 EX_ROW_EN[1] = 0x0
732 12:14:51.972744 LP4Y_EN = 0x0
733 12:14:51.976038 WORK_FSP = 0x0
734 12:14:51.976122 WL = 0x2
735 12:14:51.979275 RL = 0x2
736 12:14:51.979423 BL = 0x2
737 12:14:51.982725 RPST = 0x0
738 12:14:51.982809 RD_PRE = 0x0
739 12:14:51.986129 WR_PRE = 0x1
740 12:14:51.986213 WR_PST = 0x0
741 12:14:51.989479 DBI_WR = 0x0
742 12:14:51.989576 DBI_RD = 0x0
743 12:14:51.992760 OTF = 0x1
744 12:14:51.996047 ===================================
745 12:14:51.999203 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:14:52.002817 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:14:52.009730 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:14:52.013059 ===================================
749 12:14:52.013143 LPDDR4 DRAM CONFIGURATION
750 12:14:52.016432 ===================================
751 12:14:52.019935 EX_ROW_EN[0] = 0x10
752 12:14:52.023239 EX_ROW_EN[1] = 0x0
753 12:14:52.023372 LP4Y_EN = 0x0
754 12:14:52.026592 WORK_FSP = 0x0
755 12:14:52.026676 WL = 0x2
756 12:14:52.029933 RL = 0x2
757 12:14:52.030017 BL = 0x2
758 12:14:52.033362 RPST = 0x0
759 12:14:52.033445 RD_PRE = 0x0
760 12:14:52.036627 WR_PRE = 0x1
761 12:14:52.036711 WR_PST = 0x0
762 12:14:52.039525 DBI_WR = 0x0
763 12:14:52.039609 DBI_RD = 0x0
764 12:14:52.042893 OTF = 0x1
765 12:14:52.046344 ===================================
766 12:14:52.049756 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:14:52.055081 nWR fixed to 40
768 12:14:52.058202 [ModeRegInit_LP4] CH0 RK0
769 12:14:52.058316 [ModeRegInit_LP4] CH0 RK1
770 12:14:52.062253 [ModeRegInit_LP4] CH1 RK0
771 12:14:52.065297 [ModeRegInit_LP4] CH1 RK1
772 12:14:52.065388 match AC timing 13
773 12:14:52.071709 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:14:52.075571 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:14:52.078991 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:14:52.085147 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:14:52.088534 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:14:52.088613 [EMI DOE] emi_dcm 0
779 12:14:52.095262 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:14:52.095411 ==
781 12:14:52.098600 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:14:52.102368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:14:52.102490 ==
784 12:14:52.109083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:14:52.112234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:14:52.122589 [CA 0] Center 36 (6~67) winsize 62
787 12:14:52.125850 [CA 1] Center 36 (6~67) winsize 62
788 12:14:52.129278 [CA 2] Center 34 (4~65) winsize 62
789 12:14:52.132617 [CA 3] Center 34 (4~64) winsize 61
790 12:14:52.136025 [CA 4] Center 33 (3~64) winsize 62
791 12:14:52.139309 [CA 5] Center 32 (2~62) winsize 61
792 12:14:52.139423
793 12:14:52.142803 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 12:14:52.142901
795 12:14:52.146229 [CATrainingPosCal] consider 1 rank data
796 12:14:52.149622 u2DelayCellTimex100 = 270/100 ps
797 12:14:52.153150 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 12:14:52.155898 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 12:14:52.162799 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 12:14:52.165895 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
801 12:14:52.169231 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
802 12:14:52.172641 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 12:14:52.172725
804 12:14:52.176357 CA PerBit enable=1, Macro0, CA PI delay=32
805 12:14:52.176442
806 12:14:52.179408 [CBTSetCACLKResult] CA Dly = 32
807 12:14:52.179493 CS Dly: 5 (0~36)
808 12:14:52.179576 ==
809 12:14:52.182764 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:14:52.189406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:14:52.189518 ==
812 12:14:52.192723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:14:52.199580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:14:52.208911 [CA 0] Center 36 (6~67) winsize 62
815 12:14:52.212139 [CA 1] Center 36 (6~67) winsize 62
816 12:14:52.215355 [CA 2] Center 34 (4~65) winsize 62
817 12:14:52.219107 [CA 3] Center 33 (3~64) winsize 62
818 12:14:52.222358 [CA 4] Center 32 (2~63) winsize 62
819 12:14:52.225597 [CA 5] Center 32 (2~63) winsize 62
820 12:14:52.225682
821 12:14:52.228722 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 12:14:52.228807
823 12:14:52.232717 [CATrainingPosCal] consider 2 rank data
824 12:14:52.236101 u2DelayCellTimex100 = 270/100 ps
825 12:14:52.238918 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 12:14:52.242274 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 12:14:52.249230 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 12:14:52.252662 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 12:14:52.256086 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 12:14:52.258857 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 12:14:52.258942
832 12:14:52.262170 CA PerBit enable=1, Macro0, CA PI delay=32
833 12:14:52.262255
834 12:14:52.265625 [CBTSetCACLKResult] CA Dly = 32
835 12:14:52.265709 CS Dly: 5 (0~37)
836 12:14:52.265777
837 12:14:52.268845 ----->DramcWriteLeveling(PI) begin...
838 12:14:52.272773 ==
839 12:14:52.272859 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:14:52.280209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:14:52.280297 ==
842 12:14:52.280364 Write leveling (Byte 0): 32 => 32
843 12:14:52.283500 Write leveling (Byte 1): 31 => 31
844 12:14:52.286702 DramcWriteLeveling(PI) end<-----
845 12:14:52.286787
846 12:14:52.286857 ==
847 12:14:52.290481 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:14:52.297756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:14:52.297870 ==
850 12:14:52.297983 [Gating] SW mode calibration
851 12:14:52.304662 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:14:52.311254 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:14:52.314768 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:14:52.318090 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 12:14:52.325177 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
856 12:14:52.328358 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 12:14:52.331838 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:14:52.338291 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:14:52.341605 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:14:52.345041 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:14:52.351808 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:14:52.354453 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:14:52.358002 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:14:52.364770 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:14:52.368327 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:14:52.371676 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:14:52.375043 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:14:52.381703 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:14:52.385217 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:14:52.388495 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 12:14:52.395056 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 12:14:52.398202 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:14:52.401386 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:14:52.408230 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:14:52.411595 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:14:52.415143 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:14:52.421295 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:14:52.424757 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:14:52.428111 0 9 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
880 12:14:52.434740 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
881 12:14:52.438634 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:14:52.441815 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:14:52.448628 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:14:52.451962 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:14:52.455348 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:14:52.458220 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
887 12:14:52.464984 0 10 8 | B1->B0 | 3131 2626 | 1 0 | (1 0) (1 0)
888 12:14:52.468322 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
889 12:14:52.471771 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:14:52.478574 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:14:52.481883 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:14:52.485179 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:14:52.491651 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:14:52.495051 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 12:14:52.498466 0 11 8 | B1->B0 | 2a2a 4040 | 0 0 | (0 0) (0 0)
896 12:14:52.505344 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
897 12:14:52.508408 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:14:52.512079 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:14:52.518365 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:14:52.522243 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:14:52.524949 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:14:52.528325 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 12:14:52.535764 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 12:14:52.538532 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:14:52.541837 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:14:52.548988 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:14:52.552204 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:14:52.555645 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:14:52.562448 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:14:52.565320 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:14:52.568701 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:14:52.575502 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:14:52.578820 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:14:52.582261 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:14:52.589107 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:14:52.592455 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:14:52.595798 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:14:52.599236 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 12:14:52.605394 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 12:14:52.608842 Total UI for P1: 0, mck2ui 16
921 12:14:52.612223 best dqsien dly found for B0: ( 0, 14, 6)
922 12:14:52.615557 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 12:14:52.618935 Total UI for P1: 0, mck2ui 16
924 12:14:52.622626 best dqsien dly found for B1: ( 0, 14, 8)
925 12:14:52.626247 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 12:14:52.629355 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 12:14:52.629434
928 12:14:52.632577 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 12:14:52.635945 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 12:14:52.639250 [Gating] SW calibration Done
931 12:14:52.639384 ==
932 12:14:52.643073 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:14:52.646331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:14:52.646417 ==
935 12:14:52.649588 RX Vref Scan: 0
936 12:14:52.649671
937 12:14:52.652808 RX Vref 0 -> 0, step: 1
938 12:14:52.652892
939 12:14:52.652958 RX Delay -130 -> 252, step: 16
940 12:14:52.659314 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 12:14:52.662800 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 12:14:52.666065 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
943 12:14:52.669442 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
944 12:14:52.672870 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 12:14:52.679594 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 12:14:52.683067 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 12:14:52.686495 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 12:14:52.689906 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 12:14:52.693241 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 12:14:52.696670 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
951 12:14:52.703223 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 12:14:52.706635 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
953 12:14:52.710019 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
954 12:14:52.712834 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 12:14:52.719737 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
956 12:14:52.719820 ==
957 12:14:52.723128 Dram Type= 6, Freq= 0, CH_0, rank 0
958 12:14:52.726421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 12:14:52.726505 ==
960 12:14:52.726575 DQS Delay:
961 12:14:52.730168 DQS0 = 0, DQS1 = 0
962 12:14:52.730251 DQM Delay:
963 12:14:52.733329 DQM0 = 92, DQM1 = 84
964 12:14:52.733412 DQ Delay:
965 12:14:52.736497 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
966 12:14:52.739622 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
967 12:14:52.743459 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
968 12:14:52.746758 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
969 12:14:52.746841
970 12:14:52.746907
971 12:14:52.746968 ==
972 12:14:52.749977 Dram Type= 6, Freq= 0, CH_0, rank 0
973 12:14:52.753190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 12:14:52.753274 ==
975 12:14:52.753341
976 12:14:52.753403
977 12:14:52.756507 TX Vref Scan disable
978 12:14:52.759730 == TX Byte 0 ==
979 12:14:52.763572 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 12:14:52.766731 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 12:14:52.770061 == TX Byte 1 ==
982 12:14:52.773333 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
983 12:14:52.776660 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
984 12:14:52.776779 ==
985 12:14:52.780164 Dram Type= 6, Freq= 0, CH_0, rank 0
986 12:14:52.783624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 12:14:52.783711 ==
988 12:14:52.797876 TX Vref=22, minBit 5, minWin=27, winSum=446
989 12:14:52.801290 TX Vref=24, minBit 10, minWin=27, winSum=453
990 12:14:52.804582 TX Vref=26, minBit 0, minWin=28, winSum=453
991 12:14:52.807829 TX Vref=28, minBit 0, minWin=28, winSum=456
992 12:14:52.811159 TX Vref=30, minBit 8, minWin=28, winSum=460
993 12:14:52.814366 TX Vref=32, minBit 10, minWin=27, winSum=452
994 12:14:52.821343 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
995 12:14:52.821451
996 12:14:52.824792 Final TX Range 1 Vref 30
997 12:14:52.824899
998 12:14:52.824992 ==
999 12:14:52.828233 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 12:14:52.831647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 12:14:52.831727 ==
1002 12:14:52.831791
1003 12:14:52.834461
1004 12:14:52.834564 TX Vref Scan disable
1005 12:14:52.837813 == TX Byte 0 ==
1006 12:14:52.841118 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1007 12:14:52.844937 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1008 12:14:52.847993 == TX Byte 1 ==
1009 12:14:52.851121 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1010 12:14:52.855015 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1011 12:14:52.855124
1012 12:14:52.857794 [DATLAT]
1013 12:14:52.857898 Freq=800, CH0 RK0
1014 12:14:52.857990
1015 12:14:52.861116 DATLAT Default: 0xa
1016 12:14:52.861215 0, 0xFFFF, sum = 0
1017 12:14:52.864973 1, 0xFFFF, sum = 0
1018 12:14:52.865077 2, 0xFFFF, sum = 0
1019 12:14:52.868111 3, 0xFFFF, sum = 0
1020 12:14:52.868215 4, 0xFFFF, sum = 0
1021 12:14:52.871280 5, 0xFFFF, sum = 0
1022 12:14:52.871402 6, 0xFFFF, sum = 0
1023 12:14:52.874592 7, 0xFFFF, sum = 0
1024 12:14:52.877840 8, 0xFFFF, sum = 0
1025 12:14:52.877956 9, 0x0, sum = 1
1026 12:14:52.878055 10, 0x0, sum = 2
1027 12:14:52.881144 11, 0x0, sum = 3
1028 12:14:52.881248 12, 0x0, sum = 4
1029 12:14:52.884645 best_step = 10
1030 12:14:52.884751
1031 12:14:52.884856 ==
1032 12:14:52.888115 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 12:14:52.891583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 12:14:52.891657 ==
1035 12:14:52.894955 RX Vref Scan: 1
1036 12:14:52.895056
1037 12:14:52.895148 Set Vref Range= 32 -> 127
1038 12:14:52.895241
1039 12:14:52.897777 RX Vref 32 -> 127, step: 1
1040 12:14:52.897880
1041 12:14:52.901255 RX Delay -95 -> 252, step: 8
1042 12:14:52.901355
1043 12:14:52.904641 Set Vref, RX VrefLevel [Byte0]: 32
1044 12:14:52.908041 [Byte1]: 32
1045 12:14:52.908141
1046 12:14:52.911414 Set Vref, RX VrefLevel [Byte0]: 33
1047 12:14:52.914834 [Byte1]: 33
1048 12:14:52.917983
1049 12:14:52.918082 Set Vref, RX VrefLevel [Byte0]: 34
1050 12:14:52.921272 [Byte1]: 34
1051 12:14:52.926038
1052 12:14:52.926142 Set Vref, RX VrefLevel [Byte0]: 35
1053 12:14:52.928754 [Byte1]: 35
1054 12:14:52.933964
1055 12:14:52.934068 Set Vref, RX VrefLevel [Byte0]: 36
1056 12:14:52.937422 [Byte1]: 36
1057 12:14:52.941571
1058 12:14:52.941674 Set Vref, RX VrefLevel [Byte0]: 37
1059 12:14:52.944916 [Byte1]: 37
1060 12:14:52.949018
1061 12:14:52.949120 Set Vref, RX VrefLevel [Byte0]: 38
1062 12:14:52.952458 [Byte1]: 38
1063 12:14:52.956794
1064 12:14:52.956909 Set Vref, RX VrefLevel [Byte0]: 39
1065 12:14:52.959839 [Byte1]: 39
1066 12:14:52.964389
1067 12:14:52.964492 Set Vref, RX VrefLevel [Byte0]: 40
1068 12:14:52.967725 [Byte1]: 40
1069 12:14:52.971548
1070 12:14:52.971645 Set Vref, RX VrefLevel [Byte0]: 41
1071 12:14:52.974620 [Byte1]: 41
1072 12:14:52.979036
1073 12:14:52.979141 Set Vref, RX VrefLevel [Byte0]: 42
1074 12:14:52.982188 [Byte1]: 42
1075 12:14:52.986711
1076 12:14:52.986823 Set Vref, RX VrefLevel [Byte0]: 43
1077 12:14:52.990081 [Byte1]: 43
1078 12:14:52.994295
1079 12:14:52.994380 Set Vref, RX VrefLevel [Byte0]: 44
1080 12:14:52.997845 [Byte1]: 44
1081 12:14:53.001810
1082 12:14:53.001913 Set Vref, RX VrefLevel [Byte0]: 45
1083 12:14:53.005209 [Byte1]: 45
1084 12:14:53.009260
1085 12:14:53.009368 Set Vref, RX VrefLevel [Byte0]: 46
1086 12:14:53.012739 [Byte1]: 46
1087 12:14:53.016941
1088 12:14:53.017055 Set Vref, RX VrefLevel [Byte0]: 47
1089 12:14:53.020205 [Byte1]: 47
1090 12:14:53.024866
1091 12:14:53.024946 Set Vref, RX VrefLevel [Byte0]: 48
1092 12:14:53.028302 [Byte1]: 48
1093 12:14:53.032313
1094 12:14:53.032414 Set Vref, RX VrefLevel [Byte0]: 49
1095 12:14:53.035804 [Byte1]: 49
1096 12:14:53.039750
1097 12:14:53.039820 Set Vref, RX VrefLevel [Byte0]: 50
1098 12:14:53.043229 [Byte1]: 50
1099 12:14:53.047363
1100 12:14:53.047459 Set Vref, RX VrefLevel [Byte0]: 51
1101 12:14:53.050684 [Byte1]: 51
1102 12:14:53.054718
1103 12:14:53.054792 Set Vref, RX VrefLevel [Byte0]: 52
1104 12:14:53.058155 [Byte1]: 52
1105 12:14:53.062646
1106 12:14:53.062746 Set Vref, RX VrefLevel [Byte0]: 53
1107 12:14:53.065876 [Byte1]: 53
1108 12:14:53.070331
1109 12:14:53.070434 Set Vref, RX VrefLevel [Byte0]: 54
1110 12:14:53.073647 [Byte1]: 54
1111 12:14:53.077522
1112 12:14:53.077623 Set Vref, RX VrefLevel [Byte0]: 55
1113 12:14:53.080796 [Byte1]: 55
1114 12:14:53.085193
1115 12:14:53.085329 Set Vref, RX VrefLevel [Byte0]: 56
1116 12:14:53.089081 [Byte1]: 56
1117 12:14:53.093205
1118 12:14:53.093343 Set Vref, RX VrefLevel [Byte0]: 57
1119 12:14:53.096620 [Byte1]: 57
1120 12:14:53.100465
1121 12:14:53.100537 Set Vref, RX VrefLevel [Byte0]: 58
1122 12:14:53.103879 [Byte1]: 58
1123 12:14:53.107924
1124 12:14:53.107992 Set Vref, RX VrefLevel [Byte0]: 59
1125 12:14:53.111372 [Byte1]: 59
1126 12:14:53.116163
1127 12:14:53.116233 Set Vref, RX VrefLevel [Byte0]: 60
1128 12:14:53.118910 [Byte1]: 60
1129 12:14:53.123620
1130 12:14:53.123688 Set Vref, RX VrefLevel [Byte0]: 61
1131 12:14:53.126399 [Byte1]: 61
1132 12:14:53.130989
1133 12:14:53.131085 Set Vref, RX VrefLevel [Byte0]: 62
1134 12:14:53.134167 [Byte1]: 62
1135 12:14:53.138884
1136 12:14:53.138956 Set Vref, RX VrefLevel [Byte0]: 63
1137 12:14:53.141587 [Byte1]: 63
1138 12:14:53.146383
1139 12:14:53.146477 Set Vref, RX VrefLevel [Byte0]: 64
1140 12:14:53.149766 [Byte1]: 64
1141 12:14:53.153967
1142 12:14:53.154072 Set Vref, RX VrefLevel [Byte0]: 65
1143 12:14:53.157376 [Byte1]: 65
1144 12:14:53.161604
1145 12:14:53.161699 Set Vref, RX VrefLevel [Byte0]: 66
1146 12:14:53.164350 [Byte1]: 66
1147 12:14:53.169008
1148 12:14:53.169102 Set Vref, RX VrefLevel [Byte0]: 67
1149 12:14:53.172290 [Byte1]: 67
1150 12:14:53.176900
1151 12:14:53.176976 Set Vref, RX VrefLevel [Byte0]: 68
1152 12:14:53.179718 [Byte1]: 68
1153 12:14:53.183964
1154 12:14:53.184038 Set Vref, RX VrefLevel [Byte0]: 69
1155 12:14:53.187176 [Byte1]: 69
1156 12:14:53.191801
1157 12:14:53.191885 Set Vref, RX VrefLevel [Byte0]: 70
1158 12:14:53.195018 [Byte1]: 70
1159 12:14:53.199509
1160 12:14:53.199585 Set Vref, RX VrefLevel [Byte0]: 71
1161 12:14:53.202811 [Byte1]: 71
1162 12:14:53.207247
1163 12:14:53.207389 Set Vref, RX VrefLevel [Byte0]: 72
1164 12:14:53.210469 [Byte1]: 72
1165 12:14:53.214516
1166 12:14:53.214617 Set Vref, RX VrefLevel [Byte0]: 73
1167 12:14:53.217889 [Byte1]: 73
1168 12:14:53.222537
1169 12:14:53.222637 Set Vref, RX VrefLevel [Byte0]: 74
1170 12:14:53.225203 [Byte1]: 74
1171 12:14:53.229448
1172 12:14:53.229552 Set Vref, RX VrefLevel [Byte0]: 75
1173 12:14:53.232857 [Byte1]: 75
1174 12:14:53.237447
1175 12:14:53.237518 Set Vref, RX VrefLevel [Byte0]: 76
1176 12:14:53.240726 [Byte1]: 76
1177 12:14:53.244699
1178 12:14:53.244792 Set Vref, RX VrefLevel [Byte0]: 77
1179 12:14:53.248139 [Byte1]: 77
1180 12:14:53.252231
1181 12:14:53.252328 Set Vref, RX VrefLevel [Byte0]: 78
1182 12:14:53.255607 [Byte1]: 78
1183 12:14:53.260406
1184 12:14:53.260477 Final RX Vref Byte 0 = 59 to rank0
1185 12:14:53.263153 Final RX Vref Byte 1 = 56 to rank0
1186 12:14:53.266549 Final RX Vref Byte 0 = 59 to rank1
1187 12:14:53.269856 Final RX Vref Byte 1 = 56 to rank1==
1188 12:14:53.273258 Dram Type= 6, Freq= 0, CH_0, rank 0
1189 12:14:53.279881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 12:14:53.279960 ==
1191 12:14:53.280023 DQS Delay:
1192 12:14:53.280083 DQS0 = 0, DQS1 = 0
1193 12:14:53.283254 DQM Delay:
1194 12:14:53.283371 DQM0 = 92, DQM1 = 85
1195 12:14:53.286704 DQ Delay:
1196 12:14:53.289945 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1197 12:14:53.293884 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1198 12:14:53.297097 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
1199 12:14:53.300417 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1200 12:14:53.300498
1201 12:14:53.300562
1202 12:14:53.306587 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d44, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1203 12:14:53.309851 CH0 RK0: MR19=606, MR18=4D44
1204 12:14:53.316925 CH0_RK0: MR19=0x606, MR18=0x4D44, DQSOSC=390, MR23=63, INC=97, DEC=64
1205 12:14:53.317003
1206 12:14:53.320167 ----->DramcWriteLeveling(PI) begin...
1207 12:14:53.320243 ==
1208 12:14:53.323437 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 12:14:53.326842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 12:14:53.326926 ==
1211 12:14:53.330294 Write leveling (Byte 0): 32 => 32
1212 12:14:53.333606 Write leveling (Byte 1): 31 => 31
1213 12:14:53.337101 DramcWriteLeveling(PI) end<-----
1214 12:14:53.337171
1215 12:14:53.337232 ==
1216 12:14:53.340480 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 12:14:53.343852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 12:14:53.343949 ==
1219 12:14:53.387426 [Gating] SW mode calibration
1220 12:14:53.388142 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1221 12:14:53.388447 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1222 12:14:53.388536 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 12:14:53.388616 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 12:14:53.388701 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1225 12:14:53.388870 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:14:53.388966 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:14:53.389039 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:14:53.402080 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:14:53.402169 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:14:53.402435 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:14:53.405174 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:14:53.408354 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:14:53.411784 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:14:53.415096 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:14:53.421741 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:14:53.425571 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:14:53.428803 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:14:53.435608 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:14:53.439030 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1240 12:14:53.441770 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1241 12:14:53.448565 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:14:53.451944 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:14:53.455204 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:14:53.458443 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:14:53.465201 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:14:53.468484 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:14:53.471929 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:14:53.479055 0 9 8 | B1->B0 | 3030 2a2a | 0 0 | (0 0) (0 0)
1249 12:14:53.481779 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 12:14:53.485257 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 12:14:53.492268 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 12:14:53.495581 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 12:14:53.499082 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 12:14:53.505866 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 12:14:53.509001 0 10 4 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
1256 12:14:53.512138 0 10 8 | B1->B0 | 2828 2828 | 0 0 | (1 0) (0 0)
1257 12:14:53.515982 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 12:14:53.523791 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 12:14:53.527938 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 12:14:53.531496 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 12:14:53.534651 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 12:14:53.537936 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 12:14:53.545332 0 11 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1264 12:14:53.548823 0 11 8 | B1->B0 | 3f3f 4343 | 0 0 | (0 0) (0 0)
1265 12:14:53.552238 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 12:14:53.555760 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 12:14:53.562429 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 12:14:53.565621 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 12:14:53.569047 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 12:14:53.575939 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 12:14:53.578702 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 12:14:53.581995 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1273 12:14:53.588897 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1274 12:14:53.592171 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:14:53.595516 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:14:53.602156 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:14:53.605581 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:14:53.608911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:14:53.615676 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:14:53.618882 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:14:53.622068 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 12:14:53.628958 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 12:14:53.632243 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 12:14:53.635686 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 12:14:53.639099 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 12:14:53.645765 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 12:14:53.648932 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 12:14:53.652205 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1289 12:14:53.655549 Total UI for P1: 0, mck2ui 16
1290 12:14:53.658876 best dqsien dly found for B1: ( 0, 14, 6)
1291 12:14:53.665604 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1292 12:14:53.665688 Total UI for P1: 0, mck2ui 16
1293 12:14:53.672096 best dqsien dly found for B0: ( 0, 14, 8)
1294 12:14:53.675569 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1295 12:14:53.678971 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1296 12:14:53.679054
1297 12:14:53.682527 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1298 12:14:53.685815 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1299 12:14:53.689329 [Gating] SW calibration Done
1300 12:14:53.689407 ==
1301 12:14:53.692061 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 12:14:53.695418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 12:14:53.695493 ==
1304 12:14:53.699518 RX Vref Scan: 0
1305 12:14:53.699594
1306 12:14:53.699657 RX Vref 0 -> 0, step: 1
1307 12:14:53.699720
1308 12:14:53.702166 RX Delay -130 -> 252, step: 16
1309 12:14:53.705531 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1310 12:14:53.712229 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1311 12:14:53.715556 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1312 12:14:53.718899 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1313 12:14:53.722239 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1314 12:14:53.725722 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1315 12:14:53.729025 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1316 12:14:53.735520 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1317 12:14:53.739145 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1318 12:14:53.742314 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1319 12:14:53.745745 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1320 12:14:53.752308 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1321 12:14:53.755688 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1322 12:14:53.759500 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1323 12:14:53.762558 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1324 12:14:53.765830 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1325 12:14:53.765933 ==
1326 12:14:53.769286 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 12:14:53.776055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 12:14:53.776138 ==
1329 12:14:53.776203 DQS Delay:
1330 12:14:53.779248 DQS0 = 0, DQS1 = 0
1331 12:14:53.779392 DQM Delay:
1332 12:14:53.779487 DQM0 = 91, DQM1 = 81
1333 12:14:53.782683 DQ Delay:
1334 12:14:53.786112 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1335 12:14:53.789378 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1336 12:14:53.792766 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1337 12:14:53.796232 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1338 12:14:53.796310
1339 12:14:53.796375
1340 12:14:53.796432 ==
1341 12:14:53.799537 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 12:14:53.802768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 12:14:53.802870 ==
1344 12:14:53.802963
1345 12:14:53.803050
1346 12:14:53.806228 TX Vref Scan disable
1347 12:14:53.806329 == TX Byte 0 ==
1348 12:14:53.812831 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1349 12:14:53.816247 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1350 12:14:53.816321 == TX Byte 1 ==
1351 12:14:53.822988 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1352 12:14:53.826436 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1353 12:14:53.826508 ==
1354 12:14:53.829772 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 12:14:53.832516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 12:14:53.832599 ==
1357 12:14:53.847021 TX Vref=22, minBit 8, minWin=27, winSum=446
1358 12:14:53.850145 TX Vref=24, minBit 1, minWin=28, winSum=452
1359 12:14:53.853572 TX Vref=26, minBit 5, minWin=28, winSum=456
1360 12:14:53.857046 TX Vref=28, minBit 5, minWin=28, winSum=458
1361 12:14:53.860270 TX Vref=30, minBit 0, minWin=28, winSum=456
1362 12:14:53.863603 TX Vref=32, minBit 4, minWin=28, winSum=454
1363 12:14:53.870305 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 28
1364 12:14:53.870411
1365 12:14:53.873457 Final TX Range 1 Vref 28
1366 12:14:53.873533
1367 12:14:53.873598 ==
1368 12:14:53.876870 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 12:14:53.880149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 12:14:53.880224 ==
1371 12:14:53.880285
1372 12:14:53.880348
1373 12:14:53.883530 TX Vref Scan disable
1374 12:14:53.886745 == TX Byte 0 ==
1375 12:14:53.890299 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1376 12:14:53.893464 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1377 12:14:53.896936 == TX Byte 1 ==
1378 12:14:53.900298 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1379 12:14:53.903598 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1380 12:14:53.903696
1381 12:14:53.906902 [DATLAT]
1382 12:14:53.907005 Freq=800, CH0 RK1
1383 12:14:53.907092
1384 12:14:53.910895 DATLAT Default: 0xa
1385 12:14:53.910967 0, 0xFFFF, sum = 0
1386 12:14:53.913585 1, 0xFFFF, sum = 0
1387 12:14:53.913660 2, 0xFFFF, sum = 0
1388 12:14:53.916971 3, 0xFFFF, sum = 0
1389 12:14:53.917045 4, 0xFFFF, sum = 0
1390 12:14:53.920420 5, 0xFFFF, sum = 0
1391 12:14:53.920520 6, 0xFFFF, sum = 0
1392 12:14:53.923817 7, 0xFFFF, sum = 0
1393 12:14:53.923889 8, 0xFFFF, sum = 0
1394 12:14:53.927202 9, 0x0, sum = 1
1395 12:14:53.927299 10, 0x0, sum = 2
1396 12:14:53.930725 11, 0x0, sum = 3
1397 12:14:53.930827 12, 0x0, sum = 4
1398 12:14:53.934213 best_step = 10
1399 12:14:53.934311
1400 12:14:53.934401 ==
1401 12:14:53.937553 Dram Type= 6, Freq= 0, CH_0, rank 1
1402 12:14:53.940305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 12:14:53.940378 ==
1404 12:14:53.943689 RX Vref Scan: 0
1405 12:14:53.943762
1406 12:14:53.943822 RX Vref 0 -> 0, step: 1
1407 12:14:53.943883
1408 12:14:53.947589 RX Delay -95 -> 252, step: 8
1409 12:14:53.953775 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1410 12:14:53.957487 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1411 12:14:53.960731 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1412 12:14:53.964159 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1413 12:14:53.967198 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1414 12:14:53.970620 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1415 12:14:53.977224 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1416 12:14:53.980491 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1417 12:14:53.984015 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1418 12:14:53.987429 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1419 12:14:53.990652 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1420 12:14:53.997419 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1421 12:14:54.000674 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1422 12:14:54.004186 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1423 12:14:54.007611 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1424 12:14:54.010852 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1425 12:14:54.014150 ==
1426 12:14:54.017503 Dram Type= 6, Freq= 0, CH_0, rank 1
1427 12:14:54.020996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 12:14:54.021078 ==
1429 12:14:54.021166 DQS Delay:
1430 12:14:54.023707 DQS0 = 0, DQS1 = 0
1431 12:14:54.023788 DQM Delay:
1432 12:14:54.027093 DQM0 = 92, DQM1 = 83
1433 12:14:54.027212 DQ Delay:
1434 12:14:54.030569 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1435 12:14:54.033946 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1436 12:14:54.037265 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1437 12:14:54.040670 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =92
1438 12:14:54.040751
1439 12:14:54.040815
1440 12:14:54.047280 [DQSOSCAuto] RK1, (LSB)MR18= 0x4212, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1441 12:14:54.050739 CH0 RK1: MR19=606, MR18=4212
1442 12:14:54.057631 CH0_RK1: MR19=0x606, MR18=0x4212, DQSOSC=393, MR23=63, INC=95, DEC=63
1443 12:14:54.061003 [RxdqsGatingPostProcess] freq 800
1444 12:14:54.067311 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1445 12:14:54.067414 Pre-setting of DQS Precalculation
1446 12:14:54.073808 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1447 12:14:54.073898 ==
1448 12:14:54.077650 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 12:14:54.080998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 12:14:54.081081 ==
1451 12:14:54.087456 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1452 12:14:54.094229 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1453 12:14:54.102060 [CA 0] Center 36 (6~67) winsize 62
1454 12:14:54.105320 [CA 1] Center 36 (6~67) winsize 62
1455 12:14:54.108596 [CA 2] Center 35 (5~66) winsize 62
1456 12:14:54.112024 [CA 3] Center 34 (4~65) winsize 62
1457 12:14:54.115392 [CA 4] Center 34 (4~65) winsize 62
1458 12:14:54.118820 [CA 5] Center 34 (4~64) winsize 61
1459 12:14:54.118902
1460 12:14:54.122118 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1461 12:14:54.122200
1462 12:14:54.124920 [CATrainingPosCal] consider 1 rank data
1463 12:14:54.128216 u2DelayCellTimex100 = 270/100 ps
1464 12:14:54.131754 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 12:14:54.135179 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 12:14:54.142082 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1467 12:14:54.145557 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 12:14:54.148268 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1469 12:14:54.151743 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1470 12:14:54.151916
1471 12:14:54.155019 CA PerBit enable=1, Macro0, CA PI delay=34
1472 12:14:54.155103
1473 12:14:54.158541 [CBTSetCACLKResult] CA Dly = 34
1474 12:14:54.158623 CS Dly: 6 (0~37)
1475 12:14:54.158687 ==
1476 12:14:54.161987 Dram Type= 6, Freq= 0, CH_1, rank 1
1477 12:14:54.168808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 12:14:54.168897 ==
1479 12:14:54.172032 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1480 12:14:54.178478 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1481 12:14:54.188352 [CA 0] Center 36 (6~67) winsize 62
1482 12:14:54.191645 [CA 1] Center 37 (6~68) winsize 63
1483 12:14:54.194992 [CA 2] Center 35 (5~66) winsize 62
1484 12:14:54.199052 [CA 3] Center 34 (4~65) winsize 62
1485 12:14:54.202866 [CA 4] Center 35 (5~65) winsize 61
1486 12:14:54.206186 [CA 5] Center 34 (4~65) winsize 62
1487 12:14:54.206268
1488 12:14:54.210193 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1489 12:14:54.210275
1490 12:14:54.213621 [CATrainingPosCal] consider 2 rank data
1491 12:14:54.213719 u2DelayCellTimex100 = 270/100 ps
1492 12:14:54.220436 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 12:14:54.223779 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 12:14:54.226979 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1495 12:14:54.230418 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 12:14:54.233879 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1497 12:14:54.237375 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1498 12:14:54.237456
1499 12:14:54.240301 CA PerBit enable=1, Macro0, CA PI delay=34
1500 12:14:54.240383
1501 12:14:54.243666 [CBTSetCACLKResult] CA Dly = 34
1502 12:14:54.247070 CS Dly: 6 (0~38)
1503 12:14:54.247151
1504 12:14:54.250375 ----->DramcWriteLeveling(PI) begin...
1505 12:14:54.250488 ==
1506 12:14:54.253822 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 12:14:54.257268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 12:14:54.257343 ==
1509 12:14:54.260626 Write leveling (Byte 0): 26 => 26
1510 12:14:54.263950 Write leveling (Byte 1): 27 => 27
1511 12:14:54.267304 DramcWriteLeveling(PI) end<-----
1512 12:14:54.267410
1513 12:14:54.267513 ==
1514 12:14:54.270691 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 12:14:54.274098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 12:14:54.274184 ==
1517 12:14:54.277510 [Gating] SW mode calibration
1518 12:14:54.283912 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1519 12:14:54.290983 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1520 12:14:54.293757 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1521 12:14:54.297018 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1522 12:14:54.303830 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:14:54.307206 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:14:54.310453 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:14:54.317686 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:14:54.320900 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:14:54.324238 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:14:54.327467 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:14:54.334120 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:14:54.337617 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:14:54.341010 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:14:54.347602 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:14:54.350999 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:14:54.353845 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:14:54.360661 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:14:54.363896 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1537 12:14:54.367224 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:14:54.374116 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:14:54.377523 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:14:54.380857 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:14:54.387629 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:14:54.390968 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:14:54.394602 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:14:54.397868 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:14:54.404647 0 9 4 | B1->B0 | 2323 2626 | 1 1 | (1 1) (1 1)
1546 12:14:54.407880 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1547 12:14:54.411271 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 12:14:54.417846 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 12:14:54.421170 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 12:14:54.424369 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 12:14:54.430887 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 12:14:54.434153 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 12:14:54.437436 0 10 4 | B1->B0 | 3232 2b2b | 1 0 | (1 0) (0 0)
1554 12:14:54.444222 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1555 12:14:54.447712 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 12:14:54.451077 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 12:14:54.457787 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 12:14:54.461222 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 12:14:54.464586 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 12:14:54.471216 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 12:14:54.473940 0 11 4 | B1->B0 | 2828 3838 | 0 1 | (1 1) (0 0)
1562 12:14:54.477412 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1563 12:14:54.484193 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 12:14:54.487535 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 12:14:54.490949 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 12:14:54.498017 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 12:14:54.501120 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 12:14:54.504226 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 12:14:54.507574 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1570 12:14:54.514130 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:14:54.517598 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:14:54.520892 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:14:54.527568 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:14:54.531319 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:14:54.534716 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:14:54.541143 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:14:54.544239 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 12:14:54.547563 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 12:14:54.554235 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 12:14:54.557595 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 12:14:54.561089 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 12:14:54.564414 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 12:14:54.571275 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 12:14:54.574509 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 12:14:54.577987 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1586 12:14:54.581395 Total UI for P1: 0, mck2ui 16
1587 12:14:54.584881 best dqsien dly found for B1: ( 0, 14, 2)
1588 12:14:54.591490 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1589 12:14:54.591569 Total UI for P1: 0, mck2ui 16
1590 12:14:54.598296 best dqsien dly found for B0: ( 0, 14, 4)
1591 12:14:54.601777 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1592 12:14:54.604533 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1593 12:14:54.604617
1594 12:14:54.607901 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1595 12:14:54.611806 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1596 12:14:54.614957 [Gating] SW calibration Done
1597 12:14:54.615049 ==
1598 12:14:54.618125 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 12:14:54.621424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 12:14:54.621502 ==
1601 12:14:54.624893 RX Vref Scan: 0
1602 12:14:54.624992
1603 12:14:54.625057 RX Vref 0 -> 0, step: 1
1604 12:14:54.625144
1605 12:14:54.628336 RX Delay -130 -> 252, step: 16
1606 12:14:54.631815 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1607 12:14:54.638186 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1608 12:14:54.641370 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1609 12:14:54.645238 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1610 12:14:54.648361 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1611 12:14:54.651608 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1612 12:14:54.654872 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1613 12:14:54.661588 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1614 12:14:54.665006 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1615 12:14:54.668538 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1616 12:14:54.671905 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1617 12:14:54.674721 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1618 12:14:54.681315 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1619 12:14:54.684819 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1620 12:14:54.688216 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1621 12:14:54.691596 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1622 12:14:54.691673 ==
1623 12:14:54.694953 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 12:14:54.701692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 12:14:54.701770 ==
1626 12:14:54.701834 DQS Delay:
1627 12:14:54.705084 DQS0 = 0, DQS1 = 0
1628 12:14:54.705164 DQM Delay:
1629 12:14:54.705231 DQM0 = 92, DQM1 = 87
1630 12:14:54.708603 DQ Delay:
1631 12:14:54.711888 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1632 12:14:54.715254 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1633 12:14:54.718477 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1634 12:14:54.721723 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1635 12:14:54.721807
1636 12:14:54.721872
1637 12:14:54.721933 ==
1638 12:14:54.725028 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 12:14:54.728320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 12:14:54.728407 ==
1641 12:14:54.728473
1642 12:14:54.728533
1643 12:14:54.731494 TX Vref Scan disable
1644 12:14:54.731579 == TX Byte 0 ==
1645 12:14:54.738217 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1646 12:14:54.742066 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1647 12:14:54.742142 == TX Byte 1 ==
1648 12:14:54.748697 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1649 12:14:54.751924 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1650 12:14:54.752010 ==
1651 12:14:54.755205 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 12:14:54.758380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 12:14:54.758455 ==
1654 12:14:54.772336 TX Vref=22, minBit 1, minWin=26, winSum=434
1655 12:14:54.775741 TX Vref=24, minBit 0, minWin=27, winSum=443
1656 12:14:54.779073 TX Vref=26, minBit 0, minWin=27, winSum=442
1657 12:14:54.782385 TX Vref=28, minBit 2, minWin=27, winSum=446
1658 12:14:54.785809 TX Vref=30, minBit 1, minWin=27, winSum=449
1659 12:14:54.788623 TX Vref=32, minBit 1, minWin=27, winSum=448
1660 12:14:54.795323 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 30
1661 12:14:54.795427
1662 12:14:54.798935 Final TX Range 1 Vref 30
1663 12:14:54.799018
1664 12:14:54.799082 ==
1665 12:14:54.802336 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 12:14:54.805755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 12:14:54.805838 ==
1668 12:14:54.805903
1669 12:14:54.805962
1670 12:14:54.809165 TX Vref Scan disable
1671 12:14:54.812668 == TX Byte 0 ==
1672 12:14:54.815905 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1673 12:14:54.819323 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1674 12:14:54.822637 == TX Byte 1 ==
1675 12:14:54.825849 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1676 12:14:54.829116 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1677 12:14:54.829229
1678 12:14:54.832568 [DATLAT]
1679 12:14:54.832672 Freq=800, CH1 RK0
1680 12:14:54.832775
1681 12:14:54.835887 DATLAT Default: 0xa
1682 12:14:54.835970 0, 0xFFFF, sum = 0
1683 12:14:54.839074 1, 0xFFFF, sum = 0
1684 12:14:54.839187 2, 0xFFFF, sum = 0
1685 12:14:54.842348 3, 0xFFFF, sum = 0
1686 12:14:54.842461 4, 0xFFFF, sum = 0
1687 12:14:54.845806 5, 0xFFFF, sum = 0
1688 12:14:54.845922 6, 0xFFFF, sum = 0
1689 12:14:54.849092 7, 0xFFFF, sum = 0
1690 12:14:54.849199 8, 0x0, sum = 1
1691 12:14:54.852466 9, 0x0, sum = 2
1692 12:14:54.852543 10, 0x0, sum = 3
1693 12:14:54.855837 11, 0x0, sum = 4
1694 12:14:54.855940 best_step = 9
1695 12:14:54.856020
1696 12:14:54.856080 ==
1697 12:14:54.859096 Dram Type= 6, Freq= 0, CH_1, rank 0
1698 12:14:54.862388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1699 12:14:54.862486 ==
1700 12:14:54.866114 RX Vref Scan: 1
1701 12:14:54.866213
1702 12:14:54.869527 Set Vref Range= 32 -> 127
1703 12:14:54.869624
1704 12:14:54.869720 RX Vref 32 -> 127, step: 1
1705 12:14:54.869808
1706 12:14:54.872948 RX Delay -79 -> 252, step: 8
1707 12:14:54.873048
1708 12:14:54.875663 Set Vref, RX VrefLevel [Byte0]: 32
1709 12:14:54.879071 [Byte1]: 32
1710 12:14:54.882551
1711 12:14:54.882653 Set Vref, RX VrefLevel [Byte0]: 33
1712 12:14:54.885949 [Byte1]: 33
1713 12:14:54.890541
1714 12:14:54.890623 Set Vref, RX VrefLevel [Byte0]: 34
1715 12:14:54.893828 [Byte1]: 34
1716 12:14:54.897927
1717 12:14:54.898040 Set Vref, RX VrefLevel [Byte0]: 35
1718 12:14:54.901399 [Byte1]: 35
1719 12:14:54.905546
1720 12:14:54.905643 Set Vref, RX VrefLevel [Byte0]: 36
1721 12:14:54.909052 [Byte1]: 36
1722 12:14:54.913136
1723 12:14:54.913218 Set Vref, RX VrefLevel [Byte0]: 37
1724 12:14:54.916431 [Byte1]: 37
1725 12:14:54.920539
1726 12:14:54.920621 Set Vref, RX VrefLevel [Byte0]: 38
1727 12:14:54.923880 [Byte1]: 38
1728 12:14:54.928030
1729 12:14:54.928112 Set Vref, RX VrefLevel [Byte0]: 39
1730 12:14:54.931314 [Byte1]: 39
1731 12:14:54.935918
1732 12:14:54.936020 Set Vref, RX VrefLevel [Byte0]: 40
1733 12:14:54.939128 [Byte1]: 40
1734 12:14:54.943115
1735 12:14:54.943218 Set Vref, RX VrefLevel [Byte0]: 41
1736 12:14:54.946449 [Byte1]: 41
1737 12:14:54.951088
1738 12:14:54.951162 Set Vref, RX VrefLevel [Byte0]: 42
1739 12:14:54.954249 [Byte1]: 42
1740 12:14:54.958034
1741 12:14:54.958144 Set Vref, RX VrefLevel [Byte0]: 43
1742 12:14:54.961871 [Byte1]: 43
1743 12:14:54.965768
1744 12:14:54.965876 Set Vref, RX VrefLevel [Byte0]: 44
1745 12:14:54.969011 [Byte1]: 44
1746 12:14:54.973603
1747 12:14:54.973731 Set Vref, RX VrefLevel [Byte0]: 45
1748 12:14:54.976759 [Byte1]: 45
1749 12:14:54.980871
1750 12:14:54.980980 Set Vref, RX VrefLevel [Byte0]: 46
1751 12:14:54.984266 [Byte1]: 46
1752 12:14:54.988272
1753 12:14:54.988347 Set Vref, RX VrefLevel [Byte0]: 47
1754 12:14:54.991564 [Byte1]: 47
1755 12:14:54.996096
1756 12:14:54.996198 Set Vref, RX VrefLevel [Byte0]: 48
1757 12:14:54.999431 [Byte1]: 48
1758 12:14:55.003583
1759 12:14:55.003681 Set Vref, RX VrefLevel [Byte0]: 49
1760 12:14:55.007068 [Byte1]: 49
1761 12:14:55.011115
1762 12:14:55.011186 Set Vref, RX VrefLevel [Byte0]: 50
1763 12:14:55.014563 [Byte1]: 50
1764 12:14:55.018514
1765 12:14:55.018598 Set Vref, RX VrefLevel [Byte0]: 51
1766 12:14:55.021846 [Byte1]: 51
1767 12:14:55.025817
1768 12:14:55.025924 Set Vref, RX VrefLevel [Byte0]: 52
1769 12:14:55.029174 [Byte1]: 52
1770 12:14:55.033795
1771 12:14:55.033903 Set Vref, RX VrefLevel [Byte0]: 53
1772 12:14:55.037309 [Byte1]: 53
1773 12:14:55.041406
1774 12:14:55.041505 Set Vref, RX VrefLevel [Byte0]: 54
1775 12:14:55.044746 [Byte1]: 54
1776 12:14:55.048679
1777 12:14:55.048752 Set Vref, RX VrefLevel [Byte0]: 55
1778 12:14:55.051981 [Byte1]: 55
1779 12:14:55.056093
1780 12:14:55.056167 Set Vref, RX VrefLevel [Byte0]: 56
1781 12:14:55.060092 [Byte1]: 56
1782 12:14:55.064090
1783 12:14:55.064162 Set Vref, RX VrefLevel [Byte0]: 57
1784 12:14:55.067145 [Byte1]: 57
1785 12:14:55.071615
1786 12:14:55.071697 Set Vref, RX VrefLevel [Byte0]: 58
1787 12:14:55.074833 [Byte1]: 58
1788 12:14:55.079160
1789 12:14:55.079241 Set Vref, RX VrefLevel [Byte0]: 59
1790 12:14:55.082526 [Byte1]: 59
1791 12:14:55.086384
1792 12:14:55.086466 Set Vref, RX VrefLevel [Byte0]: 60
1793 12:14:55.089891 [Byte1]: 60
1794 12:14:55.093939
1795 12:14:55.094021 Set Vref, RX VrefLevel [Byte0]: 61
1796 12:14:55.097195 [Byte1]: 61
1797 12:14:55.101849
1798 12:14:55.101932 Set Vref, RX VrefLevel [Byte0]: 62
1799 12:14:55.105217 [Byte1]: 62
1800 12:14:55.109318
1801 12:14:55.109401 Set Vref, RX VrefLevel [Byte0]: 63
1802 12:14:55.112589 [Byte1]: 63
1803 12:14:55.116642
1804 12:14:55.116718 Set Vref, RX VrefLevel [Byte0]: 64
1805 12:14:55.119989 [Byte1]: 64
1806 12:14:55.124389
1807 12:14:55.124471 Set Vref, RX VrefLevel [Byte0]: 65
1808 12:14:55.127652 [Byte1]: 65
1809 12:14:55.131711
1810 12:14:55.131829 Set Vref, RX VrefLevel [Byte0]: 66
1811 12:14:55.135094 [Byte1]: 66
1812 12:14:55.139138
1813 12:14:55.139220 Set Vref, RX VrefLevel [Byte0]: 67
1814 12:14:55.142609 [Byte1]: 67
1815 12:14:55.146736
1816 12:14:55.146820 Set Vref, RX VrefLevel [Byte0]: 68
1817 12:14:55.149956 [Byte1]: 68
1818 12:14:55.154573
1819 12:14:55.154661 Set Vref, RX VrefLevel [Byte0]: 69
1820 12:14:55.157962 [Byte1]: 69
1821 12:14:55.161844
1822 12:14:55.161935 Set Vref, RX VrefLevel [Byte0]: 70
1823 12:14:55.165202 [Byte1]: 70
1824 12:14:55.169289
1825 12:14:55.169386 Set Vref, RX VrefLevel [Byte0]: 71
1826 12:14:55.173153 [Byte1]: 71
1827 12:14:55.176890
1828 12:14:55.176988 Set Vref, RX VrefLevel [Byte0]: 72
1829 12:14:55.180147 [Byte1]: 72
1830 12:14:55.184695
1831 12:14:55.184790 Final RX Vref Byte 0 = 56 to rank0
1832 12:14:55.187892 Final RX Vref Byte 1 = 55 to rank0
1833 12:14:55.191094 Final RX Vref Byte 0 = 56 to rank1
1834 12:14:55.194943 Final RX Vref Byte 1 = 55 to rank1==
1835 12:14:55.198277 Dram Type= 6, Freq= 0, CH_1, rank 0
1836 12:14:55.204896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1837 12:14:55.205006 ==
1838 12:14:55.205108 DQS Delay:
1839 12:14:55.205211 DQS0 = 0, DQS1 = 0
1840 12:14:55.208248 DQM Delay:
1841 12:14:55.208327 DQM0 = 95, DQM1 = 89
1842 12:14:55.211676 DQ Delay:
1843 12:14:55.214557 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1844 12:14:55.217899 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1845 12:14:55.217985 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1846 12:14:55.224766 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1847 12:14:55.224850
1848 12:14:55.224965
1849 12:14:55.231585 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1850 12:14:55.234860 CH1 RK0: MR19=606, MR18=2E4A
1851 12:14:55.241673 CH1_RK0: MR19=0x606, MR18=0x2E4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1852 12:14:55.241784
1853 12:14:55.245063 ----->DramcWriteLeveling(PI) begin...
1854 12:14:55.245169 ==
1855 12:14:55.248522 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 12:14:55.251908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 12:14:55.251994 ==
1858 12:14:55.254738 Write leveling (Byte 0): 26 => 26
1859 12:14:55.258621 Write leveling (Byte 1): 31 => 31
1860 12:14:55.261942 DramcWriteLeveling(PI) end<-----
1861 12:14:55.262027
1862 12:14:55.262112 ==
1863 12:14:55.265237 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 12:14:55.268411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 12:14:55.268499 ==
1866 12:14:55.271554 [Gating] SW mode calibration
1867 12:14:55.278271 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1868 12:14:55.284840 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1869 12:14:55.288718 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1870 12:14:55.292046 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1871 12:14:55.298546 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:14:55.301807 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:14:55.304949 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:14:55.308344 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:14:55.315065 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:14:55.318395 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:14:55.321887 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:14:55.328869 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:14:55.332143 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:14:55.335600 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:14:55.342317 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:14:55.344891 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:14:55.348264 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:14:55.355162 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1885 12:14:55.358541 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1886 12:14:55.361925 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:14:55.368349 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:14:55.371689 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:14:55.374992 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:14:55.381636 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:14:55.385117 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:14:55.388525 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:14:55.395022 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:14:55.398303 0 9 4 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
1895 12:14:55.401798 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1896 12:14:55.405065 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 12:14:55.411618 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 12:14:55.414886 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 12:14:55.418751 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 12:14:55.425017 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 12:14:55.428525 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 12:14:55.431820 0 10 4 | B1->B0 | 2b2b 2f2f | 0 0 | (1 0) (0 0)
1903 12:14:55.438620 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 12:14:55.441825 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 12:14:55.445362 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 12:14:55.451902 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 12:14:55.455361 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 12:14:55.458755 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 12:14:55.465579 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1910 12:14:55.468364 0 11 4 | B1->B0 | 3838 2c2c | 1 0 | (0 0) (0 0)
1911 12:14:55.472230 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 12:14:55.478934 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 12:14:55.482076 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 12:14:55.485240 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 12:14:55.492134 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 12:14:55.494961 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 12:14:55.498359 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 12:14:55.501659 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1919 12:14:55.508696 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 12:14:55.511764 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 12:14:55.515172 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 12:14:55.522107 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 12:14:55.525414 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 12:14:55.528794 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 12:14:55.535594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 12:14:55.539009 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 12:14:55.541654 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 12:14:55.548891 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 12:14:55.552125 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 12:14:55.555582 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 12:14:55.561819 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 12:14:55.565039 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:14:55.568510 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1934 12:14:55.575382 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1935 12:14:55.578751 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 12:14:55.581898 Total UI for P1: 0, mck2ui 16
1937 12:14:55.585266 best dqsien dly found for B0: ( 0, 14, 4)
1938 12:14:55.588680 Total UI for P1: 0, mck2ui 16
1939 12:14:55.591932 best dqsien dly found for B1: ( 0, 14, 2)
1940 12:14:55.595159 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1941 12:14:55.599311 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1942 12:14:55.599404
1943 12:14:55.602047 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1944 12:14:55.605470 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1945 12:14:55.608665 [Gating] SW calibration Done
1946 12:14:55.608749 ==
1947 12:14:55.611943 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 12:14:55.615717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 12:14:55.615802 ==
1950 12:14:55.618947 RX Vref Scan: 0
1951 12:14:55.619020
1952 12:14:55.619082 RX Vref 0 -> 0, step: 1
1953 12:14:55.619142
1954 12:14:55.622124 RX Delay -130 -> 252, step: 16
1955 12:14:55.625307 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1956 12:14:55.632416 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1957 12:14:55.635967 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1958 12:14:55.638644 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1959 12:14:55.642134 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1960 12:14:55.645427 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1961 12:14:55.652135 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1962 12:14:55.655512 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1963 12:14:55.658811 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1964 12:14:55.662224 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1965 12:14:55.665634 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1966 12:14:55.672275 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1967 12:14:55.675738 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1968 12:14:55.679174 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1969 12:14:55.682618 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1970 12:14:55.685913 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1971 12:14:55.685997 ==
1972 12:14:55.688996 Dram Type= 6, Freq= 0, CH_1, rank 1
1973 12:14:55.695723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1974 12:14:55.695808 ==
1975 12:14:55.695874 DQS Delay:
1976 12:14:55.699042 DQS0 = 0, DQS1 = 0
1977 12:14:55.699125 DQM Delay:
1978 12:14:55.699221 DQM0 = 92, DQM1 = 90
1979 12:14:55.702240 DQ Delay:
1980 12:14:55.706113 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
1981 12:14:55.708891 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1982 12:14:55.712216 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1983 12:14:55.715541 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1984 12:14:55.715623
1985 12:14:55.715689
1986 12:14:55.715749 ==
1987 12:14:55.719199 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 12:14:55.722525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 12:14:55.722603 ==
1990 12:14:55.722670
1991 12:14:55.722732
1992 12:14:55.725846 TX Vref Scan disable
1993 12:14:55.729125 == TX Byte 0 ==
1994 12:14:55.732397 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1995 12:14:55.735981 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1996 12:14:55.738798 == TX Byte 1 ==
1997 12:14:55.742187 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1998 12:14:55.745583 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1999 12:14:55.745668 ==
2000 12:14:55.748883 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 12:14:55.752289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 12:14:55.752375 ==
2003 12:14:55.767016 TX Vref=22, minBit 1, minWin=26, winSum=442
2004 12:14:55.770524 TX Vref=24, minBit 1, minWin=26, winSum=444
2005 12:14:55.773931 TX Vref=26, minBit 0, minWin=27, winSum=446
2006 12:14:55.777372 TX Vref=28, minBit 2, minWin=27, winSum=449
2007 12:14:55.780807 TX Vref=30, minBit 2, minWin=27, winSum=449
2008 12:14:55.784168 TX Vref=32, minBit 1, minWin=27, winSum=447
2009 12:14:55.790365 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 28
2010 12:14:55.790448
2011 12:14:55.793693 Final TX Range 1 Vref 28
2012 12:14:55.793775
2013 12:14:55.793840 ==
2014 12:14:55.797530 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 12:14:55.800822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 12:14:55.800906 ==
2017 12:14:55.800971
2018 12:14:55.801031
2019 12:14:55.804211 TX Vref Scan disable
2020 12:14:55.806864 == TX Byte 0 ==
2021 12:14:55.810812 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2022 12:14:55.814111 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2023 12:14:55.816804 == TX Byte 1 ==
2024 12:14:55.820853 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2025 12:14:55.823525 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2026 12:14:55.826797
2027 12:14:55.826871 [DATLAT]
2028 12:14:55.826937 Freq=800, CH1 RK1
2029 12:14:55.826998
2030 12:14:55.830604 DATLAT Default: 0x9
2031 12:14:55.830677 0, 0xFFFF, sum = 0
2032 12:14:55.833811 1, 0xFFFF, sum = 0
2033 12:14:55.833884 2, 0xFFFF, sum = 0
2034 12:14:55.837065 3, 0xFFFF, sum = 0
2035 12:14:55.837140 4, 0xFFFF, sum = 0
2036 12:14:55.840210 5, 0xFFFF, sum = 0
2037 12:14:55.840296 6, 0xFFFF, sum = 0
2038 12:14:55.844060 7, 0xFFFF, sum = 0
2039 12:14:55.847514 8, 0xFFFF, sum = 0
2040 12:14:55.847599 9, 0x0, sum = 1
2041 12:14:55.847666 10, 0x0, sum = 2
2042 12:14:55.850984 11, 0x0, sum = 3
2043 12:14:55.851097 12, 0x0, sum = 4
2044 12:14:55.853799 best_step = 10
2045 12:14:55.853882
2046 12:14:55.853948 ==
2047 12:14:55.857171 Dram Type= 6, Freq= 0, CH_1, rank 1
2048 12:14:55.860538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2049 12:14:55.860627 ==
2050 12:14:55.863893 RX Vref Scan: 0
2051 12:14:55.863976
2052 12:14:55.864041 RX Vref 0 -> 0, step: 1
2053 12:14:55.864103
2054 12:14:55.867439 RX Delay -63 -> 252, step: 8
2055 12:14:55.874164 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2056 12:14:55.877548 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2057 12:14:55.880375 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2058 12:14:55.883920 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2059 12:14:55.887214 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2060 12:14:55.890607 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2061 12:14:55.897108 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2062 12:14:55.900614 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2063 12:14:55.903888 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2064 12:14:55.907198 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2065 12:14:55.910345 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2066 12:14:55.917021 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2067 12:14:55.920298 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2068 12:14:55.923667 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2069 12:14:55.927122 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2070 12:14:55.930486 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2071 12:14:55.933926 ==
2072 12:14:55.934008 Dram Type= 6, Freq= 0, CH_1, rank 1
2073 12:14:55.940321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2074 12:14:55.940406 ==
2075 12:14:55.940472 DQS Delay:
2076 12:14:55.943616 DQS0 = 0, DQS1 = 0
2077 12:14:55.943699 DQM Delay:
2078 12:14:55.946939 DQM0 = 97, DQM1 = 90
2079 12:14:55.947051 DQ Delay:
2080 12:14:55.950157 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2081 12:14:55.953632 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2082 12:14:55.957018 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2083 12:14:55.960338 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2084 12:14:55.960428
2085 12:14:55.960494
2086 12:14:55.967080 [DQSOSCAuto] RK1, (LSB)MR18= 0x440d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2087 12:14:55.970445 CH1 RK1: MR19=606, MR18=440D
2088 12:14:55.977384 CH1_RK1: MR19=0x606, MR18=0x440D, DQSOSC=392, MR23=63, INC=96, DEC=64
2089 12:14:55.980105 [RxdqsGatingPostProcess] freq 800
2090 12:14:55.983561 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2091 12:14:55.987014 Pre-setting of DQS Precalculation
2092 12:14:55.993774 [DualRankRxdatlatCal] RK0: 9, RK1: 10, Final_Datlat 10
2093 12:14:56.000445 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2094 12:14:56.007253 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2095 12:14:56.007406
2096 12:14:56.007507
2097 12:14:56.010709 [Calibration Summary] 1600 Mbps
2098 12:14:56.010810 CH 0, Rank 0
2099 12:14:56.013951 SW Impedance : PASS
2100 12:14:56.017183 DUTY Scan : NO K
2101 12:14:56.017314 ZQ Calibration : PASS
2102 12:14:56.020546 Jitter Meter : NO K
2103 12:14:56.023864 CBT Training : PASS
2104 12:14:56.023947 Write leveling : PASS
2105 12:14:56.027101 RX DQS gating : PASS
2106 12:14:56.030366 RX DQ/DQS(RDDQC) : PASS
2107 12:14:56.030475 TX DQ/DQS : PASS
2108 12:14:56.033811 RX DATLAT : PASS
2109 12:14:56.037253 RX DQ/DQS(Engine): PASS
2110 12:14:56.037361 TX OE : NO K
2111 12:14:56.037456 All Pass.
2112 12:14:56.040576
2113 12:14:56.040686 CH 0, Rank 1
2114 12:14:56.043848 SW Impedance : PASS
2115 12:14:56.043956 DUTY Scan : NO K
2116 12:14:56.047091 ZQ Calibration : PASS
2117 12:14:56.047200 Jitter Meter : NO K
2118 12:14:56.050731 CBT Training : PASS
2119 12:14:56.053931 Write leveling : PASS
2120 12:14:56.054014 RX DQS gating : PASS
2121 12:14:56.057707 RX DQ/DQS(RDDQC) : PASS
2122 12:14:56.060846 TX DQ/DQS : PASS
2123 12:14:56.060930 RX DATLAT : PASS
2124 12:14:56.064143 RX DQ/DQS(Engine): PASS
2125 12:14:56.067617 TX OE : NO K
2126 12:14:56.067700 All Pass.
2127 12:14:56.067767
2128 12:14:56.067828 CH 1, Rank 0
2129 12:14:56.071013 SW Impedance : PASS
2130 12:14:56.074341 DUTY Scan : NO K
2131 12:14:56.074450 ZQ Calibration : PASS
2132 12:14:56.077144 Jitter Meter : NO K
2133 12:14:56.080481 CBT Training : PASS
2134 12:14:56.080590 Write leveling : PASS
2135 12:14:56.083905 RX DQS gating : PASS
2136 12:14:56.083998 RX DQ/DQS(RDDQC) : PASS
2137 12:14:56.087239 TX DQ/DQS : PASS
2138 12:14:56.090746 RX DATLAT : PASS
2139 12:14:56.090857 RX DQ/DQS(Engine): PASS
2140 12:14:56.094191 TX OE : NO K
2141 12:14:56.094298 All Pass.
2142 12:14:56.094389
2143 12:14:56.097619 CH 1, Rank 1
2144 12:14:56.097703 SW Impedance : PASS
2145 12:14:56.100883 DUTY Scan : NO K
2146 12:14:56.104227 ZQ Calibration : PASS
2147 12:14:56.104314 Jitter Meter : NO K
2148 12:14:56.107646 CBT Training : PASS
2149 12:14:56.110988 Write leveling : PASS
2150 12:14:56.111128 RX DQS gating : PASS
2151 12:14:56.113697 RX DQ/DQS(RDDQC) : PASS
2152 12:14:56.117192 TX DQ/DQS : PASS
2153 12:14:56.117275 RX DATLAT : PASS
2154 12:14:56.120384 RX DQ/DQS(Engine): PASS
2155 12:14:56.124220 TX OE : NO K
2156 12:14:56.124303 All Pass.
2157 12:14:56.124380
2158 12:14:56.124459 DramC Write-DBI off
2159 12:14:56.127514 PER_BANK_REFRESH: Hybrid Mode
2160 12:14:56.130760 TX_TRACKING: ON
2161 12:14:56.134102 [GetDramInforAfterCalByMRR] Vendor 6.
2162 12:14:56.137352 [GetDramInforAfterCalByMRR] Revision 606.
2163 12:14:56.140718 [GetDramInforAfterCalByMRR] Revision 2 0.
2164 12:14:56.140801 MR0 0x3b3b
2165 12:14:56.144091 MR8 0x5151
2166 12:14:56.147573 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2167 12:14:56.147656
2168 12:14:56.147721 MR0 0x3b3b
2169 12:14:56.147782 MR8 0x5151
2170 12:14:56.150936 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2171 12:14:56.151026
2172 12:14:56.160669 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2173 12:14:56.163838 [FAST_K] Save calibration result to emmc
2174 12:14:56.167585 [FAST_K] Save calibration result to emmc
2175 12:14:56.170846 dram_init: config_dvfs: 1
2176 12:14:56.174057 dramc_set_vcore_voltage set vcore to 662500
2177 12:14:56.177435 Read voltage for 1200, 2
2178 12:14:56.177550 Vio18 = 0
2179 12:14:56.177646 Vcore = 662500
2180 12:14:56.180856 Vdram = 0
2181 12:14:56.180939 Vddq = 0
2182 12:14:56.181005 Vmddr = 0
2183 12:14:56.187589 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2184 12:14:56.190990 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2185 12:14:56.194480 MEM_TYPE=3, freq_sel=15
2186 12:14:56.197871 sv_algorithm_assistance_LP4_1600
2187 12:14:56.201197 ============ PULL DRAM RESETB DOWN ============
2188 12:14:56.204019 ========== PULL DRAM RESETB DOWN end =========
2189 12:14:56.210895 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2190 12:14:56.214168 ===================================
2191 12:14:56.217690 LPDDR4 DRAM CONFIGURATION
2192 12:14:56.221147 ===================================
2193 12:14:56.221262 EX_ROW_EN[0] = 0x0
2194 12:14:56.224424 EX_ROW_EN[1] = 0x0
2195 12:14:56.224532 LP4Y_EN = 0x0
2196 12:14:56.227199 WORK_FSP = 0x0
2197 12:14:56.227299 WL = 0x4
2198 12:14:56.230585 RL = 0x4
2199 12:14:56.230693 BL = 0x2
2200 12:14:56.234397 RPST = 0x0
2201 12:14:56.234480 RD_PRE = 0x0
2202 12:14:56.237735 WR_PRE = 0x1
2203 12:14:56.237817 WR_PST = 0x0
2204 12:14:56.241041 DBI_WR = 0x0
2205 12:14:56.241124 DBI_RD = 0x0
2206 12:14:56.244289 OTF = 0x1
2207 12:14:56.247687 ===================================
2208 12:14:56.250968 ===================================
2209 12:14:56.251077 ANA top config
2210 12:14:56.254344 ===================================
2211 12:14:56.257706 DLL_ASYNC_EN = 0
2212 12:14:56.261151 ALL_SLAVE_EN = 0
2213 12:14:56.264393 NEW_RANK_MODE = 1
2214 12:14:56.264477 DLL_IDLE_MODE = 1
2215 12:14:56.267642 LP45_APHY_COMB_EN = 1
2216 12:14:56.270709 TX_ODT_DIS = 1
2217 12:14:56.274476 NEW_8X_MODE = 1
2218 12:14:56.277728 ===================================
2219 12:14:56.281142 ===================================
2220 12:14:56.284259 data_rate = 2400
2221 12:14:56.284342 CKR = 1
2222 12:14:56.287585 DQ_P2S_RATIO = 8
2223 12:14:56.290867 ===================================
2224 12:14:56.294222 CA_P2S_RATIO = 8
2225 12:14:56.297606 DQ_CA_OPEN = 0
2226 12:14:56.301096 DQ_SEMI_OPEN = 0
2227 12:14:56.304362 CA_SEMI_OPEN = 0
2228 12:14:56.304446 CA_FULL_RATE = 0
2229 12:14:56.307846 DQ_CKDIV4_EN = 0
2230 12:14:56.311262 CA_CKDIV4_EN = 0
2231 12:14:56.314719 CA_PREDIV_EN = 0
2232 12:14:56.318110 PH8_DLY = 17
2233 12:14:56.318219 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2234 12:14:56.320834 DQ_AAMCK_DIV = 4
2235 12:14:56.324082 CA_AAMCK_DIV = 4
2236 12:14:56.327598 CA_ADMCK_DIV = 4
2237 12:14:56.331076 DQ_TRACK_CA_EN = 0
2238 12:14:56.334402 CA_PICK = 1200
2239 12:14:56.337870 CA_MCKIO = 1200
2240 12:14:56.337956 MCKIO_SEMI = 0
2241 12:14:56.341185 PLL_FREQ = 2366
2242 12:14:56.344328 DQ_UI_PI_RATIO = 32
2243 12:14:56.347662 CA_UI_PI_RATIO = 0
2244 12:14:56.350887 ===================================
2245 12:14:56.354235 ===================================
2246 12:14:56.357475 memory_type:LPDDR4
2247 12:14:56.357558 GP_NUM : 10
2248 12:14:56.360812 SRAM_EN : 1
2249 12:14:56.364351 MD32_EN : 0
2250 12:14:56.367610 ===================================
2251 12:14:56.367695 [ANA_INIT] >>>>>>>>>>>>>>
2252 12:14:56.371024 <<<<<< [CONFIGURE PHASE]: ANA_TX
2253 12:14:56.374260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2254 12:14:56.377562 ===================================
2255 12:14:56.381174 data_rate = 2400,PCW = 0X5b00
2256 12:14:56.384376 ===================================
2257 12:14:56.387568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2258 12:14:56.394132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 12:14:56.397978 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2260 12:14:56.404099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2261 12:14:56.407535 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2262 12:14:56.410973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2263 12:14:56.411072 [ANA_INIT] flow start
2264 12:14:56.414275 [ANA_INIT] PLL >>>>>>>>
2265 12:14:56.417724 [ANA_INIT] PLL <<<<<<<<
2266 12:14:56.417831 [ANA_INIT] MIDPI >>>>>>>>
2267 12:14:56.421047 [ANA_INIT] MIDPI <<<<<<<<
2268 12:14:56.424436 [ANA_INIT] DLL >>>>>>>>
2269 12:14:56.424538 [ANA_INIT] DLL <<<<<<<<
2270 12:14:56.427840 [ANA_INIT] flow end
2271 12:14:56.431275 ============ LP4 DIFF to SE enter ============
2272 12:14:56.434639 ============ LP4 DIFF to SE exit ============
2273 12:14:56.437942 [ANA_INIT] <<<<<<<<<<<<<
2274 12:14:56.441296 [Flow] Enable top DCM control >>>>>
2275 12:14:56.444785 [Flow] Enable top DCM control <<<<<
2276 12:14:56.448055 Enable DLL master slave shuffle
2277 12:14:56.454622 ==============================================================
2278 12:14:56.454731 Gating Mode config
2279 12:14:56.460778 ==============================================================
2280 12:14:56.460856 Config description:
2281 12:14:56.470891 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2282 12:14:56.477797 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2283 12:14:56.484340 SELPH_MODE 0: By rank 1: By Phase
2284 12:14:56.490712 ==============================================================
2285 12:14:56.490820 GAT_TRACK_EN = 1
2286 12:14:56.494410 RX_GATING_MODE = 2
2287 12:14:56.497811 RX_GATING_TRACK_MODE = 2
2288 12:14:56.500913 SELPH_MODE = 1
2289 12:14:56.504086 PICG_EARLY_EN = 1
2290 12:14:56.507299 VALID_LAT_VALUE = 1
2291 12:14:56.514153 ==============================================================
2292 12:14:56.517515 Enter into Gating configuration >>>>
2293 12:14:56.520822 Exit from Gating configuration <<<<
2294 12:14:56.520899 Enter into DVFS_PRE_config >>>>>
2295 12:14:56.534404 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2296 12:14:56.537265 Exit from DVFS_PRE_config <<<<<
2297 12:14:56.540559 Enter into PICG configuration >>>>
2298 12:14:56.543925 Exit from PICG configuration <<<<
2299 12:14:56.544006 [RX_INPUT] configuration >>>>>
2300 12:14:56.547225 [RX_INPUT] configuration <<<<<
2301 12:14:56.554106 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2302 12:14:56.557902 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2303 12:14:56.564375 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2304 12:14:56.571258 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2305 12:14:56.577463 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 12:14:56.584335 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 12:14:56.587653 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2308 12:14:56.590939 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2309 12:14:56.597427 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2310 12:14:56.600711 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2311 12:14:56.604467 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2312 12:14:56.607779 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2313 12:14:56.611028 ===================================
2314 12:14:56.614272 LPDDR4 DRAM CONFIGURATION
2315 12:14:56.617819 ===================================
2316 12:14:56.621118 EX_ROW_EN[0] = 0x0
2317 12:14:56.621201 EX_ROW_EN[1] = 0x0
2318 12:14:56.624486 LP4Y_EN = 0x0
2319 12:14:56.624569 WORK_FSP = 0x0
2320 12:14:56.627942 WL = 0x4
2321 12:14:56.628026 RL = 0x4
2322 12:14:56.631264 BL = 0x2
2323 12:14:56.631369 RPST = 0x0
2324 12:14:56.634747 RD_PRE = 0x0
2325 12:14:56.634830 WR_PRE = 0x1
2326 12:14:56.637413 WR_PST = 0x0
2327 12:14:56.637497 DBI_WR = 0x0
2328 12:14:56.640867 DBI_RD = 0x0
2329 12:14:56.640950 OTF = 0x1
2330 12:14:56.644241 ===================================
2331 12:14:56.647634 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2332 12:14:56.654388 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2333 12:14:56.657818 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2334 12:14:56.661039 ===================================
2335 12:14:56.664305 LPDDR4 DRAM CONFIGURATION
2336 12:14:56.667562 ===================================
2337 12:14:56.667638 EX_ROW_EN[0] = 0x10
2338 12:14:56.671387 EX_ROW_EN[1] = 0x0
2339 12:14:56.674701 LP4Y_EN = 0x0
2340 12:14:56.674784 WORK_FSP = 0x0
2341 12:14:56.677563 WL = 0x4
2342 12:14:56.677646 RL = 0x4
2343 12:14:56.680863 BL = 0x2
2344 12:14:56.680946 RPST = 0x0
2345 12:14:56.684323 RD_PRE = 0x0
2346 12:14:56.684405 WR_PRE = 0x1
2347 12:14:56.687698 WR_PST = 0x0
2348 12:14:56.687782 DBI_WR = 0x0
2349 12:14:56.691199 DBI_RD = 0x0
2350 12:14:56.691282 OTF = 0x1
2351 12:14:56.694692 ===================================
2352 12:14:56.701395 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2353 12:14:56.701479 ==
2354 12:14:56.704754 Dram Type= 6, Freq= 0, CH_0, rank 0
2355 12:14:56.707511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2356 12:14:56.707591 ==
2357 12:14:56.711384 [Duty_Offset_Calibration]
2358 12:14:56.714704 B0:2 B1:1 CA:1
2359 12:14:56.714785
2360 12:14:56.717940 [DutyScan_Calibration_Flow] k_type=0
2361 12:14:56.725855
2362 12:14:56.725937 ==CLK 0==
2363 12:14:56.729113 Final CLK duty delay cell = 0
2364 12:14:56.732474 [0] MAX Duty = 5187%(X100), DQS PI = 24
2365 12:14:56.735855 [0] MIN Duty = 4875%(X100), DQS PI = 0
2366 12:14:56.735935 [0] AVG Duty = 5031%(X100)
2367 12:14:56.736000
2368 12:14:56.739298 CH0 CLK Duty spec in!! Max-Min= 312%
2369 12:14:56.746242 [DutyScan_Calibration_Flow] ====Done====
2370 12:14:56.746327
2371 12:14:56.749183 [DutyScan_Calibration_Flow] k_type=1
2372 12:14:56.764049
2373 12:14:56.764129 ==DQS 0 ==
2374 12:14:56.767227 Final DQS duty delay cell = -4
2375 12:14:56.770589 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2376 12:14:56.773308 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2377 12:14:56.777117 [-4] AVG Duty = 4953%(X100)
2378 12:14:56.777208
2379 12:14:56.777285 ==DQS 1 ==
2380 12:14:56.780490 Final DQS duty delay cell = -4
2381 12:14:56.783741 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2382 12:14:56.787203 [-4] MIN Duty = 4844%(X100), DQS PI = 30
2383 12:14:56.790432 [-4] AVG Duty = 4906%(X100)
2384 12:14:56.790512
2385 12:14:56.793712 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2386 12:14:56.793792
2387 12:14:56.797172 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2388 12:14:56.799962 [DutyScan_Calibration_Flow] ====Done====
2389 12:14:56.800048
2390 12:14:56.803297 [DutyScan_Calibration_Flow] k_type=3
2391 12:14:56.820522
2392 12:14:56.820602 ==DQM 0 ==
2393 12:14:56.823789 Final DQM duty delay cell = 0
2394 12:14:56.827576 [0] MAX Duty = 5156%(X100), DQS PI = 30
2395 12:14:56.830768 [0] MIN Duty = 4907%(X100), DQS PI = 58
2396 12:14:56.834202 [0] AVG Duty = 5031%(X100)
2397 12:14:56.834283
2398 12:14:56.834346 ==DQM 1 ==
2399 12:14:56.837344 Final DQM duty delay cell = 0
2400 12:14:56.840709 [0] MAX Duty = 5124%(X100), DQS PI = 60
2401 12:14:56.844112 [0] MIN Duty = 5031%(X100), DQS PI = 50
2402 12:14:56.847593 [0] AVG Duty = 5077%(X100)
2403 12:14:56.847675
2404 12:14:56.850978 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2405 12:14:56.851058
2406 12:14:56.854501 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2407 12:14:56.857268 [DutyScan_Calibration_Flow] ====Done====
2408 12:14:56.857348
2409 12:14:56.860615 [DutyScan_Calibration_Flow] k_type=2
2410 12:14:56.877214
2411 12:14:56.877295 ==DQ 0 ==
2412 12:14:56.880492 Final DQ duty delay cell = 0
2413 12:14:56.883706 [0] MAX Duty = 5062%(X100), DQS PI = 32
2414 12:14:56.887673 [0] MIN Duty = 4906%(X100), DQS PI = 0
2415 12:14:56.887758 [0] AVG Duty = 4984%(X100)
2416 12:14:56.887843
2417 12:14:56.890771 ==DQ 1 ==
2418 12:14:56.894237 Final DQ duty delay cell = 0
2419 12:14:56.897638 [0] MAX Duty = 5093%(X100), DQS PI = 24
2420 12:14:56.901124 [0] MIN Duty = 4969%(X100), DQS PI = 14
2421 12:14:56.901210 [0] AVG Duty = 5031%(X100)
2422 12:14:56.901295
2423 12:14:56.903897 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2424 12:14:56.903981
2425 12:14:56.907149 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2426 12:14:56.911035 [DutyScan_Calibration_Flow] ====Done====
2427 12:14:56.914315 ==
2428 12:14:56.917852 Dram Type= 6, Freq= 0, CH_1, rank 0
2429 12:14:56.920584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2430 12:14:56.920662 ==
2431 12:14:56.924015 [Duty_Offset_Calibration]
2432 12:14:56.924093 B0:1 B1:0 CA:0
2433 12:14:56.924157
2434 12:14:56.927285 [DutyScan_Calibration_Flow] k_type=0
2435 12:14:56.936334
2436 12:14:56.936416 ==CLK 0==
2437 12:14:56.939653 Final CLK duty delay cell = -4
2438 12:14:56.942790 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2439 12:14:56.946044 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2440 12:14:56.949356 [-4] AVG Duty = 4969%(X100)
2441 12:14:56.949430
2442 12:14:56.952863 CH1 CLK Duty spec in!! Max-Min= 124%
2443 12:14:56.956263 [DutyScan_Calibration_Flow] ====Done====
2444 12:14:56.956339
2445 12:14:56.959599 [DutyScan_Calibration_Flow] k_type=1
2446 12:14:56.975957
2447 12:14:56.976037 ==DQS 0 ==
2448 12:14:56.979292 Final DQS duty delay cell = 0
2449 12:14:56.983122 [0] MAX Duty = 5094%(X100), DQS PI = 26
2450 12:14:56.985813 [0] MIN Duty = 4875%(X100), DQS PI = 0
2451 12:14:56.985886 [0] AVG Duty = 4984%(X100)
2452 12:14:56.989753
2453 12:14:56.989825 ==DQS 1 ==
2454 12:14:56.993076 Final DQS duty delay cell = 0
2455 12:14:56.996320 [0] MAX Duty = 5187%(X100), DQS PI = 18
2456 12:14:56.999687 [0] MIN Duty = 4969%(X100), DQS PI = 10
2457 12:14:56.999790 [0] AVG Duty = 5078%(X100)
2458 12:14:57.003145
2459 12:14:57.005867 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2460 12:14:57.005939
2461 12:14:57.009138 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2462 12:14:57.012447 [DutyScan_Calibration_Flow] ====Done====
2463 12:14:57.012518
2464 12:14:57.015718 [DutyScan_Calibration_Flow] k_type=3
2465 12:14:57.032937
2466 12:14:57.033017 ==DQM 0 ==
2467 12:14:57.036246 Final DQM duty delay cell = 0
2468 12:14:57.039470 [0] MAX Duty = 5156%(X100), DQS PI = 6
2469 12:14:57.042626 [0] MIN Duty = 5031%(X100), DQS PI = 0
2470 12:14:57.042699 [0] AVG Duty = 5093%(X100)
2471 12:14:57.045799
2472 12:14:57.045872 ==DQM 1 ==
2473 12:14:57.049475 Final DQM duty delay cell = 0
2474 12:14:57.052674 [0] MAX Duty = 5031%(X100), DQS PI = 16
2475 12:14:57.055947 [0] MIN Duty = 4907%(X100), DQS PI = 36
2476 12:14:57.056021 [0] AVG Duty = 4969%(X100)
2477 12:14:57.059185
2478 12:14:57.062603 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2479 12:14:57.062677
2480 12:14:57.066051 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2481 12:14:57.069543 [DutyScan_Calibration_Flow] ====Done====
2482 12:14:57.069616
2483 12:14:57.072202 [DutyScan_Calibration_Flow] k_type=2
2484 12:14:57.088165
2485 12:14:57.088250 ==DQ 0 ==
2486 12:14:57.091452 Final DQ duty delay cell = -4
2487 12:14:57.094854 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2488 12:14:57.098102 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2489 12:14:57.101972 [-4] AVG Duty = 5000%(X100)
2490 12:14:57.102056
2491 12:14:57.102121 ==DQ 1 ==
2492 12:14:57.104751 Final DQ duty delay cell = 0
2493 12:14:57.108155 [0] MAX Duty = 5125%(X100), DQS PI = 20
2494 12:14:57.111621 [0] MIN Duty = 4969%(X100), DQS PI = 12
2495 12:14:57.111703 [0] AVG Duty = 5047%(X100)
2496 12:14:57.111768
2497 12:14:57.115042 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2498 12:14:57.118360
2499 12:14:57.122132 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2500 12:14:57.125459 [DutyScan_Calibration_Flow] ====Done====
2501 12:14:57.128221 nWR fixed to 30
2502 12:14:57.128303 [ModeRegInit_LP4] CH0 RK0
2503 12:14:57.131696 [ModeRegInit_LP4] CH0 RK1
2504 12:14:57.135135 [ModeRegInit_LP4] CH1 RK0
2505 12:14:57.135216 [ModeRegInit_LP4] CH1 RK1
2506 12:14:57.138580 match AC timing 7
2507 12:14:57.141944 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2508 12:14:57.145046 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2509 12:14:57.151514 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2510 12:14:57.154762 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2511 12:14:57.161923 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2512 12:14:57.162005 ==
2513 12:14:57.165204 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 12:14:57.168564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 12:14:57.168638 ==
2516 12:14:57.175303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2517 12:14:57.178586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2518 12:14:57.188869 [CA 0] Center 39 (8~70) winsize 63
2519 12:14:57.192158 [CA 1] Center 39 (8~70) winsize 63
2520 12:14:57.195456 [CA 2] Center 35 (5~66) winsize 62
2521 12:14:57.198755 [CA 3] Center 34 (4~65) winsize 62
2522 12:14:57.202059 [CA 4] Center 33 (3~64) winsize 62
2523 12:14:57.205292 [CA 5] Center 32 (3~62) winsize 60
2524 12:14:57.205369
2525 12:14:57.208512 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2526 12:14:57.208586
2527 12:14:57.211759 [CATrainingPosCal] consider 1 rank data
2528 12:14:57.215080 u2DelayCellTimex100 = 270/100 ps
2529 12:14:57.218506 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2530 12:14:57.221896 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2531 12:14:57.228387 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2532 12:14:57.231940 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2533 12:14:57.235289 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2534 12:14:57.238678 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2535 12:14:57.238754
2536 12:14:57.241324 CA PerBit enable=1, Macro0, CA PI delay=32
2537 12:14:57.241396
2538 12:14:57.244708 [CBTSetCACLKResult] CA Dly = 32
2539 12:14:57.244779 CS Dly: 6 (0~37)
2540 12:14:57.248053 ==
2541 12:14:57.251642 Dram Type= 6, Freq= 0, CH_0, rank 1
2542 12:14:57.255133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 12:14:57.255216 ==
2544 12:14:57.258093 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2545 12:14:57.264995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2546 12:14:57.274638 [CA 0] Center 38 (8~69) winsize 62
2547 12:14:57.278149 [CA 1] Center 38 (8~69) winsize 62
2548 12:14:57.280863 [CA 2] Center 35 (4~66) winsize 63
2549 12:14:57.285264 [CA 3] Center 34 (4~65) winsize 62
2550 12:14:57.287940 [CA 4] Center 33 (3~64) winsize 62
2551 12:14:57.291393 [CA 5] Center 32 (3~62) winsize 60
2552 12:14:57.291938
2553 12:14:57.295025 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2554 12:14:57.295590
2555 12:14:57.298328 [CATrainingPosCal] consider 2 rank data
2556 12:14:57.301679 u2DelayCellTimex100 = 270/100 ps
2557 12:14:57.304862 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2558 12:14:57.308116 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2559 12:14:57.314697 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2560 12:14:57.318049 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2561 12:14:57.321244 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2562 12:14:57.324224 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2563 12:14:57.324308
2564 12:14:57.327497 CA PerBit enable=1, Macro0, CA PI delay=32
2565 12:14:57.327581
2566 12:14:57.330911 [CBTSetCACLKResult] CA Dly = 32
2567 12:14:57.330995 CS Dly: 6 (0~38)
2568 12:14:57.331060
2569 12:14:57.334204 ----->DramcWriteLeveling(PI) begin...
2570 12:14:57.337906 ==
2571 12:14:57.341523 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 12:14:57.345332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 12:14:57.345871 ==
2574 12:14:57.348511 Write leveling (Byte 0): 34 => 34
2575 12:14:57.351943 Write leveling (Byte 1): 31 => 31
2576 12:14:57.354550 DramcWriteLeveling(PI) end<-----
2577 12:14:57.355105
2578 12:14:57.355574 ==
2579 12:14:57.358048 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 12:14:57.361327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 12:14:57.361775 ==
2582 12:14:57.364506 [Gating] SW mode calibration
2583 12:14:57.371725 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2584 12:14:57.375139 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2585 12:14:57.381730 0 15 0 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
2586 12:14:57.385212 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2587 12:14:57.388000 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 12:14:57.395028 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 12:14:57.398476 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 12:14:57.401201 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 12:14:57.408132 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2592 12:14:57.411396 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
2593 12:14:57.414500 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
2594 12:14:57.421876 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 12:14:57.425113 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 12:14:57.428484 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 12:14:57.434881 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 12:14:57.438372 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 12:14:57.441766 1 0 24 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
2600 12:14:57.445322 1 0 28 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
2601 12:14:57.451951 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2602 12:14:57.455392 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 12:14:57.458136 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 12:14:57.465001 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 12:14:57.468380 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 12:14:57.471605 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 12:14:57.478071 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 12:14:57.482123 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2609 12:14:57.485449 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2610 12:14:57.491967 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 12:14:57.495405 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 12:14:57.498834 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 12:14:57.504962 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 12:14:57.508413 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 12:14:57.511728 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 12:14:57.518454 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 12:14:57.521632 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 12:14:57.525140 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 12:14:57.528460 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 12:14:57.535441 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 12:14:57.538527 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 12:14:57.541822 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 12:14:57.548672 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:14:57.551936 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2625 12:14:57.555347 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2626 12:14:57.558691 Total UI for P1: 0, mck2ui 16
2627 12:14:57.562233 best dqsien dly found for B0: ( 1, 3, 28)
2628 12:14:57.569086 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 12:14:57.569716 Total UI for P1: 0, mck2ui 16
2630 12:14:57.571897 best dqsien dly found for B1: ( 1, 3, 30)
2631 12:14:57.578664 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2632 12:14:57.582057 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2633 12:14:57.582491
2634 12:14:57.585203 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2635 12:14:57.589076 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2636 12:14:57.592207 [Gating] SW calibration Done
2637 12:14:57.592643 ==
2638 12:14:57.595548 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 12:14:57.599074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 12:14:57.599538 ==
2641 12:14:57.602463 RX Vref Scan: 0
2642 12:14:57.602880
2643 12:14:57.603216 RX Vref 0 -> 0, step: 1
2644 12:14:57.603582
2645 12:14:57.605937 RX Delay -40 -> 252, step: 8
2646 12:14:57.608618 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2647 12:14:57.612033 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2648 12:14:57.619371 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2649 12:14:57.622562 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2650 12:14:57.625868 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2651 12:14:57.629083 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2652 12:14:57.632247 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2653 12:14:57.638834 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2654 12:14:57.642366 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2655 12:14:57.645557 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2656 12:14:57.648913 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2657 12:14:57.652379 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2658 12:14:57.658566 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2659 12:14:57.662010 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2660 12:14:57.665434 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2661 12:14:57.668797 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2662 12:14:57.669216 ==
2663 12:14:57.672292 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 12:14:57.679045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 12:14:57.679599 ==
2666 12:14:57.679951 DQS Delay:
2667 12:14:57.681926 DQS0 = 0, DQS1 = 0
2668 12:14:57.682406 DQM Delay:
2669 12:14:57.682756 DQM0 = 121, DQM1 = 114
2670 12:14:57.685352 DQ Delay:
2671 12:14:57.688715 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2672 12:14:57.692027 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2673 12:14:57.695838 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2674 12:14:57.699045 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2675 12:14:57.699515
2676 12:14:57.699858
2677 12:14:57.700175 ==
2678 12:14:57.702425 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 12:14:57.705695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 12:14:57.706135 ==
2681 12:14:57.709087
2682 12:14:57.709510
2683 12:14:57.709851 TX Vref Scan disable
2684 12:14:57.712441 == TX Byte 0 ==
2685 12:14:57.715798 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2686 12:14:57.719289 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2687 12:14:57.721980 == TX Byte 1 ==
2688 12:14:57.726077 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2689 12:14:57.729501 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2690 12:14:57.729930 ==
2691 12:14:57.732092 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 12:14:57.738617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 12:14:57.739049 ==
2694 12:14:57.749980 TX Vref=22, minBit 0, minWin=25, winSum=409
2695 12:14:57.752642 TX Vref=24, minBit 1, minWin=25, winSum=413
2696 12:14:57.756333 TX Vref=26, minBit 4, minWin=25, winSum=416
2697 12:14:57.759541 TX Vref=28, minBit 12, minWin=25, winSum=421
2698 12:14:57.762990 TX Vref=30, minBit 13, minWin=25, winSum=423
2699 12:14:57.769751 TX Vref=32, minBit 1, minWin=26, winSum=424
2700 12:14:57.773073 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 32
2701 12:14:57.773499
2702 12:14:57.775972 Final TX Range 1 Vref 32
2703 12:14:57.776398
2704 12:14:57.776734 ==
2705 12:14:57.779143 Dram Type= 6, Freq= 0, CH_0, rank 0
2706 12:14:57.782602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2707 12:14:57.783029 ==
2708 12:14:57.786082
2709 12:14:57.786505
2710 12:14:57.786841 TX Vref Scan disable
2711 12:14:57.789366 == TX Byte 0 ==
2712 12:14:57.792762 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2713 12:14:57.796163 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2714 12:14:57.799378 == TX Byte 1 ==
2715 12:14:57.802710 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2716 12:14:57.806206 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2717 12:14:57.809279
2718 12:14:57.809750 [DATLAT]
2719 12:14:57.810210 Freq=1200, CH0 RK0
2720 12:14:57.810622
2721 12:14:57.812621 DATLAT Default: 0xd
2722 12:14:57.813224 0, 0xFFFF, sum = 0
2723 12:14:57.816021 1, 0xFFFF, sum = 0
2724 12:14:57.816451 2, 0xFFFF, sum = 0
2725 12:14:57.819574 3, 0xFFFF, sum = 0
2726 12:14:57.820004 4, 0xFFFF, sum = 0
2727 12:14:57.823030 5, 0xFFFF, sum = 0
2728 12:14:57.826482 6, 0xFFFF, sum = 0
2729 12:14:57.826909 7, 0xFFFF, sum = 0
2730 12:14:57.829852 8, 0xFFFF, sum = 0
2731 12:14:57.830282 9, 0xFFFF, sum = 0
2732 12:14:57.832554 10, 0xFFFF, sum = 0
2733 12:14:57.832982 11, 0xFFFF, sum = 0
2734 12:14:57.835912 12, 0x0, sum = 1
2735 12:14:57.836393 13, 0x0, sum = 2
2736 12:14:57.839566 14, 0x0, sum = 3
2737 12:14:57.840099 15, 0x0, sum = 4
2738 12:14:57.840445 best_step = 13
2739 12:14:57.840760
2740 12:14:57.842859 ==
2741 12:14:57.846030 Dram Type= 6, Freq= 0, CH_0, rank 0
2742 12:14:57.849758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2743 12:14:57.850181 ==
2744 12:14:57.850534 RX Vref Scan: 1
2745 12:14:57.850868
2746 12:14:57.853103 Set Vref Range= 32 -> 127
2747 12:14:57.853526
2748 12:14:57.856313 RX Vref 32 -> 127, step: 1
2749 12:14:57.856738
2750 12:14:57.859661 RX Delay -13 -> 252, step: 4
2751 12:14:57.860089
2752 12:14:57.862804 Set Vref, RX VrefLevel [Byte0]: 32
2753 12:14:57.866188 [Byte1]: 32
2754 12:14:57.866628
2755 12:14:57.869783 Set Vref, RX VrefLevel [Byte0]: 33
2756 12:14:57.872596 [Byte1]: 33
2757 12:14:57.873018
2758 12:14:57.875962 Set Vref, RX VrefLevel [Byte0]: 34
2759 12:14:57.879220 [Byte1]: 34
2760 12:14:57.883916
2761 12:14:57.884337 Set Vref, RX VrefLevel [Byte0]: 35
2762 12:14:57.887290 [Byte1]: 35
2763 12:14:57.891433
2764 12:14:57.891854 Set Vref, RX VrefLevel [Byte0]: 36
2765 12:14:57.895176 [Byte1]: 36
2766 12:14:57.899952
2767 12:14:57.900477 Set Vref, RX VrefLevel [Byte0]: 37
2768 12:14:57.903122 [Byte1]: 37
2769 12:14:57.907611
2770 12:14:57.908036 Set Vref, RX VrefLevel [Byte0]: 38
2771 12:14:57.910747 [Byte1]: 38
2772 12:14:57.915110
2773 12:14:57.915561 Set Vref, RX VrefLevel [Byte0]: 39
2774 12:14:57.918842 [Byte1]: 39
2775 12:14:57.923167
2776 12:14:57.923609 Set Vref, RX VrefLevel [Byte0]: 40
2777 12:14:57.926567 [Byte1]: 40
2778 12:14:57.931295
2779 12:14:57.931741 Set Vref, RX VrefLevel [Byte0]: 41
2780 12:14:57.934723 [Byte1]: 41
2781 12:14:57.939163
2782 12:14:57.939735 Set Vref, RX VrefLevel [Byte0]: 42
2783 12:14:57.942236 [Byte1]: 42
2784 12:14:57.947164
2785 12:14:57.947603 Set Vref, RX VrefLevel [Byte0]: 43
2786 12:14:57.949925 [Byte1]: 43
2787 12:14:57.954778
2788 12:14:57.955402 Set Vref, RX VrefLevel [Byte0]: 44
2789 12:14:57.957741 [Byte1]: 44
2790 12:14:57.962501
2791 12:14:57.962925 Set Vref, RX VrefLevel [Byte0]: 45
2792 12:14:57.965743 [Byte1]: 45
2793 12:14:57.970325
2794 12:14:57.970767 Set Vref, RX VrefLevel [Byte0]: 46
2795 12:14:57.974292 [Byte1]: 46
2796 12:14:57.978336
2797 12:14:57.978895 Set Vref, RX VrefLevel [Byte0]: 47
2798 12:14:57.981858 [Byte1]: 47
2799 12:14:57.986760
2800 12:14:57.987371 Set Vref, RX VrefLevel [Byte0]: 48
2801 12:14:57.989393 [Byte1]: 48
2802 12:14:57.994322
2803 12:14:57.994737 Set Vref, RX VrefLevel [Byte0]: 49
2804 12:14:57.997764 [Byte1]: 49
2805 12:14:58.002506
2806 12:14:58.002922 Set Vref, RX VrefLevel [Byte0]: 50
2807 12:14:58.005287 [Byte1]: 50
2808 12:14:58.010176
2809 12:14:58.010619 Set Vref, RX VrefLevel [Byte0]: 51
2810 12:14:58.013819 [Byte1]: 51
2811 12:14:58.018489
2812 12:14:58.019175 Set Vref, RX VrefLevel [Byte0]: 52
2813 12:14:58.021478 [Byte1]: 52
2814 12:14:58.026029
2815 12:14:58.026491 Set Vref, RX VrefLevel [Byte0]: 53
2816 12:14:58.028721 [Byte1]: 53
2817 12:14:58.033679
2818 12:14:58.034097 Set Vref, RX VrefLevel [Byte0]: 54
2819 12:14:58.037282 [Byte1]: 54
2820 12:14:58.041734
2821 12:14:58.042260 Set Vref, RX VrefLevel [Byte0]: 55
2822 12:14:58.045079 [Byte1]: 55
2823 12:14:58.049833
2824 12:14:58.053273 Set Vref, RX VrefLevel [Byte0]: 56
2825 12:14:58.053800 [Byte1]: 56
2826 12:14:58.057999
2827 12:14:58.058515 Set Vref, RX VrefLevel [Byte0]: 57
2828 12:14:58.060535 [Byte1]: 57
2829 12:14:58.064964
2830 12:14:58.065490 Set Vref, RX VrefLevel [Byte0]: 58
2831 12:14:58.068369 [Byte1]: 58
2832 12:14:58.072814
2833 12:14:58.073277 Set Vref, RX VrefLevel [Byte0]: 59
2834 12:14:58.076545 [Byte1]: 59
2835 12:14:58.081132
2836 12:14:58.081550 Set Vref, RX VrefLevel [Byte0]: 60
2837 12:14:58.084130 [Byte1]: 60
2838 12:14:58.088692
2839 12:14:58.089108 Set Vref, RX VrefLevel [Byte0]: 61
2840 12:14:58.092168 [Byte1]: 61
2841 12:14:58.096992
2842 12:14:58.097416 Set Vref, RX VrefLevel [Byte0]: 62
2843 12:14:58.100383 [Byte1]: 62
2844 12:14:58.104824
2845 12:14:58.105342 Set Vref, RX VrefLevel [Byte0]: 63
2846 12:14:58.107905 [Byte1]: 63
2847 12:14:58.112726
2848 12:14:58.113143 Set Vref, RX VrefLevel [Byte0]: 64
2849 12:14:58.115995 [Byte1]: 64
2850 12:14:58.120132
2851 12:14:58.120548 Set Vref, RX VrefLevel [Byte0]: 65
2852 12:14:58.123387 [Byte1]: 65
2853 12:14:58.128551
2854 12:14:58.128967 Set Vref, RX VrefLevel [Byte0]: 66
2855 12:14:58.131716 [Byte1]: 66
2856 12:14:58.135887
2857 12:14:58.136303 Set Vref, RX VrefLevel [Byte0]: 67
2858 12:14:58.139717 [Byte1]: 67
2859 12:14:58.144007
2860 12:14:58.144426 Set Vref, RX VrefLevel [Byte0]: 68
2861 12:14:58.147281 [Byte1]: 68
2862 12:14:58.151827
2863 12:14:58.152255 Set Vref, RX VrefLevel [Byte0]: 69
2864 12:14:58.155193 [Byte1]: 69
2865 12:14:58.159983
2866 12:14:58.160407 Final RX Vref Byte 0 = 56 to rank0
2867 12:14:58.163418 Final RX Vref Byte 1 = 49 to rank0
2868 12:14:58.166854 Final RX Vref Byte 0 = 56 to rank1
2869 12:14:58.170375 Final RX Vref Byte 1 = 49 to rank1==
2870 12:14:58.173329 Dram Type= 6, Freq= 0, CH_0, rank 0
2871 12:14:58.180050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 12:14:58.180625 ==
2873 12:14:58.181022 DQS Delay:
2874 12:14:58.181461 DQS0 = 0, DQS1 = 0
2875 12:14:58.183133 DQM Delay:
2876 12:14:58.183722 DQM0 = 120, DQM1 = 112
2877 12:14:58.186689 DQ Delay:
2878 12:14:58.190033 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =120
2879 12:14:58.193327 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2880 12:14:58.196615 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2881 12:14:58.200039 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2882 12:14:58.200466
2883 12:14:58.200805
2884 12:14:58.207468 [DQSOSCAuto] RK0, (LSB)MR18= 0x120b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2885 12:14:58.210515 CH0 RK0: MR19=404, MR18=120B
2886 12:14:58.216983 CH0_RK0: MR19=0x404, MR18=0x120B, DQSOSC=403, MR23=63, INC=40, DEC=26
2887 12:14:58.217508
2888 12:14:58.220033 ----->DramcWriteLeveling(PI) begin...
2889 12:14:58.220488 ==
2890 12:14:58.223412 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 12:14:58.226830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 12:14:58.227253 ==
2893 12:14:58.230114 Write leveling (Byte 0): 34 => 34
2894 12:14:58.233930 Write leveling (Byte 1): 30 => 30
2895 12:14:58.237142 DramcWriteLeveling(PI) end<-----
2896 12:14:58.237814
2897 12:14:58.238332 ==
2898 12:14:58.240373 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 12:14:58.243614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 12:14:58.246887 ==
2901 12:14:58.247533 [Gating] SW mode calibration
2902 12:14:58.256949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2903 12:14:58.260486 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2904 12:14:58.263942 0 15 0 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (0 0)
2905 12:14:58.270111 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 12:14:58.273470 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 12:14:58.276890 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 12:14:58.283844 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 12:14:58.287098 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 12:14:58.290331 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 12:14:58.296881 0 15 28 | B1->B0 | 3131 2b2b | 0 1 | (0 0) (1 0)
2912 12:14:58.300134 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2913 12:14:58.303830 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 12:14:58.310758 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 12:14:58.313517 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 12:14:58.316865 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 12:14:58.323894 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 12:14:58.327218 1 0 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2919 12:14:58.330579 1 0 28 | B1->B0 | 3636 3939 | 1 1 | (0 0) (0 0)
2920 12:14:58.333883 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2921 12:14:58.340478 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 12:14:58.343567 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 12:14:58.346850 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 12:14:58.353362 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 12:14:58.356753 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 12:14:58.359930 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2927 12:14:58.366719 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2928 12:14:58.370217 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2929 12:14:58.373584 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 12:14:58.380388 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 12:14:58.383646 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 12:14:58.386983 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 12:14:58.393459 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 12:14:58.397070 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 12:14:58.400297 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 12:14:58.406698 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 12:14:58.410489 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 12:14:58.413901 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 12:14:58.417394 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 12:14:58.423638 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 12:14:58.427147 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 12:14:58.430412 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2943 12:14:58.437571 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2944 12:14:58.440339 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 12:14:58.443618 Total UI for P1: 0, mck2ui 16
2946 12:14:58.446971 best dqsien dly found for B0: ( 1, 3, 28)
2947 12:14:58.450776 Total UI for P1: 0, mck2ui 16
2948 12:14:58.453987 best dqsien dly found for B1: ( 1, 3, 26)
2949 12:14:58.457151 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2950 12:14:58.460573 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2951 12:14:58.460994
2952 12:14:58.463773 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2953 12:14:58.466951 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2954 12:14:58.470563 [Gating] SW calibration Done
2955 12:14:58.470983 ==
2956 12:14:58.473943 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 12:14:58.477296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 12:14:58.480764 ==
2959 12:14:58.481226 RX Vref Scan: 0
2960 12:14:58.481566
2961 12:14:58.484178 RX Vref 0 -> 0, step: 1
2962 12:14:58.484792
2963 12:14:58.486868 RX Delay -40 -> 252, step: 8
2964 12:14:58.490339 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2965 12:14:58.493774 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2966 12:14:58.497066 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2967 12:14:58.500246 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2968 12:14:58.506941 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2969 12:14:58.510294 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2970 12:14:58.513436 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2971 12:14:58.517133 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2972 12:14:58.520103 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2973 12:14:58.526580 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2974 12:14:58.530383 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2975 12:14:58.533611 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2976 12:14:58.537288 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2977 12:14:58.540785 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2978 12:14:58.547322 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2979 12:14:58.550037 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2980 12:14:58.550514 ==
2981 12:14:58.553518 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 12:14:58.556861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 12:14:58.557293 ==
2984 12:14:58.560558 DQS Delay:
2985 12:14:58.560986 DQS0 = 0, DQS1 = 0
2986 12:14:58.561322 DQM Delay:
2987 12:14:58.563867 DQM0 = 121, DQM1 = 113
2988 12:14:58.564296 DQ Delay:
2989 12:14:58.567130 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2990 12:14:58.570441 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2991 12:14:58.573913 DQ8 =103, DQ9 =103, DQ10 =111, DQ11 =107
2992 12:14:58.580535 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2993 12:14:58.581059
2994 12:14:58.581423
2995 12:14:58.581741 ==
2996 12:14:58.583812 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 12:14:58.586637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 12:14:58.587169 ==
2999 12:14:58.587630
3000 12:14:58.588137
3001 12:14:58.590519 TX Vref Scan disable
3002 12:14:58.590937 == TX Byte 0 ==
3003 12:14:58.596621 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3004 12:14:58.599943 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3005 12:14:58.600509 == TX Byte 1 ==
3006 12:14:58.606451 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3007 12:14:58.610257 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3008 12:14:58.610699 ==
3009 12:14:58.613576 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 12:14:58.616966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 12:14:58.617389 ==
3012 12:14:58.629912 TX Vref=22, minBit 1, minWin=25, winSum=411
3013 12:14:58.633398 TX Vref=24, minBit 3, minWin=25, winSum=418
3014 12:14:58.636400 TX Vref=26, minBit 15, minWin=25, winSum=421
3015 12:14:58.639785 TX Vref=28, minBit 12, minWin=25, winSum=422
3016 12:14:58.643226 TX Vref=30, minBit 14, minWin=25, winSum=427
3017 12:14:58.650061 TX Vref=32, minBit 13, minWin=25, winSum=420
3018 12:14:58.652829 [TxChooseVref] Worse bit 14, Min win 25, Win sum 427, Final Vref 30
3019 12:14:58.653250
3020 12:14:58.656354 Final TX Range 1 Vref 30
3021 12:14:58.656774
3022 12:14:58.657106 ==
3023 12:14:58.659879 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 12:14:58.663162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 12:14:58.666465 ==
3026 12:14:58.666882
3027 12:14:58.667214
3028 12:14:58.667599 TX Vref Scan disable
3029 12:14:58.670344 == TX Byte 0 ==
3030 12:14:58.673515 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3031 12:14:58.676995 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3032 12:14:58.680127 == TX Byte 1 ==
3033 12:14:58.683577 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3034 12:14:58.686286 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3035 12:14:58.689810
3036 12:14:58.690395 [DATLAT]
3037 12:14:58.690761 Freq=1200, CH0 RK1
3038 12:14:58.691086
3039 12:14:58.693755 DATLAT Default: 0xd
3040 12:14:58.694438 0, 0xFFFF, sum = 0
3041 12:14:58.696941 1, 0xFFFF, sum = 0
3042 12:14:58.697372 2, 0xFFFF, sum = 0
3043 12:14:58.700265 3, 0xFFFF, sum = 0
3044 12:14:58.700804 4, 0xFFFF, sum = 0
3045 12:14:58.703006 5, 0xFFFF, sum = 0
3046 12:14:58.706444 6, 0xFFFF, sum = 0
3047 12:14:58.706959 7, 0xFFFF, sum = 0
3048 12:14:58.710008 8, 0xFFFF, sum = 0
3049 12:14:58.710433 9, 0xFFFF, sum = 0
3050 12:14:58.713343 10, 0xFFFF, sum = 0
3051 12:14:58.713884 11, 0xFFFF, sum = 0
3052 12:14:58.716831 12, 0x0, sum = 1
3053 12:14:58.717259 13, 0x0, sum = 2
3054 12:14:58.720158 14, 0x0, sum = 3
3055 12:14:58.720735 15, 0x0, sum = 4
3056 12:14:58.721105 best_step = 13
3057 12:14:58.723431
3058 12:14:58.723862 ==
3059 12:14:58.726851 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 12:14:58.729830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 12:14:58.730307 ==
3062 12:14:58.730650 RX Vref Scan: 0
3063 12:14:58.731035
3064 12:14:58.733419 RX Vref 0 -> 0, step: 1
3065 12:14:58.733914
3066 12:14:58.736429 RX Delay -13 -> 252, step: 4
3067 12:14:58.739956 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3068 12:14:58.746670 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3069 12:14:58.750022 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3070 12:14:58.753530 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3071 12:14:58.756993 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3072 12:14:58.760380 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3073 12:14:58.762894 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3074 12:14:58.769887 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3075 12:14:58.773118 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3076 12:14:58.776763 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3077 12:14:58.779879 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3078 12:14:58.783084 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3079 12:14:58.789703 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3080 12:14:58.793106 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3081 12:14:58.796633 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3082 12:14:58.799954 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3083 12:14:58.800089 ==
3084 12:14:58.803323 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 12:14:58.810299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 12:14:58.810409 ==
3087 12:14:58.810492 DQS Delay:
3088 12:14:58.810567 DQS0 = 0, DQS1 = 0
3089 12:14:58.812987 DQM Delay:
3090 12:14:58.813079 DQM0 = 120, DQM1 = 110
3091 12:14:58.816461 DQ Delay:
3092 12:14:58.819926 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3093 12:14:58.823285 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3094 12:14:58.826460 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3095 12:14:58.829960 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3096 12:14:58.830050
3097 12:14:58.830116
3098 12:14:58.836719 [DQSOSCAuto] RK1, (LSB)MR18= 0xded, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3099 12:14:58.839911 CH0 RK1: MR19=403, MR18=DED
3100 12:14:58.846837 CH0_RK1: MR19=0x403, MR18=0xDED, DQSOSC=405, MR23=63, INC=39, DEC=26
3101 12:14:58.850196 [RxdqsGatingPostProcess] freq 1200
3102 12:14:58.856318 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3103 12:14:58.859662 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 12:14:58.859779 best DQS1 dly(2T, 0.5T) = (0, 11)
3105 12:14:58.863086 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 12:14:58.866511 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3107 12:14:58.869853 best DQS0 dly(2T, 0.5T) = (0, 11)
3108 12:14:58.873268 best DQS1 dly(2T, 0.5T) = (0, 11)
3109 12:14:58.876662 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3110 12:14:58.879946 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3111 12:14:58.883211 Pre-setting of DQS Precalculation
3112 12:14:58.889767 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3113 12:14:58.889895 ==
3114 12:14:58.893701 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 12:14:58.896852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 12:14:58.896941 ==
3117 12:14:58.900260 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 12:14:58.906431 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3119 12:14:58.915961 [CA 0] Center 37 (7~68) winsize 62
3120 12:14:58.919348 [CA 1] Center 37 (7~68) winsize 62
3121 12:14:58.922788 [CA 2] Center 35 (5~65) winsize 61
3122 12:14:58.926114 [CA 3] Center 34 (4~64) winsize 61
3123 12:14:58.928906 [CA 4] Center 34 (4~64) winsize 61
3124 12:14:58.932798 [CA 5] Center 33 (3~63) winsize 61
3125 12:14:58.932897
3126 12:14:58.936271 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3127 12:14:58.936371
3128 12:14:58.939664 [CATrainingPosCal] consider 1 rank data
3129 12:14:58.942985 u2DelayCellTimex100 = 270/100 ps
3130 12:14:58.946179 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3131 12:14:58.949691 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3132 12:14:58.956234 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3133 12:14:58.959647 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 12:14:58.962395 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 12:14:58.965837 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3136 12:14:58.965922
3137 12:14:58.969302 CA PerBit enable=1, Macro0, CA PI delay=33
3138 12:14:58.969386
3139 12:14:58.972690 [CBTSetCACLKResult] CA Dly = 33
3140 12:14:58.972815 CS Dly: 8 (0~39)
3141 12:14:58.972915 ==
3142 12:14:58.976152 Dram Type= 6, Freq= 0, CH_1, rank 1
3143 12:14:58.983107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 12:14:58.983236 ==
3145 12:14:58.986406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3146 12:14:58.992913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3147 12:14:59.001394 [CA 0] Center 37 (7~68) winsize 62
3148 12:14:59.004556 [CA 1] Center 37 (7~68) winsize 62
3149 12:14:59.007905 [CA 2] Center 35 (5~65) winsize 61
3150 12:14:59.011215 [CA 3] Center 34 (4~65) winsize 62
3151 12:14:59.014692 [CA 4] Center 34 (4~65) winsize 62
3152 12:14:59.018165 [CA 5] Center 34 (4~64) winsize 61
3153 12:14:59.018256
3154 12:14:59.021691 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3155 12:14:59.021778
3156 12:14:59.024987 [CATrainingPosCal] consider 2 rank data
3157 12:14:59.028386 u2DelayCellTimex100 = 270/100 ps
3158 12:14:59.031849 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3159 12:14:59.035244 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3160 12:14:59.041523 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3161 12:14:59.044887 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 12:14:59.048142 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 12:14:59.052136 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3164 12:14:59.052231
3165 12:14:59.054793 CA PerBit enable=1, Macro0, CA PI delay=33
3166 12:14:59.054908
3167 12:14:59.058287 [CBTSetCACLKResult] CA Dly = 33
3168 12:14:59.058377 CS Dly: 9 (0~41)
3169 12:14:59.058444
3170 12:14:59.062038 ----->DramcWriteLeveling(PI) begin...
3171 12:14:59.062155 ==
3172 12:14:59.065428 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 12:14:59.071650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 12:14:59.071767 ==
3175 12:14:59.075001 Write leveling (Byte 0): 26 => 26
3176 12:14:59.078434 Write leveling (Byte 1): 27 => 27
3177 12:14:59.078516 DramcWriteLeveling(PI) end<-----
3178 12:14:59.078582
3179 12:14:59.081884 ==
3180 12:14:59.085394 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 12:14:59.088783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 12:14:59.088877 ==
3183 12:14:59.092094 [Gating] SW mode calibration
3184 12:14:59.098649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3185 12:14:59.101860 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3186 12:14:59.108423 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 12:14:59.112036 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 12:14:59.115243 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 12:14:59.122077 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 12:14:59.125489 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 12:14:59.128918 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 12:14:59.135073 0 15 24 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 1)
3193 12:14:59.138550 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3194 12:14:59.141873 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 12:14:59.148456 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 12:14:59.151831 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 12:14:59.155173 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 12:14:59.158640 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 12:14:59.165428 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 12:14:59.168600 1 0 24 | B1->B0 | 3333 4040 | 0 0 | (0 0) (0 0)
3201 12:14:59.171940 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 12:14:59.178736 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 12:14:59.182134 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 12:14:59.185667 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 12:14:59.191772 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 12:14:59.195299 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 12:14:59.198638 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 12:14:59.205223 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3209 12:14:59.208436 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3210 12:14:59.212374 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 12:14:59.219072 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 12:14:59.222296 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 12:14:59.225640 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 12:14:59.229010 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 12:14:59.235934 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 12:14:59.238623 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 12:14:59.242000 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 12:14:59.248932 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 12:14:59.252091 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 12:14:59.255787 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 12:14:59.262320 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 12:14:59.265716 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 12:14:59.269133 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 12:14:59.275879 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 12:14:59.279264 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3226 12:14:59.282051 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 12:14:59.285357 Total UI for P1: 0, mck2ui 16
3228 12:14:59.288943 best dqsien dly found for B0: ( 1, 3, 26)
3229 12:14:59.292281 Total UI for P1: 0, mck2ui 16
3230 12:14:59.295799 best dqsien dly found for B1: ( 1, 3, 26)
3231 12:14:59.299169 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3232 12:14:59.302466 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3233 12:14:59.302554
3234 12:14:59.305971 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3235 12:14:59.312154 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3236 12:14:59.312283 [Gating] SW calibration Done
3237 12:14:59.312381 ==
3238 12:14:59.315360 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 12:14:59.322338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 12:14:59.322427 ==
3241 12:14:59.322493 RX Vref Scan: 0
3242 12:14:59.322554
3243 12:14:59.325602 RX Vref 0 -> 0, step: 1
3244 12:14:59.325684
3245 12:14:59.328977 RX Delay -40 -> 252, step: 8
3246 12:14:59.332325 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3247 12:14:59.336093 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3248 12:14:59.338948 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3249 12:14:59.342407 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3250 12:14:59.349100 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3251 12:14:59.352625 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3252 12:14:59.356016 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3253 12:14:59.359288 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3254 12:14:59.362615 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3255 12:14:59.369065 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3256 12:14:59.372543 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3257 12:14:59.375918 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3258 12:14:59.379422 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3259 12:14:59.382803 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3260 12:14:59.388836 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3261 12:14:59.392245 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3262 12:14:59.392376 ==
3263 12:14:59.395767 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 12:14:59.399148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 12:14:59.399266 ==
3266 12:14:59.402626 DQS Delay:
3267 12:14:59.402722 DQS0 = 0, DQS1 = 0
3268 12:14:59.402788 DQM Delay:
3269 12:14:59.406179 DQM0 = 119, DQM1 = 116
3270 12:14:59.406277 DQ Delay:
3271 12:14:59.409680 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3272 12:14:59.412403 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3273 12:14:59.415840 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3274 12:14:59.422951 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3275 12:14:59.423079
3276 12:14:59.423149
3277 12:14:59.423210 ==
3278 12:14:59.426201 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 12:14:59.429348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 12:14:59.429483 ==
3281 12:14:59.429554
3282 12:14:59.429616
3283 12:14:59.432577 TX Vref Scan disable
3284 12:14:59.432739 == TX Byte 0 ==
3285 12:14:59.439178 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3286 12:14:59.442419 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3287 12:14:59.442576 == TX Byte 1 ==
3288 12:14:59.449334 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3289 12:14:59.452800 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3290 12:14:59.452948 ==
3291 12:14:59.456139 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 12:14:59.459492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 12:14:59.459677 ==
3294 12:14:59.471308 TX Vref=22, minBit 1, minWin=24, winSum=409
3295 12:14:59.474722 TX Vref=24, minBit 1, minWin=25, winSum=416
3296 12:14:59.477998 TX Vref=26, minBit 11, minWin=25, winSum=423
3297 12:14:59.481393 TX Vref=28, minBit 1, minWin=26, winSum=427
3298 12:14:59.484866 TX Vref=30, minBit 2, minWin=26, winSum=429
3299 12:14:59.491725 TX Vref=32, minBit 9, minWin=25, winSum=433
3300 12:14:59.494846 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
3301 12:14:59.495002
3302 12:14:59.498292 Final TX Range 1 Vref 30
3303 12:14:59.498408
3304 12:14:59.498476 ==
3305 12:14:59.501699 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 12:14:59.505174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 12:14:59.505286 ==
3308 12:14:59.505355
3309 12:14:59.508567
3310 12:14:59.508658 TX Vref Scan disable
3311 12:14:59.511944 == TX Byte 0 ==
3312 12:14:59.515254 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3313 12:14:59.518740 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3314 12:14:59.522223 == TX Byte 1 ==
3315 12:14:59.524877 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3316 12:14:59.528768 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3317 12:14:59.528890
3318 12:14:59.599019 [DATLAT]
3319 12:14:59.599237 Freq=1200, CH1 RK0
3320 12:14:59.599353
3321 12:14:59.599450 DATLAT Default: 0xd
3322 12:14:59.599561 0, 0xFFFF, sum = 0
3323 12:14:59.599671 1, 0xFFFF, sum = 0
3324 12:14:59.599765 2, 0xFFFF, sum = 0
3325 12:14:59.599856 3, 0xFFFF, sum = 0
3326 12:14:59.599980 4, 0xFFFF, sum = 0
3327 12:14:59.600075 5, 0xFFFF, sum = 0
3328 12:14:59.600167 6, 0xFFFF, sum = 0
3329 12:14:59.600291 7, 0xFFFF, sum = 0
3330 12:14:59.600385 8, 0xFFFF, sum = 0
3331 12:14:59.600480 9, 0xFFFF, sum = 0
3332 12:14:59.600597 10, 0xFFFF, sum = 0
3333 12:14:59.600688 11, 0xFFFF, sum = 0
3334 12:14:59.600783 12, 0x0, sum = 1
3335 12:14:59.600900 13, 0x0, sum = 2
3336 12:14:59.600998 14, 0x0, sum = 3
3337 12:14:59.601092 15, 0x0, sum = 4
3338 12:14:59.601215 best_step = 13
3339 12:14:59.601306
3340 12:14:59.601401 ==
3341 12:14:59.601513 Dram Type= 6, Freq= 0, CH_1, rank 0
3342 12:14:59.601603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3343 12:14:59.601709 ==
3344 12:14:59.601816 RX Vref Scan: 1
3345 12:14:59.601904
3346 12:14:59.601994 Set Vref Range= 32 -> 127
3347 12:14:59.602112
3348 12:14:59.602202 RX Vref 32 -> 127, step: 1
3349 12:14:59.602300
3350 12:14:59.602405 RX Delay -5 -> 252, step: 4
3351 12:14:59.602495
3352 12:14:59.602590 Set Vref, RX VrefLevel [Byte0]: 32
3353 12:14:59.602698 [Byte1]: 32
3354 12:14:59.602785
3355 12:14:59.602871 Set Vref, RX VrefLevel [Byte0]: 33
3356 12:14:59.602992 [Byte1]: 33
3357 12:14:59.603083
3358 12:14:59.603171 Set Vref, RX VrefLevel [Byte0]: 34
3359 12:14:59.603479 [Byte1]: 34
3360 12:14:59.605273
3361 12:14:59.605409 Set Vref, RX VrefLevel [Byte0]: 35
3362 12:14:59.608725 [Byte1]: 35
3363 12:14:59.613386
3364 12:14:59.613554 Set Vref, RX VrefLevel [Byte0]: 36
3365 12:14:59.616832 [Byte1]: 36
3366 12:14:59.621081
3367 12:14:59.621232 Set Vref, RX VrefLevel [Byte0]: 37
3368 12:14:59.624566 [Byte1]: 37
3369 12:14:59.629385
3370 12:14:59.629540 Set Vref, RX VrefLevel [Byte0]: 38
3371 12:14:59.632109 [Byte1]: 38
3372 12:14:59.636836
3373 12:14:59.636995 Set Vref, RX VrefLevel [Byte0]: 39
3374 12:14:59.640147 [Byte1]: 39
3375 12:14:59.644796
3376 12:14:59.644955 Set Vref, RX VrefLevel [Byte0]: 40
3377 12:14:59.648103 [Byte1]: 40
3378 12:14:59.652618
3379 12:14:59.652760 Set Vref, RX VrefLevel [Byte0]: 41
3380 12:14:59.655871 [Byte1]: 41
3381 12:14:59.660583
3382 12:14:59.660688 Set Vref, RX VrefLevel [Byte0]: 42
3383 12:14:59.666801 [Byte1]: 42
3384 12:14:59.666942
3385 12:14:59.670240 Set Vref, RX VrefLevel [Byte0]: 43
3386 12:14:59.673639 [Byte1]: 43
3387 12:14:59.673765
3388 12:14:59.676996 Set Vref, RX VrefLevel [Byte0]: 44
3389 12:14:59.680286 [Byte1]: 44
3390 12:14:59.684161
3391 12:14:59.684298 Set Vref, RX VrefLevel [Byte0]: 45
3392 12:14:59.687455 [Byte1]: 45
3393 12:14:59.692109
3394 12:14:59.692226 Set Vref, RX VrefLevel [Byte0]: 46
3395 12:14:59.695438 [Byte1]: 46
3396 12:14:59.699676
3397 12:14:59.699783 Set Vref, RX VrefLevel [Byte0]: 47
3398 12:14:59.702981 [Byte1]: 47
3399 12:14:59.707264
3400 12:14:59.707375 Set Vref, RX VrefLevel [Byte0]: 48
3401 12:14:59.711126 [Byte1]: 48
3402 12:14:59.715242
3403 12:14:59.715392 Set Vref, RX VrefLevel [Byte0]: 49
3404 12:14:59.718774 [Byte1]: 49
3405 12:14:59.723522
3406 12:14:59.723630 Set Vref, RX VrefLevel [Byte0]: 50
3407 12:14:59.726938 [Byte1]: 50
3408 12:14:59.731064
3409 12:14:59.731180 Set Vref, RX VrefLevel [Byte0]: 51
3410 12:14:59.734418 [Byte1]: 51
3411 12:14:59.739192
3412 12:14:59.739313 Set Vref, RX VrefLevel [Byte0]: 52
3413 12:14:59.742687 [Byte1]: 52
3414 12:14:59.747032
3415 12:14:59.747164 Set Vref, RX VrefLevel [Byte0]: 53
3416 12:14:59.750236 [Byte1]: 53
3417 12:14:59.754917
3418 12:14:59.755048 Set Vref, RX VrefLevel [Byte0]: 54
3419 12:14:59.758147 [Byte1]: 54
3420 12:14:59.762807
3421 12:14:59.762942 Set Vref, RX VrefLevel [Byte0]: 55
3422 12:14:59.766126 [Byte1]: 55
3423 12:14:59.770280
3424 12:14:59.770410 Set Vref, RX VrefLevel [Byte0]: 56
3425 12:14:59.773740 [Byte1]: 56
3426 12:14:59.778574
3427 12:14:59.778701 Set Vref, RX VrefLevel [Byte0]: 57
3428 12:14:59.781139 [Byte1]: 57
3429 12:14:59.785850
3430 12:14:59.785962 Set Vref, RX VrefLevel [Byte0]: 58
3431 12:14:59.789205 [Byte1]: 58
3432 12:14:59.793681
3433 12:14:59.793835 Set Vref, RX VrefLevel [Byte0]: 59
3434 12:14:59.797509 [Byte1]: 59
3435 12:14:59.801476
3436 12:14:59.801585 Set Vref, RX VrefLevel [Byte0]: 60
3437 12:14:59.804857 [Byte1]: 60
3438 12:14:59.809572
3439 12:14:59.809675 Set Vref, RX VrefLevel [Byte0]: 61
3440 12:14:59.812942 [Byte1]: 61
3441 12:14:59.817509
3442 12:14:59.817615 Set Vref, RX VrefLevel [Byte0]: 62
3443 12:14:59.820886 [Byte1]: 62
3444 12:14:59.825659
3445 12:14:59.825760 Set Vref, RX VrefLevel [Byte0]: 63
3446 12:14:59.829072 [Byte1]: 63
3447 12:14:59.833029
3448 12:14:59.833128 Set Vref, RX VrefLevel [Byte0]: 64
3449 12:14:59.836538 [Byte1]: 64
3450 12:14:59.841195
3451 12:14:59.841295 Set Vref, RX VrefLevel [Byte0]: 65
3452 12:14:59.844658 [Byte1]: 65
3453 12:14:59.848783
3454 12:14:59.848887 Set Vref, RX VrefLevel [Byte0]: 66
3455 12:14:59.852040 [Byte1]: 66
3456 12:14:59.856490
3457 12:14:59.856592 Set Vref, RX VrefLevel [Byte0]: 67
3458 12:14:59.859803 [Byte1]: 67
3459 12:14:59.864428
3460 12:14:59.864531 Final RX Vref Byte 0 = 54 to rank0
3461 12:14:59.867785 Final RX Vref Byte 1 = 48 to rank0
3462 12:14:59.871724 Final RX Vref Byte 0 = 54 to rank1
3463 12:14:59.874441 Final RX Vref Byte 1 = 48 to rank1==
3464 12:14:59.877873 Dram Type= 6, Freq= 0, CH_1, rank 0
3465 12:14:59.884730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 12:14:59.884848 ==
3467 12:14:59.884917 DQS Delay:
3468 12:14:59.884979 DQS0 = 0, DQS1 = 0
3469 12:14:59.888193 DQM Delay:
3470 12:14:59.888288 DQM0 = 120, DQM1 = 116
3471 12:14:59.890970 DQ Delay:
3472 12:14:59.894381 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3473 12:14:59.897905 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3474 12:14:59.901222 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3475 12:14:59.904897 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3476 12:14:59.904994
3477 12:14:59.905062
3478 12:14:59.911656 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3479 12:14:59.914993 CH1 RK0: MR19=304, MR18=FE11
3480 12:14:59.921708 CH1_RK0: MR19=0x304, MR18=0xFE11, DQSOSC=403, MR23=63, INC=40, DEC=26
3481 12:14:59.921862
3482 12:14:59.925035 ----->DramcWriteLeveling(PI) begin...
3483 12:14:59.925145 ==
3484 12:14:59.928334 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 12:14:59.931765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 12:14:59.931863 ==
3487 12:14:59.935097 Write leveling (Byte 0): 26 => 26
3488 12:14:59.938600 Write leveling (Byte 1): 28 => 28
3489 12:14:59.941914 DramcWriteLeveling(PI) end<-----
3490 12:14:59.942004
3491 12:14:59.942066 ==
3492 12:14:59.945289 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 12:14:59.948025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 12:14:59.951485 ==
3495 12:14:59.951583 [Gating] SW mode calibration
3496 12:14:59.961640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3497 12:14:59.964793 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3498 12:14:59.968059 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 12:14:59.975279 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 12:14:59.978621 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 12:14:59.981355 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 12:14:59.988144 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 12:14:59.991383 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3504 12:14:59.994860 0 15 24 | B1->B0 | 2929 3434 | 0 0 | (1 0) (0 1)
3505 12:15:00.001767 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3506 12:15:00.005131 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 12:15:00.008399 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 12:15:00.014740 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 12:15:00.018666 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 12:15:00.022019 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 12:15:00.024923 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3512 12:15:00.032191 1 0 24 | B1->B0 | 4444 2a2a | 1 1 | (0 0) (0 0)
3513 12:15:00.035515 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3514 12:15:00.038862 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 12:15:00.044970 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 12:15:00.048375 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 12:15:00.051825 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 12:15:00.058722 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 12:15:00.061602 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 12:15:00.065502 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3521 12:15:00.071561 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3522 12:15:00.075489 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 12:15:00.078479 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 12:15:00.085201 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 12:15:00.088668 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 12:15:00.091491 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 12:15:00.098257 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 12:15:00.101597 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 12:15:00.105045 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 12:15:00.111859 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 12:15:00.115225 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 12:15:00.118453 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 12:15:00.124795 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 12:15:00.128181 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 12:15:00.131630 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3536 12:15:00.135053 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3537 12:15:00.141695 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3538 12:15:00.145067 Total UI for P1: 0, mck2ui 16
3539 12:15:00.148483 best dqsien dly found for B1: ( 1, 3, 22)
3540 12:15:00.151267 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 12:15:00.154494 Total UI for P1: 0, mck2ui 16
3542 12:15:00.157963 best dqsien dly found for B0: ( 1, 3, 26)
3543 12:15:00.161395 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3544 12:15:00.164947 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3545 12:15:00.165047
3546 12:15:00.168386 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3547 12:15:00.171179 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3548 12:15:00.174621 [Gating] SW calibration Done
3549 12:15:00.174715 ==
3550 12:15:00.177997 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 12:15:00.184616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 12:15:00.184746 ==
3553 12:15:00.184818 RX Vref Scan: 0
3554 12:15:00.184882
3555 12:15:00.188244 RX Vref 0 -> 0, step: 1
3556 12:15:00.188342
3557 12:15:00.191517 RX Delay -40 -> 252, step: 8
3558 12:15:00.194782 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3559 12:15:00.197551 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3560 12:15:00.201006 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3561 12:15:00.207889 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3562 12:15:00.211343 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3563 12:15:00.214814 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3564 12:15:00.217668 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3565 12:15:00.221091 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3566 12:15:00.224475 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3567 12:15:00.230923 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3568 12:15:00.234761 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3569 12:15:00.237659 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3570 12:15:00.241122 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3571 12:15:00.247883 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3572 12:15:00.251152 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3573 12:15:00.254556 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3574 12:15:00.254664 ==
3575 12:15:00.257932 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 12:15:00.260761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 12:15:00.260858 ==
3578 12:15:00.264170 DQS Delay:
3579 12:15:00.264281 DQS0 = 0, DQS1 = 0
3580 12:15:00.267614 DQM Delay:
3581 12:15:00.267702 DQM0 = 121, DQM1 = 119
3582 12:15:00.267768 DQ Delay:
3583 12:15:00.274339 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3584 12:15:00.277797 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3585 12:15:00.280552 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3586 12:15:00.283890 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3587 12:15:00.283992
3588 12:15:00.284057
3589 12:15:00.284146 ==
3590 12:15:00.287181 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 12:15:00.291064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 12:15:00.291194 ==
3593 12:15:00.291290
3594 12:15:00.291424
3595 12:15:00.294382 TX Vref Scan disable
3596 12:15:00.297564 == TX Byte 0 ==
3597 12:15:00.300936 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3598 12:15:00.304205 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3599 12:15:00.307295 == TX Byte 1 ==
3600 12:15:00.310680 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3601 12:15:00.314160 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3602 12:15:00.314258 ==
3603 12:15:00.317550 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 12:15:00.320972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 12:15:00.323695 ==
3606 12:15:00.333669 TX Vref=22, minBit 9, minWin=25, winSum=418
3607 12:15:00.337381 TX Vref=24, minBit 1, minWin=26, winSum=424
3608 12:15:00.340783 TX Vref=26, minBit 8, minWin=26, winSum=428
3609 12:15:00.344070 TX Vref=28, minBit 10, minWin=25, winSum=431
3610 12:15:00.347464 TX Vref=30, minBit 9, minWin=26, winSum=435
3611 12:15:00.353616 TX Vref=32, minBit 9, minWin=26, winSum=438
3612 12:15:00.356999 [TxChooseVref] Worse bit 9, Min win 26, Win sum 438, Final Vref 32
3613 12:15:00.357105
3614 12:15:00.360175 Final TX Range 1 Vref 32
3615 12:15:00.360270
3616 12:15:00.360336 ==
3617 12:15:00.363777 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 12:15:00.367270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 12:15:00.367419 ==
3620 12:15:00.370116
3621 12:15:00.370202
3622 12:15:00.370271 TX Vref Scan disable
3623 12:15:00.373541 == TX Byte 0 ==
3624 12:15:00.376997 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3625 12:15:00.380412 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3626 12:15:00.383896 == TX Byte 1 ==
3627 12:15:00.387378 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3628 12:15:00.390673 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3629 12:15:00.394025
3630 12:15:00.394127 [DATLAT]
3631 12:15:00.394196 Freq=1200, CH1 RK1
3632 12:15:00.394258
3633 12:15:00.397300 DATLAT Default: 0xd
3634 12:15:00.397388 0, 0xFFFF, sum = 0
3635 12:15:00.400595 1, 0xFFFF, sum = 0
3636 12:15:00.400685 2, 0xFFFF, sum = 0
3637 12:15:00.403936 3, 0xFFFF, sum = 0
3638 12:15:00.407077 4, 0xFFFF, sum = 0
3639 12:15:00.407168 5, 0xFFFF, sum = 0
3640 12:15:00.410403 6, 0xFFFF, sum = 0
3641 12:15:00.410493 7, 0xFFFF, sum = 0
3642 12:15:00.413783 8, 0xFFFF, sum = 0
3643 12:15:00.413888 9, 0xFFFF, sum = 0
3644 12:15:00.417012 10, 0xFFFF, sum = 0
3645 12:15:00.417100 11, 0xFFFF, sum = 0
3646 12:15:00.420353 12, 0x0, sum = 1
3647 12:15:00.420441 13, 0x0, sum = 2
3648 12:15:00.423863 14, 0x0, sum = 3
3649 12:15:00.423950 15, 0x0, sum = 4
3650 12:15:00.426527 best_step = 13
3651 12:15:00.426612
3652 12:15:00.426677 ==
3653 12:15:00.430034 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 12:15:00.433331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 12:15:00.433430 ==
3656 12:15:00.433498 RX Vref Scan: 0
3657 12:15:00.433560
3658 12:15:00.436718 RX Vref 0 -> 0, step: 1
3659 12:15:00.436808
3660 12:15:00.439978 RX Delay -5 -> 252, step: 4
3661 12:15:00.443209 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3662 12:15:00.449744 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3663 12:15:00.453084 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3664 12:15:00.456496 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3665 12:15:00.459971 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3666 12:15:00.463388 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3667 12:15:00.469883 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3668 12:15:00.473211 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3669 12:15:00.476665 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3670 12:15:00.479515 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3671 12:15:00.482771 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3672 12:15:00.489570 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3673 12:15:00.493063 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3674 12:15:00.496281 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3675 12:15:00.499645 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3676 12:15:00.503074 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3677 12:15:00.506404 ==
3678 12:15:00.509704 Dram Type= 6, Freq= 0, CH_1, rank 1
3679 12:15:00.513568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3680 12:15:00.513674 ==
3681 12:15:00.513747 DQS Delay:
3682 12:15:00.516807 DQS0 = 0, DQS1 = 0
3683 12:15:00.516901 DQM Delay:
3684 12:15:00.519893 DQM0 = 120, DQM1 = 116
3685 12:15:00.519970 DQ Delay:
3686 12:15:00.523027 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3687 12:15:00.526359 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3688 12:15:00.529730 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3689 12:15:00.533283 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3690 12:15:00.533378
3691 12:15:00.533447
3692 12:15:00.542784 [DQSOSCAuto] RK1, (LSB)MR18= 0xeec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3693 12:15:00.546149 CH1 RK1: MR19=403, MR18=EEC
3694 12:15:00.549483 CH1_RK1: MR19=0x403, MR18=0xEEC, DQSOSC=404, MR23=63, INC=40, DEC=26
3695 12:15:00.552712 [RxdqsGatingPostProcess] freq 1200
3696 12:15:00.560070 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3697 12:15:00.562362 best DQS0 dly(2T, 0.5T) = (0, 11)
3698 12:15:00.565953 best DQS1 dly(2T, 0.5T) = (0, 11)
3699 12:15:00.569450 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3700 12:15:00.572831 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3701 12:15:00.576068 best DQS0 dly(2T, 0.5T) = (0, 11)
3702 12:15:00.579424 best DQS1 dly(2T, 0.5T) = (0, 11)
3703 12:15:00.582875 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3704 12:15:00.586354 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3705 12:15:00.586489 Pre-setting of DQS Precalculation
3706 12:15:00.592596 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3707 12:15:00.599285 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3708 12:15:00.605969 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3709 12:15:00.606094
3710 12:15:00.606164
3711 12:15:00.609317 [Calibration Summary] 2400 Mbps
3712 12:15:00.612813 CH 0, Rank 0
3713 12:15:00.612940 SW Impedance : PASS
3714 12:15:00.616241 DUTY Scan : NO K
3715 12:15:00.618973 ZQ Calibration : PASS
3716 12:15:00.619064 Jitter Meter : NO K
3717 12:15:00.622880 CBT Training : PASS
3718 12:15:00.626079 Write leveling : PASS
3719 12:15:00.626222 RX DQS gating : PASS
3720 12:15:00.629443 RX DQ/DQS(RDDQC) : PASS
3721 12:15:00.632667 TX DQ/DQS : PASS
3722 12:15:00.632792 RX DATLAT : PASS
3723 12:15:00.636075 RX DQ/DQS(Engine): PASS
3724 12:15:00.636181 TX OE : NO K
3725 12:15:00.639470 All Pass.
3726 12:15:00.639582
3727 12:15:00.639681 CH 0, Rank 1
3728 12:15:00.642243 SW Impedance : PASS
3729 12:15:00.642355 DUTY Scan : NO K
3730 12:15:00.645732 ZQ Calibration : PASS
3731 12:15:00.649186 Jitter Meter : NO K
3732 12:15:00.649304 CBT Training : PASS
3733 12:15:00.652641 Write leveling : PASS
3734 12:15:00.656018 RX DQS gating : PASS
3735 12:15:00.656113 RX DQ/DQS(RDDQC) : PASS
3736 12:15:00.659371 TX DQ/DQS : PASS
3737 12:15:00.662721 RX DATLAT : PASS
3738 12:15:00.662814 RX DQ/DQS(Engine): PASS
3739 12:15:00.665872 TX OE : NO K
3740 12:15:00.665962 All Pass.
3741 12:15:00.666030
3742 12:15:00.668994 CH 1, Rank 0
3743 12:15:00.669081 SW Impedance : PASS
3744 12:15:00.672593 DUTY Scan : NO K
3745 12:15:00.675873 ZQ Calibration : PASS
3746 12:15:00.675986 Jitter Meter : NO K
3747 12:15:00.679196 CBT Training : PASS
3748 12:15:00.682492 Write leveling : PASS
3749 12:15:00.682580 RX DQS gating : PASS
3750 12:15:00.685843 RX DQ/DQS(RDDQC) : PASS
3751 12:15:00.685931 TX DQ/DQS : PASS
3752 12:15:00.689228 RX DATLAT : PASS
3753 12:15:00.692612 RX DQ/DQS(Engine): PASS
3754 12:15:00.692718 TX OE : NO K
3755 12:15:00.696075 All Pass.
3756 12:15:00.696175
3757 12:15:00.696244 CH 1, Rank 1
3758 12:15:00.698873 SW Impedance : PASS
3759 12:15:00.698960 DUTY Scan : NO K
3760 12:15:00.702205 ZQ Calibration : PASS
3761 12:15:00.705585 Jitter Meter : NO K
3762 12:15:00.705677 CBT Training : PASS
3763 12:15:00.708837 Write leveling : PASS
3764 12:15:00.712184 RX DQS gating : PASS
3765 12:15:00.712287 RX DQ/DQS(RDDQC) : PASS
3766 12:15:00.715631 TX DQ/DQS : PASS
3767 12:15:00.718967 RX DATLAT : PASS
3768 12:15:00.719083 RX DQ/DQS(Engine): PASS
3769 12:15:00.722408 TX OE : NO K
3770 12:15:00.722499 All Pass.
3771 12:15:00.722562
3772 12:15:00.725263 DramC Write-DBI off
3773 12:15:00.728524 PER_BANK_REFRESH: Hybrid Mode
3774 12:15:00.728617 TX_TRACKING: ON
3775 12:15:00.738887 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3776 12:15:00.742193 [FAST_K] Save calibration result to emmc
3777 12:15:00.745723 dramc_set_vcore_voltage set vcore to 650000
3778 12:15:00.748441 Read voltage for 600, 5
3779 12:15:00.748535 Vio18 = 0
3780 12:15:00.748601 Vcore = 650000
3781 12:15:00.751871 Vdram = 0
3782 12:15:00.751957 Vddq = 0
3783 12:15:00.752023 Vmddr = 0
3784 12:15:00.758615 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3785 12:15:00.762119 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3786 12:15:00.765567 MEM_TYPE=3, freq_sel=19
3787 12:15:00.768806 sv_algorithm_assistance_LP4_1600
3788 12:15:00.771976 ============ PULL DRAM RESETB DOWN ============
3789 12:15:00.775404 ========== PULL DRAM RESETB DOWN end =========
3790 12:15:00.781948 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3791 12:15:00.785214 ===================================
3792 12:15:00.785319 LPDDR4 DRAM CONFIGURATION
3793 12:15:00.788497 ===================================
3794 12:15:00.791727 EX_ROW_EN[0] = 0x0
3795 12:15:00.795192 EX_ROW_EN[1] = 0x0
3796 12:15:00.795294 LP4Y_EN = 0x0
3797 12:15:00.798692 WORK_FSP = 0x0
3798 12:15:00.798789 WL = 0x2
3799 12:15:00.802077 RL = 0x2
3800 12:15:00.802164 BL = 0x2
3801 12:15:00.804872 RPST = 0x0
3802 12:15:00.804957 RD_PRE = 0x0
3803 12:15:00.808222 WR_PRE = 0x1
3804 12:15:00.808308 WR_PST = 0x0
3805 12:15:00.812115 DBI_WR = 0x0
3806 12:15:00.812199 DBI_RD = 0x0
3807 12:15:00.814877 OTF = 0x1
3808 12:15:00.818316 ===================================
3809 12:15:00.821674 ===================================
3810 12:15:00.821764 ANA top config
3811 12:15:00.825079 ===================================
3812 12:15:00.828407 DLL_ASYNC_EN = 0
3813 12:15:00.831838 ALL_SLAVE_EN = 1
3814 12:15:00.834609 NEW_RANK_MODE = 1
3815 12:15:00.834717 DLL_IDLE_MODE = 1
3816 12:15:00.838372 LP45_APHY_COMB_EN = 1
3817 12:15:00.841556 TX_ODT_DIS = 1
3818 12:15:00.844811 NEW_8X_MODE = 1
3819 12:15:00.847967 ===================================
3820 12:15:00.851297 ===================================
3821 12:15:00.854781 data_rate = 1200
3822 12:15:00.854870 CKR = 1
3823 12:15:00.858160 DQ_P2S_RATIO = 8
3824 12:15:00.861596 ===================================
3825 12:15:00.864405 CA_P2S_RATIO = 8
3826 12:15:00.867835 DQ_CA_OPEN = 0
3827 12:15:00.871159 DQ_SEMI_OPEN = 0
3828 12:15:00.874419 CA_SEMI_OPEN = 0
3829 12:15:00.874533 CA_FULL_RATE = 0
3830 12:15:00.877669 DQ_CKDIV4_EN = 1
3831 12:15:00.881057 CA_CKDIV4_EN = 1
3832 12:15:00.884477 CA_PREDIV_EN = 0
3833 12:15:00.887968 PH8_DLY = 0
3834 12:15:00.891162 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3835 12:15:00.891338 DQ_AAMCK_DIV = 4
3836 12:15:00.894581 CA_AAMCK_DIV = 4
3837 12:15:00.897805 CA_ADMCK_DIV = 4
3838 12:15:00.901708 DQ_TRACK_CA_EN = 0
3839 12:15:00.904454 CA_PICK = 600
3840 12:15:00.907970 CA_MCKIO = 600
3841 12:15:00.908083 MCKIO_SEMI = 0
3842 12:15:00.911296 PLL_FREQ = 2288
3843 12:15:00.914735 DQ_UI_PI_RATIO = 32
3844 12:15:00.917847 CA_UI_PI_RATIO = 0
3845 12:15:00.921447 ===================================
3846 12:15:00.924861 ===================================
3847 12:15:00.928221 memory_type:LPDDR4
3848 12:15:00.928328 GP_NUM : 10
3849 12:15:00.931681 SRAM_EN : 1
3850 12:15:00.934354 MD32_EN : 0
3851 12:15:00.937852 ===================================
3852 12:15:00.937955 [ANA_INIT] >>>>>>>>>>>>>>
3853 12:15:00.941268 <<<<<< [CONFIGURE PHASE]: ANA_TX
3854 12:15:00.944634 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3855 12:15:00.947805 ===================================
3856 12:15:00.951133 data_rate = 1200,PCW = 0X5800
3857 12:15:00.954572 ===================================
3858 12:15:00.957968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3859 12:15:00.964926 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 12:15:00.967767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3861 12:15:00.974710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3862 12:15:00.978002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3863 12:15:00.981534 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3864 12:15:00.981666 [ANA_INIT] flow start
3865 12:15:00.984140 [ANA_INIT] PLL >>>>>>>>
3866 12:15:00.987607 [ANA_INIT] PLL <<<<<<<<
3867 12:15:00.987723 [ANA_INIT] MIDPI >>>>>>>>
3868 12:15:00.990893 [ANA_INIT] MIDPI <<<<<<<<
3869 12:15:00.994341 [ANA_INIT] DLL >>>>>>>>
3870 12:15:00.994450 [ANA_INIT] flow end
3871 12:15:01.000825 ============ LP4 DIFF to SE enter ============
3872 12:15:01.004100 ============ LP4 DIFF to SE exit ============
3873 12:15:01.007347 [ANA_INIT] <<<<<<<<<<<<<
3874 12:15:01.010752 [Flow] Enable top DCM control >>>>>
3875 12:15:01.014184 [Flow] Enable top DCM control <<<<<
3876 12:15:01.017621 Enable DLL master slave shuffle
3877 12:15:01.020877 ==============================================================
3878 12:15:01.024094 Gating Mode config
3879 12:15:01.027446 ==============================================================
3880 12:15:01.030896 Config description:
3881 12:15:01.041074 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3882 12:15:01.047315 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3883 12:15:01.050776 SELPH_MODE 0: By rank 1: By Phase
3884 12:15:01.057223 ==============================================================
3885 12:15:01.060537 GAT_TRACK_EN = 1
3886 12:15:01.063721 RX_GATING_MODE = 2
3887 12:15:01.067297 RX_GATING_TRACK_MODE = 2
3888 12:15:01.070557 SELPH_MODE = 1
3889 12:15:01.073905 PICG_EARLY_EN = 1
3890 12:15:01.074015 VALID_LAT_VALUE = 1
3891 12:15:01.080189 ==============================================================
3892 12:15:01.083544 Enter into Gating configuration >>>>
3893 12:15:01.086783 Exit from Gating configuration <<<<
3894 12:15:01.090114 Enter into DVFS_PRE_config >>>>>
3895 12:15:01.100276 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3896 12:15:01.103724 Exit from DVFS_PRE_config <<<<<
3897 12:15:01.106727 Enter into PICG configuration >>>>
3898 12:15:01.110678 Exit from PICG configuration <<<<
3899 12:15:01.113869 [RX_INPUT] configuration >>>>>
3900 12:15:01.117102 [RX_INPUT] configuration <<<<<
3901 12:15:01.123946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3902 12:15:01.127257 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3903 12:15:01.133852 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3904 12:15:01.140580 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3905 12:15:01.146732 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3906 12:15:01.153399 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3907 12:15:01.156879 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3908 12:15:01.160232 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3909 12:15:01.163574 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3910 12:15:01.170151 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3911 12:15:01.173553 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3912 12:15:01.176975 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3913 12:15:01.180376 ===================================
3914 12:15:01.183159 LPDDR4 DRAM CONFIGURATION
3915 12:15:01.186639 ===================================
3916 12:15:01.186814 EX_ROW_EN[0] = 0x0
3917 12:15:01.189941 EX_ROW_EN[1] = 0x0
3918 12:15:01.190086 LP4Y_EN = 0x0
3919 12:15:01.193251 WORK_FSP = 0x0
3920 12:15:01.196570 WL = 0x2
3921 12:15:01.196731 RL = 0x2
3922 12:15:01.199908 BL = 0x2
3923 12:15:01.200013 RPST = 0x0
3924 12:15:01.203180 RD_PRE = 0x0
3925 12:15:01.203303 WR_PRE = 0x1
3926 12:15:01.206657 WR_PST = 0x0
3927 12:15:01.206774 DBI_WR = 0x0
3928 12:15:01.209972 DBI_RD = 0x0
3929 12:15:01.210089 OTF = 0x1
3930 12:15:01.213178 ===================================
3931 12:15:01.216529 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3932 12:15:01.223052 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3933 12:15:01.226488 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3934 12:15:01.229860 ===================================
3935 12:15:01.233010 LPDDR4 DRAM CONFIGURATION
3936 12:15:01.236387 ===================================
3937 12:15:01.236567 EX_ROW_EN[0] = 0x10
3938 12:15:01.239670 EX_ROW_EN[1] = 0x0
3939 12:15:01.239805 LP4Y_EN = 0x0
3940 12:15:01.243047 WORK_FSP = 0x0
3941 12:15:01.243176 WL = 0x2
3942 12:15:01.246433 RL = 0x2
3943 12:15:01.246540 BL = 0x2
3944 12:15:01.249848 RPST = 0x0
3945 12:15:01.253163 RD_PRE = 0x0
3946 12:15:01.253256 WR_PRE = 0x1
3947 12:15:01.256701 WR_PST = 0x0
3948 12:15:01.256809 DBI_WR = 0x0
3949 12:15:01.259406 DBI_RD = 0x0
3950 12:15:01.259580 OTF = 0x1
3951 12:15:01.262863 ===================================
3952 12:15:01.269587 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3953 12:15:01.273417 nWR fixed to 30
3954 12:15:01.276780 [ModeRegInit_LP4] CH0 RK0
3955 12:15:01.276916 [ModeRegInit_LP4] CH0 RK1
3956 12:15:01.280080 [ModeRegInit_LP4] CH1 RK0
3957 12:15:01.283321 [ModeRegInit_LP4] CH1 RK1
3958 12:15:01.283478 match AC timing 17
3959 12:15:01.290281 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3960 12:15:01.293720 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3961 12:15:01.296388 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3962 12:15:01.303108 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3963 12:15:01.306546 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3964 12:15:01.306679 ==
3965 12:15:01.309918 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 12:15:01.313369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 12:15:01.313495 ==
3968 12:15:01.319950 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3969 12:15:01.326541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3970 12:15:01.329840 [CA 0] Center 35 (5~66) winsize 62
3971 12:15:01.333159 [CA 1] Center 35 (5~66) winsize 62
3972 12:15:01.336435 [CA 2] Center 33 (3~64) winsize 62
3973 12:15:01.339742 [CA 3] Center 33 (2~64) winsize 63
3974 12:15:01.343102 [CA 4] Center 33 (2~64) winsize 63
3975 12:15:01.346526 [CA 5] Center 32 (2~63) winsize 62
3976 12:15:01.346623
3977 12:15:01.350041 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3978 12:15:01.350132
3979 12:15:01.353527 [CATrainingPosCal] consider 1 rank data
3980 12:15:01.356887 u2DelayCellTimex100 = 270/100 ps
3981 12:15:01.359683 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3982 12:15:01.363057 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3983 12:15:01.366627 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3984 12:15:01.370060 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3985 12:15:01.372765 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3986 12:15:01.376811 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3987 12:15:01.376920
3988 12:15:01.383263 CA PerBit enable=1, Macro0, CA PI delay=32
3989 12:15:01.383438
3990 12:15:01.386339 [CBTSetCACLKResult] CA Dly = 32
3991 12:15:01.386472 CS Dly: 4 (0~35)
3992 12:15:01.386574 ==
3993 12:15:01.389726 Dram Type= 6, Freq= 0, CH_0, rank 1
3994 12:15:01.393188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 12:15:01.393290 ==
3996 12:15:01.399817 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3997 12:15:01.406340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3998 12:15:01.409811 [CA 0] Center 36 (5~67) winsize 63
3999 12:15:01.413092 [CA 1] Center 35 (5~66) winsize 62
4000 12:15:01.416526 [CA 2] Center 34 (3~65) winsize 63
4001 12:15:01.419964 [CA 3] Center 34 (3~65) winsize 63
4002 12:15:01.423182 [CA 4] Center 33 (2~64) winsize 63
4003 12:15:01.426571 [CA 5] Center 32 (2~63) winsize 62
4004 12:15:01.426674
4005 12:15:01.429808 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4006 12:15:01.429929
4007 12:15:01.433177 [CATrainingPosCal] consider 2 rank data
4008 12:15:01.436309 u2DelayCellTimex100 = 270/100 ps
4009 12:15:01.439701 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4010 12:15:01.442842 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4011 12:15:01.446130 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4012 12:15:01.449422 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4013 12:15:01.452910 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4014 12:15:01.459721 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4015 12:15:01.459858
4016 12:15:01.463095 CA PerBit enable=1, Macro0, CA PI delay=32
4017 12:15:01.463195
4018 12:15:01.466370 [CBTSetCACLKResult] CA Dly = 32
4019 12:15:01.466465 CS Dly: 4 (0~36)
4020 12:15:01.466534
4021 12:15:01.469768 ----->DramcWriteLeveling(PI) begin...
4022 12:15:01.469870 ==
4023 12:15:01.473193 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 12:15:01.476566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 12:15:01.479295 ==
4026 12:15:01.479407 Write leveling (Byte 0): 34 => 34
4027 12:15:01.482845 Write leveling (Byte 1): 31 => 31
4028 12:15:01.486261 DramcWriteLeveling(PI) end<-----
4029 12:15:01.486363
4030 12:15:01.486433 ==
4031 12:15:01.489607 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 12:15:01.496131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 12:15:01.496271 ==
4034 12:15:01.499389 [Gating] SW mode calibration
4035 12:15:01.506248 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4036 12:15:01.509513 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4037 12:15:01.512947 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 12:15:01.519857 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 12:15:01.523186 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 12:15:01.526528 0 9 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
4041 12:15:01.532616 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
4042 12:15:01.536341 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 12:15:01.539664 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 12:15:01.546147 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 12:15:01.549451 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 12:15:01.552619 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 12:15:01.559144 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4048 12:15:01.562539 0 10 12 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
4049 12:15:01.565832 0 10 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
4050 12:15:01.572719 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 12:15:01.576127 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 12:15:01.578845 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 12:15:01.585679 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 12:15:01.588966 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 12:15:01.592391 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4056 12:15:01.599153 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4057 12:15:01.602353 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4058 12:15:01.606048 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 12:15:01.612407 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 12:15:01.615688 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 12:15:01.618896 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 12:15:01.625756 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 12:15:01.629162 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 12:15:01.632603 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 12:15:01.638845 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 12:15:01.642018 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 12:15:01.645542 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:15:01.652573 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:15:01.655928 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:15:01.659034 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 12:15:01.662293 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:15:01.669021 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4073 12:15:01.672516 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4074 12:15:01.675213 Total UI for P1: 0, mck2ui 16
4075 12:15:01.678561 best dqsien dly found for B0: ( 0, 13, 12)
4076 12:15:01.682067 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 12:15:01.685420 Total UI for P1: 0, mck2ui 16
4078 12:15:01.688826 best dqsien dly found for B1: ( 0, 13, 18)
4079 12:15:01.692213 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4080 12:15:01.698770 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4081 12:15:01.698891
4082 12:15:01.702210 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4083 12:15:01.705728 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4084 12:15:01.708991 [Gating] SW calibration Done
4085 12:15:01.709101 ==
4086 12:15:01.712302 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 12:15:01.715284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 12:15:01.715400 ==
4089 12:15:01.715489 RX Vref Scan: 0
4090 12:15:01.718361
4091 12:15:01.718472 RX Vref 0 -> 0, step: 1
4092 12:15:01.718557
4093 12:15:01.721576 RX Delay -230 -> 252, step: 16
4094 12:15:01.725424 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4095 12:15:01.732248 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4096 12:15:01.735044 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4097 12:15:01.738424 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4098 12:15:01.741923 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4099 12:15:01.745390 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4100 12:15:01.751870 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4101 12:15:01.755157 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4102 12:15:01.758370 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4103 12:15:01.761650 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4104 12:15:01.768824 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4105 12:15:01.772056 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4106 12:15:01.775506 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4107 12:15:01.778838 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4108 12:15:01.781631 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4109 12:15:01.788537 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4110 12:15:01.788673 ==
4111 12:15:01.791849 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 12:15:01.795188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 12:15:01.795321 ==
4114 12:15:01.795406 DQS Delay:
4115 12:15:01.798574 DQS0 = 0, DQS1 = 0
4116 12:15:01.798668 DQM Delay:
4117 12:15:01.801890 DQM0 = 51, DQM1 = 44
4118 12:15:01.801985 DQ Delay:
4119 12:15:01.805237 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4120 12:15:01.808712 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4121 12:15:01.812120 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4122 12:15:01.814905 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4123 12:15:01.815003
4124 12:15:01.815075
4125 12:15:01.815137 ==
4126 12:15:01.818226 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 12:15:01.821633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 12:15:01.825531 ==
4129 12:15:01.825674
4130 12:15:01.825783
4131 12:15:01.825878 TX Vref Scan disable
4132 12:15:01.828776 == TX Byte 0 ==
4133 12:15:01.831930 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4134 12:15:01.835156 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4135 12:15:01.838580 == TX Byte 1 ==
4136 12:15:01.841883 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4137 12:15:01.844666 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4138 12:15:01.848100 ==
4139 12:15:01.851593 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 12:15:01.854782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 12:15:01.854881 ==
4142 12:15:01.854951
4143 12:15:01.855013
4144 12:15:01.857981 TX Vref Scan disable
4145 12:15:01.861397 == TX Byte 0 ==
4146 12:15:01.864743 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4147 12:15:01.867778 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4148 12:15:01.871344 == TX Byte 1 ==
4149 12:15:01.874887 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4150 12:15:01.877981 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4151 12:15:01.878095
4152 12:15:01.878163 [DATLAT]
4153 12:15:01.881263 Freq=600, CH0 RK0
4154 12:15:01.881371
4155 12:15:01.881471 DATLAT Default: 0x9
4156 12:15:01.884584 0, 0xFFFF, sum = 0
4157 12:15:01.887905 1, 0xFFFF, sum = 0
4158 12:15:01.888008 2, 0xFFFF, sum = 0
4159 12:15:01.891167 3, 0xFFFF, sum = 0
4160 12:15:01.891297 4, 0xFFFF, sum = 0
4161 12:15:01.894574 5, 0xFFFF, sum = 0
4162 12:15:01.894679 6, 0xFFFF, sum = 0
4163 12:15:01.898106 7, 0xFFFF, sum = 0
4164 12:15:01.898205 8, 0x0, sum = 1
4165 12:15:01.900800 9, 0x0, sum = 2
4166 12:15:01.900894 10, 0x0, sum = 3
4167 12:15:01.900965 11, 0x0, sum = 4
4168 12:15:01.904242 best_step = 9
4169 12:15:01.904331
4170 12:15:01.904398 ==
4171 12:15:01.907701 Dram Type= 6, Freq= 0, CH_0, rank 0
4172 12:15:01.911211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 12:15:01.911354 ==
4174 12:15:01.914745 RX Vref Scan: 1
4175 12:15:01.914838
4176 12:15:01.914906 RX Vref 0 -> 0, step: 1
4177 12:15:01.917427
4178 12:15:01.917515 RX Delay -179 -> 252, step: 8
4179 12:15:01.917584
4180 12:15:01.920954 Set Vref, RX VrefLevel [Byte0]: 56
4181 12:15:01.924195 [Byte1]: 49
4182 12:15:01.929043
4183 12:15:01.929158 Final RX Vref Byte 0 = 56 to rank0
4184 12:15:01.931727 Final RX Vref Byte 1 = 49 to rank0
4185 12:15:01.935109 Final RX Vref Byte 0 = 56 to rank1
4186 12:15:01.938383 Final RX Vref Byte 1 = 49 to rank1==
4187 12:15:01.941676 Dram Type= 6, Freq= 0, CH_0, rank 0
4188 12:15:01.948340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 12:15:01.948465 ==
4190 12:15:01.948536 DQS Delay:
4191 12:15:01.948598 DQS0 = 0, DQS1 = 0
4192 12:15:01.951754 DQM Delay:
4193 12:15:01.951845 DQM0 = 53, DQM1 = 47
4194 12:15:01.955187 DQ Delay:
4195 12:15:01.958634 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4196 12:15:01.961945 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4197 12:15:01.962050 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4198 12:15:01.968383 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4199 12:15:01.968508
4200 12:15:01.968576
4201 12:15:01.975206 [DQSOSCAuto] RK0, (LSB)MR18= 0x7467, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4202 12:15:01.978491 CH0 RK0: MR19=808, MR18=7467
4203 12:15:01.985013 CH0_RK0: MR19=0x808, MR18=0x7467, DQSOSC=388, MR23=63, INC=174, DEC=116
4204 12:15:01.985137
4205 12:15:01.988731 ----->DramcWriteLeveling(PI) begin...
4206 12:15:01.988857 ==
4207 12:15:01.991965 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 12:15:01.995317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 12:15:01.995439 ==
4210 12:15:01.998093 Write leveling (Byte 0): 34 => 34
4211 12:15:02.002136 Write leveling (Byte 1): 33 => 33
4212 12:15:02.004844 DramcWriteLeveling(PI) end<-----
4213 12:15:02.004942
4214 12:15:02.005009 ==
4215 12:15:02.008344 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 12:15:02.011757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 12:15:02.011853 ==
4218 12:15:02.015233 [Gating] SW mode calibration
4219 12:15:02.022074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4220 12:15:02.028125 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4221 12:15:02.032039 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 12:15:02.034743 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4223 12:15:02.041384 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 12:15:02.045212 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4225 12:15:02.048559 0 9 16 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (1 0)
4226 12:15:02.055229 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 12:15:02.057904 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 12:15:02.061342 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 12:15:02.068131 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 12:15:02.071630 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 12:15:02.074820 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 12:15:02.081513 0 10 12 | B1->B0 | 2727 2d2d | 0 1 | (0 0) (0 0)
4233 12:15:02.084942 0 10 16 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
4234 12:15:02.088368 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 12:15:02.094841 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 12:15:02.098113 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 12:15:02.100908 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 12:15:02.107740 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 12:15:02.111137 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 12:15:02.114596 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4241 12:15:02.120739 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 12:15:02.124193 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 12:15:02.127682 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 12:15:02.134154 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 12:15:02.137450 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 12:15:02.140949 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 12:15:02.147554 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 12:15:02.150830 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 12:15:02.154090 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 12:15:02.160716 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:15:02.164098 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:15:02.166867 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 12:15:02.173664 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:15:02.177141 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:15:02.180589 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:15:02.186873 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:15:02.190133 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 12:15:02.193529 Total UI for P1: 0, mck2ui 16
4259 12:15:02.196747 best dqsien dly found for B0: ( 0, 13, 14)
4260 12:15:02.200505 Total UI for P1: 0, mck2ui 16
4261 12:15:02.203875 best dqsien dly found for B1: ( 0, 13, 14)
4262 12:15:02.207008 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4263 12:15:02.210558 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4264 12:15:02.210664
4265 12:15:02.213938 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4266 12:15:02.216709 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4267 12:15:02.220168 [Gating] SW calibration Done
4268 12:15:02.220264 ==
4269 12:15:02.223655 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 12:15:02.227189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 12:15:02.229897 ==
4272 12:15:02.229991 RX Vref Scan: 0
4273 12:15:02.230057
4274 12:15:02.233206 RX Vref 0 -> 0, step: 1
4275 12:15:02.233294
4276 12:15:02.236646 RX Delay -230 -> 252, step: 16
4277 12:15:02.239980 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4278 12:15:02.243535 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4279 12:15:02.246952 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4280 12:15:02.253169 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4281 12:15:02.256476 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4282 12:15:02.260328 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4283 12:15:02.263519 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4284 12:15:02.266667 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4285 12:15:02.273420 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4286 12:15:02.276181 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4287 12:15:02.279660 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4288 12:15:02.282902 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4289 12:15:02.290377 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4290 12:15:02.292974 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4291 12:15:02.296252 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4292 12:15:02.299706 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4293 12:15:02.302860 ==
4294 12:15:02.306001 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 12:15:02.309397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 12:15:02.309547 ==
4297 12:15:02.309645 DQS Delay:
4298 12:15:02.312675 DQS0 = 0, DQS1 = 0
4299 12:15:02.312819 DQM Delay:
4300 12:15:02.315964 DQM0 = 50, DQM1 = 43
4301 12:15:02.316086 DQ Delay:
4302 12:15:02.319361 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4303 12:15:02.322858 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4304 12:15:02.326186 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4305 12:15:02.329468 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4306 12:15:02.329591
4307 12:15:02.329687
4308 12:15:02.329775 ==
4309 12:15:02.332902 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 12:15:02.336253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 12:15:02.336395 ==
4312 12:15:02.336529
4313 12:15:02.336671
4314 12:15:02.339650 TX Vref Scan disable
4315 12:15:02.342340 == TX Byte 0 ==
4316 12:15:02.345700 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4317 12:15:02.349242 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4318 12:15:02.352562 == TX Byte 1 ==
4319 12:15:02.356006 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4320 12:15:02.359422 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4321 12:15:02.359553 ==
4322 12:15:02.362578 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 12:15:02.368835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 12:15:02.369003 ==
4325 12:15:02.369109
4326 12:15:02.369197
4327 12:15:02.369285 TX Vref Scan disable
4328 12:15:02.373353 == TX Byte 0 ==
4329 12:15:02.376726 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4330 12:15:02.382918 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4331 12:15:02.383079 == TX Byte 1 ==
4332 12:15:02.386249 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4333 12:15:02.392986 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4334 12:15:02.393133
4335 12:15:02.393205 [DATLAT]
4336 12:15:02.393283 Freq=600, CH0 RK1
4337 12:15:02.393374
4338 12:15:02.396456 DATLAT Default: 0x9
4339 12:15:02.396552 0, 0xFFFF, sum = 0
4340 12:15:02.399824 1, 0xFFFF, sum = 0
4341 12:15:02.402962 2, 0xFFFF, sum = 0
4342 12:15:02.403090 3, 0xFFFF, sum = 0
4343 12:15:02.406191 4, 0xFFFF, sum = 0
4344 12:15:02.406289 5, 0xFFFF, sum = 0
4345 12:15:02.409615 6, 0xFFFF, sum = 0
4346 12:15:02.409744 7, 0xFFFF, sum = 0
4347 12:15:02.412782 8, 0x0, sum = 1
4348 12:15:02.412910 9, 0x0, sum = 2
4349 12:15:02.413011 10, 0x0, sum = 3
4350 12:15:02.416035 11, 0x0, sum = 4
4351 12:15:02.416171 best_step = 9
4352 12:15:02.416271
4353 12:15:02.416369 ==
4354 12:15:02.419821 Dram Type= 6, Freq= 0, CH_0, rank 1
4355 12:15:02.426465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 12:15:02.426630 ==
4357 12:15:02.426734 RX Vref Scan: 0
4358 12:15:02.426835
4359 12:15:02.429860 RX Vref 0 -> 0, step: 1
4360 12:15:02.429963
4361 12:15:02.433240 RX Delay -163 -> 252, step: 8
4362 12:15:02.436535 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4363 12:15:02.442654 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4364 12:15:02.446207 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4365 12:15:02.449310 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4366 12:15:02.452712 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4367 12:15:02.456303 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4368 12:15:02.462523 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4369 12:15:02.465986 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4370 12:15:02.469411 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4371 12:15:02.472781 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4372 12:15:02.476083 iDelay=205, Bit 10, Center 52 (-83 ~ 188) 272
4373 12:15:02.482592 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4374 12:15:02.485883 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4375 12:15:02.489330 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4376 12:15:02.492691 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4377 12:15:02.496099 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4378 12:15:02.499602 ==
4379 12:15:02.502873 Dram Type= 6, Freq= 0, CH_0, rank 1
4380 12:15:02.506247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 12:15:02.506389 ==
4382 12:15:02.506490 DQS Delay:
4383 12:15:02.509367 DQS0 = 0, DQS1 = 0
4384 12:15:02.509461 DQM Delay:
4385 12:15:02.512566 DQM0 = 54, DQM1 = 46
4386 12:15:02.512676 DQ Delay:
4387 12:15:02.515827 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4388 12:15:02.519227 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =64
4389 12:15:02.522394 DQ8 =36, DQ9 =36, DQ10 =52, DQ11 =40
4390 12:15:02.526213 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4391 12:15:02.526361
4392 12:15:02.526463
4393 12:15:02.532773 [DQSOSCAuto] RK1, (LSB)MR18= 0x6322, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4394 12:15:02.536173 CH0 RK1: MR19=808, MR18=6322
4395 12:15:02.542384 CH0_RK1: MR19=0x808, MR18=0x6322, DQSOSC=391, MR23=63, INC=171, DEC=114
4396 12:15:02.545784 [RxdqsGatingPostProcess] freq 600
4397 12:15:02.552495 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4398 12:15:02.552635 Pre-setting of DQS Precalculation
4399 12:15:02.559278 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4400 12:15:02.559441 ==
4401 12:15:02.562652 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 12:15:02.565477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 12:15:02.565607 ==
4404 12:15:02.572415 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4405 12:15:02.579118 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4406 12:15:02.582307 [CA 0] Center 36 (5~67) winsize 63
4407 12:15:02.585613 [CA 1] Center 36 (6~67) winsize 62
4408 12:15:02.588784 [CA 2] Center 35 (4~66) winsize 63
4409 12:15:02.592604 [CA 3] Center 34 (4~65) winsize 62
4410 12:15:02.595979 [CA 4] Center 34 (4~65) winsize 62
4411 12:15:02.599304 [CA 5] Center 34 (4~65) winsize 62
4412 12:15:02.599455
4413 12:15:02.602790 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4414 12:15:02.602934
4415 12:15:02.606088 [CATrainingPosCal] consider 1 rank data
4416 12:15:02.608806 u2DelayCellTimex100 = 270/100 ps
4417 12:15:02.612743 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4418 12:15:02.615662 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4419 12:15:02.618790 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4420 12:15:02.622725 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4421 12:15:02.625482 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4422 12:15:02.628823 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4423 12:15:02.628946
4424 12:15:02.635296 CA PerBit enable=1, Macro0, CA PI delay=34
4425 12:15:02.635432
4426 12:15:02.638651 [CBTSetCACLKResult] CA Dly = 34
4427 12:15:02.638769 CS Dly: 5 (0~36)
4428 12:15:02.638876 ==
4429 12:15:02.642064 Dram Type= 6, Freq= 0, CH_1, rank 1
4430 12:15:02.645473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 12:15:02.645608 ==
4432 12:15:02.652211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4433 12:15:02.659019 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4434 12:15:02.662450 [CA 0] Center 36 (5~67) winsize 63
4435 12:15:02.665301 [CA 1] Center 36 (5~67) winsize 63
4436 12:15:02.668756 [CA 2] Center 34 (4~65) winsize 62
4437 12:15:02.672164 [CA 3] Center 34 (4~65) winsize 62
4438 12:15:02.675670 [CA 4] Center 34 (4~65) winsize 62
4439 12:15:02.679135 [CA 5] Center 34 (3~65) winsize 63
4440 12:15:02.679272
4441 12:15:02.681862 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4442 12:15:02.681960
4443 12:15:02.685329 [CATrainingPosCal] consider 2 rank data
4444 12:15:02.688471 u2DelayCellTimex100 = 270/100 ps
4445 12:15:02.691788 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4446 12:15:02.695048 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4447 12:15:02.698275 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4448 12:15:02.702116 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4449 12:15:02.705652 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4450 12:15:02.711639 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4451 12:15:02.711788
4452 12:15:02.715056 CA PerBit enable=1, Macro0, CA PI delay=34
4453 12:15:02.715195
4454 12:15:02.718637 [CBTSetCACLKResult] CA Dly = 34
4455 12:15:02.718758 CS Dly: 6 (0~38)
4456 12:15:02.718828
4457 12:15:02.721985 ----->DramcWriteLeveling(PI) begin...
4458 12:15:02.722126 ==
4459 12:15:02.725206 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 12:15:02.731587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 12:15:02.731754 ==
4462 12:15:02.735086 Write leveling (Byte 0): 33 => 33
4463 12:15:02.735226 Write leveling (Byte 1): 30 => 30
4464 12:15:02.738310 DramcWriteLeveling(PI) end<-----
4465 12:15:02.738448
4466 12:15:02.738516 ==
4467 12:15:02.741442 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 12:15:02.748033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 12:15:02.748204 ==
4470 12:15:02.751458 [Gating] SW mode calibration
4471 12:15:02.758382 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4472 12:15:02.761788 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4473 12:15:02.768441 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 12:15:02.771937 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4475 12:15:02.774797 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4476 12:15:02.781814 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (0 1) (1 0)
4477 12:15:02.785343 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 12:15:02.788559 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 12:15:02.791348 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 12:15:02.798448 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 12:15:02.801766 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 12:15:02.805004 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 12:15:02.811559 0 10 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4484 12:15:02.814947 0 10 12 | B1->B0 | 3333 3939 | 0 0 | (1 1) (0 0)
4485 12:15:02.818199 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 12:15:02.824456 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 12:15:02.827849 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 12:15:02.831170 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 12:15:02.837981 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 12:15:02.841341 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 12:15:02.844700 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 12:15:02.851087 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4493 12:15:02.854910 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4494 12:15:02.858199 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 12:15:02.865084 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 12:15:02.868336 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 12:15:02.871723 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 12:15:02.878420 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 12:15:02.881202 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 12:15:02.884693 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 12:15:02.891504 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 12:15:02.894842 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 12:15:02.897670 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 12:15:02.904960 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 12:15:02.908071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 12:15:02.911314 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 12:15:02.917800 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 12:15:02.921202 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4509 12:15:02.924652 Total UI for P1: 0, mck2ui 16
4510 12:15:02.928128 best dqsien dly found for B0: ( 0, 13, 10)
4511 12:15:02.931481 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 12:15:02.934951 Total UI for P1: 0, mck2ui 16
4513 12:15:02.937750 best dqsien dly found for B1: ( 0, 13, 12)
4514 12:15:02.941090 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4515 12:15:02.944236 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4516 12:15:02.944373
4517 12:15:02.947654 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4518 12:15:02.954390 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4519 12:15:02.954511 [Gating] SW calibration Done
4520 12:15:02.954585 ==
4521 12:15:02.957698 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 12:15:02.964796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 12:15:02.964963 ==
4524 12:15:02.965036 RX Vref Scan: 0
4525 12:15:02.965099
4526 12:15:02.967989 RX Vref 0 -> 0, step: 1
4527 12:15:02.968082
4528 12:15:02.971294 RX Delay -230 -> 252, step: 16
4529 12:15:02.974716 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4530 12:15:02.977342 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4531 12:15:02.980823 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4532 12:15:02.987588 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4533 12:15:02.990909 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4534 12:15:02.994455 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4535 12:15:02.997822 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4536 12:15:03.001206 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4537 12:15:03.007917 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4538 12:15:03.011266 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4539 12:15:03.014690 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4540 12:15:03.017969 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4541 12:15:03.024249 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4542 12:15:03.027333 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4543 12:15:03.030874 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4544 12:15:03.037646 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4545 12:15:03.037878 ==
4546 12:15:03.040493 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 12:15:03.043815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 12:15:03.043948 ==
4549 12:15:03.044044 DQS Delay:
4550 12:15:03.047219 DQS0 = 0, DQS1 = 0
4551 12:15:03.047344 DQM Delay:
4552 12:15:03.050454 DQM0 = 52, DQM1 = 48
4553 12:15:03.050568 DQ Delay:
4554 12:15:03.053896 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4555 12:15:03.057321 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4556 12:15:03.060681 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4557 12:15:03.063840 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4558 12:15:03.063978
4559 12:15:03.064078
4560 12:15:03.064166 ==
4561 12:15:03.067146 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 12:15:03.070518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 12:15:03.070670 ==
4564 12:15:03.070767
4565 12:15:03.070856
4566 12:15:03.073778 TX Vref Scan disable
4567 12:15:03.077098 == TX Byte 0 ==
4568 12:15:03.080332 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4569 12:15:03.083803 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4570 12:15:03.087242 == TX Byte 1 ==
4571 12:15:03.089939 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4572 12:15:03.093454 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4573 12:15:03.093596 ==
4574 12:15:03.096674 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 12:15:03.103278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 12:15:03.103456 ==
4577 12:15:03.103566
4578 12:15:03.103674
4579 12:15:03.103774 TX Vref Scan disable
4580 12:15:03.108130 == TX Byte 0 ==
4581 12:15:03.111445 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4582 12:15:03.117796 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4583 12:15:03.117986 == TX Byte 1 ==
4584 12:15:03.121041 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4585 12:15:03.127976 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4586 12:15:03.128165
4587 12:15:03.128269 [DATLAT]
4588 12:15:03.128360 Freq=600, CH1 RK0
4589 12:15:03.128466
4590 12:15:03.131125 DATLAT Default: 0x9
4591 12:15:03.134287 0, 0xFFFF, sum = 0
4592 12:15:03.134414 1, 0xFFFF, sum = 0
4593 12:15:03.137513 2, 0xFFFF, sum = 0
4594 12:15:03.137632 3, 0xFFFF, sum = 0
4595 12:15:03.141078 4, 0xFFFF, sum = 0
4596 12:15:03.141214 5, 0xFFFF, sum = 0
4597 12:15:03.144398 6, 0xFFFF, sum = 0
4598 12:15:03.144520 7, 0xFFFF, sum = 0
4599 12:15:03.147846 8, 0x0, sum = 1
4600 12:15:03.147979 9, 0x0, sum = 2
4601 12:15:03.148082 10, 0x0, sum = 3
4602 12:15:03.151296 11, 0x0, sum = 4
4603 12:15:03.151418 best_step = 9
4604 12:15:03.151514
4605 12:15:03.151639 ==
4606 12:15:03.154587 Dram Type= 6, Freq= 0, CH_1, rank 0
4607 12:15:03.161176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 12:15:03.161329 ==
4609 12:15:03.161458 RX Vref Scan: 1
4610 12:15:03.161553
4611 12:15:03.164466 RX Vref 0 -> 0, step: 1
4612 12:15:03.164581
4613 12:15:03.167524 RX Delay -147 -> 252, step: 8
4614 12:15:03.167648
4615 12:15:03.170908 Set Vref, RX VrefLevel [Byte0]: 54
4616 12:15:03.174419 [Byte1]: 48
4617 12:15:03.174570
4618 12:15:03.177844 Final RX Vref Byte 0 = 54 to rank0
4619 12:15:03.180673 Final RX Vref Byte 1 = 48 to rank0
4620 12:15:03.183892 Final RX Vref Byte 0 = 54 to rank1
4621 12:15:03.187687 Final RX Vref Byte 1 = 48 to rank1==
4622 12:15:03.190971 Dram Type= 6, Freq= 0, CH_1, rank 0
4623 12:15:03.194299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 12:15:03.194480 ==
4625 12:15:03.197610 DQS Delay:
4626 12:15:03.197731 DQS0 = 0, DQS1 = 0
4627 12:15:03.201025 DQM Delay:
4628 12:15:03.201152 DQM0 = 48, DQM1 = 46
4629 12:15:03.201248 DQ Delay:
4630 12:15:03.204361 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4631 12:15:03.207065 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4632 12:15:03.210499 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4633 12:15:03.213929 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4634 12:15:03.214080
4635 12:15:03.214182
4636 12:15:03.223966 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a6f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
4637 12:15:03.227559 CH1 RK0: MR19=808, MR18=4A6F
4638 12:15:03.233939 CH1_RK0: MR19=0x808, MR18=0x4A6F, DQSOSC=389, MR23=63, INC=173, DEC=115
4639 12:15:03.234124
4640 12:15:03.237211 ----->DramcWriteLeveling(PI) begin...
4641 12:15:03.237342 ==
4642 12:15:03.240440 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 12:15:03.243711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 12:15:03.243841 ==
4645 12:15:03.247204 Write leveling (Byte 0): 30 => 30
4646 12:15:03.250654 Write leveling (Byte 1): 30 => 30
4647 12:15:03.254085 DramcWriteLeveling(PI) end<-----
4648 12:15:03.254213
4649 12:15:03.254319 ==
4650 12:15:03.256802 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 12:15:03.260132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 12:15:03.260246 ==
4653 12:15:03.264002 [Gating] SW mode calibration
4654 12:15:03.269995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4655 12:15:03.277199 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4656 12:15:03.280005 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 12:15:03.283290 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 12:15:03.290203 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4659 12:15:03.293278 0 9 12 | B1->B0 | 2e2e 2e2e | 1 1 | (1 0) (1 1)
4660 12:15:03.296594 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 12:15:03.303647 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 12:15:03.307023 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 12:15:03.310447 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 12:15:03.316574 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 12:15:03.319971 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 12:15:03.323549 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4667 12:15:03.330255 0 10 12 | B1->B0 | 3e3e 3434 | 0 0 | (0 0) (0 0)
4668 12:15:03.333105 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 12:15:03.336620 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 12:15:03.343544 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 12:15:03.346782 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 12:15:03.350070 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 12:15:03.356287 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 12:15:03.359752 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4675 12:15:03.363210 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4676 12:15:03.366556 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 12:15:03.372916 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 12:15:03.376321 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 12:15:03.380145 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 12:15:03.386793 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 12:15:03.390258 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 12:15:03.392939 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 12:15:03.399723 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 12:15:03.403045 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 12:15:03.406361 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 12:15:03.412952 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 12:15:03.416237 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 12:15:03.419707 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 12:15:03.426477 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 12:15:03.429969 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 12:15:03.433254 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4692 12:15:03.440096 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 12:15:03.440242 Total UI for P1: 0, mck2ui 16
4694 12:15:03.446156 best dqsien dly found for B0: ( 0, 13, 14)
4695 12:15:03.446303 Total UI for P1: 0, mck2ui 16
4696 12:15:03.449986 best dqsien dly found for B1: ( 0, 13, 12)
4697 12:15:03.456573 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4698 12:15:03.459835 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4699 12:15:03.459957
4700 12:15:03.463287 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4701 12:15:03.466614 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4702 12:15:03.469412 [Gating] SW calibration Done
4703 12:15:03.469544 ==
4704 12:15:03.472792 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 12:15:03.476104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 12:15:03.476254 ==
4707 12:15:03.479333 RX Vref Scan: 0
4708 12:15:03.479449
4709 12:15:03.479563 RX Vref 0 -> 0, step: 1
4710 12:15:03.479678
4711 12:15:03.482786 RX Delay -230 -> 252, step: 16
4712 12:15:03.486088 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4713 12:15:03.492864 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4714 12:15:03.496284 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4715 12:15:03.499684 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4716 12:15:03.503116 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4717 12:15:03.509583 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4718 12:15:03.512943 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4719 12:15:03.516224 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4720 12:15:03.519311 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4721 12:15:03.522781 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4722 12:15:03.529666 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4723 12:15:03.532991 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4724 12:15:03.536285 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4725 12:15:03.539912 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4726 12:15:03.545916 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4727 12:15:03.549308 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4728 12:15:03.549402 ==
4729 12:15:03.552888 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 12:15:03.556025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 12:15:03.556139 ==
4732 12:15:03.559167 DQS Delay:
4733 12:15:03.559248 DQS0 = 0, DQS1 = 0
4734 12:15:03.559313 DQM Delay:
4735 12:15:03.563130 DQM0 = 50, DQM1 = 47
4736 12:15:03.563203 DQ Delay:
4737 12:15:03.565780 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4738 12:15:03.569232 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4739 12:15:03.572757 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4740 12:15:03.576163 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4741 12:15:03.576268
4742 12:15:03.576334
4743 12:15:03.576394 ==
4744 12:15:03.579534 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 12:15:03.586108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 12:15:03.586199 ==
4747 12:15:03.586267
4748 12:15:03.586329
4749 12:15:03.586387 TX Vref Scan disable
4750 12:15:03.589769 == TX Byte 0 ==
4751 12:15:03.593025 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4752 12:15:03.596379 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4753 12:15:03.599937 == TX Byte 1 ==
4754 12:15:03.603201 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4755 12:15:03.605949 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4756 12:15:03.609318 ==
4757 12:15:03.612604 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 12:15:03.616001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 12:15:03.616101 ==
4760 12:15:03.616171
4761 12:15:03.616235
4762 12:15:03.619457 TX Vref Scan disable
4763 12:15:03.619543 == TX Byte 0 ==
4764 12:15:03.626114 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4765 12:15:03.629412 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4766 12:15:03.629504 == TX Byte 1 ==
4767 12:15:03.636206 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4768 12:15:03.639681 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4769 12:15:03.639776
4770 12:15:03.639843 [DATLAT]
4771 12:15:03.642972 Freq=600, CH1 RK1
4772 12:15:03.643058
4773 12:15:03.643133 DATLAT Default: 0x9
4774 12:15:03.646391 0, 0xFFFF, sum = 0
4775 12:15:03.646478 1, 0xFFFF, sum = 0
4776 12:15:03.649829 2, 0xFFFF, sum = 0
4777 12:15:03.649920 3, 0xFFFF, sum = 0
4778 12:15:03.653147 4, 0xFFFF, sum = 0
4779 12:15:03.653235 5, 0xFFFF, sum = 0
4780 12:15:03.655981 6, 0xFFFF, sum = 0
4781 12:15:03.659151 7, 0xFFFF, sum = 0
4782 12:15:03.659268 8, 0x0, sum = 1
4783 12:15:03.659369 9, 0x0, sum = 2
4784 12:15:03.662591 10, 0x0, sum = 3
4785 12:15:03.662685 11, 0x0, sum = 4
4786 12:15:03.666487 best_step = 9
4787 12:15:03.666576
4788 12:15:03.666643 ==
4789 12:15:03.669670 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 12:15:03.672805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 12:15:03.672896 ==
4792 12:15:03.676154 RX Vref Scan: 0
4793 12:15:03.676241
4794 12:15:03.676309 RX Vref 0 -> 0, step: 1
4795 12:15:03.676372
4796 12:15:03.679506 RX Delay -163 -> 252, step: 8
4797 12:15:03.686343 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4798 12:15:03.689660 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4799 12:15:03.692976 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4800 12:15:03.696624 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4801 12:15:03.699868 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4802 12:15:03.706377 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4803 12:15:03.709783 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4804 12:15:03.713053 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4805 12:15:03.716241 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4806 12:15:03.723019 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4807 12:15:03.726433 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4808 12:15:03.729916 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4809 12:15:03.733362 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4810 12:15:03.736450 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4811 12:15:03.743102 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4812 12:15:03.746644 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4813 12:15:03.746757 ==
4814 12:15:03.749350 Dram Type= 6, Freq= 0, CH_1, rank 1
4815 12:15:03.752886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4816 12:15:03.752982 ==
4817 12:15:03.756225 DQS Delay:
4818 12:15:03.756342 DQS0 = 0, DQS1 = 0
4819 12:15:03.756436 DQM Delay:
4820 12:15:03.759650 DQM0 = 48, DQM1 = 44
4821 12:15:03.759736 DQ Delay:
4822 12:15:03.763224 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4823 12:15:03.765950 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4824 12:15:03.769427 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4825 12:15:03.772814 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4826 12:15:03.772906
4827 12:15:03.773004
4828 12:15:03.782766 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4829 12:15:03.786105 CH1 RK1: MR19=808, MR18=6B23
4830 12:15:03.789499 CH1_RK1: MR19=0x808, MR18=0x6B23, DQSOSC=389, MR23=63, INC=173, DEC=115
4831 12:15:03.792799 [RxdqsGatingPostProcess] freq 600
4832 12:15:03.798939 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4833 12:15:03.802273 Pre-setting of DQS Precalculation
4834 12:15:03.806076 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4835 12:15:03.815861 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4836 12:15:03.822483 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4837 12:15:03.822662
4838 12:15:03.822731
4839 12:15:03.825930 [Calibration Summary] 1200 Mbps
4840 12:15:03.826018 CH 0, Rank 0
4841 12:15:03.829292 SW Impedance : PASS
4842 12:15:03.829379 DUTY Scan : NO K
4843 12:15:03.832774 ZQ Calibration : PASS
4844 12:15:03.836027 Jitter Meter : NO K
4845 12:15:03.836122 CBT Training : PASS
4846 12:15:03.838777 Write leveling : PASS
4847 12:15:03.842123 RX DQS gating : PASS
4848 12:15:03.842241 RX DQ/DQS(RDDQC) : PASS
4849 12:15:03.845827 TX DQ/DQS : PASS
4850 12:15:03.845911 RX DATLAT : PASS
4851 12:15:03.849180 RX DQ/DQS(Engine): PASS
4852 12:15:03.852669 TX OE : NO K
4853 12:15:03.852759 All Pass.
4854 12:15:03.852823
4855 12:15:03.852881 CH 0, Rank 1
4856 12:15:03.855307 SW Impedance : PASS
4857 12:15:03.858783 DUTY Scan : NO K
4858 12:15:03.858914 ZQ Calibration : PASS
4859 12:15:03.862248 Jitter Meter : NO K
4860 12:15:03.865663 CBT Training : PASS
4861 12:15:03.865756 Write leveling : PASS
4862 12:15:03.869038 RX DQS gating : PASS
4863 12:15:03.872492 RX DQ/DQS(RDDQC) : PASS
4864 12:15:03.872584 TX DQ/DQS : PASS
4865 12:15:03.875946 RX DATLAT : PASS
4866 12:15:03.879200 RX DQ/DQS(Engine): PASS
4867 12:15:03.879308 TX OE : NO K
4868 12:15:03.882610 All Pass.
4869 12:15:03.882697
4870 12:15:03.882764 CH 1, Rank 0
4871 12:15:03.885807 SW Impedance : PASS
4872 12:15:03.885894 DUTY Scan : NO K
4873 12:15:03.888768 ZQ Calibration : PASS
4874 12:15:03.892521 Jitter Meter : NO K
4875 12:15:03.892620 CBT Training : PASS
4876 12:15:03.895876 Write leveling : PASS
4877 12:15:03.896058 RX DQS gating : PASS
4878 12:15:03.898582 RX DQ/DQS(RDDQC) : PASS
4879 12:15:03.901998 TX DQ/DQS : PASS
4880 12:15:03.902130 RX DATLAT : PASS
4881 12:15:03.905549 RX DQ/DQS(Engine): PASS
4882 12:15:03.909026 TX OE : NO K
4883 12:15:03.909140 All Pass.
4884 12:15:03.909239
4885 12:15:03.909324 CH 1, Rank 1
4886 12:15:03.912410 SW Impedance : PASS
4887 12:15:03.915500 DUTY Scan : NO K
4888 12:15:03.915610 ZQ Calibration : PASS
4889 12:15:03.918618 Jitter Meter : NO K
4890 12:15:03.922285 CBT Training : PASS
4891 12:15:03.922403 Write leveling : PASS
4892 12:15:03.925579 RX DQS gating : PASS
4893 12:15:03.928808 RX DQ/DQS(RDDQC) : PASS
4894 12:15:03.928926 TX DQ/DQS : PASS
4895 12:15:03.932018 RX DATLAT : PASS
4896 12:15:03.935365 RX DQ/DQS(Engine): PASS
4897 12:15:03.935483 TX OE : NO K
4898 12:15:03.935587 All Pass.
4899 12:15:03.938783
4900 12:15:03.938898 DramC Write-DBI off
4901 12:15:03.942283 PER_BANK_REFRESH: Hybrid Mode
4902 12:15:03.942395 TX_TRACKING: ON
4903 12:15:03.952169 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4904 12:15:03.955546 [FAST_K] Save calibration result to emmc
4905 12:15:03.958905 dramc_set_vcore_voltage set vcore to 662500
4906 12:15:03.962395 Read voltage for 933, 3
4907 12:15:03.962527 Vio18 = 0
4908 12:15:03.965797 Vcore = 662500
4909 12:15:03.965894 Vdram = 0
4910 12:15:03.965963 Vddq = 0
4911 12:15:03.966024 Vmddr = 0
4912 12:15:03.971945 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4913 12:15:03.975246 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4914 12:15:03.978717 MEM_TYPE=3, freq_sel=17
4915 12:15:03.981881 sv_algorithm_assistance_LP4_1600
4916 12:15:03.985277 ============ PULL DRAM RESETB DOWN ============
4917 12:15:03.992134 ========== PULL DRAM RESETB DOWN end =========
4918 12:15:03.995471 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4919 12:15:03.998669 ===================================
4920 12:15:04.001979 LPDDR4 DRAM CONFIGURATION
4921 12:15:04.005215 ===================================
4922 12:15:04.005335 EX_ROW_EN[0] = 0x0
4923 12:15:04.008600 EX_ROW_EN[1] = 0x0
4924 12:15:04.008717 LP4Y_EN = 0x0
4925 12:15:04.011989 WORK_FSP = 0x0
4926 12:15:04.012100 WL = 0x3
4927 12:15:04.015297 RL = 0x3
4928 12:15:04.015431 BL = 0x2
4929 12:15:04.018836 RPST = 0x0
4930 12:15:04.018948 RD_PRE = 0x0
4931 12:15:04.022207 WR_PRE = 0x1
4932 12:15:04.022318 WR_PST = 0x0
4933 12:15:04.025466 DBI_WR = 0x0
4934 12:15:04.028642 DBI_RD = 0x0
4935 12:15:04.028763 OTF = 0x1
4936 12:15:04.031769 ===================================
4937 12:15:04.035531 ===================================
4938 12:15:04.035650 ANA top config
4939 12:15:04.038684 ===================================
4940 12:15:04.041903 DLL_ASYNC_EN = 0
4941 12:15:04.045101 ALL_SLAVE_EN = 1
4942 12:15:04.048689 NEW_RANK_MODE = 1
4943 12:15:04.052052 DLL_IDLE_MODE = 1
4944 12:15:04.052146 LP45_APHY_COMB_EN = 1
4945 12:15:04.055372 TX_ODT_DIS = 1
4946 12:15:04.058497 NEW_8X_MODE = 1
4947 12:15:04.061815 ===================================
4948 12:15:04.065262 ===================================
4949 12:15:04.068649 data_rate = 1866
4950 12:15:04.072158 CKR = 1
4951 12:15:04.072260 DQ_P2S_RATIO = 8
4952 12:15:04.075573 ===================================
4953 12:15:04.078245 CA_P2S_RATIO = 8
4954 12:15:04.081679 DQ_CA_OPEN = 0
4955 12:15:04.084993 DQ_SEMI_OPEN = 0
4956 12:15:04.088335 CA_SEMI_OPEN = 0
4957 12:15:04.091585 CA_FULL_RATE = 0
4958 12:15:04.091683 DQ_CKDIV4_EN = 1
4959 12:15:04.095082 CA_CKDIV4_EN = 1
4960 12:15:04.098307 CA_PREDIV_EN = 0
4961 12:15:04.101782 PH8_DLY = 0
4962 12:15:04.105332 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4963 12:15:04.105427 DQ_AAMCK_DIV = 4
4964 12:15:04.108632 CA_AAMCK_DIV = 4
4965 12:15:04.111843 CA_ADMCK_DIV = 4
4966 12:15:04.115187 DQ_TRACK_CA_EN = 0
4967 12:15:04.118620 CA_PICK = 933
4968 12:15:04.122019 CA_MCKIO = 933
4969 12:15:04.125366 MCKIO_SEMI = 0
4970 12:15:04.125467 PLL_FREQ = 3732
4971 12:15:04.128641 DQ_UI_PI_RATIO = 32
4972 12:15:04.132056 CA_UI_PI_RATIO = 0
4973 12:15:04.134807 ===================================
4974 12:15:04.138070 ===================================
4975 12:15:04.141919 memory_type:LPDDR4
4976 12:15:04.145294 GP_NUM : 10
4977 12:15:04.145395 SRAM_EN : 1
4978 12:15:04.148678 MD32_EN : 0
4979 12:15:04.151809 ===================================
4980 12:15:04.151905 [ANA_INIT] >>>>>>>>>>>>>>
4981 12:15:04.155092 <<<<<< [CONFIGURE PHASE]: ANA_TX
4982 12:15:04.158461 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4983 12:15:04.161258 ===================================
4984 12:15:04.164597 data_rate = 1866,PCW = 0X8f00
4985 12:15:04.168426 ===================================
4986 12:15:04.171709 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4987 12:15:04.177924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 12:15:04.181261 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4989 12:15:04.188087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4990 12:15:04.191624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4991 12:15:04.195039 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4992 12:15:04.197870 [ANA_INIT] flow start
4993 12:15:04.197974 [ANA_INIT] PLL >>>>>>>>
4994 12:15:04.201149 [ANA_INIT] PLL <<<<<<<<
4995 12:15:04.204454 [ANA_INIT] MIDPI >>>>>>>>
4996 12:15:04.204550 [ANA_INIT] MIDPI <<<<<<<<
4997 12:15:04.207805 [ANA_INIT] DLL >>>>>>>>
4998 12:15:04.211152 [ANA_INIT] flow end
4999 12:15:04.214562 ============ LP4 DIFF to SE enter ============
5000 12:15:04.217735 ============ LP4 DIFF to SE exit ============
5001 12:15:04.221121 [ANA_INIT] <<<<<<<<<<<<<
5002 12:15:04.224517 [Flow] Enable top DCM control >>>>>
5003 12:15:04.227915 [Flow] Enable top DCM control <<<<<
5004 12:15:04.230763 Enable DLL master slave shuffle
5005 12:15:04.234674 ==============================================================
5006 12:15:04.238043 Gating Mode config
5007 12:15:04.244177 ==============================================================
5008 12:15:04.244302 Config description:
5009 12:15:04.254307 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5010 12:15:04.260714 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5011 12:15:04.267559 SELPH_MODE 0: By rank 1: By Phase
5012 12:15:04.270915 ==============================================================
5013 12:15:04.274240 GAT_TRACK_EN = 1
5014 12:15:04.277387 RX_GATING_MODE = 2
5015 12:15:04.280637 RX_GATING_TRACK_MODE = 2
5016 12:15:04.284056 SELPH_MODE = 1
5017 12:15:04.287315 PICG_EARLY_EN = 1
5018 12:15:04.290757 VALID_LAT_VALUE = 1
5019 12:15:04.294149 ==============================================================
5020 12:15:04.297598 Enter into Gating configuration >>>>
5021 12:15:04.300371 Exit from Gating configuration <<<<
5022 12:15:04.303697 Enter into DVFS_PRE_config >>>>>
5023 12:15:04.317289 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5024 12:15:04.320706 Exit from DVFS_PRE_config <<<<<
5025 12:15:04.320826 Enter into PICG configuration >>>>
5026 12:15:04.323937 Exit from PICG configuration <<<<
5027 12:15:04.327192 [RX_INPUT] configuration >>>>>
5028 12:15:04.330677 [RX_INPUT] configuration <<<<<
5029 12:15:04.337234 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5030 12:15:04.340561 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5031 12:15:04.347333 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5032 12:15:04.354205 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5033 12:15:04.360566 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5034 12:15:04.366995 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5035 12:15:04.370380 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5036 12:15:04.374042 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5037 12:15:04.376886 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5038 12:15:04.383590 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5039 12:15:04.387512 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5040 12:15:04.390212 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5041 12:15:04.393575 ===================================
5042 12:15:04.396940 LPDDR4 DRAM CONFIGURATION
5043 12:15:04.400209 ===================================
5044 12:15:04.400311 EX_ROW_EN[0] = 0x0
5045 12:15:04.403613 EX_ROW_EN[1] = 0x0
5046 12:15:04.406891 LP4Y_EN = 0x0
5047 12:15:04.406988 WORK_FSP = 0x0
5048 12:15:04.410193 WL = 0x3
5049 12:15:04.410273 RL = 0x3
5050 12:15:04.413459 BL = 0x2
5051 12:15:04.413553 RPST = 0x0
5052 12:15:04.416771 RD_PRE = 0x0
5053 12:15:04.416863 WR_PRE = 0x1
5054 12:15:04.420133 WR_PST = 0x0
5055 12:15:04.420223 DBI_WR = 0x0
5056 12:15:04.423479 DBI_RD = 0x0
5057 12:15:04.423568 OTF = 0x1
5058 12:15:04.426943 ===================================
5059 12:15:04.430117 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5060 12:15:04.436717 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5061 12:15:04.440682 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5062 12:15:04.443955 ===================================
5063 12:15:04.447243 LPDDR4 DRAM CONFIGURATION
5064 12:15:04.450591 ===================================
5065 12:15:04.450694 EX_ROW_EN[0] = 0x10
5066 12:15:04.453975 EX_ROW_EN[1] = 0x0
5067 12:15:04.454070 LP4Y_EN = 0x0
5068 12:15:04.457184 WORK_FSP = 0x0
5069 12:15:04.457280 WL = 0x3
5070 12:15:04.460575 RL = 0x3
5071 12:15:04.463909 BL = 0x2
5072 12:15:04.464022 RPST = 0x0
5073 12:15:04.467104 RD_PRE = 0x0
5074 12:15:04.467198 WR_PRE = 0x1
5075 12:15:04.470329 WR_PST = 0x0
5076 12:15:04.470430 DBI_WR = 0x0
5077 12:15:04.473719 DBI_RD = 0x0
5078 12:15:04.473812 OTF = 0x1
5079 12:15:04.476979 ===================================
5080 12:15:04.483754 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5081 12:15:04.487157 nWR fixed to 30
5082 12:15:04.490443 [ModeRegInit_LP4] CH0 RK0
5083 12:15:04.490542 [ModeRegInit_LP4] CH0 RK1
5084 12:15:04.494402 [ModeRegInit_LP4] CH1 RK0
5085 12:15:04.497177 [ModeRegInit_LP4] CH1 RK1
5086 12:15:04.497287 match AC timing 9
5087 12:15:04.503932 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5088 12:15:04.507196 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5089 12:15:04.510667 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5090 12:15:04.517299 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5091 12:15:04.520632 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5092 12:15:04.520741 ==
5093 12:15:04.524042 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 12:15:04.527533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 12:15:04.527633 ==
5096 12:15:04.533766 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5097 12:15:04.540865 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5098 12:15:04.544196 [CA 0] Center 37 (6~68) winsize 63
5099 12:15:04.547495 [CA 1] Center 37 (6~68) winsize 63
5100 12:15:04.550850 [CA 2] Center 34 (4~65) winsize 62
5101 12:15:04.554151 [CA 3] Center 33 (3~64) winsize 62
5102 12:15:04.557591 [CA 4] Center 33 (3~64) winsize 62
5103 12:15:04.560264 [CA 5] Center 32 (2~62) winsize 61
5104 12:15:04.560414
5105 12:15:04.563670 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5106 12:15:04.563785
5107 12:15:04.567120 [CATrainingPosCal] consider 1 rank data
5108 12:15:04.570587 u2DelayCellTimex100 = 270/100 ps
5109 12:15:04.573901 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5110 12:15:04.577129 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5111 12:15:04.580358 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5112 12:15:04.583750 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5113 12:15:04.586980 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5114 12:15:04.590370 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5115 12:15:04.593849
5116 12:15:04.597266 CA PerBit enable=1, Macro0, CA PI delay=32
5117 12:15:04.597413
5118 12:15:04.600565 [CBTSetCACLKResult] CA Dly = 32
5119 12:15:04.600668 CS Dly: 5 (0~36)
5120 12:15:04.600736 ==
5121 12:15:04.603957 Dram Type= 6, Freq= 0, CH_0, rank 1
5122 12:15:04.607246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 12:15:04.607366 ==
5124 12:15:04.614095 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5125 12:15:04.620309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5126 12:15:04.623487 [CA 0] Center 37 (6~68) winsize 63
5127 12:15:04.626980 [CA 1] Center 37 (7~68) winsize 62
5128 12:15:04.630299 [CA 2] Center 34 (4~65) winsize 62
5129 12:15:04.633584 [CA 3] Center 34 (3~65) winsize 63
5130 12:15:04.637012 [CA 4] Center 32 (2~63) winsize 62
5131 12:15:04.640450 [CA 5] Center 32 (2~62) winsize 61
5132 12:15:04.640569
5133 12:15:04.643787 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5134 12:15:04.643881
5135 12:15:04.647081 [CATrainingPosCal] consider 2 rank data
5136 12:15:04.650274 u2DelayCellTimex100 = 270/100 ps
5137 12:15:04.653561 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5138 12:15:04.657321 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5139 12:15:04.659935 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5140 12:15:04.663285 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5141 12:15:04.666774 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5142 12:15:04.673606 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5143 12:15:04.673730
5144 12:15:04.677024 CA PerBit enable=1, Macro0, CA PI delay=32
5145 12:15:04.677116
5146 12:15:04.680354 [CBTSetCACLKResult] CA Dly = 32
5147 12:15:04.680445 CS Dly: 5 (0~37)
5148 12:15:04.680513
5149 12:15:04.683586 ----->DramcWriteLeveling(PI) begin...
5150 12:15:04.683680 ==
5151 12:15:04.686790 Dram Type= 6, Freq= 0, CH_0, rank 0
5152 12:15:04.689983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 12:15:04.693279 ==
5154 12:15:04.696620 Write leveling (Byte 0): 31 => 31
5155 12:15:04.696735 Write leveling (Byte 1): 28 => 28
5156 12:15:04.699980 DramcWriteLeveling(PI) end<-----
5157 12:15:04.700074
5158 12:15:04.700142 ==
5159 12:15:04.703226 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 12:15:04.709981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 12:15:04.710133 ==
5162 12:15:04.713249 [Gating] SW mode calibration
5163 12:15:04.720102 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5164 12:15:04.723528 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5165 12:15:04.730265 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5166 12:15:04.733708 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 12:15:04.737111 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 12:15:04.740431 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 12:15:04.747071 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 12:15:04.749850 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 12:15:04.753136 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5172 12:15:04.760321 0 14 28 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
5173 12:15:04.763084 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5174 12:15:04.767002 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 12:15:04.772996 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 12:15:04.776405 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 12:15:04.779811 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 12:15:04.786803 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 12:15:04.789634 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 12:15:04.793016 0 15 28 | B1->B0 | 2424 3d3d | 0 0 | (0 0) (0 0)
5181 12:15:04.799577 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5182 12:15:04.802968 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 12:15:04.806457 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 12:15:04.813062 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 12:15:04.816266 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 12:15:04.819750 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 12:15:04.825900 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5188 12:15:04.829308 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5189 12:15:04.832736 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5190 12:15:04.839281 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 12:15:04.842677 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 12:15:04.846081 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 12:15:04.852928 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 12:15:04.856375 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 12:15:04.859742 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 12:15:04.866180 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 12:15:04.869601 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 12:15:04.872679 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 12:15:04.879156 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 12:15:04.882495 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 12:15:04.885998 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 12:15:04.892723 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 12:15:04.896037 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5204 12:15:04.899134 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5205 12:15:04.902925 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5206 12:15:04.909518 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 12:15:04.912933 Total UI for P1: 0, mck2ui 16
5208 12:15:04.915612 best dqsien dly found for B0: ( 1, 2, 28)
5209 12:15:04.918940 Total UI for P1: 0, mck2ui 16
5210 12:15:04.922765 best dqsien dly found for B1: ( 1, 2, 30)
5211 12:15:04.926139 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5212 12:15:04.928932 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5213 12:15:04.929027
5214 12:15:04.932349 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5215 12:15:04.935679 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5216 12:15:04.939097 [Gating] SW calibration Done
5217 12:15:04.939195 ==
5218 12:15:04.942603 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 12:15:04.946054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 12:15:04.946152 ==
5221 12:15:04.949343 RX Vref Scan: 0
5222 12:15:04.949441
5223 12:15:04.949510 RX Vref 0 -> 0, step: 1
5224 12:15:04.952701
5225 12:15:04.952791 RX Delay -80 -> 252, step: 8
5226 12:15:04.959488 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5227 12:15:04.962791 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5228 12:15:04.965571 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5229 12:15:04.968909 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5230 12:15:04.972674 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5231 12:15:04.975980 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5232 12:15:04.982408 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5233 12:15:04.985692 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5234 12:15:04.989063 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5235 12:15:04.992676 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5236 12:15:04.996026 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5237 12:15:05.002733 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5238 12:15:05.006147 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5239 12:15:05.009280 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5240 12:15:05.012600 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5241 12:15:05.015927 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5242 12:15:05.016011 ==
5243 12:15:05.019267 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 12:15:05.026027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 12:15:05.026118 ==
5246 12:15:05.026184 DQS Delay:
5247 12:15:05.029326 DQS0 = 0, DQS1 = 0
5248 12:15:05.029408 DQM Delay:
5249 12:15:05.029474 DQM0 = 106, DQM1 = 94
5250 12:15:05.032631 DQ Delay:
5251 12:15:05.036053 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5252 12:15:05.039347 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5253 12:15:05.042681 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5254 12:15:05.045944 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5255 12:15:05.046026
5256 12:15:05.046090
5257 12:15:05.046149 ==
5258 12:15:05.048728 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 12:15:05.052111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 12:15:05.052194 ==
5261 12:15:05.052296
5262 12:15:05.052355
5263 12:15:05.055586 TX Vref Scan disable
5264 12:15:05.058896 == TX Byte 0 ==
5265 12:15:05.062215 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5266 12:15:05.065552 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5267 12:15:05.068930 == TX Byte 1 ==
5268 12:15:05.072427 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5269 12:15:05.075782 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5270 12:15:05.075880 ==
5271 12:15:05.079083 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 12:15:05.082382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 12:15:05.085681 ==
5274 12:15:05.085762
5275 12:15:05.085826
5276 12:15:05.085884 TX Vref Scan disable
5277 12:15:05.089035 == TX Byte 0 ==
5278 12:15:05.092884 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5279 12:15:05.099085 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5280 12:15:05.099174 == TX Byte 1 ==
5281 12:15:05.102489 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5282 12:15:05.105992 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5283 12:15:05.109340
5284 12:15:05.109422 [DATLAT]
5285 12:15:05.109487 Freq=933, CH0 RK0
5286 12:15:05.109547
5287 12:15:05.112603 DATLAT Default: 0xd
5288 12:15:05.112690 0, 0xFFFF, sum = 0
5289 12:15:05.115817 1, 0xFFFF, sum = 0
5290 12:15:05.115903 2, 0xFFFF, sum = 0
5291 12:15:05.119743 3, 0xFFFF, sum = 0
5292 12:15:05.119816 4, 0xFFFF, sum = 0
5293 12:15:05.122438 5, 0xFFFF, sum = 0
5294 12:15:05.122512 6, 0xFFFF, sum = 0
5295 12:15:05.125939 7, 0xFFFF, sum = 0
5296 12:15:05.129359 8, 0xFFFF, sum = 0
5297 12:15:05.129446 9, 0xFFFF, sum = 0
5298 12:15:05.132266 10, 0x0, sum = 1
5299 12:15:05.132339 11, 0x0, sum = 2
5300 12:15:05.132402 12, 0x0, sum = 3
5301 12:15:05.135621 13, 0x0, sum = 4
5302 12:15:05.135729 best_step = 11
5303 12:15:05.135821
5304 12:15:05.138930 ==
5305 12:15:05.139012 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 12:15:05.145564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 12:15:05.145647 ==
5308 12:15:05.145711 RX Vref Scan: 1
5309 12:15:05.145771
5310 12:15:05.148955 RX Vref 0 -> 0, step: 1
5311 12:15:05.149037
5312 12:15:05.152235 RX Delay -53 -> 252, step: 4
5313 12:15:05.152316
5314 12:15:05.155627 Set Vref, RX VrefLevel [Byte0]: 56
5315 12:15:05.158967 [Byte1]: 49
5316 12:15:05.159050
5317 12:15:05.162429 Final RX Vref Byte 0 = 56 to rank0
5318 12:15:05.165778 Final RX Vref Byte 1 = 49 to rank0
5319 12:15:05.169300 Final RX Vref Byte 0 = 56 to rank1
5320 12:15:05.172608 Final RX Vref Byte 1 = 49 to rank1==
5321 12:15:05.175315 Dram Type= 6, Freq= 0, CH_0, rank 0
5322 12:15:05.178886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 12:15:05.178971 ==
5324 12:15:05.182284 DQS Delay:
5325 12:15:05.182400 DQS0 = 0, DQS1 = 0
5326 12:15:05.185758 DQM Delay:
5327 12:15:05.185859 DQM0 = 105, DQM1 = 96
5328 12:15:05.189009 DQ Delay:
5329 12:15:05.192321 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5330 12:15:05.195628 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5331 12:15:05.198933 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =90
5332 12:15:05.202419 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5333 12:15:05.202552
5334 12:15:05.202618
5335 12:15:05.209237 [DQSOSCAuto] RK0, (LSB)MR18= 0x342b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5336 12:15:05.211958 CH0 RK0: MR19=505, MR18=342B
5337 12:15:05.218871 CH0_RK0: MR19=0x505, MR18=0x342B, DQSOSC=405, MR23=63, INC=66, DEC=44
5338 12:15:05.218973
5339 12:15:05.222179 ----->DramcWriteLeveling(PI) begin...
5340 12:15:05.222300 ==
5341 12:15:05.225402 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 12:15:05.228664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 12:15:05.228750 ==
5344 12:15:05.231936 Write leveling (Byte 0): 33 => 33
5345 12:15:05.235235 Write leveling (Byte 1): 31 => 31
5346 12:15:05.238652 DramcWriteLeveling(PI) end<-----
5347 12:15:05.238735
5348 12:15:05.238801 ==
5349 12:15:05.241955 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 12:15:05.245182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 12:15:05.245266 ==
5352 12:15:05.248562 [Gating] SW mode calibration
5353 12:15:05.255286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5354 12:15:05.262000 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5355 12:15:05.265418 0 14 0 | B1->B0 | 3231 2f2f | 1 1 | (0 0) (1 1)
5356 12:15:05.272156 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 12:15:05.275617 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 12:15:05.279025 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 12:15:05.285125 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 12:15:05.288638 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 12:15:05.292040 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5362 12:15:05.298597 0 14 28 | B1->B0 | 2323 2929 | 0 0 | (1 0) (0 1)
5363 12:15:05.301880 0 15 0 | B1->B0 | 2424 2828 | 0 0 | (1 0) (1 0)
5364 12:15:05.305041 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 12:15:05.312059 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 12:15:05.314693 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 12:15:05.318591 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 12:15:05.321896 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 12:15:05.328577 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5370 12:15:05.331871 0 15 28 | B1->B0 | 3d3d 3939 | 0 0 | (0 0) (0 0)
5371 12:15:05.335094 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 12:15:05.341985 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 12:15:05.345253 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 12:15:05.348549 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 12:15:05.355092 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 12:15:05.358227 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 12:15:05.361606 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 12:15:05.368330 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5379 12:15:05.371694 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5380 12:15:05.375112 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 12:15:05.381397 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 12:15:05.384799 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 12:15:05.388155 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 12:15:05.395071 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 12:15:05.397846 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 12:15:05.401394 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:15:05.407693 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 12:15:05.411684 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 12:15:05.414868 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:15:05.421823 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:15:05.424633 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:15:05.427979 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 12:15:05.434768 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 12:15:05.438353 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5395 12:15:05.441622 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 12:15:05.444714 Total UI for P1: 0, mck2ui 16
5397 12:15:05.448273 best dqsien dly found for B0: ( 1, 2, 28)
5398 12:15:05.451334 Total UI for P1: 0, mck2ui 16
5399 12:15:05.454724 best dqsien dly found for B1: ( 1, 2, 30)
5400 12:15:05.458241 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5401 12:15:05.461268 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5402 12:15:05.461344
5403 12:15:05.464652 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5404 12:15:05.471579 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5405 12:15:05.471662 [Gating] SW calibration Done
5406 12:15:05.471728 ==
5407 12:15:05.474820 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 12:15:05.481679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 12:15:05.481773 ==
5410 12:15:05.481882 RX Vref Scan: 0
5411 12:15:05.481942
5412 12:15:05.484837 RX Vref 0 -> 0, step: 1
5413 12:15:05.484925
5414 12:15:05.487791 RX Delay -80 -> 252, step: 8
5415 12:15:05.491095 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5416 12:15:05.494650 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5417 12:15:05.498080 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5418 12:15:05.501485 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5419 12:15:05.508295 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5420 12:15:05.511591 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5421 12:15:05.514864 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5422 12:15:05.518021 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5423 12:15:05.521278 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5424 12:15:05.524790 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5425 12:15:05.530897 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5426 12:15:05.534420 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5427 12:15:05.537847 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5428 12:15:05.541296 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5429 12:15:05.544084 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5430 12:15:05.550872 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5431 12:15:05.550955 ==
5432 12:15:05.554701 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 12:15:05.557796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 12:15:05.557904 ==
5435 12:15:05.557996 DQS Delay:
5436 12:15:05.561216 DQS0 = 0, DQS1 = 0
5437 12:15:05.561298 DQM Delay:
5438 12:15:05.564391 DQM0 = 104, DQM1 = 95
5439 12:15:05.564473 DQ Delay:
5440 12:15:05.567584 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5441 12:15:05.570669 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5442 12:15:05.574669 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5443 12:15:05.577942 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5444 12:15:05.578024
5445 12:15:05.578089
5446 12:15:05.578147 ==
5447 12:15:05.580705 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 12:15:05.584017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 12:15:05.587454 ==
5450 12:15:05.587536
5451 12:15:05.587605
5452 12:15:05.587664 TX Vref Scan disable
5453 12:15:05.590897 == TX Byte 0 ==
5454 12:15:05.594304 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5455 12:15:05.597722 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5456 12:15:05.601124 == TX Byte 1 ==
5457 12:15:05.604506 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5458 12:15:05.607784 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5459 12:15:05.611143 ==
5460 12:15:05.611251 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 12:15:05.618055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 12:15:05.618138 ==
5463 12:15:05.618202
5464 12:15:05.618261
5465 12:15:05.621224 TX Vref Scan disable
5466 12:15:05.621305 == TX Byte 0 ==
5467 12:15:05.627569 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5468 12:15:05.630922 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5469 12:15:05.631005 == TX Byte 1 ==
5470 12:15:05.637484 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5471 12:15:05.640781 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5472 12:15:05.640864
5473 12:15:05.640929 [DATLAT]
5474 12:15:05.644339 Freq=933, CH0 RK1
5475 12:15:05.644421
5476 12:15:05.644486 DATLAT Default: 0xb
5477 12:15:05.647804 0, 0xFFFF, sum = 0
5478 12:15:05.647887 1, 0xFFFF, sum = 0
5479 12:15:05.650573 2, 0xFFFF, sum = 0
5480 12:15:05.650656 3, 0xFFFF, sum = 0
5481 12:15:05.653952 4, 0xFFFF, sum = 0
5482 12:15:05.654036 5, 0xFFFF, sum = 0
5483 12:15:05.657327 6, 0xFFFF, sum = 0
5484 12:15:05.657410 7, 0xFFFF, sum = 0
5485 12:15:05.660618 8, 0xFFFF, sum = 0
5486 12:15:05.660703 9, 0xFFFF, sum = 0
5487 12:15:05.664462 10, 0x0, sum = 1
5488 12:15:05.664545 11, 0x0, sum = 2
5489 12:15:05.667560 12, 0x0, sum = 3
5490 12:15:05.667644 13, 0x0, sum = 4
5491 12:15:05.670747 best_step = 11
5492 12:15:05.670829
5493 12:15:05.670894 ==
5494 12:15:05.673949 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 12:15:05.677257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 12:15:05.677340 ==
5497 12:15:05.680412 RX Vref Scan: 0
5498 12:15:05.680494
5499 12:15:05.680559 RX Vref 0 -> 0, step: 1
5500 12:15:05.680619
5501 12:15:05.683713 RX Delay -45 -> 252, step: 4
5502 12:15:05.690841 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5503 12:15:05.694192 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5504 12:15:05.697562 iDelay=199, Bit 2, Center 100 (11 ~ 190) 180
5505 12:15:05.701114 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5506 12:15:05.704482 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5507 12:15:05.711214 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5508 12:15:05.714623 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5509 12:15:05.717986 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5510 12:15:05.720732 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5511 12:15:05.724162 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5512 12:15:05.727592 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5513 12:15:05.733937 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5514 12:15:05.737614 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5515 12:15:05.740774 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5516 12:15:05.744229 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5517 12:15:05.747491 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5518 12:15:05.750886 ==
5519 12:15:05.754178 Dram Type= 6, Freq= 0, CH_0, rank 1
5520 12:15:05.757604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 12:15:05.757690 ==
5522 12:15:05.757757 DQS Delay:
5523 12:15:05.761004 DQS0 = 0, DQS1 = 0
5524 12:15:05.761085 DQM Delay:
5525 12:15:05.764378 DQM0 = 104, DQM1 = 94
5526 12:15:05.764460 DQ Delay:
5527 12:15:05.767183 DQ0 =100, DQ1 =106, DQ2 =100, DQ3 =102
5528 12:15:05.770579 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5529 12:15:05.773827 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =86
5530 12:15:05.777528 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5531 12:15:05.777611
5532 12:15:05.777676
5533 12:15:05.787096 [DQSOSCAuto] RK1, (LSB)MR18= 0x26ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5534 12:15:05.787188 CH0 RK1: MR19=504, MR18=26FF
5535 12:15:05.794211 CH0_RK1: MR19=0x504, MR18=0x26FF, DQSOSC=409, MR23=63, INC=64, DEC=43
5536 12:15:05.797242 [RxdqsGatingPostProcess] freq 933
5537 12:15:05.803845 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5538 12:15:05.807217 best DQS0 dly(2T, 0.5T) = (0, 10)
5539 12:15:05.810648 best DQS1 dly(2T, 0.5T) = (0, 10)
5540 12:15:05.814106 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5541 12:15:05.817618 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5542 12:15:05.817695 best DQS0 dly(2T, 0.5T) = (0, 10)
5543 12:15:05.820395 best DQS1 dly(2T, 0.5T) = (0, 10)
5544 12:15:05.823935 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5545 12:15:05.827303 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5546 12:15:05.830830 Pre-setting of DQS Precalculation
5547 12:15:05.837419 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5548 12:15:05.837503 ==
5549 12:15:05.840692 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 12:15:05.843876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 12:15:05.843960 ==
5552 12:15:05.850380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 12:15:05.857046 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5554 12:15:05.860613 [CA 0] Center 36 (6~67) winsize 62
5555 12:15:05.863994 [CA 1] Center 36 (6~67) winsize 62
5556 12:15:05.867467 [CA 2] Center 34 (4~65) winsize 62
5557 12:15:05.870878 [CA 3] Center 34 (4~65) winsize 62
5558 12:15:05.873562 [CA 4] Center 34 (4~64) winsize 61
5559 12:15:05.873646 [CA 5] Center 33 (3~64) winsize 62
5560 12:15:05.873713
5561 12:15:05.880608 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5562 12:15:05.880694
5563 12:15:05.883831 [CATrainingPosCal] consider 1 rank data
5564 12:15:05.887022 u2DelayCellTimex100 = 270/100 ps
5565 12:15:05.890200 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 12:15:05.893449 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 12:15:05.896731 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5568 12:15:05.900236 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5569 12:15:05.903642 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5570 12:15:05.906732 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5571 12:15:05.906843
5572 12:15:05.910399 CA PerBit enable=1, Macro0, CA PI delay=33
5573 12:15:05.910482
5574 12:15:05.913770 [CBTSetCACLKResult] CA Dly = 33
5575 12:15:05.916580 CS Dly: 7 (0~38)
5576 12:15:05.916670 ==
5577 12:15:05.919993 Dram Type= 6, Freq= 0, CH_1, rank 1
5578 12:15:05.923438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 12:15:05.923521 ==
5580 12:15:05.929672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5581 12:15:05.936518 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5582 12:15:05.939821 [CA 0] Center 36 (6~67) winsize 62
5583 12:15:05.943005 [CA 1] Center 37 (6~68) winsize 63
5584 12:15:05.946350 [CA 2] Center 34 (4~65) winsize 62
5585 12:15:05.949801 [CA 3] Center 34 (4~65) winsize 62
5586 12:15:05.953311 [CA 4] Center 34 (4~65) winsize 62
5587 12:15:05.956618 [CA 5] Center 33 (3~64) winsize 62
5588 12:15:05.956700
5589 12:15:05.959766 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5590 12:15:05.959899
5591 12:15:05.963172 [CATrainingPosCal] consider 2 rank data
5592 12:15:05.965955 u2DelayCellTimex100 = 270/100 ps
5593 12:15:05.969404 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5594 12:15:05.972851 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5595 12:15:05.976326 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5596 12:15:05.979709 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5597 12:15:05.983053 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5598 12:15:05.986381 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5599 12:15:05.989069
5600 12:15:05.992396 CA PerBit enable=1, Macro0, CA PI delay=33
5601 12:15:05.992497
5602 12:15:05.995769 [CBTSetCACLKResult] CA Dly = 33
5603 12:15:05.995877 CS Dly: 8 (0~40)
5604 12:15:05.995950
5605 12:15:05.999008 ----->DramcWriteLeveling(PI) begin...
5606 12:15:05.999118 ==
5607 12:15:06.002176 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 12:15:06.006040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 12:15:06.009430 ==
5610 12:15:06.009512 Write leveling (Byte 0): 25 => 25
5611 12:15:06.012232 Write leveling (Byte 1): 27 => 27
5612 12:15:06.015447 DramcWriteLeveling(PI) end<-----
5613 12:15:06.015528
5614 12:15:06.015592 ==
5615 12:15:06.018860 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 12:15:06.025598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 12:15:06.025682 ==
5618 12:15:06.025747 [Gating] SW mode calibration
5619 12:15:06.035724 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5620 12:15:06.039259 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5621 12:15:06.045865 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 12:15:06.049241 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 12:15:06.052723 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 12:15:06.058881 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 12:15:06.062185 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 12:15:06.065416 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 12:15:06.069265 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5628 12:15:06.075309 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5629 12:15:06.078686 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 12:15:06.082066 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 12:15:06.088743 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 12:15:06.092048 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 12:15:06.095270 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 12:15:06.102001 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 12:15:06.105300 0 15 24 | B1->B0 | 2424 3433 | 0 1 | (0 0) (1 1)
5636 12:15:06.108458 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
5637 12:15:06.115731 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 12:15:06.118504 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 12:15:06.121949 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 12:15:06.128402 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 12:15:06.131704 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 12:15:06.135070 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 12:15:06.142002 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5644 12:15:06.145385 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5645 12:15:06.148799 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 12:15:06.155197 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 12:15:06.158666 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 12:15:06.162200 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 12:15:06.168292 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 12:15:06.171493 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 12:15:06.175226 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 12:15:06.181437 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 12:15:06.184825 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 12:15:06.188253 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 12:15:06.194957 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 12:15:06.198158 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 12:15:06.201492 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 12:15:06.208365 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5659 12:15:06.211620 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5660 12:15:06.214795 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5661 12:15:06.218067 Total UI for P1: 0, mck2ui 16
5662 12:15:06.221325 best dqsien dly found for B0: ( 1, 2, 22)
5663 12:15:06.225039 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 12:15:06.228452 Total UI for P1: 0, mck2ui 16
5665 12:15:06.231199 best dqsien dly found for B1: ( 1, 2, 24)
5666 12:15:06.234530 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5667 12:15:06.241266 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5668 12:15:06.241350
5669 12:15:06.244619 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5670 12:15:06.248057 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5671 12:15:06.251298 [Gating] SW calibration Done
5672 12:15:06.251421 ==
5673 12:15:06.254606 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 12:15:06.257994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 12:15:06.258079 ==
5676 12:15:06.261436 RX Vref Scan: 0
5677 12:15:06.261520
5678 12:15:06.261605 RX Vref 0 -> 0, step: 1
5679 12:15:06.261684
5680 12:15:06.264848 RX Delay -80 -> 252, step: 8
5681 12:15:06.268289 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5682 12:15:06.270977 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5683 12:15:06.277729 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5684 12:15:06.281649 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5685 12:15:06.284835 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5686 12:15:06.288093 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5687 12:15:06.291565 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5688 12:15:06.294990 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5689 12:15:06.301587 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5690 12:15:06.304843 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5691 12:15:06.308211 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5692 12:15:06.311034 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5693 12:15:06.314420 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5694 12:15:06.317834 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5695 12:15:06.324658 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5696 12:15:06.327934 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5697 12:15:06.328018 ==
5698 12:15:06.331093 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 12:15:06.334368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 12:15:06.334455 ==
5701 12:15:06.337746 DQS Delay:
5702 12:15:06.337828 DQS0 = 0, DQS1 = 0
5703 12:15:06.337894 DQM Delay:
5704 12:15:06.341035 DQM0 = 104, DQM1 = 99
5705 12:15:06.341117 DQ Delay:
5706 12:15:06.344390 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5707 12:15:06.347843 DQ4 =99, DQ5 =119, DQ6 =115, DQ7 =103
5708 12:15:06.351232 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5709 12:15:06.354619 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5710 12:15:06.354693
5711 12:15:06.357869
5712 12:15:06.357951 ==
5713 12:15:06.361142 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 12:15:06.364471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 12:15:06.364554 ==
5716 12:15:06.364648
5717 12:15:06.364709
5718 12:15:06.367843 TX Vref Scan disable
5719 12:15:06.367940 == TX Byte 0 ==
5720 12:15:06.374742 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5721 12:15:06.377490 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5722 12:15:06.377582 == TX Byte 1 ==
5723 12:15:06.384413 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5724 12:15:06.387570 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5725 12:15:06.387655 ==
5726 12:15:06.390815 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 12:15:06.394082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 12:15:06.394165 ==
5729 12:15:06.394231
5730 12:15:06.394302
5731 12:15:06.397469 TX Vref Scan disable
5732 12:15:06.400921 == TX Byte 0 ==
5733 12:15:06.404232 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5734 12:15:06.407579 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5735 12:15:06.410980 == TX Byte 1 ==
5736 12:15:06.414324 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5737 12:15:06.417867 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5738 12:15:06.418002
5739 12:15:06.421223 [DATLAT]
5740 12:15:06.421328 Freq=933, CH1 RK0
5741 12:15:06.421422
5742 12:15:06.424053 DATLAT Default: 0xd
5743 12:15:06.424127 0, 0xFFFF, sum = 0
5744 12:15:06.427233 1, 0xFFFF, sum = 0
5745 12:15:06.427311 2, 0xFFFF, sum = 0
5746 12:15:06.431075 3, 0xFFFF, sum = 0
5747 12:15:06.431223 4, 0xFFFF, sum = 0
5748 12:15:06.434420 5, 0xFFFF, sum = 0
5749 12:15:06.434535 6, 0xFFFF, sum = 0
5750 12:15:06.437514 7, 0xFFFF, sum = 0
5751 12:15:06.437643 8, 0xFFFF, sum = 0
5752 12:15:06.440848 9, 0xFFFF, sum = 0
5753 12:15:06.440932 10, 0x0, sum = 1
5754 12:15:06.444223 11, 0x0, sum = 2
5755 12:15:06.444310 12, 0x0, sum = 3
5756 12:15:06.447587 13, 0x0, sum = 4
5757 12:15:06.447671 best_step = 11
5758 12:15:06.447736
5759 12:15:06.447798 ==
5760 12:15:06.451024 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 12:15:06.457223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 12:15:06.457360 ==
5763 12:15:06.457430 RX Vref Scan: 1
5764 12:15:06.457492
5765 12:15:06.460616 RX Vref 0 -> 0, step: 1
5766 12:15:06.460719
5767 12:15:06.463957 RX Delay -45 -> 252, step: 4
5768 12:15:06.464096
5769 12:15:06.467888 Set Vref, RX VrefLevel [Byte0]: 54
5770 12:15:06.470551 [Byte1]: 48
5771 12:15:06.470640
5772 12:15:06.473849 Final RX Vref Byte 0 = 54 to rank0
5773 12:15:06.477137 Final RX Vref Byte 1 = 48 to rank0
5774 12:15:06.480519 Final RX Vref Byte 0 = 54 to rank1
5775 12:15:06.483907 Final RX Vref Byte 1 = 48 to rank1==
5776 12:15:06.487237 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 12:15:06.490677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 12:15:06.490764 ==
5779 12:15:06.493911 DQS Delay:
5780 12:15:06.493996 DQS0 = 0, DQS1 = 0
5781 12:15:06.494062 DQM Delay:
5782 12:15:06.497022 DQM0 = 103, DQM1 = 98
5783 12:15:06.497107 DQ Delay:
5784 12:15:06.500376 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5785 12:15:06.503794 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5786 12:15:06.507190 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =90
5787 12:15:06.510466 DQ12 =104, DQ13 =104, DQ14 =106, DQ15 =108
5788 12:15:06.510556
5789 12:15:06.513641
5790 12:15:06.520542 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5791 12:15:06.523911 CH1 RK0: MR19=505, MR18=1B32
5792 12:15:06.530784 CH1_RK0: MR19=0x505, MR18=0x1B32, DQSOSC=406, MR23=63, INC=65, DEC=43
5793 12:15:06.530870
5794 12:15:06.533476 ----->DramcWriteLeveling(PI) begin...
5795 12:15:06.533561 ==
5796 12:15:06.537119 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 12:15:06.540209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 12:15:06.540294 ==
5799 12:15:06.543394 Write leveling (Byte 0): 28 => 28
5800 12:15:06.547231 Write leveling (Byte 1): 28 => 28
5801 12:15:06.550668 DramcWriteLeveling(PI) end<-----
5802 12:15:06.550754
5803 12:15:06.550819 ==
5804 12:15:06.553340 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 12:15:06.556663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 12:15:06.556747 ==
5807 12:15:06.560105 [Gating] SW mode calibration
5808 12:15:06.566550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5809 12:15:06.573387 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5810 12:15:06.576807 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 12:15:06.580233 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 12:15:06.586471 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 12:15:06.589895 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 12:15:06.593325 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 12:15:06.600116 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 12:15:06.603335 0 14 24 | B1->B0 | 2e2e 3030 | 0 0 | (1 0) (1 0)
5817 12:15:06.606717 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (1 0)
5818 12:15:06.612964 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 12:15:06.616239 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 12:15:06.619653 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 12:15:06.626418 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 12:15:06.629746 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 12:15:06.633215 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 12:15:06.639897 0 15 24 | B1->B0 | 3434 2a2a | 0 1 | (0 0) (0 0)
5825 12:15:06.643196 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 12:15:06.646544 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 12:15:06.652927 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 12:15:06.656345 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 12:15:06.659560 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 12:15:06.666235 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 12:15:06.669636 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 12:15:06.672902 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5833 12:15:06.679843 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 12:15:06.683180 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 12:15:06.686685 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 12:15:06.689446 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 12:15:06.696218 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 12:15:06.699534 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 12:15:06.702871 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 12:15:06.709550 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 12:15:06.712693 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 12:15:06.716177 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 12:15:06.722960 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 12:15:06.726302 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 12:15:06.729699 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 12:15:06.735822 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 12:15:06.739339 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5848 12:15:06.742680 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5849 12:15:06.749374 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 12:15:06.752980 Total UI for P1: 0, mck2ui 16
5851 12:15:06.756248 best dqsien dly found for B0: ( 1, 2, 24)
5852 12:15:06.756333 Total UI for P1: 0, mck2ui 16
5853 12:15:06.762572 best dqsien dly found for B1: ( 1, 2, 22)
5854 12:15:06.765856 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5855 12:15:06.769208 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5856 12:15:06.769292
5857 12:15:06.772531 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5858 12:15:06.775856 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5859 12:15:06.778999 [Gating] SW calibration Done
5860 12:15:06.779119 ==
5861 12:15:06.782385 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 12:15:06.785749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 12:15:06.785849 ==
5864 12:15:06.789174 RX Vref Scan: 0
5865 12:15:06.789256
5866 12:15:06.789321 RX Vref 0 -> 0, step: 1
5867 12:15:06.789385
5868 12:15:06.792585 RX Delay -80 -> 252, step: 8
5869 12:15:06.795888 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5870 12:15:06.802810 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5871 12:15:06.806168 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5872 12:15:06.808942 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5873 12:15:06.812365 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5874 12:15:06.815638 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5875 12:15:06.819553 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5876 12:15:06.825422 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5877 12:15:06.829400 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5878 12:15:06.832141 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5879 12:15:06.835544 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5880 12:15:06.838967 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5881 12:15:06.842276 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5882 12:15:06.849001 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5883 12:15:06.852623 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5884 12:15:06.856086 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5885 12:15:06.856174 ==
5886 12:15:06.858889 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 12:15:06.862271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 12:15:06.862350 ==
5889 12:15:06.865673 DQS Delay:
5890 12:15:06.865749 DQS0 = 0, DQS1 = 0
5891 12:15:06.868933 DQM Delay:
5892 12:15:06.869007 DQM0 = 102, DQM1 = 98
5893 12:15:06.869069 DQ Delay:
5894 12:15:06.872111 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5895 12:15:06.875386 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5896 12:15:06.878665 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5897 12:15:06.885694 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5898 12:15:06.885791
5899 12:15:06.885860
5900 12:15:06.885933 ==
5901 12:15:06.888718 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 12:15:06.891897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 12:15:06.891984 ==
5904 12:15:06.892051
5905 12:15:06.892113
5906 12:15:06.895180 TX Vref Scan disable
5907 12:15:06.895282 == TX Byte 0 ==
5908 12:15:06.901872 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5909 12:15:06.905163 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5910 12:15:06.905251 == TX Byte 1 ==
5911 12:15:06.912092 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5912 12:15:06.915460 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5913 12:15:06.915545 ==
5914 12:15:06.918832 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 12:15:06.921453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 12:15:06.921569 ==
5917 12:15:06.924920
5918 12:15:06.925030
5919 12:15:06.925126 TX Vref Scan disable
5920 12:15:06.928201 == TX Byte 0 ==
5921 12:15:06.931526 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5922 12:15:06.937993 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5923 12:15:06.938080 == TX Byte 1 ==
5924 12:15:06.941454 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5925 12:15:06.948348 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5926 12:15:06.948434
5927 12:15:06.948502 [DATLAT]
5928 12:15:06.948563 Freq=933, CH1 RK1
5929 12:15:06.948624
5930 12:15:06.951881 DATLAT Default: 0xb
5931 12:15:06.951968 0, 0xFFFF, sum = 0
5932 12:15:06.954550 1, 0xFFFF, sum = 0
5933 12:15:06.958029 2, 0xFFFF, sum = 0
5934 12:15:06.958118 3, 0xFFFF, sum = 0
5935 12:15:06.961356 4, 0xFFFF, sum = 0
5936 12:15:06.961444 5, 0xFFFF, sum = 0
5937 12:15:06.964832 6, 0xFFFF, sum = 0
5938 12:15:06.964921 7, 0xFFFF, sum = 0
5939 12:15:06.968156 8, 0xFFFF, sum = 0
5940 12:15:06.968271 9, 0xFFFF, sum = 0
5941 12:15:06.971563 10, 0x0, sum = 1
5942 12:15:06.971652 11, 0x0, sum = 2
5943 12:15:06.974850 12, 0x0, sum = 3
5944 12:15:06.974939 13, 0x0, sum = 4
5945 12:15:06.975027 best_step = 11
5946 12:15:06.975130
5947 12:15:06.978031 ==
5948 12:15:06.981344 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 12:15:06.984578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 12:15:06.984673 ==
5951 12:15:06.984764 RX Vref Scan: 0
5952 12:15:06.984847
5953 12:15:06.987857 RX Vref 0 -> 0, step: 1
5954 12:15:06.987944
5955 12:15:06.991158 RX Delay -45 -> 252, step: 4
5956 12:15:06.997709 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5957 12:15:07.001066 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5958 12:15:07.004296 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5959 12:15:07.007744 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5960 12:15:07.011159 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5961 12:15:07.014705 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5962 12:15:07.020844 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5963 12:15:07.024355 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5964 12:15:07.027824 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5965 12:15:07.031180 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5966 12:15:07.034530 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5967 12:15:07.037811 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5968 12:15:07.044341 iDelay=203, Bit 12, Center 108 (23 ~ 194) 172
5969 12:15:07.047731 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5970 12:15:07.051114 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5971 12:15:07.054588 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5972 12:15:07.054695 ==
5973 12:15:07.057806 Dram Type= 6, Freq= 0, CH_1, rank 1
5974 12:15:07.064029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5975 12:15:07.064137 ==
5976 12:15:07.064246 DQS Delay:
5977 12:15:07.067507 DQS0 = 0, DQS1 = 0
5978 12:15:07.067588 DQM Delay:
5979 12:15:07.070936 DQM0 = 104, DQM1 = 99
5980 12:15:07.071041 DQ Delay:
5981 12:15:07.074354 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5982 12:15:07.077705 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5983 12:15:07.081178 DQ8 =90, DQ9 =90, DQ10 =100, DQ11 =92
5984 12:15:07.084491 DQ12 =108, DQ13 =106, DQ14 =104, DQ15 =108
5985 12:15:07.084602
5986 12:15:07.084706
5987 12:15:07.094381 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5988 12:15:07.094498 CH1 RK1: MR19=505, MR18=2E01
5989 12:15:07.100818 CH1_RK1: MR19=0x505, MR18=0x2E01, DQSOSC=407, MR23=63, INC=65, DEC=43
5990 12:15:07.104042 [RxdqsGatingPostProcess] freq 933
5991 12:15:07.110622 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5992 12:15:07.114043 best DQS0 dly(2T, 0.5T) = (0, 10)
5993 12:15:07.117499 best DQS1 dly(2T, 0.5T) = (0, 10)
5994 12:15:07.120876 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5995 12:15:07.124315 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5996 12:15:07.124425 best DQS0 dly(2T, 0.5T) = (0, 10)
5997 12:15:07.127102 best DQS1 dly(2T, 0.5T) = (0, 10)
5998 12:15:07.130502 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5999 12:15:07.133970 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6000 12:15:07.137351 Pre-setting of DQS Precalculation
6001 12:15:07.144009 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6002 12:15:07.150761 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6003 12:15:07.157356 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6004 12:15:07.157474
6005 12:15:07.157585
6006 12:15:07.160827 [Calibration Summary] 1866 Mbps
6007 12:15:07.160940 CH 0, Rank 0
6008 12:15:07.163573 SW Impedance : PASS
6009 12:15:07.166999 DUTY Scan : NO K
6010 12:15:07.167106 ZQ Calibration : PASS
6011 12:15:07.170479 Jitter Meter : NO K
6012 12:15:07.173929 CBT Training : PASS
6013 12:15:07.174036 Write leveling : PASS
6014 12:15:07.177253 RX DQS gating : PASS
6015 12:15:07.180575 RX DQ/DQS(RDDQC) : PASS
6016 12:15:07.180682 TX DQ/DQS : PASS
6017 12:15:07.184007 RX DATLAT : PASS
6018 12:15:07.187476 RX DQ/DQS(Engine): PASS
6019 12:15:07.187565 TX OE : NO K
6020 12:15:07.190139 All Pass.
6021 12:15:07.190216
6022 12:15:07.190318 CH 0, Rank 1
6023 12:15:07.193393 SW Impedance : PASS
6024 12:15:07.193480 DUTY Scan : NO K
6025 12:15:07.197176 ZQ Calibration : PASS
6026 12:15:07.200634 Jitter Meter : NO K
6027 12:15:07.200750 CBT Training : PASS
6028 12:15:07.203941 Write leveling : PASS
6029 12:15:07.204029 RX DQS gating : PASS
6030 12:15:07.207100 RX DQ/DQS(RDDQC) : PASS
6031 12:15:07.210461 TX DQ/DQS : PASS
6032 12:15:07.210550 RX DATLAT : PASS
6033 12:15:07.213630 RX DQ/DQS(Engine): PASS
6034 12:15:07.216860 TX OE : NO K
6035 12:15:07.216950 All Pass.
6036 12:15:07.217038
6037 12:15:07.217120 CH 1, Rank 0
6038 12:15:07.220172 SW Impedance : PASS
6039 12:15:07.223667 DUTY Scan : NO K
6040 12:15:07.223755 ZQ Calibration : PASS
6041 12:15:07.226945 Jitter Meter : NO K
6042 12:15:07.230312 CBT Training : PASS
6043 12:15:07.230400 Write leveling : PASS
6044 12:15:07.233884 RX DQS gating : PASS
6045 12:15:07.237201 RX DQ/DQS(RDDQC) : PASS
6046 12:15:07.237289 TX DQ/DQS : PASS
6047 12:15:07.239987 RX DATLAT : PASS
6048 12:15:07.243334 RX DQ/DQS(Engine): PASS
6049 12:15:07.243423 TX OE : NO K
6050 12:15:07.243511 All Pass.
6051 12:15:07.246782
6052 12:15:07.246869 CH 1, Rank 1
6053 12:15:07.250096 SW Impedance : PASS
6054 12:15:07.250183 DUTY Scan : NO K
6055 12:15:07.253506 ZQ Calibration : PASS
6056 12:15:07.256740 Jitter Meter : NO K
6057 12:15:07.256828 CBT Training : PASS
6058 12:15:07.259816 Write leveling : PASS
6059 12:15:07.259904 RX DQS gating : PASS
6060 12:15:07.263617 RX DQ/DQS(RDDQC) : PASS
6061 12:15:07.266805 TX DQ/DQS : PASS
6062 12:15:07.266893 RX DATLAT : PASS
6063 12:15:07.270235 RX DQ/DQS(Engine): PASS
6064 12:15:07.273007 TX OE : NO K
6065 12:15:07.273096 All Pass.
6066 12:15:07.273183
6067 12:15:07.276504 DramC Write-DBI off
6068 12:15:07.276591 PER_BANK_REFRESH: Hybrid Mode
6069 12:15:07.279781 TX_TRACKING: ON
6070 12:15:07.286493 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6071 12:15:07.293273 [FAST_K] Save calibration result to emmc
6072 12:15:07.296581 dramc_set_vcore_voltage set vcore to 650000
6073 12:15:07.296666 Read voltage for 400, 6
6074 12:15:07.299783 Vio18 = 0
6075 12:15:07.299897 Vcore = 650000
6076 12:15:07.300013 Vdram = 0
6077 12:15:07.302994 Vddq = 0
6078 12:15:07.303107 Vmddr = 0
6079 12:15:07.306730 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6080 12:15:07.313317 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6081 12:15:07.316699 MEM_TYPE=3, freq_sel=20
6082 12:15:07.319915 sv_algorithm_assistance_LP4_800
6083 12:15:07.323185 ============ PULL DRAM RESETB DOWN ============
6084 12:15:07.326556 ========== PULL DRAM RESETB DOWN end =========
6085 12:15:07.333356 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6086 12:15:07.336110 ===================================
6087 12:15:07.336196 LPDDR4 DRAM CONFIGURATION
6088 12:15:07.339435 ===================================
6089 12:15:07.342967 EX_ROW_EN[0] = 0x0
6090 12:15:07.343051 EX_ROW_EN[1] = 0x0
6091 12:15:07.346197 LP4Y_EN = 0x0
6092 12:15:07.346309 WORK_FSP = 0x0
6093 12:15:07.349753 WL = 0x2
6094 12:15:07.349860 RL = 0x2
6095 12:15:07.353118 BL = 0x2
6096 12:15:07.355909 RPST = 0x0
6097 12:15:07.356019 RD_PRE = 0x0
6098 12:15:07.359923 WR_PRE = 0x1
6099 12:15:07.360027 WR_PST = 0x0
6100 12:15:07.362608 DBI_WR = 0x0
6101 12:15:07.362694 DBI_RD = 0x0
6102 12:15:07.365901 OTF = 0x1
6103 12:15:07.369270 ===================================
6104 12:15:07.372494 ===================================
6105 12:15:07.372582 ANA top config
6106 12:15:07.376414 ===================================
6107 12:15:07.379851 DLL_ASYNC_EN = 0
6108 12:15:07.383128 ALL_SLAVE_EN = 1
6109 12:15:07.383213 NEW_RANK_MODE = 1
6110 12:15:07.386398 DLL_IDLE_MODE = 1
6111 12:15:07.389688 LP45_APHY_COMB_EN = 1
6112 12:15:07.393126 TX_ODT_DIS = 1
6113 12:15:07.393211 NEW_8X_MODE = 1
6114 12:15:07.395912 ===================================
6115 12:15:07.399243 ===================================
6116 12:15:07.402777 data_rate = 800
6117 12:15:07.406089 CKR = 1
6118 12:15:07.409360 DQ_P2S_RATIO = 4
6119 12:15:07.412545 ===================================
6120 12:15:07.415955 CA_P2S_RATIO = 4
6121 12:15:07.419239 DQ_CA_OPEN = 0
6122 12:15:07.419391 DQ_SEMI_OPEN = 1
6123 12:15:07.422971 CA_SEMI_OPEN = 1
6124 12:15:07.426241 CA_FULL_RATE = 0
6125 12:15:07.429414 DQ_CKDIV4_EN = 0
6126 12:15:07.432753 CA_CKDIV4_EN = 1
6127 12:15:07.436032 CA_PREDIV_EN = 0
6128 12:15:07.436148 PH8_DLY = 0
6129 12:15:07.439507 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6130 12:15:07.442902 DQ_AAMCK_DIV = 0
6131 12:15:07.446159 CA_AAMCK_DIV = 0
6132 12:15:07.449678 CA_ADMCK_DIV = 4
6133 12:15:07.453030 DQ_TRACK_CA_EN = 0
6134 12:15:07.453121 CA_PICK = 800
6135 12:15:07.455889 CA_MCKIO = 400
6136 12:15:07.459254 MCKIO_SEMI = 400
6137 12:15:07.462784 PLL_FREQ = 3016
6138 12:15:07.466156 DQ_UI_PI_RATIO = 32
6139 12:15:07.469568 CA_UI_PI_RATIO = 32
6140 12:15:07.472907 ===================================
6141 12:15:07.476357 ===================================
6142 12:15:07.479579 memory_type:LPDDR4
6143 12:15:07.479669 GP_NUM : 10
6144 12:15:07.482611 SRAM_EN : 1
6145 12:15:07.482697 MD32_EN : 0
6146 12:15:07.485972 ===================================
6147 12:15:07.489226 [ANA_INIT] >>>>>>>>>>>>>>
6148 12:15:07.492512 <<<<<< [CONFIGURE PHASE]: ANA_TX
6149 12:15:07.495932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6150 12:15:07.499500 ===================================
6151 12:15:07.502209 data_rate = 800,PCW = 0X7400
6152 12:15:07.505763 ===================================
6153 12:15:07.509140 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6154 12:15:07.512407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6155 12:15:07.526230 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6156 12:15:07.529534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6157 12:15:07.532741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6158 12:15:07.535897 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6159 12:15:07.539116 [ANA_INIT] flow start
6160 12:15:07.542383 [ANA_INIT] PLL >>>>>>>>
6161 12:15:07.542475 [ANA_INIT] PLL <<<<<<<<
6162 12:15:07.545840 [ANA_INIT] MIDPI >>>>>>>>
6163 12:15:07.549273 [ANA_INIT] MIDPI <<<<<<<<
6164 12:15:07.549389 [ANA_INIT] DLL >>>>>>>>
6165 12:15:07.552574 [ANA_INIT] flow end
6166 12:15:07.555990 ============ LP4 DIFF to SE enter ============
6167 12:15:07.559195 ============ LP4 DIFF to SE exit ============
6168 12:15:07.562614 [ANA_INIT] <<<<<<<<<<<<<
6169 12:15:07.566053 [Flow] Enable top DCM control >>>>>
6170 12:15:07.569331 [Flow] Enable top DCM control <<<<<
6171 12:15:07.572870 Enable DLL master slave shuffle
6172 12:15:07.579518 ==============================================================
6173 12:15:07.579638 Gating Mode config
6174 12:15:07.585585 ==============================================================
6175 12:15:07.585707 Config description:
6176 12:15:07.595990 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6177 12:15:07.602789 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6178 12:15:07.609559 SELPH_MODE 0: By rank 1: By Phase
6179 12:15:07.612299 ==============================================================
6180 12:15:07.615745 GAT_TRACK_EN = 0
6181 12:15:07.619188 RX_GATING_MODE = 2
6182 12:15:07.622673 RX_GATING_TRACK_MODE = 2
6183 12:15:07.626000 SELPH_MODE = 1
6184 12:15:07.629154 PICG_EARLY_EN = 1
6185 12:15:07.632578 VALID_LAT_VALUE = 1
6186 12:15:07.639123 ==============================================================
6187 12:15:07.642141 Enter into Gating configuration >>>>
6188 12:15:07.646144 Exit from Gating configuration <<<<
6189 12:15:07.646273 Enter into DVFS_PRE_config >>>>>
6190 12:15:07.658970 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6191 12:15:07.662368 Exit from DVFS_PRE_config <<<<<
6192 12:15:07.665836 Enter into PICG configuration >>>>
6193 12:15:07.669128 Exit from PICG configuration <<<<
6194 12:15:07.669254 [RX_INPUT] configuration >>>>>
6195 12:15:07.671949 [RX_INPUT] configuration <<<<<
6196 12:15:07.678795 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6197 12:15:07.685634 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6198 12:15:07.689123 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6199 12:15:07.695721 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6200 12:15:07.702224 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6201 12:15:07.708858 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6202 12:15:07.712175 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6203 12:15:07.715607 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6204 12:15:07.721748 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6205 12:15:07.725147 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6206 12:15:07.728620 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6207 12:15:07.732002 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6208 12:15:07.735246 ===================================
6209 12:15:07.738445 LPDDR4 DRAM CONFIGURATION
6210 12:15:07.741711 ===================================
6211 12:15:07.745069 EX_ROW_EN[0] = 0x0
6212 12:15:07.745201 EX_ROW_EN[1] = 0x0
6213 12:15:07.748318 LP4Y_EN = 0x0
6214 12:15:07.748478 WORK_FSP = 0x0
6215 12:15:07.751708 WL = 0x2
6216 12:15:07.751851 RL = 0x2
6217 12:15:07.755316 BL = 0x2
6218 12:15:07.755478 RPST = 0x0
6219 12:15:07.758800 RD_PRE = 0x0
6220 12:15:07.758937 WR_PRE = 0x1
6221 12:15:07.762248 WR_PST = 0x0
6222 12:15:07.765681 DBI_WR = 0x0
6223 12:15:07.765823 DBI_RD = 0x0
6224 12:15:07.769271 OTF = 0x1
6225 12:15:07.769380 ===================================
6226 12:15:07.775194 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6227 12:15:07.778689 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6228 12:15:07.781957 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6229 12:15:07.785420 ===================================
6230 12:15:07.788856 LPDDR4 DRAM CONFIGURATION
6231 12:15:07.792256 ===================================
6232 12:15:07.795563 EX_ROW_EN[0] = 0x10
6233 12:15:07.795668 EX_ROW_EN[1] = 0x0
6234 12:15:07.798883 LP4Y_EN = 0x0
6235 12:15:07.799004 WORK_FSP = 0x0
6236 12:15:07.802295 WL = 0x2
6237 12:15:07.802404 RL = 0x2
6238 12:15:07.805488 BL = 0x2
6239 12:15:07.805584 RPST = 0x0
6240 12:15:07.808707 RD_PRE = 0x0
6241 12:15:07.808826 WR_PRE = 0x1
6242 12:15:07.811824 WR_PST = 0x0
6243 12:15:07.811951 DBI_WR = 0x0
6244 12:15:07.815200 DBI_RD = 0x0
6245 12:15:07.815364 OTF = 0x1
6246 12:15:07.818592 ===================================
6247 12:15:07.825429 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6248 12:15:07.829653 nWR fixed to 30
6249 12:15:07.833534 [ModeRegInit_LP4] CH0 RK0
6250 12:15:07.833651 [ModeRegInit_LP4] CH0 RK1
6251 12:15:07.836300 [ModeRegInit_LP4] CH1 RK0
6252 12:15:07.839692 [ModeRegInit_LP4] CH1 RK1
6253 12:15:07.839802 match AC timing 19
6254 12:15:07.846331 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6255 12:15:07.849587 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6256 12:15:07.852921 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6257 12:15:07.859575 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6258 12:15:07.863338 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6259 12:15:07.863493 ==
6260 12:15:07.866782 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 12:15:07.870070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 12:15:07.870236 ==
6263 12:15:07.876165 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6264 12:15:07.882926 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6265 12:15:07.886289 [CA 0] Center 36 (8~64) winsize 57
6266 12:15:07.889634 [CA 1] Center 36 (8~64) winsize 57
6267 12:15:07.893044 [CA 2] Center 36 (8~64) winsize 57
6268 12:15:07.893191 [CA 3] Center 36 (8~64) winsize 57
6269 12:15:07.896385 [CA 4] Center 36 (8~64) winsize 57
6270 12:15:07.899806 [CA 5] Center 36 (8~64) winsize 57
6271 12:15:07.899968
6272 12:15:07.905969 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6273 12:15:07.906153
6274 12:15:07.909412 [CATrainingPosCal] consider 1 rank data
6275 12:15:07.912800 u2DelayCellTimex100 = 270/100 ps
6276 12:15:07.916012 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 12:15:07.919617 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 12:15:07.922861 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 12:15:07.925918 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 12:15:07.929275 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 12:15:07.932695 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 12:15:07.932838
6283 12:15:07.936025 CA PerBit enable=1, Macro0, CA PI delay=36
6284 12:15:07.936162
6285 12:15:07.939466 [CBTSetCACLKResult] CA Dly = 36
6286 12:15:07.942884 CS Dly: 1 (0~32)
6287 12:15:07.943016 ==
6288 12:15:07.946242 Dram Type= 6, Freq= 0, CH_0, rank 1
6289 12:15:07.949658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 12:15:07.949798 ==
6291 12:15:07.956230 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6292 12:15:07.962252 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6293 12:15:07.962418 [CA 0] Center 36 (8~64) winsize 57
6294 12:15:07.965591 [CA 1] Center 36 (8~64) winsize 57
6295 12:15:07.968924 [CA 2] Center 36 (8~64) winsize 57
6296 12:15:07.972203 [CA 3] Center 36 (8~64) winsize 57
6297 12:15:07.975405 [CA 4] Center 36 (8~64) winsize 57
6298 12:15:07.978647 [CA 5] Center 36 (8~64) winsize 57
6299 12:15:07.978792
6300 12:15:07.982053 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6301 12:15:07.982180
6302 12:15:07.985440 [CATrainingPosCal] consider 2 rank data
6303 12:15:07.988945 u2DelayCellTimex100 = 270/100 ps
6304 12:15:07.992366 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 12:15:07.998542 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 12:15:08.001983 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 12:15:08.005364 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 12:15:08.008635 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 12:15:08.012178 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 12:15:08.012338
6311 12:15:08.015561 CA PerBit enable=1, Macro0, CA PI delay=36
6312 12:15:08.015686
6313 12:15:08.019052 [CBTSetCACLKResult] CA Dly = 36
6314 12:15:08.019178 CS Dly: 1 (0~32)
6315 12:15:08.022378
6316 12:15:08.025823 ----->DramcWriteLeveling(PI) begin...
6317 12:15:08.025935 ==
6318 12:15:08.028867 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 12:15:08.032147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 12:15:08.032257 ==
6321 12:15:08.035336 Write leveling (Byte 0): 40 => 8
6322 12:15:08.038566 Write leveling (Byte 1): 40 => 8
6323 12:15:08.041972 DramcWriteLeveling(PI) end<-----
6324 12:15:08.042109
6325 12:15:08.042207 ==
6326 12:15:08.045272 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 12:15:08.048753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 12:15:08.048891 ==
6329 12:15:08.052223 [Gating] SW mode calibration
6330 12:15:08.058894 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6331 12:15:08.065608 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6332 12:15:08.068877 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6333 12:15:08.072206 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6334 12:15:08.075708 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 12:15:08.082213 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 12:15:08.085492 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 12:15:08.088949 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 12:15:08.095155 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 12:15:08.098626 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 12:15:08.102014 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 12:15:08.105492 Total UI for P1: 0, mck2ui 16
6342 12:15:08.108874 best dqsien dly found for B0: ( 0, 14, 24)
6343 12:15:08.112232 Total UI for P1: 0, mck2ui 16
6344 12:15:08.115014 best dqsien dly found for B1: ( 0, 14, 24)
6345 12:15:08.118458 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6346 12:15:08.121836 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6347 12:15:08.125331
6348 12:15:08.128689 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6349 12:15:08.132115 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6350 12:15:08.135277 [Gating] SW calibration Done
6351 12:15:08.135421 ==
6352 12:15:08.138731 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 12:15:08.142114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 12:15:08.142247 ==
6355 12:15:08.142348 RX Vref Scan: 0
6356 12:15:08.142444
6357 12:15:08.145284 RX Vref 0 -> 0, step: 1
6358 12:15:08.145400
6359 12:15:08.148469 RX Delay -410 -> 252, step: 16
6360 12:15:08.151948 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6361 12:15:08.158675 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6362 12:15:08.161477 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6363 12:15:08.164866 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6364 12:15:08.168582 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6365 12:15:08.175198 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6366 12:15:08.178181 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6367 12:15:08.181539 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6368 12:15:08.184777 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6369 12:15:08.191788 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6370 12:15:08.195195 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6371 12:15:08.198644 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6372 12:15:08.201284 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6373 12:15:08.208093 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6374 12:15:08.211495 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6375 12:15:08.214841 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6376 12:15:08.214967 ==
6377 12:15:08.218137 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 12:15:08.221607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 12:15:08.225149 ==
6380 12:15:08.225279 DQS Delay:
6381 12:15:08.225375 DQS0 = 27, DQS1 = 35
6382 12:15:08.228497 DQM Delay:
6383 12:15:08.228616 DQM0 = 9, DQM1 = 12
6384 12:15:08.231112 DQ Delay:
6385 12:15:08.231222 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6386 12:15:08.234693 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6387 12:15:08.237954 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6388 12:15:08.241230 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6389 12:15:08.241355
6390 12:15:08.241452
6391 12:15:08.241549 ==
6392 12:15:08.245067 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 12:15:08.251663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 12:15:08.251813 ==
6395 12:15:08.251914
6396 12:15:08.252006
6397 12:15:08.252098 TX Vref Scan disable
6398 12:15:08.254822 == TX Byte 0 ==
6399 12:15:08.257918 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 12:15:08.261474 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 12:15:08.264904 == TX Byte 1 ==
6402 12:15:08.268349 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 12:15:08.271691 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 12:15:08.275068 ==
6405 12:15:08.275192 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 12:15:08.281534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 12:15:08.281698 ==
6408 12:15:08.281812
6409 12:15:08.281917
6410 12:15:08.284921 TX Vref Scan disable
6411 12:15:08.285063 == TX Byte 0 ==
6412 12:15:08.288084 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6413 12:15:08.294632 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6414 12:15:08.294796 == TX Byte 1 ==
6415 12:15:08.297892 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 12:15:08.304770 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 12:15:08.304905
6418 12:15:08.304972 [DATLAT]
6419 12:15:08.305040 Freq=400, CH0 RK0
6420 12:15:08.305101
6421 12:15:08.307539 DATLAT Default: 0xf
6422 12:15:08.307628 0, 0xFFFF, sum = 0
6423 12:15:08.310903 1, 0xFFFF, sum = 0
6424 12:15:08.310995 2, 0xFFFF, sum = 0
6425 12:15:08.314307 3, 0xFFFF, sum = 0
6426 12:15:08.314413 4, 0xFFFF, sum = 0
6427 12:15:08.317669 5, 0xFFFF, sum = 0
6428 12:15:08.321051 6, 0xFFFF, sum = 0
6429 12:15:08.321152 7, 0xFFFF, sum = 0
6430 12:15:08.324428 8, 0xFFFF, sum = 0
6431 12:15:08.324524 9, 0xFFFF, sum = 0
6432 12:15:08.327872 10, 0xFFFF, sum = 0
6433 12:15:08.327970 11, 0xFFFF, sum = 0
6434 12:15:08.331261 12, 0xFFFF, sum = 0
6435 12:15:08.331366 13, 0x0, sum = 1
6436 12:15:08.334790 14, 0x0, sum = 2
6437 12:15:08.334884 15, 0x0, sum = 3
6438 12:15:08.337538 16, 0x0, sum = 4
6439 12:15:08.337628 best_step = 14
6440 12:15:08.337697
6441 12:15:08.337766 ==
6442 12:15:08.340883 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 12:15:08.344286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 12:15:08.344390 ==
6445 12:15:08.347648 RX Vref Scan: 1
6446 12:15:08.347743
6447 12:15:08.350885 RX Vref 0 -> 0, step: 1
6448 12:15:08.350988
6449 12:15:08.351058 RX Delay -311 -> 252, step: 8
6450 12:15:08.354011
6451 12:15:08.354131 Set Vref, RX VrefLevel [Byte0]: 56
6452 12:15:08.357252 [Byte1]: 49
6453 12:15:08.363104
6454 12:15:08.363240 Final RX Vref Byte 0 = 56 to rank0
6455 12:15:08.366573 Final RX Vref Byte 1 = 49 to rank0
6456 12:15:08.370080 Final RX Vref Byte 0 = 56 to rank1
6457 12:15:08.373402 Final RX Vref Byte 1 = 49 to rank1==
6458 12:15:08.376155 Dram Type= 6, Freq= 0, CH_0, rank 0
6459 12:15:08.382981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 12:15:08.383151 ==
6461 12:15:08.383257 DQS Delay:
6462 12:15:08.386179 DQS0 = 28, DQS1 = 36
6463 12:15:08.386312 DQM Delay:
6464 12:15:08.386420 DQM0 = 11, DQM1 = 13
6465 12:15:08.389591 DQ Delay:
6466 12:15:08.392931 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6467 12:15:08.393063 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6468 12:15:08.396062 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6469 12:15:08.399474 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6470 12:15:08.399606
6471 12:15:08.402744
6472 12:15:08.409492 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6473 12:15:08.412864 CH0 RK0: MR19=C0C, MR18=CBB8
6474 12:15:08.419624 CH0_RK0: MR19=0xC0C, MR18=0xCBB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6475 12:15:08.419798 ==
6476 12:15:08.422965 Dram Type= 6, Freq= 0, CH_0, rank 1
6477 12:15:08.426304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 12:15:08.426441 ==
6479 12:15:08.429121 [Gating] SW mode calibration
6480 12:15:08.435869 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6481 12:15:08.442610 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6482 12:15:08.446045 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6483 12:15:08.449495 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6484 12:15:08.455999 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 12:15:08.459131 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 12:15:08.462932 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 12:15:08.466158 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 12:15:08.472835 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 12:15:08.476226 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 12:15:08.479022 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 12:15:08.482369 Total UI for P1: 0, mck2ui 16
6492 12:15:08.485869 best dqsien dly found for B0: ( 0, 14, 24)
6493 12:15:08.489212 Total UI for P1: 0, mck2ui 16
6494 12:15:08.492502 best dqsien dly found for B1: ( 0, 14, 24)
6495 12:15:08.495682 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6496 12:15:08.502401 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6497 12:15:08.502600
6498 12:15:08.505708 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6499 12:15:08.509037 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6500 12:15:08.512201 [Gating] SW calibration Done
6501 12:15:08.512355 ==
6502 12:15:08.515595 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 12:15:08.518953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 12:15:08.519115 ==
6505 12:15:08.519236 RX Vref Scan: 0
6506 12:15:08.522379
6507 12:15:08.522516 RX Vref 0 -> 0, step: 1
6508 12:15:08.522630
6509 12:15:08.525942 RX Delay -410 -> 252, step: 16
6510 12:15:08.529162 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6511 12:15:08.536087 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6512 12:15:08.539403 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6513 12:15:08.542771 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6514 12:15:08.546223 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6515 12:15:08.552254 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6516 12:15:08.555679 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6517 12:15:08.559139 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6518 12:15:08.562521 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6519 12:15:08.565814 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6520 12:15:08.572808 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6521 12:15:08.575958 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6522 12:15:08.579128 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6523 12:15:08.585962 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6524 12:15:08.588727 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6525 12:15:08.592832 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6526 12:15:08.592986 ==
6527 12:15:08.595556 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 12:15:08.599496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 12:15:08.599636 ==
6530 12:15:08.602582 DQS Delay:
6531 12:15:08.602691 DQS0 = 27, DQS1 = 35
6532 12:15:08.605814 DQM Delay:
6533 12:15:08.605957 DQM0 = 12, DQM1 = 12
6534 12:15:08.609214 DQ Delay:
6535 12:15:08.609337 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6536 12:15:08.612567 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6537 12:15:08.615827 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6538 12:15:08.619138 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6539 12:15:08.619279
6540 12:15:08.619388
6541 12:15:08.619473 ==
6542 12:15:08.622573 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 12:15:08.628698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 12:15:08.628832 ==
6545 12:15:08.628928
6546 12:15:08.629011
6547 12:15:08.629091 TX Vref Scan disable
6548 12:15:08.632153 == TX Byte 0 ==
6549 12:15:08.635355 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6550 12:15:08.638757 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6551 12:15:08.642221 == TX Byte 1 ==
6552 12:15:08.645584 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6553 12:15:08.649035 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6554 12:15:08.651796 ==
6555 12:15:08.651902 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 12:15:08.658610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 12:15:08.658740 ==
6558 12:15:08.658846
6559 12:15:08.658953
6560 12:15:08.661970 TX Vref Scan disable
6561 12:15:08.662061 == TX Byte 0 ==
6562 12:15:08.665395 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6563 12:15:08.672216 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6564 12:15:08.672361 == TX Byte 1 ==
6565 12:15:08.675590 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6566 12:15:08.678844 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6567 12:15:08.682002
6568 12:15:08.682155 [DATLAT]
6569 12:15:08.682259 Freq=400, CH0 RK1
6570 12:15:08.682359
6571 12:15:08.685252 DATLAT Default: 0xe
6572 12:15:08.685398 0, 0xFFFF, sum = 0
6573 12:15:08.688568 1, 0xFFFF, sum = 0
6574 12:15:08.688703 2, 0xFFFF, sum = 0
6575 12:15:08.692006 3, 0xFFFF, sum = 0
6576 12:15:08.692140 4, 0xFFFF, sum = 0
6577 12:15:08.695400 5, 0xFFFF, sum = 0
6578 12:15:08.695525 6, 0xFFFF, sum = 0
6579 12:15:08.698737 7, 0xFFFF, sum = 0
6580 12:15:08.702225 8, 0xFFFF, sum = 0
6581 12:15:08.702378 9, 0xFFFF, sum = 0
6582 12:15:08.704908 10, 0xFFFF, sum = 0
6583 12:15:08.705029 11, 0xFFFF, sum = 0
6584 12:15:08.708233 12, 0xFFFF, sum = 0
6585 12:15:08.708360 13, 0x0, sum = 1
6586 12:15:08.711973 14, 0x0, sum = 2
6587 12:15:08.712120 15, 0x0, sum = 3
6588 12:15:08.715406 16, 0x0, sum = 4
6589 12:15:08.715533 best_step = 14
6590 12:15:08.715632
6591 12:15:08.715726 ==
6592 12:15:08.718534 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 12:15:08.721828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 12:15:08.721961 ==
6595 12:15:08.725155 RX Vref Scan: 0
6596 12:15:08.725280
6597 12:15:08.728551 RX Vref 0 -> 0, step: 1
6598 12:15:08.728686
6599 12:15:08.728790 RX Delay -311 -> 252, step: 8
6600 12:15:08.736781 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6601 12:15:08.740176 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6602 12:15:08.743606 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6603 12:15:08.746952 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6604 12:15:08.753759 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6605 12:15:08.757088 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6606 12:15:08.760401 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6607 12:15:08.763944 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6608 12:15:08.770602 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6609 12:15:08.773868 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6610 12:15:08.777323 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6611 12:15:08.780036 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6612 12:15:08.787238 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6613 12:15:08.790018 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6614 12:15:08.793276 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6615 12:15:08.800062 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6616 12:15:08.800194 ==
6617 12:15:08.803385 Dram Type= 6, Freq= 0, CH_0, rank 1
6618 12:15:08.806790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 12:15:08.806898 ==
6620 12:15:08.806975 DQS Delay:
6621 12:15:08.810169 DQS0 = 24, DQS1 = 32
6622 12:15:08.810293 DQM Delay:
6623 12:15:08.813587 DQM0 = 7, DQM1 = 10
6624 12:15:08.813684 DQ Delay:
6625 12:15:08.816750 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6626 12:15:08.820016 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6627 12:15:08.823367 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6628 12:15:08.826710 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =16
6629 12:15:08.826830
6630 12:15:08.826931
6631 12:15:08.833159 [DQSOSCAuto] RK1, (LSB)MR18= 0xb758, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6632 12:15:08.836635 CH0 RK1: MR19=C0C, MR18=B758
6633 12:15:08.843274 CH0_RK1: MR19=0xC0C, MR18=0xB758, DQSOSC=387, MR23=63, INC=394, DEC=262
6634 12:15:08.846732 [RxdqsGatingPostProcess] freq 400
6635 12:15:08.850189 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6636 12:15:08.853562 best DQS0 dly(2T, 0.5T) = (0, 10)
6637 12:15:08.856888 best DQS1 dly(2T, 0.5T) = (0, 10)
6638 12:15:08.860271 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6639 12:15:08.863619 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6640 12:15:08.866397 best DQS0 dly(2T, 0.5T) = (0, 10)
6641 12:15:08.869846 best DQS1 dly(2T, 0.5T) = (0, 10)
6642 12:15:08.873398 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6643 12:15:08.876966 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6644 12:15:08.880342 Pre-setting of DQS Precalculation
6645 12:15:08.883172 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6646 12:15:08.886418 ==
6647 12:15:08.886529 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 12:15:08.893108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 12:15:08.893254 ==
6650 12:15:08.896962 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6651 12:15:08.903471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6652 12:15:08.906995 [CA 0] Center 36 (8~64) winsize 57
6653 12:15:08.909763 [CA 1] Center 36 (8~64) winsize 57
6654 12:15:08.913122 [CA 2] Center 36 (8~64) winsize 57
6655 12:15:08.916561 [CA 3] Center 36 (8~64) winsize 57
6656 12:15:08.919991 [CA 4] Center 36 (8~64) winsize 57
6657 12:15:08.923205 [CA 5] Center 36 (8~64) winsize 57
6658 12:15:08.923337
6659 12:15:08.926510 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6660 12:15:08.926610
6661 12:15:08.929972 [CATrainingPosCal] consider 1 rank data
6662 12:15:08.933318 u2DelayCellTimex100 = 270/100 ps
6663 12:15:08.936548 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 12:15:08.939810 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 12:15:08.943117 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 12:15:08.946495 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 12:15:08.949848 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 12:15:08.953271 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 12:15:08.956608
6670 12:15:08.959933 CA PerBit enable=1, Macro0, CA PI delay=36
6671 12:15:08.960037
6672 12:15:08.963289 [CBTSetCACLKResult] CA Dly = 36
6673 12:15:08.963409 CS Dly: 1 (0~32)
6674 12:15:08.963482 ==
6675 12:15:08.966069 Dram Type= 6, Freq= 0, CH_1, rank 1
6676 12:15:08.969451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 12:15:08.969583 ==
6678 12:15:08.976087 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6679 12:15:08.983014 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6680 12:15:08.986529 [CA 0] Center 36 (8~64) winsize 57
6681 12:15:08.989958 [CA 1] Center 36 (8~64) winsize 57
6682 12:15:08.992643 [CA 2] Center 36 (8~64) winsize 57
6683 12:15:08.996043 [CA 3] Center 36 (8~64) winsize 57
6684 12:15:08.999373 [CA 4] Center 36 (8~64) winsize 57
6685 12:15:09.002633 [CA 5] Center 36 (8~64) winsize 57
6686 12:15:09.002808
6687 12:15:09.006464 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6688 12:15:09.006627
6689 12:15:09.009587 [CATrainingPosCal] consider 2 rank data
6690 12:15:09.012736 u2DelayCellTimex100 = 270/100 ps
6691 12:15:09.016235 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 12:15:09.019588 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 12:15:09.023084 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 12:15:09.025830 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 12:15:09.029841 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 12:15:09.032870 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 12:15:09.033019
6698 12:15:09.036268 CA PerBit enable=1, Macro0, CA PI delay=36
6699 12:15:09.036402
6700 12:15:09.039465 [CBTSetCACLKResult] CA Dly = 36
6701 12:15:09.042774 CS Dly: 1 (0~32)
6702 12:15:09.042885
6703 12:15:09.045982 ----->DramcWriteLeveling(PI) begin...
6704 12:15:09.046077 ==
6705 12:15:09.049238 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 12:15:09.052493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 12:15:09.052622 ==
6708 12:15:09.055838 Write leveling (Byte 0): 40 => 8
6709 12:15:09.059207 Write leveling (Byte 1): 40 => 8
6710 12:15:09.062791 DramcWriteLeveling(PI) end<-----
6711 12:15:09.062929
6712 12:15:09.063029 ==
6713 12:15:09.066190 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 12:15:09.069596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 12:15:09.069726 ==
6716 12:15:09.072991 [Gating] SW mode calibration
6717 12:15:09.079155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6718 12:15:09.085855 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6719 12:15:09.089304 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6720 12:15:09.092668 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6721 12:15:09.099420 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 12:15:09.102781 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 12:15:09.106117 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 12:15:09.112496 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 12:15:09.116325 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 12:15:09.119611 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 12:15:09.125720 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 12:15:09.125915 Total UI for P1: 0, mck2ui 16
6729 12:15:09.132510 best dqsien dly found for B0: ( 0, 14, 24)
6730 12:15:09.132727 Total UI for P1: 0, mck2ui 16
6731 12:15:09.139131 best dqsien dly found for B1: ( 0, 14, 24)
6732 12:15:09.142406 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6733 12:15:09.145831 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6734 12:15:09.145976
6735 12:15:09.149016 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6736 12:15:09.152852 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6737 12:15:09.156073 [Gating] SW calibration Done
6738 12:15:09.156208 ==
6739 12:15:09.159255 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 12:15:09.162531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 12:15:09.162646 ==
6742 12:15:09.165740 RX Vref Scan: 0
6743 12:15:09.165891
6744 12:15:09.165992 RX Vref 0 -> 0, step: 1
6745 12:15:09.166085
6746 12:15:09.169230 RX Delay -410 -> 252, step: 16
6747 12:15:09.176006 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6748 12:15:09.179357 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6749 12:15:09.182792 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6750 12:15:09.186224 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6751 12:15:09.192289 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6752 12:15:09.195766 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6753 12:15:09.199124 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6754 12:15:09.202557 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6755 12:15:09.209435 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6756 12:15:09.212314 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6757 12:15:09.215535 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6758 12:15:09.218877 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6759 12:15:09.225488 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6760 12:15:09.228881 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6761 12:15:09.232378 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6762 12:15:09.235833 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6763 12:15:09.239204 ==
6764 12:15:09.239353 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 12:15:09.245397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 12:15:09.245555 ==
6767 12:15:09.245661 DQS Delay:
6768 12:15:09.248771 DQS0 = 27, DQS1 = 35
6769 12:15:09.248903 DQM Delay:
6770 12:15:09.252100 DQM0 = 11, DQM1 = 12
6771 12:15:09.252221 DQ Delay:
6772 12:15:09.255418 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6773 12:15:09.258764 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6774 12:15:09.261995 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6775 12:15:09.265420 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6776 12:15:09.265561
6777 12:15:09.265663
6778 12:15:09.265760 ==
6779 12:15:09.268557 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 12:15:09.272538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 12:15:09.272684 ==
6782 12:15:09.272787
6783 12:15:09.272883
6784 12:15:09.275668 TX Vref Scan disable
6785 12:15:09.275786 == TX Byte 0 ==
6786 12:15:09.282354 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 12:15:09.285249 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 12:15:09.285387 == TX Byte 1 ==
6789 12:15:09.292040 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 12:15:09.295332 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 12:15:09.295475 ==
6792 12:15:09.298799 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 12:15:09.302161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 12:15:09.302301 ==
6795 12:15:09.302408
6796 12:15:09.302506
6797 12:15:09.305636 TX Vref Scan disable
6798 12:15:09.305738 == TX Byte 0 ==
6799 12:15:09.312279 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6800 12:15:09.315088 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6801 12:15:09.315218 == TX Byte 1 ==
6802 12:15:09.321883 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 12:15:09.325177 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 12:15:09.325291
6805 12:15:09.325359 [DATLAT]
6806 12:15:09.328894 Freq=400, CH1 RK0
6807 12:15:09.329022
6808 12:15:09.329099 DATLAT Default: 0xf
6809 12:15:09.332224 0, 0xFFFF, sum = 0
6810 12:15:09.332320 1, 0xFFFF, sum = 0
6811 12:15:09.335621 2, 0xFFFF, sum = 0
6812 12:15:09.335718 3, 0xFFFF, sum = 0
6813 12:15:09.338321 4, 0xFFFF, sum = 0
6814 12:15:09.338460 5, 0xFFFF, sum = 0
6815 12:15:09.341778 6, 0xFFFF, sum = 0
6816 12:15:09.341901 7, 0xFFFF, sum = 0
6817 12:15:09.345208 8, 0xFFFF, sum = 0
6818 12:15:09.345324 9, 0xFFFF, sum = 0
6819 12:15:09.348748 10, 0xFFFF, sum = 0
6820 12:15:09.351876 11, 0xFFFF, sum = 0
6821 12:15:09.351970 12, 0xFFFF, sum = 0
6822 12:15:09.355061 13, 0x0, sum = 1
6823 12:15:09.355182 14, 0x0, sum = 2
6824 12:15:09.355281 15, 0x0, sum = 3
6825 12:15:09.358323 16, 0x0, sum = 4
6826 12:15:09.358406 best_step = 14
6827 12:15:09.358471
6828 12:15:09.358532 ==
6829 12:15:09.361534 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 12:15:09.368304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 12:15:09.368437 ==
6832 12:15:09.368506 RX Vref Scan: 1
6833 12:15:09.368569
6834 12:15:09.371735 RX Vref 0 -> 0, step: 1
6835 12:15:09.371830
6836 12:15:09.375134 RX Delay -311 -> 252, step: 8
6837 12:15:09.375266
6838 12:15:09.378443 Set Vref, RX VrefLevel [Byte0]: 54
6839 12:15:09.381421 [Byte1]: 48
6840 12:15:09.385284
6841 12:15:09.385396 Final RX Vref Byte 0 = 54 to rank0
6842 12:15:09.388483 Final RX Vref Byte 1 = 48 to rank0
6843 12:15:09.391954 Final RX Vref Byte 0 = 54 to rank1
6844 12:15:09.394710 Final RX Vref Byte 1 = 48 to rank1==
6845 12:15:09.398062 Dram Type= 6, Freq= 0, CH_1, rank 0
6846 12:15:09.404785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 12:15:09.404935 ==
6848 12:15:09.405005 DQS Delay:
6849 12:15:09.408255 DQS0 = 28, DQS1 = 32
6850 12:15:09.408354 DQM Delay:
6851 12:15:09.408431 DQM0 = 10, DQM1 = 11
6852 12:15:09.411640 DQ Delay:
6853 12:15:09.414927 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6854 12:15:09.415059 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6855 12:15:09.418284 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6856 12:15:09.421600 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6857 12:15:09.421732
6858 12:15:09.421803
6859 12:15:09.430979 [DQSOSCAuto] RK0, (LSB)MR18= 0x8bc3, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6860 12:15:09.434867 CH1 RK0: MR19=C0C, MR18=8BC3
6861 12:15:09.441379 CH1_RK0: MR19=0xC0C, MR18=0x8BC3, DQSOSC=385, MR23=63, INC=398, DEC=265
6862 12:15:09.441527 ==
6863 12:15:09.444645 Dram Type= 6, Freq= 0, CH_1, rank 1
6864 12:15:09.448116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 12:15:09.448248 ==
6866 12:15:09.451476 [Gating] SW mode calibration
6867 12:15:09.457586 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6868 12:15:09.461477 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6869 12:15:09.468085 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6870 12:15:09.471414 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6871 12:15:09.474172 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 12:15:09.480902 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 12:15:09.484298 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 12:15:09.487519 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 12:15:09.494606 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 12:15:09.497872 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 12:15:09.501077 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 12:15:09.504413 Total UI for P1: 0, mck2ui 16
6879 12:15:09.507857 best dqsien dly found for B0: ( 0, 14, 24)
6880 12:15:09.511213 Total UI for P1: 0, mck2ui 16
6881 12:15:09.514734 best dqsien dly found for B1: ( 0, 14, 24)
6882 12:15:09.517414 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6883 12:15:09.521472 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6884 12:15:09.521629
6885 12:15:09.527719 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6886 12:15:09.531165 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6887 12:15:09.534524 [Gating] SW calibration Done
6888 12:15:09.534647 ==
6889 12:15:09.537859 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 12:15:09.541102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 12:15:09.541252 ==
6892 12:15:09.541358 RX Vref Scan: 0
6893 12:15:09.541453
6894 12:15:09.544258 RX Vref 0 -> 0, step: 1
6895 12:15:09.544387
6896 12:15:09.547587 RX Delay -410 -> 252, step: 16
6897 12:15:09.550839 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6898 12:15:09.557759 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6899 12:15:09.560624 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6900 12:15:09.564006 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6901 12:15:09.567885 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6902 12:15:09.574325 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6903 12:15:09.577587 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6904 12:15:09.581024 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6905 12:15:09.584445 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6906 12:15:09.587793 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6907 12:15:09.594053 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6908 12:15:09.597472 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6909 12:15:09.600834 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6910 12:15:09.607209 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6911 12:15:09.610389 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6912 12:15:09.613887 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6913 12:15:09.614036 ==
6914 12:15:09.617277 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 12:15:09.620775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 12:15:09.624228 ==
6917 12:15:09.624380 DQS Delay:
6918 12:15:09.624484 DQS0 = 35, DQS1 = 35
6919 12:15:09.627641 DQM Delay:
6920 12:15:09.627769 DQM0 = 18, DQM1 = 13
6921 12:15:09.630938 DQ Delay:
6922 12:15:09.631071 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6923 12:15:09.633685 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6924 12:15:09.637162 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6925 12:15:09.640587 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6926 12:15:09.640735
6927 12:15:09.640836
6928 12:15:09.643986 ==
6929 12:15:09.647137 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 12:15:09.650559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 12:15:09.650722 ==
6932 12:15:09.650827
6933 12:15:09.650922
6934 12:15:09.653851 TX Vref Scan disable
6935 12:15:09.653972 == TX Byte 0 ==
6936 12:15:09.656872 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6937 12:15:09.663668 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6938 12:15:09.663842 == TX Byte 1 ==
6939 12:15:09.666987 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6940 12:15:09.670508 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6941 12:15:09.673782 ==
6942 12:15:09.677071 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 12:15:09.680995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 12:15:09.681122 ==
6945 12:15:09.681197
6946 12:15:09.681259
6947 12:15:09.684232 TX Vref Scan disable
6948 12:15:09.684339 == TX Byte 0 ==
6949 12:15:09.686853 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6950 12:15:09.693610 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6951 12:15:09.693757 == TX Byte 1 ==
6952 12:15:09.697011 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6953 12:15:09.703825 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6954 12:15:09.703974
6955 12:15:09.704051 [DATLAT]
6956 12:15:09.704116 Freq=400, CH1 RK1
6957 12:15:09.704179
6958 12:15:09.706889 DATLAT Default: 0xe
6959 12:15:09.707045 0, 0xFFFF, sum = 0
6960 12:15:09.710666 1, 0xFFFF, sum = 0
6961 12:15:09.710843 2, 0xFFFF, sum = 0
6962 12:15:09.713932 3, 0xFFFF, sum = 0
6963 12:15:09.717171 4, 0xFFFF, sum = 0
6964 12:15:09.717356 5, 0xFFFF, sum = 0
6965 12:15:09.720436 6, 0xFFFF, sum = 0
6966 12:15:09.720601 7, 0xFFFF, sum = 0
6967 12:15:09.723823 8, 0xFFFF, sum = 0
6968 12:15:09.724006 9, 0xFFFF, sum = 0
6969 12:15:09.727189 10, 0xFFFF, sum = 0
6970 12:15:09.727372 11, 0xFFFF, sum = 0
6971 12:15:09.730581 12, 0xFFFF, sum = 0
6972 12:15:09.730774 13, 0x0, sum = 1
6973 12:15:09.734015 14, 0x0, sum = 2
6974 12:15:09.734186 15, 0x0, sum = 3
6975 12:15:09.736833 16, 0x0, sum = 4
6976 12:15:09.736999 best_step = 14
6977 12:15:09.737127
6978 12:15:09.737254 ==
6979 12:15:09.740126 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 12:15:09.743601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 12:15:09.746903 ==
6982 12:15:09.747078 RX Vref Scan: 0
6983 12:15:09.747212
6984 12:15:09.750311 RX Vref 0 -> 0, step: 1
6985 12:15:09.750465
6986 12:15:09.753579 RX Delay -311 -> 252, step: 8
6987 12:15:09.756777 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6988 12:15:09.763039 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6989 12:15:09.766435 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6990 12:15:09.769760 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6991 12:15:09.773224 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6992 12:15:09.780029 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6993 12:15:09.783175 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6994 12:15:09.786567 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6995 12:15:09.789799 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6996 12:15:09.796184 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6997 12:15:09.799510 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6998 12:15:09.802789 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6999 12:15:09.806249 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7000 12:15:09.812943 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7001 12:15:09.816422 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7002 12:15:09.819724 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
7003 12:15:09.819843 ==
7004 12:15:09.822992 Dram Type= 6, Freq= 0, CH_1, rank 1
7005 12:15:09.829563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7006 12:15:09.829699 ==
7007 12:15:09.829770 DQS Delay:
7008 12:15:09.832909 DQS0 = 28, DQS1 = 32
7009 12:15:09.833003 DQM Delay:
7010 12:15:09.836291 DQM0 = 11, DQM1 = 11
7011 12:15:09.836408 DQ Delay:
7012 12:15:09.839718 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =4
7013 12:15:09.842412 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
7014 12:15:09.842533 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7015 12:15:09.849222 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7016 12:15:09.849368
7017 12:15:09.849436
7018 12:15:09.856011 [DQSOSCAuto] RK1, (LSB)MR18= 0xc758, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7019 12:15:09.859305 CH1 RK1: MR19=C0C, MR18=C758
7020 12:15:09.865563 CH1_RK1: MR19=0xC0C, MR18=0xC758, DQSOSC=385, MR23=63, INC=398, DEC=265
7021 12:15:09.868884 [RxdqsGatingPostProcess] freq 400
7022 12:15:09.872210 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7023 12:15:09.875707 best DQS0 dly(2T, 0.5T) = (0, 10)
7024 12:15:09.879140 best DQS1 dly(2T, 0.5T) = (0, 10)
7025 12:15:09.882418 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7026 12:15:09.885750 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7027 12:15:09.889005 best DQS0 dly(2T, 0.5T) = (0, 10)
7028 12:15:09.892217 best DQS1 dly(2T, 0.5T) = (0, 10)
7029 12:15:09.895346 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7030 12:15:09.898696 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7031 12:15:09.901832 Pre-setting of DQS Precalculation
7032 12:15:09.905169 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7033 12:15:09.915383 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7034 12:15:09.922198 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7035 12:15:09.922376
7036 12:15:09.922474
7037 12:15:09.925670 [Calibration Summary] 800 Mbps
7038 12:15:09.925808 CH 0, Rank 0
7039 12:15:09.928994 SW Impedance : PASS
7040 12:15:09.929139 DUTY Scan : NO K
7041 12:15:09.932290 ZQ Calibration : PASS
7042 12:15:09.935515 Jitter Meter : NO K
7043 12:15:09.935679 CBT Training : PASS
7044 12:15:09.938707 Write leveling : PASS
7045 12:15:09.941983 RX DQS gating : PASS
7046 12:15:09.942109 RX DQ/DQS(RDDQC) : PASS
7047 12:15:09.945265 TX DQ/DQS : PASS
7048 12:15:09.945382 RX DATLAT : PASS
7049 12:15:09.948845 RX DQ/DQS(Engine): PASS
7050 12:15:09.952213 TX OE : NO K
7051 12:15:09.952345 All Pass.
7052 12:15:09.952415
7053 12:15:09.952476 CH 0, Rank 1
7054 12:15:09.955639 SW Impedance : PASS
7055 12:15:09.958941 DUTY Scan : NO K
7056 12:15:09.959071 ZQ Calibration : PASS
7057 12:15:09.962327 Jitter Meter : NO K
7058 12:15:09.965766 CBT Training : PASS
7059 12:15:09.965905 Write leveling : NO K
7060 12:15:09.968463 RX DQS gating : PASS
7061 12:15:09.972050 RX DQ/DQS(RDDQC) : PASS
7062 12:15:09.972185 TX DQ/DQS : PASS
7063 12:15:09.975315 RX DATLAT : PASS
7064 12:15:09.978549 RX DQ/DQS(Engine): PASS
7065 12:15:09.978686 TX OE : NO K
7066 12:15:09.981926 All Pass.
7067 12:15:09.982051
7068 12:15:09.982119 CH 1, Rank 0
7069 12:15:09.985279 SW Impedance : PASS
7070 12:15:09.985397 DUTY Scan : NO K
7071 12:15:09.988588 ZQ Calibration : PASS
7072 12:15:09.991964 Jitter Meter : NO K
7073 12:15:09.992133 CBT Training : PASS
7074 12:15:09.995255 Write leveling : PASS
7075 12:15:09.995406 RX DQS gating : PASS
7076 12:15:09.998552 RX DQ/DQS(RDDQC) : PASS
7077 12:15:10.002273 TX DQ/DQS : PASS
7078 12:15:10.002411 RX DATLAT : PASS
7079 12:15:10.005662 RX DQ/DQS(Engine): PASS
7080 12:15:10.008893 TX OE : NO K
7081 12:15:10.009034 All Pass.
7082 12:15:10.009106
7083 12:15:10.009168 CH 1, Rank 1
7084 12:15:10.012104 SW Impedance : PASS
7085 12:15:10.015563 DUTY Scan : NO K
7086 12:15:10.015725 ZQ Calibration : PASS
7087 12:15:10.018949 Jitter Meter : NO K
7088 12:15:10.022233 CBT Training : PASS
7089 12:15:10.022388 Write leveling : NO K
7090 12:15:10.025798 RX DQS gating : PASS
7091 12:15:10.028534 RX DQ/DQS(RDDQC) : PASS
7092 12:15:10.028688 TX DQ/DQS : PASS
7093 12:15:10.031826 RX DATLAT : PASS
7094 12:15:10.031980 RX DQ/DQS(Engine): PASS
7095 12:15:10.035170 TX OE : NO K
7096 12:15:10.035316 All Pass.
7097 12:15:10.035405
7098 12:15:10.038480 DramC Write-DBI off
7099 12:15:10.041779 PER_BANK_REFRESH: Hybrid Mode
7100 12:15:10.041914 TX_TRACKING: ON
7101 12:15:10.052148 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7102 12:15:10.055586 [FAST_K] Save calibration result to emmc
7103 12:15:10.058289 dramc_set_vcore_voltage set vcore to 725000
7104 12:15:10.061733 Read voltage for 1600, 0
7105 12:15:10.061945 Vio18 = 0
7106 12:15:10.065290 Vcore = 725000
7107 12:15:10.065505 Vdram = 0
7108 12:15:10.065627 Vddq = 0
7109 12:15:10.065761 Vmddr = 0
7110 12:15:10.071998 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7111 12:15:10.078520 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7112 12:15:10.078756 MEM_TYPE=3, freq_sel=13
7113 12:15:10.081905 sv_algorithm_assistance_LP4_3733
7114 12:15:10.085183 ============ PULL DRAM RESETB DOWN ============
7115 12:15:10.091925 ========== PULL DRAM RESETB DOWN end =========
7116 12:15:10.095237 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7117 12:15:10.098717 ===================================
7118 12:15:10.101947 LPDDR4 DRAM CONFIGURATION
7119 12:15:10.104705 ===================================
7120 12:15:10.104889 EX_ROW_EN[0] = 0x0
7121 12:15:10.108505 EX_ROW_EN[1] = 0x0
7122 12:15:10.108640 LP4Y_EN = 0x0
7123 12:15:10.111881 WORK_FSP = 0x1
7124 12:15:10.112046 WL = 0x5
7125 12:15:10.115068 RL = 0x5
7126 12:15:10.115189 BL = 0x2
7127 12:15:10.118310 RPST = 0x0
7128 12:15:10.121663 RD_PRE = 0x0
7129 12:15:10.121824 WR_PRE = 0x1
7130 12:15:10.124954 WR_PST = 0x1
7131 12:15:10.125076 DBI_WR = 0x0
7132 12:15:10.128447 DBI_RD = 0x0
7133 12:15:10.128567 OTF = 0x1
7134 12:15:10.131809 ===================================
7135 12:15:10.135198 ===================================
7136 12:15:10.137985 ANA top config
7137 12:15:10.141328 ===================================
7138 12:15:10.141488 DLL_ASYNC_EN = 0
7139 12:15:10.144783 ALL_SLAVE_EN = 0
7140 12:15:10.148233 NEW_RANK_MODE = 1
7141 12:15:10.151451 DLL_IDLE_MODE = 1
7142 12:15:10.151579 LP45_APHY_COMB_EN = 1
7143 12:15:10.154715 TX_ODT_DIS = 0
7144 12:15:10.157952 NEW_8X_MODE = 1
7145 12:15:10.161826 ===================================
7146 12:15:10.164666 ===================================
7147 12:15:10.167970 data_rate = 3200
7148 12:15:10.171319 CKR = 1
7149 12:15:10.171473 DQ_P2S_RATIO = 8
7150 12:15:10.174869 ===================================
7151 12:15:10.178330 CA_P2S_RATIO = 8
7152 12:15:10.181734 DQ_CA_OPEN = 0
7153 12:15:10.184875 DQ_SEMI_OPEN = 0
7154 12:15:10.188129 CA_SEMI_OPEN = 0
7155 12:15:10.191396 CA_FULL_RATE = 0
7156 12:15:10.191535 DQ_CKDIV4_EN = 0
7157 12:15:10.194729 CA_CKDIV4_EN = 0
7158 12:15:10.198204 CA_PREDIV_EN = 0
7159 12:15:10.201556 PH8_DLY = 12
7160 12:15:10.204805 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7161 12:15:10.208185 DQ_AAMCK_DIV = 4
7162 12:15:10.208340 CA_AAMCK_DIV = 4
7163 12:15:10.211582 CA_ADMCK_DIV = 4
7164 12:15:10.214851 DQ_TRACK_CA_EN = 0
7165 12:15:10.218096 CA_PICK = 1600
7166 12:15:10.221269 CA_MCKIO = 1600
7167 12:15:10.224626 MCKIO_SEMI = 0
7168 12:15:10.227815 PLL_FREQ = 3068
7169 12:15:10.231277 DQ_UI_PI_RATIO = 32
7170 12:15:10.231427 CA_UI_PI_RATIO = 0
7171 12:15:10.234565 ===================================
7172 12:15:10.238023 ===================================
7173 12:15:10.241549 memory_type:LPDDR4
7174 12:15:10.244219 GP_NUM : 10
7175 12:15:10.244385 SRAM_EN : 1
7176 12:15:10.247667 MD32_EN : 0
7177 12:15:10.251018 ===================================
7178 12:15:10.254441 [ANA_INIT] >>>>>>>>>>>>>>
7179 12:15:10.257559 <<<<<< [CONFIGURE PHASE]: ANA_TX
7180 12:15:10.261292 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7181 12:15:10.264581 ===================================
7182 12:15:10.264713 data_rate = 3200,PCW = 0X7600
7183 12:15:10.267864 ===================================
7184 12:15:10.271129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7185 12:15:10.277235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7186 12:15:10.284287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7187 12:15:10.287559 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7188 12:15:10.290839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7189 12:15:10.294171 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7190 12:15:10.297442 [ANA_INIT] flow start
7191 12:15:10.297575 [ANA_INIT] PLL >>>>>>>>
7192 12:15:10.300736 [ANA_INIT] PLL <<<<<<<<
7193 12:15:10.304523 [ANA_INIT] MIDPI >>>>>>>>
7194 12:15:10.307620 [ANA_INIT] MIDPI <<<<<<<<
7195 12:15:10.307790 [ANA_INIT] DLL >>>>>>>>
7196 12:15:10.311036 [ANA_INIT] DLL <<<<<<<<
7197 12:15:10.311203 [ANA_INIT] flow end
7198 12:15:10.317687 ============ LP4 DIFF to SE enter ============
7199 12:15:10.320949 ============ LP4 DIFF to SE exit ============
7200 12:15:10.324106 [ANA_INIT] <<<<<<<<<<<<<
7201 12:15:10.327281 [Flow] Enable top DCM control >>>>>
7202 12:15:10.330956 [Flow] Enable top DCM control <<<<<
7203 12:15:10.334041 Enable DLL master slave shuffle
7204 12:15:10.337382 ==============================================================
7205 12:15:10.340726 Gating Mode config
7206 12:15:10.344154 ==============================================================
7207 12:15:10.347373 Config description:
7208 12:15:10.357544 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7209 12:15:10.364174 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7210 12:15:10.367273 SELPH_MODE 0: By rank 1: By Phase
7211 12:15:10.373720 ==============================================================
7212 12:15:10.376953 GAT_TRACK_EN = 1
7213 12:15:10.380390 RX_GATING_MODE = 2
7214 12:15:10.383764 RX_GATING_TRACK_MODE = 2
7215 12:15:10.387149 SELPH_MODE = 1
7216 12:15:10.390457 PICG_EARLY_EN = 1
7217 12:15:10.390627 VALID_LAT_VALUE = 1
7218 12:15:10.397110 ==============================================================
7219 12:15:10.400256 Enter into Gating configuration >>>>
7220 12:15:10.403486 Exit from Gating configuration <<<<
7221 12:15:10.407283 Enter into DVFS_PRE_config >>>>>
7222 12:15:10.417285 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7223 12:15:10.420646 Exit from DVFS_PRE_config <<<<<
7224 12:15:10.424007 Enter into PICG configuration >>>>
7225 12:15:10.427361 Exit from PICG configuration <<<<
7226 12:15:10.430424 [RX_INPUT] configuration >>>>>
7227 12:15:10.433706 [RX_INPUT] configuration <<<<<
7228 12:15:10.437357 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7229 12:15:10.443751 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7230 12:15:10.450415 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7231 12:15:10.457058 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7232 12:15:10.463848 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7233 12:15:10.470392 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7234 12:15:10.473627 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7235 12:15:10.477158 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7236 12:15:10.479716 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7237 12:15:10.486837 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7238 12:15:10.490198 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7239 12:15:10.493652 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7240 12:15:10.497031 ===================================
7241 12:15:10.500186 LPDDR4 DRAM CONFIGURATION
7242 12:15:10.503486 ===================================
7243 12:15:10.503651 EX_ROW_EN[0] = 0x0
7244 12:15:10.506723 EX_ROW_EN[1] = 0x0
7245 12:15:10.506901 LP4Y_EN = 0x0
7246 12:15:10.509773 WORK_FSP = 0x1
7247 12:15:10.509929 WL = 0x5
7248 12:15:10.513429 RL = 0x5
7249 12:15:10.516729 BL = 0x2
7250 12:15:10.516913 RPST = 0x0
7251 12:15:10.519796 RD_PRE = 0x0
7252 12:15:10.519945 WR_PRE = 0x1
7253 12:15:10.523013 WR_PST = 0x1
7254 12:15:10.523178 DBI_WR = 0x0
7255 12:15:10.526957 DBI_RD = 0x0
7256 12:15:10.527136 OTF = 0x1
7257 12:15:10.529622 ===================================
7258 12:15:10.532986 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7259 12:15:10.540009 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7260 12:15:10.543104 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7261 12:15:10.546709 ===================================
7262 12:15:10.549935 LPDDR4 DRAM CONFIGURATION
7263 12:15:10.553134 ===================================
7264 12:15:10.553269 EX_ROW_EN[0] = 0x10
7265 12:15:10.557028 EX_ROW_EN[1] = 0x0
7266 12:15:10.557149 LP4Y_EN = 0x0
7267 12:15:10.559744 WORK_FSP = 0x1
7268 12:15:10.559844 WL = 0x5
7269 12:15:10.563124 RL = 0x5
7270 12:15:10.563283 BL = 0x2
7271 12:15:10.566470 RPST = 0x0
7272 12:15:10.566591 RD_PRE = 0x0
7273 12:15:10.570511 WR_PRE = 0x1
7274 12:15:10.570638 WR_PST = 0x1
7275 12:15:10.573797 DBI_WR = 0x0
7276 12:15:10.573999 DBI_RD = 0x0
7277 12:15:10.577089 OTF = 0x1
7278 12:15:10.580308 ===================================
7279 12:15:10.586758 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7280 12:15:10.586996 ==
7281 12:15:10.590589 Dram Type= 6, Freq= 0, CH_0, rank 0
7282 12:15:10.593298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7283 12:15:10.593489 ==
7284 12:15:10.596773 [Duty_Offset_Calibration]
7285 12:15:10.596959 B0:2 B1:1 CA:1
7286 12:15:10.597097
7287 12:15:10.599966 [DutyScan_Calibration_Flow] k_type=0
7288 12:15:10.610825
7289 12:15:10.611062 ==CLK 0==
7290 12:15:10.614657 Final CLK duty delay cell = 0
7291 12:15:10.617833 [0] MAX Duty = 5187%(X100), DQS PI = 22
7292 12:15:10.621118 [0] MIN Duty = 4876%(X100), DQS PI = 48
7293 12:15:10.621251 [0] AVG Duty = 5031%(X100)
7294 12:15:10.624576
7295 12:15:10.624721 CH0 CLK Duty spec in!! Max-Min= 311%
7296 12:15:10.631344 [DutyScan_Calibration_Flow] ====Done====
7297 12:15:10.631507
7298 12:15:10.634519 [DutyScan_Calibration_Flow] k_type=1
7299 12:15:10.650381
7300 12:15:10.650548 ==DQS 0 ==
7301 12:15:10.653654 Final DQS duty delay cell = -4
7302 12:15:10.656853 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7303 12:15:10.659987 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7304 12:15:10.663138 [-4] AVG Duty = 4891%(X100)
7305 12:15:10.663267
7306 12:15:10.663379 ==DQS 1 ==
7307 12:15:10.666533 Final DQS duty delay cell = 0
7308 12:15:10.669802 [0] MAX Duty = 5187%(X100), DQS PI = 20
7309 12:15:10.673699 [0] MIN Duty = 5031%(X100), DQS PI = 52
7310 12:15:10.676460 [0] AVG Duty = 5109%(X100)
7311 12:15:10.676597
7312 12:15:10.679814 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7313 12:15:10.679954
7314 12:15:10.683180 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7315 12:15:10.687053 [DutyScan_Calibration_Flow] ====Done====
7316 12:15:10.687206
7317 12:15:10.690294 [DutyScan_Calibration_Flow] k_type=3
7318 12:15:10.707140
7319 12:15:10.707320 ==DQM 0 ==
7320 12:15:10.710399 Final DQM duty delay cell = 0
7321 12:15:10.713128 [0] MAX Duty = 5187%(X100), DQS PI = 28
7322 12:15:10.717085 [0] MIN Duty = 4907%(X100), DQS PI = 0
7323 12:15:10.720371 [0] AVG Duty = 5047%(X100)
7324 12:15:10.720533
7325 12:15:10.720645 ==DQM 1 ==
7326 12:15:10.723712 Final DQM duty delay cell = -4
7327 12:15:10.726907 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7328 12:15:10.729847 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7329 12:15:10.733601 [-4] AVG Duty = 4906%(X100)
7330 12:15:10.733752
7331 12:15:10.736778 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7332 12:15:10.736887
7333 12:15:10.739871 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7334 12:15:10.743603 [DutyScan_Calibration_Flow] ====Done====
7335 12:15:10.743744
7336 12:15:10.746971 [DutyScan_Calibration_Flow] k_type=2
7337 12:15:10.764252
7338 12:15:10.764465 ==DQ 0 ==
7339 12:15:10.768226 Final DQ duty delay cell = 0
7340 12:15:10.771519 [0] MAX Duty = 5062%(X100), DQS PI = 24
7341 12:15:10.774180 [0] MIN Duty = 4907%(X100), DQS PI = 0
7342 12:15:10.774333 [0] AVG Duty = 4984%(X100)
7343 12:15:10.774408
7344 12:15:10.777522 ==DQ 1 ==
7345 12:15:10.780850 Final DQ duty delay cell = 0
7346 12:15:10.784758 [0] MAX Duty = 5124%(X100), DQS PI = 22
7347 12:15:10.787536 [0] MIN Duty = 4938%(X100), DQS PI = 36
7348 12:15:10.787704 [0] AVG Duty = 5031%(X100)
7349 12:15:10.787813
7350 12:15:10.790748 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7351 12:15:10.790918
7352 12:15:10.794164 CH0 DQ 1 Duty spec in!! Max-Min= 186%
7353 12:15:10.801108 [DutyScan_Calibration_Flow] ====Done====
7354 12:15:10.801304 ==
7355 12:15:10.804279 Dram Type= 6, Freq= 0, CH_1, rank 0
7356 12:15:10.808229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7357 12:15:10.808420 ==
7358 12:15:10.810840 [Duty_Offset_Calibration]
7359 12:15:10.810974 B0:1 B1:0 CA:0
7360 12:15:10.811080
7361 12:15:10.814164 [DutyScan_Calibration_Flow] k_type=0
7362 12:15:10.824048
7363 12:15:10.824240 ==CLK 0==
7364 12:15:10.827206 Final CLK duty delay cell = -4
7365 12:15:10.830571 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7366 12:15:10.833829 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7367 12:15:10.837110 [-4] AVG Duty = 4922%(X100)
7368 12:15:10.837279
7369 12:15:10.840230 CH1 CLK Duty spec in!! Max-Min= 156%
7370 12:15:10.843415 [DutyScan_Calibration_Flow] ====Done====
7371 12:15:10.843579
7372 12:15:10.847132 [DutyScan_Calibration_Flow] k_type=1
7373 12:15:10.863961
7374 12:15:10.864163 ==DQS 0 ==
7375 12:15:10.867074 Final DQS duty delay cell = 0
7376 12:15:10.870044 [0] MAX Duty = 5094%(X100), DQS PI = 16
7377 12:15:10.873914 [0] MIN Duty = 4875%(X100), DQS PI = 0
7378 12:15:10.876655 [0] AVG Duty = 4984%(X100)
7379 12:15:10.876821
7380 12:15:10.876926 ==DQS 1 ==
7381 12:15:10.880565 Final DQS duty delay cell = 0
7382 12:15:10.883123 [0] MAX Duty = 5249%(X100), DQS PI = 16
7383 12:15:10.887069 [0] MIN Duty = 4938%(X100), DQS PI = 8
7384 12:15:10.890442 [0] AVG Duty = 5093%(X100)
7385 12:15:10.890601
7386 12:15:10.893623 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7387 12:15:10.893754
7388 12:15:10.896851 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7389 12:15:10.900201 [DutyScan_Calibration_Flow] ====Done====
7390 12:15:10.900347
7391 12:15:10.903559 [DutyScan_Calibration_Flow] k_type=3
7392 12:15:10.920903
7393 12:15:10.921105 ==DQM 0 ==
7394 12:15:10.923626 Final DQM duty delay cell = 0
7395 12:15:10.927050 [0] MAX Duty = 5187%(X100), DQS PI = 8
7396 12:15:10.930309 [0] MIN Duty = 4969%(X100), DQS PI = 48
7397 12:15:10.934244 [0] AVG Duty = 5078%(X100)
7398 12:15:10.934397
7399 12:15:10.934494 ==DQM 1 ==
7400 12:15:10.936888 Final DQM duty delay cell = 0
7401 12:15:10.940154 [0] MAX Duty = 5093%(X100), DQS PI = 18
7402 12:15:10.943952 [0] MIN Duty = 4907%(X100), DQS PI = 52
7403 12:15:10.947057 [0] AVG Duty = 5000%(X100)
7404 12:15:10.947207
7405 12:15:10.950266 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7406 12:15:10.950414
7407 12:15:10.954002 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7408 12:15:10.957255 [DutyScan_Calibration_Flow] ====Done====
7409 12:15:10.957397
7410 12:15:10.960433 [DutyScan_Calibration_Flow] k_type=2
7411 12:15:10.976644
7412 12:15:10.976830 ==DQ 0 ==
7413 12:15:10.980175 Final DQ duty delay cell = -4
7414 12:15:10.983192 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7415 12:15:10.986417 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7416 12:15:10.989744 [-4] AVG Duty = 4968%(X100)
7417 12:15:10.989855
7418 12:15:10.989920 ==DQ 1 ==
7419 12:15:10.993191 Final DQ duty delay cell = 0
7420 12:15:10.996544 [0] MAX Duty = 5093%(X100), DQS PI = 16
7421 12:15:10.999788 [0] MIN Duty = 4938%(X100), DQS PI = 8
7422 12:15:11.003068 [0] AVG Duty = 5015%(X100)
7423 12:15:11.003214
7424 12:15:11.006568 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7425 12:15:11.006689
7426 12:15:11.009940 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7427 12:15:11.013133 [DutyScan_Calibration_Flow] ====Done====
7428 12:15:11.016384 nWR fixed to 30
7429 12:15:11.016499 [ModeRegInit_LP4] CH0 RK0
7430 12:15:11.020106 [ModeRegInit_LP4] CH0 RK1
7431 12:15:11.023173 [ModeRegInit_LP4] CH1 RK0
7432 12:15:11.026634 [ModeRegInit_LP4] CH1 RK1
7433 12:15:11.026750 match AC timing 5
7434 12:15:11.033576 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7435 12:15:11.036115 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7436 12:15:11.039408 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7437 12:15:11.046103 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7438 12:15:11.049476 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7439 12:15:11.049635 [MiockJmeterHQA]
7440 12:15:11.049708
7441 12:15:11.052715 [DramcMiockJmeter] u1RxGatingPI = 0
7442 12:15:11.056472 0 : 4253, 4026
7443 12:15:11.056603 4 : 4252, 4027
7444 12:15:11.059551 8 : 4253, 4027
7445 12:15:11.059694 12 : 4365, 4140
7446 12:15:11.059765 16 : 4253, 4026
7447 12:15:11.062776 20 : 4252, 4027
7448 12:15:11.062877 24 : 4252, 4027
7449 12:15:11.066535 28 : 4255, 4029
7450 12:15:11.066655 32 : 4252, 4026
7451 12:15:11.069841 36 : 4253, 4027
7452 12:15:11.069954 40 : 4366, 4140
7453 12:15:11.073031 44 : 4250, 4027
7454 12:15:11.073141 48 : 4255, 4029
7455 12:15:11.073209 52 : 4250, 4027
7456 12:15:11.076379 56 : 4360, 4138
7457 12:15:11.076504 60 : 4250, 4027
7458 12:15:11.079671 64 : 4361, 4138
7459 12:15:11.079785 68 : 4253, 4026
7460 12:15:11.082856 72 : 4250, 4027
7461 12:15:11.082970 76 : 4250, 4027
7462 12:15:11.086067 80 : 4253, 4029
7463 12:15:11.086208 84 : 4360, 4137
7464 12:15:11.086318 88 : 4253, 78
7465 12:15:11.089251 92 : 4361, 0
7466 12:15:11.089386 96 : 4250, 0
7467 12:15:11.089499 100 : 4250, 0
7468 12:15:11.093032 104 : 4253, 0
7469 12:15:11.093183 108 : 4250, 0
7470 12:15:11.096257 112 : 4250, 0
7471 12:15:11.096407 116 : 4252, 0
7472 12:15:11.096509 120 : 4250, 0
7473 12:15:11.099564 124 : 4250, 0
7474 12:15:11.099682 128 : 4252, 0
7475 12:15:11.103084 132 : 4360, 0
7476 12:15:11.103237 136 : 4250, 0
7477 12:15:11.103365 140 : 4250, 0
7478 12:15:11.105674 144 : 4250, 0
7479 12:15:11.105802 148 : 4360, 0
7480 12:15:11.109018 152 : 4361, 0
7481 12:15:11.109139 156 : 4250, 0
7482 12:15:11.109208 160 : 4250, 0
7483 12:15:11.112928 164 : 4250, 0
7484 12:15:11.113089 168 : 4252, 0
7485 12:15:11.116144 172 : 4250, 0
7486 12:15:11.116278 176 : 4250, 0
7487 12:15:11.116388 180 : 4252, 0
7488 12:15:11.119687 184 : 4360, 0
7489 12:15:11.119799 188 : 4250, 0
7490 12:15:11.119876 192 : 4250, 0
7491 12:15:11.122882 196 : 4250, 0
7492 12:15:11.122993 200 : 4360, 0
7493 12:15:11.125990 204 : 4361, 1593
7494 12:15:11.126092 208 : 4360, 4127
7495 12:15:11.129166 212 : 4250, 4027
7496 12:15:11.129272 216 : 4250, 4027
7497 12:15:11.132249 220 : 4253, 4029
7498 12:15:11.132356 224 : 4250, 4027
7499 12:15:11.132429 228 : 4250, 4027
7500 12:15:11.135996 232 : 4250, 4026
7501 12:15:11.136112 236 : 4253, 4029
7502 12:15:11.139507 240 : 4250, 4027
7503 12:15:11.139631 244 : 4360, 4137
7504 12:15:11.142921 248 : 4360, 4137
7505 12:15:11.143050 252 : 4248, 4025
7506 12:15:11.146162 256 : 4363, 4140
7507 12:15:11.146274 260 : 4360, 4137
7508 12:15:11.148934 264 : 4250, 4027
7509 12:15:11.149046 268 : 4250, 4026
7510 12:15:11.152378 272 : 4253, 4029
7511 12:15:11.152512 276 : 4250, 4027
7512 12:15:11.155817 280 : 4250, 4027
7513 12:15:11.155944 284 : 4250, 4026
7514 12:15:11.159152 288 : 4253, 4029
7515 12:15:11.159267 292 : 4250, 4027
7516 12:15:11.159355 296 : 4360, 4137
7517 12:15:11.162348 300 : 4360, 4137
7518 12:15:11.162451 304 : 4250, 4027
7519 12:15:11.165564 308 : 4363, 4051
7520 12:15:11.165695 312 : 4360, 1943
7521 12:15:11.165788
7522 12:15:11.168811 MIOCK jitter meter ch=0
7523 12:15:11.168918
7524 12:15:11.172176 1T = (312-88) = 224 dly cells
7525 12:15:11.178788 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7526 12:15:11.178964 ==
7527 12:15:11.182056 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 12:15:11.185388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 12:15:11.185540 ==
7530 12:15:11.191824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7531 12:15:11.195992 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7532 12:15:11.199246 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7533 12:15:11.205545 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7534 12:15:11.214135 [CA 0] Center 43 (13~74) winsize 62
7535 12:15:11.217341 [CA 1] Center 43 (13~74) winsize 62
7536 12:15:11.220651 [CA 2] Center 38 (9~68) winsize 60
7537 12:15:11.224038 [CA 3] Center 38 (8~68) winsize 61
7538 12:15:11.227186 [CA 4] Center 37 (7~67) winsize 61
7539 12:15:11.230988 [CA 5] Center 36 (7~65) winsize 59
7540 12:15:11.231152
7541 12:15:11.234144 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7542 12:15:11.234289
7543 12:15:11.237558 [CATrainingPosCal] consider 1 rank data
7544 12:15:11.240614 u2DelayCellTimex100 = 290/100 ps
7545 12:15:11.243913 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7546 12:15:11.250961 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7547 12:15:11.253701 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7548 12:15:11.257224 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7549 12:15:11.260664 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7550 12:15:11.263980 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7551 12:15:11.264155
7552 12:15:11.267132 CA PerBit enable=1, Macro0, CA PI delay=36
7553 12:15:11.267278
7554 12:15:11.270477 [CBTSetCACLKResult] CA Dly = 36
7555 12:15:11.273575 CS Dly: 9 (0~40)
7556 12:15:11.277270 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7557 12:15:11.280484 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7558 12:15:11.280608 ==
7559 12:15:11.283802 Dram Type= 6, Freq= 0, CH_0, rank 1
7560 12:15:11.287025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 12:15:11.290479 ==
7562 12:15:11.293629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7563 12:15:11.296956 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7564 12:15:11.303653 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7565 12:15:11.306967 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7566 12:15:11.317527 [CA 0] Center 42 (12~73) winsize 62
7567 12:15:11.320936 [CA 1] Center 42 (12~73) winsize 62
7568 12:15:11.324152 [CA 2] Center 38 (8~68) winsize 61
7569 12:15:11.327455 [CA 3] Center 38 (8~68) winsize 61
7570 12:15:11.330681 [CA 4] Center 36 (6~66) winsize 61
7571 12:15:11.333953 [CA 5] Center 35 (5~65) winsize 61
7572 12:15:11.334095
7573 12:15:11.337182 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7574 12:15:11.337311
7575 12:15:11.341058 [CATrainingPosCal] consider 2 rank data
7576 12:15:11.344361 u2DelayCellTimex100 = 290/100 ps
7577 12:15:11.347670 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7578 12:15:11.354083 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7579 12:15:11.357453 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7580 12:15:11.360780 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7581 12:15:11.364065 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7582 12:15:11.367497 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7583 12:15:11.367643
7584 12:15:11.370711 CA PerBit enable=1, Macro0, CA PI delay=36
7585 12:15:11.370838
7586 12:15:11.373996 [CBTSetCACLKResult] CA Dly = 36
7587 12:15:11.377355 CS Dly: 10 (0~42)
7588 12:15:11.380534 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7589 12:15:11.383678 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7590 12:15:11.383837
7591 12:15:11.387606 ----->DramcWriteLeveling(PI) begin...
7592 12:15:11.387749 ==
7593 12:15:11.390882 Dram Type= 6, Freq= 0, CH_0, rank 0
7594 12:15:11.394206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 12:15:11.397345 ==
7596 12:15:11.397492 Write leveling (Byte 0): 37 => 37
7597 12:15:11.400637 Write leveling (Byte 1): 29 => 29
7598 12:15:11.404054 DramcWriteLeveling(PI) end<-----
7599 12:15:11.404192
7600 12:15:11.404293 ==
7601 12:15:11.407222 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 12:15:11.413869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 12:15:11.414045 ==
7604 12:15:11.414151 [Gating] SW mode calibration
7605 12:15:11.423660 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7606 12:15:11.427026 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7607 12:15:11.430348 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7608 12:15:11.437494 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 12:15:11.440660 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7610 12:15:11.443897 1 4 12 | B1->B0 | 2323 3737 | 0 1 | (0 0) (1 1)
7611 12:15:11.450481 1 4 16 | B1->B0 | 2323 3535 | 0 1 | (0 0) (1 1)
7612 12:15:11.453763 1 4 20 | B1->B0 | 3434 3a3a | 0 1 | (0 0) (1 1)
7613 12:15:11.457020 1 4 24 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7614 12:15:11.464154 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7615 12:15:11.467388 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7616 12:15:11.470725 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7617 12:15:11.477443 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7618 12:15:11.480752 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7619 12:15:11.484157 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 1)
7620 12:15:11.490334 1 5 20 | B1->B0 | 2727 2c2b | 0 1 | (0 0) (1 1)
7621 12:15:11.493581 1 5 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7622 12:15:11.497343 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7623 12:15:11.503808 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 12:15:11.507055 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 12:15:11.510408 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7626 12:15:11.517039 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7627 12:15:11.520259 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7628 12:15:11.524064 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7629 12:15:11.530202 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7630 12:15:11.533543 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 12:15:11.536747 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 12:15:11.540249 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 12:15:11.546744 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 12:15:11.550021 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 12:15:11.553969 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7636 12:15:11.559997 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 12:15:11.563976 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 12:15:11.567113 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 12:15:11.573595 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 12:15:11.576916 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 12:15:11.580394 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 12:15:11.586976 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 12:15:11.590248 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 12:15:11.593665 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 12:15:11.600423 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 12:15:11.603607 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 12:15:11.606840 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 12:15:11.613742 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 12:15:11.617053 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 12:15:11.620337 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7651 12:15:11.627064 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7652 12:15:11.627207 Total UI for P1: 0, mck2ui 16
7653 12:15:11.630013 best dqsien dly found for B0: ( 1, 9, 12)
7654 12:15:11.636708 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7655 12:15:11.640027 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 12:15:11.643235 Total UI for P1: 0, mck2ui 16
7657 12:15:11.646662 best dqsien dly found for B1: ( 1, 9, 18)
7658 12:15:11.649980 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7659 12:15:11.653681 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7660 12:15:11.653798
7661 12:15:11.656871 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7662 12:15:11.663375 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7663 12:15:11.663514 [Gating] SW calibration Done
7664 12:15:11.663605 ==
7665 12:15:11.666724 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 12:15:11.673939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 12:15:11.674096 ==
7668 12:15:11.674194 RX Vref Scan: 0
7669 12:15:11.674284
7670 12:15:11.677169 RX Vref 0 -> 0, step: 1
7671 12:15:11.677277
7672 12:15:11.680390 RX Delay 0 -> 252, step: 8
7673 12:15:11.683679 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7674 12:15:11.686989 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7675 12:15:11.689772 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7676 12:15:11.696974 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7677 12:15:11.700304 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7678 12:15:11.703489 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7679 12:15:11.706593 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7680 12:15:11.709662 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7681 12:15:11.713054 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7682 12:15:11.719920 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7683 12:15:11.723171 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7684 12:15:11.726819 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7685 12:15:11.730242 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7686 12:15:11.733395 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7687 12:15:11.739678 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7688 12:15:11.743068 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7689 12:15:11.743182 ==
7690 12:15:11.746498 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 12:15:11.749785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 12:15:11.749931 ==
7693 12:15:11.753117 DQS Delay:
7694 12:15:11.753247 DQS0 = 0, DQS1 = 0
7695 12:15:11.753315 DQM Delay:
7696 12:15:11.756821 DQM0 = 137, DQM1 = 129
7697 12:15:11.756918 DQ Delay:
7698 12:15:11.760206 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7699 12:15:11.762887 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7700 12:15:11.770089 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7701 12:15:11.772837 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7702 12:15:11.772965
7703 12:15:11.773059
7704 12:15:11.773147 ==
7705 12:15:11.776170 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 12:15:11.779450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 12:15:11.779586 ==
7708 12:15:11.779687
7709 12:15:11.779780
7710 12:15:11.783341 TX Vref Scan disable
7711 12:15:11.786262 == TX Byte 0 ==
7712 12:15:11.789682 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7713 12:15:11.793074 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7714 12:15:11.796256 == TX Byte 1 ==
7715 12:15:11.799691 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7716 12:15:11.803018 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7717 12:15:11.803119 ==
7718 12:15:11.806218 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 12:15:11.809301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 12:15:11.812357 ==
7721 12:15:11.823196
7722 12:15:11.826884 TX Vref early break, caculate TX vref
7723 12:15:11.830172 TX Vref=16, minBit 0, minWin=22, winSum=378
7724 12:15:11.833436 TX Vref=18, minBit 0, minWin=23, winSum=386
7725 12:15:11.836704 TX Vref=20, minBit 1, minWin=23, winSum=395
7726 12:15:11.839969 TX Vref=22, minBit 7, minWin=24, winSum=407
7727 12:15:11.843129 TX Vref=24, minBit 1, minWin=25, winSum=415
7728 12:15:11.849969 TX Vref=26, minBit 0, minWin=25, winSum=419
7729 12:15:11.853412 TX Vref=28, minBit 2, minWin=24, winSum=424
7730 12:15:11.856822 TX Vref=30, minBit 1, minWin=24, winSum=411
7731 12:15:11.860071 TX Vref=32, minBit 1, minWin=24, winSum=401
7732 12:15:11.866403 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 26
7733 12:15:11.866563
7734 12:15:11.869719 Final TX Range 0 Vref 26
7735 12:15:11.869843
7736 12:15:11.869937 ==
7737 12:15:11.873039 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 12:15:11.876247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 12:15:11.876377 ==
7740 12:15:11.876473
7741 12:15:11.876564
7742 12:15:11.879620 TX Vref Scan disable
7743 12:15:11.882876 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7744 12:15:11.886225 == TX Byte 0 ==
7745 12:15:11.889483 u2DelayCellOfst[0]=13 cells (4 PI)
7746 12:15:11.892606 u2DelayCellOfst[1]=16 cells (5 PI)
7747 12:15:11.896398 u2DelayCellOfst[2]=13 cells (4 PI)
7748 12:15:11.899785 u2DelayCellOfst[3]=13 cells (4 PI)
7749 12:15:11.903073 u2DelayCellOfst[4]=10 cells (3 PI)
7750 12:15:11.906525 u2DelayCellOfst[5]=0 cells (0 PI)
7751 12:15:11.906697 u2DelayCellOfst[6]=20 cells (6 PI)
7752 12:15:11.909925 u2DelayCellOfst[7]=20 cells (6 PI)
7753 12:15:11.916192 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7754 12:15:11.919463 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7755 12:15:11.919619 == TX Byte 1 ==
7756 12:15:11.922775 u2DelayCellOfst[8]=0 cells (0 PI)
7757 12:15:11.926488 u2DelayCellOfst[9]=0 cells (0 PI)
7758 12:15:11.929596 u2DelayCellOfst[10]=6 cells (2 PI)
7759 12:15:11.932871 u2DelayCellOfst[11]=3 cells (1 PI)
7760 12:15:11.936247 u2DelayCellOfst[12]=10 cells (3 PI)
7761 12:15:11.939627 u2DelayCellOfst[13]=10 cells (3 PI)
7762 12:15:11.942838 u2DelayCellOfst[14]=13 cells (4 PI)
7763 12:15:11.946121 u2DelayCellOfst[15]=10 cells (3 PI)
7764 12:15:11.949488 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7765 12:15:11.952680 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7766 12:15:11.955779 DramC Write-DBI on
7767 12:15:11.955925 ==
7768 12:15:11.959709 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 12:15:11.962964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 12:15:11.963102 ==
7771 12:15:11.963198
7772 12:15:11.963289
7773 12:15:11.966239 TX Vref Scan disable
7774 12:15:11.969498 == TX Byte 0 ==
7775 12:15:11.972725 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7776 12:15:11.976049 == TX Byte 1 ==
7777 12:15:11.979346 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7778 12:15:11.979494 DramC Write-DBI off
7779 12:15:11.979596
7780 12:15:11.982647 [DATLAT]
7781 12:15:11.982756 Freq=1600, CH0 RK0
7782 12:15:11.982827
7783 12:15:11.985972 DATLAT Default: 0xf
7784 12:15:11.986077 0, 0xFFFF, sum = 0
7785 12:15:11.989326 1, 0xFFFF, sum = 0
7786 12:15:11.989432 2, 0xFFFF, sum = 0
7787 12:15:11.992717 3, 0xFFFF, sum = 0
7788 12:15:11.992856 4, 0xFFFF, sum = 0
7789 12:15:11.996046 5, 0xFFFF, sum = 0
7790 12:15:11.996180 6, 0xFFFF, sum = 0
7791 12:15:11.999111 7, 0xFFFF, sum = 0
7792 12:15:11.999239 8, 0xFFFF, sum = 0
7793 12:15:12.002940 9, 0xFFFF, sum = 0
7794 12:15:12.006304 10, 0xFFFF, sum = 0
7795 12:15:12.006456 11, 0xFFFF, sum = 0
7796 12:15:12.009706 12, 0xFFFF, sum = 0
7797 12:15:12.009858 13, 0xFFFF, sum = 0
7798 12:15:12.012860 14, 0x0, sum = 1
7799 12:15:12.012990 15, 0x0, sum = 2
7800 12:15:12.016296 16, 0x0, sum = 3
7801 12:15:12.016444 17, 0x0, sum = 4
7802 12:15:12.016566 best_step = 15
7803 12:15:12.016680
7804 12:15:12.019747 ==
7805 12:15:12.022463 Dram Type= 6, Freq= 0, CH_0, rank 0
7806 12:15:12.026134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7807 12:15:12.026271 ==
7808 12:15:12.026367 RX Vref Scan: 1
7809 12:15:12.026456
7810 12:15:12.029236 Set Vref Range= 24 -> 127
7811 12:15:12.029331
7812 12:15:12.032356 RX Vref 24 -> 127, step: 1
7813 12:15:12.032447
7814 12:15:12.035681 RX Delay 19 -> 252, step: 4
7815 12:15:12.035786
7816 12:15:12.038978 Set Vref, RX VrefLevel [Byte0]: 24
7817 12:15:12.042288 [Byte1]: 24
7818 12:15:12.042435
7819 12:15:12.046178 Set Vref, RX VrefLevel [Byte0]: 25
7820 12:15:12.048828 [Byte1]: 25
7821 12:15:12.048952
7822 12:15:12.052803 Set Vref, RX VrefLevel [Byte0]: 26
7823 12:15:12.055499 [Byte1]: 26
7824 12:15:12.059250
7825 12:15:12.059396 Set Vref, RX VrefLevel [Byte0]: 27
7826 12:15:12.062438 [Byte1]: 27
7827 12:15:12.067078
7828 12:15:12.067225 Set Vref, RX VrefLevel [Byte0]: 28
7829 12:15:12.070352 [Byte1]: 28
7830 12:15:12.074819
7831 12:15:12.074995 Set Vref, RX VrefLevel [Byte0]: 29
7832 12:15:12.077935 [Byte1]: 29
7833 12:15:12.082035
7834 12:15:12.082209 Set Vref, RX VrefLevel [Byte0]: 30
7835 12:15:12.085368 [Byte1]: 30
7836 12:15:12.089345
7837 12:15:12.089496 Set Vref, RX VrefLevel [Byte0]: 31
7838 12:15:12.092854 [Byte1]: 31
7839 12:15:12.097533
7840 12:15:12.097705 Set Vref, RX VrefLevel [Byte0]: 32
7841 12:15:12.100109 [Byte1]: 32
7842 12:15:12.104858
7843 12:15:12.105018 Set Vref, RX VrefLevel [Byte0]: 33
7844 12:15:12.108074 [Byte1]: 33
7845 12:15:12.112563
7846 12:15:12.112713 Set Vref, RX VrefLevel [Byte0]: 34
7847 12:15:12.115938 [Byte1]: 34
7848 12:15:12.120031
7849 12:15:12.120183 Set Vref, RX VrefLevel [Byte0]: 35
7850 12:15:12.123435 [Byte1]: 35
7851 12:15:12.127517
7852 12:15:12.127680 Set Vref, RX VrefLevel [Byte0]: 36
7853 12:15:12.130844 [Byte1]: 36
7854 12:15:12.135215
7855 12:15:12.135388 Set Vref, RX VrefLevel [Byte0]: 37
7856 12:15:12.138357 [Byte1]: 37
7857 12:15:12.142856
7858 12:15:12.143025 Set Vref, RX VrefLevel [Byte0]: 38
7859 12:15:12.145851 [Byte1]: 38
7860 12:15:12.149885
7861 12:15:12.150008 Set Vref, RX VrefLevel [Byte0]: 39
7862 12:15:12.153888 [Byte1]: 39
7863 12:15:12.157868
7864 12:15:12.157992 Set Vref, RX VrefLevel [Byte0]: 40
7865 12:15:12.161343 [Byte1]: 40
7866 12:15:12.165210
7867 12:15:12.165331 Set Vref, RX VrefLevel [Byte0]: 41
7868 12:15:12.168827 [Byte1]: 41
7869 12:15:12.172662
7870 12:15:12.172788 Set Vref, RX VrefLevel [Byte0]: 42
7871 12:15:12.175935 [Byte1]: 42
7872 12:15:12.180303
7873 12:15:12.180430 Set Vref, RX VrefLevel [Byte0]: 43
7874 12:15:12.183758 [Byte1]: 43
7875 12:15:12.188391
7876 12:15:12.188521 Set Vref, RX VrefLevel [Byte0]: 44
7877 12:15:12.191734 [Byte1]: 44
7878 12:15:12.195823
7879 12:15:12.195947 Set Vref, RX VrefLevel [Byte0]: 45
7880 12:15:12.199119 [Byte1]: 45
7881 12:15:12.203176
7882 12:15:12.203315 Set Vref, RX VrefLevel [Byte0]: 46
7883 12:15:12.206551 [Byte1]: 46
7884 12:15:12.210602
7885 12:15:12.210731 Set Vref, RX VrefLevel [Byte0]: 47
7886 12:15:12.213862 [Byte1]: 47
7887 12:15:12.218248
7888 12:15:12.218399 Set Vref, RX VrefLevel [Byte0]: 48
7889 12:15:12.221656 [Byte1]: 48
7890 12:15:12.225662
7891 12:15:12.225809 Set Vref, RX VrefLevel [Byte0]: 49
7892 12:15:12.229083 [Byte1]: 49
7893 12:15:12.233744
7894 12:15:12.233891 Set Vref, RX VrefLevel [Byte0]: 50
7895 12:15:12.237129 [Byte1]: 50
7896 12:15:12.240888
7897 12:15:12.241028 Set Vref, RX VrefLevel [Byte0]: 51
7898 12:15:12.244754 [Byte1]: 51
7899 12:15:12.248556
7900 12:15:12.248703 Set Vref, RX VrefLevel [Byte0]: 52
7901 12:15:12.251694 [Byte1]: 52
7902 12:15:12.256094
7903 12:15:12.256250 Set Vref, RX VrefLevel [Byte0]: 53
7904 12:15:12.259302 [Byte1]: 53
7905 12:15:12.264035
7906 12:15:12.264186 Set Vref, RX VrefLevel [Byte0]: 54
7907 12:15:12.267262 [Byte1]: 54
7908 12:15:12.271223
7909 12:15:12.271381 Set Vref, RX VrefLevel [Byte0]: 55
7910 12:15:12.274595 [Byte1]: 55
7911 12:15:12.278992
7912 12:15:12.279149 Set Vref, RX VrefLevel [Byte0]: 56
7913 12:15:12.282020 [Byte1]: 56
7914 12:15:12.286766
7915 12:15:12.286895 Set Vref, RX VrefLevel [Byte0]: 57
7916 12:15:12.289864 [Byte1]: 57
7917 12:15:12.293785
7918 12:15:12.293902 Set Vref, RX VrefLevel [Byte0]: 58
7919 12:15:12.297232 [Byte1]: 58
7920 12:15:12.301791
7921 12:15:12.301914 Set Vref, RX VrefLevel [Byte0]: 59
7922 12:15:12.305051 [Byte1]: 59
7923 12:15:12.308916
7924 12:15:12.309069 Set Vref, RX VrefLevel [Byte0]: 60
7925 12:15:12.312257 [Byte1]: 60
7926 12:15:12.316936
7927 12:15:12.317088 Set Vref, RX VrefLevel [Byte0]: 61
7928 12:15:12.320057 [Byte1]: 61
7929 12:15:12.324392
7930 12:15:12.324510 Set Vref, RX VrefLevel [Byte0]: 62
7931 12:15:12.327808 [Byte1]: 62
7932 12:15:12.331851
7933 12:15:12.331990 Set Vref, RX VrefLevel [Byte0]: 63
7934 12:15:12.335259 [Byte1]: 63
7935 12:15:12.339198
7936 12:15:12.339357 Set Vref, RX VrefLevel [Byte0]: 64
7937 12:15:12.342538 [Byte1]: 64
7938 12:15:12.347075
7939 12:15:12.347224 Set Vref, RX VrefLevel [Byte0]: 65
7940 12:15:12.350176 [Byte1]: 65
7941 12:15:12.354623
7942 12:15:12.354744 Set Vref, RX VrefLevel [Byte0]: 66
7943 12:15:12.357920 [Byte1]: 66
7944 12:15:12.362251
7945 12:15:12.362372 Set Vref, RX VrefLevel [Byte0]: 67
7946 12:15:12.365396 [Byte1]: 67
7947 12:15:12.370124
7948 12:15:12.370251 Set Vref, RX VrefLevel [Byte0]: 68
7949 12:15:12.372745 [Byte1]: 68
7950 12:15:12.377443
7951 12:15:12.377570 Set Vref, RX VrefLevel [Byte0]: 69
7952 12:15:12.380767 [Byte1]: 69
7953 12:15:12.384619
7954 12:15:12.384727 Set Vref, RX VrefLevel [Byte0]: 70
7955 12:15:12.388327 [Byte1]: 70
7956 12:15:12.392117
7957 12:15:12.392255 Set Vref, RX VrefLevel [Byte0]: 71
7958 12:15:12.396069 [Byte1]: 71
7959 12:15:12.400095
7960 12:15:12.400216 Set Vref, RX VrefLevel [Byte0]: 72
7961 12:15:12.403392 [Byte1]: 72
7962 12:15:12.407367
7963 12:15:12.407510 Set Vref, RX VrefLevel [Byte0]: 73
7964 12:15:12.410729 [Byte1]: 73
7965 12:15:12.415387
7966 12:15:12.415511 Set Vref, RX VrefLevel [Byte0]: 74
7967 12:15:12.418766 [Byte1]: 74
7968 12:15:12.422686
7969 12:15:12.422835 Set Vref, RX VrefLevel [Byte0]: 75
7970 12:15:12.425956 [Byte1]: 75
7971 12:15:12.430564
7972 12:15:12.430724 Final RX Vref Byte 0 = 58 to rank0
7973 12:15:12.433922 Final RX Vref Byte 1 = 60 to rank0
7974 12:15:12.437107 Final RX Vref Byte 0 = 58 to rank1
7975 12:15:12.440475 Final RX Vref Byte 1 = 60 to rank1==
7976 12:15:12.443694 Dram Type= 6, Freq= 0, CH_0, rank 0
7977 12:15:12.450444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 12:15:12.450622 ==
7979 12:15:12.450734 DQS Delay:
7980 12:15:12.450832 DQS0 = 0, DQS1 = 0
7981 12:15:12.453652 DQM Delay:
7982 12:15:12.453775 DQM0 = 134, DQM1 = 127
7983 12:15:12.456887 DQ Delay:
7984 12:15:12.460105 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7985 12:15:12.463296 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
7986 12:15:12.466607 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7987 12:15:12.470293 DQ12 =130, DQ13 =134, DQ14 =138, DQ15 =136
7988 12:15:12.470449
7989 12:15:12.470558
7990 12:15:12.470654
7991 12:15:12.473321 [DramC_TX_OE_Calibration] TA2
7992 12:15:12.476705 Original DQ_B0 (3 6) =30, OEN = 27
7993 12:15:12.480022 Original DQ_B1 (3 6) =30, OEN = 27
7994 12:15:12.483294 24, 0x0, End_B0=24 End_B1=24
7995 12:15:12.483456 25, 0x0, End_B0=25 End_B1=25
7996 12:15:12.486670 26, 0x0, End_B0=26 End_B1=26
7997 12:15:12.490092 27, 0x0, End_B0=27 End_B1=27
7998 12:15:12.493314 28, 0x0, End_B0=28 End_B1=28
7999 12:15:12.493468 29, 0x0, End_B0=29 End_B1=29
8000 12:15:12.497065 30, 0x0, End_B0=30 End_B1=30
8001 12:15:12.500219 31, 0x4141, End_B0=30 End_B1=30
8002 12:15:12.503353 Byte0 end_step=30 best_step=27
8003 12:15:12.506661 Byte1 end_step=30 best_step=27
8004 12:15:12.510083 Byte0 TX OE(2T, 0.5T) = (3, 3)
8005 12:15:12.510213 Byte1 TX OE(2T, 0.5T) = (3, 3)
8006 12:15:12.513517
8007 12:15:12.513622
8008 12:15:12.520188 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
8009 12:15:12.523576 CH0 RK0: MR19=303, MR18=2723
8010 12:15:12.530003 CH0_RK0: MR19=0x303, MR18=0x2723, DQSOSC=390, MR23=63, INC=24, DEC=16
8011 12:15:12.530146
8012 12:15:12.533432 ----->DramcWriteLeveling(PI) begin...
8013 12:15:12.533543 ==
8014 12:15:12.536489 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 12:15:12.540396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 12:15:12.540524 ==
8017 12:15:12.543711 Write leveling (Byte 0): 34 => 34
8018 12:15:12.546302 Write leveling (Byte 1): 29 => 29
8019 12:15:12.549729 DramcWriteLeveling(PI) end<-----
8020 12:15:12.549835
8021 12:15:12.549907 ==
8022 12:15:12.553264 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 12:15:12.556626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 12:15:12.556739 ==
8025 12:15:12.559786 [Gating] SW mode calibration
8026 12:15:12.566452 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8027 12:15:12.573445 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8028 12:15:12.576589 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 12:15:12.579532 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 12:15:12.586005 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8031 12:15:12.589546 1 4 12 | B1->B0 | 2323 2726 | 0 1 | (0 0) (1 1)
8032 12:15:12.592804 1 4 16 | B1->B0 | 2d2d 3535 | 0 1 | (0 0) (1 1)
8033 12:15:12.599428 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8034 12:15:12.602773 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
8035 12:15:12.605775 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8036 12:15:12.612821 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 12:15:12.616022 1 5 4 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
8038 12:15:12.619529 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8039 12:15:12.626058 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
8040 12:15:12.629411 1 5 16 | B1->B0 | 2e2e 2424 | 0 0 | (1 0) (0 1)
8041 12:15:12.632825 1 5 20 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8042 12:15:12.639576 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 12:15:12.642901 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8044 12:15:12.646009 1 6 0 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8045 12:15:12.652426 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8046 12:15:12.655861 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 12:15:12.659051 1 6 12 | B1->B0 | 2626 3737 | 1 0 | (0 0) (0 0)
8048 12:15:12.665724 1 6 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8049 12:15:12.669517 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 12:15:12.672563 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 12:15:12.679221 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 12:15:12.682309 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 12:15:12.685967 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 12:15:12.692290 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 12:15:12.695564 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8056 12:15:12.698823 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 12:15:12.705470 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 12:15:12.709156 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:15:12.712155 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 12:15:12.718753 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 12:15:12.722171 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 12:15:12.725465 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 12:15:12.732031 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 12:15:12.735376 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 12:15:12.738721 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 12:15:12.745469 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 12:15:12.748774 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 12:15:12.751979 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 12:15:12.755574 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 12:15:12.762239 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 12:15:12.765639 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8072 12:15:12.768523 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 12:15:12.771942 Total UI for P1: 0, mck2ui 16
8074 12:15:12.775269 best dqsien dly found for B0: ( 1, 9, 12)
8075 12:15:12.778430 Total UI for P1: 0, mck2ui 16
8076 12:15:12.782031 best dqsien dly found for B1: ( 1, 9, 12)
8077 12:15:12.785189 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8078 12:15:12.788878 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8079 12:15:12.791956
8080 12:15:12.795657 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8081 12:15:12.798683 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8082 12:15:12.801838 [Gating] SW calibration Done
8083 12:15:12.801963 ==
8084 12:15:12.805638 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 12:15:12.808902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 12:15:12.809063 ==
8087 12:15:12.809172 RX Vref Scan: 0
8088 12:15:12.812202
8089 12:15:12.812326 RX Vref 0 -> 0, step: 1
8090 12:15:12.812425
8091 12:15:12.815617 RX Delay 0 -> 252, step: 8
8092 12:15:12.818689 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8093 12:15:12.821736 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8094 12:15:12.828658 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8095 12:15:12.831993 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8096 12:15:12.835356 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8097 12:15:12.838789 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8098 12:15:12.842069 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8099 12:15:12.845486 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8100 12:15:12.852109 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8101 12:15:12.855450 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8102 12:15:12.858726 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8103 12:15:12.861733 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8104 12:15:12.868401 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8105 12:15:12.871803 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8106 12:15:12.875106 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8107 12:15:12.878516 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8108 12:15:12.878664 ==
8109 12:15:12.881729 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 12:15:12.884967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 12:15:12.888724 ==
8112 12:15:12.888877 DQS Delay:
8113 12:15:12.888978 DQS0 = 0, DQS1 = 0
8114 12:15:12.892049 DQM Delay:
8115 12:15:12.892172 DQM0 = 137, DQM1 = 130
8116 12:15:12.894985 DQ Delay:
8117 12:15:12.898664 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8118 12:15:12.901629 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8119 12:15:12.904832 DQ8 =123, DQ9 =119, DQ10 =127, DQ11 =123
8120 12:15:12.908096 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8121 12:15:12.908243
8122 12:15:12.908346
8123 12:15:12.908440 ==
8124 12:15:12.911877 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 12:15:12.915149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 12:15:12.915297 ==
8127 12:15:12.918465
8128 12:15:12.918594
8129 12:15:12.918696 TX Vref Scan disable
8130 12:15:12.921743 == TX Byte 0 ==
8131 12:15:12.925201 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8132 12:15:12.928393 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8133 12:15:12.931505 == TX Byte 1 ==
8134 12:15:12.934927 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8135 12:15:12.938148 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8136 12:15:12.938293 ==
8137 12:15:12.941517 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 12:15:12.948206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 12:15:12.948363 ==
8140 12:15:12.960293
8141 12:15:12.963741 TX Vref early break, caculate TX vref
8142 12:15:12.966982 TX Vref=16, minBit 0, minWin=23, winSum=386
8143 12:15:12.970214 TX Vref=18, minBit 1, minWin=23, winSum=397
8144 12:15:12.973616 TX Vref=20, minBit 1, minWin=24, winSum=404
8145 12:15:12.976947 TX Vref=22, minBit 1, minWin=24, winSum=410
8146 12:15:12.980359 TX Vref=24, minBit 7, minWin=24, winSum=419
8147 12:15:12.987048 TX Vref=26, minBit 1, minWin=25, winSum=425
8148 12:15:12.990497 TX Vref=28, minBit 1, minWin=25, winSum=424
8149 12:15:12.993703 TX Vref=30, minBit 1, minWin=25, winSum=420
8150 12:15:12.996834 TX Vref=32, minBit 0, minWin=25, winSum=410
8151 12:15:13.000538 TX Vref=34, minBit 0, minWin=24, winSum=401
8152 12:15:13.006848 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 26
8153 12:15:13.007030
8154 12:15:13.010531 Final TX Range 0 Vref 26
8155 12:15:13.010700
8156 12:15:13.010802 ==
8157 12:15:13.013703 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 12:15:13.016859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 12:15:13.017004 ==
8160 12:15:13.017106
8161 12:15:13.017201
8162 12:15:13.020604 TX Vref Scan disable
8163 12:15:13.027143 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8164 12:15:13.027321 == TX Byte 0 ==
8165 12:15:13.030542 u2DelayCellOfst[0]=13 cells (4 PI)
8166 12:15:13.033974 u2DelayCellOfst[1]=16 cells (5 PI)
8167 12:15:13.037003 u2DelayCellOfst[2]=10 cells (3 PI)
8168 12:15:13.040781 u2DelayCellOfst[3]=10 cells (3 PI)
8169 12:15:13.043859 u2DelayCellOfst[4]=6 cells (2 PI)
8170 12:15:13.047014 u2DelayCellOfst[5]=0 cells (0 PI)
8171 12:15:13.050350 u2DelayCellOfst[6]=16 cells (5 PI)
8172 12:15:13.050498 u2DelayCellOfst[7]=13 cells (4 PI)
8173 12:15:13.057158 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8174 12:15:13.060360 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8175 12:15:13.060514 == TX Byte 1 ==
8176 12:15:13.063768 u2DelayCellOfst[8]=0 cells (0 PI)
8177 12:15:13.067136 u2DelayCellOfst[9]=0 cells (0 PI)
8178 12:15:13.070415 u2DelayCellOfst[10]=10 cells (3 PI)
8179 12:15:13.073593 u2DelayCellOfst[11]=3 cells (1 PI)
8180 12:15:13.076913 u2DelayCellOfst[12]=10 cells (3 PI)
8181 12:15:13.080250 u2DelayCellOfst[13]=10 cells (3 PI)
8182 12:15:13.083573 u2DelayCellOfst[14]=13 cells (4 PI)
8183 12:15:13.086746 u2DelayCellOfst[15]=10 cells (3 PI)
8184 12:15:13.090162 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8185 12:15:13.097042 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8186 12:15:13.097179 DramC Write-DBI on
8187 12:15:13.097253 ==
8188 12:15:13.100189 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 12:15:13.103421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 12:15:13.103524 ==
8191 12:15:13.106483
8192 12:15:13.106613
8193 12:15:13.106716 TX Vref Scan disable
8194 12:15:13.110359 == TX Byte 0 ==
8195 12:15:13.113750 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8196 12:15:13.116793 == TX Byte 1 ==
8197 12:15:13.120014 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8198 12:15:13.120174 DramC Write-DBI off
8199 12:15:13.123685
8200 12:15:13.123832 [DATLAT]
8201 12:15:13.123935 Freq=1600, CH0 RK1
8202 12:15:13.124030
8203 12:15:13.126889 DATLAT Default: 0xf
8204 12:15:13.127013 0, 0xFFFF, sum = 0
8205 12:15:13.130102 1, 0xFFFF, sum = 0
8206 12:15:13.130257 2, 0xFFFF, sum = 0
8207 12:15:13.133439 3, 0xFFFF, sum = 0
8208 12:15:13.133599 4, 0xFFFF, sum = 0
8209 12:15:13.136865 5, 0xFFFF, sum = 0
8210 12:15:13.140210 6, 0xFFFF, sum = 0
8211 12:15:13.140381 7, 0xFFFF, sum = 0
8212 12:15:13.143461 8, 0xFFFF, sum = 0
8213 12:15:13.143611 9, 0xFFFF, sum = 0
8214 12:15:13.146670 10, 0xFFFF, sum = 0
8215 12:15:13.146782 11, 0xFFFF, sum = 0
8216 12:15:13.149793 12, 0xFFFF, sum = 0
8217 12:15:13.149940 13, 0xFFFF, sum = 0
8218 12:15:13.153620 14, 0x0, sum = 1
8219 12:15:13.153765 15, 0x0, sum = 2
8220 12:15:13.156862 16, 0x0, sum = 3
8221 12:15:13.156966 17, 0x0, sum = 4
8222 12:15:13.160056 best_step = 15
8223 12:15:13.160158
8224 12:15:13.160225 ==
8225 12:15:13.163359 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 12:15:13.166643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 12:15:13.166751 ==
8228 12:15:13.166819 RX Vref Scan: 0
8229 12:15:13.170098
8230 12:15:13.170220 RX Vref 0 -> 0, step: 1
8231 12:15:13.170314
8232 12:15:13.173525 RX Delay 19 -> 252, step: 4
8233 12:15:13.176850 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8234 12:15:13.183356 iDelay=195, Bit 1, Center 138 (91 ~ 186) 96
8235 12:15:13.186774 iDelay=195, Bit 2, Center 130 (79 ~ 182) 104
8236 12:15:13.190137 iDelay=195, Bit 3, Center 134 (83 ~ 186) 104
8237 12:15:13.193592 iDelay=195, Bit 4, Center 136 (87 ~ 186) 100
8238 12:15:13.196786 iDelay=195, Bit 5, Center 126 (75 ~ 178) 104
8239 12:15:13.203361 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
8240 12:15:13.206761 iDelay=195, Bit 7, Center 142 (91 ~ 194) 104
8241 12:15:13.210088 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8242 12:15:13.213241 iDelay=195, Bit 9, Center 116 (67 ~ 166) 100
8243 12:15:13.216334 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8244 12:15:13.223014 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8245 12:15:13.226273 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8246 12:15:13.229901 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8247 12:15:13.233233 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8248 12:15:13.236334 iDelay=195, Bit 15, Center 136 (87 ~ 186) 100
8249 12:15:13.236492 ==
8250 12:15:13.239537 Dram Type= 6, Freq= 0, CH_0, rank 1
8251 12:15:13.246154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 12:15:13.246336 ==
8253 12:15:13.246441 DQS Delay:
8254 12:15:13.249492 DQS0 = 0, DQS1 = 0
8255 12:15:13.249625 DQM Delay:
8256 12:15:13.252915 DQM0 = 135, DQM1 = 127
8257 12:15:13.253054 DQ Delay:
8258 12:15:13.256135 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8259 12:15:13.259918 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =142
8260 12:15:13.263094 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8261 12:15:13.266184 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8262 12:15:13.266336
8263 12:15:13.266438
8264 12:15:13.266538
8265 12:15:13.269469 [DramC_TX_OE_Calibration] TA2
8266 12:15:13.272912 Original DQ_B0 (3 6) =30, OEN = 27
8267 12:15:13.276274 Original DQ_B1 (3 6) =30, OEN = 27
8268 12:15:13.279571 24, 0x0, End_B0=24 End_B1=24
8269 12:15:13.282897 25, 0x0, End_B0=25 End_B1=25
8270 12:15:13.283049 26, 0x0, End_B0=26 End_B1=26
8271 12:15:13.286122 27, 0x0, End_B0=27 End_B1=27
8272 12:15:13.289273 28, 0x0, End_B0=28 End_B1=28
8273 12:15:13.292688 29, 0x0, End_B0=29 End_B1=29
8274 12:15:13.296047 30, 0x0, End_B0=30 End_B1=30
8275 12:15:13.296196 31, 0x4141, End_B0=30 End_B1=30
8276 12:15:13.299306 Byte0 end_step=30 best_step=27
8277 12:15:13.302567 Byte1 end_step=30 best_step=27
8278 12:15:13.306015 Byte0 TX OE(2T, 0.5T) = (3, 3)
8279 12:15:13.309285 Byte1 TX OE(2T, 0.5T) = (3, 3)
8280 12:15:13.309435
8281 12:15:13.309548
8282 12:15:13.315967 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
8283 12:15:13.319251 CH0 RK1: MR19=303, MR18=1F08
8284 12:15:13.325491 CH0_RK1: MR19=0x303, MR18=0x1F08, DQSOSC=394, MR23=63, INC=23, DEC=15
8285 12:15:13.329361 [RxdqsGatingPostProcess] freq 1600
8286 12:15:13.335688 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8287 12:15:13.335861 best DQS0 dly(2T, 0.5T) = (1, 1)
8288 12:15:13.339267 best DQS1 dly(2T, 0.5T) = (1, 1)
8289 12:15:13.342506 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8290 12:15:13.345672 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8291 12:15:13.349016 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 12:15:13.352458 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 12:15:13.355854 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 12:15:13.359100 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 12:15:13.362457 Pre-setting of DQS Precalculation
8296 12:15:13.365544 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8297 12:15:13.365690 ==
8298 12:15:13.368793 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 12:15:13.375372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 12:15:13.375546 ==
8301 12:15:13.378673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8302 12:15:13.385365 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8303 12:15:13.388835 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8304 12:15:13.395119 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8305 12:15:13.403083 [CA 0] Center 42 (13~72) winsize 60
8306 12:15:13.406502 [CA 1] Center 42 (13~72) winsize 60
8307 12:15:13.409681 [CA 2] Center 39 (10~69) winsize 60
8308 12:15:13.413002 [CA 3] Center 38 (9~67) winsize 59
8309 12:15:13.416373 [CA 4] Center 39 (10~68) winsize 59
8310 12:15:13.419745 [CA 5] Center 37 (8~67) winsize 60
8311 12:15:13.419882
8312 12:15:13.423013 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8313 12:15:13.423137
8314 12:15:13.429712 [CATrainingPosCal] consider 1 rank data
8315 12:15:13.429845 u2DelayCellTimex100 = 290/100 ps
8316 12:15:13.436060 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8317 12:15:13.439293 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8318 12:15:13.442371 CA2 delay=39 (10~69),Diff = 2 PI (6 cell)
8319 12:15:13.446165 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8320 12:15:13.449349 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8321 12:15:13.452479 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8322 12:15:13.452638
8323 12:15:13.455921 CA PerBit enable=1, Macro0, CA PI delay=37
8324 12:15:13.456062
8325 12:15:13.459150 [CBTSetCACLKResult] CA Dly = 37
8326 12:15:13.462506 CS Dly: 12 (0~43)
8327 12:15:13.465839 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8328 12:15:13.469069 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8329 12:15:13.469230 ==
8330 12:15:13.472769 Dram Type= 6, Freq= 0, CH_1, rank 1
8331 12:15:13.479000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 12:15:13.479196 ==
8333 12:15:13.482936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8334 12:15:13.488782 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8335 12:15:13.492123 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8336 12:15:13.498797 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8337 12:15:13.506609 [CA 0] Center 42 (12~72) winsize 61
8338 12:15:13.509908 [CA 1] Center 42 (13~72) winsize 60
8339 12:15:13.513239 [CA 2] Center 39 (10~69) winsize 60
8340 12:15:13.516511 [CA 3] Center 38 (9~68) winsize 60
8341 12:15:13.519911 [CA 4] Center 39 (9~69) winsize 61
8342 12:15:13.523269 [CA 5] Center 38 (9~67) winsize 59
8343 12:15:13.523404
8344 12:15:13.526638 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8345 12:15:13.526757
8346 12:15:13.530001 [CATrainingPosCal] consider 2 rank data
8347 12:15:13.533203 u2DelayCellTimex100 = 290/100 ps
8348 12:15:13.536556 CA0 delay=42 (13~72),Diff = 4 PI (13 cell)
8349 12:15:13.543396 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8350 12:15:13.546639 CA2 delay=39 (10~69),Diff = 1 PI (3 cell)
8351 12:15:13.549959 CA3 delay=38 (9~67),Diff = 0 PI (0 cell)
8352 12:15:13.553030 CA4 delay=39 (10~68),Diff = 1 PI (3 cell)
8353 12:15:13.556188 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8354 12:15:13.556330
8355 12:15:13.560030 CA PerBit enable=1, Macro0, CA PI delay=38
8356 12:15:13.560160
8357 12:15:13.563291 [CBTSetCACLKResult] CA Dly = 38
8358 12:15:13.566659 CS Dly: 12 (0~44)
8359 12:15:13.569988 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8360 12:15:13.573081 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8361 12:15:13.573225
8362 12:15:13.576262 ----->DramcWriteLeveling(PI) begin...
8363 12:15:13.576392 ==
8364 12:15:13.579595 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 12:15:13.586666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 12:15:13.586833 ==
8367 12:15:13.590046 Write leveling (Byte 0): 24 => 24
8368 12:15:13.590167 Write leveling (Byte 1): 27 => 27
8369 12:15:13.593286 DramcWriteLeveling(PI) end<-----
8370 12:15:13.593406
8371 12:15:13.593501 ==
8372 12:15:13.596685 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 12:15:13.603321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 12:15:13.603496 ==
8375 12:15:13.606574 [Gating] SW mode calibration
8376 12:15:13.613372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8377 12:15:13.616822 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8378 12:15:13.623467 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 12:15:13.626741 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 12:15:13.630192 1 4 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
8381 12:15:13.633568 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8382 12:15:13.640038 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 12:15:13.643344 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 12:15:13.646615 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 12:15:13.653413 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 12:15:13.656657 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 12:15:13.659731 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8388 12:15:13.666222 1 5 8 | B1->B0 | 3434 2626 | 0 0 | (0 1) (0 1)
8389 12:15:13.669637 1 5 12 | B1->B0 | 2424 2323 | 1 0 | (1 0) (1 0)
8390 12:15:13.672797 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 12:15:13.679973 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 12:15:13.682742 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 12:15:13.685979 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 12:15:13.693006 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 12:15:13.696338 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 12:15:13.699781 1 6 8 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
8397 12:15:13.706356 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8398 12:15:13.709653 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 12:15:13.713073 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 12:15:13.719654 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 12:15:13.722576 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 12:15:13.725992 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 12:15:13.732807 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 12:15:13.736156 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8405 12:15:13.739469 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8406 12:15:13.746129 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8407 12:15:13.749542 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:15:13.752864 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:15:13.759345 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:15:13.763111 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:15:13.766218 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:15:13.772327 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:15:13.776220 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 12:15:13.779450 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 12:15:13.782804 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 12:15:13.789309 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 12:15:13.792669 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 12:15:13.795795 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 12:15:13.802194 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 12:15:13.805496 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8421 12:15:13.808753 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8422 12:15:13.815484 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 12:15:13.819457 Total UI for P1: 0, mck2ui 16
8424 12:15:13.822055 best dqsien dly found for B0: ( 1, 9, 10)
8425 12:15:13.825387 Total UI for P1: 0, mck2ui 16
8426 12:15:13.829258 best dqsien dly found for B1: ( 1, 9, 10)
8427 12:15:13.832374 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8428 12:15:13.835731 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8429 12:15:13.835900
8430 12:15:13.839009 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8431 12:15:13.842579 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8432 12:15:13.845793 [Gating] SW calibration Done
8433 12:15:13.845957 ==
8434 12:15:13.849082 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 12:15:13.852503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 12:15:13.852669 ==
8437 12:15:13.855715 RX Vref Scan: 0
8438 12:15:13.855859
8439 12:15:13.859112 RX Vref 0 -> 0, step: 1
8440 12:15:13.859259
8441 12:15:13.859374 RX Delay 0 -> 252, step: 8
8442 12:15:13.865698 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8443 12:15:13.868832 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8444 12:15:13.872049 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8445 12:15:13.875211 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8446 12:15:13.878868 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8447 12:15:13.885468 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8448 12:15:13.888827 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8449 12:15:13.892207 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8450 12:15:13.895574 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8451 12:15:13.898926 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8452 12:15:13.901843 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8453 12:15:13.908787 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8454 12:15:13.912118 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8455 12:15:13.915526 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8456 12:15:13.918867 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8457 12:15:13.925345 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8458 12:15:13.925634 ==
8459 12:15:13.928827 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 12:15:13.932086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 12:15:13.932324 ==
8462 12:15:13.932460 DQS Delay:
8463 12:15:13.935412 DQS0 = 0, DQS1 = 0
8464 12:15:13.935570 DQM Delay:
8465 12:15:13.938582 DQM0 = 135, DQM1 = 133
8466 12:15:13.938732 DQ Delay:
8467 12:15:13.941477 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8468 12:15:13.945400 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8469 12:15:13.948684 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8470 12:15:13.951492 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8471 12:15:13.951666
8472 12:15:13.951767
8473 12:15:13.954863 ==
8474 12:15:13.958068 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 12:15:13.961468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 12:15:13.961645 ==
8477 12:15:13.961750
8478 12:15:13.961843
8479 12:15:13.964775 TX Vref Scan disable
8480 12:15:13.964927 == TX Byte 0 ==
8481 12:15:13.967996 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8482 12:15:13.975089 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8483 12:15:13.975279 == TX Byte 1 ==
8484 12:15:13.978059 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8485 12:15:13.984934 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8486 12:15:13.985130 ==
8487 12:15:13.988021 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 12:15:13.991276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 12:15:13.991446 ==
8490 12:15:14.004779
8491 12:15:14.008020 TX Vref early break, caculate TX vref
8492 12:15:14.011222 TX Vref=16, minBit 0, minWin=22, winSum=377
8493 12:15:14.014926 TX Vref=18, minBit 0, minWin=23, winSum=384
8494 12:15:14.018219 TX Vref=20, minBit 0, minWin=24, winSum=398
8495 12:15:14.021337 TX Vref=22, minBit 0, minWin=25, winSum=410
8496 12:15:14.024707 TX Vref=24, minBit 0, minWin=25, winSum=416
8497 12:15:14.031175 TX Vref=26, minBit 0, minWin=26, winSum=430
8498 12:15:14.034539 TX Vref=28, minBit 0, minWin=26, winSum=428
8499 12:15:14.037872 TX Vref=30, minBit 2, minWin=25, winSum=424
8500 12:15:14.041161 TX Vref=32, minBit 2, minWin=24, winSum=415
8501 12:15:14.044489 TX Vref=34, minBit 0, minWin=24, winSum=402
8502 12:15:14.050996 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 26
8503 12:15:14.051192
8504 12:15:14.054262 Final TX Range 0 Vref 26
8505 12:15:14.054419
8506 12:15:14.054544 ==
8507 12:15:14.057536 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 12:15:14.060778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 12:15:14.060933 ==
8510 12:15:14.061036
8511 12:15:14.061128
8512 12:15:14.064131 TX Vref Scan disable
8513 12:15:14.070882 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8514 12:15:14.071029 == TX Byte 0 ==
8515 12:15:14.074136 u2DelayCellOfst[0]=16 cells (5 PI)
8516 12:15:14.077514 u2DelayCellOfst[1]=10 cells (3 PI)
8517 12:15:14.080786 u2DelayCellOfst[2]=0 cells (0 PI)
8518 12:15:14.083937 u2DelayCellOfst[3]=6 cells (2 PI)
8519 12:15:14.087534 u2DelayCellOfst[4]=6 cells (2 PI)
8520 12:15:14.091225 u2DelayCellOfst[5]=16 cells (5 PI)
8521 12:15:14.094632 u2DelayCellOfst[6]=16 cells (5 PI)
8522 12:15:14.094772 u2DelayCellOfst[7]=6 cells (2 PI)
8523 12:15:14.101089 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8524 12:15:14.104363 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8525 12:15:14.104552 == TX Byte 1 ==
8526 12:15:14.107698 u2DelayCellOfst[8]=0 cells (0 PI)
8527 12:15:14.111035 u2DelayCellOfst[9]=3 cells (1 PI)
8528 12:15:14.114203 u2DelayCellOfst[10]=13 cells (4 PI)
8529 12:15:14.117430 u2DelayCellOfst[11]=3 cells (1 PI)
8530 12:15:14.120712 u2DelayCellOfst[12]=13 cells (4 PI)
8531 12:15:14.123936 u2DelayCellOfst[13]=16 cells (5 PI)
8532 12:15:14.127680 u2DelayCellOfst[14]=16 cells (5 PI)
8533 12:15:14.130955 u2DelayCellOfst[15]=16 cells (5 PI)
8534 12:15:14.134303 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8535 12:15:14.141069 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8536 12:15:14.141248 DramC Write-DBI on
8537 12:15:14.141349 ==
8538 12:15:14.144257 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 12:15:14.147596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 12:15:14.147744 ==
8541 12:15:14.147847
8542 12:15:14.150835
8543 12:15:14.150978 TX Vref Scan disable
8544 12:15:14.154108 == TX Byte 0 ==
8545 12:15:14.157167 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8546 12:15:14.160374 == TX Byte 1 ==
8547 12:15:14.164338 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8548 12:15:14.164480 DramC Write-DBI off
8549 12:15:14.164558
8550 12:15:14.167054 [DATLAT]
8551 12:15:14.167186 Freq=1600, CH1 RK0
8552 12:15:14.167292
8553 12:15:14.171054 DATLAT Default: 0xf
8554 12:15:14.171207 0, 0xFFFF, sum = 0
8555 12:15:14.173735 1, 0xFFFF, sum = 0
8556 12:15:14.173875 2, 0xFFFF, sum = 0
8557 12:15:14.177138 3, 0xFFFF, sum = 0
8558 12:15:14.177287 4, 0xFFFF, sum = 0
8559 12:15:14.180506 5, 0xFFFF, sum = 0
8560 12:15:14.180659 6, 0xFFFF, sum = 0
8561 12:15:14.183848 7, 0xFFFF, sum = 0
8562 12:15:14.187139 8, 0xFFFF, sum = 0
8563 12:15:14.187317 9, 0xFFFF, sum = 0
8564 12:15:14.190393 10, 0xFFFF, sum = 0
8565 12:15:14.190527 11, 0xFFFF, sum = 0
8566 12:15:14.193641 12, 0xFFFF, sum = 0
8567 12:15:14.193794 13, 0xFFFF, sum = 0
8568 12:15:14.197391 14, 0x0, sum = 1
8569 12:15:14.197716 15, 0x0, sum = 2
8570 12:15:14.200348 16, 0x0, sum = 3
8571 12:15:14.200488 17, 0x0, sum = 4
8572 12:15:14.204043 best_step = 15
8573 12:15:14.204187
8574 12:15:14.204286 ==
8575 12:15:14.207221 Dram Type= 6, Freq= 0, CH_1, rank 0
8576 12:15:14.210507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8577 12:15:14.210644 ==
8578 12:15:14.210763 RX Vref Scan: 1
8579 12:15:14.210857
8580 12:15:14.213870 Set Vref Range= 24 -> 127
8581 12:15:14.214023
8582 12:15:14.217053 RX Vref 24 -> 127, step: 1
8583 12:15:14.217191
8584 12:15:14.220496 RX Delay 27 -> 252, step: 4
8585 12:15:14.220645
8586 12:15:14.223539 Set Vref, RX VrefLevel [Byte0]: 24
8587 12:15:14.227243 [Byte1]: 24
8588 12:15:14.227394
8589 12:15:14.230300 Set Vref, RX VrefLevel [Byte0]: 25
8590 12:15:14.233648 [Byte1]: 25
8591 12:15:14.233778
8592 12:15:14.237350 Set Vref, RX VrefLevel [Byte0]: 26
8593 12:15:14.240694 [Byte1]: 26
8594 12:15:14.243980
8595 12:15:14.244122 Set Vref, RX VrefLevel [Byte0]: 27
8596 12:15:14.246918 [Byte1]: 27
8597 12:15:14.251559
8598 12:15:14.251696 Set Vref, RX VrefLevel [Byte0]: 28
8599 12:15:14.254930 [Byte1]: 28
8600 12:15:14.258853
8601 12:15:14.258967 Set Vref, RX VrefLevel [Byte0]: 29
8602 12:15:14.261943 [Byte1]: 29
8603 12:15:14.266382
8604 12:15:14.266538 Set Vref, RX VrefLevel [Byte0]: 30
8605 12:15:14.269692 [Byte1]: 30
8606 12:15:14.273792
8607 12:15:14.273923 Set Vref, RX VrefLevel [Byte0]: 31
8608 12:15:14.277176 [Byte1]: 31
8609 12:15:14.281712
8610 12:15:14.281889 Set Vref, RX VrefLevel [Byte0]: 32
8611 12:15:14.285022 [Byte1]: 32
8612 12:15:14.289067
8613 12:15:14.289194 Set Vref, RX VrefLevel [Byte0]: 33
8614 12:15:14.292543 [Byte1]: 33
8615 12:15:14.296337
8616 12:15:14.296473 Set Vref, RX VrefLevel [Byte0]: 34
8617 12:15:14.300208 [Byte1]: 34
8618 12:15:14.304283
8619 12:15:14.304417 Set Vref, RX VrefLevel [Byte0]: 35
8620 12:15:14.307632 [Byte1]: 35
8621 12:15:14.311874
8622 12:15:14.312048 Set Vref, RX VrefLevel [Byte0]: 36
8623 12:15:14.314718 [Byte1]: 36
8624 12:15:14.319187
8625 12:15:14.319388 Set Vref, RX VrefLevel [Byte0]: 37
8626 12:15:14.322590 [Byte1]: 37
8627 12:15:14.326517
8628 12:15:14.326693 Set Vref, RX VrefLevel [Byte0]: 38
8629 12:15:14.330405 [Byte1]: 38
8630 12:15:14.334037
8631 12:15:14.334158 Set Vref, RX VrefLevel [Byte0]: 39
8632 12:15:14.337937 [Byte1]: 39
8633 12:15:14.341729
8634 12:15:14.341841 Set Vref, RX VrefLevel [Byte0]: 40
8635 12:15:14.344948 [Byte1]: 40
8636 12:15:14.349407
8637 12:15:14.349568 Set Vref, RX VrefLevel [Byte0]: 41
8638 12:15:14.352661 [Byte1]: 41
8639 12:15:14.356829
8640 12:15:14.356983 Set Vref, RX VrefLevel [Byte0]: 42
8641 12:15:14.360068 [Byte1]: 42
8642 12:15:14.364703
8643 12:15:14.364874 Set Vref, RX VrefLevel [Byte0]: 43
8644 12:15:14.367847 [Byte1]: 43
8645 12:15:14.371802
8646 12:15:14.371945 Set Vref, RX VrefLevel [Byte0]: 44
8647 12:15:14.375346 [Byte1]: 44
8648 12:15:14.379275
8649 12:15:14.379465 Set Vref, RX VrefLevel [Byte0]: 45
8650 12:15:14.382695 [Byte1]: 45
8651 12:15:14.387250
8652 12:15:14.387442 Set Vref, RX VrefLevel [Byte0]: 46
8653 12:15:14.390526 [Byte1]: 46
8654 12:15:14.394562
8655 12:15:14.394674 Set Vref, RX VrefLevel [Byte0]: 47
8656 12:15:14.397828 [Byte1]: 47
8657 12:15:14.402266
8658 12:15:14.402378 Set Vref, RX VrefLevel [Byte0]: 48
8659 12:15:14.405447 [Byte1]: 48
8660 12:15:14.409461
8661 12:15:14.409573 Set Vref, RX VrefLevel [Byte0]: 49
8662 12:15:14.412803 [Byte1]: 49
8663 12:15:14.417402
8664 12:15:14.417521 Set Vref, RX VrefLevel [Byte0]: 50
8665 12:15:14.420571 [Byte1]: 50
8666 12:15:14.424842
8667 12:15:14.424970 Set Vref, RX VrefLevel [Byte0]: 51
8668 12:15:14.427984 [Byte1]: 51
8669 12:15:14.432168
8670 12:15:14.432311 Set Vref, RX VrefLevel [Byte0]: 52
8671 12:15:14.435519 [Byte1]: 52
8672 12:15:14.440001
8673 12:15:14.440184 Set Vref, RX VrefLevel [Byte0]: 53
8674 12:15:14.443035 [Byte1]: 53
8675 12:15:14.447560
8676 12:15:14.447733 Set Vref, RX VrefLevel [Byte0]: 54
8677 12:15:14.450738 [Byte1]: 54
8678 12:15:14.454576
8679 12:15:14.454728 Set Vref, RX VrefLevel [Byte0]: 55
8680 12:15:14.457829 [Byte1]: 55
8681 12:15:14.462654
8682 12:15:14.462819 Set Vref, RX VrefLevel [Byte0]: 56
8683 12:15:14.465956 [Byte1]: 56
8684 12:15:14.469750
8685 12:15:14.469879 Set Vref, RX VrefLevel [Byte0]: 57
8686 12:15:14.473181 [Byte1]: 57
8687 12:15:14.477081
8688 12:15:14.477237 Set Vref, RX VrefLevel [Byte0]: 58
8689 12:15:14.480950 [Byte1]: 58
8690 12:15:14.484856
8691 12:15:14.484998 Set Vref, RX VrefLevel [Byte0]: 59
8692 12:15:14.488197 [Byte1]: 59
8693 12:15:14.492295
8694 12:15:14.492426 Set Vref, RX VrefLevel [Byte0]: 60
8695 12:15:14.495634 [Byte1]: 60
8696 12:15:14.499603
8697 12:15:14.499760 Set Vref, RX VrefLevel [Byte0]: 61
8698 12:15:14.503332 [Byte1]: 61
8699 12:15:14.507820
8700 12:15:14.508001 Set Vref, RX VrefLevel [Byte0]: 62
8701 12:15:14.510482 [Byte1]: 62
8702 12:15:14.515132
8703 12:15:14.515313 Set Vref, RX VrefLevel [Byte0]: 63
8704 12:15:14.518488 [Byte1]: 63
8705 12:15:14.522839
8706 12:15:14.523019 Set Vref, RX VrefLevel [Byte0]: 64
8707 12:15:14.526092 [Byte1]: 64
8708 12:15:14.530103
8709 12:15:14.530278 Set Vref, RX VrefLevel [Byte0]: 65
8710 12:15:14.533229 [Byte1]: 65
8711 12:15:14.537710
8712 12:15:14.537893 Set Vref, RX VrefLevel [Byte0]: 66
8713 12:15:14.541048 [Byte1]: 66
8714 12:15:14.545095
8715 12:15:14.545277 Set Vref, RX VrefLevel [Byte0]: 67
8716 12:15:14.548260 [Byte1]: 67
8717 12:15:14.552559
8718 12:15:14.552747 Set Vref, RX VrefLevel [Byte0]: 68
8719 12:15:14.555951 [Byte1]: 68
8720 12:15:14.560486
8721 12:15:14.560670 Set Vref, RX VrefLevel [Byte0]: 69
8722 12:15:14.563644 [Byte1]: 69
8723 12:15:14.567536
8724 12:15:14.567711 Set Vref, RX VrefLevel [Byte0]: 70
8725 12:15:14.570856 [Byte1]: 70
8726 12:15:14.575532
8727 12:15:14.575717 Set Vref, RX VrefLevel [Byte0]: 71
8728 12:15:14.578946 [Byte1]: 71
8729 12:15:14.582982
8730 12:15:14.583163 Set Vref, RX VrefLevel [Byte0]: 72
8731 12:15:14.586286 [Byte1]: 72
8732 12:15:14.590083
8733 12:15:14.590266 Set Vref, RX VrefLevel [Byte0]: 73
8734 12:15:14.593475 [Byte1]: 73
8735 12:15:14.598056
8736 12:15:14.598208 Set Vref, RX VrefLevel [Byte0]: 74
8737 12:15:14.601304 [Byte1]: 74
8738 12:15:14.605402
8739 12:15:14.605560 Set Vref, RX VrefLevel [Byte0]: 75
8740 12:15:14.608631 [Byte1]: 75
8741 12:15:14.613073
8742 12:15:14.613252 Set Vref, RX VrefLevel [Byte0]: 76
8743 12:15:14.616452 [Byte1]: 76
8744 12:15:14.620545
8745 12:15:14.620685 Set Vref, RX VrefLevel [Byte0]: 77
8746 12:15:14.623945 [Byte1]: 77
8747 12:15:14.627790
8748 12:15:14.627935 Set Vref, RX VrefLevel [Byte0]: 78
8749 12:15:14.631640 [Byte1]: 78
8750 12:15:14.635587
8751 12:15:14.635734 Set Vref, RX VrefLevel [Byte0]: 79
8752 12:15:14.638731 [Byte1]: 79
8753 12:15:14.643078
8754 12:15:14.643230 Final RX Vref Byte 0 = 57 to rank0
8755 12:15:14.646371 Final RX Vref Byte 1 = 55 to rank0
8756 12:15:14.649833 Final RX Vref Byte 0 = 57 to rank1
8757 12:15:14.652895 Final RX Vref Byte 1 = 55 to rank1==
8758 12:15:14.656635 Dram Type= 6, Freq= 0, CH_1, rank 0
8759 12:15:14.663083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 12:15:14.663242 ==
8761 12:15:14.663313 DQS Delay:
8762 12:15:14.663421 DQS0 = 0, DQS1 = 0
8763 12:15:14.666368 DQM Delay:
8764 12:15:14.666565 DQM0 = 134, DQM1 = 131
8765 12:15:14.669546 DQ Delay:
8766 12:15:14.672863 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8767 12:15:14.676192 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =134
8768 12:15:14.679609 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8769 12:15:14.682823 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8770 12:15:14.683034
8771 12:15:14.683176
8772 12:15:14.683305
8773 12:15:14.686316 [DramC_TX_OE_Calibration] TA2
8774 12:15:14.689511 Original DQ_B0 (3 6) =30, OEN = 27
8775 12:15:14.692812 Original DQ_B1 (3 6) =30, OEN = 27
8776 12:15:14.695988 24, 0x0, End_B0=24 End_B1=24
8777 12:15:14.696208 25, 0x0, End_B0=25 End_B1=25
8778 12:15:14.699299 26, 0x0, End_B0=26 End_B1=26
8779 12:15:14.702792 27, 0x0, End_B0=27 End_B1=27
8780 12:15:14.706023 28, 0x0, End_B0=28 End_B1=28
8781 12:15:14.706237 29, 0x0, End_B0=29 End_B1=29
8782 12:15:14.709358 30, 0x0, End_B0=30 End_B1=30
8783 12:15:14.712701 31, 0x4141, End_B0=30 End_B1=30
8784 12:15:14.715883 Byte0 end_step=30 best_step=27
8785 12:15:14.719241 Byte1 end_step=30 best_step=27
8786 12:15:14.722532 Byte0 TX OE(2T, 0.5T) = (3, 3)
8787 12:15:14.722670 Byte1 TX OE(2T, 0.5T) = (3, 3)
8788 12:15:14.725895
8789 12:15:14.726039
8790 12:15:14.732961 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8791 12:15:14.736371 CH1 RK0: MR19=303, MR18=1825
8792 12:15:14.742937 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8793 12:15:14.743131
8794 12:15:14.746239 ----->DramcWriteLeveling(PI) begin...
8795 12:15:14.746399 ==
8796 12:15:14.749597 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 12:15:14.752723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 12:15:14.752902 ==
8799 12:15:14.756056 Write leveling (Byte 0): 25 => 25
8800 12:15:14.759352 Write leveling (Byte 1): 30 => 30
8801 12:15:14.762545 DramcWriteLeveling(PI) end<-----
8802 12:15:14.762703
8803 12:15:14.762796 ==
8804 12:15:14.766236 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 12:15:14.769361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 12:15:14.769497 ==
8807 12:15:14.772575 [Gating] SW mode calibration
8808 12:15:14.779368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8809 12:15:14.786013 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8810 12:15:14.789394 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 12:15:14.792716 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 12:15:14.799286 1 4 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8813 12:15:14.802596 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8814 12:15:14.805692 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 12:15:14.812366 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 12:15:14.815808 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 12:15:14.819700 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 12:15:14.826384 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 12:15:14.829735 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8820 12:15:14.832346 1 5 8 | B1->B0 | 3333 3434 | 1 0 | (0 0) (0 1)
8821 12:15:14.839585 1 5 12 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (1 0)
8822 12:15:14.842853 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 12:15:14.846222 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 12:15:14.852269 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 12:15:14.855572 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 12:15:14.859235 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 12:15:14.865963 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 12:15:14.869218 1 6 8 | B1->B0 | 3c3c 2323 | 0 0 | (0 0) (0 0)
8829 12:15:14.872592 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 12:15:14.878928 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 12:15:14.882152 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 12:15:14.886011 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 12:15:14.889191 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 12:15:14.896020 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 12:15:14.898693 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8836 12:15:14.902205 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8837 12:15:14.908724 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8838 12:15:14.912111 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8839 12:15:14.915291 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 12:15:14.922500 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 12:15:14.925713 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 12:15:14.928996 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 12:15:14.935772 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 12:15:14.939083 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 12:15:14.942319 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 12:15:14.948823 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 12:15:14.952181 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 12:15:14.955659 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 12:15:14.962146 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 12:15:14.965331 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 12:15:14.968958 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8852 12:15:14.975647 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8853 12:15:14.979037 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8854 12:15:14.982333 Total UI for P1: 0, mck2ui 16
8855 12:15:14.985344 best dqsien dly found for B1: ( 1, 9, 6)
8856 12:15:14.988485 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 12:15:14.992410 Total UI for P1: 0, mck2ui 16
8858 12:15:14.995607 best dqsien dly found for B0: ( 1, 9, 12)
8859 12:15:14.999045 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8860 12:15:15.001874 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8861 12:15:15.002008
8862 12:15:15.005877 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8863 12:15:15.012302 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8864 12:15:15.012474 [Gating] SW calibration Done
8865 12:15:15.012574 ==
8866 12:15:15.015661 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 12:15:15.021836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 12:15:15.022006 ==
8869 12:15:15.022107 RX Vref Scan: 0
8870 12:15:15.022199
8871 12:15:15.025153 RX Vref 0 -> 0, step: 1
8872 12:15:15.025283
8873 12:15:15.028557 RX Delay 0 -> 252, step: 8
8874 12:15:15.032336 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8875 12:15:15.035681 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8876 12:15:15.038938 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8877 12:15:15.042254 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8878 12:15:15.048705 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8879 12:15:15.051981 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8880 12:15:15.055389 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8881 12:15:15.058731 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8882 12:15:15.062119 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8883 12:15:15.068857 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8884 12:15:15.072022 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8885 12:15:15.075059 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8886 12:15:15.078655 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8887 12:15:15.081883 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8888 12:15:15.088556 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8889 12:15:15.091861 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8890 12:15:15.091994 ==
8891 12:15:15.094885 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 12:15:15.098687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 12:15:15.098867 ==
8894 12:15:15.102025 DQS Delay:
8895 12:15:15.102172 DQS0 = 0, DQS1 = 0
8896 12:15:15.105270 DQM Delay:
8897 12:15:15.105408 DQM0 = 136, DQM1 = 133
8898 12:15:15.105506 DQ Delay:
8899 12:15:15.108616 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8900 12:15:15.112037 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8901 12:15:15.118770 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8902 12:15:15.122067 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8903 12:15:15.122194
8904 12:15:15.122266
8905 12:15:15.122328 ==
8906 12:15:15.124990 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 12:15:15.128174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 12:15:15.128291 ==
8909 12:15:15.128386
8910 12:15:15.128477
8911 12:15:15.131649 TX Vref Scan disable
8912 12:15:15.134918 == TX Byte 0 ==
8913 12:15:15.138217 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8914 12:15:15.141624 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8915 12:15:15.145010 == TX Byte 1 ==
8916 12:15:15.148339 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8917 12:15:15.151609 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8918 12:15:15.151711 ==
8919 12:15:15.154877 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 12:15:15.158144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 12:15:15.161508 ==
8922 12:15:15.172979
8923 12:15:15.176491 TX Vref early break, caculate TX vref
8924 12:15:15.179090 TX Vref=16, minBit 0, minWin=23, winSum=385
8925 12:15:15.182890 TX Vref=18, minBit 0, minWin=23, winSum=393
8926 12:15:15.185875 TX Vref=20, minBit 0, minWin=24, winSum=398
8927 12:15:15.189064 TX Vref=22, minBit 0, minWin=25, winSum=413
8928 12:15:15.192395 TX Vref=24, minBit 13, minWin=25, winSum=418
8929 12:15:15.199015 TX Vref=26, minBit 0, minWin=25, winSum=425
8930 12:15:15.202708 TX Vref=28, minBit 0, minWin=26, winSum=424
8931 12:15:15.205865 TX Vref=30, minBit 6, minWin=25, winSum=420
8932 12:15:15.208982 TX Vref=32, minBit 6, minWin=24, winSum=410
8933 12:15:15.212477 TX Vref=34, minBit 0, minWin=24, winSum=400
8934 12:15:15.219223 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8935 12:15:15.219373
8936 12:15:15.222506 Final TX Range 0 Vref 28
8937 12:15:15.222590
8938 12:15:15.222665 ==
8939 12:15:15.225864 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 12:15:15.229087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 12:15:15.229200 ==
8942 12:15:15.229290
8943 12:15:15.229382
8944 12:15:15.232820 TX Vref Scan disable
8945 12:15:15.239296 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8946 12:15:15.239466 == TX Byte 0 ==
8947 12:15:15.242407 u2DelayCellOfst[0]=16 cells (5 PI)
8948 12:15:15.245756 u2DelayCellOfst[1]=10 cells (3 PI)
8949 12:15:15.248988 u2DelayCellOfst[2]=0 cells (0 PI)
8950 12:15:15.252427 u2DelayCellOfst[3]=6 cells (2 PI)
8951 12:15:15.255713 u2DelayCellOfst[4]=10 cells (3 PI)
8952 12:15:15.258719 u2DelayCellOfst[5]=16 cells (5 PI)
8953 12:15:15.262053 u2DelayCellOfst[6]=16 cells (5 PI)
8954 12:15:15.265353 u2DelayCellOfst[7]=6 cells (2 PI)
8955 12:15:15.268701 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8956 12:15:15.272694 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8957 12:15:15.275524 == TX Byte 1 ==
8958 12:15:15.275690 u2DelayCellOfst[8]=0 cells (0 PI)
8959 12:15:15.279296 u2DelayCellOfst[9]=3 cells (1 PI)
8960 12:15:15.282686 u2DelayCellOfst[10]=10 cells (3 PI)
8961 12:15:15.285492 u2DelayCellOfst[11]=3 cells (1 PI)
8962 12:15:15.288706 u2DelayCellOfst[12]=13 cells (4 PI)
8963 12:15:15.292551 u2DelayCellOfst[13]=16 cells (5 PI)
8964 12:15:15.295698 u2DelayCellOfst[14]=16 cells (5 PI)
8965 12:15:15.298952 u2DelayCellOfst[15]=16 cells (5 PI)
8966 12:15:15.302318 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8967 12:15:15.308848 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8968 12:15:15.308978 DramC Write-DBI on
8969 12:15:15.309076 ==
8970 12:15:15.312017 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 12:15:15.315805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 12:15:15.315931 ==
8973 12:15:15.319016
8974 12:15:15.319124
8975 12:15:15.319219 TX Vref Scan disable
8976 12:15:15.322395 == TX Byte 0 ==
8977 12:15:15.325750 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8978 12:15:15.329031 == TX Byte 1 ==
8979 12:15:15.332343 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8980 12:15:15.335773 DramC Write-DBI off
8981 12:15:15.335870
8982 12:15:15.335937 [DATLAT]
8983 12:15:15.335999 Freq=1600, CH1 RK1
8984 12:15:15.336086
8985 12:15:15.338810 DATLAT Default: 0xf
8986 12:15:15.338913 0, 0xFFFF, sum = 0
8987 12:15:15.342072 1, 0xFFFF, sum = 0
8988 12:15:15.342178 2, 0xFFFF, sum = 0
8989 12:15:15.345673 3, 0xFFFF, sum = 0
8990 12:15:15.348921 4, 0xFFFF, sum = 0
8991 12:15:15.349031 5, 0xFFFF, sum = 0
8992 12:15:15.352287 6, 0xFFFF, sum = 0
8993 12:15:15.352412 7, 0xFFFF, sum = 0
8994 12:15:15.355718 8, 0xFFFF, sum = 0
8995 12:15:15.355825 9, 0xFFFF, sum = 0
8996 12:15:15.359012 10, 0xFFFF, sum = 0
8997 12:15:15.359145 11, 0xFFFF, sum = 0
8998 12:15:15.362200 12, 0xFFFF, sum = 0
8999 12:15:15.362313 13, 0xFFFF, sum = 0
9000 12:15:15.365275 14, 0x0, sum = 1
9001 12:15:15.365394 15, 0x0, sum = 2
9002 12:15:15.368610 16, 0x0, sum = 3
9003 12:15:15.368724 17, 0x0, sum = 4
9004 12:15:15.371884 best_step = 15
9005 12:15:15.371990
9006 12:15:15.372082 ==
9007 12:15:15.375291 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 12:15:15.378599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 12:15:15.378713 ==
9010 12:15:15.378809 RX Vref Scan: 0
9011 12:15:15.381877
9012 12:15:15.381981 RX Vref 0 -> 0, step: 1
9013 12:15:15.382073
9014 12:15:15.385223 RX Delay 19 -> 252, step: 4
9015 12:15:15.388624 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9016 12:15:15.395160 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9017 12:15:15.398479 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9018 12:15:15.402403 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9019 12:15:15.405576 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9020 12:15:15.408784 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9021 12:15:15.412060 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9022 12:15:15.418585 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9023 12:15:15.421760 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9024 12:15:15.425603 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
9025 12:15:15.428932 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9026 12:15:15.432166 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9027 12:15:15.438711 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9028 12:15:15.442054 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9029 12:15:15.445287 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9030 12:15:15.448431 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9031 12:15:15.448516 ==
9032 12:15:15.452557 Dram Type= 6, Freq= 0, CH_1, rank 1
9033 12:15:15.458972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9034 12:15:15.459063 ==
9035 12:15:15.459132 DQS Delay:
9036 12:15:15.459193 DQS0 = 0, DQS1 = 0
9037 12:15:15.461677 DQM Delay:
9038 12:15:15.461761 DQM0 = 134, DQM1 = 130
9039 12:15:15.465471 DQ Delay:
9040 12:15:15.468759 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9041 12:15:15.472083 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9042 12:15:15.475239 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
9043 12:15:15.478524 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
9044 12:15:15.478612
9045 12:15:15.478678
9046 12:15:15.478739
9047 12:15:15.481903 [DramC_TX_OE_Calibration] TA2
9048 12:15:15.485389 Original DQ_B0 (3 6) =30, OEN = 27
9049 12:15:15.488683 Original DQ_B1 (3 6) =30, OEN = 27
9050 12:15:15.492062 24, 0x0, End_B0=24 End_B1=24
9051 12:15:15.492154 25, 0x0, End_B0=25 End_B1=25
9052 12:15:15.495281 26, 0x0, End_B0=26 End_B1=26
9053 12:15:15.498658 27, 0x0, End_B0=27 End_B1=27
9054 12:15:15.502060 28, 0x0, End_B0=28 End_B1=28
9055 12:15:15.502148 29, 0x0, End_B0=29 End_B1=29
9056 12:15:15.505252 30, 0x0, End_B0=30 End_B1=30
9057 12:15:15.508465 31, 0x4141, End_B0=30 End_B1=30
9058 12:15:15.511583 Byte0 end_step=30 best_step=27
9059 12:15:15.515336 Byte1 end_step=30 best_step=27
9060 12:15:15.518502 Byte0 TX OE(2T, 0.5T) = (3, 3)
9061 12:15:15.521929 Byte1 TX OE(2T, 0.5T) = (3, 3)
9062 12:15:15.522017
9063 12:15:15.522085
9064 12:15:15.528562 [DQSOSCAuto] RK1, (LSB)MR18= 0x2208, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9065 12:15:15.531691 CH1 RK1: MR19=303, MR18=2208
9066 12:15:15.538412 CH1_RK1: MR19=0x303, MR18=0x2208, DQSOSC=392, MR23=63, INC=24, DEC=16
9067 12:15:15.541732 [RxdqsGatingPostProcess] freq 1600
9068 12:15:15.545098 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9069 12:15:15.548341 best DQS0 dly(2T, 0.5T) = (1, 1)
9070 12:15:15.551729 best DQS1 dly(2T, 0.5T) = (1, 1)
9071 12:15:15.554925 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9072 12:15:15.558103 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9073 12:15:15.561274 best DQS0 dly(2T, 0.5T) = (1, 1)
9074 12:15:15.564625 best DQS1 dly(2T, 0.5T) = (1, 1)
9075 12:15:15.568516 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9076 12:15:15.571678 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9077 12:15:15.574852 Pre-setting of DQS Precalculation
9078 12:15:15.578164 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9079 12:15:15.584821 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9080 12:15:15.591501 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9081 12:15:15.594790
9082 12:15:15.594902
9083 12:15:15.594970 [Calibration Summary] 3200 Mbps
9084 12:15:15.598073 CH 0, Rank 0
9085 12:15:15.598159 SW Impedance : PASS
9086 12:15:15.601454 DUTY Scan : NO K
9087 12:15:15.604787 ZQ Calibration : PASS
9088 12:15:15.604871 Jitter Meter : NO K
9089 12:15:15.607981 CBT Training : PASS
9090 12:15:15.611481 Write leveling : PASS
9091 12:15:15.611563 RX DQS gating : PASS
9092 12:15:15.614685 RX DQ/DQS(RDDQC) : PASS
9093 12:15:15.617879 TX DQ/DQS : PASS
9094 12:15:15.617964 RX DATLAT : PASS
9095 12:15:15.620996 RX DQ/DQS(Engine): PASS
9096 12:15:15.624459 TX OE : PASS
9097 12:15:15.624544 All Pass.
9098 12:15:15.624608
9099 12:15:15.624669 CH 0, Rank 1
9100 12:15:15.627891 SW Impedance : PASS
9101 12:15:15.631174 DUTY Scan : NO K
9102 12:15:15.631304 ZQ Calibration : PASS
9103 12:15:15.634567 Jitter Meter : NO K
9104 12:15:15.637781 CBT Training : PASS
9105 12:15:15.637940 Write leveling : PASS
9106 12:15:15.641069 RX DQS gating : PASS
9107 12:15:15.641176 RX DQ/DQS(RDDQC) : PASS
9108 12:15:15.644756 TX DQ/DQS : PASS
9109 12:15:15.647972 RX DATLAT : PASS
9110 12:15:15.648100 RX DQ/DQS(Engine): PASS
9111 12:15:15.651248 TX OE : PASS
9112 12:15:15.651418 All Pass.
9113 12:15:15.651513
9114 12:15:15.654528 CH 1, Rank 0
9115 12:15:15.654720 SW Impedance : PASS
9116 12:15:15.657842 DUTY Scan : NO K
9117 12:15:15.660993 ZQ Calibration : PASS
9118 12:15:15.661144 Jitter Meter : NO K
9119 12:15:15.664301 CBT Training : PASS
9120 12:15:15.667531 Write leveling : PASS
9121 12:15:15.667671 RX DQS gating : PASS
9122 12:15:15.670819 RX DQ/DQS(RDDQC) : PASS
9123 12:15:15.674151 TX DQ/DQS : PASS
9124 12:15:15.674282 RX DATLAT : PASS
9125 12:15:15.677992 RX DQ/DQS(Engine): PASS
9126 12:15:15.681292 TX OE : PASS
9127 12:15:15.681386 All Pass.
9128 12:15:15.681454
9129 12:15:15.681516 CH 1, Rank 1
9130 12:15:15.684705 SW Impedance : PASS
9131 12:15:15.688082 DUTY Scan : NO K
9132 12:15:15.688168 ZQ Calibration : PASS
9133 12:15:15.690810 Jitter Meter : NO K
9134 12:15:15.690897 CBT Training : PASS
9135 12:15:15.694120 Write leveling : PASS
9136 12:15:15.697563 RX DQS gating : PASS
9137 12:15:15.697649 RX DQ/DQS(RDDQC) : PASS
9138 12:15:15.700835 TX DQ/DQS : PASS
9139 12:15:15.704129 RX DATLAT : PASS
9140 12:15:15.704218 RX DQ/DQS(Engine): PASS
9141 12:15:15.707522 TX OE : PASS
9142 12:15:15.707618 All Pass.
9143 12:15:15.707686
9144 12:15:15.710833 DramC Write-DBI on
9145 12:15:15.714148 PER_BANK_REFRESH: Hybrid Mode
9146 12:15:15.714280 TX_TRACKING: ON
9147 12:15:15.723995 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9148 12:15:15.730609 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9149 12:15:15.737587 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9150 12:15:15.744072 [FAST_K] Save calibration result to emmc
9151 12:15:15.744162 sync common calibartion params.
9152 12:15:15.747434 sync cbt_mode0:1, 1:1
9153 12:15:15.750686 dram_init: ddr_geometry: 2
9154 12:15:15.750772 dram_init: ddr_geometry: 2
9155 12:15:15.753874 dram_init: ddr_geometry: 2
9156 12:15:15.756950 0:dram_rank_size:100000000
9157 12:15:15.760235 1:dram_rank_size:100000000
9158 12:15:15.763716 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9159 12:15:15.767092 DFS_SHUFFLE_HW_MODE: ON
9160 12:15:15.770217 dramc_set_vcore_voltage set vcore to 725000
9161 12:15:15.773547 Read voltage for 1600, 0
9162 12:15:15.773660 Vio18 = 0
9163 12:15:15.776966 Vcore = 725000
9164 12:15:15.777076 Vdram = 0
9165 12:15:15.777172 Vddq = 0
9166 12:15:15.777264 Vmddr = 0
9167 12:15:15.780282 switch to 3200 Mbps bootup
9168 12:15:15.783598 [DramcRunTimeConfig]
9169 12:15:15.783710 PHYPLL
9170 12:15:15.786866 DPM_CONTROL_AFTERK: ON
9171 12:15:15.786975 PER_BANK_REFRESH: ON
9172 12:15:15.790343 REFRESH_OVERHEAD_REDUCTION: ON
9173 12:15:15.793597 CMD_PICG_NEW_MODE: OFF
9174 12:15:15.793704 XRTWTW_NEW_MODE: ON
9175 12:15:15.796916 XRTRTR_NEW_MODE: ON
9176 12:15:15.797023 TX_TRACKING: ON
9177 12:15:15.800442 RDSEL_TRACKING: OFF
9178 12:15:15.803776 DQS Precalculation for DVFS: ON
9179 12:15:15.803882 RX_TRACKING: OFF
9180 12:15:15.803977 HW_GATING DBG: ON
9181 12:15:15.807183 ZQCS_ENABLE_LP4: ON
9182 12:15:15.809807 RX_PICG_NEW_MODE: ON
9183 12:15:15.809916 TX_PICG_NEW_MODE: ON
9184 12:15:15.813297 ENABLE_RX_DCM_DPHY: ON
9185 12:15:15.816603 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9186 12:15:15.816717 DUMMY_READ_FOR_TRACKING: OFF
9187 12:15:15.819929 !!! SPM_CONTROL_AFTERK: OFF
9188 12:15:15.823300 !!! SPM could not control APHY
9189 12:15:15.826571 IMPEDANCE_TRACKING: ON
9190 12:15:15.826675 TEMP_SENSOR: ON
9191 12:15:15.829982 HW_SAVE_FOR_SR: OFF
9192 12:15:15.833219 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9193 12:15:15.836420 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9194 12:15:15.836526 Read ODT Tracking: ON
9195 12:15:15.839947 Refresh Rate DeBounce: ON
9196 12:15:15.843345 DFS_NO_QUEUE_FLUSH: ON
9197 12:15:15.846535 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9198 12:15:15.846619 ENABLE_DFS_RUNTIME_MRW: OFF
9199 12:15:15.849749 DDR_RESERVE_NEW_MODE: ON
9200 12:15:15.853014 MR_CBT_SWITCH_FREQ: ON
9201 12:15:15.853100 =========================
9202 12:15:15.873197 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9203 12:15:15.876570 dram_init: ddr_geometry: 2
9204 12:15:15.895099 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9205 12:15:15.897832 dram_init: dram init end (result: 0)
9206 12:15:15.904471 DRAM-K: Full calibration passed in 24456 msecs
9207 12:15:15.907940 MRC: failed to locate region type 0.
9208 12:15:15.908057 DRAM rank0 size:0x100000000,
9209 12:15:15.911414 DRAM rank1 size=0x100000000
9210 12:15:15.921625 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9211 12:15:15.928576 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9212 12:15:15.934472 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9213 12:15:15.941442 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9214 12:15:15.944779 DRAM rank0 size:0x100000000,
9215 12:15:15.948122 DRAM rank1 size=0x100000000
9216 12:15:15.948206 CBMEM:
9217 12:15:15.951441 IMD: root @ 0xfffff000 254 entries.
9218 12:15:15.954737 IMD: root @ 0xffffec00 62 entries.
9219 12:15:15.958033 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9220 12:15:15.961372 WARNING: RO_VPD is uninitialized or empty.
9221 12:15:15.967984 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9222 12:15:15.974607 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9223 12:15:15.987554 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9224 12:15:15.998903 BS: romstage times (exec / console): total (unknown) / 23987 ms
9225 12:15:15.999040
9226 12:15:15.999147
9227 12:15:16.008859 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9228 12:15:16.012188 ARM64: Exception handlers installed.
9229 12:15:16.015537 ARM64: Testing exception
9230 12:15:16.018836 ARM64: Done test exception
9231 12:15:16.018948 Enumerating buses...
9232 12:15:16.022109 Show all devs... Before device enumeration.
9233 12:15:16.025700 Root Device: enabled 1
9234 12:15:16.029023 CPU_CLUSTER: 0: enabled 1
9235 12:15:16.029128 CPU: 00: enabled 1
9236 12:15:16.032315 Compare with tree...
9237 12:15:16.032418 Root Device: enabled 1
9238 12:15:16.035740 CPU_CLUSTER: 0: enabled 1
9239 12:15:16.039085 CPU: 00: enabled 1
9240 12:15:16.039188 Root Device scanning...
9241 12:15:16.042405 scan_static_bus for Root Device
9242 12:15:16.045715 CPU_CLUSTER: 0 enabled
9243 12:15:16.048969 scan_static_bus for Root Device done
9244 12:15:16.052336 scan_bus: bus Root Device finished in 8 msecs
9245 12:15:16.052452 done
9246 12:15:16.058930 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9247 12:15:16.062193 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9248 12:15:16.068959 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9249 12:15:16.072227 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9250 12:15:16.075283 Allocating resources...
9251 12:15:16.078335 Reading resources...
9252 12:15:16.081649 Root Device read_resources bus 0 link: 0
9253 12:15:16.081741 DRAM rank0 size:0x100000000,
9254 12:15:16.084997 DRAM rank1 size=0x100000000
9255 12:15:16.088397 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9256 12:15:16.091717 CPU: 00 missing read_resources
9257 12:15:16.094988 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9258 12:15:16.102097 Root Device read_resources bus 0 link: 0 done
9259 12:15:16.102194 Done reading resources.
9260 12:15:16.108459 Show resources in subtree (Root Device)...After reading.
9261 12:15:16.111766 Root Device child on link 0 CPU_CLUSTER: 0
9262 12:15:16.115059 CPU_CLUSTER: 0 child on link 0 CPU: 00
9263 12:15:16.125105 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9264 12:15:16.125247 CPU: 00
9265 12:15:16.128509 Root Device assign_resources, bus 0 link: 0
9266 12:15:16.131699 CPU_CLUSTER: 0 missing set_resources
9267 12:15:16.137884 Root Device assign_resources, bus 0 link: 0 done
9268 12:15:16.138014 Done setting resources.
9269 12:15:16.144609 Show resources in subtree (Root Device)...After assigning values.
9270 12:15:16.147942 Root Device child on link 0 CPU_CLUSTER: 0
9271 12:15:16.151200 CPU_CLUSTER: 0 child on link 0 CPU: 00
9272 12:15:16.161201 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9273 12:15:16.161339 CPU: 00
9274 12:15:16.164886 Done allocating resources.
9275 12:15:16.171065 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9276 12:15:16.171192 Enabling resources...
9277 12:15:16.171304 done.
9278 12:15:16.177799 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9279 12:15:16.177938 Initializing devices...
9280 12:15:16.180947 Root Device init
9281 12:15:16.184163 init hardware done!
9282 12:15:16.184301 0x00000018: ctrlr->caps
9283 12:15:16.187302 52.000 MHz: ctrlr->f_max
9284 12:15:16.187459 0.400 MHz: ctrlr->f_min
9285 12:15:16.190650 0x40ff8080: ctrlr->voltages
9286 12:15:16.194070 sclk: 390625
9287 12:15:16.194192 Bus Width = 1
9288 12:15:16.194298 sclk: 390625
9289 12:15:16.197483 Bus Width = 1
9290 12:15:16.197603 Early init status = 3
9291 12:15:16.203990 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9292 12:15:16.207139 in-header: 03 fc 00 00 01 00 00 00
9293 12:15:16.210416 in-data: 00
9294 12:15:16.213616 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9295 12:15:16.217475 in-header: 03 fd 00 00 00 00 00 00
9296 12:15:16.220789 in-data:
9297 12:15:16.224170 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9298 12:15:16.228155 in-header: 03 fc 00 00 01 00 00 00
9299 12:15:16.230861 in-data: 00
9300 12:15:16.234244 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9301 12:15:16.239753 in-header: 03 fd 00 00 00 00 00 00
9302 12:15:16.243121 in-data:
9303 12:15:16.246487 [SSUSB] Setting up USB HOST controller...
9304 12:15:16.249931 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9305 12:15:16.253270 [SSUSB] phy power-on done.
9306 12:15:16.256014 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9307 12:15:16.262637 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9308 12:15:16.266518 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9309 12:15:16.273043 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9310 12:15:16.279759 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9311 12:15:16.286559 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9312 12:15:16.292904 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9313 12:15:16.299553 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9314 12:15:16.303007 SPM: binary array size = 0x9dc
9315 12:15:16.306263 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9316 12:15:16.312927 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9317 12:15:16.319189 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9318 12:15:16.322559 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9319 12:15:16.329418 configure_display: Starting display init
9320 12:15:16.362990 anx7625_power_on_init: Init interface.
9321 12:15:16.366421 anx7625_disable_pd_protocol: Disabled PD feature.
9322 12:15:16.369743 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9323 12:15:16.397326 anx7625_start_dp_work: Secure OCM version=00
9324 12:15:16.400640 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9325 12:15:16.415961 sp_tx_get_edid_block: EDID Block = 1
9326 12:15:16.518159 Extracted contents:
9327 12:15:16.521506 header: 00 ff ff ff ff ff ff 00
9328 12:15:16.524848 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9329 12:15:16.528235 version: 01 04
9330 12:15:16.531310 basic params: 95 1f 11 78 0a
9331 12:15:16.534464 chroma info: 76 90 94 55 54 90 27 21 50 54
9332 12:15:16.537780 established: 00 00 00
9333 12:15:16.544889 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9334 12:15:16.548264 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9335 12:15:16.554345 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9336 12:15:16.561117 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9337 12:15:16.568000 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9338 12:15:16.571349 extensions: 00
9339 12:15:16.571449 checksum: fb
9340 12:15:16.571551
9341 12:15:16.574828 Manufacturer: IVO Model 57d Serial Number 0
9342 12:15:16.577595 Made week 0 of 2020
9343 12:15:16.577696 EDID version: 1.4
9344 12:15:16.580936 Digital display
9345 12:15:16.584293 6 bits per primary color channel
9346 12:15:16.584428 DisplayPort interface
9347 12:15:16.587520 Maximum image size: 31 cm x 17 cm
9348 12:15:16.591704 Gamma: 220%
9349 12:15:16.591839 Check DPMS levels
9350 12:15:16.594144 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9351 12:15:16.597896 First detailed timing is preferred timing
9352 12:15:16.601287 Established timings supported:
9353 12:15:16.604610 Standard timings supported:
9354 12:15:16.607969 Detailed timings
9355 12:15:16.610639 Hex of detail: 383680a07038204018303c0035ae10000019
9356 12:15:16.614000 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9357 12:15:16.621092 0780 0798 07c8 0820 hborder 0
9358 12:15:16.624224 0438 043b 0447 0458 vborder 0
9359 12:15:16.627543 -hsync -vsync
9360 12:15:16.627699 Did detailed timing
9361 12:15:16.634309 Hex of detail: 000000000000000000000000000000000000
9362 12:15:16.634457 Manufacturer-specified data, tag 0
9363 12:15:16.640843 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9364 12:15:16.644005 ASCII string: InfoVision
9365 12:15:16.647194 Hex of detail: 000000fe00523134304e574635205248200a
9366 12:15:16.650475 ASCII string: R140NWF5 RH
9367 12:15:16.650657 Checksum
9368 12:15:16.650782 Checksum: 0xfb (valid)
9369 12:15:16.657159 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9370 12:15:16.660584 DSI data_rate: 832800000 bps
9371 12:15:16.667420 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9372 12:15:16.670748 anx7625_parse_edid: pixelclock(138800).
9373 12:15:16.674152 hactive(1920), hsync(48), hfp(24), hbp(88)
9374 12:15:16.677495 vactive(1080), vsync(12), vfp(3), vbp(17)
9375 12:15:16.680847 anx7625_dsi_config: config dsi.
9376 12:15:16.687617 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9377 12:15:16.700281 anx7625_dsi_config: success to config DSI
9378 12:15:16.703446 anx7625_dp_start: MIPI phy setup OK.
9379 12:15:16.706477 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9380 12:15:16.710169 mtk_ddp_mode_set invalid vrefresh 60
9381 12:15:16.713419 main_disp_path_setup
9382 12:15:16.713588 ovl_layer_smi_id_en
9383 12:15:16.716855 ovl_layer_smi_id_en
9384 12:15:16.717013 ccorr_config
9385 12:15:16.717137 aal_config
9386 12:15:16.720299 gamma_config
9387 12:15:16.720385 postmask_config
9388 12:15:16.723012 dither_config
9389 12:15:16.726316 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9390 12:15:16.733512 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9391 12:15:16.736953 Root Device init finished in 552 msecs
9392 12:15:16.739580 CPU_CLUSTER: 0 init
9393 12:15:16.746308 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9394 12:15:16.749979 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9395 12:15:16.753231 APU_MBOX 0x190000b0 = 0x10001
9396 12:15:16.756641 APU_MBOX 0x190001b0 = 0x10001
9397 12:15:16.759642 APU_MBOX 0x190005b0 = 0x10001
9398 12:15:16.762963 APU_MBOX 0x190006b0 = 0x10001
9399 12:15:16.766525 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9400 12:15:16.779240 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9401 12:15:16.791585 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9402 12:15:16.798206 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9403 12:15:16.809470 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9404 12:15:16.818960 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9405 12:15:16.822195 CPU_CLUSTER: 0 init finished in 81 msecs
9406 12:15:16.825601 Devices initialized
9407 12:15:16.828946 Show all devs... After init.
9408 12:15:16.829081 Root Device: enabled 1
9409 12:15:16.832289 CPU_CLUSTER: 0: enabled 1
9410 12:15:16.835619 CPU: 00: enabled 1
9411 12:15:16.838733 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9412 12:15:16.842536 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9413 12:15:16.856238 ELOG: NV offset 0x57f000 size 0x1000
9414 12:15:16.856434 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9415 12:15:16.858473 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9416 12:15:16.862313 ELOG: Event(17) added with size 13 at 2023-06-06 12:15:10 UTC
9417 12:15:16.865613 out: cmd=0x121: 03 db 21 01 00 00 00 00
9418 12:15:16.869516 in-header: 03 db 00 00 2c 00 00 00
9419 12:15:16.882223 in-data: 84 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9420 12:15:16.889117 ELOG: Event(A1) added with size 10 at 2023-06-06 12:15:10 UTC
9421 12:15:16.895956 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9422 12:15:16.902282 ELOG: Event(A0) added with size 9 at 2023-06-06 12:15:10 UTC
9423 12:15:16.905695 elog_add_boot_reason: Logged dev mode boot
9424 12:15:16.908783 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9425 12:15:16.912160 Finalize devices...
9426 12:15:16.912263 Devices finalized
9427 12:15:16.918979 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9428 12:15:16.922333 Writing coreboot table at 0xffe64000
9429 12:15:16.925697 0. 000000000010a000-0000000000113fff: RAMSTAGE
9430 12:15:16.928670 1. 0000000040000000-00000000400fffff: RAM
9431 12:15:16.932597 2. 0000000040100000-000000004032afff: RAMSTAGE
9432 12:15:16.938762 3. 000000004032b000-00000000545fffff: RAM
9433 12:15:16.942137 4. 0000000054600000-000000005465ffff: BL31
9434 12:15:16.945587 5. 0000000054660000-00000000ffe63fff: RAM
9435 12:15:16.951904 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9436 12:15:16.955222 7. 0000000100000000-000000023fffffff: RAM
9437 12:15:16.955356 Passing 5 GPIOs to payload:
9438 12:15:16.961974 NAME | PORT | POLARITY | VALUE
9439 12:15:16.965214 EC in RW | 0x000000aa | low | undefined
9440 12:15:16.972325 EC interrupt | 0x00000005 | low | undefined
9441 12:15:16.975638 TPM interrupt | 0x000000ab | high | undefined
9442 12:15:16.978937 SD card detect | 0x00000011 | high | undefined
9443 12:15:16.985775 speaker enable | 0x00000093 | high | undefined
9444 12:15:16.988546 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9445 12:15:16.991955 in-header: 03 f9 00 00 02 00 00 00
9446 12:15:16.992088 in-data: 02 00
9447 12:15:16.995292 ADC[4]: Raw value=903988 ID=7
9448 12:15:16.998701 ADC[3]: Raw value=213810 ID=1
9449 12:15:16.998838 RAM Code: 0x71
9450 12:15:17.002310 ADC[6]: Raw value=75701 ID=0
9451 12:15:17.005551 ADC[5]: Raw value=213072 ID=1
9452 12:15:17.005652 SKU Code: 0x1
9453 12:15:17.012303 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d697
9454 12:15:17.015634 coreboot table: 964 bytes.
9455 12:15:17.018890 IMD ROOT 0. 0xfffff000 0x00001000
9456 12:15:17.022338 IMD SMALL 1. 0xffffe000 0x00001000
9457 12:15:17.025845 RO MCACHE 2. 0xffffc000 0x00001104
9458 12:15:17.028551 CONSOLE 3. 0xfff7c000 0x00080000
9459 12:15:17.032405 FMAP 4. 0xfff7b000 0x00000452
9460 12:15:17.035677 TIME STAMP 5. 0xfff7a000 0x00000910
9461 12:15:17.038765 VBOOT WORK 6. 0xfff66000 0x00014000
9462 12:15:17.042019 RAMOOPS 7. 0xffe66000 0x00100000
9463 12:15:17.045392 COREBOOT 8. 0xffe64000 0x00002000
9464 12:15:17.045498 IMD small region:
9465 12:15:17.048807 IMD ROOT 0. 0xffffec00 0x00000400
9466 12:15:17.052102 VPD 1. 0xffffeba0 0x0000004c
9467 12:15:17.055217 MMC STATUS 2. 0xffffeb80 0x00000004
9468 12:15:17.062587 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9469 12:15:17.062734 Probing TPM: done!
9470 12:15:17.069327 Connected to device vid:did:rid of 1ae0:0028:00
9471 12:15:17.075922 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9472 12:15:17.083307 Initialized TPM device CR50 revision 0
9473 12:15:17.083471 Checking cr50 for pending updates
9474 12:15:17.088569 Reading cr50 TPM mode
9475 12:15:17.097194 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9476 12:15:17.103884 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9477 12:15:17.144014 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9478 12:15:17.147828 Checking segment from ROM address 0x40100000
9479 12:15:17.151070 Checking segment from ROM address 0x4010001c
9480 12:15:17.157832 Loading segment from ROM address 0x40100000
9481 12:15:17.157999 code (compression=0)
9482 12:15:17.164299 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9483 12:15:17.174691 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9484 12:15:17.174880 it's not compressed!
9485 12:15:17.180894 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9486 12:15:17.184176 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9487 12:15:17.204450 Loading segment from ROM address 0x4010001c
9488 12:15:17.204605 Entry Point 0x80000000
9489 12:15:17.207931 Loaded segments
9490 12:15:17.211207 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9491 12:15:17.218124 Jumping to boot code at 0x80000000(0xffe64000)
9492 12:15:17.224731 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9493 12:15:17.231490 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9494 12:15:17.238984 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9495 12:15:17.242268 Checking segment from ROM address 0x40100000
9496 12:15:17.245801 Checking segment from ROM address 0x4010001c
9497 12:15:17.252348 Loading segment from ROM address 0x40100000
9498 12:15:17.252517 code (compression=1)
9499 12:15:17.258796 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9500 12:15:17.269020 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9501 12:15:17.269162 using LZMA
9502 12:15:17.277430 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9503 12:15:17.284106 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9504 12:15:17.287299 Loading segment from ROM address 0x4010001c
9505 12:15:17.287489 Entry Point 0x54601000
9506 12:15:17.290621 Loaded segments
9507 12:15:17.293876 NOTICE: MT8192 bl31_setup
9508 12:15:17.301341 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9509 12:15:17.304527 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9510 12:15:17.307869 WARNING: region 0:
9511 12:15:17.311098 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 12:15:17.311250 WARNING: region 1:
9513 12:15:17.317971 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9514 12:15:17.321332 WARNING: region 2:
9515 12:15:17.324528 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9516 12:15:17.327865 WARNING: region 3:
9517 12:15:17.331144 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9518 12:15:17.334643 WARNING: region 4:
9519 12:15:17.337954 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9520 12:15:17.341424 WARNING: region 5:
9521 12:15:17.344719 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 12:15:17.348034 WARNING: region 6:
9523 12:15:17.350837 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 12:15:17.350977 WARNING: region 7:
9525 12:15:17.357562 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 12:15:17.364641 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9527 12:15:17.367914 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9528 12:15:17.370714 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9529 12:15:17.378050 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9530 12:15:17.381305 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9531 12:15:17.384713 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9532 12:15:17.391224 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9533 12:15:17.394622 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9534 12:15:17.401224 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9535 12:15:17.404602 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9536 12:15:17.407896 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9537 12:15:17.414460 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9538 12:15:17.417836 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9539 12:15:17.421112 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9540 12:15:17.427868 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9541 12:15:17.431216 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9542 12:15:17.434565 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9543 12:15:17.441057 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9544 12:15:17.444503 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9545 12:15:17.447887 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9546 12:15:17.454628 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9547 12:15:17.458219 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9548 12:15:17.464369 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9549 12:15:17.467675 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9550 12:15:17.474608 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9551 12:15:17.477951 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9552 12:15:17.481257 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9553 12:15:17.487721 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9554 12:15:17.491478 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9555 12:15:17.494710 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9556 12:15:17.501401 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9557 12:15:17.504623 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9558 12:15:17.507982 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9559 12:15:17.514626 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9560 12:15:17.517673 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9561 12:15:17.520998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9562 12:15:17.524471 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9563 12:15:17.531130 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9564 12:15:17.534446 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9565 12:15:17.538313 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9566 12:15:17.540994 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9567 12:15:17.548368 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9568 12:15:17.551591 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9569 12:15:17.555034 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9570 12:15:17.557704 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9571 12:15:17.564556 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9572 12:15:17.567960 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9573 12:15:17.571183 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9574 12:15:17.578392 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9575 12:15:17.581587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9576 12:15:17.584878 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9577 12:15:17.591694 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9578 12:15:17.594869 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9579 12:15:17.601399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9580 12:15:17.604669 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9581 12:15:17.608587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9582 12:15:17.614734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9583 12:15:17.617998 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9584 12:15:17.625098 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9585 12:15:17.628394 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9586 12:15:17.635083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9587 12:15:17.637897 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9588 12:15:17.644843 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9589 12:15:17.648256 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9590 12:15:17.651433 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9591 12:15:17.658177 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9592 12:15:17.661535 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9593 12:15:17.668288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9594 12:15:17.671703 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9595 12:15:17.677871 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9596 12:15:17.681869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9597 12:15:17.685069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9598 12:15:17.691725 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9599 12:15:17.695104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9600 12:15:17.701756 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9601 12:15:17.705020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9602 12:15:17.711294 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9603 12:15:17.714694 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9604 12:15:17.718112 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9605 12:15:17.724905 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9606 12:15:17.728121 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9607 12:15:17.735180 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9608 12:15:17.737923 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9609 12:15:17.744868 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9610 12:15:17.747954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9611 12:15:17.751262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9612 12:15:17.758009 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9613 12:15:17.761488 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9614 12:15:17.768367 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9615 12:15:17.771659 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9616 12:15:17.778350 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9617 12:15:17.781875 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9618 12:15:17.785244 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9619 12:15:17.791828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9620 12:15:17.794902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9621 12:15:17.801450 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9622 12:15:17.804788 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9623 12:15:17.808089 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9624 12:15:17.815147 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9625 12:15:17.818495 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9626 12:15:17.821739 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9627 12:15:17.825109 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9628 12:15:17.831932 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9629 12:15:17.835136 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9630 12:15:17.841621 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9631 12:15:17.845013 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9632 12:15:17.848603 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9633 12:15:17.855008 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9634 12:15:17.858373 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9635 12:15:17.865103 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9636 12:15:17.868533 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9637 12:15:17.871852 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9638 12:15:17.878559 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9639 12:15:17.882053 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9640 12:15:17.888799 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9641 12:15:17.891642 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9642 12:15:17.895035 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9643 12:15:17.898353 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9644 12:15:17.905496 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9645 12:15:17.908792 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9646 12:15:17.912209 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9647 12:15:17.915524 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9648 12:15:17.921914 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9649 12:15:17.925725 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9650 12:15:17.928933 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9651 12:15:17.935051 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9652 12:15:17.938330 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9653 12:15:17.945056 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9654 12:15:17.948791 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9655 12:15:17.952086 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9656 12:15:17.958582 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9657 12:15:17.961981 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9658 12:15:17.965344 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9659 12:15:17.972084 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9660 12:15:17.975501 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9661 12:15:17.981698 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9662 12:15:17.985142 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9663 12:15:17.988545 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9664 12:15:17.995143 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9665 12:15:17.998630 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9666 12:15:18.005139 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9667 12:15:18.008610 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9668 12:15:18.011619 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9669 12:15:18.018747 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9670 12:15:18.022087 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9671 12:15:18.025475 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9672 12:15:18.031780 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9673 12:15:18.035435 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9674 12:15:18.042217 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9675 12:15:18.045443 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9676 12:15:18.048797 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9677 12:15:18.055103 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9678 12:15:18.058928 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9679 12:15:18.062159 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9680 12:15:18.068532 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9681 12:15:18.072508 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9682 12:15:18.078593 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9683 12:15:18.081905 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9684 12:15:18.085474 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9685 12:15:18.092084 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9686 12:15:18.095418 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9687 12:15:18.102114 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9688 12:15:18.105426 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9689 12:15:18.108722 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9690 12:15:18.115494 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9691 12:15:18.118696 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9692 12:15:18.121920 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9693 12:15:18.128643 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9694 12:15:18.131975 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9695 12:15:18.138371 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9696 12:15:18.142161 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9697 12:15:18.145188 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9698 12:15:18.151831 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9699 12:15:18.155215 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9700 12:15:18.161883 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9701 12:15:18.165121 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9702 12:15:18.168456 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9703 12:15:18.174978 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9704 12:15:18.178061 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9705 12:15:18.184570 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9706 12:15:18.187934 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9707 12:15:18.191320 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9708 12:15:18.198107 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9709 12:15:18.201545 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9710 12:15:18.208332 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9711 12:15:18.211683 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9712 12:15:18.214452 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9713 12:15:18.221150 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9714 12:15:18.224475 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9715 12:15:18.231134 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9716 12:15:18.234560 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9717 12:15:18.241381 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9718 12:15:18.244615 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9719 12:15:18.247866 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9720 12:15:18.254139 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9721 12:15:18.258157 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9722 12:15:18.264201 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9723 12:15:18.267567 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9724 12:15:18.271236 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9725 12:15:18.277757 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9726 12:15:18.281130 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9727 12:15:18.287619 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9728 12:15:18.291286 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9729 12:15:18.294013 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9730 12:15:18.300709 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9731 12:15:18.304763 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9732 12:15:18.310728 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9733 12:15:18.314266 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9734 12:15:18.320869 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9735 12:15:18.324198 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9736 12:15:18.327606 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9737 12:15:18.333904 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9738 12:15:18.337265 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9739 12:15:18.344705 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9740 12:15:18.348109 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9741 12:15:18.350569 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9742 12:15:18.357556 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9743 12:15:18.360709 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9744 12:15:18.367779 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9745 12:15:18.371066 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9746 12:15:18.377538 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9747 12:15:18.380572 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9748 12:15:18.384481 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9749 12:15:18.390956 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9750 12:15:18.394232 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9751 12:15:18.400609 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9752 12:15:18.403947 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9753 12:15:18.407306 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9754 12:15:18.414033 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9755 12:15:18.417355 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9756 12:15:18.420834 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9757 12:15:18.424330 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9758 12:15:18.431011 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9759 12:15:18.433792 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9760 12:15:18.437048 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9761 12:15:18.444174 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9762 12:15:18.447494 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9763 12:15:18.454047 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9764 12:15:18.457341 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9765 12:15:18.460734 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9766 12:15:18.467466 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9767 12:15:18.470622 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9768 12:15:18.474011 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9769 12:15:18.480587 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9770 12:15:18.483804 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9771 12:15:18.487223 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9772 12:15:18.493425 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9773 12:15:18.496778 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9774 12:15:18.500665 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9775 12:15:18.507017 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9776 12:15:18.510389 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9777 12:15:18.517042 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9778 12:15:18.520333 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9779 12:15:18.523594 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9780 12:15:18.530371 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9781 12:15:18.533832 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9782 12:15:18.537240 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9783 12:15:18.543196 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9784 12:15:18.546962 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9785 12:15:18.550325 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9786 12:15:18.556440 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9787 12:15:18.560331 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9788 12:15:18.567014 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9789 12:15:18.569813 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9790 12:15:18.573160 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9791 12:15:18.580138 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9792 12:15:18.583539 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9793 12:15:18.587021 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9794 12:15:18.592979 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9795 12:15:18.596998 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9796 12:15:18.600154 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9797 12:15:18.603050 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9798 12:15:18.609650 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9799 12:15:18.613004 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9800 12:15:18.616288 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9801 12:15:18.619758 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9802 12:15:18.626494 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9803 12:15:18.630018 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9804 12:15:18.633609 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9805 12:15:18.636778 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9806 12:15:18.643131 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9807 12:15:18.646538 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9808 12:15:18.649854 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9809 12:15:18.656418 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9810 12:15:18.660103 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9811 12:15:18.666737 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9812 12:15:18.670010 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9813 12:15:18.673516 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9814 12:15:18.680329 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9815 12:15:18.683522 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9816 12:15:18.686949 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9817 12:15:18.692975 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9818 12:15:18.696348 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9819 12:15:18.703057 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9820 12:15:18.706458 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9821 12:15:18.713295 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9822 12:15:18.716581 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9823 12:15:18.719941 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9824 12:15:18.726575 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9825 12:15:18.729937 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9826 12:15:18.736705 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9827 12:15:18.740058 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9828 12:15:18.742808 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9829 12:15:18.749590 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9830 12:15:18.752951 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9831 12:15:18.759571 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9832 12:15:18.762817 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9833 12:15:18.766617 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9834 12:15:18.773095 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9835 12:15:18.776571 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9836 12:15:18.783262 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9837 12:15:18.785978 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9838 12:15:18.792751 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9839 12:15:18.795884 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9840 12:15:18.799671 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9841 12:15:18.806250 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9842 12:15:18.809594 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9843 12:15:18.816258 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9844 12:15:18.819344 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9845 12:15:18.825206 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9846 12:15:18.829375 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9847 12:15:18.832689 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9848 12:15:18.839453 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9849 12:15:18.842917 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9850 12:15:18.846250 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9851 12:15:18.852370 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9852 12:15:18.855780 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9853 12:15:18.862511 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9854 12:15:18.865782 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9855 12:15:18.869170 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9856 12:15:18.876229 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9857 12:15:18.879260 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9858 12:15:18.885906 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9859 12:15:18.889334 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9860 12:15:18.892770 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9861 12:15:18.899390 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9862 12:15:18.902701 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9863 12:15:18.909137 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9864 12:15:18.912507 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9865 12:15:18.915874 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9866 12:15:18.922551 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9867 12:15:18.925833 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9868 12:15:18.932407 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9869 12:15:18.935745 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9870 12:15:18.942179 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9871 12:15:18.945480 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9872 12:15:18.948912 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9873 12:15:18.955596 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9874 12:15:18.959060 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9875 12:15:18.965916 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9876 12:15:18.968645 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9877 12:15:18.972076 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9878 12:15:18.978810 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9879 12:15:18.981855 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9880 12:15:18.989148 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9881 12:15:18.992142 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9882 12:15:18.998738 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9883 12:15:19.002139 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9884 12:15:19.005585 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9885 12:15:19.011644 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9886 12:15:19.014934 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9887 12:15:19.021987 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9888 12:15:19.025437 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9889 12:15:19.031657 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9890 12:15:19.034926 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9891 12:15:19.038113 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9892 12:15:19.045307 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9893 12:15:19.048717 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9894 12:15:19.054846 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9895 12:15:19.058248 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9896 12:15:19.065039 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9897 12:15:19.068496 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9898 12:15:19.071808 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9899 12:15:19.078802 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9900 12:15:19.082043 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9901 12:15:19.088456 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9902 12:15:19.091685 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9903 12:15:19.097952 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9904 12:15:19.101380 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9905 12:15:19.104815 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9906 12:15:19.111561 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9907 12:15:19.114876 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9908 12:15:19.121644 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9909 12:15:19.124855 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9910 12:15:19.131859 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9911 12:15:19.135141 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9912 12:15:19.138685 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9913 12:15:19.145173 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9914 12:15:19.148393 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9915 12:15:19.155088 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9916 12:15:19.158426 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9917 12:15:19.165273 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9918 12:15:19.168746 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9919 12:15:19.172026 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9920 12:15:19.178704 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9921 12:15:19.181551 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9922 12:15:19.188238 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9923 12:15:19.191601 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9924 12:15:19.198537 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9925 12:15:19.201645 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9926 12:15:19.208664 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9927 12:15:19.211255 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9928 12:15:19.214741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9929 12:15:19.221343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9930 12:15:19.224676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9931 12:15:19.231285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9932 12:15:19.234581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9933 12:15:19.241490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9934 12:15:19.244956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9935 12:15:19.248222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9936 12:15:19.254639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9937 12:15:19.257959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9938 12:15:19.264743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9939 12:15:19.268043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9940 12:15:19.274771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9941 12:15:19.278048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9942 12:15:19.284828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9943 12:15:19.288077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9944 12:15:19.294308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9945 12:15:19.297732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9946 12:15:19.304919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9947 12:15:19.308098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9948 12:15:19.314518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9949 12:15:19.317635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9950 12:15:19.324367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9951 12:15:19.327838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9952 12:15:19.334431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9953 12:15:19.337847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9954 12:15:19.344211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9955 12:15:19.347681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9956 12:15:19.354361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9957 12:15:19.357616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9958 12:15:19.364900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9959 12:15:19.367317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9960 12:15:19.370759 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9961 12:15:19.374061 INFO: [APUAPC] vio 0
9962 12:15:19.380870 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9963 12:15:19.384286 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9964 12:15:19.387603 INFO: [APUAPC] D0_APC_0: 0x400510
9965 12:15:19.390990 INFO: [APUAPC] D0_APC_1: 0x0
9966 12:15:19.394485 INFO: [APUAPC] D0_APC_2: 0x1540
9967 12:15:19.397841 INFO: [APUAPC] D0_APC_3: 0x0
9968 12:15:19.400662 INFO: [APUAPC] D1_APC_0: 0xffffffff
9969 12:15:19.404049 INFO: [APUAPC] D1_APC_1: 0xffffffff
9970 12:15:19.407396 INFO: [APUAPC] D1_APC_2: 0x3fffff
9971 12:15:19.410576 INFO: [APUAPC] D1_APC_3: 0x0
9972 12:15:19.414271 INFO: [APUAPC] D2_APC_0: 0xffffffff
9973 12:15:19.417549 INFO: [APUAPC] D2_APC_1: 0xffffffff
9974 12:15:19.420789 INFO: [APUAPC] D2_APC_2: 0x3fffff
9975 12:15:19.424042 INFO: [APUAPC] D2_APC_3: 0x0
9976 12:15:19.427193 INFO: [APUAPC] D3_APC_0: 0xffffffff
9977 12:15:19.430598 INFO: [APUAPC] D3_APC_1: 0xffffffff
9978 12:15:19.434426 INFO: [APUAPC] D3_APC_2: 0x3fffff
9979 12:15:19.434514 INFO: [APUAPC] D3_APC_3: 0x0
9980 12:15:19.437252 INFO: [APUAPC] D4_APC_0: 0xffffffff
9981 12:15:19.443976 INFO: [APUAPC] D4_APC_1: 0xffffffff
9982 12:15:19.444066 INFO: [APUAPC] D4_APC_2: 0x3fffff
9983 12:15:19.447315 INFO: [APUAPC] D4_APC_3: 0x0
9984 12:15:19.450608 INFO: [APUAPC] D5_APC_0: 0xffffffff
9985 12:15:19.453827 INFO: [APUAPC] D5_APC_1: 0xffffffff
9986 12:15:19.457280 INFO: [APUAPC] D5_APC_2: 0x3fffff
9987 12:15:19.460746 INFO: [APUAPC] D5_APC_3: 0x0
9988 12:15:19.463964 INFO: [APUAPC] D6_APC_0: 0xffffffff
9989 12:15:19.467220 INFO: [APUAPC] D6_APC_1: 0xffffffff
9990 12:15:19.470954 INFO: [APUAPC] D6_APC_2: 0x3fffff
9991 12:15:19.474223 INFO: [APUAPC] D6_APC_3: 0x0
9992 12:15:19.477543 INFO: [APUAPC] D7_APC_0: 0xffffffff
9993 12:15:19.480867 INFO: [APUAPC] D7_APC_1: 0xffffffff
9994 12:15:19.484219 INFO: [APUAPC] D7_APC_2: 0x3fffff
9995 12:15:19.487522 INFO: [APUAPC] D7_APC_3: 0x0
9996 12:15:19.490801 INFO: [APUAPC] D8_APC_0: 0xffffffff
9997 12:15:19.494095 INFO: [APUAPC] D8_APC_1: 0xffffffff
9998 12:15:19.497385 INFO: [APUAPC] D8_APC_2: 0x3fffff
9999 12:15:19.500745 INFO: [APUAPC] D8_APC_3: 0x0
10000 12:15:19.503571 INFO: [APUAPC] D9_APC_0: 0xffffffff
10001 12:15:19.506862 INFO: [APUAPC] D9_APC_1: 0xffffffff
10002 12:15:19.510344 INFO: [APUAPC] D9_APC_2: 0x3fffff
10003 12:15:19.513601 INFO: [APUAPC] D9_APC_3: 0x0
10004 12:15:19.516944 INFO: [APUAPC] D10_APC_0: 0xffffffff
10005 12:15:19.520698 INFO: [APUAPC] D10_APC_1: 0xffffffff
10006 12:15:19.523836 INFO: [APUAPC] D10_APC_2: 0x3fffff
10007 12:15:19.527014 INFO: [APUAPC] D10_APC_3: 0x0
10008 12:15:19.530195 INFO: [APUAPC] D11_APC_0: 0xffffffff
10009 12:15:19.534107 INFO: [APUAPC] D11_APC_1: 0xffffffff
10010 12:15:19.537336 INFO: [APUAPC] D11_APC_2: 0x3fffff
10011 12:15:19.540040 INFO: [APUAPC] D11_APC_3: 0x0
10012 12:15:19.543555 INFO: [APUAPC] D12_APC_0: 0xffffffff
10013 12:15:19.546850 INFO: [APUAPC] D12_APC_1: 0xffffffff
10014 12:15:19.550191 INFO: [APUAPC] D12_APC_2: 0x3fffff
10015 12:15:19.553541 INFO: [APUAPC] D12_APC_3: 0x0
10016 12:15:19.556865 INFO: [APUAPC] D13_APC_0: 0xffffffff
10017 12:15:19.560026 INFO: [APUAPC] D13_APC_1: 0xffffffff
10018 12:15:19.563342 INFO: [APUAPC] D13_APC_2: 0x3fffff
10019 12:15:19.566703 INFO: [APUAPC] D13_APC_3: 0x0
10020 12:15:19.570022 INFO: [APUAPC] D14_APC_0: 0xffffffff
10021 12:15:19.573162 INFO: [APUAPC] D14_APC_1: 0xffffffff
10022 12:15:19.577041 INFO: [APUAPC] D14_APC_2: 0x3fffff
10023 12:15:19.580307 INFO: [APUAPC] D14_APC_3: 0x0
10024 12:15:19.583297 INFO: [APUAPC] D15_APC_0: 0xffffffff
10025 12:15:19.586635 INFO: [APUAPC] D15_APC_1: 0xffffffff
10026 12:15:19.590571 INFO: [APUAPC] D15_APC_2: 0x3fffff
10027 12:15:19.593187 INFO: [APUAPC] D15_APC_3: 0x0
10028 12:15:19.596566 INFO: [APUAPC] APC_CON: 0x4
10029 12:15:19.599960 INFO: [NOCDAPC] D0_APC_0: 0x0
10030 12:15:19.603384 INFO: [NOCDAPC] D0_APC_1: 0x0
10031 12:15:19.606838 INFO: [NOCDAPC] D1_APC_0: 0x0
10032 12:15:19.610007 INFO: [NOCDAPC] D1_APC_1: 0xfff
10033 12:15:19.610179 INFO: [NOCDAPC] D2_APC_0: 0x0
10034 12:15:19.613529 INFO: [NOCDAPC] D2_APC_1: 0xfff
10035 12:15:19.616850 INFO: [NOCDAPC] D3_APC_0: 0x0
10036 12:15:19.620231 INFO: [NOCDAPC] D3_APC_1: 0xfff
10037 12:15:19.623695 INFO: [NOCDAPC] D4_APC_0: 0x0
10038 12:15:19.626298 INFO: [NOCDAPC] D4_APC_1: 0xfff
10039 12:15:19.630125 INFO: [NOCDAPC] D5_APC_0: 0x0
10040 12:15:19.633314 INFO: [NOCDAPC] D5_APC_1: 0xfff
10041 12:15:19.636657 INFO: [NOCDAPC] D6_APC_0: 0x0
10042 12:15:19.639986 INFO: [NOCDAPC] D6_APC_1: 0xfff
10043 12:15:19.640141 INFO: [NOCDAPC] D7_APC_0: 0x0
10044 12:15:19.643184 INFO: [NOCDAPC] D7_APC_1: 0xfff
10045 12:15:19.646501 INFO: [NOCDAPC] D8_APC_0: 0x0
10046 12:15:19.649815 INFO: [NOCDAPC] D8_APC_1: 0xfff
10047 12:15:19.653197 INFO: [NOCDAPC] D9_APC_0: 0x0
10048 12:15:19.656834 INFO: [NOCDAPC] D9_APC_1: 0xfff
10049 12:15:19.660343 INFO: [NOCDAPC] D10_APC_0: 0x0
10050 12:15:19.663623 INFO: [NOCDAPC] D10_APC_1: 0xfff
10051 12:15:19.667039 INFO: [NOCDAPC] D11_APC_0: 0x0
10052 12:15:19.670269 INFO: [NOCDAPC] D11_APC_1: 0xfff
10053 12:15:19.673082 INFO: [NOCDAPC] D12_APC_0: 0x0
10054 12:15:19.676550 INFO: [NOCDAPC] D12_APC_1: 0xfff
10055 12:15:19.676715 INFO: [NOCDAPC] D13_APC_0: 0x0
10056 12:15:19.680024 INFO: [NOCDAPC] D13_APC_1: 0xfff
10057 12:15:19.683094 INFO: [NOCDAPC] D14_APC_0: 0x0
10058 12:15:19.686379 INFO: [NOCDAPC] D14_APC_1: 0xfff
10059 12:15:19.689810 INFO: [NOCDAPC] D15_APC_0: 0x0
10060 12:15:19.693129 INFO: [NOCDAPC] D15_APC_1: 0xfff
10061 12:15:19.696566 INFO: [NOCDAPC] APC_CON: 0x4
10062 12:15:19.699893 INFO: [APUAPC] set_apusys_apc done
10063 12:15:19.703574 INFO: [DEVAPC] devapc_init done
10064 12:15:19.706359 INFO: GICv3 without legacy support detected.
10065 12:15:19.709861 INFO: ARM GICv3 driver initialized in EL3
10066 12:15:19.716850 INFO: Maximum SPI INTID supported: 639
10067 12:15:19.719528 INFO: BL31: Initializing runtime services
10068 12:15:19.726644 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10069 12:15:19.726780 INFO: SPM: enable CPC mode
10070 12:15:19.732924 INFO: mcdi ready for mcusys-off-idle and system suspend
10071 12:15:19.736258 INFO: BL31: Preparing for EL3 exit to normal world
10072 12:15:19.739802 INFO: Entry point address = 0x80000000
10073 12:15:19.743098 INFO: SPSR = 0x8
10074 12:15:19.748967
10075 12:15:19.749114
10076 12:15:19.749221
10077 12:15:19.752551 Starting depthcharge on Spherion...
10078 12:15:19.752666
10079 12:15:19.752764 Wipe memory regions:
10080 12:15:19.752855
10081 12:15:19.753822 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10082 12:15:19.754005 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10083 12:15:19.754156 Setting prompt string to ['asurada:']
10084 12:15:19.754312 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10085 12:15:19.755321 [0x00000040000000, 0x00000054600000)
10086 12:15:19.877951
10087 12:15:19.878103 [0x00000054660000, 0x00000080000000)
10088 12:15:20.138092
10089 12:15:20.138272 [0x000000821a7280, 0x000000ffe64000)
10090 12:15:20.883064
10091 12:15:20.883248 [0x00000100000000, 0x00000240000000)
10092 12:15:22.773841
10093 12:15:22.777195 Initializing XHCI USB controller at 0x11200000.
10094 12:15:23.815235
10095 12:15:23.818131 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10096 12:15:23.818555
10097 12:15:23.818888
10098 12:15:23.819199
10099 12:15:23.819980 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10101 12:15:23.921097 asurada: tftpboot 192.168.201.1 10605418/tftp-deploy-2hk8o711/kernel/image.itb 10605418/tftp-deploy-2hk8o711/kernel/cmdline
10102 12:15:23.921726 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10103 12:15:23.922177 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10104 12:15:23.926485 tftpboot 192.168.201.1 10605418/tftp-deploy-2hk8o711/kernel/image.ittp-deploy-2hk8o711/kernel/cmdline
10105 12:15:23.926917
10106 12:15:23.927250 Waiting for link
10107 12:15:24.087201
10108 12:15:24.087753 R8152: Initializing
10109 12:15:24.088093
10110 12:15:24.090650 Version 9 (ocp_data = 6010)
10111 12:15:24.091068
10112 12:15:24.093474 R8152: Done initializing
10113 12:15:24.093895
10114 12:15:24.094226 Adding net device
10115 12:15:25.962801
10116 12:15:25.963316 done.
10117 12:15:25.963705
10118 12:15:25.964028 MAC: 00:e0:4c:78:7a:aa
10119 12:15:25.964334
10120 12:15:25.966358 Sending DHCP discover... done.
10121 12:15:25.966783
10122 12:15:29.103536 Waiting for reply... done.
10123 12:15:29.104135
10124 12:15:29.104629 Sending DHCP request... done.
10125 12:15:29.106771
10126 12:15:29.409285 Waiting for reply... done.
10127 12:15:29.409491
10128 12:15:29.409609 My ip is 192.168.201.12
10129 12:15:29.409698
10130 12:15:29.411979 The DHCP server ip is 192.168.201.1
10131 12:15:29.412100
10132 12:15:29.418937 TFTP server IP predefined by user: 192.168.201.1
10133 12:15:29.419041
10134 12:15:29.425249 Bootfile predefined by user: 10605418/tftp-deploy-2hk8o711/kernel/image.itb
10135 12:15:29.425361
10136 12:15:29.428424 Sending tftp read request... done.
10137 12:15:29.428539
10138 12:15:29.432337 Waiting for the transfer...
10139 12:15:29.432440
10140 12:15:29.678200 00000000 ################################################################
10141 12:15:29.678337
10142 12:15:29.937773 00080000 ################################################################
10143 12:15:29.937930
10144 12:15:30.205716 00100000 ################################################################
10145 12:15:30.205893
10146 12:15:30.462629 00180000 ################################################################
10147 12:15:30.462761
10148 12:15:30.718545 00200000 ################################################################
10149 12:15:30.718738
10150 12:15:30.964685 00280000 ################################################################
10151 12:15:30.964858
10152 12:15:31.209301 00300000 ################################################################
10153 12:15:31.209441
10154 12:15:31.500544 00380000 ################################################################
10155 12:15:31.500750
10156 12:15:31.726700 00400000 ################################################################
10157 12:15:31.726875
10158 12:15:31.977951 00480000 ################################################################
10159 12:15:31.978088
10160 12:15:32.219673 00500000 ################################################################
10161 12:15:32.219836
10162 12:15:32.468201 00580000 ################################################################
10163 12:15:32.468375
10164 12:15:32.712336 00600000 ################################################################
10165 12:15:32.712501
10166 12:15:32.954583 00680000 ################################################################
10167 12:15:32.954745
10168 12:15:33.196267 00700000 ################################################################
10169 12:15:33.196431
10170 12:15:33.437280 00780000 ################################################################
10171 12:15:33.437459
10172 12:15:33.679011 00800000 ################################################################
10173 12:15:33.679177
10174 12:15:33.917422 00880000 ################################################################
10175 12:15:33.917590
10176 12:15:34.163307 00900000 ################################################################
10177 12:15:34.163486
10178 12:15:34.406693 00980000 ################################################################
10179 12:15:34.406859
10180 12:15:34.662235 00a00000 ################################################################
10181 12:15:34.662379
10182 12:15:34.925172 00a80000 ################################################################
10183 12:15:34.925319
10184 12:15:35.181435 00b00000 ################################################################
10185 12:15:35.181600
10186 12:15:35.440904 00b80000 ################################################################
10187 12:15:35.441041
10188 12:15:35.693971 00c00000 ################################################################
10189 12:15:35.694138
10190 12:15:35.949873 00c80000 ################################################################
10191 12:15:35.950005
10192 12:15:36.199537 00d00000 ################################################################
10193 12:15:36.199705
10194 12:15:36.447826 00d80000 ################################################################
10195 12:15:36.447966
10196 12:15:36.710996 00e00000 ################################################################
10197 12:15:36.711144
10198 12:15:36.976616 00e80000 ################################################################
10199 12:15:36.976764
10200 12:15:37.236377 00f00000 ################################################################
10201 12:15:37.236537
10202 12:15:37.486477 00f80000 ################################################################
10203 12:15:37.486632
10204 12:15:37.743027 01000000 ################################################################
10205 12:15:37.743191
10206 12:15:37.995911 01080000 ################################################################
10207 12:15:37.996072
10208 12:15:38.277884 01100000 ################################################################
10209 12:15:38.278053
10210 12:15:38.551606 01180000 ################################################################
10211 12:15:38.551749
10212 12:15:38.800393 01200000 ################################################################
10213 12:15:38.800579
10214 12:15:39.047316 01280000 ################################################################
10215 12:15:39.047484
10216 12:15:39.294211 01300000 ################################################################
10217 12:15:39.294379
10218 12:15:39.542373 01380000 ################################################################
10219 12:15:39.542513
10220 12:15:39.790985 01400000 ################################################################
10221 12:15:39.791152
10222 12:15:40.038828 01480000 ################################################################
10223 12:15:40.038995
10224 12:15:40.292373 01500000 ################################################################
10225 12:15:40.292513
10226 12:15:40.592650 01580000 ################################################################
10227 12:15:40.592834
10228 12:15:40.856316 01600000 ################################################################
10229 12:15:40.856493
10230 12:15:41.114884 01680000 ################################################################
10231 12:15:41.115050
10232 12:15:41.365499 01700000 ################################################################
10233 12:15:41.365632
10234 12:15:41.616805 01780000 ################################################################
10235 12:15:41.616976
10236 12:15:41.870785 01800000 ################################################################
10237 12:15:41.870919
10238 12:15:42.127284 01880000 ################################################################
10239 12:15:42.127432
10240 12:15:42.417794 01900000 ################################################################
10241 12:15:42.417946
10242 12:15:42.667295 01980000 ################################################################
10243 12:15:42.667476
10244 12:15:42.917525 01a00000 ################################################################ done.
10245 12:15:42.921113
10246 12:15:42.924693 The bootfile was 27785110 bytes long.
10247 12:15:42.924798
10248 12:15:42.924866 Sending tftp read request... done.
10249 12:15:42.924936
10250 12:15:42.927967 Waiting for the transfer...
10251 12:15:42.928078
10252 12:15:42.931533 00000000 # done.
10253 12:15:42.931627
10254 12:15:42.937549 Command line loaded dynamically from TFTP file: 10605418/tftp-deploy-2hk8o711/kernel/cmdline
10255 12:15:42.937679
10256 12:15:42.957470 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605418/extract-nfsrootfs-xjdocy5u,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10257 12:15:42.957567
10258 12:15:42.957636 Loading FIT.
10259 12:15:42.957730
10260 12:15:42.961028 Image ramdisk-1 has 17641531 bytes.
10261 12:15:42.961136
10262 12:15:42.964500 Image fdt-1 has 46924 bytes.
10263 12:15:42.964585
10264 12:15:42.967432 Image kernel-1 has 10094623 bytes.
10265 12:15:42.967517
10266 12:15:42.977307 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10267 12:15:42.977424
10268 12:15:42.994297 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10269 12:15:42.994443
10270 12:15:43.000741 Choosing best match conf-1 for compat google,spherion-rev2.
10271 12:15:43.000859
10272 12:15:43.008600 Connected to device vid:did:rid of 1ae0:0028:00
10273 12:15:43.016615
10274 12:15:43.020340 tpm_get_response: command 0x17b, return code 0x0
10275 12:15:43.020455
10276 12:15:43.023209 ec_init: CrosEC protocol v3 supported (256, 248)
10277 12:15:43.028207
10278 12:15:43.031757 tpm_cleanup: add release locality here.
10279 12:15:43.031867
10280 12:15:43.031965 Shutting down all USB controllers.
10281 12:15:43.032058
10282 12:15:43.035163 Removing current net device
10283 12:15:43.035269
10284 12:15:43.042050 Exiting depthcharge with code 4 at timestamp: 52568096
10285 12:15:43.042170
10286 12:15:43.045082 LZMA decompressing kernel-1 to 0x821a6718
10287 12:15:43.045189
10288 12:15:43.048642 LZMA decompressing kernel-1 to 0x40000000
10289 12:15:44.316781
10290 12:15:44.316990 jumping to kernel
10291 12:15:44.317553 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10292 12:15:44.317766 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10293 12:15:44.317875 Setting prompt string to ['Linux version [0-9]']
10294 12:15:44.317978 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10295 12:15:44.318088 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10296 12:15:44.398040
10297 12:15:44.401768 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10298 12:15:44.404821 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10299 12:15:44.404955 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10300 12:15:44.405086 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10301 12:15:44.405206 Using line separator: #'\n'#
10302 12:15:44.405307 No login prompt set.
10303 12:15:44.405415 Parsing kernel messages
10304 12:15:44.405513 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10305 12:15:44.405703 [login-action] Waiting for messages, (timeout 00:04:01)
10306 12:15:44.424748 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
10307 12:15:44.427707 [ 0.000000] random: crng init done
10308 12:15:44.431290 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10309 12:15:44.434880 [ 0.000000] efi: UEFI not found.
10310 12:15:44.444392 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10311 12:15:44.451370 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10312 12:15:44.461385 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10313 12:15:44.470821 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10314 12:15:44.478072 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10315 12:15:44.480881 [ 0.000000] printk: bootconsole [mtk8250] enabled
10316 12:15:44.489737 [ 0.000000] NUMA: No NUMA configuration found
10317 12:15:44.496104 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10318 12:15:44.503338 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10319 12:15:44.503427 [ 0.000000] Zone ranges:
10320 12:15:44.509655 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10321 12:15:44.513313 [ 0.000000] DMA32 empty
10322 12:15:44.519779 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10323 12:15:44.522705 [ 0.000000] Movable zone start for each node
10324 12:15:44.526285 [ 0.000000] Early memory node ranges
10325 12:15:44.532766 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10326 12:15:44.539180 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10327 12:15:44.546347 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10328 12:15:44.552756 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10329 12:15:44.559137 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10330 12:15:44.565576 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10331 12:15:44.622032 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10332 12:15:44.629118 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10333 12:15:44.635657 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10334 12:15:44.638677 [ 0.000000] psci: probing for conduit method from DT.
10335 12:15:44.645733 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10336 12:15:44.648681 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10337 12:15:44.655804 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10338 12:15:44.658604 [ 0.000000] psci: SMC Calling Convention v1.2
10339 12:15:44.665207 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10340 12:15:44.668940 [ 0.000000] Detected VIPT I-cache on CPU0
10341 12:15:44.675108 [ 0.000000] CPU features: detected: GIC system register CPU interface
10342 12:15:44.682310 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10343 12:15:44.688916 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10344 12:15:44.695277 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10345 12:15:44.701685 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10346 12:15:44.708138 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10347 12:15:44.715157 [ 0.000000] alternatives: applying boot alternatives
10348 12:15:44.718536 [ 0.000000] Fallback order for Node 0: 0
10349 12:15:44.728381 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10350 12:15:44.728471 [ 0.000000] Policy zone: Normal
10351 12:15:44.751783 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605418/extract-nfsrootfs-xjdocy5u,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10352 12:15:44.761324 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10353 12:15:44.771380 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10354 12:15:44.781740 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10355 12:15:44.788303 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10356 12:15:44.791263 <6>[ 0.000000] software IO TLB: area num 8.
10357 12:15:44.847914 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10358 12:15:44.997806 <6>[ 0.000000] Memory: 7955716K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397052K reserved, 32768K cma-reserved)
10359 12:15:45.004500 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10360 12:15:45.010937 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10361 12:15:45.014411 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10362 12:15:45.020761 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10363 12:15:45.027644 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10364 12:15:45.031070 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10365 12:15:45.040930 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10366 12:15:45.047714 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10367 12:15:45.054221 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10368 12:15:45.060614 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10369 12:15:45.064215 <6>[ 0.000000] GICv3: 608 SPIs implemented
10370 12:15:45.067111 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10371 12:15:45.073704 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10372 12:15:45.077388 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10373 12:15:45.083978 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10374 12:15:45.097077 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10375 12:15:45.106873 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10376 12:15:45.116990 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10377 12:15:45.124090 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10378 12:15:45.137620 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10379 12:15:45.143941 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10380 12:15:45.150745 <6>[ 0.009177] Console: colour dummy device 80x25
10381 12:15:45.161115 <6>[ 0.013903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10382 12:15:45.164696 <6>[ 0.024410] pid_max: default: 32768 minimum: 301
10383 12:15:45.170713 <6>[ 0.029284] LSM: Security Framework initializing
10384 12:15:45.177811 <6>[ 0.034251] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10385 12:15:45.187212 <6>[ 0.042066] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10386 12:15:45.194419 <6>[ 0.051498] cblist_init_generic: Setting adjustable number of callback queues.
10387 12:15:45.200762 <6>[ 0.058953] cblist_init_generic: Setting shift to 3 and lim to 1.
10388 12:15:45.207297 <6>[ 0.065291] cblist_init_generic: Setting shift to 3 and lim to 1.
10389 12:15:45.213659 <6>[ 0.071698] rcu: Hierarchical SRCU implementation.
10390 12:15:45.217153 <6>[ 0.076712] rcu: Max phase no-delay instances is 1000.
10391 12:15:45.225179 <6>[ 0.083727] EFI services will not be available.
10392 12:15:45.228902 <6>[ 0.088704] smp: Bringing up secondary CPUs ...
10393 12:15:45.237331 <6>[ 0.093756] Detected VIPT I-cache on CPU1
10394 12:15:45.244148 <6>[ 0.093829] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10395 12:15:45.250591 <6>[ 0.093860] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10396 12:15:45.254178 <6>[ 0.094192] Detected VIPT I-cache on CPU2
10397 12:15:45.261281 <6>[ 0.094242] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10398 12:15:45.267241 <6>[ 0.094257] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10399 12:15:45.274399 <6>[ 0.094511] Detected VIPT I-cache on CPU3
10400 12:15:45.280816 <6>[ 0.094553] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10401 12:15:45.287234 <6>[ 0.094567] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10402 12:15:45.290786 <6>[ 0.094856] CPU features: detected: Spectre-v4
10403 12:15:45.297432 <6>[ 0.094861] CPU features: detected: Spectre-BHB
10404 12:15:45.300291 <6>[ 0.094868] Detected PIPT I-cache on CPU4
10405 12:15:45.307002 <6>[ 0.094923] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10406 12:15:45.313790 <6>[ 0.094940] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10407 12:15:45.320788 <6>[ 0.095242] Detected PIPT I-cache on CPU5
10408 12:15:45.326841 <6>[ 0.095307] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10409 12:15:45.333540 <6>[ 0.095323] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10410 12:15:45.337174 <6>[ 0.095609] Detected PIPT I-cache on CPU6
10411 12:15:45.343805 <6>[ 0.095674] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10412 12:15:45.350145 <6>[ 0.095690] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10413 12:15:45.357146 <6>[ 0.095991] Detected PIPT I-cache on CPU7
10414 12:15:45.363620 <6>[ 0.096056] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10415 12:15:45.369929 <6>[ 0.096072] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10416 12:15:45.373427 <6>[ 0.096119] smp: Brought up 1 node, 8 CPUs
10417 12:15:45.380354 <6>[ 0.237500] SMP: Total of 8 processors activated.
10418 12:15:45.383203 <6>[ 0.242421] CPU features: detected: 32-bit EL0 Support
10419 12:15:45.393394 <6>[ 0.247785] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10420 12:15:45.399786 <6>[ 0.256584] CPU features: detected: Common not Private translations
10421 12:15:45.406865 <6>[ 0.263100] CPU features: detected: CRC32 instructions
10422 12:15:45.409775 <6>[ 0.268485] CPU features: detected: RCpc load-acquire (LDAPR)
10423 12:15:45.416283 <6>[ 0.274445] CPU features: detected: LSE atomic instructions
10424 12:15:45.423446 <6>[ 0.280226] CPU features: detected: Privileged Access Never
10425 12:15:45.426449 <6>[ 0.286006] CPU features: detected: RAS Extension Support
10426 12:15:45.436400 <6>[ 0.291615] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10427 12:15:45.440031 <6>[ 0.298836] CPU: All CPU(s) started at EL2
10428 12:15:45.446256 <6>[ 0.303152] alternatives: applying system-wide alternatives
10429 12:15:45.455667 <6>[ 0.313898] devtmpfs: initialized
10430 12:15:45.470859 <6>[ 0.323033] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10431 12:15:45.477745 <6>[ 0.332995] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10432 12:15:45.484723 <6>[ 0.341215] pinctrl core: initialized pinctrl subsystem
10433 12:15:45.487614 <6>[ 0.347894] DMI not present or invalid.
10434 12:15:45.494482 <6>[ 0.352308] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10435 12:15:45.504582 <6>[ 0.359195] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10436 12:15:45.510549 <6>[ 0.366781] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10437 12:15:45.520643 <6>[ 0.375010] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10438 12:15:45.524300 <6>[ 0.383251] audit: initializing netlink subsys (disabled)
10439 12:15:45.534323 <5>[ 0.388950] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10440 12:15:45.540709 <6>[ 0.389669] thermal_sys: Registered thermal governor 'step_wise'
10441 12:15:45.547156 <6>[ 0.396916] thermal_sys: Registered thermal governor 'power_allocator'
10442 12:15:45.550830 <6>[ 0.403174] cpuidle: using governor menu
10443 12:15:45.557338 <6>[ 0.414137] NET: Registered PF_QIPCRTR protocol family
10444 12:15:45.564213 <6>[ 0.419657] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10445 12:15:45.566957 <6>[ 0.426762] ASID allocator initialised with 32768 entries
10446 12:15:45.574797 <6>[ 0.433356] Serial: AMBA PL011 UART driver
10447 12:15:45.583747 <4>[ 0.442059] Trying to register duplicate clock ID: 134
10448 12:15:45.637593 <6>[ 0.499270] KASLR enabled
10449 12:15:45.652162 <6>[ 0.507054] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10450 12:15:45.658677 <6>[ 0.514068] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10451 12:15:45.665301 <6>[ 0.520558] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10452 12:15:45.671585 <6>[ 0.527564] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10453 12:15:45.678644 <6>[ 0.534054] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10454 12:15:45.684937 <6>[ 0.541060] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10455 12:15:45.691463 <6>[ 0.547547] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10456 12:15:45.698639 <6>[ 0.554553] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10457 12:15:45.701420 <6>[ 0.562084] ACPI: Interpreter disabled.
10458 12:15:45.709943 <6>[ 0.568474] iommu: Default domain type: Translated
10459 12:15:45.716545 <6>[ 0.573587] iommu: DMA domain TLB invalidation policy: strict mode
10460 12:15:45.719567 <5>[ 0.580244] SCSI subsystem initialized
10461 12:15:45.726164 <6>[ 0.584412] usbcore: registered new interface driver usbfs
10462 12:15:45.733315 <6>[ 0.590147] usbcore: registered new interface driver hub
10463 12:15:45.736315 <6>[ 0.595698] usbcore: registered new device driver usb
10464 12:15:45.743708 <6>[ 0.601775] pps_core: LinuxPPS API ver. 1 registered
10465 12:15:45.753528 <6>[ 0.606970] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10466 12:15:45.756919 <6>[ 0.616320] PTP clock support registered
10467 12:15:45.759640 <6>[ 0.620560] EDAC MC: Ver: 3.0.0
10468 12:15:45.767345 <6>[ 0.625706] FPGA manager framework
10469 12:15:45.773898 <6>[ 0.629386] Advanced Linux Sound Architecture Driver Initialized.
10470 12:15:45.776823 <6>[ 0.636165] vgaarb: loaded
10471 12:15:45.783814 <6>[ 0.639348] clocksource: Switched to clocksource arch_sys_counter
10472 12:15:45.786676 <5>[ 0.645786] VFS: Disk quotas dquot_6.6.0
10473 12:15:45.793609 <6>[ 0.649972] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10474 12:15:45.796541 <6>[ 0.657158] pnp: PnP ACPI: disabled
10475 12:15:45.805056 <6>[ 0.663906] NET: Registered PF_INET protocol family
10476 12:15:45.815155 <6>[ 0.669500] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10477 12:15:45.827015 <6>[ 0.681805] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10478 12:15:45.836394 <6>[ 0.690618] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10479 12:15:45.842881 <6>[ 0.698588] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10480 12:15:45.849560 <6>[ 0.707284] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10481 12:15:45.861640 <6>[ 0.717028] TCP: Hash tables configured (established 65536 bind 65536)
10482 12:15:45.868452 <6>[ 0.723881] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10483 12:15:45.875212 <6>[ 0.731077] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10484 12:15:45.881715 <6>[ 0.738766] NET: Registered PF_UNIX/PF_LOCAL protocol family
10485 12:15:45.888720 <6>[ 0.744917] RPC: Registered named UNIX socket transport module.
10486 12:15:45.892010 <6>[ 0.751069] RPC: Registered udp transport module.
10487 12:15:45.898269 <6>[ 0.756002] RPC: Registered tcp transport module.
10488 12:15:45.904999 <6>[ 0.760932] RPC: Registered tcp NFSv4.1 backchannel transport module.
10489 12:15:45.908587 <6>[ 0.767598] PCI: CLS 0 bytes, default 64
10490 12:15:45.911558 <6>[ 0.771952] Unpacking initramfs...
10491 12:15:45.928624 <6>[ 0.783922] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10492 12:15:45.938945 <6>[ 0.792582] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10493 12:15:45.941866 <6>[ 0.801424] kvm [1]: IPA Size Limit: 40 bits
10494 12:15:45.948326 <6>[ 0.805954] kvm [1]: GICv3: no GICV resource entry
10495 12:15:45.951995 <6>[ 0.810976] kvm [1]: disabling GICv2 emulation
10496 12:15:45.958664 <6>[ 0.815665] kvm [1]: GIC system register CPU interface enabled
10497 12:15:45.961698 <6>[ 0.821830] kvm [1]: vgic interrupt IRQ18
10498 12:15:45.968969 <6>[ 0.827445] kvm [1]: VHE mode initialized successfully
10499 12:15:45.975238 <5>[ 0.833876] Initialise system trusted keyrings
10500 12:15:45.981964 <6>[ 0.838682] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10501 12:15:45.989963 <6>[ 0.848672] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10502 12:15:45.997026 <5>[ 0.855060] NFS: Registering the id_resolver key type
10503 12:15:45.999892 <5>[ 0.860363] Key type id_resolver registered
10504 12:15:46.006881 <5>[ 0.864777] Key type id_legacy registered
10505 12:15:46.013785 <6>[ 0.869057] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10506 12:15:46.020331 <6>[ 0.875982] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10507 12:15:46.026775 <6>[ 0.883718] 9p: Installing v9fs 9p2000 file system support
10508 12:15:46.062982 <5>[ 0.921327] Key type asymmetric registered
10509 12:15:46.065859 <5>[ 0.925659] Asymmetric key parser 'x509' registered
10510 12:15:46.075882 <6>[ 0.930818] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10511 12:15:46.079541 <6>[ 0.938431] io scheduler mq-deadline registered
10512 12:15:46.082321 <6>[ 0.943206] io scheduler kyber registered
10513 12:15:46.101803 <6>[ 0.960052] EINJ: ACPI disabled.
10514 12:15:46.133880 <4>[ 0.985749] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10515 12:15:46.143619 <4>[ 0.996403] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10516 12:15:46.158737 <6>[ 1.017009] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10517 12:15:46.166633 <6>[ 1.025093] printk: console [ttyS0] disabled
10518 12:15:46.194674 <6>[ 1.049764] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10519 12:15:46.201201 <6>[ 1.059236] printk: console [ttyS0] enabled
10520 12:15:46.204030 <6>[ 1.059236] printk: console [ttyS0] enabled
10521 12:15:46.211155 <6>[ 1.068131] printk: bootconsole [mtk8250] disabled
10522 12:15:46.213932 <6>[ 1.068131] printk: bootconsole [mtk8250] disabled
10523 12:15:46.220901 <6>[ 1.079460] SuperH (H)SCI(F) driver initialized
10524 12:15:46.224409 <6>[ 1.084737] msm_serial: driver initialized
10525 12:15:46.238690 <6>[ 1.093638] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10526 12:15:46.248689 <6>[ 1.102186] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10527 12:15:46.255209 <6>[ 1.110729] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10528 12:15:46.264686 <6>[ 1.119361] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10529 12:15:46.274641 <6>[ 1.128070] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10530 12:15:46.281177 <6>[ 1.136797] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10531 12:15:46.291503 <6>[ 1.145340] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10532 12:15:46.297879 <6>[ 1.154152] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10533 12:15:46.308004 <6>[ 1.162696] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10534 12:15:46.319701 <6>[ 1.178295] loop: module loaded
10535 12:15:46.326475 <6>[ 1.184252] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10536 12:15:46.348874 <4>[ 1.207596] mtk-pmic-keys: Failed to locate of_node [id: -1]
10537 12:15:46.355954 <6>[ 1.214485] megasas: 07.719.03.00-rc1
10538 12:15:46.365349 <6>[ 1.224066] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10539 12:15:46.372723 <6>[ 1.230743] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10540 12:15:46.389513 <6>[ 1.247564] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10541 12:15:46.446526 <6>[ 1.298310] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10542 12:15:46.641035 <6>[ 1.499765] Freeing initrd memory: 17224K
10543 12:15:46.651818 <6>[ 1.510236] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10544 12:15:46.662946 <6>[ 1.521120] tun: Universal TUN/TAP device driver, 1.6
10545 12:15:46.665746 <6>[ 1.527162] thunder_xcv, ver 1.0
10546 12:15:46.669425 <6>[ 1.530666] thunder_bgx, ver 1.0
10547 12:15:46.672288 <6>[ 1.534164] nicpf, ver 1.0
10548 12:15:46.682660 <6>[ 1.538165] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10549 12:15:46.686153 <6>[ 1.545641] hns3: Copyright (c) 2017 Huawei Corporation.
10550 12:15:46.689754 <6>[ 1.551228] hclge is initializing
10551 12:15:46.696226 <6>[ 1.554807] e1000: Intel(R) PRO/1000 Network Driver
10552 12:15:46.702856 <6>[ 1.559937] e1000: Copyright (c) 1999-2006 Intel Corporation.
10553 12:15:46.706400 <6>[ 1.565952] e1000e: Intel(R) PRO/1000 Network Driver
10554 12:15:46.713019 <6>[ 1.571168] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10555 12:15:46.719581 <6>[ 1.577354] igb: Intel(R) Gigabit Ethernet Network Driver
10556 12:15:46.726655 <6>[ 1.583003] igb: Copyright (c) 2007-2014 Intel Corporation.
10557 12:15:46.732806 <6>[ 1.588839] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10558 12:15:46.736275 <6>[ 1.595356] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10559 12:15:46.743280 <6>[ 1.601816] sky2: driver version 1.30
10560 12:15:46.749974 <6>[ 1.606782] VFIO - User Level meta-driver version: 0.3
10561 12:15:46.756501 <6>[ 1.614994] usbcore: registered new interface driver usb-storage
10562 12:15:46.763030 <6>[ 1.621445] usbcore: registered new device driver onboard-usb-hub
10563 12:15:46.772016 <6>[ 1.630542] mt6397-rtc mt6359-rtc: registered as rtc0
10564 12:15:46.782050 <6>[ 1.636010] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:15:40 UTC (1686053740)
10565 12:15:46.784928 <6>[ 1.645563] i2c_dev: i2c /dev entries driver
10566 12:15:46.802155 <6>[ 1.657197] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10567 12:15:46.808568 <6>[ 1.667399] sdhci: Secure Digital Host Controller Interface driver
10568 12:15:46.815769 <6>[ 1.673835] sdhci: Copyright(c) Pierre Ossman
10569 12:15:46.822326 <6>[ 1.679227] Synopsys Designware Multimedia Card Interface Driver
10570 12:15:46.825250 <6>[ 1.685807] mmc0: CQHCI version 5.10
10571 12:15:46.832363 <6>[ 1.686377] sdhci-pltfm: SDHCI platform and OF driver helper
10572 12:15:46.838843 <6>[ 1.697640] ledtrig-cpu: registered to indicate activity on CPUs
10573 12:15:46.849679 <6>[ 1.704979] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10574 12:15:46.853216 <6>[ 1.712364] usbcore: registered new interface driver usbhid
10575 12:15:46.859863 <6>[ 1.718196] usbhid: USB HID core driver
10576 12:15:46.866215 <6>[ 1.722443] spi_master spi0: will run message pump with realtime priority
10577 12:15:46.912653 <6>[ 1.764528] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10578 12:15:46.928793 <6>[ 1.780617] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10579 12:15:46.935879 <6>[ 1.794205] mmc0: Command Queue Engine enabled
10580 12:15:46.943090 <6>[ 1.797140] cros-ec-spi spi0.0: Chrome EC device registered
10581 12:15:46.946680 <6>[ 1.798940] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10582 12:15:46.953100 <6>[ 1.812050] mmcblk0: mmc0:0001 DA4128 116 GiB
10583 12:15:46.967049 <6>[ 1.822451] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10584 12:15:46.973739 <6>[ 1.824889] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10585 12:15:46.980742 <6>[ 1.833899] NET: Registered PF_PACKET protocol family
10586 12:15:46.983974 <6>[ 1.839027] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10587 12:15:46.990478 <6>[ 1.843104] 9pnet: Installing 9P2000 support
10588 12:15:46.993419 <6>[ 1.848881] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10589 12:15:47.000761 <5>[ 1.852783] Key type dns_resolver registered
10590 12:15:47.003723 <6>[ 1.858598] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10591 12:15:47.010887 <6>[ 1.862990] registered taskstats version 1
10592 12:15:47.013793 <5>[ 1.873429] Loading compiled-in X.509 certificates
10593 12:15:47.051210 <4>[ 1.903385] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 12:15:47.061385 <4>[ 1.914058] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 12:15:47.071573 <3>[ 1.926710] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10596 12:15:47.083891 <6>[ 1.942276] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10597 12:15:47.090667 <6>[ 1.949102] xhci-mtk 11200000.usb: xHCI Host Controller
10598 12:15:47.097407 <6>[ 1.954631] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10599 12:15:47.107604 <6>[ 1.962585] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10600 12:15:47.114185 <6>[ 1.972023] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10601 12:15:47.120797 <6>[ 1.978108] xhci-mtk 11200000.usb: xHCI Host Controller
10602 12:15:47.127436 <6>[ 1.983593] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10603 12:15:47.134008 <6>[ 1.991245] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10604 12:15:47.140559 <6>[ 1.999138] hub 1-0:1.0: USB hub found
10605 12:15:47.144060 <6>[ 2.003193] hub 1-0:1.0: 1 port detected
10606 12:15:47.150733 <6>[ 2.007567] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10607 12:15:47.157995 <6>[ 2.016403] hub 2-0:1.0: USB hub found
10608 12:15:47.160869 <6>[ 2.020460] hub 2-0:1.0: 1 port detected
10609 12:15:47.169230 <6>[ 2.027699] mtk-msdc 11f70000.mmc: Got CD GPIO
10610 12:15:47.186847 <6>[ 2.042176] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10611 12:15:47.193453 <6>[ 2.050241] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10612 12:15:47.204187 <4>[ 2.058217] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10613 12:15:47.213679 <6>[ 2.067886] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10614 12:15:47.220811 <6>[ 2.075970] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10615 12:15:47.227330 <6>[ 2.084002] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10616 12:15:47.236936 <6>[ 2.091926] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10617 12:15:47.243974 <6>[ 2.099747] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10618 12:15:47.254143 <6>[ 2.107569] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10619 12:15:47.263560 <6>[ 2.118202] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10620 12:15:47.270867 <6>[ 2.126595] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10621 12:15:47.281327 <6>[ 2.134948] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10622 12:15:47.287414 <6>[ 2.143295] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10623 12:15:47.297655 <6>[ 2.151640] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10624 12:15:47.303593 <6>[ 2.159984] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10625 12:15:47.314063 <6>[ 2.168328] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10626 12:15:47.320323 <6>[ 2.176674] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10627 12:15:47.330408 <6>[ 2.185018] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10628 12:15:47.336925 <6>[ 2.193362] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10629 12:15:47.346968 <6>[ 2.201706] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10630 12:15:47.353581 <6>[ 2.210050] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10631 12:15:47.363556 <6>[ 2.218409] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10632 12:15:47.370214 <6>[ 2.226753] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10633 12:15:47.380258 <6>[ 2.235100] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10634 12:15:47.387290 <6>[ 2.244001] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10635 12:15:47.393949 <6>[ 2.251470] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10636 12:15:47.400587 <6>[ 2.258538] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10637 12:15:47.407178 <6>[ 2.265655] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10638 12:15:47.417425 <6>[ 2.272951] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10639 12:15:47.424194 <6>[ 2.279878] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10640 12:15:47.434126 <6>[ 2.289020] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10641 12:15:47.443962 <6>[ 2.298148] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10642 12:15:47.453982 <6>[ 2.307452] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10643 12:15:47.464130 <6>[ 2.316928] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10644 12:15:47.470806 <6>[ 2.326403] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10645 12:15:47.480928 <6>[ 2.335530] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10646 12:15:47.490701 <6>[ 2.345005] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10647 12:15:47.500611 <6>[ 2.354132] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10648 12:15:47.510751 <6>[ 2.363433] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10649 12:15:47.520014 <6>[ 2.373600] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10650 12:15:47.530182 <6>[ 2.385591] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10651 12:15:47.537185 <6>[ 2.395559] Trying to probe devices needed for running init ...
10652 12:15:47.576072 <6>[ 2.431624] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10653 12:15:47.728245 <6>[ 2.586996] hub 1-1:1.0: USB hub found
10654 12:15:47.731851 <6>[ 2.591296] hub 1-1:1.0: 4 ports detected
10655 12:15:47.856139 <6>[ 2.711833] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10656 12:15:47.881134 <6>[ 2.739876] hub 2-1:1.0: USB hub found
10657 12:15:47.884634 <6>[ 2.744311] hub 2-1:1.0: 3 ports detected
10658 12:15:48.052176 <6>[ 2.907672] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10659 12:15:48.185082 <6>[ 3.043596] hub 1-1.4:1.0: USB hub found
10660 12:15:48.188304 <6>[ 3.048244] hub 1-1.4:1.0: 2 ports detected
10661 12:15:48.264086 <6>[ 3.119879] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10662 12:15:48.484167 <6>[ 3.339621] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10663 12:15:48.675938 <6>[ 3.531622] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10664 12:15:59.836651 <6>[ 14.700176] ALSA device list:
10665 12:15:59.843475 <6>[ 14.703434] No soundcards found.
10666 12:15:59.855519 <6>[ 14.715870] Freeing unused kernel memory: 8384K
10667 12:15:59.858933 <6>[ 14.720783] Run /init as init process
10668 12:15:59.870006 Loading, please wait...
10669 12:15:59.889028 Starting version 247.3-7+deb11u2
10670 12:16:00.210910 <6>[ 15.067603] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10671 12:16:00.226328 <6>[ 15.086347] remoteproc remoteproc0: scp is available
10672 12:16:00.236271 <4>[ 15.091923] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10673 12:16:00.242949 <6>[ 15.101819] remoteproc remoteproc0: powering up scp
10674 12:16:00.252731 <4>[ 15.107000] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10675 12:16:00.259233 <3>[ 15.116847] remoteproc remoteproc0: request_firmware failed: -2
10676 12:16:00.266300 <6>[ 15.125185] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10677 12:16:00.275989 <3>[ 15.127249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 12:16:00.282611 <3>[ 15.141058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 12:16:00.292585 <4>[ 15.144569] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10680 12:16:00.299466 <3>[ 15.149166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 12:16:00.311758 <6>[ 15.168197] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10682 12:16:00.317604 <4>[ 15.173704] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10683 12:16:00.324736 <4>[ 15.173704] Fallback method does not support PEC.
10684 12:16:00.334220 <6>[ 15.175836] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10685 12:16:00.341294 <4>[ 15.175984] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10686 12:16:00.348007 <3>[ 15.179264] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 12:16:00.355010 <3>[ 15.179290] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 12:16:00.365129 <3>[ 15.179299] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 12:16:00.372278 <3>[ 15.179317] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 12:16:00.382085 <3>[ 15.179325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 12:16:00.385606 <6>[ 15.184865] usbcore: registered new interface driver r8152
10692 12:16:00.395264 <3>[ 15.185258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 12:16:00.401587 <3>[ 15.185348] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 12:16:00.411530 <3>[ 15.185357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 12:16:00.418665 <3>[ 15.185365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 12:16:00.428604 <3>[ 15.185446] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 12:16:00.435063 <3>[ 15.185455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 12:16:00.441561 <3>[ 15.185462] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 12:16:00.451697 <3>[ 15.185471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 12:16:00.458466 <3>[ 15.185479] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 12:16:00.468201 <3>[ 15.185517] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 12:16:00.471665 <6>[ 15.200125] mc: Linux media interface: v0.10
10703 12:16:00.482474 <6>[ 15.205445] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10704 12:16:00.488930 <3>[ 15.228881] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10705 12:16:00.495246 <6>[ 15.287917] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10706 12:16:00.505383 <6>[ 15.299429] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10707 12:16:00.512252 <6>[ 15.324835] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10708 12:16:00.522028 <4>[ 15.336180] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10709 12:16:00.528482 <6>[ 15.337247] pci_bus 0000:00: root bus resource [bus 00-ff]
10710 12:16:00.538466 <6>[ 15.339906] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10711 12:16:00.548096 <6>[ 15.340246] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10712 12:16:00.555102 <4>[ 15.345923] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10713 12:16:00.564885 <3>[ 15.347872] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10714 12:16:00.571680 <6>[ 15.354751] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10715 12:16:00.578282 <6>[ 15.355549] videodev: Linux video capture interface: v2.00
10716 12:16:00.581860 <6>[ 15.371562] usbcore: registered new interface driver cdc_ether
10717 12:16:00.591162 <6>[ 15.377886] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10718 12:16:00.598025 <6>[ 15.378099] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10719 12:16:00.601448 <6>[ 15.393876] Bluetooth: Core ver 2.22
10720 12:16:00.608310 <6>[ 15.393981] usbcore: registered new interface driver r8153_ecm
10721 12:16:00.614440 <6>[ 15.402971] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10722 12:16:00.621556 <6>[ 15.412071] NET: Registered PF_BLUETOOTH protocol family
10723 12:16:00.624262 <6>[ 15.415501] r8152 2-1.3:1.0 eth0: v1.12.13
10724 12:16:00.631243 <6>[ 15.420162] pci 0000:00:00.0: supports D1 D2
10725 12:16:00.637566 <6>[ 15.421628] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10726 12:16:00.651316 <6>[ 15.423154] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10727 12:16:00.657753 <6>[ 15.423351] usbcore: registered new interface driver uvcvideo
10728 12:16:00.660816 <6>[ 15.424186] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10729 12:16:00.667497 <6>[ 15.428867] Bluetooth: HCI device and connection manager initialized
10730 12:16:00.674550 <6>[ 15.428889] Bluetooth: HCI socket layer initialized
10731 12:16:00.680870 <6>[ 15.435998] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10732 12:16:00.687503 <6>[ 15.441736] Bluetooth: L2CAP socket layer initialized
10733 12:16:00.693969 <6>[ 15.449797] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10734 12:16:00.700494 <6>[ 15.450028] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10735 12:16:00.707106 <6>[ 15.457729] Bluetooth: SCO socket layer initialized
10736 12:16:00.710598 <6>[ 15.487751] usbcore: registered new interface driver btusb
10737 12:16:00.717514 <6>[ 15.491499] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10738 12:16:00.727482 <4>[ 15.496330] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10739 12:16:00.737339 <6>[ 15.502950] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10740 12:16:00.740845 <3>[ 15.515359] Bluetooth: hci0: Failed to load firmware file (-2)
10741 12:16:00.750293 <6>[ 15.521367] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10742 12:16:00.753955 <3>[ 15.527458] Bluetooth: hci0: Failed to set up firmware (-2)
10743 12:16:00.764081 <6>[ 15.534070] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10744 12:16:00.766963 <6>[ 15.534188] pci 0000:01:00.0: supports D1 D2
10745 12:16:00.777363 <4>[ 15.539251] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10746 12:16:00.783709 <6>[ 15.546100] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10747 12:16:00.802676 <6>[ 15.659393] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10748 12:16:00.809087 <6>[ 15.666291] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10749 12:16:00.815834 <6>[ 15.674379] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10750 12:16:00.825806 <6>[ 15.682388] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10751 12:16:00.832487 <6>[ 15.690396] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10752 12:16:00.842119 <6>[ 15.698406] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10753 12:16:00.845614 <6>[ 15.706411] pci 0000:00:00.0: PCI bridge to [bus 01]
10754 12:16:00.855348 <6>[ 15.711632] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10755 12:16:00.861846 <6>[ 15.719772] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10756 12:16:00.868407 <6>[ 15.726969] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10757 12:16:00.874888 <6>[ 15.733730] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10758 12:16:00.893676 <5>[ 15.750416] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10759 12:16:00.912818 <5>[ 15.769969] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10760 12:16:00.919958 <4>[ 15.776867] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10761 12:16:00.926429 <6>[ 15.785750] cfg80211: failed to load regulatory.db
10762 12:16:00.971099 <6>[ 15.828341] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10763 12:16:00.977812 <6>[ 15.835934] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10764 12:16:01.002439 <6>[ 15.862755] mt7921e 0000:01:00.0: ASIC revision: 79610010
10765 12:16:01.109431 <4>[ 15.962725] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10766 12:16:01.122864 Begin: Loading essential drivers ... done.
10767 12:16:01.126496 Begin: Running /scripts/init-premount ... done.
10768 12:16:01.133230 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10769 12:16:01.142592 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10770 12:16:01.146120 Device /sys/class/net/enx00e04c787aaa found
10771 12:16:01.146235 done.
10772 12:16:01.228470 <4>[ 16.082074] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 12:16:01.234938 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10774 12:16:01.347473 <4>[ 16.201290] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 12:16:01.463866 <4>[ 16.317171] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 12:16:01.579294 <4>[ 16.433058] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 12:16:01.695143 <4>[ 16.549033] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 12:16:01.811458 <4>[ 16.664964] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 12:16:01.927010 <4>[ 16.780862] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 12:16:02.043403 <4>[ 16.896844] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 12:16:02.159356 <4>[ 17.012793] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 12:16:02.199653 <6>[ 17.059900] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10783 12:16:02.266621 <3>[ 17.126738] mt7921e 0000:01:00.0: hardware init failed
10784 12:16:02.276056 IP-Config: no response after 2 secs - giving up
10785 12:16:02.310460 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10786 12:16:02.314154 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10787 12:16:02.323694 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10788 12:16:02.330371 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10789 12:16:02.336867 host : mt8192-asurada-spherion-r0-cbg-0
10790 12:16:02.343557 domain : lava-rack
10791 12:16:02.347061 rootserver: 192.168.201.1 rootpath:
10792 12:16:02.347184 filename :
10793 12:16:02.377065 done.
10794 12:16:02.383629 Begin: Running /scripts/nfs-bottom ... done.
10795 12:16:02.400713 Begin: Running /scripts/init-bottom ... done.
10796 12:16:03.515537 <6>[ 18.376294] NET: Registered PF_INET6 protocol family
10797 12:16:03.522545 <6>[ 18.383036] Segment Routing with IPv6
10798 12:16:03.525445 <6>[ 18.387003] In-situ OAM (IOAM) with IPv6
10799 12:16:03.626685 <30>[ 18.467451] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10800 12:16:03.629665 <30>[ 18.491224] systemd[1]: Detected architecture arm64.
10801 12:16:03.646953
10802 12:16:03.650551 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10803 12:16:03.650679
10804 12:16:03.665010 <30>[ 18.525310] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10805 12:16:04.130314 <30>[ 18.987577] systemd[1]: Queued start job for default target Graphical Interface.
10806 12:16:04.144016 <30>[ 19.004629] systemd[1]: Created slice system-getty.slice.
10807 12:16:04.150544 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10808 12:16:04.167743 <30>[ 19.028279] systemd[1]: Created slice system-modprobe.slice.
10809 12:16:04.174213 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10810 12:16:04.191610 <30>[ 19.052196] systemd[1]: Created slice system-serial\x2dgetty.slice.
10811 12:16:04.201680 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10812 12:16:04.216163 <30>[ 19.076596] systemd[1]: Created slice User and Session Slice.
10813 12:16:04.222707 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10814 12:16:04.242850 <30>[ 19.100171] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10815 12:16:04.249553 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10816 12:16:04.271117 <30>[ 19.128158] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10817 12:16:04.277693 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10818 12:16:04.297703 <30>[ 19.151744] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10819 12:16:04.304551 <30>[ 19.163778] systemd[1]: Reached target Local Encrypted Volumes.
10820 12:16:04.310751 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10821 12:16:04.327550 <30>[ 19.187987] systemd[1]: Reached target Paths.
10822 12:16:04.330360 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10823 12:16:04.347224 <30>[ 19.207609] systemd[1]: Reached target Remote File Systems.
10824 12:16:04.353794 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10825 12:16:04.366780 <30>[ 19.227646] systemd[1]: Reached target Slices.
10826 12:16:04.370197 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10827 12:16:04.386822 <30>[ 19.247668] systemd[1]: Reached target Swap.
10828 12:16:04.390401 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10829 12:16:04.410436 <30>[ 19.267923] systemd[1]: Listening on initctl Compatibility Named Pipe.
10830 12:16:04.417125 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10831 12:16:04.423972 <30>[ 19.283098] systemd[1]: Listening on Journal Audit Socket.
10832 12:16:04.430410 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10833 12:16:04.444249 <30>[ 19.304370] systemd[1]: Listening on Journal Socket (/dev/log).
10834 12:16:04.450611 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10835 12:16:04.467448 <30>[ 19.327919] systemd[1]: Listening on Journal Socket.
10836 12:16:04.473989 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10837 12:16:04.488259 <30>[ 19.348523] systemd[1]: Listening on Network Service Netlink Socket.
10838 12:16:04.498290 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10839 12:16:04.513391 <30>[ 19.374241] systemd[1]: Listening on udev Control Socket.
10840 12:16:04.520378 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10841 12:16:04.535023 <30>[ 19.395887] systemd[1]: Listening on udev Kernel Socket.
10842 12:16:04.541913 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10843 12:16:04.591315 <30>[ 19.451936] systemd[1]: Mounting Huge Pages File System...
10844 12:16:04.597752 Mounting [0;1;39mHuge Pages File System[0m...
10845 12:16:04.613368 <30>[ 19.474059] systemd[1]: Mounting POSIX Message Queue File System...
10846 12:16:04.620021 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10847 12:16:04.637400 <30>[ 19.498119] systemd[1]: Mounting Kernel Debug File System...
10848 12:16:04.643816 Mounting [0;1;39mKernel Debug File System[0m...
10849 12:16:04.662425 <30>[ 19.519945] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10850 12:16:04.680281 <30>[ 19.537799] systemd[1]: Starting Create list of static device nodes for the current kernel...
10851 12:16:04.687308 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10852 12:16:04.705671 <30>[ 19.566432] systemd[1]: Starting Load Kernel Module configfs...
10853 12:16:04.712227 Starting [0;1;39mLoad Kernel Module configfs[0m...
10854 12:16:04.729945 <30>[ 19.590334] systemd[1]: Starting Load Kernel Module drm...
10855 12:16:04.736313 Starting [0;1;39mLoad Kernel Module drm[0m...
10856 12:16:04.753512 <30>[ 19.614363] systemd[1]: Starting Load Kernel Module fuse...
10857 12:16:04.760284 Starting [0;1;39mLoad Kernel Module fuse[0m...
10858 12:16:04.785253 <6>[ 19.646213] fuse: init (API version 7.37)
10859 12:16:04.795596 <30>[ 19.646613] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10860 12:16:04.803848 <30>[ 19.664756] systemd[1]: Starting Journal Service...
10861 12:16:04.807356 Starting [0;1;39mJournal Service[0m...
10862 12:16:04.851554 <30>[ 19.712059] systemd[1]: Starting Load Kernel Modules...
10863 12:16:04.857753 Starting [0;1;39mLoad Kernel Modules[0m...
10864 12:16:04.877454 <30>[ 19.734921] systemd[1]: Starting Remount Root and Kernel File Systems...
10865 12:16:04.884290 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10866 12:16:04.902040 <30>[ 19.763025] systemd[1]: Starting Coldplug All udev Devices...
10867 12:16:04.908952 Starting [0;1;39mColdplug All udev Devices[0m...
10868 12:16:04.925782 <30>[ 19.786810] systemd[1]: Mounted Huge Pages File System.
10869 12:16:04.932404 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10870 12:16:04.952255 <30>[ 19.812086] systemd[1]: Mounted POSIX Message Queue File System.
10871 12:16:04.961991 <3>[ 19.812875] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 12:16:04.968523 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10873 12:16:04.983615 <30>[ 19.844042] systemd[1]: Mounted Kernel Debug File System.
10874 12:16:04.993706 [[0;32m OK [<3>[ 19.851179] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 12:16:05.000066 0m] Mounted [0;1;39mKernel Debug File System[0m.
10876 12:16:05.018866 <30>[ 19.876592] systemd[1]: Finished Create list of static device nodes for the current kernel.
10877 12:16:05.029054 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10878 12:16:05.040456 <3>[ 19.897788] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 12:16:05.047357 <30>[ 19.908200] systemd[1]: modprobe@configfs.service: Succeeded.
10880 12:16:05.054490 <30>[ 19.915097] systemd[1]: Finished Load Kernel Module configfs.
10881 12:16:05.061543 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10882 12:16:05.071273 <3>[ 19.928597] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 12:16:05.078041 <30>[ 19.938796] systemd[1]: modprobe@drm.service: Succeeded.
10884 12:16:05.084582 <30>[ 19.945137] systemd[1]: Finished Load Kernel Module drm.
10885 12:16:05.091532 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10886 12:16:05.102153 <3>[ 19.959390] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 12:16:05.109067 <30>[ 19.969359] systemd[1]: modprobe@fuse.service: Succeeded.
10888 12:16:05.115356 <30>[ 19.975851] systemd[1]: Finished Load Kernel Module fuse.
10889 12:16:05.121953 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10890 12:16:05.132972 <3>[ 19.990673] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 12:16:05.140042 <30>[ 20.000909] systemd[1]: Finished Load Kernel Modules.
10892 12:16:05.147078 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10893 12:16:05.160286 <30>[ 20.021055] systemd[1]: Finished Remount Root and Kernel File Systems.
10894 12:16:05.170364 <3>[ 20.022943] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 12:16:05.177453 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10896 12:16:05.199414 <3>[ 20.057014] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 12:16:05.234816 <30>[ 20.095795] systemd[1]: Mounting FUSE Control File System...
10898 12:16:05.241728 Mounting [0;1;39mFUSE Control File System[0m...
10899 12:16:05.260548 <30>[ 20.118232] systemd[1]: Mounting Kernel Configuration File System...
10900 12:16:05.264105 Mounting [0;1;39mKernel Configuration File System[0m...
10901 12:16:05.289761 <30>[ 20.146990] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10902 12:16:05.299125 <30>[ 20.155989] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10903 12:16:05.308022 <30>[ 20.168564] systemd[1]: Starting Load/Save Random Seed...
10904 12:16:05.314486 Starting [0;1;39mLoad/Save Random Seed[0m...
10905 12:16:05.333987 <30>[ 20.194531] systemd[1]: Starting Apply Kernel Variables...
10906 12:16:05.340039 Starting [0;1;39mApply Kernel Variables[0m...
10907 12:16:05.362136 <30>[ 20.223112] systemd[1]: Starting Create System Users...
10908 12:16:05.369257 Starting [0;1;39mCreate System Users[0m...
10909 12:16:05.384510 <30>[ 20.245192] systemd[1]: Started Journal Service.
10910 12:16:05.390733 <4>[ 20.245864] power_supply_show_property: 2 callbacks suppressed
10911 12:16:05.401390 <3>[ 20.245876] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 12:16:05.405209 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10913 12:16:05.415047 <3>[ 20.270761] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 12:16:05.421479 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10915 12:16:05.450386 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File S<3>[ 20.305804] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 12:16:05.450550 ystem[0m.
10917 12:16:05.474698 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.<3>[ 20.329981] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 12:16:05.480966 <3>[ 20.330743] power_supply sbs-5-000b: driver failed to report `health' property: -6
10919 12:16:05.498394 <4>[ 20.339052] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10920 12:16:05.505335 <3>[ 20.362494] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10921 12:16:05.512026 <3>[ 20.369004] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 12:16:05.512146
10923 12:16:05.528778 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10924 12:16:05.543749 <3>[ 20.401261] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 12:16:05.553933 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10926 12:16:05.577210 See 'systemctl status systemd-udev-trigger.service' for details.<3>[ 20.433213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 12:16:05.577366
10928 12:16:05.591862 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10929 12:16:05.606779 <3>[ 20.464476] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 12:16:05.638710 Starting [0;1;39mFlush<3>[ 20.494789] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 12:16:05.642226 Journal to Persistent Storage[0m...
10932 12:16:05.658487 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10933 12:16:05.711747 <46>[ 20.569520] systemd-journald[301]: Received client request to flush runtime journal.
10934 12:16:05.718705 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10935 12:16:05.736355 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10936 12:16:05.751318 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10937 12:16:05.799233 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10938 12:16:07.079529 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10939 12:16:07.123534 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10940 12:16:07.143846 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10941 12:16:07.166144 Starting [0;1;39mNetwork Service[0m...
10942 12:16:07.487002 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10943 12:16:07.511539 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10944 12:16:07.568130 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10945 12:16:07.728232 <6>[ 22.589173] remoteproc remoteproc0: powering up scp
10946 12:16:07.755299 <4>[ 22.612801] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10947 12:16:07.761459 <3>[ 22.622761] remoteproc remoteproc0: request_firmware failed: -2
10948 12:16:07.771455 <3>[ 22.628950] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10949 12:16:07.909211 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10950 12:16:07.923141 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10951 12:16:07.960443 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10952 12:16:07.984407 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10953 12:16:08.002006 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10954 12:16:08.047166 Starting [0;1;39mNetwork Name Resolution[0m...
10955 12:16:08.070398 Starting [0;1;39mNetwork Time Synchronization[0m...
10956 12:16:08.116984 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10957 12:16:08.138870 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10958 12:16:08.171717 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10959 12:16:08.210101 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10960 12:16:08.540630 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10961 12:16:08.558686 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10962 12:16:08.578179 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10963 12:16:08.590729 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10964 12:16:08.606499 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10965 12:16:08.627969 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10966 12:16:08.662341 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10967 12:16:09.036711 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10968 12:16:09.390165 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10969 12:16:09.407035 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10970 12:16:09.670153 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10971 12:16:09.682718 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10972 12:16:09.698700 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10973 12:16:09.743427 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10974 12:16:09.778911 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10975 12:16:09.831054 Starting [0;1;39mUser Login Management[0m...
10976 12:16:09.847514 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10977 12:16:09.864417 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10978 12:16:09.882037 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10979 12:16:09.930832 Starting [0;1;39mPermit User Sessions[0m...
10980 12:16:10.019935 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10981 12:16:10.055493 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10982 12:16:10.073427 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10983 12:16:10.091150 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10984 12:16:10.111919 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10985 12:16:10.137755 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10986 12:16:10.159570 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10987 12:16:10.178386 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10988 12:16:10.230189 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10989 12:16:10.260476 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10990 12:16:10.364810
10991 12:16:10.365008
10992 12:16:10.368393 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10993 12:16:10.368509
10994 12:16:10.370980 debian-bullseye-arm64 login: root (automatic login)
10995 12:16:10.371096
10996 12:16:10.371213
10997 12:16:10.631802 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023 aarch64
10998 12:16:10.631945
10999 12:16:10.638222 The programs included with the Debian GNU/Linux system are free software;
11000 12:16:10.644657 the exact distribution terms for each program are described in the
11001 12:16:10.648338 individual files in /usr/share/doc/*/copyright.
11002 12:16:10.648421
11003 12:16:10.654608 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11004 12:16:10.654690 permitted by applicable law.
11005 12:16:11.431660 Matched prompt #10: / #
11007 12:16:11.431931 Setting prompt string to ['/ #']
11008 12:16:11.432026 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11010 12:16:11.432250 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11011 12:16:11.432353 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
11012 12:16:11.432424 Setting prompt string to ['/ #']
11013 12:16:11.432485 Forcing a shell prompt, looking for ['/ #']
11015 12:16:11.482699 / #
11016 12:16:11.482825 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11017 12:16:11.482933 Waiting using forced prompt support (timeout 00:02:30)
11018 12:16:11.487599
11019 12:16:11.487881 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11020 12:16:11.487976 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
11022 12:16:11.588291 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605418/extract-nfsrootfs-xjdocy5u'
11023 12:16:11.593493 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605418/extract-nfsrootfs-xjdocy5u'
11025 12:16:11.694129 / # export NFS_SERVER_IP='192.168.201.1'
11026 12:16:11.698840 export NFS_SERVER_IP='192.168.201.1'
11027 12:16:11.699140 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11028 12:16:11.699278 end: 2.2 depthcharge-retry (duration 00:01:27) [common]
11029 12:16:11.699393 end: 2 depthcharge-action (duration 00:01:27) [common]
11030 12:16:11.699487 start: 3 lava-test-retry (timeout 00:07:49) [common]
11031 12:16:11.699576 start: 3.1 lava-test-shell (timeout 00:07:49) [common]
11032 12:16:11.699651 Using namespace: common
11034 12:16:11.799965 / # #
11035 12:16:11.800127 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11036 12:16:11.804843 #
11037 12:16:11.805153 Using /lava-10605418
11039 12:16:11.905523 / # export SHELL=/bin/bash
11040 12:16:11.910313 export SHELL=/bin/bash
11042 12:16:12.010808 / # . /lava-10605418/environment
11043 12:16:12.015875 . /lava-10605418/environment
11045 12:16:12.120582 / # /lava-10605418/bin/lava-test-runner /lava-10605418/0
11046 12:16:12.120772 Test shell timeout: 10s (minimum of the action and connection timeout)
11047 12:16:12.125408 /lava-10605418/bin/lava-test-runner /lava-10605418/0
11048 12:16:12.539079 + export TESTRUN_ID=0_timesync-off
11049 12:16:12.542725 + TESTRUN_ID=0_timesync-off
11050 12:16:12.545574 + cd /lava-10605418/0/tests/0_timesync-off
11051 12:16:12.549154 ++ cat uuid
11052 12:16:12.549418 + UUID=10605418_1.6.2.3.1
11053 12:16:12.552173 + set +x
11054 12:16:12.555650 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10605418_1.6.2.3.1>
11055 12:16:12.556110 Received signal: <STARTRUN> 0_timesync-off 10605418_1.6.2.3.1
11056 12:16:12.556370 Starting test lava.0_timesync-off (10605418_1.6.2.3.1)
11057 12:16:12.556650 Skipping test definition patterns.
11058 12:16:12.559295 + systemctl stop systemd-timesyncd
11059 12:16:12.582516 + set +x
11060 12:16:12.585156 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10605418_1.6.2.3.1>
11061 12:16:12.585630 Received signal: <ENDRUN> 0_timesync-off 10605418_1.6.2.3.1
11062 12:16:12.585901 Ending use of test pattern.
11063 12:16:12.586133 Ending test lava.0_timesync-off (10605418_1.6.2.3.1), duration 0.03
11065 12:16:12.634339 + export TESTRUN_ID=1_kselftest-tpm2
11066 12:16:12.637833 + TESTRUN_ID=1_kselftest-tpm2
11067 12:16:12.640859 + cd /lava-10605418/0/tests/1_kselftest-tpm2
11068 12:16:12.644491 ++ cat uuid
11069 12:16:12.647424 + UUID=10605418_1.6.2.3.5
11070 12:16:12.647503 + set +x
11071 12:16:12.650974 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 10605418_1.6.2.3.5>
11072 12:16:12.651250 Received signal: <STARTRUN> 1_kselftest-tpm2 10605418_1.6.2.3.5
11073 12:16:12.651357 Starting test lava.1_kselftest-tpm2 (10605418_1.6.2.3.5)
11074 12:16:12.651443 Skipping test definition patterns.
11075 12:16:12.654704 + cd ./automated/linux/kselftest/
11076 12:16:12.683826 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11077 12:16:12.693181 INFO: install_deps skipped
11078 12:16:12.790306 --2023-06-06 12:16:00-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11079 12:16:12.804955 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11080 12:16:12.948651 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11081 12:16:13.092670 HTTP request sent, awaiting response... 200 OK
11082 12:16:13.095478 Length: 2704052 (2.6M) [application/octet-stream]
11083 12:16:13.098924 Saving to: 'kselftest.tar.xz'
11084 12:16:13.099042
11085 12:16:13.099165
11086 12:16:13.378661 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11087 12:16:13.662557 kselftest.tar.xz 1%[ ] 44.98K 158KB/s
11088 12:16:14.136570 kselftest.tar.xz 8%[> ] 213.25K 375KB/s
11089 12:16:14.431949 kselftest.tar.xz 29%[====> ] 774.64K 743KB/s
11090 12:16:14.574367 kselftest.tar.xz 90%[=================> ] 2.34M 1.75MB/s
11091 12:16:14.580697 kselftest.tar.xz 100%[===================>] 2.58M 1.74MB/s in 1.5s
11092 12:16:14.580802
11093 12:16:14.811420 2023-06-06 12:16:02 (1.74 MB/s) - 'kselftest.tar.xz' saved [2704052/2704052]
11094 12:16:14.814986
11095 12:16:19.854915 skiplist:
11096 12:16:19.857995 ========================================
11097 12:16:19.861476 ========================================
11098 12:16:19.891929 tpm2:test_smoke.sh
11099 12:16:19.895319 tpm2:test_space.sh
11100 12:16:19.907078 ============== Tests to run ===============
11101 12:16:19.907164 tpm2:test_smoke.sh
11102 12:16:19.910527 tpm2:test_space.sh
11103 12:16:19.913343 ===========End Tests to run ===============
11104 12:16:19.986292 <12>[ 34.848700] kselftest: Running tests in tpm2
11105 12:16:19.993149 TAP version 13
11106 12:16:20.004285 1..2
11107 12:16:20.028118 # selftests: tpm2: test_smoke.sh
11108 12:16:21.141380 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11109 12:16:21.144924 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11110 12:16:21.151188 # Exception ignored in: <function Client.__del__ at 0xffff95862d30>
11111 12:16:21.154719 # Traceback (most recent call last):
11112 12:16:21.164675 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11113 12:16:21.164785 # if self.tpm:
11114 12:16:21.171249 # AttributeError: 'Client' object has no attribute 'tpm'
11115 12:16:21.174590 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11116 12:16:21.181474 # Exception ignored in: <function Client.__del__ at 0xffff95862d30>
11117 12:16:21.184826 # Traceback (most recent call last):
11118 12:16:21.194654 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11119 12:16:21.197811 # if self.tpm:
11120 12:16:21.201631 # AttributeError: 'Client' object has no attribute 'tpm'
11121 12:16:21.208241 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11122 12:16:21.214918 # Exception ignored in: <function Client.__del__ at 0xffff95862d30>
11123 12:16:21.217733 # Traceback (most recent call last):
11124 12:16:21.224617 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11125 12:16:21.228012 # if self.tpm:
11126 12:16:21.234589 # AttributeError: 'Client' object has no attribute 'tpm'
11127 12:16:21.237766 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11128 12:16:21.244586 # Exception ignored in: <function Client.__del__ at 0xffff95862d30>
11129 12:16:21.247975 # Traceback (most recent call last):
11130 12:16:21.257585 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11131 12:16:21.257671 # if self.tpm:
11132 12:16:21.264451 # AttributeError: 'Client' object has no attribute 'tpm'
11133 12:16:21.267767 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11134 12:16:21.274505 # Exception ignored in: <function Client.__del__ at 0xffff95862d30>
11135 12:16:21.277856 # Traceback (most recent call last):
11136 12:16:21.287698 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11137 12:16:21.291525 # if self.tpm:
11138 12:16:21.294354 # AttributeError: 'Client' object has no attribute 'tpm'
11139 12:16:21.301590 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11140 12:16:21.304852 # Exception ignored in: <function Client.__del__ at 0xffff95862d30>
11141 12:16:21.308038 # Traceback (most recent call last):
11142 12:16:21.318264 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11143 12:16:21.321654 # if self.tpm:
11144 12:16:21.324370 # AttributeError: 'Client' object has no attribute 'tpm'
11145 12:16:21.331210 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11146 12:16:21.337776 # Exception ignored in: <function Client.__del__ at 0xffff95862d30>
11147 12:16:21.340969 # Traceback (most recent call last):
11148 12:16:21.350870 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11149 12:16:21.350983 # if self.tpm:
11150 12:16:21.357824 # AttributeError: 'Client' object has no attribute 'tpm'
11151 12:16:21.364096 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11152 12:16:21.367435 # Exception ignored in: <function Client.__del__ at 0xffff95862d30>
11153 12:16:21.371310 # Traceback (most recent call last):
11154 12:16:21.380736 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11155 12:16:21.384288 # if self.tpm:
11156 12:16:21.387712 # AttributeError: 'Client' object has no attribute 'tpm'
11157 12:16:21.391096 #
11158 12:16:21.394631 # ======================================================================
11159 12:16:21.402133 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11160 12:16:21.411097 # ----------------------------------------------------------------------
11161 12:16:21.411181 # Traceback (most recent call last):
11162 12:16:21.421286 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11163 12:16:21.424452 # self.root_key = self.client.create_root_key()
11164 12:16:21.438112 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11165 12:16:21.441542 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11166 12:16:21.451224 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11167 12:16:21.454564 # raise ProtocolError(cc, rc)
11168 12:16:21.461489 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11169 12:16:21.461603 #
11170 12:16:21.467693 # ======================================================================
11171 12:16:21.471023 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11172 12:16:21.478342 # ----------------------------------------------------------------------
11173 12:16:21.481077 # Traceback (most recent call last):
11174 12:16:21.491443 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11175 12:16:21.494718 # self.client = tpm2.Client()
11176 12:16:21.504986 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11177 12:16:21.511248 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11178 12:16:21.514559 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11179 12:16:21.514660 #
11180 12:16:21.521466 # ======================================================================
11181 12:16:21.527938 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11182 12:16:21.534930 # ----------------------------------------------------------------------
11183 12:16:21.538388 # Traceback (most recent call last):
11184 12:16:21.547880 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11185 12:16:21.547966 # self.client = tpm2.Client()
11186 12:16:21.557792 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11187 12:16:21.564684 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11188 12:16:21.568079 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11189 12:16:21.571557 #
11190 12:16:21.574885 # ======================================================================
11191 12:16:21.581404 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11192 12:16:21.588209 # ----------------------------------------------------------------------
11193 12:16:21.591692 # Traceback (most recent call last):
11194 12:16:21.601920 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11195 12:16:21.605334 # self.client = tpm2.Client()
11196 12:16:21.615012 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11197 12:16:21.618382 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11198 12:16:21.624696 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11199 12:16:21.624816 #
11200 12:16:21.631367 # ======================================================================
11201 12:16:21.634803 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11202 12:16:21.641728 # ----------------------------------------------------------------------
11203 12:16:21.644998 # Traceback (most recent call last):
11204 12:16:21.655185 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11205 12:16:21.658512 # self.client = tpm2.Client()
11206 12:16:21.668067 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11207 12:16:21.674945 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11208 12:16:21.678418 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11209 12:16:21.678572 #
11210 12:16:21.687685 # ======================================================================
11211 12:16:21.692964 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11212 12:16:21.697017 # ----------------------------------------------------------------------
11213 12:16:21.701803 # Traceback (most recent call last):
11214 12:16:21.713787 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11215 12:16:21.713877 # self.client = tpm2.Client()
11216 12:16:21.725620 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11217 12:16:21.729683 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11218 12:16:21.732468 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11219 12:16:21.732556 #
11220 12:16:21.739407 # ======================================================================
11221 12:16:21.742734 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11222 12:16:21.749111 # ----------------------------------------------------------------------
11223 12:16:21.752349 # Traceback (most recent call last):
11224 12:16:21.762851 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11225 12:16:21.766325 # self.client = tpm2.Client()
11226 12:16:21.775280 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11227 12:16:21.782013 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11228 12:16:21.785357 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11229 12:16:21.788770 #
11230 12:16:21.792064 # ======================================================================
11231 12:16:21.798862 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11232 12:16:21.805506 # ----------------------------------------------------------------------
11233 12:16:21.808911 # Traceback (most recent call last):
11234 12:16:21.819115 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11235 12:16:21.822596 # self.client = tpm2.Client()
11236 12:16:21.832653 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11237 12:16:21.836061 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11238 12:16:21.842894 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11239 12:16:21.842977 #
11240 12:16:21.848933 # ======================================================================
11241 12:16:21.852308 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11242 12:16:21.859300 # ----------------------------------------------------------------------
11243 12:16:21.862476 # Traceback (most recent call last):
11244 12:16:21.872683 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11245 12:16:21.876018 # self.client = tpm2.Client()
11246 12:16:21.886308 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11247 12:16:21.892870 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11248 12:16:21.896163 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11249 12:16:21.896247 #
11250 12:16:21.902956 # ----------------------------------------------------------------------
11251 12:16:21.906238 # Ran 9 tests in 0.023s
11252 12:16:21.906352 #
11253 12:16:21.909068 # FAILED (errors=9)
11254 12:16:21.912478 # test_async (tpm2_tests.AsyncTest) ... ok
11255 12:16:21.915875 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11256 12:16:21.915958 #
11257 12:16:21.922680 # ----------------------------------------------------------------------
11258 12:16:21.925998 # Ran 2 tests in 0.027s
11259 12:16:21.926080 #
11260 12:16:21.926144 # OK
11261 12:16:21.929451 ok 1 selftests: tpm2: test_smoke.sh
11262 12:16:21.932835 # selftests: tpm2: test_space.sh
11263 12:16:21.939580 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11264 12:16:21.943086 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11265 12:16:21.945775 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11266 12:16:21.952675 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11267 12:16:21.952759 #
11268 12:16:21.959495 # ======================================================================
11269 12:16:21.962887 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11270 12:16:21.969372 # ----------------------------------------------------------------------
11271 12:16:21.972552 # Traceback (most recent call last):
11272 12:16:21.982858 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11273 12:16:21.986263 # root1 = space1.create_root_key()
11274 12:16:21.999818 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11275 12:16:22.002973 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11276 12:16:22.012718 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11277 12:16:22.015889 # raise ProtocolError(cc, rc)
11278 12:16:22.022858 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11279 12:16:22.022944 #
11280 12:16:22.029231 # ======================================================================
11281 12:16:22.032691 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11282 12:16:22.039510 # ----------------------------------------------------------------------
11283 12:16:22.042801 # Traceback (most recent call last):
11284 12:16:22.052984 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11285 12:16:22.056526 # space1.create_root_key()
11286 12:16:22.066699 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11287 12:16:22.073078 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11288 12:16:22.083313 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11289 12:16:22.086712 # raise ProtocolError(cc, rc)
11290 12:16:22.093456 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11291 12:16:22.093533 #
11292 12:16:22.100029 # ======================================================================
11293 12:16:22.102766 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11294 12:16:22.109771 # ----------------------------------------------------------------------
11295 12:16:22.112856 # Traceback (most recent call last):
11296 12:16:22.122756 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11297 12:16:22.126200 # root1 = space1.create_root_key()
11298 12:16:22.136440 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11299 12:16:22.143150 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11300 12:16:22.152849 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11301 12:16:22.156405 # raise ProtocolError(cc, rc)
11302 12:16:22.163217 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11303 12:16:22.163312 #
11304 12:16:22.169327 # ======================================================================
11305 12:16:22.172796 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11306 12:16:22.180021 # ----------------------------------------------------------------------
11307 12:16:22.183179 # Traceback (most recent call last):
11308 12:16:22.196240 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11309 12:16:22.199579 # root1 = space1.create_root_key()
11310 12:16:22.209657 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11311 12:16:22.213018 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11312 12:16:22.222998 # File "/lava-10605418/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11313 12:16:22.226865 # raise ProtocolError(cc, rc)
11314 12:16:22.233586 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11315 12:16:22.233689 #
11316 12:16:22.240083 # ----------------------------------------------------------------------
11317 12:16:22.243480 # Ran 4 tests in 0.055s
11318 12:16:22.243571 #
11319 12:16:22.243640 # FAILED (errors=4)
11320 12:16:22.249457 not ok 2 selftests: tpm2: test_space.sh # exit=1
11321 12:16:22.249583 tpm2_test_smoke_sh pass
11322 12:16:22.252831 tpm2_test_space_sh fail
11323 12:16:22.269151 + ../../utils/send-to-lava.sh ./output/result.txt
11324 12:16:22.317611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11325 12:16:22.317985 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11327 12:16:22.351700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11328 12:16:22.352026 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11330 12:16:22.355018 + set +x
11331 12:16:22.358400 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 10605418_1.6.2.3.5>
11332 12:16:22.358655 Received signal: <ENDRUN> 1_kselftest-tpm2 10605418_1.6.2.3.5
11333 12:16:22.358740 Ending use of test pattern.
11334 12:16:22.358811 Ending test lava.1_kselftest-tpm2 (10605418_1.6.2.3.5), duration 9.71
11336 12:16:22.361796 <LAVA_TEST_RUNNER EXIT>
11337 12:16:22.362075 ok: lava_test_shell seems to have completed
11338 12:16:22.362219 tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11339 12:16:22.362344 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11340 12:16:22.362458 end: 3 lava-test-retry (duration 00:00:11) [common]
11341 12:16:22.362573 start: 4 finalize (timeout 00:07:38) [common]
11342 12:16:22.362704 start: 4.1 power-off (timeout 00:00:30) [common]
11343 12:16:22.362870 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11344 12:16:22.438183 >> Command sent successfully.
11345 12:16:22.440763 Returned 0 in 0 seconds
11346 12:16:22.541154 end: 4.1 power-off (duration 00:00:00) [common]
11348 12:16:22.541487 start: 4.2 read-feedback (timeout 00:07:38) [common]
11349 12:16:22.541751 Listened to connection for namespace 'common' for up to 1s
11350 12:16:23.542674 Finalising connection for namespace 'common'
11351 12:16:23.542844 Disconnecting from shell: Finalise
11352 12:16:23.542954 / #
11353 12:16:23.643598 end: 4.2 read-feedback (duration 00:00:01) [common]
11354 12:16:23.644456 end: 4 finalize (duration 00:00:01) [common]
11355 12:16:23.645447 Cleaning after the job
11356 12:16:23.646011 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/ramdisk
11357 12:16:23.657982 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/kernel
11358 12:16:23.686487 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/dtb
11359 12:16:23.686873 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/nfsrootfs
11360 12:16:23.756738 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605418/tftp-deploy-2hk8o711/modules
11361 12:16:23.761960 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605418
11362 12:16:24.284702 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605418
11363 12:16:24.284869 Job finished correctly