Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 63
1 12:10:21.867664 lava-dispatcher, installed at version: 2023.05.1
2 12:10:21.867889 start: 0 validate
3 12:10:21.868027 Start time: 2023-06-06 12:10:21.868020+00:00 (UTC)
4 12:10:21.868170 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:10:21.868302 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:10:22.388914 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:10:22.389807 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:10:45.728551 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:10:45.729282 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:10:46.025640 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:10:46.025832 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:10:49.319154 validate duration: 27.45
14 12:10:49.319523 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:10:49.319648 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:10:49.319781 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:10:49.319962 Not decompressing ramdisk as can be used compressed.
18 12:10:49.320080 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 12:10:49.320146 saving as /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/ramdisk/rootfs.cpio.gz
20 12:10:49.320207 total size: 27151647 (25MB)
21 12:10:49.610636 progress 0% (0MB)
22 12:10:49.622187 progress 5% (1MB)
23 12:10:49.633599 progress 10% (2MB)
24 12:10:49.645138 progress 15% (3MB)
25 12:10:49.654474 progress 20% (5MB)
26 12:10:49.661582 progress 25% (6MB)
27 12:10:49.668485 progress 30% (7MB)
28 12:10:49.675451 progress 35% (9MB)
29 12:10:49.682238 progress 40% (10MB)
30 12:10:49.689043 progress 45% (11MB)
31 12:10:49.695989 progress 50% (12MB)
32 12:10:49.702779 progress 55% (14MB)
33 12:10:49.709745 progress 60% (15MB)
34 12:10:49.716550 progress 65% (16MB)
35 12:10:49.723526 progress 70% (18MB)
36 12:10:49.730405 progress 75% (19MB)
37 12:10:49.737289 progress 80% (20MB)
38 12:10:49.744252 progress 85% (22MB)
39 12:10:49.751358 progress 90% (23MB)
40 12:10:49.758316 progress 95% (24MB)
41 12:10:49.765132 progress 100% (25MB)
42 12:10:49.765347 25MB downloaded in 0.45s (58.17MB/s)
43 12:10:49.765508 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:10:49.765749 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:10:49.765837 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:10:49.765923 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:10:49.766056 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:10:49.766130 saving as /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/kernel/Image
50 12:10:49.766196 total size: 45746688 (43MB)
51 12:10:49.766258 No compression specified
52 12:10:49.767358 progress 0% (0MB)
53 12:10:49.778845 progress 5% (2MB)
54 12:10:49.790409 progress 10% (4MB)
55 12:10:49.802039 progress 15% (6MB)
56 12:10:49.813631 progress 20% (8MB)
57 12:10:49.825172 progress 25% (10MB)
58 12:10:49.836624 progress 30% (13MB)
59 12:10:49.848463 progress 35% (15MB)
60 12:10:49.860110 progress 40% (17MB)
61 12:10:49.871802 progress 45% (19MB)
62 12:10:49.883377 progress 50% (21MB)
63 12:10:49.894879 progress 55% (24MB)
64 12:10:49.906567 progress 60% (26MB)
65 12:10:49.918217 progress 65% (28MB)
66 12:10:49.929797 progress 70% (30MB)
67 12:10:49.941509 progress 75% (32MB)
68 12:10:49.953105 progress 80% (34MB)
69 12:10:49.964922 progress 85% (37MB)
70 12:10:49.976608 progress 90% (39MB)
71 12:10:49.988072 progress 95% (41MB)
72 12:10:49.999593 progress 100% (43MB)
73 12:10:49.999730 43MB downloaded in 0.23s (186.82MB/s)
74 12:10:49.999880 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:10:50.000114 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:10:50.000203 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:10:50.000297 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:10:50.000437 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:10:50.000512 saving as /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/dtb/mt8192-asurada-spherion-r0.dtb
81 12:10:50.000575 total size: 46924 (0MB)
82 12:10:50.000637 No compression specified
83 12:10:50.001736 progress 69% (0MB)
84 12:10:50.002009 progress 100% (0MB)
85 12:10:50.002163 0MB downloaded in 0.00s (28.22MB/s)
86 12:10:50.002284 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:10:50.002510 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:10:50.002595 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:10:50.002680 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:10:50.002791 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:10:50.002860 saving as /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/modules/modules.tar
93 12:10:50.002921 total size: 8553528 (8MB)
94 12:10:50.002981 Using unxz to decompress xz
95 12:10:50.006513 progress 0% (0MB)
96 12:10:50.027473 progress 5% (0MB)
97 12:10:50.051568 progress 10% (0MB)
98 12:10:50.082375 progress 15% (1MB)
99 12:10:50.108292 progress 20% (1MB)
100 12:10:50.132997 progress 25% (2MB)
101 12:10:50.158477 progress 30% (2MB)
102 12:10:50.184440 progress 35% (2MB)
103 12:10:50.209314 progress 40% (3MB)
104 12:10:50.234747 progress 45% (3MB)
105 12:10:50.259840 progress 50% (4MB)
106 12:10:50.284278 progress 55% (4MB)
107 12:10:50.308565 progress 60% (4MB)
108 12:10:50.333444 progress 65% (5MB)
109 12:10:50.358839 progress 70% (5MB)
110 12:10:50.383327 progress 75% (6MB)
111 12:10:50.409595 progress 80% (6MB)
112 12:10:50.434961 progress 85% (6MB)
113 12:10:50.460349 progress 90% (7MB)
114 12:10:50.483792 progress 95% (7MB)
115 12:10:50.510003 progress 100% (8MB)
116 12:10:50.514617 8MB downloaded in 0.51s (15.94MB/s)
117 12:10:50.514967 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:10:50.515422 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:10:50.515555 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:10:50.515699 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:10:50.515822 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:10:50.515960 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:10:50.516236 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj
125 12:10:50.516417 makedir: /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin
126 12:10:50.516557 makedir: /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/tests
127 12:10:50.516707 makedir: /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/results
128 12:10:50.516865 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-add-keys
129 12:10:50.517064 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-add-sources
130 12:10:50.517230 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-background-process-start
131 12:10:50.517413 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-background-process-stop
132 12:10:50.517574 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-common-functions
133 12:10:50.517749 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-echo-ipv4
134 12:10:50.517911 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-install-packages
135 12:10:50.518084 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-installed-packages
136 12:10:50.518244 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-os-build
137 12:10:50.518405 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-probe-channel
138 12:10:50.518582 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-probe-ip
139 12:10:50.518743 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-target-ip
140 12:10:50.518915 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-target-mac
141 12:10:50.519077 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-target-storage
142 12:10:50.519249 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-test-case
143 12:10:50.519422 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-test-event
144 12:10:50.519549 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-test-feedback
145 12:10:50.519698 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-test-raise
146 12:10:50.519859 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-test-reference
147 12:10:50.520040 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-test-runner
148 12:10:50.520204 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-test-set
149 12:10:50.520377 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-test-shell
150 12:10:50.520556 Updating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-install-packages (oe)
151 12:10:50.520742 Updating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/bin/lava-installed-packages (oe)
152 12:10:50.520911 Creating /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/environment
153 12:10:50.521046 LAVA metadata
154 12:10:50.521153 - LAVA_JOB_ID=10605394
155 12:10:50.521258 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:10:50.521417 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:10:50.521520 skipped lava-vland-overlay
158 12:10:50.521634 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:10:50.521767 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:10:50.521864 skipped lava-multinode-overlay
161 12:10:50.521976 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:10:50.522107 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:10:50.522220 Loading test definitions
164 12:10:50.522360 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:10:50.522449 Using /lava-10605394 at stage 0
166 12:10:50.522852 uuid=10605394_1.5.2.3.1 testdef=None
167 12:10:50.522977 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:10:50.523101 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:10:50.523880 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:10:50.524210 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:10:50.525136 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:10:50.525544 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:10:50.526485 runner path: /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 10605394_1.5.2.3.1
176 12:10:50.526683 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:10:50.527051 Creating lava-test-runner.conf files
179 12:10:50.527154 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605394/lava-overlay-yt69w0pj/lava-10605394/0 for stage 0
180 12:10:50.527288 - 0_v4l2-compliance-mtk-vcodec-enc
181 12:10:50.527433 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:10:50.527566 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:10:50.536242 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:10:50.536393 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:10:50.536516 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:10:50.536653 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:10:50.536783 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:10:51.260654 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:10:51.261028 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:10:51.261178 extracting modules file /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605394/extract-overlay-ramdisk-3x113uu7/ramdisk
191 12:10:51.492916 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:10:51.493093 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:10:51.493196 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605394/compress-overlay-wst4nwfq/overlay-1.5.2.4.tar.gz to ramdisk
194 12:10:51.493272 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605394/compress-overlay-wst4nwfq/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605394/extract-overlay-ramdisk-3x113uu7/ramdisk
195 12:10:51.499819 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:10:51.499935 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:10:51.500031 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:10:51.500127 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:10:51.500210 Building ramdisk /var/lib/lava/dispatcher/tmp/10605394/extract-overlay-ramdisk-3x113uu7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605394/extract-overlay-ramdisk-3x113uu7/ramdisk
200 12:10:52.043741 >> 230342 blocks
201 12:10:56.152025 rename /var/lib/lava/dispatcher/tmp/10605394/extract-overlay-ramdisk-3x113uu7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/ramdisk/ramdisk.cpio.gz
202 12:10:56.152479 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:10:56.152623 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 12:10:56.152735 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 12:10:56.152907 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/kernel/Image'
206 12:11:09.169722 Returned 0 in 13 seconds
207 12:11:09.270336 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/kernel/image.itb
208 12:11:09.945681 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:11:09.946067 output: Created: Tue Jun 6 13:11:09 2023
210 12:11:09.946197 output: Image 0 (kernel-1)
211 12:11:09.946297 output: Description:
212 12:11:09.946401 output: Created: Tue Jun 6 13:11:09 2023
213 12:11:09.946506 output: Type: Kernel Image
214 12:11:09.946598 output: Compression: lzma compressed
215 12:11:09.946707 output: Data Size: 10094623 Bytes = 9858.03 KiB = 9.63 MiB
216 12:11:09.946799 output: Architecture: AArch64
217 12:11:09.946911 output: OS: Linux
218 12:11:09.947018 output: Load Address: 0x00000000
219 12:11:09.947110 output: Entry Point: 0x00000000
220 12:11:09.947210 output: Hash algo: crc32
221 12:11:09.947318 output: Hash value: fd97082e
222 12:11:09.947399 output: Image 1 (fdt-1)
223 12:11:09.947457 output: Description: mt8192-asurada-spherion-r0
224 12:11:09.947527 output: Created: Tue Jun 6 13:11:09 2023
225 12:11:09.947593 output: Type: Flat Device Tree
226 12:11:09.947649 output: Compression: uncompressed
227 12:11:09.947705 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:11:09.947782 output: Architecture: AArch64
229 12:11:09.947855 output: Hash algo: crc32
230 12:11:09.947912 output: Hash value: 1df858fa
231 12:11:09.947967 output: Image 2 (ramdisk-1)
232 12:11:09.948037 output: Description: unavailable
233 12:11:09.948102 output: Created: Tue Jun 6 13:11:09 2023
234 12:11:09.948158 output: Type: RAMDisk Image
235 12:11:09.948214 output: Compression: Unknown Compression
236 12:11:09.948269 output: Data Size: 40135491 Bytes = 39194.82 KiB = 38.28 MiB
237 12:11:09.948347 output: Architecture: AArch64
238 12:11:09.948403 output: OS: Linux
239 12:11:09.948458 output: Load Address: unavailable
240 12:11:09.948526 output: Entry Point: unavailable
241 12:11:09.948582 output: Hash algo: crc32
242 12:11:09.948637 output: Hash value: edaa38dc
243 12:11:09.948703 output: Default Configuration: 'conf-1'
244 12:11:09.948772 output: Configuration 0 (conf-1)
245 12:11:09.948828 output: Description: mt8192-asurada-spherion-r0
246 12:11:09.948883 output: Kernel: kernel-1
247 12:11:09.948948 output: Init Ramdisk: ramdisk-1
248 12:11:09.949005 output: FDT: fdt-1
249 12:11:09.949060 output: Loadables: kernel-1
250 12:11:09.949114 output:
251 12:11:09.949331 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:11:09.949452 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:11:09.949593 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 12:11:09.949743 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 12:11:09.949858 No LXC device requested
256 12:11:09.949999 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:11:09.950120 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 12:11:09.950245 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:11:09.950348 Checking files for TFTP limit of 4294967296 bytes.
260 12:11:09.951105 end: 1 tftp-deploy (duration 00:00:21) [common]
261 12:11:09.951259 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:11:09.951399 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:11:09.951532 substitutions:
264 12:11:09.951609 - {DTB}: 10605394/tftp-deploy-aoyxsptu/dtb/mt8192-asurada-spherion-r0.dtb
265 12:11:09.951679 - {INITRD}: 10605394/tftp-deploy-aoyxsptu/ramdisk/ramdisk.cpio.gz
266 12:11:09.951740 - {KERNEL}: 10605394/tftp-deploy-aoyxsptu/kernel/Image
267 12:11:09.951818 - {LAVA_MAC}: None
268 12:11:09.951887 - {PRESEED_CONFIG}: None
269 12:11:09.951946 - {PRESEED_LOCAL}: None
270 12:11:09.952003 - {RAMDISK}: 10605394/tftp-deploy-aoyxsptu/ramdisk/ramdisk.cpio.gz
271 12:11:09.952078 - {ROOT_PART}: None
272 12:11:09.952151 - {ROOT}: None
273 12:11:09.952208 - {SERVER_IP}: 192.168.201.1
274 12:11:09.952285 - {TEE}: None
275 12:11:09.952350 Parsed boot commands:
276 12:11:09.952416 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:11:09.952643 Parsed boot commands: tftpboot 192.168.201.1 10605394/tftp-deploy-aoyxsptu/kernel/image.itb 10605394/tftp-deploy-aoyxsptu/kernel/cmdline
278 12:11:09.952767 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:11:09.952858 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:11:09.952983 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:11:09.953079 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:11:09.953153 Not connected, no need to disconnect.
283 12:11:09.953255 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:11:09.953342 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:11:09.953429 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
286 12:11:09.957022 Setting prompt string to ['lava-test: # ']
287 12:11:09.957432 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:11:09.957585 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:11:09.957694 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:11:09.957803 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:11:09.958162 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 12:11:15.096990 >> Command sent successfully.
293 12:11:15.100812 Returned 0 in 5 seconds
294 12:11:15.201258 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:11:15.201914 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:11:15.202041 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:11:15.202180 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:11:15.202299 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:11:15.202442 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:11:15.202885 [Enter `^Ec?' for help]
302 12:11:15.374028
303 12:11:15.374214
304 12:11:15.374325 F0: 102B 0000
305 12:11:15.374421
306 12:11:15.374518 F3: 1001 0000 [0200]
307 12:11:15.377802
308 12:11:15.377925 F3: 1001 0000
309 12:11:15.378025
310 12:11:15.378121 F7: 102D 0000
311 12:11:15.378212
312 12:11:15.381001 F1: 0000 0000
313 12:11:15.381117
314 12:11:15.381213 V0: 0000 0000 [0001]
315 12:11:15.381304
316 12:11:15.384146 00: 0007 8000
317 12:11:15.384236
318 12:11:15.384302 01: 0000 0000
319 12:11:15.384366
320 12:11:15.387655 BP: 0C00 0209 [0000]
321 12:11:15.387786
322 12:11:15.387885 G0: 1182 0000
323 12:11:15.387977
324 12:11:15.391210 EC: 0000 0021 [4000]
325 12:11:15.391333
326 12:11:15.391467 S7: 0000 0000 [0000]
327 12:11:15.391558
328 12:11:15.394359 CC: 0000 0000 [0001]
329 12:11:15.394470
330 12:11:15.394576 T0: 0000 0040 [010F]
331 12:11:15.394643
332 12:11:15.397656 Jump to BL
333 12:11:15.397776
334 12:11:15.421146
335 12:11:15.421341
336 12:11:15.421450
337 12:11:15.428576 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:11:15.431977 ARM64: Exception handlers installed.
339 12:11:15.435715 ARM64: Testing exception
340 12:11:15.438702 ARM64: Done test exception
341 12:11:15.445638 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:11:15.455940 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:11:15.462228 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:11:15.472143 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:11:15.478852 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:11:15.489273 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:11:15.498675 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:11:15.505638 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:11:15.524142 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:11:15.527189 WDT: Last reset was cold boot
351 12:11:15.530894 SPI1(PAD0) initialized at 2873684 Hz
352 12:11:15.534141 SPI5(PAD0) initialized at 992727 Hz
353 12:11:15.537185 VBOOT: Loading verstage.
354 12:11:15.544105 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:11:15.547169 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:11:15.551054 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:11:15.554246 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:11:15.561716 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:11:15.568160 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:11:15.578830 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:11:15.579087
362 12:11:15.579229
363 12:11:15.589152 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:11:15.592208 ARM64: Exception handlers installed.
365 12:11:15.596034 ARM64: Testing exception
366 12:11:15.596170 ARM64: Done test exception
367 12:11:15.602287 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:11:15.606330 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:11:15.619817 Probing TPM: . done!
370 12:11:15.620042 TPM ready after 0 ms
371 12:11:15.627328 Connected to device vid:did:rid of 1ae0:0028:00
372 12:11:15.634432 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 12:11:15.637441 Initialized TPM device CR50 revision 0
374 12:11:15.704743 tlcl_send_startup: Startup return code is 0
375 12:11:15.704968 TPM: setup succeeded
376 12:11:15.716726 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:11:15.724893 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:11:15.736863 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:11:15.746924 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:11:15.750653 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:11:15.755644 in-header: 03 07 00 00 08 00 00 00
382 12:11:15.759496 in-data: aa e4 47 04 13 02 00 00
383 12:11:15.763287 Chrome EC: UHEPI supported
384 12:11:15.769639 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:11:15.773386 in-header: 03 ad 00 00 08 00 00 00
386 12:11:15.777071 in-data: 00 20 20 08 00 00 00 00
387 12:11:15.777236 Phase 1
388 12:11:15.780492 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:11:15.787924 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:11:15.791257 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:11:15.794801 Recovery requested (1009000e)
392 12:11:15.805035 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:11:15.811215 tlcl_extend: response is 0
394 12:11:15.820747 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:11:15.827076 tlcl_extend: response is 0
396 12:11:15.834035 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:11:15.853843 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:11:15.860977 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:11:15.861170
400 12:11:15.861307
401 12:11:15.871703 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:11:15.874597 ARM64: Exception handlers installed.
403 12:11:15.874777 ARM64: Testing exception
404 12:11:15.878296 ARM64: Done test exception
405 12:11:15.899714 pmic_efuse_setting: Set efuses in 11 msecs
406 12:11:15.902710 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:11:15.909540 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:11:15.913052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:11:15.916510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:11:15.924033 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:11:15.927891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:11:15.934787 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:11:15.938423 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:11:15.941693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:11:15.945026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:11:15.952632 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:11:15.955792 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:11:15.959505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:11:15.967174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:11:15.970826 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:11:15.977982 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:11:15.981802 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:11:15.988844 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:11:15.995829 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:11:15.999659 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:11:16.006919 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:11:16.010481 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:11:16.018200 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:11:16.021706 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:11:16.029406 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:11:16.032524 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:11:16.039690 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:11:16.043435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:11:16.050498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:11:16.054258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:11:16.057434 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:11:16.065067 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:11:16.068262 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:11:16.071911 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:11:16.079159 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:11:16.082860 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:11:16.089977 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:11:16.093778 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:11:16.097727 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:11:16.101591 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:11:16.108951 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:11:16.112398 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:11:16.115836 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:11:16.119982 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:11:16.123586 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:11:16.130688 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:11:16.134228 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:11:16.138110 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:11:16.142040 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:11:16.145774 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:11:16.148916 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:11:16.152756 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:11:16.163524 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:11:16.171091 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:11:16.174977 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:11:16.182115 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:11:16.193595 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:11:16.196765 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:11:16.200605 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:11:16.204397 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:11:16.212645 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x5
467 12:11:16.216407 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:11:16.224072 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 12:11:16.227050 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:11:16.236722 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 12:11:16.246586 [RTC]rtc_get_frequency_meter,154: input=23, output=978
472 12:11:16.255501 [RTC]rtc_get_frequency_meter,154: input=19, output=883
473 12:11:16.265730 [RTC]rtc_get_frequency_meter,154: input=17, output=837
474 12:11:16.275204 [RTC]rtc_get_frequency_meter,154: input=16, output=813
475 12:11:16.284191 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 12:11:16.293782 [RTC]rtc_get_frequency_meter,154: input=16, output=813
477 12:11:16.297457 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 12:11:16.303795 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 12:11:16.308192 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:11:16.311381 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:11:16.315230 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:11:16.318484 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:11:16.322443 ADC[4]: Raw value=901697 ID=7
484 12:11:16.326116 ADC[3]: Raw value=213336 ID=1
485 12:11:16.326312 RAM Code: 0x71
486 12:11:16.329744 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:11:16.337033 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:11:16.344256 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:11:16.351849 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:11:16.355751 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:11:16.358974 in-header: 03 07 00 00 08 00 00 00
492 12:11:16.362926 in-data: aa e4 47 04 13 02 00 00
493 12:11:16.363116 Chrome EC: UHEPI supported
494 12:11:16.369872 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:11:16.374033 in-header: 03 ed 00 00 08 00 00 00
496 12:11:16.377621 in-data: 80 20 60 08 00 00 00 00
497 12:11:16.381575 MRC: failed to locate region type 0.
498 12:11:16.389240 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:11:16.389432 DRAM-K: Running full calibration
500 12:11:16.396222 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:11:16.400030 header.status = 0x0
502 12:11:16.400238 header.version = 0x6 (expected: 0x6)
503 12:11:16.403877 header.size = 0xd00 (expected: 0xd00)
504 12:11:16.407691 header.flags = 0x0
505 12:11:16.414057 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:11:16.430782 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 12:11:16.438060 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:11:16.441146 dram_init: ddr_geometry: 2
509 12:11:16.441357 [EMI] MDL number = 2
510 12:11:16.444805 [EMI] Get MDL freq = 0
511 12:11:16.444986 dram_init: ddr_type: 0
512 12:11:16.448442 is_discrete_lpddr4: 1
513 12:11:16.451477 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:11:16.451675
515 12:11:16.451794
516 12:11:16.455006 [Bian_co] ETT version 0.0.0.1
517 12:11:16.458582 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:11:16.458764
519 12:11:16.461596 dramc_set_vcore_voltage set vcore to 650000
520 12:11:16.465294 Read voltage for 800, 4
521 12:11:16.465470 Vio18 = 0
522 12:11:16.468480 Vcore = 650000
523 12:11:16.468636 Vdram = 0
524 12:11:16.468737 Vddq = 0
525 12:11:16.471645 Vmddr = 0
526 12:11:16.471782 dram_init: config_dvfs: 1
527 12:11:16.478488 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:11:16.484841 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:11:16.488070 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 12:11:16.491851 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 12:11:16.494960 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 12:11:16.498069 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 12:11:16.501191 MEM_TYPE=3, freq_sel=18
534 12:11:16.504452 sv_algorithm_assistance_LP4_1600
535 12:11:16.508328 ============ PULL DRAM RESETB DOWN ============
536 12:11:16.511695 ========== PULL DRAM RESETB DOWN end =========
537 12:11:16.518440 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:11:16.521667 ===================================
539 12:11:16.521852 LPDDR4 DRAM CONFIGURATION
540 12:11:16.524725 ===================================
541 12:11:16.528436 EX_ROW_EN[0] = 0x0
542 12:11:16.528635 EX_ROW_EN[1] = 0x0
543 12:11:16.531654 LP4Y_EN = 0x0
544 12:11:16.531837 WORK_FSP = 0x0
545 12:11:16.534738 WL = 0x2
546 12:11:16.537906 RL = 0x2
547 12:11:16.538091 BL = 0x2
548 12:11:16.541525 RPST = 0x0
549 12:11:16.541682 RD_PRE = 0x0
550 12:11:16.544569 WR_PRE = 0x1
551 12:11:16.544690 WR_PST = 0x0
552 12:11:16.548091 DBI_WR = 0x0
553 12:11:16.548240 DBI_RD = 0x0
554 12:11:16.551711 OTF = 0x1
555 12:11:16.554658 ===================================
556 12:11:16.557855 ===================================
557 12:11:16.557969 ANA top config
558 12:11:16.561273 ===================================
559 12:11:16.564772 DLL_ASYNC_EN = 0
560 12:11:16.567878 ALL_SLAVE_EN = 1
561 12:11:16.568080 NEW_RANK_MODE = 1
562 12:11:16.571330 DLL_IDLE_MODE = 1
563 12:11:16.574745 LP45_APHY_COMB_EN = 1
564 12:11:16.578035 TX_ODT_DIS = 1
565 12:11:16.578188 NEW_8X_MODE = 1
566 12:11:16.581177 ===================================
567 12:11:16.585021 ===================================
568 12:11:16.588225 data_rate = 1600
569 12:11:16.591411 CKR = 1
570 12:11:16.607361 DQ_P2S_RATIO = 8
571 12:11:16.607571 ===================================
572 12:11:16.607688 CA_P2S_RATIO = 8
573 12:11:16.607784 DQ_CA_OPEN = 0
574 12:11:16.607877 DQ_SEMI_OPEN = 0
575 12:11:16.608169 CA_SEMI_OPEN = 0
576 12:11:16.611293 CA_FULL_RATE = 0
577 12:11:16.615096 DQ_CKDIV4_EN = 1
578 12:11:16.618166 CA_CKDIV4_EN = 1
579 12:11:16.621403 CA_PREDIV_EN = 0
580 12:11:16.621586 PH8_DLY = 0
581 12:11:16.625155 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:11:16.628336 DQ_AAMCK_DIV = 4
583 12:11:16.641990 CA_AAMCK_DIV = 4
584 12:11:16.642226 CA_ADMCK_DIV = 4
585 12:11:16.642394 DQ_TRACK_CA_EN = 0
586 12:11:16.642534 CA_PICK = 800
587 12:11:16.642655 CA_MCKIO = 800
588 12:11:16.644718 MCKIO_SEMI = 0
589 12:11:16.648503 PLL_FREQ = 3068
590 12:11:16.652216 DQ_UI_PI_RATIO = 32
591 12:11:16.652424 CA_UI_PI_RATIO = 0
592 12:11:16.655850 ===================================
593 12:11:16.660239 ===================================
594 12:11:16.663427 memory_type:LPDDR4
595 12:11:16.663610 GP_NUM : 10
596 12:11:16.667489 SRAM_EN : 1
597 12:11:16.667766 MD32_EN : 0
598 12:11:16.671170 ===================================
599 12:11:16.674821 [ANA_INIT] >>>>>>>>>>>>>>
600 12:11:16.678602 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:11:16.682319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:11:16.685958 ===================================
603 12:11:16.686194 data_rate = 1600,PCW = 0X7600
604 12:11:16.689310 ===================================
605 12:11:16.692445 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:11:16.698884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:11:16.706020 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:11:16.709183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:11:16.712394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:11:16.715593 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:11:16.719506 [ANA_INIT] flow start
612 12:11:16.719696 [ANA_INIT] PLL >>>>>>>>
613 12:11:16.722423 [ANA_INIT] PLL <<<<<<<<
614 12:11:16.725880 [ANA_INIT] MIDPI >>>>>>>>
615 12:11:16.728948 [ANA_INIT] MIDPI <<<<<<<<
616 12:11:16.729120 [ANA_INIT] DLL >>>>>>>>
617 12:11:16.732096 [ANA_INIT] flow end
618 12:11:16.735979 ============ LP4 DIFF to SE enter ============
619 12:11:16.738975 ============ LP4 DIFF to SE exit ============
620 12:11:16.742220 [ANA_INIT] <<<<<<<<<<<<<
621 12:11:16.745472 [Flow] Enable top DCM control >>>>>
622 12:11:16.749275 [Flow] Enable top DCM control <<<<<
623 12:11:16.752325 Enable DLL master slave shuffle
624 12:11:16.755494 ==============================================================
625 12:11:16.759298 Gating Mode config
626 12:11:16.766094 ==============================================================
627 12:11:16.766284 Config description:
628 12:11:16.776065 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:11:16.782616 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:11:16.785593 SELPH_MODE 0: By rank 1: By Phase
631 12:11:16.792127 ==============================================================
632 12:11:16.795443 GAT_TRACK_EN = 1
633 12:11:16.799275 RX_GATING_MODE = 2
634 12:11:16.802537 RX_GATING_TRACK_MODE = 2
635 12:11:16.805667 SELPH_MODE = 1
636 12:11:16.808906 PICG_EARLY_EN = 1
637 12:11:16.812653 VALID_LAT_VALUE = 1
638 12:11:16.815833 ==============================================================
639 12:11:16.819086 Enter into Gating configuration >>>>
640 12:11:16.822279 Exit from Gating configuration <<<<
641 12:11:16.825592 Enter into DVFS_PRE_config >>>>>
642 12:11:16.835693 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:11:16.838852 Exit from DVFS_PRE_config <<<<<
644 12:11:16.842635 Enter into PICG configuration >>>>
645 12:11:16.845829 Exit from PICG configuration <<<<
646 12:11:16.848980 [RX_INPUT] configuration >>>>>
647 12:11:16.852815 [RX_INPUT] configuration <<<<<
648 12:11:16.859126 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:11:16.862312 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:11:16.869865 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:11:16.876518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:11:16.883105 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:11:16.886636 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:11:16.893258 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:11:16.896691 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:11:16.899898 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:11:16.903010 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:11:16.906996 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:11:16.913476 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:11:16.916635 ===================================
661 12:11:16.919806 LPDDR4 DRAM CONFIGURATION
662 12:11:16.922950 ===================================
663 12:11:16.923110 EX_ROW_EN[0] = 0x0
664 12:11:16.926942 EX_ROW_EN[1] = 0x0
665 12:11:16.927101 LP4Y_EN = 0x0
666 12:11:16.929997 WORK_FSP = 0x0
667 12:11:16.930155 WL = 0x2
668 12:11:16.933160 RL = 0x2
669 12:11:16.933302 BL = 0x2
670 12:11:16.936319 RPST = 0x0
671 12:11:16.936461 RD_PRE = 0x0
672 12:11:16.940155 WR_PRE = 0x1
673 12:11:16.940306 WR_PST = 0x0
674 12:11:16.943005 DBI_WR = 0x0
675 12:11:16.943136 DBI_RD = 0x0
676 12:11:16.946306 OTF = 0x1
677 12:11:16.949667 ===================================
678 12:11:16.953305 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:11:16.956412 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:11:16.963485 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:11:16.966623 ===================================
682 12:11:16.966798 LPDDR4 DRAM CONFIGURATION
683 12:11:16.969682 ===================================
684 12:11:16.973446 EX_ROW_EN[0] = 0x10
685 12:11:16.976615 EX_ROW_EN[1] = 0x0
686 12:11:16.976793 LP4Y_EN = 0x0
687 12:11:16.979748 WORK_FSP = 0x0
688 12:11:16.979903 WL = 0x2
689 12:11:16.983254 RL = 0x2
690 12:11:16.983426 BL = 0x2
691 12:11:16.986764 RPST = 0x0
692 12:11:16.986924 RD_PRE = 0x0
693 12:11:16.989803 WR_PRE = 0x1
694 12:11:16.989921 WR_PST = 0x0
695 12:11:16.992897 DBI_WR = 0x0
696 12:11:16.993047 DBI_RD = 0x0
697 12:11:16.996511 OTF = 0x1
698 12:11:17.000194 ===================================
699 12:11:17.006212 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:11:17.010136 nWR fixed to 40
701 12:11:17.010334 [ModeRegInit_LP4] CH0 RK0
702 12:11:17.013150 [ModeRegInit_LP4] CH0 RK1
703 12:11:17.016349 [ModeRegInit_LP4] CH1 RK0
704 12:11:17.016511 [ModeRegInit_LP4] CH1 RK1
705 12:11:17.020135 match AC timing 13
706 12:11:17.023409 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:11:17.026577 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:11:17.032990 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:11:17.036868 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:11:17.043110 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:11:17.043288 [EMI DOE] emi_dcm 0
712 12:11:17.046977 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:11:17.050095 ==
714 12:11:17.053208 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:11:17.057053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:11:17.057235 ==
717 12:11:17.060226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:11:17.066695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:11:17.076764 [CA 0] Center 37 (7~68) winsize 62
720 12:11:17.079859 [CA 1] Center 37 (6~68) winsize 63
721 12:11:17.082994 [CA 2] Center 35 (5~66) winsize 62
722 12:11:17.086895 [CA 3] Center 34 (4~65) winsize 62
723 12:11:17.089829 [CA 4] Center 34 (3~65) winsize 63
724 12:11:17.093241 [CA 5] Center 33 (3~64) winsize 62
725 12:11:17.093403
726 12:11:17.096655 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:11:17.096818
728 12:11:17.099638 [CATrainingPosCal] consider 1 rank data
729 12:11:17.103221 u2DelayCellTimex100 = 270/100 ps
730 12:11:17.106868 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 12:11:17.109734 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 12:11:17.116613 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 12:11:17.119772 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 12:11:17.122978 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 12:11:17.126989 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 12:11:17.127207
737 12:11:17.130058 CA PerBit enable=1, Macro0, CA PI delay=33
738 12:11:17.130223
739 12:11:17.133262 [CBTSetCACLKResult] CA Dly = 33
740 12:11:17.133398 CS Dly: 5 (0~36)
741 12:11:17.133514 ==
742 12:11:17.136460 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:11:17.143270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:11:17.143466 ==
745 12:11:17.146485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:11:17.152938 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:11:17.163059 [CA 0] Center 37 (6~68) winsize 63
748 12:11:17.166232 [CA 1] Center 37 (6~68) winsize 63
749 12:11:17.169315 [CA 2] Center 35 (4~66) winsize 63
750 12:11:17.172494 [CA 3] Center 35 (4~66) winsize 63
751 12:11:17.176292 [CA 4] Center 34 (4~65) winsize 62
752 12:11:17.179550 [CA 5] Center 33 (3~64) winsize 62
753 12:11:17.179734
754 12:11:17.182598 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 12:11:17.182749
756 12:11:17.186550 [CATrainingPosCal] consider 2 rank data
757 12:11:17.189432 u2DelayCellTimex100 = 270/100 ps
758 12:11:17.192904 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 12:11:17.196323 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
760 12:11:17.202980 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 12:11:17.205972 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 12:11:17.209597 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
763 12:11:17.212737 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 12:11:17.212925
765 12:11:17.216402 CA PerBit enable=1, Macro0, CA PI delay=33
766 12:11:17.216564
767 12:11:17.219494 [CBTSetCACLKResult] CA Dly = 33
768 12:11:17.219742 CS Dly: 6 (0~38)
769 12:11:17.219904
770 12:11:17.223029 ----->DramcWriteLeveling(PI) begin...
771 12:11:17.223227 ==
772 12:11:17.226237 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:11:17.233793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:11:17.233979 ==
775 12:11:17.234084 Write leveling (Byte 0): 28 => 28
776 12:11:17.237606 Write leveling (Byte 1): 29 => 29
777 12:11:17.241510 DramcWriteLeveling(PI) end<-----
778 12:11:17.241756
779 12:11:17.241933 ==
780 12:11:17.245220 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:11:17.248411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:11:17.248604 ==
783 12:11:17.251570 [Gating] SW mode calibration
784 12:11:17.258426 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:11:17.266096 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:11:17.269348 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:11:17.272670 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 12:11:17.275794 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 12:11:17.282211 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 12:11:17.286047 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:11:17.289207 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:11:17.295624 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:11:17.299568 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:11:17.302672 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:11:17.309797 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:11:17.312634 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:11:17.315592 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:11:17.322743 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:11:17.325616 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:11:17.329187 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:11:17.335667 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:11:17.339428 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:11:17.342444 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:11:17.349217 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 12:11:17.352354 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
806 12:11:17.355489 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:11:17.362398 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:11:17.365661 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:11:17.369368 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:11:17.372595 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:11:17.378857 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:11:17.382821 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
813 12:11:17.385940 0 9 12 | B1->B0 | 2828 3232 | 1 1 | (1 1) (1 1)
814 12:11:17.392376 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:11:17.396191 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:11:17.399142 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:11:17.405657 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:11:17.409471 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:11:17.412670 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 12:11:17.419290 0 10 8 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 1)
821 12:11:17.422845 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
822 12:11:17.425923 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:11:17.432569 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:11:17.435726 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:11:17.439216 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:11:17.445461 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:11:17.449276 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:11:17.452449 0 11 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
829 12:11:17.458969 0 11 12 | B1->B0 | 3737 3f3f | 1 1 | (0 0) (0 0)
830 12:11:17.461970 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:11:17.465751 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:11:17.472122 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:11:17.475379 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:11:17.479174 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:11:17.482272 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:11:17.488855 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 12:11:17.492575 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 12:11:17.495699 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:11:17.502073 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:11:17.505323 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:11:17.509112 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:11:17.515480 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:11:17.518673 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:11:17.522405 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:11:17.528798 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:11:17.531971 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:11:17.535552 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:11:17.542168 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:11:17.545774 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:11:17.548938 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:11:17.555266 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 12:11:17.559111 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 12:11:17.562341 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 12:11:17.565651 Total UI for P1: 0, mck2ui 16
855 12:11:17.569015 best dqsien dly found for B0: ( 0, 14, 6)
856 12:11:17.572386 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 12:11:17.575651 Total UI for P1: 0, mck2ui 16
858 12:11:17.578740 best dqsien dly found for B1: ( 0, 14, 10)
859 12:11:17.582387 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
860 12:11:17.588946 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 12:11:17.589149
862 12:11:17.592156 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 12:11:17.595331 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 12:11:17.598502 [Gating] SW calibration Done
865 12:11:17.598686 ==
866 12:11:17.602272 Dram Type= 6, Freq= 0, CH_0, rank 0
867 12:11:17.605435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 12:11:17.605604 ==
869 12:11:17.608587 RX Vref Scan: 0
870 12:11:17.608767
871 12:11:17.608904 RX Vref 0 -> 0, step: 1
872 12:11:17.609032
873 12:11:17.611921 RX Delay -130 -> 252, step: 16
874 12:11:17.615697 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 12:11:17.622015 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 12:11:17.625200 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 12:11:17.628526 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 12:11:17.632153 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 12:11:17.635143 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 12:11:17.641782 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
881 12:11:17.645395 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
882 12:11:17.648914 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 12:11:17.651991 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 12:11:17.655691 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
885 12:11:17.658713 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 12:11:17.665785 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
887 12:11:17.668823 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
888 12:11:17.672151 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
889 12:11:17.675827 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 12:11:17.675966 ==
891 12:11:17.679114 Dram Type= 6, Freq= 0, CH_0, rank 0
892 12:11:17.685395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 12:11:17.685594 ==
894 12:11:17.685724 DQS Delay:
895 12:11:17.688732 DQS0 = 0, DQS1 = 0
896 12:11:17.688842 DQM Delay:
897 12:11:17.688948 DQM0 = 86, DQM1 = 79
898 12:11:17.692639 DQ Delay:
899 12:11:17.695746 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 12:11:17.698952 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
901 12:11:17.702166 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
902 12:11:17.705299 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
903 12:11:17.705429
904 12:11:17.705534
905 12:11:17.705635 ==
906 12:11:17.709027 Dram Type= 6, Freq= 0, CH_0, rank 0
907 12:11:17.712220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 12:11:17.712368 ==
909 12:11:17.712472
910 12:11:17.712572
911 12:11:17.716035 TX Vref Scan disable
912 12:11:17.716185 == TX Byte 0 ==
913 12:11:17.722496 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
914 12:11:17.725733 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
915 12:11:17.725912 == TX Byte 1 ==
916 12:11:17.732640 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
917 12:11:17.735791 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
918 12:11:17.735967 ==
919 12:11:17.739008 Dram Type= 6, Freq= 0, CH_0, rank 0
920 12:11:17.742676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 12:11:17.742868 ==
922 12:11:17.756276 TX Vref=22, minBit 0, minWin=27, winSum=437
923 12:11:17.759183 TX Vref=24, minBit 0, minWin=27, winSum=443
924 12:11:17.762863 TX Vref=26, minBit 1, minWin=27, winSum=443
925 12:11:17.766138 TX Vref=28, minBit 12, minWin=27, winSum=449
926 12:11:17.769300 TX Vref=30, minBit 2, minWin=28, winSum=456
927 12:11:17.776205 TX Vref=32, minBit 2, minWin=28, winSum=454
928 12:11:17.779445 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 30
929 12:11:17.779636
930 12:11:17.782564 Final TX Range 1 Vref 30
931 12:11:17.782705
932 12:11:17.782813 ==
933 12:11:17.786266 Dram Type= 6, Freq= 0, CH_0, rank 0
934 12:11:17.789484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 12:11:17.789652 ==
936 12:11:17.789759
937 12:11:17.792769
938 12:11:17.792909 TX Vref Scan disable
939 12:11:17.796580 == TX Byte 0 ==
940 12:11:17.799690 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
941 12:11:17.802807 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
942 12:11:17.806034 == TX Byte 1 ==
943 12:11:17.809853 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
944 12:11:17.816233 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
945 12:11:17.816425
946 12:11:17.816535 [DATLAT]
947 12:11:17.816657 Freq=800, CH0 RK0
948 12:11:17.816763
949 12:11:17.819503 DATLAT Default: 0xa
950 12:11:17.819670 0, 0xFFFF, sum = 0
951 12:11:17.823367 1, 0xFFFF, sum = 0
952 12:11:17.823558 2, 0xFFFF, sum = 0
953 12:11:17.825824 3, 0xFFFF, sum = 0
954 12:11:17.825978 4, 0xFFFF, sum = 0
955 12:11:17.829685 5, 0xFFFF, sum = 0
956 12:11:17.832854 6, 0xFFFF, sum = 0
957 12:11:17.832991 7, 0xFFFF, sum = 0
958 12:11:17.836185 8, 0xFFFF, sum = 0
959 12:11:17.836329 9, 0x0, sum = 1
960 12:11:17.836461 10, 0x0, sum = 2
961 12:11:17.839404 11, 0x0, sum = 3
962 12:11:17.839553 12, 0x0, sum = 4
963 12:11:17.842716 best_step = 10
964 12:11:17.842882
965 12:11:17.843001 ==
966 12:11:17.846466 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:11:17.849614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 12:11:17.849791 ==
969 12:11:17.853253 RX Vref Scan: 1
970 12:11:17.853426
971 12:11:17.853534 Set Vref Range= 32 -> 127
972 12:11:17.853633
973 12:11:17.856191 RX Vref 32 -> 127, step: 1
974 12:11:17.856365
975 12:11:17.859835 RX Delay -95 -> 252, step: 8
976 12:11:17.860083
977 12:11:17.862817 Set Vref, RX VrefLevel [Byte0]: 32
978 12:11:17.866283 [Byte1]: 32
979 12:11:17.866460
980 12:11:17.869968 Set Vref, RX VrefLevel [Byte0]: 33
981 12:11:17.873795 [Byte1]: 33
982 12:11:17.873983
983 12:11:17.877092 Set Vref, RX VrefLevel [Byte0]: 34
984 12:11:17.880156 [Byte1]: 34
985 12:11:17.884034
986 12:11:17.884209 Set Vref, RX VrefLevel [Byte0]: 35
987 12:11:17.887216 [Byte1]: 35
988 12:11:17.891730
989 12:11:17.891934 Set Vref, RX VrefLevel [Byte0]: 36
990 12:11:17.894716 [Byte1]: 36
991 12:11:17.899677
992 12:11:17.899876 Set Vref, RX VrefLevel [Byte0]: 37
993 12:11:17.902792 [Byte1]: 37
994 12:11:17.907423
995 12:11:17.907610 Set Vref, RX VrefLevel [Byte0]: 38
996 12:11:17.910443 [Byte1]: 38
997 12:11:17.914823
998 12:11:17.915014 Set Vref, RX VrefLevel [Byte0]: 39
999 12:11:17.918108 [Byte1]: 39
1000 12:11:17.922640
1001 12:11:17.922816 Set Vref, RX VrefLevel [Byte0]: 40
1002 12:11:17.926448 [Byte1]: 40
1003 12:11:17.930257
1004 12:11:17.930428 Set Vref, RX VrefLevel [Byte0]: 41
1005 12:11:17.933468 [Byte1]: 41
1006 12:11:17.937412
1007 12:11:17.937571 Set Vref, RX VrefLevel [Byte0]: 42
1008 12:11:17.940570 [Byte1]: 42
1009 12:11:17.945103
1010 12:11:17.945261 Set Vref, RX VrefLevel [Byte0]: 43
1011 12:11:17.948240 [Byte1]: 43
1012 12:11:17.952677
1013 12:11:17.952831 Set Vref, RX VrefLevel [Byte0]: 44
1014 12:11:17.955848 [Byte1]: 44
1015 12:11:17.959937
1016 12:11:17.960099 Set Vref, RX VrefLevel [Byte0]: 45
1017 12:11:17.963416 [Byte1]: 45
1018 12:11:17.967430
1019 12:11:17.967649 Set Vref, RX VrefLevel [Byte0]: 46
1020 12:11:17.970870 [Byte1]: 46
1021 12:11:17.975125
1022 12:11:17.975290 Set Vref, RX VrefLevel [Byte0]: 47
1023 12:11:17.978868 [Byte1]: 47
1024 12:11:17.982653
1025 12:11:17.982805 Set Vref, RX VrefLevel [Byte0]: 48
1026 12:11:17.985867 [Byte1]: 48
1027 12:11:17.990243
1028 12:11:17.990400 Set Vref, RX VrefLevel [Byte0]: 49
1029 12:11:17.994080 [Byte1]: 49
1030 12:11:17.997907
1031 12:11:17.998058 Set Vref, RX VrefLevel [Byte0]: 50
1032 12:11:18.001646 [Byte1]: 50
1033 12:11:18.005413
1034 12:11:18.005595 Set Vref, RX VrefLevel [Byte0]: 51
1035 12:11:18.008723 [Byte1]: 51
1036 12:11:18.012996
1037 12:11:18.013188 Set Vref, RX VrefLevel [Byte0]: 52
1038 12:11:18.016705 [Byte1]: 52
1039 12:11:18.020593
1040 12:11:18.020741 Set Vref, RX VrefLevel [Byte0]: 53
1041 12:11:18.023795 [Byte1]: 53
1042 12:11:18.028335
1043 12:11:18.028490 Set Vref, RX VrefLevel [Byte0]: 54
1044 12:11:18.031687 [Byte1]: 54
1045 12:11:18.036143
1046 12:11:18.036296 Set Vref, RX VrefLevel [Byte0]: 55
1047 12:11:18.039400 [Byte1]: 55
1048 12:11:18.043896
1049 12:11:18.044094 Set Vref, RX VrefLevel [Byte0]: 56
1050 12:11:18.047076 [Byte1]: 56
1051 12:11:18.050919
1052 12:11:18.051059 Set Vref, RX VrefLevel [Byte0]: 57
1053 12:11:18.054175 [Byte1]: 57
1054 12:11:18.058681
1055 12:11:18.058829 Set Vref, RX VrefLevel [Byte0]: 58
1056 12:11:18.061846 [Byte1]: 58
1057 12:11:18.066615
1058 12:11:18.066764 Set Vref, RX VrefLevel [Byte0]: 59
1059 12:11:18.069412 [Byte1]: 59
1060 12:11:18.073744
1061 12:11:18.073882 Set Vref, RX VrefLevel [Byte0]: 60
1062 12:11:18.077300 [Byte1]: 60
1063 12:11:18.081374
1064 12:11:18.081514 Set Vref, RX VrefLevel [Byte0]: 61
1065 12:11:18.085087 [Byte1]: 61
1066 12:11:18.089450
1067 12:11:18.089625 Set Vref, RX VrefLevel [Byte0]: 62
1068 12:11:18.092441 [Byte1]: 62
1069 12:11:18.096365
1070 12:11:18.100353 Set Vref, RX VrefLevel [Byte0]: 63
1071 12:11:18.103155 [Byte1]: 63
1072 12:11:18.103286
1073 12:11:18.106407 Set Vref, RX VrefLevel [Byte0]: 64
1074 12:11:18.109662 [Byte1]: 64
1075 12:11:18.109795
1076 12:11:18.113522 Set Vref, RX VrefLevel [Byte0]: 65
1077 12:11:18.116681 [Byte1]: 65
1078 12:11:18.116834
1079 12:11:18.119876 Set Vref, RX VrefLevel [Byte0]: 66
1080 12:11:18.123132 [Byte1]: 66
1081 12:11:18.126961
1082 12:11:18.127107 Set Vref, RX VrefLevel [Byte0]: 67
1083 12:11:18.133312 [Byte1]: 67
1084 12:11:18.133475
1085 12:11:18.137072 Set Vref, RX VrefLevel [Byte0]: 68
1086 12:11:18.140266 [Byte1]: 68
1087 12:11:18.140407
1088 12:11:18.143395 Set Vref, RX VrefLevel [Byte0]: 69
1089 12:11:18.146544 [Byte1]: 69
1090 12:11:18.146659
1091 12:11:18.150428 Set Vref, RX VrefLevel [Byte0]: 70
1092 12:11:18.153664 [Byte1]: 70
1093 12:11:18.157546
1094 12:11:18.157704 Set Vref, RX VrefLevel [Byte0]: 71
1095 12:11:18.160811 [Byte1]: 71
1096 12:11:18.165240
1097 12:11:18.165410 Set Vref, RX VrefLevel [Byte0]: 72
1098 12:11:18.168479 [Byte1]: 72
1099 12:11:18.172797
1100 12:11:18.172922 Set Vref, RX VrefLevel [Byte0]: 73
1101 12:11:18.175752 [Byte1]: 73
1102 12:11:18.180517
1103 12:11:18.180687 Set Vref, RX VrefLevel [Byte0]: 74
1104 12:11:18.183635 [Byte1]: 74
1105 12:11:18.187770
1106 12:11:18.187906 Set Vref, RX VrefLevel [Byte0]: 75
1107 12:11:18.191370 [Byte1]: 75
1108 12:11:18.195677
1109 12:11:18.195914 Set Vref, RX VrefLevel [Byte0]: 76
1110 12:11:18.198712 [Byte1]: 76
1111 12:11:18.203102
1112 12:11:18.203280 Final RX Vref Byte 0 = 61 to rank0
1113 12:11:18.206200 Final RX Vref Byte 1 = 56 to rank0
1114 12:11:18.209987 Final RX Vref Byte 0 = 61 to rank1
1115 12:11:18.213223 Final RX Vref Byte 1 = 56 to rank1==
1116 12:11:18.216455 Dram Type= 6, Freq= 0, CH_0, rank 0
1117 12:11:18.223335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1118 12:11:18.223515 ==
1119 12:11:18.223624 DQS Delay:
1120 12:11:18.223723 DQS0 = 0, DQS1 = 0
1121 12:11:18.226591 DQM Delay:
1122 12:11:18.226710 DQM0 = 87, DQM1 = 79
1123 12:11:18.229791 DQ Delay:
1124 12:11:18.232953 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1125 12:11:18.236193 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1126 12:11:18.239594 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1127 12:11:18.243131 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1128 12:11:18.243291
1129 12:11:18.243466
1130 12:11:18.249632 [DQSOSCAuto] RK0, (LSB)MR18= 0x260d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1131 12:11:18.252801 CH0 RK0: MR19=606, MR18=260D
1132 12:11:18.259891 CH0_RK0: MR19=0x606, MR18=0x260D, DQSOSC=400, MR23=63, INC=92, DEC=61
1133 12:11:18.260040
1134 12:11:18.263073 ----->DramcWriteLeveling(PI) begin...
1135 12:11:18.263219 ==
1136 12:11:18.266168 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 12:11:18.269245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 12:11:18.269406 ==
1139 12:11:18.273055 Write leveling (Byte 0): 29 => 29
1140 12:11:18.276138 Write leveling (Byte 1): 28 => 28
1141 12:11:18.279914 DramcWriteLeveling(PI) end<-----
1142 12:11:18.280066
1143 12:11:18.280201 ==
1144 12:11:18.282819 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 12:11:18.286499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 12:11:18.286689 ==
1147 12:11:18.289659 [Gating] SW mode calibration
1148 12:11:18.296215 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1149 12:11:18.302609 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1150 12:11:18.306260 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 12:11:18.309483 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 12:11:18.353294 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1153 12:11:18.353706 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1154 12:11:18.353829 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:11:18.353948 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:11:18.354063 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:11:18.354167 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:11:18.354258 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:11:18.354392 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:11:18.354489 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:11:18.354593 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:11:18.397703 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:11:18.398117 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:11:18.398246 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:11:18.398368 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:11:18.398470 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 12:11:18.398597 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1168 12:11:18.398702 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1169 12:11:18.398794 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:11:18.398893 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:11:18.398982 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:11:18.439913 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:11:18.440303 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:11:18.440437 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:11:18.440559 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:11:18.440656 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
1177 12:11:18.440756 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 12:11:18.440863 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 12:11:18.440991 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 12:11:18.443773 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 12:11:18.443893 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:11:18.447569 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:11:18.450782 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
1184 12:11:18.457047 0 10 8 | B1->B0 | 3030 2727 | 1 1 | (1 1) (1 0)
1185 12:11:18.460833 0 10 12 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
1186 12:11:18.464064 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:11:18.470581 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:11:18.473775 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:11:18.477503 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:11:18.481250 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:11:18.488216 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1192 12:11:18.492106 0 11 8 | B1->B0 | 2929 4141 | 0 0 | (0 0) (1 1)
1193 12:11:18.495182 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1194 12:11:18.498377 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 12:11:18.505333 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 12:11:18.508560 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 12:11:18.511965 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:11:18.518715 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1199 12:11:18.522068 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1200 12:11:18.525801 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1201 12:11:18.528905 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1202 12:11:18.535293 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:11:18.539022 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:11:18.542252 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:11:18.548614 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:11:18.552569 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:11:18.555609 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:11:18.561979 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:11:18.565211 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:11:18.569030 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:11:18.575721 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:11:18.578732 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:11:18.582411 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:11:18.588793 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:11:18.592097 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1216 12:11:18.595234 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1217 12:11:18.598944 Total UI for P1: 0, mck2ui 16
1218 12:11:18.602115 best dqsien dly found for B0: ( 0, 14, 4)
1219 12:11:18.608779 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 12:11:18.608941 Total UI for P1: 0, mck2ui 16
1221 12:11:18.612306 best dqsien dly found for B1: ( 0, 14, 8)
1222 12:11:18.618952 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1223 12:11:18.622335 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1224 12:11:18.622476
1225 12:11:18.625198 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1226 12:11:18.628846 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1227 12:11:18.632218 [Gating] SW calibration Done
1228 12:11:18.632373 ==
1229 12:11:18.635705 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 12:11:18.638858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 12:11:18.639045 ==
1232 12:11:18.641971 RX Vref Scan: 0
1233 12:11:18.642092
1234 12:11:18.642201 RX Vref 0 -> 0, step: 1
1235 12:11:18.642294
1236 12:11:18.645113 RX Delay -130 -> 252, step: 16
1237 12:11:18.648766 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1238 12:11:18.651986 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1239 12:11:18.658947 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1240 12:11:18.662130 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1241 12:11:18.665312 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1242 12:11:18.669075 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1243 12:11:18.672288 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1244 12:11:18.678687 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1245 12:11:18.681868 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1246 12:11:18.685678 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1247 12:11:18.688846 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1248 12:11:18.691941 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1249 12:11:18.698799 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1250 12:11:18.702037 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1251 12:11:18.705255 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1252 12:11:18.708902 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1253 12:11:18.709064 ==
1254 12:11:18.712047 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 12:11:18.718709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 12:11:18.718902 ==
1257 12:11:18.719014 DQS Delay:
1258 12:11:18.722171 DQS0 = 0, DQS1 = 0
1259 12:11:18.722306 DQM Delay:
1260 12:11:18.722404 DQM0 = 86, DQM1 = 76
1261 12:11:18.725637 DQ Delay:
1262 12:11:18.728607 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1263 12:11:18.732256 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1264 12:11:18.735234 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1265 12:11:18.739003 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1266 12:11:18.739158
1267 12:11:18.739260
1268 12:11:18.739361 ==
1269 12:11:18.742007 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 12:11:18.745713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 12:11:18.745882 ==
1272 12:11:18.745995
1273 12:11:18.746090
1274 12:11:18.748862 TX Vref Scan disable
1275 12:11:18.749010 == TX Byte 0 ==
1276 12:11:18.755211 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1277 12:11:18.759009 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1278 12:11:18.759185 == TX Byte 1 ==
1279 12:11:18.765332 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1280 12:11:18.768565 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1281 12:11:18.768690 ==
1282 12:11:18.772395 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 12:11:18.775650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 12:11:18.775803 ==
1285 12:11:18.789474 TX Vref=22, minBit 2, minWin=27, winSum=440
1286 12:11:18.792787 TX Vref=24, minBit 0, minWin=27, winSum=446
1287 12:11:18.796597 TX Vref=26, minBit 3, minWin=27, winSum=451
1288 12:11:18.799795 TX Vref=28, minBit 9, minWin=27, winSum=453
1289 12:11:18.802958 TX Vref=30, minBit 3, minWin=27, winSum=453
1290 12:11:18.806084 TX Vref=32, minBit 0, minWin=28, winSum=455
1291 12:11:18.813202 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 32
1292 12:11:18.813392
1293 12:11:18.816454 Final TX Range 1 Vref 32
1294 12:11:18.816714
1295 12:11:18.816917 ==
1296 12:11:18.819579 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 12:11:18.822755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 12:11:18.822958 ==
1299 12:11:18.823092
1300 12:11:18.823251
1301 12:11:18.826237 TX Vref Scan disable
1302 12:11:18.829886 == TX Byte 0 ==
1303 12:11:18.832799 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1304 12:11:18.836315 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1305 12:11:18.839763 == TX Byte 1 ==
1306 12:11:18.842680 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1307 12:11:18.846521 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1308 12:11:18.846668
1309 12:11:18.849581 [DATLAT]
1310 12:11:18.849724 Freq=800, CH0 RK1
1311 12:11:18.849837
1312 12:11:18.852615 DATLAT Default: 0xa
1313 12:11:18.852737 0, 0xFFFF, sum = 0
1314 12:11:18.856142 1, 0xFFFF, sum = 0
1315 12:11:18.856307 2, 0xFFFF, sum = 0
1316 12:11:18.859887 3, 0xFFFF, sum = 0
1317 12:11:18.860062 4, 0xFFFF, sum = 0
1318 12:11:18.863088 5, 0xFFFF, sum = 0
1319 12:11:18.863217 6, 0xFFFF, sum = 0
1320 12:11:18.866250 7, 0xFFFF, sum = 0
1321 12:11:18.866373 8, 0xFFFF, sum = 0
1322 12:11:18.869433 9, 0x0, sum = 1
1323 12:11:18.869572 10, 0x0, sum = 2
1324 12:11:18.872702 11, 0x0, sum = 3
1325 12:11:18.872827 12, 0x0, sum = 4
1326 12:11:18.876063 best_step = 10
1327 12:11:18.876210
1328 12:11:18.876307 ==
1329 12:11:18.879786 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 12:11:18.882810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 12:11:18.882979 ==
1332 12:11:18.885975 RX Vref Scan: 0
1333 12:11:18.886108
1334 12:11:18.886231 RX Vref 0 -> 0, step: 1
1335 12:11:18.886323
1336 12:11:18.889753 RX Delay -95 -> 252, step: 8
1337 12:11:18.896135 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1338 12:11:18.899221 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1339 12:11:18.903085 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1340 12:11:18.906297 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1341 12:11:18.909433 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1342 12:11:18.916480 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1343 12:11:18.919714 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1344 12:11:18.922809 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1345 12:11:18.926044 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1346 12:11:18.929780 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1347 12:11:18.935809 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1348 12:11:18.939696 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1349 12:11:18.942578 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1350 12:11:18.946096 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1351 12:11:18.949616 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1352 12:11:18.956320 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1353 12:11:18.956539 ==
1354 12:11:18.959196 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 12:11:18.962672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 12:11:18.962823 ==
1357 12:11:18.962933 DQS Delay:
1358 12:11:18.966398 DQS0 = 0, DQS1 = 0
1359 12:11:18.966536 DQM Delay:
1360 12:11:18.969455 DQM0 = 87, DQM1 = 77
1361 12:11:18.969590 DQ Delay:
1362 12:11:18.972761 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1363 12:11:18.975974 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1364 12:11:18.979101 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1365 12:11:18.982985 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1366 12:11:18.983155
1367 12:11:18.983277
1368 12:11:18.989311 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1369 12:11:18.993172 CH0 RK1: MR19=606, MR18=2D15
1370 12:11:18.999539 CH0_RK1: MR19=0x606, MR18=0x2D15, DQSOSC=398, MR23=63, INC=93, DEC=62
1371 12:11:19.002594 [RxdqsGatingPostProcess] freq 800
1372 12:11:19.009019 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 12:11:19.012843 Pre-setting of DQS Precalculation
1374 12:11:19.016072 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 12:11:19.016285 ==
1376 12:11:19.019265 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 12:11:19.022377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 12:11:19.022527 ==
1379 12:11:19.029289 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 12:11:19.035825 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 12:11:19.044082 [CA 0] Center 36 (6~66) winsize 61
1382 12:11:19.047609 [CA 1] Center 36 (6~66) winsize 61
1383 12:11:19.050619 [CA 2] Center 35 (5~65) winsize 61
1384 12:11:19.054277 [CA 3] Center 33 (3~64) winsize 62
1385 12:11:19.057246 [CA 4] Center 34 (4~65) winsize 62
1386 12:11:19.060909 [CA 5] Center 33 (3~64) winsize 62
1387 12:11:19.061056
1388 12:11:19.064467 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1389 12:11:19.064628
1390 12:11:19.067307 [CATrainingPosCal] consider 1 rank data
1391 12:11:19.070902 u2DelayCellTimex100 = 270/100 ps
1392 12:11:19.074078 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1393 12:11:19.077297 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1394 12:11:19.084260 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1395 12:11:19.087446 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 12:11:19.090655 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1397 12:11:19.093975 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1398 12:11:19.094106
1399 12:11:19.097634 CA PerBit enable=1, Macro0, CA PI delay=33
1400 12:11:19.097784
1401 12:11:19.100958 [CBTSetCACLKResult] CA Dly = 33
1402 12:11:19.101115 CS Dly: 5 (0~36)
1403 12:11:19.104081 ==
1404 12:11:19.104240 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 12:11:19.110988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 12:11:19.111174 ==
1407 12:11:19.114101 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 12:11:19.121100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 12:11:19.130101 [CA 0] Center 36 (6~66) winsize 61
1410 12:11:19.134004 [CA 1] Center 36 (6~66) winsize 61
1411 12:11:19.137056 [CA 2] Center 34 (4~65) winsize 62
1412 12:11:19.140341 [CA 3] Center 33 (3~64) winsize 62
1413 12:11:19.144002 [CA 4] Center 34 (4~65) winsize 62
1414 12:11:19.147159 [CA 5] Center 33 (3~64) winsize 62
1415 12:11:19.147302
1416 12:11:19.150931 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1417 12:11:19.151105
1418 12:11:19.154437 [CATrainingPosCal] consider 2 rank data
1419 12:11:19.157888 u2DelayCellTimex100 = 270/100 ps
1420 12:11:19.161902 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1421 12:11:19.165477 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1422 12:11:19.169141 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1423 12:11:19.172879 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1424 12:11:19.176735 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1425 12:11:19.180736 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1426 12:11:19.180912
1427 12:11:19.183916 CA PerBit enable=1, Macro0, CA PI delay=33
1428 12:11:19.184065
1429 12:11:19.187134 [CBTSetCACLKResult] CA Dly = 33
1430 12:11:19.187269 CS Dly: 5 (0~36)
1431 12:11:19.187384
1432 12:11:19.190325 ----->DramcWriteLeveling(PI) begin...
1433 12:11:19.194022 ==
1434 12:11:19.194170 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 12:11:19.200310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 12:11:19.200475 ==
1437 12:11:19.203554 Write leveling (Byte 0): 25 => 25
1438 12:11:19.207324 Write leveling (Byte 1): 26 => 26
1439 12:11:19.210541 DramcWriteLeveling(PI) end<-----
1440 12:11:19.210682
1441 12:11:19.210783 ==
1442 12:11:19.213739 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 12:11:19.216895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 12:11:19.217043 ==
1445 12:11:19.220163 [Gating] SW mode calibration
1446 12:11:19.227224 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 12:11:19.230365 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 12:11:19.237316 0 6 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 1)
1449 12:11:19.240550 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 12:11:19.243622 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1451 12:11:19.250968 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1452 12:11:19.253987 0 6 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1453 12:11:19.257092 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:11:19.263625 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:11:19.267084 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:11:19.270237 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:11:19.276853 0 7 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1458 12:11:19.280467 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:11:19.283566 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1460 12:11:19.290119 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:11:19.294063 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:11:19.297087 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1463 12:11:19.304147 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1464 12:11:19.307232 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1465 12:11:19.310427 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1466 12:11:19.313462 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 1)
1467 12:11:19.320478 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:11:19.323648 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1469 12:11:19.326884 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:11:19.333814 0 8 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1471 12:11:19.336991 0 8 28 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1472 12:11:19.340852 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:11:19.347069 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:11:19.350291 0 9 8 | B1->B0 | 2a2a 2c2c | 1 1 | (1 1) (1 1)
1475 12:11:19.354057 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1476 12:11:19.360424 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1477 12:11:19.363996 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1478 12:11:19.367276 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 12:11:19.373846 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1480 12:11:19.376982 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:11:19.380627 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1482 12:11:19.387088 0 10 8 | B1->B0 | 2d2d 2e2e | 1 1 | (1 0) (1 0)
1483 12:11:19.390776 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:11:19.393800 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1485 12:11:19.397363 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:11:19.403762 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1487 12:11:19.407626 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:11:19.410780 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:11:19.417775 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:11:19.420930 0 11 8 | B1->B0 | 3131 3131 | 0 0 | (0 0) (0 0)
1491 12:11:19.424044 0 11 12 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
1492 12:11:19.430717 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 12:11:19.433839 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 12:11:19.437642 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 12:11:19.444044 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:11:19.447825 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:11:19.451046 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:11:19.454203 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1499 12:11:19.461104 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1500 12:11:19.464236 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:11:19.467440 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:11:19.474463 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:11:19.477781 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:11:19.480532 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:11:19.487269 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:11:19.490924 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:11:19.494490 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:11:19.501028 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:11:19.503925 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:11:19.507130 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:11:19.514092 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:11:19.517830 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:11:19.521005 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1514 12:11:19.527305 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1515 12:11:19.531121 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 12:11:19.534353 Total UI for P1: 0, mck2ui 16
1517 12:11:19.537538 best dqsien dly found for B0: ( 0, 14, 6)
1518 12:11:19.540620 Total UI for P1: 0, mck2ui 16
1519 12:11:19.543831 best dqsien dly found for B1: ( 0, 14, 6)
1520 12:11:19.547061 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1521 12:11:19.550760 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1522 12:11:19.550902
1523 12:11:19.553979 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 12:11:19.557184 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 12:11:19.560341 [Gating] SW calibration Done
1526 12:11:19.560473 ==
1527 12:11:19.564132 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 12:11:19.567193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 12:11:19.567333 ==
1530 12:11:19.570397 RX Vref Scan: 0
1531 12:11:19.570520
1532 12:11:19.574121 RX Vref 0 -> 0, step: 1
1533 12:11:19.574241
1534 12:11:19.574355 RX Delay -130 -> 252, step: 16
1535 12:11:19.580561 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1536 12:11:19.583634 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1537 12:11:19.587321 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1538 12:11:19.590395 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1539 12:11:19.593919 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1540 12:11:19.600671 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1541 12:11:19.604131 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1542 12:11:19.607083 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1543 12:11:19.610566 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1544 12:11:19.613604 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1545 12:11:19.620796 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1546 12:11:19.623927 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1547 12:11:19.627085 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1548 12:11:19.630398 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1549 12:11:19.637430 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1550 12:11:19.640350 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1551 12:11:19.640458 ==
1552 12:11:19.643655 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 12:11:19.646838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 12:11:19.646979 ==
1555 12:11:19.647079 DQS Delay:
1556 12:11:19.650073 DQS0 = 0, DQS1 = 0
1557 12:11:19.650169 DQM Delay:
1558 12:11:19.653828 DQM0 = 85, DQM1 = 77
1559 12:11:19.653954 DQ Delay:
1560 12:11:19.657072 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1561 12:11:19.660226 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1562 12:11:19.663893 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1563 12:11:19.667110 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1564 12:11:19.667237
1565 12:11:19.667374
1566 12:11:19.667446 ==
1567 12:11:19.670284 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 12:11:19.673375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 12:11:19.677251 ==
1570 12:11:19.677359
1571 12:11:19.677441
1572 12:11:19.677518 TX Vref Scan disable
1573 12:11:19.680552 == TX Byte 0 ==
1574 12:11:19.683708 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1575 12:11:19.686946 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1576 12:11:19.690162 == TX Byte 1 ==
1577 12:11:19.693986 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1578 12:11:19.697107 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1579 12:11:19.700141 ==
1580 12:11:19.703660 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 12:11:19.706761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 12:11:19.706900 ==
1583 12:11:19.718825 TX Vref=22, minBit 4, minWin=26, winSum=435
1584 12:11:19.722344 TX Vref=24, minBit 1, minWin=27, winSum=440
1585 12:11:19.725711 TX Vref=26, minBit 4, minWin=27, winSum=442
1586 12:11:19.729555 TX Vref=28, minBit 4, minWin=27, winSum=447
1587 12:11:19.733283 TX Vref=30, minBit 0, minWin=28, winSum=449
1588 12:11:19.736360 TX Vref=32, minBit 11, minWin=27, winSum=449
1589 12:11:19.743266 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 30
1590 12:11:19.743465
1591 12:11:19.746558 Final TX Range 1 Vref 30
1592 12:11:19.746701
1593 12:11:19.746807 ==
1594 12:11:19.749716 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 12:11:19.752759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 12:11:19.752916 ==
1597 12:11:19.753044
1598 12:11:19.753188
1599 12:11:19.756559 TX Vref Scan disable
1600 12:11:19.759685 == TX Byte 0 ==
1601 12:11:19.762811 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1602 12:11:19.765913 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1603 12:11:19.769691 == TX Byte 1 ==
1604 12:11:19.772855 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1605 12:11:19.776076 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1606 12:11:19.776265
1607 12:11:19.779845 [DATLAT]
1608 12:11:19.780006 Freq=800, CH1 RK0
1609 12:11:19.780111
1610 12:11:19.783066 DATLAT Default: 0xa
1611 12:11:19.783218 0, 0xFFFF, sum = 0
1612 12:11:19.786205 1, 0xFFFF, sum = 0
1613 12:11:19.786342 2, 0xFFFF, sum = 0
1614 12:11:19.789443 3, 0xFFFF, sum = 0
1615 12:11:19.789585 4, 0xFFFF, sum = 0
1616 12:11:19.792976 5, 0xFFFF, sum = 0
1617 12:11:19.793111 6, 0xFFFF, sum = 0
1618 12:11:19.796369 7, 0xFFFF, sum = 0
1619 12:11:19.796506 8, 0xFFFF, sum = 0
1620 12:11:19.799626 9, 0x0, sum = 1
1621 12:11:19.799771 10, 0x0, sum = 2
1622 12:11:19.802747 11, 0x0, sum = 3
1623 12:11:19.802894 12, 0x0, sum = 4
1624 12:11:19.806372 best_step = 10
1625 12:11:19.806512
1626 12:11:19.806610 ==
1627 12:11:19.809476 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 12:11:19.813019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 12:11:19.813149 ==
1630 12:11:19.815946 RX Vref Scan: 1
1631 12:11:19.816125
1632 12:11:19.816264 Set Vref Range= 32 -> 127
1633 12:11:19.816395
1634 12:11:19.819644 RX Vref 32 -> 127, step: 1
1635 12:11:19.819815
1636 12:11:19.822633 RX Delay -95 -> 252, step: 8
1637 12:11:19.822784
1638 12:11:19.826108 Set Vref, RX VrefLevel [Byte0]: 32
1639 12:11:19.829323 [Byte1]: 32
1640 12:11:19.829486
1641 12:11:19.833227 Set Vref, RX VrefLevel [Byte0]: 33
1642 12:11:19.836334 [Byte1]: 33
1643 12:11:19.836506
1644 12:11:19.839405 Set Vref, RX VrefLevel [Byte0]: 34
1645 12:11:19.842576 [Byte1]: 34
1646 12:11:19.847101
1647 12:11:19.847297 Set Vref, RX VrefLevel [Byte0]: 35
1648 12:11:19.850286 [Byte1]: 35
1649 12:11:19.854283
1650 12:11:19.854457 Set Vref, RX VrefLevel [Byte0]: 36
1651 12:11:19.857992 [Byte1]: 36
1652 12:11:19.862349
1653 12:11:19.862528 Set Vref, RX VrefLevel [Byte0]: 37
1654 12:11:19.865537 [Byte1]: 37
1655 12:11:19.869375
1656 12:11:19.873150 Set Vref, RX VrefLevel [Byte0]: 38
1657 12:11:19.873323 [Byte1]: 38
1658 12:11:19.877586
1659 12:11:19.877763 Set Vref, RX VrefLevel [Byte0]: 39
1660 12:11:19.880718 [Byte1]: 39
1661 12:11:19.885179
1662 12:11:19.885377 Set Vref, RX VrefLevel [Byte0]: 40
1663 12:11:19.888386 [Byte1]: 40
1664 12:11:19.892685
1665 12:11:19.892872 Set Vref, RX VrefLevel [Byte0]: 41
1666 12:11:19.895811 [Byte1]: 41
1667 12:11:19.900425
1668 12:11:19.900678 Set Vref, RX VrefLevel [Byte0]: 42
1669 12:11:19.906700 [Byte1]: 42
1670 12:11:19.906889
1671 12:11:19.909766 Set Vref, RX VrefLevel [Byte0]: 43
1672 12:11:19.913445 [Byte1]: 43
1673 12:11:19.913609
1674 12:11:19.916886 Set Vref, RX VrefLevel [Byte0]: 44
1675 12:11:19.919804 [Byte1]: 44
1676 12:11:19.919954
1677 12:11:19.922941 Set Vref, RX VrefLevel [Byte0]: 45
1678 12:11:19.926611 [Byte1]: 45
1679 12:11:19.930658
1680 12:11:19.930851 Set Vref, RX VrefLevel [Byte0]: 46
1681 12:11:19.934147 [Byte1]: 46
1682 12:11:19.938044
1683 12:11:19.938192 Set Vref, RX VrefLevel [Byte0]: 47
1684 12:11:19.941236 [Byte1]: 47
1685 12:11:19.945493
1686 12:11:19.945622 Set Vref, RX VrefLevel [Byte0]: 48
1687 12:11:19.949618 [Byte1]: 48
1688 12:11:19.953075
1689 12:11:19.953233 Set Vref, RX VrefLevel [Byte0]: 49
1690 12:11:19.956428 [Byte1]: 49
1691 12:11:19.960762
1692 12:11:19.960942 Set Vref, RX VrefLevel [Byte0]: 50
1693 12:11:19.964582 [Byte1]: 50
1694 12:11:19.968324
1695 12:11:19.968441 Set Vref, RX VrefLevel [Byte0]: 51
1696 12:11:19.972115 [Byte1]: 51
1697 12:11:19.975780
1698 12:11:19.975922 Set Vref, RX VrefLevel [Byte0]: 52
1699 12:11:19.979662 [Byte1]: 52
1700 12:11:19.983442
1701 12:11:19.983588 Set Vref, RX VrefLevel [Byte0]: 53
1702 12:11:19.987371 [Byte1]: 53
1703 12:11:19.991127
1704 12:11:19.991259 Set Vref, RX VrefLevel [Byte0]: 54
1705 12:11:19.994893 [Byte1]: 54
1706 12:11:19.998813
1707 12:11:19.998962 Set Vref, RX VrefLevel [Byte0]: 55
1708 12:11:20.001914 [Byte1]: 55
1709 12:11:20.006296
1710 12:11:20.006464 Set Vref, RX VrefLevel [Byte0]: 56
1711 12:11:20.010242 [Byte1]: 56
1712 12:11:20.013919
1713 12:11:20.014050 Set Vref, RX VrefLevel [Byte0]: 57
1714 12:11:20.017715 [Byte1]: 57
1715 12:11:20.021440
1716 12:11:20.021588 Set Vref, RX VrefLevel [Byte0]: 58
1717 12:11:20.024942 [Byte1]: 58
1718 12:11:20.029010
1719 12:11:20.029167 Set Vref, RX VrefLevel [Byte0]: 59
1720 12:11:20.032870 [Byte1]: 59
1721 12:11:20.036743
1722 12:11:20.036892 Set Vref, RX VrefLevel [Byte0]: 60
1723 12:11:20.040466 [Byte1]: 60
1724 12:11:20.044726
1725 12:11:20.044862 Set Vref, RX VrefLevel [Byte0]: 61
1726 12:11:20.047849 [Byte1]: 61
1727 12:11:20.052271
1728 12:11:20.052406 Set Vref, RX VrefLevel [Byte0]: 62
1729 12:11:20.055534 [Byte1]: 62
1730 12:11:20.059977
1731 12:11:20.060113 Set Vref, RX VrefLevel [Byte0]: 63
1732 12:11:20.063086 [Byte1]: 63
1733 12:11:20.066987
1734 12:11:20.067128 Set Vref, RX VrefLevel [Byte0]: 64
1735 12:11:20.070754 [Byte1]: 64
1736 12:11:20.074531
1737 12:11:20.074683 Set Vref, RX VrefLevel [Byte0]: 65
1738 12:11:20.078323 [Byte1]: 65
1739 12:11:20.082771
1740 12:11:20.082921 Set Vref, RX VrefLevel [Byte0]: 66
1741 12:11:20.085839 [Byte1]: 66
1742 12:11:20.090417
1743 12:11:20.090553 Set Vref, RX VrefLevel [Byte0]: 67
1744 12:11:20.093545 [Byte1]: 67
1745 12:11:20.097936
1746 12:11:20.098072 Set Vref, RX VrefLevel [Byte0]: 68
1747 12:11:20.101209 [Byte1]: 68
1748 12:11:20.105633
1749 12:11:20.105803 Set Vref, RX VrefLevel [Byte0]: 69
1750 12:11:20.108762 [Byte1]: 69
1751 12:11:20.112672
1752 12:11:20.112830 Set Vref, RX VrefLevel [Byte0]: 70
1753 12:11:20.116431 [Byte1]: 70
1754 12:11:20.120271
1755 12:11:20.120418 Set Vref, RX VrefLevel [Byte0]: 71
1756 12:11:20.123649 [Byte1]: 71
1757 12:11:20.127892
1758 12:11:20.128033 Set Vref, RX VrefLevel [Byte0]: 72
1759 12:11:20.131173 [Byte1]: 72
1760 12:11:20.135676
1761 12:11:20.135824 Set Vref, RX VrefLevel [Byte0]: 73
1762 12:11:20.138712 [Byte1]: 73
1763 12:11:20.143445
1764 12:11:20.143600 Set Vref, RX VrefLevel [Byte0]: 74
1765 12:11:20.146565 [Byte1]: 74
1766 12:11:20.150683
1767 12:11:20.150824 Set Vref, RX VrefLevel [Byte0]: 75
1768 12:11:20.154342 [Byte1]: 75
1769 12:11:20.158345
1770 12:11:20.158469 Set Vref, RX VrefLevel [Byte0]: 76
1771 12:11:20.162061 [Byte1]: 76
1772 12:11:20.165816
1773 12:11:20.165980 Set Vref, RX VrefLevel [Byte0]: 77
1774 12:11:20.169659 [Byte1]: 77
1775 12:11:20.173417
1776 12:11:20.173563 Set Vref, RX VrefLevel [Byte0]: 78
1777 12:11:20.176680 [Byte1]: 78
1778 12:11:20.180934
1779 12:11:20.181079 Set Vref, RX VrefLevel [Byte0]: 79
1780 12:11:20.184718 [Byte1]: 79
1781 12:11:20.189095
1782 12:11:20.189242 Set Vref, RX VrefLevel [Byte0]: 80
1783 12:11:20.192194 [Byte1]: 80
1784 12:11:20.196691
1785 12:11:20.196846 Final RX Vref Byte 0 = 61 to rank0
1786 12:11:20.199805 Final RX Vref Byte 1 = 58 to rank0
1787 12:11:20.202956 Final RX Vref Byte 0 = 61 to rank1
1788 12:11:20.206595 Final RX Vref Byte 1 = 58 to rank1==
1789 12:11:20.209855 Dram Type= 6, Freq= 0, CH_1, rank 0
1790 12:11:20.216801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 12:11:20.216988 ==
1792 12:11:20.217097 DQS Delay:
1793 12:11:20.217190 DQS0 = 0, DQS1 = 0
1794 12:11:20.219856 DQM Delay:
1795 12:11:20.219975 DQM0 = 84, DQM1 = 75
1796 12:11:20.222936 DQ Delay:
1797 12:11:20.226767 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1798 12:11:20.226912 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =80
1799 12:11:20.229896 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
1800 12:11:20.233036 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
1801 12:11:20.236797
1802 12:11:20.236953
1803 12:11:20.243252 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1804 12:11:20.246187 CH1 RK0: MR19=605, MR18=26FB
1805 12:11:20.252798 CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1806 12:11:20.252987
1807 12:11:20.256730 ----->DramcWriteLeveling(PI) begin...
1808 12:11:20.256916 ==
1809 12:11:20.259985 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 12:11:20.263102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 12:11:20.263248 ==
1812 12:11:20.266367 Write leveling (Byte 0): 26 => 26
1813 12:11:20.269548 Write leveling (Byte 1): 31 => 31
1814 12:11:20.273299 DramcWriteLeveling(PI) end<-----
1815 12:11:20.273464
1816 12:11:20.273567 ==
1817 12:11:20.276433 Dram Type= 6, Freq= 0, CH_1, rank 1
1818 12:11:20.279617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1819 12:11:20.279753 ==
1820 12:11:20.283437 [Gating] SW mode calibration
1821 12:11:20.289701 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1822 12:11:20.296785 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1823 12:11:20.299952 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1824 12:11:20.303053 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1825 12:11:20.309899 0 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1826 12:11:20.313179 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:11:20.316351 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:11:20.323394 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:11:20.326598 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:11:20.329975 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:11:20.336801 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:11:20.339989 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:11:20.343135 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:11:20.346858 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:11:20.353335 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:11:20.356601 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1837 12:11:20.360062 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1838 12:11:20.366708 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1839 12:11:20.369739 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1840 12:11:20.373591 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1841 12:11:20.379961 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1842 12:11:20.383711 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:11:20.386773 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:11:20.393724 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:11:20.396784 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:11:20.400009 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:11:20.406913 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:11:20.410270 0 9 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1849 12:11:20.413256 0 9 8 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
1850 12:11:20.417116 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 12:11:20.423461 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 12:11:20.426566 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 12:11:20.430393 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 12:11:20.436620 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1855 12:11:20.440464 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 12:11:20.443569 0 10 4 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 1)
1857 12:11:20.450364 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1858 12:11:20.453574 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1859 12:11:20.456703 0 10 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1860 12:11:20.463422 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:11:20.466918 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:11:20.470433 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 12:11:20.476934 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 12:11:20.480069 0 11 4 | B1->B0 | 2b2b 3b3b | 1 1 | (0 0) (1 1)
1865 12:11:20.483254 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1866 12:11:20.490418 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 12:11:20.493606 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 12:11:20.496776 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 12:11:20.503614 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 12:11:20.506887 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 12:11:20.509906 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 12:11:20.513745 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1873 12:11:20.520012 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1874 12:11:20.523454 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:11:20.527137 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:11:20.533487 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:11:20.536610 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:11:20.539797 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:11:20.546692 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:11:20.549855 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:11:20.553065 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 12:11:20.560160 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 12:11:20.563252 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 12:11:20.566886 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 12:11:20.573007 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 12:11:20.576626 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 12:11:20.579654 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 12:11:20.586822 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1889 12:11:20.590135 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 12:11:20.593261 Total UI for P1: 0, mck2ui 16
1891 12:11:20.596542 best dqsien dly found for B0: ( 0, 14, 4)
1892 12:11:20.599673 Total UI for P1: 0, mck2ui 16
1893 12:11:20.603456 best dqsien dly found for B1: ( 0, 14, 4)
1894 12:11:20.606738 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1895 12:11:20.609948 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1896 12:11:20.610090
1897 12:11:20.613311 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1898 12:11:20.616247 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1899 12:11:20.620015 [Gating] SW calibration Done
1900 12:11:20.620274 ==
1901 12:11:20.623151 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 12:11:20.626311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 12:11:20.626463 ==
1904 12:11:20.630094 RX Vref Scan: 0
1905 12:11:20.630242
1906 12:11:20.633343 RX Vref 0 -> 0, step: 1
1907 12:11:20.633491
1908 12:11:20.633596 RX Delay -130 -> 252, step: 16
1909 12:11:20.639660 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1910 12:11:20.643453 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1911 12:11:20.646611 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1912 12:11:20.649820 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1913 12:11:20.652955 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1914 12:11:20.659843 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1915 12:11:20.662925 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1916 12:11:20.666093 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1917 12:11:20.669783 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1918 12:11:20.672863 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1919 12:11:20.680191 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1920 12:11:20.682982 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1921 12:11:20.686555 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1922 12:11:20.689552 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1923 12:11:20.693233 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1924 12:11:20.699784 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1925 12:11:20.699969 ==
1926 12:11:20.702966 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 12:11:20.706693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 12:11:20.706855 ==
1929 12:11:20.706989 DQS Delay:
1930 12:11:20.709728 DQS0 = 0, DQS1 = 0
1931 12:11:20.709886 DQM Delay:
1932 12:11:20.712923 DQM0 = 81, DQM1 = 76
1933 12:11:20.713082 DQ Delay:
1934 12:11:20.716127 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1935 12:11:20.719836 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =69
1936 12:11:20.722988 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1937 12:11:20.726095 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1938 12:11:20.726251
1939 12:11:20.726393
1940 12:11:20.726518 ==
1941 12:11:20.729855 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 12:11:20.733036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 12:11:20.736172 ==
1944 12:11:20.736354
1945 12:11:20.736460
1946 12:11:20.736570 TX Vref Scan disable
1947 12:11:20.739319 == TX Byte 0 ==
1948 12:11:20.743000 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1949 12:11:20.746289 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1950 12:11:20.749414 == TX Byte 1 ==
1951 12:11:20.752684 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1952 12:11:20.756450 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1953 12:11:20.756619 ==
1954 12:11:20.759703 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 12:11:20.765897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 12:11:20.766077 ==
1957 12:11:20.778619 TX Vref=22, minBit 8, minWin=27, winSum=445
1958 12:11:20.781665 TX Vref=24, minBit 0, minWin=27, winSum=443
1959 12:11:20.785135 TX Vref=26, minBit 1, minWin=27, winSum=448
1960 12:11:20.788276 TX Vref=28, minBit 0, minWin=28, winSum=453
1961 12:11:20.791779 TX Vref=30, minBit 0, minWin=28, winSum=455
1962 12:11:20.798325 TX Vref=32, minBit 0, minWin=28, winSum=455
1963 12:11:20.802007 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1964 12:11:20.802172
1965 12:11:20.805623 Final TX Range 1 Vref 30
1966 12:11:20.805771
1967 12:11:20.805872 ==
1968 12:11:20.808666 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 12:11:20.811793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 12:11:20.811921 ==
1971 12:11:20.814937
1972 12:11:20.815062
1973 12:11:20.815160 TX Vref Scan disable
1974 12:11:20.818872 == TX Byte 0 ==
1975 12:11:20.821969 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1976 12:11:20.825075 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1977 12:11:20.829064 == TX Byte 1 ==
1978 12:11:20.832145 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1979 12:11:20.835310 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1980 12:11:20.838471
1981 12:11:20.838643 [DATLAT]
1982 12:11:20.838758 Freq=800, CH1 RK1
1983 12:11:20.838853
1984 12:11:20.842311 DATLAT Default: 0xa
1985 12:11:20.842486 0, 0xFFFF, sum = 0
1986 12:11:20.845493 1, 0xFFFF, sum = 0
1987 12:11:20.845660 2, 0xFFFF, sum = 0
1988 12:11:20.848792 3, 0xFFFF, sum = 0
1989 12:11:20.848981 4, 0xFFFF, sum = 0
1990 12:11:20.851925 5, 0xFFFF, sum = 0
1991 12:11:20.852103 6, 0xFFFF, sum = 0
1992 12:11:20.855635 7, 0xFFFF, sum = 0
1993 12:11:20.858746 8, 0xFFFF, sum = 0
1994 12:11:20.858883 9, 0x0, sum = 1
1995 12:11:20.858999 10, 0x0, sum = 2
1996 12:11:20.861974 11, 0x0, sum = 3
1997 12:11:20.862086 12, 0x0, sum = 4
1998 12:11:20.865043 best_step = 10
1999 12:11:20.865179
2000 12:11:20.865283 ==
2001 12:11:20.868347 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 12:11:20.872108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 12:11:20.872249 ==
2004 12:11:20.875409 RX Vref Scan: 0
2005 12:11:20.875552
2006 12:11:20.875653 RX Vref 0 -> 0, step: 1
2007 12:11:20.875757
2008 12:11:20.878478 RX Delay -111 -> 252, step: 8
2009 12:11:20.885408 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2010 12:11:20.888488 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2011 12:11:20.891913 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2012 12:11:20.895838 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2013 12:11:20.898549 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2014 12:11:20.905196 iDelay=209, Bit 5, Center 92 (-15 ~ 200) 216
2015 12:11:20.908829 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2016 12:11:20.912085 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2017 12:11:20.915645 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2018 12:11:20.918790 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2019 12:11:20.925134 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2020 12:11:20.928974 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2021 12:11:20.932179 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2022 12:11:20.935321 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2023 12:11:20.938381 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2024 12:11:20.945383 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2025 12:11:20.945548 ==
2026 12:11:20.948578 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 12:11:20.951765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 12:11:20.951894 ==
2029 12:11:20.951994 DQS Delay:
2030 12:11:20.955598 DQS0 = 0, DQS1 = 0
2031 12:11:20.955714 DQM Delay:
2032 12:11:20.958764 DQM0 = 80, DQM1 = 75
2033 12:11:20.958879 DQ Delay:
2034 12:11:20.961841 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2035 12:11:20.965110 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2036 12:11:20.968504 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2037 12:11:20.971980 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2038 12:11:20.972141
2039 12:11:20.972261
2040 12:11:20.978970 [DQSOSCAuto] RK1, (LSB)MR18= 0x222d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2041 12:11:20.982170 CH1 RK1: MR19=606, MR18=222D
2042 12:11:20.988523 CH1_RK1: MR19=0x606, MR18=0x222D, DQSOSC=398, MR23=63, INC=93, DEC=62
2043 12:11:20.992276 [RxdqsGatingPostProcess] freq 800
2044 12:11:20.998279 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2045 12:11:21.001701 Pre-setting of DQS Precalculation
2046 12:11:21.005507 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2047 12:11:21.011940 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2048 12:11:21.018831 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2049 12:11:21.018985
2050 12:11:21.019106
2051 12:11:21.021797 [Calibration Summary] 1600 Mbps
2052 12:11:21.025308 CH 0, Rank 0
2053 12:11:21.025425 SW Impedance : PASS
2054 12:11:21.028541 DUTY Scan : NO K
2055 12:11:21.031856 ZQ Calibration : PASS
2056 12:11:21.032057 Jitter Meter : NO K
2057 12:11:21.034952 CBT Training : PASS
2058 12:11:21.038824 Write leveling : PASS
2059 12:11:21.038998 RX DQS gating : PASS
2060 12:11:21.041949 RX DQ/DQS(RDDQC) : PASS
2061 12:11:21.045064 TX DQ/DQS : PASS
2062 12:11:21.045281 RX DATLAT : PASS
2063 12:11:21.048806 RX DQ/DQS(Engine): PASS
2064 12:11:21.048967 TX OE : NO K
2065 12:11:21.052142 All Pass.
2066 12:11:21.052253
2067 12:11:21.052364 CH 0, Rank 1
2068 12:11:21.055154 SW Impedance : PASS
2069 12:11:21.055291 DUTY Scan : NO K
2070 12:11:21.058969 ZQ Calibration : PASS
2071 12:11:21.062087 Jitter Meter : NO K
2072 12:11:21.062237 CBT Training : PASS
2073 12:11:21.065253 Write leveling : PASS
2074 12:11:21.068534 RX DQS gating : PASS
2075 12:11:21.068710 RX DQ/DQS(RDDQC) : PASS
2076 12:11:21.071771 TX DQ/DQS : PASS
2077 12:11:21.074938 RX DATLAT : PASS
2078 12:11:21.075074 RX DQ/DQS(Engine): PASS
2079 12:11:21.078681 TX OE : NO K
2080 12:11:21.078818 All Pass.
2081 12:11:21.078925
2082 12:11:21.081758 CH 1, Rank 0
2083 12:11:21.081888 SW Impedance : PASS
2084 12:11:21.084903 DUTY Scan : NO K
2085 12:11:21.088862 ZQ Calibration : PASS
2086 12:11:21.089050 Jitter Meter : NO K
2087 12:11:21.092024 CBT Training : PASS
2088 12:11:21.092163 Write leveling : PASS
2089 12:11:21.095150 RX DQS gating : PASS
2090 12:11:21.098347 RX DQ/DQS(RDDQC) : PASS
2091 12:11:21.098496 TX DQ/DQS : PASS
2092 12:11:21.101662 RX DATLAT : PASS
2093 12:11:21.105393 RX DQ/DQS(Engine): PASS
2094 12:11:21.105559 TX OE : NO K
2095 12:11:21.108407 All Pass.
2096 12:11:21.108532
2097 12:11:21.108678 CH 1, Rank 1
2098 12:11:21.112325 SW Impedance : PASS
2099 12:11:21.112462 DUTY Scan : NO K
2100 12:11:21.115344 ZQ Calibration : PASS
2101 12:11:21.118406 Jitter Meter : NO K
2102 12:11:21.118647 CBT Training : PASS
2103 12:11:21.122071 Write leveling : PASS
2104 12:11:21.125125 RX DQS gating : PASS
2105 12:11:21.125307 RX DQ/DQS(RDDQC) : PASS
2106 12:11:21.128740 TX DQ/DQS : PASS
2107 12:11:21.131611 RX DATLAT : PASS
2108 12:11:21.131810 RX DQ/DQS(Engine): PASS
2109 12:11:21.135237 TX OE : NO K
2110 12:11:21.135414 All Pass.
2111 12:11:21.135574
2112 12:11:21.138363 DramC Write-DBI off
2113 12:11:21.141601 PER_BANK_REFRESH: Hybrid Mode
2114 12:11:21.141776 TX_TRACKING: ON
2115 12:11:21.144804 [GetDramInforAfterCalByMRR] Vendor 6.
2116 12:11:21.148575 [GetDramInforAfterCalByMRR] Revision 606.
2117 12:11:21.151705 [GetDramInforAfterCalByMRR] Revision 2 0.
2118 12:11:21.154861 MR0 0x3b3b
2119 12:11:21.155057 MR8 0x5151
2120 12:11:21.158714 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 12:11:21.158874
2122 12:11:21.158992 MR0 0x3b3b
2123 12:11:21.161876 MR8 0x5151
2124 12:11:21.165030 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2125 12:11:21.165195
2126 12:11:21.172118 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2127 12:11:21.178384 [FAST_K] Save calibration result to emmc
2128 12:11:21.181679 [FAST_K] Save calibration result to emmc
2129 12:11:21.181887 dram_init: config_dvfs: 1
2130 12:11:21.185519 dramc_set_vcore_voltage set vcore to 662500
2131 12:11:21.188532 Read voltage for 1200, 2
2132 12:11:21.188684 Vio18 = 0
2133 12:11:21.191797 Vcore = 662500
2134 12:11:21.191916 Vdram = 0
2135 12:11:21.192004 Vddq = 0
2136 12:11:21.194816 Vmddr = 0
2137 12:11:21.198735 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2138 12:11:21.204864 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2139 12:11:21.205014 MEM_TYPE=3, freq_sel=15
2140 12:11:21.208089 sv_algorithm_assistance_LP4_1600
2141 12:11:21.215420 ============ PULL DRAM RESETB DOWN ============
2142 12:11:21.218274 ========== PULL DRAM RESETB DOWN end =========
2143 12:11:21.221701 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2144 12:11:21.224854 ===================================
2145 12:11:21.228568 LPDDR4 DRAM CONFIGURATION
2146 12:11:21.231915 ===================================
2147 12:11:21.235244 EX_ROW_EN[0] = 0x0
2148 12:11:21.235414 EX_ROW_EN[1] = 0x0
2149 12:11:21.238150 LP4Y_EN = 0x0
2150 12:11:21.238305 WORK_FSP = 0x0
2151 12:11:21.241739 WL = 0x4
2152 12:11:21.241905 RL = 0x4
2153 12:11:21.244840 BL = 0x2
2154 12:11:21.244977 RPST = 0x0
2155 12:11:21.248009 RD_PRE = 0x0
2156 12:11:21.248162 WR_PRE = 0x1
2157 12:11:21.251839 WR_PST = 0x0
2158 12:11:21.252015 DBI_WR = 0x0
2159 12:11:21.255060 DBI_RD = 0x0
2160 12:11:21.255211 OTF = 0x1
2161 12:11:21.258184 ===================================
2162 12:11:21.262056 ===================================
2163 12:11:21.265114 ANA top config
2164 12:11:21.268265 ===================================
2165 12:11:21.268443 DLL_ASYNC_EN = 0
2166 12:11:21.271371 ALL_SLAVE_EN = 0
2167 12:11:21.274773 NEW_RANK_MODE = 1
2168 12:11:21.278428 DLL_IDLE_MODE = 1
2169 12:11:21.281574 LP45_APHY_COMB_EN = 1
2170 12:11:21.281732 TX_ODT_DIS = 1
2171 12:11:21.285424 NEW_8X_MODE = 1
2172 12:11:21.288626 ===================================
2173 12:11:21.291742 ===================================
2174 12:11:21.294895 data_rate = 2400
2175 12:11:21.298031 CKR = 1
2176 12:11:21.301919 DQ_P2S_RATIO = 8
2177 12:11:21.305124 ===================================
2178 12:11:21.305286 CA_P2S_RATIO = 8
2179 12:11:21.308344 DQ_CA_OPEN = 0
2180 12:11:21.311476 DQ_SEMI_OPEN = 0
2181 12:11:21.315285 CA_SEMI_OPEN = 0
2182 12:11:21.318429 CA_FULL_RATE = 0
2183 12:11:21.321604 DQ_CKDIV4_EN = 0
2184 12:11:21.321775 CA_CKDIV4_EN = 0
2185 12:11:21.325155 CA_PREDIV_EN = 0
2186 12:11:21.328183 PH8_DLY = 17
2187 12:11:21.331718 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2188 12:11:21.334803 DQ_AAMCK_DIV = 4
2189 12:11:21.338444 CA_AAMCK_DIV = 4
2190 12:11:21.338617 CA_ADMCK_DIV = 4
2191 12:11:21.341417 DQ_TRACK_CA_EN = 0
2192 12:11:21.345023 CA_PICK = 1200
2193 12:11:21.348049 CA_MCKIO = 1200
2194 12:11:21.351750 MCKIO_SEMI = 0
2195 12:11:21.354944 PLL_FREQ = 2366
2196 12:11:21.358059 DQ_UI_PI_RATIO = 32
2197 12:11:21.361354 CA_UI_PI_RATIO = 0
2198 12:11:21.361522 ===================================
2199 12:11:21.364586 ===================================
2200 12:11:21.368299 memory_type:LPDDR4
2201 12:11:21.371415 GP_NUM : 10
2202 12:11:21.371654 SRAM_EN : 1
2203 12:11:21.374674 MD32_EN : 0
2204 12:11:21.377772 ===================================
2205 12:11:21.381613 [ANA_INIT] >>>>>>>>>>>>>>
2206 12:11:21.384813 <<<<<< [CONFIGURE PHASE]: ANA_TX
2207 12:11:21.387934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2208 12:11:21.391736 ===================================
2209 12:11:21.391993 data_rate = 2400,PCW = 0X5b00
2210 12:11:21.395032 ===================================
2211 12:11:21.398083 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2212 12:11:21.405080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 12:11:21.411255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 12:11:21.415101 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2215 12:11:21.418324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2216 12:11:21.421551 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2217 12:11:21.424674 [ANA_INIT] flow start
2218 12:11:21.428041 [ANA_INIT] PLL >>>>>>>>
2219 12:11:21.428217 [ANA_INIT] PLL <<<<<<<<
2220 12:11:21.431086 [ANA_INIT] MIDPI >>>>>>>>
2221 12:11:21.434726 [ANA_INIT] MIDPI <<<<<<<<
2222 12:11:21.434876 [ANA_INIT] DLL >>>>>>>>
2223 12:11:21.438399 [ANA_INIT] DLL <<<<<<<<
2224 12:11:21.441376 [ANA_INIT] flow end
2225 12:11:21.444400 ============ LP4 DIFF to SE enter ============
2226 12:11:21.447937 ============ LP4 DIFF to SE exit ============
2227 12:11:21.451449 [ANA_INIT] <<<<<<<<<<<<<
2228 12:11:21.454556 [Flow] Enable top DCM control >>>>>
2229 12:11:21.458104 [Flow] Enable top DCM control <<<<<
2230 12:11:21.461151 Enable DLL master slave shuffle
2231 12:11:21.464999 ==============================================================
2232 12:11:21.468272 Gating Mode config
2233 12:11:21.471244 ==============================================================
2234 12:11:21.475073 Config description:
2235 12:11:21.484643 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2236 12:11:21.491717 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2237 12:11:21.495065 SELPH_MODE 0: By rank 1: By Phase
2238 12:11:21.501480 ==============================================================
2239 12:11:21.504640 GAT_TRACK_EN = 1
2240 12:11:21.507840 RX_GATING_MODE = 2
2241 12:11:21.511622 RX_GATING_TRACK_MODE = 2
2242 12:11:21.515019 SELPH_MODE = 1
2243 12:11:21.515160 PICG_EARLY_EN = 1
2244 12:11:21.518071 VALID_LAT_VALUE = 1
2245 12:11:21.524935 ==============================================================
2246 12:11:21.528110 Enter into Gating configuration >>>>
2247 12:11:21.531461 Exit from Gating configuration <<<<
2248 12:11:21.534575 Enter into DVFS_PRE_config >>>>>
2249 12:11:21.545232 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2250 12:11:21.547925 Exit from DVFS_PRE_config <<<<<
2251 12:11:21.551552 Enter into PICG configuration >>>>
2252 12:11:21.554600 Exit from PICG configuration <<<<
2253 12:11:21.558187 [RX_INPUT] configuration >>>>>
2254 12:11:21.561925 [RX_INPUT] configuration <<<<<
2255 12:11:21.564849 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2256 12:11:21.571533 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2257 12:11:21.577944 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 12:11:21.585067 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 12:11:21.591280 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 12:11:21.595161 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 12:11:21.601607 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2262 12:11:21.604722 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2263 12:11:21.607961 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2264 12:11:21.611038 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2265 12:11:21.614906 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2266 12:11:21.621319 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 12:11:21.624537 ===================================
2268 12:11:21.627798 LPDDR4 DRAM CONFIGURATION
2269 12:11:21.631458 ===================================
2270 12:11:21.631630 EX_ROW_EN[0] = 0x0
2271 12:11:21.634608 EX_ROW_EN[1] = 0x0
2272 12:11:21.634742 LP4Y_EN = 0x0
2273 12:11:21.637826 WORK_FSP = 0x0
2274 12:11:21.637957 WL = 0x4
2275 12:11:21.641035 RL = 0x4
2276 12:11:21.641173 BL = 0x2
2277 12:11:21.644804 RPST = 0x0
2278 12:11:21.644945 RD_PRE = 0x0
2279 12:11:21.648034 WR_PRE = 0x1
2280 12:11:21.648185 WR_PST = 0x0
2281 12:11:21.651022 DBI_WR = 0x0
2282 12:11:21.651149 DBI_RD = 0x0
2283 12:11:21.654713 OTF = 0x1
2284 12:11:21.657797 ===================================
2285 12:11:21.661236 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2286 12:11:21.664208 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2287 12:11:21.670842 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 12:11:21.674453 ===================================
2289 12:11:21.674624 LPDDR4 DRAM CONFIGURATION
2290 12:11:21.677578 ===================================
2291 12:11:21.680947 EX_ROW_EN[0] = 0x10
2292 12:11:21.684607 EX_ROW_EN[1] = 0x0
2293 12:11:21.684777 LP4Y_EN = 0x0
2294 12:11:21.687796 WORK_FSP = 0x0
2295 12:11:21.687969 WL = 0x4
2296 12:11:21.690990 RL = 0x4
2297 12:11:21.691131 BL = 0x2
2298 12:11:21.694710 RPST = 0x0
2299 12:11:21.694848 RD_PRE = 0x0
2300 12:11:21.697387 WR_PRE = 0x1
2301 12:11:21.697484 WR_PST = 0x0
2302 12:11:21.701074 DBI_WR = 0x0
2303 12:11:21.701194 DBI_RD = 0x0
2304 12:11:21.704239 OTF = 0x1
2305 12:11:21.707454 ===================================
2306 12:11:21.714426 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2307 12:11:21.714610 ==
2308 12:11:21.717576 Dram Type= 6, Freq= 0, CH_0, rank 0
2309 12:11:21.721374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2310 12:11:21.721545 ==
2311 12:11:21.724585 [Duty_Offset_Calibration]
2312 12:11:21.724719 B0:2 B1:-1 CA:1
2313 12:11:21.724828
2314 12:11:21.727616 [DutyScan_Calibration_Flow] k_type=0
2315 12:11:21.737205
2316 12:11:21.737386 ==CLK 0==
2317 12:11:21.740917 Final CLK duty delay cell = -4
2318 12:11:21.743519 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2319 12:11:21.747303 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2320 12:11:21.750491 [-4] AVG Duty = 4953%(X100)
2321 12:11:21.750652
2322 12:11:21.753707 CH0 CLK Duty spec in!! Max-Min= 156%
2323 12:11:21.756845 [DutyScan_Calibration_Flow] ====Done====
2324 12:11:21.757010
2325 12:11:21.760542 [DutyScan_Calibration_Flow] k_type=1
2326 12:11:21.775424
2327 12:11:21.775610 ==DQS 0 ==
2328 12:11:21.779089 Final DQS duty delay cell = -4
2329 12:11:21.782014 [-4] MAX Duty = 5000%(X100), DQS PI = 44
2330 12:11:21.785337 [-4] MIN Duty = 4876%(X100), DQS PI = 10
2331 12:11:21.788947 [-4] AVG Duty = 4938%(X100)
2332 12:11:21.789091
2333 12:11:21.789228 ==DQS 1 ==
2334 12:11:21.792110 Final DQS duty delay cell = -4
2335 12:11:21.795337 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2336 12:11:21.798346 [-4] MIN Duty = 5000%(X100), DQS PI = 46
2337 12:11:21.802263 [-4] AVG Duty = 5062%(X100)
2338 12:11:21.802415
2339 12:11:21.805549 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2340 12:11:21.805711
2341 12:11:21.808683 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2342 12:11:21.811861 [DutyScan_Calibration_Flow] ====Done====
2343 12:11:21.811998
2344 12:11:21.815076 [DutyScan_Calibration_Flow] k_type=3
2345 12:11:21.832667
2346 12:11:21.832851 ==DQM 0 ==
2347 12:11:21.835867 Final DQM duty delay cell = 0
2348 12:11:21.839064 [0] MAX Duty = 5000%(X100), DQS PI = 52
2349 12:11:21.842251 [0] MIN Duty = 4907%(X100), DQS PI = 2
2350 12:11:21.842394 [0] AVG Duty = 4953%(X100)
2351 12:11:21.846181
2352 12:11:21.846324 ==DQM 1 ==
2353 12:11:21.849301 Final DQM duty delay cell = 0
2354 12:11:21.852576 [0] MAX Duty = 5156%(X100), DQS PI = 62
2355 12:11:21.855644 [0] MIN Duty = 4969%(X100), DQS PI = 58
2356 12:11:21.855773 [0] AVG Duty = 5062%(X100)
2357 12:11:21.859494
2358 12:11:21.862679 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2359 12:11:21.862820
2360 12:11:21.865734 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2361 12:11:21.869536 [DutyScan_Calibration_Flow] ====Done====
2362 12:11:21.869699
2363 12:11:21.872566 [DutyScan_Calibration_Flow] k_type=2
2364 12:11:21.888020
2365 12:11:21.888197 ==DQ 0 ==
2366 12:11:21.891658 Final DQ duty delay cell = -4
2367 12:11:21.894682 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2368 12:11:21.897785 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2369 12:11:21.901582 [-4] AVG Duty = 4984%(X100)
2370 12:11:21.901747
2371 12:11:21.901862 ==DQ 1 ==
2372 12:11:21.904838 Final DQ duty delay cell = 0
2373 12:11:21.907930 [0] MAX Duty = 5031%(X100), DQS PI = 18
2374 12:11:21.911813 [0] MIN Duty = 4907%(X100), DQS PI = 62
2375 12:11:21.914940 [0] AVG Duty = 4969%(X100)
2376 12:11:21.915104
2377 12:11:21.918068 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2378 12:11:21.918232
2379 12:11:21.921212 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2380 12:11:21.925022 [DutyScan_Calibration_Flow] ====Done====
2381 12:11:21.925206 ==
2382 12:11:21.928216 Dram Type= 6, Freq= 0, CH_1, rank 0
2383 12:11:21.931414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2384 12:11:21.931625 ==
2385 12:11:21.934605 [Duty_Offset_Calibration]
2386 12:11:21.934790 B0:1 B1:1 CA:2
2387 12:11:21.934911
2388 12:11:21.937753 [DutyScan_Calibration_Flow] k_type=0
2389 12:11:21.948501
2390 12:11:21.948654 ==CLK 0==
2391 12:11:21.951778 Final CLK duty delay cell = 0
2392 12:11:21.955458 [0] MAX Duty = 5187%(X100), DQS PI = 24
2393 12:11:21.958418 [0] MIN Duty = 4969%(X100), DQS PI = 40
2394 12:11:21.958583 [0] AVG Duty = 5078%(X100)
2395 12:11:21.961626
2396 12:11:21.965323 CH1 CLK Duty spec in!! Max-Min= 218%
2397 12:11:21.968389 [DutyScan_Calibration_Flow] ====Done====
2398 12:11:21.968537
2399 12:11:21.971606 [DutyScan_Calibration_Flow] k_type=1
2400 12:11:21.988054
2401 12:11:21.988276 ==DQS 0 ==
2402 12:11:21.990998 Final DQS duty delay cell = 0
2403 12:11:21.994684 [0] MAX Duty = 5031%(X100), DQS PI = 18
2404 12:11:21.997460 [0] MIN Duty = 4844%(X100), DQS PI = 48
2405 12:11:22.000973 [0] AVG Duty = 4937%(X100)
2406 12:11:22.001136
2407 12:11:22.001248 ==DQS 1 ==
2408 12:11:22.004133 Final DQS duty delay cell = 0
2409 12:11:22.007332 [0] MAX Duty = 5062%(X100), DQS PI = 36
2410 12:11:22.011210 [0] MIN Duty = 4907%(X100), DQS PI = 16
2411 12:11:22.014402 [0] AVG Duty = 4984%(X100)
2412 12:11:22.014531
2413 12:11:22.017587 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2414 12:11:22.017730
2415 12:11:22.020957 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2416 12:11:22.024559 [DutyScan_Calibration_Flow] ====Done====
2417 12:11:22.024714
2418 12:11:22.027726 [DutyScan_Calibration_Flow] k_type=3
2419 12:11:22.044664
2420 12:11:22.044857 ==DQM 0 ==
2421 12:11:22.047783 Final DQM duty delay cell = 0
2422 12:11:22.051086 [0] MAX Duty = 5093%(X100), DQS PI = 16
2423 12:11:22.054126 [0] MIN Duty = 4907%(X100), DQS PI = 48
2424 12:11:22.057391 [0] AVG Duty = 5000%(X100)
2425 12:11:22.057563
2426 12:11:22.057678 ==DQM 1 ==
2427 12:11:22.061186 Final DQM duty delay cell = 0
2428 12:11:22.064346 [0] MAX Duty = 5156%(X100), DQS PI = 62
2429 12:11:22.067623 [0] MIN Duty = 4938%(X100), DQS PI = 22
2430 12:11:22.070701 [0] AVG Duty = 5047%(X100)
2431 12:11:22.070869
2432 12:11:22.074595 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2433 12:11:22.074758
2434 12:11:22.077677 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2435 12:11:22.080829 [DutyScan_Calibration_Flow] ====Done====
2436 12:11:22.081005
2437 12:11:22.084778 [DutyScan_Calibration_Flow] k_type=2
2438 12:11:22.100984
2439 12:11:22.101187 ==DQ 0 ==
2440 12:11:22.104055 Final DQ duty delay cell = 0
2441 12:11:22.107547 [0] MAX Duty = 5125%(X100), DQS PI = 18
2442 12:11:22.110853 [0] MIN Duty = 4907%(X100), DQS PI = 50
2443 12:11:22.111038 [0] AVG Duty = 5016%(X100)
2444 12:11:22.111143
2445 12:11:22.114445 ==DQ 1 ==
2446 12:11:22.117694 Final DQ duty delay cell = 0
2447 12:11:22.120840 [0] MAX Duty = 5093%(X100), DQS PI = 10
2448 12:11:22.124047 [0] MIN Duty = 5000%(X100), DQS PI = 50
2449 12:11:22.124213 [0] AVG Duty = 5046%(X100)
2450 12:11:22.124318
2451 12:11:22.127770 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2452 12:11:22.130915
2453 12:11:22.131081 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2454 12:11:22.137824 [DutyScan_Calibration_Flow] ====Done====
2455 12:11:22.140990 nWR fixed to 30
2456 12:11:22.141138 [ModeRegInit_LP4] CH0 RK0
2457 12:11:22.144278 [ModeRegInit_LP4] CH0 RK1
2458 12:11:22.147360 [ModeRegInit_LP4] CH1 RK0
2459 12:11:22.147608 [ModeRegInit_LP4] CH1 RK1
2460 12:11:22.151117 match AC timing 7
2461 12:11:22.154378 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2462 12:11:22.157430 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2463 12:11:22.164657 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2464 12:11:22.167794 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2465 12:11:22.174185 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2466 12:11:22.174368 ==
2467 12:11:22.177990 Dram Type= 6, Freq= 0, CH_0, rank 0
2468 12:11:22.181190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2469 12:11:22.181426 ==
2470 12:11:22.187588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2471 12:11:22.191424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2472 12:11:22.201112 [CA 0] Center 40 (10~71) winsize 62
2473 12:11:22.204206 [CA 1] Center 39 (9~70) winsize 62
2474 12:11:22.207636 [CA 2] Center 36 (6~67) winsize 62
2475 12:11:22.210568 [CA 3] Center 36 (5~67) winsize 63
2476 12:11:22.214326 [CA 4] Center 34 (4~65) winsize 62
2477 12:11:22.217934 [CA 5] Center 34 (4~64) winsize 61
2478 12:11:22.218101
2479 12:11:22.221323 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2480 12:11:22.221511
2481 12:11:22.224211 [CATrainingPosCal] consider 1 rank data
2482 12:11:22.227493 u2DelayCellTimex100 = 270/100 ps
2483 12:11:22.230662 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2484 12:11:22.237585 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2485 12:11:22.240729 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2486 12:11:22.244646 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2487 12:11:22.247773 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2488 12:11:22.250863 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2489 12:11:22.251025
2490 12:11:22.254085 CA PerBit enable=1, Macro0, CA PI delay=34
2491 12:11:22.254233
2492 12:11:22.257826 [CBTSetCACLKResult] CA Dly = 34
2493 12:11:22.257967 CS Dly: 7 (0~38)
2494 12:11:22.261015 ==
2495 12:11:22.261150 Dram Type= 6, Freq= 0, CH_0, rank 1
2496 12:11:22.267454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 12:11:22.267625 ==
2498 12:11:22.271204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2499 12:11:22.277450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2500 12:11:22.287124 [CA 0] Center 39 (9~70) winsize 62
2501 12:11:22.290330 [CA 1] Center 40 (10~70) winsize 61
2502 12:11:22.293471 [CA 2] Center 36 (6~67) winsize 62
2503 12:11:22.296759 [CA 3] Center 36 (5~67) winsize 63
2504 12:11:22.299921 [CA 4] Center 34 (4~65) winsize 62
2505 12:11:22.303620 [CA 5] Center 34 (4~64) winsize 61
2506 12:11:22.303792
2507 12:11:22.306565 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2508 12:11:22.306703
2509 12:11:22.310205 [CATrainingPosCal] consider 2 rank data
2510 12:11:22.313256 u2DelayCellTimex100 = 270/100 ps
2511 12:11:22.316707 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2512 12:11:22.323317 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2513 12:11:22.327046 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2514 12:11:22.330201 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2515 12:11:22.333851 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2516 12:11:22.337157 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2517 12:11:22.337306
2518 12:11:22.340344 CA PerBit enable=1, Macro0, CA PI delay=34
2519 12:11:22.340489
2520 12:11:22.343481 [CBTSetCACLKResult] CA Dly = 34
2521 12:11:22.343625 CS Dly: 8 (0~41)
2522 12:11:22.343740
2523 12:11:22.347192 ----->DramcWriteLeveling(PI) begin...
2524 12:11:22.350258 ==
2525 12:11:22.353439 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 12:11:22.357164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 12:11:22.357329 ==
2528 12:11:22.360377 Write leveling (Byte 0): 32 => 32
2529 12:11:22.363714 Write leveling (Byte 1): 29 => 29
2530 12:11:22.367240 DramcWriteLeveling(PI) end<-----
2531 12:11:22.367408
2532 12:11:22.367519 ==
2533 12:11:22.370401 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 12:11:22.373817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 12:11:22.373973 ==
2536 12:11:22.377505 [Gating] SW mode calibration
2537 12:11:22.383681 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2538 12:11:22.386878 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2539 12:11:22.393317 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 12:11:22.397019 0 15 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
2541 12:11:22.400153 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2542 12:11:22.407177 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 12:11:22.410327 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 12:11:22.413894 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 12:11:22.420380 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 12:11:22.423590 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 12:11:22.427140 1 0 0 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
2548 12:11:22.433892 1 0 4 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
2549 12:11:22.437020 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 12:11:22.440260 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 12:11:22.446944 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 12:11:22.450101 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 12:11:22.453444 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 12:11:22.460398 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 12:11:22.463639 1 1 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2556 12:11:22.466703 1 1 4 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
2557 12:11:22.473673 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 12:11:22.476947 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 12:11:22.480184 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 12:11:22.487228 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 12:11:22.490068 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 12:11:22.493320 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 12:11:22.500220 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2564 12:11:22.503400 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:11:22.506621 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:11:22.509756 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:11:22.516917 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:11:22.519915 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:11:22.523468 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 12:11:22.529973 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 12:11:22.533041 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 12:11:22.536700 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 12:11:22.543546 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 12:11:22.546529 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 12:11:22.550287 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 12:11:22.556612 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 12:11:22.559758 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 12:11:22.562965 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2579 12:11:22.570024 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2580 12:11:22.573094 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2581 12:11:22.576298 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 12:11:22.579575 Total UI for P1: 0, mck2ui 16
2583 12:11:22.583168 best dqsien dly found for B0: ( 1, 4, 0)
2584 12:11:22.586421 Total UI for P1: 0, mck2ui 16
2585 12:11:22.589605 best dqsien dly found for B1: ( 1, 4, 4)
2586 12:11:22.593341 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2587 12:11:22.596536 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2588 12:11:22.596657
2589 12:11:22.599621 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2590 12:11:22.606583 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2591 12:11:22.606726 [Gating] SW calibration Done
2592 12:11:22.606798 ==
2593 12:11:22.609784 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 12:11:22.616170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 12:11:22.616299 ==
2596 12:11:22.616370 RX Vref Scan: 0
2597 12:11:22.616431
2598 12:11:22.620039 RX Vref 0 -> 0, step: 1
2599 12:11:22.620204
2600 12:11:22.623212 RX Delay -40 -> 252, step: 8
2601 12:11:22.626295 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2602 12:11:22.629809 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2603 12:11:22.632813 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2604 12:11:22.639306 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2605 12:11:22.642967 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2606 12:11:22.646573 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2607 12:11:22.649625 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2608 12:11:22.652904 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2609 12:11:22.656160 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2610 12:11:22.663087 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2611 12:11:22.666245 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2612 12:11:22.669390 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2613 12:11:22.672635 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2614 12:11:22.676403 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2615 12:11:22.682679 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2616 12:11:22.686408 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2617 12:11:22.686549 ==
2618 12:11:22.689571 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 12:11:22.692724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 12:11:22.692864 ==
2621 12:11:22.696572 DQS Delay:
2622 12:11:22.696728 DQS0 = 0, DQS1 = 0
2623 12:11:22.696831 DQM Delay:
2624 12:11:22.699778 DQM0 = 116, DQM1 = 107
2625 12:11:22.699911 DQ Delay:
2626 12:11:22.703043 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2627 12:11:22.706106 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2628 12:11:22.709451 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2629 12:11:22.716384 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2630 12:11:22.716552
2631 12:11:22.716656
2632 12:11:22.716761 ==
2633 12:11:22.719394 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 12:11:22.723185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 12:11:22.723343 ==
2636 12:11:22.723462
2637 12:11:22.723572
2638 12:11:22.726264 TX Vref Scan disable
2639 12:11:22.726374 == TX Byte 0 ==
2640 12:11:22.732616 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2641 12:11:22.736442 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2642 12:11:22.736605 == TX Byte 1 ==
2643 12:11:22.743080 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2644 12:11:22.746114 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2645 12:11:22.746246 ==
2646 12:11:22.749750 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 12:11:22.752891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 12:11:22.753036 ==
2649 12:11:22.765672 TX Vref=22, minBit 1, minWin=24, winSum=416
2650 12:11:22.768846 TX Vref=24, minBit 1, minWin=25, winSum=419
2651 12:11:22.772575 TX Vref=26, minBit 0, minWin=26, winSum=430
2652 12:11:22.775745 TX Vref=28, minBit 0, minWin=26, winSum=430
2653 12:11:22.778891 TX Vref=30, minBit 0, minWin=26, winSum=431
2654 12:11:22.782044 TX Vref=32, minBit 0, minWin=26, winSum=431
2655 12:11:22.789228 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 30
2656 12:11:22.789432
2657 12:11:22.792051 Final TX Range 1 Vref 30
2658 12:11:22.792221
2659 12:11:22.792371 ==
2660 12:11:22.795879 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 12:11:22.799070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 12:11:22.799222 ==
2663 12:11:22.799380
2664 12:11:22.802200
2665 12:11:22.802340 TX Vref Scan disable
2666 12:11:22.805458 == TX Byte 0 ==
2667 12:11:22.809251 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2668 12:11:22.812534 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2669 12:11:22.815685 == TX Byte 1 ==
2670 12:11:22.818853 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2671 12:11:22.822116 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2672 12:11:22.822306
2673 12:11:22.825730 [DATLAT]
2674 12:11:22.825890 Freq=1200, CH0 RK0
2675 12:11:22.826045
2676 12:11:22.828823 DATLAT Default: 0xd
2677 12:11:22.828982 0, 0xFFFF, sum = 0
2678 12:11:22.832613 1, 0xFFFF, sum = 0
2679 12:11:22.832778 2, 0xFFFF, sum = 0
2680 12:11:22.835834 3, 0xFFFF, sum = 0
2681 12:11:22.835993 4, 0xFFFF, sum = 0
2682 12:11:22.839049 5, 0xFFFF, sum = 0
2683 12:11:22.839233 6, 0xFFFF, sum = 0
2684 12:11:22.842294 7, 0xFFFF, sum = 0
2685 12:11:22.842460 8, 0xFFFF, sum = 0
2686 12:11:22.846155 9, 0xFFFF, sum = 0
2687 12:11:22.848904 10, 0xFFFF, sum = 0
2688 12:11:22.849073 11, 0xFFFF, sum = 0
2689 12:11:22.852553 12, 0x0, sum = 1
2690 12:11:22.852732 13, 0x0, sum = 2
2691 12:11:22.852906 14, 0x0, sum = 3
2692 12:11:22.855653 15, 0x0, sum = 4
2693 12:11:22.855816 best_step = 13
2694 12:11:22.855949
2695 12:11:22.856106 ==
2696 12:11:22.859103 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 12:11:22.865811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 12:11:22.866017 ==
2699 12:11:22.866155 RX Vref Scan: 1
2700 12:11:22.866306
2701 12:11:22.869190 Set Vref Range= 32 -> 127
2702 12:11:22.869361
2703 12:11:22.872260 RX Vref 32 -> 127, step: 1
2704 12:11:22.872426
2705 12:11:22.876095 RX Delay -21 -> 252, step: 4
2706 12:11:22.876224
2707 12:11:22.879168 Set Vref, RX VrefLevel [Byte0]: 32
2708 12:11:22.882288 [Byte1]: 32
2709 12:11:22.882418
2710 12:11:22.885515 Set Vref, RX VrefLevel [Byte0]: 33
2711 12:11:22.888648 [Byte1]: 33
2712 12:11:22.888766
2713 12:11:22.892519 Set Vref, RX VrefLevel [Byte0]: 34
2714 12:11:22.895678 [Byte1]: 34
2715 12:11:22.900118
2716 12:11:22.900243 Set Vref, RX VrefLevel [Byte0]: 35
2717 12:11:22.903334 [Byte1]: 35
2718 12:11:22.907891
2719 12:11:22.908012 Set Vref, RX VrefLevel [Byte0]: 36
2720 12:11:22.910947 [Byte1]: 36
2721 12:11:22.915497
2722 12:11:22.915651 Set Vref, RX VrefLevel [Byte0]: 37
2723 12:11:22.918639 [Byte1]: 37
2724 12:11:22.923880
2725 12:11:22.924018 Set Vref, RX VrefLevel [Byte0]: 38
2726 12:11:22.926880 [Byte1]: 38
2727 12:11:22.931311
2728 12:11:22.931483 Set Vref, RX VrefLevel [Byte0]: 39
2729 12:11:22.935088 [Byte1]: 39
2730 12:11:22.939551
2731 12:11:22.939716 Set Vref, RX VrefLevel [Byte0]: 40
2732 12:11:22.942677 [Byte1]: 40
2733 12:11:22.947204
2734 12:11:22.947381 Set Vref, RX VrefLevel [Byte0]: 41
2735 12:11:22.950867 [Byte1]: 41
2736 12:11:22.955161
2737 12:11:22.955292 Set Vref, RX VrefLevel [Byte0]: 42
2738 12:11:22.958672 [Byte1]: 42
2739 12:11:22.963394
2740 12:11:22.963527 Set Vref, RX VrefLevel [Byte0]: 43
2741 12:11:22.966292 [Byte1]: 43
2742 12:11:22.971160
2743 12:11:22.971323 Set Vref, RX VrefLevel [Byte0]: 44
2744 12:11:22.974443 [Byte1]: 44
2745 12:11:22.979495
2746 12:11:22.979706 Set Vref, RX VrefLevel [Byte0]: 45
2747 12:11:22.982338 [Byte1]: 45
2748 12:11:22.986854
2749 12:11:22.986990 Set Vref, RX VrefLevel [Byte0]: 46
2750 12:11:22.990070 [Byte1]: 46
2751 12:11:22.995233
2752 12:11:22.995407 Set Vref, RX VrefLevel [Byte0]: 47
2753 12:11:22.998581 [Byte1]: 47
2754 12:11:23.002970
2755 12:11:23.003137 Set Vref, RX VrefLevel [Byte0]: 48
2756 12:11:23.006172 [Byte1]: 48
2757 12:11:23.010758
2758 12:11:23.010936 Set Vref, RX VrefLevel [Byte0]: 49
2759 12:11:23.013782 [Byte1]: 49
2760 12:11:23.018414
2761 12:11:23.018554 Set Vref, RX VrefLevel [Byte0]: 50
2762 12:11:23.021731 [Byte1]: 50
2763 12:11:23.026411
2764 12:11:23.026565 Set Vref, RX VrefLevel [Byte0]: 51
2765 12:11:23.030159 [Byte1]: 51
2766 12:11:23.034733
2767 12:11:23.034841 Set Vref, RX VrefLevel [Byte0]: 52
2768 12:11:23.037850 [Byte1]: 52
2769 12:11:23.042360
2770 12:11:23.042491 Set Vref, RX VrefLevel [Byte0]: 53
2771 12:11:23.045764 [Byte1]: 53
2772 12:11:23.050132
2773 12:11:23.050251 Set Vref, RX VrefLevel [Byte0]: 54
2774 12:11:23.053419 [Byte1]: 54
2775 12:11:23.057992
2776 12:11:23.061736 Set Vref, RX VrefLevel [Byte0]: 55
2777 12:11:23.061881 [Byte1]: 55
2778 12:11:23.066027
2779 12:11:23.066139 Set Vref, RX VrefLevel [Byte0]: 56
2780 12:11:23.069590 [Byte1]: 56
2781 12:11:23.074083
2782 12:11:23.074203 Set Vref, RX VrefLevel [Byte0]: 57
2783 12:11:23.077839 [Byte1]: 57
2784 12:11:23.082064
2785 12:11:23.082190 Set Vref, RX VrefLevel [Byte0]: 58
2786 12:11:23.085219 [Byte1]: 58
2787 12:11:23.090303
2788 12:11:23.090421 Set Vref, RX VrefLevel [Byte0]: 59
2789 12:11:23.092967 [Byte1]: 59
2790 12:11:23.098179
2791 12:11:23.098292 Set Vref, RX VrefLevel [Byte0]: 60
2792 12:11:23.101440 [Byte1]: 60
2793 12:11:23.105902
2794 12:11:23.106014 Set Vref, RX VrefLevel [Byte0]: 61
2795 12:11:23.109075 [Byte1]: 61
2796 12:11:23.113633
2797 12:11:23.113749 Set Vref, RX VrefLevel [Byte0]: 62
2798 12:11:23.116874 [Byte1]: 62
2799 12:11:23.122034
2800 12:11:23.122172 Set Vref, RX VrefLevel [Byte0]: 63
2801 12:11:23.125326 [Byte1]: 63
2802 12:11:23.129907
2803 12:11:23.130037 Set Vref, RX VrefLevel [Byte0]: 64
2804 12:11:23.133222 [Byte1]: 64
2805 12:11:23.137675
2806 12:11:23.137794 Set Vref, RX VrefLevel [Byte0]: 65
2807 12:11:23.140897 [Byte1]: 65
2808 12:11:23.145354
2809 12:11:23.145483 Set Vref, RX VrefLevel [Byte0]: 66
2810 12:11:23.148649 [Byte1]: 66
2811 12:11:23.153106
2812 12:11:23.153213 Set Vref, RX VrefLevel [Byte0]: 67
2813 12:11:23.156989 [Byte1]: 67
2814 12:11:23.161565
2815 12:11:23.161758 Set Vref, RX VrefLevel [Byte0]: 68
2816 12:11:23.164651 [Byte1]: 68
2817 12:11:23.169280
2818 12:11:23.169379 Set Vref, RX VrefLevel [Byte0]: 69
2819 12:11:23.172849 [Byte1]: 69
2820 12:11:23.177047
2821 12:11:23.177253 Final RX Vref Byte 0 = 53 to rank0
2822 12:11:23.180179 Final RX Vref Byte 1 = 52 to rank0
2823 12:11:23.183993 Final RX Vref Byte 0 = 53 to rank1
2824 12:11:23.186965 Final RX Vref Byte 1 = 52 to rank1==
2825 12:11:23.190674 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 12:11:23.197441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 12:11:23.197590 ==
2828 12:11:23.197701 DQS Delay:
2829 12:11:23.197817 DQS0 = 0, DQS1 = 0
2830 12:11:23.200666 DQM Delay:
2831 12:11:23.200812 DQM0 = 115, DQM1 = 104
2832 12:11:23.203951 DQ Delay:
2833 12:11:23.207178 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2834 12:11:23.210503 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2835 12:11:23.213727 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2836 12:11:23.216952 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2837 12:11:23.217065
2838 12:11:23.217188
2839 12:11:23.224050 [DQSOSCAuto] RK0, (LSB)MR18= 0xffee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2840 12:11:23.227286 CH0 RK0: MR19=303, MR18=FFEE
2841 12:11:23.233744 CH0_RK0: MR19=0x303, MR18=0xFFEE, DQSOSC=410, MR23=63, INC=39, DEC=26
2842 12:11:23.233894
2843 12:11:23.237058 ----->DramcWriteLeveling(PI) begin...
2844 12:11:23.237190 ==
2845 12:11:23.240275 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 12:11:23.244036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 12:11:23.247235 ==
2848 12:11:23.247357 Write leveling (Byte 0): 34 => 34
2849 12:11:23.250563 Write leveling (Byte 1): 30 => 30
2850 12:11:23.253692 DramcWriteLeveling(PI) end<-----
2851 12:11:23.253790
2852 12:11:23.253872 ==
2853 12:11:23.256943 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 12:11:23.264029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 12:11:23.264138 ==
2856 12:11:23.264229 [Gating] SW mode calibration
2857 12:11:23.273579 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 12:11:23.277414 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 12:11:23.280529 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2860 12:11:23.287019 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
2861 12:11:23.290084 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 12:11:23.293701 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 12:11:23.300243 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 12:11:23.303953 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 12:11:23.307047 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2866 12:11:23.313490 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
2867 12:11:23.316772 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2868 12:11:23.320577 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 12:11:23.327148 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 12:11:23.330383 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 12:11:23.333686 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 12:11:23.340050 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 12:11:23.343977 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2874 12:11:23.347086 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2875 12:11:23.353648 1 1 0 | B1->B0 | 2e2e 3e3e | 0 1 | (0 0) (0 0)
2876 12:11:23.356840 1 1 4 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
2877 12:11:23.360572 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 12:11:23.367102 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 12:11:23.370283 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 12:11:23.374131 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 12:11:23.377234 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 12:11:23.383677 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2883 12:11:23.387044 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2884 12:11:23.390520 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:11:23.397181 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:11:23.400721 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:11:23.403817 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:11:23.410282 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:11:23.413502 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:11:23.417192 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:11:23.423721 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:11:23.426917 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:11:23.430074 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:11:23.436705 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 12:11:23.440632 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 12:11:23.443884 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 12:11:23.450369 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 12:11:23.453752 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2899 12:11:23.456857 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2900 12:11:23.460074 Total UI for P1: 0, mck2ui 16
2901 12:11:23.463856 best dqsien dly found for B0: ( 1, 3, 26)
2902 12:11:23.470182 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 12:11:23.470308 Total UI for P1: 0, mck2ui 16
2904 12:11:23.473426 best dqsien dly found for B1: ( 1, 3, 30)
2905 12:11:23.476603 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2906 12:11:23.483984 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2907 12:11:23.484120
2908 12:11:23.487142 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2909 12:11:23.490345 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2910 12:11:23.493691 [Gating] SW calibration Done
2911 12:11:23.493828 ==
2912 12:11:23.497075 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 12:11:23.500060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 12:11:23.500180 ==
2915 12:11:23.503653 RX Vref Scan: 0
2916 12:11:23.503765
2917 12:11:23.503862 RX Vref 0 -> 0, step: 1
2918 12:11:23.503957
2919 12:11:23.506615 RX Delay -40 -> 252, step: 8
2920 12:11:23.510310 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2921 12:11:23.513322 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2922 12:11:23.520104 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2923 12:11:23.523210 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2924 12:11:23.527082 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2925 12:11:23.530349 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2926 12:11:23.533542 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2927 12:11:23.540009 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2928 12:11:23.543247 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2929 12:11:23.546586 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2930 12:11:23.550001 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2931 12:11:23.553638 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2932 12:11:23.560135 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2933 12:11:23.563321 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2934 12:11:23.566520 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2935 12:11:23.570605 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2936 12:11:23.570706 ==
2937 12:11:23.573431 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 12:11:23.580018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 12:11:23.580118 ==
2940 12:11:23.580187 DQS Delay:
2941 12:11:23.580249 DQS0 = 0, DQS1 = 0
2942 12:11:23.583185 DQM Delay:
2943 12:11:23.583297 DQM0 = 115, DQM1 = 106
2944 12:11:23.587124 DQ Delay:
2945 12:11:23.590258 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2946 12:11:23.593743 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2947 12:11:23.596866 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2948 12:11:23.600114 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2949 12:11:23.600205
2950 12:11:23.600272
2951 12:11:23.600334 ==
2952 12:11:23.603158 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 12:11:23.606409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 12:11:23.606501 ==
2955 12:11:23.606569
2956 12:11:23.609653
2957 12:11:23.609766 TX Vref Scan disable
2958 12:11:23.613118 == TX Byte 0 ==
2959 12:11:23.616823 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2960 12:11:23.619820 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2961 12:11:23.623460 == TX Byte 1 ==
2962 12:11:23.626469 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2963 12:11:23.630157 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2964 12:11:23.630278 ==
2965 12:11:23.633329 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 12:11:23.639806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 12:11:23.639935 ==
2968 12:11:23.650750 TX Vref=22, minBit 0, minWin=25, winSum=420
2969 12:11:23.653972 TX Vref=24, minBit 1, minWin=25, winSum=427
2970 12:11:23.657311 TX Vref=26, minBit 4, minWin=26, winSum=431
2971 12:11:23.660482 TX Vref=28, minBit 0, minWin=26, winSum=431
2972 12:11:23.663694 TX Vref=30, minBit 2, minWin=26, winSum=435
2973 12:11:23.670813 TX Vref=32, minBit 0, minWin=26, winSum=431
2974 12:11:23.673956 [TxChooseVref] Worse bit 2, Min win 26, Win sum 435, Final Vref 30
2975 12:11:23.674085
2976 12:11:23.677110 Final TX Range 1 Vref 30
2977 12:11:23.677239
2978 12:11:23.677353 ==
2979 12:11:23.680510 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 12:11:23.683819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 12:11:23.683956 ==
2982 12:11:23.687022
2983 12:11:23.687135
2984 12:11:23.687260 TX Vref Scan disable
2985 12:11:23.690221 == TX Byte 0 ==
2986 12:11:23.694147 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2987 12:11:23.697244 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2988 12:11:23.700420 == TX Byte 1 ==
2989 12:11:23.703737 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2990 12:11:23.706970 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2991 12:11:23.710878
2992 12:11:23.710990 [DATLAT]
2993 12:11:23.711099 Freq=1200, CH0 RK1
2994 12:11:23.711191
2995 12:11:23.713876 DATLAT Default: 0xd
2996 12:11:23.714007 0, 0xFFFF, sum = 0
2997 12:11:23.717292 1, 0xFFFF, sum = 0
2998 12:11:23.717421 2, 0xFFFF, sum = 0
2999 12:11:23.720303 3, 0xFFFF, sum = 0
3000 12:11:23.720412 4, 0xFFFF, sum = 0
3001 12:11:23.723867 5, 0xFFFF, sum = 0
3002 12:11:23.726931 6, 0xFFFF, sum = 0
3003 12:11:23.727070 7, 0xFFFF, sum = 0
3004 12:11:23.730031 8, 0xFFFF, sum = 0
3005 12:11:23.730135 9, 0xFFFF, sum = 0
3006 12:11:23.733583 10, 0xFFFF, sum = 0
3007 12:11:23.733738 11, 0xFFFF, sum = 0
3008 12:11:23.736769 12, 0x0, sum = 1
3009 12:11:23.736906 13, 0x0, sum = 2
3010 12:11:23.740070 14, 0x0, sum = 3
3011 12:11:23.740196 15, 0x0, sum = 4
3012 12:11:23.740333 best_step = 13
3013 12:11:23.743838
3014 12:11:23.743990 ==
3015 12:11:23.746989 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 12:11:23.750233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 12:11:23.750324 ==
3018 12:11:23.750406 RX Vref Scan: 0
3019 12:11:23.750509
3020 12:11:23.753354 RX Vref 0 -> 0, step: 1
3021 12:11:23.753434
3022 12:11:23.756652 RX Delay -21 -> 252, step: 4
3023 12:11:23.759867 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3024 12:11:23.767162 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3025 12:11:23.770231 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3026 12:11:23.773443 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3027 12:11:23.776680 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3028 12:11:23.780045 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3029 12:11:23.787577 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3030 12:11:23.790044 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3031 12:11:23.793291 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3032 12:11:23.797115 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3033 12:11:23.800271 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3034 12:11:23.806670 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3035 12:11:23.809980 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3036 12:11:23.813266 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3037 12:11:23.817159 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3038 12:11:23.820248 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3039 12:11:23.820387 ==
3040 12:11:23.823479 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 12:11:23.830109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 12:11:23.830260 ==
3043 12:11:23.830361 DQS Delay:
3044 12:11:23.833678 DQS0 = 0, DQS1 = 0
3045 12:11:23.833788 DQM Delay:
3046 12:11:23.836875 DQM0 = 114, DQM1 = 104
3047 12:11:23.836988 DQ Delay:
3048 12:11:23.839974 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3049 12:11:23.843534 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3050 12:11:23.846710 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3051 12:11:23.849861 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =114
3052 12:11:23.849993
3053 12:11:23.850100
3054 12:11:23.860081 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 409 ps
3055 12:11:23.860208 CH0 RK1: MR19=403, MR18=1F1
3056 12:11:23.866624 CH0_RK1: MR19=0x403, MR18=0x1F1, DQSOSC=409, MR23=63, INC=39, DEC=26
3057 12:11:23.870431 [RxdqsGatingPostProcess] freq 1200
3058 12:11:23.876420 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3059 12:11:23.879970 best DQS0 dly(2T, 0.5T) = (0, 12)
3060 12:11:23.883217 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 12:11:23.886530 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3062 12:11:23.886659 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 12:11:23.889716 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 12:11:23.893741 best DQS1 dly(2T, 0.5T) = (0, 11)
3065 12:11:23.896998 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 12:11:23.900173 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3067 12:11:23.903404 Pre-setting of DQS Precalculation
3068 12:11:23.909813 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3069 12:11:23.909947 ==
3070 12:11:23.913824 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 12:11:23.916999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 12:11:23.917088 ==
3073 12:11:23.923478 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 12:11:23.926571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3075 12:11:23.936294 [CA 0] Center 38 (8~68) winsize 61
3076 12:11:23.939978 [CA 1] Center 38 (8~68) winsize 61
3077 12:11:23.943007 [CA 2] Center 35 (5~65) winsize 61
3078 12:11:23.946819 [CA 3] Center 34 (4~65) winsize 62
3079 12:11:23.949847 [CA 4] Center 34 (4~65) winsize 62
3080 12:11:23.952888 [CA 5] Center 33 (3~64) winsize 62
3081 12:11:23.953010
3082 12:11:23.956667 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3083 12:11:23.956776
3084 12:11:23.959992 [CATrainingPosCal] consider 1 rank data
3085 12:11:23.963161 u2DelayCellTimex100 = 270/100 ps
3086 12:11:23.966545 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3087 12:11:23.969627 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3088 12:11:23.976767 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3089 12:11:23.979915 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3090 12:11:23.983254 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3091 12:11:23.986447 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3092 12:11:23.986567
3093 12:11:23.989571 CA PerBit enable=1, Macro0, CA PI delay=33
3094 12:11:23.989693
3095 12:11:23.992876 [CBTSetCACLKResult] CA Dly = 33
3096 12:11:23.992992 CS Dly: 6 (0~37)
3097 12:11:23.993112 ==
3098 12:11:23.996770 Dram Type= 6, Freq= 0, CH_1, rank 1
3099 12:11:24.003322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 12:11:24.003484 ==
3101 12:11:24.006582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3102 12:11:24.012983 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3103 12:11:24.022123 [CA 0] Center 38 (8~68) winsize 61
3104 12:11:24.025276 [CA 1] Center 38 (8~68) winsize 61
3105 12:11:24.028470 [CA 2] Center 34 (4~65) winsize 62
3106 12:11:24.031698 [CA 3] Center 34 (4~65) winsize 62
3107 12:11:24.035587 [CA 4] Center 35 (5~65) winsize 61
3108 12:11:24.038728 [CA 5] Center 33 (3~63) winsize 61
3109 12:11:24.038835
3110 12:11:24.041707 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3111 12:11:24.041832
3112 12:11:24.045277 [CATrainingPosCal] consider 2 rank data
3113 12:11:24.048588 u2DelayCellTimex100 = 270/100 ps
3114 12:11:24.052449 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3115 12:11:24.055249 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3116 12:11:24.061898 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3117 12:11:24.065501 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3118 12:11:24.068790 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3119 12:11:24.072014 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3120 12:11:24.072106
3121 12:11:24.075284 CA PerBit enable=1, Macro0, CA PI delay=33
3122 12:11:24.075400
3123 12:11:24.078493 [CBTSetCACLKResult] CA Dly = 33
3124 12:11:24.078603 CS Dly: 7 (0~39)
3125 12:11:24.078697
3126 12:11:24.081638 ----->DramcWriteLeveling(PI) begin...
3127 12:11:24.085471 ==
3128 12:11:24.085588 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 12:11:24.091987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 12:11:24.092120 ==
3131 12:11:24.095209 Write leveling (Byte 0): 27 => 27
3132 12:11:24.098423 Write leveling (Byte 1): 28 => 28
3133 12:11:24.101677 DramcWriteLeveling(PI) end<-----
3134 12:11:24.101811
3135 12:11:24.101929 ==
3136 12:11:24.105004 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 12:11:24.108211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 12:11:24.108337 ==
3139 12:11:24.111452 [Gating] SW mode calibration
3140 12:11:24.118771 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3141 12:11:24.124991 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3142 12:11:24.128066 0 15 0 | B1->B0 | 2626 2323 | 1 0 | (1 1) (0 0)
3143 12:11:24.131214 0 15 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3144 12:11:24.138256 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 12:11:24.141448 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 12:11:24.144628 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 12:11:24.148473 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 12:11:24.154454 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3149 12:11:24.158041 0 15 28 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 0)
3150 12:11:24.161047 1 0 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3151 12:11:24.167870 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3152 12:11:24.171531 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 12:11:24.174627 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 12:11:24.181138 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 12:11:24.184500 1 0 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
3156 12:11:24.188174 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3157 12:11:24.194633 1 0 28 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)
3158 12:11:24.197867 1 1 0 | B1->B0 | 4343 3434 | 0 1 | (0 0) (0 0)
3159 12:11:24.201091 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 12:11:24.207674 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 12:11:24.211561 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 12:11:24.214729 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 12:11:24.221228 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 12:11:24.224398 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 12:11:24.227648 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 12:11:24.234754 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3167 12:11:24.237972 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:11:24.241097 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:11:24.247656 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:11:24.250907 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:11:24.254719 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:11:24.260703 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:11:24.264472 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:11:24.267618 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:11:24.274234 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:11:24.278046 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:11:24.281016 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 12:11:24.284048 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 12:11:24.291020 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 12:11:24.294232 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 12:11:24.297579 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 12:11:24.304076 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3183 12:11:24.307298 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 12:11:24.311197 Total UI for P1: 0, mck2ui 16
3185 12:11:24.314446 best dqsien dly found for B0: ( 1, 4, 0)
3186 12:11:24.317622 Total UI for P1: 0, mck2ui 16
3187 12:11:24.320744 best dqsien dly found for B1: ( 1, 4, 0)
3188 12:11:24.324062 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
3189 12:11:24.327324 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3190 12:11:24.327439
3191 12:11:24.331134 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
3192 12:11:24.334299 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3193 12:11:24.337643 [Gating] SW calibration Done
3194 12:11:24.337732 ==
3195 12:11:24.340901 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 12:11:24.344099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 12:11:24.347405 ==
3198 12:11:24.347521 RX Vref Scan: 0
3199 12:11:24.347627
3200 12:11:24.350556 RX Vref 0 -> 0, step: 1
3201 12:11:24.350681
3202 12:11:24.350777 RX Delay -40 -> 252, step: 8
3203 12:11:24.357715 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3204 12:11:24.361005 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3205 12:11:24.364195 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3206 12:11:24.367827 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3207 12:11:24.370877 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3208 12:11:24.377603 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3209 12:11:24.381215 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3210 12:11:24.384359 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3211 12:11:24.387281 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3212 12:11:24.390896 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3213 12:11:24.397828 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3214 12:11:24.401187 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3215 12:11:24.404386 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3216 12:11:24.407719 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3217 12:11:24.410925 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3218 12:11:24.417997 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3219 12:11:24.418169 ==
3220 12:11:24.421218 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 12:11:24.424442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 12:11:24.424589 ==
3223 12:11:24.424705 DQS Delay:
3224 12:11:24.427663 DQS0 = 0, DQS1 = 0
3225 12:11:24.427754 DQM Delay:
3226 12:11:24.430921 DQM0 = 115, DQM1 = 108
3227 12:11:24.431034 DQ Delay:
3228 12:11:24.434156 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3229 12:11:24.437995 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3230 12:11:24.441291 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
3231 12:11:24.444452 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3232 12:11:24.444567
3233 12:11:24.444674
3234 12:11:24.444786 ==
3235 12:11:24.447728 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 12:11:24.454249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 12:11:24.454384 ==
3238 12:11:24.454502
3239 12:11:24.454606
3240 12:11:24.454720 TX Vref Scan disable
3241 12:11:24.458093 == TX Byte 0 ==
3242 12:11:24.461361 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3243 12:11:24.465177 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3244 12:11:24.468387 == TX Byte 1 ==
3245 12:11:24.471500 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3246 12:11:24.478222 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3247 12:11:24.478368 ==
3248 12:11:24.481298 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 12:11:24.485060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 12:11:24.485198 ==
3251 12:11:24.496218 TX Vref=22, minBit 0, minWin=24, winSum=413
3252 12:11:24.499121 TX Vref=24, minBit 2, minWin=25, winSum=419
3253 12:11:24.502304 TX Vref=26, minBit 0, minWin=26, winSum=425
3254 12:11:24.506046 TX Vref=28, minBit 0, minWin=26, winSum=430
3255 12:11:24.509287 TX Vref=30, minBit 1, minWin=26, winSum=435
3256 12:11:24.512541 TX Vref=32, minBit 2, minWin=26, winSum=432
3257 12:11:24.519540 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 30
3258 12:11:24.519663
3259 12:11:24.522725 Final TX Range 1 Vref 30
3260 12:11:24.522839
3261 12:11:24.522961 ==
3262 12:11:24.525991 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 12:11:24.529231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 12:11:24.529400 ==
3265 12:11:24.532388
3266 12:11:24.532499
3267 12:11:24.532621 TX Vref Scan disable
3268 12:11:24.535798 == TX Byte 0 ==
3269 12:11:24.538882 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3270 12:11:24.542736 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3271 12:11:24.545937 == TX Byte 1 ==
3272 12:11:24.549139 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3273 12:11:24.552406 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3274 12:11:24.552541
3275 12:11:24.555613 [DATLAT]
3276 12:11:24.555724 Freq=1200, CH1 RK0
3277 12:11:24.555830
3278 12:11:24.559398 DATLAT Default: 0xd
3279 12:11:24.559512 0, 0xFFFF, sum = 0
3280 12:11:24.562642 1, 0xFFFF, sum = 0
3281 12:11:24.562755 2, 0xFFFF, sum = 0
3282 12:11:24.565869 3, 0xFFFF, sum = 0
3283 12:11:24.565982 4, 0xFFFF, sum = 0
3284 12:11:24.569039 5, 0xFFFF, sum = 0
3285 12:11:24.569146 6, 0xFFFF, sum = 0
3286 12:11:24.572312 7, 0xFFFF, sum = 0
3287 12:11:24.575538 8, 0xFFFF, sum = 0
3288 12:11:24.575652 9, 0xFFFF, sum = 0
3289 12:11:24.579267 10, 0xFFFF, sum = 0
3290 12:11:24.579383 11, 0xFFFF, sum = 0
3291 12:11:24.582398 12, 0x0, sum = 1
3292 12:11:24.582510 13, 0x0, sum = 2
3293 12:11:24.585425 14, 0x0, sum = 3
3294 12:11:24.585541 15, 0x0, sum = 4
3295 12:11:24.585660 best_step = 13
3296 12:11:24.585768
3297 12:11:24.589076 ==
3298 12:11:24.592138 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 12:11:24.595836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 12:11:24.595953 ==
3301 12:11:24.596049 RX Vref Scan: 1
3302 12:11:24.596137
3303 12:11:24.599566 Set Vref Range= 32 -> 127
3304 12:11:24.599659
3305 12:11:24.602427 RX Vref 32 -> 127, step: 1
3306 12:11:24.602531
3307 12:11:24.605866 RX Delay -13 -> 252, step: 4
3308 12:11:24.605977
3309 12:11:24.609118 Set Vref, RX VrefLevel [Byte0]: 32
3310 12:11:24.612773 [Byte1]: 32
3311 12:11:24.612862
3312 12:11:24.615994 Set Vref, RX VrefLevel [Byte0]: 33
3313 12:11:24.618996 [Byte1]: 33
3314 12:11:24.619076
3315 12:11:24.622328 Set Vref, RX VrefLevel [Byte0]: 34
3316 12:11:24.625499 [Byte1]: 34
3317 12:11:24.630152
3318 12:11:24.630246 Set Vref, RX VrefLevel [Byte0]: 35
3319 12:11:24.633259 [Byte1]: 35
3320 12:11:24.637777
3321 12:11:24.637871 Set Vref, RX VrefLevel [Byte0]: 36
3322 12:11:24.640937 [Byte1]: 36
3323 12:11:24.645503
3324 12:11:24.645627 Set Vref, RX VrefLevel [Byte0]: 37
3325 12:11:24.648757 [Byte1]: 37
3326 12:11:24.653271
3327 12:11:24.653401 Set Vref, RX VrefLevel [Byte0]: 38
3328 12:11:24.657118 [Byte1]: 38
3329 12:11:24.661637
3330 12:11:24.661750 Set Vref, RX VrefLevel [Byte0]: 39
3331 12:11:24.664954 [Byte1]: 39
3332 12:11:24.669403
3333 12:11:24.669496 Set Vref, RX VrefLevel [Byte0]: 40
3334 12:11:24.672636 [Byte1]: 40
3335 12:11:24.677158
3336 12:11:24.677244 Set Vref, RX VrefLevel [Byte0]: 41
3337 12:11:24.680374 [Byte1]: 41
3338 12:11:24.684922
3339 12:11:24.685013 Set Vref, RX VrefLevel [Byte0]: 42
3340 12:11:24.688067 [Byte1]: 42
3341 12:11:24.693114
3342 12:11:24.693210 Set Vref, RX VrefLevel [Byte0]: 43
3343 12:11:24.696083 [Byte1]: 43
3344 12:11:24.700992
3345 12:11:24.701080 Set Vref, RX VrefLevel [Byte0]: 44
3346 12:11:24.704037 [Byte1]: 44
3347 12:11:24.708498
3348 12:11:24.708590 Set Vref, RX VrefLevel [Byte0]: 45
3349 12:11:24.712030 [Byte1]: 45
3350 12:11:24.716343
3351 12:11:24.716436 Set Vref, RX VrefLevel [Byte0]: 46
3352 12:11:24.720073 [Byte1]: 46
3353 12:11:24.724501
3354 12:11:24.724600 Set Vref, RX VrefLevel [Byte0]: 47
3355 12:11:24.727706 [Byte1]: 47
3356 12:11:24.732335
3357 12:11:24.732418 Set Vref, RX VrefLevel [Byte0]: 48
3358 12:11:24.735632 [Byte1]: 48
3359 12:11:24.740063
3360 12:11:24.740147 Set Vref, RX VrefLevel [Byte0]: 49
3361 12:11:24.743240 [Byte1]: 49
3362 12:11:24.747806
3363 12:11:24.747966 Set Vref, RX VrefLevel [Byte0]: 50
3364 12:11:24.751637 [Byte1]: 50
3365 12:11:24.756119
3366 12:11:24.756260 Set Vref, RX VrefLevel [Byte0]: 51
3367 12:11:24.759320 [Byte1]: 51
3368 12:11:24.764028
3369 12:11:24.764140 Set Vref, RX VrefLevel [Byte0]: 52
3370 12:11:24.767140 [Byte1]: 52
3371 12:11:24.771715
3372 12:11:24.771853 Set Vref, RX VrefLevel [Byte0]: 53
3373 12:11:24.774992 [Byte1]: 53
3374 12:11:24.779511
3375 12:11:24.779652 Set Vref, RX VrefLevel [Byte0]: 54
3376 12:11:24.782704 [Byte1]: 54
3377 12:11:24.787280
3378 12:11:24.787430 Set Vref, RX VrefLevel [Byte0]: 55
3379 12:11:24.791071 [Byte1]: 55
3380 12:11:24.795595
3381 12:11:24.795717 Set Vref, RX VrefLevel [Byte0]: 56
3382 12:11:24.798723 [Byte1]: 56
3383 12:11:24.803037
3384 12:11:24.803158 Set Vref, RX VrefLevel [Byte0]: 57
3385 12:11:24.806717 [Byte1]: 57
3386 12:11:24.810966
3387 12:11:24.811108 Set Vref, RX VrefLevel [Byte0]: 58
3388 12:11:24.814897 [Byte1]: 58
3389 12:11:24.819523
3390 12:11:24.819653 Set Vref, RX VrefLevel [Byte0]: 59
3391 12:11:24.822323 [Byte1]: 59
3392 12:11:24.827188
3393 12:11:24.827353 Set Vref, RX VrefLevel [Byte0]: 60
3394 12:11:24.830189 [Byte1]: 60
3395 12:11:24.834795
3396 12:11:24.834944 Set Vref, RX VrefLevel [Byte0]: 61
3397 12:11:24.838098 [Byte1]: 61
3398 12:11:24.842493
3399 12:11:24.842622 Set Vref, RX VrefLevel [Byte0]: 62
3400 12:11:24.846276 [Byte1]: 62
3401 12:11:24.850820
3402 12:11:24.850993 Set Vref, RX VrefLevel [Byte0]: 63
3403 12:11:24.854008 [Byte1]: 63
3404 12:11:24.858558
3405 12:11:24.858707 Set Vref, RX VrefLevel [Byte0]: 64
3406 12:11:24.861830 [Byte1]: 64
3407 12:11:24.866293
3408 12:11:24.866412 Set Vref, RX VrefLevel [Byte0]: 65
3409 12:11:24.869593 [Byte1]: 65
3410 12:11:24.874145
3411 12:11:24.874278 Set Vref, RX VrefLevel [Byte0]: 66
3412 12:11:24.877392 [Byte1]: 66
3413 12:11:24.881905
3414 12:11:24.882012 Set Vref, RX VrefLevel [Byte0]: 67
3415 12:11:24.885147 [Byte1]: 67
3416 12:11:24.890239
3417 12:11:24.890342 Set Vref, RX VrefLevel [Byte0]: 68
3418 12:11:24.893456 [Byte1]: 68
3419 12:11:24.898016
3420 12:11:24.898169 Set Vref, RX VrefLevel [Byte0]: 69
3421 12:11:24.901395 [Byte1]: 69
3422 12:11:24.905918
3423 12:11:24.906054 Set Vref, RX VrefLevel [Byte0]: 70
3424 12:11:24.909032 [Byte1]: 70
3425 12:11:24.913293
3426 12:11:24.913448 Set Vref, RX VrefLevel [Byte0]: 71
3427 12:11:24.916870 [Byte1]: 71
3428 12:11:24.921264
3429 12:11:24.921398 Final RX Vref Byte 0 = 59 to rank0
3430 12:11:24.924761 Final RX Vref Byte 1 = 53 to rank0
3431 12:11:24.928362 Final RX Vref Byte 0 = 59 to rank1
3432 12:11:24.931396 Final RX Vref Byte 1 = 53 to rank1==
3433 12:11:24.935017 Dram Type= 6, Freq= 0, CH_1, rank 0
3434 12:11:24.938113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 12:11:24.941324 ==
3436 12:11:24.941410 DQS Delay:
3437 12:11:24.941476 DQS0 = 0, DQS1 = 0
3438 12:11:24.944579 DQM Delay:
3439 12:11:24.944685 DQM0 = 116, DQM1 = 109
3440 12:11:24.947870 DQ Delay:
3441 12:11:24.951823 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3442 12:11:24.954992 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =114
3443 12:11:24.958294 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3444 12:11:24.961594 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =114
3445 12:11:24.961744
3446 12:11:24.961863
3447 12:11:24.968157 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3448 12:11:24.971363 CH1 RK0: MR19=303, MR18=FCE1
3449 12:11:24.978496 CH1_RK0: MR19=0x303, MR18=0xFCE1, DQSOSC=411, MR23=63, INC=38, DEC=25
3450 12:11:24.978657
3451 12:11:24.981604 ----->DramcWriteLeveling(PI) begin...
3452 12:11:24.981714 ==
3453 12:11:24.984885 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 12:11:24.988082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 12:11:24.988208 ==
3456 12:11:24.991823 Write leveling (Byte 0): 25 => 25
3457 12:11:24.995009 Write leveling (Byte 1): 29 => 29
3458 12:11:24.998266 DramcWriteLeveling(PI) end<-----
3459 12:11:24.998382
3460 12:11:24.998476 ==
3461 12:11:25.001495 Dram Type= 6, Freq= 0, CH_1, rank 1
3462 12:11:25.007999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3463 12:11:25.008138 ==
3464 12:11:25.008240 [Gating] SW mode calibration
3465 12:11:25.018318 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3466 12:11:25.021848 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3467 12:11:25.024787 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3468 12:11:25.031660 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3469 12:11:25.034776 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 12:11:25.038544 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 12:11:25.045235 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3472 12:11:25.048528 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3473 12:11:25.051858 0 15 24 | B1->B0 | 3535 2626 | 0 1 | (0 0) (1 0)
3474 12:11:25.058201 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3475 12:11:25.061500 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3476 12:11:25.064746 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 12:11:25.071776 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3478 12:11:25.075068 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3479 12:11:25.078228 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 12:11:25.084702 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 12:11:25.087944 1 0 24 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
3482 12:11:25.091700 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 12:11:25.098126 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 12:11:25.101379 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 12:11:25.104615 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 12:11:25.111725 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 12:11:25.114327 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 12:11:25.118149 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3489 12:11:25.124520 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3490 12:11:25.127684 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3491 12:11:25.131120 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 12:11:25.134728 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 12:11:25.140800 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 12:11:25.144410 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 12:11:25.147503 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 12:11:25.154248 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 12:11:25.157514 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 12:11:25.161232 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 12:11:25.167806 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 12:11:25.171081 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 12:11:25.174299 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 12:11:25.180833 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 12:11:25.184071 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 12:11:25.187289 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 12:11:25.194353 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3506 12:11:25.197566 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3507 12:11:25.200819 Total UI for P1: 0, mck2ui 16
3508 12:11:25.204082 best dqsien dly found for B0: ( 1, 3, 24)
3509 12:11:25.207315 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 12:11:25.210609 Total UI for P1: 0, mck2ui 16
3511 12:11:25.214392 best dqsien dly found for B1: ( 1, 3, 26)
3512 12:11:25.217565 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3513 12:11:25.220803 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3514 12:11:25.220896
3515 12:11:25.227264 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3516 12:11:25.230522 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3517 12:11:25.233748 [Gating] SW calibration Done
3518 12:11:25.233890 ==
3519 12:11:25.236906 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 12:11:25.240370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 12:11:25.240502 ==
3522 12:11:25.240626 RX Vref Scan: 0
3523 12:11:25.240723
3524 12:11:25.244063 RX Vref 0 -> 0, step: 1
3525 12:11:25.244192
3526 12:11:25.247223 RX Delay -40 -> 252, step: 8
3527 12:11:25.250276 iDelay=192, Bit 0, Center 115 (40 ~ 191) 152
3528 12:11:25.253845 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3529 12:11:25.260285 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3530 12:11:25.263743 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3531 12:11:25.266877 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3532 12:11:25.270135 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3533 12:11:25.274021 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3534 12:11:25.277181 iDelay=192, Bit 7, Center 111 (48 ~ 175) 128
3535 12:11:25.283638 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3536 12:11:25.286965 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3537 12:11:25.290125 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3538 12:11:25.294031 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3539 12:11:25.300443 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3540 12:11:25.303710 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3541 12:11:25.306851 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3542 12:11:25.310027 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3543 12:11:25.310148 ==
3544 12:11:25.313351 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 12:11:25.317410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 12:11:25.320562 ==
3547 12:11:25.320689 DQS Delay:
3548 12:11:25.320784 DQS0 = 0, DQS1 = 0
3549 12:11:25.323743 DQM Delay:
3550 12:11:25.323856 DQM0 = 113, DQM1 = 110
3551 12:11:25.327050 DQ Delay:
3552 12:11:25.330332 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3553 12:11:25.333528 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3554 12:11:25.336918 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3555 12:11:25.340217 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3556 12:11:25.340340
3557 12:11:25.340412
3558 12:11:25.340473 ==
3559 12:11:25.343847 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 12:11:25.346739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 12:11:25.346861 ==
3562 12:11:25.346959
3563 12:11:25.350163
3564 12:11:25.350278 TX Vref Scan disable
3565 12:11:25.353668 == TX Byte 0 ==
3566 12:11:25.356724 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3567 12:11:25.360355 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3568 12:11:25.363229 == TX Byte 1 ==
3569 12:11:25.366934 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3570 12:11:25.370057 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3571 12:11:25.370183 ==
3572 12:11:25.373218 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 12:11:25.380232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 12:11:25.380360 ==
3575 12:11:25.390626 TX Vref=22, minBit 0, minWin=25, winSum=418
3576 12:11:25.394449 TX Vref=24, minBit 1, minWin=25, winSum=426
3577 12:11:25.397058 TX Vref=26, minBit 1, minWin=25, winSum=427
3578 12:11:25.401040 TX Vref=28, minBit 2, minWin=25, winSum=430
3579 12:11:25.404160 TX Vref=30, minBit 0, minWin=27, winSum=436
3580 12:11:25.410610 TX Vref=32, minBit 0, minWin=27, winSum=435
3581 12:11:25.413910 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 30
3582 12:11:25.414045
3583 12:11:25.417127 Final TX Range 1 Vref 30
3584 12:11:25.417264
3585 12:11:25.417379 ==
3586 12:11:25.420442 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 12:11:25.423639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 12:11:25.426821 ==
3589 12:11:25.426974
3590 12:11:25.427086
3591 12:11:25.427197 TX Vref Scan disable
3592 12:11:25.430754 == TX Byte 0 ==
3593 12:11:25.433933 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3594 12:11:25.440358 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3595 12:11:25.440520 == TX Byte 1 ==
3596 12:11:25.443659 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3597 12:11:25.450750 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3598 12:11:25.450922
3599 12:11:25.451030 [DATLAT]
3600 12:11:25.451124 Freq=1200, CH1 RK1
3601 12:11:25.451219
3602 12:11:25.453841 DATLAT Default: 0xd
3603 12:11:25.453950 0, 0xFFFF, sum = 0
3604 12:11:25.456840 1, 0xFFFF, sum = 0
3605 12:11:25.456953 2, 0xFFFF, sum = 0
3606 12:11:25.460444 3, 0xFFFF, sum = 0
3607 12:11:25.463409 4, 0xFFFF, sum = 0
3608 12:11:25.463536 5, 0xFFFF, sum = 0
3609 12:11:25.467210 6, 0xFFFF, sum = 0
3610 12:11:25.467334 7, 0xFFFF, sum = 0
3611 12:11:25.470321 8, 0xFFFF, sum = 0
3612 12:11:25.470433 9, 0xFFFF, sum = 0
3613 12:11:25.473321 10, 0xFFFF, sum = 0
3614 12:11:25.473435 11, 0xFFFF, sum = 0
3615 12:11:25.477086 12, 0x0, sum = 1
3616 12:11:25.477219 13, 0x0, sum = 2
3617 12:11:25.480284 14, 0x0, sum = 3
3618 12:11:25.480385 15, 0x0, sum = 4
3619 12:11:25.483657 best_step = 13
3620 12:11:25.483760
3621 12:11:25.483845 ==
3622 12:11:25.486767 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 12:11:25.490049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 12:11:25.490190 ==
3625 12:11:25.490303 RX Vref Scan: 0
3626 12:11:25.490419
3627 12:11:25.493825 RX Vref 0 -> 0, step: 1
3628 12:11:25.493946
3629 12:11:25.497139 RX Delay -21 -> 252, step: 4
3630 12:11:25.500344 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3631 12:11:25.506796 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3632 12:11:25.509966 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3633 12:11:25.513145 iDelay=191, Bit 3, Center 114 (51 ~ 178) 128
3634 12:11:25.516387 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3635 12:11:25.519719 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3636 12:11:25.526777 iDelay=191, Bit 6, Center 120 (51 ~ 190) 140
3637 12:11:25.529956 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3638 12:11:25.533210 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3639 12:11:25.536434 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3640 12:11:25.539611 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3641 12:11:25.546749 iDelay=191, Bit 11, Center 104 (39 ~ 170) 132
3642 12:11:25.550016 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3643 12:11:25.553158 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3644 12:11:25.556441 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3645 12:11:25.562882 iDelay=191, Bit 15, Center 118 (51 ~ 186) 136
3646 12:11:25.563033 ==
3647 12:11:25.566273 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 12:11:25.569828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 12:11:25.569957 ==
3650 12:11:25.570061 DQS Delay:
3651 12:11:25.573068 DQS0 = 0, DQS1 = 0
3652 12:11:25.573183 DQM Delay:
3653 12:11:25.576110 DQM0 = 113, DQM1 = 110
3654 12:11:25.576220 DQ Delay:
3655 12:11:25.580063 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =114
3656 12:11:25.582804 DQ4 =116, DQ5 =124, DQ6 =120, DQ7 =110
3657 12:11:25.586650 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3658 12:11:25.589978 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3659 12:11:25.590110
3660 12:11:25.590218
3661 12:11:25.599652 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 414 ps
3662 12:11:25.602767 CH1 RK1: MR19=303, MR18=F6FE
3663 12:11:25.605976 CH1_RK1: MR19=0x303, MR18=0xF6FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3664 12:11:25.609838 [RxdqsGatingPostProcess] freq 1200
3665 12:11:25.616312 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3666 12:11:25.619437 best DQS0 dly(2T, 0.5T) = (0, 12)
3667 12:11:25.622637 best DQS1 dly(2T, 0.5T) = (0, 12)
3668 12:11:25.626576 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3669 12:11:25.629708 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3670 12:11:25.632981 best DQS0 dly(2T, 0.5T) = (0, 11)
3671 12:11:25.636195 best DQS1 dly(2T, 0.5T) = (0, 11)
3672 12:11:25.639542 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3673 12:11:25.642725 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3674 12:11:25.642853 Pre-setting of DQS Precalculation
3675 12:11:25.649159 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3676 12:11:25.656123 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3677 12:11:25.662630 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3678 12:11:25.662813
3679 12:11:25.662935
3680 12:11:25.665831 [Calibration Summary] 2400 Mbps
3681 12:11:25.669034 CH 0, Rank 0
3682 12:11:25.669181 SW Impedance : PASS
3683 12:11:25.672673 DUTY Scan : NO K
3684 12:11:25.675720 ZQ Calibration : PASS
3685 12:11:25.675872 Jitter Meter : NO K
3686 12:11:25.679395 CBT Training : PASS
3687 12:11:25.682342 Write leveling : PASS
3688 12:11:25.682482 RX DQS gating : PASS
3689 12:11:25.686042 RX DQ/DQS(RDDQC) : PASS
3690 12:11:25.689104 TX DQ/DQS : PASS
3691 12:11:25.689236 RX DATLAT : PASS
3692 12:11:25.692129 RX DQ/DQS(Engine): PASS
3693 12:11:25.692258 TX OE : NO K
3694 12:11:25.696004 All Pass.
3695 12:11:25.696127
3696 12:11:25.696240 CH 0, Rank 1
3697 12:11:25.699157 SW Impedance : PASS
3698 12:11:25.699269 DUTY Scan : NO K
3699 12:11:25.702391 ZQ Calibration : PASS
3700 12:11:25.705518 Jitter Meter : NO K
3701 12:11:25.705651 CBT Training : PASS
3702 12:11:25.708856 Write leveling : PASS
3703 12:11:25.712738 RX DQS gating : PASS
3704 12:11:25.712840 RX DQ/DQS(RDDQC) : PASS
3705 12:11:25.715907 TX DQ/DQS : PASS
3706 12:11:25.719242 RX DATLAT : PASS
3707 12:11:25.719384 RX DQ/DQS(Engine): PASS
3708 12:11:25.722477 TX OE : NO K
3709 12:11:25.722559 All Pass.
3710 12:11:25.722625
3711 12:11:25.725727 CH 1, Rank 0
3712 12:11:25.725843 SW Impedance : PASS
3713 12:11:25.728985 DUTY Scan : NO K
3714 12:11:25.732062 ZQ Calibration : PASS
3715 12:11:25.732154 Jitter Meter : NO K
3716 12:11:25.735370 CBT Training : PASS
3717 12:11:25.739120 Write leveling : PASS
3718 12:11:25.739233 RX DQS gating : PASS
3719 12:11:25.741881 RX DQ/DQS(RDDQC) : PASS
3720 12:11:25.745758 TX DQ/DQS : PASS
3721 12:11:25.745911 RX DATLAT : PASS
3722 12:11:25.748851 RX DQ/DQS(Engine): PASS
3723 12:11:25.748985 TX OE : NO K
3724 12:11:25.752076 All Pass.
3725 12:11:25.752194
3726 12:11:25.752294 CH 1, Rank 1
3727 12:11:25.755276 SW Impedance : PASS
3728 12:11:25.755399 DUTY Scan : NO K
3729 12:11:25.759250 ZQ Calibration : PASS
3730 12:11:25.762716 Jitter Meter : NO K
3731 12:11:25.762831 CBT Training : PASS
3732 12:11:25.765363 Write leveling : PASS
3733 12:11:25.769058 RX DQS gating : PASS
3734 12:11:25.769180 RX DQ/DQS(RDDQC) : PASS
3735 12:11:25.772234 TX DQ/DQS : PASS
3736 12:11:25.775487 RX DATLAT : PASS
3737 12:11:25.775611 RX DQ/DQS(Engine): PASS
3738 12:11:25.778860 TX OE : NO K
3739 12:11:25.778980 All Pass.
3740 12:11:25.779081
3741 12:11:25.781741 DramC Write-DBI off
3742 12:11:25.785221 PER_BANK_REFRESH: Hybrid Mode
3743 12:11:25.785344 TX_TRACKING: ON
3744 12:11:25.794929 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3745 12:11:25.798548 [FAST_K] Save calibration result to emmc
3746 12:11:25.801576 dramc_set_vcore_voltage set vcore to 650000
3747 12:11:25.805615 Read voltage for 600, 5
3748 12:11:25.805764 Vio18 = 0
3749 12:11:25.805880 Vcore = 650000
3750 12:11:25.808168 Vdram = 0
3751 12:11:25.808286 Vddq = 0
3752 12:11:25.808402 Vmddr = 0
3753 12:11:25.815345 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3754 12:11:25.818577 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3755 12:11:25.821802 MEM_TYPE=3, freq_sel=19
3756 12:11:25.824968 sv_algorithm_assistance_LP4_1600
3757 12:11:25.828469 ============ PULL DRAM RESETB DOWN ============
3758 12:11:25.831559 ========== PULL DRAM RESETB DOWN end =========
3759 12:11:25.838665 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3760 12:11:25.841691 ===================================
3761 12:11:25.845019 LPDDR4 DRAM CONFIGURATION
3762 12:11:25.848229 ===================================
3763 12:11:25.848357 EX_ROW_EN[0] = 0x0
3764 12:11:25.851403 EX_ROW_EN[1] = 0x0
3765 12:11:25.851563 LP4Y_EN = 0x0
3766 12:11:25.855270 WORK_FSP = 0x0
3767 12:11:25.855403 WL = 0x2
3768 12:11:25.858572 RL = 0x2
3769 12:11:25.858686 BL = 0x2
3770 12:11:25.861724 RPST = 0x0
3771 12:11:25.861834 RD_PRE = 0x0
3772 12:11:25.864997 WR_PRE = 0x1
3773 12:11:25.865105 WR_PST = 0x0
3774 12:11:25.868272 DBI_WR = 0x0
3775 12:11:25.868387 DBI_RD = 0x0
3776 12:11:25.871506 OTF = 0x1
3777 12:11:25.874713 ===================================
3778 12:11:25.878012 ===================================
3779 12:11:25.878138 ANA top config
3780 12:11:25.881992 ===================================
3781 12:11:25.885284 DLL_ASYNC_EN = 0
3782 12:11:25.888267 ALL_SLAVE_EN = 1
3783 12:11:25.891382 NEW_RANK_MODE = 1
3784 12:11:25.891549 DLL_IDLE_MODE = 1
3785 12:11:25.895031 LP45_APHY_COMB_EN = 1
3786 12:11:25.898041 TX_ODT_DIS = 1
3787 12:11:25.901960 NEW_8X_MODE = 1
3788 12:11:25.904930 ===================================
3789 12:11:25.907998 ===================================
3790 12:11:25.911586 data_rate = 1200
3791 12:11:25.911728 CKR = 1
3792 12:11:25.914866 DQ_P2S_RATIO = 8
3793 12:11:25.917937 ===================================
3794 12:11:25.921787 CA_P2S_RATIO = 8
3795 12:11:25.925082 DQ_CA_OPEN = 0
3796 12:11:25.928281 DQ_SEMI_OPEN = 0
3797 12:11:25.931520 CA_SEMI_OPEN = 0
3798 12:11:25.931651 CA_FULL_RATE = 0
3799 12:11:25.934711 DQ_CKDIV4_EN = 1
3800 12:11:25.938044 CA_CKDIV4_EN = 1
3801 12:11:25.941323 CA_PREDIV_EN = 0
3802 12:11:25.944516 PH8_DLY = 0
3803 12:11:25.947757 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3804 12:11:25.947911 DQ_AAMCK_DIV = 4
3805 12:11:25.951668 CA_AAMCK_DIV = 4
3806 12:11:25.954872 CA_ADMCK_DIV = 4
3807 12:11:25.958024 DQ_TRACK_CA_EN = 0
3808 12:11:25.961125 CA_PICK = 600
3809 12:11:25.964432 CA_MCKIO = 600
3810 12:11:25.964570 MCKIO_SEMI = 0
3811 12:11:25.967824 PLL_FREQ = 2288
3812 12:11:25.970956 DQ_UI_PI_RATIO = 32
3813 12:11:25.974833 CA_UI_PI_RATIO = 0
3814 12:11:25.978039 ===================================
3815 12:11:25.981224 ===================================
3816 12:11:25.984563 memory_type:LPDDR4
3817 12:11:25.984688 GP_NUM : 10
3818 12:11:25.988313 SRAM_EN : 1
3819 12:11:25.990902 MD32_EN : 0
3820 12:11:25.994725 ===================================
3821 12:11:25.994853 [ANA_INIT] >>>>>>>>>>>>>>
3822 12:11:25.997777 <<<<<< [CONFIGURE PHASE]: ANA_TX
3823 12:11:26.001399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3824 12:11:26.004606 ===================================
3825 12:11:26.007532 data_rate = 1200,PCW = 0X5800
3826 12:11:26.011209 ===================================
3827 12:11:26.014255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3828 12:11:26.021072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3829 12:11:26.024643 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3830 12:11:26.031113 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3831 12:11:26.034347 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3832 12:11:26.037593 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3833 12:11:26.037727 [ANA_INIT] flow start
3834 12:11:26.040773 [ANA_INIT] PLL >>>>>>>>
3835 12:11:26.044651 [ANA_INIT] PLL <<<<<<<<
3836 12:11:26.047925 [ANA_INIT] MIDPI >>>>>>>>
3837 12:11:26.048053 [ANA_INIT] MIDPI <<<<<<<<
3838 12:11:26.051077 [ANA_INIT] DLL >>>>>>>>
3839 12:11:26.051194 [ANA_INIT] flow end
3840 12:11:26.057497 ============ LP4 DIFF to SE enter ============
3841 12:11:26.060701 ============ LP4 DIFF to SE exit ============
3842 12:11:26.063911 [ANA_INIT] <<<<<<<<<<<<<
3843 12:11:26.067170 [Flow] Enable top DCM control >>>>>
3844 12:11:26.071103 [Flow] Enable top DCM control <<<<<
3845 12:11:26.074300 Enable DLL master slave shuffle
3846 12:11:26.077435 ==============================================================
3847 12:11:26.080634 Gating Mode config
3848 12:11:26.083792 ==============================================================
3849 12:11:26.087868 Config description:
3850 12:11:26.097598 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3851 12:11:26.103899 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3852 12:11:26.107481 SELPH_MODE 0: By rank 1: By Phase
3853 12:11:26.113568 ==============================================================
3854 12:11:26.117115 GAT_TRACK_EN = 1
3855 12:11:26.120803 RX_GATING_MODE = 2
3856 12:11:26.123779 RX_GATING_TRACK_MODE = 2
3857 12:11:26.127444 SELPH_MODE = 1
3858 12:11:26.130541 PICG_EARLY_EN = 1
3859 12:11:26.130641 VALID_LAT_VALUE = 1
3860 12:11:26.137018 ==============================================================
3861 12:11:26.140361 Enter into Gating configuration >>>>
3862 12:11:26.143521 Exit from Gating configuration <<<<
3863 12:11:26.147286 Enter into DVFS_PRE_config >>>>>
3864 12:11:26.157120 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3865 12:11:26.160361 Exit from DVFS_PRE_config <<<<<
3866 12:11:26.163705 Enter into PICG configuration >>>>
3867 12:11:26.167512 Exit from PICG configuration <<<<
3868 12:11:26.170097 [RX_INPUT] configuration >>>>>
3869 12:11:26.174160 [RX_INPUT] configuration <<<<<
3870 12:11:26.180421 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3871 12:11:26.183701 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3872 12:11:26.190103 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 12:11:26.197169 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 12:11:26.203669 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 12:11:26.209963 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 12:11:26.213612 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3877 12:11:26.216629 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3878 12:11:26.219704 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3879 12:11:26.226482 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3880 12:11:26.230229 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3881 12:11:26.233311 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3882 12:11:26.236393 ===================================
3883 12:11:26.240246 LPDDR4 DRAM CONFIGURATION
3884 12:11:26.243473 ===================================
3885 12:11:26.243581 EX_ROW_EN[0] = 0x0
3886 12:11:26.246752 EX_ROW_EN[1] = 0x0
3887 12:11:26.246847 LP4Y_EN = 0x0
3888 12:11:26.250038 WORK_FSP = 0x0
3889 12:11:26.253170 WL = 0x2
3890 12:11:26.253265 RL = 0x2
3891 12:11:26.256355 BL = 0x2
3892 12:11:26.256473 RPST = 0x0
3893 12:11:26.259545 RD_PRE = 0x0
3894 12:11:26.259649 WR_PRE = 0x1
3895 12:11:26.263483 WR_PST = 0x0
3896 12:11:26.263576 DBI_WR = 0x0
3897 12:11:26.266513 DBI_RD = 0x0
3898 12:11:26.266622 OTF = 0x1
3899 12:11:26.269806 ===================================
3900 12:11:26.273059 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3901 12:11:26.279701 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3902 12:11:26.282999 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3903 12:11:26.286063 ===================================
3904 12:11:26.289317 LPDDR4 DRAM CONFIGURATION
3905 12:11:26.293187 ===================================
3906 12:11:26.293314 EX_ROW_EN[0] = 0x10
3907 12:11:26.296489 EX_ROW_EN[1] = 0x0
3908 12:11:26.296608 LP4Y_EN = 0x0
3909 12:11:26.299680 WORK_FSP = 0x0
3910 12:11:26.302998 WL = 0x2
3911 12:11:26.303122 RL = 0x2
3912 12:11:26.306192 BL = 0x2
3913 12:11:26.306302 RPST = 0x0
3914 12:11:26.309455 RD_PRE = 0x0
3915 12:11:26.309568 WR_PRE = 0x1
3916 12:11:26.312706 WR_PST = 0x0
3917 12:11:26.312814 DBI_WR = 0x0
3918 12:11:26.316027 DBI_RD = 0x0
3919 12:11:26.316138 OTF = 0x1
3920 12:11:26.319732 ===================================
3921 12:11:26.326341 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3922 12:11:26.330082 nWR fixed to 30
3923 12:11:26.333067 [ModeRegInit_LP4] CH0 RK0
3924 12:11:26.333188 [ModeRegInit_LP4] CH0 RK1
3925 12:11:26.336678 [ModeRegInit_LP4] CH1 RK0
3926 12:11:26.339811 [ModeRegInit_LP4] CH1 RK1
3927 12:11:26.339908 match AC timing 17
3928 12:11:26.346575 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3929 12:11:26.349727 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3930 12:11:26.352905 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3931 12:11:26.359996 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3932 12:11:26.363318 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3933 12:11:26.363460 ==
3934 12:11:26.366673 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 12:11:26.369893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3936 12:11:26.370019 ==
3937 12:11:26.376139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3938 12:11:26.382710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3939 12:11:26.386495 [CA 0] Center 36 (6~66) winsize 61
3940 12:11:26.389746 [CA 1] Center 36 (6~66) winsize 61
3941 12:11:26.393031 [CA 2] Center 34 (4~65) winsize 62
3942 12:11:26.396152 [CA 3] Center 34 (4~65) winsize 62
3943 12:11:26.399416 [CA 4] Center 34 (4~64) winsize 61
3944 12:11:26.402719 [CA 5] Center 33 (3~64) winsize 62
3945 12:11:26.402841
3946 12:11:26.406078 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3947 12:11:26.406184
3948 12:11:26.409792 [CATrainingPosCal] consider 1 rank data
3949 12:11:26.413011 u2DelayCellTimex100 = 270/100 ps
3950 12:11:26.416425 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3951 12:11:26.419691 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3952 12:11:26.423063 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3953 12:11:26.426330 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3954 12:11:26.432413 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3955 12:11:26.435886 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3956 12:11:26.436021
3957 12:11:26.439128 CA PerBit enable=1, Macro0, CA PI delay=33
3958 12:11:26.439241
3959 12:11:26.442219 [CBTSetCACLKResult] CA Dly = 33
3960 12:11:26.442359 CS Dly: 5 (0~36)
3961 12:11:26.442485 ==
3962 12:11:26.445803 Dram Type= 6, Freq= 0, CH_0, rank 1
3963 12:11:26.452497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 12:11:26.452649 ==
3965 12:11:26.455639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3966 12:11:26.462281 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3967 12:11:26.465569 [CA 0] Center 36 (6~66) winsize 61
3968 12:11:26.469021 [CA 1] Center 36 (6~66) winsize 61
3969 12:11:26.472078 [CA 2] Center 34 (4~65) winsize 62
3970 12:11:26.475313 [CA 3] Center 34 (4~64) winsize 61
3971 12:11:26.478708 [CA 4] Center 33 (3~64) winsize 62
3972 12:11:26.482608 [CA 5] Center 33 (3~64) winsize 62
3973 12:11:26.482742
3974 12:11:26.485776 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3975 12:11:26.485893
3976 12:11:26.489003 [CATrainingPosCal] consider 2 rank data
3977 12:11:26.492218 u2DelayCellTimex100 = 270/100 ps
3978 12:11:26.495544 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3979 12:11:26.498700 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3980 12:11:26.505816 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3981 12:11:26.509047 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3982 12:11:26.512275 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3983 12:11:26.515506 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3984 12:11:26.515640
3985 12:11:26.518631 CA PerBit enable=1, Macro0, CA PI delay=33
3986 12:11:26.518752
3987 12:11:26.521868 [CBTSetCACLKResult] CA Dly = 33
3988 12:11:26.521978 CS Dly: 5 (0~36)
3989 12:11:26.522074
3990 12:11:26.525082 ----->DramcWriteLeveling(PI) begin...
3991 12:11:26.528336 ==
3992 12:11:26.531634 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 12:11:26.535318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 12:11:26.535467 ==
3995 12:11:26.538487 Write leveling (Byte 0): 33 => 33
3996 12:11:26.541607 Write leveling (Byte 1): 30 => 30
3997 12:11:26.545223 DramcWriteLeveling(PI) end<-----
3998 12:11:26.545344
3999 12:11:26.545445 ==
4000 12:11:26.548192 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 12:11:26.551986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 12:11:26.552111 ==
4003 12:11:26.554940 [Gating] SW mode calibration
4004 12:11:26.561531 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4005 12:11:26.568532 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4006 12:11:26.571588 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 12:11:26.574754 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 12:11:26.581284 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 12:11:26.584550 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4010 12:11:26.588369 0 9 16 | B1->B0 | 3131 2e2e | 0 0 | (1 1) (1 1)
4011 12:11:26.594898 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4012 12:11:26.598132 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 12:11:26.601261 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 12:11:26.605105 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 12:11:26.611610 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 12:11:26.614864 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 12:11:26.618233 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 12:11:26.624587 0 10 16 | B1->B0 | 3333 3b3b | 0 1 | (1 1) (0 0)
4019 12:11:26.627781 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 12:11:26.631671 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 12:11:26.638224 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 12:11:26.687585 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 12:11:26.687841 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 12:11:26.687999 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 12:11:26.688137 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 12:11:26.688268 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4027 12:11:26.688395 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4028 12:11:26.688521 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 12:11:26.688636 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 12:11:26.688733 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 12:11:26.688822 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 12:11:26.688914 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 12:11:26.691260 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 12:11:26.694500 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 12:11:26.697653 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 12:11:26.704159 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 12:11:26.707508 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 12:11:26.710721 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 12:11:26.717821 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 12:11:26.721043 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 12:11:26.724262 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 12:11:26.730649 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4043 12:11:26.733987 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 12:11:26.737220 Total UI for P1: 0, mck2ui 16
4045 12:11:26.740986 best dqsien dly found for B0: ( 0, 13, 16)
4046 12:11:26.744533 Total UI for P1: 0, mck2ui 16
4047 12:11:26.747559 best dqsien dly found for B1: ( 0, 13, 16)
4048 12:11:26.750636 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4049 12:11:26.753812 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4050 12:11:26.753939
4051 12:11:26.757568 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4052 12:11:26.760655 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4053 12:11:26.764069 [Gating] SW calibration Done
4054 12:11:26.764212 ==
4055 12:11:26.766998 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 12:11:26.770817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 12:11:26.773831 ==
4058 12:11:26.773970 RX Vref Scan: 0
4059 12:11:26.774071
4060 12:11:26.777513 RX Vref 0 -> 0, step: 1
4061 12:11:26.777632
4062 12:11:26.780421 RX Delay -230 -> 252, step: 16
4063 12:11:26.783508 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4064 12:11:26.787440 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4065 12:11:26.790764 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4066 12:11:26.794123 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4067 12:11:26.800630 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4068 12:11:26.803762 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4069 12:11:26.806994 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4070 12:11:26.810260 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4071 12:11:26.816846 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4072 12:11:26.820098 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4073 12:11:26.823318 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4074 12:11:26.826759 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4075 12:11:26.833644 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4076 12:11:26.836868 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4077 12:11:26.839997 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4078 12:11:26.843178 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4079 12:11:26.843327 ==
4080 12:11:26.846604 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 12:11:26.853601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 12:11:26.853770 ==
4083 12:11:26.853888 DQS Delay:
4084 12:11:26.856830 DQS0 = 0, DQS1 = 0
4085 12:11:26.856959 DQM Delay:
4086 12:11:26.857065 DQM0 = 42, DQM1 = 34
4087 12:11:26.860019 DQ Delay:
4088 12:11:26.863286 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4089 12:11:26.867011 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4090 12:11:26.870037 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4091 12:11:26.873080 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =49
4092 12:11:26.873224
4093 12:11:26.873334
4094 12:11:26.873435 ==
4095 12:11:26.876867 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 12:11:26.880019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 12:11:26.880145 ==
4098 12:11:26.880240
4099 12:11:26.880330
4100 12:11:26.883796 TX Vref Scan disable
4101 12:11:26.883912 == TX Byte 0 ==
4102 12:11:26.889840 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4103 12:11:26.893496 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4104 12:11:26.893635 == TX Byte 1 ==
4105 12:11:26.899790 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4106 12:11:26.903146 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4107 12:11:26.903282 ==
4108 12:11:26.906293 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 12:11:26.909678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 12:11:26.909776 ==
4111 12:11:26.912889
4112 12:11:26.912987
4113 12:11:26.913055 TX Vref Scan disable
4114 12:11:26.916886 == TX Byte 0 ==
4115 12:11:26.920023 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4116 12:11:26.926547 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4117 12:11:26.926682 == TX Byte 1 ==
4118 12:11:26.930321 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4119 12:11:26.936643 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4120 12:11:26.936803
4121 12:11:26.936904 [DATLAT]
4122 12:11:26.936995 Freq=600, CH0 RK0
4123 12:11:26.937085
4124 12:11:26.939929 DATLAT Default: 0x9
4125 12:11:26.940062 0, 0xFFFF, sum = 0
4126 12:11:26.943683 1, 0xFFFF, sum = 0
4127 12:11:26.943780 2, 0xFFFF, sum = 0
4128 12:11:26.946868 3, 0xFFFF, sum = 0
4129 12:11:26.950049 4, 0xFFFF, sum = 0
4130 12:11:26.950137 5, 0xFFFF, sum = 0
4131 12:11:26.953232 6, 0xFFFF, sum = 0
4132 12:11:26.953323 7, 0xFFFF, sum = 0
4133 12:11:26.956537 8, 0x0, sum = 1
4134 12:11:26.956626 9, 0x0, sum = 2
4135 12:11:26.956694 10, 0x0, sum = 3
4136 12:11:26.959814 11, 0x0, sum = 4
4137 12:11:26.959900 best_step = 9
4138 12:11:26.959966
4139 12:11:26.960026 ==
4140 12:11:26.963080 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 12:11:26.969652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 12:11:26.969781 ==
4143 12:11:26.969874 RX Vref Scan: 1
4144 12:11:26.969948
4145 12:11:26.973534 RX Vref 0 -> 0, step: 1
4146 12:11:26.973671
4147 12:11:26.976595 RX Delay -195 -> 252, step: 8
4148 12:11:26.976715
4149 12:11:26.979627 Set Vref, RX VrefLevel [Byte0]: 53
4150 12:11:26.983281 [Byte1]: 52
4151 12:11:26.983442
4152 12:11:26.986493 Final RX Vref Byte 0 = 53 to rank0
4153 12:11:26.990160 Final RX Vref Byte 1 = 52 to rank0
4154 12:11:26.993251 Final RX Vref Byte 0 = 53 to rank1
4155 12:11:26.996397 Final RX Vref Byte 1 = 52 to rank1==
4156 12:11:26.999953 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 12:11:27.003113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 12:11:27.003247 ==
4159 12:11:27.006310 DQS Delay:
4160 12:11:27.006428 DQS0 = 0, DQS1 = 0
4161 12:11:27.006525 DQM Delay:
4162 12:11:27.010117 DQM0 = 42, DQM1 = 33
4163 12:11:27.010204 DQ Delay:
4164 12:11:27.013338 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4165 12:11:27.016590 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4166 12:11:27.019859 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4167 12:11:27.022972 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4168 12:11:27.023093
4169 12:11:27.023194
4170 12:11:27.032986 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c1a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
4171 12:11:27.036827 CH0 RK0: MR19=808, MR18=3C1A
4172 12:11:27.040228 CH0_RK0: MR19=0x808, MR18=0x3C1A, DQSOSC=398, MR23=63, INC=165, DEC=110
4173 12:11:27.040355
4174 12:11:27.046420 ----->DramcWriteLeveling(PI) begin...
4175 12:11:27.046539 ==
4176 12:11:27.049640 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 12:11:27.052955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 12:11:27.053144 ==
4179 12:11:27.056745 Write leveling (Byte 0): 31 => 31
4180 12:11:27.059884 Write leveling (Byte 1): 31 => 31
4181 12:11:27.063184 DramcWriteLeveling(PI) end<-----
4182 12:11:27.063284
4183 12:11:27.063361 ==
4184 12:11:27.066290 Dram Type= 6, Freq= 0, CH_0, rank 1
4185 12:11:27.069505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 12:11:27.069600 ==
4187 12:11:27.073464 [Gating] SW mode calibration
4188 12:11:27.079988 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4189 12:11:27.086047 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4190 12:11:27.089584 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 12:11:27.092658 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 12:11:27.099243 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4193 12:11:27.102976 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
4194 12:11:27.105939 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (0 1) (0 0)
4195 12:11:27.109545 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4196 12:11:27.115826 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 12:11:27.119179 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 12:11:27.122358 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 12:11:27.129411 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 12:11:27.132783 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 12:11:27.135924 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4202 12:11:27.142353 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
4203 12:11:27.146134 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 12:11:27.149374 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 12:11:27.155813 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 12:11:27.158959 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 12:11:27.162786 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 12:11:27.169253 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 12:11:27.172565 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 12:11:27.175712 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4211 12:11:27.182224 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 12:11:27.185528 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 12:11:27.189231 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 12:11:27.195373 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 12:11:27.199057 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 12:11:27.202052 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 12:11:27.208969 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 12:11:27.212073 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 12:11:27.215641 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 12:11:27.222689 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 12:11:27.226116 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 12:11:27.229217 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 12:11:27.235553 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 12:11:27.238847 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 12:11:27.241823 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4226 12:11:27.245200 Total UI for P1: 0, mck2ui 16
4227 12:11:27.249051 best dqsien dly found for B0: ( 0, 13, 10)
4228 12:11:27.255489 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4229 12:11:27.258615 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 12:11:27.261836 Total UI for P1: 0, mck2ui 16
4231 12:11:27.265036 best dqsien dly found for B1: ( 0, 13, 14)
4232 12:11:27.268267 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4233 12:11:27.271690 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4234 12:11:27.271866
4235 12:11:27.275309 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4236 12:11:27.278594 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4237 12:11:27.281771 [Gating] SW calibration Done
4238 12:11:27.281907 ==
4239 12:11:27.285123 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 12:11:27.289056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 12:11:27.289189 ==
4242 12:11:27.292065 RX Vref Scan: 0
4243 12:11:27.292178
4244 12:11:27.295294 RX Vref 0 -> 0, step: 1
4245 12:11:27.295430
4246 12:11:27.298678 RX Delay -230 -> 252, step: 16
4247 12:11:27.301582 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4248 12:11:27.305054 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4249 12:11:27.308538 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4250 12:11:27.311591 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4251 12:11:27.318374 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4252 12:11:27.321970 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4253 12:11:27.324881 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4254 12:11:27.328800 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4255 12:11:27.335337 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4256 12:11:27.338591 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4257 12:11:27.341894 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4258 12:11:27.344980 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4259 12:11:27.351640 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4260 12:11:27.355263 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4261 12:11:27.358560 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4262 12:11:27.361824 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4263 12:11:27.361970 ==
4264 12:11:27.365022 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 12:11:27.371654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 12:11:27.371822 ==
4267 12:11:27.371931 DQS Delay:
4268 12:11:27.372026 DQS0 = 0, DQS1 = 0
4269 12:11:27.374756 DQM Delay:
4270 12:11:27.374887 DQM0 = 39, DQM1 = 31
4271 12:11:27.377998 DQ Delay:
4272 12:11:27.381300 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4273 12:11:27.384765 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4274 12:11:27.388004 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4275 12:11:27.391117 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4276 12:11:27.391240
4277 12:11:27.391378
4278 12:11:27.391484 ==
4279 12:11:27.394951 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 12:11:27.398142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 12:11:27.398277 ==
4282 12:11:27.398385
4283 12:11:27.398476
4284 12:11:27.401592 TX Vref Scan disable
4285 12:11:27.401702 == TX Byte 0 ==
4286 12:11:27.408043 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4287 12:11:27.411592 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4288 12:11:27.411748 == TX Byte 1 ==
4289 12:11:27.418055 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4290 12:11:27.421325 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4291 12:11:27.421530 ==
4292 12:11:27.424336 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 12:11:27.428010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 12:11:27.428182 ==
4295 12:11:27.428300
4296 12:11:27.431184
4297 12:11:27.431326 TX Vref Scan disable
4298 12:11:27.434321 == TX Byte 0 ==
4299 12:11:27.438213 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4300 12:11:27.444629 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4301 12:11:27.444781 == TX Byte 1 ==
4302 12:11:27.447858 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4303 12:11:27.454328 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4304 12:11:27.454489
4305 12:11:27.454586 [DATLAT]
4306 12:11:27.454685 Freq=600, CH0 RK1
4307 12:11:27.454780
4308 12:11:27.458165 DATLAT Default: 0x9
4309 12:11:27.458326 0, 0xFFFF, sum = 0
4310 12:11:27.461423 1, 0xFFFF, sum = 0
4311 12:11:27.461512 2, 0xFFFF, sum = 0
4312 12:11:27.464721 3, 0xFFFF, sum = 0
4313 12:11:27.467816 4, 0xFFFF, sum = 0
4314 12:11:27.467963 5, 0xFFFF, sum = 0
4315 12:11:27.471003 6, 0xFFFF, sum = 0
4316 12:11:27.471128 7, 0xFFFF, sum = 0
4317 12:11:27.474319 8, 0x0, sum = 1
4318 12:11:27.474420 9, 0x0, sum = 2
4319 12:11:27.474489 10, 0x0, sum = 3
4320 12:11:27.478099 11, 0x0, sum = 4
4321 12:11:27.478237 best_step = 9
4322 12:11:27.478357
4323 12:11:27.478450 ==
4324 12:11:27.481329 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 12:11:27.487731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 12:11:27.487890 ==
4327 12:11:27.488021 RX Vref Scan: 0
4328 12:11:27.488124
4329 12:11:27.491543 RX Vref 0 -> 0, step: 1
4330 12:11:27.491683
4331 12:11:27.494589 RX Delay -195 -> 252, step: 8
4332 12:11:27.497976 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4333 12:11:27.504233 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4334 12:11:27.507532 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4335 12:11:27.511287 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4336 12:11:27.514501 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4337 12:11:27.521277 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4338 12:11:27.524373 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4339 12:11:27.528017 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4340 12:11:27.531138 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4341 12:11:27.534085 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4342 12:11:27.540943 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4343 12:11:27.544213 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4344 12:11:27.547265 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4345 12:11:27.551335 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4346 12:11:27.557701 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4347 12:11:27.560950 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4348 12:11:27.561054 ==
4349 12:11:27.564133 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 12:11:27.567454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 12:11:27.567575 ==
4352 12:11:27.570697 DQS Delay:
4353 12:11:27.570868 DQS0 = 0, DQS1 = 0
4354 12:11:27.570990 DQM Delay:
4355 12:11:27.573987 DQM0 = 39, DQM1 = 33
4356 12:11:27.574130 DQ Delay:
4357 12:11:27.577352 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4358 12:11:27.581039 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4359 12:11:27.584157 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4360 12:11:27.587336 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4361 12:11:27.587484
4362 12:11:27.587603
4363 12:11:27.597280 [DQSOSCAuto] RK1, (LSB)MR18= 0x4627, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4364 12:11:27.597415 CH0 RK1: MR19=808, MR18=4627
4365 12:11:27.604385 CH0_RK1: MR19=0x808, MR18=0x4627, DQSOSC=396, MR23=63, INC=167, DEC=111
4366 12:11:27.607588 [RxdqsGatingPostProcess] freq 600
4367 12:11:27.614059 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4368 12:11:27.617249 Pre-setting of DQS Precalculation
4369 12:11:27.620482 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4370 12:11:27.620606 ==
4371 12:11:27.623675 Dram Type= 6, Freq= 0, CH_1, rank 0
4372 12:11:27.630654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 12:11:27.630824 ==
4374 12:11:27.634000 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4375 12:11:27.640776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4376 12:11:27.644157 [CA 0] Center 35 (5~65) winsize 61
4377 12:11:27.647527 [CA 1] Center 35 (5~66) winsize 62
4378 12:11:27.650633 [CA 2] Center 34 (3~65) winsize 63
4379 12:11:27.653857 [CA 3] Center 33 (3~64) winsize 62
4380 12:11:27.657199 [CA 4] Center 34 (3~65) winsize 63
4381 12:11:27.660317 [CA 5] Center 33 (2~64) winsize 63
4382 12:11:27.660450
4383 12:11:27.663619 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4384 12:11:27.663747
4385 12:11:27.667422 [CATrainingPosCal] consider 1 rank data
4386 12:11:27.670109 u2DelayCellTimex100 = 270/100 ps
4387 12:11:27.673971 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4388 12:11:27.677203 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4389 12:11:27.683617 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4390 12:11:27.686895 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4391 12:11:27.690045 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4392 12:11:27.693329 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4393 12:11:27.693521
4394 12:11:27.697214 CA PerBit enable=1, Macro0, CA PI delay=33
4395 12:11:27.697312
4396 12:11:27.700346 [CBTSetCACLKResult] CA Dly = 33
4397 12:11:27.700470 CS Dly: 4 (0~35)
4398 12:11:27.703581 ==
4399 12:11:27.703691 Dram Type= 6, Freq= 0, CH_1, rank 1
4400 12:11:27.709904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 12:11:27.710057 ==
4402 12:11:27.713809 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4403 12:11:27.720170 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4404 12:11:27.723495 [CA 0] Center 35 (6~65) winsize 60
4405 12:11:27.727299 [CA 1] Center 35 (5~65) winsize 61
4406 12:11:27.730613 [CA 2] Center 34 (4~65) winsize 62
4407 12:11:27.733755 [CA 3] Center 33 (3~64) winsize 62
4408 12:11:27.737004 [CA 4] Center 34 (4~65) winsize 62
4409 12:11:27.740697 [CA 5] Center 33 (3~64) winsize 62
4410 12:11:27.740845
4411 12:11:27.743599 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4412 12:11:27.743722
4413 12:11:27.747302 [CATrainingPosCal] consider 2 rank data
4414 12:11:27.750173 u2DelayCellTimex100 = 270/100 ps
4415 12:11:27.753831 CA0 delay=35 (6~65),Diff = 2 PI (19 cell)
4416 12:11:27.757599 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4417 12:11:27.763832 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4418 12:11:27.767109 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4419 12:11:27.770237 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4420 12:11:27.773464 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4421 12:11:27.773604
4422 12:11:27.776800 CA PerBit enable=1, Macro0, CA PI delay=33
4423 12:11:27.776894
4424 12:11:27.779953 [CBTSetCACLKResult] CA Dly = 33
4425 12:11:27.780035 CS Dly: 4 (0~36)
4426 12:11:27.780113
4427 12:11:27.786485 ----->DramcWriteLeveling(PI) begin...
4428 12:11:27.786603 ==
4429 12:11:27.790229 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 12:11:27.793570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 12:11:27.793663 ==
4432 12:11:27.796738 Write leveling (Byte 0): 30 => 30
4433 12:11:27.799955 Write leveling (Byte 1): 32 => 32
4434 12:11:27.803198 DramcWriteLeveling(PI) end<-----
4435 12:11:27.803328
4436 12:11:27.803441 ==
4437 12:11:27.807077 Dram Type= 6, Freq= 0, CH_1, rank 0
4438 12:11:27.809854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 12:11:27.809952 ==
4440 12:11:27.813494 [Gating] SW mode calibration
4441 12:11:27.819899 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4442 12:11:27.826361 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4443 12:11:27.829716 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4444 12:11:27.832905 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4445 12:11:27.839955 0 9 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4446 12:11:27.843217 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4447 12:11:27.846379 0 9 16 | B1->B0 | 2929 2828 | 0 0 | (0 0) (0 0)
4448 12:11:27.853052 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 12:11:27.856088 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 12:11:27.859671 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 12:11:27.866848 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 12:11:27.869690 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4453 12:11:27.872963 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 12:11:27.876071 0 10 12 | B1->B0 | 2828 2c2c | 0 0 | (0 0) (0 0)
4455 12:11:27.883108 0 10 16 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
4456 12:11:27.886354 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 12:11:27.889571 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 12:11:27.896006 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 12:11:27.899301 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 12:11:27.902491 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 12:11:27.909615 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 12:11:27.912677 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 12:11:27.915839 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 12:11:27.923011 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 12:11:27.925699 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 12:11:27.929498 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 12:11:27.936025 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 12:11:27.939312 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 12:11:27.942465 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 12:11:27.949538 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 12:11:27.952775 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 12:11:27.955848 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 12:11:27.962347 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 12:11:27.966068 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 12:11:27.969125 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 12:11:27.975819 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 12:11:27.978988 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 12:11:27.982170 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 12:11:27.989134 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 12:11:27.989306 Total UI for P1: 0, mck2ui 16
4481 12:11:27.995511 best dqsien dly found for B0: ( 0, 13, 14)
4482 12:11:27.995628 Total UI for P1: 0, mck2ui 16
4483 12:11:27.998789 best dqsien dly found for B1: ( 0, 13, 14)
4484 12:11:28.005890 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4485 12:11:28.009050 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4486 12:11:28.009147
4487 12:11:28.012334 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4488 12:11:28.015472 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4489 12:11:28.018689 [Gating] SW calibration Done
4490 12:11:28.018826 ==
4491 12:11:28.021987 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 12:11:28.025106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 12:11:28.025229 ==
4494 12:11:28.029035 RX Vref Scan: 0
4495 12:11:28.029152
4496 12:11:28.029264 RX Vref 0 -> 0, step: 1
4497 12:11:28.029357
4498 12:11:28.032294 RX Delay -230 -> 252, step: 16
4499 12:11:28.038698 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4500 12:11:28.041887 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4501 12:11:28.045084 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4502 12:11:28.048862 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4503 12:11:28.052169 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4504 12:11:28.058599 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4505 12:11:28.062053 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4506 12:11:28.065481 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4507 12:11:28.068330 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4508 12:11:28.075149 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4509 12:11:28.078256 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4510 12:11:28.081992 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4511 12:11:28.085179 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4512 12:11:28.091642 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4513 12:11:28.095333 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4514 12:11:28.098621 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4515 12:11:28.098763 ==
4516 12:11:28.101849 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 12:11:28.105161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 12:11:28.105291 ==
4519 12:11:28.108292 DQS Delay:
4520 12:11:28.108400 DQS0 = 0, DQS1 = 0
4521 12:11:28.111516 DQM Delay:
4522 12:11:28.111625 DQM0 = 44, DQM1 = 36
4523 12:11:28.111717 DQ Delay:
4524 12:11:28.114616 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4525 12:11:28.118004 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4526 12:11:28.121704 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4527 12:11:28.124898 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4528 12:11:28.125011
4529 12:11:28.125110
4530 12:11:28.128046 ==
4531 12:11:28.131838 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 12:11:28.135047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 12:11:28.135168 ==
4534 12:11:28.135268
4535 12:11:28.135411
4536 12:11:28.138225 TX Vref Scan disable
4537 12:11:28.138354 == TX Byte 0 ==
4538 12:11:28.141386 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4539 12:11:28.148376 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4540 12:11:28.148546 == TX Byte 1 ==
4541 12:11:28.155063 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4542 12:11:28.158270 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4543 12:11:28.158430 ==
4544 12:11:28.161442 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 12:11:28.164670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 12:11:28.164829 ==
4547 12:11:28.164928
4548 12:11:28.165017
4549 12:11:28.167778 TX Vref Scan disable
4550 12:11:28.171023 == TX Byte 0 ==
4551 12:11:28.174611 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4552 12:11:28.177561 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4553 12:11:28.181302 == TX Byte 1 ==
4554 12:11:28.184882 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4555 12:11:28.188049 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4556 12:11:28.188221
4557 12:11:28.190992 [DATLAT]
4558 12:11:28.191136 Freq=600, CH1 RK0
4559 12:11:28.191236
4560 12:11:28.194870 DATLAT Default: 0x9
4561 12:11:28.195026 0, 0xFFFF, sum = 0
4562 12:11:28.198108 1, 0xFFFF, sum = 0
4563 12:11:28.198231 2, 0xFFFF, sum = 0
4564 12:11:28.200735 3, 0xFFFF, sum = 0
4565 12:11:28.200845 4, 0xFFFF, sum = 0
4566 12:11:28.204636 5, 0xFFFF, sum = 0
4567 12:11:28.204775 6, 0xFFFF, sum = 0
4568 12:11:28.207874 7, 0xFFFF, sum = 0
4569 12:11:28.208007 8, 0x0, sum = 1
4570 12:11:28.211146 9, 0x0, sum = 2
4571 12:11:28.211269 10, 0x0, sum = 3
4572 12:11:28.214214 11, 0x0, sum = 4
4573 12:11:28.214322 best_step = 9
4574 12:11:28.214393
4575 12:11:28.214455 ==
4576 12:11:28.217505 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 12:11:28.221315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 12:11:28.224529 ==
4579 12:11:28.224635 RX Vref Scan: 1
4580 12:11:28.224705
4581 12:11:28.227690 RX Vref 0 -> 0, step: 1
4582 12:11:28.227783
4583 12:11:28.230864 RX Delay -179 -> 252, step: 8
4584 12:11:28.231003
4585 12:11:28.234105 Set Vref, RX VrefLevel [Byte0]: 59
4586 12:11:28.237267 [Byte1]: 53
4587 12:11:28.237403
4588 12:11:28.240621 Final RX Vref Byte 0 = 59 to rank0
4589 12:11:28.243829 Final RX Vref Byte 1 = 53 to rank0
4590 12:11:28.247181 Final RX Vref Byte 0 = 59 to rank1
4591 12:11:28.250943 Final RX Vref Byte 1 = 53 to rank1==
4592 12:11:28.254146 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 12:11:28.257340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 12:11:28.257482 ==
4595 12:11:28.260653 DQS Delay:
4596 12:11:28.260814 DQS0 = 0, DQS1 = 0
4597 12:11:28.260930 DQM Delay:
4598 12:11:28.263924 DQM0 = 40, DQM1 = 33
4599 12:11:28.264067 DQ Delay:
4600 12:11:28.267184 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4601 12:11:28.270974 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4602 12:11:28.274212 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4603 12:11:28.277425 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4604 12:11:28.277610
4605 12:11:28.277718
4606 12:11:28.287084 [DQSOSCAuto] RK0, (LSB)MR18= 0x4309, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4607 12:11:28.287273 CH1 RK0: MR19=808, MR18=4309
4608 12:11:28.293900 CH1_RK0: MR19=0x808, MR18=0x4309, DQSOSC=397, MR23=63, INC=166, DEC=110
4609 12:11:28.294066
4610 12:11:28.296898 ----->DramcWriteLeveling(PI) begin...
4611 12:11:28.300553 ==
4612 12:11:28.303846 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 12:11:28.307152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 12:11:28.307271 ==
4615 12:11:28.310328 Write leveling (Byte 0): 30 => 30
4616 12:11:28.313703 Write leveling (Byte 1): 29 => 29
4617 12:11:28.317310 DramcWriteLeveling(PI) end<-----
4618 12:11:28.317443
4619 12:11:28.317545 ==
4620 12:11:28.320628 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 12:11:28.323921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 12:11:28.324040 ==
4623 12:11:28.327043 [Gating] SW mode calibration
4624 12:11:28.333509 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4625 12:11:28.339907 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4626 12:11:28.343807 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4627 12:11:28.346918 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 12:11:28.350322 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4629 12:11:28.356738 0 9 12 | B1->B0 | 3131 2c2c | 1 1 | (1 1) (1 0)
4630 12:11:28.359896 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 12:11:28.363786 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 12:11:28.370193 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 12:11:28.373433 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4634 12:11:28.376723 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4635 12:11:28.383047 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 12:11:28.386890 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4637 12:11:28.389940 0 10 12 | B1->B0 | 2e2e 3c3c | 1 0 | (0 0) (0 0)
4638 12:11:28.396588 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4639 12:11:28.400277 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 12:11:28.403428 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 12:11:28.410198 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 12:11:28.413385 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 12:11:28.416596 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 12:11:28.422925 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 12:11:28.426874 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4646 12:11:28.430053 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4647 12:11:28.436400 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 12:11:28.439758 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 12:11:28.442913 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 12:11:28.450006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 12:11:28.453241 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 12:11:28.456393 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 12:11:28.462833 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 12:11:28.466304 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 12:11:28.469297 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 12:11:28.475957 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 12:11:28.479659 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 12:11:28.482827 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 12:11:28.489150 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 12:11:28.492336 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 12:11:28.496194 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4662 12:11:28.502875 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 12:11:28.503028 Total UI for P1: 0, mck2ui 16
4664 12:11:28.506042 best dqsien dly found for B0: ( 0, 13, 12)
4665 12:11:28.509051 Total UI for P1: 0, mck2ui 16
4666 12:11:28.512688 best dqsien dly found for B1: ( 0, 13, 14)
4667 12:11:28.518919 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4668 12:11:28.522703 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4669 12:11:28.522837
4670 12:11:28.525914 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4671 12:11:28.529125 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4672 12:11:28.532405 [Gating] SW calibration Done
4673 12:11:28.532530 ==
4674 12:11:28.535639 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 12:11:28.538802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 12:11:28.538933 ==
4677 12:11:28.542053 RX Vref Scan: 0
4678 12:11:28.542182
4679 12:11:28.542282 RX Vref 0 -> 0, step: 1
4680 12:11:28.542389
4681 12:11:28.545896 RX Delay -230 -> 252, step: 16
4682 12:11:28.549123 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4683 12:11:28.555770 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4684 12:11:28.559037 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4685 12:11:28.562264 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4686 12:11:28.565542 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4687 12:11:28.572050 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4688 12:11:28.575368 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4689 12:11:28.578679 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4690 12:11:28.581970 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4691 12:11:28.585182 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4692 12:11:28.592335 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4693 12:11:28.595625 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4694 12:11:28.598894 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4695 12:11:28.601585 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4696 12:11:28.608675 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4697 12:11:28.611837 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4698 12:11:28.611961 ==
4699 12:11:28.615431 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 12:11:28.618363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 12:11:28.618475 ==
4702 12:11:28.622068 DQS Delay:
4703 12:11:28.622159 DQS0 = 0, DQS1 = 0
4704 12:11:28.625006 DQM Delay:
4705 12:11:28.625129 DQM0 = 40, DQM1 = 36
4706 12:11:28.625238 DQ Delay:
4707 12:11:28.628831 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4708 12:11:28.632075 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4709 12:11:28.635201 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4710 12:11:28.638426 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4711 12:11:28.638551
4712 12:11:28.638650
4713 12:11:28.638751 ==
4714 12:11:28.641667 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 12:11:28.648223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 12:11:28.648367 ==
4717 12:11:28.648519
4718 12:11:28.648621
4719 12:11:28.651359 TX Vref Scan disable
4720 12:11:28.651532 == TX Byte 0 ==
4721 12:11:28.654603 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4722 12:11:28.661734 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4723 12:11:28.661876 == TX Byte 1 ==
4724 12:11:28.668107 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4725 12:11:28.671414 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4726 12:11:28.671540 ==
4727 12:11:28.674666 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 12:11:28.677827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 12:11:28.677946 ==
4730 12:11:28.678043
4731 12:11:28.678135
4732 12:11:28.681738 TX Vref Scan disable
4733 12:11:28.684924 == TX Byte 0 ==
4734 12:11:28.688119 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4735 12:11:28.691180 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4736 12:11:28.694493 == TX Byte 1 ==
4737 12:11:28.698327 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4738 12:11:28.701642 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4739 12:11:28.701761
4740 12:11:28.704821 [DATLAT]
4741 12:11:28.704936 Freq=600, CH1 RK1
4742 12:11:28.705033
4743 12:11:28.708116 DATLAT Default: 0x9
4744 12:11:28.708204 0, 0xFFFF, sum = 0
4745 12:11:28.711197 1, 0xFFFF, sum = 0
4746 12:11:28.711317 2, 0xFFFF, sum = 0
4747 12:11:28.714894 3, 0xFFFF, sum = 0
4748 12:11:28.715041 4, 0xFFFF, sum = 0
4749 12:11:28.717911 5, 0xFFFF, sum = 0
4750 12:11:28.718054 6, 0xFFFF, sum = 0
4751 12:11:28.721599 7, 0xFFFF, sum = 0
4752 12:11:28.721690 8, 0x0, sum = 1
4753 12:11:28.724747 9, 0x0, sum = 2
4754 12:11:28.724854 10, 0x0, sum = 3
4755 12:11:28.727889 11, 0x0, sum = 4
4756 12:11:28.727993 best_step = 9
4757 12:11:28.728090
4758 12:11:28.728213 ==
4759 12:11:28.731358 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 12:11:28.734603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 12:11:28.737587 ==
4762 12:11:28.737749 RX Vref Scan: 0
4763 12:11:28.737895
4764 12:11:28.741353 RX Vref 0 -> 0, step: 1
4765 12:11:28.741463
4766 12:11:28.744650 RX Delay -179 -> 252, step: 8
4767 12:11:28.747803 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4768 12:11:28.751050 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4769 12:11:28.757662 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4770 12:11:28.761352 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4771 12:11:28.764531 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4772 12:11:28.767807 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4773 12:11:28.774064 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4774 12:11:28.777952 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4775 12:11:28.780570 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4776 12:11:28.784387 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4777 12:11:28.787559 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4778 12:11:28.793963 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4779 12:11:28.797221 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4780 12:11:28.801031 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4781 12:11:28.804299 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4782 12:11:28.810796 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4783 12:11:28.810952 ==
4784 12:11:28.814017 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 12:11:28.817183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 12:11:28.817297 ==
4787 12:11:28.817371 DQS Delay:
4788 12:11:28.820834 DQS0 = 0, DQS1 = 0
4789 12:11:28.820950 DQM Delay:
4790 12:11:28.823705 DQM0 = 38, DQM1 = 33
4791 12:11:28.823818 DQ Delay:
4792 12:11:28.827553 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4793 12:11:28.830579 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4794 12:11:28.833709 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4795 12:11:28.837357 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4796 12:11:28.837483
4797 12:11:28.837583
4798 12:11:28.847214 [DQSOSCAuto] RK1, (LSB)MR18= 0x3947, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4799 12:11:28.847391 CH1 RK1: MR19=808, MR18=3947
4800 12:11:28.853789 CH1_RK1: MR19=0x808, MR18=0x3947, DQSOSC=396, MR23=63, INC=167, DEC=111
4801 12:11:28.857016 [RxdqsGatingPostProcess] freq 600
4802 12:11:28.864051 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4803 12:11:28.867225 Pre-setting of DQS Precalculation
4804 12:11:28.870531 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4805 12:11:28.876994 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4806 12:11:28.886774 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4807 12:11:28.886930
4808 12:11:28.887037
4809 12:11:28.887135 [Calibration Summary] 1200 Mbps
4810 12:11:28.890628 CH 0, Rank 0
4811 12:11:28.890764 SW Impedance : PASS
4812 12:11:28.893872 DUTY Scan : NO K
4813 12:11:28.896991 ZQ Calibration : PASS
4814 12:11:28.897114 Jitter Meter : NO K
4815 12:11:28.900304 CBT Training : PASS
4816 12:11:28.903459 Write leveling : PASS
4817 12:11:28.903581 RX DQS gating : PASS
4818 12:11:28.906593 RX DQ/DQS(RDDQC) : PASS
4819 12:11:28.910333 TX DQ/DQS : PASS
4820 12:11:28.910449 RX DATLAT : PASS
4821 12:11:28.913524 RX DQ/DQS(Engine): PASS
4822 12:11:28.916702 TX OE : NO K
4823 12:11:28.916825 All Pass.
4824 12:11:28.916921
4825 12:11:28.917030 CH 0, Rank 1
4826 12:11:28.919983 SW Impedance : PASS
4827 12:11:28.923248 DUTY Scan : NO K
4828 12:11:28.923369 ZQ Calibration : PASS
4829 12:11:28.926982 Jitter Meter : NO K
4830 12:11:28.929998 CBT Training : PASS
4831 12:11:28.930119 Write leveling : PASS
4832 12:11:28.933488 RX DQS gating : PASS
4833 12:11:28.933616 RX DQ/DQS(RDDQC) : PASS
4834 12:11:28.936639 TX DQ/DQS : PASS
4835 12:11:28.940270 RX DATLAT : PASS
4836 12:11:28.940396 RX DQ/DQS(Engine): PASS
4837 12:11:28.943235 TX OE : NO K
4838 12:11:28.943364 All Pass.
4839 12:11:28.943449
4840 12:11:28.946879 CH 1, Rank 0
4841 12:11:28.946994 SW Impedance : PASS
4842 12:11:28.949912 DUTY Scan : NO K
4843 12:11:28.953405 ZQ Calibration : PASS
4844 12:11:28.953538 Jitter Meter : NO K
4845 12:11:28.956585 CBT Training : PASS
4846 12:11:28.959829 Write leveling : PASS
4847 12:11:28.959949 RX DQS gating : PASS
4848 12:11:28.963167 RX DQ/DQS(RDDQC) : PASS
4849 12:11:28.966271 TX DQ/DQS : PASS
4850 12:11:28.966373 RX DATLAT : PASS
4851 12:11:28.970332 RX DQ/DQS(Engine): PASS
4852 12:11:28.973329 TX OE : NO K
4853 12:11:28.973439 All Pass.
4854 12:11:28.973533
4855 12:11:28.973616 CH 1, Rank 1
4856 12:11:28.976659 SW Impedance : PASS
4857 12:11:28.979938 DUTY Scan : NO K
4858 12:11:28.980038 ZQ Calibration : PASS
4859 12:11:28.983090 Jitter Meter : NO K
4860 12:11:28.986245 CBT Training : PASS
4861 12:11:28.986350 Write leveling : PASS
4862 12:11:28.989520 RX DQS gating : PASS
4863 12:11:28.989645 RX DQ/DQS(RDDQC) : PASS
4864 12:11:28.993350 TX DQ/DQS : PASS
4865 12:11:28.996733 RX DATLAT : PASS
4866 12:11:28.996854 RX DQ/DQS(Engine): PASS
4867 12:11:28.999897 TX OE : NO K
4868 12:11:28.999995 All Pass.
4869 12:11:29.000107
4870 12:11:29.003117 DramC Write-DBI off
4871 12:11:29.006265 PER_BANK_REFRESH: Hybrid Mode
4872 12:11:29.006385 TX_TRACKING: ON
4873 12:11:29.016611 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4874 12:11:29.019960 [FAST_K] Save calibration result to emmc
4875 12:11:29.023252 dramc_set_vcore_voltage set vcore to 662500
4876 12:11:29.026385 Read voltage for 933, 3
4877 12:11:29.026491 Vio18 = 0
4878 12:11:29.026562 Vcore = 662500
4879 12:11:29.029574 Vdram = 0
4880 12:11:29.029666 Vddq = 0
4881 12:11:29.029735 Vmddr = 0
4882 12:11:29.036512 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4883 12:11:29.039560 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4884 12:11:29.043191 MEM_TYPE=3, freq_sel=17
4885 12:11:29.046302 sv_algorithm_assistance_LP4_1600
4886 12:11:29.049356 ============ PULL DRAM RESETB DOWN ============
4887 12:11:29.056182 ========== PULL DRAM RESETB DOWN end =========
4888 12:11:29.059294 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4889 12:11:29.062709 ===================================
4890 12:11:29.066069 LPDDR4 DRAM CONFIGURATION
4891 12:11:29.069265 ===================================
4892 12:11:29.069407 EX_ROW_EN[0] = 0x0
4893 12:11:29.072653 EX_ROW_EN[1] = 0x0
4894 12:11:29.072766 LP4Y_EN = 0x0
4895 12:11:29.075801 WORK_FSP = 0x0
4896 12:11:29.075889 WL = 0x3
4897 12:11:29.079143 RL = 0x3
4898 12:11:29.079254 BL = 0x2
4899 12:11:29.082981 RPST = 0x0
4900 12:11:29.083095 RD_PRE = 0x0
4901 12:11:29.086265 WR_PRE = 0x1
4902 12:11:29.086376 WR_PST = 0x0
4903 12:11:29.089504 DBI_WR = 0x0
4904 12:11:29.092622 DBI_RD = 0x0
4905 12:11:29.092716 OTF = 0x1
4906 12:11:29.095754 ===================================
4907 12:11:29.099699 ===================================
4908 12:11:29.099822 ANA top config
4909 12:11:29.102962 ===================================
4910 12:11:29.106102 DLL_ASYNC_EN = 0
4911 12:11:29.109320 ALL_SLAVE_EN = 1
4912 12:11:29.112538 NEW_RANK_MODE = 1
4913 12:11:29.115784 DLL_IDLE_MODE = 1
4914 12:11:29.115917 LP45_APHY_COMB_EN = 1
4915 12:11:29.119614 TX_ODT_DIS = 1
4916 12:11:29.122956 NEW_8X_MODE = 1
4917 12:11:29.125571 ===================================
4918 12:11:29.128866 ===================================
4919 12:11:29.132732 data_rate = 1866
4920 12:11:29.135932 CKR = 1
4921 12:11:29.136066 DQ_P2S_RATIO = 8
4922 12:11:29.139184 ===================================
4923 12:11:29.142321 CA_P2S_RATIO = 8
4924 12:11:29.145878 DQ_CA_OPEN = 0
4925 12:11:29.148802 DQ_SEMI_OPEN = 0
4926 12:11:29.152651 CA_SEMI_OPEN = 0
4927 12:11:29.155719 CA_FULL_RATE = 0
4928 12:11:29.155835 DQ_CKDIV4_EN = 1
4929 12:11:29.159251 CA_CKDIV4_EN = 1
4930 12:11:29.162276 CA_PREDIV_EN = 0
4931 12:11:29.166016 PH8_DLY = 0
4932 12:11:29.169121 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4933 12:11:29.172056 DQ_AAMCK_DIV = 4
4934 12:11:29.172193 CA_AAMCK_DIV = 4
4935 12:11:29.175937 CA_ADMCK_DIV = 4
4936 12:11:29.178922 DQ_TRACK_CA_EN = 0
4937 12:11:29.182201 CA_PICK = 933
4938 12:11:29.185421 CA_MCKIO = 933
4939 12:11:29.188645 MCKIO_SEMI = 0
4940 12:11:29.192522 PLL_FREQ = 3732
4941 12:11:29.192645 DQ_UI_PI_RATIO = 32
4942 12:11:29.195638 CA_UI_PI_RATIO = 0
4943 12:11:29.198840 ===================================
4944 12:11:29.202002 ===================================
4945 12:11:29.205269 memory_type:LPDDR4
4946 12:11:29.209103 GP_NUM : 10
4947 12:11:29.209227 SRAM_EN : 1
4948 12:11:29.212405 MD32_EN : 0
4949 12:11:29.215583 ===================================
4950 12:11:29.215694 [ANA_INIT] >>>>>>>>>>>>>>
4951 12:11:29.218711 <<<<<< [CONFIGURE PHASE]: ANA_TX
4952 12:11:29.221910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4953 12:11:29.225521 ===================================
4954 12:11:29.228519 data_rate = 1866,PCW = 0X8f00
4955 12:11:29.232329 ===================================
4956 12:11:29.235512 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4957 12:11:29.242221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 12:11:29.248684 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4959 12:11:29.251810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4960 12:11:29.255398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4961 12:11:29.258383 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4962 12:11:29.262078 [ANA_INIT] flow start
4963 12:11:29.262297 [ANA_INIT] PLL >>>>>>>>
4964 12:11:29.265119 [ANA_INIT] PLL <<<<<<<<
4965 12:11:29.268829 [ANA_INIT] MIDPI >>>>>>>>
4966 12:11:29.269038 [ANA_INIT] MIDPI <<<<<<<<
4967 12:11:29.271915 [ANA_INIT] DLL >>>>>>>>
4968 12:11:29.275594 [ANA_INIT] flow end
4969 12:11:29.278819 ============ LP4 DIFF to SE enter ============
4970 12:11:29.282038 ============ LP4 DIFF to SE exit ============
4971 12:11:29.285271 [ANA_INIT] <<<<<<<<<<<<<
4972 12:11:29.288462 [Flow] Enable top DCM control >>>>>
4973 12:11:29.291667 [Flow] Enable top DCM control <<<<<
4974 12:11:29.294961 Enable DLL master slave shuffle
4975 12:11:29.298832 ==============================================================
4976 12:11:29.301939 Gating Mode config
4977 12:11:29.308345 ==============================================================
4978 12:11:29.308501 Config description:
4979 12:11:29.318055 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4980 12:11:29.325165 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4981 12:11:29.328473 SELPH_MODE 0: By rank 1: By Phase
4982 12:11:29.334699 ==============================================================
4983 12:11:29.338043 GAT_TRACK_EN = 1
4984 12:11:29.341827 RX_GATING_MODE = 2
4985 12:11:29.345109 RX_GATING_TRACK_MODE = 2
4986 12:11:29.348299 SELPH_MODE = 1
4987 12:11:29.351613 PICG_EARLY_EN = 1
4988 12:11:29.354816 VALID_LAT_VALUE = 1
4989 12:11:29.358807 ==============================================================
4990 12:11:29.361867 Enter into Gating configuration >>>>
4991 12:11:29.364992 Exit from Gating configuration <<<<
4992 12:11:29.368424 Enter into DVFS_PRE_config >>>>>
4993 12:11:29.381362 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4994 12:11:29.381522 Exit from DVFS_PRE_config <<<<<
4995 12:11:29.385248 Enter into PICG configuration >>>>
4996 12:11:29.388242 Exit from PICG configuration <<<<
4997 12:11:29.391403 [RX_INPUT] configuration >>>>>
4998 12:11:29.394678 [RX_INPUT] configuration <<<<<
4999 12:11:29.401657 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5000 12:11:29.404834 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5001 12:11:29.411212 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5002 12:11:29.417721 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5003 12:11:29.424770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5004 12:11:29.431269 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5005 12:11:29.434488 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5006 12:11:29.437705 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5007 12:11:29.440993 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5008 12:11:29.447872 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5009 12:11:29.451070 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5010 12:11:29.454264 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5011 12:11:29.458110 ===================================
5012 12:11:29.461261 LPDDR4 DRAM CONFIGURATION
5013 12:11:29.464541 ===================================
5014 12:11:29.464680 EX_ROW_EN[0] = 0x0
5015 12:11:29.467756 EX_ROW_EN[1] = 0x0
5016 12:11:29.471335 LP4Y_EN = 0x0
5017 12:11:29.471487 WORK_FSP = 0x0
5018 12:11:29.474463 WL = 0x3
5019 12:11:29.474580 RL = 0x3
5020 12:11:29.477499 BL = 0x2
5021 12:11:29.477627 RPST = 0x0
5022 12:11:29.481059 RD_PRE = 0x0
5023 12:11:29.481179 WR_PRE = 0x1
5024 12:11:29.484170 WR_PST = 0x0
5025 12:11:29.484278 DBI_WR = 0x0
5026 12:11:29.487670 DBI_RD = 0x0
5027 12:11:29.487794 OTF = 0x1
5028 12:11:29.490787 ===================================
5029 12:11:29.494397 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5030 12:11:29.500741 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5031 12:11:29.504590 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5032 12:11:29.507759 ===================================
5033 12:11:29.511116 LPDDR4 DRAM CONFIGURATION
5034 12:11:29.514297 ===================================
5035 12:11:29.514429 EX_ROW_EN[0] = 0x10
5036 12:11:29.517486 EX_ROW_EN[1] = 0x0
5037 12:11:29.517601 LP4Y_EN = 0x0
5038 12:11:29.520721 WORK_FSP = 0x0
5039 12:11:29.524563 WL = 0x3
5040 12:11:29.524701 RL = 0x3
5041 12:11:29.527775 BL = 0x2
5042 12:11:29.527872 RPST = 0x0
5043 12:11:29.531006 RD_PRE = 0x0
5044 12:11:29.531122 WR_PRE = 0x1
5045 12:11:29.534270 WR_PST = 0x0
5046 12:11:29.534392 DBI_WR = 0x0
5047 12:11:29.537720 DBI_RD = 0x0
5048 12:11:29.537820 OTF = 0x1
5049 12:11:29.540969 ===================================
5050 12:11:29.547503 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5051 12:11:29.551272 nWR fixed to 30
5052 12:11:29.554548 [ModeRegInit_LP4] CH0 RK0
5053 12:11:29.554669 [ModeRegInit_LP4] CH0 RK1
5054 12:11:29.558508 [ModeRegInit_LP4] CH1 RK0
5055 12:11:29.561630 [ModeRegInit_LP4] CH1 RK1
5056 12:11:29.561772 match AC timing 9
5057 12:11:29.567980 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5058 12:11:29.571259 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5059 12:11:29.575049 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5060 12:11:29.581502 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5061 12:11:29.584484 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5062 12:11:29.584648 ==
5063 12:11:29.588044 Dram Type= 6, Freq= 0, CH_0, rank 0
5064 12:11:29.591155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5065 12:11:29.591285 ==
5066 12:11:29.597885 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5067 12:11:29.604149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5068 12:11:29.607907 [CA 0] Center 38 (8~69) winsize 62
5069 12:11:29.611125 [CA 1] Center 38 (8~69) winsize 62
5070 12:11:29.614442 [CA 2] Center 35 (5~66) winsize 62
5071 12:11:29.617769 [CA 3] Center 34 (4~65) winsize 62
5072 12:11:29.621028 [CA 4] Center 33 (3~64) winsize 62
5073 12:11:29.624292 [CA 5] Center 33 (3~64) winsize 62
5074 12:11:29.624413
5075 12:11:29.627614 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5076 12:11:29.627709
5077 12:11:29.630713 [CATrainingPosCal] consider 1 rank data
5078 12:11:29.634095 u2DelayCellTimex100 = 270/100 ps
5079 12:11:29.637339 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5080 12:11:29.640658 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5081 12:11:29.644562 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5082 12:11:29.647764 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5083 12:11:29.651028 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5084 12:11:29.657377 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5085 12:11:29.657513
5086 12:11:29.660675 CA PerBit enable=1, Macro0, CA PI delay=33
5087 12:11:29.660791
5088 12:11:29.663918 [CBTSetCACLKResult] CA Dly = 33
5089 12:11:29.664022 CS Dly: 6 (0~37)
5090 12:11:29.664101 ==
5091 12:11:29.667061 Dram Type= 6, Freq= 0, CH_0, rank 1
5092 12:11:29.673546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 12:11:29.673713 ==
5094 12:11:29.677405 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5095 12:11:29.683822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5096 12:11:29.687104 [CA 0] Center 38 (7~69) winsize 63
5097 12:11:29.690176 [CA 1] Center 37 (7~68) winsize 62
5098 12:11:29.693831 [CA 2] Center 35 (5~66) winsize 62
5099 12:11:29.697324 [CA 3] Center 35 (4~66) winsize 63
5100 12:11:29.700395 [CA 4] Center 34 (4~65) winsize 62
5101 12:11:29.704017 [CA 5] Center 33 (3~64) winsize 62
5102 12:11:29.704154
5103 12:11:29.707257 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5104 12:11:29.707396
5105 12:11:29.710261 [CATrainingPosCal] consider 2 rank data
5106 12:11:29.714109 u2DelayCellTimex100 = 270/100 ps
5107 12:11:29.717309 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5108 12:11:29.720585 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5109 12:11:29.723771 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5110 12:11:29.730143 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5111 12:11:29.734001 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5112 12:11:29.737235 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5113 12:11:29.737380
5114 12:11:29.740418 CA PerBit enable=1, Macro0, CA PI delay=33
5115 12:11:29.740507
5116 12:11:29.743643 [CBTSetCACLKResult] CA Dly = 33
5117 12:11:29.743759 CS Dly: 7 (0~39)
5118 12:11:29.743871
5119 12:11:29.746771 ----->DramcWriteLeveling(PI) begin...
5120 12:11:29.746878 ==
5121 12:11:29.750028 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 12:11:29.757205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 12:11:29.757325 ==
5124 12:11:29.760380 Write leveling (Byte 0): 30 => 30
5125 12:11:29.763614 Write leveling (Byte 1): 27 => 27
5126 12:11:29.766847 DramcWriteLeveling(PI) end<-----
5127 12:11:29.766952
5128 12:11:29.767022 ==
5129 12:11:29.770087 Dram Type= 6, Freq= 0, CH_0, rank 0
5130 12:11:29.773359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 12:11:29.773473 ==
5132 12:11:29.776580 [Gating] SW mode calibration
5133 12:11:29.783624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5134 12:11:29.786820 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5135 12:11:29.793216 0 14 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
5136 12:11:29.796636 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5137 12:11:29.800235 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 12:11:29.807128 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 12:11:29.809987 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 12:11:29.813082 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 12:11:29.819863 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 12:11:29.822883 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 12:11:29.826172 0 15 0 | B1->B0 | 3232 2929 | 0 0 | (0 1) (0 0)
5144 12:11:29.832554 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5145 12:11:29.835892 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 12:11:29.839094 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 12:11:29.846027 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 12:11:29.849418 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 12:11:29.852572 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 12:11:29.859517 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5151 12:11:29.862666 1 0 0 | B1->B0 | 3131 3a3a | 0 0 | (1 1) (0 0)
5152 12:11:29.865963 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 12:11:29.872440 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 12:11:29.875646 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 12:11:29.878965 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 12:11:29.885935 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 12:11:29.889119 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 12:11:29.892410 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5159 12:11:29.898758 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5160 12:11:29.902104 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 12:11:29.905296 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 12:11:29.912012 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 12:11:29.915761 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 12:11:29.918803 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 12:11:29.925590 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 12:11:29.928574 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 12:11:29.931787 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 12:11:29.938794 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 12:11:29.942048 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 12:11:29.945327 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 12:11:29.952367 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 12:11:29.955612 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 12:11:29.958844 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 12:11:29.965219 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5175 12:11:29.968387 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5176 12:11:29.971643 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 12:11:29.975536 Total UI for P1: 0, mck2ui 16
5178 12:11:29.978829 best dqsien dly found for B0: ( 1, 2, 30)
5179 12:11:29.982023 Total UI for P1: 0, mck2ui 16
5180 12:11:29.985327 best dqsien dly found for B1: ( 1, 2, 30)
5181 12:11:29.988540 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5182 12:11:29.991781 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5183 12:11:29.991878
5184 12:11:29.995048 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5185 12:11:30.001531 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5186 12:11:30.001639 [Gating] SW calibration Done
5187 12:11:30.004766 ==
5188 12:11:30.004848 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 12:11:30.011813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 12:11:30.011911 ==
5191 12:11:30.011997 RX Vref Scan: 0
5192 12:11:30.012068
5193 12:11:30.014990 RX Vref 0 -> 0, step: 1
5194 12:11:30.015075
5195 12:11:30.018077 RX Delay -80 -> 252, step: 8
5196 12:11:30.021844 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5197 12:11:30.024849 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5198 12:11:30.027931 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5199 12:11:30.034757 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5200 12:11:30.038091 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5201 12:11:30.041735 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5202 12:11:30.044949 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5203 12:11:30.048233 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5204 12:11:30.051669 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5205 12:11:30.058136 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5206 12:11:30.061313 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5207 12:11:30.064517 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5208 12:11:30.067716 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5209 12:11:30.071058 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5210 12:11:30.078090 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5211 12:11:30.081439 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5212 12:11:30.081558 ==
5213 12:11:30.084704 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 12:11:30.087884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 12:11:30.087996 ==
5216 12:11:30.088109 DQS Delay:
5217 12:11:30.091229 DQS0 = 0, DQS1 = 0
5218 12:11:30.091336 DQM Delay:
5219 12:11:30.094336 DQM0 = 97, DQM1 = 87
5220 12:11:30.094448 DQ Delay:
5221 12:11:30.097621 DQ0 =95, DQ1 =103, DQ2 =95, DQ3 =91
5222 12:11:30.101013 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5223 12:11:30.104154 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5224 12:11:30.107321 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5225 12:11:30.107454
5226 12:11:30.107552
5227 12:11:30.107653 ==
5228 12:11:30.111227 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 12:11:30.117665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 12:11:30.117811 ==
5231 12:11:30.117923
5232 12:11:30.118021
5233 12:11:30.118132 TX Vref Scan disable
5234 12:11:30.120996 == TX Byte 0 ==
5235 12:11:30.123961 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5236 12:11:30.130536 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5237 12:11:30.130668 == TX Byte 1 ==
5238 12:11:30.134317 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5239 12:11:30.140524 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5240 12:11:30.140658 ==
5241 12:11:30.144137 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 12:11:30.147329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 12:11:30.147460 ==
5244 12:11:30.147561
5245 12:11:30.147655
5246 12:11:30.150759 TX Vref Scan disable
5247 12:11:30.150872 == TX Byte 0 ==
5248 12:11:30.157263 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5249 12:11:30.161062 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5250 12:11:30.161206 == TX Byte 1 ==
5251 12:11:30.167598 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5252 12:11:30.170860 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5253 12:11:30.170989
5254 12:11:30.171095 [DATLAT]
5255 12:11:30.174187 Freq=933, CH0 RK0
5256 12:11:30.174297
5257 12:11:30.174417 DATLAT Default: 0xd
5258 12:11:30.177313 0, 0xFFFF, sum = 0
5259 12:11:30.177429 1, 0xFFFF, sum = 0
5260 12:11:30.180636 2, 0xFFFF, sum = 0
5261 12:11:30.183813 3, 0xFFFF, sum = 0
5262 12:11:30.183903 4, 0xFFFF, sum = 0
5263 12:11:30.187509 5, 0xFFFF, sum = 0
5264 12:11:30.187594 6, 0xFFFF, sum = 0
5265 12:11:30.190624 7, 0xFFFF, sum = 0
5266 12:11:30.190732 8, 0xFFFF, sum = 0
5267 12:11:30.193903 9, 0xFFFF, sum = 0
5268 12:11:30.194012 10, 0x0, sum = 1
5269 12:11:30.197091 11, 0x0, sum = 2
5270 12:11:30.197199 12, 0x0, sum = 3
5271 12:11:30.200363 13, 0x0, sum = 4
5272 12:11:30.200472 best_step = 11
5273 12:11:30.200572
5274 12:11:30.200658 ==
5275 12:11:30.203592 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 12:11:30.206851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 12:11:30.206952 ==
5278 12:11:30.210167 RX Vref Scan: 1
5279 12:11:30.210273
5280 12:11:30.213504 RX Vref 0 -> 0, step: 1
5281 12:11:30.213607
5282 12:11:30.213706 RX Delay -61 -> 252, step: 4
5283 12:11:30.213805
5284 12:11:30.216766 Set Vref, RX VrefLevel [Byte0]: 53
5285 12:11:30.219993 [Byte1]: 52
5286 12:11:30.225119
5287 12:11:30.225232 Final RX Vref Byte 0 = 53 to rank0
5288 12:11:30.228256 Final RX Vref Byte 1 = 52 to rank0
5289 12:11:30.231365 Final RX Vref Byte 0 = 53 to rank1
5290 12:11:30.234903 Final RX Vref Byte 1 = 52 to rank1==
5291 12:11:30.238031 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 12:11:30.244545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 12:11:30.244689 ==
5294 12:11:30.244786 DQS Delay:
5295 12:11:30.248344 DQS0 = 0, DQS1 = 0
5296 12:11:30.248431 DQM Delay:
5297 12:11:30.248496 DQM0 = 96, DQM1 = 88
5298 12:11:30.251395 DQ Delay:
5299 12:11:30.254629 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5300 12:11:30.257791 DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =102
5301 12:11:30.261081 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =80
5302 12:11:30.264406 DQ12 =94, DQ13 =90, DQ14 =102, DQ15 =96
5303 12:11:30.264503
5304 12:11:30.264571
5305 12:11:30.270731 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5306 12:11:30.274029 CH0 RK0: MR19=504, MR18=11FC
5307 12:11:30.281263 CH0_RK0: MR19=0x504, MR18=0x11FC, DQSOSC=416, MR23=63, INC=62, DEC=41
5308 12:11:30.281385
5309 12:11:30.284535 ----->DramcWriteLeveling(PI) begin...
5310 12:11:30.284625 ==
5311 12:11:30.287763 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 12:11:30.290976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 12:11:30.291072 ==
5314 12:11:30.294279 Write leveling (Byte 0): 32 => 32
5315 12:11:30.297422 Write leveling (Byte 1): 31 => 31
5316 12:11:30.300727 DramcWriteLeveling(PI) end<-----
5317 12:11:30.300812
5318 12:11:30.300884 ==
5319 12:11:30.303859 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 12:11:30.307598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 12:11:30.310885 ==
5322 12:11:30.311031 [Gating] SW mode calibration
5323 12:11:30.320542 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5324 12:11:30.323833 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5325 12:11:30.327070 0 14 0 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
5326 12:11:30.333551 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5327 12:11:30.337338 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 12:11:30.340567 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 12:11:30.347283 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 12:11:30.350282 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 12:11:30.353283 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5332 12:11:30.360150 0 14 28 | B1->B0 | 3030 2929 | 1 0 | (1 0) (0 0)
5333 12:11:30.363343 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
5334 12:11:30.366532 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 12:11:30.373605 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 12:11:30.376869 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 12:11:30.379987 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 12:11:30.386542 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 12:11:30.389797 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 12:11:30.393645 0 15 28 | B1->B0 | 2727 3838 | 0 1 | (0 0) (0 0)
5341 12:11:30.400091 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5342 12:11:30.403310 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 12:11:30.406662 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 12:11:30.413583 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 12:11:30.416783 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 12:11:30.420065 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 12:11:30.426550 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5348 12:11:30.429802 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5349 12:11:30.433056 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5350 12:11:30.439520 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5351 12:11:30.442816 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 12:11:30.446703 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 12:11:30.452924 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 12:11:30.456391 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 12:11:30.459354 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 12:11:30.466390 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 12:11:30.469505 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 12:11:30.472596 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 12:11:30.479626 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 12:11:30.482813 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 12:11:30.486053 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 12:11:30.492549 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 12:11:30.495804 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5364 12:11:30.499080 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5365 12:11:30.502272 Total UI for P1: 0, mck2ui 16
5366 12:11:30.506096 best dqsien dly found for B0: ( 1, 2, 24)
5367 12:11:30.512587 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5368 12:11:30.515972 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 12:11:30.519307 Total UI for P1: 0, mck2ui 16
5370 12:11:30.522461 best dqsien dly found for B1: ( 1, 2, 30)
5371 12:11:30.525655 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5372 12:11:30.528949 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5373 12:11:30.529059
5374 12:11:30.532279 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5375 12:11:30.535532 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5376 12:11:30.538854 [Gating] SW calibration Done
5377 12:11:30.538963 ==
5378 12:11:30.542188 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 12:11:30.545507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 12:11:30.545616 ==
5381 12:11:30.548797 RX Vref Scan: 0
5382 12:11:30.548910
5383 12:11:30.551983 RX Vref 0 -> 0, step: 1
5384 12:11:30.552089
5385 12:11:30.552184 RX Delay -80 -> 252, step: 8
5386 12:11:30.558979 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5387 12:11:30.561881 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5388 12:11:30.565459 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5389 12:11:30.569283 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5390 12:11:30.572155 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5391 12:11:30.575315 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5392 12:11:30.581923 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5393 12:11:30.585191 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5394 12:11:30.589055 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5395 12:11:30.592223 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5396 12:11:30.595652 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5397 12:11:30.602088 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5398 12:11:30.605464 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5399 12:11:30.608707 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5400 12:11:30.611994 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5401 12:11:30.615233 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5402 12:11:30.615344 ==
5403 12:11:30.618433 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 12:11:30.624902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 12:11:30.625019 ==
5406 12:11:30.625114 DQS Delay:
5407 12:11:30.625198 DQS0 = 0, DQS1 = 0
5408 12:11:30.628799 DQM Delay:
5409 12:11:30.628881 DQM0 = 97, DQM1 = 87
5410 12:11:30.631981 DQ Delay:
5411 12:11:30.635283 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5412 12:11:30.638568 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5413 12:11:30.641803 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5414 12:11:30.645088 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5415 12:11:30.645199
5416 12:11:30.645292
5417 12:11:30.645388 ==
5418 12:11:30.648357 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 12:11:30.651657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 12:11:30.651762 ==
5421 12:11:30.651855
5422 12:11:30.651942
5423 12:11:30.654856 TX Vref Scan disable
5424 12:11:30.654993 == TX Byte 0 ==
5425 12:11:30.661906 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5426 12:11:30.665276 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5427 12:11:30.665385 == TX Byte 1 ==
5428 12:11:30.671326 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5429 12:11:30.674934 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5430 12:11:30.675038 ==
5431 12:11:30.678007 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 12:11:30.681808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 12:11:30.681924 ==
5434 12:11:30.682022
5435 12:11:30.684702
5436 12:11:30.684780 TX Vref Scan disable
5437 12:11:30.688210 == TX Byte 0 ==
5438 12:11:30.691286 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5439 12:11:30.694922 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5440 12:11:30.698103 == TX Byte 1 ==
5441 12:11:30.701140 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5442 12:11:30.705027 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5443 12:11:30.708190
5444 12:11:30.708308 [DATLAT]
5445 12:11:30.708412 Freq=933, CH0 RK1
5446 12:11:30.708514
5447 12:11:30.711324 DATLAT Default: 0xb
5448 12:11:30.711433 0, 0xFFFF, sum = 0
5449 12:11:30.714878 1, 0xFFFF, sum = 0
5450 12:11:30.714986 2, 0xFFFF, sum = 0
5451 12:11:30.717811 3, 0xFFFF, sum = 0
5452 12:11:30.717922 4, 0xFFFF, sum = 0
5453 12:11:30.721017 5, 0xFFFF, sum = 0
5454 12:11:30.724873 6, 0xFFFF, sum = 0
5455 12:11:30.724984 7, 0xFFFF, sum = 0
5456 12:11:30.728224 8, 0xFFFF, sum = 0
5457 12:11:30.728330 9, 0xFFFF, sum = 0
5458 12:11:30.731307 10, 0x0, sum = 1
5459 12:11:30.731473 11, 0x0, sum = 2
5460 12:11:30.734579 12, 0x0, sum = 3
5461 12:11:30.734682 13, 0x0, sum = 4
5462 12:11:30.734748 best_step = 11
5463 12:11:30.734808
5464 12:11:30.737925 ==
5465 12:11:30.741176 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 12:11:30.744359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 12:11:30.744459 ==
5468 12:11:30.744553 RX Vref Scan: 0
5469 12:11:30.744658
5470 12:11:30.747635 RX Vref 0 -> 0, step: 1
5471 12:11:30.747736
5472 12:11:30.750791 RX Delay -61 -> 252, step: 4
5473 12:11:30.754775 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5474 12:11:30.761279 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5475 12:11:30.764626 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5476 12:11:30.767940 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5477 12:11:30.771142 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5478 12:11:30.774599 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5479 12:11:30.777580 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5480 12:11:30.784311 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5481 12:11:30.787435 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5482 12:11:30.791026 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5483 12:11:30.794186 iDelay=199, Bit 10, Center 90 (3 ~ 178) 176
5484 12:11:30.797374 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5485 12:11:30.803903 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5486 12:11:30.806975 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5487 12:11:30.810212 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5488 12:11:30.814083 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5489 12:11:30.814217 ==
5490 12:11:30.817231 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 12:11:30.820524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 12:11:30.820649 ==
5493 12:11:30.823911 DQS Delay:
5494 12:11:30.824025 DQS0 = 0, DQS1 = 0
5495 12:11:30.827023 DQM Delay:
5496 12:11:30.827134 DQM0 = 95, DQM1 = 87
5497 12:11:30.827229 DQ Delay:
5498 12:11:30.830275 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5499 12:11:30.833602 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5500 12:11:30.836800 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =78
5501 12:11:30.840763 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5502 12:11:30.840890
5503 12:11:30.840989
5504 12:11:30.850499 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a06, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5505 12:11:30.853669 CH0 RK1: MR19=505, MR18=1A06
5506 12:11:30.860152 CH0_RK1: MR19=0x505, MR18=0x1A06, DQSOSC=413, MR23=63, INC=63, DEC=42
5507 12:11:30.860316 [RxdqsGatingPostProcess] freq 933
5508 12:11:30.866676 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5509 12:11:30.870502 best DQS0 dly(2T, 0.5T) = (0, 10)
5510 12:11:30.873888 best DQS1 dly(2T, 0.5T) = (0, 10)
5511 12:11:30.877099 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5512 12:11:30.880429 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5513 12:11:30.883604 best DQS0 dly(2T, 0.5T) = (0, 10)
5514 12:11:30.886774 best DQS1 dly(2T, 0.5T) = (0, 10)
5515 12:11:30.889816 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5516 12:11:30.893577 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5517 12:11:30.896484 Pre-setting of DQS Precalculation
5518 12:11:30.900088 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5519 12:11:30.900213 ==
5520 12:11:30.903658 Dram Type= 6, Freq= 0, CH_1, rank 0
5521 12:11:30.906581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 12:11:30.910181 ==
5523 12:11:30.913326 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5524 12:11:30.920056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5525 12:11:30.923171 [CA 0] Center 36 (6~67) winsize 62
5526 12:11:30.926424 [CA 1] Center 36 (6~67) winsize 62
5527 12:11:30.929665 [CA 2] Center 34 (4~64) winsize 61
5528 12:11:30.932969 [CA 3] Center 33 (3~64) winsize 62
5529 12:11:30.937027 [CA 4] Center 34 (4~64) winsize 61
5530 12:11:30.940124 [CA 5] Center 33 (3~64) winsize 62
5531 12:11:30.940269
5532 12:11:30.943457 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5533 12:11:30.943573
5534 12:11:30.946633 [CATrainingPosCal] consider 1 rank data
5535 12:11:30.950006 u2DelayCellTimex100 = 270/100 ps
5536 12:11:30.953152 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5537 12:11:30.956344 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5538 12:11:30.959693 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5539 12:11:30.962952 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5540 12:11:30.969468 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5541 12:11:30.973308 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5542 12:11:30.973431
5543 12:11:30.976590 CA PerBit enable=1, Macro0, CA PI delay=33
5544 12:11:30.976703
5545 12:11:30.979844 [CBTSetCACLKResult] CA Dly = 33
5546 12:11:30.979930 CS Dly: 4 (0~35)
5547 12:11:30.980025 ==
5548 12:11:30.983197 Dram Type= 6, Freq= 0, CH_1, rank 1
5549 12:11:30.989723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 12:11:30.989858 ==
5551 12:11:30.992890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5552 12:11:30.999958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5553 12:11:31.002920 [CA 0] Center 36 (6~67) winsize 62
5554 12:11:31.006672 [CA 1] Center 36 (6~67) winsize 62
5555 12:11:31.009611 [CA 2] Center 33 (3~64) winsize 62
5556 12:11:31.013084 [CA 3] Center 33 (3~64) winsize 62
5557 12:11:31.016461 [CA 4] Center 34 (4~64) winsize 61
5558 12:11:31.019616 [CA 5] Center 33 (3~63) winsize 61
5559 12:11:31.019758
5560 12:11:31.023054 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5561 12:11:31.023171
5562 12:11:31.026182 [CATrainingPosCal] consider 2 rank data
5563 12:11:31.029768 u2DelayCellTimex100 = 270/100 ps
5564 12:11:31.032810 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5565 12:11:31.036193 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 12:11:31.039369 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5567 12:11:31.045963 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5568 12:11:31.049261 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5569 12:11:31.052545 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5570 12:11:31.052670
5571 12:11:31.055847 CA PerBit enable=1, Macro0, CA PI delay=33
5572 12:11:31.055939
5573 12:11:31.059797 [CBTSetCACLKResult] CA Dly = 33
5574 12:11:31.059892 CS Dly: 5 (0~37)
5575 12:11:31.059965
5576 12:11:31.063012 ----->DramcWriteLeveling(PI) begin...
5577 12:11:31.063102 ==
5578 12:11:31.066190 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 12:11:31.072755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 12:11:31.072868 ==
5581 12:11:31.076070 Write leveling (Byte 0): 27 => 27
5582 12:11:31.079292 Write leveling (Byte 1): 29 => 29
5583 12:11:31.079394 DramcWriteLeveling(PI) end<-----
5584 12:11:31.079463
5585 12:11:31.083076 ==
5586 12:11:31.086346 Dram Type= 6, Freq= 0, CH_1, rank 0
5587 12:11:31.089628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 12:11:31.089762 ==
5589 12:11:31.092803 [Gating] SW mode calibration
5590 12:11:31.099411 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5591 12:11:31.102589 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5592 12:11:31.109157 0 14 0 | B1->B0 | 3131 3333 | 0 1 | (0 0) (1 1)
5593 12:11:31.112771 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5594 12:11:31.116242 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 12:11:31.122766 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 12:11:31.125631 0 14 16 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5597 12:11:31.129226 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5598 12:11:31.136036 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 12:11:31.139147 0 14 28 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (0 1)
5600 12:11:31.142246 0 15 0 | B1->B0 | 2c2c 2d2d | 0 0 | (0 0) (1 1)
5601 12:11:31.148943 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 12:11:31.152785 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 12:11:31.156026 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 12:11:31.162466 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 12:11:31.165624 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 12:11:31.168744 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5607 12:11:31.175801 0 15 28 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (1 1)
5608 12:11:31.178992 1 0 0 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
5609 12:11:31.182267 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 12:11:31.188882 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 12:11:31.192217 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 12:11:31.195371 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 12:11:31.201975 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 12:11:31.205883 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 12:11:31.209091 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5616 12:11:31.212291 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5617 12:11:31.218691 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 12:11:31.222472 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 12:11:31.225352 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 12:11:31.231884 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 12:11:31.235489 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 12:11:31.238468 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 12:11:31.245178 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 12:11:31.249007 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 12:11:31.251914 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 12:11:31.258183 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 12:11:31.262080 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 12:11:31.265476 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 12:11:31.271840 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 12:11:31.275144 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5631 12:11:31.278485 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5632 12:11:31.284951 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 12:11:31.288064 Total UI for P1: 0, mck2ui 16
5634 12:11:31.292052 best dqsien dly found for B0: ( 1, 2, 26)
5635 12:11:31.292180 Total UI for P1: 0, mck2ui 16
5636 12:11:31.298625 best dqsien dly found for B1: ( 1, 2, 26)
5637 12:11:31.301870 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5638 12:11:31.305171 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5639 12:11:31.305310
5640 12:11:31.308382 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5641 12:11:31.311589 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5642 12:11:31.314985 [Gating] SW calibration Done
5643 12:11:31.315088 ==
5644 12:11:31.318049 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 12:11:31.321333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 12:11:31.321425 ==
5647 12:11:31.325247 RX Vref Scan: 0
5648 12:11:31.325344
5649 12:11:31.325420 RX Vref 0 -> 0, step: 1
5650 12:11:31.325489
5651 12:11:31.328462 RX Delay -80 -> 252, step: 8
5652 12:11:31.331582 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5653 12:11:31.338485 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5654 12:11:31.341486 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5655 12:11:31.345002 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5656 12:11:31.348091 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5657 12:11:31.351574 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5658 12:11:31.358263 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5659 12:11:31.361348 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5660 12:11:31.364997 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5661 12:11:31.368270 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5662 12:11:31.371507 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5663 12:11:31.374666 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5664 12:11:31.381190 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5665 12:11:31.384484 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5666 12:11:31.387737 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5667 12:11:31.390969 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5668 12:11:31.391096 ==
5669 12:11:31.394264 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 12:11:31.398069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 12:11:31.401255 ==
5672 12:11:31.401357 DQS Delay:
5673 12:11:31.401428 DQS0 = 0, DQS1 = 0
5674 12:11:31.404463 DQM Delay:
5675 12:11:31.404583 DQM0 = 95, DQM1 = 88
5676 12:11:31.407824 DQ Delay:
5677 12:11:31.410964 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =91
5678 12:11:31.414203 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =91
5679 12:11:31.414325 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5680 12:11:31.420746 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5681 12:11:31.420904
5682 12:11:31.421012
5683 12:11:31.421110 ==
5684 12:11:31.424571 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 12:11:31.427832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 12:11:31.427950 ==
5687 12:11:31.428047
5688 12:11:31.428140
5689 12:11:31.431080 TX Vref Scan disable
5690 12:11:31.431197 == TX Byte 0 ==
5691 12:11:31.437667 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5692 12:11:31.440930 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5693 12:11:31.441037 == TX Byte 1 ==
5694 12:11:31.447764 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5695 12:11:31.450744 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5696 12:11:31.450872 ==
5697 12:11:31.454346 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 12:11:31.457572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 12:11:31.457697 ==
5700 12:11:31.457797
5701 12:11:31.457889
5702 12:11:31.461084 TX Vref Scan disable
5703 12:11:31.463973 == TX Byte 0 ==
5704 12:11:31.467698 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5705 12:11:31.470722 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5706 12:11:31.473852 == TX Byte 1 ==
5707 12:11:31.477479 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5708 12:11:31.480728 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5709 12:11:31.480834
5710 12:11:31.484078 [DATLAT]
5711 12:11:31.484175 Freq=933, CH1 RK0
5712 12:11:31.484246
5713 12:11:31.487304 DATLAT Default: 0xd
5714 12:11:31.487410 0, 0xFFFF, sum = 0
5715 12:11:31.490670 1, 0xFFFF, sum = 0
5716 12:11:31.490768 2, 0xFFFF, sum = 0
5717 12:11:31.493861 3, 0xFFFF, sum = 0
5718 12:11:31.493994 4, 0xFFFF, sum = 0
5719 12:11:31.497118 5, 0xFFFF, sum = 0
5720 12:11:31.497209 6, 0xFFFF, sum = 0
5721 12:11:31.500304 7, 0xFFFF, sum = 0
5722 12:11:31.504213 8, 0xFFFF, sum = 0
5723 12:11:31.504315 9, 0xFFFF, sum = 0
5724 12:11:31.504388 10, 0x0, sum = 1
5725 12:11:31.507532 11, 0x0, sum = 2
5726 12:11:31.507623 12, 0x0, sum = 3
5727 12:11:31.510699 13, 0x0, sum = 4
5728 12:11:31.510792 best_step = 11
5729 12:11:31.510861
5730 12:11:31.510923 ==
5731 12:11:31.513979 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 12:11:31.520421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 12:11:31.520567 ==
5734 12:11:31.520665 RX Vref Scan: 1
5735 12:11:31.520757
5736 12:11:31.523665 RX Vref 0 -> 0, step: 1
5737 12:11:31.523769
5738 12:11:31.527536 RX Delay -69 -> 252, step: 4
5739 12:11:31.527633
5740 12:11:31.530817 Set Vref, RX VrefLevel [Byte0]: 59
5741 12:11:31.534158 [Byte1]: 53
5742 12:11:31.534254
5743 12:11:31.537382 Final RX Vref Byte 0 = 59 to rank0
5744 12:11:31.540490 Final RX Vref Byte 1 = 53 to rank0
5745 12:11:31.543738 Final RX Vref Byte 0 = 59 to rank1
5746 12:11:31.546944 Final RX Vref Byte 1 = 53 to rank1==
5747 12:11:31.550853 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 12:11:31.554003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 12:11:31.554136 ==
5750 12:11:31.557121 DQS Delay:
5751 12:11:31.557230 DQS0 = 0, DQS1 = 0
5752 12:11:31.557334 DQM Delay:
5753 12:11:31.560904 DQM0 = 97, DQM1 = 90
5754 12:11:31.561017 DQ Delay:
5755 12:11:31.564015 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5756 12:11:31.567067 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5757 12:11:31.570796 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =86
5758 12:11:31.573731 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
5759 12:11:31.573864
5760 12:11:31.573997
5761 12:11:31.583781 [DQSOSCAuto] RK0, (LSB)MR18= 0x10ed, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5762 12:11:31.587077 CH1 RK0: MR19=504, MR18=10ED
5763 12:11:31.590326 CH1_RK0: MR19=0x504, MR18=0x10ED, DQSOSC=416, MR23=63, INC=62, DEC=41
5764 12:11:31.593573
5765 12:11:31.597329 ----->DramcWriteLeveling(PI) begin...
5766 12:11:31.597459 ==
5767 12:11:31.600641 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 12:11:31.603972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 12:11:31.604114 ==
5770 12:11:31.607170 Write leveling (Byte 0): 28 => 28
5771 12:11:31.610473 Write leveling (Byte 1): 31 => 31
5772 12:11:31.613759 DramcWriteLeveling(PI) end<-----
5773 12:11:31.613880
5774 12:11:31.613976 ==
5775 12:11:31.617005 Dram Type= 6, Freq= 0, CH_1, rank 1
5776 12:11:31.620331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 12:11:31.620450 ==
5778 12:11:31.623517 [Gating] SW mode calibration
5779 12:11:31.630602 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5780 12:11:31.637114 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5781 12:11:31.640302 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 12:11:31.643488 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 12:11:31.649951 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5784 12:11:31.653835 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 12:11:31.657107 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5786 12:11:31.663465 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5787 12:11:31.666921 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
5788 12:11:31.669957 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
5789 12:11:31.673614 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 12:11:31.680518 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 12:11:31.683519 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5792 12:11:31.686701 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 12:11:31.693566 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 12:11:31.696871 0 15 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5795 12:11:31.700116 0 15 24 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
5796 12:11:31.706622 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5797 12:11:31.709695 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 12:11:31.713581 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 12:11:31.720077 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 12:11:31.723272 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 12:11:31.726528 1 0 16 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
5802 12:11:31.733513 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 12:11:31.736909 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5804 12:11:31.740009 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 12:11:31.746364 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 12:11:31.749642 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 12:11:31.752842 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 12:11:31.759979 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 12:11:31.762678 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 12:11:31.766612 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 12:11:31.772934 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 12:11:31.775970 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 12:11:31.779617 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 12:11:31.785763 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 12:11:31.789623 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 12:11:31.792570 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 12:11:31.799502 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 12:11:31.802844 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5819 12:11:31.806143 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5820 12:11:31.809384 Total UI for P1: 0, mck2ui 16
5821 12:11:31.812708 best dqsien dly found for B0: ( 1, 2, 20)
5822 12:11:31.819090 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5823 12:11:31.822321 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 12:11:31.826181 Total UI for P1: 0, mck2ui 16
5825 12:11:31.829487 best dqsien dly found for B1: ( 1, 2, 28)
5826 12:11:31.832778 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5827 12:11:31.835956 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5828 12:11:31.836067
5829 12:11:31.839231 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5830 12:11:31.842436 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5831 12:11:31.845643 [Gating] SW calibration Done
5832 12:11:31.845738 ==
5833 12:11:31.849617 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 12:11:31.852198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 12:11:31.852296 ==
5836 12:11:31.855638 RX Vref Scan: 0
5837 12:11:31.855733
5838 12:11:31.858876 RX Vref 0 -> 0, step: 1
5839 12:11:31.858969
5840 12:11:31.859060 RX Delay -80 -> 252, step: 8
5841 12:11:31.865697 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5842 12:11:31.868871 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5843 12:11:31.872639 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5844 12:11:31.875971 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5845 12:11:31.879190 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5846 12:11:31.883168 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5847 12:11:31.889265 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5848 12:11:31.892299 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5849 12:11:31.895475 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5850 12:11:31.899151 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5851 12:11:31.902167 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5852 12:11:31.909204 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5853 12:11:31.912519 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5854 12:11:31.915717 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5855 12:11:31.918969 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5856 12:11:31.922090 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5857 12:11:31.922230 ==
5858 12:11:31.925394 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 12:11:31.932030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 12:11:31.932188 ==
5861 12:11:31.932310 DQS Delay:
5862 12:11:31.935222 DQS0 = 0, DQS1 = 0
5863 12:11:31.935344 DQM Delay:
5864 12:11:31.935460 DQM0 = 94, DQM1 = 88
5865 12:11:31.939159 DQ Delay:
5866 12:11:31.942487 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5867 12:11:31.945084 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5868 12:11:31.948957 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5869 12:11:31.952147 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5870 12:11:31.952286
5871 12:11:31.952384
5872 12:11:31.952475 ==
5873 12:11:31.955528 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 12:11:31.958741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 12:11:31.958838 ==
5876 12:11:31.958906
5877 12:11:31.958970
5878 12:11:31.961966 TX Vref Scan disable
5879 12:11:31.962057 == TX Byte 0 ==
5880 12:11:31.968712 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5881 12:11:31.971813 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5882 12:11:31.971941 == TX Byte 1 ==
5883 12:11:31.978258 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5884 12:11:31.981568 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5885 12:11:31.981703 ==
5886 12:11:31.985494 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 12:11:31.988837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 12:11:31.988965 ==
5889 12:11:31.992041
5890 12:11:31.992152
5891 12:11:31.992257 TX Vref Scan disable
5892 12:11:31.995197 == TX Byte 0 ==
5893 12:11:31.998302 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5894 12:11:32.004907 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5895 12:11:32.005053 == TX Byte 1 ==
5896 12:11:32.008508 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5897 12:11:32.011719 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5898 12:11:32.014858
5899 12:11:32.014980 [DATLAT]
5900 12:11:32.015086 Freq=933, CH1 RK1
5901 12:11:32.015180
5902 12:11:32.018674 DATLAT Default: 0xb
5903 12:11:32.018782 0, 0xFFFF, sum = 0
5904 12:11:32.021883 1, 0xFFFF, sum = 0
5905 12:11:32.021979 2, 0xFFFF, sum = 0
5906 12:11:32.025115 3, 0xFFFF, sum = 0
5907 12:11:32.025230 4, 0xFFFF, sum = 0
5908 12:11:32.028450 5, 0xFFFF, sum = 0
5909 12:11:32.031654 6, 0xFFFF, sum = 0
5910 12:11:32.031781 7, 0xFFFF, sum = 0
5911 12:11:32.034951 8, 0xFFFF, sum = 0
5912 12:11:32.035063 9, 0xFFFF, sum = 0
5913 12:11:32.038047 10, 0x0, sum = 1
5914 12:11:32.038180 11, 0x0, sum = 2
5915 12:11:32.038298 12, 0x0, sum = 3
5916 12:11:32.041869 13, 0x0, sum = 4
5917 12:11:32.041995 best_step = 11
5918 12:11:32.042099
5919 12:11:32.045172 ==
5920 12:11:32.045286 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 12:11:32.051505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 12:11:32.051621 ==
5923 12:11:32.051694 RX Vref Scan: 0
5924 12:11:32.051774
5925 12:11:32.054805 RX Vref 0 -> 0, step: 1
5926 12:11:32.054920
5927 12:11:32.058669 RX Delay -61 -> 252, step: 4
5928 12:11:32.061932 iDelay=195, Bit 0, Center 96 (3 ~ 190) 188
5929 12:11:32.068565 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5930 12:11:32.071744 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5931 12:11:32.074949 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5932 12:11:32.078156 iDelay=195, Bit 4, Center 94 (3 ~ 186) 184
5933 12:11:32.081570 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5934 12:11:32.084691 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5935 12:11:32.091821 iDelay=195, Bit 7, Center 92 (3 ~ 182) 180
5936 12:11:32.095132 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5937 12:11:32.098347 iDelay=195, Bit 9, Center 80 (-9 ~ 170) 180
5938 12:11:32.101550 iDelay=195, Bit 10, Center 90 (-5 ~ 186) 192
5939 12:11:32.104639 iDelay=195, Bit 11, Center 82 (-9 ~ 174) 184
5940 12:11:32.108222 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
5941 12:11:32.114394 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5942 12:11:32.118135 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5943 12:11:32.121258 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
5944 12:11:32.121361 ==
5945 12:11:32.124315 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 12:11:32.128234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 12:11:32.128336 ==
5948 12:11:32.131528 DQS Delay:
5949 12:11:32.131666 DQS0 = 0, DQS1 = 0
5950 12:11:32.134806 DQM Delay:
5951 12:11:32.134925 DQM0 = 94, DQM1 = 90
5952 12:11:32.135035 DQ Delay:
5953 12:11:32.138010 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =94
5954 12:11:32.141343 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5955 12:11:32.144683 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =82
5956 12:11:32.147854 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
5957 12:11:32.147950
5958 12:11:32.148019
5959 12:11:32.157764 [DQSOSCAuto] RK1, (LSB)MR18= 0xa13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
5960 12:11:32.161100 CH1 RK1: MR19=505, MR18=A13
5961 12:11:32.164791 CH1_RK1: MR19=0x505, MR18=0xA13, DQSOSC=415, MR23=63, INC=62, DEC=41
5962 12:11:32.168053 [RxdqsGatingPostProcess] freq 933
5963 12:11:32.174506 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5964 12:11:32.177655 best DQS0 dly(2T, 0.5T) = (0, 10)
5965 12:11:32.181649 best DQS1 dly(2T, 0.5T) = (0, 10)
5966 12:11:32.184192 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5967 12:11:32.187965 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5968 12:11:32.191198 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 12:11:32.194370 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 12:11:32.197693 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 12:11:32.200974 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 12:11:32.204107 Pre-setting of DQS Precalculation
5973 12:11:32.207954 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5974 12:11:32.214208 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5975 12:11:32.220821 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5976 12:11:32.221000
5977 12:11:32.221112
5978 12:11:32.224050 [Calibration Summary] 1866 Mbps
5979 12:11:32.227169 CH 0, Rank 0
5980 12:11:32.227282 SW Impedance : PASS
5981 12:11:32.230981 DUTY Scan : NO K
5982 12:11:32.233994 ZQ Calibration : PASS
5983 12:11:32.234089 Jitter Meter : NO K
5984 12:11:32.237021 CBT Training : PASS
5985 12:11:32.240979 Write leveling : PASS
5986 12:11:32.241089 RX DQS gating : PASS
5987 12:11:32.244171 RX DQ/DQS(RDDQC) : PASS
5988 12:11:32.247527 TX DQ/DQS : PASS
5989 12:11:32.247625 RX DATLAT : PASS
5990 12:11:32.250746 RX DQ/DQS(Engine): PASS
5991 12:11:32.253931 TX OE : NO K
5992 12:11:32.254057 All Pass.
5993 12:11:32.254174
5994 12:11:32.254280 CH 0, Rank 1
5995 12:11:32.257297 SW Impedance : PASS
5996 12:11:32.260563 DUTY Scan : NO K
5997 12:11:32.260686 ZQ Calibration : PASS
5998 12:11:32.263802 Jitter Meter : NO K
5999 12:11:32.267001 CBT Training : PASS
6000 12:11:32.267127 Write leveling : PASS
6001 12:11:32.270217 RX DQS gating : PASS
6002 12:11:32.270312 RX DQ/DQS(RDDQC) : PASS
6003 12:11:32.273576 TX DQ/DQS : PASS
6004 12:11:32.276697 RX DATLAT : PASS
6005 12:11:32.276801 RX DQ/DQS(Engine): PASS
6006 12:11:32.280036 TX OE : NO K
6007 12:11:32.280134 All Pass.
6008 12:11:32.280203
6009 12:11:32.283851 CH 1, Rank 0
6010 12:11:32.283942 SW Impedance : PASS
6011 12:11:32.286999 DUTY Scan : NO K
6012 12:11:32.290340 ZQ Calibration : PASS
6013 12:11:32.290469 Jitter Meter : NO K
6014 12:11:32.293524 CBT Training : PASS
6015 12:11:32.296715 Write leveling : PASS
6016 12:11:32.296847 RX DQS gating : PASS
6017 12:11:32.299973 RX DQ/DQS(RDDQC) : PASS
6018 12:11:32.303317 TX DQ/DQS : PASS
6019 12:11:32.303430 RX DATLAT : PASS
6020 12:11:32.306634 RX DQ/DQS(Engine): PASS
6021 12:11:32.309800 TX OE : NO K
6022 12:11:32.309921 All Pass.
6023 12:11:32.310046
6024 12:11:32.310148 CH 1, Rank 1
6025 12:11:32.313075 SW Impedance : PASS
6026 12:11:32.316428 DUTY Scan : NO K
6027 12:11:32.316570 ZQ Calibration : PASS
6028 12:11:32.320088 Jitter Meter : NO K
6029 12:11:32.323208 CBT Training : PASS
6030 12:11:32.323326 Write leveling : PASS
6031 12:11:32.326208 RX DQS gating : PASS
6032 12:11:32.326338 RX DQ/DQS(RDDQC) : PASS
6033 12:11:32.329933 TX DQ/DQS : PASS
6034 12:11:32.333107 RX DATLAT : PASS
6035 12:11:32.333232 RX DQ/DQS(Engine): PASS
6036 12:11:32.336147 TX OE : NO K
6037 12:11:32.336265 All Pass.
6038 12:11:32.336371
6039 12:11:32.339850 DramC Write-DBI off
6040 12:11:32.342935 PER_BANK_REFRESH: Hybrid Mode
6041 12:11:32.343065 TX_TRACKING: ON
6042 12:11:32.353359 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6043 12:11:32.356696 [FAST_K] Save calibration result to emmc
6044 12:11:32.359920 dramc_set_vcore_voltage set vcore to 650000
6045 12:11:32.363128 Read voltage for 400, 6
6046 12:11:32.363267 Vio18 = 0
6047 12:11:32.366540 Vcore = 650000
6048 12:11:32.366670 Vdram = 0
6049 12:11:32.366782 Vddq = 0
6050 12:11:32.366885 Vmddr = 0
6051 12:11:32.372993 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6052 12:11:32.379590 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6053 12:11:32.379747 MEM_TYPE=3, freq_sel=20
6054 12:11:32.382860 sv_algorithm_assistance_LP4_800
6055 12:11:32.386097 ============ PULL DRAM RESETB DOWN ============
6056 12:11:32.392669 ========== PULL DRAM RESETB DOWN end =========
6057 12:11:32.395959 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6058 12:11:32.399798 ===================================
6059 12:11:32.403003 LPDDR4 DRAM CONFIGURATION
6060 12:11:32.406281 ===================================
6061 12:11:32.406408 EX_ROW_EN[0] = 0x0
6062 12:11:32.409414 EX_ROW_EN[1] = 0x0
6063 12:11:32.409530 LP4Y_EN = 0x0
6064 12:11:32.412655 WORK_FSP = 0x0
6065 12:11:32.412767 WL = 0x2
6066 12:11:32.415824 RL = 0x2
6067 12:11:32.415935 BL = 0x2
6068 12:11:32.419074 RPST = 0x0
6069 12:11:32.419183 RD_PRE = 0x0
6070 12:11:32.423024 WR_PRE = 0x1
6071 12:11:32.423108 WR_PST = 0x0
6072 12:11:32.426123 DBI_WR = 0x0
6073 12:11:32.429464 DBI_RD = 0x0
6074 12:11:32.429600 OTF = 0x1
6075 12:11:32.432330 ===================================
6076 12:11:32.435990 ===================================
6077 12:11:32.436189 ANA top config
6078 12:11:32.438995 ===================================
6079 12:11:32.442734 DLL_ASYNC_EN = 0
6080 12:11:32.445774 ALL_SLAVE_EN = 1
6081 12:11:32.449472 NEW_RANK_MODE = 1
6082 12:11:32.452665 DLL_IDLE_MODE = 1
6083 12:11:32.452897 LP45_APHY_COMB_EN = 1
6084 12:11:32.455835 TX_ODT_DIS = 1
6085 12:11:32.459058 NEW_8X_MODE = 1
6086 12:11:32.462315 ===================================
6087 12:11:32.465588 ===================================
6088 12:11:32.468906 data_rate = 800
6089 12:11:32.472116 CKR = 1
6090 12:11:32.472230 DQ_P2S_RATIO = 4
6091 12:11:32.475437 ===================================
6092 12:11:32.479170 CA_P2S_RATIO = 4
6093 12:11:32.482638 DQ_CA_OPEN = 0
6094 12:11:32.485727 DQ_SEMI_OPEN = 1
6095 12:11:32.488907 CA_SEMI_OPEN = 1
6096 12:11:32.492115 CA_FULL_RATE = 0
6097 12:11:32.492242 DQ_CKDIV4_EN = 0
6098 12:11:32.495456 CA_CKDIV4_EN = 1
6099 12:11:32.499267 CA_PREDIV_EN = 0
6100 12:11:32.502542 PH8_DLY = 0
6101 12:11:32.505666 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6102 12:11:32.508941 DQ_AAMCK_DIV = 0
6103 12:11:32.509065 CA_AAMCK_DIV = 0
6104 12:11:32.512062 CA_ADMCK_DIV = 4
6105 12:11:32.515303 DQ_TRACK_CA_EN = 0
6106 12:11:32.518696 CA_PICK = 800
6107 12:11:32.521889 CA_MCKIO = 400
6108 12:11:32.525172 MCKIO_SEMI = 400
6109 12:11:32.528541 PLL_FREQ = 3016
6110 12:11:32.528652 DQ_UI_PI_RATIO = 32
6111 12:11:32.531799 CA_UI_PI_RATIO = 32
6112 12:11:32.535670 ===================================
6113 12:11:32.538782 ===================================
6114 12:11:32.541817 memory_type:LPDDR4
6115 12:11:32.545346 GP_NUM : 10
6116 12:11:32.545469 SRAM_EN : 1
6117 12:11:32.548342 MD32_EN : 0
6118 12:11:32.552065 ===================================
6119 12:11:32.554971 [ANA_INIT] >>>>>>>>>>>>>>
6120 12:11:32.558707 <<<<<< [CONFIGURE PHASE]: ANA_TX
6121 12:11:32.561785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6122 12:11:32.564987 ===================================
6123 12:11:32.565087 data_rate = 800,PCW = 0X7400
6124 12:11:32.568250 ===================================
6125 12:11:32.571559 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6126 12:11:32.578654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 12:11:32.588262 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6128 12:11:32.594807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6129 12:11:32.598076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6130 12:11:32.602128 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6131 12:11:32.604618 [ANA_INIT] flow start
6132 12:11:32.604756 [ANA_INIT] PLL >>>>>>>>
6133 12:11:32.608381 [ANA_INIT] PLL <<<<<<<<
6134 12:11:32.611628 [ANA_INIT] MIDPI >>>>>>>>
6135 12:11:32.611782 [ANA_INIT] MIDPI <<<<<<<<
6136 12:11:32.614960 [ANA_INIT] DLL >>>>>>>>
6137 12:11:32.618199 [ANA_INIT] flow end
6138 12:11:32.621401 ============ LP4 DIFF to SE enter ============
6139 12:11:32.624610 ============ LP4 DIFF to SE exit ============
6140 12:11:32.627923 [ANA_INIT] <<<<<<<<<<<<<
6141 12:11:32.631753 [Flow] Enable top DCM control >>>>>
6142 12:11:32.634519 [Flow] Enable top DCM control <<<<<
6143 12:11:32.638455 Enable DLL master slave shuffle
6144 12:11:32.641540 ==============================================================
6145 12:11:32.644840 Gating Mode config
6146 12:11:32.651174 ==============================================================
6147 12:11:32.651343 Config description:
6148 12:11:32.661683 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6149 12:11:32.667800 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6150 12:11:32.671591 SELPH_MODE 0: By rank 1: By Phase
6151 12:11:32.677787 ==============================================================
6152 12:11:32.681037 GAT_TRACK_EN = 0
6153 12:11:32.684913 RX_GATING_MODE = 2
6154 12:11:32.688139 RX_GATING_TRACK_MODE = 2
6155 12:11:32.691342 SELPH_MODE = 1
6156 12:11:32.694698 PICG_EARLY_EN = 1
6157 12:11:32.697830 VALID_LAT_VALUE = 1
6158 12:11:32.701128 ==============================================================
6159 12:11:32.704356 Enter into Gating configuration >>>>
6160 12:11:32.707640 Exit from Gating configuration <<<<
6161 12:11:32.710817 Enter into DVFS_PRE_config >>>>>
6162 12:11:32.724440 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6163 12:11:32.724616 Exit from DVFS_PRE_config <<<<<
6164 12:11:32.727554 Enter into PICG configuration >>>>
6165 12:11:32.730818 Exit from PICG configuration <<<<
6166 12:11:32.734082 [RX_INPUT] configuration >>>>>
6167 12:11:32.737965 [RX_INPUT] configuration <<<<<
6168 12:11:32.744387 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6169 12:11:32.747680 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6170 12:11:32.754163 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6171 12:11:32.760608 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6172 12:11:32.767193 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6173 12:11:32.773786 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6174 12:11:32.777412 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6175 12:11:32.780490 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6176 12:11:32.784149 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6177 12:11:32.790372 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6178 12:11:32.793791 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6179 12:11:32.797646 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 12:11:32.800872 ===================================
6181 12:11:32.804033 LPDDR4 DRAM CONFIGURATION
6182 12:11:32.807337 ===================================
6183 12:11:32.807450 EX_ROW_EN[0] = 0x0
6184 12:11:32.810666 EX_ROW_EN[1] = 0x0
6185 12:11:32.813915 LP4Y_EN = 0x0
6186 12:11:32.814045 WORK_FSP = 0x0
6187 12:11:32.817129 WL = 0x2
6188 12:11:32.817250 RL = 0x2
6189 12:11:32.820442 BL = 0x2
6190 12:11:32.820557 RPST = 0x0
6191 12:11:32.823727 RD_PRE = 0x0
6192 12:11:32.823841 WR_PRE = 0x1
6193 12:11:32.826961 WR_PST = 0x0
6194 12:11:32.827083 DBI_WR = 0x0
6195 12:11:32.830271 DBI_RD = 0x0
6196 12:11:32.830383 OTF = 0x1
6197 12:11:32.833469 ===================================
6198 12:11:32.836784 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6199 12:11:32.844032 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6200 12:11:32.847225 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6201 12:11:32.850490 ===================================
6202 12:11:32.853685 LPDDR4 DRAM CONFIGURATION
6203 12:11:32.856895 ===================================
6204 12:11:32.857023 EX_ROW_EN[0] = 0x10
6205 12:11:32.860123 EX_ROW_EN[1] = 0x0
6206 12:11:32.863485 LP4Y_EN = 0x0
6207 12:11:32.863621 WORK_FSP = 0x0
6208 12:11:32.866762 WL = 0x2
6209 12:11:32.866890 RL = 0x2
6210 12:11:32.870600 BL = 0x2
6211 12:11:32.870722 RPST = 0x0
6212 12:11:32.873617 RD_PRE = 0x0
6213 12:11:32.873732 WR_PRE = 0x1
6214 12:11:32.877150 WR_PST = 0x0
6215 12:11:32.877271 DBI_WR = 0x0
6216 12:11:32.880029 DBI_RD = 0x0
6217 12:11:32.880127 OTF = 0x1
6218 12:11:32.883709 ===================================
6219 12:11:32.889946 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6220 12:11:32.894453 nWR fixed to 30
6221 12:11:32.897522 [ModeRegInit_LP4] CH0 RK0
6222 12:11:32.897672 [ModeRegInit_LP4] CH0 RK1
6223 12:11:32.901150 [ModeRegInit_LP4] CH1 RK0
6224 12:11:32.904492 [ModeRegInit_LP4] CH1 RK1
6225 12:11:32.904617 match AC timing 19
6226 12:11:32.910834 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6227 12:11:32.914733 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6228 12:11:32.917328 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6229 12:11:32.923964 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6230 12:11:32.927916 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6231 12:11:32.928035 ==
6232 12:11:32.930616 Dram Type= 6, Freq= 0, CH_0, rank 0
6233 12:11:32.934417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6234 12:11:32.934518 ==
6235 12:11:32.940985 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6236 12:11:32.947463 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6237 12:11:32.950640 [CA 0] Center 36 (8~64) winsize 57
6238 12:11:32.953937 [CA 1] Center 36 (8~64) winsize 57
6239 12:11:32.957106 [CA 2] Center 36 (8~64) winsize 57
6240 12:11:32.960543 [CA 3] Center 36 (8~64) winsize 57
6241 12:11:32.960673 [CA 4] Center 36 (8~64) winsize 57
6242 12:11:32.963682 [CA 5] Center 36 (8~64) winsize 57
6243 12:11:32.963802
6244 12:11:32.970764 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6245 12:11:32.970904
6246 12:11:32.974067 [CATrainingPosCal] consider 1 rank data
6247 12:11:32.977342 u2DelayCellTimex100 = 270/100 ps
6248 12:11:32.980587 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 12:11:32.983627 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 12:11:32.987345 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 12:11:32.990376 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 12:11:32.993456 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 12:11:32.997180 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 12:11:32.997287
6255 12:11:33.000330 CA PerBit enable=1, Macro0, CA PI delay=36
6256 12:11:33.000426
6257 12:11:33.003664 [CBTSetCACLKResult] CA Dly = 36
6258 12:11:33.006765 CS Dly: 1 (0~32)
6259 12:11:33.006889 ==
6260 12:11:33.010332 Dram Type= 6, Freq= 0, CH_0, rank 1
6261 12:11:33.013449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 12:11:33.013585 ==
6263 12:11:33.020030 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6264 12:11:33.026513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6265 12:11:33.029785 [CA 0] Center 36 (8~64) winsize 57
6266 12:11:33.029924 [CA 1] Center 36 (8~64) winsize 57
6267 12:11:33.033035 [CA 2] Center 36 (8~64) winsize 57
6268 12:11:33.036273 [CA 3] Center 36 (8~64) winsize 57
6269 12:11:33.040221 [CA 4] Center 36 (8~64) winsize 57
6270 12:11:33.042835 [CA 5] Center 36 (8~64) winsize 57
6271 12:11:33.042956
6272 12:11:33.046200 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6273 12:11:33.046317
6274 12:11:33.053245 [CATrainingPosCal] consider 2 rank data
6275 12:11:33.053404 u2DelayCellTimex100 = 270/100 ps
6276 12:11:33.059814 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 12:11:33.063011 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 12:11:33.066393 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 12:11:33.069644 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 12:11:33.072745 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 12:11:33.075960 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 12:11:33.076097
6283 12:11:33.079295 CA PerBit enable=1, Macro0, CA PI delay=36
6284 12:11:33.079440
6285 12:11:33.083174 [CBTSetCACLKResult] CA Dly = 36
6286 12:11:33.086251 CS Dly: 1 (0~32)
6287 12:11:33.086378
6288 12:11:33.089526 ----->DramcWriteLeveling(PI) begin...
6289 12:11:33.089648 ==
6290 12:11:33.092829 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 12:11:33.096055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 12:11:33.096182 ==
6293 12:11:33.099719 Write leveling (Byte 0): 40 => 8
6294 12:11:33.102863 Write leveling (Byte 1): 32 => 0
6295 12:11:33.105971 DramcWriteLeveling(PI) end<-----
6296 12:11:33.106092
6297 12:11:33.106194 ==
6298 12:11:33.109084 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 12:11:33.112865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 12:11:33.112997 ==
6301 12:11:33.116022 [Gating] SW mode calibration
6302 12:11:33.122937 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6303 12:11:33.129442 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6304 12:11:33.132188 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 12:11:33.136061 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6306 12:11:33.142555 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 12:11:33.145859 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 12:11:33.149175 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 12:11:33.155524 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 12:11:33.158760 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 12:11:33.162048 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 12:11:33.169033 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 12:11:33.169195 Total UI for P1: 0, mck2ui 16
6314 12:11:33.175433 best dqsien dly found for B0: ( 0, 14, 24)
6315 12:11:33.175539 Total UI for P1: 0, mck2ui 16
6316 12:11:33.181922 best dqsien dly found for B1: ( 0, 14, 24)
6317 12:11:33.185830 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6318 12:11:33.188525 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6319 12:11:33.188617
6320 12:11:33.192145 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 12:11:33.195251 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6322 12:11:33.198451 [Gating] SW calibration Done
6323 12:11:33.198543 ==
6324 12:11:33.202316 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 12:11:33.205433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 12:11:33.205520 ==
6327 12:11:33.208479 RX Vref Scan: 0
6328 12:11:33.208589
6329 12:11:33.208714 RX Vref 0 -> 0, step: 1
6330 12:11:33.208810
6331 12:11:33.212057 RX Delay -410 -> 252, step: 16
6332 12:11:33.218897 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6333 12:11:33.222099 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6334 12:11:33.225309 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6335 12:11:33.228252 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6336 12:11:33.235191 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6337 12:11:33.238383 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6338 12:11:33.241553 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6339 12:11:33.244882 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6340 12:11:33.251420 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6341 12:11:33.255108 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6342 12:11:33.258333 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6343 12:11:33.261666 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6344 12:11:33.268040 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6345 12:11:33.271430 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6346 12:11:33.274720 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6347 12:11:33.281140 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6348 12:11:33.281285 ==
6349 12:11:33.284997 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 12:11:33.288227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 12:11:33.288343 ==
6352 12:11:33.288444 DQS Delay:
6353 12:11:33.291485 DQS0 = 35, DQS1 = 51
6354 12:11:33.291565 DQM Delay:
6355 12:11:33.294758 DQM0 = 7, DQM1 = 10
6356 12:11:33.294877 DQ Delay:
6357 12:11:33.297818 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6358 12:11:33.301604 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6359 12:11:33.304921 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6360 12:11:33.308041 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6361 12:11:33.308169
6362 12:11:33.308280
6363 12:11:33.308392 ==
6364 12:11:33.311270 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 12:11:33.314457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 12:11:33.314574 ==
6367 12:11:33.314691
6368 12:11:33.314786
6369 12:11:33.317907 TX Vref Scan disable
6370 12:11:33.318033 == TX Byte 0 ==
6371 12:11:33.324769 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 12:11:33.327832 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 12:11:33.327964 == TX Byte 1 ==
6374 12:11:33.334249 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6375 12:11:33.338001 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6376 12:11:33.338132 ==
6377 12:11:33.341381 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 12:11:33.344469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 12:11:33.344617 ==
6380 12:11:33.344737
6381 12:11:33.344844
6382 12:11:33.347765 TX Vref Scan disable
6383 12:11:33.347896 == TX Byte 0 ==
6384 12:11:33.354232 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 12:11:33.357562 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 12:11:33.357694 == TX Byte 1 ==
6387 12:11:33.364144 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6388 12:11:33.367481 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6389 12:11:33.367615
6390 12:11:33.367731 [DATLAT]
6391 12:11:33.371209 Freq=400, CH0 RK0
6392 12:11:33.371331
6393 12:11:33.371449 DATLAT Default: 0xf
6394 12:11:33.374554 0, 0xFFFF, sum = 0
6395 12:11:33.374671 1, 0xFFFF, sum = 0
6396 12:11:33.377657 2, 0xFFFF, sum = 0
6397 12:11:33.377773 3, 0xFFFF, sum = 0
6398 12:11:33.380823 4, 0xFFFF, sum = 0
6399 12:11:33.380941 5, 0xFFFF, sum = 0
6400 12:11:33.384132 6, 0xFFFF, sum = 0
6401 12:11:33.388086 7, 0xFFFF, sum = 0
6402 12:11:33.388213 8, 0xFFFF, sum = 0
6403 12:11:33.391285 9, 0xFFFF, sum = 0
6404 12:11:33.391421 10, 0xFFFF, sum = 0
6405 12:11:33.394543 11, 0xFFFF, sum = 0
6406 12:11:33.394655 12, 0xFFFF, sum = 0
6407 12:11:33.397655 13, 0x0, sum = 1
6408 12:11:33.397766 14, 0x0, sum = 2
6409 12:11:33.400829 15, 0x0, sum = 3
6410 12:11:33.400914 16, 0x0, sum = 4
6411 12:11:33.400979 best_step = 14
6412 12:11:33.404549
6413 12:11:33.404635 ==
6414 12:11:33.407843 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 12:11:33.411013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 12:11:33.411112 ==
6417 12:11:33.411214 RX Vref Scan: 1
6418 12:11:33.411305
6419 12:11:33.414161 RX Vref 0 -> 0, step: 1
6420 12:11:33.414267
6421 12:11:33.417328 RX Delay -343 -> 252, step: 8
6422 12:11:33.417411
6423 12:11:33.420520 Set Vref, RX VrefLevel [Byte0]: 53
6424 12:11:33.424225 [Byte1]: 52
6425 12:11:33.427767
6426 12:11:33.427909 Final RX Vref Byte 0 = 53 to rank0
6427 12:11:33.431605 Final RX Vref Byte 1 = 52 to rank0
6428 12:11:33.434772 Final RX Vref Byte 0 = 53 to rank1
6429 12:11:33.438137 Final RX Vref Byte 1 = 52 to rank1==
6430 12:11:33.441264 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 12:11:33.447621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 12:11:33.447781 ==
6433 12:11:33.447900 DQS Delay:
6434 12:11:33.451286 DQS0 = 44, DQS1 = 60
6435 12:11:33.451426 DQM Delay:
6436 12:11:33.451525 DQM0 = 11, DQM1 = 15
6437 12:11:33.454558 DQ Delay:
6438 12:11:33.457826 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6439 12:11:33.461037 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6440 12:11:33.461180 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6441 12:11:33.464273 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6442 12:11:33.467595
6443 12:11:33.467729
6444 12:11:33.474094 [DQSOSCAuto] RK0, (LSB)MR18= 0x804e, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
6445 12:11:33.477322 CH0 RK0: MR19=C0C, MR18=804E
6446 12:11:33.484485 CH0_RK0: MR19=0xC0C, MR18=0x804E, DQSOSC=393, MR23=63, INC=382, DEC=254
6447 12:11:33.484636 ==
6448 12:11:33.487704 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 12:11:33.490914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 12:11:33.491037 ==
6451 12:11:33.494157 [Gating] SW mode calibration
6452 12:11:33.500563 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6453 12:11:33.507563 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6454 12:11:33.510668 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 12:11:33.513817 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6456 12:11:33.521018 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 12:11:33.524194 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 12:11:33.527295 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 12:11:33.534163 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 12:11:33.537291 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 12:11:33.540620 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 12:11:33.547318 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 12:11:33.547463 Total UI for P1: 0, mck2ui 16
6464 12:11:33.550390 best dqsien dly found for B0: ( 0, 14, 24)
6465 12:11:33.554152 Total UI for P1: 0, mck2ui 16
6466 12:11:33.557220 best dqsien dly found for B1: ( 0, 14, 24)
6467 12:11:33.563743 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6468 12:11:33.567013 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6469 12:11:33.567137
6470 12:11:33.570300 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 12:11:33.574124 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6472 12:11:33.577366 [Gating] SW calibration Done
6473 12:11:33.577492 ==
6474 12:11:33.580740 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 12:11:33.583916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 12:11:33.584039 ==
6477 12:11:33.587132 RX Vref Scan: 0
6478 12:11:33.587248
6479 12:11:33.587359 RX Vref 0 -> 0, step: 1
6480 12:11:33.587428
6481 12:11:33.590444 RX Delay -410 -> 252, step: 16
6482 12:11:33.596887 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6483 12:11:33.600145 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6484 12:11:33.603416 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6485 12:11:33.606634 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6486 12:11:33.613089 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6487 12:11:33.616774 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6488 12:11:33.620158 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6489 12:11:33.623337 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6490 12:11:33.629806 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6491 12:11:33.633050 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6492 12:11:33.636336 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6493 12:11:33.640048 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6494 12:11:33.646283 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6495 12:11:33.649897 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6496 12:11:33.653159 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6497 12:11:33.659480 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6498 12:11:33.659583 ==
6499 12:11:33.663121 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 12:11:33.666415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 12:11:33.666515 ==
6502 12:11:33.666605 DQS Delay:
6503 12:11:33.669646 DQS0 = 43, DQS1 = 51
6504 12:11:33.669757 DQM Delay:
6505 12:11:33.672859 DQM0 = 11, DQM1 = 10
6506 12:11:33.672966 DQ Delay:
6507 12:11:33.676062 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6508 12:11:33.679207 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6509 12:11:33.682535 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6510 12:11:33.686516 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6511 12:11:33.686623
6512 12:11:33.686722
6513 12:11:33.686818 ==
6514 12:11:33.689098 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 12:11:33.693013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 12:11:33.693130 ==
6517 12:11:33.693232
6518 12:11:33.693323
6519 12:11:33.696231 TX Vref Scan disable
6520 12:11:33.696345 == TX Byte 0 ==
6521 12:11:33.702691 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6522 12:11:33.706007 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6523 12:11:33.706127 == TX Byte 1 ==
6524 12:11:33.712629 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6525 12:11:33.715757 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6526 12:11:33.715846 ==
6527 12:11:33.719486 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 12:11:33.722553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 12:11:33.722669 ==
6530 12:11:33.722770
6531 12:11:33.722862
6532 12:11:33.725725 TX Vref Scan disable
6533 12:11:33.725810 == TX Byte 0 ==
6534 12:11:33.732911 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6535 12:11:33.736214 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6536 12:11:33.736306 == TX Byte 1 ==
6537 12:11:33.742739 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6538 12:11:33.746003 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6539 12:11:33.746116
6540 12:11:33.746210 [DATLAT]
6541 12:11:33.748937 Freq=400, CH0 RK1
6542 12:11:33.749027
6543 12:11:33.749094 DATLAT Default: 0xe
6544 12:11:33.752535 0, 0xFFFF, sum = 0
6545 12:11:33.752632 1, 0xFFFF, sum = 0
6546 12:11:33.755551 2, 0xFFFF, sum = 0
6547 12:11:33.755665 3, 0xFFFF, sum = 0
6548 12:11:33.758827 4, 0xFFFF, sum = 0
6549 12:11:33.758942 5, 0xFFFF, sum = 0
6550 12:11:33.762568 6, 0xFFFF, sum = 0
6551 12:11:33.762680 7, 0xFFFF, sum = 0
6552 12:11:33.765777 8, 0xFFFF, sum = 0
6553 12:11:33.765864 9, 0xFFFF, sum = 0
6554 12:11:33.768920 10, 0xFFFF, sum = 0
6555 12:11:33.772032 11, 0xFFFF, sum = 0
6556 12:11:33.772152 12, 0xFFFF, sum = 0
6557 12:11:33.775879 13, 0x0, sum = 1
6558 12:11:33.775962 14, 0x0, sum = 2
6559 12:11:33.776031 15, 0x0, sum = 3
6560 12:11:33.779047 16, 0x0, sum = 4
6561 12:11:33.779151 best_step = 14
6562 12:11:33.779244
6563 12:11:33.782295 ==
6564 12:11:33.785634 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 12:11:33.788872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 12:11:33.788985 ==
6567 12:11:33.789098 RX Vref Scan: 0
6568 12:11:33.789191
6569 12:11:33.792131 RX Vref 0 -> 0, step: 1
6570 12:11:33.792260
6571 12:11:33.795336 RX Delay -343 -> 252, step: 8
6572 12:11:33.802468 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6573 12:11:33.805684 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6574 12:11:33.808844 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6575 12:11:33.812133 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6576 12:11:33.819298 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6577 12:11:33.822336 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6578 12:11:33.826043 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6579 12:11:33.829259 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6580 12:11:33.835739 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6581 12:11:33.838965 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6582 12:11:33.842151 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6583 12:11:33.845492 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6584 12:11:33.852451 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6585 12:11:33.855773 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6586 12:11:33.858943 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6587 12:11:33.865653 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6588 12:11:33.865790 ==
6589 12:11:33.868682 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 12:11:33.872453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 12:11:33.872572 ==
6592 12:11:33.872670 DQS Delay:
6593 12:11:33.875543 DQS0 = 48, DQS1 = 60
6594 12:11:33.875653 DQM Delay:
6595 12:11:33.878648 DQM0 = 13, DQM1 = 13
6596 12:11:33.878742 DQ Delay:
6597 12:11:33.882636 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6598 12:11:33.885928 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6599 12:11:33.889230 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =4
6600 12:11:33.892601 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6601 12:11:33.892702
6602 12:11:33.892802
6603 12:11:33.899088 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e60, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 392 ps
6604 12:11:33.902308 CH0 RK1: MR19=C0C, MR18=8E60
6605 12:11:33.908814 CH0_RK1: MR19=0xC0C, MR18=0x8E60, DQSOSC=392, MR23=63, INC=384, DEC=256
6606 12:11:33.912000 [RxdqsGatingPostProcess] freq 400
6607 12:11:33.918644 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6608 12:11:33.918751 best DQS0 dly(2T, 0.5T) = (0, 10)
6609 12:11:33.921879 best DQS1 dly(2T, 0.5T) = (0, 10)
6610 12:11:33.925186 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6611 12:11:33.929012 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6612 12:11:33.932152 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 12:11:33.935450 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 12:11:33.938779 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 12:11:33.942012 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 12:11:33.945329 Pre-setting of DQS Precalculation
6617 12:11:33.951940 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6618 12:11:33.952085 ==
6619 12:11:33.955206 Dram Type= 6, Freq= 0, CH_1, rank 0
6620 12:11:33.958431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 12:11:33.958514 ==
6622 12:11:33.965530 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6623 12:11:33.968572 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6624 12:11:33.971682 [CA 0] Center 36 (8~64) winsize 57
6625 12:11:33.975491 [CA 1] Center 36 (8~64) winsize 57
6626 12:11:33.978517 [CA 2] Center 36 (8~64) winsize 57
6627 12:11:33.981735 [CA 3] Center 36 (8~64) winsize 57
6628 12:11:33.984927 [CA 4] Center 36 (8~64) winsize 57
6629 12:11:33.988602 [CA 5] Center 36 (8~64) winsize 57
6630 12:11:33.988702
6631 12:11:33.991918 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6632 12:11:33.992012
6633 12:11:33.995158 [CATrainingPosCal] consider 1 rank data
6634 12:11:33.998487 u2DelayCellTimex100 = 270/100 ps
6635 12:11:34.001653 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 12:11:34.004913 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 12:11:34.008814 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 12:11:34.011431 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 12:11:34.018581 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 12:11:34.021702 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 12:11:34.021824
6642 12:11:34.025048 CA PerBit enable=1, Macro0, CA PI delay=36
6643 12:11:34.025163
6644 12:11:34.028286 [CBTSetCACLKResult] CA Dly = 36
6645 12:11:34.028383 CS Dly: 1 (0~32)
6646 12:11:34.028451 ==
6647 12:11:34.031676 Dram Type= 6, Freq= 0, CH_1, rank 1
6648 12:11:34.038483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 12:11:34.038612 ==
6650 12:11:34.041794 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6651 12:11:34.048327 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6652 12:11:34.051709 [CA 0] Center 36 (8~64) winsize 57
6653 12:11:34.054848 [CA 1] Center 36 (8~64) winsize 57
6654 12:11:34.058112 [CA 2] Center 36 (8~64) winsize 57
6655 12:11:34.061282 [CA 3] Center 36 (8~64) winsize 57
6656 12:11:34.064436 [CA 4] Center 36 (8~64) winsize 57
6657 12:11:34.067711 [CA 5] Center 36 (8~64) winsize 57
6658 12:11:34.067797
6659 12:11:34.071589 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6660 12:11:34.071675
6661 12:11:34.074879 [CATrainingPosCal] consider 2 rank data
6662 12:11:34.077803 u2DelayCellTimex100 = 270/100 ps
6663 12:11:34.081264 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 12:11:34.084352 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 12:11:34.087612 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 12:11:34.091392 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 12:11:34.094550 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 12:11:34.097753 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 12:11:34.097865
6670 12:11:34.104166 CA PerBit enable=1, Macro0, CA PI delay=36
6671 12:11:34.104322
6672 12:11:34.108135 [CBTSetCACLKResult] CA Dly = 36
6673 12:11:34.108252 CS Dly: 1 (0~32)
6674 12:11:34.108380
6675 12:11:34.111286 ----->DramcWriteLeveling(PI) begin...
6676 12:11:34.111431 ==
6677 12:11:34.114527 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 12:11:34.117723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 12:11:34.117856 ==
6680 12:11:34.120936 Write leveling (Byte 0): 40 => 8
6681 12:11:34.124715 Write leveling (Byte 1): 40 => 8
6682 12:11:34.127845 DramcWriteLeveling(PI) end<-----
6683 12:11:34.127947
6684 12:11:34.128016 ==
6685 12:11:34.131070 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 12:11:34.134353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 12:11:34.137494 ==
6688 12:11:34.137585 [Gating] SW mode calibration
6689 12:11:34.147703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6690 12:11:34.150991 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6691 12:11:34.154074 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6692 12:11:34.161238 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6693 12:11:34.164626 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 12:11:34.167664 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 12:11:34.174250 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 12:11:34.177532 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 12:11:34.180679 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 12:11:34.187571 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 12:11:34.190545 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 12:11:34.194033 Total UI for P1: 0, mck2ui 16
6701 12:11:34.197080 best dqsien dly found for B0: ( 0, 14, 24)
6702 12:11:34.200850 Total UI for P1: 0, mck2ui 16
6703 12:11:34.204046 best dqsien dly found for B1: ( 0, 14, 24)
6704 12:11:34.207273 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6705 12:11:34.210566 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6706 12:11:34.210679
6707 12:11:34.213870 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 12:11:34.217042 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6709 12:11:34.220913 [Gating] SW calibration Done
6710 12:11:34.221033 ==
6711 12:11:34.224158 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 12:11:34.230764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 12:11:34.230857 ==
6714 12:11:34.230925 RX Vref Scan: 0
6715 12:11:34.230988
6716 12:11:34.233966 RX Vref 0 -> 0, step: 1
6717 12:11:34.234051
6718 12:11:34.237197 RX Delay -410 -> 252, step: 16
6719 12:11:34.240361 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6720 12:11:34.244132 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6721 12:11:34.247330 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6722 12:11:34.253824 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6723 12:11:34.257028 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6724 12:11:34.260887 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6725 12:11:34.264014 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6726 12:11:34.270399 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6727 12:11:34.273691 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6728 12:11:34.277507 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6729 12:11:34.280234 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6730 12:11:34.287203 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6731 12:11:34.290333 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6732 12:11:34.294036 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6733 12:11:34.296972 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6734 12:11:34.303761 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6735 12:11:34.303862 ==
6736 12:11:34.306828 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 12:11:34.310581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 12:11:34.310668 ==
6739 12:11:34.313762 DQS Delay:
6740 12:11:34.313849 DQS0 = 51, DQS1 = 59
6741 12:11:34.313915 DQM Delay:
6742 12:11:34.317048 DQM0 = 19, DQM1 = 16
6743 12:11:34.317137 DQ Delay:
6744 12:11:34.320309 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6745 12:11:34.323540 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6746 12:11:34.326835 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6747 12:11:34.330007 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6748 12:11:34.330113
6749 12:11:34.330205
6750 12:11:34.330293 ==
6751 12:11:34.333316 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 12:11:34.339784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 12:11:34.339876 ==
6754 12:11:34.339941
6755 12:11:34.340003
6756 12:11:34.340061 TX Vref Scan disable
6757 12:11:34.343654 == TX Byte 0 ==
6758 12:11:34.346857 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 12:11:34.350046 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 12:11:34.353199 == TX Byte 1 ==
6761 12:11:34.356533 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 12:11:34.359705 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 12:11:34.359802 ==
6764 12:11:34.363528 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 12:11:34.369999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 12:11:34.370126 ==
6767 12:11:34.370228
6768 12:11:34.370324
6769 12:11:34.370421 TX Vref Scan disable
6770 12:11:34.373229 == TX Byte 0 ==
6771 12:11:34.376420 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 12:11:34.379674 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 12:11:34.382881 == TX Byte 1 ==
6774 12:11:34.386774 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 12:11:34.389952 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 12:11:34.390057
6777 12:11:34.393254 [DATLAT]
6778 12:11:34.393340 Freq=400, CH1 RK0
6779 12:11:34.393408
6780 12:11:34.396616 DATLAT Default: 0xf
6781 12:11:34.396702 0, 0xFFFF, sum = 0
6782 12:11:34.399576 1, 0xFFFF, sum = 0
6783 12:11:34.399663 2, 0xFFFF, sum = 0
6784 12:11:34.403144 3, 0xFFFF, sum = 0
6785 12:11:34.403233 4, 0xFFFF, sum = 0
6786 12:11:34.406079 5, 0xFFFF, sum = 0
6787 12:11:34.406163 6, 0xFFFF, sum = 0
6788 12:11:34.409840 7, 0xFFFF, sum = 0
6789 12:11:34.409928 8, 0xFFFF, sum = 0
6790 12:11:34.412973 9, 0xFFFF, sum = 0
6791 12:11:34.413062 10, 0xFFFF, sum = 0
6792 12:11:34.416696 11, 0xFFFF, sum = 0
6793 12:11:34.419958 12, 0xFFFF, sum = 0
6794 12:11:34.420074 13, 0x0, sum = 1
6795 12:11:34.423267 14, 0x0, sum = 2
6796 12:11:34.423389 15, 0x0, sum = 3
6797 12:11:34.423486 16, 0x0, sum = 4
6798 12:11:34.426528 best_step = 14
6799 12:11:34.426630
6800 12:11:34.426721 ==
6801 12:11:34.429719 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 12:11:34.432980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 12:11:34.433097 ==
6804 12:11:34.436329 RX Vref Scan: 1
6805 12:11:34.436442
6806 12:11:34.436539 RX Vref 0 -> 0, step: 1
6807 12:11:34.439564
6808 12:11:34.439648 RX Delay -359 -> 252, step: 8
6809 12:11:34.439749
6810 12:11:34.442721 Set Vref, RX VrefLevel [Byte0]: 59
6811 12:11:34.445769 [Byte1]: 53
6812 12:11:34.451678
6813 12:11:34.451772 Final RX Vref Byte 0 = 59 to rank0
6814 12:11:34.454802 Final RX Vref Byte 1 = 53 to rank0
6815 12:11:34.457920 Final RX Vref Byte 0 = 59 to rank1
6816 12:11:34.461133 Final RX Vref Byte 1 = 53 to rank1==
6817 12:11:34.464440 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 12:11:34.470992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 12:11:34.471114 ==
6820 12:11:34.471212 DQS Delay:
6821 12:11:34.474316 DQS0 = 48, DQS1 = 60
6822 12:11:34.474412 DQM Delay:
6823 12:11:34.474482 DQM0 = 11, DQM1 = 13
6824 12:11:34.478131 DQ Delay:
6825 12:11:34.481546 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6826 12:11:34.481647 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6827 12:11:34.484683 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =12
6828 12:11:34.487941 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6829 12:11:34.491167
6830 12:11:34.491284
6831 12:11:34.497613 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a32, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6832 12:11:34.500973 CH1 RK0: MR19=C0C, MR18=8A32
6833 12:11:34.508036 CH1_RK0: MR19=0xC0C, MR18=0x8A32, DQSOSC=392, MR23=63, INC=384, DEC=256
6834 12:11:34.508127 ==
6835 12:11:34.511046 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 12:11:34.514090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 12:11:34.514174 ==
6838 12:11:34.517609 [Gating] SW mode calibration
6839 12:11:34.524562 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6840 12:11:34.531003 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6841 12:11:34.534249 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6842 12:11:34.537578 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6843 12:11:34.544033 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 12:11:34.547250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 12:11:34.550574 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 12:11:34.557097 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 12:11:34.560906 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 12:11:34.564057 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 12:11:34.570772 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 12:11:34.570898 Total UI for P1: 0, mck2ui 16
6851 12:11:34.573951 best dqsien dly found for B0: ( 0, 14, 24)
6852 12:11:34.577281 Total UI for P1: 0, mck2ui 16
6853 12:11:34.580339 best dqsien dly found for B1: ( 0, 14, 24)
6854 12:11:34.586979 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6855 12:11:34.590765 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6856 12:11:34.590858
6857 12:11:34.594013 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 12:11:34.597345 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6859 12:11:34.600598 [Gating] SW calibration Done
6860 12:11:34.600687 ==
6861 12:11:34.603880 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 12:11:34.607600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 12:11:34.607681 ==
6864 12:11:34.610953 RX Vref Scan: 0
6865 12:11:34.611056
6866 12:11:34.611148 RX Vref 0 -> 0, step: 1
6867 12:11:34.611237
6868 12:11:34.614220 RX Delay -410 -> 252, step: 16
6869 12:11:34.617346 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6870 12:11:34.623951 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6871 12:11:34.627323 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6872 12:11:34.630277 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6873 12:11:34.633999 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6874 12:11:34.640242 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6875 12:11:34.643506 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6876 12:11:34.646689 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6877 12:11:34.650584 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6878 12:11:34.657049 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6879 12:11:34.660553 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6880 12:11:34.663489 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6881 12:11:34.670138 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6882 12:11:34.673886 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6883 12:11:34.677249 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6884 12:11:34.680307 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6885 12:11:34.680417 ==
6886 12:11:34.683575 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 12:11:34.690599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 12:11:34.690714 ==
6889 12:11:34.690785 DQS Delay:
6890 12:11:34.693158 DQS0 = 51, DQS1 = 59
6891 12:11:34.693245 DQM Delay:
6892 12:11:34.696996 DQM0 = 17, DQM1 = 20
6893 12:11:34.697073 DQ Delay:
6894 12:11:34.700131 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6895 12:11:34.703369 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6896 12:11:34.706622 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6897 12:11:34.709853 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6898 12:11:34.709937
6899 12:11:34.710003
6900 12:11:34.710065 ==
6901 12:11:34.713672 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 12:11:34.717076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 12:11:34.717192 ==
6904 12:11:34.717268
6905 12:11:34.717336
6906 12:11:34.720222 TX Vref Scan disable
6907 12:11:34.720308 == TX Byte 0 ==
6908 12:11:34.726793 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6909 12:11:34.729800 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6910 12:11:34.729915 == TX Byte 1 ==
6911 12:11:34.736591 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6912 12:11:34.740035 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6913 12:11:34.740164 ==
6914 12:11:34.743002 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 12:11:34.746243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 12:11:34.746342 ==
6917 12:11:34.746412
6918 12:11:34.746474
6919 12:11:34.749799 TX Vref Scan disable
6920 12:11:34.749901 == TX Byte 0 ==
6921 12:11:34.756717 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6922 12:11:34.760080 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6923 12:11:34.760204 == TX Byte 1 ==
6924 12:11:34.766658 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6925 12:11:34.769770 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6926 12:11:34.769885
6927 12:11:34.769958 [DATLAT]
6928 12:11:34.772977 Freq=400, CH1 RK1
6929 12:11:34.773060
6930 12:11:34.773139 DATLAT Default: 0xe
6931 12:11:34.776750 0, 0xFFFF, sum = 0
6932 12:11:34.776839 1, 0xFFFF, sum = 0
6933 12:11:34.780041 2, 0xFFFF, sum = 0
6934 12:11:34.780178 3, 0xFFFF, sum = 0
6935 12:11:34.783198 4, 0xFFFF, sum = 0
6936 12:11:34.783325 5, 0xFFFF, sum = 0
6937 12:11:34.786554 6, 0xFFFF, sum = 0
6938 12:11:34.786664 7, 0xFFFF, sum = 0
6939 12:11:34.789717 8, 0xFFFF, sum = 0
6940 12:11:34.789797 9, 0xFFFF, sum = 0
6941 12:11:34.793058 10, 0xFFFF, sum = 0
6942 12:11:34.793181 11, 0xFFFF, sum = 0
6943 12:11:34.796148 12, 0xFFFF, sum = 0
6944 12:11:34.799464 13, 0x0, sum = 1
6945 12:11:34.799566 14, 0x0, sum = 2
6946 12:11:34.799633 15, 0x0, sum = 3
6947 12:11:34.802776 16, 0x0, sum = 4
6948 12:11:34.802868 best_step = 14
6949 12:11:34.802956
6950 12:11:34.803058 ==
6951 12:11:34.806626 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 12:11:34.812791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 12:11:34.812892 ==
6954 12:11:34.812980 RX Vref Scan: 0
6955 12:11:34.813062
6956 12:11:34.816038 RX Vref 0 -> 0, step: 1
6957 12:11:34.816127
6958 12:11:34.819328 RX Delay -359 -> 252, step: 8
6959 12:11:34.826516 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6960 12:11:34.829681 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6961 12:11:34.832806 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6962 12:11:34.836079 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6963 12:11:34.842880 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6964 12:11:34.845916 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6965 12:11:34.849657 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6966 12:11:34.852646 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6967 12:11:34.859495 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6968 12:11:34.862771 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6969 12:11:34.866033 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6970 12:11:34.869285 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6971 12:11:34.876168 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6972 12:11:34.879285 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6973 12:11:34.882608 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6974 12:11:34.889869 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6975 12:11:34.889968 ==
6976 12:11:34.892545 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 12:11:34.896550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 12:11:34.896679 ==
6979 12:11:34.896761 DQS Delay:
6980 12:11:34.899695 DQS0 = 52, DQS1 = 56
6981 12:11:34.899784 DQM Delay:
6982 12:11:34.902996 DQM0 = 14, DQM1 = 9
6983 12:11:34.903085 DQ Delay:
6984 12:11:34.906228 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6985 12:11:34.909528 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6986 12:11:34.912666 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6987 12:11:34.916581 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6988 12:11:34.916675
6989 12:11:34.916745
6990 12:11:34.923205 [DQSOSCAuto] RK1, (LSB)MR18= 0x738a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6991 12:11:34.926629 CH1 RK1: MR19=C0C, MR18=738A
6992 12:11:34.932935 CH1_RK1: MR19=0xC0C, MR18=0x738A, DQSOSC=392, MR23=63, INC=384, DEC=256
6993 12:11:34.936241 [RxdqsGatingPostProcess] freq 400
6994 12:11:34.939428 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6995 12:11:34.943158 best DQS0 dly(2T, 0.5T) = (0, 10)
6996 12:11:34.946451 best DQS1 dly(2T, 0.5T) = (0, 10)
6997 12:11:34.949416 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6998 12:11:34.952711 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6999 12:11:34.956235 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 12:11:34.959294 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 12:11:34.963039 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 12:11:34.966042 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 12:11:34.969252 Pre-setting of DQS Precalculation
7004 12:11:34.972448 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7005 12:11:34.982499 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7006 12:11:34.989300 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7007 12:11:34.989436
7008 12:11:34.989534
7009 12:11:34.992604 [Calibration Summary] 800 Mbps
7010 12:11:34.992718 CH 0, Rank 0
7011 12:11:34.995925 SW Impedance : PASS
7012 12:11:34.996039 DUTY Scan : NO K
7013 12:11:34.999002 ZQ Calibration : PASS
7014 12:11:35.002441 Jitter Meter : NO K
7015 12:11:35.002557 CBT Training : PASS
7016 12:11:35.005703 Write leveling : PASS
7017 12:11:35.008966 RX DQS gating : PASS
7018 12:11:35.009080 RX DQ/DQS(RDDQC) : PASS
7019 12:11:35.012191 TX DQ/DQS : PASS
7020 12:11:35.016090 RX DATLAT : PASS
7021 12:11:35.016182 RX DQ/DQS(Engine): PASS
7022 12:11:35.019198 TX OE : NO K
7023 12:11:35.019331 All Pass.
7024 12:11:35.019442
7025 12:11:35.022473 CH 0, Rank 1
7026 12:11:35.022607 SW Impedance : PASS
7027 12:11:35.025710 DUTY Scan : NO K
7028 12:11:35.029106 ZQ Calibration : PASS
7029 12:11:35.029198 Jitter Meter : NO K
7030 12:11:35.032253 CBT Training : PASS
7031 12:11:35.032343 Write leveling : NO K
7032 12:11:35.035467 RX DQS gating : PASS
7033 12:11:35.038682 RX DQ/DQS(RDDQC) : PASS
7034 12:11:35.038764 TX DQ/DQS : PASS
7035 12:11:35.042498 RX DATLAT : PASS
7036 12:11:35.045586 RX DQ/DQS(Engine): PASS
7037 12:11:35.045682 TX OE : NO K
7038 12:11:35.048782 All Pass.
7039 12:11:35.048896
7040 12:11:35.049004 CH 1, Rank 0
7041 12:11:35.051969 SW Impedance : PASS
7042 12:11:35.052079 DUTY Scan : NO K
7043 12:11:35.055184 ZQ Calibration : PASS
7044 12:11:35.058966 Jitter Meter : NO K
7045 12:11:35.059079 CBT Training : PASS
7046 12:11:35.061960 Write leveling : PASS
7047 12:11:35.065131 RX DQS gating : PASS
7048 12:11:35.065228 RX DQ/DQS(RDDQC) : PASS
7049 12:11:35.068903 TX DQ/DQS : PASS
7050 12:11:35.071874 RX DATLAT : PASS
7051 12:11:35.071970 RX DQ/DQS(Engine): PASS
7052 12:11:35.075141 TX OE : NO K
7053 12:11:35.075262 All Pass.
7054 12:11:35.075378
7055 12:11:35.078452 CH 1, Rank 1
7056 12:11:35.078562 SW Impedance : PASS
7057 12:11:35.082324 DUTY Scan : NO K
7058 12:11:35.085632 ZQ Calibration : PASS
7059 12:11:35.085750 Jitter Meter : NO K
7060 12:11:35.088743 CBT Training : PASS
7061 12:11:35.088853 Write leveling : NO K
7062 12:11:35.091910 RX DQS gating : PASS
7063 12:11:35.095155 RX DQ/DQS(RDDQC) : PASS
7064 12:11:35.095270 TX DQ/DQS : PASS
7065 12:11:35.098538 RX DATLAT : PASS
7066 12:11:35.102235 RX DQ/DQS(Engine): PASS
7067 12:11:35.102331 TX OE : NO K
7068 12:11:35.105531 All Pass.
7069 12:11:35.105648
7070 12:11:35.105743 DramC Write-DBI off
7071 12:11:35.108769 PER_BANK_REFRESH: Hybrid Mode
7072 12:11:35.111987 TX_TRACKING: ON
7073 12:11:35.118455 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7074 12:11:35.121581 [FAST_K] Save calibration result to emmc
7075 12:11:35.124898 dramc_set_vcore_voltage set vcore to 725000
7076 12:11:35.128781 Read voltage for 1600, 0
7077 12:11:35.128908 Vio18 = 0
7078 12:11:35.132114 Vcore = 725000
7079 12:11:35.132221 Vdram = 0
7080 12:11:35.132319 Vddq = 0
7081 12:11:35.135460 Vmddr = 0
7082 12:11:35.138600 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7083 12:11:35.145100 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7084 12:11:35.145233 MEM_TYPE=3, freq_sel=13
7085 12:11:35.148203 sv_algorithm_assistance_LP4_3733
7086 12:11:35.155382 ============ PULL DRAM RESETB DOWN ============
7087 12:11:35.158574 ========== PULL DRAM RESETB DOWN end =========
7088 12:11:35.161897 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7089 12:11:35.165059 ===================================
7090 12:11:35.168220 LPDDR4 DRAM CONFIGURATION
7091 12:11:35.171792 ===================================
7092 12:11:35.174890 EX_ROW_EN[0] = 0x0
7093 12:11:35.174987 EX_ROW_EN[1] = 0x0
7094 12:11:35.177984 LP4Y_EN = 0x0
7095 12:11:35.178073 WORK_FSP = 0x1
7096 12:11:35.181228 WL = 0x5
7097 12:11:35.181348 RL = 0x5
7098 12:11:35.184981 BL = 0x2
7099 12:11:35.185105 RPST = 0x0
7100 12:11:35.188293 RD_PRE = 0x0
7101 12:11:35.188412 WR_PRE = 0x1
7102 12:11:35.191299 WR_PST = 0x1
7103 12:11:35.191417 DBI_WR = 0x0
7104 12:11:35.194603 DBI_RD = 0x0
7105 12:11:35.194716 OTF = 0x1
7106 12:11:35.198096 ===================================
7107 12:11:35.201291 ===================================
7108 12:11:35.204549 ANA top config
7109 12:11:35.207786 ===================================
7110 12:11:35.211106 DLL_ASYNC_EN = 0
7111 12:11:35.211202 ALL_SLAVE_EN = 0
7112 12:11:35.214893 NEW_RANK_MODE = 1
7113 12:11:35.218090 DLL_IDLE_MODE = 1
7114 12:11:35.221336 LP45_APHY_COMB_EN = 1
7115 12:11:35.221433 TX_ODT_DIS = 0
7116 12:11:35.224629 NEW_8X_MODE = 1
7117 12:11:35.227808 ===================================
7118 12:11:35.230981 ===================================
7119 12:11:35.234413 data_rate = 3200
7120 12:11:35.237690 CKR = 1
7121 12:11:35.240867 DQ_P2S_RATIO = 8
7122 12:11:35.244787 ===================================
7123 12:11:35.248048 CA_P2S_RATIO = 8
7124 12:11:35.248183 DQ_CA_OPEN = 0
7125 12:11:35.251285 DQ_SEMI_OPEN = 0
7126 12:11:35.254520 CA_SEMI_OPEN = 0
7127 12:11:35.257827 CA_FULL_RATE = 0
7128 12:11:35.261187 DQ_CKDIV4_EN = 0
7129 12:11:35.264479 CA_CKDIV4_EN = 0
7130 12:11:35.264581 CA_PREDIV_EN = 0
7131 12:11:35.267761 PH8_DLY = 12
7132 12:11:35.270973 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7133 12:11:35.274226 DQ_AAMCK_DIV = 4
7134 12:11:35.277365 CA_AAMCK_DIV = 4
7135 12:11:35.280500 CA_ADMCK_DIV = 4
7136 12:11:35.280622 DQ_TRACK_CA_EN = 0
7137 12:11:35.284164 CA_PICK = 1600
7138 12:11:35.287795 CA_MCKIO = 1600
7139 12:11:35.290873 MCKIO_SEMI = 0
7140 12:11:35.293809 PLL_FREQ = 3068
7141 12:11:35.297622 DQ_UI_PI_RATIO = 32
7142 12:11:35.300765 CA_UI_PI_RATIO = 0
7143 12:11:35.303967 ===================================
7144 12:11:35.307281 ===================================
7145 12:11:35.307405 memory_type:LPDDR4
7146 12:11:35.310656 GP_NUM : 10
7147 12:11:35.313843 SRAM_EN : 1
7148 12:11:35.313960 MD32_EN : 0
7149 12:11:35.317731 ===================================
7150 12:11:35.320975 [ANA_INIT] >>>>>>>>>>>>>>
7151 12:11:35.324210 <<<<<< [CONFIGURE PHASE]: ANA_TX
7152 12:11:35.327555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7153 12:11:35.330761 ===================================
7154 12:11:35.333956 data_rate = 3200,PCW = 0X7600
7155 12:11:35.337320 ===================================
7156 12:11:35.340503 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7157 12:11:35.343706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 12:11:35.350640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7159 12:11:35.353826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7160 12:11:35.357045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7161 12:11:35.363847 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7162 12:11:35.363952 [ANA_INIT] flow start
7163 12:11:35.367048 [ANA_INIT] PLL >>>>>>>>
7164 12:11:35.367165 [ANA_INIT] PLL <<<<<<<<
7165 12:11:35.370225 [ANA_INIT] MIDPI >>>>>>>>
7166 12:11:35.373467 [ANA_INIT] MIDPI <<<<<<<<
7167 12:11:35.376805 [ANA_INIT] DLL >>>>>>>>
7168 12:11:35.376923 [ANA_INIT] DLL <<<<<<<<
7169 12:11:35.380674 [ANA_INIT] flow end
7170 12:11:35.383975 ============ LP4 DIFF to SE enter ============
7171 12:11:35.387051 ============ LP4 DIFF to SE exit ============
7172 12:11:35.390200 [ANA_INIT] <<<<<<<<<<<<<
7173 12:11:35.393334 [Flow] Enable top DCM control >>>>>
7174 12:11:35.397176 [Flow] Enable top DCM control <<<<<
7175 12:11:35.400339 Enable DLL master slave shuffle
7176 12:11:35.407053 ==============================================================
7177 12:11:35.407166 Gating Mode config
7178 12:11:35.413656 ==============================================================
7179 12:11:35.413761 Config description:
7180 12:11:35.423418 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7181 12:11:35.430350 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7182 12:11:35.436819 SELPH_MODE 0: By rank 1: By Phase
7183 12:11:35.440122 ==============================================================
7184 12:11:35.443527 GAT_TRACK_EN = 1
7185 12:11:35.446692 RX_GATING_MODE = 2
7186 12:11:35.449910 RX_GATING_TRACK_MODE = 2
7187 12:11:35.453070 SELPH_MODE = 1
7188 12:11:35.456318 PICG_EARLY_EN = 1
7189 12:11:35.459697 VALID_LAT_VALUE = 1
7190 12:11:35.466695 ==============================================================
7191 12:11:35.469749 Enter into Gating configuration >>>>
7192 12:11:35.473045 Exit from Gating configuration <<<<
7193 12:11:35.473173 Enter into DVFS_PRE_config >>>>>
7194 12:11:35.486699 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7195 12:11:35.489880 Exit from DVFS_PRE_config <<<<<
7196 12:11:35.492982 Enter into PICG configuration >>>>
7197 12:11:35.496602 Exit from PICG configuration <<<<
7198 12:11:35.496696 [RX_INPUT] configuration >>>>>
7199 12:11:35.499761 [RX_INPUT] configuration <<<<<
7200 12:11:35.506477 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7201 12:11:35.509605 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7202 12:11:35.516591 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7203 12:11:35.523064 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7204 12:11:35.530076 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7205 12:11:35.536655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7206 12:11:35.539947 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7207 12:11:35.543185 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7208 12:11:35.549717 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7209 12:11:35.552905 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7210 12:11:35.556130 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7211 12:11:35.559296 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 12:11:35.562565 ===================================
7213 12:11:35.566373 LPDDR4 DRAM CONFIGURATION
7214 12:11:35.569604 ===================================
7215 12:11:35.572722 EX_ROW_EN[0] = 0x0
7216 12:11:35.572859 EX_ROW_EN[1] = 0x0
7217 12:11:35.575898 LP4Y_EN = 0x0
7218 12:11:35.575983 WORK_FSP = 0x1
7219 12:11:35.579152 WL = 0x5
7220 12:11:35.579255 RL = 0x5
7221 12:11:35.582357 BL = 0x2
7222 12:11:35.582448 RPST = 0x0
7223 12:11:35.586280 RD_PRE = 0x0
7224 12:11:35.586368 WR_PRE = 0x1
7225 12:11:35.589504 WR_PST = 0x1
7226 12:11:35.589630 DBI_WR = 0x0
7227 12:11:35.592750 DBI_RD = 0x0
7228 12:11:35.595918 OTF = 0x1
7229 12:11:35.599627 ===================================
7230 12:11:35.602648 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7231 12:11:35.605811 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7232 12:11:35.609549 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7233 12:11:35.612659 ===================================
7234 12:11:35.616096 LPDDR4 DRAM CONFIGURATION
7235 12:11:35.619626 ===================================
7236 12:11:35.622695 EX_ROW_EN[0] = 0x10
7237 12:11:35.622781 EX_ROW_EN[1] = 0x0
7238 12:11:35.625953 LP4Y_EN = 0x0
7239 12:11:35.626079 WORK_FSP = 0x1
7240 12:11:35.629201 WL = 0x5
7241 12:11:35.629324 RL = 0x5
7242 12:11:35.632469 BL = 0x2
7243 12:11:35.632562 RPST = 0x0
7244 12:11:35.636284 RD_PRE = 0x0
7245 12:11:35.636406 WR_PRE = 0x1
7246 12:11:35.639516 WR_PST = 0x1
7247 12:11:35.639637 DBI_WR = 0x0
7248 12:11:35.642747 DBI_RD = 0x0
7249 12:11:35.642850 OTF = 0x1
7250 12:11:35.646048 ===================================
7251 12:11:35.652429 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7252 12:11:35.652543 ==
7253 12:11:35.655594 Dram Type= 6, Freq= 0, CH_0, rank 0
7254 12:11:35.662691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7255 12:11:35.662801 ==
7256 12:11:35.662878 [Duty_Offset_Calibration]
7257 12:11:35.665891 B0:2 B1:-1 CA:1
7258 12:11:35.666018
7259 12:11:35.669181 [DutyScan_Calibration_Flow] k_type=0
7260 12:11:35.677526
7261 12:11:35.677636 ==CLK 0==
7262 12:11:35.680614 Final CLK duty delay cell = -4
7263 12:11:35.684344 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7264 12:11:35.687557 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7265 12:11:35.690790 [-4] AVG Duty = 4937%(X100)
7266 12:11:35.690887
7267 12:11:35.694121 CH0 CLK Duty spec in!! Max-Min= 187%
7268 12:11:35.697429 [DutyScan_Calibration_Flow] ====Done====
7269 12:11:35.697511
7270 12:11:35.700648 [DutyScan_Calibration_Flow] k_type=1
7271 12:11:35.717002
7272 12:11:35.717134 ==DQS 0 ==
7273 12:11:35.720649 Final DQS duty delay cell = 0
7274 12:11:35.723848 [0] MAX Duty = 5125%(X100), DQS PI = 20
7275 12:11:35.726982 [0] MIN Duty = 5000%(X100), DQS PI = 14
7276 12:11:35.727078 [0] AVG Duty = 5062%(X100)
7277 12:11:35.730894
7278 12:11:35.731000 ==DQS 1 ==
7279 12:11:35.734067 Final DQS duty delay cell = -4
7280 12:11:35.737318 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7281 12:11:35.740640 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7282 12:11:35.743892 [-4] AVG Duty = 5046%(X100)
7283 12:11:35.744033
7284 12:11:35.747186 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7285 12:11:35.747303
7286 12:11:35.750548 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7287 12:11:35.753590 [DutyScan_Calibration_Flow] ====Done====
7288 12:11:35.753717
7289 12:11:35.756822 [DutyScan_Calibration_Flow] k_type=3
7290 12:11:35.774415
7291 12:11:35.774576 ==DQM 0 ==
7292 12:11:35.777528 Final DQM duty delay cell = 0
7293 12:11:35.781650 [0] MAX Duty = 5000%(X100), DQS PI = 20
7294 12:11:35.784588 [0] MIN Duty = 4875%(X100), DQS PI = 4
7295 12:11:35.784711 [0] AVG Duty = 4937%(X100)
7296 12:11:35.787739
7297 12:11:35.787819 ==DQM 1 ==
7298 12:11:35.791481 Final DQM duty delay cell = 0
7299 12:11:35.794660 [0] MAX Duty = 5218%(X100), DQS PI = 58
7300 12:11:35.797995 [0] MIN Duty = 4969%(X100), DQS PI = 18
7301 12:11:35.798112 [0] AVG Duty = 5093%(X100)
7302 12:11:35.801120
7303 12:11:35.804281 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7304 12:11:35.804363
7305 12:11:35.807564 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7306 12:11:35.811323 [DutyScan_Calibration_Flow] ====Done====
7307 12:11:35.811458
7308 12:11:35.814524 [DutyScan_Calibration_Flow] k_type=2
7309 12:11:35.831835
7310 12:11:35.831978 ==DQ 0 ==
7311 12:11:35.834845 Final DQ duty delay cell = 0
7312 12:11:35.838011 [0] MAX Duty = 5156%(X100), DQS PI = 0
7313 12:11:35.841948 [0] MIN Duty = 5031%(X100), DQS PI = 12
7314 12:11:35.842062 [0] AVG Duty = 5093%(X100)
7315 12:11:35.842157
7316 12:11:35.844999 ==DQ 1 ==
7317 12:11:35.848296 Final DQ duty delay cell = 0
7318 12:11:35.851548 [0] MAX Duty = 5031%(X100), DQS PI = 30
7319 12:11:35.854721 [0] MIN Duty = 4907%(X100), DQS PI = 20
7320 12:11:35.854837 [0] AVG Duty = 4969%(X100)
7321 12:11:35.854935
7322 12:11:35.858574 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7323 12:11:35.861764
7324 12:11:35.864921 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7325 12:11:35.868075 [DutyScan_Calibration_Flow] ====Done====
7326 12:11:35.868197 ==
7327 12:11:35.871335 Dram Type= 6, Freq= 0, CH_1, rank 0
7328 12:11:35.875056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7329 12:11:35.875171 ==
7330 12:11:35.878342 [Duty_Offset_Calibration]
7331 12:11:35.878467 B0:1 B1:1 CA:2
7332 12:11:35.878567
7333 12:11:35.881674 [DutyScan_Calibration_Flow] k_type=0
7334 12:11:35.891694
7335 12:11:35.891845 ==CLK 0==
7336 12:11:35.895326 Final CLK duty delay cell = 0
7337 12:11:35.898617 [0] MAX Duty = 5187%(X100), DQS PI = 24
7338 12:11:35.901794 [0] MIN Duty = 4969%(X100), DQS PI = 40
7339 12:11:35.905068 [0] AVG Duty = 5078%(X100)
7340 12:11:35.905189
7341 12:11:35.908196 CH1 CLK Duty spec in!! Max-Min= 218%
7342 12:11:35.911445 [DutyScan_Calibration_Flow] ====Done====
7343 12:11:35.911555
7344 12:11:35.914648 [DutyScan_Calibration_Flow] k_type=1
7345 12:11:35.931533
7346 12:11:35.931717 ==DQS 0 ==
7347 12:11:35.934688 Final DQS duty delay cell = 0
7348 12:11:35.938342 [0] MAX Duty = 5062%(X100), DQS PI = 20
7349 12:11:35.941545 [0] MIN Duty = 4844%(X100), DQS PI = 50
7350 12:11:35.944629 [0] AVG Duty = 4953%(X100)
7351 12:11:35.944767
7352 12:11:35.944869 ==DQS 1 ==
7353 12:11:35.947918 Final DQS duty delay cell = 0
7354 12:11:35.951169 [0] MAX Duty = 5031%(X100), DQS PI = 34
7355 12:11:35.954476 [0] MIN Duty = 4938%(X100), DQS PI = 14
7356 12:11:35.958272 [0] AVG Duty = 4984%(X100)
7357 12:11:35.958392
7358 12:11:35.961571 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7359 12:11:35.961689
7360 12:11:35.964726 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7361 12:11:35.967902 [DutyScan_Calibration_Flow] ====Done====
7362 12:11:35.968019
7363 12:11:35.971107 [DutyScan_Calibration_Flow] k_type=3
7364 12:11:35.988676
7365 12:11:35.988834 ==DQM 0 ==
7366 12:11:35.991767 Final DQM duty delay cell = 0
7367 12:11:35.994938 [0] MAX Duty = 5187%(X100), DQS PI = 22
7368 12:11:35.998101 [0] MIN Duty = 4876%(X100), DQS PI = 48
7369 12:11:36.001325 [0] AVG Duty = 5031%(X100)
7370 12:11:36.001462
7371 12:11:36.001569 ==DQM 1 ==
7372 12:11:36.004539 Final DQM duty delay cell = 0
7373 12:11:36.008523 [0] MAX Duty = 5187%(X100), DQS PI = 60
7374 12:11:36.011792 [0] MIN Duty = 4875%(X100), DQS PI = 20
7375 12:11:36.015029 [0] AVG Duty = 5031%(X100)
7376 12:11:36.015170
7377 12:11:36.018206 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7378 12:11:36.018326
7379 12:11:36.021495 CH1 DQM 1 Duty spec in!! Max-Min= 312%
7380 12:11:36.024718 [DutyScan_Calibration_Flow] ====Done====
7381 12:11:36.024845
7382 12:11:36.027988 [DutyScan_Calibration_Flow] k_type=2
7383 12:11:36.045321
7384 12:11:36.045506 ==DQ 0 ==
7385 12:11:36.048568 Final DQ duty delay cell = 0
7386 12:11:36.051799 [0] MAX Duty = 5156%(X100), DQS PI = 20
7387 12:11:36.055089 [0] MIN Duty = 4907%(X100), DQS PI = 52
7388 12:11:36.055224 [0] AVG Duty = 5031%(X100)
7389 12:11:36.058957
7390 12:11:36.059080 ==DQ 1 ==
7391 12:11:36.062223 Final DQ duty delay cell = 0
7392 12:11:36.065252 [0] MAX Duty = 5093%(X100), DQS PI = 6
7393 12:11:36.068598 [0] MIN Duty = 5031%(X100), DQS PI = 0
7394 12:11:36.068744 [0] AVG Duty = 5062%(X100)
7395 12:11:36.068866
7396 12:11:36.071791 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7397 12:11:36.071918
7398 12:11:36.075488 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7399 12:11:36.082052 [DutyScan_Calibration_Flow] ====Done====
7400 12:11:36.085293 nWR fixed to 30
7401 12:11:36.085431 [ModeRegInit_LP4] CH0 RK0
7402 12:11:36.088476 [ModeRegInit_LP4] CH0 RK1
7403 12:11:36.091716 [ModeRegInit_LP4] CH1 RK0
7404 12:11:36.091846 [ModeRegInit_LP4] CH1 RK1
7405 12:11:36.094978 match AC timing 5
7406 12:11:36.098252 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7407 12:11:36.102190 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7408 12:11:36.108622 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7409 12:11:36.111919 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7410 12:11:36.118323 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7411 12:11:36.118455 [MiockJmeterHQA]
7412 12:11:36.118594
7413 12:11:36.121703 [DramcMiockJmeter] u1RxGatingPI = 0
7414 12:11:36.124981 0 : 4363, 4138
7415 12:11:36.125100 4 : 4257, 4030
7416 12:11:36.125211 8 : 4257, 4030
7417 12:11:36.128212 12 : 4258, 4029
7418 12:11:36.128346 16 : 4260, 4031
7419 12:11:36.131537 20 : 4363, 4137
7420 12:11:36.131667 24 : 4252, 4027
7421 12:11:36.134714 28 : 4371, 4140
7422 12:11:36.134840 32 : 4253, 4026
7423 12:11:36.137976 36 : 4252, 4027
7424 12:11:36.138097 40 : 4252, 4027
7425 12:11:36.138198 44 : 4361, 4137
7426 12:11:36.141710 48 : 4363, 4138
7427 12:11:36.141837 52 : 4250, 4026
7428 12:11:36.144820 56 : 4250, 4027
7429 12:11:36.144950 60 : 4250, 4027
7430 12:11:36.148447 64 : 4250, 4026
7431 12:11:36.148546 68 : 4252, 4030
7432 12:11:36.148615 72 : 4361, 4137
7433 12:11:36.151922 76 : 4250, 4027
7434 12:11:36.152014 80 : 4250, 4026
7435 12:11:36.154721 84 : 4250, 4026
7436 12:11:36.154809 88 : 4252, 4029
7437 12:11:36.158529 92 : 4250, 4026
7438 12:11:36.158621 96 : 4361, 2962
7439 12:11:36.161782 100 : 4361, 0
7440 12:11:36.161923 104 : 4360, 0
7441 12:11:36.162030 108 : 4361, 0
7442 12:11:36.165019 112 : 4363, 0
7443 12:11:36.165139 116 : 4250, 0
7444 12:11:36.165259 120 : 4252, 0
7445 12:11:36.168248 124 : 4249, 0
7446 12:11:36.168338 128 : 4250, 0
7447 12:11:36.171595 132 : 4250, 0
7448 12:11:36.171746 136 : 4250, 0
7449 12:11:36.171862 140 : 4250, 0
7450 12:11:36.174705 144 : 4361, 0
7451 12:11:36.174836 148 : 4360, 0
7452 12:11:36.177818 152 : 4249, 0
7453 12:11:36.177952 156 : 4250, 0
7454 12:11:36.178065 160 : 4250, 0
7455 12:11:36.181193 164 : 4249, 0
7456 12:11:36.181312 168 : 4250, 0
7457 12:11:36.185029 172 : 4250, 0
7458 12:11:36.185148 176 : 4249, 0
7459 12:11:36.185273 180 : 4252, 0
7460 12:11:36.188304 184 : 4250, 0
7461 12:11:36.188434 188 : 4250, 0
7462 12:11:36.188551 192 : 4252, 0
7463 12:11:36.191437 196 : 4361, 0
7464 12:11:36.191567 200 : 4360, 0
7465 12:11:36.194609 204 : 4249, 0
7466 12:11:36.194726 208 : 4252, 0
7467 12:11:36.194837 212 : 4250, 121
7468 12:11:36.197916 216 : 4250, 3748
7469 12:11:36.198049 220 : 4360, 4138
7470 12:11:36.201150 224 : 4250, 4027
7471 12:11:36.201280 228 : 4250, 4026
7472 12:11:36.204982 232 : 4250, 4027
7473 12:11:36.205102 236 : 4252, 4030
7474 12:11:36.208176 240 : 4249, 4027
7475 12:11:36.208307 244 : 4250, 4026
7476 12:11:36.211446 248 : 4361, 4137
7477 12:11:36.211585 252 : 4250, 4027
7478 12:11:36.214721 256 : 4249, 4027
7479 12:11:36.214854 260 : 4360, 4137
7480 12:11:36.217886 264 : 4250, 4026
7481 12:11:36.218004 268 : 4250, 4027
7482 12:11:36.218136 272 : 4363, 4140
7483 12:11:36.221132 276 : 4249, 4027
7484 12:11:36.221249 280 : 4250, 4026
7485 12:11:36.224488 284 : 4250, 4027
7486 12:11:36.224619 288 : 4252, 4030
7487 12:11:36.228250 292 : 4249, 4027
7488 12:11:36.228380 296 : 4250, 4026
7489 12:11:36.231495 300 : 4361, 4137
7490 12:11:36.231635 304 : 4250, 4027
7491 12:11:36.234731 308 : 4249, 4027
7492 12:11:36.234843 312 : 4360, 4137
7493 12:11:36.237918 316 : 4250, 4026
7494 12:11:36.238049 320 : 4250, 4027
7495 12:11:36.241177 324 : 4363, 4140
7496 12:11:36.241306 328 : 4249, 4027
7497 12:11:36.241436 332 : 4250, 3022
7498 12:11:36.244509 336 : 4250, 48
7499 12:11:36.244635
7500 12:11:36.247730 MIOCK jitter meter ch=0
7501 12:11:36.247869
7502 12:11:36.247971 1T = (336-100) = 236 dly cells
7503 12:11:36.254444 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7504 12:11:36.254539 ==
7505 12:11:36.257870 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 12:11:36.261051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 12:11:36.264215 ==
7508 12:11:36.267598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 12:11:36.271293 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 12:11:36.277892 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 12:11:36.284331 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 12:11:36.291659 [CA 0] Center 44 (14~75) winsize 62
7513 12:11:36.295554 [CA 1] Center 43 (13~74) winsize 62
7514 12:11:36.298716 [CA 2] Center 39 (10~68) winsize 59
7515 12:11:36.301853 [CA 3] Center 39 (10~68) winsize 59
7516 12:11:36.305067 [CA 4] Center 37 (7~67) winsize 61
7517 12:11:36.308262 [CA 5] Center 37 (7~67) winsize 61
7518 12:11:36.308380
7519 12:11:36.311495 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 12:11:36.311578
7521 12:11:36.318567 [CATrainingPosCal] consider 1 rank data
7522 12:11:36.318708 u2DelayCellTimex100 = 275/100 ps
7523 12:11:36.325030 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7524 12:11:36.328285 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7525 12:11:36.331650 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7526 12:11:36.334822 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7527 12:11:36.338025 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7528 12:11:36.341175 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7529 12:11:36.341297
7530 12:11:36.344489 CA PerBit enable=1, Macro0, CA PI delay=37
7531 12:11:36.344585
7532 12:11:36.348303 [CBTSetCACLKResult] CA Dly = 37
7533 12:11:36.351536 CS Dly: 11 (0~42)
7534 12:11:36.354694 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 12:11:36.357907 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 12:11:36.358020 ==
7537 12:11:36.360984 Dram Type= 6, Freq= 0, CH_0, rank 1
7538 12:11:36.368083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 12:11:36.368189 ==
7540 12:11:36.371039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7541 12:11:36.377689 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7542 12:11:36.380965 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7543 12:11:36.387541 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7544 12:11:36.395876 [CA 0] Center 43 (13~74) winsize 62
7545 12:11:36.399024 [CA 1] Center 43 (13~74) winsize 62
7546 12:11:36.402261 [CA 2] Center 39 (10~69) winsize 60
7547 12:11:36.405564 [CA 3] Center 38 (9~68) winsize 60
7548 12:11:36.408775 [CA 4] Center 37 (7~67) winsize 61
7549 12:11:36.411976 [CA 5] Center 37 (7~67) winsize 61
7550 12:11:36.412114
7551 12:11:36.415364 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7552 12:11:36.415487
7553 12:11:36.418567 [CATrainingPosCal] consider 2 rank data
7554 12:11:36.422239 u2DelayCellTimex100 = 275/100 ps
7555 12:11:36.428786 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7556 12:11:36.431927 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7557 12:11:36.435615 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7558 12:11:36.438863 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7559 12:11:36.442122 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7560 12:11:36.445246 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7561 12:11:36.445379
7562 12:11:36.448485 CA PerBit enable=1, Macro0, CA PI delay=37
7563 12:11:36.448569
7564 12:11:36.451650 [CBTSetCACLKResult] CA Dly = 37
7565 12:11:36.455530 CS Dly: 12 (0~44)
7566 12:11:36.458672 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7567 12:11:36.462042 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7568 12:11:36.462125
7569 12:11:36.465278 ----->DramcWriteLeveling(PI) begin...
7570 12:11:36.465399 ==
7571 12:11:36.468550 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 12:11:36.475295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 12:11:36.475432 ==
7574 12:11:36.478561 Write leveling (Byte 0): 32 => 32
7575 12:11:36.481929 Write leveling (Byte 1): 27 => 27
7576 12:11:36.482017 DramcWriteLeveling(PI) end<-----
7577 12:11:36.482098
7578 12:11:36.484914 ==
7579 12:11:36.485023 Dram Type= 6, Freq= 0, CH_0, rank 0
7580 12:11:36.491705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 12:11:36.491818 ==
7582 12:11:36.495156 [Gating] SW mode calibration
7583 12:11:36.501467 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7584 12:11:36.504774 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7585 12:11:36.511921 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 12:11:36.515108 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 12:11:36.518386 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 12:11:36.524704 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 12:11:36.528089 1 4 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7590 12:11:36.531976 1 4 20 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7591 12:11:36.538263 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7592 12:11:36.541492 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 12:11:36.544722 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 12:11:36.551709 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 12:11:36.554480 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 12:11:36.558549 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7597 12:11:36.564885 1 5 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7598 12:11:36.568082 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7599 12:11:36.571261 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
7600 12:11:36.578416 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 12:11:36.581588 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 12:11:36.584744 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 12:11:36.588351 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 12:11:36.594882 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7605 12:11:36.597942 1 6 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7606 12:11:36.601482 1 6 20 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
7607 12:11:36.607974 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7608 12:11:36.611108 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 12:11:36.614316 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 12:11:36.621510 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 12:11:36.624721 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 12:11:36.627900 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 12:11:36.634261 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 12:11:36.637512 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7615 12:11:36.640730 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7616 12:11:36.647750 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 12:11:36.651001 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 12:11:36.654293 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 12:11:36.660842 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 12:11:36.664239 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 12:11:36.667472 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 12:11:36.674098 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 12:11:36.677747 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 12:11:36.680837 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 12:11:36.687313 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 12:11:36.691218 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 12:11:36.694330 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 12:11:36.700807 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 12:11:36.703819 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7630 12:11:36.707431 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7631 12:11:36.714032 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 12:11:36.714129 Total UI for P1: 0, mck2ui 16
7633 12:11:36.720570 best dqsien dly found for B0: ( 1, 9, 18)
7634 12:11:36.720687 Total UI for P1: 0, mck2ui 16
7635 12:11:36.723839 best dqsien dly found for B1: ( 1, 9, 20)
7636 12:11:36.730402 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7637 12:11:36.733684 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7638 12:11:36.733769
7639 12:11:36.737324 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7640 12:11:36.740508 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7641 12:11:36.743739 [Gating] SW calibration Done
7642 12:11:36.743834 ==
7643 12:11:36.747009 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 12:11:36.750347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 12:11:36.750438 ==
7646 12:11:36.753502 RX Vref Scan: 0
7647 12:11:36.753588
7648 12:11:36.753655 RX Vref 0 -> 0, step: 1
7649 12:11:36.753717
7650 12:11:36.756744 RX Delay 0 -> 252, step: 8
7651 12:11:36.760576 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7652 12:11:36.767171 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7653 12:11:36.769908 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7654 12:11:36.773202 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7655 12:11:36.776578 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7656 12:11:36.780402 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7657 12:11:36.786802 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7658 12:11:36.789947 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7659 12:11:36.793309 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7660 12:11:36.796578 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7661 12:11:36.800456 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7662 12:11:36.806445 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7663 12:11:36.810018 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7664 12:11:36.813654 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7665 12:11:36.816742 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7666 12:11:36.819931 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7667 12:11:36.823371 ==
7668 12:11:36.826444 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 12:11:36.830350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 12:11:36.830463 ==
7671 12:11:36.830589 DQS Delay:
7672 12:11:36.833541 DQS0 = 0, DQS1 = 0
7673 12:11:36.833685 DQM Delay:
7674 12:11:36.836673 DQM0 = 132, DQM1 = 125
7675 12:11:36.836797 DQ Delay:
7676 12:11:36.839862 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7677 12:11:36.843430 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7678 12:11:36.846634 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =123
7679 12:11:36.849959 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7680 12:11:36.850060
7681 12:11:36.850126
7682 12:11:36.850201 ==
7683 12:11:36.853182 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 12:11:36.859653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 12:11:36.859748 ==
7686 12:11:36.859823
7687 12:11:36.859888
7688 12:11:36.859950 TX Vref Scan disable
7689 12:11:36.863637 == TX Byte 0 ==
7690 12:11:36.866990 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7691 12:11:36.873507 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7692 12:11:36.873632 == TX Byte 1 ==
7693 12:11:36.876757 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7694 12:11:36.883301 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7695 12:11:36.883414 ==
7696 12:11:36.887089 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 12:11:36.890142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 12:11:36.890266 ==
7699 12:11:36.904170
7700 12:11:36.907490 TX Vref early break, caculate TX vref
7701 12:11:36.910735 TX Vref=16, minBit 0, minWin=21, winSum=350
7702 12:11:36.913998 TX Vref=18, minBit 0, minWin=22, winSum=369
7703 12:11:36.917670 TX Vref=20, minBit 7, minWin=22, winSum=377
7704 12:11:36.921313 TX Vref=22, minBit 7, minWin=23, winSum=392
7705 12:11:36.924419 TX Vref=24, minBit 7, minWin=23, winSum=398
7706 12:11:36.931200 TX Vref=26, minBit 1, minWin=25, winSum=414
7707 12:11:36.934207 TX Vref=28, minBit 0, minWin=25, winSum=414
7708 12:11:36.937490 TX Vref=30, minBit 4, minWin=24, winSum=419
7709 12:11:36.940718 TX Vref=32, minBit 4, minWin=23, winSum=407
7710 12:11:36.943888 TX Vref=34, minBit 0, minWin=24, winSum=398
7711 12:11:36.947621 TX Vref=36, minBit 0, minWin=23, winSum=390
7712 12:11:36.954044 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 26
7713 12:11:36.954160
7714 12:11:36.957188 Final TX Range 0 Vref 26
7715 12:11:36.957315
7716 12:11:36.957401 ==
7717 12:11:36.960477 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 12:11:36.963753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 12:11:36.963838 ==
7720 12:11:36.963904
7721 12:11:36.963984
7722 12:11:36.967586 TX Vref Scan disable
7723 12:11:36.974135 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7724 12:11:36.974259 == TX Byte 0 ==
7725 12:11:36.977404 u2DelayCellOfst[0]=14 cells (4 PI)
7726 12:11:36.980616 u2DelayCellOfst[1]=21 cells (6 PI)
7727 12:11:36.983862 u2DelayCellOfst[2]=14 cells (4 PI)
7728 12:11:36.987069 u2DelayCellOfst[3]=14 cells (4 PI)
7729 12:11:36.990852 u2DelayCellOfst[4]=10 cells (3 PI)
7730 12:11:36.993926 u2DelayCellOfst[5]=0 cells (0 PI)
7731 12:11:36.997159 u2DelayCellOfst[6]=21 cells (6 PI)
7732 12:11:37.000424 u2DelayCellOfst[7]=21 cells (6 PI)
7733 12:11:37.003823 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7734 12:11:37.007055 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7735 12:11:37.010319 == TX Byte 1 ==
7736 12:11:37.013533 u2DelayCellOfst[8]=0 cells (0 PI)
7737 12:11:37.016810 u2DelayCellOfst[9]=0 cells (0 PI)
7738 12:11:37.020624 u2DelayCellOfst[10]=7 cells (2 PI)
7739 12:11:37.020748 u2DelayCellOfst[11]=0 cells (0 PI)
7740 12:11:37.023777 u2DelayCellOfst[12]=14 cells (4 PI)
7741 12:11:37.026900 u2DelayCellOfst[13]=10 cells (3 PI)
7742 12:11:37.030284 u2DelayCellOfst[14]=17 cells (5 PI)
7743 12:11:37.033530 u2DelayCellOfst[15]=10 cells (3 PI)
7744 12:11:37.040294 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7745 12:11:37.043509 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7746 12:11:37.043635 DramC Write-DBI on
7747 12:11:37.046620 ==
7748 12:11:37.046744 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 12:11:37.053474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 12:11:37.053599 ==
7751 12:11:37.053698
7752 12:11:37.053806
7753 12:11:37.056767 TX Vref Scan disable
7754 12:11:37.056852 == TX Byte 0 ==
7755 12:11:37.063345 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7756 12:11:37.063458 == TX Byte 1 ==
7757 12:11:37.066559 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7758 12:11:37.070282 DramC Write-DBI off
7759 12:11:37.070364
7760 12:11:37.070429 [DATLAT]
7761 12:11:37.073607 Freq=1600, CH0 RK0
7762 12:11:37.073722
7763 12:11:37.073818 DATLAT Default: 0xf
7764 12:11:37.076873 0, 0xFFFF, sum = 0
7765 12:11:37.076958 1, 0xFFFF, sum = 0
7766 12:11:37.080182 2, 0xFFFF, sum = 0
7767 12:11:37.080287 3, 0xFFFF, sum = 0
7768 12:11:37.083430 4, 0xFFFF, sum = 0
7769 12:11:37.083505 5, 0xFFFF, sum = 0
7770 12:11:37.086728 6, 0xFFFF, sum = 0
7771 12:11:37.086805 7, 0xFFFF, sum = 0
7772 12:11:37.089934 8, 0xFFFF, sum = 0
7773 12:11:37.090021 9, 0xFFFF, sum = 0
7774 12:11:37.093174 10, 0xFFFF, sum = 0
7775 12:11:37.096560 11, 0xFFFF, sum = 0
7776 12:11:37.096678 12, 0xFFFF, sum = 0
7777 12:11:37.100240 13, 0xFFFF, sum = 0
7778 12:11:37.100335 14, 0x0, sum = 1
7779 12:11:37.103619 15, 0x0, sum = 2
7780 12:11:37.103707 16, 0x0, sum = 3
7781 12:11:37.103776 17, 0x0, sum = 4
7782 12:11:37.106788 best_step = 15
7783 12:11:37.106903
7784 12:11:37.106998 ==
7785 12:11:37.110108 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 12:11:37.113465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 12:11:37.113574 ==
7788 12:11:37.116752 RX Vref Scan: 1
7789 12:11:37.116860
7790 12:11:37.120002 Set Vref Range= 24 -> 127
7791 12:11:37.120115
7792 12:11:37.120211 RX Vref 24 -> 127, step: 1
7793 12:11:37.120302
7794 12:11:37.123224 RX Delay 11 -> 252, step: 4
7795 12:11:37.123340
7796 12:11:37.126493 Set Vref, RX VrefLevel [Byte0]: 24
7797 12:11:37.129695 [Byte1]: 24
7798 12:11:37.129804
7799 12:11:37.133493 Set Vref, RX VrefLevel [Byte0]: 25
7800 12:11:37.136480 [Byte1]: 25
7801 12:11:37.140797
7802 12:11:37.140916 Set Vref, RX VrefLevel [Byte0]: 26
7803 12:11:37.143849 [Byte1]: 26
7804 12:11:37.148194
7805 12:11:37.148296 Set Vref, RX VrefLevel [Byte0]: 27
7806 12:11:37.151246 [Byte1]: 27
7807 12:11:37.155596
7808 12:11:37.158739 Set Vref, RX VrefLevel [Byte0]: 28
7809 12:11:37.158851 [Byte1]: 28
7810 12:11:37.163080
7811 12:11:37.163188 Set Vref, RX VrefLevel [Byte0]: 29
7812 12:11:37.166432 [Byte1]: 29
7813 12:11:37.170885
7814 12:11:37.170996 Set Vref, RX VrefLevel [Byte0]: 30
7815 12:11:37.174128 [Byte1]: 30
7816 12:11:37.178647
7817 12:11:37.178758 Set Vref, RX VrefLevel [Byte0]: 31
7818 12:11:37.181926 [Byte1]: 31
7819 12:11:37.185947
7820 12:11:37.186062 Set Vref, RX VrefLevel [Byte0]: 32
7821 12:11:37.189805 [Byte1]: 32
7822 12:11:37.193677
7823 12:11:37.193788 Set Vref, RX VrefLevel [Byte0]: 33
7824 12:11:37.196957 [Byte1]: 33
7825 12:11:37.201502
7826 12:11:37.201616 Set Vref, RX VrefLevel [Byte0]: 34
7827 12:11:37.204752 [Byte1]: 34
7828 12:11:37.209203
7829 12:11:37.209318 Set Vref, RX VrefLevel [Byte0]: 35
7830 12:11:37.212508 [Byte1]: 35
7831 12:11:37.216927
7832 12:11:37.217052 Set Vref, RX VrefLevel [Byte0]: 36
7833 12:11:37.220133 [Byte1]: 36
7834 12:11:37.224656
7835 12:11:37.224771 Set Vref, RX VrefLevel [Byte0]: 37
7836 12:11:37.227862 [Byte1]: 37
7837 12:11:37.231698
7838 12:11:37.231832 Set Vref, RX VrefLevel [Byte0]: 38
7839 12:11:37.235024 [Byte1]: 38
7840 12:11:37.239560
7841 12:11:37.239652 Set Vref, RX VrefLevel [Byte0]: 39
7842 12:11:37.242718 [Byte1]: 39
7843 12:11:37.247365
7844 12:11:37.247468 Set Vref, RX VrefLevel [Byte0]: 40
7845 12:11:37.250236 [Byte1]: 40
7846 12:11:37.254692
7847 12:11:37.254780 Set Vref, RX VrefLevel [Byte0]: 41
7848 12:11:37.258289 [Byte1]: 41
7849 12:11:37.262054
7850 12:11:37.262144 Set Vref, RX VrefLevel [Byte0]: 42
7851 12:11:37.265876 [Byte1]: 42
7852 12:11:37.269638
7853 12:11:37.269727 Set Vref, RX VrefLevel [Byte0]: 43
7854 12:11:37.272935 [Byte1]: 43
7855 12:11:37.277607
7856 12:11:37.277689 Set Vref, RX VrefLevel [Byte0]: 44
7857 12:11:37.280678 [Byte1]: 44
7858 12:11:37.285241
7859 12:11:37.285359 Set Vref, RX VrefLevel [Byte0]: 45
7860 12:11:37.291385 [Byte1]: 45
7861 12:11:37.291489
7862 12:11:37.294546 Set Vref, RX VrefLevel [Byte0]: 46
7863 12:11:37.298502 [Byte1]: 46
7864 12:11:37.298591
7865 12:11:37.301757 Set Vref, RX VrefLevel [Byte0]: 47
7866 12:11:37.304938 [Byte1]: 47
7867 12:11:37.305027
7868 12:11:37.308034 Set Vref, RX VrefLevel [Byte0]: 48
7869 12:11:37.311375 [Byte1]: 48
7870 12:11:37.315937
7871 12:11:37.316053 Set Vref, RX VrefLevel [Byte0]: 49
7872 12:11:37.318610 [Byte1]: 49
7873 12:11:37.323012
7874 12:11:37.323138 Set Vref, RX VrefLevel [Byte0]: 50
7875 12:11:37.326254 [Byte1]: 50
7876 12:11:37.330927
7877 12:11:37.331042 Set Vref, RX VrefLevel [Byte0]: 51
7878 12:11:37.334151 [Byte1]: 51
7879 12:11:37.338723
7880 12:11:37.338856 Set Vref, RX VrefLevel [Byte0]: 52
7881 12:11:37.341893 [Byte1]: 52
7882 12:11:37.345860
7883 12:11:37.345970 Set Vref, RX VrefLevel [Byte0]: 53
7884 12:11:37.349122 [Byte1]: 53
7885 12:11:37.353898
7886 12:11:37.354018 Set Vref, RX VrefLevel [Byte0]: 54
7887 12:11:37.357015 [Byte1]: 54
7888 12:11:37.361131
7889 12:11:37.361222 Set Vref, RX VrefLevel [Byte0]: 55
7890 12:11:37.364981 [Byte1]: 55
7891 12:11:37.368635
7892 12:11:37.368729 Set Vref, RX VrefLevel [Byte0]: 56
7893 12:11:37.372307 [Byte1]: 56
7894 12:11:37.376978
7895 12:11:37.377103 Set Vref, RX VrefLevel [Byte0]: 57
7896 12:11:37.379553 [Byte1]: 57
7897 12:11:37.384031
7898 12:11:37.384138 Set Vref, RX VrefLevel [Byte0]: 58
7899 12:11:37.390574 [Byte1]: 58
7900 12:11:37.390662
7901 12:11:37.393742 Set Vref, RX VrefLevel [Byte0]: 59
7902 12:11:37.396999 [Byte1]: 59
7903 12:11:37.397107
7904 12:11:37.400195 Set Vref, RX VrefLevel [Byte0]: 60
7905 12:11:37.404056 [Byte1]: 60
7906 12:11:37.407200
7907 12:11:37.407314 Set Vref, RX VrefLevel [Byte0]: 61
7908 12:11:37.410449 [Byte1]: 61
7909 12:11:37.414889
7910 12:11:37.415009 Set Vref, RX VrefLevel [Byte0]: 62
7911 12:11:37.418050 [Byte1]: 62
7912 12:11:37.421979
7913 12:11:37.422066 Set Vref, RX VrefLevel [Byte0]: 63
7914 12:11:37.425275 [Byte1]: 63
7915 12:11:37.429740
7916 12:11:37.429828 Set Vref, RX VrefLevel [Byte0]: 64
7917 12:11:37.432999 [Byte1]: 64
7918 12:11:37.437428
7919 12:11:37.437517 Set Vref, RX VrefLevel [Byte0]: 65
7920 12:11:37.440627 [Byte1]: 65
7921 12:11:37.445180
7922 12:11:37.445296 Set Vref, RX VrefLevel [Byte0]: 66
7923 12:11:37.448414 [Byte1]: 66
7924 12:11:37.452986
7925 12:11:37.453083 Set Vref, RX VrefLevel [Byte0]: 67
7926 12:11:37.456127 [Byte1]: 67
7927 12:11:37.460050
7928 12:11:37.460172 Set Vref, RX VrefLevel [Byte0]: 68
7929 12:11:37.463721 [Byte1]: 68
7930 12:11:37.468041
7931 12:11:37.468130 Set Vref, RX VrefLevel [Byte0]: 69
7932 12:11:37.471044 [Byte1]: 69
7933 12:11:37.475255
7934 12:11:37.475383 Set Vref, RX VrefLevel [Byte0]: 70
7935 12:11:37.479074 [Byte1]: 70
7936 12:11:37.483422
7937 12:11:37.483546 Set Vref, RX VrefLevel [Byte0]: 71
7938 12:11:37.486737 [Byte1]: 71
7939 12:11:37.490699
7940 12:11:37.490831 Set Vref, RX VrefLevel [Byte0]: 72
7941 12:11:37.494022 [Byte1]: 72
7942 12:11:37.498636
7943 12:11:37.498760 Set Vref, RX VrefLevel [Byte0]: 73
7944 12:11:37.501730 [Byte1]: 73
7945 12:11:37.506217
7946 12:11:37.506355 Set Vref, RX VrefLevel [Byte0]: 74
7947 12:11:37.508922 [Byte1]: 74
7948 12:11:37.513539
7949 12:11:37.513655 Set Vref, RX VrefLevel [Byte0]: 75
7950 12:11:37.516731 [Byte1]: 75
7951 12:11:37.521216
7952 12:11:37.521313 Set Vref, RX VrefLevel [Byte0]: 76
7953 12:11:37.524423 [Byte1]: 76
7954 12:11:37.529130
7955 12:11:37.529228 Final RX Vref Byte 0 = 61 to rank0
7956 12:11:37.531733 Final RX Vref Byte 1 = 63 to rank0
7957 12:11:37.535716 Final RX Vref Byte 0 = 61 to rank1
7958 12:11:37.538911 Final RX Vref Byte 1 = 63 to rank1==
7959 12:11:37.542157 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 12:11:37.548793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 12:11:37.548917 ==
7962 12:11:37.549002 DQS Delay:
7963 12:11:37.549077 DQS0 = 0, DQS1 = 0
7964 12:11:37.551980 DQM Delay:
7965 12:11:37.552078 DQM0 = 129, DQM1 = 122
7966 12:11:37.555202 DQ Delay:
7967 12:11:37.558447 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7968 12:11:37.561666 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7969 12:11:37.564858 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7970 12:11:37.568745 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =132
7971 12:11:37.568840
7972 12:11:37.568910
7973 12:11:37.568977
7974 12:11:37.571804 [DramC_TX_OE_Calibration] TA2
7975 12:11:37.575313 Original DQ_B0 (3 6) =30, OEN = 27
7976 12:11:37.578467 Original DQ_B1 (3 6) =30, OEN = 27
7977 12:11:37.581491 24, 0x0, End_B0=24 End_B1=24
7978 12:11:37.581584 25, 0x0, End_B0=25 End_B1=25
7979 12:11:37.585080 26, 0x0, End_B0=26 End_B1=26
7980 12:11:37.588267 27, 0x0, End_B0=27 End_B1=27
7981 12:11:37.591553 28, 0x0, End_B0=28 End_B1=28
7982 12:11:37.595466 29, 0x0, End_B0=29 End_B1=29
7983 12:11:37.595560 30, 0x0, End_B0=30 End_B1=30
7984 12:11:37.598636 31, 0x5151, End_B0=30 End_B1=30
7985 12:11:37.601796 Byte0 end_step=30 best_step=27
7986 12:11:37.605068 Byte1 end_step=30 best_step=27
7987 12:11:37.608271 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 12:11:37.611453 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 12:11:37.611583
7990 12:11:37.611661
7991 12:11:37.618699 [DQSOSCAuto] RK0, (LSB)MR18= 0x1206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7992 12:11:37.621951 CH0 RK0: MR19=303, MR18=1206
7993 12:11:37.628222 CH0_RK0: MR19=0x303, MR18=0x1206, DQSOSC=400, MR23=63, INC=23, DEC=15
7994 12:11:37.628337
7995 12:11:37.631544 ----->DramcWriteLeveling(PI) begin...
7996 12:11:37.631629 ==
7997 12:11:37.634738 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 12:11:37.638617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 12:11:37.638731 ==
8000 12:11:37.641846 Write leveling (Byte 0): 34 => 34
8001 12:11:37.645114 Write leveling (Byte 1): 28 => 28
8002 12:11:37.648321 DramcWriteLeveling(PI) end<-----
8003 12:11:37.648424
8004 12:11:37.648528 ==
8005 12:11:37.651532 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 12:11:37.654763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 12:11:37.654874 ==
8008 12:11:37.657961 [Gating] SW mode calibration
8009 12:11:37.665261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 12:11:37.671077 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 12:11:37.674489 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 12:11:37.681301 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 12:11:37.684264 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8014 12:11:37.688041 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8015 12:11:37.694234 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8016 12:11:37.697975 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8017 12:11:37.701161 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 12:11:37.704483 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 12:11:37.710983 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 12:11:37.714294 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8021 12:11:37.717599 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8022 12:11:37.724568 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
8023 12:11:37.727899 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8024 12:11:37.730997 1 5 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8025 12:11:37.737347 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 12:11:37.741212 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 12:11:37.744326 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 12:11:37.750777 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 12:11:37.754113 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8030 12:11:37.757289 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8031 12:11:37.763911 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8032 12:11:37.767102 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8033 12:11:37.770858 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 12:11:37.777256 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 12:11:37.780553 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 12:11:37.783790 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 12:11:37.790639 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 12:11:37.793719 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 12:11:37.797473 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8040 12:11:37.803701 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 12:11:37.806994 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8042 12:11:37.810130 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 12:11:37.817081 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 12:11:37.820311 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 12:11:37.823606 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 12:11:37.830197 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 12:11:37.833509 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 12:11:37.837307 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 12:11:37.843726 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 12:11:37.846908 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:11:37.850186 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:11:37.856660 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8053 12:11:37.860579 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 12:11:37.863776 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8055 12:11:37.870005 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8056 12:11:37.870106 Total UI for P1: 0, mck2ui 16
8057 12:11:37.873184 best dqsien dly found for B0: ( 1, 9, 12)
8058 12:11:37.879756 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8059 12:11:37.883631 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 12:11:37.886774 Total UI for P1: 0, mck2ui 16
8061 12:11:37.889949 best dqsien dly found for B1: ( 1, 9, 20)
8062 12:11:37.893234 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8063 12:11:37.896796 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8064 12:11:37.896894
8065 12:11:37.899850 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8066 12:11:37.906749 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8067 12:11:37.906863 [Gating] SW calibration Done
8068 12:11:37.909800 ==
8069 12:11:37.913052 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 12:11:37.916301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 12:11:37.916424 ==
8072 12:11:37.916533 RX Vref Scan: 0
8073 12:11:37.916643
8074 12:11:37.919597 RX Vref 0 -> 0, step: 1
8075 12:11:37.919704
8076 12:11:37.923449 RX Delay 0 -> 252, step: 8
8077 12:11:37.926674 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8078 12:11:37.930020 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8079 12:11:37.933230 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8080 12:11:37.939557 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8081 12:11:37.943295 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8082 12:11:37.946578 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8083 12:11:37.949833 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8084 12:11:37.952938 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8085 12:11:37.959457 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8086 12:11:37.963397 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8087 12:11:37.966538 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8088 12:11:37.969727 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8089 12:11:37.972749 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8090 12:11:37.979242 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8091 12:11:37.983091 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8092 12:11:37.986383 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8093 12:11:37.986494 ==
8094 12:11:37.989610 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 12:11:37.992993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 12:11:37.993093 ==
8097 12:11:37.996178 DQS Delay:
8098 12:11:37.996260 DQS0 = 0, DQS1 = 0
8099 12:11:37.999406 DQM Delay:
8100 12:11:37.999505 DQM0 = 131, DQM1 = 126
8101 12:11:38.002573 DQ Delay:
8102 12:11:38.006218 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8103 12:11:38.009186 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8104 12:11:38.012882 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
8105 12:11:38.016106 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
8106 12:11:38.016205
8107 12:11:38.016291
8108 12:11:38.016358 ==
8109 12:11:38.019100 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 12:11:38.022978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 12:11:38.023066 ==
8112 12:11:38.023133
8113 12:11:38.023195
8114 12:11:38.026099 TX Vref Scan disable
8115 12:11:38.029232 == TX Byte 0 ==
8116 12:11:38.032533 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8117 12:11:38.036225 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8118 12:11:38.039558 == TX Byte 1 ==
8119 12:11:38.042747 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8120 12:11:38.046058 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8121 12:11:38.046170 ==
8122 12:11:38.049010 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 12:11:38.056077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 12:11:38.056210 ==
8125 12:11:38.068788
8126 12:11:38.072610 TX Vref early break, caculate TX vref
8127 12:11:38.075949 TX Vref=16, minBit 0, minWin=23, winSum=376
8128 12:11:38.079142 TX Vref=18, minBit 3, minWin=23, winSum=391
8129 12:11:38.082430 TX Vref=20, minBit 3, minWin=23, winSum=391
8130 12:11:38.085614 TX Vref=22, minBit 9, minWin=24, winSum=404
8131 12:11:38.088756 TX Vref=24, minBit 8, minWin=24, winSum=413
8132 12:11:38.095821 TX Vref=26, minBit 4, minWin=25, winSum=425
8133 12:11:38.098990 TX Vref=28, minBit 4, minWin=25, winSum=427
8134 12:11:38.102184 TX Vref=30, minBit 10, minWin=25, winSum=424
8135 12:11:38.105455 TX Vref=32, minBit 5, minWin=25, winSum=421
8136 12:11:38.109158 TX Vref=34, minBit 4, minWin=24, winSum=410
8137 12:11:38.112053 TX Vref=36, minBit 13, minWin=23, winSum=398
8138 12:11:38.118824 [TxChooseVref] Worse bit 4, Min win 25, Win sum 427, Final Vref 28
8139 12:11:38.118947
8140 12:11:38.122078 Final TX Range 0 Vref 28
8141 12:11:38.122188
8142 12:11:38.122288 ==
8143 12:11:38.125240 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 12:11:38.128963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 12:11:38.129078 ==
8146 12:11:38.129182
8147 12:11:38.132276
8148 12:11:38.132388 TX Vref Scan disable
8149 12:11:38.138672 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8150 12:11:38.138780 == TX Byte 0 ==
8151 12:11:38.141925 u2DelayCellOfst[0]=14 cells (4 PI)
8152 12:11:38.145123 u2DelayCellOfst[1]=17 cells (5 PI)
8153 12:11:38.148414 u2DelayCellOfst[2]=7 cells (2 PI)
8154 12:11:38.152164 u2DelayCellOfst[3]=10 cells (3 PI)
8155 12:11:38.155268 u2DelayCellOfst[4]=7 cells (2 PI)
8156 12:11:38.158506 u2DelayCellOfst[5]=0 cells (0 PI)
8157 12:11:38.161768 u2DelayCellOfst[6]=14 cells (4 PI)
8158 12:11:38.165524 u2DelayCellOfst[7]=17 cells (5 PI)
8159 12:11:38.168767 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8160 12:11:38.171997 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8161 12:11:38.175173 == TX Byte 1 ==
8162 12:11:38.178420 u2DelayCellOfst[8]=0 cells (0 PI)
8163 12:11:38.181698 u2DelayCellOfst[9]=0 cells (0 PI)
8164 12:11:38.181812 u2DelayCellOfst[10]=7 cells (2 PI)
8165 12:11:38.184994 u2DelayCellOfst[11]=0 cells (0 PI)
8166 12:11:38.188757 u2DelayCellOfst[12]=14 cells (4 PI)
8167 12:11:38.191983 u2DelayCellOfst[13]=10 cells (3 PI)
8168 12:11:38.195263 u2DelayCellOfst[14]=17 cells (5 PI)
8169 12:11:38.198637 u2DelayCellOfst[15]=10 cells (3 PI)
8170 12:11:38.205026 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8171 12:11:38.208427 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8172 12:11:38.208533 DramC Write-DBI on
8173 12:11:38.208603 ==
8174 12:11:38.211629 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 12:11:38.218417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 12:11:38.218522 ==
8177 12:11:38.218631
8178 12:11:38.218721
8179 12:11:38.218786 TX Vref Scan disable
8180 12:11:38.222188 == TX Byte 0 ==
8181 12:11:38.226068 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8182 12:11:38.229145 == TX Byte 1 ==
8183 12:11:38.232312 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8184 12:11:38.235478 DramC Write-DBI off
8185 12:11:38.235599
8186 12:11:38.235706 [DATLAT]
8187 12:11:38.235813 Freq=1600, CH0 RK1
8188 12:11:38.235914
8189 12:11:38.239370 DATLAT Default: 0xf
8190 12:11:38.239455 0, 0xFFFF, sum = 0
8191 12:11:38.242677 1, 0xFFFF, sum = 0
8192 12:11:38.245891 2, 0xFFFF, sum = 0
8193 12:11:38.246011 3, 0xFFFF, sum = 0
8194 12:11:38.249125 4, 0xFFFF, sum = 0
8195 12:11:38.249248 5, 0xFFFF, sum = 0
8196 12:11:38.252449 6, 0xFFFF, sum = 0
8197 12:11:38.252566 7, 0xFFFF, sum = 0
8198 12:11:38.255695 8, 0xFFFF, sum = 0
8199 12:11:38.255813 9, 0xFFFF, sum = 0
8200 12:11:38.258792 10, 0xFFFF, sum = 0
8201 12:11:38.258912 11, 0xFFFF, sum = 0
8202 12:11:38.262050 12, 0xFFFF, sum = 0
8203 12:11:38.262182 13, 0xFFFF, sum = 0
8204 12:11:38.265260 14, 0x0, sum = 1
8205 12:11:38.265376 15, 0x0, sum = 2
8206 12:11:38.269049 16, 0x0, sum = 3
8207 12:11:38.269184 17, 0x0, sum = 4
8208 12:11:38.272321 best_step = 15
8209 12:11:38.272432
8210 12:11:38.272546 ==
8211 12:11:38.275672 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 12:11:38.279320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 12:11:38.279446 ==
8214 12:11:38.282447 RX Vref Scan: 0
8215 12:11:38.282556
8216 12:11:38.282657 RX Vref 0 -> 0, step: 1
8217 12:11:38.282752
8218 12:11:38.285705 RX Delay 11 -> 252, step: 4
8219 12:11:38.288925 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8220 12:11:38.295283 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8221 12:11:38.298643 iDelay=195, Bit 2, Center 124 (67 ~ 182) 116
8222 12:11:38.301868 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8223 12:11:38.305207 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8224 12:11:38.309265 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8225 12:11:38.315562 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
8226 12:11:38.318720 iDelay=195, Bit 7, Center 134 (79 ~ 190) 112
8227 12:11:38.322423 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8228 12:11:38.325313 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8229 12:11:38.329034 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8230 12:11:38.335190 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8231 12:11:38.338906 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8232 12:11:38.341894 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8233 12:11:38.345711 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8234 12:11:38.349013 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8235 12:11:38.352237 ==
8236 12:11:38.355514 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 12:11:38.358843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 12:11:38.358960 ==
8239 12:11:38.359071 DQS Delay:
8240 12:11:38.361991 DQS0 = 0, DQS1 = 0
8241 12:11:38.362122 DQM Delay:
8242 12:11:38.365194 DQM0 = 127, DQM1 = 122
8243 12:11:38.365325 DQ Delay:
8244 12:11:38.368478 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8245 12:11:38.371664 DQ4 =126, DQ5 =116, DQ6 =136, DQ7 =134
8246 12:11:38.374961 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8247 12:11:38.378663 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8248 12:11:38.378779
8249 12:11:38.378892
8250 12:11:38.378987
8251 12:11:38.381910 [DramC_TX_OE_Calibration] TA2
8252 12:11:38.385174 Original DQ_B0 (3 6) =30, OEN = 27
8253 12:11:38.388412 Original DQ_B1 (3 6) =30, OEN = 27
8254 12:11:38.391741 24, 0x0, End_B0=24 End_B1=24
8255 12:11:38.395622 25, 0x0, End_B0=25 End_B1=25
8256 12:11:38.395714 26, 0x0, End_B0=26 End_B1=26
8257 12:11:38.398806 27, 0x0, End_B0=27 End_B1=27
8258 12:11:38.402050 28, 0x0, End_B0=28 End_B1=28
8259 12:11:38.405325 29, 0x0, End_B0=29 End_B1=29
8260 12:11:38.408638 30, 0x0, End_B0=30 End_B1=30
8261 12:11:38.408731 31, 0x4141, End_B0=30 End_B1=30
8262 12:11:38.411854 Byte0 end_step=30 best_step=27
8263 12:11:38.415111 Byte1 end_step=30 best_step=27
8264 12:11:38.418172 Byte0 TX OE(2T, 0.5T) = (3, 3)
8265 12:11:38.421995 Byte1 TX OE(2T, 0.5T) = (3, 3)
8266 12:11:38.422112
8267 12:11:38.422226
8268 12:11:38.428579 [DQSOSCAuto] RK1, (LSB)MR18= 0x1609, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
8269 12:11:38.431470 CH0 RK1: MR19=303, MR18=1609
8270 12:11:38.438690 CH0_RK1: MR19=0x303, MR18=0x1609, DQSOSC=398, MR23=63, INC=23, DEC=15
8271 12:11:38.441976 [RxdqsGatingPostProcess] freq 1600
8272 12:11:38.448660 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8273 12:11:38.448834 best DQS0 dly(2T, 0.5T) = (1, 1)
8274 12:11:38.451720 best DQS1 dly(2T, 0.5T) = (1, 1)
8275 12:11:38.455085 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8276 12:11:38.458277 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8277 12:11:38.461501 best DQS0 dly(2T, 0.5T) = (1, 1)
8278 12:11:38.464606 best DQS1 dly(2T, 0.5T) = (1, 1)
8279 12:11:38.468526 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8280 12:11:38.471745 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8281 12:11:38.474914 Pre-setting of DQS Precalculation
8282 12:11:38.478247 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8283 12:11:38.478342 ==
8284 12:11:38.481627 Dram Type= 6, Freq= 0, CH_1, rank 0
8285 12:11:38.488104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 12:11:38.488198 ==
8287 12:11:38.491472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8288 12:11:38.497810 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8289 12:11:38.501602 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8290 12:11:38.508113 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8291 12:11:38.515930 [CA 0] Center 42 (13~71) winsize 59
8292 12:11:38.518610 [CA 1] Center 42 (13~71) winsize 59
8293 12:11:38.522526 [CA 2] Center 37 (8~66) winsize 59
8294 12:11:38.525858 [CA 3] Center 36 (7~65) winsize 59
8295 12:11:38.529026 [CA 4] Center 37 (7~67) winsize 61
8296 12:11:38.532355 [CA 5] Center 36 (7~66) winsize 60
8297 12:11:38.532434
8298 12:11:38.535588 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8299 12:11:38.535675
8300 12:11:38.538746 [CATrainingPosCal] consider 1 rank data
8301 12:11:38.542405 u2DelayCellTimex100 = 275/100 ps
8302 12:11:38.545453 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8303 12:11:38.552158 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8304 12:11:38.555202 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8305 12:11:38.558934 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8306 12:11:38.562154 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8307 12:11:38.565442 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8308 12:11:38.565558
8309 12:11:38.568670 CA PerBit enable=1, Macro0, CA PI delay=36
8310 12:11:38.568779
8311 12:11:38.571856 [CBTSetCACLKResult] CA Dly = 36
8312 12:11:38.575508 CS Dly: 9 (0~40)
8313 12:11:38.578492 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8314 12:11:38.581728 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8315 12:11:38.581832 ==
8316 12:11:38.584905 Dram Type= 6, Freq= 0, CH_1, rank 1
8317 12:11:38.588132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 12:11:38.592042 ==
8319 12:11:38.595180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8320 12:11:38.598547 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8321 12:11:38.605166 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8322 12:11:38.608242 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8323 12:11:38.618703 [CA 0] Center 43 (14~73) winsize 60
8324 12:11:38.622024 [CA 1] Center 43 (14~72) winsize 59
8325 12:11:38.625139 [CA 2] Center 38 (9~67) winsize 59
8326 12:11:38.628535 [CA 3] Center 37 (8~66) winsize 59
8327 12:11:38.631728 [CA 4] Center 38 (9~68) winsize 60
8328 12:11:38.635543 [CA 5] Center 36 (7~66) winsize 60
8329 12:11:38.635630
8330 12:11:38.638742 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8331 12:11:38.638826
8332 12:11:38.642102 [CATrainingPosCal] consider 2 rank data
8333 12:11:38.645287 u2DelayCellTimex100 = 275/100 ps
8334 12:11:38.648587 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8335 12:11:38.655111 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8336 12:11:38.658717 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8337 12:11:38.661906 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8338 12:11:38.664838 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8339 12:11:38.668551 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8340 12:11:38.668640
8341 12:11:38.671731 CA PerBit enable=1, Macro0, CA PI delay=36
8342 12:11:38.671816
8343 12:11:38.674876 [CBTSetCACLKResult] CA Dly = 36
8344 12:11:38.678057 CS Dly: 11 (0~44)
8345 12:11:38.681850 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8346 12:11:38.685009 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8347 12:11:38.685099
8348 12:11:38.688099 ----->DramcWriteLeveling(PI) begin...
8349 12:11:38.688187 ==
8350 12:11:38.691948 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 12:11:38.698332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 12:11:38.698427 ==
8353 12:11:38.701561 Write leveling (Byte 0): 25 => 25
8354 12:11:38.701646 Write leveling (Byte 1): 27 => 27
8355 12:11:38.704647 DramcWriteLeveling(PI) end<-----
8356 12:11:38.704745
8357 12:11:38.704813 ==
8358 12:11:38.708615 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 12:11:38.715137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 12:11:38.715265 ==
8361 12:11:38.718471 [Gating] SW mode calibration
8362 12:11:38.724993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8363 12:11:38.728253 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8364 12:11:38.734694 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 12:11:38.737985 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 12:11:38.741854 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 12:11:38.748344 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 12:11:38.751612 1 4 16 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (0 0)
8369 12:11:38.754788 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 12:11:38.761150 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 12:11:38.764707 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 12:11:38.767742 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 12:11:38.774664 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 12:11:38.777635 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 12:11:38.781462 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8376 12:11:38.787768 1 5 16 | B1->B0 | 2e2e 3434 | 0 1 | (1 0) (1 0)
8377 12:11:38.790917 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8378 12:11:38.794701 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 12:11:38.797892 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 12:11:38.804287 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 12:11:38.807625 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 12:11:38.810819 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 12:11:38.817386 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 12:11:38.820574 1 6 16 | B1->B0 | 3838 2c2c | 0 0 | (0 0) (0 0)
8385 12:11:38.823901 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 12:11:38.830798 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 12:11:38.834120 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 12:11:38.837290 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 12:11:38.844225 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 12:11:38.847662 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 12:11:38.850846 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 12:11:38.857373 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8393 12:11:38.860709 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 12:11:38.863929 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 12:11:38.870582 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 12:11:38.874049 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 12:11:38.877079 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 12:11:38.883455 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 12:11:38.887113 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 12:11:38.890393 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 12:11:38.897132 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:11:38.900400 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:11:38.903638 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:11:38.910128 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:11:38.913926 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:11:38.917105 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:11:38.923621 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8408 12:11:38.926924 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 12:11:38.930161 Total UI for P1: 0, mck2ui 16
8410 12:11:38.933397 best dqsien dly found for B0: ( 1, 9, 12)
8411 12:11:38.936715 Total UI for P1: 0, mck2ui 16
8412 12:11:38.940584 best dqsien dly found for B1: ( 1, 9, 14)
8413 12:11:38.943853 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8414 12:11:38.946953 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8415 12:11:38.947061
8416 12:11:38.950203 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8417 12:11:38.953470 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8418 12:11:38.956729 [Gating] SW calibration Done
8419 12:11:38.956811 ==
8420 12:11:38.960542 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 12:11:38.963922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 12:11:38.967100 ==
8423 12:11:38.967217 RX Vref Scan: 0
8424 12:11:38.967319
8425 12:11:38.970441 RX Vref 0 -> 0, step: 1
8426 12:11:38.970547
8427 12:11:38.970644 RX Delay 0 -> 252, step: 8
8428 12:11:38.976640 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8429 12:11:38.980075 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8430 12:11:38.983667 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8431 12:11:38.986716 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8432 12:11:38.989874 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8433 12:11:38.996898 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8434 12:11:38.999968 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8435 12:11:39.003684 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8436 12:11:39.006830 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8437 12:11:39.009864 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8438 12:11:39.016963 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8439 12:11:39.020268 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8440 12:11:39.023556 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8441 12:11:39.026718 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8442 12:11:39.029891 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8443 12:11:39.036450 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8444 12:11:39.036585 ==
8445 12:11:39.039715 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 12:11:39.043639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 12:11:39.043722 ==
8448 12:11:39.043788 DQS Delay:
8449 12:11:39.047001 DQS0 = 0, DQS1 = 0
8450 12:11:39.047178 DQM Delay:
8451 12:11:39.050210 DQM0 = 133, DQM1 = 127
8452 12:11:39.050323 DQ Delay:
8453 12:11:39.053465 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8454 12:11:39.056652 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8455 12:11:39.059800 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8456 12:11:39.063063 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8457 12:11:39.066788
8458 12:11:39.066888
8459 12:11:39.066956 ==
8460 12:11:39.069492 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 12:11:39.073283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 12:11:39.073370 ==
8463 12:11:39.073449
8464 12:11:39.073519
8465 12:11:39.076595 TX Vref Scan disable
8466 12:11:39.076679 == TX Byte 0 ==
8467 12:11:39.082894 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8468 12:11:39.086344 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8469 12:11:39.086433 == TX Byte 1 ==
8470 12:11:39.092823 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8471 12:11:39.096300 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8472 12:11:39.096399 ==
8473 12:11:39.099326 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 12:11:39.103052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 12:11:39.103169 ==
8476 12:11:39.116485
8477 12:11:39.119465 TX Vref early break, caculate TX vref
8478 12:11:39.123137 TX Vref=16, minBit 8, minWin=21, winSum=367
8479 12:11:39.125884 TX Vref=18, minBit 5, minWin=22, winSum=373
8480 12:11:39.129700 TX Vref=20, minBit 8, minWin=22, winSum=385
8481 12:11:39.132826 TX Vref=22, minBit 5, minWin=23, winSum=393
8482 12:11:39.136132 TX Vref=24, minBit 5, minWin=24, winSum=403
8483 12:11:39.142670 TX Vref=26, minBit 8, minWin=25, winSum=417
8484 12:11:39.145915 TX Vref=28, minBit 0, minWin=26, winSum=423
8485 12:11:39.149118 TX Vref=30, minBit 0, minWin=26, winSum=421
8486 12:11:39.152362 TX Vref=32, minBit 0, minWin=25, winSum=412
8487 12:11:39.156226 TX Vref=34, minBit 0, minWin=24, winSum=400
8488 12:11:39.162677 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
8489 12:11:39.162774
8490 12:11:39.165954 Final TX Range 0 Vref 28
8491 12:11:39.166077
8492 12:11:39.166175 ==
8493 12:11:39.169259 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 12:11:39.172661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 12:11:39.172745 ==
8496 12:11:39.172820
8497 12:11:39.172911
8498 12:11:39.175747 TX Vref Scan disable
8499 12:11:39.182452 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8500 12:11:39.182547 == TX Byte 0 ==
8501 12:11:39.185634 u2DelayCellOfst[0]=17 cells (5 PI)
8502 12:11:39.188941 u2DelayCellOfst[1]=10 cells (3 PI)
8503 12:11:39.192653 u2DelayCellOfst[2]=0 cells (0 PI)
8504 12:11:39.195760 u2DelayCellOfst[3]=7 cells (2 PI)
8505 12:11:39.198962 u2DelayCellOfst[4]=10 cells (3 PI)
8506 12:11:39.202552 u2DelayCellOfst[5]=17 cells (5 PI)
8507 12:11:39.205582 u2DelayCellOfst[6]=17 cells (5 PI)
8508 12:11:39.209313 u2DelayCellOfst[7]=7 cells (2 PI)
8509 12:11:39.212327 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8510 12:11:39.215444 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8511 12:11:39.219105 == TX Byte 1 ==
8512 12:11:39.219228 u2DelayCellOfst[8]=0 cells (0 PI)
8513 12:11:39.222074 u2DelayCellOfst[9]=3 cells (1 PI)
8514 12:11:39.225348 u2DelayCellOfst[10]=10 cells (3 PI)
8515 12:11:39.228567 u2DelayCellOfst[11]=7 cells (2 PI)
8516 12:11:39.232498 u2DelayCellOfst[12]=14 cells (4 PI)
8517 12:11:39.235675 u2DelayCellOfst[13]=14 cells (4 PI)
8518 12:11:39.238959 u2DelayCellOfst[14]=17 cells (5 PI)
8519 12:11:39.242142 u2DelayCellOfst[15]=17 cells (5 PI)
8520 12:11:39.245554 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8521 12:11:39.252000 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8522 12:11:39.252148 DramC Write-DBI on
8523 12:11:39.252268 ==
8524 12:11:39.255167 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 12:11:39.261611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 12:11:39.261732 ==
8527 12:11:39.261843
8528 12:11:39.261937
8529 12:11:39.262039 TX Vref Scan disable
8530 12:11:39.265524 == TX Byte 0 ==
8531 12:11:39.268739 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8532 12:11:39.271996 == TX Byte 1 ==
8533 12:11:39.275279 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8534 12:11:39.278547 DramC Write-DBI off
8535 12:11:39.278632
8536 12:11:39.278699 [DATLAT]
8537 12:11:39.278761 Freq=1600, CH1 RK0
8538 12:11:39.278821
8539 12:11:39.281941 DATLAT Default: 0xf
8540 12:11:39.282029 0, 0xFFFF, sum = 0
8541 12:11:39.285779 1, 0xFFFF, sum = 0
8542 12:11:39.289038 2, 0xFFFF, sum = 0
8543 12:11:39.289129 3, 0xFFFF, sum = 0
8544 12:11:39.292323 4, 0xFFFF, sum = 0
8545 12:11:39.292412 5, 0xFFFF, sum = 0
8546 12:11:39.295605 6, 0xFFFF, sum = 0
8547 12:11:39.295706 7, 0xFFFF, sum = 0
8548 12:11:39.298619 8, 0xFFFF, sum = 0
8549 12:11:39.298748 9, 0xFFFF, sum = 0
8550 12:11:39.302231 10, 0xFFFF, sum = 0
8551 12:11:39.302343 11, 0xFFFF, sum = 0
8552 12:11:39.305197 12, 0xFFFF, sum = 0
8553 12:11:39.305277 13, 0xFFFF, sum = 0
8554 12:11:39.308746 14, 0x0, sum = 1
8555 12:11:39.308857 15, 0x0, sum = 2
8556 12:11:39.311792 16, 0x0, sum = 3
8557 12:11:39.311874 17, 0x0, sum = 4
8558 12:11:39.315405 best_step = 15
8559 12:11:39.315527
8560 12:11:39.315621 ==
8561 12:11:39.318489 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 12:11:39.321654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 12:11:39.321734 ==
8564 12:11:39.324854 RX Vref Scan: 1
8565 12:11:39.324937
8566 12:11:39.325044 Set Vref Range= 24 -> 127
8567 12:11:39.325134
8568 12:11:39.328486 RX Vref 24 -> 127, step: 1
8569 12:11:39.328568
8570 12:11:39.331593 RX Delay 19 -> 252, step: 4
8571 12:11:39.331673
8572 12:11:39.334813 Set Vref, RX VrefLevel [Byte0]: 24
8573 12:11:39.338703 [Byte1]: 24
8574 12:11:39.338821
8575 12:11:39.341904 Set Vref, RX VrefLevel [Byte0]: 25
8576 12:11:39.345122 [Byte1]: 25
8577 12:11:39.348256
8578 12:11:39.348338 Set Vref, RX VrefLevel [Byte0]: 26
8579 12:11:39.351514 [Byte1]: 26
8580 12:11:39.355994
8581 12:11:39.356111 Set Vref, RX VrefLevel [Byte0]: 27
8582 12:11:39.359055 [Byte1]: 27
8583 12:11:39.363579
8584 12:11:39.363667 Set Vref, RX VrefLevel [Byte0]: 28
8585 12:11:39.366889 [Byte1]: 28
8586 12:11:39.371280
8587 12:11:39.371393 Set Vref, RX VrefLevel [Byte0]: 29
8588 12:11:39.374575 [Byte1]: 29
8589 12:11:39.378512
8590 12:11:39.378602 Set Vref, RX VrefLevel [Byte0]: 30
8591 12:11:39.381908 [Byte1]: 30
8592 12:11:39.386303
8593 12:11:39.386415 Set Vref, RX VrefLevel [Byte0]: 31
8594 12:11:39.389515 [Byte1]: 31
8595 12:11:39.393882
8596 12:11:39.393972 Set Vref, RX VrefLevel [Byte0]: 32
8597 12:11:39.396998 [Byte1]: 32
8598 12:11:39.401493
8599 12:11:39.401581 Set Vref, RX VrefLevel [Byte0]: 33
8600 12:11:39.404683 [Byte1]: 33
8601 12:11:39.409081
8602 12:11:39.409170 Set Vref, RX VrefLevel [Byte0]: 34
8603 12:11:39.412255 [Byte1]: 34
8604 12:11:39.416296
8605 12:11:39.416418 Set Vref, RX VrefLevel [Byte0]: 35
8606 12:11:39.419529 [Byte1]: 35
8607 12:11:39.423802
8608 12:11:39.423885 Set Vref, RX VrefLevel [Byte0]: 36
8609 12:11:39.427491 [Byte1]: 36
8610 12:11:39.431872
8611 12:11:39.431968 Set Vref, RX VrefLevel [Byte0]: 37
8612 12:11:39.435102 [Byte1]: 37
8613 12:11:39.439395
8614 12:11:39.439521 Set Vref, RX VrefLevel [Byte0]: 38
8615 12:11:39.442577 [Byte1]: 38
8616 12:11:39.446483
8617 12:11:39.446596 Set Vref, RX VrefLevel [Byte0]: 39
8618 12:11:39.449788 [Byte1]: 39
8619 12:11:39.454242
8620 12:11:39.454338 Set Vref, RX VrefLevel [Byte0]: 40
8621 12:11:39.457576 [Byte1]: 40
8622 12:11:39.462105
8623 12:11:39.462199 Set Vref, RX VrefLevel [Byte0]: 41
8624 12:11:39.465311 [Byte1]: 41
8625 12:11:39.469358
8626 12:11:39.469447 Set Vref, RX VrefLevel [Byte0]: 42
8627 12:11:39.472680 [Byte1]: 42
8628 12:11:39.477089
8629 12:11:39.477221 Set Vref, RX VrefLevel [Byte0]: 43
8630 12:11:39.480275 [Byte1]: 43
8631 12:11:39.484906
8632 12:11:39.484991 Set Vref, RX VrefLevel [Byte0]: 44
8633 12:11:39.488148 [Byte1]: 44
8634 12:11:39.492053
8635 12:11:39.492165 Set Vref, RX VrefLevel [Byte0]: 45
8636 12:11:39.495298 [Byte1]: 45
8637 12:11:39.499878
8638 12:11:39.499973 Set Vref, RX VrefLevel [Byte0]: 46
8639 12:11:39.503108 [Byte1]: 46
8640 12:11:39.507003
8641 12:11:39.507124 Set Vref, RX VrefLevel [Byte0]: 47
8642 12:11:39.510871 [Byte1]: 47
8643 12:11:39.514755
8644 12:11:39.514839 Set Vref, RX VrefLevel [Byte0]: 48
8645 12:11:39.517959 [Byte1]: 48
8646 12:11:39.522239
8647 12:11:39.522354 Set Vref, RX VrefLevel [Byte0]: 49
8648 12:11:39.526017 [Byte1]: 49
8649 12:11:39.530318
8650 12:11:39.530448 Set Vref, RX VrefLevel [Byte0]: 50
8651 12:11:39.533443 [Byte1]: 50
8652 12:11:39.538010
8653 12:11:39.538137 Set Vref, RX VrefLevel [Byte0]: 51
8654 12:11:39.541092 [Byte1]: 51
8655 12:11:39.544892
8656 12:11:39.545006 Set Vref, RX VrefLevel [Byte0]: 52
8657 12:11:39.548627 [Byte1]: 52
8658 12:11:39.552550
8659 12:11:39.552673 Set Vref, RX VrefLevel [Byte0]: 53
8660 12:11:39.555797 [Byte1]: 53
8661 12:11:39.560217
8662 12:11:39.560329 Set Vref, RX VrefLevel [Byte0]: 54
8663 12:11:39.563477 [Byte1]: 54
8664 12:11:39.567936
8665 12:11:39.568043 Set Vref, RX VrefLevel [Byte0]: 55
8666 12:11:39.571015 [Byte1]: 55
8667 12:11:39.575655
8668 12:11:39.575743 Set Vref, RX VrefLevel [Byte0]: 56
8669 12:11:39.578830 [Byte1]: 56
8670 12:11:39.583493
8671 12:11:39.583624 Set Vref, RX VrefLevel [Byte0]: 57
8672 12:11:39.586082 [Byte1]: 57
8673 12:11:39.590607
8674 12:11:39.590750 Set Vref, RX VrefLevel [Byte0]: 58
8675 12:11:39.593848 [Byte1]: 58
8676 12:11:39.598191
8677 12:11:39.598314 Set Vref, RX VrefLevel [Byte0]: 59
8678 12:11:39.601470 [Byte1]: 59
8679 12:11:39.605943
8680 12:11:39.606054 Set Vref, RX VrefLevel [Byte0]: 60
8681 12:11:39.612311 [Byte1]: 60
8682 12:11:39.612409
8683 12:11:39.615693 Set Vref, RX VrefLevel [Byte0]: 61
8684 12:11:39.618804 [Byte1]: 61
8685 12:11:39.618922
8686 12:11:39.622178 Set Vref, RX VrefLevel [Byte0]: 62
8687 12:11:39.625391 [Byte1]: 62
8688 12:11:39.625512
8689 12:11:39.628916 Set Vref, RX VrefLevel [Byte0]: 63
8690 12:11:39.631857 [Byte1]: 63
8691 12:11:39.636357
8692 12:11:39.636486 Set Vref, RX VrefLevel [Byte0]: 64
8693 12:11:39.639392 [Byte1]: 64
8694 12:11:39.643610
8695 12:11:39.643730 Set Vref, RX VrefLevel [Byte0]: 65
8696 12:11:39.646895 [Byte1]: 65
8697 12:11:39.651109
8698 12:11:39.651245 Set Vref, RX VrefLevel [Byte0]: 66
8699 12:11:39.654272 [Byte1]: 66
8700 12:11:39.658858
8701 12:11:39.658960 Set Vref, RX VrefLevel [Byte0]: 67
8702 12:11:39.662150 [Byte1]: 67
8703 12:11:39.666661
8704 12:11:39.666759 Set Vref, RX VrefLevel [Byte0]: 68
8705 12:11:39.669904 [Byte1]: 68
8706 12:11:39.673842
8707 12:11:39.673929 Set Vref, RX VrefLevel [Byte0]: 69
8708 12:11:39.677042 [Byte1]: 69
8709 12:11:39.681494
8710 12:11:39.681606 Set Vref, RX VrefLevel [Byte0]: 70
8711 12:11:39.684764 [Byte1]: 70
8712 12:11:39.689288
8713 12:11:39.689381 Set Vref, RX VrefLevel [Byte0]: 71
8714 12:11:39.692548 [Byte1]: 71
8715 12:11:39.696455
8716 12:11:39.696573 Set Vref, RX VrefLevel [Byte0]: 72
8717 12:11:39.699599 [Byte1]: 72
8718 12:11:39.704186
8719 12:11:39.704271 Final RX Vref Byte 0 = 58 to rank0
8720 12:11:39.707430 Final RX Vref Byte 1 = 59 to rank0
8721 12:11:39.710625 Final RX Vref Byte 0 = 58 to rank1
8722 12:11:39.713962 Final RX Vref Byte 1 = 59 to rank1==
8723 12:11:39.717899 Dram Type= 6, Freq= 0, CH_1, rank 0
8724 12:11:39.724185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8725 12:11:39.724282 ==
8726 12:11:39.724350 DQS Delay:
8727 12:11:39.724429 DQS0 = 0, DQS1 = 0
8728 12:11:39.727601 DQM Delay:
8729 12:11:39.727678 DQM0 = 131, DQM1 = 124
8730 12:11:39.731031 DQ Delay:
8731 12:11:39.734032 DQ0 =134, DQ1 =124, DQ2 =120, DQ3 =130
8732 12:11:39.737924 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8733 12:11:39.740843 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =118
8734 12:11:39.744000 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8735 12:11:39.744092
8736 12:11:39.744161
8737 12:11:39.744222
8738 12:11:39.747667 [DramC_TX_OE_Calibration] TA2
8739 12:11:39.750567 Original DQ_B0 (3 6) =30, OEN = 27
8740 12:11:39.753794 Original DQ_B1 (3 6) =30, OEN = 27
8741 12:11:39.757572 24, 0x0, End_B0=24 End_B1=24
8742 12:11:39.757691 25, 0x0, End_B0=25 End_B1=25
8743 12:11:39.760758 26, 0x0, End_B0=26 End_B1=26
8744 12:11:39.764188 27, 0x0, End_B0=27 End_B1=27
8745 12:11:39.767196 28, 0x0, End_B0=28 End_B1=28
8746 12:11:39.770605 29, 0x0, End_B0=29 End_B1=29
8747 12:11:39.770699 30, 0x0, End_B0=30 End_B1=30
8748 12:11:39.773718 31, 0x4141, End_B0=30 End_B1=30
8749 12:11:39.777028 Byte0 end_step=30 best_step=27
8750 12:11:39.780211 Byte1 end_step=30 best_step=27
8751 12:11:39.783519 Byte0 TX OE(2T, 0.5T) = (3, 3)
8752 12:11:39.787335 Byte1 TX OE(2T, 0.5T) = (3, 3)
8753 12:11:39.787429
8754 12:11:39.787493
8755 12:11:39.793784 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 400 ps
8756 12:11:39.797069 CH1 RK0: MR19=302, MR18=13FF
8757 12:11:39.803664 CH1_RK0: MR19=0x302, MR18=0x13FF, DQSOSC=400, MR23=63, INC=23, DEC=15
8758 12:11:39.803761
8759 12:11:39.806806 ----->DramcWriteLeveling(PI) begin...
8760 12:11:39.806884 ==
8761 12:11:39.810581 Dram Type= 6, Freq= 0, CH_1, rank 1
8762 12:11:39.813789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 12:11:39.813874 ==
8764 12:11:39.817062 Write leveling (Byte 0): 25 => 25
8765 12:11:39.820429 Write leveling (Byte 1): 27 => 27
8766 12:11:39.823678 DramcWriteLeveling(PI) end<-----
8767 12:11:39.823781
8768 12:11:39.823868 ==
8769 12:11:39.826915 Dram Type= 6, Freq= 0, CH_1, rank 1
8770 12:11:39.830250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 12:11:39.830363 ==
8772 12:11:39.833459 [Gating] SW mode calibration
8773 12:11:39.839802 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8774 12:11:39.846518 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8775 12:11:39.850243 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 12:11:39.856831 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 12:11:39.859877 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8778 12:11:39.863005 1 4 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8779 12:11:39.869957 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8780 12:11:39.873267 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 12:11:39.876534 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 12:11:39.882886 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 12:11:39.886179 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 12:11:39.889469 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 12:11:39.896632 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8786 12:11:39.899833 1 5 12 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
8787 12:11:39.903028 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 12:11:39.906423 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 12:11:39.912903 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 12:11:39.915961 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 12:11:39.919994 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 12:11:39.926414 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 12:11:39.929763 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8794 12:11:39.932937 1 6 12 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
8795 12:11:39.939662 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 12:11:39.942853 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 12:11:39.946113 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 12:11:39.952582 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 12:11:39.956113 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 12:11:39.958985 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 12:11:39.965868 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8802 12:11:39.969038 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8803 12:11:39.972414 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8804 12:11:39.979150 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 12:11:39.982500 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 12:11:39.985690 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 12:11:39.992913 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 12:11:39.995614 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 12:11:39.998905 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 12:11:40.005991 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 12:11:40.009193 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 12:11:40.012378 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 12:11:40.019298 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 12:11:40.022632 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 12:11:40.025915 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:11:40.032268 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8817 12:11:40.036128 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8818 12:11:40.039237 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8819 12:11:40.042460 Total UI for P1: 0, mck2ui 16
8820 12:11:40.045611 best dqsien dly found for B0: ( 1, 9, 6)
8821 12:11:40.048764 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8822 12:11:40.055360 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 12:11:40.059221 Total UI for P1: 0, mck2ui 16
8824 12:11:40.062359 best dqsien dly found for B1: ( 1, 9, 14)
8825 12:11:40.065865 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8826 12:11:40.068986 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8827 12:11:40.069158
8828 12:11:40.072160 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8829 12:11:40.075955 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8830 12:11:40.078962 [Gating] SW calibration Done
8831 12:11:40.079079 ==
8832 12:11:40.082037 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 12:11:40.085815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 12:11:40.085928 ==
8835 12:11:40.088803 RX Vref Scan: 0
8836 12:11:40.088909
8837 12:11:40.091999 RX Vref 0 -> 0, step: 1
8838 12:11:40.092111
8839 12:11:40.092217 RX Delay 0 -> 252, step: 8
8840 12:11:40.098644 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8841 12:11:40.101892 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8842 12:11:40.105152 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8843 12:11:40.108518 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8844 12:11:40.112315 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8845 12:11:40.118668 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8846 12:11:40.121996 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8847 12:11:40.125287 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8848 12:11:40.128512 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8849 12:11:40.131914 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8850 12:11:40.135233 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8851 12:11:40.142261 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8852 12:11:40.145433 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8853 12:11:40.148722 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8854 12:11:40.152027 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8855 12:11:40.158310 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8856 12:11:40.158436 ==
8857 12:11:40.161599 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 12:11:40.164791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 12:11:40.164882 ==
8860 12:11:40.164950 DQS Delay:
8861 12:11:40.168108 DQS0 = 0, DQS1 = 0
8862 12:11:40.168218 DQM Delay:
8863 12:11:40.171783 DQM0 = 133, DQM1 = 128
8864 12:11:40.171899 DQ Delay:
8865 12:11:40.174860 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8866 12:11:40.178067 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8867 12:11:40.181785 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8868 12:11:40.184923 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =139
8869 12:11:40.185016
8870 12:11:40.188562
8871 12:11:40.188659 ==
8872 12:11:40.191596 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 12:11:40.194685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 12:11:40.194781 ==
8875 12:11:40.194851
8876 12:11:40.194921
8877 12:11:40.197960 TX Vref Scan disable
8878 12:11:40.198054 == TX Byte 0 ==
8879 12:11:40.204481 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8880 12:11:40.208392 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8881 12:11:40.208477 == TX Byte 1 ==
8882 12:11:40.214851 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8883 12:11:40.218003 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8884 12:11:40.218093 ==
8885 12:11:40.221090 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 12:11:40.224350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 12:11:40.224439 ==
8888 12:11:40.239163
8889 12:11:40.242393 TX Vref early break, caculate TX vref
8890 12:11:40.245610 TX Vref=16, minBit 8, minWin=21, winSum=376
8891 12:11:40.248943 TX Vref=18, minBit 0, minWin=23, winSum=388
8892 12:11:40.252232 TX Vref=20, minBit 5, minWin=24, winSum=400
8893 12:11:40.255564 TX Vref=22, minBit 8, minWin=24, winSum=404
8894 12:11:40.258811 TX Vref=24, minBit 6, minWin=25, winSum=415
8895 12:11:40.265834 TX Vref=26, minBit 0, minWin=26, winSum=420
8896 12:11:40.269032 TX Vref=28, minBit 0, minWin=26, winSum=424
8897 12:11:40.272339 TX Vref=30, minBit 5, minWin=25, winSum=423
8898 12:11:40.275632 TX Vref=32, minBit 0, minWin=25, winSum=415
8899 12:11:40.278821 TX Vref=34, minBit 0, minWin=24, winSum=406
8900 12:11:40.282306 TX Vref=36, minBit 0, minWin=23, winSum=397
8901 12:11:40.288632 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8902 12:11:40.288753
8903 12:11:40.292222 Final TX Range 0 Vref 28
8904 12:11:40.292312
8905 12:11:40.292379 ==
8906 12:11:40.295222 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 12:11:40.299136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 12:11:40.299223 ==
8909 12:11:40.299291
8910 12:11:40.299361
8911 12:11:40.302063 TX Vref Scan disable
8912 12:11:40.308634 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8913 12:11:40.308721 == TX Byte 0 ==
8914 12:11:40.312303 u2DelayCellOfst[0]=17 cells (5 PI)
8915 12:11:40.315500 u2DelayCellOfst[1]=14 cells (4 PI)
8916 12:11:40.318605 u2DelayCellOfst[2]=0 cells (0 PI)
8917 12:11:40.322457 u2DelayCellOfst[3]=7 cells (2 PI)
8918 12:11:40.325643 u2DelayCellOfst[4]=10 cells (3 PI)
8919 12:11:40.328834 u2DelayCellOfst[5]=17 cells (5 PI)
8920 12:11:40.331984 u2DelayCellOfst[6]=17 cells (5 PI)
8921 12:11:40.335290 u2DelayCellOfst[7]=7 cells (2 PI)
8922 12:11:40.338822 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8923 12:11:40.342397 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8924 12:11:40.345565 == TX Byte 1 ==
8925 12:11:40.345650 u2DelayCellOfst[8]=0 cells (0 PI)
8926 12:11:40.348893 u2DelayCellOfst[9]=7 cells (2 PI)
8927 12:11:40.352126 u2DelayCellOfst[10]=14 cells (4 PI)
8928 12:11:40.355255 u2DelayCellOfst[11]=10 cells (3 PI)
8929 12:11:40.358554 u2DelayCellOfst[12]=17 cells (5 PI)
8930 12:11:40.361879 u2DelayCellOfst[13]=17 cells (5 PI)
8931 12:11:40.365655 u2DelayCellOfst[14]=21 cells (6 PI)
8932 12:11:40.368917 u2DelayCellOfst[15]=17 cells (5 PI)
8933 12:11:40.372141 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8934 12:11:40.378834 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8935 12:11:40.378979 DramC Write-DBI on
8936 12:11:40.379079 ==
8937 12:11:40.382165 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 12:11:40.388611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 12:11:40.388739 ==
8940 12:11:40.388858
8941 12:11:40.388975
8942 12:11:40.389081 TX Vref Scan disable
8943 12:11:40.392087 == TX Byte 0 ==
8944 12:11:40.395839 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8945 12:11:40.399064 == TX Byte 1 ==
8946 12:11:40.401826 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8947 12:11:40.405445 DramC Write-DBI off
8948 12:11:40.405554
8949 12:11:40.405649 [DATLAT]
8950 12:11:40.405742 Freq=1600, CH1 RK1
8951 12:11:40.405841
8952 12:11:40.408645 DATLAT Default: 0xf
8953 12:11:40.408765 0, 0xFFFF, sum = 0
8954 12:11:40.411955 1, 0xFFFF, sum = 0
8955 12:11:40.415135 2, 0xFFFF, sum = 0
8956 12:11:40.415247 3, 0xFFFF, sum = 0
8957 12:11:40.418548 4, 0xFFFF, sum = 0
8958 12:11:40.418666 5, 0xFFFF, sum = 0
8959 12:11:40.422308 6, 0xFFFF, sum = 0
8960 12:11:40.422420 7, 0xFFFF, sum = 0
8961 12:11:40.425518 8, 0xFFFF, sum = 0
8962 12:11:40.425625 9, 0xFFFF, sum = 0
8963 12:11:40.428794 10, 0xFFFF, sum = 0
8964 12:11:40.428897 11, 0xFFFF, sum = 0
8965 12:11:40.432213 12, 0xFFFF, sum = 0
8966 12:11:40.432320 13, 0xFFFF, sum = 0
8967 12:11:40.435442 14, 0x0, sum = 1
8968 12:11:40.435547 15, 0x0, sum = 2
8969 12:11:40.438732 16, 0x0, sum = 3
8970 12:11:40.438838 17, 0x0, sum = 4
8971 12:11:40.442101 best_step = 15
8972 12:11:40.442214
8973 12:11:40.442321 ==
8974 12:11:40.445276 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 12:11:40.448658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 12:11:40.448764 ==
8977 12:11:40.452089 RX Vref Scan: 0
8978 12:11:40.452203
8979 12:11:40.452277 RX Vref 0 -> 0, step: 1
8980 12:11:40.452346
8981 12:11:40.455264 RX Delay 11 -> 252, step: 4
8982 12:11:40.458593 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8983 12:11:40.464950 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8984 12:11:40.468306 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8985 12:11:40.471623 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8986 12:11:40.474949 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8987 12:11:40.478326 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8988 12:11:40.484922 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8989 12:11:40.488153 iDelay=191, Bit 7, Center 124 (71 ~ 178) 108
8990 12:11:40.491422 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8991 12:11:40.494812 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8992 12:11:40.498559 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8993 12:11:40.504833 iDelay=191, Bit 11, Center 118 (63 ~ 174) 112
8994 12:11:40.508739 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8995 12:11:40.511945 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8996 12:11:40.515222 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8997 12:11:40.521820 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8998 12:11:40.521910 ==
8999 12:11:40.525117 Dram Type= 6, Freq= 0, CH_1, rank 1
9000 12:11:40.528269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9001 12:11:40.528350 ==
9002 12:11:40.528416 DQS Delay:
9003 12:11:40.531611 DQS0 = 0, DQS1 = 0
9004 12:11:40.531685 DQM Delay:
9005 12:11:40.534883 DQM0 = 129, DQM1 = 126
9006 12:11:40.534978 DQ Delay:
9007 12:11:40.538082 DQ0 =132, DQ1 =126, DQ2 =118, DQ3 =126
9008 12:11:40.541427 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =124
9009 12:11:40.544691 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9010 12:11:40.548028 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
9011 12:11:40.548114
9012 12:11:40.548188
9013 12:11:40.548250
9014 12:11:40.551124 [DramC_TX_OE_Calibration] TA2
9015 12:11:40.554541 Original DQ_B0 (3 6) =30, OEN = 27
9016 12:11:40.557817 Original DQ_B1 (3 6) =30, OEN = 27
9017 12:11:40.561647 24, 0x0, End_B0=24 End_B1=24
9018 12:11:40.564896 25, 0x0, End_B0=25 End_B1=25
9019 12:11:40.564990 26, 0x0, End_B0=26 End_B1=26
9020 12:11:40.568032 27, 0x0, End_B0=27 End_B1=27
9021 12:11:40.571245 28, 0x0, End_B0=28 End_B1=28
9022 12:11:40.574579 29, 0x0, End_B0=29 End_B1=29
9023 12:11:40.577815 30, 0x0, End_B0=30 End_B1=30
9024 12:11:40.577933 31, 0x4141, End_B0=30 End_B1=30
9025 12:11:40.581117 Byte0 end_step=30 best_step=27
9026 12:11:40.584397 Byte1 end_step=30 best_step=27
9027 12:11:40.587704 Byte0 TX OE(2T, 0.5T) = (3, 3)
9028 12:11:40.590868 Byte1 TX OE(2T, 0.5T) = (3, 3)
9029 12:11:40.590975
9030 12:11:40.591112
9031 12:11:40.598090 [DQSOSCAuto] RK1, (LSB)MR18= 0xd13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
9032 12:11:40.601487 CH1 RK1: MR19=303, MR18=D13
9033 12:11:40.607834 CH1_RK1: MR19=0x303, MR18=0xD13, DQSOSC=400, MR23=63, INC=23, DEC=15
9034 12:11:40.610930 [RxdqsGatingPostProcess] freq 1600
9035 12:11:40.617467 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9036 12:11:40.617583 best DQS0 dly(2T, 0.5T) = (1, 1)
9037 12:11:40.621090 best DQS1 dly(2T, 0.5T) = (1, 1)
9038 12:11:40.624385 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9039 12:11:40.627629 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9040 12:11:40.630781 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 12:11:40.634006 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 12:11:40.637938 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 12:11:40.641206 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 12:11:40.644524 Pre-setting of DQS Precalculation
9045 12:11:40.647866 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9046 12:11:40.657694 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9047 12:11:40.664231 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9048 12:11:40.664355
9049 12:11:40.664455
9050 12:11:40.667535 [Calibration Summary] 3200 Mbps
9051 12:11:40.667626 CH 0, Rank 0
9052 12:11:40.670688 SW Impedance : PASS
9053 12:11:40.670774 DUTY Scan : NO K
9054 12:11:40.673930 ZQ Calibration : PASS
9055 12:11:40.677261 Jitter Meter : NO K
9056 12:11:40.677374 CBT Training : PASS
9057 12:11:40.680618 Write leveling : PASS
9058 12:11:40.683939 RX DQS gating : PASS
9059 12:11:40.684030 RX DQ/DQS(RDDQC) : PASS
9060 12:11:40.687264 TX DQ/DQS : PASS
9061 12:11:40.690586 RX DATLAT : PASS
9062 12:11:40.690665 RX DQ/DQS(Engine): PASS
9063 12:11:40.693770 TX OE : PASS
9064 12:11:40.693848 All Pass.
9065 12:11:40.693912
9066 12:11:40.697113 CH 0, Rank 1
9067 12:11:40.697198 SW Impedance : PASS
9068 12:11:40.700465 DUTY Scan : NO K
9069 12:11:40.700546 ZQ Calibration : PASS
9070 12:11:40.703695 Jitter Meter : NO K
9071 12:11:40.706993 CBT Training : PASS
9072 12:11:40.707108 Write leveling : PASS
9073 12:11:40.710337 RX DQS gating : PASS
9074 12:11:40.714060 RX DQ/DQS(RDDQC) : PASS
9075 12:11:40.714166 TX DQ/DQS : PASS
9076 12:11:40.717118 RX DATLAT : PASS
9077 12:11:40.720897 RX DQ/DQS(Engine): PASS
9078 12:11:40.720983 TX OE : PASS
9079 12:11:40.724080 All Pass.
9080 12:11:40.724168
9081 12:11:40.724244 CH 1, Rank 0
9082 12:11:40.727139 SW Impedance : PASS
9083 12:11:40.727245 DUTY Scan : NO K
9084 12:11:40.730254 ZQ Calibration : PASS
9085 12:11:40.734076 Jitter Meter : NO K
9086 12:11:40.734176 CBT Training : PASS
9087 12:11:40.737255 Write leveling : PASS
9088 12:11:40.740573 RX DQS gating : PASS
9089 12:11:40.740649 RX DQ/DQS(RDDQC) : PASS
9090 12:11:40.743776 TX DQ/DQS : PASS
9091 12:11:40.743854 RX DATLAT : PASS
9092 12:11:40.747128 RX DQ/DQS(Engine): PASS
9093 12:11:40.750241 TX OE : PASS
9094 12:11:40.750355 All Pass.
9095 12:11:40.750454
9096 12:11:40.750544 CH 1, Rank 1
9097 12:11:40.753536 SW Impedance : PASS
9098 12:11:40.757462 DUTY Scan : NO K
9099 12:11:40.757571 ZQ Calibration : PASS
9100 12:11:40.760143 Jitter Meter : NO K
9101 12:11:40.764087 CBT Training : PASS
9102 12:11:40.764195 Write leveling : PASS
9103 12:11:40.767465 RX DQS gating : PASS
9104 12:11:40.770174 RX DQ/DQS(RDDQC) : PASS
9105 12:11:40.770255 TX DQ/DQS : PASS
9106 12:11:40.774075 RX DATLAT : PASS
9107 12:11:40.777257 RX DQ/DQS(Engine): PASS
9108 12:11:40.777366 TX OE : PASS
9109 12:11:40.780458 All Pass.
9110 12:11:40.780568
9111 12:11:40.780666 DramC Write-DBI on
9112 12:11:40.783884 PER_BANK_REFRESH: Hybrid Mode
9113 12:11:40.783966 TX_TRACKING: ON
9114 12:11:40.793802 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9115 12:11:40.800505 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9116 12:11:40.810247 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9117 12:11:40.813581 [FAST_K] Save calibration result to emmc
9118 12:11:40.816919 sync common calibartion params.
9119 12:11:40.817033 sync cbt_mode0:1, 1:1
9120 12:11:40.820121 dram_init: ddr_geometry: 2
9121 12:11:40.823779 dram_init: ddr_geometry: 2
9122 12:11:40.823862 dram_init: ddr_geometry: 2
9123 12:11:40.827123 0:dram_rank_size:100000000
9124 12:11:40.830337 1:dram_rank_size:100000000
9125 12:11:40.836633 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9126 12:11:40.836739 DFS_SHUFFLE_HW_MODE: ON
9127 12:11:40.840421 dramc_set_vcore_voltage set vcore to 725000
9128 12:11:40.843524 Read voltage for 1600, 0
9129 12:11:40.843643 Vio18 = 0
9130 12:11:40.847138 Vcore = 725000
9131 12:11:40.847243 Vdram = 0
9132 12:11:40.847361 Vddq = 0
9133 12:11:40.849848 Vmddr = 0
9134 12:11:40.849964 switch to 3200 Mbps bootup
9135 12:11:40.853146 [DramcRunTimeConfig]
9136 12:11:40.853257 PHYPLL
9137 12:11:40.856865 DPM_CONTROL_AFTERK: ON
9138 12:11:40.856944 PER_BANK_REFRESH: ON
9139 12:11:40.860168 REFRESH_OVERHEAD_REDUCTION: ON
9140 12:11:40.863462 CMD_PICG_NEW_MODE: OFF
9141 12:11:40.863571 XRTWTW_NEW_MODE: ON
9142 12:11:40.866778 XRTRTR_NEW_MODE: ON
9143 12:11:40.866886 TX_TRACKING: ON
9144 12:11:40.870060 RDSEL_TRACKING: OFF
9145 12:11:40.873420 DQS Precalculation for DVFS: ON
9146 12:11:40.873525 RX_TRACKING: OFF
9147 12:11:40.876615 HW_GATING DBG: ON
9148 12:11:40.876721 ZQCS_ENABLE_LP4: ON
9149 12:11:40.879987 RX_PICG_NEW_MODE: ON
9150 12:11:40.880062 TX_PICG_NEW_MODE: ON
9151 12:11:40.883232 ENABLE_RX_DCM_DPHY: ON
9152 12:11:40.886604 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9153 12:11:40.889940 DUMMY_READ_FOR_TRACKING: OFF
9154 12:11:40.890054 !!! SPM_CONTROL_AFTERK: OFF
9155 12:11:40.893183 !!! SPM could not control APHY
9156 12:11:40.896489 IMPEDANCE_TRACKING: ON
9157 12:11:40.896603 TEMP_SENSOR: ON
9158 12:11:40.899784 HW_SAVE_FOR_SR: OFF
9159 12:11:40.903100 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9160 12:11:40.906416 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9161 12:11:40.906501 Read ODT Tracking: ON
9162 12:11:40.909726 Refresh Rate DeBounce: ON
9163 12:11:40.912981 DFS_NO_QUEUE_FLUSH: ON
9164 12:11:40.916305 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9165 12:11:40.919548 ENABLE_DFS_RUNTIME_MRW: OFF
9166 12:11:40.919636 DDR_RESERVE_NEW_MODE: ON
9167 12:11:40.922850 MR_CBT_SWITCH_FREQ: ON
9168 12:11:40.926083 =========================
9169 12:11:40.943753 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9170 12:11:40.946866 dram_init: ddr_geometry: 2
9171 12:11:40.964803 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9172 12:11:40.968010 dram_init: dram init end (result: 0)
9173 12:11:40.975083 DRAM-K: Full calibration passed in 24572 msecs
9174 12:11:40.978229 MRC: failed to locate region type 0.
9175 12:11:40.978324 DRAM rank0 size:0x100000000,
9176 12:11:40.981543 DRAM rank1 size=0x100000000
9177 12:11:40.991533 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9178 12:11:40.998154 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9179 12:11:41.004669 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9180 12:11:41.011229 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9181 12:11:41.014552 DRAM rank0 size:0x100000000,
9182 12:11:41.017817 DRAM rank1 size=0x100000000
9183 12:11:41.017908 CBMEM:
9184 12:11:41.021193 IMD: root @ 0xfffff000 254 entries.
9185 12:11:41.024487 IMD: root @ 0xffffec00 62 entries.
9186 12:11:41.027811 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9187 12:11:41.031102 WARNING: RO_VPD is uninitialized or empty.
9188 12:11:41.038342 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9189 12:11:41.045163 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9190 12:11:41.057580 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9191 12:11:41.068839 BS: romstage times (exec / console): total (unknown) / 24080 ms
9192 12:11:41.068973
9193 12:11:41.069072
9194 12:11:41.079297 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9195 12:11:41.082532 ARM64: Exception handlers installed.
9196 12:11:41.085682 ARM64: Testing exception
9197 12:11:41.089016 ARM64: Done test exception
9198 12:11:41.089128 Enumerating buses...
9199 12:11:41.092377 Show all devs... Before device enumeration.
9200 12:11:41.095597 Root Device: enabled 1
9201 12:11:41.099483 CPU_CLUSTER: 0: enabled 1
9202 12:11:41.099609 CPU: 00: enabled 1
9203 12:11:41.102635 Compare with tree...
9204 12:11:41.102741 Root Device: enabled 1
9205 12:11:41.105866 CPU_CLUSTER: 0: enabled 1
9206 12:11:41.109142 CPU: 00: enabled 1
9207 12:11:41.109253 Root Device scanning...
9208 12:11:41.112602 scan_static_bus for Root Device
9209 12:11:41.115922 CPU_CLUSTER: 0 enabled
9210 12:11:41.119118 scan_static_bus for Root Device done
9211 12:11:41.122427 scan_bus: bus Root Device finished in 8 msecs
9212 12:11:41.122539 done
9213 12:11:41.128985 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9214 12:11:41.132292 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9215 12:11:41.138892 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9216 12:11:41.142135 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9217 12:11:41.145843 Allocating resources...
9218 12:11:41.148986 Reading resources...
9219 12:11:41.152188 Root Device read_resources bus 0 link: 0
9220 12:11:41.152272 DRAM rank0 size:0x100000000,
9221 12:11:41.155319 DRAM rank1 size=0x100000000
9222 12:11:41.159235 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9223 12:11:41.162316 CPU: 00 missing read_resources
9224 12:11:41.165422 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9225 12:11:41.172181 Root Device read_resources bus 0 link: 0 done
9226 12:11:41.172294 Done reading resources.
9227 12:11:41.178739 Show resources in subtree (Root Device)...After reading.
9228 12:11:41.181954 Root Device child on link 0 CPU_CLUSTER: 0
9229 12:11:41.185216 CPU_CLUSTER: 0 child on link 0 CPU: 00
9230 12:11:41.195103 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9231 12:11:41.195219 CPU: 00
9232 12:11:41.198382 Root Device assign_resources, bus 0 link: 0
9233 12:11:41.201679 CPU_CLUSTER: 0 missing set_resources
9234 12:11:41.208845 Root Device assign_resources, bus 0 link: 0 done
9235 12:11:41.208932 Done setting resources.
9236 12:11:41.215222 Show resources in subtree (Root Device)...After assigning values.
9237 12:11:41.218466 Root Device child on link 0 CPU_CLUSTER: 0
9238 12:11:41.221854 CPU_CLUSTER: 0 child on link 0 CPU: 00
9239 12:11:41.231664 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9240 12:11:41.231752 CPU: 00
9241 12:11:41.235044 Done allocating resources.
9242 12:11:41.238317 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9243 12:11:41.241615 Enabling resources...
9244 12:11:41.241694 done.
9245 12:11:41.248206 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9246 12:11:41.248291 Initializing devices...
9247 12:11:41.251988 Root Device init
9248 12:11:41.252076 init hardware done!
9249 12:11:41.255026 0x00000018: ctrlr->caps
9250 12:11:41.258216 52.000 MHz: ctrlr->f_max
9251 12:11:41.258334 0.400 MHz: ctrlr->f_min
9252 12:11:41.261863 0x40ff8080: ctrlr->voltages
9253 12:11:41.261949 sclk: 390625
9254 12:11:41.264999 Bus Width = 1
9255 12:11:41.265103 sclk: 390625
9256 12:11:41.268721 Bus Width = 1
9257 12:11:41.268816 Early init status = 3
9258 12:11:41.275015 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9259 12:11:41.278094 in-header: 03 fb 00 00 01 00 00 00
9260 12:11:41.281974 in-data: 01
9261 12:11:41.285146 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9262 12:11:41.289126 in-header: 03 fb 00 00 01 00 00 00
9263 12:11:41.292519 in-data: 01
9264 12:11:41.295941 [SSUSB] Setting up USB HOST controller...
9265 12:11:41.299218 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9266 12:11:41.301910 [SSUSB] phy power-on done.
9267 12:11:41.305781 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9268 12:11:41.312373 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9269 12:11:41.315568 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9270 12:11:41.321957 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9271 12:11:41.328578 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9272 12:11:41.335152 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9273 12:11:41.341826 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9274 12:11:41.348357 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9275 12:11:41.352241 SPM: binary array size = 0x9dc
9276 12:11:41.355538 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9277 12:11:41.361765 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9278 12:11:41.368136 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9279 12:11:41.374902 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9280 12:11:41.378220 configure_display: Starting display init
9281 12:11:41.412566 anx7625_power_on_init: Init interface.
9282 12:11:41.415881 anx7625_disable_pd_protocol: Disabled PD feature.
9283 12:11:41.419061 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9284 12:11:41.447006 anx7625_start_dp_work: Secure OCM version=00
9285 12:11:41.450124 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9286 12:11:41.464887 sp_tx_get_edid_block: EDID Block = 1
9287 12:11:41.567755 Extracted contents:
9288 12:11:41.571001 header: 00 ff ff ff ff ff ff 00
9289 12:11:41.574284 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9290 12:11:41.577646 version: 01 04
9291 12:11:41.580665 basic params: 95 1f 11 78 0a
9292 12:11:41.584430 chroma info: 76 90 94 55 54 90 27 21 50 54
9293 12:11:41.587572 established: 00 00 00
9294 12:11:41.593825 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9295 12:11:41.597120 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9296 12:11:41.604008 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9297 12:11:41.610549 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9298 12:11:41.617113 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9299 12:11:41.620376 extensions: 00
9300 12:11:41.620458 checksum: fb
9301 12:11:41.620531
9302 12:11:41.623780 Manufacturer: IVO Model 57d Serial Number 0
9303 12:11:41.626985 Made week 0 of 2020
9304 12:11:41.627071 EDID version: 1.4
9305 12:11:41.630489 Digital display
9306 12:11:41.633597 6 bits per primary color channel
9307 12:11:41.633676 DisplayPort interface
9308 12:11:41.637007 Maximum image size: 31 cm x 17 cm
9309 12:11:41.640270 Gamma: 220%
9310 12:11:41.640345 Check DPMS levels
9311 12:11:41.643568 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9312 12:11:41.650134 First detailed timing is preferred timing
9313 12:11:41.650213 Established timings supported:
9314 12:11:41.653446 Standard timings supported:
9315 12:11:41.656801 Detailed timings
9316 12:11:41.660125 Hex of detail: 383680a07038204018303c0035ae10000019
9317 12:11:41.663473 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9318 12:11:41.670150 0780 0798 07c8 0820 hborder 0
9319 12:11:41.673522 0438 043b 0447 0458 vborder 0
9320 12:11:41.676731 -hsync -vsync
9321 12:11:41.676809 Did detailed timing
9322 12:11:41.683322 Hex of detail: 000000000000000000000000000000000000
9323 12:11:41.683414 Manufacturer-specified data, tag 0
9324 12:11:41.690282 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9325 12:11:41.693780 ASCII string: InfoVision
9326 12:11:41.696935 Hex of detail: 000000fe00523134304e574635205248200a
9327 12:11:41.699980 ASCII string: R140NWF5 RH
9328 12:11:41.700058 Checksum
9329 12:11:41.703610 Checksum: 0xfb (valid)
9330 12:11:41.706830 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9331 12:11:41.709908 DSI data_rate: 832800000 bps
9332 12:11:41.716486 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9333 12:11:41.720371 anx7625_parse_edid: pixelclock(138800).
9334 12:11:41.722945 hactive(1920), hsync(48), hfp(24), hbp(88)
9335 12:11:41.726914 vactive(1080), vsync(12), vfp(3), vbp(17)
9336 12:11:41.729473 anx7625_dsi_config: config dsi.
9337 12:11:41.736163 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9338 12:11:41.749444 anx7625_dsi_config: success to config DSI
9339 12:11:41.752736 anx7625_dp_start: MIPI phy setup OK.
9340 12:11:41.756005 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9341 12:11:41.759232 mtk_ddp_mode_set invalid vrefresh 60
9342 12:11:41.762649 main_disp_path_setup
9343 12:11:41.762742 ovl_layer_smi_id_en
9344 12:11:41.765988 ovl_layer_smi_id_en
9345 12:11:41.766070 ccorr_config
9346 12:11:41.766148 aal_config
9347 12:11:41.769197 gamma_config
9348 12:11:41.769293 postmask_config
9349 12:11:41.772604 dither_config
9350 12:11:41.775720 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9351 12:11:41.782941 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9352 12:11:41.786203 Root Device init finished in 531 msecs
9353 12:11:41.789453 CPU_CLUSTER: 0 init
9354 12:11:41.795792 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9355 12:11:41.798995 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9356 12:11:41.802703 APU_MBOX 0x190000b0 = 0x10001
9357 12:11:41.805812 APU_MBOX 0x190001b0 = 0x10001
9358 12:11:41.808856 APU_MBOX 0x190005b0 = 0x10001
9359 12:11:41.812493 APU_MBOX 0x190006b0 = 0x10001
9360 12:11:41.815792 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9361 12:11:41.828546 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9362 12:11:41.841118 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9363 12:11:41.847694 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9364 12:11:41.859142 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9365 12:11:41.868381 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9366 12:11:41.871544 CPU_CLUSTER: 0 init finished in 81 msecs
9367 12:11:41.874988 Devices initialized
9368 12:11:41.878285 Show all devs... After init.
9369 12:11:41.878366 Root Device: enabled 1
9370 12:11:41.881548 CPU_CLUSTER: 0: enabled 1
9371 12:11:41.884861 CPU: 00: enabled 1
9372 12:11:41.888229 BS: BS_DEV_INIT run times (exec / console): 208 / 428 ms
9373 12:11:41.891506 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9374 12:11:41.894773 ELOG: NV offset 0x57f000 size 0x1000
9375 12:11:41.901354 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9376 12:11:41.908460 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9377 12:11:41.911641 ELOG: Event(17) added with size 13 at 2023-06-06 12:11:52 UTC
9378 12:11:41.914894 out: cmd=0x121: 03 db 21 01 00 00 00 00
9379 12:11:41.918883 in-header: 03 ee 00 00 2c 00 00 00
9380 12:11:41.932261 in-data: 71 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9381 12:11:41.938881 ELOG: Event(A1) added with size 10 at 2023-06-06 12:11:52 UTC
9382 12:11:41.945025 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9383 12:11:41.951702 ELOG: Event(A0) added with size 9 at 2023-06-06 12:11:52 UTC
9384 12:11:41.955662 elog_add_boot_reason: Logged dev mode boot
9385 12:11:41.958975 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9386 12:11:41.962392 Finalize devices...
9387 12:11:41.962479 Devices finalized
9388 12:11:41.968310 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9389 12:11:41.971649 Writing coreboot table at 0xffe64000
9390 12:11:41.975599 0. 000000000010a000-0000000000113fff: RAMSTAGE
9391 12:11:41.978798 1. 0000000040000000-00000000400fffff: RAM
9392 12:11:41.985389 2. 0000000040100000-000000004032afff: RAMSTAGE
9393 12:11:41.988605 3. 000000004032b000-00000000545fffff: RAM
9394 12:11:41.991880 4. 0000000054600000-000000005465ffff: BL31
9395 12:11:41.995151 5. 0000000054660000-00000000ffe63fff: RAM
9396 12:11:42.001732 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9397 12:11:42.004949 7. 0000000100000000-000000023fffffff: RAM
9398 12:11:42.005063 Passing 5 GPIOs to payload:
9399 12:11:42.011606 NAME | PORT | POLARITY | VALUE
9400 12:11:42.014825 EC in RW | 0x000000aa | low | undefined
9401 12:11:42.021504 EC interrupt | 0x00000005 | low | undefined
9402 12:11:42.024654 TPM interrupt | 0x000000ab | high | undefined
9403 12:11:42.028495 SD card detect | 0x00000011 | high | undefined
9404 12:11:42.034959 speaker enable | 0x00000093 | high | undefined
9405 12:11:42.038166 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9406 12:11:42.041856 in-header: 03 f9 00 00 02 00 00 00
9407 12:11:42.041974 in-data: 02 00
9408 12:11:42.045173 ADC[4]: Raw value=901697 ID=7
9409 12:11:42.047891 ADC[3]: Raw value=213336 ID=1
9410 12:11:42.048002 RAM Code: 0x71
9411 12:11:42.051227 ADC[6]: Raw value=74557 ID=0
9412 12:11:42.054609 ADC[5]: Raw value=212229 ID=1
9413 12:11:42.054724 SKU Code: 0x1
9414 12:11:42.061197 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9415 12:11:42.064493 coreboot table: 964 bytes.
9416 12:11:42.067852 IMD ROOT 0. 0xfffff000 0x00001000
9417 12:11:42.071227 IMD SMALL 1. 0xffffe000 0x00001000
9418 12:11:42.074583 RO MCACHE 2. 0xffffc000 0x00001104
9419 12:11:42.077963 CONSOLE 3. 0xfff7c000 0x00080000
9420 12:11:42.081183 FMAP 4. 0xfff7b000 0x00000452
9421 12:11:42.084514 TIME STAMP 5. 0xfff7a000 0x00000910
9422 12:11:42.087813 VBOOT WORK 6. 0xfff66000 0x00014000
9423 12:11:42.091041 RAMOOPS 7. 0xffe66000 0x00100000
9424 12:11:42.094457 COREBOOT 8. 0xffe64000 0x00002000
9425 12:11:42.094570 IMD small region:
9426 12:11:42.097722 IMD ROOT 0. 0xffffec00 0x00000400
9427 12:11:42.101104 VPD 1. 0xffffeba0 0x0000004c
9428 12:11:42.104398 MMC STATUS 2. 0xffffeb80 0x00000004
9429 12:11:42.111027 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9430 12:11:42.114385 Probing TPM: done!
9431 12:11:42.117626 Connected to device vid:did:rid of 1ae0:0028:00
9432 12:11:42.127958 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9433 12:11:42.131203 Initialized TPM device CR50 revision 0
9434 12:11:42.134977 Checking cr50 for pending updates
9435 12:11:42.138178 Reading cr50 TPM mode
9436 12:11:42.147234 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9437 12:11:42.153827 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9438 12:11:42.193469 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9439 12:11:42.196822 Checking segment from ROM address 0x40100000
9440 12:11:42.200077 Checking segment from ROM address 0x4010001c
9441 12:11:42.206736 Loading segment from ROM address 0x40100000
9442 12:11:42.206846 code (compression=0)
9443 12:11:42.217143 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9444 12:11:42.223695 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9445 12:11:42.223781 it's not compressed!
9446 12:11:42.230259 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9447 12:11:42.233757 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9448 12:11:42.254253 Loading segment from ROM address 0x4010001c
9449 12:11:42.254377 Entry Point 0x80000000
9450 12:11:42.257551 Loaded segments
9451 12:11:42.260938 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9452 12:11:42.267630 Jumping to boot code at 0x80000000(0xffe64000)
9453 12:11:42.274157 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9454 12:11:42.280726 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9455 12:11:42.288550 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9456 12:11:42.291903 Checking segment from ROM address 0x40100000
9457 12:11:42.295142 Checking segment from ROM address 0x4010001c
9458 12:11:42.301708 Loading segment from ROM address 0x40100000
9459 12:11:42.301820 code (compression=1)
9460 12:11:42.308348 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9461 12:11:42.318186 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9462 12:11:42.318307 using LZMA
9463 12:11:42.326637 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9464 12:11:42.333860 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9465 12:11:42.336498 Loading segment from ROM address 0x4010001c
9466 12:11:42.336612 Entry Point 0x54601000
9467 12:11:42.340481 Loaded segments
9468 12:11:42.343542 NOTICE: MT8192 bl31_setup
9469 12:11:42.350194 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9470 12:11:42.353961 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9471 12:11:42.357689 WARNING: region 0:
9472 12:11:42.360035 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 12:11:42.360154 WARNING: region 1:
9474 12:11:42.367269 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9475 12:11:42.370508 WARNING: region 2:
9476 12:11:42.373739 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9477 12:11:42.377046 WARNING: region 3:
9478 12:11:42.380410 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 12:11:42.383681 WARNING: region 4:
9480 12:11:42.390271 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9481 12:11:42.390381 WARNING: region 5:
9482 12:11:42.393642 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 12:11:42.396938 WARNING: region 6:
9484 12:11:42.400232 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 12:11:42.403488 WARNING: region 7:
9486 12:11:42.406746 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 12:11:42.413852 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9488 12:11:42.417056 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9489 12:11:42.420243 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9490 12:11:42.426921 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9491 12:11:42.430160 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9492 12:11:42.433526 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9493 12:11:42.440755 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9494 12:11:42.443983 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9495 12:11:42.450514 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9496 12:11:42.453804 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9497 12:11:42.457337 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9498 12:11:42.463591 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9499 12:11:42.467280 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9500 12:11:42.470497 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9501 12:11:42.476883 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9502 12:11:42.480164 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9503 12:11:42.483465 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9504 12:11:42.490767 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9505 12:11:42.493515 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9506 12:11:42.500647 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9507 12:11:42.504033 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9508 12:11:42.507241 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9509 12:11:42.513888 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9510 12:11:42.517146 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9511 12:11:42.523766 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9512 12:11:42.526964 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9513 12:11:42.530246 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9514 12:11:42.536799 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9515 12:11:42.540748 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9516 12:11:42.547195 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9517 12:11:42.550527 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9518 12:11:42.553888 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9519 12:11:42.560406 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9520 12:11:42.563518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9521 12:11:42.567089 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9522 12:11:42.570429 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9523 12:11:42.577074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9524 12:11:42.580248 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9525 12:11:42.583544 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9526 12:11:42.586796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9527 12:11:42.593298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9528 12:11:42.596566 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9529 12:11:42.599920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9530 12:11:42.603786 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9531 12:11:42.610444 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9532 12:11:42.613698 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9533 12:11:42.616935 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9534 12:11:42.620214 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9535 12:11:42.626795 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9536 12:11:42.629966 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9537 12:11:42.636620 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9538 12:11:42.639950 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9539 12:11:42.643580 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9540 12:11:42.650247 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9541 12:11:42.653520 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9542 12:11:42.660192 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9543 12:11:42.663431 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9544 12:11:42.669813 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9545 12:11:42.673540 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9546 12:11:42.679766 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9547 12:11:42.683488 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9548 12:11:42.686607 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9549 12:11:42.693179 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9550 12:11:42.696535 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9551 12:11:42.703128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9552 12:11:42.706537 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9553 12:11:42.713124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9554 12:11:42.716409 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9555 12:11:42.720297 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9556 12:11:42.726951 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9557 12:11:42.730281 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9558 12:11:42.736960 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9559 12:11:42.740288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9560 12:11:42.746701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9561 12:11:42.749968 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9562 12:11:42.753306 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9563 12:11:42.759951 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9564 12:11:42.763171 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9565 12:11:42.769867 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9566 12:11:42.773128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9567 12:11:42.780090 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9568 12:11:42.783224 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9569 12:11:42.789618 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9570 12:11:42.793392 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9571 12:11:42.796567 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9572 12:11:42.803357 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9573 12:11:42.806724 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9574 12:11:42.813218 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9575 12:11:42.816598 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9576 12:11:42.823190 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9577 12:11:42.826555 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9578 12:11:42.829821 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9579 12:11:42.836237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9580 12:11:42.839603 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9581 12:11:42.846096 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9582 12:11:42.850041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9583 12:11:42.853256 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9584 12:11:42.859834 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9585 12:11:42.863136 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9586 12:11:42.866425 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9587 12:11:42.869738 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9588 12:11:42.876272 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9589 12:11:42.879507 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9590 12:11:42.886211 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9591 12:11:42.889273 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9592 12:11:42.892986 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9593 12:11:42.899297 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9594 12:11:42.903026 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9595 12:11:42.909778 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9596 12:11:42.912929 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9597 12:11:42.916109 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9598 12:11:42.922801 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9599 12:11:42.926078 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9600 12:11:42.932944 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9601 12:11:42.936318 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9602 12:11:42.939420 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9603 12:11:42.946116 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9604 12:11:42.949302 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9605 12:11:42.952633 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9606 12:11:42.959174 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9607 12:11:42.962517 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9608 12:11:42.965789 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9609 12:11:42.969246 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9610 12:11:42.976432 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9611 12:11:42.979660 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9612 12:11:42.983033 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9613 12:11:42.989729 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9614 12:11:42.992444 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9615 12:11:42.999267 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9616 12:11:43.002466 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9617 12:11:43.006097 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9618 12:11:43.012568 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9619 12:11:43.016275 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9620 12:11:43.019696 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9621 12:11:43.026236 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9622 12:11:43.029517 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9623 12:11:43.035976 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9624 12:11:43.039188 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9625 12:11:43.042488 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9626 12:11:43.049163 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9627 12:11:43.052905 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9628 12:11:43.058996 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9629 12:11:43.063124 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9630 12:11:43.066448 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9631 12:11:43.072934 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9632 12:11:43.076289 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9633 12:11:43.079572 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9634 12:11:43.086044 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9635 12:11:43.089419 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9636 12:11:43.095953 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9637 12:11:43.099204 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9638 12:11:43.102583 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9639 12:11:43.109473 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9640 12:11:43.112554 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9641 12:11:43.116195 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9642 12:11:43.122418 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9643 12:11:43.126201 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9644 12:11:43.132780 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9645 12:11:43.136048 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9646 12:11:43.139244 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9647 12:11:43.145875 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9648 12:11:43.149164 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9649 12:11:43.155634 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9650 12:11:43.158961 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9651 12:11:43.162307 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9652 12:11:43.168943 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9653 12:11:43.172237 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9654 12:11:43.178938 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9655 12:11:43.182383 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9656 12:11:43.185524 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9657 12:11:43.192224 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9658 12:11:43.195442 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9659 12:11:43.202662 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9660 12:11:43.205909 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9661 12:11:43.209202 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9662 12:11:43.215594 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9663 12:11:43.219153 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9664 12:11:43.222819 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9665 12:11:43.228785 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9666 12:11:43.231993 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9667 12:11:43.238808 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9668 12:11:43.242240 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9669 12:11:43.245575 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9670 12:11:43.252120 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9671 12:11:43.255408 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9672 12:11:43.261988 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9673 12:11:43.265249 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9674 12:11:43.268543 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9675 12:11:43.275019 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9676 12:11:43.278958 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9677 12:11:43.285446 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9678 12:11:43.288719 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9679 12:11:43.295413 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9680 12:11:43.298755 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9681 12:11:43.301967 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9682 12:11:43.308641 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9683 12:11:43.311970 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9684 12:11:43.318519 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9685 12:11:43.321659 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9686 12:11:43.328053 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9687 12:11:43.331794 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9688 12:11:43.334813 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9689 12:11:43.341654 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9690 12:11:43.344856 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9691 12:11:43.351898 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9692 12:11:43.355094 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9693 12:11:43.358420 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9694 12:11:43.364880 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9695 12:11:43.368147 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9696 12:11:43.374786 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9697 12:11:43.378098 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9698 12:11:43.384670 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9699 12:11:43.387903 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9700 12:11:43.391208 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9701 12:11:43.397729 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9702 12:11:43.400990 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9703 12:11:43.407660 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9704 12:11:43.410943 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9705 12:11:43.414217 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9706 12:11:43.421415 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9707 12:11:43.424591 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9708 12:11:43.431034 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9709 12:11:43.434206 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9710 12:11:43.440759 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9711 12:11:43.444427 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9712 12:11:43.447464 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9713 12:11:43.454543 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9714 12:11:43.457740 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9715 12:11:43.464023 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9716 12:11:43.467339 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9717 12:11:43.470543 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9718 12:11:43.473927 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9719 12:11:43.477104 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9720 12:11:43.484376 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9721 12:11:43.487638 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9722 12:11:43.490920 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9723 12:11:43.497537 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9724 12:11:43.500822 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9725 12:11:43.507450 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9726 12:11:43.510700 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9727 12:11:43.514082 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9728 12:11:43.520745 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9729 12:11:43.524018 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9730 12:11:43.527168 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9731 12:11:43.533434 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9732 12:11:43.537315 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9733 12:11:43.543946 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9734 12:11:43.547053 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9735 12:11:43.550166 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9736 12:11:43.557029 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9737 12:11:43.560290 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9738 12:11:43.563988 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9739 12:11:43.570537 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9740 12:11:43.573878 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9741 12:11:43.577190 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9742 12:11:43.583747 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9743 12:11:43.587039 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9744 12:11:43.593630 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9745 12:11:43.596855 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9746 12:11:43.600215 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9747 12:11:43.606869 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9748 12:11:43.610144 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9749 12:11:43.613484 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9750 12:11:43.620169 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9751 12:11:43.623452 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9752 12:11:43.626753 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9753 12:11:43.633194 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9754 12:11:43.636894 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9755 12:11:43.643060 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9756 12:11:43.646975 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9757 12:11:43.650237 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9758 12:11:43.653484 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9759 12:11:43.656654 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9760 12:11:43.663441 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9761 12:11:43.666506 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9762 12:11:43.669705 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9763 12:11:43.673513 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9764 12:11:43.679911 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9765 12:11:43.683355 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9766 12:11:43.686511 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9767 12:11:43.693089 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9768 12:11:43.696417 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9769 12:11:43.699657 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9770 12:11:43.706181 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9771 12:11:43.709375 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9772 12:11:43.712770 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9773 12:11:43.719436 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9774 12:11:43.722722 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9775 12:11:43.729484 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9776 12:11:43.732714 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9777 12:11:43.736070 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9778 12:11:43.743186 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9779 12:11:43.746254 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9780 12:11:43.752576 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9781 12:11:43.755967 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9782 12:11:43.763110 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9783 12:11:43.766261 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9784 12:11:43.769495 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9785 12:11:43.775889 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9786 12:11:43.779168 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9787 12:11:43.786208 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9788 12:11:43.789459 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9789 12:11:43.792894 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9790 12:11:43.799463 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9791 12:11:43.802782 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9792 12:11:43.809283 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9793 12:11:43.812710 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9794 12:11:43.815891 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9795 12:11:43.822629 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9796 12:11:43.826104 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9797 12:11:43.832584 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9798 12:11:43.835841 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9799 12:11:43.842515 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9800 12:11:43.845677 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9801 12:11:43.848812 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9802 12:11:43.855770 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9803 12:11:43.859010 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9804 12:11:43.865537 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9805 12:11:43.868887 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9806 12:11:43.872226 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9807 12:11:43.879382 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9808 12:11:43.882292 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9809 12:11:43.885517 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9810 12:11:43.892469 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9811 12:11:43.895793 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9812 12:11:43.902302 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9813 12:11:43.905684 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9814 12:11:43.912144 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9815 12:11:43.915481 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9816 12:11:43.918752 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9817 12:11:43.925519 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9818 12:11:43.928763 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9819 12:11:43.935304 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9820 12:11:43.938573 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9821 12:11:43.945109 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9822 12:11:43.948440 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9823 12:11:43.951577 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9824 12:11:43.958568 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9825 12:11:43.961774 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9826 12:11:43.968248 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9827 12:11:43.971490 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9828 12:11:43.974797 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9829 12:11:43.981443 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9830 12:11:43.984715 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9831 12:11:43.991643 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9832 12:11:43.995256 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9833 12:11:43.998524 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9834 12:11:44.004925 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9835 12:11:44.008158 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9836 12:11:44.014851 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9837 12:11:44.018202 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9838 12:11:44.021480 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9839 12:11:44.028183 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9840 12:11:44.031601 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9841 12:11:44.038015 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9842 12:11:44.041258 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9843 12:11:44.047925 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9844 12:11:44.051254 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9845 12:11:44.054587 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9846 12:11:44.061440 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9847 12:11:44.064546 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9848 12:11:44.071056 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9849 12:11:44.074456 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9850 12:11:44.080974 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9851 12:11:44.084244 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9852 12:11:44.091522 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9853 12:11:44.094592 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9854 12:11:44.097684 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9855 12:11:44.104646 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9856 12:11:44.107660 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9857 12:11:44.114057 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9858 12:11:44.118024 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9859 12:11:44.124709 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9860 12:11:44.127971 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9861 12:11:44.130624 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9862 12:11:44.137799 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9863 12:11:44.141127 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9864 12:11:44.147604 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9865 12:11:44.150863 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9866 12:11:44.157443 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9867 12:11:44.160720 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9868 12:11:44.167058 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9869 12:11:44.170937 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9870 12:11:44.174071 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9871 12:11:44.180683 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9872 12:11:44.184011 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9873 12:11:44.190508 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9874 12:11:44.193817 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9875 12:11:44.200443 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9876 12:11:44.203686 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9877 12:11:44.206859 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9878 12:11:44.213733 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9879 12:11:44.216897 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9880 12:11:44.223536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9881 12:11:44.226837 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9882 12:11:44.233490 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9883 12:11:44.236686 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9884 12:11:44.240068 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9885 12:11:44.247138 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9886 12:11:44.250246 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9887 12:11:44.256920 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9888 12:11:44.260211 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9889 12:11:44.263487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9890 12:11:44.269842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9891 12:11:44.273649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9892 12:11:44.279905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9893 12:11:44.283300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9894 12:11:44.289792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9895 12:11:44.293097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9896 12:11:44.299750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9897 12:11:44.302966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9898 12:11:44.310120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9899 12:11:44.313297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9900 12:11:44.319444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9901 12:11:44.323263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9902 12:11:44.329789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9903 12:11:44.333117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9904 12:11:44.339811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9905 12:11:44.343146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9906 12:11:44.349668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9907 12:11:44.353062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9908 12:11:44.359650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9909 12:11:44.362847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9910 12:11:44.369405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9911 12:11:44.372691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9912 12:11:44.379235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9913 12:11:44.382487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9914 12:11:44.389041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9915 12:11:44.392441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9916 12:11:44.399627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9917 12:11:44.402776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9918 12:11:44.409408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9919 12:11:44.412679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9920 12:11:44.419361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9921 12:11:44.422599 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9922 12:11:44.425717 INFO: [APUAPC] vio 0
9923 12:11:44.428845 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9924 12:11:44.432632 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9925 12:11:44.435886 INFO: [APUAPC] D0_APC_0: 0x400510
9926 12:11:44.439136 INFO: [APUAPC] D0_APC_1: 0x0
9927 12:11:44.442447 INFO: [APUAPC] D0_APC_2: 0x1540
9928 12:11:44.445897 INFO: [APUAPC] D0_APC_3: 0x0
9929 12:11:44.449113 INFO: [APUAPC] D1_APC_0: 0xffffffff
9930 12:11:44.452490 INFO: [APUAPC] D1_APC_1: 0xffffffff
9931 12:11:44.455819 INFO: [APUAPC] D1_APC_2: 0x3fffff
9932 12:11:44.459027 INFO: [APUAPC] D1_APC_3: 0x0
9933 12:11:44.462245 INFO: [APUAPC] D2_APC_0: 0xffffffff
9934 12:11:44.465606 INFO: [APUAPC] D2_APC_1: 0xffffffff
9935 12:11:44.468763 INFO: [APUAPC] D2_APC_2: 0x3fffff
9936 12:11:44.472082 INFO: [APUAPC] D2_APC_3: 0x0
9937 12:11:44.475158 INFO: [APUAPC] D3_APC_0: 0xffffffff
9938 12:11:44.478443 INFO: [APUAPC] D3_APC_1: 0xffffffff
9939 12:11:44.482246 INFO: [APUAPC] D3_APC_2: 0x3fffff
9940 12:11:44.485476 INFO: [APUAPC] D3_APC_3: 0x0
9941 12:11:44.488682 INFO: [APUAPC] D4_APC_0: 0xffffffff
9942 12:11:44.491973 INFO: [APUAPC] D4_APC_1: 0xffffffff
9943 12:11:44.495166 INFO: [APUAPC] D4_APC_2: 0x3fffff
9944 12:11:44.498405 INFO: [APUAPC] D4_APC_3: 0x0
9945 12:11:44.501711 INFO: [APUAPC] D5_APC_0: 0xffffffff
9946 12:11:44.505056 INFO: [APUAPC] D5_APC_1: 0xffffffff
9947 12:11:44.508356 INFO: [APUAPC] D5_APC_2: 0x3fffff
9948 12:11:44.511714 INFO: [APUAPC] D5_APC_3: 0x0
9949 12:11:44.514891 INFO: [APUAPC] D6_APC_0: 0xffffffff
9950 12:11:44.518910 INFO: [APUAPC] D6_APC_1: 0xffffffff
9951 12:11:44.522198 INFO: [APUAPC] D6_APC_2: 0x3fffff
9952 12:11:44.525508 INFO: [APUAPC] D6_APC_3: 0x0
9953 12:11:44.528686 INFO: [APUAPC] D7_APC_0: 0xffffffff
9954 12:11:44.531869 INFO: [APUAPC] D7_APC_1: 0xffffffff
9955 12:11:44.535463 INFO: [APUAPC] D7_APC_2: 0x3fffff
9956 12:11:44.538702 INFO: [APUAPC] D7_APC_3: 0x0
9957 12:11:44.541837 INFO: [APUAPC] D8_APC_0: 0xffffffff
9958 12:11:44.545126 INFO: [APUAPC] D8_APC_1: 0xffffffff
9959 12:11:44.548280 INFO: [APUAPC] D8_APC_2: 0x3fffff
9960 12:11:44.548385 INFO: [APUAPC] D8_APC_3: 0x0
9961 12:11:44.554845 INFO: [APUAPC] D9_APC_0: 0xffffffff
9962 12:11:44.558168 INFO: [APUAPC] D9_APC_1: 0xffffffff
9963 12:11:44.562081 INFO: [APUAPC] D9_APC_2: 0x3fffff
9964 12:11:44.562193 INFO: [APUAPC] D9_APC_3: 0x0
9965 12:11:44.565373 INFO: [APUAPC] D10_APC_0: 0xffffffff
9966 12:11:44.571920 INFO: [APUAPC] D10_APC_1: 0xffffffff
9967 12:11:44.575185 INFO: [APUAPC] D10_APC_2: 0x3fffff
9968 12:11:44.575300 INFO: [APUAPC] D10_APC_3: 0x0
9969 12:11:44.578576 INFO: [APUAPC] D11_APC_0: 0xffffffff
9970 12:11:44.585134 INFO: [APUAPC] D11_APC_1: 0xffffffff
9971 12:11:44.588713 INFO: [APUAPC] D11_APC_2: 0x3fffff
9972 12:11:44.588834 INFO: [APUAPC] D11_APC_3: 0x0
9973 12:11:44.595130 INFO: [APUAPC] D12_APC_0: 0xffffffff
9974 12:11:44.598403 INFO: [APUAPC] D12_APC_1: 0xffffffff
9975 12:11:44.601770 INFO: [APUAPC] D12_APC_2: 0x3fffff
9976 12:11:44.601879 INFO: [APUAPC] D12_APC_3: 0x0
9977 12:11:44.608335 INFO: [APUAPC] D13_APC_0: 0xffffffff
9978 12:11:44.611650 INFO: [APUAPC] D13_APC_1: 0xffffffff
9979 12:11:44.614924 INFO: [APUAPC] D13_APC_2: 0x3fffff
9980 12:11:44.615049 INFO: [APUAPC] D13_APC_3: 0x0
9981 12:11:44.621506 INFO: [APUAPC] D14_APC_0: 0xffffffff
9982 12:11:44.624760 INFO: [APUAPC] D14_APC_1: 0xffffffff
9983 12:11:44.628107 INFO: [APUAPC] D14_APC_2: 0x3fffff
9984 12:11:44.631210 INFO: [APUAPC] D14_APC_3: 0x0
9985 12:11:44.634616 INFO: [APUAPC] D15_APC_0: 0xffffffff
9986 12:11:44.637975 INFO: [APUAPC] D15_APC_1: 0xffffffff
9987 12:11:44.641634 INFO: [APUAPC] D15_APC_2: 0x3fffff
9988 12:11:44.644864 INFO: [APUAPC] D15_APC_3: 0x0
9989 12:11:44.644945 INFO: [APUAPC] APC_CON: 0x4
9990 12:11:44.647931 INFO: [NOCDAPC] D0_APC_0: 0x0
9991 12:11:44.651109 INFO: [NOCDAPC] D0_APC_1: 0x0
9992 12:11:44.654942 INFO: [NOCDAPC] D1_APC_0: 0x0
9993 12:11:44.658331 INFO: [NOCDAPC] D1_APC_1: 0xfff
9994 12:11:44.661592 INFO: [NOCDAPC] D2_APC_0: 0x0
9995 12:11:44.664851 INFO: [NOCDAPC] D2_APC_1: 0xfff
9996 12:11:44.668054 INFO: [NOCDAPC] D3_APC_0: 0x0
9997 12:11:44.671373 INFO: [NOCDAPC] D3_APC_1: 0xfff
9998 12:11:44.671481 INFO: [NOCDAPC] D4_APC_0: 0x0
9999 12:11:44.674618 INFO: [NOCDAPC] D4_APC_1: 0xfff
10000 12:11:44.677913 INFO: [NOCDAPC] D5_APC_0: 0x0
10001 12:11:44.681226 INFO: [NOCDAPC] D5_APC_1: 0xfff
10002 12:11:44.684606 INFO: [NOCDAPC] D6_APC_0: 0x0
10003 12:11:44.687891 INFO: [NOCDAPC] D6_APC_1: 0xfff
10004 12:11:44.691077 INFO: [NOCDAPC] D7_APC_0: 0x0
10005 12:11:44.694729 INFO: [NOCDAPC] D7_APC_1: 0xfff
10006 12:11:44.698110 INFO: [NOCDAPC] D8_APC_0: 0x0
10007 12:11:44.701427 INFO: [NOCDAPC] D8_APC_1: 0xfff
10008 12:11:44.704595 INFO: [NOCDAPC] D9_APC_0: 0x0
10009 12:11:44.704696 INFO: [NOCDAPC] D9_APC_1: 0xfff
10010 12:11:44.707935 INFO: [NOCDAPC] D10_APC_0: 0x0
10011 12:11:44.711151 INFO: [NOCDAPC] D10_APC_1: 0xfff
10012 12:11:44.714404 INFO: [NOCDAPC] D11_APC_0: 0x0
10013 12:11:44.717728 INFO: [NOCDAPC] D11_APC_1: 0xfff
10014 12:11:44.720968 INFO: [NOCDAPC] D12_APC_0: 0x0
10015 12:11:44.724298 INFO: [NOCDAPC] D12_APC_1: 0xfff
10016 12:11:44.727614 INFO: [NOCDAPC] D13_APC_0: 0x0
10017 12:11:44.730863 INFO: [NOCDAPC] D13_APC_1: 0xfff
10018 12:11:44.734143 INFO: [NOCDAPC] D14_APC_0: 0x0
10019 12:11:44.737487 INFO: [NOCDAPC] D14_APC_1: 0xfff
10020 12:11:44.740752 INFO: [NOCDAPC] D15_APC_0: 0x0
10021 12:11:44.743925 INFO: [NOCDAPC] D15_APC_1: 0xfff
10022 12:11:44.747774 INFO: [NOCDAPC] APC_CON: 0x4
10023 12:11:44.750944 INFO: [APUAPC] set_apusys_apc done
10024 12:11:44.754120 INFO: [DEVAPC] devapc_init done
10025 12:11:44.757431 INFO: GICv3 without legacy support detected.
10026 12:11:44.760796 INFO: ARM GICv3 driver initialized in EL3
10027 12:11:44.764044 INFO: Maximum SPI INTID supported: 639
10028 12:11:44.767213 INFO: BL31: Initializing runtime services
10029 12:11:44.773799 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10030 12:11:44.777020 INFO: SPM: enable CPC mode
10031 12:11:44.780329 INFO: mcdi ready for mcusys-off-idle and system suspend
10032 12:11:44.786922 INFO: BL31: Preparing for EL3 exit to normal world
10033 12:11:44.790901 INFO: Entry point address = 0x80000000
10034 12:11:44.793479 INFO: SPSR = 0x8
10035 12:11:44.798165
10036 12:11:44.798241
10037 12:11:44.798305
10038 12:11:44.801412 Starting depthcharge on Spherion...
10039 12:11:44.801500
10040 12:11:44.801567 Wipe memory regions:
10041 12:11:44.801629
10042 12:11:44.802235 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10043 12:11:44.802337 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10044 12:11:44.802420 Setting prompt string to ['asurada:']
10045 12:11:44.802501 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10046 12:11:44.804631 [0x00000040000000, 0x00000054600000)
10047 12:11:44.927175
10048 12:11:44.927359 [0x00000054660000, 0x00000080000000)
10049 12:11:45.187788
10050 12:11:45.187937 [0x000000821a7280, 0x000000ffe64000)
10051 12:11:45.932764
10052 12:11:45.932918 [0x00000100000000, 0x00000240000000)
10053 12:11:47.823187
10054 12:11:47.826446 Initializing XHCI USB controller at 0x11200000.
10055 12:11:48.864221
10056 12:11:48.867519 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10057 12:11:48.867635
10058 12:11:48.867712
10059 12:11:48.867811
10060 12:11:48.868139 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 12:11:48.968528 asurada: tftpboot 192.168.201.1 10605394/tftp-deploy-aoyxsptu/kernel/image.itb 10605394/tftp-deploy-aoyxsptu/kernel/cmdline
10063 12:11:48.968726 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10064 12:11:48.968860 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10065 12:11:48.972449 tftpboot 192.168.201.1 10605394/tftp-deploy-aoyxsptu/kernel/image.itp-deploy-aoyxsptu/kernel/cmdline
10066 12:11:48.972564
10067 12:11:48.972674 Waiting for link
10068 12:11:49.133238
10069 12:11:49.133419 R8152: Initializing
10070 12:11:49.133528
10071 12:11:49.136521 Version 6 (ocp_data = 5c30)
10072 12:11:49.136641
10073 12:11:49.139671 R8152: Done initializing
10074 12:11:49.139787
10075 12:11:49.139882 Adding net device
10076 12:11:51.011278
10077 12:11:51.011439 done.
10078 12:11:51.011548
10079 12:11:51.011641 MAC: 00:24:32:30:78:52
10080 12:11:51.011736
10081 12:11:51.015174 Sending DHCP discover... done.
10082 12:11:51.015283
10083 12:11:51.018425 Waiting for reply... done.
10084 12:11:51.018535
10085 12:11:51.021585 Sending DHCP request... done.
10086 12:11:51.021703
10087 12:11:51.039392 Waiting for reply... done.
10088 12:11:51.039576
10089 12:11:51.039664 My ip is 192.168.201.14
10090 12:11:51.039732
10091 12:11:51.042596 The DHCP server ip is 192.168.201.1
10092 12:11:51.042719
10093 12:11:51.049595 TFTP server IP predefined by user: 192.168.201.1
10094 12:11:51.049726
10095 12:11:51.056156 Bootfile predefined by user: 10605394/tftp-deploy-aoyxsptu/kernel/image.itb
10096 12:11:51.056267
10097 12:11:51.056372 Sending tftp read request... done.
10098 12:11:51.059433
10099 12:11:51.063356 Waiting for the transfer...
10100 12:11:51.063466
10101 12:11:51.593755 00000000 ################################################################
10102 12:11:51.593950
10103 12:11:52.115556 00080000 ################################################################
10104 12:11:52.115703
10105 12:11:52.624965 00100000 ################################################################
10106 12:11:52.625112
10107 12:11:53.159232 00180000 ################################################################
10108 12:11:53.159416
10109 12:11:53.688598 00200000 ################################################################
10110 12:11:53.688765
10111 12:11:54.213384 00280000 ################################################################
10112 12:11:54.213550
10113 12:11:54.735664 00300000 ################################################################
10114 12:11:54.735809
10115 12:11:55.256159 00380000 ################################################################
10116 12:11:55.256328
10117 12:11:55.776085 00400000 ################################################################
10118 12:11:55.776274
10119 12:11:56.297494 00480000 ################################################################
10120 12:11:56.297664
10121 12:11:56.820699 00500000 ################################################################
10122 12:11:56.820880
10123 12:11:57.346657 00580000 ################################################################
10124 12:11:57.346801
10125 12:11:58.729985 00600000 ################################################################
10126 12:11:58.730740
10127 12:11:58.730883 00680000 ################################################################
10128 12:11:58.730993
10129 12:11:58.911475 00700000 ################################################################
10130 12:11:58.911713
10131 12:11:59.420053 00780000 ################################################################
10132 12:11:59.420220
10133 12:11:59.976472 00800000 ################################################################
10134 12:11:59.976882
10135 12:12:00.514120 00880000 ################################################################
10136 12:12:00.514289
10137 12:12:01.022549 00900000 ################################################################
10138 12:12:01.022687
10139 12:12:01.536149 00980000 ################################################################
10140 12:12:01.536389
10141 12:12:02.062890 00a00000 ################################################################
10142 12:12:02.063072
10143 12:12:02.583497 00a80000 ################################################################
10144 12:12:02.583667
10145 12:12:03.129138 00b00000 ################################################################
10146 12:12:03.129304
10147 12:12:03.669964 00b80000 ################################################################
10148 12:12:03.670116
10149 12:12:04.209718 00c00000 ################################################################
10150 12:12:04.209874
10151 12:12:04.737712 00c80000 ################################################################
10152 12:12:04.737864
10153 12:12:05.263879 00d00000 ################################################################
10154 12:12:05.264046
10155 12:12:05.826313 00d80000 ################################################################
10156 12:12:05.826476
10157 12:12:06.347337 00e00000 ################################################################
10158 12:12:06.347507
10159 12:12:06.869867 00e80000 ################################################################
10160 12:12:06.870004
10161 12:12:07.382941 00f00000 ################################################################
10162 12:12:07.383112
10163 12:12:07.912273 00f80000 ################################################################
10164 12:12:07.912418
10165 12:12:08.437383 01000000 ################################################################
10166 12:12:08.437555
10167 12:12:08.969731 01080000 ################################################################
10168 12:12:08.969905
10169 12:12:09.502374 01100000 ################################################################
10170 12:12:09.502532
10171 12:12:10.027703 01180000 ################################################################
10172 12:12:10.027846
10173 12:12:10.557342 01200000 ################################################################
10174 12:12:10.557506
10175 12:12:11.114307 01280000 ################################################################
10176 12:12:11.114478
10177 12:12:11.667691 01300000 ################################################################
10178 12:12:11.667869
10179 12:12:12.207293 01380000 ################################################################
10180 12:12:12.207501
10181 12:12:12.749495 01400000 ################################################################
10182 12:12:12.749674
10183 12:12:13.303972 01480000 ################################################################
10184 12:12:13.304130
10185 12:12:13.850401 01500000 ################################################################
10186 12:12:13.850558
10187 12:12:14.389499 01580000 ################################################################
10188 12:12:14.389696
10189 12:12:14.927381 01600000 ################################################################
10190 12:12:14.927566
10191 12:12:15.463591 01680000 ################################################################
10192 12:12:15.463773
10193 12:12:16.004986 01700000 ################################################################
10194 12:12:16.005172
10195 12:12:16.537044 01780000 ################################################################
10196 12:12:16.537198
10197 12:12:17.066310 01800000 ################################################################
10198 12:12:17.066497
10199 12:12:17.595262 01880000 ################################################################
10200 12:12:17.595428
10201 12:12:18.131090 01900000 ################################################################
10202 12:12:18.131265
10203 12:12:18.657868 01980000 ################################################################
10204 12:12:18.658008
10205 12:12:19.180270 01a00000 ################################################################
10206 12:12:19.180442
10207 12:12:19.714263 01a80000 ################################################################
10208 12:12:19.714434
10209 12:12:20.266332 01b00000 ################################################################
10210 12:12:20.266494
10211 12:12:20.791487 01b80000 ################################################################
10212 12:12:20.791636
10213 12:12:21.311765 01c00000 ################################################################
10214 12:12:21.311951
10215 12:12:21.834217 01c80000 ################################################################
10216 12:12:21.834374
10217 12:12:22.361946 01d00000 ################################################################
10218 12:12:22.362099
10219 12:12:22.891623 01d80000 ################################################################
10220 12:12:22.891793
10221 12:12:23.420641 01e00000 ################################################################
10222 12:12:23.420791
10223 12:12:23.945366 01e80000 ################################################################
10224 12:12:23.945528
10225 12:12:24.490933 01f00000 ################################################################
10226 12:12:24.491117
10227 12:12:25.019252 01f80000 ################################################################
10228 12:12:25.019402
10229 12:12:25.550932 02000000 ################################################################
10230 12:12:25.551102
10231 12:12:26.088142 02080000 ################################################################
10232 12:12:26.088304
10233 12:12:26.623297 02100000 ################################################################
10234 12:12:26.623495
10235 12:12:27.152378 02180000 ################################################################
10236 12:12:27.152531
10237 12:12:27.705920 02200000 ################################################################
10238 12:12:27.706070
10239 12:12:28.254617 02280000 ################################################################
10240 12:12:28.254772
10241 12:12:28.787255 02300000 ################################################################
10242 12:12:28.787430
10243 12:12:29.323939 02380000 ################################################################
10244 12:12:29.324085
10245 12:12:29.853145 02400000 ################################################################
10246 12:12:29.853357
10247 12:12:30.375948 02480000 ################################################################
10248 12:12:30.376107
10249 12:12:30.903899 02500000 ################################################################
10250 12:12:30.904065
10251 12:12:31.477614 02580000 ################################################################
10252 12:12:31.477769
10253 12:12:32.091646 02600000 ################################################################
10254 12:12:32.091827
10255 12:12:32.694539 02680000 ################################################################
10256 12:12:32.694692
10257 12:12:33.235564 02700000 ################################################################
10258 12:12:33.235709
10259 12:12:33.781564 02780000 ################################################################
10260 12:12:33.781718
10261 12:12:34.324716 02800000 ################################################################
10262 12:12:34.324859
10263 12:12:34.888570 02880000 ################################################################
10264 12:12:34.888732
10265 12:12:35.433403 02900000 ################################################################
10266 12:12:35.433557
10267 12:12:35.965303 02980000 ################################################################
10268 12:12:35.965481
10269 12:12:36.494708 02a00000 ################################################################
10270 12:12:36.494847
10271 12:12:37.027507 02a80000 ################################################################
10272 12:12:37.027646
10273 12:12:37.560286 02b00000 ################################################################
10274 12:12:37.560426
10275 12:12:38.093230 02b80000 ################################################################
10276 12:12:38.093366
10277 12:12:38.638576 02c00000 ################################################################
10278 12:12:38.638714
10279 12:12:39.183624 02c80000 ################################################################
10280 12:12:39.183797
10281 12:12:39.744216 02d00000 ################################################################
10282 12:12:39.744360
10283 12:12:40.305319 02d80000 ################################################################
10284 12:12:40.305498
10285 12:12:40.885027 02e00000 ################################################################
10286 12:12:40.885198
10287 12:12:41.450529 02e80000 ################################################################
10288 12:12:41.450684
10289 12:12:42.003648 02f00000 ################################################################
10290 12:12:42.003834
10291 12:12:42.547524 02f80000 ########################################################## done.
10292 12:12:42.547663
10293 12:12:42.550878 The bootfile was 50279070 bytes long.
10294 12:12:42.550995
10295 12:12:42.554179 Sending tftp read request... done.
10296 12:12:42.554285
10297 12:12:42.554381 Waiting for the transfer...
10298 12:12:42.554481
10299 12:12:42.557519 00000000 # done.
10300 12:12:42.557611
10301 12:12:42.564180 Command line loaded dynamically from TFTP file: 10605394/tftp-deploy-aoyxsptu/kernel/cmdline
10302 12:12:42.564265
10303 12:12:42.577385 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10304 12:12:42.577476
10305 12:12:42.577544 Loading FIT.
10306 12:12:42.577606
10307 12:12:42.580556 Image ramdisk-1 has 40135491 bytes.
10308 12:12:42.580642
10309 12:12:42.583765 Image fdt-1 has 46924 bytes.
10310 12:12:42.583851
10311 12:12:42.587511 Image kernel-1 has 10094623 bytes.
10312 12:12:42.587596
10313 12:12:42.593972 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10314 12:12:42.594083
10315 12:12:42.613621 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10316 12:12:42.613778
10317 12:12:42.616789 Choosing best match conf-1 for compat google,spherion-rev2.
10318 12:12:42.622147
10319 12:12:42.626768 Connected to device vid:did:rid of 1ae0:0028:00
10320 12:12:42.634024
10321 12:12:42.637044 tpm_get_response: command 0x17b, return code 0x0
10322 12:12:42.637154
10323 12:12:42.640398 ec_init: CrosEC protocol v3 supported (256, 248)
10324 12:12:42.644339
10325 12:12:42.647640 tpm_cleanup: add release locality here.
10326 12:12:42.647745
10327 12:12:42.647843 Shutting down all USB controllers.
10328 12:12:42.651011
10329 12:12:42.651096 Removing current net device
10330 12:12:42.651219
10331 12:12:42.657568 Exiting depthcharge with code 4 at timestamp: 87233083
10332 12:12:42.657656
10333 12:12:42.660850 LZMA decompressing kernel-1 to 0x821a6718
10334 12:12:42.660933
10335 12:12:42.664209 LZMA decompressing kernel-1 to 0x40000000
10336 12:12:43.932884
10337 12:12:43.933044 jumping to kernel
10338 12:12:43.933471 end: 2.2.4 bootloader-commands (duration 00:00:59) [common]
10339 12:12:43.933576 start: 2.2.5 auto-login-action (timeout 00:03:26) [common]
10340 12:12:43.933654 Setting prompt string to ['Linux version [0-9]']
10341 12:12:43.933723 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10342 12:12:43.933792 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10343 12:12:44.013953
10344 12:12:44.017159 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10345 12:12:44.020707 start: 2.2.5.1 login-action (timeout 00:03:26) [common]
10346 12:12:44.020803 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10347 12:12:44.020890 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10348 12:12:44.020966 Using line separator: #'\n'#
10349 12:12:44.021027 No login prompt set.
10350 12:12:44.021091 Parsing kernel messages
10351 12:12:44.021147 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10352 12:12:44.021247 [login-action] Waiting for messages, (timeout 00:03:26)
10353 12:12:44.040807 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
10354 12:12:44.043936 [ 0.000000] random: crng init done
10355 12:12:44.047682 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10356 12:12:44.050816 [ 0.000000] efi: UEFI not found.
10357 12:12:44.060555 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10358 12:12:44.067015 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10359 12:12:44.077138 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10360 12:12:44.087161 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10361 12:12:44.093628 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10362 12:12:44.101079 [ 0.000000] printk: bootconsole [mtk8250] enabled
10363 12:12:44.105939 [ 0.000000] NUMA: No NUMA configuration found
10364 12:12:44.112587 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10365 12:12:44.119131 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10366 12:12:44.119216 [ 0.000000] Zone ranges:
10367 12:12:44.125453 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10368 12:12:44.129298 [ 0.000000] DMA32 empty
10369 12:12:44.135769 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10370 12:12:44.139068 [ 0.000000] Movable zone start for each node
10371 12:12:44.142229 [ 0.000000] Early memory node ranges
10372 12:12:44.148542 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10373 12:12:44.155527 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10374 12:12:44.162086 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10375 12:12:44.168582 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10376 12:12:44.175028 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10377 12:12:44.181767 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10378 12:12:44.237971 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10379 12:12:44.244519 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10380 12:12:44.251807 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10381 12:12:44.254687 [ 0.000000] psci: probing for conduit method from DT.
10382 12:12:44.261622 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10383 12:12:44.264801 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10384 12:12:44.271219 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10385 12:12:44.274658 [ 0.000000] psci: SMC Calling Convention v1.2
10386 12:12:44.281188 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10387 12:12:44.284485 [ 0.000000] Detected VIPT I-cache on CPU0
10388 12:12:44.290991 [ 0.000000] CPU features: detected: GIC system register CPU interface
10389 12:12:44.298059 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10390 12:12:44.304479 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10391 12:12:44.310924 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10392 12:12:44.317580 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10393 12:12:44.327352 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10394 12:12:44.330649 [ 0.000000] alternatives: applying boot alternatives
10395 12:12:44.337646 [ 0.000000] Fallback order for Node 0: 0
10396 12:12:44.344051 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10397 12:12:44.347464 [ 0.000000] Policy zone: Normal
10398 12:12:44.357222 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10399 12:12:44.367189 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10400 12:12:44.380422 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10401 12:12:44.390490 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10402 12:12:44.393802 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10403 12:12:44.400261 <6>[ 0.000000] software IO TLB: area num 8.
10404 12:12:44.456025 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10405 12:12:44.604855 <6>[ 0.000000] Memory: 7933748K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419020K reserved, 32768K cma-reserved)
10406 12:12:44.611289 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10407 12:12:44.618308 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10408 12:12:44.621644 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10409 12:12:44.628160 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10410 12:12:44.634709 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10411 12:12:44.637922 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10412 12:12:44.647703 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10413 12:12:44.654709 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10414 12:12:44.661209 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10415 12:12:44.667720 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10416 12:12:44.671030 <6>[ 0.000000] GICv3: 608 SPIs implemented
10417 12:12:44.674220 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10418 12:12:44.680628 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10419 12:12:44.684452 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10420 12:12:44.690932 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10421 12:12:44.704083 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10422 12:12:44.713942 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10423 12:12:44.723970 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10424 12:12:44.731663 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10425 12:12:44.744213 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10426 12:12:44.751377 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10427 12:12:44.757719 <6>[ 0.009177] Console: colour dummy device 80x25
10428 12:12:44.768085 <6>[ 0.013934] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10429 12:12:44.774663 <6>[ 0.024375] pid_max: default: 32768 minimum: 301
10430 12:12:44.777841 <6>[ 0.029248] LSM: Security Framework initializing
10431 12:12:44.784530 <6>[ 0.034187] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10432 12:12:44.794798 <6>[ 0.042001] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10433 12:12:44.801347 <6>[ 0.051432] cblist_init_generic: Setting adjustable number of callback queues.
10434 12:12:44.807968 <6>[ 0.058931] cblist_init_generic: Setting shift to 3 and lim to 1.
10435 12:12:44.814504 <6>[ 0.065270] cblist_init_generic: Setting shift to 3 and lim to 1.
10436 12:12:44.820979 <6>[ 0.071677] rcu: Hierarchical SRCU implementation.
10437 12:12:44.824175 <6>[ 0.076722] rcu: Max phase no-delay instances is 1000.
10438 12:12:44.832639 <6>[ 0.083742] EFI services will not be available.
10439 12:12:44.835746 <6>[ 0.088747] smp: Bringing up secondary CPUs ...
10440 12:12:44.845055 <6>[ 0.093802] Detected VIPT I-cache on CPU1
10441 12:12:44.851596 <6>[ 0.093874] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10442 12:12:44.858170 <6>[ 0.093906] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10443 12:12:44.861203 <6>[ 0.094243] Detected VIPT I-cache on CPU2
10444 12:12:44.870854 <6>[ 0.094292] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10445 12:12:44.877990 <6>[ 0.094307] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10446 12:12:44.881290 <6>[ 0.094566] Detected VIPT I-cache on CPU3
10447 12:12:44.887832 <6>[ 0.094612] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10448 12:12:44.894067 <6>[ 0.094626] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10449 12:12:44.897342 <6>[ 0.094933] CPU features: detected: Spectre-v4
10450 12:12:44.904575 <6>[ 0.094940] CPU features: detected: Spectre-BHB
10451 12:12:44.907205 <6>[ 0.094946] Detected PIPT I-cache on CPU4
10452 12:12:44.914535 <6>[ 0.095004] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10453 12:12:44.920832 <6>[ 0.095021] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10454 12:12:44.927295 <6>[ 0.095321] Detected PIPT I-cache on CPU5
10455 12:12:44.934266 <6>[ 0.095385] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10456 12:12:44.940861 <6>[ 0.095401] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10457 12:12:44.944302 <6>[ 0.095685] Detected PIPT I-cache on CPU6
10458 12:12:44.950914 <6>[ 0.095751] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10459 12:12:44.957353 <6>[ 0.095767] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10460 12:12:44.963673 <6>[ 0.096066] Detected PIPT I-cache on CPU7
10461 12:12:44.970589 <6>[ 0.096134] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10462 12:12:44.976907 <6>[ 0.096151] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10463 12:12:44.980217 <6>[ 0.096198] smp: Brought up 1 node, 8 CPUs
10464 12:12:44.986846 <6>[ 0.237493] SMP: Total of 8 processors activated.
10465 12:12:44.990018 <6>[ 0.242414] CPU features: detected: 32-bit EL0 Support
10466 12:12:45.000169 <6>[ 0.247777] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10467 12:12:45.006619 <6>[ 0.256577] CPU features: detected: Common not Private translations
10468 12:12:45.013251 <6>[ 0.263053] CPU features: detected: CRC32 instructions
10469 12:12:45.016635 <6>[ 0.268404] CPU features: detected: RCpc load-acquire (LDAPR)
10470 12:12:45.023148 <6>[ 0.274364] CPU features: detected: LSE atomic instructions
10471 12:12:45.029673 <6>[ 0.280145] CPU features: detected: Privileged Access Never
10472 12:12:45.036579 <6>[ 0.285961] CPU features: detected: RAS Extension Support
10473 12:12:45.043140 <6>[ 0.291570] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10474 12:12:45.046519 <6>[ 0.298793] CPU: All CPU(s) started at EL2
10475 12:12:45.053103 <6>[ 0.303109] alternatives: applying system-wide alternatives
10476 12:12:45.062149 <6>[ 0.313850] devtmpfs: initialized
10477 12:12:45.074695 <6>[ 0.322663] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10478 12:12:45.084443 <6>[ 0.332622] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10479 12:12:45.091055 <6>[ 0.340585] pinctrl core: initialized pinctrl subsystem
10480 12:12:45.094292 <6>[ 0.347246] DMI not present or invalid.
10481 12:12:45.101121 <6>[ 0.351651] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10482 12:12:45.111304 <6>[ 0.358528] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10483 12:12:45.117809 <6>[ 0.366106] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10484 12:12:45.127776 <6>[ 0.374316] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10485 12:12:45.130959 <6>[ 0.382557] audit: initializing netlink subsys (disabled)
10486 12:12:45.140937 <5>[ 0.388250] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10487 12:12:45.147730 <6>[ 0.388956] thermal_sys: Registered thermal governor 'step_wise'
10488 12:12:45.154311 <6>[ 0.396215] thermal_sys: Registered thermal governor 'power_allocator'
10489 12:12:45.157633 <6>[ 0.402469] cpuidle: using governor menu
10490 12:12:45.164243 <6>[ 0.413431] NET: Registered PF_QIPCRTR protocol family
10491 12:12:45.170174 <6>[ 0.418911] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10492 12:12:45.173519 <6>[ 0.426014] ASID allocator initialised with 32768 entries
10493 12:12:45.180929 <6>[ 0.432577] Serial: AMBA PL011 UART driver
10494 12:12:45.189988 <4>[ 0.441208] Trying to register duplicate clock ID: 134
10495 12:12:45.243745 <6>[ 0.498255] KASLR enabled
10496 12:12:45.257860 <6>[ 0.505968] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10497 12:12:45.264473 <6>[ 0.512978] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10498 12:12:45.271030 <6>[ 0.519469] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10499 12:12:45.277501 <6>[ 0.526475] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10500 12:12:45.284403 <6>[ 0.532963] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10501 12:12:45.290960 <6>[ 0.539969] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10502 12:12:45.297531 <6>[ 0.546456] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10503 12:12:45.304252 <6>[ 0.553460] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10504 12:12:45.307563 <6>[ 0.560962] ACPI: Interpreter disabled.
10505 12:12:45.316199 <6>[ 0.567342] iommu: Default domain type: Translated
10506 12:12:45.322538 <6>[ 0.572451] iommu: DMA domain TLB invalidation policy: strict mode
10507 12:12:45.325832 <5>[ 0.579104] SCSI subsystem initialized
10508 12:12:45.332361 <6>[ 0.583272] usbcore: registered new interface driver usbfs
10509 12:12:45.338798 <6>[ 0.589004] usbcore: registered new interface driver hub
10510 12:12:45.342130 <6>[ 0.594555] usbcore: registered new device driver usb
10511 12:12:45.349126 <6>[ 0.600633] pps_core: LinuxPPS API ver. 1 registered
10512 12:12:45.359540 <6>[ 0.605827] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10513 12:12:45.362926 <6>[ 0.615173] PTP clock support registered
10514 12:12:45.365542 <6>[ 0.619414] EDAC MC: Ver: 3.0.0
10515 12:12:45.372922 <6>[ 0.624560] FPGA manager framework
10516 12:12:45.379537 <6>[ 0.628238] Advanced Linux Sound Architecture Driver Initialized.
10517 12:12:45.382890 <6>[ 0.635007] vgaarb: loaded
10518 12:12:45.389710 <6>[ 0.638164] clocksource: Switched to clocksource arch_sys_counter
10519 12:12:45.392957 <5>[ 0.644604] VFS: Disk quotas dquot_6.6.0
10520 12:12:45.399723 <6>[ 0.648787] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10521 12:12:45.402985 <6>[ 0.655976] pnp: PnP ACPI: disabled
10522 12:12:45.411603 <6>[ 0.662633] NET: Registered PF_INET protocol family
10523 12:12:45.421013 <6>[ 0.668216] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10524 12:12:45.432447 <6>[ 0.680489] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10525 12:12:45.442298 <6>[ 0.689305] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10526 12:12:45.448850 <6>[ 0.697274] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10527 12:12:45.455755 <6>[ 0.705974] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10528 12:12:45.467534 <6>[ 0.715722] TCP: Hash tables configured (established 65536 bind 65536)
10529 12:12:45.474537 <6>[ 0.722576] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10530 12:12:45.481104 <6>[ 0.729769] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10531 12:12:45.487631 <6>[ 0.737470] NET: Registered PF_UNIX/PF_LOCAL protocol family
10532 12:12:45.493928 <6>[ 0.743640] RPC: Registered named UNIX socket transport module.
10533 12:12:45.497032 <6>[ 0.749795] RPC: Registered udp transport module.
10534 12:12:45.503685 <6>[ 0.754727] RPC: Registered tcp transport module.
10535 12:12:45.510327 <6>[ 0.759660] RPC: Registered tcp NFSv4.1 backchannel transport module.
10536 12:12:45.513665 <6>[ 0.766327] PCI: CLS 0 bytes, default 64
10537 12:12:45.516826 <6>[ 0.770681] Unpacking initramfs...
10538 12:12:45.534551 <6>[ 0.782822] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10539 12:12:45.545041 <6>[ 0.791486] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10540 12:12:45.547672 <6>[ 0.800321] kvm [1]: IPA Size Limit: 40 bits
10541 12:12:45.554254 <6>[ 0.804848] kvm [1]: GICv3: no GICV resource entry
10542 12:12:45.557936 <6>[ 0.809866] kvm [1]: disabling GICv2 emulation
10543 12:12:45.564268 <6>[ 0.814553] kvm [1]: GIC system register CPU interface enabled
10544 12:12:45.568129 <6>[ 0.820714] kvm [1]: vgic interrupt IRQ18
10545 12:12:45.574173 <6>[ 0.825079] kvm [1]: VHE mode initialized successfully
10546 12:12:45.581351 <5>[ 0.831535] Initialise system trusted keyrings
10547 12:12:45.587223 <6>[ 0.836353] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10548 12:12:45.594566 <6>[ 0.846286] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10549 12:12:45.601403 <5>[ 0.852669] NFS: Registering the id_resolver key type
10550 12:12:45.604721 <5>[ 0.857971] Key type id_resolver registered
10551 12:12:45.611292 <5>[ 0.862387] Key type id_legacy registered
10552 12:12:45.618063 <6>[ 0.866669] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10553 12:12:45.625129 <6>[ 0.873591] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10554 12:12:45.631501 <6>[ 0.881321] 9p: Installing v9fs 9p2000 file system support
10555 12:12:45.667423 <5>[ 0.919115] Key type asymmetric registered
10556 12:12:45.671177 <5>[ 0.923444] Asymmetric key parser 'x509' registered
10557 12:12:45.681103 <6>[ 0.928579] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10558 12:12:45.684372 <6>[ 0.936191] io scheduler mq-deadline registered
10559 12:12:45.687643 <6>[ 0.940953] io scheduler kyber registered
10560 12:12:45.706361 <6>[ 0.957817] EINJ: ACPI disabled.
10561 12:12:45.738058 <4>[ 0.983124] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10562 12:12:45.748429 <4>[ 0.993772] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10563 12:12:45.763262 <6>[ 1.014528] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10564 12:12:45.770914 <6>[ 1.022569] printk: console [ttyS0] disabled
10565 12:12:45.798828 <6>[ 1.047215] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10566 12:12:45.805407 <6>[ 1.056689] printk: console [ttyS0] enabled
10567 12:12:45.809197 <6>[ 1.056689] printk: console [ttyS0] enabled
10568 12:12:45.815883 <6>[ 1.065584] printk: bootconsole [mtk8250] disabled
10569 12:12:45.819177 <6>[ 1.065584] printk: bootconsole [mtk8250] disabled
10570 12:12:45.825767 <6>[ 1.076778] SuperH (H)SCI(F) driver initialized
10571 12:12:45.829112 <6>[ 1.082054] msm_serial: driver initialized
10572 12:12:45.842897 <6>[ 1.091057] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10573 12:12:45.853218 <6>[ 1.099608] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10574 12:12:45.859730 <6>[ 1.108150] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10575 12:12:45.869517 <6>[ 1.116779] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10576 12:12:45.879578 <6>[ 1.125489] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10577 12:12:45.886128 <6>[ 1.134209] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10578 12:12:45.895985 <6>[ 1.142750] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10579 12:12:45.902593 <6>[ 1.151560] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10580 12:12:45.912307 <6>[ 1.160103] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10581 12:12:45.924298 <6>[ 1.175795] loop: module loaded
10582 12:12:45.930946 <6>[ 1.181829] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10583 12:12:45.953857 <4>[ 1.205340] mtk-pmic-keys: Failed to locate of_node [id: -1]
10584 12:12:45.961028 <6>[ 1.212205] megasas: 07.719.03.00-rc1
10585 12:12:45.970110 <6>[ 1.221739] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10586 12:12:45.982097 <6>[ 1.233536] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10587 12:12:45.998990 <6>[ 1.250208] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10588 12:12:46.060168 <6>[ 1.304414] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10589 12:12:47.139935 <6>[ 2.392070] Freeing initrd memory: 39188K
10590 12:12:47.150409 <6>[ 2.402250] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10591 12:12:47.161609 <6>[ 2.412988] tun: Universal TUN/TAP device driver, 1.6
10592 12:12:47.164782 <6>[ 2.419029] thunder_xcv, ver 1.0
10593 12:12:47.167998 <6>[ 2.422536] thunder_bgx, ver 1.0
10594 12:12:47.171332 <6>[ 2.426024] nicpf, ver 1.0
10595 12:12:47.181827 <6>[ 2.430034] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10596 12:12:47.185155 <6>[ 2.437510] hns3: Copyright (c) 2017 Huawei Corporation.
10597 12:12:47.191649 <6>[ 2.443096] hclge is initializing
10598 12:12:47.195076 <6>[ 2.446672] e1000: Intel(R) PRO/1000 Network Driver
10599 12:12:47.201647 <6>[ 2.451801] e1000: Copyright (c) 1999-2006 Intel Corporation.
10600 12:12:47.204916 <6>[ 2.457830] e1000e: Intel(R) PRO/1000 Network Driver
10601 12:12:47.211574 <6>[ 2.463046] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10602 12:12:47.218193 <6>[ 2.469231] igb: Intel(R) Gigabit Ethernet Network Driver
10603 12:12:47.224680 <6>[ 2.474881] igb: Copyright (c) 2007-2014 Intel Corporation.
10604 12:12:47.231507 <6>[ 2.480719] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10605 12:12:47.238253 <6>[ 2.487238] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10606 12:12:47.241422 <6>[ 2.493695] sky2: driver version 1.30
10607 12:12:47.247570 <6>[ 2.498668] VFIO - User Level meta-driver version: 0.3
10608 12:12:47.255008 <6>[ 2.506870] usbcore: registered new interface driver usb-storage
10609 12:12:47.261543 <6>[ 2.513312] usbcore: registered new device driver onboard-usb-hub
10610 12:12:47.271185 <6>[ 2.522379] mt6397-rtc mt6359-rtc: registered as rtc0
10611 12:12:47.280680 <6>[ 2.527841] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:12:58 UTC (1686053578)
10612 12:12:47.284035 <6>[ 2.537393] i2c_dev: i2c /dev entries driver
10613 12:12:47.301008 <6>[ 2.549089] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10614 12:12:47.307671 <6>[ 2.559283] sdhci: Secure Digital Host Controller Interface driver
10615 12:12:47.314223 <6>[ 2.565721] sdhci: Copyright(c) Pierre Ossman
10616 12:12:47.320879 <6>[ 2.571111] Synopsys Designware Multimedia Card Interface Driver
10617 12:12:47.324203 <6>[ 2.577708] mmc0: CQHCI version 5.10
10618 12:12:47.330714 <6>[ 2.578269] sdhci-pltfm: SDHCI platform and OF driver helper
10619 12:12:47.338294 <6>[ 2.589629] ledtrig-cpu: registered to indicate activity on CPUs
10620 12:12:47.348652 <6>[ 2.596998] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10621 12:12:47.352203 <6>[ 2.604393] usbcore: registered new interface driver usbhid
10622 12:12:47.358836 <6>[ 2.610226] usbhid: USB HID core driver
10623 12:12:47.365157 <6>[ 2.614461] spi_master spi0: will run message pump with realtime priority
10624 12:12:47.411510 <6>[ 2.656452] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10625 12:12:47.430138 <6>[ 2.671602] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10626 12:12:47.433400 <6>[ 2.685188] mmc0: Command Queue Engine enabled
10627 12:12:47.440613 <6>[ 2.686798] cros-ec-spi spi0.0: Chrome EC device registered
10628 12:12:47.446990 <6>[ 2.689922] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10629 12:12:47.450069 <6>[ 2.703308] mmcblk0: mmc0:0001 DA4128 116 GiB
10630 12:12:47.466021 <6>[ 2.714671] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10631 12:12:47.473223 <6>[ 2.715580] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10632 12:12:47.479687 <6>[ 2.726020] NET: Registered PF_PACKET protocol family
10633 12:12:47.482907 <6>[ 2.731178] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10634 12:12:47.489214 <6>[ 2.735302] 9pnet: Installing 9P2000 support
10635 12:12:47.492576 <6>[ 2.741136] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10636 12:12:47.499812 <5>[ 2.744982] Key type dns_resolver registered
10637 12:12:47.506326 <6>[ 2.750865] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10638 12:12:47.509621 <6>[ 2.755188] registered taskstats version 1
10639 12:12:47.512300 <5>[ 2.765599] Loading compiled-in X.509 certificates
10640 12:12:47.548431 <4>[ 2.793672] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10641 12:12:47.558456 <4>[ 2.804386] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10642 12:12:47.569086 <3>[ 2.817262] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10643 12:12:47.581125 <6>[ 2.832872] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10644 12:12:47.588153 <6>[ 2.839796] xhci-mtk 11200000.usb: xHCI Host Controller
10645 12:12:47.594587 <6>[ 2.845308] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10646 12:12:47.604879 <6>[ 2.853158] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10647 12:12:47.611470 <6>[ 2.862589] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10648 12:12:47.618126 <6>[ 2.868663] xhci-mtk 11200000.usb: xHCI Host Controller
10649 12:12:47.624778 <6>[ 2.874145] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10650 12:12:47.631197 <6>[ 2.881795] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10651 12:12:47.637829 <6>[ 2.889495] hub 1-0:1.0: USB hub found
10652 12:12:47.641214 <6>[ 2.893534] hub 1-0:1.0: 1 port detected
10653 12:12:47.651039 <6>[ 2.897874] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10654 12:12:47.654247 <6>[ 2.906506] hub 2-0:1.0: USB hub found
10655 12:12:47.657473 <6>[ 2.910531] hub 2-0:1.0: 1 port detected
10656 12:12:47.666241 <6>[ 2.917720] mtk-msdc 11f70000.mmc: Got CD GPIO
10657 12:12:47.683841 <6>[ 2.931966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10658 12:12:47.690515 <6>[ 2.940079] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10659 12:12:47.699962 <4>[ 2.948062] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10660 12:12:47.709783 <6>[ 2.957790] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10661 12:12:47.716413 <6>[ 2.965877] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10662 12:12:47.726358 <6>[ 2.973941] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10663 12:12:47.732927 <6>[ 2.981861] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10664 12:12:47.739695 <6>[ 2.989725] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10665 12:12:47.749592 <6>[ 2.997551] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10666 12:12:47.760005 <6>[ 3.008193] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10667 12:12:47.769571 <6>[ 3.016556] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10668 12:12:47.776438 <6>[ 3.024955] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10669 12:12:47.785915 <6>[ 3.033303] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10670 12:12:47.793184 <6>[ 3.041674] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10671 12:12:47.802741 <6>[ 3.050020] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10672 12:12:47.809362 <6>[ 3.058391] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10673 12:12:47.819118 <6>[ 3.066737] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10674 12:12:47.825670 <6>[ 3.075101] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10675 12:12:47.835579 <6>[ 3.083445] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10676 12:12:47.842171 <6>[ 3.091790] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10677 12:12:47.852157 <6>[ 3.100134] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10678 12:12:47.858697 <6>[ 3.108479] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10679 12:12:47.869039 <6>[ 3.116822] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10680 12:12:47.875213 <6>[ 3.125167] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10681 12:12:47.882399 <6>[ 3.134075] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10682 12:12:47.889938 <6>[ 3.141539] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10683 12:12:47.896970 <6>[ 3.148645] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10684 12:12:47.904096 <6>[ 3.155794] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10685 12:12:47.914857 <6>[ 3.163128] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10686 12:12:47.921510 <6>[ 3.170058] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10687 12:12:47.931476 <6>[ 3.179206] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10688 12:12:47.941498 <6>[ 3.188383] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10689 12:12:47.951140 <6>[ 3.197804] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10690 12:12:47.961176 <6>[ 3.207282] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10691 12:12:47.967601 <6>[ 3.216756] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10692 12:12:47.977199 <6>[ 3.225883] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10693 12:12:47.987194 <6>[ 3.235358] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10694 12:12:47.997198 <6>[ 3.244489] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10695 12:12:48.006943 <6>[ 3.253792] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10696 12:12:48.017248 <6>[ 3.263979] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10697 12:12:48.027142 <6>[ 3.275486] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10698 12:12:48.073886 <6>[ 3.322442] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10699 12:12:48.228416 <6>[ 3.479628] hub 1-1:1.0: USB hub found
10700 12:12:48.230912 <6>[ 3.483976] hub 1-1:1.0: 4 ports detected
10701 12:12:48.354268 <6>[ 3.602663] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10702 12:12:48.379159 <6>[ 3.630852] hub 2-1:1.0: USB hub found
10703 12:12:48.382544 <6>[ 3.635247] hub 2-1:1.0: 3 ports detected
10704 12:12:48.549902 <6>[ 3.798435] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10705 12:12:48.682709 <6>[ 3.934301] hub 1-1.4:1.0: USB hub found
10706 12:12:48.686092 <6>[ 3.938927] hub 1-1.4:1.0: 2 ports detected
10707 12:12:48.761989 <6>[ 4.010630] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10708 12:12:48.982028 <6>[ 4.230435] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10709 12:12:49.174069 <6>[ 4.422438] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10710 12:13:00.306731 <6>[ 15.562990] ALSA device list:
10711 12:13:00.313188 <6>[ 15.566247] No soundcards found.
10712 12:13:00.325449 <6>[ 15.578690] Freeing unused kernel memory: 8384K
10713 12:13:00.328706 <6>[ 15.583622] Run /init as init process
10714 12:13:00.359366 <6>[ 15.612542] NET: Registered PF_INET6 protocol family
10715 12:13:00.366144 <6>[ 15.619050] Segment Routing with IPv6
10716 12:13:00.369285 <6>[ 15.622998] In-situ OAM (IOAM) with IPv6
10717 12:13:00.404045 <30>[ 15.637556] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10718 12:13:00.407392 <30>[ 15.661552] systemd[1]: Detected architecture arm64.
10719 12:13:00.410587
10720 12:13:00.413860 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10721 12:13:00.413952
10722 12:13:00.429249 <30>[ 15.682532] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10723 12:13:00.577937 <30>[ 15.827837] systemd[1]: Queued start job for default target Graphical Interface.
10724 12:13:00.610820 <30>[ 15.863699] systemd[1]: Created slice system-getty.slice.
10725 12:13:00.617445 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10726 12:13:00.633623 <30>[ 15.887053] systemd[1]: Created slice system-modprobe.slice.
10727 12:13:00.640688 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10728 12:13:00.658338 <30>[ 15.911588] systemd[1]: Created slice system-serial\x2dgetty.slice.
10729 12:13:00.668938 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10730 12:13:00.681605 <30>[ 15.934910] systemd[1]: Created slice User and Session Slice.
10731 12:13:00.688289 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10732 12:13:00.708869 <30>[ 15.958663] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10733 12:13:00.718567 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10734 12:13:00.732754 <30>[ 15.982565] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10735 12:13:00.739189 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10736 12:13:00.759791 <30>[ 16.006510] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10737 12:13:00.766727 <30>[ 16.018528] systemd[1]: Reached target Local Encrypted Volumes.
10738 12:13:00.773249 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10739 12:13:00.789339 <30>[ 16.042797] systemd[1]: Reached target Paths.
10740 12:13:00.793038 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10741 12:13:00.809445 <30>[ 16.062419] systemd[1]: Reached target Remote File Systems.
10742 12:13:00.815964 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10743 12:13:00.829464 <30>[ 16.082419] systemd[1]: Reached target Slices.
10744 12:13:00.832619 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10745 12:13:00.849471 <30>[ 16.102502] systemd[1]: Reached target Swap.
10746 12:13:00.852650 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10747 12:13:00.872513 <30>[ 16.122717] systemd[1]: Listening on initctl Compatibility Named Pipe.
10748 12:13:00.879593 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10749 12:13:00.885834 <30>[ 16.137378] systemd[1]: Listening on Journal Audit Socket.
10750 12:13:00.892639 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10751 12:13:00.905432 <30>[ 16.158744] systemd[1]: Listening on Journal Socket (/dev/log).
10752 12:13:00.912222 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10753 12:13:00.929851 <30>[ 16.183224] systemd[1]: Listening on Journal Socket.
10754 12:13:00.936440 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10755 12:13:00.952579 <30>[ 16.202847] systemd[1]: Listening on Network Service Netlink Socket.
10756 12:13:00.959111 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10757 12:13:00.974001 <30>[ 16.227225] systemd[1]: Listening on udev Control Socket.
10758 12:13:00.980395 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10759 12:13:00.998177 <30>[ 16.251171] systemd[1]: Listening on udev Kernel Socket.
10760 12:13:01.004608 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10761 12:13:01.037472 <30>[ 16.290592] systemd[1]: Mounting Huge Pages File System...
10762 12:13:01.044086 Mounting [0;1;39mHuge Pages File System[0m...
10763 12:13:01.059473 <30>[ 16.312411] systemd[1]: Mounting POSIX Message Queue File System...
10764 12:13:01.065896 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10765 12:13:01.083296 <30>[ 16.336336] systemd[1]: Mounting Kernel Debug File System...
10766 12:13:01.089493 Mounting [0;1;39mKernel Debug File System[0m...
10767 12:13:01.108331 <30>[ 16.358643] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10768 12:13:01.119720 <30>[ 16.369386] systemd[1]: Starting Create list of static device nodes for the current kernel...
10769 12:13:01.126221 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10770 12:13:01.143406 <30>[ 16.396597] systemd[1]: Starting Load Kernel Module configfs...
10771 12:13:01.149723 Starting [0;1;39mLoad Kernel Module configfs[0m...
10772 12:13:01.167290 <30>[ 16.420561] systemd[1]: Starting Load Kernel Module drm...
10773 12:13:01.173705 Starting [0;1;39mLoad Kernel Module drm[0m...
10774 12:13:01.192774 <30>[ 16.442615] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10775 12:13:01.202767 <30>[ 16.456175] systemd[1]: Starting Journal Service...
10776 12:13:01.206051 Starting [0;1;39mJournal Service[0m...
10777 12:13:01.223329 <30>[ 16.476954] systemd[1]: Starting Load Kernel Modules...
10778 12:13:01.229861 Starting [0;1;39mLoad Kernel Modules[0m...
10779 12:13:01.251566 <30>[ 16.501218] systemd[1]: Starting Remount Root and Kernel File Systems...
10780 12:13:01.258046 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10781 12:13:01.271660 <30>[ 16.525040] systemd[1]: Starting Coldplug All udev Devices...
10782 12:13:01.278108 Starting [0;1;39mColdplug All udev Devices[0m...
10783 12:13:01.295899 <30>[ 16.549208] systemd[1]: Mounted Huge Pages File System.
10784 12:13:01.302572 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10785 12:13:01.318121 <30>[ 16.571013] systemd[1]: Started Journal Service.
10786 12:13:01.324440 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10787 12:13:01.338760 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10788 12:13:01.353998 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10789 12:13:01.373451 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10790 12:13:01.391002 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10791 12:13:01.407253 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10792 12:13:01.422352 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10793 12:13:01.442170 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10794 12:13:01.457305 See 'systemctl status systemd-remount-fs.service' for details.
10795 12:13:01.510106 Mounting [0;1;39mKernel Configuration File System[0m...
10796 12:13:01.532348 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10797 12:13:01.549206 <46>[ 16.799573] systemd-journald[182]: Received client request to flush runtime journal.
10798 12:13:01.557940 Starting [0;1;39mLoad/Save Random Seed[0m...
10799 12:13:01.576897 Starting [0;1;39mApply Kernel Variables[0m...
10800 12:13:01.592823 Starting [0;1;39mCreate System Users[0m...
10801 12:13:01.615025 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10802 12:13:01.637440 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10803 12:13:01.651012 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10804 12:13:01.666115 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10805 12:13:01.682679 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10806 12:13:01.698986 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10807 12:13:01.745839 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10808 12:13:01.768922 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10809 12:13:01.781562 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10810 12:13:01.797401 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10811 12:13:01.853653 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10812 12:13:01.876718 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10813 12:13:01.894410 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10814 12:13:01.914663 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10815 12:13:01.962836 Starting [0;1;39mNetwork Service[0m...
10816 12:13:01.983386 Starting [0;1;39mNetwork Time Synchronization[0m...
10817 12:13:02.002215 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10818 12:13:02.044420 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10819 12:13:02.062181 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10820 12:13:02.084016 Starting [0;1;39mNetwork Name Resolution[0m...
10821 12:13:02.119721 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10822 12:13:02.140023 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10823 12:13:02.161727 <6>[ 17.411807] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10824 12:13:02.178480 [[0;32m OK [<6>[ 17.429001] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10825 12:13:02.188106 0m] Created slic<6>[ 17.437689] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10826 12:13:02.197994 e [0;1;39msyste<6>[ 17.447647] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10827 12:13:02.204816 <6>[ 17.454356] remoteproc remoteproc0: scp is available
10828 12:13:02.211553 m-systemd\x2dbac<6>[ 17.458610] usbcore: registered new interface driver r8152
10829 12:13:02.218273 <6>[ 17.463771] remoteproc remoteproc0: powering up scp
10830 12:13:02.227972 klight.slice[0m<6>[ 17.475522] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10831 12:13:02.228063 .
10832 12:13:02.231164 <6>[ 17.485014] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10833 12:13:02.242009 [[0;32m OK [<4>[ 17.492680] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10834 12:13:02.251775 <3>[ 17.493661] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10835 12:13:02.258719 0m] Reached targ<3>[ 17.508940] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10836 12:13:02.268428 et [0;1;39mSyst<4>[ 17.509332] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10837 12:13:02.278180 em Time Set[0m.<3>[ 17.518338] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10838 12:13:02.278300
10839 12:13:02.292967 <3>[ 17.542907] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10840 12:13:02.299118 <3>[ 17.551071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10841 12:13:02.309281 <3>[ 17.559180] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10842 12:13:02.316077 <3>[ 17.559194] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 12:13:02.325565 <3>[ 17.559202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10844 12:13:02.332404 <6>[ 17.561643] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10845 12:13:02.342378 [[0;32m OK [0m] Reached targ<6>[ 17.592156] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10846 12:13:02.352052 et [0;1;39mSyst<6>[ 17.592284] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10847 12:13:02.358714 <3>[ 17.597732] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10848 12:13:02.368502 em Time Synchron<4>[ 17.601735] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10849 12:13:02.368620 ized[0m.
10850 12:13:02.375631 <6>[ 17.609283] pci_bus 0000:00: root bus resource [bus 00-ff]
10851 12:13:02.382102 <6>[ 17.609952] mc: Linux media interface: v0.10
10852 12:13:02.388656 <3>[ 17.611081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 12:13:02.395438 <3>[ 17.611101] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10854 12:13:02.405353 <3>[ 17.611109] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10855 12:13:02.412382 <6>[ 17.611959] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10856 12:13:02.418759 <6>[ 17.611964] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10857 12:13:02.425831 <6>[ 17.611967] remoteproc remoteproc0: remote processor scp is now up
10858 12:13:02.435592 <4>[ 17.617412] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10859 12:13:02.442105 <3>[ 17.621254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10860 12:13:02.452215 <3>[ 17.623443] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10861 12:13:02.458460 <3>[ 17.623462] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 12:13:02.468492 <3>[ 17.623471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10863 12:13:02.475724 <3>[ 17.623480] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10864 12:13:02.482343 <6>[ 17.627794] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10865 12:13:02.492425 <6>[ 17.627801] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10866 12:13:02.502315 <4>[ 17.632993] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10867 12:13:02.505598 <4>[ 17.632993] Fallback method does not support PEC.
10868 12:13:02.515918 <3>[ 17.637124] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 12:13:02.522445 <6>[ 17.639226] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10870 12:13:02.525817 <6>[ 17.645177] videodev: Linux video capture interface: v2.00
10871 12:13:02.535316 <6>[ 17.648630] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10872 12:13:02.545544 <6>[ 17.651748] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10873 12:13:02.552352 <6>[ 17.655417] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10874 12:13:02.562104 <6>[ 17.664628] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10875 12:13:02.572020 <3>[ 17.670278] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 12:13:02.575147 <6>[ 17.672371] pci 0000:00:00.0: supports D1 D2
10877 12:13:02.582355 <6>[ 17.696285] usbcore: registered new interface driver cdc_ether
10878 12:13:02.589462 <6>[ 17.701738] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10879 12:13:02.596477 <3>[ 17.730910] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 12:13:02.606055 <6>[ 17.743360] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10881 12:13:02.616280 <3>[ 17.751536] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10882 12:13:02.619603 <6>[ 17.752517] Bluetooth: Core ver 2.22
10883 12:13:02.623334 <6>[ 17.752608] NET: Registered PF_BLUETOOTH protocol family
10884 12:13:02.629801 <6>[ 17.752611] Bluetooth: HCI device and connection manager initialized
10885 12:13:02.636920 <6>[ 17.752629] Bluetooth: HCI socket layer initialized
10886 12:13:02.640122 <6>[ 17.752636] Bluetooth: L2CAP socket layer initialized
10887 12:13:02.646581 <6>[ 17.752648] Bluetooth: SCO socket layer initialized
10888 12:13:02.653245 <6>[ 17.765154] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10889 12:13:02.659822 <6>[ 17.765418] usbcore: registered new interface driver r8153_ecm
10890 12:13:02.662776 <6>[ 17.809882] r8152 2-1.3:1.0 eth0: v1.12.13
10891 12:13:02.669441 <6>[ 17.811926] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10892 12:13:02.679746 <3>[ 17.844583] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 12:13:02.686256 <6>[ 17.847211] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10894 12:13:02.693492 <6>[ 17.848992] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10895 12:13:02.703920 <4>[ 17.866801] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10896 12:13:02.711498 <6>[ 17.873312] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10897 12:13:02.718051 <3>[ 17.876953] Bluetooth: hci0: Failed to load firmware file (-2)
10898 12:13:02.725027 <6>[ 17.877941] usbcore: registered new interface driver btusb
10899 12:13:02.731508 <3>[ 17.880457] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 12:13:02.738043 <6>[ 17.882618] pci 0000:01:00.0: supports D1 D2
10901 12:13:02.744408 <3>[ 17.889092] Bluetooth: hci0: Failed to set up firmware (-2)
10902 12:13:02.751166 <6>[ 17.894219] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10903 12:13:02.760977 <4>[ 17.900131] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10904 12:13:02.768075 <6>[ 17.901759] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10905 12:13:02.778670 <6>[ 17.903369] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10906 12:13:02.785664 <6>[ 17.905684] usbcore: registered new interface driver uvcvideo
10907 12:13:02.791913 <6>[ 17.929295] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10908 12:13:02.798486 <6>[ 17.930282] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10909 12:13:02.804991 <6>[ 17.930305] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10910 12:13:02.814715 <6>[ 17.930327] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10911 12:13:02.821927 <6>[ 17.930336] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10912 12:13:02.831808 <6>[ 17.930351] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10913 12:13:02.838124 <6>[ 17.930367] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10914 12:13:02.848276 <6>[ 17.930383] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10915 12:13:02.851560 <6>[ 17.930400] pci 0000:00:00.0: PCI bridge to [bus 01]
10916 12:13:02.861318 <6>[ 17.930409] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10917 12:13:02.864938 <6>[ 17.930635] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10918 12:13:02.871223 <6>[ 17.931680] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10919 12:13:02.878120 <6>[ 17.931913] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10920 12:13:02.887994 <6>[ 17.932029] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10921 12:13:02.894593 <3>[ 17.959073] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10922 12:13:02.904604 <3>[ 17.972065] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 12:13:02.914229 <3>[ 18.048045] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 12:13:02.921255 <5>[ 18.057772] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10925 12:13:02.927830 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10926 12:13:02.942639 <5>[ 18.192539] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10927 12:13:02.949038 <4>[ 18.199486] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10928 12:13:02.955527 <6>[ 18.208420] cfg80211: failed to load regulatory.db
10929 12:13:02.962191 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10930 12:13:02.987455 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10931 12:13:02.997958 <3>[ 18.246103] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 12:13:03.004204 <3>[ 18.249206] power_supply sbs-5-000b: driver failed to report `energy_full' property: -6
10933 12:13:03.011294 <6>[ 18.253121] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10934 12:13:03.017755 <6>[ 18.253228] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10935 12:13:03.024858 <6>[ 18.273653] mt7921e 0000:01:00.0: ASIC revision: 79610010
10936 12:13:03.131598 <4>[ 18.378592] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10937 12:13:03.190651 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10938 12:13:03.205667 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10939 12:13:03.224864 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10940 12:13:03.238504 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10941 12:13:03.251912 <4>[ 18.497335] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10942 12:13:03.258497 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10943 12:13:03.276686 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10944 12:13:03.289654 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10945 12:13:03.309374 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10946 12:13:03.321269 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10947 12:13:03.337352 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10948 12:13:03.358242 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10949 12:13:03.371278 <4>[ 18.617527] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10950 12:13:03.409863 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10951 12:13:03.436178 Starting [0;1;39mUser Login Management[0m...
10952 12:13:03.451642 Starting [0;1;39mPermit User Sessions[0m...
10953 12:13:03.469443 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10954 12:13:03.481748 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10955 12:13:03.494703 <4>[ 18.739869] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10956 12:13:03.494827
10957 12:13:03.504863 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10958 12:13:03.554194 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10959 12:13:03.571908 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10960 12:13:03.589476 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10961 12:13:03.619988 [[0;32m OK [0m] Started [0;<4>[ 18.865653] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10962 12:13:03.623170 1;39mUser Login Management[0m.
10963 12:13:03.630178 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10964 12:13:03.638231 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10965 12:13:03.681847 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10966 12:13:03.706050 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10967 12:13:03.732693
10968 12:13:03.732822
10969 12:13:03.745920 Debian GNU/Linux 11 debian-bullseye-arm64 tty<4>[ 18.993007] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10970 12:13:03.746016 S0
10971 12:13:03.746107
10972 12:13:03.752677 debian-bullseye-arm64 login: root (automatic login)
10973 12:13:03.752769
10974 12:13:03.752853
10975 12:13:03.759520 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023 aarch64
10976 12:13:03.759606
10977 12:13:03.765921 The programs included with the Debian GNU/Linux system are free software;
10978 12:13:03.772338 the exact distribution terms for each program are described in the
10979 12:13:03.775476 individual files in /usr/share/doc/*/copyright.
10980 12:13:03.775585
10981 12:13:03.782023 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10982 12:13:03.785252 permitted by applicable law.
10983 12:13:03.785707 Matched prompt #10: / #
10985 12:13:03.786046 Setting prompt string to ['/ #']
10986 12:13:03.786176 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10988 12:13:03.786491 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10989 12:13:03.786614 start: 2.2.6 expect-shell-connection (timeout 00:03:06) [common]
10990 12:13:03.786689 Setting prompt string to ['/ #']
10991 12:13:03.786752 Forcing a shell prompt, looking for ['/ #']
10993 12:13:03.836956 / #
10994 12:13:03.837121 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10995 12:13:03.837218 Waiting using forced prompt support (timeout 00:02:30)
10996 12:13:03.841497
10997 12:13:03.841814 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10998 12:13:03.841949 start: 2.2.7 export-device-env (timeout 00:03:06) [common]
10999 12:13:03.842082 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11000 12:13:03.842208 end: 2.2 depthcharge-retry (duration 00:01:54) [common]
11001 12:13:03.842328 end: 2 depthcharge-action (duration 00:01:54) [common]
11002 12:13:03.842460 start: 3 lava-test-retry (timeout 00:07:45) [common]
11003 12:13:03.842578 start: 3.1 lava-test-shell (timeout 00:07:45) [common]
11004 12:13:03.842678 Using namespace: common
11006 12:13:03.942981 / # #
11007 12:13:03.943207 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11008 12:13:03.943385 <4>[ 19.116729] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11009 12:13:03.948501 #
11010 12:13:03.948817 Using /lava-10605394
11012 12:13:04.049188 / # export SHELL=/bin/sh
11013 12:13:04.049411 <4>[ 19.236765] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11014 12:13:04.054311 export SHELL=/bin/sh
11016 12:13:04.154785 / # . /lava-10605394/environment
11017 12:13:04.154988 <4>[ 19.356724] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11018 12:13:04.160143 . /lava-10605394/environment
11020 12:13:04.260634 / # /lava-10605394/bin/lava-test-runner /lava-10605394/0
11021 12:13:04.260857 Test shell timeout: 10s (minimum of the action and connection timeout)
11022 12:13:04.261406 /lava-10605394/bin/lava-test-runner /lav<4>[ 19.476101] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11023 12:13:04.261516 a-10605<6>[ 19.484247] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready
11024 12:13:04.261618 394/0<6>[ 19.496234] r8152 2-1.3:1.0 enx002432307852: carrier on
11025 12:13:04.266175
11026 12:13:04.307477 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11027 12:13:04.307608 + cd /lava-10605394/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11028 12:13:04.307698 + cat uuid
11029 12:13:04.307790 + UUID=10605394_1.5.2.3.1
11030 12:13:04.307868 + set +x
11031 12:13:04.307928 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 10605394_1.5.2.3.1>
11032 12:13:04.308164 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 10605394_1.5.2.3.1
11033 12:13:04.308236 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (10605394_1.5.2.3.1)
11034 12:13:04.308318 Skipping test definition patterns.
11035 12:13:04.309016 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11036 12:13:04.316013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11037 12:13:04.316267 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11039 12:13:04.322473 d<4>[ 19.572836] use of bytesused == 0 is deprecated and will be removed in the future,
11040 12:13:04.329506 evice: /dev/vide<4>[ 19.581640] use the actual size instead.
11041 12:13:04.329616 o2
11042 12:13:04.335952 <4>[ 19.588732] ------------[ cut here ]------------
11043 12:13:04.342207 <4>[ 19.593989] get_vaddr_frames() cannot follow VM_IO mapping
11044 12:13:04.355518 <4>[ 19.594862] WARNING: CPU: 1 PID: 318 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11045 12:13:04.358835 <3>[ 19.602951] mt7921e 0000:01:00.0: hardware init failed
11046 12:13:04.408427 <4>[ 19.613053] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 cros_ec_rpmsg mtk_vcodec_enc mtk_vcodec_common btusb uvcvideo mtk_vpu v4l2_mem2mem btintel videobuf2_vmalloc videobuf2_dma_contig btmtk videobuf2_memops btrtl btbcm r8153_ecm bluetooth videobuf2_v4l2 ecdh_generic cdc_ether videobuf2_common ecc videodev rfkill crct10dif_ce mc cros_ec_chardev usbnet elan_i2c elants_i2c sbs_battery cros_ec_typec r8152 hid_google_hammer hid_vivaldi_common pcie_mediatek_gen3 mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11047 12:13:04.415170 <4>[ 19.667825] CPU: 1 PID: 318 Comm: v4l2-compliance Not tainted 6.1.31 #1
11048 12:13:04.421478 <4>[ 19.674689] Hardware name: Google Spherion (rev0 - 3) (DT)
11049 12:13:04.428002 <4>[ 19.680424] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11050 12:13:04.435155 <4>[ 19.687635] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11051 12:13:04.441161 <4>[ 19.693726] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11052 12:13:04.444971 <4>[ 19.699816] sp : ffff8000091c3850
11053 12:13:04.451702 <4>[ 19.703380] x29: ffff8000091c3850 x28: ffffcf3a37e17000 x27: ffffcf3a37e13238
11054 12:13:04.458108 <4>[ 19.710767] x26: 0000000000000000 x25: ffffcf3aa5cdb3b8 x24: ffff768a4ea41298
11055 12:13:04.467987 <4>[ 19.718154] x23: ffff768a4bf44800 x22: ffff768a40d48010 x21: 0000000000000000
11056 12:13:04.474368 <4>[ 19.725541] x20: 00000000fffffff2 x19: ffff768a4bf20880 x18: fffffffffffe9578
11057 12:13:04.480946 <4>[ 19.732928] x17: 0000000000000000 x16: ffffcf3aa3e8bb60 x15: 0000000000000038
11058 12:13:04.488012 <4>[ 19.740316] x14: 0000000000000256 x13: 0000000000000000 x12: 0000000000000000
11059 12:13:04.497980 <4>[ 19.747702] x11: 0000000000000000 x10: 0000000000000a60 x9 : ffff8000091c3700
11060 12:13:04.504296 <4>[ 19.755089] x8 : ffff768a4942b700 x7 : ffff768b7ef2ee40 x6 : ffff768a40815400
11061 12:13:04.510841 <4>[ 19.762476] x5 : 00000000410fd050 x4 : 0000000000c0000e x3 : 0000000000200000
11062 12:13:04.517464 <4>[ 19.769862] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff768a4942ac40
11063 12:13:04.520988 <4>[ 19.777249] Call trace:
11064 12:13:04.527683 <4>[ 19.779946] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11065 12:13:04.534325 <4>[ 19.785690] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11066 12:13:04.540639 <4>[ 19.791691] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11067 12:13:04.543889 <4>[ 19.798042] __prepare_userptr+0x280/0x410 [videobuf2_common]
11068 12:13:04.550969 <4>[ 19.804046] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11069 12:13:04.557099 <4>[ 19.809703] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11070 12:13:04.563545 <4>[ 19.815880] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11071 12:13:04.567491 <4>[ 19.821381] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11072 12:13:04.574042 <4>[ 19.827154] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11073 12:13:04.580428 <4>[ 19.833419] v4l_prepare_buf+0x48/0x60 [videodev]
11074 12:13:04.583733 <4>[ 19.838443] __video_do_ioctl+0x184/0x3d0 [videodev]
11075 12:13:04.590088 <4>[ 19.843687] video_usercopy+0x358/0x680 [videodev]
11076 12:13:04.593263 <4>[ 19.848758] video_ioctl2+0x18/0x30 [videodev]
11077 12:13:04.600403 <4>[ 19.853480] v4l2_ioctl+0x40/0x60 [videodev]
11078 12:13:04.603631 <4>[ 19.858030] __arm64_sys_ioctl+0xa8/0xf0
11079 12:13:04.606854 <4>[ 19.862211] invoke_syscall+0x48/0x114
11080 12:13:04.613231 <4>[ 19.866221] el0_svc_common.constprop.0+0x44/0xec
11081 12:13:04.616404 <4>[ 19.871177] do_el0_svc+0x2c/0xd0
11082 12:13:04.619892 <4>[ 19.874743] el0_svc+0x2c/0x84
11083 12:13:04.623464 <4>[ 19.878055] el0t_64_sync_handler+0xb8/0xc0
11084 12:13:04.626380 <4>[ 19.882488] el0t_64_sync+0x18c/0x190
11085 12:13:04.632882 <4>[ 19.886402] ---[ end trace 0000000000000000 ]---
11086 12:13:04.646084 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11087 12:13:04.656376 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11088 12:13:04.663099
11089 12:13:04.676662 Compliance test for mtk-vcodec-enc device /dev/video2:
11090 12:13:04.683070
11091 12:13:04.693415 Driver Info:
11092 12:13:04.703642 Driver name : mtk-vcodec-enc
11093 12:13:04.718003 Card type : MT8192 video encoder
11094 12:13:04.728414 Bus info : platform:17020000.vcodec
11095 12:13:04.734952 Driver version : 6.1.31
11096 12:13:04.745898 Capabilities : 0x84204000
11097 12:13:04.755643 Video Memory-to-Memory Multiplanar
11098 12:13:04.766934 Streaming
11099 12:13:04.777831 Extended Pix Format
11100 12:13:04.788204 Device Capabilities
11101 12:13:04.799050 Device Caps : 0x04204000
11102 12:13:04.808067 Video Memory-to-Memory Multiplanar
11103 12:13:04.817901 Streaming
11104 12:13:04.828432 Extended Pix Format
11105 12:13:04.838509 Detected Stateful Encoder
11106 12:13:04.849442
11107 12:13:04.860630 Required ioctls:
11108 12:13:04.875322 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11109 12:13:04.875462 test VIDIOC_QUERYCAP: OK
11110 12:13:04.875728 Received signal: <TESTSET> START Required-ioctls
11111 12:13:04.875803 Starting test_set Required-ioctls
11112 12:13:04.898760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11113 12:13:04.899029 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11115 12:13:04.902052 test invalid ioctls: OK
11116 12:13:04.922981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11117 12:13:04.923073
11118 12:13:04.923306 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11120 12:13:04.933672 Allow for multiple opens:
11121 12:13:04.940008 <LAVA_SIGNAL_TESTSET STOP>
11122 12:13:04.940261 Received signal: <TESTSET> STOP
11123 12:13:04.940337 Closing test_set Required-ioctls
11124 12:13:04.949301 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11125 12:13:04.949553 Received signal: <TESTSET> START Allow-for-multiple-opens
11126 12:13:04.949623 Starting test_set Allow-for-multiple-opens
11127 12:13:04.953031 test second /dev/video2 open: OK
11128 12:13:04.973516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11129 12:13:04.973768 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11131 12:13:04.976529 test VIDIOC_QUERYCAP: OK
11132 12:13:04.997851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11133 12:13:04.998105 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11135 12:13:05.001105 test VIDIOC_G/S_PRIORITY: OK
11136 12:13:05.021766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11137 12:13:05.022024 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11139 12:13:05.025099 test for unlimited opens: OK
11140 12:13:05.043994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11141 12:13:05.044080
11142 12:13:05.044313 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11144 12:13:05.054201 Debug ioctls:
11145 12:13:05.060124 <LAVA_SIGNAL_TESTSET STOP>
11146 12:13:05.060375 Received signal: <TESTSET> STOP
11147 12:13:05.060444 Closing test_set Allow-for-multiple-opens
11148 12:13:05.068224 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11149 12:13:05.068476 Received signal: <TESTSET> START Debug-ioctls
11150 12:13:05.068548 Starting test_set Debug-ioctls
11151 12:13:05.071306 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11152 12:13:05.094254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11153 12:13:05.094510 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11155 12:13:05.100732 test VIDIOC_LOG_STATUS: OK (Not Supported)
11156 12:13:05.117123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11157 12:13:05.117212
11158 12:13:05.117446 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11160 12:13:05.127377 Input ioctls:
11161 12:13:05.133798 <LAVA_SIGNAL_TESTSET STOP>
11162 12:13:05.134048 Received signal: <TESTSET> STOP
11163 12:13:05.134117 Closing test_set Debug-ioctls
11164 12:13:05.142743 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11165 12:13:05.142995 Received signal: <TESTSET> START Input-ioctls
11166 12:13:05.143064 Starting test_set Input-ioctls
11167 12:13:05.145973 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11168 12:13:05.170781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11169 12:13:05.171035 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11171 12:13:05.173793 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11172 12:13:05.190944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11173 12:13:05.191199 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11175 12:13:05.197246 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11176 12:13:05.214727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11177 12:13:05.215035 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11179 12:13:05.221153 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11180 12:13:05.238546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11181 12:13:05.238796 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11183 12:13:05.241723 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11184 12:13:05.263422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11185 12:13:05.263675 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11187 12:13:05.266082 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11188 12:13:05.287289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11189 12:13:05.287563 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11191 12:13:05.290544 Inputs: 0 Audio Inputs: 0 Tuners: 0
11192 12:13:05.297877
11193 12:13:05.319228 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11194 12:13:05.342680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11195 12:13:05.342951 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11197 12:13:05.349087 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11198 12:13:05.366636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11199 12:13:05.366889 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11201 12:13:05.373541 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11202 12:13:05.391027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11203 12:13:05.391279 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11205 12:13:05.397607 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11206 12:13:05.415477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11207 12:13:05.415770 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11209 12:13:05.421493 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11210 12:13:05.440426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11211 12:13:05.440535
11212 12:13:05.440819 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11214 12:13:05.459542 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11215 12:13:05.480693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11216 12:13:05.480982 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11218 12:13:05.487115 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11219 12:13:05.508576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11220 12:13:05.508858 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11222 12:13:05.512222 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11223 12:13:05.530653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11224 12:13:05.530955 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11226 12:13:05.533910 test VIDIOC_G/S_EDID: OK (Not Supported)
11227 12:13:05.555641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11228 12:13:05.555724
11229 12:13:05.555966 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11231 12:13:05.570092 Control ioctls:
11232 12:13:05.577834 <LAVA_SIGNAL_TESTSET STOP>
11233 12:13:05.578080 Received signal: <TESTSET> STOP
11234 12:13:05.578172 Closing test_set Input-ioctls
11235 12:13:05.588248 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11236 12:13:05.588502 Received signal: <TESTSET> START Control-ioctls
11237 12:13:05.588612 Starting test_set Control-ioctls
11238 12:13:05.591427 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11239 12:13:05.619666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11240 12:13:05.619765 test VIDIOC_QUERYCTRL: OK
11241 12:13:05.620011 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11243 12:13:05.640877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11244 12:13:05.641163 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11246 12:13:05.643957 test VIDIOC_G/S_CTRL: OK
11247 12:13:05.663447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11248 12:13:05.663702 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11250 12:13:05.666600 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11251 12:13:05.689502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11252 12:13:05.689756 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11254 12:13:05.699038 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11255 12:13:05.702290 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11256 12:13:05.726555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11257 12:13:05.726858 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11259 12:13:05.730308 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11260 12:13:05.747095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11261 12:13:05.747412 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11263 12:13:05.750250 Standard Controls: 16 Private Controls: 0
11264 12:13:05.757332
11265 12:13:05.768356 Format ioctls:
11266 12:13:05.774628 <LAVA_SIGNAL_TESTSET STOP>
11267 12:13:05.774917 Received signal: <TESTSET> STOP
11268 12:13:05.775018 Closing test_set Control-ioctls
11269 12:13:05.783603 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11270 12:13:05.783890 Received signal: <TESTSET> START Format-ioctls
11271 12:13:05.783995 Starting test_set Format-ioctls
11272 12:13:05.786774 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11273 12:13:05.809424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11274 12:13:05.809703 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11276 12:13:05.812630 test VIDIOC_G/S_PARM: OK
11277 12:13:05.827509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11278 12:13:05.827766 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11280 12:13:05.831101 test VIDIOC_G_FBUF: OK (Not Supported)
11281 12:13:05.851198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11282 12:13:05.851456 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11284 12:13:05.854474 test VIDIOC_G_FMT: OK
11285 12:13:05.875111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11286 12:13:05.875386 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11288 12:13:05.878363 test VIDIOC_TRY_FMT: OK
11289 12:13:05.898795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11290 12:13:05.899051 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11292 12:13:05.908680 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11293 12:13:05.908797 test VIDIOC_S_FMT: FAIL
11294 12:13:05.931457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11295 12:13:05.931774 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11297 12:13:05.934456 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11298 12:13:05.956143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11299 12:13:05.956411 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11301 12:13:05.959299 test Cropping: OK
11302 12:13:05.979187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11303 12:13:05.979479 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11305 12:13:05.982416 test Composing: OK (Not Supported)
11306 12:13:06.003212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11307 12:13:06.003501 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11309 12:13:06.006424 test Scaling: OK (Not Supported)
11310 12:13:06.027712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11311 12:13:06.027838
11312 12:13:06.028107 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11314 12:13:06.037589 Codec ioctls:
11315 12:13:06.044407 <LAVA_SIGNAL_TESTSET STOP>
11316 12:13:06.044684 Received signal: <TESTSET> STOP
11317 12:13:06.044785 Closing test_set Format-ioctls
11318 12:13:06.054041 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11319 12:13:06.054324 Received signal: <TESTSET> START Codec-ioctls
11320 12:13:06.054423 Starting test_set Codec-ioctls
11321 12:13:06.057067 test VIDIOC_(TRY_)ENCODER_CMD: OK
11322 12:13:06.077303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11323 12:13:06.077591 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11325 12:13:06.083692 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11326 12:13:06.102098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11327 12:13:06.102386 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11329 12:13:06.108351 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11330 12:13:06.125975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11331 12:13:06.126071
11332 12:13:06.126308 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11334 12:13:06.136129 Buffer ioctls:
11335 12:13:06.143065 <LAVA_SIGNAL_TESTSET STOP>
11336 12:13:06.143320 Received signal: <TESTSET> STOP
11337 12:13:06.143397 Closing test_set Codec-ioctls
11338 12:13:06.151781 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11339 12:13:06.152036 Received signal: <TESTSET> START Buffer-ioctls
11340 12:13:06.152106 Starting test_set Buffer-ioctls
11341 12:13:06.154981 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11342 12:13:06.179233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11343 12:13:06.179326 test VIDIOC_EXPBUF: OK
11344 12:13:06.179570 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11346 12:13:06.200111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11347 12:13:06.200368 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11349 12:13:06.203386 test Requests: OK (Not Supported)
11350 12:13:06.225222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11351 12:13:06.225315
11352 12:13:06.225549 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11354 12:13:06.236188 Test input 0:
11355 12:13:06.245487
11356 12:13:06.256242 Streaming ioctls:
11357 12:13:06.263521 <LAVA_SIGNAL_TESTSET STOP>
11358 12:13:06.263776 Received signal: <TESTSET> STOP
11359 12:13:06.263848 Closing test_set Buffer-ioctls
11360 12:13:06.272642 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11361 12:13:06.272899 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11362 12:13:06.273057 Starting test_set Streaming-ioctls_Test-input-0
11363 12:13:06.276267 test read/write: OK (Not Supported)
11364 12:13:06.296220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11365 12:13:06.296492 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11367 12:13:06.302998 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2778): node->streamon(q.g_type())
11368 12:13:06.313656 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2825): testBlockingDQBuf(node, q)
11369 12:13:06.317593 test blocking wait: FAIL
11370 12:13:06.342955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11371 12:13:06.343215 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11373 12:13:06.353033 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11374 12:13:06.353119 test MMAP (select): FAIL
11375 12:13:06.378700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11376 12:13:06.378959 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11378 12:13:06.385407 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11379 12:13:06.388704 test MMAP (epoll): FAIL
11380 12:13:06.414041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11381 12:13:06.414308 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11383 12:13:06.423814 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11384 12:13:06.430271 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11385 12:13:06.434874 test USERPTR (select): FAIL
11386 12:13:06.458733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11387 12:13:06.458988 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11389 12:13:06.465289 test DMABUF: Cannot test, specify --expbuf-device
11390 12:13:06.468508
11391 12:13:06.486052 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11392 12:13:06.488977 <LAVA_TEST_RUNNER EXIT>
11393 12:13:06.489244 ok: lava_test_shell seems to have completed
11394 12:13:06.489353 Marking unfinished test run as failed
11396 12:13:06.490514 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11397 12:13:06.490637 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11398 12:13:06.490730 end: 3 lava-test-retry (duration 00:00:03) [common]
11399 12:13:06.490856 start: 4 finalize (timeout 00:07:43) [common]
11400 12:13:06.490947 start: 4.1 power-off (timeout 00:00:30) [common]
11401 12:13:06.491106 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11402 12:13:06.568678 >> Command sent successfully.
11403 12:13:06.570985 Returned 0 in 0 seconds
11404 12:13:06.671366 end: 4.1 power-off (duration 00:00:00) [common]
11406 12:13:06.671743 start: 4.2 read-feedback (timeout 00:07:43) [common]
11407 12:13:06.672018 Listened to connection for namespace 'common' for up to 1s
11408 12:13:07.672957 Finalising connection for namespace 'common'
11409 12:13:07.673194 Disconnecting from shell: Finalise
11410 12:13:07.673339 / #
11411 12:13:07.773695 end: 4.2 read-feedback (duration 00:00:01) [common]
11412 12:13:07.773890 end: 4 finalize (duration 00:00:01) [common]
11413 12:13:07.774024 Cleaning after the job
11414 12:13:07.774131 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/ramdisk
11415 12:13:07.778609 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/kernel
11416 12:13:07.784798 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/dtb
11417 12:13:07.784987 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605394/tftp-deploy-aoyxsptu/modules
11418 12:13:07.790584 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605394
11419 12:13:07.846723 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605394
11420 12:13:07.846911 Job finished correctly