Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 67
1 12:13:41.782391 lava-dispatcher, installed at version: 2023.05.1
2 12:13:41.782582 start: 0 validate
3 12:13:41.782713 Start time: 2023-06-06 12:13:41.782706+00:00 (UTC)
4 12:13:41.782831 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:13:41.782959 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:13:42.088432 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:13:42.088677 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:13:42.385317 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:13:42.385498 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:13:42.679920 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:13:42.680108 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:13:42.974373 validate duration: 1.19
14 12:13:42.974742 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:13:42.974907 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:13:42.975041 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:13:42.975237 Not decompressing ramdisk as can be used compressed.
18 12:13:42.975359 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 12:13:42.975483 saving as /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/ramdisk/rootfs.cpio.gz
20 12:13:42.975576 total size: 27151647 (25MB)
21 12:13:42.979365 progress 0% (0MB)
22 12:13:42.990892 progress 5% (1MB)
23 12:13:43.002898 progress 10% (2MB)
24 12:13:43.015275 progress 15% (3MB)
25 12:13:43.026915 progress 20% (5MB)
26 12:13:43.040177 progress 25% (6MB)
27 12:13:43.053576 progress 30% (7MB)
28 12:13:43.067896 progress 35% (9MB)
29 12:13:43.081294 progress 40% (10MB)
30 12:13:43.095083 progress 45% (11MB)
31 12:13:43.107897 progress 50% (12MB)
32 12:13:43.123363 progress 55% (14MB)
33 12:13:43.136114 progress 60% (15MB)
34 12:13:43.150018 progress 65% (16MB)
35 12:13:43.165870 progress 70% (18MB)
36 12:13:43.180351 progress 75% (19MB)
37 12:13:43.197925 progress 80% (20MB)
38 12:13:43.217691 progress 85% (22MB)
39 12:13:43.231575 progress 90% (23MB)
40 12:13:43.246356 progress 95% (24MB)
41 12:13:43.259298 progress 100% (25MB)
42 12:13:43.259539 25MB downloaded in 0.28s (91.19MB/s)
43 12:13:43.259717 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:13:43.259999 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:13:43.260101 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:13:43.260209 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:13:43.260357 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:13:43.260435 saving as /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/kernel/Image
50 12:13:43.260498 total size: 45746688 (43MB)
51 12:13:43.260574 No compression specified
52 12:13:43.261792 progress 0% (0MB)
53 12:13:43.274463 progress 5% (2MB)
54 12:13:43.287223 progress 10% (4MB)
55 12:13:43.299984 progress 15% (6MB)
56 12:13:43.312490 progress 20% (8MB)
57 12:13:43.324720 progress 25% (10MB)
58 12:13:43.336761 progress 30% (13MB)
59 12:13:43.349128 progress 35% (15MB)
60 12:13:43.361314 progress 40% (17MB)
61 12:13:43.373647 progress 45% (19MB)
62 12:13:43.385966 progress 50% (21MB)
63 12:13:43.398025 progress 55% (24MB)
64 12:13:43.410303 progress 60% (26MB)
65 12:13:43.422495 progress 65% (28MB)
66 12:13:43.435070 progress 70% (30MB)
67 12:13:43.447539 progress 75% (32MB)
68 12:13:43.459641 progress 80% (34MB)
69 12:13:43.473160 progress 85% (37MB)
70 12:13:43.485479 progress 90% (39MB)
71 12:13:43.498257 progress 95% (41MB)
72 12:13:43.510747 progress 100% (43MB)
73 12:13:43.510892 43MB downloaded in 0.25s (174.24MB/s)
74 12:13:43.511040 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:13:43.511300 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:13:43.511446 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:13:43.511548 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:13:43.511702 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:13:43.511777 saving as /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/dtb/mt8192-asurada-spherion-r0.dtb
81 12:13:43.511890 total size: 46924 (0MB)
82 12:13:43.511987 No compression specified
83 12:13:43.513216 progress 69% (0MB)
84 12:13:43.513500 progress 100% (0MB)
85 12:13:43.513667 0MB downloaded in 0.00s (25.21MB/s)
86 12:13:43.513798 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:13:43.514047 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:13:43.514144 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:13:43.514229 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:13:43.514358 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:13:43.514429 saving as /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/modules/modules.tar
93 12:13:43.514497 total size: 8553528 (8MB)
94 12:13:43.514565 Using unxz to decompress xz
95 12:13:43.517896 progress 0% (0MB)
96 12:13:43.539560 progress 5% (0MB)
97 12:13:43.564013 progress 10% (0MB)
98 12:13:43.595764 progress 15% (1MB)
99 12:13:43.622481 progress 20% (1MB)
100 12:13:43.648163 progress 25% (2MB)
101 12:13:43.673428 progress 30% (2MB)
102 12:13:43.700343 progress 35% (2MB)
103 12:13:43.727381 progress 40% (3MB)
104 12:13:43.753999 progress 45% (3MB)
105 12:13:43.780139 progress 50% (4MB)
106 12:13:43.805238 progress 55% (4MB)
107 12:13:43.830191 progress 60% (4MB)
108 12:13:43.855285 progress 65% (5MB)
109 12:13:43.880504 progress 70% (5MB)
110 12:13:43.909259 progress 75% (6MB)
111 12:13:43.937357 progress 80% (6MB)
112 12:13:43.963836 progress 85% (6MB)
113 12:13:43.988941 progress 90% (7MB)
114 12:13:44.012498 progress 95% (7MB)
115 12:13:44.039286 progress 100% (8MB)
116 12:13:44.044292 8MB downloaded in 0.53s (15.40MB/s)
117 12:13:44.044617 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:13:44.044942 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:13:44.045035 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:13:44.045175 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:13:44.045301 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:13:44.045403 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:13:44.045678 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_
125 12:13:44.045806 makedir: /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin
126 12:13:44.045921 makedir: /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/tests
127 12:13:44.046017 makedir: /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/results
128 12:13:44.046131 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-add-keys
129 12:13:44.046368 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-add-sources
130 12:13:44.046512 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-background-process-start
131 12:13:44.046644 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-background-process-stop
132 12:13:44.046771 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-common-functions
133 12:13:44.046916 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-echo-ipv4
134 12:13:44.047074 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-install-packages
135 12:13:44.047219 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-installed-packages
136 12:13:44.047374 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-os-build
137 12:13:44.047495 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-probe-channel
138 12:13:44.047680 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-probe-ip
139 12:13:44.047802 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-target-ip
140 12:13:44.047922 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-target-mac
141 12:13:44.048077 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-target-storage
142 12:13:44.048201 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-test-case
143 12:13:44.048353 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-test-event
144 12:13:44.048471 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-test-feedback
145 12:13:44.048609 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-test-raise
146 12:13:44.048734 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-test-reference
147 12:13:44.048879 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-test-runner
148 12:13:44.049049 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-test-set
149 12:13:44.049217 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-test-shell
150 12:13:44.049339 Updating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-install-packages (oe)
151 12:13:44.049488 Updating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/bin/lava-installed-packages (oe)
152 12:13:44.049612 Creating /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/environment
153 12:13:44.049712 LAVA metadata
154 12:13:44.049785 - LAVA_JOB_ID=10605413
155 12:13:44.049849 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:13:44.049950 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:13:44.050016 skipped lava-vland-overlay
158 12:13:44.050092 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:13:44.050171 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:13:44.050233 skipped lava-multinode-overlay
161 12:13:44.050322 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:13:44.050451 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:13:44.050525 Loading test definitions
164 12:13:44.050617 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:13:44.050689 Using /lava-10605413 at stage 0
166 12:13:44.050979 uuid=10605413_1.5.2.3.1 testdef=None
167 12:13:44.051066 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:13:44.051150 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:13:44.051644 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:13:44.051931 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:13:44.052662 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:13:44.053010 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:13:44.053775 runner path: /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/0/tests/0_v4l2-compliance-uvc test_uuid 10605413_1.5.2.3.1
176 12:13:44.053929 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:13:44.054137 Creating lava-test-runner.conf files
179 12:13:44.054201 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605413/lava-overlay-zkgyi_6_/lava-10605413/0 for stage 0
180 12:13:44.054291 - 0_v4l2-compliance-uvc
181 12:13:44.054390 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:13:44.054475 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:13:44.061387 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:13:44.061491 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:13:44.061577 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:13:44.061662 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:13:44.061753 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:13:44.769535 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:13:44.769890 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:13:44.770003 extracting modules file /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605413/extract-overlay-ramdisk-lgsnx39s/ramdisk
191 12:13:44.980162 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:13:44.980339 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:13:44.980435 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605413/compress-overlay-kc9v6633/overlay-1.5.2.4.tar.gz to ramdisk
194 12:13:44.980511 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605413/compress-overlay-kc9v6633/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605413/extract-overlay-ramdisk-lgsnx39s/ramdisk
195 12:13:44.986943 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:13:44.987058 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:13:44.987150 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:13:44.987241 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:13:44.987322 Building ramdisk /var/lib/lava/dispatcher/tmp/10605413/extract-overlay-ramdisk-lgsnx39s/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605413/extract-overlay-ramdisk-lgsnx39s/ramdisk
200 12:13:45.521419 >> 230342 blocks
201 12:13:49.752674 rename /var/lib/lava/dispatcher/tmp/10605413/extract-overlay-ramdisk-lgsnx39s/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/ramdisk/ramdisk.cpio.gz
202 12:13:49.753169 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:13:49.753298 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 12:13:49.753422 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 12:13:49.753542 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/kernel/Image'
206 12:14:02.321132 Returned 0 in 12 seconds
207 12:14:02.421709 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/kernel/image.itb
208 12:14:02.966693 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:14:02.967047 output: Created: Tue Jun 6 13:14:02 2023
210 12:14:02.967127 output: Image 0 (kernel-1)
211 12:14:02.967192 output: Description:
212 12:14:02.967255 output: Created: Tue Jun 6 13:14:02 2023
213 12:14:02.967316 output: Type: Kernel Image
214 12:14:02.967375 output: Compression: lzma compressed
215 12:14:02.967432 output: Data Size: 10094623 Bytes = 9858.03 KiB = 9.63 MiB
216 12:14:02.967489 output: Architecture: AArch64
217 12:14:02.967546 output: OS: Linux
218 12:14:02.967607 output: Load Address: 0x00000000
219 12:14:02.967665 output: Entry Point: 0x00000000
220 12:14:02.967723 output: Hash algo: crc32
221 12:14:02.967777 output: Hash value: fd97082e
222 12:14:02.967830 output: Image 1 (fdt-1)
223 12:14:02.967884 output: Description: mt8192-asurada-spherion-r0
224 12:14:02.967942 output: Created: Tue Jun 6 13:14:02 2023
225 12:14:02.967995 output: Type: Flat Device Tree
226 12:14:02.968048 output: Compression: uncompressed
227 12:14:02.968102 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:14:02.968155 output: Architecture: AArch64
229 12:14:02.968207 output: Hash algo: crc32
230 12:14:02.968263 output: Hash value: 1df858fa
231 12:14:02.968316 output: Image 2 (ramdisk-1)
232 12:14:02.968370 output: Description: unavailable
233 12:14:02.968431 output: Created: Tue Jun 6 13:14:02 2023
234 12:14:02.968487 output: Type: RAMDisk Image
235 12:14:02.968540 output: Compression: Unknown Compression
236 12:14:02.968592 output: Data Size: 40138410 Bytes = 39197.67 KiB = 38.28 MiB
237 12:14:02.968646 output: Architecture: AArch64
238 12:14:02.968698 output: OS: Linux
239 12:14:02.968751 output: Load Address: unavailable
240 12:14:02.968851 output: Entry Point: unavailable
241 12:14:02.968904 output: Hash algo: crc32
242 12:14:02.968956 output: Hash value: 911e0857
243 12:14:02.969010 output: Default Configuration: 'conf-1'
244 12:14:02.969062 output: Configuration 0 (conf-1)
245 12:14:02.969114 output: Description: mt8192-asurada-spherion-r0
246 12:14:02.969166 output: Kernel: kernel-1
247 12:14:02.969218 output: Init Ramdisk: ramdisk-1
248 12:14:02.969270 output: FDT: fdt-1
249 12:14:02.969322 output: Loadables: kernel-1
250 12:14:02.969374 output:
251 12:14:02.969578 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 12:14:02.969679 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 12:14:02.969786 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 12:14:02.969879 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 12:14:02.969960 No LXC device requested
256 12:14:02.970038 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:14:02.970125 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 12:14:02.970203 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:14:02.970276 Checking files for TFTP limit of 4294967296 bytes.
260 12:14:02.970756 end: 1 tftp-deploy (duration 00:00:20) [common]
261 12:14:02.970858 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:14:02.970954 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:14:02.971073 substitutions:
264 12:14:02.971141 - {DTB}: 10605413/tftp-deploy-wfkue_y5/dtb/mt8192-asurada-spherion-r0.dtb
265 12:14:02.971203 - {INITRD}: 10605413/tftp-deploy-wfkue_y5/ramdisk/ramdisk.cpio.gz
266 12:14:02.971261 - {KERNEL}: 10605413/tftp-deploy-wfkue_y5/kernel/Image
267 12:14:02.971318 - {LAVA_MAC}: None
268 12:14:02.971373 - {PRESEED_CONFIG}: None
269 12:14:02.971431 - {PRESEED_LOCAL}: None
270 12:14:02.971498 - {RAMDISK}: 10605413/tftp-deploy-wfkue_y5/ramdisk/ramdisk.cpio.gz
271 12:14:02.971554 - {ROOT_PART}: None
272 12:14:02.971608 - {ROOT}: None
273 12:14:02.971660 - {SERVER_IP}: 192.168.201.1
274 12:14:02.971716 - {TEE}: None
275 12:14:02.971768 Parsed boot commands:
276 12:14:02.971821 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:14:02.971989 Parsed boot commands: tftpboot 192.168.201.1 10605413/tftp-deploy-wfkue_y5/kernel/image.itb 10605413/tftp-deploy-wfkue_y5/kernel/cmdline
278 12:14:02.972078 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:14:02.972163 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:14:02.972255 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:14:02.972341 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:14:02.972408 Not connected, no need to disconnect.
283 12:14:02.972480 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:14:02.972557 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:14:02.972622 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
286 12:14:02.975898 Setting prompt string to ['lava-test: # ']
287 12:14:02.976262 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:14:02.976401 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:14:02.976531 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:14:02.976696 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:14:02.976947 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 12:14:08.111333 >> Command sent successfully.
293 12:14:08.114033 Returned 0 in 5 seconds
294 12:14:08.214396 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:14:08.214960 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:14:08.215062 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:14:08.215154 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:14:08.215223 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:14:08.215295 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:14:08.215565 [Enter `^Ec?' for help]
302 12:14:08.390003
303 12:14:08.390162
304 12:14:08.390235 F0: 102B 0000
305 12:14:08.390301
306 12:14:08.390361 F3: 1001 0000 [0200]
307 12:14:08.390427
308 12:14:08.393616 F3: 1001 0000
309 12:14:08.393706
310 12:14:08.393772 F7: 102D 0000
311 12:14:08.393837
312 12:14:08.393903 F1: 0000 0000
313 12:14:08.393964
314 12:14:08.397248 V0: 0000 0000 [0001]
315 12:14:08.397318
316 12:14:08.397376 00: 0007 8000
317 12:14:08.397438
318 12:14:08.400771 01: 0000 0000
319 12:14:08.400859
320 12:14:08.400948 BP: 0C00 0209 [0000]
321 12:14:08.401040
322 12:14:08.404424 G0: 1182 0000
323 12:14:08.404518
324 12:14:08.404604 EC: 0000 0021 [4000]
325 12:14:08.404690
326 12:14:08.407984 S7: 0000 0000 [0000]
327 12:14:08.408057
328 12:14:08.408116 CC: 0000 0000 [0001]
329 12:14:08.408173
330 12:14:08.411574 T0: 0000 0040 [010F]
331 12:14:08.411672
332 12:14:08.411762 Jump to BL
333 12:14:08.411836
334 12:14:08.436561
335 12:14:08.436681
336 12:14:08.436799
337 12:14:08.443492 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:14:08.446823 ARM64: Exception handlers installed.
339 12:14:08.450400 ARM64: Testing exception
340 12:14:08.454091 ARM64: Done test exception
341 12:14:08.461558 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:14:08.472040 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:14:08.478782 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:14:08.488736 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:14:08.495643 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:14:08.502392 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:14:08.513332 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:14:08.519897 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:14:08.539334 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:14:08.542453 WDT: Last reset was cold boot
351 12:14:08.545970 SPI1(PAD0) initialized at 2873684 Hz
352 12:14:08.549379 SPI5(PAD0) initialized at 992727 Hz
353 12:14:08.552332 VBOOT: Loading verstage.
354 12:14:08.558997 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:14:08.562255 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:14:08.565688 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:14:08.572398 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:14:08.579038 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:14:08.585580 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:14:08.594462 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:14:08.594548
362 12:14:08.594615
363 12:14:08.604728 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:14:08.607827 ARM64: Exception handlers installed.
365 12:14:08.610872 ARM64: Testing exception
366 12:14:08.610978 ARM64: Done test exception
367 12:14:08.617875 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:14:08.620883 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:14:08.635171 Probing TPM: . done!
370 12:14:08.635267 TPM ready after 0 ms
371 12:14:08.641848 Connected to device vid:did:rid of 1ae0:0028:00
372 12:14:08.649150 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 12:14:08.652564 Initialized TPM device CR50 revision 0
374 12:14:08.719090 tlcl_send_startup: Startup return code is 0
375 12:14:08.719243 TPM: setup succeeded
376 12:14:08.730741 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:14:08.739608 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:14:08.746284 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:14:08.758204 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:14:08.761920 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:14:08.767605 in-header: 03 07 00 00 08 00 00 00
382 12:14:08.771269 in-data: aa e4 47 04 13 02 00 00
383 12:14:08.775016 Chrome EC: UHEPI supported
384 12:14:08.781992 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:14:08.785228 in-header: 03 ad 00 00 08 00 00 00
386 12:14:08.788996 in-data: 00 20 20 08 00 00 00 00
387 12:14:08.789100 Phase 1
388 12:14:08.792384 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:14:08.799464 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:14:08.806692 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:14:08.809766 Recovery requested (1009000e)
392 12:14:08.818013 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:14:08.824250 tlcl_extend: response is 0
394 12:14:08.835626 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:14:08.839172 tlcl_extend: response is 0
396 12:14:08.846389 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:14:08.866743 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:14:08.873416 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:14:08.873545
400 12:14:08.873641
401 12:14:08.883337 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:14:08.886823 ARM64: Exception handlers installed.
403 12:14:08.886944 ARM64: Testing exception
404 12:14:08.890221 ARM64: Done test exception
405 12:14:08.912017 pmic_efuse_setting: Set efuses in 11 msecs
406 12:14:08.914985 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:14:08.922249 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:14:08.925320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:14:08.932149 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:14:08.935213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:14:08.939007 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:14:08.945751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:14:08.949383 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:14:08.953022 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:14:08.960172 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:14:08.963854 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:14:08.967872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:14:08.971579 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:14:08.977884 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:14:08.984901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:14:08.988355 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:14:08.995340 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:14:09.002432 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:14:09.006294 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:14:09.013211 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:14:09.016745 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:14:09.023474 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:14:09.029787 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:14:09.033329 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:14:09.039864 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:14:09.046607 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:14:09.049679 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:14:09.056528 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:14:09.060014 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:14:09.066672 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:14:09.069659 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:14:09.076488 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:14:09.079987 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:14:09.086574 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:14:09.089892 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:14:09.096120 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:14:09.099536 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:14:09.106696 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:14:09.109672 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:14:09.116206 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:14:09.119641 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:14:09.122763 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:14:09.129428 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:14:09.133486 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:14:09.136977 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:14:09.140562 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:14:09.144214 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:14:09.151464 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:14:09.154630 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:14:09.158215 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:14:09.161691 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:14:09.165340 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:14:09.173129 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:14:09.184235 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:14:09.187754 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:14:09.195450 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:14:09.202531 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:14:09.209708 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:14:09.213047 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:14:09.215943 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:14:09.224505 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
467 12:14:09.230931 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:14:09.234532 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:14:09.237661 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:14:09.248684 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 12:14:09.258541 [RTC]rtc_get_frequency_meter,154: input=23, output=955
472 12:14:09.268448 [RTC]rtc_get_frequency_meter,154: input=19, output=864
473 12:14:09.277275 [RTC]rtc_get_frequency_meter,154: input=17, output=819
474 12:14:09.287565 [RTC]rtc_get_frequency_meter,154: input=16, output=795
475 12:14:09.290641 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 12:14:09.293791 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 12:14:09.300664 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 12:14:09.304206 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 12:14:09.307286 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 12:14:09.310287 ADC[4]: Raw value=902876 ID=7
481 12:14:09.313707 ADC[3]: Raw value=213179 ID=1
482 12:14:09.313784 RAM Code: 0x71
483 12:14:09.320465 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 12:14:09.323833 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 12:14:09.333408 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 12:14:09.340005 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 12:14:09.343482 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 12:14:09.346455 in-header: 03 07 00 00 08 00 00 00
489 12:14:09.350014 in-data: aa e4 47 04 13 02 00 00
490 12:14:09.353628 Chrome EC: UHEPI supported
491 12:14:09.360278 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 12:14:09.363309 in-header: 03 ed 00 00 08 00 00 00
493 12:14:09.366887 in-data: 80 20 60 08 00 00 00 00
494 12:14:09.370004 MRC: failed to locate region type 0.
495 12:14:09.376693 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 12:14:09.379806 DRAM-K: Running full calibration
497 12:14:09.383407 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 12:14:09.386399 header.status = 0x0
499 12:14:09.389965 header.version = 0x6 (expected: 0x6)
500 12:14:09.393052 header.size = 0xd00 (expected: 0xd00)
501 12:14:09.396623 header.flags = 0x0
502 12:14:09.399505 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 12:14:09.418590 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
504 12:14:09.425458 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 12:14:09.428625 dram_init: ddr_geometry: 2
506 12:14:09.431917 [EMI] MDL number = 2
507 12:14:09.432000 [EMI] Get MDL freq = 0
508 12:14:09.435230 dram_init: ddr_type: 0
509 12:14:09.435307 is_discrete_lpddr4: 1
510 12:14:09.438409 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 12:14:09.438484
512 12:14:09.438548
513 12:14:09.441862 [Bian_co] ETT version 0.0.0.1
514 12:14:09.448556 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 12:14:09.448633
516 12:14:09.452054 dramc_set_vcore_voltage set vcore to 650000
517 12:14:09.454937 Read voltage for 800, 4
518 12:14:09.455022 Vio18 = 0
519 12:14:09.455085 Vcore = 650000
520 12:14:09.458643 Vdram = 0
521 12:14:09.458723 Vddq = 0
522 12:14:09.458785 Vmddr = 0
523 12:14:09.461799 dram_init: config_dvfs: 1
524 12:14:09.464997 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 12:14:09.471772 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 12:14:09.474908 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 12:14:09.478148 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 12:14:09.481806 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 12:14:09.488325 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 12:14:09.488438 MEM_TYPE=3, freq_sel=18
531 12:14:09.491562 sv_algorithm_assistance_LP4_1600
532 12:14:09.495030 ============ PULL DRAM RESETB DOWN ============
533 12:14:09.501595 ========== PULL DRAM RESETB DOWN end =========
534 12:14:09.505009 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 12:14:09.508125 ===================================
536 12:14:09.511707 LPDDR4 DRAM CONFIGURATION
537 12:14:09.514884 ===================================
538 12:14:09.515006 EX_ROW_EN[0] = 0x0
539 12:14:09.518553 EX_ROW_EN[1] = 0x0
540 12:14:09.518666 LP4Y_EN = 0x0
541 12:14:09.521681 WORK_FSP = 0x0
542 12:14:09.521757 WL = 0x2
543 12:14:09.524664 RL = 0x2
544 12:14:09.524783 BL = 0x2
545 12:14:09.528205 RPST = 0x0
546 12:14:09.528305 RD_PRE = 0x0
547 12:14:09.531430 WR_PRE = 0x1
548 12:14:09.534786 WR_PST = 0x0
549 12:14:09.534865 DBI_WR = 0x0
550 12:14:09.538188 DBI_RD = 0x0
551 12:14:09.538311 OTF = 0x1
552 12:14:09.541331 ===================================
553 12:14:09.544678 ===================================
554 12:14:09.548338 ANA top config
555 12:14:09.548451 ===================================
556 12:14:09.551258 DLL_ASYNC_EN = 0
557 12:14:09.554835 ALL_SLAVE_EN = 1
558 12:14:09.558315 NEW_RANK_MODE = 1
559 12:14:09.561447 DLL_IDLE_MODE = 1
560 12:14:09.561570 LP45_APHY_COMB_EN = 1
561 12:14:09.564506 TX_ODT_DIS = 1
562 12:14:09.568188 NEW_8X_MODE = 1
563 12:14:09.571210 ===================================
564 12:14:09.574754 ===================================
565 12:14:09.577959 data_rate = 1600
566 12:14:09.581024 CKR = 1
567 12:14:09.581105 DQ_P2S_RATIO = 8
568 12:14:09.584644 ===================================
569 12:14:09.587925 CA_P2S_RATIO = 8
570 12:14:09.591393 DQ_CA_OPEN = 0
571 12:14:09.594807 DQ_SEMI_OPEN = 0
572 12:14:09.597855 CA_SEMI_OPEN = 0
573 12:14:09.601426 CA_FULL_RATE = 0
574 12:14:09.601503 DQ_CKDIV4_EN = 1
575 12:14:09.604455 CA_CKDIV4_EN = 1
576 12:14:09.608036 CA_PREDIV_EN = 0
577 12:14:09.611097 PH8_DLY = 0
578 12:14:09.614558 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 12:14:09.617586 DQ_AAMCK_DIV = 4
580 12:14:09.617660 CA_AAMCK_DIV = 4
581 12:14:09.621133 CA_ADMCK_DIV = 4
582 12:14:09.624705 DQ_TRACK_CA_EN = 0
583 12:14:09.627869 CA_PICK = 800
584 12:14:09.631391 CA_MCKIO = 800
585 12:14:09.634340 MCKIO_SEMI = 0
586 12:14:09.637451 PLL_FREQ = 3068
587 12:14:09.637533 DQ_UI_PI_RATIO = 32
588 12:14:09.640819 CA_UI_PI_RATIO = 0
589 12:14:09.644249 ===================================
590 12:14:09.647578 ===================================
591 12:14:09.651114 memory_type:LPDDR4
592 12:14:09.654669 GP_NUM : 10
593 12:14:09.654754 SRAM_EN : 1
594 12:14:09.658293 MD32_EN : 0
595 12:14:09.661726 ===================================
596 12:14:09.661805 [ANA_INIT] >>>>>>>>>>>>>>
597 12:14:09.665375 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 12:14:09.669004 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 12:14:09.672607 ===================================
600 12:14:09.676254 data_rate = 1600,PCW = 0X7600
601 12:14:09.679897 ===================================
602 12:14:09.683597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 12:14:09.687230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 12:14:09.694851 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 12:14:09.698337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 12:14:09.701920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 12:14:09.705016 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 12:14:09.705090 [ANA_INIT] flow start
609 12:14:09.709178 [ANA_INIT] PLL >>>>>>>>
610 12:14:09.712652 [ANA_INIT] PLL <<<<<<<<
611 12:14:09.712747 [ANA_INIT] MIDPI >>>>>>>>
612 12:14:09.716858 [ANA_INIT] MIDPI <<<<<<<<
613 12:14:09.716959 [ANA_INIT] DLL >>>>>>>>
614 12:14:09.719995 [ANA_INIT] flow end
615 12:14:09.723740 ============ LP4 DIFF to SE enter ============
616 12:14:09.727405 ============ LP4 DIFF to SE exit ============
617 12:14:09.731154 [ANA_INIT] <<<<<<<<<<<<<
618 12:14:09.734589 [Flow] Enable top DCM control >>>>>
619 12:14:09.738082 [Flow] Enable top DCM control <<<<<
620 12:14:09.741656 Enable DLL master slave shuffle
621 12:14:09.745381 ==============================================================
622 12:14:09.745465 Gating Mode config
623 12:14:09.752906 ==============================================================
624 12:14:09.752989 Config description:
625 12:14:09.763880 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 12:14:09.771553 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 12:14:09.775061 SELPH_MODE 0: By rank 1: By Phase
628 12:14:09.782446 ==============================================================
629 12:14:09.785995 GAT_TRACK_EN = 1
630 12:14:09.786078 RX_GATING_MODE = 2
631 12:14:09.789532 RX_GATING_TRACK_MODE = 2
632 12:14:09.793309 SELPH_MODE = 1
633 12:14:09.796969 PICG_EARLY_EN = 1
634 12:14:09.800503 VALID_LAT_VALUE = 1
635 12:14:09.804494 ==============================================================
636 12:14:09.808001 Enter into Gating configuration >>>>
637 12:14:09.811642 Exit from Gating configuration <<<<
638 12:14:09.815188 Enter into DVFS_PRE_config >>>>>
639 12:14:09.826684 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 12:14:09.830370 Exit from DVFS_PRE_config <<<<<
641 12:14:09.834006 Enter into PICG configuration >>>>
642 12:14:09.834106 Exit from PICG configuration <<<<
643 12:14:09.837503 [RX_INPUT] configuration >>>>>
644 12:14:09.841512 [RX_INPUT] configuration <<<<<
645 12:14:09.844988 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 12:14:09.852543 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 12:14:09.856048 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 12:14:09.863467 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 12:14:09.870870 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 12:14:09.877572 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 12:14:09.881500 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 12:14:09.885223 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 12:14:09.888390 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 12:14:09.892058 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 12:14:09.896212 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 12:14:09.899824 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 12:14:09.903384 ===================================
658 12:14:09.906879 LPDDR4 DRAM CONFIGURATION
659 12:14:09.910585 ===================================
660 12:14:09.910670 EX_ROW_EN[0] = 0x0
661 12:14:09.914415 EX_ROW_EN[1] = 0x0
662 12:14:09.914499 LP4Y_EN = 0x0
663 12:14:09.918096 WORK_FSP = 0x0
664 12:14:09.918179 WL = 0x2
665 12:14:09.921577 RL = 0x2
666 12:14:09.921662 BL = 0x2
667 12:14:09.925517 RPST = 0x0
668 12:14:09.925600 RD_PRE = 0x0
669 12:14:09.929240 WR_PRE = 0x1
670 12:14:09.929324 WR_PST = 0x0
671 12:14:09.932903 DBI_WR = 0x0
672 12:14:09.932987 DBI_RD = 0x0
673 12:14:09.936472 OTF = 0x1
674 12:14:09.936555 ===================================
675 12:14:09.939724 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 12:14:09.946311 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 12:14:09.949683 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 12:14:09.953324 ===================================
679 12:14:09.956451 LPDDR4 DRAM CONFIGURATION
680 12:14:09.959926 ===================================
681 12:14:09.960010 EX_ROW_EN[0] = 0x10
682 12:14:09.962895 EX_ROW_EN[1] = 0x0
683 12:14:09.966400 LP4Y_EN = 0x0
684 12:14:09.966484 WORK_FSP = 0x0
685 12:14:09.969727 WL = 0x2
686 12:14:09.969811 RL = 0x2
687 12:14:09.973238 BL = 0x2
688 12:14:09.973322 RPST = 0x0
689 12:14:09.976147 RD_PRE = 0x0
690 12:14:09.976256 WR_PRE = 0x1
691 12:14:09.979588 WR_PST = 0x0
692 12:14:09.979671 DBI_WR = 0x0
693 12:14:09.982954 DBI_RD = 0x0
694 12:14:09.983038 OTF = 0x1
695 12:14:09.986165 ===================================
696 12:14:09.992880 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 12:14:09.997552 nWR fixed to 40
698 12:14:10.000640 [ModeRegInit_LP4] CH0 RK0
699 12:14:10.000750 [ModeRegInit_LP4] CH0 RK1
700 12:14:10.003662 [ModeRegInit_LP4] CH1 RK0
701 12:14:10.007187 [ModeRegInit_LP4] CH1 RK1
702 12:14:10.007271 match AC timing 13
703 12:14:10.013769 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 12:14:10.016791 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 12:14:10.020433 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 12:14:10.026915 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 12:14:10.030391 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 12:14:10.033482 [EMI DOE] emi_dcm 0
709 12:14:10.037197 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 12:14:10.037281 ==
711 12:14:10.040437 Dram Type= 6, Freq= 0, CH_0, rank 0
712 12:14:10.043922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 12:14:10.044007 ==
714 12:14:10.050481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 12:14:10.056793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 12:14:10.065069 [CA 0] Center 38 (7~69) winsize 63
717 12:14:10.068466 [CA 1] Center 38 (7~69) winsize 63
718 12:14:10.071511 [CA 2] Center 35 (5~66) winsize 62
719 12:14:10.074521 [CA 3] Center 35 (5~66) winsize 62
720 12:14:10.077872 [CA 4] Center 35 (4~66) winsize 63
721 12:14:10.081367 [CA 5] Center 33 (3~64) winsize 62
722 12:14:10.081452
723 12:14:10.084694 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 12:14:10.084841
725 12:14:10.088086 [CATrainingPosCal] consider 1 rank data
726 12:14:10.091504 u2DelayCellTimex100 = 270/100 ps
727 12:14:10.094898 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 12:14:10.101165 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 12:14:10.104354 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 12:14:10.108004 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 12:14:10.110998 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
732 12:14:10.114638 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 12:14:10.114730
734 12:14:10.117719 CA PerBit enable=1, Macro0, CA PI delay=33
735 12:14:10.117804
736 12:14:10.120883 [CBTSetCACLKResult] CA Dly = 33
737 12:14:10.124455 CS Dly: 5 (0~36)
738 12:14:10.124539 ==
739 12:14:10.127524 Dram Type= 6, Freq= 0, CH_0, rank 1
740 12:14:10.130949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 12:14:10.131034 ==
742 12:14:10.137606 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 12:14:10.140692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 12:14:10.151204 [CA 0] Center 38 (7~69) winsize 63
745 12:14:10.154819 [CA 1] Center 38 (7~69) winsize 63
746 12:14:10.158276 [CA 2] Center 36 (5~67) winsize 63
747 12:14:10.161362 [CA 3] Center 35 (5~66) winsize 62
748 12:14:10.164874 [CA 4] Center 35 (4~66) winsize 63
749 12:14:10.168019 [CA 5] Center 34 (4~65) winsize 62
750 12:14:10.168103
751 12:14:10.171379 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 12:14:10.171464
753 12:14:10.174803 [CATrainingPosCal] consider 2 rank data
754 12:14:10.177973 u2DelayCellTimex100 = 270/100 ps
755 12:14:10.181449 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 12:14:10.184359 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 12:14:10.191445 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
758 12:14:10.194500 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 12:14:10.197792 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
760 12:14:10.201352 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 12:14:10.201459
762 12:14:10.204635 CA PerBit enable=1, Macro0, CA PI delay=34
763 12:14:10.204748
764 12:14:10.207631 [CBTSetCACLKResult] CA Dly = 34
765 12:14:10.207733 CS Dly: 6 (0~38)
766 12:14:10.207817
767 12:14:10.211166 ----->DramcWriteLeveling(PI) begin...
768 12:14:10.214615 ==
769 12:14:10.218234 Dram Type= 6, Freq= 0, CH_0, rank 0
770 12:14:10.221255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 12:14:10.221341 ==
772 12:14:10.224852 Write leveling (Byte 0): 34 => 34
773 12:14:10.227865 Write leveling (Byte 1): 28 => 28
774 12:14:10.230988 DramcWriteLeveling(PI) end<-----
775 12:14:10.231093
776 12:14:10.231189 ==
777 12:14:10.234445 Dram Type= 6, Freq= 0, CH_0, rank 0
778 12:14:10.237952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 12:14:10.238042 ==
780 12:14:10.241157 [Gating] SW mode calibration
781 12:14:10.247859 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 12:14:10.251161 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 12:14:10.258135 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
784 12:14:10.261020 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 12:14:10.264483 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 12:14:10.271101 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 12:14:10.274691 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 12:14:10.277522 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:14:10.284399 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:14:10.287928 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:14:10.291844 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:14:10.295225 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:14:10.302779 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:14:10.306183 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:14:10.309570 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:14:10.312536 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:14:10.320297 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:14:10.323934 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:14:10.327079 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:14:10.330181 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
801 12:14:10.336793 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
802 12:14:10.340234 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:14:10.343850 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:14:10.350393 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:14:10.353437 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:14:10.356865 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:14:10.363499 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:14:10.367042 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
809 12:14:10.370017 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 12:14:10.376710 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
811 12:14:10.380298 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 12:14:10.383249 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 12:14:10.390102 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 12:14:10.393559 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:14:10.396619 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
816 12:14:10.403088 0 10 4 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
817 12:14:10.406474 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 1) (1 0)
818 12:14:10.409811 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
819 12:14:10.416511 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 12:14:10.420106 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 12:14:10.423299 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:14:10.429823 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:14:10.433444 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:14:10.436586 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
825 12:14:10.443326 0 11 8 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
826 12:14:10.446696 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
827 12:14:10.449801 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 12:14:10.456602 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 12:14:10.460102 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 12:14:10.463256 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:14:10.466827 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
832 12:14:10.473311 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 12:14:10.476502 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 12:14:10.480037 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 12:14:10.486476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 12:14:10.490097 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 12:14:10.493201 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:14:10.499799 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:14:10.503494 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:14:10.506589 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:14:10.513154 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:14:10.516476 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:14:10.520219 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:14:10.526874 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:14:10.529959 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:14:10.533266 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:14:10.539986 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
848 12:14:10.543120 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 12:14:10.546567 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 12:14:10.549858 Total UI for P1: 0, mck2ui 16
851 12:14:10.552979 best dqsien dly found for B0: ( 0, 14, 2)
852 12:14:10.556444 Total UI for P1: 0, mck2ui 16
853 12:14:10.559895 best dqsien dly found for B1: ( 0, 14, 6)
854 12:14:10.562968 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
855 12:14:10.566217 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
856 12:14:10.566301
857 12:14:10.569712 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
858 12:14:10.576445 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
859 12:14:10.576556 [Gating] SW calibration Done
860 12:14:10.576651 ==
861 12:14:10.579752 Dram Type= 6, Freq= 0, CH_0, rank 0
862 12:14:10.586450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 12:14:10.586535 ==
864 12:14:10.586601 RX Vref Scan: 0
865 12:14:10.586664
866 12:14:10.589877 RX Vref 0 -> 0, step: 1
867 12:14:10.589961
868 12:14:10.593004 RX Delay -130 -> 252, step: 16
869 12:14:10.596589 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
870 12:14:10.599635 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
871 12:14:10.602699 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
872 12:14:10.609482 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
873 12:14:10.613035 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
874 12:14:10.616246 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
875 12:14:10.619302 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
876 12:14:10.622756 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 12:14:10.629614 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
878 12:14:10.633018 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
879 12:14:10.636298 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
880 12:14:10.639625 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
881 12:14:10.642652 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
882 12:14:10.650194 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
883 12:14:10.652649 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 12:14:10.656177 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
885 12:14:10.656284 ==
886 12:14:10.659238 Dram Type= 6, Freq= 0, CH_0, rank 0
887 12:14:10.662730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 12:14:10.662871 ==
889 12:14:10.665933 DQS Delay:
890 12:14:10.666033 DQS0 = 0, DQS1 = 0
891 12:14:10.669212 DQM Delay:
892 12:14:10.669313 DQM0 = 90, DQM1 = 78
893 12:14:10.669406 DQ Delay:
894 12:14:10.672667 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
895 12:14:10.675813 DQ4 =85, DQ5 =85, DQ6 =101, DQ7 =101
896 12:14:10.679140 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
897 12:14:10.682859 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
898 12:14:10.682961
899 12:14:10.685988
900 12:14:10.686086 ==
901 12:14:10.689515 Dram Type= 6, Freq= 0, CH_0, rank 0
902 12:14:10.692393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 12:14:10.692496 ==
904 12:14:10.692594
905 12:14:10.692688
906 12:14:10.695919 TX Vref Scan disable
907 12:14:10.695996 == TX Byte 0 ==
908 12:14:10.702726 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
909 12:14:10.705868 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
910 12:14:10.705968 == TX Byte 1 ==
911 12:14:10.712521 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
912 12:14:10.715847 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
913 12:14:10.715936 ==
914 12:14:10.719450 Dram Type= 6, Freq= 0, CH_0, rank 0
915 12:14:10.722622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 12:14:10.722725 ==
917 12:14:10.736264 TX Vref=22, minBit 6, minWin=27, winSum=441
918 12:14:10.739548 TX Vref=24, minBit 11, minWin=26, winSum=446
919 12:14:10.742799 TX Vref=26, minBit 10, minWin=27, winSum=448
920 12:14:10.746245 TX Vref=28, minBit 13, minWin=27, winSum=450
921 12:14:10.749638 TX Vref=30, minBit 3, minWin=28, winSum=455
922 12:14:10.756362 TX Vref=32, minBit 6, minWin=28, winSum=456
923 12:14:10.759978 [TxChooseVref] Worse bit 6, Min win 28, Win sum 456, Final Vref 32
924 12:14:10.760053
925 12:14:10.762981 Final TX Range 1 Vref 32
926 12:14:10.763081
927 12:14:10.763175 ==
928 12:14:10.766527 Dram Type= 6, Freq= 0, CH_0, rank 0
929 12:14:10.769703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 12:14:10.772705 ==
931 12:14:10.772824
932 12:14:10.772915
933 12:14:10.773005 TX Vref Scan disable
934 12:14:10.776927 == TX Byte 0 ==
935 12:14:10.780444 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
936 12:14:10.783788 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
937 12:14:10.786919 == TX Byte 1 ==
938 12:14:10.789991 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
939 12:14:10.793651 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
940 12:14:10.797057
941 12:14:10.797157 [DATLAT]
942 12:14:10.797321 Freq=800, CH0 RK0
943 12:14:10.797417
944 12:14:10.800138 DATLAT Default: 0xa
945 12:14:10.800217 0, 0xFFFF, sum = 0
946 12:14:10.803634 1, 0xFFFF, sum = 0
947 12:14:10.803736 2, 0xFFFF, sum = 0
948 12:14:10.806696 3, 0xFFFF, sum = 0
949 12:14:10.806798 4, 0xFFFF, sum = 0
950 12:14:10.810464 5, 0xFFFF, sum = 0
951 12:14:10.813655 6, 0xFFFF, sum = 0
952 12:14:10.813726 7, 0xFFFF, sum = 0
953 12:14:10.816622 8, 0xFFFF, sum = 0
954 12:14:10.816719 9, 0x0, sum = 1
955 12:14:10.816836 10, 0x0, sum = 2
956 12:14:10.820236 11, 0x0, sum = 3
957 12:14:10.820303 12, 0x0, sum = 4
958 12:14:10.823303 best_step = 10
959 12:14:10.823386
960 12:14:10.823461 ==
961 12:14:10.826965 Dram Type= 6, Freq= 0, CH_0, rank 0
962 12:14:10.830039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 12:14:10.830151 ==
964 12:14:10.833537 RX Vref Scan: 1
965 12:14:10.833640
966 12:14:10.833736 Set Vref Range= 32 -> 127
967 12:14:10.837059
968 12:14:10.837158 RX Vref 32 -> 127, step: 1
969 12:14:10.837253
970 12:14:10.840104 RX Delay -95 -> 252, step: 8
971 12:14:10.840214
972 12:14:10.843348 Set Vref, RX VrefLevel [Byte0]: 32
973 12:14:10.846683 [Byte1]: 32
974 12:14:10.846810
975 12:14:10.849943 Set Vref, RX VrefLevel [Byte0]: 33
976 12:14:10.853435 [Byte1]: 33
977 12:14:10.857237
978 12:14:10.857346 Set Vref, RX VrefLevel [Byte0]: 34
979 12:14:10.860402 [Byte1]: 34
980 12:14:10.865117
981 12:14:10.865206 Set Vref, RX VrefLevel [Byte0]: 35
982 12:14:10.868060 [Byte1]: 35
983 12:14:10.872660
984 12:14:10.872762 Set Vref, RX VrefLevel [Byte0]: 36
985 12:14:10.875800 [Byte1]: 36
986 12:14:10.879916
987 12:14:10.880015 Set Vref, RX VrefLevel [Byte0]: 37
988 12:14:10.883110 [Byte1]: 37
989 12:14:10.887547
990 12:14:10.887646 Set Vref, RX VrefLevel [Byte0]: 38
991 12:14:10.890974 [Byte1]: 38
992 12:14:10.895764
993 12:14:10.895861 Set Vref, RX VrefLevel [Byte0]: 39
994 12:14:10.898757 [Byte1]: 39
995 12:14:10.902639
996 12:14:10.902714 Set Vref, RX VrefLevel [Byte0]: 40
997 12:14:10.906381 [Byte1]: 40
998 12:14:10.910417
999 12:14:10.910490 Set Vref, RX VrefLevel [Byte0]: 41
1000 12:14:10.913457 [Byte1]: 41
1001 12:14:10.918128
1002 12:14:10.918207 Set Vref, RX VrefLevel [Byte0]: 42
1003 12:14:10.921263 [Byte1]: 42
1004 12:14:10.925724
1005 12:14:10.925797 Set Vref, RX VrefLevel [Byte0]: 43
1006 12:14:10.928694 [Byte1]: 43
1007 12:14:10.933408
1008 12:14:10.933478 Set Vref, RX VrefLevel [Byte0]: 44
1009 12:14:10.936417 [Byte1]: 44
1010 12:14:10.941051
1011 12:14:10.941125 Set Vref, RX VrefLevel [Byte0]: 45
1012 12:14:10.944075 [Byte1]: 45
1013 12:14:10.948200
1014 12:14:10.948272 Set Vref, RX VrefLevel [Byte0]: 46
1015 12:14:10.951519 [Byte1]: 46
1016 12:14:10.956299
1017 12:14:10.956398 Set Vref, RX VrefLevel [Byte0]: 47
1018 12:14:10.959602 [Byte1]: 47
1019 12:14:10.963468
1020 12:14:10.963567 Set Vref, RX VrefLevel [Byte0]: 48
1021 12:14:10.966823 [Byte1]: 48
1022 12:14:10.971583
1023 12:14:10.971680 Set Vref, RX VrefLevel [Byte0]: 49
1024 12:14:10.975183 [Byte1]: 49
1025 12:14:10.978868
1026 12:14:10.978969 Set Vref, RX VrefLevel [Byte0]: 50
1027 12:14:10.982468 [Byte1]: 50
1028 12:14:10.986641
1029 12:14:10.986738 Set Vref, RX VrefLevel [Byte0]: 51
1030 12:14:10.989640 [Byte1]: 51
1031 12:14:10.994125
1032 12:14:10.994225 Set Vref, RX VrefLevel [Byte0]: 52
1033 12:14:10.997181 [Byte1]: 52
1034 12:14:11.001369
1035 12:14:11.001471 Set Vref, RX VrefLevel [Byte0]: 53
1036 12:14:11.004834 [Byte1]: 53
1037 12:14:11.009385
1038 12:14:11.009484 Set Vref, RX VrefLevel [Byte0]: 54
1039 12:14:11.012389 [Byte1]: 54
1040 12:14:11.016957
1041 12:14:11.017032 Set Vref, RX VrefLevel [Byte0]: 55
1042 12:14:11.019990 [Byte1]: 55
1043 12:14:11.024135
1044 12:14:11.024232 Set Vref, RX VrefLevel [Byte0]: 56
1045 12:14:11.027560 [Byte1]: 56
1046 12:14:11.031738
1047 12:14:11.031833 Set Vref, RX VrefLevel [Byte0]: 57
1048 12:14:11.035409 [Byte1]: 57
1049 12:14:11.039404
1050 12:14:11.039477 Set Vref, RX VrefLevel [Byte0]: 58
1051 12:14:11.043001 [Byte1]: 58
1052 12:14:11.047276
1053 12:14:11.047376 Set Vref, RX VrefLevel [Byte0]: 59
1054 12:14:11.050346 [Byte1]: 59
1055 12:14:11.054863
1056 12:14:11.054960 Set Vref, RX VrefLevel [Byte0]: 60
1057 12:14:11.057863 [Byte1]: 60
1058 12:14:11.062190
1059 12:14:11.062258 Set Vref, RX VrefLevel [Byte0]: 61
1060 12:14:11.065409 [Byte1]: 61
1061 12:14:11.069684
1062 12:14:11.069756 Set Vref, RX VrefLevel [Byte0]: 62
1063 12:14:11.073031 [Byte1]: 62
1064 12:14:11.077260
1065 12:14:11.077336 Set Vref, RX VrefLevel [Byte0]: 63
1066 12:14:11.080692 [Byte1]: 63
1067 12:14:11.085285
1068 12:14:11.085358 Set Vref, RX VrefLevel [Byte0]: 64
1069 12:14:11.088402 [Byte1]: 64
1070 12:14:11.092637
1071 12:14:11.092736 Set Vref, RX VrefLevel [Byte0]: 65
1072 12:14:11.096059 [Byte1]: 65
1073 12:14:11.100368
1074 12:14:11.100468 Set Vref, RX VrefLevel [Byte0]: 66
1075 12:14:11.103475 [Byte1]: 66
1076 12:14:11.107990
1077 12:14:11.108060 Set Vref, RX VrefLevel [Byte0]: 67
1078 12:14:11.111037 [Byte1]: 67
1079 12:14:11.115688
1080 12:14:11.115785 Set Vref, RX VrefLevel [Byte0]: 68
1081 12:14:11.118605 [Byte1]: 68
1082 12:14:11.123267
1083 12:14:11.123362 Set Vref, RX VrefLevel [Byte0]: 69
1084 12:14:11.126407 [Byte1]: 69
1085 12:14:11.130489
1086 12:14:11.130587 Set Vref, RX VrefLevel [Byte0]: 70
1087 12:14:11.134043 [Byte1]: 70
1088 12:14:11.138199
1089 12:14:11.138267 Set Vref, RX VrefLevel [Byte0]: 71
1090 12:14:11.141371 [Byte1]: 71
1091 12:14:11.145869
1092 12:14:11.145965 Set Vref, RX VrefLevel [Byte0]: 72
1093 12:14:11.149493 [Byte1]: 72
1094 12:14:11.153666
1095 12:14:11.153766 Set Vref, RX VrefLevel [Byte0]: 73
1096 12:14:11.156722 [Byte1]: 73
1097 12:14:11.160907
1098 12:14:11.160979 Set Vref, RX VrefLevel [Byte0]: 74
1099 12:14:11.164440 [Byte1]: 74
1100 12:14:11.168517
1101 12:14:11.168616 Set Vref, RX VrefLevel [Byte0]: 75
1102 12:14:11.171892 [Byte1]: 75
1103 12:14:11.176297
1104 12:14:11.176403 Set Vref, RX VrefLevel [Byte0]: 76
1105 12:14:11.179608 [Byte1]: 76
1106 12:14:11.183886
1107 12:14:11.183969 Final RX Vref Byte 0 = 62 to rank0
1108 12:14:11.187316 Final RX Vref Byte 1 = 60 to rank0
1109 12:14:11.190616 Final RX Vref Byte 0 = 62 to rank1
1110 12:14:11.194152 Final RX Vref Byte 1 = 60 to rank1==
1111 12:14:11.197137 Dram Type= 6, Freq= 0, CH_0, rank 0
1112 12:14:11.203622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1113 12:14:11.203728 ==
1114 12:14:11.203818 DQS Delay:
1115 12:14:11.203889 DQS0 = 0, DQS1 = 0
1116 12:14:11.207274 DQM Delay:
1117 12:14:11.207461 DQM0 = 93, DQM1 = 82
1118 12:14:11.210818 DQ Delay:
1119 12:14:11.213861 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1120 12:14:11.217214 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1121 12:14:11.220288 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1122 12:14:11.223920 DQ12 =88, DQ13 =80, DQ14 =92, DQ15 =92
1123 12:14:11.224021
1124 12:14:11.224119
1125 12:14:11.230208 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1126 12:14:11.233671 CH0 RK0: MR19=606, MR18=3C37
1127 12:14:11.240189 CH0_RK0: MR19=0x606, MR18=0x3C37, DQSOSC=394, MR23=63, INC=95, DEC=63
1128 12:14:11.240305
1129 12:14:11.243751 ----->DramcWriteLeveling(PI) begin...
1130 12:14:11.243855 ==
1131 12:14:11.246885 Dram Type= 6, Freq= 0, CH_0, rank 1
1132 12:14:11.250357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 12:14:11.250459 ==
1134 12:14:11.253437 Write leveling (Byte 0): 33 => 33
1135 12:14:11.256978 Write leveling (Byte 1): 32 => 32
1136 12:14:11.260614 DramcWriteLeveling(PI) end<-----
1137 12:14:11.260725
1138 12:14:11.260868 ==
1139 12:14:11.263651 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 12:14:11.266765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 12:14:11.266867 ==
1142 12:14:11.270254 [Gating] SW mode calibration
1143 12:14:11.276770 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1144 12:14:11.283635 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1145 12:14:11.286984 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1146 12:14:11.290320 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1147 12:14:11.296682 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 12:14:11.299981 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 12:14:11.303649 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 12:14:11.310463 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 12:14:11.313605 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 12:14:11.357329 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 12:14:11.357649 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 12:14:11.357772 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:14:11.357876 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:14:11.357956 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:14:11.358021 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:14:11.358079 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:14:11.358162 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:14:11.358251 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:14:11.358336 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1162 12:14:11.401575 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1163 12:14:11.401871 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:14:11.402015 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:14:11.402117 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:14:11.402230 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:14:11.402334 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:14:11.402611 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:14:11.402723 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:14:11.402883 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1171 12:14:11.402990 0 9 8 | B1->B0 | 2d2c 3434 | 1 1 | (1 1) (1 1)
1172 12:14:11.437227 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 12:14:11.437494 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 12:14:11.437565 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 12:14:11.437646 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 12:14:11.437749 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 12:14:11.437839 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 12:14:11.437928 0 10 4 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
1179 12:14:11.441353 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (1 0)
1180 12:14:11.441422 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:14:11.444295 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:14:11.450881 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:14:11.454436 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:14:11.457537 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:14:11.464317 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:14:11.467444 0 11 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
1187 12:14:11.471127 0 11 8 | B1->B0 | 4040 4141 | 0 0 | (0 0) (1 1)
1188 12:14:11.477892 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 12:14:11.480909 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 12:14:11.484428 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 12:14:11.491018 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 12:14:11.494125 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 12:14:11.497186 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 12:14:11.504148 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1195 12:14:11.507540 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1196 12:14:11.510879 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 12:14:11.517219 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 12:14:11.520432 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 12:14:11.523973 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 12:14:11.530656 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 12:14:11.533830 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 12:14:11.537931 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:14:11.541459 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:14:11.545176 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:14:11.552529 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:14:11.556166 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:14:11.559390 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:14:11.562910 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:14:11.569993 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:14:11.573238 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1211 12:14:11.576429 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 12:14:11.579986 Total UI for P1: 0, mck2ui 16
1213 12:14:11.583094 best dqsien dly found for B0: ( 0, 14, 4)
1214 12:14:11.586637 Total UI for P1: 0, mck2ui 16
1215 12:14:11.589767 best dqsien dly found for B1: ( 0, 14, 4)
1216 12:14:11.592938 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1217 12:14:11.596611 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1218 12:14:11.596711
1219 12:14:11.599576 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1220 12:14:11.606545 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1221 12:14:11.606650 [Gating] SW calibration Done
1222 12:14:11.606745 ==
1223 12:14:11.609870 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 12:14:11.616325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1225 12:14:11.616430 ==
1226 12:14:11.616527 RX Vref Scan: 0
1227 12:14:11.616618
1228 12:14:11.619461 RX Vref 0 -> 0, step: 1
1229 12:14:11.619556
1230 12:14:11.622814 RX Delay -130 -> 252, step: 16
1231 12:14:11.626260 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1232 12:14:11.629514 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1233 12:14:11.632980 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1234 12:14:11.639388 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1235 12:14:11.642883 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1236 12:14:11.646094 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1237 12:14:11.649609 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1238 12:14:11.653169 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1239 12:14:11.659370 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1240 12:14:11.662953 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1241 12:14:11.666110 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1242 12:14:11.669426 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1243 12:14:11.672928 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1244 12:14:11.679445 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1245 12:14:11.682627 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1246 12:14:11.686014 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1247 12:14:11.686085 ==
1248 12:14:11.689631 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 12:14:11.692726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1250 12:14:11.692852 ==
1251 12:14:11.696388 DQS Delay:
1252 12:14:11.696489 DQS0 = 0, DQS1 = 0
1253 12:14:11.699581 DQM Delay:
1254 12:14:11.699680 DQM0 = 91, DQM1 = 80
1255 12:14:11.699769 DQ Delay:
1256 12:14:11.702649 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1257 12:14:11.706382 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =109
1258 12:14:11.709275 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1259 12:14:11.712792 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1260 12:14:11.712886
1261 12:14:11.712952
1262 12:14:11.715780 ==
1263 12:14:11.719143 Dram Type= 6, Freq= 0, CH_0, rank 1
1264 12:14:11.722520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1265 12:14:11.722628 ==
1266 12:14:11.722717
1267 12:14:11.722780
1268 12:14:11.726238 TX Vref Scan disable
1269 12:14:11.726338 == TX Byte 0 ==
1270 12:14:11.732459 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1271 12:14:11.735739 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1272 12:14:11.735818 == TX Byte 1 ==
1273 12:14:11.742626 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1274 12:14:11.745744 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1275 12:14:11.745823 ==
1276 12:14:11.748921 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 12:14:11.752493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1278 12:14:11.752566 ==
1279 12:14:11.766118 TX Vref=22, minBit 1, minWin=27, winSum=448
1280 12:14:11.769227 TX Vref=24, minBit 8, minWin=27, winSum=453
1281 12:14:11.772845 TX Vref=26, minBit 8, minWin=27, winSum=453
1282 12:14:11.775801 TX Vref=28, minBit 8, minWin=27, winSum=455
1283 12:14:11.779427 TX Vref=30, minBit 8, minWin=27, winSum=456
1284 12:14:11.782865 TX Vref=32, minBit 6, minWin=28, winSum=458
1285 12:14:11.789259 [TxChooseVref] Worse bit 6, Min win 28, Win sum 458, Final Vref 32
1286 12:14:11.789360
1287 12:14:11.792578 Final TX Range 1 Vref 32
1288 12:14:11.792683
1289 12:14:11.792781 ==
1290 12:14:11.795841 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 12:14:11.799696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 12:14:11.799801 ==
1293 12:14:11.799967
1294 12:14:11.802836
1295 12:14:11.802929 TX Vref Scan disable
1296 12:14:11.805889 == TX Byte 0 ==
1297 12:14:11.809375 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1298 12:14:11.815940 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1299 12:14:11.816042 == TX Byte 1 ==
1300 12:14:11.819053 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1301 12:14:11.825990 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1302 12:14:11.826071
1303 12:14:11.826141 [DATLAT]
1304 12:14:11.826230 Freq=800, CH0 RK1
1305 12:14:11.826315
1306 12:14:11.829363 DATLAT Default: 0xa
1307 12:14:11.829433 0, 0xFFFF, sum = 0
1308 12:14:11.832647 1, 0xFFFF, sum = 0
1309 12:14:11.832751 2, 0xFFFF, sum = 0
1310 12:14:11.835454 3, 0xFFFF, sum = 0
1311 12:14:11.838868 4, 0xFFFF, sum = 0
1312 12:14:11.838969 5, 0xFFFF, sum = 0
1313 12:14:11.842257 6, 0xFFFF, sum = 0
1314 12:14:11.842356 7, 0xFFFF, sum = 0
1315 12:14:11.845614 8, 0xFFFF, sum = 0
1316 12:14:11.845688 9, 0x0, sum = 1
1317 12:14:11.849014 10, 0x0, sum = 2
1318 12:14:11.849085 11, 0x0, sum = 3
1319 12:14:11.852148 12, 0x0, sum = 4
1320 12:14:11.852219 best_step = 10
1321 12:14:11.852278
1322 12:14:11.852356 ==
1323 12:14:11.855730 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 12:14:11.858761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 12:14:11.858857 ==
1326 12:14:11.861871 RX Vref Scan: 0
1327 12:14:11.861948
1328 12:14:11.865441 RX Vref 0 -> 0, step: 1
1329 12:14:11.865511
1330 12:14:11.865570 RX Delay -95 -> 252, step: 8
1331 12:14:11.872579 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1332 12:14:11.875751 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1333 12:14:11.879428 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1334 12:14:11.882489 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1335 12:14:11.889303 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1336 12:14:11.892585 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1337 12:14:11.895566 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1338 12:14:11.899093 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1339 12:14:11.902142 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1340 12:14:11.908932 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1341 12:14:11.911982 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1342 12:14:11.915631 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1343 12:14:11.918651 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1344 12:14:11.922211 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1345 12:14:11.928509 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1346 12:14:11.931955 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1347 12:14:11.932026 ==
1348 12:14:11.935235 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 12:14:11.938533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 12:14:11.938634 ==
1351 12:14:11.941852 DQS Delay:
1352 12:14:11.941953 DQS0 = 0, DQS1 = 0
1353 12:14:11.942041 DQM Delay:
1354 12:14:11.945198 DQM0 = 91, DQM1 = 81
1355 12:14:11.945298 DQ Delay:
1356 12:14:11.948600 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =84
1357 12:14:11.952003 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1358 12:14:11.955442 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1359 12:14:11.958559 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1360 12:14:11.958660
1361 12:14:11.958758
1362 12:14:11.968390 [DQSOSCAuto] RK1, (LSB)MR18= 0x451f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1363 12:14:11.971979 CH0 RK1: MR19=606, MR18=451F
1364 12:14:11.974865 CH0_RK1: MR19=0x606, MR18=0x451F, DQSOSC=392, MR23=63, INC=96, DEC=64
1365 12:14:11.978295 [RxdqsGatingPostProcess] freq 800
1366 12:14:11.985153 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1367 12:14:11.988232 Pre-setting of DQS Precalculation
1368 12:14:11.991425 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1369 12:14:11.991528 ==
1370 12:14:11.994873 Dram Type= 6, Freq= 0, CH_1, rank 0
1371 12:14:12.001355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 12:14:12.001465 ==
1373 12:14:12.004947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1374 12:14:12.011632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1375 12:14:12.021428 [CA 0] Center 36 (6~67) winsize 62
1376 12:14:12.024411 [CA 1] Center 36 (6~67) winsize 62
1377 12:14:12.027508 [CA 2] Center 35 (5~65) winsize 61
1378 12:14:12.031205 [CA 3] Center 34 (4~65) winsize 62
1379 12:14:12.034419 [CA 4] Center 34 (4~65) winsize 62
1380 12:14:12.037982 [CA 5] Center 33 (3~64) winsize 62
1381 12:14:12.038089
1382 12:14:12.040804 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1383 12:14:12.040919
1384 12:14:12.044433 [CATrainingPosCal] consider 1 rank data
1385 12:14:12.047442 u2DelayCellTimex100 = 270/100 ps
1386 12:14:12.050861 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1387 12:14:12.057582 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1388 12:14:12.061085 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1389 12:14:12.063970 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1390 12:14:12.067325 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1391 12:14:12.070882 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1392 12:14:12.070987
1393 12:14:12.074316 CA PerBit enable=1, Macro0, CA PI delay=33
1394 12:14:12.074414
1395 12:14:12.077531 [CBTSetCACLKResult] CA Dly = 33
1396 12:14:12.080713 CS Dly: 5 (0~36)
1397 12:14:12.080817 ==
1398 12:14:12.083984 Dram Type= 6, Freq= 0, CH_1, rank 1
1399 12:14:12.087618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 12:14:12.087716 ==
1401 12:14:12.090694 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1402 12:14:12.097570 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1403 12:14:12.107160 [CA 0] Center 37 (7~68) winsize 62
1404 12:14:12.110758 [CA 1] Center 37 (6~68) winsize 63
1405 12:14:12.114312 [CA 2] Center 35 (5~66) winsize 62
1406 12:14:12.117401 [CA 3] Center 34 (4~65) winsize 62
1407 12:14:12.120958 [CA 4] Center 34 (4~65) winsize 62
1408 12:14:12.123963 [CA 5] Center 34 (4~65) winsize 62
1409 12:14:12.124047
1410 12:14:12.127446 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1411 12:14:12.127546
1412 12:14:12.130407 [CATrainingPosCal] consider 2 rank data
1413 12:14:12.134111 u2DelayCellTimex100 = 270/100 ps
1414 12:14:12.137262 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1415 12:14:12.143836 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1416 12:14:12.147350 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1417 12:14:12.150448 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1418 12:14:12.153893 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1419 12:14:12.157409 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1420 12:14:12.157494
1421 12:14:12.160488 CA PerBit enable=1, Macro0, CA PI delay=34
1422 12:14:12.160573
1423 12:14:12.163708 [CBTSetCACLKResult] CA Dly = 34
1424 12:14:12.163815 CS Dly: 6 (0~38)
1425 12:14:12.167126
1426 12:14:12.170524 ----->DramcWriteLeveling(PI) begin...
1427 12:14:12.170634 ==
1428 12:14:12.173892 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 12:14:12.177315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 12:14:12.177459 ==
1431 12:14:12.180268 Write leveling (Byte 0): 26 => 26
1432 12:14:12.183740 Write leveling (Byte 1): 30 => 30
1433 12:14:12.186835 DramcWriteLeveling(PI) end<-----
1434 12:14:12.186943
1435 12:14:12.187067 ==
1436 12:14:12.190410 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 12:14:12.193494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 12:14:12.193646 ==
1439 12:14:12.196954 [Gating] SW mode calibration
1440 12:14:12.204259 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1441 12:14:12.207790 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1442 12:14:12.215013 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1443 12:14:12.218463 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1444 12:14:12.222161 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 12:14:12.225753 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 12:14:12.229808 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 12:14:12.236896 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 12:14:12.240572 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 12:14:12.243710 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 12:14:12.247199 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 12:14:12.253895 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 12:14:12.256992 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:14:12.260420 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:14:12.266616 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:14:12.270123 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:14:12.273554 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:14:12.279890 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:14:12.283280 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1459 12:14:12.286914 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1460 12:14:12.293478 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1461 12:14:12.296621 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:14:12.300192 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:14:12.306375 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:14:12.309961 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:14:12.313132 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:14:12.319903 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:14:12.322967 0 9 4 | B1->B0 | 2323 2727 | 1 1 | (0 0) (0 0)
1468 12:14:12.326593 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1469 12:14:12.332753 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 12:14:12.336206 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 12:14:12.339395 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 12:14:12.346457 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 12:14:12.349545 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 12:14:12.353036 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1475 12:14:12.359398 0 10 4 | B1->B0 | 3131 2f2f | 1 0 | (1 1) (0 1)
1476 12:14:12.362936 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:14:12.365872 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:14:12.372940 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:14:12.375883 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:14:12.379168 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 12:14:12.386048 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 12:14:12.389468 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:14:12.392724 0 11 4 | B1->B0 | 2929 3232 | 0 1 | (1 1) (0 0)
1484 12:14:12.399343 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1485 12:14:12.402613 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 12:14:12.405705 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 12:14:12.412385 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 12:14:12.415445 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 12:14:12.419085 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 12:14:12.425675 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1491 12:14:12.428749 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1492 12:14:12.432406 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1493 12:14:12.438751 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 12:14:12.442323 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 12:14:12.445381 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 12:14:12.452133 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 12:14:12.455181 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 12:14:12.458616 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 12:14:12.465158 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 12:14:12.468697 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:14:12.471625 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:14:12.475050 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:14:12.481697 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:14:12.485139 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:14:12.488427 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:14:12.495345 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:14:12.498204 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1508 12:14:12.501638 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 12:14:12.504910 Total UI for P1: 0, mck2ui 16
1510 12:14:12.508480 best dqsien dly found for B0: ( 0, 14, 4)
1511 12:14:12.511691 Total UI for P1: 0, mck2ui 16
1512 12:14:12.514868 best dqsien dly found for B1: ( 0, 14, 4)
1513 12:14:12.517962 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1514 12:14:12.525009 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1515 12:14:12.525097
1516 12:14:12.528150 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1517 12:14:12.531264 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1518 12:14:12.534864 [Gating] SW calibration Done
1519 12:14:12.534950 ==
1520 12:14:12.537998 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 12:14:12.541531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1522 12:14:12.541651 ==
1523 12:14:12.541733 RX Vref Scan: 0
1524 12:14:12.544384
1525 12:14:12.544466 RX Vref 0 -> 0, step: 1
1526 12:14:12.544532
1527 12:14:12.547951 RX Delay -130 -> 252, step: 16
1528 12:14:12.551347 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1529 12:14:12.554410 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1530 12:14:12.561627 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1531 12:14:12.564652 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1532 12:14:12.567737 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1533 12:14:12.571340 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1534 12:14:12.574297 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1535 12:14:12.581335 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1536 12:14:12.584448 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1537 12:14:12.587974 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1538 12:14:12.590930 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1539 12:14:12.594393 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1540 12:14:12.601170 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1541 12:14:12.604142 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1542 12:14:12.607487 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1543 12:14:12.611109 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1544 12:14:12.611182 ==
1545 12:14:12.614109 Dram Type= 6, Freq= 0, CH_1, rank 0
1546 12:14:12.620759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1547 12:14:12.620861 ==
1548 12:14:12.620927 DQS Delay:
1549 12:14:12.624344 DQS0 = 0, DQS1 = 0
1550 12:14:12.624426 DQM Delay:
1551 12:14:12.624491 DQM0 = 89, DQM1 = 81
1552 12:14:12.627345 DQ Delay:
1553 12:14:12.630797 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1554 12:14:12.633987 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1555 12:14:12.637642 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1556 12:14:12.640614 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1557 12:14:12.640685
1558 12:14:12.640746
1559 12:14:12.640851 ==
1560 12:14:12.644289 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 12:14:12.647332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1562 12:14:12.647426 ==
1563 12:14:12.647507
1564 12:14:12.647577
1565 12:14:12.650795 TX Vref Scan disable
1566 12:14:12.653869 == TX Byte 0 ==
1567 12:14:12.657474 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1568 12:14:12.660542 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1569 12:14:12.664207 == TX Byte 1 ==
1570 12:14:12.667272 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1571 12:14:12.670765 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1572 12:14:12.670848 ==
1573 12:14:12.673840 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 12:14:12.677488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 12:14:12.680515 ==
1576 12:14:12.692093 TX Vref=22, minBit 8, minWin=27, winSum=447
1577 12:14:12.695093 TX Vref=24, minBit 8, minWin=27, winSum=451
1578 12:14:12.698623 TX Vref=26, minBit 8, minWin=27, winSum=452
1579 12:14:12.702011 TX Vref=28, minBit 15, minWin=27, winSum=457
1580 12:14:12.705203 TX Vref=30, minBit 12, minWin=27, winSum=456
1581 12:14:12.711799 TX Vref=32, minBit 8, minWin=27, winSum=455
1582 12:14:12.715153 [TxChooseVref] Worse bit 15, Min win 27, Win sum 457, Final Vref 28
1583 12:14:12.715235
1584 12:14:12.718647 Final TX Range 1 Vref 28
1585 12:14:12.718736
1586 12:14:12.718801 ==
1587 12:14:12.721766 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 12:14:12.725389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 12:14:12.728396 ==
1590 12:14:12.728472
1591 12:14:12.728535
1592 12:14:12.728595 TX Vref Scan disable
1593 12:14:12.731969 == TX Byte 0 ==
1594 12:14:12.735593 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1595 12:14:12.742069 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1596 12:14:12.742150 == TX Byte 1 ==
1597 12:14:12.745228 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1598 12:14:12.751800 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1599 12:14:12.751883
1600 12:14:12.751948 [DATLAT]
1601 12:14:12.752010 Freq=800, CH1 RK0
1602 12:14:12.752069
1603 12:14:12.755372 DATLAT Default: 0xa
1604 12:14:12.755444 0, 0xFFFF, sum = 0
1605 12:14:12.758363 1, 0xFFFF, sum = 0
1606 12:14:12.761903 2, 0xFFFF, sum = 0
1607 12:14:12.761976 3, 0xFFFF, sum = 0
1608 12:14:12.765006 4, 0xFFFF, sum = 0
1609 12:14:12.765080 5, 0xFFFF, sum = 0
1610 12:14:12.768506 6, 0xFFFF, sum = 0
1611 12:14:12.768586 7, 0xFFFF, sum = 0
1612 12:14:12.771966 8, 0xFFFF, sum = 0
1613 12:14:12.772038 9, 0x0, sum = 1
1614 12:14:12.775164 10, 0x0, sum = 2
1615 12:14:12.775236 11, 0x0, sum = 3
1616 12:14:12.775298 12, 0x0, sum = 4
1617 12:14:12.778301 best_step = 10
1618 12:14:12.778369
1619 12:14:12.778428 ==
1620 12:14:12.781869 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 12:14:12.784948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 12:14:12.785020 ==
1623 12:14:12.788922 RX Vref Scan: 1
1624 12:14:12.789048
1625 12:14:12.789152 Set Vref Range= 32 -> 127
1626 12:14:12.789222
1627 12:14:12.792397 RX Vref 32 -> 127, step: 1
1628 12:14:12.792501
1629 12:14:12.795929 RX Delay -95 -> 252, step: 8
1630 12:14:12.796003
1631 12:14:12.799179 Set Vref, RX VrefLevel [Byte0]: 32
1632 12:14:12.802267 [Byte1]: 32
1633 12:14:12.802338
1634 12:14:12.805360 Set Vref, RX VrefLevel [Byte0]: 33
1635 12:14:12.808773 [Byte1]: 33
1636 12:14:12.812519
1637 12:14:12.812627 Set Vref, RX VrefLevel [Byte0]: 34
1638 12:14:12.816523 [Byte1]: 34
1639 12:14:12.820171
1640 12:14:12.820273 Set Vref, RX VrefLevel [Byte0]: 35
1641 12:14:12.823519 [Byte1]: 35
1642 12:14:12.827622
1643 12:14:12.827737 Set Vref, RX VrefLevel [Byte0]: 36
1644 12:14:12.830735 [Byte1]: 36
1645 12:14:12.835254
1646 12:14:12.835353 Set Vref, RX VrefLevel [Byte0]: 37
1647 12:14:12.838479 [Byte1]: 37
1648 12:14:12.842827
1649 12:14:12.842927 Set Vref, RX VrefLevel [Byte0]: 38
1650 12:14:12.846057 [Byte1]: 38
1651 12:14:12.850192
1652 12:14:12.850297 Set Vref, RX VrefLevel [Byte0]: 39
1653 12:14:12.853721 [Byte1]: 39
1654 12:14:12.858108
1655 12:14:12.858224 Set Vref, RX VrefLevel [Byte0]: 40
1656 12:14:12.861198 [Byte1]: 40
1657 12:14:12.865405
1658 12:14:12.865517 Set Vref, RX VrefLevel [Byte0]: 41
1659 12:14:12.869151 [Byte1]: 41
1660 12:14:12.873244
1661 12:14:12.873320 Set Vref, RX VrefLevel [Byte0]: 42
1662 12:14:12.876587 [Byte1]: 42
1663 12:14:12.880518
1664 12:14:12.880620 Set Vref, RX VrefLevel [Byte0]: 43
1665 12:14:12.884170 [Byte1]: 43
1666 12:14:12.888171
1667 12:14:12.888258 Set Vref, RX VrefLevel [Byte0]: 44
1668 12:14:12.891511 [Byte1]: 44
1669 12:14:12.895590
1670 12:14:12.899194 Set Vref, RX VrefLevel [Byte0]: 45
1671 12:14:12.902335 [Byte1]: 45
1672 12:14:12.902415
1673 12:14:12.905424 Set Vref, RX VrefLevel [Byte0]: 46
1674 12:14:12.909064 [Byte1]: 46
1675 12:14:12.909139
1676 12:14:12.912076 Set Vref, RX VrefLevel [Byte0]: 47
1677 12:14:12.915763 [Byte1]: 47
1678 12:14:12.918748
1679 12:14:12.918831 Set Vref, RX VrefLevel [Byte0]: 48
1680 12:14:12.922083 [Byte1]: 48
1681 12:14:12.926305
1682 12:14:12.926381 Set Vref, RX VrefLevel [Byte0]: 49
1683 12:14:12.929870 [Byte1]: 49
1684 12:14:12.933838
1685 12:14:12.933908 Set Vref, RX VrefLevel [Byte0]: 50
1686 12:14:12.937482 [Byte1]: 50
1687 12:14:12.941660
1688 12:14:12.941742 Set Vref, RX VrefLevel [Byte0]: 51
1689 12:14:12.944675 [Byte1]: 51
1690 12:14:12.949324
1691 12:14:12.949407 Set Vref, RX VrefLevel [Byte0]: 52
1692 12:14:12.952360 [Byte1]: 52
1693 12:14:12.956907
1694 12:14:12.956990 Set Vref, RX VrefLevel [Byte0]: 53
1695 12:14:12.959930 [Byte1]: 53
1696 12:14:12.964341
1697 12:14:12.964451 Set Vref, RX VrefLevel [Byte0]: 54
1698 12:14:12.967532 [Byte1]: 54
1699 12:14:12.972206
1700 12:14:12.972284 Set Vref, RX VrefLevel [Byte0]: 55
1701 12:14:12.975332 [Byte1]: 55
1702 12:14:12.979366
1703 12:14:12.979448 Set Vref, RX VrefLevel [Byte0]: 56
1704 12:14:12.982940 [Byte1]: 56
1705 12:14:12.986989
1706 12:14:12.987072 Set Vref, RX VrefLevel [Byte0]: 57
1707 12:14:12.990502 [Byte1]: 57
1708 12:14:12.994468
1709 12:14:12.994544 Set Vref, RX VrefLevel [Byte0]: 58
1710 12:14:12.997982 [Byte1]: 58
1711 12:14:13.002364
1712 12:14:13.002477 Set Vref, RX VrefLevel [Byte0]: 59
1713 12:14:13.005533 [Byte1]: 59
1714 12:14:13.010324
1715 12:14:13.010396 Set Vref, RX VrefLevel [Byte0]: 60
1716 12:14:13.013507 [Byte1]: 60
1717 12:14:13.017617
1718 12:14:13.017700 Set Vref, RX VrefLevel [Byte0]: 61
1719 12:14:13.020592 [Byte1]: 61
1720 12:14:13.025219
1721 12:14:13.025344 Set Vref, RX VrefLevel [Byte0]: 62
1722 12:14:13.031521 [Byte1]: 62
1723 12:14:13.031602
1724 12:14:13.034810 Set Vref, RX VrefLevel [Byte0]: 63
1725 12:14:13.038160 [Byte1]: 63
1726 12:14:13.038245
1727 12:14:13.041559 Set Vref, RX VrefLevel [Byte0]: 64
1728 12:14:13.044978 [Byte1]: 64
1729 12:14:13.045059
1730 12:14:13.048101 Set Vref, RX VrefLevel [Byte0]: 65
1731 12:14:13.051206 [Byte1]: 65
1732 12:14:13.055413
1733 12:14:13.055498 Set Vref, RX VrefLevel [Byte0]: 66
1734 12:14:13.059088 [Byte1]: 66
1735 12:14:13.062994
1736 12:14:13.063076 Set Vref, RX VrefLevel [Byte0]: 67
1737 12:14:13.066435 [Byte1]: 67
1738 12:14:13.070612
1739 12:14:13.070693 Set Vref, RX VrefLevel [Byte0]: 68
1740 12:14:13.074267 [Byte1]: 68
1741 12:14:13.078410
1742 12:14:13.078491 Set Vref, RX VrefLevel [Byte0]: 69
1743 12:14:13.081921 [Byte1]: 69
1744 12:14:13.085807
1745 12:14:13.085950 Set Vref, RX VrefLevel [Byte0]: 70
1746 12:14:13.089354 [Byte1]: 70
1747 12:14:13.093511
1748 12:14:13.093592 Set Vref, RX VrefLevel [Byte0]: 71
1749 12:14:13.096693 [Byte1]: 71
1750 12:14:13.101325
1751 12:14:13.101434 Set Vref, RX VrefLevel [Byte0]: 72
1752 12:14:13.104143 [Byte1]: 72
1753 12:14:13.108690
1754 12:14:13.108798 Set Vref, RX VrefLevel [Byte0]: 73
1755 12:14:13.111933 [Byte1]: 73
1756 12:14:13.116104
1757 12:14:13.116205 Set Vref, RX VrefLevel [Byte0]: 74
1758 12:14:13.119721 [Byte1]: 74
1759 12:14:13.124155
1760 12:14:13.124252 Final RX Vref Byte 0 = 53 to rank0
1761 12:14:13.127268 Final RX Vref Byte 1 = 62 to rank0
1762 12:14:13.130361 Final RX Vref Byte 0 = 53 to rank1
1763 12:14:13.133927 Final RX Vref Byte 1 = 62 to rank1==
1764 12:14:13.136869 Dram Type= 6, Freq= 0, CH_1, rank 0
1765 12:14:13.143801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1766 12:14:13.143884 ==
1767 12:14:13.143950 DQS Delay:
1768 12:14:13.147010 DQS0 = 0, DQS1 = 0
1769 12:14:13.147092 DQM Delay:
1770 12:14:13.147156 DQM0 = 93, DQM1 = 83
1771 12:14:13.150267 DQ Delay:
1772 12:14:13.153831 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1773 12:14:13.156931 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1774 12:14:13.160099 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1775 12:14:13.163637 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1776 12:14:13.163718
1777 12:14:13.163782
1778 12:14:13.170204 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1779 12:14:13.173652 CH1 RK0: MR19=606, MR18=2F4C
1780 12:14:13.180317 CH1_RK0: MR19=0x606, MR18=0x2F4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1781 12:14:13.180400
1782 12:14:13.183441 ----->DramcWriteLeveling(PI) begin...
1783 12:14:13.183524 ==
1784 12:14:13.186955 Dram Type= 6, Freq= 0, CH_1, rank 1
1785 12:14:13.190534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 12:14:13.190616 ==
1787 12:14:13.193525 Write leveling (Byte 0): 27 => 27
1788 12:14:13.197178 Write leveling (Byte 1): 29 => 29
1789 12:14:13.200227 DramcWriteLeveling(PI) end<-----
1790 12:14:13.200334
1791 12:14:13.200432 ==
1792 12:14:13.203766 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 12:14:13.207051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 12:14:13.207139 ==
1795 12:14:13.210628 [Gating] SW mode calibration
1796 12:14:13.216795 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1797 12:14:13.223480 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1798 12:14:13.226413 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1799 12:14:13.233254 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1800 12:14:13.236752 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1801 12:14:13.239935 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 12:14:13.246493 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 12:14:13.249747 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 12:14:13.253339 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 12:14:13.259881 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 12:14:13.263024 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 12:14:13.266565 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 12:14:13.269593 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:14:13.276134 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:14:13.279788 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:14:13.282837 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:14:13.289534 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:14:13.293006 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:14:13.296056 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1815 12:14:13.302784 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1816 12:14:13.306354 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:14:13.309384 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:14:13.315909 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:14:13.319213 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:14:13.322831 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:14:13.329549 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:14:13.333099 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:14:13.336261 0 9 4 | B1->B0 | 2424 2323 | 1 0 | (1 1) (1 1)
1824 12:14:13.342990 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1825 12:14:13.346142 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 12:14:13.349653 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 12:14:13.356184 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 12:14:13.359132 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 12:14:13.362569 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 12:14:13.369323 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1831 12:14:13.372333 0 10 4 | B1->B0 | 2f2f 3030 | 0 1 | (0 0) (1 0)
1832 12:14:13.375985 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 0)
1833 12:14:13.382370 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:14:13.385846 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:14:13.389000 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:14:13.395678 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:14:13.399154 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:14:13.402198 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:14:13.408840 0 11 4 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
1840 12:14:13.412067 0 11 8 | B1->B0 | 4343 3f3f | 0 0 | (0 0) (0 0)
1841 12:14:13.415381 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 12:14:13.422439 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 12:14:13.425631 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 12:14:13.429220 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 12:14:13.435388 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 12:14:13.438918 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 12:14:13.441878 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1848 12:14:13.445550 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1849 12:14:13.452032 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 12:14:13.455440 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 12:14:13.458499 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 12:14:13.465622 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 12:14:13.468593 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 12:14:13.471791 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 12:14:13.478964 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 12:14:13.481867 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:14:13.485501 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:14:13.491805 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:14:13.495368 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:14:13.498362 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:14:13.505436 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:14:13.508466 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1863 12:14:13.511547 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1864 12:14:13.515195 Total UI for P1: 0, mck2ui 16
1865 12:14:13.518652 best dqsien dly found for B1: ( 0, 14, 0)
1866 12:14:13.525128 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 12:14:13.525225 Total UI for P1: 0, mck2ui 16
1868 12:14:13.531639 best dqsien dly found for B0: ( 0, 14, 4)
1869 12:14:13.535294 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1870 12:14:13.538334 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1871 12:14:13.538454
1872 12:14:13.541863 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1873 12:14:13.544872 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1874 12:14:13.548662 [Gating] SW calibration Done
1875 12:14:13.548771 ==
1876 12:14:13.551766 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 12:14:13.554951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1878 12:14:13.555058 ==
1879 12:14:13.558481 RX Vref Scan: 0
1880 12:14:13.558593
1881 12:14:13.558702 RX Vref 0 -> 0, step: 1
1882 12:14:13.558797
1883 12:14:13.561612 RX Delay -130 -> 252, step: 16
1884 12:14:13.565116 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1885 12:14:13.571465 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1886 12:14:13.574915 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1887 12:14:13.578327 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1888 12:14:13.581378 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1889 12:14:13.584848 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1890 12:14:13.591432 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1891 12:14:13.594606 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1892 12:14:13.598310 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1893 12:14:13.601458 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1894 12:14:13.604582 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1895 12:14:13.611449 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1896 12:14:13.614679 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1897 12:14:13.618386 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1898 12:14:13.621500 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1899 12:14:13.624784 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1900 12:14:13.627893 ==
1901 12:14:13.631469 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 12:14:13.634607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 12:14:13.634709 ==
1904 12:14:13.634800 DQS Delay:
1905 12:14:13.637857 DQS0 = 0, DQS1 = 0
1906 12:14:13.637956 DQM Delay:
1907 12:14:13.641447 DQM0 = 90, DQM1 = 84
1908 12:14:13.641547 DQ Delay:
1909 12:14:13.644776 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1910 12:14:13.647893 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1911 12:14:13.651577 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1912 12:14:13.654492 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1913 12:14:13.654593
1914 12:14:13.654683
1915 12:14:13.654775 ==
1916 12:14:13.658055 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 12:14:13.661134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 12:14:13.661240 ==
1919 12:14:13.661332
1920 12:14:13.661423
1921 12:14:13.664681 TX Vref Scan disable
1922 12:14:13.667800 == TX Byte 0 ==
1923 12:14:13.671429 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1924 12:14:13.674913 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1925 12:14:13.678180 == TX Byte 1 ==
1926 12:14:13.681142 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1927 12:14:13.684565 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1928 12:14:13.684682 ==
1929 12:14:13.688066 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 12:14:13.694390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 12:14:13.694491 ==
1932 12:14:13.705582 TX Vref=22, minBit 9, minWin=27, winSum=449
1933 12:14:13.709191 TX Vref=24, minBit 13, minWin=27, winSum=455
1934 12:14:13.712546 TX Vref=26, minBit 13, minWin=27, winSum=456
1935 12:14:13.715990 TX Vref=28, minBit 8, minWin=28, winSum=459
1936 12:14:13.719182 TX Vref=30, minBit 8, minWin=28, winSum=462
1937 12:14:13.725870 TX Vref=32, minBit 9, minWin=27, winSum=456
1938 12:14:13.729392 [TxChooseVref] Worse bit 8, Min win 28, Win sum 462, Final Vref 30
1939 12:14:13.729503
1940 12:14:13.732537 Final TX Range 1 Vref 30
1941 12:14:13.732637
1942 12:14:13.732729 ==
1943 12:14:13.735708 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 12:14:13.739300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 12:14:13.739400 ==
1946 12:14:13.742512
1947 12:14:13.742611
1948 12:14:13.742703 TX Vref Scan disable
1949 12:14:13.746054 == TX Byte 0 ==
1950 12:14:13.749060 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1951 12:14:13.755596 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1952 12:14:13.755701 == TX Byte 1 ==
1953 12:14:13.759291 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1954 12:14:13.765933 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1955 12:14:13.766040
1956 12:14:13.766132 [DATLAT]
1957 12:14:13.766227 Freq=800, CH1 RK1
1958 12:14:13.766317
1959 12:14:13.769075 DATLAT Default: 0xa
1960 12:14:13.769196 0, 0xFFFF, sum = 0
1961 12:14:13.772570 1, 0xFFFF, sum = 0
1962 12:14:13.772672 2, 0xFFFF, sum = 0
1963 12:14:13.775525 3, 0xFFFF, sum = 0
1964 12:14:13.779100 4, 0xFFFF, sum = 0
1965 12:14:13.779203 5, 0xFFFF, sum = 0
1966 12:14:13.782489 6, 0xFFFF, sum = 0
1967 12:14:13.782615 7, 0xFFFF, sum = 0
1968 12:14:13.785969 8, 0xFFFF, sum = 0
1969 12:14:13.786091 9, 0x0, sum = 1
1970 12:14:13.788911 10, 0x0, sum = 2
1971 12:14:13.789019 11, 0x0, sum = 3
1972 12:14:13.789161 12, 0x0, sum = 4
1973 12:14:13.792332 best_step = 10
1974 12:14:13.792451
1975 12:14:13.792573 ==
1976 12:14:13.795688 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 12:14:13.798947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 12:14:13.799092 ==
1979 12:14:13.802142 RX Vref Scan: 0
1980 12:14:13.802252
1981 12:14:13.802347 RX Vref 0 -> 0, step: 1
1982 12:14:13.805838
1983 12:14:13.805943 RX Delay -95 -> 252, step: 8
1984 12:14:13.812456 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
1985 12:14:13.815841 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
1986 12:14:13.819123 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
1987 12:14:13.822624 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1988 12:14:13.825583 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
1989 12:14:13.832541 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1990 12:14:13.835689 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1991 12:14:13.838869 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
1992 12:14:13.842575 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1993 12:14:13.845745 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1994 12:14:13.852359 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
1995 12:14:13.856058 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
1996 12:14:13.859073 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1997 12:14:13.862719 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1998 12:14:13.865671 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1999 12:14:13.872184 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2000 12:14:13.872292 ==
2001 12:14:13.875830 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 12:14:13.878852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 12:14:13.878960 ==
2004 12:14:13.879055 DQS Delay:
2005 12:14:13.882411 DQS0 = 0, DQS1 = 0
2006 12:14:13.882510 DQM Delay:
2007 12:14:13.885997 DQM0 = 92, DQM1 = 85
2008 12:14:13.886098 DQ Delay:
2009 12:14:13.889006 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2010 12:14:13.892409 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2011 12:14:13.895833 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2012 12:14:13.898987 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =96
2013 12:14:13.899094
2014 12:14:13.899174
2015 12:14:13.905429 [DQSOSCAuto] RK1, (LSB)MR18= 0x370d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2016 12:14:13.908957 CH1 RK1: MR19=606, MR18=370D
2017 12:14:13.915636 CH1_RK1: MR19=0x606, MR18=0x370D, DQSOSC=395, MR23=63, INC=94, DEC=63
2018 12:14:13.918813 [RxdqsGatingPostProcess] freq 800
2019 12:14:13.925381 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2020 12:14:13.928511 Pre-setting of DQS Precalculation
2021 12:14:13.932215 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2022 12:14:13.938866 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2023 12:14:13.945231 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2024 12:14:13.948711
2025 12:14:13.948821
2026 12:14:13.948889 [Calibration Summary] 1600 Mbps
2027 12:14:13.951836 CH 0, Rank 0
2028 12:14:13.951932 SW Impedance : PASS
2029 12:14:13.955320 DUTY Scan : NO K
2030 12:14:13.958360 ZQ Calibration : PASS
2031 12:14:13.958458 Jitter Meter : NO K
2032 12:14:13.961889 CBT Training : PASS
2033 12:14:13.964992 Write leveling : PASS
2034 12:14:13.965065 RX DQS gating : PASS
2035 12:14:13.968602 RX DQ/DQS(RDDQC) : PASS
2036 12:14:13.972106 TX DQ/DQS : PASS
2037 12:14:13.972204 RX DATLAT : PASS
2038 12:14:13.974983 RX DQ/DQS(Engine): PASS
2039 12:14:13.978739 TX OE : NO K
2040 12:14:13.978810 All Pass.
2041 12:14:13.978869
2042 12:14:13.978927 CH 0, Rank 1
2043 12:14:13.981697 SW Impedance : PASS
2044 12:14:13.985310 DUTY Scan : NO K
2045 12:14:13.985378 ZQ Calibration : PASS
2046 12:14:13.988515 Jitter Meter : NO K
2047 12:14:13.992143 CBT Training : PASS
2048 12:14:13.992212 Write leveling : PASS
2049 12:14:13.995204 RX DQS gating : PASS
2050 12:14:13.995299 RX DQ/DQS(RDDQC) : PASS
2051 12:14:13.998541 TX DQ/DQS : PASS
2052 12:14:14.001856 RX DATLAT : PASS
2053 12:14:14.001951 RX DQ/DQS(Engine): PASS
2054 12:14:14.005248 TX OE : NO K
2055 12:14:14.005317 All Pass.
2056 12:14:14.005377
2057 12:14:14.008468 CH 1, Rank 0
2058 12:14:14.008561 SW Impedance : PASS
2059 12:14:14.011655 DUTY Scan : NO K
2060 12:14:14.014974 ZQ Calibration : PASS
2061 12:14:14.015069 Jitter Meter : NO K
2062 12:14:14.018688 CBT Training : PASS
2063 12:14:14.021837 Write leveling : PASS
2064 12:14:14.021932 RX DQS gating : PASS
2065 12:14:14.025429 RX DQ/DQS(RDDQC) : PASS
2066 12:14:14.028462 TX DQ/DQS : PASS
2067 12:14:14.028556 RX DATLAT : PASS
2068 12:14:14.032044 RX DQ/DQS(Engine): PASS
2069 12:14:14.035170 TX OE : NO K
2070 12:14:14.035272 All Pass.
2071 12:14:14.035362
2072 12:14:14.035448 CH 1, Rank 1
2073 12:14:14.038642 SW Impedance : PASS
2074 12:14:14.041499 DUTY Scan : NO K
2075 12:14:14.041598 ZQ Calibration : PASS
2076 12:14:14.045166 Jitter Meter : NO K
2077 12:14:14.045268 CBT Training : PASS
2078 12:14:14.048314 Write leveling : PASS
2079 12:14:14.051928 RX DQS gating : PASS
2080 12:14:14.052031 RX DQ/DQS(RDDQC) : PASS
2081 12:14:14.055039 TX DQ/DQS : PASS
2082 12:14:14.058529 RX DATLAT : PASS
2083 12:14:14.058629 RX DQ/DQS(Engine): PASS
2084 12:14:14.061874 TX OE : NO K
2085 12:14:14.061971 All Pass.
2086 12:14:14.062059
2087 12:14:14.064922 DramC Write-DBI off
2088 12:14:14.068173 PER_BANK_REFRESH: Hybrid Mode
2089 12:14:14.068282 TX_TRACKING: ON
2090 12:14:14.071478 [GetDramInforAfterCalByMRR] Vendor 6.
2091 12:14:14.075168 [GetDramInforAfterCalByMRR] Revision 606.
2092 12:14:14.078144 [GetDramInforAfterCalByMRR] Revision 2 0.
2093 12:14:14.081672 MR0 0x3b3b
2094 12:14:14.081798 MR8 0x5151
2095 12:14:14.084697 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2096 12:14:14.084822
2097 12:14:14.088403 MR0 0x3b3b
2098 12:14:14.088501 MR8 0x5151
2099 12:14:14.091518 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 12:14:14.091618
2101 12:14:14.101367 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2102 12:14:14.104672 [FAST_K] Save calibration result to emmc
2103 12:14:14.108234 [FAST_K] Save calibration result to emmc
2104 12:14:14.111441 dram_init: config_dvfs: 1
2105 12:14:14.114493 dramc_set_vcore_voltage set vcore to 662500
2106 12:14:14.114602 Read voltage for 1200, 2
2107 12:14:14.117907 Vio18 = 0
2108 12:14:14.118015 Vcore = 662500
2109 12:14:14.118123 Vdram = 0
2110 12:14:14.121508 Vddq = 0
2111 12:14:14.121609 Vmddr = 0
2112 12:14:14.124454 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2113 12:14:14.131102 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2114 12:14:14.134612 MEM_TYPE=3, freq_sel=15
2115 12:14:14.137695 sv_algorithm_assistance_LP4_1600
2116 12:14:14.141343 ============ PULL DRAM RESETB DOWN ============
2117 12:14:14.144302 ========== PULL DRAM RESETB DOWN end =========
2118 12:14:14.150935 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2119 12:14:14.154118 ===================================
2120 12:14:14.154226 LPDDR4 DRAM CONFIGURATION
2121 12:14:14.157835 ===================================
2122 12:14:14.160936 EX_ROW_EN[0] = 0x0
2123 12:14:14.161067 EX_ROW_EN[1] = 0x0
2124 12:14:14.164389 LP4Y_EN = 0x0
2125 12:14:14.164487 WORK_FSP = 0x0
2126 12:14:14.167425 WL = 0x4
2127 12:14:14.171001 RL = 0x4
2128 12:14:14.171100 BL = 0x2
2129 12:14:14.174531 RPST = 0x0
2130 12:14:14.174634 RD_PRE = 0x0
2131 12:14:14.177651 WR_PRE = 0x1
2132 12:14:14.177762 WR_PST = 0x0
2133 12:14:14.180686 DBI_WR = 0x0
2134 12:14:14.180831 DBI_RD = 0x0
2135 12:14:14.184124 OTF = 0x1
2136 12:14:14.187598 ===================================
2137 12:14:14.190698 ===================================
2138 12:14:14.190798 ANA top config
2139 12:14:14.194251 ===================================
2140 12:14:14.197261 DLL_ASYNC_EN = 0
2141 12:14:14.200841 ALL_SLAVE_EN = 0
2142 12:14:14.200958 NEW_RANK_MODE = 1
2143 12:14:14.203999 DLL_IDLE_MODE = 1
2144 12:14:14.207443 LP45_APHY_COMB_EN = 1
2145 12:14:14.210818 TX_ODT_DIS = 1
2146 12:14:14.214067 NEW_8X_MODE = 1
2147 12:14:14.217571 ===================================
2148 12:14:14.220609 ===================================
2149 12:14:14.220710 data_rate = 2400
2150 12:14:14.224099 CKR = 1
2151 12:14:14.227448 DQ_P2S_RATIO = 8
2152 12:14:14.230341 ===================================
2153 12:14:14.233857 CA_P2S_RATIO = 8
2154 12:14:14.237425 DQ_CA_OPEN = 0
2155 12:14:14.240492 DQ_SEMI_OPEN = 0
2156 12:14:14.240596 CA_SEMI_OPEN = 0
2157 12:14:14.244135 CA_FULL_RATE = 0
2158 12:14:14.247078 DQ_CKDIV4_EN = 0
2159 12:14:14.250603 CA_CKDIV4_EN = 0
2160 12:14:14.253643 CA_PREDIV_EN = 0
2161 12:14:14.257184 PH8_DLY = 17
2162 12:14:14.257263 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2163 12:14:14.260681 DQ_AAMCK_DIV = 4
2164 12:14:14.263945 CA_AAMCK_DIV = 4
2165 12:14:14.267417 CA_ADMCK_DIV = 4
2166 12:14:14.270666 DQ_TRACK_CA_EN = 0
2167 12:14:14.273702 CA_PICK = 1200
2168 12:14:14.273777 CA_MCKIO = 1200
2169 12:14:14.277423 MCKIO_SEMI = 0
2170 12:14:14.280636 PLL_FREQ = 2366
2171 12:14:14.284129 DQ_UI_PI_RATIO = 32
2172 12:14:14.287140 CA_UI_PI_RATIO = 0
2173 12:14:14.290125 ===================================
2174 12:14:14.293670 ===================================
2175 12:14:14.296861 memory_type:LPDDR4
2176 12:14:14.296930 GP_NUM : 10
2177 12:14:14.299955 SRAM_EN : 1
2178 12:14:14.303644 MD32_EN : 0
2179 12:14:14.306675 ===================================
2180 12:14:14.306742 [ANA_INIT] >>>>>>>>>>>>>>
2181 12:14:14.310236 <<<<<< [CONFIGURE PHASE]: ANA_TX
2182 12:14:14.313657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2183 12:14:14.317005 ===================================
2184 12:14:14.320218 data_rate = 2400,PCW = 0X5b00
2185 12:14:14.323500 ===================================
2186 12:14:14.326967 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2187 12:14:14.333464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2188 12:14:14.336914 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2189 12:14:14.343495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2190 12:14:14.346537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2191 12:14:14.350188 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2192 12:14:14.350294 [ANA_INIT] flow start
2193 12:14:14.353167 [ANA_INIT] PLL >>>>>>>>
2194 12:14:14.356690 [ANA_INIT] PLL <<<<<<<<
2195 12:14:14.356806 [ANA_INIT] MIDPI >>>>>>>>
2196 12:14:14.359916 [ANA_INIT] MIDPI <<<<<<<<
2197 12:14:14.363474 [ANA_INIT] DLL >>>>>>>>
2198 12:14:14.366645 [ANA_INIT] DLL <<<<<<<<
2199 12:14:14.366740 [ANA_INIT] flow end
2200 12:14:14.370175 ============ LP4 DIFF to SE enter ============
2201 12:14:14.376589 ============ LP4 DIFF to SE exit ============
2202 12:14:14.376689 [ANA_INIT] <<<<<<<<<<<<<
2203 12:14:14.380188 [Flow] Enable top DCM control >>>>>
2204 12:14:14.383238 [Flow] Enable top DCM control <<<<<
2205 12:14:14.386370 Enable DLL master slave shuffle
2206 12:14:14.393409 ==============================================================
2207 12:14:14.393488 Gating Mode config
2208 12:14:14.400157 ==============================================================
2209 12:14:14.403223 Config description:
2210 12:14:14.409927 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2211 12:14:14.416164 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2212 12:14:14.422780 SELPH_MODE 0: By rank 1: By Phase
2213 12:14:14.429480 ==============================================================
2214 12:14:14.432698 GAT_TRACK_EN = 1
2215 12:14:14.432815 RX_GATING_MODE = 2
2216 12:14:14.436123 RX_GATING_TRACK_MODE = 2
2217 12:14:14.439460 SELPH_MODE = 1
2218 12:14:14.442805 PICG_EARLY_EN = 1
2219 12:14:14.446131 VALID_LAT_VALUE = 1
2220 12:14:14.452853 ==============================================================
2221 12:14:14.455911 Enter into Gating configuration >>>>
2222 12:14:14.459363 Exit from Gating configuration <<<<
2223 12:14:14.462482 Enter into DVFS_PRE_config >>>>>
2224 12:14:14.472683 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2225 12:14:14.476106 Exit from DVFS_PRE_config <<<<<
2226 12:14:14.479248 Enter into PICG configuration >>>>
2227 12:14:14.482377 Exit from PICG configuration <<<<
2228 12:14:14.485918 [RX_INPUT] configuration >>>>>
2229 12:14:14.489077 [RX_INPUT] configuration <<<<<
2230 12:14:14.492563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2231 12:14:14.499107 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2232 12:14:14.505760 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 12:14:14.508907 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 12:14:14.515706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 12:14:14.522278 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 12:14:14.525895 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2237 12:14:14.532271 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2238 12:14:14.535412 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2239 12:14:14.538807 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2240 12:14:14.542051 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2241 12:14:14.548746 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2242 12:14:14.552045 ===================================
2243 12:14:14.552124 LPDDR4 DRAM CONFIGURATION
2244 12:14:14.555298 ===================================
2245 12:14:14.558863 EX_ROW_EN[0] = 0x0
2246 12:14:14.562264 EX_ROW_EN[1] = 0x0
2247 12:14:14.562365 LP4Y_EN = 0x0
2248 12:14:14.565382 WORK_FSP = 0x0
2249 12:14:14.565455 WL = 0x4
2250 12:14:14.568436 RL = 0x4
2251 12:14:14.568530 BL = 0x2
2252 12:14:14.572100 RPST = 0x0
2253 12:14:14.572195 RD_PRE = 0x0
2254 12:14:14.575172 WR_PRE = 0x1
2255 12:14:14.575272 WR_PST = 0x0
2256 12:14:14.578790 DBI_WR = 0x0
2257 12:14:14.578891 DBI_RD = 0x0
2258 12:14:14.582119 OTF = 0x1
2259 12:14:14.585416 ===================================
2260 12:14:14.588483 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2261 12:14:14.592184 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2262 12:14:14.598708 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2263 12:14:14.602138 ===================================
2264 12:14:14.602211 LPDDR4 DRAM CONFIGURATION
2265 12:14:14.605185 ===================================
2266 12:14:14.608631 EX_ROW_EN[0] = 0x10
2267 12:14:14.612261 EX_ROW_EN[1] = 0x0
2268 12:14:14.612362 LP4Y_EN = 0x0
2269 12:14:14.615456 WORK_FSP = 0x0
2270 12:14:14.615529 WL = 0x4
2271 12:14:14.618614 RL = 0x4
2272 12:14:14.618686 BL = 0x2
2273 12:14:14.621976 RPST = 0x0
2274 12:14:14.622050 RD_PRE = 0x0
2275 12:14:14.625294 WR_PRE = 0x1
2276 12:14:14.625370 WR_PST = 0x0
2277 12:14:14.628387 DBI_WR = 0x0
2278 12:14:14.628456 DBI_RD = 0x0
2279 12:14:14.632032 OTF = 0x1
2280 12:14:14.635219 ===================================
2281 12:14:14.641832 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2282 12:14:14.641936 ==
2283 12:14:14.645339 Dram Type= 6, Freq= 0, CH_0, rank 0
2284 12:14:14.648338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2285 12:14:14.648441 ==
2286 12:14:14.651724 [Duty_Offset_Calibration]
2287 12:14:14.651829 B0:2 B1:0 CA:1
2288 12:14:14.651958
2289 12:14:14.655161 [DutyScan_Calibration_Flow] k_type=0
2290 12:14:14.664325
2291 12:14:14.664453 ==CLK 0==
2292 12:14:14.667782 Final CLK duty delay cell = -4
2293 12:14:14.670797 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2294 12:14:14.674370 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2295 12:14:14.677441 [-4] AVG Duty = 4953%(X100)
2296 12:14:14.677538
2297 12:14:14.680939 CH0 CLK Duty spec in!! Max-Min= 156%
2298 12:14:14.684084 [DutyScan_Calibration_Flow] ====Done====
2299 12:14:14.684178
2300 12:14:14.687606 [DutyScan_Calibration_Flow] k_type=1
2301 12:14:14.702970
2302 12:14:14.703042 ==DQS 0 ==
2303 12:14:14.706520 Final DQS duty delay cell = 0
2304 12:14:14.709644 [0] MAX Duty = 5187%(X100), DQS PI = 30
2305 12:14:14.713225 [0] MIN Duty = 4938%(X100), DQS PI = 0
2306 12:14:14.716302 [0] AVG Duty = 5062%(X100)
2307 12:14:14.716373
2308 12:14:14.716464 ==DQS 1 ==
2309 12:14:14.719495 Final DQS duty delay cell = -4
2310 12:14:14.723111 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2311 12:14:14.726575 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2312 12:14:14.729721 [-4] AVG Duty = 5031%(X100)
2313 12:14:14.729788
2314 12:14:14.732842 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2315 12:14:14.732908
2316 12:14:14.736079 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2317 12:14:14.739614 [DutyScan_Calibration_Flow] ====Done====
2318 12:14:14.739694
2319 12:14:14.742699 [DutyScan_Calibration_Flow] k_type=3
2320 12:14:14.758960
2321 12:14:14.759059 ==DQM 0 ==
2322 12:14:14.762397 Final DQM duty delay cell = 0
2323 12:14:14.766050 [0] MAX Duty = 5062%(X100), DQS PI = 24
2324 12:14:14.769079 [0] MIN Duty = 4813%(X100), DQS PI = 2
2325 12:14:14.772086 [0] AVG Duty = 4937%(X100)
2326 12:14:14.772155
2327 12:14:14.772213 ==DQM 1 ==
2328 12:14:14.775815 Final DQM duty delay cell = -4
2329 12:14:14.778801 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2330 12:14:14.782432 [-4] MIN Duty = 4813%(X100), DQS PI = 14
2331 12:14:14.785456 [-4] AVG Duty = 4906%(X100)
2332 12:14:14.785548
2333 12:14:14.789128 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2334 12:14:14.789198
2335 12:14:14.792136 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2336 12:14:14.795640 [DutyScan_Calibration_Flow] ====Done====
2337 12:14:14.795711
2338 12:14:14.798788 [DutyScan_Calibration_Flow] k_type=2
2339 12:14:14.816044
2340 12:14:14.816127 ==DQ 0 ==
2341 12:14:14.819191 Final DQ duty delay cell = -4
2342 12:14:14.822243 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2343 12:14:14.825933 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2344 12:14:14.829096 [-4] AVG Duty = 4968%(X100)
2345 12:14:14.829190
2346 12:14:14.829269 ==DQ 1 ==
2347 12:14:14.832683 Final DQ duty delay cell = 4
2348 12:14:14.835920 [4] MAX Duty = 5093%(X100), DQS PI = 4
2349 12:14:14.839007 [4] MIN Duty = 5031%(X100), DQS PI = 0
2350 12:14:14.842592 [4] AVG Duty = 5062%(X100)
2351 12:14:14.842662
2352 12:14:14.845723 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2353 12:14:14.845804
2354 12:14:14.849346 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2355 12:14:14.852496 [DutyScan_Calibration_Flow] ====Done====
2356 12:14:14.852596 ==
2357 12:14:14.855631 Dram Type= 6, Freq= 0, CH_1, rank 0
2358 12:14:14.858813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 12:14:14.858908 ==
2360 12:14:14.862384 [Duty_Offset_Calibration]
2361 12:14:14.862479 B0:0 B1:-1 CA:2
2362 12:14:14.862570
2363 12:14:14.865631 [DutyScan_Calibration_Flow] k_type=0
2364 12:14:14.876235
2365 12:14:14.876310 ==CLK 0==
2366 12:14:14.879327 Final CLK duty delay cell = 0
2367 12:14:14.882701 [0] MAX Duty = 5156%(X100), DQS PI = 16
2368 12:14:14.886315 [0] MIN Duty = 4938%(X100), DQS PI = 44
2369 12:14:14.889374 [0] AVG Duty = 5047%(X100)
2370 12:14:14.889441
2371 12:14:14.892511 CH1 CLK Duty spec in!! Max-Min= 218%
2372 12:14:14.896160 [DutyScan_Calibration_Flow] ====Done====
2373 12:14:14.896236
2374 12:14:14.899139 [DutyScan_Calibration_Flow] k_type=1
2375 12:14:14.915520
2376 12:14:14.915651 ==DQS 0 ==
2377 12:14:14.918662 Final DQS duty delay cell = 0
2378 12:14:14.922396 [0] MAX Duty = 5093%(X100), DQS PI = 22
2379 12:14:14.925473 [0] MIN Duty = 4969%(X100), DQS PI = 0
2380 12:14:14.928510 [0] AVG Duty = 5031%(X100)
2381 12:14:14.928608
2382 12:14:14.928700 ==DQS 1 ==
2383 12:14:14.932157 Final DQS duty delay cell = 0
2384 12:14:14.935244 [0] MAX Duty = 5156%(X100), DQS PI = 0
2385 12:14:14.938760 [0] MIN Duty = 4844%(X100), DQS PI = 36
2386 12:14:14.941893 [0] AVG Duty = 5000%(X100)
2387 12:14:14.941988
2388 12:14:14.945459 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2389 12:14:14.945533
2390 12:14:14.948597 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2391 12:14:14.951719 [DutyScan_Calibration_Flow] ====Done====
2392 12:14:14.951815
2393 12:14:14.955157 [DutyScan_Calibration_Flow] k_type=3
2394 12:14:14.972718
2395 12:14:14.972832 ==DQM 0 ==
2396 12:14:14.976131 Final DQM duty delay cell = 4
2397 12:14:14.979436 [4] MAX Duty = 5093%(X100), DQS PI = 20
2398 12:14:14.982368 [4] MIN Duty = 4938%(X100), DQS PI = 48
2399 12:14:14.985783 [4] AVG Duty = 5015%(X100)
2400 12:14:14.985857
2401 12:14:14.985917 ==DQM 1 ==
2402 12:14:14.989029 Final DQM duty delay cell = 0
2403 12:14:14.992431 [0] MAX Duty = 5249%(X100), DQS PI = 0
2404 12:14:14.995947 [0] MIN Duty = 4907%(X100), DQS PI = 36
2405 12:14:14.999416 [0] AVG Duty = 5078%(X100)
2406 12:14:14.999513
2407 12:14:15.002638 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2408 12:14:15.002732
2409 12:14:15.006157 CH1 DQM 1 Duty spec in!! Max-Min= 342%
2410 12:14:15.009206 [DutyScan_Calibration_Flow] ====Done====
2411 12:14:15.009275
2412 12:14:15.012361 [DutyScan_Calibration_Flow] k_type=2
2413 12:14:15.029084
2414 12:14:15.029161 ==DQ 0 ==
2415 12:14:15.032736 Final DQ duty delay cell = 0
2416 12:14:15.035819 [0] MAX Duty = 5062%(X100), DQS PI = 20
2417 12:14:15.039415 [0] MIN Duty = 4938%(X100), DQS PI = 46
2418 12:14:15.039512 [0] AVG Duty = 5000%(X100)
2419 12:14:15.042517
2420 12:14:15.042611 ==DQ 1 ==
2421 12:14:15.046171 Final DQ duty delay cell = 0
2422 12:14:15.049221 [0] MAX Duty = 5031%(X100), DQS PI = 2
2423 12:14:15.052737 [0] MIN Duty = 4813%(X100), DQS PI = 34
2424 12:14:15.052841 [0] AVG Duty = 4922%(X100)
2425 12:14:15.052905
2426 12:14:15.056183 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2427 12:14:15.056282
2428 12:14:15.059159 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2429 12:14:15.065965 [DutyScan_Calibration_Flow] ====Done====
2430 12:14:15.069144 nWR fixed to 30
2431 12:14:15.069239 [ModeRegInit_LP4] CH0 RK0
2432 12:14:15.072204 [ModeRegInit_LP4] CH0 RK1
2433 12:14:15.075644 [ModeRegInit_LP4] CH1 RK0
2434 12:14:15.075717 [ModeRegInit_LP4] CH1 RK1
2435 12:14:15.079270 match AC timing 7
2436 12:14:15.082359 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2437 12:14:15.088919 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2438 12:14:15.092351 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2439 12:14:15.095559 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2440 12:14:15.102277 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2441 12:14:15.102403 ==
2442 12:14:15.105820 Dram Type= 6, Freq= 0, CH_0, rank 0
2443 12:14:15.108971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2444 12:14:15.109076 ==
2445 12:14:15.115786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2446 12:14:15.122401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2447 12:14:15.129039 [CA 0] Center 38 (8~69) winsize 62
2448 12:14:15.132484 [CA 1] Center 38 (8~69) winsize 62
2449 12:14:15.135537 [CA 2] Center 35 (5~66) winsize 62
2450 12:14:15.139204 [CA 3] Center 35 (4~66) winsize 63
2451 12:14:15.142234 [CA 4] Center 34 (4~65) winsize 62
2452 12:14:15.145744 [CA 5] Center 33 (3~63) winsize 61
2453 12:14:15.145826
2454 12:14:15.148815 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2455 12:14:15.148898
2456 12:14:15.152425 [CATrainingPosCal] consider 1 rank data
2457 12:14:15.155567 u2DelayCellTimex100 = 270/100 ps
2458 12:14:15.159021 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2459 12:14:15.165363 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2460 12:14:15.169106 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2461 12:14:15.172213 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2462 12:14:15.175306 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2463 12:14:15.178786 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2464 12:14:15.178870
2465 12:14:15.182351 CA PerBit enable=1, Macro0, CA PI delay=33
2466 12:14:15.182434
2467 12:14:15.185356 [CBTSetCACLKResult] CA Dly = 33
2468 12:14:15.185439 CS Dly: 6 (0~37)
2469 12:14:15.188908 ==
2470 12:14:15.192273 Dram Type= 6, Freq= 0, CH_0, rank 1
2471 12:14:15.195605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2472 12:14:15.195689 ==
2473 12:14:15.198906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2474 12:14:15.205441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2475 12:14:15.214668 [CA 0] Center 39 (8~70) winsize 63
2476 12:14:15.218363 [CA 1] Center 38 (8~69) winsize 62
2477 12:14:15.221373 [CA 2] Center 35 (5~66) winsize 62
2478 12:14:15.224896 [CA 3] Center 35 (5~66) winsize 62
2479 12:14:15.227937 [CA 4] Center 34 (4~65) winsize 62
2480 12:14:15.231600 [CA 5] Center 34 (4~64) winsize 61
2481 12:14:15.231683
2482 12:14:15.234627 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2483 12:14:15.234709
2484 12:14:15.238370 [CATrainingPosCal] consider 2 rank data
2485 12:14:15.241437 u2DelayCellTimex100 = 270/100 ps
2486 12:14:15.244865 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2487 12:14:15.247970 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2488 12:14:15.254673 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2489 12:14:15.257722 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2490 12:14:15.261357 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2491 12:14:15.264589 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2492 12:14:15.264696
2493 12:14:15.268200 CA PerBit enable=1, Macro0, CA PI delay=33
2494 12:14:15.268283
2495 12:14:15.271113 [CBTSetCACLKResult] CA Dly = 33
2496 12:14:15.271196 CS Dly: 7 (0~39)
2497 12:14:15.271278
2498 12:14:15.274732 ----->DramcWriteLeveling(PI) begin...
2499 12:14:15.277886 ==
2500 12:14:15.281485 Dram Type= 6, Freq= 0, CH_0, rank 0
2501 12:14:15.284530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2502 12:14:15.284638 ==
2503 12:14:15.287668 Write leveling (Byte 0): 34 => 34
2504 12:14:15.291444 Write leveling (Byte 1): 31 => 31
2505 12:14:15.294507 DramcWriteLeveling(PI) end<-----
2506 12:14:15.294592
2507 12:14:15.294687 ==
2508 12:14:15.298000 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 12:14:15.301013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 12:14:15.301097 ==
2511 12:14:15.304528 [Gating] SW mode calibration
2512 12:14:15.311211 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2513 12:14:15.317838 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2514 12:14:15.321377 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2515 12:14:15.324378 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
2516 12:14:15.331282 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 12:14:15.334386 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 12:14:15.338121 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 12:14:15.341155 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 12:14:15.347879 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2521 12:14:15.351154 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2522 12:14:15.354634 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2523 12:14:15.361331 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 12:14:15.364497 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 12:14:15.367566 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 12:14:15.374479 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 12:14:15.377751 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 12:14:15.380796 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2529 12:14:15.387896 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2530 12:14:15.390911 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (1 1) (0 0)
2531 12:14:15.394605 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2532 12:14:15.401018 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 12:14:15.404194 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 12:14:15.407897 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 12:14:15.414340 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 12:14:15.417814 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 12:14:15.421132 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2538 12:14:15.427602 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2539 12:14:15.430722 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 12:14:15.434208 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 12:14:15.440817 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 12:14:15.444472 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 12:14:15.447458 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 12:14:15.454183 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 12:14:15.457280 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 12:14:15.460703 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 12:14:15.464269 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:14:15.470467 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:14:15.474247 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:14:15.480583 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:14:15.483802 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:14:15.486820 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2553 12:14:15.490441 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2554 12:14:15.497106 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2555 12:14:15.500596 Total UI for P1: 0, mck2ui 16
2556 12:14:15.503590 best dqsien dly found for B0: ( 1, 3, 26)
2557 12:14:15.506856 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 12:14:15.510356 Total UI for P1: 0, mck2ui 16
2559 12:14:15.513888 best dqsien dly found for B1: ( 1, 4, 0)
2560 12:14:15.516884 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2561 12:14:15.520310 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2562 12:14:15.520409
2563 12:14:15.523534 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2564 12:14:15.526806 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2565 12:14:15.530174 [Gating] SW calibration Done
2566 12:14:15.530274 ==
2567 12:14:15.533637 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 12:14:15.540202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 12:14:15.540305 ==
2570 12:14:15.540402 RX Vref Scan: 0
2571 12:14:15.540493
2572 12:14:15.543670 RX Vref 0 -> 0, step: 1
2573 12:14:15.543767
2574 12:14:15.546693 RX Delay -40 -> 252, step: 8
2575 12:14:15.550263 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2576 12:14:15.553372 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2577 12:14:15.556863 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2578 12:14:15.560078 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2579 12:14:15.566612 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2580 12:14:15.570272 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2581 12:14:15.573359 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2582 12:14:15.576930 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2583 12:14:15.579966 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2584 12:14:15.586469 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2585 12:14:15.590128 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2586 12:14:15.593166 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2587 12:14:15.596718 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2588 12:14:15.599803 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2589 12:14:15.606395 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2590 12:14:15.609736 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2591 12:14:15.609833 ==
2592 12:14:15.613412 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 12:14:15.616437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 12:14:15.616533 ==
2595 12:14:15.620044 DQS Delay:
2596 12:14:15.620125 DQS0 = 0, DQS1 = 0
2597 12:14:15.620215 DQM Delay:
2598 12:14:15.622941 DQM0 = 122, DQM1 = 110
2599 12:14:15.623038 DQ Delay:
2600 12:14:15.626486 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2601 12:14:15.629868 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2602 12:14:15.636173 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2603 12:14:15.639681 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2604 12:14:15.639782
2605 12:14:15.639872
2606 12:14:15.639959 ==
2607 12:14:15.643013 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 12:14:15.646028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 12:14:15.646134 ==
2610 12:14:15.646237
2611 12:14:15.646324
2612 12:14:15.649528 TX Vref Scan disable
2613 12:14:15.649600 == TX Byte 0 ==
2614 12:14:15.656263 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2615 12:14:15.659362 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2616 12:14:15.659463 == TX Byte 1 ==
2617 12:14:15.666119 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2618 12:14:15.669253 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2619 12:14:15.669354 ==
2620 12:14:15.672936 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 12:14:15.676105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 12:14:15.676205 ==
2623 12:14:15.689223 TX Vref=22, minBit 0, minWin=24, winSum=402
2624 12:14:15.692755 TX Vref=24, minBit 0, minWin=25, winSum=413
2625 12:14:15.695822 TX Vref=26, minBit 1, minWin=24, winSum=412
2626 12:14:15.698909 TX Vref=28, minBit 0, minWin=24, winSum=417
2627 12:14:15.702595 TX Vref=30, minBit 3, minWin=25, winSum=420
2628 12:14:15.705711 TX Vref=32, minBit 1, minWin=25, winSum=415
2629 12:14:15.712396 [TxChooseVref] Worse bit 3, Min win 25, Win sum 420, Final Vref 30
2630 12:14:15.712498
2631 12:14:15.715399 Final TX Range 1 Vref 30
2632 12:14:15.715502
2633 12:14:15.715592 ==
2634 12:14:15.719073 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 12:14:15.722541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 12:14:15.722647 ==
2637 12:14:15.722746
2638 12:14:15.725598
2639 12:14:15.725703 TX Vref Scan disable
2640 12:14:15.729012 == TX Byte 0 ==
2641 12:14:15.732478 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2642 12:14:15.735481 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2643 12:14:15.738823 == TX Byte 1 ==
2644 12:14:15.742328 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2645 12:14:15.745325 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2646 12:14:15.748966
2647 12:14:15.749069 [DATLAT]
2648 12:14:15.749164 Freq=1200, CH0 RK0
2649 12:14:15.749259
2650 12:14:15.752523 DATLAT Default: 0xd
2651 12:14:15.752622 0, 0xFFFF, sum = 0
2652 12:14:15.755512 1, 0xFFFF, sum = 0
2653 12:14:15.755611 2, 0xFFFF, sum = 0
2654 12:14:15.758921 3, 0xFFFF, sum = 0
2655 12:14:15.758994 4, 0xFFFF, sum = 0
2656 12:14:15.762576 5, 0xFFFF, sum = 0
2657 12:14:15.765678 6, 0xFFFF, sum = 0
2658 12:14:15.765762 7, 0xFFFF, sum = 0
2659 12:14:15.768719 8, 0xFFFF, sum = 0
2660 12:14:15.768815 9, 0xFFFF, sum = 0
2661 12:14:15.772450 10, 0xFFFF, sum = 0
2662 12:14:15.772534 11, 0xFFFF, sum = 0
2663 12:14:15.775579 12, 0x0, sum = 1
2664 12:14:15.775662 13, 0x0, sum = 2
2665 12:14:15.779071 14, 0x0, sum = 3
2666 12:14:15.779155 15, 0x0, sum = 4
2667 12:14:15.779221 best_step = 13
2668 12:14:15.782286
2669 12:14:15.782368 ==
2670 12:14:15.785473 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 12:14:15.788734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 12:14:15.788834 ==
2673 12:14:15.788900 RX Vref Scan: 1
2674 12:14:15.788961
2675 12:14:15.792313 Set Vref Range= 32 -> 127
2676 12:14:15.792396
2677 12:14:15.795421 RX Vref 32 -> 127, step: 1
2678 12:14:15.795503
2679 12:14:15.798910 RX Delay -13 -> 252, step: 4
2680 12:14:15.798993
2681 12:14:15.802366 Set Vref, RX VrefLevel [Byte0]: 32
2682 12:14:15.805492 [Byte1]: 32
2683 12:14:15.805574
2684 12:14:15.808568 Set Vref, RX VrefLevel [Byte0]: 33
2685 12:14:15.812154 [Byte1]: 33
2686 12:14:15.815166
2687 12:14:15.815244 Set Vref, RX VrefLevel [Byte0]: 34
2688 12:14:15.818688 [Byte1]: 34
2689 12:14:15.823214
2690 12:14:15.823282 Set Vref, RX VrefLevel [Byte0]: 35
2691 12:14:15.826657 [Byte1]: 35
2692 12:14:15.831252
2693 12:14:15.831321 Set Vref, RX VrefLevel [Byte0]: 36
2694 12:14:15.834197 [Byte1]: 36
2695 12:14:15.838922
2696 12:14:15.839003 Set Vref, RX VrefLevel [Byte0]: 37
2697 12:14:15.842251 [Byte1]: 37
2698 12:14:15.846687
2699 12:14:15.846881 Set Vref, RX VrefLevel [Byte0]: 38
2700 12:14:15.850434 [Byte1]: 38
2701 12:14:15.854529
2702 12:14:15.854611 Set Vref, RX VrefLevel [Byte0]: 39
2703 12:14:15.857934 [Byte1]: 39
2704 12:14:15.862672
2705 12:14:15.862753 Set Vref, RX VrefLevel [Byte0]: 40
2706 12:14:15.865700 [Byte1]: 40
2707 12:14:15.870415
2708 12:14:15.870493 Set Vref, RX VrefLevel [Byte0]: 41
2709 12:14:15.873922 [Byte1]: 41
2710 12:14:15.878611
2711 12:14:15.878692 Set Vref, RX VrefLevel [Byte0]: 42
2712 12:14:15.881702 [Byte1]: 42
2713 12:14:15.886382
2714 12:14:15.886465 Set Vref, RX VrefLevel [Byte0]: 43
2715 12:14:15.889484 [Byte1]: 43
2716 12:14:15.893905
2717 12:14:15.893991 Set Vref, RX VrefLevel [Byte0]: 44
2718 12:14:15.897552 [Byte1]: 44
2719 12:14:15.902263
2720 12:14:15.902356 Set Vref, RX VrefLevel [Byte0]: 45
2721 12:14:15.905455 [Byte1]: 45
2722 12:14:15.909890
2723 12:14:15.909973 Set Vref, RX VrefLevel [Byte0]: 46
2724 12:14:15.913441 [Byte1]: 46
2725 12:14:15.917974
2726 12:14:15.918056 Set Vref, RX VrefLevel [Byte0]: 47
2727 12:14:15.920881 [Byte1]: 47
2728 12:14:15.925610
2729 12:14:15.925692 Set Vref, RX VrefLevel [Byte0]: 48
2730 12:14:15.929245 [Byte1]: 48
2731 12:14:15.933380
2732 12:14:15.933462 Set Vref, RX VrefLevel [Byte0]: 49
2733 12:14:15.937018 [Byte1]: 49
2734 12:14:15.941411
2735 12:14:15.941499 Set Vref, RX VrefLevel [Byte0]: 50
2736 12:14:15.944686 [Byte1]: 50
2737 12:14:15.949446
2738 12:14:15.949528 Set Vref, RX VrefLevel [Byte0]: 51
2739 12:14:15.952742 [Byte1]: 51
2740 12:14:15.957554
2741 12:14:15.957636 Set Vref, RX VrefLevel [Byte0]: 52
2742 12:14:15.960915 [Byte1]: 52
2743 12:14:15.965040
2744 12:14:15.965128 Set Vref, RX VrefLevel [Byte0]: 53
2745 12:14:15.968563 [Byte1]: 53
2746 12:14:15.973207
2747 12:14:15.973289 Set Vref, RX VrefLevel [Byte0]: 54
2748 12:14:15.976209 [Byte1]: 54
2749 12:14:15.980944
2750 12:14:15.981027 Set Vref, RX VrefLevel [Byte0]: 55
2751 12:14:15.984420 [Byte1]: 55
2752 12:14:15.989158
2753 12:14:15.989240 Set Vref, RX VrefLevel [Byte0]: 56
2754 12:14:15.992304 [Byte1]: 56
2755 12:14:15.996893
2756 12:14:15.996975 Set Vref, RX VrefLevel [Byte0]: 57
2757 12:14:15.999940 [Byte1]: 57
2758 12:14:16.004628
2759 12:14:16.004711 Set Vref, RX VrefLevel [Byte0]: 58
2760 12:14:16.007748 [Byte1]: 58
2761 12:14:16.012365
2762 12:14:16.012447 Set Vref, RX VrefLevel [Byte0]: 59
2763 12:14:16.015946 [Byte1]: 59
2764 12:14:16.020195
2765 12:14:16.020277 Set Vref, RX VrefLevel [Byte0]: 60
2766 12:14:16.023668 [Byte1]: 60
2767 12:14:16.028437
2768 12:14:16.028519 Set Vref, RX VrefLevel [Byte0]: 61
2769 12:14:16.031485 [Byte1]: 61
2770 12:14:16.036218
2771 12:14:16.036299 Set Vref, RX VrefLevel [Byte0]: 62
2772 12:14:16.039298 [Byte1]: 62
2773 12:14:16.043957
2774 12:14:16.044043 Set Vref, RX VrefLevel [Byte0]: 63
2775 12:14:16.047185 [Byte1]: 63
2776 12:14:16.052132
2777 12:14:16.052215 Set Vref, RX VrefLevel [Byte0]: 64
2778 12:14:16.054990 [Byte1]: 64
2779 12:14:16.059812
2780 12:14:16.059889 Set Vref, RX VrefLevel [Byte0]: 65
2781 12:14:16.063336 [Byte1]: 65
2782 12:14:16.067867
2783 12:14:16.067950 Set Vref, RX VrefLevel [Byte0]: 66
2784 12:14:16.070850 [Byte1]: 66
2785 12:14:16.075629
2786 12:14:16.075707 Set Vref, RX VrefLevel [Byte0]: 67
2787 12:14:16.078959 [Byte1]: 67
2788 12:14:16.083554
2789 12:14:16.083637 Set Vref, RX VrefLevel [Byte0]: 68
2790 12:14:16.086688 [Byte1]: 68
2791 12:14:16.091236
2792 12:14:16.091318 Set Vref, RX VrefLevel [Byte0]: 69
2793 12:14:16.094939 [Byte1]: 69
2794 12:14:16.099053
2795 12:14:16.099151 Set Vref, RX VrefLevel [Byte0]: 70
2796 12:14:16.102601 [Byte1]: 70
2797 12:14:16.106794
2798 12:14:16.110429 Final RX Vref Byte 0 = 58 to rank0
2799 12:14:16.110519 Final RX Vref Byte 1 = 50 to rank0
2800 12:14:16.113466 Final RX Vref Byte 0 = 58 to rank1
2801 12:14:16.117028 Final RX Vref Byte 1 = 50 to rank1==
2802 12:14:16.120125 Dram Type= 6, Freq= 0, CH_0, rank 0
2803 12:14:16.126721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2804 12:14:16.126802 ==
2805 12:14:16.126866 DQS Delay:
2806 12:14:16.130199 DQS0 = 0, DQS1 = 0
2807 12:14:16.130272 DQM Delay:
2808 12:14:16.133288 DQM0 = 122, DQM1 = 109
2809 12:14:16.133357 DQ Delay:
2810 12:14:16.136474 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2811 12:14:16.140087 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2812 12:14:16.143227 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =108
2813 12:14:16.146713 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2814 12:14:16.146782
2815 12:14:16.146842
2816 12:14:16.156569 [DQSOSCAuto] RK0, (LSB)MR18= 0x703, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 407 ps
2817 12:14:16.156644 CH0 RK0: MR19=404, MR18=703
2818 12:14:16.163408 CH0_RK0: MR19=0x404, MR18=0x703, DQSOSC=407, MR23=63, INC=39, DEC=26
2819 12:14:16.163560
2820 12:14:16.166776 ----->DramcWriteLeveling(PI) begin...
2821 12:14:16.166940 ==
2822 12:14:16.170051 Dram Type= 6, Freq= 0, CH_0, rank 1
2823 12:14:16.176741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2824 12:14:16.176836 ==
2825 12:14:16.180149 Write leveling (Byte 0): 37 => 37
2826 12:14:16.180235 Write leveling (Byte 1): 29 => 29
2827 12:14:16.183069 DramcWriteLeveling(PI) end<-----
2828 12:14:16.183144
2829 12:14:16.183207 ==
2830 12:14:16.186370 Dram Type= 6, Freq= 0, CH_0, rank 1
2831 12:14:16.193173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2832 12:14:16.193255 ==
2833 12:14:16.196866 [Gating] SW mode calibration
2834 12:14:16.203461 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2835 12:14:16.206946 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2836 12:14:16.213650 0 15 0 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
2837 12:14:16.216698 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 12:14:16.220149 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 12:14:16.226631 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 12:14:16.229704 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 12:14:16.233313 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 12:14:16.236773 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 12:14:16.243086 0 15 28 | B1->B0 | 3131 3131 | 1 1 | (1 1) (1 0)
2844 12:14:16.246067 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 12:14:16.249617 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 12:14:16.256418 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 12:14:16.259594 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 12:14:16.262761 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 12:14:16.269750 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 12:14:16.272594 1 0 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
2851 12:14:16.275874 1 0 28 | B1->B0 | 3939 4343 | 0 0 | (0 0) (1 1)
2852 12:14:16.282636 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 12:14:16.286142 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 12:14:16.289154 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 12:14:16.295962 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 12:14:16.299101 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 12:14:16.302771 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 12:14:16.309373 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 12:14:16.312514 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2860 12:14:16.315563 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2861 12:14:16.322159 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 12:14:16.325679 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 12:14:16.328820 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 12:14:16.335607 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 12:14:16.339011 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 12:14:16.342524 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 12:14:16.348700 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 12:14:16.352411 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 12:14:16.355515 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 12:14:16.362199 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 12:14:16.365792 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 12:14:16.368816 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 12:14:16.375428 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 12:14:16.378841 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2875 12:14:16.382131 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2876 12:14:16.388667 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 12:14:16.388834 Total UI for P1: 0, mck2ui 16
2878 12:14:16.395238 best dqsien dly found for B0: ( 1, 3, 26)
2879 12:14:16.395315 Total UI for P1: 0, mck2ui 16
2880 12:14:16.401966 best dqsien dly found for B1: ( 1, 3, 28)
2881 12:14:16.405518 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2882 12:14:16.408683 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2883 12:14:16.408818
2884 12:14:16.412373 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2885 12:14:16.415282 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2886 12:14:16.418950 [Gating] SW calibration Done
2887 12:14:16.419049 ==
2888 12:14:16.421977 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 12:14:16.425140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 12:14:16.425210 ==
2891 12:14:16.428666 RX Vref Scan: 0
2892 12:14:16.428762
2893 12:14:16.428853 RX Vref 0 -> 0, step: 1
2894 12:14:16.428931
2895 12:14:16.431696 RX Delay -40 -> 252, step: 8
2896 12:14:16.435326 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2897 12:14:16.441875 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2898 12:14:16.445396 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2899 12:14:16.448347 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2900 12:14:16.451840 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2901 12:14:16.455338 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2902 12:14:16.461644 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2903 12:14:16.465382 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2904 12:14:16.468563 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2905 12:14:16.471642 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2906 12:14:16.475332 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2907 12:14:16.481639 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2908 12:14:16.485155 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2909 12:14:16.488438 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2910 12:14:16.491849 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2911 12:14:16.495050 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2912 12:14:16.498408 ==
2913 12:14:16.498486 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 12:14:16.504669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 12:14:16.504788 ==
2916 12:14:16.504866 DQS Delay:
2917 12:14:16.508055 DQS0 = 0, DQS1 = 0
2918 12:14:16.508143 DQM Delay:
2919 12:14:16.511555 DQM0 = 120, DQM1 = 108
2920 12:14:16.511653 DQ Delay:
2921 12:14:16.515144 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2922 12:14:16.518102 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2923 12:14:16.521658 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2924 12:14:16.524824 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2925 12:14:16.524933
2926 12:14:16.524993
2927 12:14:16.525076 ==
2928 12:14:16.527910 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 12:14:16.534961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 12:14:16.535045 ==
2931 12:14:16.535112
2932 12:14:16.535171
2933 12:14:16.535291 TX Vref Scan disable
2934 12:14:16.537922 == TX Byte 0 ==
2935 12:14:16.541136 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2936 12:14:16.548285 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2937 12:14:16.548362 == TX Byte 1 ==
2938 12:14:16.551358 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2939 12:14:16.557871 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2940 12:14:16.557951 ==
2941 12:14:16.561446 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 12:14:16.564659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 12:14:16.564783 ==
2944 12:14:16.576587 TX Vref=22, minBit 3, minWin=25, winSum=418
2945 12:14:16.580252 TX Vref=24, minBit 1, minWin=26, winSum=424
2946 12:14:16.583355 TX Vref=26, minBit 1, minWin=26, winSum=432
2947 12:14:16.586397 TX Vref=28, minBit 1, minWin=26, winSum=433
2948 12:14:16.589914 TX Vref=30, minBit 0, minWin=27, winSum=437
2949 12:14:16.596681 TX Vref=32, minBit 12, minWin=26, winSum=434
2950 12:14:16.600121 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 30
2951 12:14:16.600199
2952 12:14:16.602951 Final TX Range 1 Vref 30
2953 12:14:16.603024
2954 12:14:16.603085 ==
2955 12:14:16.606350 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 12:14:16.609674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 12:14:16.613140 ==
2958 12:14:16.613212
2959 12:14:16.613272
2960 12:14:16.613329 TX Vref Scan disable
2961 12:14:16.616444 == TX Byte 0 ==
2962 12:14:16.620112 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2963 12:14:16.626569 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2964 12:14:16.626645 == TX Byte 1 ==
2965 12:14:16.629673 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2966 12:14:16.636433 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2967 12:14:16.636508
2968 12:14:16.636569 [DATLAT]
2969 12:14:16.636629 Freq=1200, CH0 RK1
2970 12:14:16.636686
2971 12:14:16.639648 DATLAT Default: 0xd
2972 12:14:16.643287 0, 0xFFFF, sum = 0
2973 12:14:16.643369 1, 0xFFFF, sum = 0
2974 12:14:16.646395 2, 0xFFFF, sum = 0
2975 12:14:16.646495 3, 0xFFFF, sum = 0
2976 12:14:16.649952 4, 0xFFFF, sum = 0
2977 12:14:16.650058 5, 0xFFFF, sum = 0
2978 12:14:16.652974 6, 0xFFFF, sum = 0
2979 12:14:16.653075 7, 0xFFFF, sum = 0
2980 12:14:16.656636 8, 0xFFFF, sum = 0
2981 12:14:16.656759 9, 0xFFFF, sum = 0
2982 12:14:16.659673 10, 0xFFFF, sum = 0
2983 12:14:16.659759 11, 0xFFFF, sum = 0
2984 12:14:16.663288 12, 0x0, sum = 1
2985 12:14:16.663362 13, 0x0, sum = 2
2986 12:14:16.666369 14, 0x0, sum = 3
2987 12:14:16.666444 15, 0x0, sum = 4
2988 12:14:16.669975 best_step = 13
2989 12:14:16.670045
2990 12:14:16.670106 ==
2991 12:14:16.672950 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 12:14:16.676478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 12:14:16.676586 ==
2994 12:14:16.676679 RX Vref Scan: 0
2995 12:14:16.676773
2996 12:14:16.679684 RX Vref 0 -> 0, step: 1
2997 12:14:16.679756
2998 12:14:16.683367 RX Delay -21 -> 252, step: 4
2999 12:14:16.686394 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3000 12:14:16.692961 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3001 12:14:16.696399 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3002 12:14:16.699868 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3003 12:14:16.702953 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3004 12:14:16.706289 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3005 12:14:16.713070 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3006 12:14:16.716411 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3007 12:14:16.719582 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3008 12:14:16.722827 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3009 12:14:16.726436 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3010 12:14:16.732718 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3011 12:14:16.736441 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3012 12:14:16.739451 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3013 12:14:16.742975 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3014 12:14:16.746178 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3015 12:14:16.749191 ==
3016 12:14:16.752786 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 12:14:16.755819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 12:14:16.755897 ==
3019 12:14:16.755961 DQS Delay:
3020 12:14:16.759492 DQS0 = 0, DQS1 = 0
3021 12:14:16.759571 DQM Delay:
3022 12:14:16.762589 DQM0 = 119, DQM1 = 108
3023 12:14:16.762659 DQ Delay:
3024 12:14:16.765776 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3025 12:14:16.769467 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3026 12:14:16.772643 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3027 12:14:16.776230 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3028 12:14:16.776307
3029 12:14:16.776379
3030 12:14:16.786156 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3031 12:14:16.789570 CH0 RK1: MR19=403, MR18=11F9
3032 12:14:16.792585 CH0_RK1: MR19=0x403, MR18=0x11F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3033 12:14:16.795713 [RxdqsGatingPostProcess] freq 1200
3034 12:14:16.802386 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3035 12:14:16.805572 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 12:14:16.809134 best DQS1 dly(2T, 0.5T) = (0, 12)
3037 12:14:16.812497 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 12:14:16.815815 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3039 12:14:16.819238 best DQS0 dly(2T, 0.5T) = (0, 11)
3040 12:14:16.822211 best DQS1 dly(2T, 0.5T) = (0, 11)
3041 12:14:16.825800 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3042 12:14:16.829228 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3043 12:14:16.829310 Pre-setting of DQS Precalculation
3044 12:14:16.835851 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3045 12:14:16.835935 ==
3046 12:14:16.838809 Dram Type= 6, Freq= 0, CH_1, rank 0
3047 12:14:16.842443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 12:14:16.842527 ==
3049 12:14:16.848792 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3050 12:14:16.855551 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3051 12:14:16.863183 [CA 0] Center 37 (7~68) winsize 62
3052 12:14:16.866267 [CA 1] Center 37 (7~68) winsize 62
3053 12:14:16.869358 [CA 2] Center 35 (5~65) winsize 61
3054 12:14:16.872968 [CA 3] Center 34 (4~65) winsize 62
3055 12:14:16.876081 [CA 4] Center 34 (3~65) winsize 63
3056 12:14:16.879348 [CA 5] Center 33 (3~64) winsize 62
3057 12:14:16.879430
3058 12:14:16.882922 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3059 12:14:16.882999
3060 12:14:16.886193 [CATrainingPosCal] consider 1 rank data
3061 12:14:16.889353 u2DelayCellTimex100 = 270/100 ps
3062 12:14:16.892479 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3063 12:14:16.899763 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3064 12:14:16.902800 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3065 12:14:16.905793 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3066 12:14:16.909438 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
3067 12:14:16.912580 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3068 12:14:16.912653
3069 12:14:16.916109 CA PerBit enable=1, Macro0, CA PI delay=33
3070 12:14:16.916193
3071 12:14:16.919036 [CBTSetCACLKResult] CA Dly = 33
3072 12:14:16.919110 CS Dly: 5 (0~36)
3073 12:14:16.922528 ==
3074 12:14:16.925920 Dram Type= 6, Freq= 0, CH_1, rank 1
3075 12:14:16.929207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 12:14:16.929286 ==
3077 12:14:16.932462 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3078 12:14:16.938925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3079 12:14:16.948616 [CA 0] Center 38 (8~68) winsize 61
3080 12:14:16.952233 [CA 1] Center 38 (8~68) winsize 61
3081 12:14:16.955334 [CA 2] Center 35 (5~66) winsize 62
3082 12:14:16.958364 [CA 3] Center 34 (4~65) winsize 62
3083 12:14:16.961764 [CA 4] Center 35 (5~65) winsize 61
3084 12:14:16.965187 [CA 5] Center 34 (4~65) winsize 62
3085 12:14:16.965263
3086 12:14:16.968293 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3087 12:14:16.968364
3088 12:14:16.971846 [CATrainingPosCal] consider 2 rank data
3089 12:14:16.975165 u2DelayCellTimex100 = 270/100 ps
3090 12:14:16.978190 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3091 12:14:16.985027 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3092 12:14:16.988170 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3093 12:14:16.991853 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3094 12:14:16.995026 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3095 12:14:16.998619 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3096 12:14:16.998731
3097 12:14:17.001829 CA PerBit enable=1, Macro0, CA PI delay=34
3098 12:14:17.001903
3099 12:14:17.004949 [CBTSetCACLKResult] CA Dly = 34
3100 12:14:17.005020 CS Dly: 6 (0~39)
3101 12:14:17.008520
3102 12:14:17.011651 ----->DramcWriteLeveling(PI) begin...
3103 12:14:17.011760 ==
3104 12:14:17.014940 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 12:14:17.018167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 12:14:17.018241 ==
3107 12:14:17.021827 Write leveling (Byte 0): 25 => 25
3108 12:14:17.024750 Write leveling (Byte 1): 28 => 28
3109 12:14:17.028428 DramcWriteLeveling(PI) end<-----
3110 12:14:17.028539
3111 12:14:17.028635 ==
3112 12:14:17.031465 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 12:14:17.034869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 12:14:17.034973 ==
3115 12:14:17.038140 [Gating] SW mode calibration
3116 12:14:17.044490 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3117 12:14:17.051163 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3118 12:14:17.054592 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 12:14:17.057798 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 12:14:17.064580 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 12:14:17.067690 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 12:14:17.071321 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 12:14:17.077705 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3124 12:14:17.080913 0 15 24 | B1->B0 | 2e2e 2929 | 1 0 | (1 0) (0 0)
3125 12:14:17.084350 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3126 12:14:17.091056 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 12:14:17.094279 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 12:14:17.097890 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 12:14:17.104235 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 12:14:17.107716 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 12:14:17.110817 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 12:14:17.117875 1 0 24 | B1->B0 | 3838 4444 | 0 0 | (1 1) (0 0)
3133 12:14:17.121054 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 12:14:17.124166 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 12:14:17.127666 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 12:14:17.134359 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 12:14:17.137382 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 12:14:17.140728 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 12:14:17.147592 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3140 12:14:17.150805 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3141 12:14:17.154347 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3142 12:14:17.160591 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 12:14:17.164122 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 12:14:17.167212 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 12:14:17.173883 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 12:14:17.177317 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 12:14:17.180409 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 12:14:17.187174 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 12:14:17.190389 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 12:14:17.193936 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:14:17.200277 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:14:17.203360 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:14:17.206908 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 12:14:17.213382 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 12:14:17.216945 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3156 12:14:17.220382 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3157 12:14:17.226706 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3158 12:14:17.230314 Total UI for P1: 0, mck2ui 16
3159 12:14:17.233216 best dqsien dly found for B0: ( 1, 3, 22)
3160 12:14:17.236745 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 12:14:17.240031 Total UI for P1: 0, mck2ui 16
3162 12:14:17.243454 best dqsien dly found for B1: ( 1, 3, 26)
3163 12:14:17.246569 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3164 12:14:17.250117 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3165 12:14:17.250200
3166 12:14:17.253071 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3167 12:14:17.256370 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3168 12:14:17.259630 [Gating] SW calibration Done
3169 12:14:17.259715 ==
3170 12:14:17.262968 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 12:14:17.269667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 12:14:17.269751 ==
3173 12:14:17.269816 RX Vref Scan: 0
3174 12:14:17.269878
3175 12:14:17.272724 RX Vref 0 -> 0, step: 1
3176 12:14:17.272826
3177 12:14:17.276268 RX Delay -40 -> 252, step: 8
3178 12:14:17.279774 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3179 12:14:17.282832 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3180 12:14:17.286470 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3181 12:14:17.289981 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3182 12:14:17.296173 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3183 12:14:17.299815 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3184 12:14:17.302836 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3185 12:14:17.306508 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3186 12:14:17.309479 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3187 12:14:17.315985 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3188 12:14:17.319611 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3189 12:14:17.322928 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3190 12:14:17.326059 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3191 12:14:17.329651 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3192 12:14:17.335832 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3193 12:14:17.339244 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3194 12:14:17.339327 ==
3195 12:14:17.342873 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 12:14:17.345843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 12:14:17.345927 ==
3198 12:14:17.349232 DQS Delay:
3199 12:14:17.349314 DQS0 = 0, DQS1 = 0
3200 12:14:17.352407 DQM Delay:
3201 12:14:17.352490 DQM0 = 119, DQM1 = 112
3202 12:14:17.352554 DQ Delay:
3203 12:14:17.355997 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3204 12:14:17.359150 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3205 12:14:17.365906 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3206 12:14:17.369209 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3207 12:14:17.369292
3208 12:14:17.369357
3209 12:14:17.369417 ==
3210 12:14:17.372405 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 12:14:17.375783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 12:14:17.375867 ==
3213 12:14:17.375932
3214 12:14:17.375992
3215 12:14:17.379073 TX Vref Scan disable
3216 12:14:17.382328 == TX Byte 0 ==
3217 12:14:17.385313 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3218 12:14:17.388996 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3219 12:14:17.392039 == TX Byte 1 ==
3220 12:14:17.395704 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3221 12:14:17.398852 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3222 12:14:17.398935 ==
3223 12:14:17.401980 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 12:14:17.405649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 12:14:17.408770 ==
3226 12:14:17.418735 TX Vref=22, minBit 11, minWin=24, winSum=406
3227 12:14:17.421855 TX Vref=24, minBit 1, minWin=24, winSum=407
3228 12:14:17.425602 TX Vref=26, minBit 9, minWin=25, winSum=419
3229 12:14:17.428558 TX Vref=28, minBit 10, minWin=25, winSum=421
3230 12:14:17.431760 TX Vref=30, minBit 11, minWin=25, winSum=423
3231 12:14:17.438602 TX Vref=32, minBit 10, minWin=25, winSum=422
3232 12:14:17.442068 [TxChooseVref] Worse bit 11, Min win 25, Win sum 423, Final Vref 30
3233 12:14:17.442150
3234 12:14:17.445224 Final TX Range 1 Vref 30
3235 12:14:17.445305
3236 12:14:17.445369 ==
3237 12:14:17.448328 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 12:14:17.451791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 12:14:17.455327 ==
3240 12:14:17.455408
3241 12:14:17.455471
3242 12:14:17.455530 TX Vref Scan disable
3243 12:14:17.458547 == TX Byte 0 ==
3244 12:14:17.462267 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3245 12:14:17.468809 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3246 12:14:17.468891 == TX Byte 1 ==
3247 12:14:17.471857 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3248 12:14:17.478596 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3249 12:14:17.478678
3250 12:14:17.478742 [DATLAT]
3251 12:14:17.478801 Freq=1200, CH1 RK0
3252 12:14:17.478858
3253 12:14:17.481927 DATLAT Default: 0xd
3254 12:14:17.482008 0, 0xFFFF, sum = 0
3255 12:14:17.485275 1, 0xFFFF, sum = 0
3256 12:14:17.488634 2, 0xFFFF, sum = 0
3257 12:14:17.488716 3, 0xFFFF, sum = 0
3258 12:14:17.491964 4, 0xFFFF, sum = 0
3259 12:14:17.492048 5, 0xFFFF, sum = 0
3260 12:14:17.495445 6, 0xFFFF, sum = 0
3261 12:14:17.495528 7, 0xFFFF, sum = 0
3262 12:14:17.498112 8, 0xFFFF, sum = 0
3263 12:14:17.498200 9, 0xFFFF, sum = 0
3264 12:14:17.501708 10, 0xFFFF, sum = 0
3265 12:14:17.501797 11, 0xFFFF, sum = 0
3266 12:14:17.504848 12, 0x0, sum = 1
3267 12:14:17.504959 13, 0x0, sum = 2
3268 12:14:17.507878 14, 0x0, sum = 3
3269 12:14:17.507961 15, 0x0, sum = 4
3270 12:14:17.511599 best_step = 13
3271 12:14:17.511680
3272 12:14:17.511745 ==
3273 12:14:17.515122 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 12:14:17.518319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 12:14:17.518402 ==
3276 12:14:17.521493 RX Vref Scan: 1
3277 12:14:17.521575
3278 12:14:17.521640 Set Vref Range= 32 -> 127
3279 12:14:17.521707
3280 12:14:17.524517 RX Vref 32 -> 127, step: 1
3281 12:14:17.524613
3282 12:14:17.528139 RX Delay -13 -> 252, step: 4
3283 12:14:17.528236
3284 12:14:17.531145 Set Vref, RX VrefLevel [Byte0]: 32
3285 12:14:17.534217 [Byte1]: 32
3286 12:14:17.534315
3287 12:14:17.537785 Set Vref, RX VrefLevel [Byte0]: 33
3288 12:14:17.541316 [Byte1]: 33
3289 12:14:17.545303
3290 12:14:17.545384 Set Vref, RX VrefLevel [Byte0]: 34
3291 12:14:17.548365 [Byte1]: 34
3292 12:14:17.553077
3293 12:14:17.553158 Set Vref, RX VrefLevel [Byte0]: 35
3294 12:14:17.556498 [Byte1]: 35
3295 12:14:17.560787
3296 12:14:17.560883 Set Vref, RX VrefLevel [Byte0]: 36
3297 12:14:17.564477 [Byte1]: 36
3298 12:14:17.568991
3299 12:14:17.569104 Set Vref, RX VrefLevel [Byte0]: 37
3300 12:14:17.571920 [Byte1]: 37
3301 12:14:17.576618
3302 12:14:17.576730 Set Vref, RX VrefLevel [Byte0]: 38
3303 12:14:17.580150 [Byte1]: 38
3304 12:14:17.584455
3305 12:14:17.584559 Set Vref, RX VrefLevel [Byte0]: 39
3306 12:14:17.587826 [Byte1]: 39
3307 12:14:17.592659
3308 12:14:17.592741 Set Vref, RX VrefLevel [Byte0]: 40
3309 12:14:17.596054 [Byte1]: 40
3310 12:14:17.600305
3311 12:14:17.600401 Set Vref, RX VrefLevel [Byte0]: 41
3312 12:14:17.603550 [Byte1]: 41
3313 12:14:17.608165
3314 12:14:17.608276 Set Vref, RX VrefLevel [Byte0]: 42
3315 12:14:17.611782 [Byte1]: 42
3316 12:14:17.616282
3317 12:14:17.616364 Set Vref, RX VrefLevel [Byte0]: 43
3318 12:14:17.619316 [Byte1]: 43
3319 12:14:17.624075
3320 12:14:17.624156 Set Vref, RX VrefLevel [Byte0]: 44
3321 12:14:17.627177 [Byte1]: 44
3322 12:14:17.631852
3323 12:14:17.631964 Set Vref, RX VrefLevel [Byte0]: 45
3324 12:14:17.635392 [Byte1]: 45
3325 12:14:17.640055
3326 12:14:17.640163 Set Vref, RX VrefLevel [Byte0]: 46
3327 12:14:17.643068 [Byte1]: 46
3328 12:14:17.647594
3329 12:14:17.647703 Set Vref, RX VrefLevel [Byte0]: 47
3330 12:14:17.650928 [Byte1]: 47
3331 12:14:17.655407
3332 12:14:17.655489 Set Vref, RX VrefLevel [Byte0]: 48
3333 12:14:17.659021 [Byte1]: 48
3334 12:14:17.663607
3335 12:14:17.666764 Set Vref, RX VrefLevel [Byte0]: 49
3336 12:14:17.666853 [Byte1]: 49
3337 12:14:17.671407
3338 12:14:17.671494 Set Vref, RX VrefLevel [Byte0]: 50
3339 12:14:17.674397 [Byte1]: 50
3340 12:14:17.679100
3341 12:14:17.679176 Set Vref, RX VrefLevel [Byte0]: 51
3342 12:14:17.682725 [Byte1]: 51
3343 12:14:17.687224
3344 12:14:17.687330 Set Vref, RX VrefLevel [Byte0]: 52
3345 12:14:17.690383 [Byte1]: 52
3346 12:14:17.694804
3347 12:14:17.694885 Set Vref, RX VrefLevel [Byte0]: 53
3348 12:14:17.698433 [Byte1]: 53
3349 12:14:17.703040
3350 12:14:17.703127 Set Vref, RX VrefLevel [Byte0]: 54
3351 12:14:17.706479 [Byte1]: 54
3352 12:14:17.710905
3353 12:14:17.710986 Set Vref, RX VrefLevel [Byte0]: 55
3354 12:14:17.714020 [Byte1]: 55
3355 12:14:17.718560
3356 12:14:17.718641 Set Vref, RX VrefLevel [Byte0]: 56
3357 12:14:17.722299 [Byte1]: 56
3358 12:14:17.726389
3359 12:14:17.726470 Set Vref, RX VrefLevel [Byte0]: 57
3360 12:14:17.729897 [Byte1]: 57
3361 12:14:17.734519
3362 12:14:17.734628 Set Vref, RX VrefLevel [Byte0]: 58
3363 12:14:17.737652 [Byte1]: 58
3364 12:14:17.742246
3365 12:14:17.742329 Set Vref, RX VrefLevel [Byte0]: 59
3366 12:14:17.745897 [Byte1]: 59
3367 12:14:17.750115
3368 12:14:17.750196 Set Vref, RX VrefLevel [Byte0]: 60
3369 12:14:17.753498 [Byte1]: 60
3370 12:14:17.758350
3371 12:14:17.758432 Set Vref, RX VrefLevel [Byte0]: 61
3372 12:14:17.761364 [Byte1]: 61
3373 12:14:17.765869
3374 12:14:17.765950 Set Vref, RX VrefLevel [Byte0]: 62
3375 12:14:17.769123 [Byte1]: 62
3376 12:14:17.773721
3377 12:14:17.773802 Set Vref, RX VrefLevel [Byte0]: 63
3378 12:14:17.777431 [Byte1]: 63
3379 12:14:17.781949
3380 12:14:17.782033 Set Vref, RX VrefLevel [Byte0]: 64
3381 12:14:17.784930 [Byte1]: 64
3382 12:14:17.789492
3383 12:14:17.789575 Set Vref, RX VrefLevel [Byte0]: 65
3384 12:14:17.793024 [Byte1]: 65
3385 12:14:17.797713
3386 12:14:17.797796 Final RX Vref Byte 0 = 54 to rank0
3387 12:14:17.801122 Final RX Vref Byte 1 = 52 to rank0
3388 12:14:17.804565 Final RX Vref Byte 0 = 54 to rank1
3389 12:14:17.807425 Final RX Vref Byte 1 = 52 to rank1==
3390 12:14:17.810823 Dram Type= 6, Freq= 0, CH_1, rank 0
3391 12:14:17.817345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3392 12:14:17.817432 ==
3393 12:14:17.817498 DQS Delay:
3394 12:14:17.817559 DQS0 = 0, DQS1 = 0
3395 12:14:17.820923 DQM Delay:
3396 12:14:17.821005 DQM0 = 119, DQM1 = 112
3397 12:14:17.824470 DQ Delay:
3398 12:14:17.827650 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3399 12:14:17.830644 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =118
3400 12:14:17.834301 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3401 12:14:17.837454 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3402 12:14:17.837538
3403 12:14:17.837602
3404 12:14:17.844451 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3405 12:14:17.847612 CH1 RK0: MR19=404, MR18=215
3406 12:14:17.854462 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3407 12:14:17.854545
3408 12:14:17.857519 ----->DramcWriteLeveling(PI) begin...
3409 12:14:17.857603 ==
3410 12:14:17.860731 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 12:14:17.863920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3412 12:14:17.867551 ==
3413 12:14:17.867672 Write leveling (Byte 0): 25 => 25
3414 12:14:17.870524 Write leveling (Byte 1): 30 => 30
3415 12:14:17.874212 DramcWriteLeveling(PI) end<-----
3416 12:14:17.874294
3417 12:14:17.874359 ==
3418 12:14:17.877252 Dram Type= 6, Freq= 0, CH_1, rank 1
3419 12:14:17.883826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3420 12:14:17.883909 ==
3421 12:14:17.884030 [Gating] SW mode calibration
3422 12:14:17.893883 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3423 12:14:17.897397 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3424 12:14:17.904131 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3425 12:14:17.907302 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3426 12:14:17.910742 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 12:14:17.913941 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 12:14:17.920471 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 12:14:17.923565 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3430 12:14:17.927100 0 15 24 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
3431 12:14:17.933847 0 15 28 | B1->B0 | 2323 2c2c | 0 1 | (1 0) (1 0)
3432 12:14:17.937034 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3433 12:14:17.940019 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 12:14:17.947166 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 12:14:17.950287 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 12:14:17.953362 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 12:14:17.960128 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 12:14:17.963672 1 0 24 | B1->B0 | 4242 2b2b | 1 1 | (0 0) (0 0)
3439 12:14:17.966559 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3440 12:14:17.973380 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 12:14:17.976875 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 12:14:17.979867 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 12:14:17.986885 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 12:14:17.989965 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 12:14:17.993689 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 12:14:18.000201 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3447 12:14:18.003358 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3448 12:14:18.006485 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 12:14:18.013370 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 12:14:18.016837 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 12:14:18.019803 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 12:14:18.026597 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 12:14:18.029845 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 12:14:18.033149 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 12:14:18.039827 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 12:14:18.043320 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 12:14:18.046886 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 12:14:18.050041 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 12:14:18.056800 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 12:14:18.059890 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 12:14:18.066613 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 12:14:18.069865 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3463 12:14:18.073074 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3464 12:14:18.076553 Total UI for P1: 0, mck2ui 16
3465 12:14:18.079581 best dqsien dly found for B1: ( 1, 3, 24)
3466 12:14:18.083117 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 12:14:18.086264 Total UI for P1: 0, mck2ui 16
3468 12:14:18.089770 best dqsien dly found for B0: ( 1, 3, 26)
3469 12:14:18.092721 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3470 12:14:18.099454 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3471 12:14:18.099557
3472 12:14:18.102814 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3473 12:14:18.106318 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3474 12:14:18.109367 [Gating] SW calibration Done
3475 12:14:18.109452 ==
3476 12:14:18.112901 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 12:14:18.115915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 12:14:18.116026 ==
3479 12:14:18.119435 RX Vref Scan: 0
3480 12:14:18.119519
3481 12:14:18.119589 RX Vref 0 -> 0, step: 1
3482 12:14:18.119685
3483 12:14:18.122778 RX Delay -40 -> 252, step: 8
3484 12:14:18.125898 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3485 12:14:18.132353 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3486 12:14:18.135812 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3487 12:14:18.139371 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3488 12:14:18.142613 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3489 12:14:18.145651 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3490 12:14:18.152343 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3491 12:14:18.155361 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3492 12:14:18.158869 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3493 12:14:18.162058 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3494 12:14:18.165561 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3495 12:14:18.172165 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3496 12:14:18.175159 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3497 12:14:18.178866 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3498 12:14:18.181710 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3499 12:14:18.188436 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3500 12:14:18.188519 ==
3501 12:14:18.191613 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 12:14:18.195268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 12:14:18.195351 ==
3504 12:14:18.195419 DQS Delay:
3505 12:14:18.198271 DQS0 = 0, DQS1 = 0
3506 12:14:18.198353 DQM Delay:
3507 12:14:18.201901 DQM0 = 120, DQM1 = 112
3508 12:14:18.201984 DQ Delay:
3509 12:14:18.204932 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3510 12:14:18.208359 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3511 12:14:18.211413 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3512 12:14:18.215083 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3513 12:14:18.215158
3514 12:14:18.215221
3515 12:14:18.218142 ==
3516 12:14:18.218212 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 12:14:18.224733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 12:14:18.224855 ==
3519 12:14:18.224947
3520 12:14:18.225026
3521 12:14:18.227925 TX Vref Scan disable
3522 12:14:18.228023 == TX Byte 0 ==
3523 12:14:18.231664 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3524 12:14:18.237983 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3525 12:14:18.238064 == TX Byte 1 ==
3526 12:14:18.241335 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3527 12:14:18.248223 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3528 12:14:18.248339 ==
3529 12:14:18.251363 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 12:14:18.254453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 12:14:18.254575 ==
3532 12:14:18.266945 TX Vref=22, minBit 1, minWin=25, winSum=422
3533 12:14:18.270127 TX Vref=24, minBit 1, minWin=25, winSum=424
3534 12:14:18.273243 TX Vref=26, minBit 3, minWin=26, winSum=426
3535 12:14:18.276592 TX Vref=28, minBit 3, minWin=26, winSum=433
3536 12:14:18.280150 TX Vref=30, minBit 1, minWin=26, winSum=432
3537 12:14:18.286605 TX Vref=32, minBit 9, minWin=25, winSum=427
3538 12:14:18.289808 [TxChooseVref] Worse bit 3, Min win 26, Win sum 433, Final Vref 28
3539 12:14:18.289913
3540 12:14:18.293412 Final TX Range 1 Vref 28
3541 12:14:18.293486
3542 12:14:18.293548 ==
3543 12:14:18.296483 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 12:14:18.300041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 12:14:18.302969 ==
3546 12:14:18.303067
3547 12:14:18.303156
3548 12:14:18.303242 TX Vref Scan disable
3549 12:14:18.306548 == TX Byte 0 ==
3550 12:14:18.309710 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3551 12:14:18.316451 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3552 12:14:18.316564 == TX Byte 1 ==
3553 12:14:18.320057 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3554 12:14:18.326201 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3555 12:14:18.326303
3556 12:14:18.326399 [DATLAT]
3557 12:14:18.326498 Freq=1200, CH1 RK1
3558 12:14:18.326591
3559 12:14:18.329755 DATLAT Default: 0xd
3560 12:14:18.332870 0, 0xFFFF, sum = 0
3561 12:14:18.332976 1, 0xFFFF, sum = 0
3562 12:14:18.336082 2, 0xFFFF, sum = 0
3563 12:14:18.336186 3, 0xFFFF, sum = 0
3564 12:14:18.339586 4, 0xFFFF, sum = 0
3565 12:14:18.339691 5, 0xFFFF, sum = 0
3566 12:14:18.343111 6, 0xFFFF, sum = 0
3567 12:14:18.343214 7, 0xFFFF, sum = 0
3568 12:14:18.346031 8, 0xFFFF, sum = 0
3569 12:14:18.346133 9, 0xFFFF, sum = 0
3570 12:14:18.349460 10, 0xFFFF, sum = 0
3571 12:14:18.349543 11, 0xFFFF, sum = 0
3572 12:14:18.352761 12, 0x0, sum = 1
3573 12:14:18.352883 13, 0x0, sum = 2
3574 12:14:18.356374 14, 0x0, sum = 3
3575 12:14:18.356485 15, 0x0, sum = 4
3576 12:14:18.359484 best_step = 13
3577 12:14:18.359594
3578 12:14:18.359692 ==
3579 12:14:18.362551 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 12:14:18.366235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 12:14:18.366338 ==
3582 12:14:18.369310 RX Vref Scan: 0
3583 12:14:18.369411
3584 12:14:18.369503 RX Vref 0 -> 0, step: 1
3585 12:14:18.369594
3586 12:14:18.372473 RX Delay -13 -> 252, step: 4
3587 12:14:18.379112 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3588 12:14:18.382528 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3589 12:14:18.386197 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3590 12:14:18.389047 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3591 12:14:18.392596 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3592 12:14:18.399341 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3593 12:14:18.402462 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3594 12:14:18.405845 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3595 12:14:18.409146 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3596 12:14:18.412248 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3597 12:14:18.418973 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3598 12:14:18.422345 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3599 12:14:18.425442 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3600 12:14:18.429132 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3601 12:14:18.432501 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3602 12:14:18.439065 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3603 12:14:18.439143 ==
3604 12:14:18.442089 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 12:14:18.445285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 12:14:18.445368 ==
3607 12:14:18.445440 DQS Delay:
3608 12:14:18.448740 DQS0 = 0, DQS1 = 0
3609 12:14:18.448862 DQM Delay:
3610 12:14:18.452134 DQM0 = 119, DQM1 = 113
3611 12:14:18.452232 DQ Delay:
3612 12:14:18.455160 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3613 12:14:18.458450 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3614 12:14:18.461889 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3615 12:14:18.465081 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3616 12:14:18.468194
3617 12:14:18.468281
3618 12:14:18.474927 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 407 ps
3619 12:14:18.478049 CH1 RK1: MR19=403, MR18=6EA
3620 12:14:18.484681 CH1_RK1: MR19=0x403, MR18=0x6EA, DQSOSC=407, MR23=63, INC=39, DEC=26
3621 12:14:18.488168 [RxdqsGatingPostProcess] freq 1200
3622 12:14:18.491377 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3623 12:14:18.494721 best DQS0 dly(2T, 0.5T) = (0, 11)
3624 12:14:18.497951 best DQS1 dly(2T, 0.5T) = (0, 11)
3625 12:14:18.501087 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3626 12:14:18.504656 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3627 12:14:18.507827 best DQS0 dly(2T, 0.5T) = (0, 11)
3628 12:14:18.510917 best DQS1 dly(2T, 0.5T) = (0, 11)
3629 12:14:18.514611 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3630 12:14:18.517781 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3631 12:14:18.521294 Pre-setting of DQS Precalculation
3632 12:14:18.524401 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3633 12:14:18.534482 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3634 12:14:18.540811 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3635 12:14:18.540894
3636 12:14:18.540958
3637 12:14:18.544319 [Calibration Summary] 2400 Mbps
3638 12:14:18.544401 CH 0, Rank 0
3639 12:14:18.547501 SW Impedance : PASS
3640 12:14:18.547583 DUTY Scan : NO K
3641 12:14:18.551070 ZQ Calibration : PASS
3642 12:14:18.554189 Jitter Meter : NO K
3643 12:14:18.554271 CBT Training : PASS
3644 12:14:18.557668 Write leveling : PASS
3645 12:14:18.560633 RX DQS gating : PASS
3646 12:14:18.560714 RX DQ/DQS(RDDQC) : PASS
3647 12:14:18.564046 TX DQ/DQS : PASS
3648 12:14:18.567311 RX DATLAT : PASS
3649 12:14:18.567393 RX DQ/DQS(Engine): PASS
3650 12:14:18.570957 TX OE : NO K
3651 12:14:18.571040 All Pass.
3652 12:14:18.571106
3653 12:14:18.573941 CH 0, Rank 1
3654 12:14:18.574022 SW Impedance : PASS
3655 12:14:18.577406 DUTY Scan : NO K
3656 12:14:18.580439 ZQ Calibration : PASS
3657 12:14:18.580529 Jitter Meter : NO K
3658 12:14:18.583678 CBT Training : PASS
3659 12:14:18.583750 Write leveling : PASS
3660 12:14:18.587276 RX DQS gating : PASS
3661 12:14:18.590473 RX DQ/DQS(RDDQC) : PASS
3662 12:14:18.590544 TX DQ/DQS : PASS
3663 12:14:18.593553 RX DATLAT : PASS
3664 12:14:18.597207 RX DQ/DQS(Engine): PASS
3665 12:14:18.597282 TX OE : NO K
3666 12:14:18.600331 All Pass.
3667 12:14:18.600439
3668 12:14:18.600532 CH 1, Rank 0
3669 12:14:18.603495 SW Impedance : PASS
3670 12:14:18.603563 DUTY Scan : NO K
3671 12:14:18.607035 ZQ Calibration : PASS
3672 12:14:18.610157 Jitter Meter : NO K
3673 12:14:18.610226 CBT Training : PASS
3674 12:14:18.613656 Write leveling : PASS
3675 12:14:18.616850 RX DQS gating : PASS
3676 12:14:18.616918 RX DQ/DQS(RDDQC) : PASS
3677 12:14:18.620037 TX DQ/DQS : PASS
3678 12:14:18.623557 RX DATLAT : PASS
3679 12:14:18.623638 RX DQ/DQS(Engine): PASS
3680 12:14:18.626823 TX OE : NO K
3681 12:14:18.626913 All Pass.
3682 12:14:18.626979
3683 12:14:18.629975 CH 1, Rank 1
3684 12:14:18.630055 SW Impedance : PASS
3685 12:14:18.633580 DUTY Scan : NO K
3686 12:14:18.636596 ZQ Calibration : PASS
3687 12:14:18.636703 Jitter Meter : NO K
3688 12:14:18.639718 CBT Training : PASS
3689 12:14:18.643332 Write leveling : PASS
3690 12:14:18.643418 RX DQS gating : PASS
3691 12:14:18.646399 RX DQ/DQS(RDDQC) : PASS
3692 12:14:18.649551 TX DQ/DQS : PASS
3693 12:14:18.649630 RX DATLAT : PASS
3694 12:14:18.653266 RX DQ/DQS(Engine): PASS
3695 12:14:18.656363 TX OE : NO K
3696 12:14:18.656440 All Pass.
3697 12:14:18.656501
3698 12:14:18.656559 DramC Write-DBI off
3699 12:14:18.659784 PER_BANK_REFRESH: Hybrid Mode
3700 12:14:18.662761 TX_TRACKING: ON
3701 12:14:18.669362 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3702 12:14:18.672990 [FAST_K] Save calibration result to emmc
3703 12:14:18.679551 dramc_set_vcore_voltage set vcore to 650000
3704 12:14:18.679636 Read voltage for 600, 5
3705 12:14:18.682665 Vio18 = 0
3706 12:14:18.682744 Vcore = 650000
3707 12:14:18.682812 Vdram = 0
3708 12:14:18.685813 Vddq = 0
3709 12:14:18.685891 Vmddr = 0
3710 12:14:18.689557 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3711 12:14:18.695599 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3712 12:14:18.699244 MEM_TYPE=3, freq_sel=19
3713 12:14:18.702627 sv_algorithm_assistance_LP4_1600
3714 12:14:18.705895 ============ PULL DRAM RESETB DOWN ============
3715 12:14:18.709440 ========== PULL DRAM RESETB DOWN end =========
3716 12:14:18.712485 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3717 12:14:18.715564 ===================================
3718 12:14:18.718997 LPDDR4 DRAM CONFIGURATION
3719 12:14:18.722145 ===================================
3720 12:14:18.725596 EX_ROW_EN[0] = 0x0
3721 12:14:18.725671 EX_ROW_EN[1] = 0x0
3722 12:14:18.729124 LP4Y_EN = 0x0
3723 12:14:18.729195 WORK_FSP = 0x0
3724 12:14:18.732224 WL = 0x2
3725 12:14:18.732294 RL = 0x2
3726 12:14:18.735378 BL = 0x2
3727 12:14:18.739046 RPST = 0x0
3728 12:14:18.739116 RD_PRE = 0x0
3729 12:14:18.742169 WR_PRE = 0x1
3730 12:14:18.742245 WR_PST = 0x0
3731 12:14:18.745376 DBI_WR = 0x0
3732 12:14:18.745468 DBI_RD = 0x0
3733 12:14:18.748809 OTF = 0x1
3734 12:14:18.751869 ===================================
3735 12:14:18.755613 ===================================
3736 12:14:18.755714 ANA top config
3737 12:14:18.758620 ===================================
3738 12:14:18.762305 DLL_ASYNC_EN = 0
3739 12:14:18.765303 ALL_SLAVE_EN = 1
3740 12:14:18.765377 NEW_RANK_MODE = 1
3741 12:14:18.768774 DLL_IDLE_MODE = 1
3742 12:14:18.772148 LP45_APHY_COMB_EN = 1
3743 12:14:18.775101 TX_ODT_DIS = 1
3744 12:14:18.775200 NEW_8X_MODE = 1
3745 12:14:18.778570 ===================================
3746 12:14:18.782020 ===================================
3747 12:14:18.784933 data_rate = 1200
3748 12:14:18.788477 CKR = 1
3749 12:14:18.791589 DQ_P2S_RATIO = 8
3750 12:14:18.795320 ===================================
3751 12:14:18.798259 CA_P2S_RATIO = 8
3752 12:14:18.801458 DQ_CA_OPEN = 0
3753 12:14:18.805054 DQ_SEMI_OPEN = 0
3754 12:14:18.805133 CA_SEMI_OPEN = 0
3755 12:14:18.808157 CA_FULL_RATE = 0
3756 12:14:18.811254 DQ_CKDIV4_EN = 1
3757 12:14:18.814919 CA_CKDIV4_EN = 1
3758 12:14:18.817854 CA_PREDIV_EN = 0
3759 12:14:18.821508 PH8_DLY = 0
3760 12:14:18.821602 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3761 12:14:18.824998 DQ_AAMCK_DIV = 4
3762 12:14:18.828108 CA_AAMCK_DIV = 4
3763 12:14:18.831150 CA_ADMCK_DIV = 4
3764 12:14:18.834410 DQ_TRACK_CA_EN = 0
3765 12:14:18.838079 CA_PICK = 600
3766 12:14:18.838161 CA_MCKIO = 600
3767 12:14:18.841098 MCKIO_SEMI = 0
3768 12:14:18.844718 PLL_FREQ = 2288
3769 12:14:18.847749 DQ_UI_PI_RATIO = 32
3770 12:14:18.851280 CA_UI_PI_RATIO = 0
3771 12:14:18.854795 ===================================
3772 12:14:18.858026 ===================================
3773 12:14:18.861074 memory_type:LPDDR4
3774 12:14:18.861150 GP_NUM : 10
3775 12:14:18.864694 SRAM_EN : 1
3776 12:14:18.864802 MD32_EN : 0
3777 12:14:18.867776 ===================================
3778 12:14:18.870933 [ANA_INIT] >>>>>>>>>>>>>>
3779 12:14:18.874587 <<<<<< [CONFIGURE PHASE]: ANA_TX
3780 12:14:18.877556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3781 12:14:18.880684 ===================================
3782 12:14:18.884193 data_rate = 1200,PCW = 0X5800
3783 12:14:18.887540 ===================================
3784 12:14:18.890919 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3785 12:14:18.897514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3786 12:14:18.900592 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3787 12:14:18.907534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3788 12:14:18.911010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3789 12:14:18.914292 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3790 12:14:18.914395 [ANA_INIT] flow start
3791 12:14:18.917429 [ANA_INIT] PLL >>>>>>>>
3792 12:14:18.920519 [ANA_INIT] PLL <<<<<<<<
3793 12:14:18.920593 [ANA_INIT] MIDPI >>>>>>>>
3794 12:14:18.924127 [ANA_INIT] MIDPI <<<<<<<<
3795 12:14:18.927547 [ANA_INIT] DLL >>>>>>>>
3796 12:14:18.927618 [ANA_INIT] flow end
3797 12:14:18.934059 ============ LP4 DIFF to SE enter ============
3798 12:14:18.937523 ============ LP4 DIFF to SE exit ============
3799 12:14:18.940349 [ANA_INIT] <<<<<<<<<<<<<
3800 12:14:18.944072 [Flow] Enable top DCM control >>>>>
3801 12:14:18.947119 [Flow] Enable top DCM control <<<<<
3802 12:14:18.947202 Enable DLL master slave shuffle
3803 12:14:18.953659 ==============================================================
3804 12:14:18.957139 Gating Mode config
3805 12:14:18.960244 ==============================================================
3806 12:14:18.963735 Config description:
3807 12:14:18.973803 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3808 12:14:18.980376 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3809 12:14:18.983401 SELPH_MODE 0: By rank 1: By Phase
3810 12:14:18.990241 ==============================================================
3811 12:14:18.993645 GAT_TRACK_EN = 1
3812 12:14:18.996564 RX_GATING_MODE = 2
3813 12:14:19.000048 RX_GATING_TRACK_MODE = 2
3814 12:14:19.003276 SELPH_MODE = 1
3815 12:14:19.006761 PICG_EARLY_EN = 1
3816 12:14:19.006871 VALID_LAT_VALUE = 1
3817 12:14:19.013341 ==============================================================
3818 12:14:19.016388 Enter into Gating configuration >>>>
3819 12:14:19.020099 Exit from Gating configuration <<<<
3820 12:14:19.023321 Enter into DVFS_PRE_config >>>>>
3821 12:14:19.033179 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3822 12:14:19.036269 Exit from DVFS_PRE_config <<<<<
3823 12:14:19.039912 Enter into PICG configuration >>>>
3824 12:14:19.042946 Exit from PICG configuration <<<<
3825 12:14:19.046134 [RX_INPUT] configuration >>>>>
3826 12:14:19.049864 [RX_INPUT] configuration <<<<<
3827 12:14:19.056034 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3828 12:14:19.059524 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3829 12:14:19.066274 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3830 12:14:19.072762 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3831 12:14:19.079501 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3832 12:14:19.086292 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3833 12:14:19.089348 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3834 12:14:19.092947 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3835 12:14:19.095792 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3836 12:14:19.102737 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3837 12:14:19.106275 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3838 12:14:19.109336 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3839 12:14:19.112819 ===================================
3840 12:14:19.115955 LPDDR4 DRAM CONFIGURATION
3841 12:14:19.119541 ===================================
3842 12:14:19.119626 EX_ROW_EN[0] = 0x0
3843 12:14:19.122488 EX_ROW_EN[1] = 0x0
3844 12:14:19.125949 LP4Y_EN = 0x0
3845 12:14:19.126032 WORK_FSP = 0x0
3846 12:14:19.129097 WL = 0x2
3847 12:14:19.129181 RL = 0x2
3848 12:14:19.132602 BL = 0x2
3849 12:14:19.132685 RPST = 0x0
3850 12:14:19.135647 RD_PRE = 0x0
3851 12:14:19.135731 WR_PRE = 0x1
3852 12:14:19.139280 WR_PST = 0x0
3853 12:14:19.139364 DBI_WR = 0x0
3854 12:14:19.142397 DBI_RD = 0x0
3855 12:14:19.142480 OTF = 0x1
3856 12:14:19.145494 ===================================
3857 12:14:19.149008 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3858 12:14:19.155823 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3859 12:14:19.158862 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3860 12:14:19.162461 ===================================
3861 12:14:19.165428 LPDDR4 DRAM CONFIGURATION
3862 12:14:19.169135 ===================================
3863 12:14:19.169218 EX_ROW_EN[0] = 0x10
3864 12:14:19.172273 EX_ROW_EN[1] = 0x0
3865 12:14:19.175396 LP4Y_EN = 0x0
3866 12:14:19.175479 WORK_FSP = 0x0
3867 12:14:19.178891 WL = 0x2
3868 12:14:19.178973 RL = 0x2
3869 12:14:19.182146 BL = 0x2
3870 12:14:19.182229 RPST = 0x0
3871 12:14:19.185336 RD_PRE = 0x0
3872 12:14:19.185419 WR_PRE = 0x1
3873 12:14:19.188848 WR_PST = 0x0
3874 12:14:19.188932 DBI_WR = 0x0
3875 12:14:19.191925 DBI_RD = 0x0
3876 12:14:19.192007 OTF = 0x1
3877 12:14:19.195481 ===================================
3878 12:14:19.201780 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3879 12:14:19.206363 nWR fixed to 30
3880 12:14:19.209292 [ModeRegInit_LP4] CH0 RK0
3881 12:14:19.209377 [ModeRegInit_LP4] CH0 RK1
3882 12:14:19.212609 [ModeRegInit_LP4] CH1 RK0
3883 12:14:19.216247 [ModeRegInit_LP4] CH1 RK1
3884 12:14:19.216353 match AC timing 17
3885 12:14:19.223010 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3886 12:14:19.226016 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3887 12:14:19.229236 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3888 12:14:19.235932 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3889 12:14:19.239447 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3890 12:14:19.239529 ==
3891 12:14:19.242527 Dram Type= 6, Freq= 0, CH_0, rank 0
3892 12:14:19.246191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3893 12:14:19.246273 ==
3894 12:14:19.252337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3895 12:14:19.259175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3896 12:14:19.262250 [CA 0] Center 36 (6~67) winsize 62
3897 12:14:19.265979 [CA 1] Center 36 (6~67) winsize 62
3898 12:14:19.269000 [CA 2] Center 34 (4~65) winsize 62
3899 12:14:19.272021 [CA 3] Center 34 (4~65) winsize 62
3900 12:14:19.275697 [CA 4] Center 34 (3~65) winsize 63
3901 12:14:19.278870 [CA 5] Center 33 (3~64) winsize 62
3902 12:14:19.279010
3903 12:14:19.281900 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3904 12:14:19.281982
3905 12:14:19.285532 [CATrainingPosCal] consider 1 rank data
3906 12:14:19.288650 u2DelayCellTimex100 = 270/100 ps
3907 12:14:19.291825 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3908 12:14:19.295420 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3909 12:14:19.298625 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3910 12:14:19.305904 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3911 12:14:19.308622 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3912 12:14:19.311921 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3913 12:14:19.312019
3914 12:14:19.314931 CA PerBit enable=1, Macro0, CA PI delay=33
3915 12:14:19.315009
3916 12:14:19.318254 [CBTSetCACLKResult] CA Dly = 33
3917 12:14:19.318352 CS Dly: 5 (0~36)
3918 12:14:19.318444 ==
3919 12:14:19.321616 Dram Type= 6, Freq= 0, CH_0, rank 1
3920 12:14:19.328413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3921 12:14:19.328498 ==
3922 12:14:19.331467 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3923 12:14:19.338287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3924 12:14:19.341361 [CA 0] Center 36 (6~67) winsize 62
3925 12:14:19.344762 [CA 1] Center 36 (6~67) winsize 62
3926 12:14:19.347937 [CA 2] Center 35 (5~66) winsize 62
3927 12:14:19.351521 [CA 3] Center 35 (4~66) winsize 63
3928 12:14:19.354511 [CA 4] Center 34 (3~65) winsize 63
3929 12:14:19.358075 [CA 5] Center 33 (3~64) winsize 62
3930 12:14:19.358158
3931 12:14:19.361264 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3932 12:14:19.361347
3933 12:14:19.364761 [CATrainingPosCal] consider 2 rank data
3934 12:14:19.367894 u2DelayCellTimex100 = 270/100 ps
3935 12:14:19.371102 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3936 12:14:19.378147 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3937 12:14:19.381275 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3938 12:14:19.384337 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3939 12:14:19.387947 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3940 12:14:19.391028 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3941 12:14:19.391111
3942 12:14:19.394296 CA PerBit enable=1, Macro0, CA PI delay=33
3943 12:14:19.394379
3944 12:14:19.397479 [CBTSetCACLKResult] CA Dly = 33
3945 12:14:19.401029 CS Dly: 5 (0~36)
3946 12:14:19.401112
3947 12:14:19.404216 ----->DramcWriteLeveling(PI) begin...
3948 12:14:19.404300 ==
3949 12:14:19.407777 Dram Type= 6, Freq= 0, CH_0, rank 0
3950 12:14:19.410684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 12:14:19.410767 ==
3952 12:14:19.414346 Write leveling (Byte 0): 33 => 33
3953 12:14:19.417589 Write leveling (Byte 1): 30 => 30
3954 12:14:19.420915 DramcWriteLeveling(PI) end<-----
3955 12:14:19.420998
3956 12:14:19.421062 ==
3957 12:14:19.424202 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 12:14:19.427535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 12:14:19.427619 ==
3960 12:14:19.430681 [Gating] SW mode calibration
3961 12:14:19.437423 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3962 12:14:19.443661 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3963 12:14:19.447232 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3964 12:14:19.450384 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3965 12:14:19.457321 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 12:14:19.460405 0 9 12 | B1->B0 | 3333 3030 | 1 0 | (1 0) (1 0)
3967 12:14:19.463560 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
3968 12:14:19.470107 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 12:14:19.473857 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 12:14:19.476891 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 12:14:19.483521 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 12:14:19.486661 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 12:14:19.489855 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3974 12:14:19.496501 0 10 12 | B1->B0 | 2929 3636 | 0 0 | (0 0) (0 0)
3975 12:14:19.500263 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
3976 12:14:19.503456 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 12:14:19.510064 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 12:14:19.513168 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 12:14:19.516311 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 12:14:19.523210 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 12:14:19.526138 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 12:14:19.529582 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3983 12:14:19.536514 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 12:14:19.539756 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 12:14:19.543132 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 12:14:19.549809 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 12:14:19.552802 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 12:14:19.556361 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 12:14:19.563091 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 12:14:19.566055 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 12:14:19.569647 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 12:14:19.576162 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 12:14:19.579189 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 12:14:19.582522 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 12:14:19.589424 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 12:14:19.592543 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 12:14:19.595557 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3998 12:14:19.602345 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3999 12:14:19.605963 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 12:14:19.609188 Total UI for P1: 0, mck2ui 16
4001 12:14:19.612356 best dqsien dly found for B0: ( 0, 13, 10)
4002 12:14:19.615864 Total UI for P1: 0, mck2ui 16
4003 12:14:19.618980 best dqsien dly found for B1: ( 0, 13, 12)
4004 12:14:19.622067 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4005 12:14:19.625471 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4006 12:14:19.625574
4007 12:14:19.629108 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4008 12:14:19.632100 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4009 12:14:19.635492 [Gating] SW calibration Done
4010 12:14:19.635581 ==
4011 12:14:19.638704 Dram Type= 6, Freq= 0, CH_0, rank 0
4012 12:14:19.645257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 12:14:19.645334 ==
4014 12:14:19.645412 RX Vref Scan: 0
4015 12:14:19.645473
4016 12:14:19.648748 RX Vref 0 -> 0, step: 1
4017 12:14:19.648855
4018 12:14:19.651990 RX Delay -230 -> 252, step: 16
4019 12:14:19.655481 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4020 12:14:19.658835 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4021 12:14:19.662122 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4022 12:14:19.668229 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4023 12:14:19.671847 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4024 12:14:19.674990 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4025 12:14:19.678585 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4026 12:14:19.684859 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4027 12:14:19.688310 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4028 12:14:19.691433 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4029 12:14:19.695184 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4030 12:14:19.698346 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4031 12:14:19.704666 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4032 12:14:19.707935 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4033 12:14:19.711042 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4034 12:14:19.717813 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4035 12:14:19.717890 ==
4036 12:14:19.721374 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 12:14:19.724312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 12:14:19.724384 ==
4039 12:14:19.724444 DQS Delay:
4040 12:14:19.727953 DQS0 = 0, DQS1 = 0
4041 12:14:19.728021 DQM Delay:
4042 12:14:19.731323 DQM0 = 51, DQM1 = 42
4043 12:14:19.731395 DQ Delay:
4044 12:14:19.734539 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4045 12:14:19.737643 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4046 12:14:19.741154 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4047 12:14:19.744510 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4048 12:14:19.744582
4049 12:14:19.744643
4050 12:14:19.744700 ==
4051 12:14:19.747572 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 12:14:19.750934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 12:14:19.751005 ==
4054 12:14:19.751064
4055 12:14:19.751129
4056 12:14:19.754265 TX Vref Scan disable
4057 12:14:19.757774 == TX Byte 0 ==
4058 12:14:19.760817 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4059 12:14:19.764366 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4060 12:14:19.767446 == TX Byte 1 ==
4061 12:14:19.770491 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4062 12:14:19.773945 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4063 12:14:19.774030 ==
4064 12:14:19.777538 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 12:14:19.783779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 12:14:19.783863 ==
4067 12:14:19.783948
4068 12:14:19.784027
4069 12:14:19.786835 TX Vref Scan disable
4070 12:14:19.786919 == TX Byte 0 ==
4071 12:14:19.793505 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4072 12:14:19.797045 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4073 12:14:19.797129 == TX Byte 1 ==
4074 12:14:19.803415 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4075 12:14:19.806983 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4076 12:14:19.807067
4077 12:14:19.807152 [DATLAT]
4078 12:14:19.810137 Freq=600, CH0 RK0
4079 12:14:19.810221
4080 12:14:19.810304 DATLAT Default: 0x9
4081 12:14:19.813323 0, 0xFFFF, sum = 0
4082 12:14:19.813409 1, 0xFFFF, sum = 0
4083 12:14:19.816989 2, 0xFFFF, sum = 0
4084 12:14:19.820011 3, 0xFFFF, sum = 0
4085 12:14:19.820096 4, 0xFFFF, sum = 0
4086 12:14:19.823513 5, 0xFFFF, sum = 0
4087 12:14:19.823598 6, 0xFFFF, sum = 0
4088 12:14:19.826939 7, 0xFFFF, sum = 0
4089 12:14:19.827024 8, 0x0, sum = 1
4090 12:14:19.827109 9, 0x0, sum = 2
4091 12:14:19.830099 10, 0x0, sum = 3
4092 12:14:19.830184 11, 0x0, sum = 4
4093 12:14:19.833139 best_step = 9
4094 12:14:19.833222
4095 12:14:19.833306 ==
4096 12:14:19.836465 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 12:14:19.839967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 12:14:19.840052 ==
4099 12:14:19.843019 RX Vref Scan: 1
4100 12:14:19.843102
4101 12:14:19.843186 RX Vref 0 -> 0, step: 1
4102 12:14:19.846475
4103 12:14:19.846559 RX Delay -163 -> 252, step: 8
4104 12:14:19.846644
4105 12:14:19.849979 Set Vref, RX VrefLevel [Byte0]: 58
4106 12:14:19.853021 [Byte1]: 50
4107 12:14:19.857400
4108 12:14:19.857483 Final RX Vref Byte 0 = 58 to rank0
4109 12:14:19.860800 Final RX Vref Byte 1 = 50 to rank0
4110 12:14:19.864055 Final RX Vref Byte 0 = 58 to rank1
4111 12:14:19.867147 Final RX Vref Byte 1 = 50 to rank1==
4112 12:14:19.870477 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 12:14:19.877247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 12:14:19.877333 ==
4115 12:14:19.877418 DQS Delay:
4116 12:14:19.880204 DQS0 = 0, DQS1 = 0
4117 12:14:19.880287 DQM Delay:
4118 12:14:19.880371 DQM0 = 49, DQM1 = 39
4119 12:14:19.883791 DQ Delay:
4120 12:14:19.886792 DQ0 =44, DQ1 =52, DQ2 =48, DQ3 =44
4121 12:14:19.890419 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4122 12:14:19.893470 DQ8 =32, DQ9 =28, DQ10 =36, DQ11 =32
4123 12:14:19.897110 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4124 12:14:19.897194
4125 12:14:19.897278
4126 12:14:19.903840 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c56, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4127 12:14:19.906863 CH0 RK0: MR19=808, MR18=5C56
4128 12:14:19.913672 CH0_RK0: MR19=0x808, MR18=0x5C56, DQSOSC=392, MR23=63, INC=170, DEC=113
4129 12:14:19.913758
4130 12:14:19.916751 ----->DramcWriteLeveling(PI) begin...
4131 12:14:19.916858 ==
4132 12:14:19.919906 Dram Type= 6, Freq= 0, CH_0, rank 1
4133 12:14:19.923200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 12:14:19.923284 ==
4135 12:14:19.926856 Write leveling (Byte 0): 33 => 33
4136 12:14:19.929971 Write leveling (Byte 1): 29 => 29
4137 12:14:19.933546 DramcWriteLeveling(PI) end<-----
4138 12:14:19.933647
4139 12:14:19.933744 ==
4140 12:14:19.936480 Dram Type= 6, Freq= 0, CH_0, rank 1
4141 12:14:19.940002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 12:14:19.943046 ==
4143 12:14:19.943132 [Gating] SW mode calibration
4144 12:14:19.952761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4145 12:14:19.956391 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4146 12:14:19.959839 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4147 12:14:19.966057 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4148 12:14:19.969451 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4149 12:14:19.972698 0 9 12 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
4150 12:14:19.979435 0 9 16 | B1->B0 | 2525 2525 | 1 0 | (0 0) (0 0)
4151 12:14:19.982727 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4152 12:14:19.986164 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 12:14:19.992451 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 12:14:19.995974 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 12:14:19.999171 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 12:14:20.005927 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 12:14:20.009081 0 10 12 | B1->B0 | 2d2d 2e2e | 1 0 | (0 0) (1 1)
4158 12:14:20.012271 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4159 12:14:20.019176 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4160 12:14:20.022406 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 12:14:20.025463 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 12:14:20.032100 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 12:14:20.035668 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 12:14:20.038659 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 12:14:20.045551 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4166 12:14:20.048619 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 12:14:20.052273 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 12:14:20.058655 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 12:14:20.062137 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 12:14:20.065331 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 12:14:20.071937 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 12:14:20.075532 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 12:14:20.078403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 12:14:20.085091 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 12:14:20.088403 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 12:14:20.091646 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 12:14:20.098264 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 12:14:20.101807 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 12:14:20.104697 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 12:14:20.111481 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 12:14:20.114743 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:14:20.118331 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4183 12:14:20.121401 Total UI for P1: 0, mck2ui 16
4184 12:14:20.124980 best dqsien dly found for B0: ( 0, 13, 14)
4185 12:14:20.131286 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 12:14:20.131370 Total UI for P1: 0, mck2ui 16
4187 12:14:20.134871 best dqsien dly found for B1: ( 0, 13, 16)
4188 12:14:20.141567 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4189 12:14:20.144562 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4190 12:14:20.144646
4191 12:14:20.147973 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4192 12:14:20.151163 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4193 12:14:20.154762 [Gating] SW calibration Done
4194 12:14:20.154846 ==
4195 12:14:20.157671 Dram Type= 6, Freq= 0, CH_0, rank 1
4196 12:14:20.161202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 12:14:20.161287 ==
4198 12:14:20.164411 RX Vref Scan: 0
4199 12:14:20.164495
4200 12:14:20.164595 RX Vref 0 -> 0, step: 1
4201 12:14:20.164693
4202 12:14:20.167871 RX Delay -230 -> 252, step: 16
4203 12:14:20.174567 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4204 12:14:20.177620 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4205 12:14:20.181232 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4206 12:14:20.184191 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4207 12:14:20.187872 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4208 12:14:20.194265 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4209 12:14:20.197643 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4210 12:14:20.201033 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4211 12:14:20.204385 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4212 12:14:20.210537 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4213 12:14:20.214275 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4214 12:14:20.217482 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4215 12:14:20.220589 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4216 12:14:20.227301 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4217 12:14:20.230365 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4218 12:14:20.234112 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4219 12:14:20.234223 ==
4220 12:14:20.237263 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 12:14:20.240345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 12:14:20.240444 ==
4223 12:14:20.243905 DQS Delay:
4224 12:14:20.244004 DQS0 = 0, DQS1 = 0
4225 12:14:20.247127 DQM Delay:
4226 12:14:20.247222 DQM0 = 47, DQM1 = 43
4227 12:14:20.250485 DQ Delay:
4228 12:14:20.250594 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4229 12:14:20.253544 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4230 12:14:20.257108 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4231 12:14:20.260301 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4232 12:14:20.260409
4233 12:14:20.260502
4234 12:14:20.263697 ==
4235 12:14:20.267327 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 12:14:20.270304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 12:14:20.270392 ==
4238 12:14:20.270459
4239 12:14:20.270519
4240 12:14:20.273797 TX Vref Scan disable
4241 12:14:20.273880 == TX Byte 0 ==
4242 12:14:20.280500 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4243 12:14:20.283535 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4244 12:14:20.283620 == TX Byte 1 ==
4245 12:14:20.290001 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4246 12:14:20.293333 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4247 12:14:20.293439 ==
4248 12:14:20.296960 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 12:14:20.299801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 12:14:20.299899 ==
4251 12:14:20.299988
4252 12:14:20.300074
4253 12:14:20.303253 TX Vref Scan disable
4254 12:14:20.306823 == TX Byte 0 ==
4255 12:14:20.309741 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4256 12:14:20.313591 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4257 12:14:20.316546 == TX Byte 1 ==
4258 12:14:20.319635 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4259 12:14:20.323175 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4260 12:14:20.326349
4261 12:14:20.326448 [DATLAT]
4262 12:14:20.326539 Freq=600, CH0 RK1
4263 12:14:20.326627
4264 12:14:20.330081 DATLAT Default: 0x9
4265 12:14:20.330155 0, 0xFFFF, sum = 0
4266 12:14:20.333316 1, 0xFFFF, sum = 0
4267 12:14:20.333386 2, 0xFFFF, sum = 0
4268 12:14:20.336472 3, 0xFFFF, sum = 0
4269 12:14:20.340191 4, 0xFFFF, sum = 0
4270 12:14:20.340274 5, 0xFFFF, sum = 0
4271 12:14:20.343155 6, 0xFFFF, sum = 0
4272 12:14:20.343243 7, 0xFFFF, sum = 0
4273 12:14:20.346239 8, 0x0, sum = 1
4274 12:14:20.346349 9, 0x0, sum = 2
4275 12:14:20.346448 10, 0x0, sum = 3
4276 12:14:20.349421 11, 0x0, sum = 4
4277 12:14:20.349533 best_step = 9
4278 12:14:20.349625
4279 12:14:20.349714 ==
4280 12:14:20.352942 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 12:14:20.359400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 12:14:20.359486 ==
4283 12:14:20.359552 RX Vref Scan: 0
4284 12:14:20.359612
4285 12:14:20.363004 RX Vref 0 -> 0, step: 1
4286 12:14:20.363086
4287 12:14:20.366198 RX Delay -163 -> 252, step: 8
4288 12:14:20.369651 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4289 12:14:20.376250 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4290 12:14:20.379362 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4291 12:14:20.382504 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4292 12:14:20.386168 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4293 12:14:20.389254 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4294 12:14:20.395612 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4295 12:14:20.399197 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4296 12:14:20.402199 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4297 12:14:20.405553 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4298 12:14:20.412328 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4299 12:14:20.415814 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4300 12:14:20.418760 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4301 12:14:20.422236 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4302 12:14:20.425400 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4303 12:14:20.432210 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4304 12:14:20.432291 ==
4305 12:14:20.435372 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 12:14:20.439002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 12:14:20.439084 ==
4308 12:14:20.439148 DQS Delay:
4309 12:14:20.442153 DQS0 = 0, DQS1 = 0
4310 12:14:20.442232 DQM Delay:
4311 12:14:20.445237 DQM0 = 48, DQM1 = 40
4312 12:14:20.445321 DQ Delay:
4313 12:14:20.448856 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4314 12:14:20.451855 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4315 12:14:20.455549 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4316 12:14:20.458517 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4317 12:14:20.458629
4318 12:14:20.458694
4319 12:14:20.468348 [DQSOSCAuto] RK1, (LSB)MR18= 0x612e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4320 12:14:20.468456 CH0 RK1: MR19=808, MR18=612E
4321 12:14:20.475200 CH0_RK1: MR19=0x808, MR18=0x612E, DQSOSC=391, MR23=63, INC=171, DEC=114
4322 12:14:20.478310 [RxdqsGatingPostProcess] freq 600
4323 12:14:20.485292 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4324 12:14:20.488501 Pre-setting of DQS Precalculation
4325 12:14:20.491571 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4326 12:14:20.491662 ==
4327 12:14:20.495184 Dram Type= 6, Freq= 0, CH_1, rank 0
4328 12:14:20.501531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 12:14:20.501615 ==
4330 12:14:20.505140 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4331 12:14:20.511704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4332 12:14:20.514533 [CA 0] Center 35 (5~66) winsize 62
4333 12:14:20.517779 [CA 1] Center 35 (5~66) winsize 62
4334 12:14:20.521265 [CA 2] Center 34 (3~65) winsize 63
4335 12:14:20.524713 [CA 3] Center 33 (3~64) winsize 62
4336 12:14:20.527715 [CA 4] Center 34 (3~65) winsize 63
4337 12:14:20.531270 [CA 5] Center 33 (3~64) winsize 62
4338 12:14:20.531377
4339 12:14:20.534459 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4340 12:14:20.534563
4341 12:14:20.537595 [CATrainingPosCal] consider 1 rank data
4342 12:14:20.540688 u2DelayCellTimex100 = 270/100 ps
4343 12:14:20.544433 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4344 12:14:20.550657 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4345 12:14:20.554397 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4346 12:14:20.557522 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4347 12:14:20.560592 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4348 12:14:20.564214 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4349 12:14:20.564353
4350 12:14:20.567169 CA PerBit enable=1, Macro0, CA PI delay=33
4351 12:14:20.567263
4352 12:14:20.570858 [CBTSetCACLKResult] CA Dly = 33
4353 12:14:20.570954 CS Dly: 4 (0~35)
4354 12:14:20.573781 ==
4355 12:14:20.577504 Dram Type= 6, Freq= 0, CH_1, rank 1
4356 12:14:20.580626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 12:14:20.580735 ==
4358 12:14:20.587273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4359 12:14:20.590472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4360 12:14:20.594839 [CA 0] Center 35 (5~66) winsize 62
4361 12:14:20.597860 [CA 1] Center 35 (5~66) winsize 62
4362 12:14:20.600955 [CA 2] Center 34 (4~65) winsize 62
4363 12:14:20.604406 [CA 3] Center 34 (3~65) winsize 63
4364 12:14:20.607404 [CA 4] Center 34 (4~65) winsize 62
4365 12:14:20.611182 [CA 5] Center 34 (3~65) winsize 63
4366 12:14:20.611261
4367 12:14:20.614334 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4368 12:14:20.614410
4369 12:14:20.617336 [CATrainingPosCal] consider 2 rank data
4370 12:14:20.620748 u2DelayCellTimex100 = 270/100 ps
4371 12:14:20.624307 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4372 12:14:20.630532 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4373 12:14:20.633858 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 12:14:20.637265 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 12:14:20.640405 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4376 12:14:20.643925 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4377 12:14:20.644008
4378 12:14:20.647086 CA PerBit enable=1, Macro0, CA PI delay=33
4379 12:14:20.647169
4380 12:14:20.650318 [CBTSetCACLKResult] CA Dly = 33
4381 12:14:20.653864 CS Dly: 4 (0~36)
4382 12:14:20.653947
4383 12:14:20.656896 ----->DramcWriteLeveling(PI) begin...
4384 12:14:20.656981 ==
4385 12:14:20.660492 Dram Type= 6, Freq= 0, CH_1, rank 0
4386 12:14:20.663561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 12:14:20.663645 ==
4388 12:14:20.666954 Write leveling (Byte 0): 30 => 30
4389 12:14:20.670155 Write leveling (Byte 1): 30 => 30
4390 12:14:20.673306 DramcWriteLeveling(PI) end<-----
4391 12:14:20.673388
4392 12:14:20.673453 ==
4393 12:14:20.676460 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 12:14:20.680029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 12:14:20.680113 ==
4396 12:14:20.683134 [Gating] SW mode calibration
4397 12:14:20.690105 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4398 12:14:20.696452 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4399 12:14:20.700145 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4400 12:14:20.703103 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4401 12:14:20.709541 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4402 12:14:20.713009 0 9 12 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (1 1)
4403 12:14:20.716143 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 12:14:20.722666 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 12:14:20.726265 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 12:14:20.732549 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 12:14:20.736014 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 12:14:20.739407 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 12:14:20.742389 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4410 12:14:20.749375 0 10 12 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
4411 12:14:20.752476 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 12:14:20.755616 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 12:14:20.762271 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 12:14:20.765761 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 12:14:20.768803 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 12:14:20.775867 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 12:14:20.779087 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 12:14:20.782181 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4419 12:14:20.788970 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 12:14:20.792066 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 12:14:20.795539 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 12:14:20.802207 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 12:14:20.805434 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 12:14:20.809088 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 12:14:20.815399 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 12:14:20.818558 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 12:14:20.821723 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 12:14:20.828405 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 12:14:20.831967 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 12:14:20.835072 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 12:14:20.841650 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 12:14:20.844911 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:14:20.848491 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:14:20.855035 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4435 12:14:20.858159 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 12:14:20.861324 Total UI for P1: 0, mck2ui 16
4437 12:14:20.864914 best dqsien dly found for B0: ( 0, 13, 12)
4438 12:14:20.868102 Total UI for P1: 0, mck2ui 16
4439 12:14:20.871507 best dqsien dly found for B1: ( 0, 13, 12)
4440 12:14:20.874537 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4441 12:14:20.878060 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4442 12:14:20.878142
4443 12:14:20.881132 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4444 12:14:20.887728 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4445 12:14:20.887810 [Gating] SW calibration Done
4446 12:14:20.887875 ==
4447 12:14:20.891375 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 12:14:20.897909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 12:14:20.897989 ==
4450 12:14:20.898053 RX Vref Scan: 0
4451 12:14:20.898113
4452 12:14:20.901541 RX Vref 0 -> 0, step: 1
4453 12:14:20.901623
4454 12:14:20.904408 RX Delay -230 -> 252, step: 16
4455 12:14:20.907849 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4456 12:14:20.911084 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4457 12:14:20.917672 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4458 12:14:20.921295 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4459 12:14:20.924444 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4460 12:14:20.927595 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4461 12:14:20.931062 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4462 12:14:20.937673 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4463 12:14:20.940711 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4464 12:14:20.944392 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4465 12:14:20.947444 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4466 12:14:20.954241 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4467 12:14:20.957650 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4468 12:14:20.960923 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4469 12:14:20.963946 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4470 12:14:20.970749 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4471 12:14:20.970832 ==
4472 12:14:20.973815 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 12:14:20.977362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 12:14:20.977448 ==
4475 12:14:20.977515 DQS Delay:
4476 12:14:20.980843 DQS0 = 0, DQS1 = 0
4477 12:14:20.980953 DQM Delay:
4478 12:14:20.983929 DQM0 = 50, DQM1 = 45
4479 12:14:20.984004 DQ Delay:
4480 12:14:20.987053 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4481 12:14:20.990750 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4482 12:14:20.993987 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4483 12:14:20.997175 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4484 12:14:20.997260
4485 12:14:20.997326
4486 12:14:20.997387 ==
4487 12:14:21.000175 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 12:14:21.003747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 12:14:21.003858 ==
4490 12:14:21.003956
4491 12:14:21.004050
4492 12:14:21.007300 TX Vref Scan disable
4493 12:14:21.010338 == TX Byte 0 ==
4494 12:14:21.013529 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4495 12:14:21.017381 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4496 12:14:21.020282 == TX Byte 1 ==
4497 12:14:21.023481 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4498 12:14:21.027134 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4499 12:14:21.027245 ==
4500 12:14:21.030196 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 12:14:21.036646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 12:14:21.036757 ==
4503 12:14:21.036848
4504 12:14:21.036938
4505 12:14:21.037028 TX Vref Scan disable
4506 12:14:21.041350 == TX Byte 0 ==
4507 12:14:21.044605 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4508 12:14:21.051325 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4509 12:14:21.051442 == TX Byte 1 ==
4510 12:14:21.054444 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4511 12:14:21.061152 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4512 12:14:21.061328
4513 12:14:21.061424 [DATLAT]
4514 12:14:21.061516 Freq=600, CH1 RK0
4515 12:14:21.061655
4516 12:14:21.064552 DATLAT Default: 0x9
4517 12:14:21.064646 0, 0xFFFF, sum = 0
4518 12:14:21.067879 1, 0xFFFF, sum = 0
4519 12:14:21.071131 2, 0xFFFF, sum = 0
4520 12:14:21.071242 3, 0xFFFF, sum = 0
4521 12:14:21.074132 4, 0xFFFF, sum = 0
4522 12:14:21.074244 5, 0xFFFF, sum = 0
4523 12:14:21.077651 6, 0xFFFF, sum = 0
4524 12:14:21.077735 7, 0xFFFF, sum = 0
4525 12:14:21.080763 8, 0x0, sum = 1
4526 12:14:21.080909 9, 0x0, sum = 2
4527 12:14:21.080977 10, 0x0, sum = 3
4528 12:14:21.084345 11, 0x0, sum = 4
4529 12:14:21.084455 best_step = 9
4530 12:14:21.084548
4531 12:14:21.087438 ==
4532 12:14:21.087549 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 12:14:21.094036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 12:14:21.094120 ==
4535 12:14:21.094191 RX Vref Scan: 1
4536 12:14:21.094255
4537 12:14:21.097027 RX Vref 0 -> 0, step: 1
4538 12:14:21.097109
4539 12:14:21.100606 RX Delay -179 -> 252, step: 8
4540 12:14:21.100689
4541 12:14:21.103667 Set Vref, RX VrefLevel [Byte0]: 54
4542 12:14:21.107291 [Byte1]: 52
4543 12:14:21.107374
4544 12:14:21.110357 Final RX Vref Byte 0 = 54 to rank0
4545 12:14:21.113483 Final RX Vref Byte 1 = 52 to rank0
4546 12:14:21.117146 Final RX Vref Byte 0 = 54 to rank1
4547 12:14:21.120219 Final RX Vref Byte 1 = 52 to rank1==
4548 12:14:21.123653 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 12:14:21.130221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 12:14:21.130306 ==
4551 12:14:21.130374 DQS Delay:
4552 12:14:21.130436 DQS0 = 0, DQS1 = 0
4553 12:14:21.133397 DQM Delay:
4554 12:14:21.133481 DQM0 = 48, DQM1 = 40
4555 12:14:21.136466 DQ Delay:
4556 12:14:21.139947 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4557 12:14:21.143077 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4558 12:14:21.146724 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4559 12:14:21.149819 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4560 12:14:21.149903
4561 12:14:21.149969
4562 12:14:21.156402 [DQSOSCAuto] RK0, (LSB)MR18= 0x486e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4563 12:14:21.159863 CH1 RK0: MR19=808, MR18=486E
4564 12:14:21.166359 CH1_RK0: MR19=0x808, MR18=0x486E, DQSOSC=389, MR23=63, INC=173, DEC=115
4565 12:14:21.166444
4566 12:14:21.169783 ----->DramcWriteLeveling(PI) begin...
4567 12:14:21.169889 ==
4568 12:14:21.173069 Dram Type= 6, Freq= 0, CH_1, rank 1
4569 12:14:21.176318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 12:14:21.176424 ==
4571 12:14:21.179250 Write leveling (Byte 0): 30 => 30
4572 12:14:21.182821 Write leveling (Byte 1): 30 => 30
4573 12:14:21.185957 DramcWriteLeveling(PI) end<-----
4574 12:14:21.186067
4575 12:14:21.186143 ==
4576 12:14:21.189503 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 12:14:21.192645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 12:14:21.192747 ==
4579 12:14:21.195701 [Gating] SW mode calibration
4580 12:14:21.202751 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4581 12:14:21.209283 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4582 12:14:21.212403 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4583 12:14:21.219108 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4584 12:14:21.222608 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4585 12:14:21.225799 0 9 12 | B1->B0 | 2b2b 3030 | 1 0 | (1 0) (0 1)
4586 12:14:21.232624 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
4587 12:14:21.235648 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 12:14:21.239173 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 12:14:21.245406 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 12:14:21.249057 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 12:14:21.252199 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 12:14:21.258971 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4593 12:14:21.262112 0 10 12 | B1->B0 | 3d3d 3434 | 0 0 | (0 0) (0 0)
4594 12:14:21.265630 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4595 12:14:21.272324 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 12:14:21.275262 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 12:14:21.278619 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 12:14:21.285103 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 12:14:21.288279 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 12:14:21.291851 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 12:14:21.298324 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4602 12:14:21.301511 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4603 12:14:21.305037 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 12:14:21.311706 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 12:14:21.314643 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 12:14:21.318253 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 12:14:21.324890 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 12:14:21.327998 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 12:14:21.331500 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 12:14:21.338045 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 12:14:21.341086 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 12:14:21.344695 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 12:14:21.351315 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 12:14:21.354447 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 12:14:21.357518 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 12:14:21.364169 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:14:21.367745 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4618 12:14:21.371283 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 12:14:21.374315 Total UI for P1: 0, mck2ui 16
4620 12:14:21.377526 best dqsien dly found for B0: ( 0, 13, 12)
4621 12:14:21.381166 Total UI for P1: 0, mck2ui 16
4622 12:14:21.384231 best dqsien dly found for B1: ( 0, 13, 12)
4623 12:14:21.387488 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4624 12:14:21.390900 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4625 12:14:21.391011
4626 12:14:21.397247 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4627 12:14:21.400529 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4628 12:14:21.403812 [Gating] SW calibration Done
4629 12:14:21.403916 ==
4630 12:14:21.407359 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 12:14:21.410720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 12:14:21.410842 ==
4633 12:14:21.410974 RX Vref Scan: 0
4634 12:14:21.411073
4635 12:14:21.414018 RX Vref 0 -> 0, step: 1
4636 12:14:21.414140
4637 12:14:21.416813 RX Delay -230 -> 252, step: 16
4638 12:14:21.420313 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4639 12:14:21.423348 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4640 12:14:21.430056 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4641 12:14:21.433583 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4642 12:14:21.436528 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4643 12:14:21.440144 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4644 12:14:21.446466 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4645 12:14:21.450132 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4646 12:14:21.453191 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4647 12:14:21.456410 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4648 12:14:21.460020 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4649 12:14:21.466658 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4650 12:14:21.469774 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4651 12:14:21.473324 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4652 12:14:21.476325 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4653 12:14:21.482950 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4654 12:14:21.483034 ==
4655 12:14:21.486653 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 12:14:21.489844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 12:14:21.489926 ==
4658 12:14:21.489990 DQS Delay:
4659 12:14:21.492986 DQS0 = 0, DQS1 = 0
4660 12:14:21.493067 DQM Delay:
4661 12:14:21.496266 DQM0 = 52, DQM1 = 45
4662 12:14:21.496348 DQ Delay:
4663 12:14:21.499572 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4664 12:14:21.502965 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4665 12:14:21.506505 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4666 12:14:21.509835 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4667 12:14:21.509960
4668 12:14:21.510061
4669 12:14:21.510182 ==
4670 12:14:21.513263 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 12:14:21.516221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 12:14:21.519646 ==
4673 12:14:21.519760
4674 12:14:21.519854
4675 12:14:21.519943 TX Vref Scan disable
4676 12:14:21.523141 == TX Byte 0 ==
4677 12:14:21.526360 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4678 12:14:21.529474 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4679 12:14:21.533014 == TX Byte 1 ==
4680 12:14:21.536154 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4681 12:14:21.539288 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4682 12:14:21.542748 ==
4683 12:14:21.545891 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 12:14:21.549426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 12:14:21.549510 ==
4686 12:14:21.549575
4687 12:14:21.549635
4688 12:14:21.552550 TX Vref Scan disable
4689 12:14:21.552632 == TX Byte 0 ==
4690 12:14:21.559177 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4691 12:14:21.562542 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4692 12:14:21.565638 == TX Byte 1 ==
4693 12:14:21.569141 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4694 12:14:21.572218 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4695 12:14:21.572302
4696 12:14:21.572367 [DATLAT]
4697 12:14:21.575999 Freq=600, CH1 RK1
4698 12:14:21.576084
4699 12:14:21.576150 DATLAT Default: 0x9
4700 12:14:21.578809 0, 0xFFFF, sum = 0
4701 12:14:21.582095 1, 0xFFFF, sum = 0
4702 12:14:21.582180 2, 0xFFFF, sum = 0
4703 12:14:21.585588 3, 0xFFFF, sum = 0
4704 12:14:21.585668 4, 0xFFFF, sum = 0
4705 12:14:21.588838 5, 0xFFFF, sum = 0
4706 12:14:21.588911 6, 0xFFFF, sum = 0
4707 12:14:21.592516 7, 0xFFFF, sum = 0
4708 12:14:21.592589 8, 0x0, sum = 1
4709 12:14:21.595615 9, 0x0, sum = 2
4710 12:14:21.595688 10, 0x0, sum = 3
4711 12:14:21.595759 11, 0x0, sum = 4
4712 12:14:21.598775 best_step = 9
4713 12:14:21.598850
4714 12:14:21.598913 ==
4715 12:14:21.602194 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 12:14:21.605151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 12:14:21.605228 ==
4718 12:14:21.608493 RX Vref Scan: 0
4719 12:14:21.608571
4720 12:14:21.611904 RX Vref 0 -> 0, step: 1
4721 12:14:21.611999
4722 12:14:21.612075 RX Delay -179 -> 252, step: 8
4723 12:14:21.619757 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4724 12:14:21.623196 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4725 12:14:21.626353 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4726 12:14:21.629717 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4727 12:14:21.635972 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4728 12:14:21.639496 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4729 12:14:21.642629 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4730 12:14:21.645941 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4731 12:14:21.649563 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4732 12:14:21.655866 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4733 12:14:21.659351 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4734 12:14:21.662361 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4735 12:14:21.666026 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4736 12:14:21.672315 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4737 12:14:21.675831 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4738 12:14:21.678932 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4739 12:14:21.679016 ==
4740 12:14:21.682418 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 12:14:21.685503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 12:14:21.685614 ==
4743 12:14:21.689051 DQS Delay:
4744 12:14:21.689157 DQS0 = 0, DQS1 = 0
4745 12:14:21.692253 DQM Delay:
4746 12:14:21.692355 DQM0 = 48, DQM1 = 44
4747 12:14:21.692447 DQ Delay:
4748 12:14:21.695343 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4749 12:14:21.698533 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4750 12:14:21.702088 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4751 12:14:21.705427 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =56
4752 12:14:21.705512
4753 12:14:21.705577
4754 12:14:21.715375 [DQSOSCAuto] RK1, (LSB)MR18= 0x551c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4755 12:14:21.718813 CH1 RK1: MR19=808, MR18=551C
4756 12:14:21.725414 CH1_RK1: MR19=0x808, MR18=0x551C, DQSOSC=393, MR23=63, INC=169, DEC=113
4757 12:14:21.725498 [RxdqsGatingPostProcess] freq 600
4758 12:14:21.731620 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4759 12:14:21.735101 Pre-setting of DQS Precalculation
4760 12:14:21.741639 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4761 12:14:21.748423 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4762 12:14:21.755042 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4763 12:14:21.755127
4764 12:14:21.755193
4765 12:14:21.758128 [Calibration Summary] 1200 Mbps
4766 12:14:21.758211 CH 0, Rank 0
4767 12:14:21.761161 SW Impedance : PASS
4768 12:14:21.764516 DUTY Scan : NO K
4769 12:14:21.764618 ZQ Calibration : PASS
4770 12:14:21.768233 Jitter Meter : NO K
4771 12:14:21.771352 CBT Training : PASS
4772 12:14:21.771434 Write leveling : PASS
4773 12:14:21.774333 RX DQS gating : PASS
4774 12:14:21.774424 RX DQ/DQS(RDDQC) : PASS
4775 12:14:21.777903 TX DQ/DQS : PASS
4776 12:14:21.780983 RX DATLAT : PASS
4777 12:14:21.781091 RX DQ/DQS(Engine): PASS
4778 12:14:21.784428 TX OE : NO K
4779 12:14:21.784536 All Pass.
4780 12:14:21.784629
4781 12:14:21.787927 CH 0, Rank 1
4782 12:14:21.788009 SW Impedance : PASS
4783 12:14:21.791044 DUTY Scan : NO K
4784 12:14:21.794220 ZQ Calibration : PASS
4785 12:14:21.794304 Jitter Meter : NO K
4786 12:14:21.797280 CBT Training : PASS
4787 12:14:21.800757 Write leveling : PASS
4788 12:14:21.800895 RX DQS gating : PASS
4789 12:14:21.804396 RX DQ/DQS(RDDQC) : PASS
4790 12:14:21.807521 TX DQ/DQS : PASS
4791 12:14:21.807604 RX DATLAT : PASS
4792 12:14:21.811019 RX DQ/DQS(Engine): PASS
4793 12:14:21.813976 TX OE : NO K
4794 12:14:21.814059 All Pass.
4795 12:14:21.814124
4796 12:14:21.814184 CH 1, Rank 0
4797 12:14:21.817586 SW Impedance : PASS
4798 12:14:21.820554 DUTY Scan : NO K
4799 12:14:21.820662 ZQ Calibration : PASS
4800 12:14:21.824307 Jitter Meter : NO K
4801 12:14:21.827695 CBT Training : PASS
4802 12:14:21.827778 Write leveling : PASS
4803 12:14:21.830572 RX DQS gating : PASS
4804 12:14:21.833976 RX DQ/DQS(RDDQC) : PASS
4805 12:14:21.834084 TX DQ/DQS : PASS
4806 12:14:21.837006 RX DATLAT : PASS
4807 12:14:21.840378 RX DQ/DQS(Engine): PASS
4808 12:14:21.840461 TX OE : NO K
4809 12:14:21.840527 All Pass.
4810 12:14:21.843622
4811 12:14:21.843704 CH 1, Rank 1
4812 12:14:21.847368 SW Impedance : PASS
4813 12:14:21.847451 DUTY Scan : NO K
4814 12:14:21.850525 ZQ Calibration : PASS
4815 12:14:21.850633 Jitter Meter : NO K
4816 12:14:21.853946 CBT Training : PASS
4817 12:14:21.857133 Write leveling : PASS
4818 12:14:21.857214 RX DQS gating : PASS
4819 12:14:21.860168 RX DQ/DQS(RDDQC) : PASS
4820 12:14:21.863358 TX DQ/DQS : PASS
4821 12:14:21.863433 RX DATLAT : PASS
4822 12:14:21.866848 RX DQ/DQS(Engine): PASS
4823 12:14:21.870274 TX OE : NO K
4824 12:14:21.870375 All Pass.
4825 12:14:21.870468
4826 12:14:21.873460 DramC Write-DBI off
4827 12:14:21.873529 PER_BANK_REFRESH: Hybrid Mode
4828 12:14:21.876566 TX_TRACKING: ON
4829 12:14:21.886834 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4830 12:14:21.889876 [FAST_K] Save calibration result to emmc
4831 12:14:21.893558 dramc_set_vcore_voltage set vcore to 662500
4832 12:14:21.893633 Read voltage for 933, 3
4833 12:14:21.896540 Vio18 = 0
4834 12:14:21.896608 Vcore = 662500
4835 12:14:21.896669 Vdram = 0
4836 12:14:21.900075 Vddq = 0
4837 12:14:21.900171 Vmddr = 0
4838 12:14:21.906327 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4839 12:14:21.909939 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4840 12:14:21.913048 MEM_TYPE=3, freq_sel=17
4841 12:14:21.916222 sv_algorithm_assistance_LP4_1600
4842 12:14:21.919866 ============ PULL DRAM RESETB DOWN ============
4843 12:14:21.922877 ========== PULL DRAM RESETB DOWN end =========
4844 12:14:21.929511 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4845 12:14:21.933081 ===================================
4846 12:14:21.933164 LPDDR4 DRAM CONFIGURATION
4847 12:14:21.935999 ===================================
4848 12:14:21.939438 EX_ROW_EN[0] = 0x0
4849 12:14:21.942852 EX_ROW_EN[1] = 0x0
4850 12:14:21.942953 LP4Y_EN = 0x0
4851 12:14:21.946057 WORK_FSP = 0x0
4852 12:14:21.946162 WL = 0x3
4853 12:14:21.949441 RL = 0x3
4854 12:14:21.949516 BL = 0x2
4855 12:14:21.952818 RPST = 0x0
4856 12:14:21.952920 RD_PRE = 0x0
4857 12:14:21.955783 WR_PRE = 0x1
4858 12:14:21.955857 WR_PST = 0x0
4859 12:14:21.959267 DBI_WR = 0x0
4860 12:14:21.959368 DBI_RD = 0x0
4861 12:14:21.962427 OTF = 0x1
4862 12:14:21.966121 ===================================
4863 12:14:21.969272 ===================================
4864 12:14:21.969350 ANA top config
4865 12:14:21.972304 ===================================
4866 12:14:21.975907 DLL_ASYNC_EN = 0
4867 12:14:21.979009 ALL_SLAVE_EN = 1
4868 12:14:21.982639 NEW_RANK_MODE = 1
4869 12:14:21.982736 DLL_IDLE_MODE = 1
4870 12:14:21.985745 LP45_APHY_COMB_EN = 1
4871 12:14:21.988848 TX_ODT_DIS = 1
4872 12:14:21.992367 NEW_8X_MODE = 1
4873 12:14:21.995789 ===================================
4874 12:14:21.998785 ===================================
4875 12:14:22.002344 data_rate = 1866
4876 12:14:22.002454 CKR = 1
4877 12:14:22.005488 DQ_P2S_RATIO = 8
4878 12:14:22.008499 ===================================
4879 12:14:22.012263 CA_P2S_RATIO = 8
4880 12:14:22.015302 DQ_CA_OPEN = 0
4881 12:14:22.018773 DQ_SEMI_OPEN = 0
4882 12:14:22.021954 CA_SEMI_OPEN = 0
4883 12:14:22.022056 CA_FULL_RATE = 0
4884 12:14:22.025442 DQ_CKDIV4_EN = 1
4885 12:14:22.028510 CA_CKDIV4_EN = 1
4886 12:14:22.031958 CA_PREDIV_EN = 0
4887 12:14:22.035022 PH8_DLY = 0
4888 12:14:22.038335 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4889 12:14:22.038442 DQ_AAMCK_DIV = 4
4890 12:14:22.041909 CA_AAMCK_DIV = 4
4891 12:14:22.045047 CA_ADMCK_DIV = 4
4892 12:14:22.048572 DQ_TRACK_CA_EN = 0
4893 12:14:22.051889 CA_PICK = 933
4894 12:14:22.055163 CA_MCKIO = 933
4895 12:14:22.058062 MCKIO_SEMI = 0
4896 12:14:22.058165 PLL_FREQ = 3732
4897 12:14:22.061443 DQ_UI_PI_RATIO = 32
4898 12:14:22.064762 CA_UI_PI_RATIO = 0
4899 12:14:22.068463 ===================================
4900 12:14:22.071610 ===================================
4901 12:14:22.074869 memory_type:LPDDR4
4902 12:14:22.077879 GP_NUM : 10
4903 12:14:22.077981 SRAM_EN : 1
4904 12:14:22.081399 MD32_EN : 0
4905 12:14:22.084593 ===================================
4906 12:14:22.084696 [ANA_INIT] >>>>>>>>>>>>>>
4907 12:14:22.088154 <<<<<< [CONFIGURE PHASE]: ANA_TX
4908 12:14:22.091269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4909 12:14:22.094900 ===================================
4910 12:14:22.098049 data_rate = 1866,PCW = 0X8f00
4911 12:14:22.101618 ===================================
4912 12:14:22.104791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4913 12:14:22.111376 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4914 12:14:22.118076 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4915 12:14:22.121447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4916 12:14:22.124613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4917 12:14:22.127728 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4918 12:14:22.131350 [ANA_INIT] flow start
4919 12:14:22.131451 [ANA_INIT] PLL >>>>>>>>
4920 12:14:22.134346 [ANA_INIT] PLL <<<<<<<<
4921 12:14:22.137808 [ANA_INIT] MIDPI >>>>>>>>
4922 12:14:22.137909 [ANA_INIT] MIDPI <<<<<<<<
4923 12:14:22.140812 [ANA_INIT] DLL >>>>>>>>
4924 12:14:22.144340 [ANA_INIT] flow end
4925 12:14:22.147400 ============ LP4 DIFF to SE enter ============
4926 12:14:22.151018 ============ LP4 DIFF to SE exit ============
4927 12:14:22.154238 [ANA_INIT] <<<<<<<<<<<<<
4928 12:14:22.157675 [Flow] Enable top DCM control >>>>>
4929 12:14:22.161026 [Flow] Enable top DCM control <<<<<
4930 12:14:22.164337 Enable DLL master slave shuffle
4931 12:14:22.167266 ==============================================================
4932 12:14:22.170902 Gating Mode config
4933 12:14:22.177608 ==============================================================
4934 12:14:22.177722 Config description:
4935 12:14:22.187308 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4936 12:14:22.194083 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4937 12:14:22.200336 SELPH_MODE 0: By rank 1: By Phase
4938 12:14:22.204096 ==============================================================
4939 12:14:22.207241 GAT_TRACK_EN = 1
4940 12:14:22.210567 RX_GATING_MODE = 2
4941 12:14:22.213780 RX_GATING_TRACK_MODE = 2
4942 12:14:22.216894 SELPH_MODE = 1
4943 12:14:22.220092 PICG_EARLY_EN = 1
4944 12:14:22.223334 VALID_LAT_VALUE = 1
4945 12:14:22.226902 ==============================================================
4946 12:14:22.233528 Enter into Gating configuration >>>>
4947 12:14:22.236617 Exit from Gating configuration <<<<
4948 12:14:22.236701 Enter into DVFS_PRE_config >>>>>
4949 12:14:22.249840 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4950 12:14:22.253372 Exit from DVFS_PRE_config <<<<<
4951 12:14:22.256390 Enter into PICG configuration >>>>
4952 12:14:22.259892 Exit from PICG configuration <<<<
4953 12:14:22.259975 [RX_INPUT] configuration >>>>>
4954 12:14:22.262772 [RX_INPUT] configuration <<<<<
4955 12:14:22.269304 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4956 12:14:22.276002 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4957 12:14:22.279399 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4958 12:14:22.286098 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4959 12:14:22.292614 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4960 12:14:22.298804 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4961 12:14:22.302382 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4962 12:14:22.305528 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4963 12:14:22.312222 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4964 12:14:22.315337 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4965 12:14:22.318922 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4966 12:14:22.325553 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4967 12:14:22.328509 ===================================
4968 12:14:22.328609 LPDDR4 DRAM CONFIGURATION
4969 12:14:22.332034 ===================================
4970 12:14:22.335230 EX_ROW_EN[0] = 0x0
4971 12:14:22.338345 EX_ROW_EN[1] = 0x0
4972 12:14:22.338416 LP4Y_EN = 0x0
4973 12:14:22.341955 WORK_FSP = 0x0
4974 12:14:22.342026 WL = 0x3
4975 12:14:22.345169 RL = 0x3
4976 12:14:22.345244 BL = 0x2
4977 12:14:22.348277 RPST = 0x0
4978 12:14:22.348347 RD_PRE = 0x0
4979 12:14:22.351826 WR_PRE = 0x1
4980 12:14:22.351897 WR_PST = 0x0
4981 12:14:22.354878 DBI_WR = 0x0
4982 12:14:22.354977 DBI_RD = 0x0
4983 12:14:22.358550 OTF = 0x1
4984 12:14:22.361640 ===================================
4985 12:14:22.365199 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4986 12:14:22.368028 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4987 12:14:22.375120 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4988 12:14:22.378036 ===================================
4989 12:14:22.378118 LPDDR4 DRAM CONFIGURATION
4990 12:14:22.381396 ===================================
4991 12:14:22.384606 EX_ROW_EN[0] = 0x10
4992 12:14:22.387958 EX_ROW_EN[1] = 0x0
4993 12:14:22.388032 LP4Y_EN = 0x0
4994 12:14:22.391357 WORK_FSP = 0x0
4995 12:14:22.391432 WL = 0x3
4996 12:14:22.394655 RL = 0x3
4997 12:14:22.394736 BL = 0x2
4998 12:14:22.397746 RPST = 0x0
4999 12:14:22.397846 RD_PRE = 0x0
5000 12:14:22.401365 WR_PRE = 0x1
5001 12:14:22.401436 WR_PST = 0x0
5002 12:14:22.404571 DBI_WR = 0x0
5003 12:14:22.404640 DBI_RD = 0x0
5004 12:14:22.407610 OTF = 0x1
5005 12:14:22.411070 ===================================
5006 12:14:22.417753 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5007 12:14:22.420845 nWR fixed to 30
5008 12:14:22.424392 [ModeRegInit_LP4] CH0 RK0
5009 12:14:22.424465 [ModeRegInit_LP4] CH0 RK1
5010 12:14:22.427536 [ModeRegInit_LP4] CH1 RK0
5011 12:14:22.430719 [ModeRegInit_LP4] CH1 RK1
5012 12:14:22.430847 match AC timing 9
5013 12:14:22.437332 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5014 12:14:22.440962 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5015 12:14:22.443954 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5016 12:14:22.450865 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5017 12:14:22.453821 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5018 12:14:22.453895 ==
5019 12:14:22.457047 Dram Type= 6, Freq= 0, CH_0, rank 0
5020 12:14:22.460537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5021 12:14:22.460637 ==
5022 12:14:22.467748 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5023 12:14:22.473795 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5024 12:14:22.477300 [CA 0] Center 38 (7~69) winsize 63
5025 12:14:22.480406 [CA 1] Center 38 (8~69) winsize 62
5026 12:14:22.483815 [CA 2] Center 35 (5~66) winsize 62
5027 12:14:22.487188 [CA 3] Center 34 (4~65) winsize 62
5028 12:14:22.490215 [CA 4] Center 34 (4~65) winsize 62
5029 12:14:22.493507 [CA 5] Center 33 (3~64) winsize 62
5030 12:14:22.493616
5031 12:14:22.496947 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5032 12:14:22.497049
5033 12:14:22.500305 [CATrainingPosCal] consider 1 rank data
5034 12:14:22.503171 u2DelayCellTimex100 = 270/100 ps
5035 12:14:22.506789 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5036 12:14:22.509876 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5037 12:14:22.513434 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5038 12:14:22.516467 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5039 12:14:22.523200 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5040 12:14:22.526614 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5041 12:14:22.526710
5042 12:14:22.529838 CA PerBit enable=1, Macro0, CA PI delay=33
5043 12:14:22.529912
5044 12:14:22.533476 [CBTSetCACLKResult] CA Dly = 33
5045 12:14:22.533574 CS Dly: 6 (0~37)
5046 12:14:22.533731 ==
5047 12:14:22.536497 Dram Type= 6, Freq= 0, CH_0, rank 1
5048 12:14:22.542738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 12:14:22.542847 ==
5050 12:14:22.546323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 12:14:22.552991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5052 12:14:22.556170 [CA 0] Center 38 (8~69) winsize 62
5053 12:14:22.559665 [CA 1] Center 38 (8~69) winsize 62
5054 12:14:22.563206 [CA 2] Center 36 (6~66) winsize 61
5055 12:14:22.566397 [CA 3] Center 35 (5~66) winsize 62
5056 12:14:22.569631 [CA 4] Center 34 (4~65) winsize 62
5057 12:14:22.572709 [CA 5] Center 34 (4~64) winsize 61
5058 12:14:22.572811
5059 12:14:22.576296 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5060 12:14:22.576377
5061 12:14:22.579385 [CATrainingPosCal] consider 2 rank data
5062 12:14:22.582925 u2DelayCellTimex100 = 270/100 ps
5063 12:14:22.586073 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5064 12:14:22.589476 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5065 12:14:22.596069 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5066 12:14:22.599430 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5067 12:14:22.602619 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5068 12:14:22.605779 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5069 12:14:22.605863
5070 12:14:22.609224 CA PerBit enable=1, Macro0, CA PI delay=34
5071 12:14:22.609305
5072 12:14:22.612240 [CBTSetCACLKResult] CA Dly = 34
5073 12:14:22.612320 CS Dly: 7 (0~39)
5074 12:14:22.612384
5075 12:14:22.615850 ----->DramcWriteLeveling(PI) begin...
5076 12:14:22.618920 ==
5077 12:14:22.622321 Dram Type= 6, Freq= 0, CH_0, rank 0
5078 12:14:22.625451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 12:14:22.625533 ==
5080 12:14:22.628990 Write leveling (Byte 0): 31 => 31
5081 12:14:22.632486 Write leveling (Byte 1): 31 => 31
5082 12:14:22.635583 DramcWriteLeveling(PI) end<-----
5083 12:14:22.635663
5084 12:14:22.635727 ==
5085 12:14:22.639214 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 12:14:22.642143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 12:14:22.642224 ==
5088 12:14:22.645282 [Gating] SW mode calibration
5089 12:14:22.652479 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5090 12:14:22.658927 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5091 12:14:22.661906 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5092 12:14:22.665321 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 12:14:22.672084 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 12:14:22.675037 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 12:14:22.678520 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 12:14:22.685146 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 12:14:22.688203 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5098 12:14:22.691772 0 14 28 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
5099 12:14:22.698187 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5100 12:14:22.701877 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 12:14:22.704779 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 12:14:22.711563 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 12:14:22.714806 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 12:14:22.718075 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 12:14:22.724588 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
5106 12:14:22.728253 0 15 28 | B1->B0 | 2d2d 4444 | 0 0 | (0 0) (0 0)
5107 12:14:22.731309 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5108 12:14:22.738353 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 12:14:22.741339 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 12:14:22.744790 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 12:14:22.751479 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 12:14:22.754546 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 12:14:22.757625 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 12:14:22.764563 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5115 12:14:22.767707 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 12:14:22.770818 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 12:14:22.777570 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 12:14:22.781121 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 12:14:22.784149 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 12:14:22.790911 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 12:14:22.793934 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 12:14:22.797361 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 12:14:22.804041 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 12:14:22.807159 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 12:14:22.810227 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 12:14:22.816833 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 12:14:22.820199 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 12:14:22.823477 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 12:14:22.830234 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:14:22.833772 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5131 12:14:22.836739 Total UI for P1: 0, mck2ui 16
5132 12:14:22.839931 best dqsien dly found for B0: ( 1, 2, 26)
5133 12:14:22.843476 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 12:14:22.846949 Total UI for P1: 0, mck2ui 16
5135 12:14:22.849944 best dqsien dly found for B1: ( 1, 2, 30)
5136 12:14:22.853268 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5137 12:14:22.856982 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5138 12:14:22.857064
5139 12:14:22.859989 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5140 12:14:22.866547 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5141 12:14:22.866629 [Gating] SW calibration Done
5142 12:14:22.866694 ==
5143 12:14:22.870104 Dram Type= 6, Freq= 0, CH_0, rank 0
5144 12:14:22.876621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 12:14:22.876703 ==
5146 12:14:22.876791 RX Vref Scan: 0
5147 12:14:22.876867
5148 12:14:22.880210 RX Vref 0 -> 0, step: 1
5149 12:14:22.880292
5150 12:14:22.883318 RX Delay -80 -> 252, step: 8
5151 12:14:22.886332 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5152 12:14:22.889968 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5153 12:14:22.893065 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5154 12:14:22.899523 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5155 12:14:22.903242 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5156 12:14:22.906373 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5157 12:14:22.909417 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5158 12:14:22.912615 iDelay=208, Bit 7, Center 119 (32 ~ 207) 176
5159 12:14:22.916290 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5160 12:14:22.922859 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5161 12:14:22.925865 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5162 12:14:22.929128 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5163 12:14:22.932425 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5164 12:14:22.935798 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5165 12:14:22.942759 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5166 12:14:22.945787 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5167 12:14:22.945895 ==
5168 12:14:22.948907 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 12:14:22.952336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 12:14:22.952436 ==
5171 12:14:22.952527 DQS Delay:
5172 12:14:22.955675 DQS0 = 0, DQS1 = 0
5173 12:14:22.955771 DQM Delay:
5174 12:14:22.958777 DQM0 = 106, DQM1 = 90
5175 12:14:22.958875 DQ Delay:
5176 12:14:22.962031 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5177 12:14:22.965566 DQ4 =107, DQ5 =95, DQ6 =119, DQ7 =119
5178 12:14:22.969007 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5179 12:14:22.972115 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5180 12:14:22.972213
5181 12:14:22.972309
5182 12:14:22.972384 ==
5183 12:14:22.975603 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 12:14:22.981832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 12:14:22.981915 ==
5186 12:14:22.981980
5187 12:14:22.982041
5188 12:14:22.982099 TX Vref Scan disable
5189 12:14:22.985857 == TX Byte 0 ==
5190 12:14:22.989330 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5191 12:14:22.995817 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5192 12:14:22.995900 == TX Byte 1 ==
5193 12:14:22.998874 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5194 12:14:23.005355 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5195 12:14:23.005439 ==
5196 12:14:23.008974 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 12:14:23.012060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 12:14:23.012143 ==
5199 12:14:23.012208
5200 12:14:23.012269
5201 12:14:23.015544 TX Vref Scan disable
5202 12:14:23.015628 == TX Byte 0 ==
5203 12:14:23.022075 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5204 12:14:23.025549 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5205 12:14:23.025634 == TX Byte 1 ==
5206 12:14:23.032139 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5207 12:14:23.035458 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5208 12:14:23.035542
5209 12:14:23.035616 [DATLAT]
5210 12:14:23.038703 Freq=933, CH0 RK0
5211 12:14:23.038787
5212 12:14:23.038853 DATLAT Default: 0xd
5213 12:14:23.042088 0, 0xFFFF, sum = 0
5214 12:14:23.042175 1, 0xFFFF, sum = 0
5215 12:14:23.045381 2, 0xFFFF, sum = 0
5216 12:14:23.045467 3, 0xFFFF, sum = 0
5217 12:14:23.048661 4, 0xFFFF, sum = 0
5218 12:14:23.051702 5, 0xFFFF, sum = 0
5219 12:14:23.051813 6, 0xFFFF, sum = 0
5220 12:14:23.055319 7, 0xFFFF, sum = 0
5221 12:14:23.055406 8, 0xFFFF, sum = 0
5222 12:14:23.058434 9, 0xFFFF, sum = 0
5223 12:14:23.058519 10, 0x0, sum = 1
5224 12:14:23.061793 11, 0x0, sum = 2
5225 12:14:23.061879 12, 0x0, sum = 3
5226 12:14:23.061948 13, 0x0, sum = 4
5227 12:14:23.065352 best_step = 11
5228 12:14:23.065454
5229 12:14:23.065548 ==
5230 12:14:23.068595 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 12:14:23.071722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 12:14:23.071836 ==
5233 12:14:23.075246 RX Vref Scan: 1
5234 12:14:23.075354
5235 12:14:23.078438 RX Vref 0 -> 0, step: 1
5236 12:14:23.078541
5237 12:14:23.078639 RX Delay -53 -> 252, step: 4
5238 12:14:23.078733
5239 12:14:23.082009 Set Vref, RX VrefLevel [Byte0]: 58
5240 12:14:23.085111 [Byte1]: 50
5241 12:14:23.089767
5242 12:14:23.089878 Final RX Vref Byte 0 = 58 to rank0
5243 12:14:23.092836 Final RX Vref Byte 1 = 50 to rank0
5244 12:14:23.096262 Final RX Vref Byte 0 = 58 to rank1
5245 12:14:23.099353 Final RX Vref Byte 1 = 50 to rank1==
5246 12:14:23.102893 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 12:14:23.109522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 12:14:23.109631 ==
5249 12:14:23.109744 DQS Delay:
5250 12:14:23.113068 DQS0 = 0, DQS1 = 0
5251 12:14:23.113176 DQM Delay:
5252 12:14:23.113278 DQM0 = 107, DQM1 = 92
5253 12:14:23.116284 DQ Delay:
5254 12:14:23.119420 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5255 12:14:23.122910 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =114
5256 12:14:23.126061 DQ8 =88, DQ9 =76, DQ10 =92, DQ11 =90
5257 12:14:23.129290 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =100
5258 12:14:23.129397
5259 12:14:23.129500
5260 12:14:23.135925 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5261 12:14:23.139527 CH0 RK0: MR19=505, MR18=2622
5262 12:14:23.146086 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5263 12:14:23.146189
5264 12:14:23.149296 ----->DramcWriteLeveling(PI) begin...
5265 12:14:23.149419 ==
5266 12:14:23.152232 Dram Type= 6, Freq= 0, CH_0, rank 1
5267 12:14:23.155513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 12:14:23.159008 ==
5269 12:14:23.159133 Write leveling (Byte 0): 32 => 32
5270 12:14:23.162141 Write leveling (Byte 1): 29 => 29
5271 12:14:23.165373 DramcWriteLeveling(PI) end<-----
5272 12:14:23.165502
5273 12:14:23.165633 ==
5274 12:14:23.168849 Dram Type= 6, Freq= 0, CH_0, rank 1
5275 12:14:23.175602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 12:14:23.175723 ==
5277 12:14:23.179167 [Gating] SW mode calibration
5278 12:14:23.185204 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5279 12:14:23.188617 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5280 12:14:23.195347 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5281 12:14:23.198840 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5282 12:14:23.201726 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 12:14:23.208469 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 12:14:23.212077 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 12:14:23.215536 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 12:14:23.221849 0 14 24 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
5287 12:14:23.225271 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
5288 12:14:23.228388 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5289 12:14:23.235206 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5290 12:14:23.238350 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5291 12:14:23.241376 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 12:14:23.248474 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 12:14:23.251307 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 12:14:23.255058 0 15 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5295 12:14:23.261420 0 15 28 | B1->B0 | 3b3b 3f3f | 0 0 | (0 0) (0 0)
5296 12:14:23.264791 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5297 12:14:23.268174 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5298 12:14:23.271574 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 12:14:23.277911 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 12:14:23.281293 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 12:14:23.284357 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 12:14:23.291069 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 12:14:23.294531 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 12:14:23.297611 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 12:14:23.304681 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 12:14:23.307775 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 12:14:23.310891 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 12:14:23.317270 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 12:14:23.320750 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 12:14:23.327579 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 12:14:23.330640 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 12:14:23.333842 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 12:14:23.337515 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 12:14:23.343894 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 12:14:23.347073 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 12:14:23.353554 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 12:14:23.357158 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 12:14:23.360203 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 12:14:23.363640 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 12:14:23.367071 Total UI for P1: 0, mck2ui 16
5321 12:14:23.370333 best dqsien dly found for B0: ( 1, 2, 26)
5322 12:14:23.373670 Total UI for P1: 0, mck2ui 16
5323 12:14:23.377124 best dqsien dly found for B1: ( 1, 2, 26)
5324 12:14:23.380217 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5325 12:14:23.386764 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5326 12:14:23.386870
5327 12:14:23.390438 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5328 12:14:23.393566 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5329 12:14:23.397084 [Gating] SW calibration Done
5330 12:14:23.397165 ==
5331 12:14:23.400134 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 12:14:23.403246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 12:14:23.403344 ==
5334 12:14:23.406771 RX Vref Scan: 0
5335 12:14:23.406867
5336 12:14:23.406955 RX Vref 0 -> 0, step: 1
5337 12:14:23.407045
5338 12:14:23.409914 RX Delay -80 -> 252, step: 8
5339 12:14:23.413543 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5340 12:14:23.416652 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5341 12:14:23.423320 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5342 12:14:23.426387 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5343 12:14:23.430010 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5344 12:14:23.433173 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5345 12:14:23.436660 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5346 12:14:23.443089 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5347 12:14:23.446184 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5348 12:14:23.449409 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5349 12:14:23.453077 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5350 12:14:23.456212 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5351 12:14:23.459525 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5352 12:14:23.466223 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5353 12:14:23.469551 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5354 12:14:23.473077 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5355 12:14:23.473159 ==
5356 12:14:23.476384 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 12:14:23.479457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 12:14:23.479564 ==
5359 12:14:23.483041 DQS Delay:
5360 12:14:23.483119 DQS0 = 0, DQS1 = 0
5361 12:14:23.483182 DQM Delay:
5362 12:14:23.486134 DQM0 = 104, DQM1 = 90
5363 12:14:23.486230 DQ Delay:
5364 12:14:23.489259 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5365 12:14:23.492641 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5366 12:14:23.495722 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5367 12:14:23.499183 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5368 12:14:23.499284
5369 12:14:23.499374
5370 12:14:23.502772 ==
5371 12:14:23.505821 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 12:14:23.508963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 12:14:23.509038 ==
5374 12:14:23.509099
5375 12:14:23.509163
5376 12:14:23.512322 TX Vref Scan disable
5377 12:14:23.512398 == TX Byte 0 ==
5378 12:14:23.519239 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5379 12:14:23.522374 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5380 12:14:23.522445 == TX Byte 1 ==
5381 12:14:23.529044 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5382 12:14:23.532167 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5383 12:14:23.532248 ==
5384 12:14:23.535277 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 12:14:23.538790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 12:14:23.538871 ==
5387 12:14:23.538935
5388 12:14:23.538992
5389 12:14:23.541939 TX Vref Scan disable
5390 12:14:23.545621 == TX Byte 0 ==
5391 12:14:23.548707 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5392 12:14:23.551955 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5393 12:14:23.555122 == TX Byte 1 ==
5394 12:14:23.558789 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5395 12:14:23.561766 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5396 12:14:23.561838
5397 12:14:23.565188 [DATLAT]
5398 12:14:23.565258 Freq=933, CH0 RK1
5399 12:14:23.565318
5400 12:14:23.568333 DATLAT Default: 0xb
5401 12:14:23.568414 0, 0xFFFF, sum = 0
5402 12:14:23.571836 1, 0xFFFF, sum = 0
5403 12:14:23.571922 2, 0xFFFF, sum = 0
5404 12:14:23.574983 3, 0xFFFF, sum = 0
5405 12:14:23.575069 4, 0xFFFF, sum = 0
5406 12:14:23.578503 5, 0xFFFF, sum = 0
5407 12:14:23.578589 6, 0xFFFF, sum = 0
5408 12:14:23.581405 7, 0xFFFF, sum = 0
5409 12:14:23.584710 8, 0xFFFF, sum = 0
5410 12:14:23.584836 9, 0xFFFF, sum = 0
5411 12:14:23.588110 10, 0x0, sum = 1
5412 12:14:23.588196 11, 0x0, sum = 2
5413 12:14:23.588282 12, 0x0, sum = 3
5414 12:14:23.591473 13, 0x0, sum = 4
5415 12:14:23.591559 best_step = 11
5416 12:14:23.591644
5417 12:14:23.591723 ==
5418 12:14:23.594661 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 12:14:23.601359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 12:14:23.601442 ==
5421 12:14:23.601508 RX Vref Scan: 0
5422 12:14:23.601567
5423 12:14:23.604860 RX Vref 0 -> 0, step: 1
5424 12:14:23.604949
5425 12:14:23.607944 RX Delay -53 -> 252, step: 4
5426 12:14:23.611071 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5427 12:14:23.618075 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5428 12:14:23.621303 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5429 12:14:23.624342 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5430 12:14:23.627774 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5431 12:14:23.630846 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5432 12:14:23.637802 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5433 12:14:23.640840 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5434 12:14:23.644376 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5435 12:14:23.647430 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5436 12:14:23.650979 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5437 12:14:23.657343 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5438 12:14:23.660908 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5439 12:14:23.663948 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5440 12:14:23.667286 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5441 12:14:23.670817 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5442 12:14:23.670939 ==
5443 12:14:23.673935 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 12:14:23.680631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 12:14:23.680755 ==
5446 12:14:23.680831 DQS Delay:
5447 12:14:23.684104 DQS0 = 0, DQS1 = 0
5448 12:14:23.684190 DQM Delay:
5449 12:14:23.687050 DQM0 = 104, DQM1 = 92
5450 12:14:23.687147 DQ Delay:
5451 12:14:23.690370 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5452 12:14:23.693708 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5453 12:14:23.697112 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5454 12:14:23.700584 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =98
5455 12:14:23.700656
5456 12:14:23.700724
5457 12:14:23.706992 [DQSOSCAuto] RK1, (LSB)MR18= 0x2809, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5458 12:14:23.710571 CH0 RK1: MR19=505, MR18=2809
5459 12:14:23.717291 CH0_RK1: MR19=0x505, MR18=0x2809, DQSOSC=409, MR23=63, INC=64, DEC=43
5460 12:14:23.720272 [RxdqsGatingPostProcess] freq 933
5461 12:14:23.726814 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5462 12:14:23.730051 best DQS0 dly(2T, 0.5T) = (0, 10)
5463 12:14:23.733480 best DQS1 dly(2T, 0.5T) = (0, 10)
5464 12:14:23.736932 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5465 12:14:23.739978 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5466 12:14:23.740049 best DQS0 dly(2T, 0.5T) = (0, 10)
5467 12:14:23.743453 best DQS1 dly(2T, 0.5T) = (0, 10)
5468 12:14:23.746537 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5469 12:14:23.750174 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5470 12:14:23.753385 Pre-setting of DQS Precalculation
5471 12:14:23.759537 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5472 12:14:23.759613 ==
5473 12:14:23.763139 Dram Type= 6, Freq= 0, CH_1, rank 0
5474 12:14:23.766244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 12:14:23.766328 ==
5476 12:14:23.772970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5477 12:14:23.779256 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5478 12:14:23.782984 [CA 0] Center 37 (7~68) winsize 62
5479 12:14:23.786029 [CA 1] Center 37 (7~68) winsize 62
5480 12:14:23.789099 [CA 2] Center 35 (5~65) winsize 61
5481 12:14:23.792537 [CA 3] Center 35 (5~65) winsize 61
5482 12:14:23.795883 [CA 4] Center 35 (5~66) winsize 62
5483 12:14:23.799336 [CA 5] Center 34 (4~65) winsize 62
5484 12:14:23.799406
5485 12:14:23.802625 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5486 12:14:23.802716
5487 12:14:23.805944 [CATrainingPosCal] consider 1 rank data
5488 12:14:23.809376 u2DelayCellTimex100 = 270/100 ps
5489 12:14:23.812332 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5490 12:14:23.816156 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5491 12:14:23.819299 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5492 12:14:23.822459 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5493 12:14:23.825838 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5494 12:14:23.829117 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5495 12:14:23.832257
5496 12:14:23.835931 CA PerBit enable=1, Macro0, CA PI delay=34
5497 12:14:23.836041
5498 12:14:23.838757 [CBTSetCACLKResult] CA Dly = 34
5499 12:14:23.838875 CS Dly: 6 (0~37)
5500 12:14:23.838978 ==
5501 12:14:23.841985 Dram Type= 6, Freq= 0, CH_1, rank 1
5502 12:14:23.845498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 12:14:23.845573 ==
5504 12:14:23.851917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5505 12:14:23.858786 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5506 12:14:23.861857 [CA 0] Center 38 (8~68) winsize 61
5507 12:14:23.865360 [CA 1] Center 38 (8~69) winsize 62
5508 12:14:23.868451 [CA 2] Center 36 (6~67) winsize 62
5509 12:14:23.872053 [CA 3] Center 35 (5~66) winsize 62
5510 12:14:23.875046 [CA 4] Center 36 (6~66) winsize 61
5511 12:14:23.878445 [CA 5] Center 35 (5~66) winsize 62
5512 12:14:23.878522
5513 12:14:23.881644 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5514 12:14:23.881712
5515 12:14:23.884747 [CATrainingPosCal] consider 2 rank data
5516 12:14:23.888426 u2DelayCellTimex100 = 270/100 ps
5517 12:14:23.891599 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5518 12:14:23.894996 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5519 12:14:23.897861 CA2 delay=35 (6~65),Diff = 0 PI (0 cell)
5520 12:14:23.904540 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5521 12:14:23.907911 CA4 delay=36 (6~66),Diff = 1 PI (6 cell)
5522 12:14:23.911346 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5523 12:14:23.911424
5524 12:14:23.914751 CA PerBit enable=1, Macro0, CA PI delay=35
5525 12:14:23.914863
5526 12:14:23.917735 [CBTSetCACLKResult] CA Dly = 35
5527 12:14:23.917833 CS Dly: 7 (0~39)
5528 12:14:23.917921
5529 12:14:23.921500 ----->DramcWriteLeveling(PI) begin...
5530 12:14:23.921600 ==
5531 12:14:23.924667 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 12:14:23.931331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 12:14:23.931433 ==
5534 12:14:23.934388 Write leveling (Byte 0): 28 => 28
5535 12:14:23.938038 Write leveling (Byte 1): 30 => 30
5536 12:14:23.938113 DramcWriteLeveling(PI) end<-----
5537 12:14:23.941058
5538 12:14:23.941153 ==
5539 12:14:23.944478 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 12:14:23.947481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 12:14:23.947580 ==
5542 12:14:23.951214 [Gating] SW mode calibration
5543 12:14:23.957289 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5544 12:14:23.963974 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5545 12:14:23.967532 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 12:14:23.970612 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 12:14:23.977249 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 12:14:23.980630 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 12:14:23.983738 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 12:14:23.990428 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5551 12:14:23.993522 0 14 24 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5552 12:14:23.997057 0 14 28 | B1->B0 | 2a2a 2424 | 0 0 | (1 1) (1 1)
5553 12:14:24.000482 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 12:14:24.006998 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 12:14:24.010160 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 12:14:24.013565 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 12:14:24.020347 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 12:14:24.023616 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 12:14:24.026827 0 15 24 | B1->B0 | 2b2b 2626 | 0 1 | (0 0) (0 0)
5560 12:14:24.033336 0 15 28 | B1->B0 | 3939 4141 | 0 0 | (1 1) (1 1)
5561 12:14:24.036908 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 12:14:24.040135 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 12:14:24.046578 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 12:14:24.050283 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 12:14:24.053375 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 12:14:24.059615 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 12:14:24.063203 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5568 12:14:24.066834 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 12:14:24.072996 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 12:14:24.076655 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 12:14:24.079772 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 12:14:24.086690 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 12:14:24.089775 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 12:14:24.093250 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 12:14:24.099462 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 12:14:24.103003 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 12:14:24.105983 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 12:14:24.113025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 12:14:24.116054 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 12:14:24.119451 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 12:14:24.125839 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 12:14:24.129268 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 12:14:24.132384 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5584 12:14:24.139440 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5585 12:14:24.139517 Total UI for P1: 0, mck2ui 16
5586 12:14:24.146168 best dqsien dly found for B0: ( 1, 2, 24)
5587 12:14:24.149412 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 12:14:24.152320 Total UI for P1: 0, mck2ui 16
5589 12:14:24.155776 best dqsien dly found for B1: ( 1, 2, 26)
5590 12:14:24.158878 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5591 12:14:24.162165 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5592 12:14:24.162238
5593 12:14:24.165763 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5594 12:14:24.169065 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5595 12:14:24.172141 [Gating] SW calibration Done
5596 12:14:24.172211 ==
5597 12:14:24.175339 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 12:14:24.182061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 12:14:24.182143 ==
5600 12:14:24.182208 RX Vref Scan: 0
5601 12:14:24.182267
5602 12:14:24.185207 RX Vref 0 -> 0, step: 1
5603 12:14:24.185307
5604 12:14:24.188554 RX Delay -80 -> 252, step: 8
5605 12:14:24.192227 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5606 12:14:24.195322 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5607 12:14:24.198757 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5608 12:14:24.201972 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5609 12:14:24.208224 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5610 12:14:24.211734 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5611 12:14:24.215189 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5612 12:14:24.218571 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5613 12:14:24.221482 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5614 12:14:24.228175 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5615 12:14:24.231540 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5616 12:14:24.234831 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5617 12:14:24.238322 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5618 12:14:24.241848 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5619 12:14:24.245060 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5620 12:14:24.251786 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5621 12:14:24.251870 ==
5622 12:14:24.255166 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 12:14:24.258342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 12:14:24.258427 ==
5625 12:14:24.258493 DQS Delay:
5626 12:14:24.261589 DQS0 = 0, DQS1 = 0
5627 12:14:24.261672 DQM Delay:
5628 12:14:24.265224 DQM0 = 102, DQM1 = 95
5629 12:14:24.265308 DQ Delay:
5630 12:14:24.268128 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =103
5631 12:14:24.271672 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5632 12:14:24.274844 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5633 12:14:24.278415 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5634 12:14:24.278500
5635 12:14:24.278566
5636 12:14:24.278626 ==
5637 12:14:24.281518 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 12:14:24.288144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 12:14:24.288231 ==
5640 12:14:24.288298
5641 12:14:24.288357
5642 12:14:24.288415 TX Vref Scan disable
5643 12:14:24.291558 == TX Byte 0 ==
5644 12:14:24.294496 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5645 12:14:24.301230 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5646 12:14:24.301314 == TX Byte 1 ==
5647 12:14:24.304775 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5648 12:14:24.311593 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5649 12:14:24.311677 ==
5650 12:14:24.314743 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 12:14:24.317796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 12:14:24.317879 ==
5653 12:14:24.317944
5654 12:14:24.318003
5655 12:14:24.321208 TX Vref Scan disable
5656 12:14:24.321290 == TX Byte 0 ==
5657 12:14:24.327961 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5658 12:14:24.331329 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5659 12:14:24.331430 == TX Byte 1 ==
5660 12:14:24.337477 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5661 12:14:24.340828 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5662 12:14:24.340911
5663 12:14:24.340978 [DATLAT]
5664 12:14:24.344176 Freq=933, CH1 RK0
5665 12:14:24.344258
5666 12:14:24.344322 DATLAT Default: 0xd
5667 12:14:24.347412 0, 0xFFFF, sum = 0
5668 12:14:24.351021 1, 0xFFFF, sum = 0
5669 12:14:24.351105 2, 0xFFFF, sum = 0
5670 12:14:24.354177 3, 0xFFFF, sum = 0
5671 12:14:24.354260 4, 0xFFFF, sum = 0
5672 12:14:24.357378 5, 0xFFFF, sum = 0
5673 12:14:24.357461 6, 0xFFFF, sum = 0
5674 12:14:24.360901 7, 0xFFFF, sum = 0
5675 12:14:24.360984 8, 0xFFFF, sum = 0
5676 12:14:24.364178 9, 0xFFFF, sum = 0
5677 12:14:24.364260 10, 0x0, sum = 1
5678 12:14:24.367718 11, 0x0, sum = 2
5679 12:14:24.367801 12, 0x0, sum = 3
5680 12:14:24.370724 13, 0x0, sum = 4
5681 12:14:24.370821 best_step = 11
5682 12:14:24.370886
5683 12:14:24.370962 ==
5684 12:14:24.374365 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 12:14:24.377406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 12:14:24.377491 ==
5687 12:14:24.380548 RX Vref Scan: 1
5688 12:14:24.380660
5689 12:14:24.384078 RX Vref 0 -> 0, step: 1
5690 12:14:24.384161
5691 12:14:24.384225 RX Delay -53 -> 252, step: 4
5692 12:14:24.384309
5693 12:14:24.387080 Set Vref, RX VrefLevel [Byte0]: 54
5694 12:14:24.390733 [Byte1]: 52
5695 12:14:24.395284
5696 12:14:24.395385 Final RX Vref Byte 0 = 54 to rank0
5697 12:14:24.398717 Final RX Vref Byte 1 = 52 to rank0
5698 12:14:24.401899 Final RX Vref Byte 0 = 54 to rank1
5699 12:14:24.405475 Final RX Vref Byte 1 = 52 to rank1==
5700 12:14:24.408599 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 12:14:24.415392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 12:14:24.415483 ==
5703 12:14:24.415574 DQS Delay:
5704 12:14:24.418504 DQS0 = 0, DQS1 = 0
5705 12:14:24.418585 DQM Delay:
5706 12:14:24.418650 DQM0 = 104, DQM1 = 96
5707 12:14:24.421544 DQ Delay:
5708 12:14:24.424942 DQ0 =110, DQ1 =98, DQ2 =96, DQ3 =102
5709 12:14:24.428415 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5710 12:14:24.431847 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =92
5711 12:14:24.434841 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5712 12:14:24.434923
5713 12:14:24.435042
5714 12:14:24.441532 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5715 12:14:24.444928 CH1 RK0: MR19=505, MR18=1A32
5716 12:14:24.451543 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5717 12:14:24.451661
5718 12:14:24.454622 ----->DramcWriteLeveling(PI) begin...
5719 12:14:24.454722 ==
5720 12:14:24.457765 Dram Type= 6, Freq= 0, CH_1, rank 1
5721 12:14:24.464706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 12:14:24.464812 ==
5723 12:14:24.467813 Write leveling (Byte 0): 28 => 28
5724 12:14:24.467898 Write leveling (Byte 1): 28 => 28
5725 12:14:24.471489 DramcWriteLeveling(PI) end<-----
5726 12:14:24.471571
5727 12:14:24.471635 ==
5728 12:14:24.474677 Dram Type= 6, Freq= 0, CH_1, rank 1
5729 12:14:24.481385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 12:14:24.481468 ==
5731 12:14:24.484429 [Gating] SW mode calibration
5732 12:14:24.491062 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5733 12:14:24.494245 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5734 12:14:24.500725 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5735 12:14:24.504401 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5736 12:14:24.507401 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 12:14:24.514356 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 12:14:24.517454 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 12:14:24.521076 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 12:14:24.527264 0 14 24 | B1->B0 | 2f2f 3232 | 1 1 | (1 0) (1 1)
5741 12:14:24.530792 0 14 28 | B1->B0 | 2323 2e2e | 0 0 | (1 0) (1 0)
5742 12:14:24.533873 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5743 12:14:24.540613 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5744 12:14:24.544080 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 12:14:24.547387 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 12:14:24.553765 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 12:14:24.557069 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 12:14:24.560525 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5749 12:14:24.567103 0 15 28 | B1->B0 | 4040 3c3c | 1 1 | (1 1) (0 0)
5750 12:14:24.570306 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5751 12:14:24.573864 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5752 12:14:24.580511 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 12:14:24.583599 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 12:14:24.587157 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 12:14:24.593469 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 12:14:24.597031 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5757 12:14:24.600109 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5758 12:14:24.606681 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 12:14:24.610383 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 12:14:24.613451 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 12:14:24.620176 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 12:14:24.623287 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 12:14:24.626857 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 12:14:24.629883 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 12:14:24.636543 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 12:14:24.639717 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 12:14:24.643192 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 12:14:24.649981 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 12:14:24.653136 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 12:14:24.656322 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 12:14:24.663129 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 12:14:24.666545 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5773 12:14:24.669895 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5774 12:14:24.676356 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 12:14:24.679435 Total UI for P1: 0, mck2ui 16
5776 12:14:24.682928 best dqsien dly found for B0: ( 1, 2, 28)
5777 12:14:24.686493 Total UI for P1: 0, mck2ui 16
5778 12:14:24.689579 best dqsien dly found for B1: ( 1, 2, 26)
5779 12:14:24.692806 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5780 12:14:24.695963 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5781 12:14:24.696045
5782 12:14:24.699558 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5783 12:14:24.702733 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5784 12:14:24.705827 [Gating] SW calibration Done
5785 12:14:24.705909 ==
5786 12:14:24.709309 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 12:14:24.712807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 12:14:24.712908 ==
5789 12:14:24.715817 RX Vref Scan: 0
5790 12:14:24.715899
5791 12:14:24.715963 RX Vref 0 -> 0, step: 1
5792 12:14:24.719453
5793 12:14:24.719534 RX Delay -80 -> 252, step: 8
5794 12:14:24.726149 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5795 12:14:24.729238 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5796 12:14:24.732898 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5797 12:14:24.736071 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5798 12:14:24.739129 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5799 12:14:24.745796 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5800 12:14:24.749449 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5801 12:14:24.752288 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5802 12:14:24.755648 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5803 12:14:24.758991 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5804 12:14:24.762260 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5805 12:14:24.768677 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5806 12:14:24.772231 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5807 12:14:24.775415 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5808 12:14:24.778584 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5809 12:14:24.782100 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5810 12:14:24.785157 ==
5811 12:14:24.788680 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 12:14:24.791820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 12:14:24.791924 ==
5814 12:14:24.791992 DQS Delay:
5815 12:14:24.795452 DQS0 = 0, DQS1 = 0
5816 12:14:24.795556 DQM Delay:
5817 12:14:24.798619 DQM0 = 102, DQM1 = 97
5818 12:14:24.798716 DQ Delay:
5819 12:14:24.802201 DQ0 =103, DQ1 =99, DQ2 =87, DQ3 =103
5820 12:14:24.805255 DQ4 =103, DQ5 =115, DQ6 =107, DQ7 =103
5821 12:14:24.808363 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5822 12:14:24.811755 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5823 12:14:24.811845
5824 12:14:24.811929
5825 12:14:24.812011 ==
5826 12:14:24.815239 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 12:14:24.821581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 12:14:24.821682 ==
5829 12:14:24.821773
5830 12:14:24.821860
5831 12:14:24.821949 TX Vref Scan disable
5832 12:14:24.825270 == TX Byte 0 ==
5833 12:14:24.828303 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5834 12:14:24.831842 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5835 12:14:24.834833 == TX Byte 1 ==
5836 12:14:24.838399 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5837 12:14:24.844623 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5838 12:14:24.844727 ==
5839 12:14:24.848357 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 12:14:24.851506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 12:14:24.851608 ==
5842 12:14:24.851697
5843 12:14:24.851785
5844 12:14:24.854964 TX Vref Scan disable
5845 12:14:24.855061 == TX Byte 0 ==
5846 12:14:24.861410 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5847 12:14:24.864419 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5848 12:14:24.864524 == TX Byte 1 ==
5849 12:14:24.871187 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5850 12:14:24.874392 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5851 12:14:24.874492
5852 12:14:24.874587 [DATLAT]
5853 12:14:24.878006 Freq=933, CH1 RK1
5854 12:14:24.878116
5855 12:14:24.878221 DATLAT Default: 0xb
5856 12:14:24.881034 0, 0xFFFF, sum = 0
5857 12:14:24.881146 1, 0xFFFF, sum = 0
5858 12:14:24.884415 2, 0xFFFF, sum = 0
5859 12:14:24.884524 3, 0xFFFF, sum = 0
5860 12:14:24.887916 4, 0xFFFF, sum = 0
5861 12:14:24.890967 5, 0xFFFF, sum = 0
5862 12:14:24.891071 6, 0xFFFF, sum = 0
5863 12:14:24.894481 7, 0xFFFF, sum = 0
5864 12:14:24.894591 8, 0xFFFF, sum = 0
5865 12:14:24.897558 9, 0xFFFF, sum = 0
5866 12:14:24.897662 10, 0x0, sum = 1
5867 12:14:24.901232 11, 0x0, sum = 2
5868 12:14:24.901308 12, 0x0, sum = 3
5869 12:14:24.904316 13, 0x0, sum = 4
5870 12:14:24.904417 best_step = 11
5871 12:14:24.904510
5872 12:14:24.904596 ==
5873 12:14:24.907880 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 12:14:24.911070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 12:14:24.911171 ==
5876 12:14:24.914081 RX Vref Scan: 0
5877 12:14:24.914189
5878 12:14:24.917436 RX Vref 0 -> 0, step: 1
5879 12:14:24.917535
5880 12:14:24.917637 RX Delay -53 -> 252, step: 4
5881 12:14:24.925315 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5882 12:14:24.928444 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5883 12:14:24.932042 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5884 12:14:24.935098 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5885 12:14:24.938176 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5886 12:14:24.944925 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5887 12:14:24.948075 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5888 12:14:24.951588 iDelay=199, Bit 7, Center 100 (19 ~ 182) 164
5889 12:14:24.954621 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5890 12:14:24.958216 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5891 12:14:24.964748 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5892 12:14:24.967781 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5893 12:14:24.970992 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5894 12:14:24.974276 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5895 12:14:24.977667 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5896 12:14:24.984119 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5897 12:14:24.984227 ==
5898 12:14:24.987507 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 12:14:24.990852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 12:14:24.990953 ==
5901 12:14:24.991081 DQS Delay:
5902 12:14:24.994180 DQS0 = 0, DQS1 = 0
5903 12:14:24.994281 DQM Delay:
5904 12:14:24.997619 DQM0 = 104, DQM1 = 97
5905 12:14:24.997694 DQ Delay:
5906 12:14:25.000710 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5907 12:14:25.003987 DQ4 =106, DQ5 =116, DQ6 =110, DQ7 =100
5908 12:14:25.007592 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5909 12:14:25.010657 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5910 12:14:25.010779
5911 12:14:25.013739
5912 12:14:25.020333 [DQSOSCAuto] RK1, (LSB)MR18= 0x2502, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5913 12:14:25.023898 CH1 RK1: MR19=505, MR18=2502
5914 12:14:25.030537 CH1_RK1: MR19=0x505, MR18=0x2502, DQSOSC=410, MR23=63, INC=64, DEC=42
5915 12:14:25.033705 [RxdqsGatingPostProcess] freq 933
5916 12:14:25.036697 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5917 12:14:25.040306 best DQS0 dly(2T, 0.5T) = (0, 10)
5918 12:14:25.043611 best DQS1 dly(2T, 0.5T) = (0, 10)
5919 12:14:25.046734 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5920 12:14:25.049784 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5921 12:14:25.053372 best DQS0 dly(2T, 0.5T) = (0, 10)
5922 12:14:25.056462 best DQS1 dly(2T, 0.5T) = (0, 10)
5923 12:14:25.060061 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5924 12:14:25.063416 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5925 12:14:25.066556 Pre-setting of DQS Precalculation
5926 12:14:25.069753 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5927 12:14:25.079900 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5928 12:14:25.086589 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5929 12:14:25.086695
5930 12:14:25.086787
5931 12:14:25.089487 [Calibration Summary] 1866 Mbps
5932 12:14:25.089563 CH 0, Rank 0
5933 12:14:25.093046 SW Impedance : PASS
5934 12:14:25.093120 DUTY Scan : NO K
5935 12:14:25.096027 ZQ Calibration : PASS
5936 12:14:25.099784 Jitter Meter : NO K
5937 12:14:25.099863 CBT Training : PASS
5938 12:14:25.102791 Write leveling : PASS
5939 12:14:25.106309 RX DQS gating : PASS
5940 12:14:25.106412 RX DQ/DQS(RDDQC) : PASS
5941 12:14:25.109369 TX DQ/DQS : PASS
5942 12:14:25.109455 RX DATLAT : PASS
5943 12:14:25.112993 RX DQ/DQS(Engine): PASS
5944 12:14:25.116253 TX OE : NO K
5945 12:14:25.116355 All Pass.
5946 12:14:25.116450
5947 12:14:25.119304 CH 0, Rank 1
5948 12:14:25.119376 SW Impedance : PASS
5949 12:14:25.122833 DUTY Scan : NO K
5950 12:14:25.122905 ZQ Calibration : PASS
5951 12:14:25.126205 Jitter Meter : NO K
5952 12:14:25.129273 CBT Training : PASS
5953 12:14:25.129349 Write leveling : PASS
5954 12:14:25.132563 RX DQS gating : PASS
5955 12:14:25.135716 RX DQ/DQS(RDDQC) : PASS
5956 12:14:25.135814 TX DQ/DQS : PASS
5957 12:14:25.139234 RX DATLAT : PASS
5958 12:14:25.142395 RX DQ/DQS(Engine): PASS
5959 12:14:25.142494 TX OE : NO K
5960 12:14:25.145549 All Pass.
5961 12:14:25.145625
5962 12:14:25.145687 CH 1, Rank 0
5963 12:14:25.148823 SW Impedance : PASS
5964 12:14:25.148907 DUTY Scan : NO K
5965 12:14:25.152464 ZQ Calibration : PASS
5966 12:14:25.155550 Jitter Meter : NO K
5967 12:14:25.155621 CBT Training : PASS
5968 12:14:25.158702 Write leveling : PASS
5969 12:14:25.162245 RX DQS gating : PASS
5970 12:14:25.162344 RX DQ/DQS(RDDQC) : PASS
5971 12:14:25.165484 TX DQ/DQS : PASS
5972 12:14:25.168888 RX DATLAT : PASS
5973 12:14:25.168962 RX DQ/DQS(Engine): PASS
5974 12:14:25.171982 TX OE : NO K
5975 12:14:25.172054 All Pass.
5976 12:14:25.172115
5977 12:14:25.175550 CH 1, Rank 1
5978 12:14:25.175648 SW Impedance : PASS
5979 12:14:25.179019 DUTY Scan : NO K
5980 12:14:25.181800 ZQ Calibration : PASS
5981 12:14:25.181871 Jitter Meter : NO K
5982 12:14:25.185174 CBT Training : PASS
5983 12:14:25.188577 Write leveling : PASS
5984 12:14:25.188678 RX DQS gating : PASS
5985 12:14:25.192093 RX DQ/DQS(RDDQC) : PASS
5986 12:14:25.192199 TX DQ/DQS : PASS
5987 12:14:25.195300 RX DATLAT : PASS
5988 12:14:25.198324 RX DQ/DQS(Engine): PASS
5989 12:14:25.198402 TX OE : NO K
5990 12:14:25.201727 All Pass.
5991 12:14:25.201799
5992 12:14:25.201859 DramC Write-DBI off
5993 12:14:25.205042 PER_BANK_REFRESH: Hybrid Mode
5994 12:14:25.208615 TX_TRACKING: ON
5995 12:14:25.215292 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5996 12:14:25.218407 [FAST_K] Save calibration result to emmc
5997 12:14:25.224734 dramc_set_vcore_voltage set vcore to 650000
5998 12:14:25.224862 Read voltage for 400, 6
5999 12:14:25.224926 Vio18 = 0
6000 12:14:25.228175 Vcore = 650000
6001 12:14:25.228278 Vdram = 0
6002 12:14:25.228397 Vddq = 0
6003 12:14:25.231648 Vmddr = 0
6004 12:14:25.234812 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6005 12:14:25.241493 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6006 12:14:25.244664 MEM_TYPE=3, freq_sel=20
6007 12:14:25.244771 sv_algorithm_assistance_LP4_800
6008 12:14:25.250967 ============ PULL DRAM RESETB DOWN ============
6009 12:14:25.254462 ========== PULL DRAM RESETB DOWN end =========
6010 12:14:25.258069 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6011 12:14:25.261224 ===================================
6012 12:14:25.264441 LPDDR4 DRAM CONFIGURATION
6013 12:14:25.267498 ===================================
6014 12:14:25.271180 EX_ROW_EN[0] = 0x0
6015 12:14:25.271284 EX_ROW_EN[1] = 0x0
6016 12:14:25.274219 LP4Y_EN = 0x0
6017 12:14:25.274317 WORK_FSP = 0x0
6018 12:14:25.277883 WL = 0x2
6019 12:14:25.277955 RL = 0x2
6020 12:14:25.280753 BL = 0x2
6021 12:14:25.280832 RPST = 0x0
6022 12:14:25.284320 RD_PRE = 0x0
6023 12:14:25.284417 WR_PRE = 0x1
6024 12:14:25.287567 WR_PST = 0x0
6025 12:14:25.287664 DBI_WR = 0x0
6026 12:14:25.290936 DBI_RD = 0x0
6027 12:14:25.294233 OTF = 0x1
6028 12:14:25.297642 ===================================
6029 12:14:25.300671 ===================================
6030 12:14:25.300794 ANA top config
6031 12:14:25.304090 ===================================
6032 12:14:25.307537 DLL_ASYNC_EN = 0
6033 12:14:25.310934 ALL_SLAVE_EN = 1
6034 12:14:25.311036 NEW_RANK_MODE = 1
6035 12:14:25.314255 DLL_IDLE_MODE = 1
6036 12:14:25.317239 LP45_APHY_COMB_EN = 1
6037 12:14:25.320722 TX_ODT_DIS = 1
6038 12:14:25.320860 NEW_8X_MODE = 1
6039 12:14:25.323730 ===================================
6040 12:14:25.326967 ===================================
6041 12:14:25.330596 data_rate = 800
6042 12:14:25.333969 CKR = 1
6043 12:14:25.337015 DQ_P2S_RATIO = 4
6044 12:14:25.340114 ===================================
6045 12:14:25.343695 CA_P2S_RATIO = 4
6046 12:14:25.346690 DQ_CA_OPEN = 0
6047 12:14:25.350270 DQ_SEMI_OPEN = 1
6048 12:14:25.350373 CA_SEMI_OPEN = 1
6049 12:14:25.353349 CA_FULL_RATE = 0
6050 12:14:25.356976 DQ_CKDIV4_EN = 0
6051 12:14:25.360046 CA_CKDIV4_EN = 1
6052 12:14:25.363197 CA_PREDIV_EN = 0
6053 12:14:25.366752 PH8_DLY = 0
6054 12:14:25.366853 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6055 12:14:25.369892 DQ_AAMCK_DIV = 0
6056 12:14:25.373098 CA_AAMCK_DIV = 0
6057 12:14:25.376589 CA_ADMCK_DIV = 4
6058 12:14:25.380126 DQ_TRACK_CA_EN = 0
6059 12:14:25.383343 CA_PICK = 800
6060 12:14:25.383440 CA_MCKIO = 400
6061 12:14:25.386889 MCKIO_SEMI = 400
6062 12:14:25.389936 PLL_FREQ = 3016
6063 12:14:25.393419 DQ_UI_PI_RATIO = 32
6064 12:14:25.396781 CA_UI_PI_RATIO = 32
6065 12:14:25.400026 ===================================
6066 12:14:25.403532 ===================================
6067 12:14:25.406901 memory_type:LPDDR4
6068 12:14:25.406974 GP_NUM : 10
6069 12:14:25.410258 SRAM_EN : 1
6070 12:14:25.410335 MD32_EN : 0
6071 12:14:25.413210 ===================================
6072 12:14:25.416624 [ANA_INIT] >>>>>>>>>>>>>>
6073 12:14:25.419875 <<<<<< [CONFIGURE PHASE]: ANA_TX
6074 12:14:25.423201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6075 12:14:25.426770 ===================================
6076 12:14:25.429991 data_rate = 800,PCW = 0X7400
6077 12:14:25.432902 ===================================
6078 12:14:25.436373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6079 12:14:25.443071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6080 12:14:25.452985 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6081 12:14:25.456112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6082 12:14:25.459773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6083 12:14:25.462999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6084 12:14:25.466075 [ANA_INIT] flow start
6085 12:14:25.469814 [ANA_INIT] PLL >>>>>>>>
6086 12:14:25.469888 [ANA_INIT] PLL <<<<<<<<
6087 12:14:25.472996 [ANA_INIT] MIDPI >>>>>>>>
6088 12:14:25.476118 [ANA_INIT] MIDPI <<<<<<<<
6089 12:14:25.479550 [ANA_INIT] DLL >>>>>>>>
6090 12:14:25.479622 [ANA_INIT] flow end
6091 12:14:25.482563 ============ LP4 DIFF to SE enter ============
6092 12:14:25.489406 ============ LP4 DIFF to SE exit ============
6093 12:14:25.489510 [ANA_INIT] <<<<<<<<<<<<<
6094 12:14:25.492547 [Flow] Enable top DCM control >>>>>
6095 12:14:25.496065 [Flow] Enable top DCM control <<<<<
6096 12:14:25.499039 Enable DLL master slave shuffle
6097 12:14:25.505828 ==============================================================
6098 12:14:25.509329 Gating Mode config
6099 12:14:25.512230 ==============================================================
6100 12:14:25.515525 Config description:
6101 12:14:25.525832 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6102 12:14:25.532328 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6103 12:14:25.535473 SELPH_MODE 0: By rank 1: By Phase
6104 12:14:25.542140 ==============================================================
6105 12:14:25.545584 GAT_TRACK_EN = 0
6106 12:14:25.548723 RX_GATING_MODE = 2
6107 12:14:25.551847 RX_GATING_TRACK_MODE = 2
6108 12:14:25.551919 SELPH_MODE = 1
6109 12:14:25.555480 PICG_EARLY_EN = 1
6110 12:14:25.558594 VALID_LAT_VALUE = 1
6111 12:14:25.564913 ==============================================================
6112 12:14:25.568498 Enter into Gating configuration >>>>
6113 12:14:25.571602 Exit from Gating configuration <<<<
6114 12:14:25.575268 Enter into DVFS_PRE_config >>>>>
6115 12:14:25.584949 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6116 12:14:25.587987 Exit from DVFS_PRE_config <<<<<
6117 12:14:25.591543 Enter into PICG configuration >>>>
6118 12:14:25.594651 Exit from PICG configuration <<<<
6119 12:14:25.598277 [RX_INPUT] configuration >>>>>
6120 12:14:25.601362 [RX_INPUT] configuration <<<<<
6121 12:14:25.604798 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6122 12:14:25.611151 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6123 12:14:25.618169 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6124 12:14:25.624352 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6125 12:14:25.631236 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6126 12:14:25.637963 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6127 12:14:25.641095 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6128 12:14:25.644535 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6129 12:14:25.647885 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6130 12:14:25.654094 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6131 12:14:25.657360 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6132 12:14:25.661026 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6133 12:14:25.664170 ===================================
6134 12:14:25.667238 LPDDR4 DRAM CONFIGURATION
6135 12:14:25.670781 ===================================
6136 12:14:25.670887 EX_ROW_EN[0] = 0x0
6137 12:14:25.673861 EX_ROW_EN[1] = 0x0
6138 12:14:25.677654 LP4Y_EN = 0x0
6139 12:14:25.677777 WORK_FSP = 0x0
6140 12:14:25.680817 WL = 0x2
6141 12:14:25.680933 RL = 0x2
6142 12:14:25.684057 BL = 0x2
6143 12:14:25.684172 RPST = 0x0
6144 12:14:25.687198 RD_PRE = 0x0
6145 12:14:25.687318 WR_PRE = 0x1
6146 12:14:25.690560 WR_PST = 0x0
6147 12:14:25.690677 DBI_WR = 0x0
6148 12:14:25.693694 DBI_RD = 0x0
6149 12:14:25.693797 OTF = 0x1
6150 12:14:25.697280 ===================================
6151 12:14:25.700390 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6152 12:14:25.706986 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6153 12:14:25.710419 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6154 12:14:25.713756 ===================================
6155 12:14:25.717093 LPDDR4 DRAM CONFIGURATION
6156 12:14:25.720196 ===================================
6157 12:14:25.720321 EX_ROW_EN[0] = 0x10
6158 12:14:25.723641 EX_ROW_EN[1] = 0x0
6159 12:14:25.726873 LP4Y_EN = 0x0
6160 12:14:25.726992 WORK_FSP = 0x0
6161 12:14:25.730371 WL = 0x2
6162 12:14:25.730493 RL = 0x2
6163 12:14:25.733180 BL = 0x2
6164 12:14:25.733313 RPST = 0x0
6165 12:14:25.736620 RD_PRE = 0x0
6166 12:14:25.736743 WR_PRE = 0x1
6167 12:14:25.740046 WR_PST = 0x0
6168 12:14:25.740155 DBI_WR = 0x0
6169 12:14:25.743197 DBI_RD = 0x0
6170 12:14:25.743314 OTF = 0x1
6171 12:14:25.746770 ===================================
6172 12:14:25.753494 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6173 12:14:25.757529 nWR fixed to 30
6174 12:14:25.760657 [ModeRegInit_LP4] CH0 RK0
6175 12:14:25.760761 [ModeRegInit_LP4] CH0 RK1
6176 12:14:25.764288 [ModeRegInit_LP4] CH1 RK0
6177 12:14:25.767465 [ModeRegInit_LP4] CH1 RK1
6178 12:14:25.767569 match AC timing 19
6179 12:14:25.774274 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6180 12:14:25.777420 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6181 12:14:25.780463 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6182 12:14:25.787289 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6183 12:14:25.790439 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6184 12:14:25.790559 ==
6185 12:14:25.793774 Dram Type= 6, Freq= 0, CH_0, rank 0
6186 12:14:25.796884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6187 12:14:25.796995 ==
6188 12:14:25.803579 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6189 12:14:25.810296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6190 12:14:25.813404 [CA 0] Center 36 (8~64) winsize 57
6191 12:14:25.816754 [CA 1] Center 36 (8~64) winsize 57
6192 12:14:25.820257 [CA 2] Center 36 (8~64) winsize 57
6193 12:14:25.823484 [CA 3] Center 36 (8~64) winsize 57
6194 12:14:25.826385 [CA 4] Center 36 (8~64) winsize 57
6195 12:14:25.829695 [CA 5] Center 36 (8~64) winsize 57
6196 12:14:25.829795
6197 12:14:25.833143 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6198 12:14:25.833300
6199 12:14:25.836489 [CATrainingPosCal] consider 1 rank data
6200 12:14:25.839949 u2DelayCellTimex100 = 270/100 ps
6201 12:14:25.842798 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6202 12:14:25.846083 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 12:14:25.849620 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 12:14:25.853354 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 12:14:25.856266 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 12:14:25.859822 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 12:14:25.859937
6208 12:14:25.866177 CA PerBit enable=1, Macro0, CA PI delay=36
6209 12:14:25.866285
6210 12:14:25.866397 [CBTSetCACLKResult] CA Dly = 36
6211 12:14:25.869321 CS Dly: 1 (0~32)
6212 12:14:25.869424 ==
6213 12:14:25.872934 Dram Type= 6, Freq= 0, CH_0, rank 1
6214 12:14:25.876031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6215 12:14:25.876133 ==
6216 12:14:25.882799 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6217 12:14:25.889090 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6218 12:14:25.892723 [CA 0] Center 36 (8~64) winsize 57
6219 12:14:25.895791 [CA 1] Center 36 (8~64) winsize 57
6220 12:14:25.899265 [CA 2] Center 36 (8~64) winsize 57
6221 12:14:25.902855 [CA 3] Center 36 (8~64) winsize 57
6222 12:14:25.902970 [CA 4] Center 36 (8~64) winsize 57
6223 12:14:25.906076 [CA 5] Center 36 (8~64) winsize 57
6224 12:14:25.906183
6225 12:14:25.912666 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6226 12:14:25.912811
6227 12:14:25.915816 [CATrainingPosCal] consider 2 rank data
6228 12:14:25.919013 u2DelayCellTimex100 = 270/100 ps
6229 12:14:25.922511 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 12:14:25.925935 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 12:14:25.929325 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 12:14:25.932219 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 12:14:25.935764 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 12:14:25.939095 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 12:14:25.939192
6236 12:14:25.942405 CA PerBit enable=1, Macro0, CA PI delay=36
6237 12:14:25.942507
6238 12:14:25.945505 [CBTSetCACLKResult] CA Dly = 36
6239 12:14:25.948939 CS Dly: 1 (0~32)
6240 12:14:25.949012
6241 12:14:25.952232 ----->DramcWriteLeveling(PI) begin...
6242 12:14:25.952316 ==
6243 12:14:25.955801 Dram Type= 6, Freq= 0, CH_0, rank 0
6244 12:14:25.958865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 12:14:25.958980 ==
6246 12:14:25.961850 Write leveling (Byte 0): 40 => 8
6247 12:14:25.965389 Write leveling (Byte 1): 32 => 0
6248 12:14:25.969032 DramcWriteLeveling(PI) end<-----
6249 12:14:25.969122
6250 12:14:25.969208 ==
6251 12:14:25.972192 Dram Type= 6, Freq= 0, CH_0, rank 0
6252 12:14:25.975306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 12:14:25.975428 ==
6254 12:14:25.978795 [Gating] SW mode calibration
6255 12:14:25.985415 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6256 12:14:25.991994 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6257 12:14:25.995214 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6258 12:14:26.001882 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 12:14:26.004935 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6260 12:14:26.008134 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6261 12:14:26.014996 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6262 12:14:26.018067 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 12:14:26.021619 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 12:14:26.028265 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 12:14:26.031276 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 12:14:26.034642 Total UI for P1: 0, mck2ui 16
6267 12:14:26.038069 best dqsien dly found for B0: ( 0, 14, 24)
6268 12:14:26.041081 Total UI for P1: 0, mck2ui 16
6269 12:14:26.044486 best dqsien dly found for B1: ( 0, 14, 24)
6270 12:14:26.047815 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6271 12:14:26.051184 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6272 12:14:26.051287
6273 12:14:26.054607 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6274 12:14:26.057887 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6275 12:14:26.061249 [Gating] SW calibration Done
6276 12:14:26.061321 ==
6277 12:14:26.064122 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 12:14:26.067761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 12:14:26.070883 ==
6280 12:14:26.070978 RX Vref Scan: 0
6281 12:14:26.071069
6282 12:14:26.074046 RX Vref 0 -> 0, step: 1
6283 12:14:26.074139
6284 12:14:26.077650 RX Delay -410 -> 252, step: 16
6285 12:14:26.080722 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6286 12:14:26.083874 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6287 12:14:26.087545 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6288 12:14:26.093810 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6289 12:14:26.097414 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6290 12:14:26.100537 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6291 12:14:26.103573 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6292 12:14:26.110069 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6293 12:14:26.113795 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6294 12:14:26.116854 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6295 12:14:26.123631 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6296 12:14:26.126749 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6297 12:14:26.129837 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6298 12:14:26.133342 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6299 12:14:26.140080 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6300 12:14:26.143424 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6301 12:14:26.143525 ==
6302 12:14:26.146908 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 12:14:26.149827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 12:14:26.149939 ==
6305 12:14:26.153250 DQS Delay:
6306 12:14:26.153358 DQS0 = 27, DQS1 = 43
6307 12:14:26.156664 DQM Delay:
6308 12:14:26.156768 DQM0 = 13, DQM1 = 12
6309 12:14:26.156854 DQ Delay:
6310 12:14:26.160049 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6311 12:14:26.163001 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6312 12:14:26.166216 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6313 12:14:26.169634 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6314 12:14:26.169747
6315 12:14:26.169841
6316 12:14:26.169927 ==
6317 12:14:26.173099 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 12:14:26.179324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 12:14:26.179450 ==
6320 12:14:26.179554
6321 12:14:26.179686
6322 12:14:26.179772 TX Vref Scan disable
6323 12:14:26.182975 == TX Byte 0 ==
6324 12:14:26.185996 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6325 12:14:26.189508 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6326 12:14:26.192675 == TX Byte 1 ==
6327 12:14:26.195735 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6328 12:14:26.199443 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6329 12:14:26.202623 ==
6330 12:14:26.202721 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 12:14:26.209335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 12:14:26.209408 ==
6333 12:14:26.209467
6334 12:14:26.209526
6335 12:14:26.212406 TX Vref Scan disable
6336 12:14:26.212499 == TX Byte 0 ==
6337 12:14:26.216125 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 12:14:26.222336 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 12:14:26.222433 == TX Byte 1 ==
6340 12:14:26.225930 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6341 12:14:26.232257 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6342 12:14:26.232335
6343 12:14:26.232396 [DATLAT]
6344 12:14:26.232461 Freq=400, CH0 RK0
6345 12:14:26.232520
6346 12:14:26.235416 DATLAT Default: 0xf
6347 12:14:26.239022 0, 0xFFFF, sum = 0
6348 12:14:26.239122 1, 0xFFFF, sum = 0
6349 12:14:26.242434 2, 0xFFFF, sum = 0
6350 12:14:26.242535 3, 0xFFFF, sum = 0
6351 12:14:26.245669 4, 0xFFFF, sum = 0
6352 12:14:26.245768 5, 0xFFFF, sum = 0
6353 12:14:26.249101 6, 0xFFFF, sum = 0
6354 12:14:26.249172 7, 0xFFFF, sum = 0
6355 12:14:26.252484 8, 0xFFFF, sum = 0
6356 12:14:26.252556 9, 0xFFFF, sum = 0
6357 12:14:26.255708 10, 0xFFFF, sum = 0
6358 12:14:26.255832 11, 0xFFFF, sum = 0
6359 12:14:26.258918 12, 0xFFFF, sum = 0
6360 12:14:26.259040 13, 0x0, sum = 1
6361 12:14:26.262303 14, 0x0, sum = 2
6362 12:14:26.262436 15, 0x0, sum = 3
6363 12:14:26.265661 16, 0x0, sum = 4
6364 12:14:26.265793 best_step = 14
6365 12:14:26.265929
6366 12:14:26.266053 ==
6367 12:14:26.268638 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 12:14:26.275530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 12:14:26.275644 ==
6370 12:14:26.275739 RX Vref Scan: 1
6371 12:14:26.275828
6372 12:14:26.278593 RX Vref 0 -> 0, step: 1
6373 12:14:26.278708
6374 12:14:26.282079 RX Delay -327 -> 252, step: 8
6375 12:14:26.282188
6376 12:14:26.285266 Set Vref, RX VrefLevel [Byte0]: 58
6377 12:14:26.288352 [Byte1]: 50
6378 12:14:26.288435
6379 12:14:26.291883 Final RX Vref Byte 0 = 58 to rank0
6380 12:14:26.294999 Final RX Vref Byte 1 = 50 to rank0
6381 12:14:26.298431 Final RX Vref Byte 0 = 58 to rank1
6382 12:14:26.301585 Final RX Vref Byte 1 = 50 to rank1==
6383 12:14:26.304713 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 12:14:26.308377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 12:14:26.311425 ==
6386 12:14:26.311536 DQS Delay:
6387 12:14:26.311632 DQS0 = 24, DQS1 = 48
6388 12:14:26.314868 DQM Delay:
6389 12:14:26.314961 DQM0 = 8, DQM1 = 15
6390 12:14:26.318018 DQ Delay:
6391 12:14:26.318111 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6392 12:14:26.321623 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =16
6393 12:14:26.324710 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6394 12:14:26.328339 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6395 12:14:26.328432
6396 12:14:26.328518
6397 12:14:26.337784 [DQSOSCAuto] RK0, (LSB)MR18= 0xafa7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6398 12:14:26.341511 CH0 RK0: MR19=C0C, MR18=AFA7
6399 12:14:26.344509 CH0_RK0: MR19=0xC0C, MR18=0xAFA7, DQSOSC=388, MR23=63, INC=392, DEC=261
6400 12:14:26.348081 ==
6401 12:14:26.351334 Dram Type= 6, Freq= 0, CH_0, rank 1
6402 12:14:26.354671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 12:14:26.354770 ==
6404 12:14:26.358098 [Gating] SW mode calibration
6405 12:14:26.364356 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6406 12:14:26.367680 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6407 12:14:26.374416 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6408 12:14:26.377786 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6409 12:14:26.381034 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6410 12:14:26.387492 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 12:14:26.390706 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6412 12:14:26.394379 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6413 12:14:26.400699 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 12:14:26.403814 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 12:14:26.407553 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6416 12:14:26.410734 Total UI for P1: 0, mck2ui 16
6417 12:14:26.413770 best dqsien dly found for B0: ( 0, 14, 24)
6418 12:14:26.417385 Total UI for P1: 0, mck2ui 16
6419 12:14:26.420452 best dqsien dly found for B1: ( 0, 14, 24)
6420 12:14:26.424086 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6421 12:14:26.430241 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6422 12:14:26.430347
6423 12:14:26.433922 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6424 12:14:26.436902 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6425 12:14:26.440181 [Gating] SW calibration Done
6426 12:14:26.440290 ==
6427 12:14:26.443762 Dram Type= 6, Freq= 0, CH_0, rank 1
6428 12:14:26.446932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 12:14:26.447014 ==
6430 12:14:26.450142 RX Vref Scan: 0
6431 12:14:26.450223
6432 12:14:26.450286 RX Vref 0 -> 0, step: 1
6433 12:14:26.450344
6434 12:14:26.453626 RX Delay -410 -> 252, step: 16
6435 12:14:26.460230 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6436 12:14:26.463133 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6437 12:14:26.466620 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6438 12:14:26.470051 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6439 12:14:26.476307 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6440 12:14:26.479630 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6441 12:14:26.482985 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6442 12:14:26.486398 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6443 12:14:26.492846 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6444 12:14:26.496599 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6445 12:14:26.499637 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6446 12:14:26.502885 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6447 12:14:26.509722 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6448 12:14:26.512666 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6449 12:14:26.515773 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6450 12:14:26.522774 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6451 12:14:26.522855 ==
6452 12:14:26.525858 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 12:14:26.529419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 12:14:26.529503 ==
6455 12:14:26.529568 DQS Delay:
6456 12:14:26.532579 DQS0 = 27, DQS1 = 43
6457 12:14:26.532661 DQM Delay:
6458 12:14:26.536181 DQM0 = 9, DQM1 = 14
6459 12:14:26.536263 DQ Delay:
6460 12:14:26.539179 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6461 12:14:26.542397 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6462 12:14:26.545948 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6463 12:14:26.549056 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6464 12:14:26.549138
6465 12:14:26.549203
6466 12:14:26.549262 ==
6467 12:14:26.552577 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 12:14:26.555743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 12:14:26.555825 ==
6470 12:14:26.555890
6471 12:14:26.555949
6472 12:14:26.558778 TX Vref Scan disable
6473 12:14:26.558859 == TX Byte 0 ==
6474 12:14:26.565604 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6475 12:14:26.568888 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6476 12:14:26.568988 == TX Byte 1 ==
6477 12:14:26.575530 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6478 12:14:26.578688 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6479 12:14:26.578810 ==
6480 12:14:26.582153 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 12:14:26.585621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 12:14:26.585744 ==
6483 12:14:26.585840
6484 12:14:26.585946
6485 12:14:26.588915 TX Vref Scan disable
6486 12:14:26.589021 == TX Byte 0 ==
6487 12:14:26.595099 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6488 12:14:26.598437 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6489 12:14:26.598608 == TX Byte 1 ==
6490 12:14:26.605414 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6491 12:14:26.608618 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6492 12:14:26.608731
6493 12:14:26.608860 [DATLAT]
6494 12:14:26.611626 Freq=400, CH0 RK1
6495 12:14:26.611740
6496 12:14:26.611830 DATLAT Default: 0xe
6497 12:14:26.615258 0, 0xFFFF, sum = 0
6498 12:14:26.615361 1, 0xFFFF, sum = 0
6499 12:14:26.618428 2, 0xFFFF, sum = 0
6500 12:14:26.618510 3, 0xFFFF, sum = 0
6501 12:14:26.621910 4, 0xFFFF, sum = 0
6502 12:14:26.621993 5, 0xFFFF, sum = 0
6503 12:14:26.624898 6, 0xFFFF, sum = 0
6504 12:14:26.624981 7, 0xFFFF, sum = 0
6505 12:14:26.628362 8, 0xFFFF, sum = 0
6506 12:14:26.631476 9, 0xFFFF, sum = 0
6507 12:14:26.631559 10, 0xFFFF, sum = 0
6508 12:14:26.635138 11, 0xFFFF, sum = 0
6509 12:14:26.635221 12, 0xFFFF, sum = 0
6510 12:14:26.638294 13, 0x0, sum = 1
6511 12:14:26.638377 14, 0x0, sum = 2
6512 12:14:26.641386 15, 0x0, sum = 3
6513 12:14:26.641468 16, 0x0, sum = 4
6514 12:14:26.641534 best_step = 14
6515 12:14:26.644957
6516 12:14:26.645038 ==
6517 12:14:26.648098 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 12:14:26.651522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 12:14:26.651604 ==
6520 12:14:26.651669 RX Vref Scan: 0
6521 12:14:26.651730
6522 12:14:26.654720 RX Vref 0 -> 0, step: 1
6523 12:14:26.654801
6524 12:14:26.657844 RX Delay -327 -> 252, step: 8
6525 12:14:26.665113 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6526 12:14:26.668559 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6527 12:14:26.671505 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6528 12:14:26.678274 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6529 12:14:26.681560 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6530 12:14:26.685039 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6531 12:14:26.688211 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6532 12:14:26.691648 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6533 12:14:26.698274 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6534 12:14:26.701533 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6535 12:14:26.704714 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6536 12:14:26.711322 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6537 12:14:26.715007 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6538 12:14:26.718034 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6539 12:14:26.721268 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6540 12:14:26.727885 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6541 12:14:26.727967 ==
6542 12:14:26.731414 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 12:14:26.734453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 12:14:26.734536 ==
6545 12:14:26.734601 DQS Delay:
6546 12:14:26.738168 DQS0 = 28, DQS1 = 44
6547 12:14:26.738249 DQM Delay:
6548 12:14:26.741342 DQM0 = 10, DQM1 = 15
6549 12:14:26.741423 DQ Delay:
6550 12:14:26.744423 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6551 12:14:26.748126 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6552 12:14:26.751296 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6553 12:14:26.754287 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6554 12:14:26.754368
6555 12:14:26.754434
6556 12:14:26.761271 [DQSOSCAuto] RK1, (LSB)MR18= 0xb469, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6557 12:14:26.764383 CH0 RK1: MR19=C0C, MR18=B469
6558 12:14:26.771206 CH0_RK1: MR19=0xC0C, MR18=0xB469, DQSOSC=387, MR23=63, INC=394, DEC=262
6559 12:14:26.774297 [RxdqsGatingPostProcess] freq 400
6560 12:14:26.781045 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6561 12:14:26.783997 best DQS0 dly(2T, 0.5T) = (0, 10)
6562 12:14:26.787443 best DQS1 dly(2T, 0.5T) = (0, 10)
6563 12:14:26.790793 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6564 12:14:26.794267 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6565 12:14:26.794349 best DQS0 dly(2T, 0.5T) = (0, 10)
6566 12:14:26.797526 best DQS1 dly(2T, 0.5T) = (0, 10)
6567 12:14:26.800745 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6568 12:14:26.804230 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6569 12:14:26.807477 Pre-setting of DQS Precalculation
6570 12:14:26.814298 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6571 12:14:26.814389 ==
6572 12:14:26.817287 Dram Type= 6, Freq= 0, CH_1, rank 0
6573 12:14:26.820747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 12:14:26.820840 ==
6575 12:14:26.827130 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6576 12:14:26.833744 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6577 12:14:26.837356 [CA 0] Center 36 (8~64) winsize 57
6578 12:14:26.837440 [CA 1] Center 36 (8~64) winsize 57
6579 12:14:26.840557 [CA 2] Center 36 (8~64) winsize 57
6580 12:14:26.843689 [CA 3] Center 36 (8~64) winsize 57
6581 12:14:26.847247 [CA 4] Center 36 (8~64) winsize 57
6582 12:14:26.850403 [CA 5] Center 36 (8~64) winsize 57
6583 12:14:26.850498
6584 12:14:26.853460 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6585 12:14:26.853543
6586 12:14:26.860126 [CATrainingPosCal] consider 1 rank data
6587 12:14:26.860207 u2DelayCellTimex100 = 270/100 ps
6588 12:14:26.866874 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6589 12:14:26.869999 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 12:14:26.873607 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 12:14:26.876748 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 12:14:26.880173 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 12:14:26.883254 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 12:14:26.883371
6595 12:14:26.886713 CA PerBit enable=1, Macro0, CA PI delay=36
6596 12:14:26.886796
6597 12:14:26.890223 [CBTSetCACLKResult] CA Dly = 36
6598 12:14:26.893173 CS Dly: 1 (0~32)
6599 12:14:26.893329 ==
6600 12:14:26.896628 Dram Type= 6, Freq= 0, CH_1, rank 1
6601 12:14:26.899642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 12:14:26.899742 ==
6603 12:14:26.906389 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6604 12:14:26.909733 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6605 12:14:26.913096 [CA 0] Center 36 (8~64) winsize 57
6606 12:14:26.916499 [CA 1] Center 36 (8~64) winsize 57
6607 12:14:26.919721 [CA 2] Center 36 (8~64) winsize 57
6608 12:14:26.922766 [CA 3] Center 36 (8~64) winsize 57
6609 12:14:26.926292 [CA 4] Center 36 (8~64) winsize 57
6610 12:14:26.929799 [CA 5] Center 36 (8~64) winsize 57
6611 12:14:26.929899
6612 12:14:26.932925 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6613 12:14:26.933007
6614 12:14:26.936087 [CATrainingPosCal] consider 2 rank data
6615 12:14:26.939672 u2DelayCellTimex100 = 270/100 ps
6616 12:14:26.942740 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 12:14:26.945868 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 12:14:26.952532 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 12:14:26.956081 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 12:14:26.959024 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 12:14:26.962607 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 12:14:26.962691
6623 12:14:26.965732 CA PerBit enable=1, Macro0, CA PI delay=36
6624 12:14:26.965814
6625 12:14:26.969322 [CBTSetCACLKResult] CA Dly = 36
6626 12:14:26.969403 CS Dly: 1 (0~32)
6627 12:14:26.969468
6628 12:14:26.975879 ----->DramcWriteLeveling(PI) begin...
6629 12:14:26.975963 ==
6630 12:14:26.978903 Dram Type= 6, Freq= 0, CH_1, rank 0
6631 12:14:26.982392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 12:14:26.982474 ==
6633 12:14:26.985377 Write leveling (Byte 0): 40 => 8
6634 12:14:26.989005 Write leveling (Byte 1): 32 => 0
6635 12:14:26.991893 DramcWriteLeveling(PI) end<-----
6636 12:14:26.991976
6637 12:14:26.992070 ==
6638 12:14:26.995258 Dram Type= 6, Freq= 0, CH_1, rank 0
6639 12:14:26.998831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 12:14:26.998946 ==
6641 12:14:27.002207 [Gating] SW mode calibration
6642 12:14:27.008392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6643 12:14:27.015195 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6644 12:14:27.018701 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6645 12:14:27.021659 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6646 12:14:27.028566 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6647 12:14:27.032113 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6648 12:14:27.035244 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6649 12:14:27.041846 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6650 12:14:27.045118 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 12:14:27.048272 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 12:14:27.054925 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 12:14:27.055007 Total UI for P1: 0, mck2ui 16
6654 12:14:27.061604 best dqsien dly found for B0: ( 0, 14, 24)
6655 12:14:27.061687 Total UI for P1: 0, mck2ui 16
6656 12:14:27.064701 best dqsien dly found for B1: ( 0, 14, 24)
6657 12:14:27.071621 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6658 12:14:27.075182 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6659 12:14:27.075265
6660 12:14:27.078328 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6661 12:14:27.081341 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6662 12:14:27.084905 [Gating] SW calibration Done
6663 12:14:27.085004 ==
6664 12:14:27.087806 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 12:14:27.091462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 12:14:27.091562 ==
6667 12:14:27.094465 RX Vref Scan: 0
6668 12:14:27.094563
6669 12:14:27.094659 RX Vref 0 -> 0, step: 1
6670 12:14:27.094753
6671 12:14:27.097998 RX Delay -410 -> 252, step: 16
6672 12:14:27.104508 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6673 12:14:27.108025 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6674 12:14:27.111087 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6675 12:14:27.114397 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6676 12:14:27.121233 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6677 12:14:27.124057 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6678 12:14:27.127450 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6679 12:14:27.131030 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6680 12:14:27.137577 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6681 12:14:27.140715 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6682 12:14:27.144228 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6683 12:14:27.147221 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6684 12:14:27.154059 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6685 12:14:27.157636 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6686 12:14:27.160701 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6687 12:14:27.167437 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6688 12:14:27.167519 ==
6689 12:14:27.170572 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 12:14:27.173733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 12:14:27.173816 ==
6692 12:14:27.173881 DQS Delay:
6693 12:14:27.177358 DQS0 = 27, DQS1 = 43
6694 12:14:27.177440 DQM Delay:
6695 12:14:27.180472 DQM0 = 8, DQM1 = 16
6696 12:14:27.180553 DQ Delay:
6697 12:14:27.183574 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6698 12:14:27.187199 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6699 12:14:27.190631 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6700 12:14:27.193610 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6701 12:14:27.193692
6702 12:14:27.193756
6703 12:14:27.193815 ==
6704 12:14:27.196689 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 12:14:27.200288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 12:14:27.200376 ==
6707 12:14:27.200472
6708 12:14:27.200560
6709 12:14:27.203679 TX Vref Scan disable
6710 12:14:27.203790 == TX Byte 0 ==
6711 12:14:27.210347 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6712 12:14:27.213335 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6713 12:14:27.213440 == TX Byte 1 ==
6714 12:14:27.220037 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6715 12:14:27.223038 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6716 12:14:27.223139 ==
6717 12:14:27.226407 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 12:14:27.230077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 12:14:27.230160 ==
6720 12:14:27.230225
6721 12:14:27.233354
6722 12:14:27.233436 TX Vref Scan disable
6723 12:14:27.236678 == TX Byte 0 ==
6724 12:14:27.239634 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 12:14:27.243256 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 12:14:27.246373 == TX Byte 1 ==
6727 12:14:27.249871 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6728 12:14:27.252860 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6729 12:14:27.252935
6730 12:14:27.252999 [DATLAT]
6731 12:14:27.256475 Freq=400, CH1 RK0
6732 12:14:27.256573
6733 12:14:27.259991 DATLAT Default: 0xf
6734 12:14:27.260063 0, 0xFFFF, sum = 0
6735 12:14:27.263065 1, 0xFFFF, sum = 0
6736 12:14:27.263168 2, 0xFFFF, sum = 0
6737 12:14:27.266260 3, 0xFFFF, sum = 0
6738 12:14:27.266362 4, 0xFFFF, sum = 0
6739 12:14:27.269808 5, 0xFFFF, sum = 0
6740 12:14:27.269913 6, 0xFFFF, sum = 0
6741 12:14:27.272945 7, 0xFFFF, sum = 0
6742 12:14:27.273049 8, 0xFFFF, sum = 0
6743 12:14:27.276196 9, 0xFFFF, sum = 0
6744 12:14:27.276299 10, 0xFFFF, sum = 0
6745 12:14:27.279723 11, 0xFFFF, sum = 0
6746 12:14:27.279820 12, 0xFFFF, sum = 0
6747 12:14:27.282768 13, 0x0, sum = 1
6748 12:14:27.282871 14, 0x0, sum = 2
6749 12:14:27.285951 15, 0x0, sum = 3
6750 12:14:27.286050 16, 0x0, sum = 4
6751 12:14:27.289547 best_step = 14
6752 12:14:27.289649
6753 12:14:27.289744 ==
6754 12:14:27.292692 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 12:14:27.296220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 12:14:27.296290 ==
6757 12:14:27.299332 RX Vref Scan: 1
6758 12:14:27.299425
6759 12:14:27.299519 RX Vref 0 -> 0, step: 1
6760 12:14:27.299616
6761 12:14:27.302336 RX Delay -327 -> 252, step: 8
6762 12:14:27.302406
6763 12:14:27.305768 Set Vref, RX VrefLevel [Byte0]: 54
6764 12:14:27.309336 [Byte1]: 52
6765 12:14:27.313993
6766 12:14:27.314062 Final RX Vref Byte 0 = 54 to rank0
6767 12:14:27.317130 Final RX Vref Byte 1 = 52 to rank0
6768 12:14:27.320495 Final RX Vref Byte 0 = 54 to rank1
6769 12:14:27.323783 Final RX Vref Byte 1 = 52 to rank1==
6770 12:14:27.327077 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 12:14:27.333577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 12:14:27.333688 ==
6773 12:14:27.333781 DQS Delay:
6774 12:14:27.336863 DQS0 = 28, DQS1 = 44
6775 12:14:27.336972 DQM Delay:
6776 12:14:27.337069 DQM0 = 8, DQM1 = 16
6777 12:14:27.340119 DQ Delay:
6778 12:14:27.343371 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6779 12:14:27.343449 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6780 12:14:27.346690 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6781 12:14:27.350269 DQ12 =28, DQ13 =24, DQ14 =20, DQ15 =24
6782 12:14:27.350356
6783 12:14:27.353299
6784 12:14:27.360059 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6785 12:14:27.363204 CH1 RK0: MR19=C0C, MR18=8FCA
6786 12:14:27.369859 CH1_RK0: MR19=0xC0C, MR18=0x8FCA, DQSOSC=384, MR23=63, INC=400, DEC=267
6787 12:14:27.369942 ==
6788 12:14:27.373035 Dram Type= 6, Freq= 0, CH_1, rank 1
6789 12:14:27.376490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 12:14:27.376578 ==
6791 12:14:27.379765 [Gating] SW mode calibration
6792 12:14:27.386393 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6793 12:14:27.393160 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6794 12:14:27.396078 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6795 12:14:27.399559 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6796 12:14:27.406303 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6797 12:14:27.409730 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6798 12:14:27.412727 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6799 12:14:27.419518 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6800 12:14:27.422721 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6801 12:14:27.425809 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 12:14:27.432687 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6803 12:14:27.432790 Total UI for P1: 0, mck2ui 16
6804 12:14:27.439195 best dqsien dly found for B0: ( 0, 14, 24)
6805 12:14:27.439279 Total UI for P1: 0, mck2ui 16
6806 12:14:27.446176 best dqsien dly found for B1: ( 0, 14, 24)
6807 12:14:27.449379 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6808 12:14:27.452587 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6809 12:14:27.452674
6810 12:14:27.455906 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6811 12:14:27.458940 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6812 12:14:27.462529 [Gating] SW calibration Done
6813 12:14:27.462611 ==
6814 12:14:27.465625 Dram Type= 6, Freq= 0, CH_1, rank 1
6815 12:14:27.469123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 12:14:27.469206 ==
6817 12:14:27.472194 RX Vref Scan: 0
6818 12:14:27.472278
6819 12:14:27.472343 RX Vref 0 -> 0, step: 1
6820 12:14:27.472404
6821 12:14:27.475771 RX Delay -410 -> 252, step: 16
6822 12:14:27.482491 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6823 12:14:27.485485 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6824 12:14:27.489209 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6825 12:14:27.492300 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6826 12:14:27.498944 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6827 12:14:27.502043 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6828 12:14:27.505277 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6829 12:14:27.508887 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6830 12:14:27.515320 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6831 12:14:27.518430 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6832 12:14:27.522152 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6833 12:14:27.525243 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6834 12:14:27.531855 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6835 12:14:27.534896 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6836 12:14:27.538500 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6837 12:14:27.545171 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6838 12:14:27.545255 ==
6839 12:14:27.548351 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 12:14:27.551610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 12:14:27.551694 ==
6842 12:14:27.551758 DQS Delay:
6843 12:14:27.554947 DQS0 = 35, DQS1 = 43
6844 12:14:27.555037 DQM Delay:
6845 12:14:27.558338 DQM0 = 17, DQM1 = 18
6846 12:14:27.558421 DQ Delay:
6847 12:14:27.561690 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6848 12:14:27.565052 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6849 12:14:27.567952 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6850 12:14:27.571663 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6851 12:14:27.571739
6852 12:14:27.571810
6853 12:14:27.571870 ==
6854 12:14:27.574641 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 12:14:27.577734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 12:14:27.577804 ==
6857 12:14:27.577864
6858 12:14:27.581350
6859 12:14:27.581426 TX Vref Scan disable
6860 12:14:27.584388 == TX Byte 0 ==
6861 12:14:27.587556 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6862 12:14:27.591061 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6863 12:14:27.594450 == TX Byte 1 ==
6864 12:14:27.597593 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6865 12:14:27.601182 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6866 12:14:27.601269 ==
6867 12:14:27.604302 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 12:14:27.607636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 12:14:27.610685 ==
6870 12:14:27.610756
6871 12:14:27.610832
6872 12:14:27.610892 TX Vref Scan disable
6873 12:14:27.614390 == TX Byte 0 ==
6874 12:14:27.617398 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6875 12:14:27.620746 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6876 12:14:27.624300 == TX Byte 1 ==
6877 12:14:27.627471 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6878 12:14:27.631112 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6879 12:14:27.631183
6880 12:14:27.631251 [DATLAT]
6881 12:14:27.634246 Freq=400, CH1 RK1
6882 12:14:27.634326
6883 12:14:27.637689 DATLAT Default: 0xe
6884 12:14:27.637765 0, 0xFFFF, sum = 0
6885 12:14:27.640730 1, 0xFFFF, sum = 0
6886 12:14:27.640850 2, 0xFFFF, sum = 0
6887 12:14:27.643749 3, 0xFFFF, sum = 0
6888 12:14:27.643821 4, 0xFFFF, sum = 0
6889 12:14:27.647323 5, 0xFFFF, sum = 0
6890 12:14:27.647405 6, 0xFFFF, sum = 0
6891 12:14:27.650387 7, 0xFFFF, sum = 0
6892 12:14:27.650458 8, 0xFFFF, sum = 0
6893 12:14:27.653804 9, 0xFFFF, sum = 0
6894 12:14:27.653879 10, 0xFFFF, sum = 0
6895 12:14:27.657180 11, 0xFFFF, sum = 0
6896 12:14:27.657300 12, 0xFFFF, sum = 0
6897 12:14:27.660606 13, 0x0, sum = 1
6898 12:14:27.660702 14, 0x0, sum = 2
6899 12:14:27.663835 15, 0x0, sum = 3
6900 12:14:27.663915 16, 0x0, sum = 4
6901 12:14:27.667252 best_step = 14
6902 12:14:27.667320
6903 12:14:27.667386 ==
6904 12:14:27.670578 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 12:14:27.673673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 12:14:27.673744 ==
6907 12:14:27.677009 RX Vref Scan: 0
6908 12:14:27.677079
6909 12:14:27.677216 RX Vref 0 -> 0, step: 1
6910 12:14:27.677273
6911 12:14:27.680064 RX Delay -327 -> 252, step: 8
6912 12:14:27.688251 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6913 12:14:27.691297 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6914 12:14:27.694753 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6915 12:14:27.698258 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6916 12:14:27.704494 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6917 12:14:27.708113 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6918 12:14:27.711162 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6919 12:14:27.714576 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6920 12:14:27.721374 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6921 12:14:27.724819 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6922 12:14:27.727972 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6923 12:14:27.734248 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6924 12:14:27.737964 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6925 12:14:27.740900 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6926 12:14:27.744493 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6927 12:14:27.751014 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6928 12:14:27.751089 ==
6929 12:14:27.753984 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 12:14:27.757469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 12:14:27.757547 ==
6932 12:14:27.757610 DQS Delay:
6933 12:14:27.760476 DQS0 = 32, DQS1 = 36
6934 12:14:27.760579 DQM Delay:
6935 12:14:27.764290 DQM0 = 13, DQM1 = 11
6936 12:14:27.764362 DQ Delay:
6937 12:14:27.767099 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6938 12:14:27.770409 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
6939 12:14:27.773727 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6940 12:14:27.776984 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6941 12:14:27.777056
6942 12:14:27.777119
6943 12:14:27.787184 [DQSOSCAuto] RK1, (LSB)MR18= 0xa74f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
6944 12:14:27.787267 CH1 RK1: MR19=C0C, MR18=A74F
6945 12:14:27.793545 CH1_RK1: MR19=0xC0C, MR18=0xA74F, DQSOSC=389, MR23=63, INC=390, DEC=260
6946 12:14:27.796667 [RxdqsGatingPostProcess] freq 400
6947 12:14:27.803523 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6948 12:14:27.806501 best DQS0 dly(2T, 0.5T) = (0, 10)
6949 12:14:27.809979 best DQS1 dly(2T, 0.5T) = (0, 10)
6950 12:14:27.813146 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6951 12:14:27.816653 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6952 12:14:27.819733 best DQS0 dly(2T, 0.5T) = (0, 10)
6953 12:14:27.823310 best DQS1 dly(2T, 0.5T) = (0, 10)
6954 12:14:27.826280 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6955 12:14:27.829656 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6956 12:14:27.829727 Pre-setting of DQS Precalculation
6957 12:14:27.836443 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6958 12:14:27.843213 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6959 12:14:27.849612 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6960 12:14:27.849693
6961 12:14:27.849796
6962 12:14:27.852732 [Calibration Summary] 800 Mbps
6963 12:14:27.856424 CH 0, Rank 0
6964 12:14:27.856501 SW Impedance : PASS
6965 12:14:27.859418 DUTY Scan : NO K
6966 12:14:27.862579 ZQ Calibration : PASS
6967 12:14:27.862662 Jitter Meter : NO K
6968 12:14:27.866657 CBT Training : PASS
6969 12:14:27.869522 Write leveling : PASS
6970 12:14:27.869595 RX DQS gating : PASS
6971 12:14:27.872865 RX DQ/DQS(RDDQC) : PASS
6972 12:14:27.872936 TX DQ/DQS : PASS
6973 12:14:27.875702 RX DATLAT : PASS
6974 12:14:27.879097 RX DQ/DQS(Engine): PASS
6975 12:14:27.879167 TX OE : NO K
6976 12:14:27.882405 All Pass.
6977 12:14:27.882490
6978 12:14:27.882550 CH 0, Rank 1
6979 12:14:27.885718 SW Impedance : PASS
6980 12:14:27.885795 DUTY Scan : NO K
6981 12:14:27.888864 ZQ Calibration : PASS
6982 12:14:27.892255 Jitter Meter : NO K
6983 12:14:27.892326 CBT Training : PASS
6984 12:14:27.895776 Write leveling : NO K
6985 12:14:27.899005 RX DQS gating : PASS
6986 12:14:27.899087 RX DQ/DQS(RDDQC) : PASS
6987 12:14:27.902107 TX DQ/DQS : PASS
6988 12:14:27.905772 RX DATLAT : PASS
6989 12:14:27.905849 RX DQ/DQS(Engine): PASS
6990 12:14:27.908747 TX OE : NO K
6991 12:14:27.908859 All Pass.
6992 12:14:27.908928
6993 12:14:27.912003 CH 1, Rank 0
6994 12:14:27.912086 SW Impedance : PASS
6995 12:14:27.915569 DUTY Scan : NO K
6996 12:14:27.918653 ZQ Calibration : PASS
6997 12:14:27.918726 Jitter Meter : NO K
6998 12:14:27.922055 CBT Training : PASS
6999 12:14:27.925697 Write leveling : PASS
7000 12:14:27.925769 RX DQS gating : PASS
7001 12:14:27.928713 RX DQ/DQS(RDDQC) : PASS
7002 12:14:27.932207 TX DQ/DQS : PASS
7003 12:14:27.932289 RX DATLAT : PASS
7004 12:14:27.935302 RX DQ/DQS(Engine): PASS
7005 12:14:27.938592 TX OE : NO K
7006 12:14:27.938665 All Pass.
7007 12:14:27.938726
7008 12:14:27.938796 CH 1, Rank 1
7009 12:14:27.941694 SW Impedance : PASS
7010 12:14:27.945334 DUTY Scan : NO K
7011 12:14:27.945407 ZQ Calibration : PASS
7012 12:14:27.948412 Jitter Meter : NO K
7013 12:14:27.952015 CBT Training : PASS
7014 12:14:27.952088 Write leveling : NO K
7015 12:14:27.955105 RX DQS gating : PASS
7016 12:14:27.955185 RX DQ/DQS(RDDQC) : PASS
7017 12:14:27.958224 TX DQ/DQS : PASS
7018 12:14:27.961669 RX DATLAT : PASS
7019 12:14:27.961752 RX DQ/DQS(Engine): PASS
7020 12:14:27.964746 TX OE : NO K
7021 12:14:27.964833 All Pass.
7022 12:14:27.964897
7023 12:14:27.967945 DramC Write-DBI off
7024 12:14:27.971501 PER_BANK_REFRESH: Hybrid Mode
7025 12:14:27.971618 TX_TRACKING: ON
7026 12:14:27.981407 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7027 12:14:27.984782 [FAST_K] Save calibration result to emmc
7028 12:14:27.988117 dramc_set_vcore_voltage set vcore to 725000
7029 12:14:27.991084 Read voltage for 1600, 0
7030 12:14:27.991171 Vio18 = 0
7031 12:14:27.994397 Vcore = 725000
7032 12:14:27.994473 Vdram = 0
7033 12:14:27.994544 Vddq = 0
7034 12:14:27.994603 Vmddr = 0
7035 12:14:28.001072 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7036 12:14:28.007548 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7037 12:14:28.007642 MEM_TYPE=3, freq_sel=13
7038 12:14:28.011341 sv_algorithm_assistance_LP4_3733
7039 12:14:28.014535 ============ PULL DRAM RESETB DOWN ============
7040 12:14:28.021098 ========== PULL DRAM RESETB DOWN end =========
7041 12:14:28.024056 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7042 12:14:28.027487 ===================================
7043 12:14:28.030672 LPDDR4 DRAM CONFIGURATION
7044 12:14:28.033994 ===================================
7045 12:14:28.034075 EX_ROW_EN[0] = 0x0
7046 12:14:28.037473 EX_ROW_EN[1] = 0x0
7047 12:14:28.037543 LP4Y_EN = 0x0
7048 12:14:28.041082 WORK_FSP = 0x1
7049 12:14:28.044220 WL = 0x5
7050 12:14:28.044290 RL = 0x5
7051 12:14:28.047330 BL = 0x2
7052 12:14:28.047407 RPST = 0x0
7053 12:14:28.051016 RD_PRE = 0x0
7054 12:14:28.051095 WR_PRE = 0x1
7055 12:14:28.053974 WR_PST = 0x1
7056 12:14:28.054067 DBI_WR = 0x0
7057 12:14:28.057571 DBI_RD = 0x0
7058 12:14:28.057642 OTF = 0x1
7059 12:14:28.060682 ===================================
7060 12:14:28.063811 ===================================
7061 12:14:28.067452 ANA top config
7062 12:14:28.070641 ===================================
7063 12:14:28.070713 DLL_ASYNC_EN = 0
7064 12:14:28.073783 ALL_SLAVE_EN = 0
7065 12:14:28.077323 NEW_RANK_MODE = 1
7066 12:14:28.080262 DLL_IDLE_MODE = 1
7067 12:14:28.083806 LP45_APHY_COMB_EN = 1
7068 12:14:28.083894 TX_ODT_DIS = 0
7069 12:14:28.086880 NEW_8X_MODE = 1
7070 12:14:28.090409 ===================================
7071 12:14:28.093750 ===================================
7072 12:14:28.096989 data_rate = 3200
7073 12:14:28.100170 CKR = 1
7074 12:14:28.103482 DQ_P2S_RATIO = 8
7075 12:14:28.107196 ===================================
7076 12:14:28.107278 CA_P2S_RATIO = 8
7077 12:14:28.110456 DQ_CA_OPEN = 0
7078 12:14:28.113522 DQ_SEMI_OPEN = 0
7079 12:14:28.117056 CA_SEMI_OPEN = 0
7080 12:14:28.120182 CA_FULL_RATE = 0
7081 12:14:28.123847 DQ_CKDIV4_EN = 0
7082 12:14:28.123921 CA_CKDIV4_EN = 0
7083 12:14:28.126910 CA_PREDIV_EN = 0
7084 12:14:28.130341 PH8_DLY = 12
7085 12:14:28.133388 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7086 12:14:28.136988 DQ_AAMCK_DIV = 4
7087 12:14:28.139730 CA_AAMCK_DIV = 4
7088 12:14:28.143362 CA_ADMCK_DIV = 4
7089 12:14:28.143433 DQ_TRACK_CA_EN = 0
7090 12:14:28.146447 CA_PICK = 1600
7091 12:14:28.149998 CA_MCKIO = 1600
7092 12:14:28.153232 MCKIO_SEMI = 0
7093 12:14:28.156265 PLL_FREQ = 3068
7094 12:14:28.159778 DQ_UI_PI_RATIO = 32
7095 12:14:28.162820 CA_UI_PI_RATIO = 0
7096 12:14:28.166469 ===================================
7097 12:14:28.169498 ===================================
7098 12:14:28.169573 memory_type:LPDDR4
7099 12:14:28.173017 GP_NUM : 10
7100 12:14:28.176146 SRAM_EN : 1
7101 12:14:28.176218 MD32_EN : 0
7102 12:14:28.179259 ===================================
7103 12:14:28.182780 [ANA_INIT] >>>>>>>>>>>>>>
7104 12:14:28.186201 <<<<<< [CONFIGURE PHASE]: ANA_TX
7105 12:14:28.189313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7106 12:14:28.192825 ===================================
7107 12:14:28.196001 data_rate = 3200,PCW = 0X7600
7108 12:14:28.199445 ===================================
7109 12:14:28.202695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7110 12:14:28.206057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7111 12:14:28.212315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7112 12:14:28.215611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7113 12:14:28.219016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7114 12:14:28.225401 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7115 12:14:28.225481 [ANA_INIT] flow start
7116 12:14:28.228994 [ANA_INIT] PLL >>>>>>>>
7117 12:14:28.232081 [ANA_INIT] PLL <<<<<<<<
7118 12:14:28.232157 [ANA_INIT] MIDPI >>>>>>>>
7119 12:14:28.235410 [ANA_INIT] MIDPI <<<<<<<<
7120 12:14:28.239120 [ANA_INIT] DLL >>>>>>>>
7121 12:14:28.239207 [ANA_INIT] DLL <<<<<<<<
7122 12:14:28.242196 [ANA_INIT] flow end
7123 12:14:28.245271 ============ LP4 DIFF to SE enter ============
7124 12:14:28.249007 ============ LP4 DIFF to SE exit ============
7125 12:14:28.251996 [ANA_INIT] <<<<<<<<<<<<<
7126 12:14:28.255529 [Flow] Enable top DCM control >>>>>
7127 12:14:28.258556 [Flow] Enable top DCM control <<<<<
7128 12:14:28.261983 Enable DLL master slave shuffle
7129 12:14:28.268691 ==============================================================
7130 12:14:28.268839 Gating Mode config
7131 12:14:28.275327 ==============================================================
7132 12:14:28.275415 Config description:
7133 12:14:28.285020 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7134 12:14:28.291867 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7135 12:14:28.298150 SELPH_MODE 0: By rank 1: By Phase
7136 12:14:28.305095 ==============================================================
7137 12:14:28.305187 GAT_TRACK_EN = 1
7138 12:14:28.308070 RX_GATING_MODE = 2
7139 12:14:28.311631 RX_GATING_TRACK_MODE = 2
7140 12:14:28.314899 SELPH_MODE = 1
7141 12:14:28.318227 PICG_EARLY_EN = 1
7142 12:14:28.321613 VALID_LAT_VALUE = 1
7143 12:14:28.328068 ==============================================================
7144 12:14:28.331508 Enter into Gating configuration >>>>
7145 12:14:28.334503 Exit from Gating configuration <<<<
7146 12:14:28.337941 Enter into DVFS_PRE_config >>>>>
7147 12:14:28.347634 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7148 12:14:28.351289 Exit from DVFS_PRE_config <<<<<
7149 12:14:28.354251 Enter into PICG configuration >>>>
7150 12:14:28.357974 Exit from PICG configuration <<<<
7151 12:14:28.361193 [RX_INPUT] configuration >>>>>
7152 12:14:28.364305 [RX_INPUT] configuration <<<<<
7153 12:14:28.367681 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7154 12:14:28.374394 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7155 12:14:28.380676 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7156 12:14:28.384385 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7157 12:14:28.390646 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7158 12:14:28.397081 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7159 12:14:28.400626 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7160 12:14:28.407392 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7161 12:14:28.410274 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7162 12:14:28.413883 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7163 12:14:28.416962 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7164 12:14:28.423847 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7165 12:14:28.427082 ===================================
7166 12:14:28.427180 LPDDR4 DRAM CONFIGURATION
7167 12:14:28.430355 ===================================
7168 12:14:28.433770 EX_ROW_EN[0] = 0x0
7169 12:14:28.437114 EX_ROW_EN[1] = 0x0
7170 12:14:28.437189 LP4Y_EN = 0x0
7171 12:14:28.440107 WORK_FSP = 0x1
7172 12:14:28.440180 WL = 0x5
7173 12:14:28.443674 RL = 0x5
7174 12:14:28.443749 BL = 0x2
7175 12:14:28.446818 RPST = 0x0
7176 12:14:28.446884 RD_PRE = 0x0
7177 12:14:28.449978 WR_PRE = 0x1
7178 12:14:28.450056 WR_PST = 0x1
7179 12:14:28.453479 DBI_WR = 0x0
7180 12:14:28.453562 DBI_RD = 0x0
7181 12:14:28.456510 OTF = 0x1
7182 12:14:28.460056 ===================================
7183 12:14:28.463251 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7184 12:14:28.466774 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7185 12:14:28.473302 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7186 12:14:28.476323 ===================================
7187 12:14:28.476422 LPDDR4 DRAM CONFIGURATION
7188 12:14:28.479809 ===================================
7189 12:14:28.483306 EX_ROW_EN[0] = 0x10
7190 12:14:28.486342 EX_ROW_EN[1] = 0x0
7191 12:14:28.486441 LP4Y_EN = 0x0
7192 12:14:28.489844 WORK_FSP = 0x1
7193 12:14:28.489958 WL = 0x5
7194 12:14:28.493024 RL = 0x5
7195 12:14:28.493106 BL = 0x2
7196 12:14:28.496027 RPST = 0x0
7197 12:14:28.496125 RD_PRE = 0x0
7198 12:14:28.499458 WR_PRE = 0x1
7199 12:14:28.499539 WR_PST = 0x1
7200 12:14:28.503045 DBI_WR = 0x0
7201 12:14:28.503127 DBI_RD = 0x0
7202 12:14:28.506030 OTF = 0x1
7203 12:14:28.509554 ===================================
7204 12:14:28.515941 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7205 12:14:28.516041 ==
7206 12:14:28.519511 Dram Type= 6, Freq= 0, CH_0, rank 0
7207 12:14:28.522632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7208 12:14:28.522715 ==
7209 12:14:28.526330 [Duty_Offset_Calibration]
7210 12:14:28.526429 B0:2 B1:0 CA:1
7211 12:14:28.526524
7212 12:14:28.529225 [DutyScan_Calibration_Flow] k_type=0
7213 12:14:28.539686
7214 12:14:28.539767 ==CLK 0==
7215 12:14:28.543054 Final CLK duty delay cell = -4
7216 12:14:28.546379 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7217 12:14:28.549866 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7218 12:14:28.552943 [-4] AVG Duty = 4906%(X100)
7219 12:14:28.553029
7220 12:14:28.556408 CH0 CLK Duty spec in!! Max-Min= 187%
7221 12:14:28.559486 [DutyScan_Calibration_Flow] ====Done====
7222 12:14:28.559568
7223 12:14:28.562644 [DutyScan_Calibration_Flow] k_type=1
7224 12:14:28.579082
7225 12:14:28.579164 ==DQS 0 ==
7226 12:14:28.582268 Final DQS duty delay cell = 0
7227 12:14:28.585814 [0] MAX Duty = 5249%(X100), DQS PI = 32
7228 12:14:28.588922 [0] MIN Duty = 4938%(X100), DQS PI = 0
7229 12:14:28.589004 [0] AVG Duty = 5093%(X100)
7230 12:14:28.592512
7231 12:14:28.592593 ==DQS 1 ==
7232 12:14:28.596055 Final DQS duty delay cell = -4
7233 12:14:28.599120 [-4] MAX Duty = 5156%(X100), DQS PI = 46
7234 12:14:28.602189 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7235 12:14:28.605553 [-4] AVG Duty = 5015%(X100)
7236 12:14:28.605634
7237 12:14:28.608712 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7238 12:14:28.608815
7239 12:14:28.612348 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7240 12:14:28.615368 [DutyScan_Calibration_Flow] ====Done====
7241 12:14:28.615450
7242 12:14:28.618934 [DutyScan_Calibration_Flow] k_type=3
7243 12:14:28.636052
7244 12:14:28.636136 ==DQM 0 ==
7245 12:14:28.639204 Final DQM duty delay cell = 0
7246 12:14:28.642730 [0] MAX Duty = 5124%(X100), DQS PI = 26
7247 12:14:28.645908 [0] MIN Duty = 4813%(X100), DQS PI = 50
7248 12:14:28.649327 [0] AVG Duty = 4968%(X100)
7249 12:14:28.649410
7250 12:14:28.649475 ==DQM 1 ==
7251 12:14:28.652240 Final DQM duty delay cell = -4
7252 12:14:28.655524 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7253 12:14:28.658821 [-4] MIN Duty = 4751%(X100), DQS PI = 10
7254 12:14:28.662358 [-4] AVG Duty = 4875%(X100)
7255 12:14:28.662440
7256 12:14:28.665809 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7257 12:14:28.665891
7258 12:14:28.668808 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7259 12:14:28.672109 [DutyScan_Calibration_Flow] ====Done====
7260 12:14:28.672192
7261 12:14:28.675537 [DutyScan_Calibration_Flow] k_type=2
7262 12:14:28.693515
7263 12:14:28.693598 ==DQ 0 ==
7264 12:14:28.696610 Final DQ duty delay cell = 0
7265 12:14:28.700242 [0] MAX Duty = 5124%(X100), DQS PI = 32
7266 12:14:28.703251 [0] MIN Duty = 5000%(X100), DQS PI = 0
7267 12:14:28.703324 [0] AVG Duty = 5062%(X100)
7268 12:14:28.706398
7269 12:14:28.706531 ==DQ 1 ==
7270 12:14:28.709843 Final DQ duty delay cell = 0
7271 12:14:28.713390 [0] MAX Duty = 4969%(X100), DQS PI = 42
7272 12:14:28.716524 [0] MIN Duty = 4875%(X100), DQS PI = 12
7273 12:14:28.716620 [0] AVG Duty = 4922%(X100)
7274 12:14:28.716709
7275 12:14:28.722941 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7276 12:14:28.723024
7277 12:14:28.726588 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7278 12:14:28.729573 [DutyScan_Calibration_Flow] ====Done====
7279 12:14:28.729656 ==
7280 12:14:28.733234 Dram Type= 6, Freq= 0, CH_1, rank 0
7281 12:14:28.736268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7282 12:14:28.736381 ==
7283 12:14:28.739728 [Duty_Offset_Calibration]
7284 12:14:28.739811 B0:0 B1:-1 CA:2
7285 12:14:28.739877
7286 12:14:28.743312 [DutyScan_Calibration_Flow] k_type=0
7287 12:14:28.753572
7288 12:14:28.753655 ==CLK 0==
7289 12:14:28.756797 Final CLK duty delay cell = 0
7290 12:14:28.760136 [0] MAX Duty = 5156%(X100), DQS PI = 10
7291 12:14:28.763310 [0] MIN Duty = 4906%(X100), DQS PI = 46
7292 12:14:28.766937 [0] AVG Duty = 5031%(X100)
7293 12:14:28.767044
7294 12:14:28.770287 CH1 CLK Duty spec in!! Max-Min= 250%
7295 12:14:28.773332 [DutyScan_Calibration_Flow] ====Done====
7296 12:14:28.773410
7297 12:14:28.776372 [DutyScan_Calibration_Flow] k_type=1
7298 12:14:28.793296
7299 12:14:28.793377 ==DQS 0 ==
7300 12:14:28.796802 Final DQS duty delay cell = 0
7301 12:14:28.799799 [0] MAX Duty = 5124%(X100), DQS PI = 26
7302 12:14:28.803463 [0] MIN Duty = 4969%(X100), DQS PI = 2
7303 12:14:28.803573 [0] AVG Duty = 5046%(X100)
7304 12:14:28.806496
7305 12:14:28.806614 ==DQS 1 ==
7306 12:14:28.809999 Final DQS duty delay cell = 0
7307 12:14:28.813067 [0] MAX Duty = 5187%(X100), DQS PI = 0
7308 12:14:28.816582 [0] MIN Duty = 4844%(X100), DQS PI = 34
7309 12:14:28.819685 [0] AVG Duty = 5015%(X100)
7310 12:14:28.819790
7311 12:14:28.823324 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7312 12:14:28.823405
7313 12:14:28.826201 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7314 12:14:28.829874 [DutyScan_Calibration_Flow] ====Done====
7315 12:14:28.829954
7316 12:14:28.832904 [DutyScan_Calibration_Flow] k_type=3
7317 12:14:28.850999
7318 12:14:28.851079 ==DQM 0 ==
7319 12:14:28.854125 Final DQM duty delay cell = 4
7320 12:14:28.857468 [4] MAX Duty = 5125%(X100), DQS PI = 8
7321 12:14:28.860551 [4] MIN Duty = 4969%(X100), DQS PI = 46
7322 12:14:28.864026 [4] AVG Duty = 5047%(X100)
7323 12:14:28.864097
7324 12:14:28.864160 ==DQM 1 ==
7325 12:14:28.867216 Final DQM duty delay cell = 0
7326 12:14:28.870187 [0] MAX Duty = 5281%(X100), DQS PI = 58
7327 12:14:28.873585 [0] MIN Duty = 4907%(X100), DQS PI = 34
7328 12:14:28.877385 [0] AVG Duty = 5094%(X100)
7329 12:14:28.877466
7330 12:14:28.880500 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7331 12:14:28.880605
7332 12:14:28.883674 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7333 12:14:28.886765 [DutyScan_Calibration_Flow] ====Done====
7334 12:14:28.886845
7335 12:14:28.890234 [DutyScan_Calibration_Flow] k_type=2
7336 12:14:28.907543
7337 12:14:28.907669 ==DQ 0 ==
7338 12:14:28.911104 Final DQ duty delay cell = 0
7339 12:14:28.914522 [0] MAX Duty = 5093%(X100), DQS PI = 18
7340 12:14:28.917506 [0] MIN Duty = 4969%(X100), DQS PI = 46
7341 12:14:28.917589 [0] AVG Duty = 5031%(X100)
7342 12:14:28.921055
7343 12:14:28.921163 ==DQ 1 ==
7344 12:14:28.924095 Final DQ duty delay cell = 0
7345 12:14:28.927540 [0] MAX Duty = 5062%(X100), DQS PI = 2
7346 12:14:28.930484 [0] MIN Duty = 4844%(X100), DQS PI = 32
7347 12:14:28.930608 [0] AVG Duty = 4953%(X100)
7348 12:14:28.934246
7349 12:14:28.937387 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7350 12:14:28.937497
7351 12:14:28.940494 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7352 12:14:28.943608 [DutyScan_Calibration_Flow] ====Done====
7353 12:14:28.947266 nWR fixed to 30
7354 12:14:28.947374 [ModeRegInit_LP4] CH0 RK0
7355 12:14:28.950318 [ModeRegInit_LP4] CH0 RK1
7356 12:14:28.953898 [ModeRegInit_LP4] CH1 RK0
7357 12:14:28.957137 [ModeRegInit_LP4] CH1 RK1
7358 12:14:28.957227 match AC timing 5
7359 12:14:28.963514 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7360 12:14:28.967068 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7361 12:14:28.970497 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7362 12:14:28.977086 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7363 12:14:28.980312 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7364 12:14:28.980476 [MiockJmeterHQA]
7365 12:14:28.980584
7366 12:14:28.983554 [DramcMiockJmeter] u1RxGatingPI = 0
7367 12:14:28.986959 0 : 4368, 4139
7368 12:14:28.987086 4 : 4255, 4029
7369 12:14:28.990069 8 : 4257, 4030
7370 12:14:28.990153 12 : 4253, 4027
7371 12:14:28.990282 16 : 4363, 4137
7372 12:14:28.993556 20 : 4252, 4027
7373 12:14:28.993640 24 : 4252, 4027
7374 12:14:28.997059 28 : 4253, 4027
7375 12:14:28.997156 32 : 4255, 4029
7376 12:14:28.999970 36 : 4363, 4137
7377 12:14:29.000128 40 : 4252, 4027
7378 12:14:29.003506 44 : 4363, 4137
7379 12:14:29.003636 48 : 4252, 4027
7380 12:14:29.003765 52 : 4252, 4027
7381 12:14:29.006640 56 : 4250, 4027
7382 12:14:29.006761 60 : 4361, 4137
7383 12:14:29.010224 64 : 4250, 4027
7384 12:14:29.010332 68 : 4361, 4137
7385 12:14:29.013300 72 : 4250, 4027
7386 12:14:29.013405 76 : 4250, 4026
7387 12:14:29.017060 80 : 4252, 4029
7388 12:14:29.017172 84 : 4252, 4030
7389 12:14:29.017267 88 : 4250, 3424
7390 12:14:29.020005 92 : 4253, 0
7391 12:14:29.020113 96 : 4253, 0
7392 12:14:29.023566 100 : 4363, 0
7393 12:14:29.023674 104 : 4249, 0
7394 12:14:29.023779 108 : 4250, 0
7395 12:14:29.026740 112 : 4250, 0
7396 12:14:29.026849 116 : 4250, 0
7397 12:14:29.029781 120 : 4253, 0
7398 12:14:29.029892 124 : 4250, 0
7399 12:14:29.029988 128 : 4250, 0
7400 12:14:29.033213 132 : 4252, 0
7401 12:14:29.033318 136 : 4250, 0
7402 12:14:29.033415 140 : 4250, 0
7403 12:14:29.036329 144 : 4252, 0
7404 12:14:29.036432 148 : 4361, 0
7405 12:14:29.039846 152 : 4360, 0
7406 12:14:29.039946 156 : 4250, 0
7407 12:14:29.040043 160 : 4250, 0
7408 12:14:29.042895 164 : 4250, 0
7409 12:14:29.042996 168 : 4360, 0
7410 12:14:29.046055 172 : 4250, 0
7411 12:14:29.046161 176 : 4250, 0
7412 12:14:29.046256 180 : 4250, 0
7413 12:14:29.049732 184 : 4250, 0
7414 12:14:29.049841 188 : 4250, 0
7415 12:14:29.052726 192 : 4250, 0
7416 12:14:29.052835 196 : 4250, 0
7417 12:14:29.052936 200 : 4250, 5
7418 12:14:29.056414 204 : 4361, 2511
7419 12:14:29.056514 208 : 4361, 4137
7420 12:14:29.059532 212 : 4250, 4026
7421 12:14:29.059633 216 : 4361, 4137
7422 12:14:29.063082 220 : 4361, 4137
7423 12:14:29.063185 224 : 4250, 4027
7424 12:14:29.066120 228 : 4252, 4027
7425 12:14:29.066228 232 : 4250, 4026
7426 12:14:29.069235 236 : 4250, 4027
7427 12:14:29.069336 240 : 4250, 4027
7428 12:14:29.072739 244 : 4250, 4027
7429 12:14:29.072831 248 : 4250, 4026
7430 12:14:29.075876 252 : 4250, 4027
7431 12:14:29.075984 256 : 4360, 4138
7432 12:14:29.076080 260 : 4361, 4137
7433 12:14:29.078966 264 : 4250, 4027
7434 12:14:29.079072 268 : 4361, 4138
7435 12:14:29.082369 272 : 4250, 4027
7436 12:14:29.082477 276 : 4250, 4027
7437 12:14:29.085727 280 : 4250, 4027
7438 12:14:29.085836 284 : 4250, 4026
7439 12:14:29.089160 288 : 4250, 4027
7440 12:14:29.089263 292 : 4250, 4026
7441 12:14:29.092297 296 : 4250, 4027
7442 12:14:29.092415 300 : 4250, 4027
7443 12:14:29.095651 304 : 4250, 4027
7444 12:14:29.095770 308 : 4360, 4138
7445 12:14:29.099265 312 : 4361, 4054
7446 12:14:29.099378 316 : 4250, 2074
7447 12:14:29.099484
7448 12:14:29.102355 MIOCK jitter meter ch=0
7449 12:14:29.102461
7450 12:14:29.105492 1T = (316-92) = 224 dly cells
7451 12:14:29.108974 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7452 12:14:29.109053 ==
7453 12:14:29.112570 Dram Type= 6, Freq= 0, CH_0, rank 0
7454 12:14:29.118785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7455 12:14:29.118891 ==
7456 12:14:29.122406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7457 12:14:29.128840 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7458 12:14:29.131991 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7459 12:14:29.138911 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7460 12:14:29.146645 [CA 0] Center 42 (12~72) winsize 61
7461 12:14:29.149773 [CA 1] Center 42 (12~72) winsize 61
7462 12:14:29.152911 [CA 2] Center 37 (7~67) winsize 61
7463 12:14:29.156528 [CA 3] Center 37 (7~67) winsize 61
7464 12:14:29.159652 [CA 4] Center 36 (6~66) winsize 61
7465 12:14:29.162780 [CA 5] Center 35 (5~65) winsize 61
7466 12:14:29.162880
7467 12:14:29.166401 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7468 12:14:29.166504
7469 12:14:29.173014 [CATrainingPosCal] consider 1 rank data
7470 12:14:29.173124 u2DelayCellTimex100 = 290/100 ps
7471 12:14:29.179520 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7472 12:14:29.182607 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7473 12:14:29.186241 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7474 12:14:29.189388 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7475 12:14:29.192745 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7476 12:14:29.196046 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7477 12:14:29.196153
7478 12:14:29.199263 CA PerBit enable=1, Macro0, CA PI delay=35
7479 12:14:29.199366
7480 12:14:29.202510 [CBTSetCACLKResult] CA Dly = 35
7481 12:14:29.205799 CS Dly: 9 (0~40)
7482 12:14:29.209016 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7483 12:14:29.212472 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7484 12:14:29.212576 ==
7485 12:14:29.215597 Dram Type= 6, Freq= 0, CH_0, rank 1
7486 12:14:29.222265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7487 12:14:29.222378 ==
7488 12:14:29.225811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7489 12:14:29.232330 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7490 12:14:29.235454 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7491 12:14:29.242200 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7492 12:14:29.249818 [CA 0] Center 43 (13~74) winsize 62
7493 12:14:29.252832 [CA 1] Center 43 (13~73) winsize 61
7494 12:14:29.256467 [CA 2] Center 38 (9~68) winsize 60
7495 12:14:29.259551 [CA 3] Center 38 (9~68) winsize 60
7496 12:14:29.263044 [CA 4] Center 37 (7~67) winsize 61
7497 12:14:29.266208 [CA 5] Center 36 (6~66) winsize 61
7498 12:14:29.266309
7499 12:14:29.269809 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7500 12:14:29.269907
7501 12:14:29.273138 [CATrainingPosCal] consider 2 rank data
7502 12:14:29.276193 u2DelayCellTimex100 = 290/100 ps
7503 12:14:29.282984 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7504 12:14:29.286082 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7505 12:14:29.289493 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7506 12:14:29.292556 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7507 12:14:29.296175 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7508 12:14:29.299247 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7509 12:14:29.299348
7510 12:14:29.302393 CA PerBit enable=1, Macro0, CA PI delay=35
7511 12:14:29.302494
7512 12:14:29.305715 [CBTSetCACLKResult] CA Dly = 35
7513 12:14:29.308925 CS Dly: 10 (0~43)
7514 12:14:29.312192 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7515 12:14:29.315791 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7516 12:14:29.315869
7517 12:14:29.318729 ----->DramcWriteLeveling(PI) begin...
7518 12:14:29.318832 ==
7519 12:14:29.322297 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 12:14:29.329113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 12:14:29.329216 ==
7522 12:14:29.332115 Write leveling (Byte 0): 36 => 36
7523 12:14:29.335548 Write leveling (Byte 1): 30 => 30
7524 12:14:29.335652 DramcWriteLeveling(PI) end<-----
7525 12:14:29.338604
7526 12:14:29.338707 ==
7527 12:14:29.342203 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 12:14:29.345550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 12:14:29.345655 ==
7530 12:14:29.348613 [Gating] SW mode calibration
7531 12:14:29.355369 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7532 12:14:29.358626 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7533 12:14:29.365139 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7534 12:14:29.368745 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7535 12:14:29.371862 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7536 12:14:29.378442 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7537 12:14:29.382147 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7538 12:14:29.385378 1 4 20 | B1->B0 | 3433 3434 | 1 1 | (1 1) (1 1)
7539 12:14:29.392015 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7540 12:14:29.394932 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7541 12:14:29.398566 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7542 12:14:29.405234 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7543 12:14:29.408155 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7544 12:14:29.411464 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7545 12:14:29.418081 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7546 12:14:29.421458 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7547 12:14:29.424631 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 12:14:29.431673 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 12:14:29.434819 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 12:14:29.438179 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 12:14:29.444731 1 6 8 | B1->B0 | 2323 3f3e | 0 1 | (0 0) (0 0)
7552 12:14:29.448076 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7553 12:14:29.451460 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7554 12:14:29.457918 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7555 12:14:29.461078 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 12:14:29.464695 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 12:14:29.471450 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 12:14:29.474578 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7559 12:14:29.477818 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 12:14:29.484123 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7561 12:14:29.487763 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7562 12:14:29.490841 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7563 12:14:29.497496 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7564 12:14:29.500706 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 12:14:29.504356 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 12:14:29.510846 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 12:14:29.514095 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 12:14:29.517368 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 12:14:29.524051 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 12:14:29.527504 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 12:14:29.530504 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 12:14:29.537226 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 12:14:29.540289 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 12:14:29.543791 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 12:14:29.550585 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7576 12:14:29.553527 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7577 12:14:29.556970 Total UI for P1: 0, mck2ui 16
7578 12:14:29.560091 best dqsien dly found for B0: ( 1, 9, 8)
7579 12:14:29.563362 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7580 12:14:29.570000 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7581 12:14:29.573572 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 12:14:29.576635 Total UI for P1: 0, mck2ui 16
7583 12:14:29.580407 best dqsien dly found for B1: ( 1, 9, 18)
7584 12:14:29.583313 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7585 12:14:29.586814 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7586 12:14:29.587062
7587 12:14:29.589720 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7588 12:14:29.593290 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7589 12:14:29.596494 [Gating] SW calibration Done
7590 12:14:29.596592 ==
7591 12:14:29.599470 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 12:14:29.606149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 12:14:29.606257 ==
7594 12:14:29.606354 RX Vref Scan: 0
7595 12:14:29.606443
7596 12:14:29.609312 RX Vref 0 -> 0, step: 1
7597 12:14:29.609424
7598 12:14:29.613026 RX Delay 0 -> 252, step: 8
7599 12:14:29.616135 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7600 12:14:29.619584 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7601 12:14:29.622600 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7602 12:14:29.626168 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7603 12:14:29.632978 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7604 12:14:29.635946 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7605 12:14:29.639365 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7606 12:14:29.642613 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7607 12:14:29.646139 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7608 12:14:29.649630 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7609 12:14:29.656328 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7610 12:14:29.659622 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7611 12:14:29.662558 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7612 12:14:29.666309 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7613 12:14:29.672560 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7614 12:14:29.676484 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7615 12:14:29.676594 ==
7616 12:14:29.679526 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 12:14:29.682555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 12:14:29.682668 ==
7619 12:14:29.685778 DQS Delay:
7620 12:14:29.685867 DQS0 = 0, DQS1 = 0
7621 12:14:29.685942 DQM Delay:
7622 12:14:29.689146 DQM0 = 138, DQM1 = 126
7623 12:14:29.689232 DQ Delay:
7624 12:14:29.692552 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7625 12:14:29.695719 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7626 12:14:29.699397 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7627 12:14:29.705369 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7628 12:14:29.705445
7629 12:14:29.705508
7630 12:14:29.705566 ==
7631 12:14:29.708984 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 12:14:29.712102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 12:14:29.712175 ==
7634 12:14:29.712236
7635 12:14:29.712294
7636 12:14:29.715741 TX Vref Scan disable
7637 12:14:29.715826 == TX Byte 0 ==
7638 12:14:29.721896 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7639 12:14:29.725339 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7640 12:14:29.725439 == TX Byte 1 ==
7641 12:14:29.731752 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7642 12:14:29.735008 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7643 12:14:29.735108 ==
7644 12:14:29.738261 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 12:14:29.741805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 12:14:29.741901 ==
7647 12:14:29.756618
7648 12:14:29.759676 TX Vref early break, caculate TX vref
7649 12:14:29.763166 TX Vref=16, minBit 7, minWin=22, winSum=376
7650 12:14:29.766224 TX Vref=18, minBit 6, minWin=23, winSum=384
7651 12:14:29.769845 TX Vref=20, minBit 1, minWin=24, winSum=399
7652 12:14:29.773020 TX Vref=22, minBit 1, minWin=25, winSum=409
7653 12:14:29.776159 TX Vref=24, minBit 7, minWin=24, winSum=416
7654 12:14:29.782806 TX Vref=26, minBit 4, minWin=25, winSum=422
7655 12:14:29.786450 TX Vref=28, minBit 0, minWin=26, winSum=432
7656 12:14:29.789461 TX Vref=30, minBit 2, minWin=25, winSum=423
7657 12:14:29.792803 TX Vref=32, minBit 0, minWin=25, winSum=415
7658 12:14:29.795949 TX Vref=34, minBit 0, minWin=25, winSum=405
7659 12:14:29.802714 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
7660 12:14:29.802817
7661 12:14:29.805788 Final TX Range 0 Vref 28
7662 12:14:29.805862
7663 12:14:29.805923 ==
7664 12:14:29.809299 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 12:14:29.812774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 12:14:29.812879 ==
7667 12:14:29.812941
7668 12:14:29.813004
7669 12:14:29.815812 TX Vref Scan disable
7670 12:14:29.822526 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7671 12:14:29.822626 == TX Byte 0 ==
7672 12:14:29.825537 u2DelayCellOfst[0]=10 cells (3 PI)
7673 12:14:29.828909 u2DelayCellOfst[1]=16 cells (5 PI)
7674 12:14:29.832109 u2DelayCellOfst[2]=10 cells (3 PI)
7675 12:14:29.835749 u2DelayCellOfst[3]=13 cells (4 PI)
7676 12:14:29.838782 u2DelayCellOfst[4]=6 cells (2 PI)
7677 12:14:29.842234 u2DelayCellOfst[5]=0 cells (0 PI)
7678 12:14:29.845464 u2DelayCellOfst[6]=16 cells (5 PI)
7679 12:14:29.848746 u2DelayCellOfst[7]=16 cells (5 PI)
7680 12:14:29.852139 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7681 12:14:29.855601 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7682 12:14:29.858382 == TX Byte 1 ==
7683 12:14:29.862013 u2DelayCellOfst[8]=3 cells (1 PI)
7684 12:14:29.865055 u2DelayCellOfst[9]=0 cells (0 PI)
7685 12:14:29.868610 u2DelayCellOfst[10]=6 cells (2 PI)
7686 12:14:29.868709 u2DelayCellOfst[11]=3 cells (1 PI)
7687 12:14:29.871679 u2DelayCellOfst[12]=13 cells (4 PI)
7688 12:14:29.875225 u2DelayCellOfst[13]=13 cells (4 PI)
7689 12:14:29.878381 u2DelayCellOfst[14]=13 cells (4 PI)
7690 12:14:29.882052 u2DelayCellOfst[15]=10 cells (3 PI)
7691 12:14:29.888235 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7692 12:14:29.891805 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7693 12:14:29.891877 DramC Write-DBI on
7694 12:14:29.891938 ==
7695 12:14:29.894900 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 12:14:29.901500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 12:14:29.901575 ==
7698 12:14:29.901637
7699 12:14:29.901695
7700 12:14:29.904665 TX Vref Scan disable
7701 12:14:29.904762 == TX Byte 0 ==
7702 12:14:29.911252 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7703 12:14:29.911354 == TX Byte 1 ==
7704 12:14:29.914683 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7705 12:14:29.918277 DramC Write-DBI off
7706 12:14:29.918375
7707 12:14:29.918465 [DATLAT]
7708 12:14:29.921305 Freq=1600, CH0 RK0
7709 12:14:29.921374
7710 12:14:29.921433 DATLAT Default: 0xf
7711 12:14:29.924451 0, 0xFFFF, sum = 0
7712 12:14:29.924546 1, 0xFFFF, sum = 0
7713 12:14:29.928088 2, 0xFFFF, sum = 0
7714 12:14:29.928162 3, 0xFFFF, sum = 0
7715 12:14:29.931175 4, 0xFFFF, sum = 0
7716 12:14:29.931273 5, 0xFFFF, sum = 0
7717 12:14:29.934302 6, 0xFFFF, sum = 0
7718 12:14:29.934403 7, 0xFFFF, sum = 0
7719 12:14:29.937785 8, 0xFFFF, sum = 0
7720 12:14:29.940870 9, 0xFFFF, sum = 0
7721 12:14:29.940944 10, 0xFFFF, sum = 0
7722 12:14:29.944527 11, 0xFFFF, sum = 0
7723 12:14:29.944629 12, 0xFFFF, sum = 0
7724 12:14:29.947612 13, 0xFFFF, sum = 0
7725 12:14:29.947712 14, 0x0, sum = 1
7726 12:14:29.950912 15, 0x0, sum = 2
7727 12:14:29.951013 16, 0x0, sum = 3
7728 12:14:29.954196 17, 0x0, sum = 4
7729 12:14:29.954296 best_step = 15
7730 12:14:29.954394
7731 12:14:29.954482 ==
7732 12:14:29.957415 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 12:14:29.960660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 12:14:29.964090 ==
7735 12:14:29.964197 RX Vref Scan: 1
7736 12:14:29.964294
7737 12:14:29.967352 Set Vref Range= 24 -> 127
7738 12:14:29.967452
7739 12:14:29.967551 RX Vref 24 -> 127, step: 1
7740 12:14:29.970599
7741 12:14:29.970700 RX Delay 19 -> 252, step: 4
7742 12:14:29.970797
7743 12:14:29.974073 Set Vref, RX VrefLevel [Byte0]: 24
7744 12:14:29.977235 [Byte1]: 24
7745 12:14:29.980694
7746 12:14:29.980834 Set Vref, RX VrefLevel [Byte0]: 25
7747 12:14:29.984221 [Byte1]: 25
7748 12:14:29.988739
7749 12:14:29.988822 Set Vref, RX VrefLevel [Byte0]: 26
7750 12:14:29.991738 [Byte1]: 26
7751 12:14:29.996192
7752 12:14:29.996292 Set Vref, RX VrefLevel [Byte0]: 27
7753 12:14:29.999201 [Byte1]: 27
7754 12:14:30.003673
7755 12:14:30.003770 Set Vref, RX VrefLevel [Byte0]: 28
7756 12:14:30.006761 [Byte1]: 28
7757 12:14:30.011259
7758 12:14:30.011369 Set Vref, RX VrefLevel [Byte0]: 29
7759 12:14:30.014450 [Byte1]: 29
7760 12:14:30.018759
7761 12:14:30.018868 Set Vref, RX VrefLevel [Byte0]: 30
7762 12:14:30.022087 [Byte1]: 30
7763 12:14:30.026559
7764 12:14:30.026666 Set Vref, RX VrefLevel [Byte0]: 31
7765 12:14:30.029796 [Byte1]: 31
7766 12:14:30.033783
7767 12:14:30.033861 Set Vref, RX VrefLevel [Byte0]: 32
7768 12:14:30.037348 [Byte1]: 32
7769 12:14:30.041510
7770 12:14:30.041585 Set Vref, RX VrefLevel [Byte0]: 33
7771 12:14:30.045113 [Byte1]: 33
7772 12:14:30.049295
7773 12:14:30.049369 Set Vref, RX VrefLevel [Byte0]: 34
7774 12:14:30.052419 [Byte1]: 34
7775 12:14:30.056811
7776 12:14:30.059855 Set Vref, RX VrefLevel [Byte0]: 35
7777 12:14:30.059933 [Byte1]: 35
7778 12:14:30.064129
7779 12:14:30.064228 Set Vref, RX VrefLevel [Byte0]: 36
7780 12:14:30.067297 [Byte1]: 36
7781 12:14:30.071645
7782 12:14:30.071720 Set Vref, RX VrefLevel [Byte0]: 37
7783 12:14:30.074952 [Byte1]: 37
7784 12:14:30.079221
7785 12:14:30.079295 Set Vref, RX VrefLevel [Byte0]: 38
7786 12:14:30.082737 [Byte1]: 38
7787 12:14:30.086971
7788 12:14:30.087073 Set Vref, RX VrefLevel [Byte0]: 39
7789 12:14:30.090547 [Byte1]: 39
7790 12:14:30.094518
7791 12:14:30.094592 Set Vref, RX VrefLevel [Byte0]: 40
7792 12:14:30.097672 [Byte1]: 40
7793 12:14:30.102224
7794 12:14:30.102294 Set Vref, RX VrefLevel [Byte0]: 41
7795 12:14:30.105204 [Byte1]: 41
7796 12:14:30.109759
7797 12:14:30.109834 Set Vref, RX VrefLevel [Byte0]: 42
7798 12:14:30.112952 [Byte1]: 42
7799 12:14:30.117059
7800 12:14:30.117132 Set Vref, RX VrefLevel [Byte0]: 43
7801 12:14:30.120592 [Byte1]: 43
7802 12:14:30.124646
7803 12:14:30.124744 Set Vref, RX VrefLevel [Byte0]: 44
7804 12:14:30.128290 [Byte1]: 44
7805 12:14:30.132424
7806 12:14:30.132521 Set Vref, RX VrefLevel [Byte0]: 45
7807 12:14:30.135524 [Byte1]: 45
7808 12:14:30.140303
7809 12:14:30.140409 Set Vref, RX VrefLevel [Byte0]: 46
7810 12:14:30.143225 [Byte1]: 46
7811 12:14:30.147331
7812 12:14:30.147431 Set Vref, RX VrefLevel [Byte0]: 47
7813 12:14:30.151039 [Byte1]: 47
7814 12:14:30.155300
7815 12:14:30.155399 Set Vref, RX VrefLevel [Byte0]: 48
7816 12:14:30.158325 [Byte1]: 48
7817 12:14:30.162805
7818 12:14:30.162905 Set Vref, RX VrefLevel [Byte0]: 49
7819 12:14:30.166069 [Byte1]: 49
7820 12:14:30.170412
7821 12:14:30.170512 Set Vref, RX VrefLevel [Byte0]: 50
7822 12:14:30.173342 [Byte1]: 50
7823 12:14:30.177701
7824 12:14:30.177804 Set Vref, RX VrefLevel [Byte0]: 51
7825 12:14:30.181020 [Byte1]: 51
7826 12:14:30.185472
7827 12:14:30.185572 Set Vref, RX VrefLevel [Byte0]: 52
7828 12:14:30.188649 [Byte1]: 52
7829 12:14:30.193213
7830 12:14:30.193316 Set Vref, RX VrefLevel [Byte0]: 53
7831 12:14:30.196239 [Byte1]: 53
7832 12:14:30.200687
7833 12:14:30.200809 Set Vref, RX VrefLevel [Byte0]: 54
7834 12:14:30.203813 [Byte1]: 54
7835 12:14:30.207920
7836 12:14:30.207994 Set Vref, RX VrefLevel [Byte0]: 55
7837 12:14:30.211403 [Byte1]: 55
7838 12:14:30.215528
7839 12:14:30.215625 Set Vref, RX VrefLevel [Byte0]: 56
7840 12:14:30.219109 [Byte1]: 56
7841 12:14:30.223141
7842 12:14:30.223242 Set Vref, RX VrefLevel [Byte0]: 57
7843 12:14:30.226680 [Byte1]: 57
7844 12:14:30.230743
7845 12:14:30.230841 Set Vref, RX VrefLevel [Byte0]: 58
7846 12:14:30.233884 [Byte1]: 58
7847 12:14:30.238497
7848 12:14:30.238591 Set Vref, RX VrefLevel [Byte0]: 59
7849 12:14:30.241719 [Byte1]: 59
7850 12:14:30.246041
7851 12:14:30.246142 Set Vref, RX VrefLevel [Byte0]: 60
7852 12:14:30.249526 [Byte1]: 60
7853 12:14:30.253677
7854 12:14:30.253754 Set Vref, RX VrefLevel [Byte0]: 61
7855 12:14:30.256693 [Byte1]: 61
7856 12:14:30.260995
7857 12:14:30.261065 Set Vref, RX VrefLevel [Byte0]: 62
7858 12:14:30.264345 [Byte1]: 62
7859 12:14:30.268514
7860 12:14:30.268614 Set Vref, RX VrefLevel [Byte0]: 63
7861 12:14:30.272181 [Byte1]: 63
7862 12:14:30.276460
7863 12:14:30.276559 Set Vref, RX VrefLevel [Byte0]: 64
7864 12:14:30.279530 [Byte1]: 64
7865 12:14:30.283992
7866 12:14:30.284081 Set Vref, RX VrefLevel [Byte0]: 65
7867 12:14:30.287312 [Byte1]: 65
7868 12:14:30.291543
7869 12:14:30.291615 Set Vref, RX VrefLevel [Byte0]: 66
7870 12:14:30.294473 [Byte1]: 66
7871 12:14:30.298875
7872 12:14:30.298957 Set Vref, RX VrefLevel [Byte0]: 67
7873 12:14:30.302469 [Byte1]: 67
7874 12:14:30.306575
7875 12:14:30.306682 Set Vref, RX VrefLevel [Byte0]: 68
7876 12:14:30.309721 [Byte1]: 68
7877 12:14:30.314106
7878 12:14:30.314215 Set Vref, RX VrefLevel [Byte0]: 69
7879 12:14:30.317651 [Byte1]: 69
7880 12:14:30.321781
7881 12:14:30.321853 Set Vref, RX VrefLevel [Byte0]: 70
7882 12:14:30.324941 [Byte1]: 70
7883 12:14:30.329394
7884 12:14:30.329480 Set Vref, RX VrefLevel [Byte0]: 71
7885 12:14:30.332468 [Byte1]: 71
7886 12:14:30.337005
7887 12:14:30.337080 Set Vref, RX VrefLevel [Byte0]: 72
7888 12:14:30.340020 [Byte1]: 72
7889 12:14:30.344237
7890 12:14:30.344314 Set Vref, RX VrefLevel [Byte0]: 73
7891 12:14:30.347628 [Byte1]: 73
7892 12:14:30.352010
7893 12:14:30.352084 Set Vref, RX VrefLevel [Byte0]: 74
7894 12:14:30.355563 [Byte1]: 74
7895 12:14:30.359772
7896 12:14:30.359860 Set Vref, RX VrefLevel [Byte0]: 75
7897 12:14:30.362849 [Byte1]: 75
7898 12:14:30.367300
7899 12:14:30.367401 Set Vref, RX VrefLevel [Byte0]: 76
7900 12:14:30.370274 [Byte1]: 76
7901 12:14:30.374820
7902 12:14:30.374919 Set Vref, RX VrefLevel [Byte0]: 77
7903 12:14:30.377841 [Byte1]: 77
7904 12:14:30.382191
7905 12:14:30.382259 Set Vref, RX VrefLevel [Byte0]: 78
7906 12:14:30.385371 [Byte1]: 78
7907 12:14:30.389806
7908 12:14:30.389900 Set Vref, RX VrefLevel [Byte0]: 79
7909 12:14:30.393267 [Byte1]: 79
7910 12:14:30.397433
7911 12:14:30.397532 Set Vref, RX VrefLevel [Byte0]: 80
7912 12:14:30.400846 [Byte1]: 80
7913 12:14:30.405030
7914 12:14:30.405113 Final RX Vref Byte 0 = 63 to rank0
7915 12:14:30.408484 Final RX Vref Byte 1 = 62 to rank0
7916 12:14:30.411550 Final RX Vref Byte 0 = 63 to rank1
7917 12:14:30.414756 Final RX Vref Byte 1 = 62 to rank1==
7918 12:14:30.418257 Dram Type= 6, Freq= 0, CH_0, rank 0
7919 12:14:30.424853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7920 12:14:30.424967 ==
7921 12:14:30.425057 DQS Delay:
7922 12:14:30.427974 DQS0 = 0, DQS1 = 0
7923 12:14:30.428057 DQM Delay:
7924 12:14:30.428122 DQM0 = 136, DQM1 = 124
7925 12:14:30.431516 DQ Delay:
7926 12:14:30.434556 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7927 12:14:30.438279 DQ4 =138, DQ5 =126, DQ6 =144, DQ7 =142
7928 12:14:30.441435 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7929 12:14:30.444406 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7930 12:14:30.444489
7931 12:14:30.444554
7932 12:14:30.444614
7933 12:14:30.448097 [DramC_TX_OE_Calibration] TA2
7934 12:14:30.451185 Original DQ_B0 (3 6) =30, OEN = 27
7935 12:14:30.454459 Original DQ_B1 (3 6) =30, OEN = 27
7936 12:14:30.458007 24, 0x0, End_B0=24 End_B1=24
7937 12:14:30.458096 25, 0x0, End_B0=25 End_B1=25
7938 12:14:30.461111 26, 0x0, End_B0=26 End_B1=26
7939 12:14:30.464316 27, 0x0, End_B0=27 End_B1=27
7940 12:14:30.467967 28, 0x0, End_B0=28 End_B1=28
7941 12:14:30.471023 29, 0x0, End_B0=29 End_B1=29
7942 12:14:30.471140 30, 0x0, End_B0=30 End_B1=30
7943 12:14:30.474471 31, 0x4141, End_B0=30 End_B1=30
7944 12:14:30.477442 Byte0 end_step=30 best_step=27
7945 12:14:30.480942 Byte1 end_step=30 best_step=27
7946 12:14:30.484318 Byte0 TX OE(2T, 0.5T) = (3, 3)
7947 12:14:30.487341 Byte1 TX OE(2T, 0.5T) = (3, 3)
7948 12:14:30.487455
7949 12:14:30.487549
7950 12:14:30.494012 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7951 12:14:30.497478 CH0 RK0: MR19=303, MR18=1F1E
7952 12:14:30.503837 CH0_RK0: MR19=0x303, MR18=0x1F1E, DQSOSC=394, MR23=63, INC=23, DEC=15
7953 12:14:30.503940
7954 12:14:30.507228 ----->DramcWriteLeveling(PI) begin...
7955 12:14:30.507307 ==
7956 12:14:30.510605 Dram Type= 6, Freq= 0, CH_0, rank 1
7957 12:14:30.513813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 12:14:30.513915 ==
7959 12:14:30.517528 Write leveling (Byte 0): 38 => 38
7960 12:14:30.520525 Write leveling (Byte 1): 30 => 30
7961 12:14:30.524003 DramcWriteLeveling(PI) end<-----
7962 12:14:30.524076
7963 12:14:30.524146 ==
7964 12:14:30.527213 Dram Type= 6, Freq= 0, CH_0, rank 1
7965 12:14:30.530349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7966 12:14:30.534036 ==
7967 12:14:30.534109 [Gating] SW mode calibration
7968 12:14:30.540500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7969 12:14:30.547251 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7970 12:14:30.550441 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 12:14:30.557031 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 12:14:30.559938 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 12:14:30.563518 1 4 12 | B1->B0 | 2323 2a2a | 1 1 | (0 0) (1 1)
7974 12:14:30.569918 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7975 12:14:30.573536 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7976 12:14:30.576572 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7977 12:14:30.583273 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7978 12:14:30.586368 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7979 12:14:30.589774 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7980 12:14:30.596639 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7981 12:14:30.599738 1 5 12 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (1 0)
7982 12:14:30.603213 1 5 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7983 12:14:30.609832 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 12:14:30.613274 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 12:14:30.616498 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 12:14:30.623096 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 12:14:30.626135 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 12:14:30.629606 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7989 12:14:30.636361 1 6 12 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
7990 12:14:30.639494 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 12:14:30.642991 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 12:14:30.649216 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 12:14:30.652721 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 12:14:30.655816 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 12:14:30.662856 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 12:14:30.665784 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 12:14:30.669093 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7998 12:14:30.675767 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7999 12:14:30.679358 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 12:14:30.682431 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 12:14:30.689055 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 12:14:30.692469 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 12:14:30.695437 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 12:14:30.702102 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 12:14:30.705807 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 12:14:30.708878 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 12:14:30.715498 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 12:14:30.718910 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 12:14:30.722231 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:14:30.728406 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 12:14:30.731782 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 12:14:30.735257 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 12:14:30.741969 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8014 12:14:30.745038 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8015 12:14:30.748527 Total UI for P1: 0, mck2ui 16
8016 12:14:30.751648 best dqsien dly found for B0: ( 1, 9, 12)
8017 12:14:30.755224 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 12:14:30.758193 Total UI for P1: 0, mck2ui 16
8019 12:14:30.761381 best dqsien dly found for B1: ( 1, 9, 14)
8020 12:14:30.764925 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8021 12:14:30.768350 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8022 12:14:30.768433
8023 12:14:30.775008 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8024 12:14:30.778083 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8025 12:14:30.778166 [Gating] SW calibration Done
8026 12:14:30.781221 ==
8027 12:14:30.784754 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 12:14:30.788152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 12:14:30.788277 ==
8030 12:14:30.788341 RX Vref Scan: 0
8031 12:14:30.788402
8032 12:14:30.791359 RX Vref 0 -> 0, step: 1
8033 12:14:30.791442
8034 12:14:30.794511 RX Delay 0 -> 252, step: 8
8035 12:14:30.797975 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8036 12:14:30.801561 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8037 12:14:30.804654 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8038 12:14:30.811271 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8039 12:14:30.814408 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8040 12:14:30.817548 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8041 12:14:30.821079 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8042 12:14:30.824122 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8043 12:14:30.831086 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8044 12:14:30.834431 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8045 12:14:30.837767 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8046 12:14:30.841136 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8047 12:14:30.847248 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8048 12:14:30.850990 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8049 12:14:30.853987 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8050 12:14:30.857499 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8051 12:14:30.857610 ==
8052 12:14:30.860485 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 12:14:30.867296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 12:14:30.867377 ==
8055 12:14:30.867474 DQS Delay:
8056 12:14:30.870744 DQS0 = 0, DQS1 = 0
8057 12:14:30.870841 DQM Delay:
8058 12:14:30.870935 DQM0 = 136, DQM1 = 125
8059 12:14:30.873783 DQ Delay:
8060 12:14:30.877374 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8061 12:14:30.880349 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8062 12:14:30.883970 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8063 12:14:30.887011 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8064 12:14:30.887112
8065 12:14:30.887202
8066 12:14:30.887302 ==
8067 12:14:30.890464 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 12:14:30.893426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 12:14:30.897084 ==
8070 12:14:30.897162
8071 12:14:30.897272
8072 12:14:30.897362 TX Vref Scan disable
8073 12:14:30.900149 == TX Byte 0 ==
8074 12:14:30.903637 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8075 12:14:30.906702 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8076 12:14:30.910238 == TX Byte 1 ==
8077 12:14:30.913361 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8078 12:14:30.919774 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8079 12:14:30.919851 ==
8080 12:14:30.923412 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 12:14:30.926461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 12:14:30.926544 ==
8083 12:14:30.941210
8084 12:14:30.944499 TX Vref early break, caculate TX vref
8085 12:14:30.947811 TX Vref=16, minBit 8, minWin=23, winSum=389
8086 12:14:30.950811 TX Vref=18, minBit 12, minWin=23, winSum=398
8087 12:14:30.954320 TX Vref=20, minBit 8, minWin=24, winSum=406
8088 12:14:30.957400 TX Vref=22, minBit 8, minWin=24, winSum=414
8089 12:14:30.960894 TX Vref=24, minBit 0, minWin=25, winSum=426
8090 12:14:30.967584 TX Vref=26, minBit 0, minWin=26, winSum=430
8091 12:14:30.971140 TX Vref=28, minBit 1, minWin=26, winSum=432
8092 12:14:30.974182 TX Vref=30, minBit 2, minWin=26, winSum=426
8093 12:14:30.977662 TX Vref=32, minBit 0, minWin=25, winSum=421
8094 12:14:30.980755 TX Vref=34, minBit 0, minWin=25, winSum=414
8095 12:14:30.987473 TX Vref=36, minBit 2, minWin=24, winSum=401
8096 12:14:30.990373 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 28
8097 12:14:30.990483
8098 12:14:30.994023 Final TX Range 0 Vref 28
8099 12:14:30.994109
8100 12:14:30.994175 ==
8101 12:14:30.997080 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 12:14:31.000617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 12:14:31.000724 ==
8104 12:14:31.003738
8105 12:14:31.003839
8106 12:14:31.003944 TX Vref Scan disable
8107 12:14:31.010366 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8108 12:14:31.010450 == TX Byte 0 ==
8109 12:14:31.013949 u2DelayCellOfst[0]=13 cells (4 PI)
8110 12:14:31.017029 u2DelayCellOfst[1]=20 cells (6 PI)
8111 12:14:31.020491 u2DelayCellOfst[2]=13 cells (4 PI)
8112 12:14:31.024071 u2DelayCellOfst[3]=13 cells (4 PI)
8113 12:14:31.027132 u2DelayCellOfst[4]=10 cells (3 PI)
8114 12:14:31.030255 u2DelayCellOfst[5]=0 cells (0 PI)
8115 12:14:31.033849 u2DelayCellOfst[6]=20 cells (6 PI)
8116 12:14:31.037321 u2DelayCellOfst[7]=20 cells (6 PI)
8117 12:14:31.040406 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8118 12:14:31.043797 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8119 12:14:31.047105 == TX Byte 1 ==
8120 12:14:31.050366 u2DelayCellOfst[8]=3 cells (1 PI)
8121 12:14:31.053650 u2DelayCellOfst[9]=0 cells (0 PI)
8122 12:14:31.056813 u2DelayCellOfst[10]=6 cells (2 PI)
8123 12:14:31.060285 u2DelayCellOfst[11]=3 cells (1 PI)
8124 12:14:31.063258 u2DelayCellOfst[12]=13 cells (4 PI)
8125 12:14:31.066722 u2DelayCellOfst[13]=13 cells (4 PI)
8126 12:14:31.069869 u2DelayCellOfst[14]=13 cells (4 PI)
8127 12:14:31.069948 u2DelayCellOfst[15]=10 cells (3 PI)
8128 12:14:31.076588 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8129 12:14:31.079557 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8130 12:14:31.083193 DramC Write-DBI on
8131 12:14:31.083274 ==
8132 12:14:31.086291 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 12:14:31.089495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 12:14:31.089596 ==
8135 12:14:31.089684
8136 12:14:31.089771
8137 12:14:31.093152 TX Vref Scan disable
8138 12:14:31.093295 == TX Byte 0 ==
8139 12:14:31.099760 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8140 12:14:31.099938 == TX Byte 1 ==
8141 12:14:31.102713 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8142 12:14:31.106328 DramC Write-DBI off
8143 12:14:31.106428
8144 12:14:31.106521 [DATLAT]
8145 12:14:31.109731 Freq=1600, CH0 RK1
8146 12:14:31.109829
8147 12:14:31.109920 DATLAT Default: 0xf
8148 12:14:31.112685 0, 0xFFFF, sum = 0
8149 12:14:31.116381 1, 0xFFFF, sum = 0
8150 12:14:31.116497 2, 0xFFFF, sum = 0
8151 12:14:31.119574 3, 0xFFFF, sum = 0
8152 12:14:31.119732 4, 0xFFFF, sum = 0
8153 12:14:31.123072 5, 0xFFFF, sum = 0
8154 12:14:31.123180 6, 0xFFFF, sum = 0
8155 12:14:31.125900 7, 0xFFFF, sum = 0
8156 12:14:31.126045 8, 0xFFFF, sum = 0
8157 12:14:31.129670 9, 0xFFFF, sum = 0
8158 12:14:31.129797 10, 0xFFFF, sum = 0
8159 12:14:31.132739 11, 0xFFFF, sum = 0
8160 12:14:31.132856 12, 0xFFFF, sum = 0
8161 12:14:31.136418 13, 0xFFFF, sum = 0
8162 12:14:31.136608 14, 0x0, sum = 1
8163 12:14:31.139433 15, 0x0, sum = 2
8164 12:14:31.139561 16, 0x0, sum = 3
8165 12:14:31.142921 17, 0x0, sum = 4
8166 12:14:31.143029 best_step = 15
8167 12:14:31.143126
8168 12:14:31.143219 ==
8169 12:14:31.146167 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 12:14:31.152635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 12:14:31.152876 ==
8172 12:14:31.153040 RX Vref Scan: 0
8173 12:14:31.153149
8174 12:14:31.155967 RX Vref 0 -> 0, step: 1
8175 12:14:31.156100
8176 12:14:31.159331 RX Delay 11 -> 252, step: 4
8177 12:14:31.162465 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8178 12:14:31.165750 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8179 12:14:31.168876 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8180 12:14:31.175289 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8181 12:14:31.178850 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8182 12:14:31.182067 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8183 12:14:31.185459 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8184 12:14:31.189042 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8185 12:14:31.195183 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8186 12:14:31.198710 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8187 12:14:31.201830 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8188 12:14:31.205339 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8189 12:14:31.211877 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8190 12:14:31.215401 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8191 12:14:31.218401 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8192 12:14:31.221512 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8193 12:14:31.221583 ==
8194 12:14:31.225352 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 12:14:31.231756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 12:14:31.231843 ==
8197 12:14:31.231910 DQS Delay:
8198 12:14:31.234783 DQS0 = 0, DQS1 = 0
8199 12:14:31.234859 DQM Delay:
8200 12:14:31.234923 DQM0 = 133, DQM1 = 123
8201 12:14:31.237855 DQ Delay:
8202 12:14:31.241482 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8203 12:14:31.244994 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8204 12:14:31.247978 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8205 12:14:31.251130 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8206 12:14:31.251215
8207 12:14:31.251281
8208 12:14:31.251342
8209 12:14:31.254605 [DramC_TX_OE_Calibration] TA2
8210 12:14:31.258078 Original DQ_B0 (3 6) =30, OEN = 27
8211 12:14:31.261214 Original DQ_B1 (3 6) =30, OEN = 27
8212 12:14:31.264569 24, 0x0, End_B0=24 End_B1=24
8213 12:14:31.264655 25, 0x0, End_B0=25 End_B1=25
8214 12:14:31.267784 26, 0x0, End_B0=26 End_B1=26
8215 12:14:31.271185 27, 0x0, End_B0=27 End_B1=27
8216 12:14:31.274434 28, 0x0, End_B0=28 End_B1=28
8217 12:14:31.277778 29, 0x0, End_B0=29 End_B1=29
8218 12:14:31.277853 30, 0x0, End_B0=30 End_B1=30
8219 12:14:31.281115 31, 0x4141, End_B0=30 End_B1=30
8220 12:14:31.284180 Byte0 end_step=30 best_step=27
8221 12:14:31.287549 Byte1 end_step=30 best_step=27
8222 12:14:31.291018 Byte0 TX OE(2T, 0.5T) = (3, 3)
8223 12:14:31.294250 Byte1 TX OE(2T, 0.5T) = (3, 3)
8224 12:14:31.294323
8225 12:14:31.294387
8226 12:14:31.301081 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8227 12:14:31.304041 CH0 RK1: MR19=303, MR18=1F0C
8228 12:14:31.310805 CH0_RK1: MR19=0x303, MR18=0x1F0C, DQSOSC=394, MR23=63, INC=23, DEC=15
8229 12:14:31.313764 [RxdqsGatingPostProcess] freq 1600
8230 12:14:31.320250 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8231 12:14:31.320360 best DQS0 dly(2T, 0.5T) = (1, 1)
8232 12:14:31.323786 best DQS1 dly(2T, 0.5T) = (1, 1)
8233 12:14:31.327044 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8234 12:14:31.330243 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8235 12:14:31.333713 best DQS0 dly(2T, 0.5T) = (1, 1)
8236 12:14:31.336693 best DQS1 dly(2T, 0.5T) = (1, 1)
8237 12:14:31.340291 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8238 12:14:31.343369 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8239 12:14:31.346865 Pre-setting of DQS Precalculation
8240 12:14:31.350345 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8241 12:14:31.350428 ==
8242 12:14:31.353452 Dram Type= 6, Freq= 0, CH_1, rank 0
8243 12:14:31.359852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 12:14:31.359941 ==
8245 12:14:31.363511 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8246 12:14:31.369773 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8247 12:14:31.373179 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8248 12:14:31.379669 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8249 12:14:31.387760 [CA 0] Center 40 (11~70) winsize 60
8250 12:14:31.391182 [CA 1] Center 41 (11~71) winsize 61
8251 12:14:31.394537 [CA 2] Center 36 (7~66) winsize 60
8252 12:14:31.397682 [CA 3] Center 36 (7~66) winsize 60
8253 12:14:31.401281 [CA 4] Center 36 (6~67) winsize 62
8254 12:14:31.404329 [CA 5] Center 36 (6~66) winsize 61
8255 12:14:31.404411
8256 12:14:31.408083 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8257 12:14:31.408166
8258 12:14:31.411225 [CATrainingPosCal] consider 1 rank data
8259 12:14:31.414234 u2DelayCellTimex100 = 290/100 ps
8260 12:14:31.417905 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8261 12:14:31.424449 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8262 12:14:31.427700 CA2 delay=36 (7~66),Diff = 0 PI (0 cell)
8263 12:14:31.430808 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8264 12:14:31.433905 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
8265 12:14:31.437556 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8266 12:14:31.437638
8267 12:14:31.440680 CA PerBit enable=1, Macro0, CA PI delay=36
8268 12:14:31.440786
8269 12:14:31.444391 [CBTSetCACLKResult] CA Dly = 36
8270 12:14:31.447509 CS Dly: 8 (0~39)
8271 12:14:31.450983 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8272 12:14:31.454040 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8273 12:14:31.454150 ==
8274 12:14:31.457598 Dram Type= 6, Freq= 0, CH_1, rank 1
8275 12:14:31.460677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 12:14:31.464216 ==
8277 12:14:31.467250 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8278 12:14:31.470914 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8279 12:14:31.477615 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8280 12:14:31.480496 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8281 12:14:31.490773 [CA 0] Center 42 (12~72) winsize 61
8282 12:14:31.493814 [CA 1] Center 41 (11~71) winsize 61
8283 12:14:31.497289 [CA 2] Center 37 (8~67) winsize 60
8284 12:14:31.500600 [CA 3] Center 37 (8~66) winsize 59
8285 12:14:31.504083 [CA 4] Center 37 (8~66) winsize 59
8286 12:14:31.507275 [CA 5] Center 36 (7~66) winsize 60
8287 12:14:31.507352
8288 12:14:31.510246 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8289 12:14:31.510321
8290 12:14:31.513809 [CATrainingPosCal] consider 2 rank data
8291 12:14:31.517254 u2DelayCellTimex100 = 290/100 ps
8292 12:14:31.524052 CA0 delay=41 (12~70),Diff = 5 PI (16 cell)
8293 12:14:31.526861 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8294 12:14:31.530429 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8295 12:14:31.533611 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8296 12:14:31.537218 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8297 12:14:31.540265 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8298 12:14:31.540336
8299 12:14:31.543656 CA PerBit enable=1, Macro0, CA PI delay=36
8300 12:14:31.543740
8301 12:14:31.546855 [CBTSetCACLKResult] CA Dly = 36
8302 12:14:31.550391 CS Dly: 10 (0~43)
8303 12:14:31.553476 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8304 12:14:31.556475 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8305 12:14:31.556557
8306 12:14:31.560028 ----->DramcWriteLeveling(PI) begin...
8307 12:14:31.560109 ==
8308 12:14:31.563014 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 12:14:31.569939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 12:14:31.570026 ==
8311 12:14:31.573060 Write leveling (Byte 0): 25 => 25
8312 12:14:31.576221 Write leveling (Byte 1): 30 => 30
8313 12:14:31.579809 DramcWriteLeveling(PI) end<-----
8314 12:14:31.579879
8315 12:14:31.579939 ==
8316 12:14:31.582906 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 12:14:31.586544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 12:14:31.586618 ==
8319 12:14:31.589676 [Gating] SW mode calibration
8320 12:14:31.596441 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8321 12:14:31.599745 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8322 12:14:31.606522 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 12:14:31.609311 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 12:14:31.613043 1 4 8 | B1->B0 | 2424 2d2d | 0 1 | (0 0) (1 1)
8325 12:14:31.619452 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 12:14:31.622544 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 12:14:31.626257 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 12:14:31.632695 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 12:14:31.635859 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 12:14:31.639491 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 12:14:31.645546 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8332 12:14:31.649237 1 5 8 | B1->B0 | 3333 2e2e | 1 1 | (1 0) (1 0)
8333 12:14:31.652344 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 12:14:31.659338 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 12:14:31.662755 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 12:14:31.665771 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 12:14:31.672508 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 12:14:31.675828 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 12:14:31.679274 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8340 12:14:31.685829 1 6 8 | B1->B0 | 3131 4444 | 0 1 | (0 0) (0 0)
8341 12:14:31.688885 1 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8342 12:14:31.692632 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 12:14:31.698823 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 12:14:31.702105 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 12:14:31.705384 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 12:14:31.712156 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 12:14:31.715638 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8348 12:14:31.718712 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8349 12:14:31.725623 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8350 12:14:31.728583 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8351 12:14:31.731637 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 12:14:31.738349 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 12:14:31.741903 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 12:14:31.745112 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 12:14:31.751652 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 12:14:31.755107 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 12:14:31.758232 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 12:14:31.764832 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 12:14:31.768324 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 12:14:31.771404 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 12:14:31.777804 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 12:14:31.781398 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 12:14:31.784464 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8364 12:14:31.790811 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8365 12:14:31.794505 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8366 12:14:31.797453 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 12:14:31.800965 Total UI for P1: 0, mck2ui 16
8368 12:14:31.804055 best dqsien dly found for B0: ( 1, 9, 8)
8369 12:14:31.807134 Total UI for P1: 0, mck2ui 16
8370 12:14:31.810436 best dqsien dly found for B1: ( 1, 9, 10)
8371 12:14:31.816656 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8372 12:14:31.820124 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8373 12:14:31.820215
8374 12:14:31.823310 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8375 12:14:31.826962 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8376 12:14:31.830338 [Gating] SW calibration Done
8377 12:14:31.830417 ==
8378 12:14:31.833427 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 12:14:31.836424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 12:14:31.836513 ==
8381 12:14:31.839833 RX Vref Scan: 0
8382 12:14:31.839905
8383 12:14:31.839966 RX Vref 0 -> 0, step: 1
8384 12:14:31.840024
8385 12:14:31.843041 RX Delay 0 -> 252, step: 8
8386 12:14:31.846501 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8387 12:14:31.853336 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8388 12:14:31.856404 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8389 12:14:31.859587 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8390 12:14:31.862998 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8391 12:14:31.866559 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8392 12:14:31.869481 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8393 12:14:31.876277 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8394 12:14:31.879378 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8395 12:14:31.882813 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8396 12:14:31.886012 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8397 12:14:31.889519 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8398 12:14:31.896110 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8399 12:14:31.899564 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8400 12:14:31.902657 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8401 12:14:31.905824 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8402 12:14:31.905911 ==
8403 12:14:31.909358 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 12:14:31.915885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 12:14:31.915970 ==
8406 12:14:31.916034 DQS Delay:
8407 12:14:31.919214 DQS0 = 0, DQS1 = 0
8408 12:14:31.919312 DQM Delay:
8409 12:14:31.922646 DQM0 = 139, DQM1 = 131
8410 12:14:31.922746 DQ Delay:
8411 12:14:31.925592 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8412 12:14:31.928916 DQ4 =139, DQ5 =151, DQ6 =147, DQ7 =135
8413 12:14:31.932181 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8414 12:14:31.935396 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8415 12:14:31.935507
8416 12:14:31.935602
8417 12:14:31.935689 ==
8418 12:14:31.939018 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 12:14:31.945642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 12:14:31.945717 ==
8421 12:14:31.945780
8422 12:14:31.945854
8423 12:14:31.945910 TX Vref Scan disable
8424 12:14:31.949170 == TX Byte 0 ==
8425 12:14:31.952219 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8426 12:14:31.958797 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8427 12:14:31.958880 == TX Byte 1 ==
8428 12:14:31.961953 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8429 12:14:31.968675 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8430 12:14:31.968783 ==
8431 12:14:31.972147 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 12:14:31.975115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 12:14:31.975187 ==
8434 12:14:31.988958
8435 12:14:31.992539 TX Vref early break, caculate TX vref
8436 12:14:31.995614 TX Vref=16, minBit 15, minWin=21, winSum=368
8437 12:14:31.999239 TX Vref=18, minBit 9, minWin=22, winSum=377
8438 12:14:32.002303 TX Vref=20, minBit 15, minWin=22, winSum=386
8439 12:14:32.005245 TX Vref=22, minBit 9, minWin=23, winSum=400
8440 12:14:32.012296 TX Vref=24, minBit 15, minWin=23, winSum=406
8441 12:14:32.015412 TX Vref=26, minBit 9, minWin=25, winSum=419
8442 12:14:32.018465 TX Vref=28, minBit 10, minWin=25, winSum=423
8443 12:14:32.021927 TX Vref=30, minBit 10, minWin=24, winSum=415
8444 12:14:32.025481 TX Vref=32, minBit 10, minWin=23, winSum=408
8445 12:14:32.031986 TX Vref=34, minBit 10, minWin=23, winSum=401
8446 12:14:32.035362 TX Vref=36, minBit 10, minWin=22, winSum=386
8447 12:14:32.041608 [TxChooseVref] Worse bit 10, Min win 25, Win sum 423, Final Vref 28
8448 12:14:32.041688
8449 12:14:32.041759 Final TX Range 0 Vref 28
8450 12:14:32.041820
8451 12:14:32.041885 ==
8452 12:14:32.045348 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 12:14:32.051729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 12:14:32.051812 ==
8455 12:14:32.051877
8456 12:14:32.051949
8457 12:14:32.052009 TX Vref Scan disable
8458 12:14:32.058923 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8459 12:14:32.059016 == TX Byte 0 ==
8460 12:14:32.062348 u2DelayCellOfst[0]=13 cells (4 PI)
8461 12:14:32.065968 u2DelayCellOfst[1]=10 cells (3 PI)
8462 12:14:32.068979 u2DelayCellOfst[2]=0 cells (0 PI)
8463 12:14:32.072020 u2DelayCellOfst[3]=6 cells (2 PI)
8464 12:14:32.075661 u2DelayCellOfst[4]=6 cells (2 PI)
8465 12:14:32.078576 u2DelayCellOfst[5]=16 cells (5 PI)
8466 12:14:32.081756 u2DelayCellOfst[6]=16 cells (5 PI)
8467 12:14:32.085266 u2DelayCellOfst[7]=3 cells (1 PI)
8468 12:14:32.088305 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8469 12:14:32.091840 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8470 12:14:32.095381 == TX Byte 1 ==
8471 12:14:32.098428 u2DelayCellOfst[8]=0 cells (0 PI)
8472 12:14:32.101645 u2DelayCellOfst[9]=3 cells (1 PI)
8473 12:14:32.104802 u2DelayCellOfst[10]=10 cells (3 PI)
8474 12:14:32.108149 u2DelayCellOfst[11]=3 cells (1 PI)
8475 12:14:32.111700 u2DelayCellOfst[12]=16 cells (5 PI)
8476 12:14:32.114798 u2DelayCellOfst[13]=13 cells (4 PI)
8477 12:14:32.118313 u2DelayCellOfst[14]=16 cells (5 PI)
8478 12:14:32.118385 u2DelayCellOfst[15]=13 cells (4 PI)
8479 12:14:32.124973 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8480 12:14:32.128118 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8481 12:14:32.131232 DramC Write-DBI on
8482 12:14:32.131306 ==
8483 12:14:32.134752 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 12:14:32.138142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 12:14:32.138218 ==
8486 12:14:32.138289
8487 12:14:32.138364
8488 12:14:32.141495 TX Vref Scan disable
8489 12:14:32.141564 == TX Byte 0 ==
8490 12:14:32.147663 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8491 12:14:32.147754 == TX Byte 1 ==
8492 12:14:32.154222 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8493 12:14:32.154298 DramC Write-DBI off
8494 12:14:32.154361
8495 12:14:32.154419 [DATLAT]
8496 12:14:32.157783 Freq=1600, CH1 RK0
8497 12:14:32.157859
8498 12:14:32.160974 DATLAT Default: 0xf
8499 12:14:32.161052 0, 0xFFFF, sum = 0
8500 12:14:32.164564 1, 0xFFFF, sum = 0
8501 12:14:32.164638 2, 0xFFFF, sum = 0
8502 12:14:32.167631 3, 0xFFFF, sum = 0
8503 12:14:32.167705 4, 0xFFFF, sum = 0
8504 12:14:32.170750 5, 0xFFFF, sum = 0
8505 12:14:32.170822 6, 0xFFFF, sum = 0
8506 12:14:32.174325 7, 0xFFFF, sum = 0
8507 12:14:32.174406 8, 0xFFFF, sum = 0
8508 12:14:32.177346 9, 0xFFFF, sum = 0
8509 12:14:32.177418 10, 0xFFFF, sum = 0
8510 12:14:32.180662 11, 0xFFFF, sum = 0
8511 12:14:32.180772 12, 0xFFFF, sum = 0
8512 12:14:32.183753 13, 0xFFFF, sum = 0
8513 12:14:32.183869 14, 0x0, sum = 1
8514 12:14:32.187299 15, 0x0, sum = 2
8515 12:14:32.187370 16, 0x0, sum = 3
8516 12:14:32.190849 17, 0x0, sum = 4
8517 12:14:32.190919 best_step = 15
8518 12:14:32.190989
8519 12:14:32.191059 ==
8520 12:14:32.193851 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 12:14:32.200379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 12:14:32.200452 ==
8523 12:14:32.200513 RX Vref Scan: 1
8524 12:14:32.200579
8525 12:14:32.203999 Set Vref Range= 24 -> 127
8526 12:14:32.204067
8527 12:14:32.207141 RX Vref 24 -> 127, step: 1
8528 12:14:32.207209
8529 12:14:32.210599 RX Delay 19 -> 252, step: 4
8530 12:14:32.210672
8531 12:14:32.210752 Set Vref, RX VrefLevel [Byte0]: 24
8532 12:14:32.214084 [Byte1]: 24
8533 12:14:32.218039
8534 12:14:32.218120 Set Vref, RX VrefLevel [Byte0]: 25
8535 12:14:32.221614 [Byte1]: 25
8536 12:14:32.225727
8537 12:14:32.225801 Set Vref, RX VrefLevel [Byte0]: 26
8538 12:14:32.229135 [Byte1]: 26
8539 12:14:32.233313
8540 12:14:32.233388 Set Vref, RX VrefLevel [Byte0]: 27
8541 12:14:32.236436 [Byte1]: 27
8542 12:14:32.240977
8543 12:14:32.241059 Set Vref, RX VrefLevel [Byte0]: 28
8544 12:14:32.244044 [Byte1]: 28
8545 12:14:32.248294
8546 12:14:32.248367 Set Vref, RX VrefLevel [Byte0]: 29
8547 12:14:32.251640 [Byte1]: 29
8548 12:14:32.255807
8549 12:14:32.255885 Set Vref, RX VrefLevel [Byte0]: 30
8550 12:14:32.259234 [Byte1]: 30
8551 12:14:32.263825
8552 12:14:32.263900 Set Vref, RX VrefLevel [Byte0]: 31
8553 12:14:32.267035 [Byte1]: 31
8554 12:14:32.270954
8555 12:14:32.271030 Set Vref, RX VrefLevel [Byte0]: 32
8556 12:14:32.274530 [Byte1]: 32
8557 12:14:32.278734
8558 12:14:32.278808 Set Vref, RX VrefLevel [Byte0]: 33
8559 12:14:32.281800 [Byte1]: 33
8560 12:14:32.286382
8561 12:14:32.286468 Set Vref, RX VrefLevel [Byte0]: 34
8562 12:14:32.289459 [Byte1]: 34
8563 12:14:32.294011
8564 12:14:32.294090 Set Vref, RX VrefLevel [Byte0]: 35
8565 12:14:32.296994 [Byte1]: 35
8566 12:14:32.301361
8567 12:14:32.301436 Set Vref, RX VrefLevel [Byte0]: 36
8568 12:14:32.304474 [Byte1]: 36
8569 12:14:32.309100
8570 12:14:32.309174 Set Vref, RX VrefLevel [Byte0]: 37
8571 12:14:32.312241 [Byte1]: 37
8572 12:14:32.316881
8573 12:14:32.316962 Set Vref, RX VrefLevel [Byte0]: 38
8574 12:14:32.319786 [Byte1]: 38
8575 12:14:32.323852
8576 12:14:32.323935 Set Vref, RX VrefLevel [Byte0]: 39
8577 12:14:32.327500 [Byte1]: 39
8578 12:14:32.331504
8579 12:14:32.331585 Set Vref, RX VrefLevel [Byte0]: 40
8580 12:14:32.334983 [Byte1]: 40
8581 12:14:32.339243
8582 12:14:32.339324 Set Vref, RX VrefLevel [Byte0]: 41
8583 12:14:32.342322 [Byte1]: 41
8584 12:14:32.346875
8585 12:14:32.346955 Set Vref, RX VrefLevel [Byte0]: 42
8586 12:14:32.350298 [Byte1]: 42
8587 12:14:32.354544
8588 12:14:32.354626 Set Vref, RX VrefLevel [Byte0]: 43
8589 12:14:32.357890 [Byte1]: 43
8590 12:14:32.362288
8591 12:14:32.362369 Set Vref, RX VrefLevel [Byte0]: 44
8592 12:14:32.365183 [Byte1]: 44
8593 12:14:32.369375
8594 12:14:32.372816 Set Vref, RX VrefLevel [Byte0]: 45
8595 12:14:32.375850 [Byte1]: 45
8596 12:14:32.375932
8597 12:14:32.379533 Set Vref, RX VrefLevel [Byte0]: 46
8598 12:14:32.382530 [Byte1]: 46
8599 12:14:32.382612
8600 12:14:32.386046 Set Vref, RX VrefLevel [Byte0]: 47
8601 12:14:32.389054 [Byte1]: 47
8602 12:14:32.389136
8603 12:14:32.392621 Set Vref, RX VrefLevel [Byte0]: 48
8604 12:14:32.395732 [Byte1]: 48
8605 12:14:32.399794
8606 12:14:32.399875 Set Vref, RX VrefLevel [Byte0]: 49
8607 12:14:32.403150 [Byte1]: 49
8608 12:14:32.407681
8609 12:14:32.407763 Set Vref, RX VrefLevel [Byte0]: 50
8610 12:14:32.410911 [Byte1]: 50
8611 12:14:32.415080
8612 12:14:32.415162 Set Vref, RX VrefLevel [Byte0]: 51
8613 12:14:32.418158 [Byte1]: 51
8614 12:14:32.422570
8615 12:14:32.422694 Set Vref, RX VrefLevel [Byte0]: 52
8616 12:14:32.425632 [Byte1]: 52
8617 12:14:32.430244
8618 12:14:32.430348 Set Vref, RX VrefLevel [Byte0]: 53
8619 12:14:32.433404 [Byte1]: 53
8620 12:14:32.437851
8621 12:14:32.437956 Set Vref, RX VrefLevel [Byte0]: 54
8622 12:14:32.440959 [Byte1]: 54
8623 12:14:32.445128
8624 12:14:32.445237 Set Vref, RX VrefLevel [Byte0]: 55
8625 12:14:32.448705 [Byte1]: 55
8626 12:14:32.452878
8627 12:14:32.452984 Set Vref, RX VrefLevel [Byte0]: 56
8628 12:14:32.456312 [Byte1]: 56
8629 12:14:32.460536
8630 12:14:32.460647 Set Vref, RX VrefLevel [Byte0]: 57
8631 12:14:32.463821 [Byte1]: 57
8632 12:14:32.468187
8633 12:14:32.468296 Set Vref, RX VrefLevel [Byte0]: 58
8634 12:14:32.471139 [Byte1]: 58
8635 12:14:32.475826
8636 12:14:32.475934 Set Vref, RX VrefLevel [Byte0]: 59
8637 12:14:32.478854 [Byte1]: 59
8638 12:14:32.483084
8639 12:14:32.483192 Set Vref, RX VrefLevel [Byte0]: 60
8640 12:14:32.486194 [Byte1]: 60
8641 12:14:32.490709
8642 12:14:32.490821 Set Vref, RX VrefLevel [Byte0]: 61
8643 12:14:32.494198 [Byte1]: 61
8644 12:14:32.498278
8645 12:14:32.498360 Set Vref, RX VrefLevel [Byte0]: 62
8646 12:14:32.504959 [Byte1]: 62
8647 12:14:32.505042
8648 12:14:32.507945 Set Vref, RX VrefLevel [Byte0]: 63
8649 12:14:32.511465 [Byte1]: 63
8650 12:14:32.511575
8651 12:14:32.514442 Set Vref, RX VrefLevel [Byte0]: 64
8652 12:14:32.518133 [Byte1]: 64
8653 12:14:32.518241
8654 12:14:32.521099 Set Vref, RX VrefLevel [Byte0]: 65
8655 12:14:32.524585 [Byte1]: 65
8656 12:14:32.528718
8657 12:14:32.528857 Set Vref, RX VrefLevel [Byte0]: 66
8658 12:14:32.531915 [Byte1]: 66
8659 12:14:32.536045
8660 12:14:32.536121 Set Vref, RX VrefLevel [Byte0]: 67
8661 12:14:32.539540 [Byte1]: 67
8662 12:14:32.543594
8663 12:14:32.543695 Set Vref, RX VrefLevel [Byte0]: 68
8664 12:14:32.546796 [Byte1]: 68
8665 12:14:32.551460
8666 12:14:32.551562 Set Vref, RX VrefLevel [Byte0]: 69
8667 12:14:32.554512 [Byte1]: 69
8668 12:14:32.559035
8669 12:14:32.559137 Set Vref, RX VrefLevel [Byte0]: 70
8670 12:14:32.561912 [Byte1]: 70
8671 12:14:32.566177
8672 12:14:32.566290 Set Vref, RX VrefLevel [Byte0]: 71
8673 12:14:32.569942 [Byte1]: 71
8674 12:14:32.573743
8675 12:14:32.573842 Set Vref, RX VrefLevel [Byte0]: 72
8676 12:14:32.576996 [Byte1]: 72
8677 12:14:32.581612
8678 12:14:32.581713 Set Vref, RX VrefLevel [Byte0]: 73
8679 12:14:32.584674 [Byte1]: 73
8680 12:14:32.588974
8681 12:14:32.589047 Set Vref, RX VrefLevel [Byte0]: 74
8682 12:14:32.592601 [Byte1]: 74
8683 12:14:32.596639
8684 12:14:32.596738 Final RX Vref Byte 0 = 59 to rank0
8685 12:14:32.600184 Final RX Vref Byte 1 = 63 to rank0
8686 12:14:32.603356 Final RX Vref Byte 0 = 59 to rank1
8687 12:14:32.606908 Final RX Vref Byte 1 = 63 to rank1==
8688 12:14:32.609735 Dram Type= 6, Freq= 0, CH_1, rank 0
8689 12:14:32.616684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8690 12:14:32.616818 ==
8691 12:14:32.616913 DQS Delay:
8692 12:14:32.619763 DQS0 = 0, DQS1 = 0
8693 12:14:32.619859 DQM Delay:
8694 12:14:32.619948 DQM0 = 135, DQM1 = 128
8695 12:14:32.623385 DQ Delay:
8696 12:14:32.626511 DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =132
8697 12:14:32.630004 DQ4 =134, DQ5 =146, DQ6 =148, DQ7 =132
8698 12:14:32.633094 DQ8 =114, DQ9 =118, DQ10 =132, DQ11 =122
8699 12:14:32.636538 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =134
8700 12:14:32.636637
8701 12:14:32.636730
8702 12:14:32.636839
8703 12:14:32.639677 [DramC_TX_OE_Calibration] TA2
8704 12:14:32.643302 Original DQ_B0 (3 6) =30, OEN = 27
8705 12:14:32.646185 Original DQ_B1 (3 6) =30, OEN = 27
8706 12:14:32.649784 24, 0x0, End_B0=24 End_B1=24
8707 12:14:32.649885 25, 0x0, End_B0=25 End_B1=25
8708 12:14:32.652874 26, 0x0, End_B0=26 End_B1=26
8709 12:14:32.656454 27, 0x0, End_B0=27 End_B1=27
8710 12:14:32.659524 28, 0x0, End_B0=28 End_B1=28
8711 12:14:32.663012 29, 0x0, End_B0=29 End_B1=29
8712 12:14:32.663089 30, 0x0, End_B0=30 End_B1=30
8713 12:14:32.666440 31, 0x4141, End_B0=30 End_B1=30
8714 12:14:32.669393 Byte0 end_step=30 best_step=27
8715 12:14:32.672739 Byte1 end_step=30 best_step=27
8716 12:14:32.676295 Byte0 TX OE(2T, 0.5T) = (3, 3)
8717 12:14:32.679470 Byte1 TX OE(2T, 0.5T) = (3, 3)
8718 12:14:32.679542
8719 12:14:32.679603
8720 12:14:32.685810 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8721 12:14:32.689469 CH1 RK0: MR19=303, MR18=1826
8722 12:14:32.695691 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8723 12:14:32.695767
8724 12:14:32.699297 ----->DramcWriteLeveling(PI) begin...
8725 12:14:32.699377 ==
8726 12:14:32.702306 Dram Type= 6, Freq= 0, CH_1, rank 1
8727 12:14:32.705739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8728 12:14:32.705813 ==
8729 12:14:32.708838 Write leveling (Byte 0): 25 => 25
8730 12:14:32.712529 Write leveling (Byte 1): 29 => 29
8731 12:14:32.715522 DramcWriteLeveling(PI) end<-----
8732 12:14:32.715622
8733 12:14:32.715711 ==
8734 12:14:32.718938 Dram Type= 6, Freq= 0, CH_1, rank 1
8735 12:14:32.722056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8736 12:14:32.722156 ==
8737 12:14:32.725725 [Gating] SW mode calibration
8738 12:14:32.732335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8739 12:14:32.739074 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8740 12:14:32.742290 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 12:14:32.748757 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 12:14:32.751954 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
8743 12:14:32.755431 1 4 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (0 0)
8744 12:14:32.762292 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 12:14:32.765391 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 12:14:32.768486 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 12:14:32.774897 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 12:14:32.778401 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 12:14:32.781782 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 12:14:32.788154 1 5 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 0) (1 0)
8751 12:14:32.791516 1 5 12 | B1->B0 | 2323 3030 | 0 0 | (1 0) (1 0)
8752 12:14:32.794633 1 5 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8753 12:14:32.801280 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 12:14:32.804750 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 12:14:32.807867 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 12:14:32.814612 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 12:14:32.818240 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 12:14:32.821117 1 6 8 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8759 12:14:32.827817 1 6 12 | B1->B0 | 4646 3c3c | 0 0 | (0 0) (0 0)
8760 12:14:32.830943 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 12:14:32.834564 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 12:14:32.841123 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 12:14:32.844098 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 12:14:32.847492 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 12:14:32.854190 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 12:14:32.857325 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8767 12:14:32.860960 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8768 12:14:32.867268 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 12:14:32.870772 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 12:14:32.873894 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 12:14:32.880731 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 12:14:32.884126 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 12:14:32.887337 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 12:14:32.893583 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 12:14:32.897419 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 12:14:32.900337 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 12:14:32.907038 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 12:14:32.910069 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 12:14:32.913541 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 12:14:32.920235 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 12:14:32.923280 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 12:14:32.926684 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8783 12:14:32.933388 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8784 12:14:32.936481 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 12:14:32.940151 Total UI for P1: 0, mck2ui 16
8786 12:14:32.943205 best dqsien dly found for B0: ( 1, 9, 10)
8787 12:14:32.946345 Total UI for P1: 0, mck2ui 16
8788 12:14:32.949928 best dqsien dly found for B1: ( 1, 9, 10)
8789 12:14:32.952962 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8790 12:14:32.956645 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8791 12:14:32.956715
8792 12:14:32.959493 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8793 12:14:32.963157 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8794 12:14:32.966254 [Gating] SW calibration Done
8795 12:14:32.966326 ==
8796 12:14:32.969218 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 12:14:32.975948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 12:14:32.976019 ==
8799 12:14:32.976081 RX Vref Scan: 0
8800 12:14:32.976146
8801 12:14:32.979579 RX Vref 0 -> 0, step: 1
8802 12:14:32.979646
8803 12:14:32.982657 RX Delay 0 -> 252, step: 8
8804 12:14:32.986224 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8805 12:14:32.989135 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8806 12:14:32.992347 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8807 12:14:32.995709 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8808 12:14:33.002329 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8809 12:14:33.005686 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8810 12:14:33.008913 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8811 12:14:33.012484 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8812 12:14:33.015886 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8813 12:14:33.022524 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8814 12:14:33.025524 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8815 12:14:33.028891 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8816 12:14:33.032099 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8817 12:14:33.039151 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8818 12:14:33.042300 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8819 12:14:33.045283 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8820 12:14:33.045352 ==
8821 12:14:33.048720 Dram Type= 6, Freq= 0, CH_1, rank 1
8822 12:14:33.051783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 12:14:33.051854 ==
8824 12:14:33.055486 DQS Delay:
8825 12:14:33.055553 DQS0 = 0, DQS1 = 0
8826 12:14:33.058469 DQM Delay:
8827 12:14:33.058550 DQM0 = 138, DQM1 = 131
8828 12:14:33.058609 DQ Delay:
8829 12:14:33.065345 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =139
8830 12:14:33.068364 DQ4 =139, DQ5 =151, DQ6 =143, DQ7 =135
8831 12:14:33.072051 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8832 12:14:33.075260 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8833 12:14:33.075329
8834 12:14:33.075390
8835 12:14:33.075447 ==
8836 12:14:33.078309 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 12:14:33.081433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 12:14:33.081511 ==
8839 12:14:33.081575
8840 12:14:33.081632
8841 12:14:33.085004 TX Vref Scan disable
8842 12:14:33.087996 == TX Byte 0 ==
8843 12:14:33.091395 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8844 12:14:33.094782 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8845 12:14:33.098210 == TX Byte 1 ==
8846 12:14:33.101503 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8847 12:14:33.104760 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8848 12:14:33.104864 ==
8849 12:14:33.107975 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 12:14:33.114536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 12:14:33.114612 ==
8852 12:14:33.126097
8853 12:14:33.129156 TX Vref early break, caculate TX vref
8854 12:14:33.132572 TX Vref=16, minBit 13, minWin=21, winSum=382
8855 12:14:33.136194 TX Vref=18, minBit 9, minWin=22, winSum=389
8856 12:14:33.139190 TX Vref=20, minBit 9, minWin=23, winSum=401
8857 12:14:33.142716 TX Vref=22, minBit 13, minWin=24, winSum=411
8858 12:14:33.149090 TX Vref=24, minBit 13, minWin=24, winSum=419
8859 12:14:33.152478 TX Vref=26, minBit 9, minWin=25, winSum=428
8860 12:14:33.155664 TX Vref=28, minBit 10, minWin=25, winSum=424
8861 12:14:33.159299 TX Vref=30, minBit 9, minWin=25, winSum=417
8862 12:14:33.162503 TX Vref=32, minBit 10, minWin=24, winSum=411
8863 12:14:33.165427 TX Vref=34, minBit 9, minWin=24, winSum=404
8864 12:14:33.172036 [TxChooseVref] Worse bit 9, Min win 25, Win sum 428, Final Vref 26
8865 12:14:33.172117
8866 12:14:33.175639 Final TX Range 0 Vref 26
8867 12:14:33.175721
8868 12:14:33.175785 ==
8869 12:14:33.178853 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 12:14:33.181937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 12:14:33.182019 ==
8872 12:14:33.185114
8873 12:14:33.185195
8874 12:14:33.185258 TX Vref Scan disable
8875 12:14:33.191741 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8876 12:14:33.191822 == TX Byte 0 ==
8877 12:14:33.195215 u2DelayCellOfst[0]=16 cells (5 PI)
8878 12:14:33.198182 u2DelayCellOfst[1]=13 cells (4 PI)
8879 12:14:33.201527 u2DelayCellOfst[2]=0 cells (0 PI)
8880 12:14:33.205132 u2DelayCellOfst[3]=6 cells (2 PI)
8881 12:14:33.208135 u2DelayCellOfst[4]=10 cells (3 PI)
8882 12:14:33.211481 u2DelayCellOfst[5]=20 cells (6 PI)
8883 12:14:33.214908 u2DelayCellOfst[6]=16 cells (5 PI)
8884 12:14:33.218360 u2DelayCellOfst[7]=6 cells (2 PI)
8885 12:14:33.221415 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8886 12:14:33.224946 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8887 12:14:33.228047 == TX Byte 1 ==
8888 12:14:33.231187 u2DelayCellOfst[8]=0 cells (0 PI)
8889 12:14:33.234692 u2DelayCellOfst[9]=3 cells (1 PI)
8890 12:14:33.238152 u2DelayCellOfst[10]=10 cells (3 PI)
8891 12:14:33.241202 u2DelayCellOfst[11]=3 cells (1 PI)
8892 12:14:33.244707 u2DelayCellOfst[12]=13 cells (4 PI)
8893 12:14:33.247940 u2DelayCellOfst[13]=13 cells (4 PI)
8894 12:14:33.250936 u2DelayCellOfst[14]=16 cells (5 PI)
8895 12:14:33.254411 u2DelayCellOfst[15]=13 cells (4 PI)
8896 12:14:33.257528 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8897 12:14:33.261170 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8898 12:14:33.264330 DramC Write-DBI on
8899 12:14:33.264416 ==
8900 12:14:33.267414 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 12:14:33.270954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 12:14:33.271036 ==
8903 12:14:33.271099
8904 12:14:33.271158
8905 12:14:33.274085 TX Vref Scan disable
8906 12:14:33.277665 == TX Byte 0 ==
8907 12:14:33.280651 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8908 12:14:33.280734 == TX Byte 1 ==
8909 12:14:33.287491 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8910 12:14:33.287572 DramC Write-DBI off
8911 12:14:33.287636
8912 12:14:33.287697 [DATLAT]
8913 12:14:33.290583 Freq=1600, CH1 RK1
8914 12:14:33.290664
8915 12:14:33.293779 DATLAT Default: 0xf
8916 12:14:33.293861 0, 0xFFFF, sum = 0
8917 12:14:33.297299 1, 0xFFFF, sum = 0
8918 12:14:33.297382 2, 0xFFFF, sum = 0
8919 12:14:33.300294 3, 0xFFFF, sum = 0
8920 12:14:33.300376 4, 0xFFFF, sum = 0
8921 12:14:33.303666 5, 0xFFFF, sum = 0
8922 12:14:33.303749 6, 0xFFFF, sum = 0
8923 12:14:33.307246 7, 0xFFFF, sum = 0
8924 12:14:33.307329 8, 0xFFFF, sum = 0
8925 12:14:33.310136 9, 0xFFFF, sum = 0
8926 12:14:33.310219 10, 0xFFFF, sum = 0
8927 12:14:33.313854 11, 0xFFFF, sum = 0
8928 12:14:33.313937 12, 0xFFFF, sum = 0
8929 12:14:33.317232 13, 0xFFFF, sum = 0
8930 12:14:33.317314 14, 0x0, sum = 1
8931 12:14:33.320493 15, 0x0, sum = 2
8932 12:14:33.320577 16, 0x0, sum = 3
8933 12:14:33.323593 17, 0x0, sum = 4
8934 12:14:33.323676 best_step = 15
8935 12:14:33.323741
8936 12:14:33.323802 ==
8937 12:14:33.326854 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 12:14:33.333562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 12:14:33.333645 ==
8940 12:14:33.333710 RX Vref Scan: 0
8941 12:14:33.333771
8942 12:14:33.336682 RX Vref 0 -> 0, step: 1
8943 12:14:33.336788
8944 12:14:33.340217 RX Delay 19 -> 252, step: 4
8945 12:14:33.343158 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8946 12:14:33.346719 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8947 12:14:33.349791 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
8948 12:14:33.356585 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8949 12:14:33.360056 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8950 12:14:33.363179 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8951 12:14:33.366197 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8952 12:14:33.369779 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8953 12:14:33.376337 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8954 12:14:33.379414 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8955 12:14:33.383011 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8956 12:14:33.386210 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8957 12:14:33.389386 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8958 12:14:33.396238 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8959 12:14:33.399455 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8960 12:14:33.402441 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8961 12:14:33.402523 ==
8962 12:14:33.405964 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 12:14:33.409434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 12:14:33.412220 ==
8965 12:14:33.412333 DQS Delay:
8966 12:14:33.412400 DQS0 = 0, DQS1 = 0
8967 12:14:33.415682 DQM Delay:
8968 12:14:33.415764 DQM0 = 134, DQM1 = 129
8969 12:14:33.419021 DQ Delay:
8970 12:14:33.422349 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8971 12:14:33.425796 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
8972 12:14:33.429140 DQ8 =112, DQ9 =118, DQ10 =128, DQ11 =124
8973 12:14:33.432224 DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =140
8974 12:14:33.432312
8975 12:14:33.432417
8976 12:14:33.432483
8977 12:14:33.435576 [DramC_TX_OE_Calibration] TA2
8978 12:14:33.438676 Original DQ_B0 (3 6) =30, OEN = 27
8979 12:14:33.442180 Original DQ_B1 (3 6) =30, OEN = 27
8980 12:14:33.445184 24, 0x0, End_B0=24 End_B1=24
8981 12:14:33.445260 25, 0x0, End_B0=25 End_B1=25
8982 12:14:33.448649 26, 0x0, End_B0=26 End_B1=26
8983 12:14:33.452211 27, 0x0, End_B0=27 End_B1=27
8984 12:14:33.455312 28, 0x0, End_B0=28 End_B1=28
8985 12:14:33.458473 29, 0x0, End_B0=29 End_B1=29
8986 12:14:33.458580 30, 0x0, End_B0=30 End_B1=30
8987 12:14:33.461920 31, 0x5151, End_B0=30 End_B1=30
8988 12:14:33.465467 Byte0 end_step=30 best_step=27
8989 12:14:33.468807 Byte1 end_step=30 best_step=27
8990 12:14:33.471959 Byte0 TX OE(2T, 0.5T) = (3, 3)
8991 12:14:33.475004 Byte1 TX OE(2T, 0.5T) = (3, 3)
8992 12:14:33.475089
8993 12:14:33.475154
8994 12:14:33.482020 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
8995 12:14:33.485135 CH1 RK1: MR19=303, MR18=1A05
8996 12:14:33.491784 CH1_RK1: MR19=0x303, MR18=0x1A05, DQSOSC=396, MR23=63, INC=23, DEC=15
8997 12:14:33.494979 [RxdqsGatingPostProcess] freq 1600
8998 12:14:33.498517 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8999 12:14:33.501690 best DQS0 dly(2T, 0.5T) = (1, 1)
9000 12:14:33.505336 best DQS1 dly(2T, 0.5T) = (1, 1)
9001 12:14:33.508299 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9002 12:14:33.511815 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9003 12:14:33.514737 best DQS0 dly(2T, 0.5T) = (1, 1)
9004 12:14:33.518170 best DQS1 dly(2T, 0.5T) = (1, 1)
9005 12:14:33.521731 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9006 12:14:33.524637 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9007 12:14:33.528156 Pre-setting of DQS Precalculation
9008 12:14:33.531454 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9009 12:14:33.537998 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9010 12:14:33.548226 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9011 12:14:33.548333
9012 12:14:33.548427
9013 12:14:33.551055 [Calibration Summary] 3200 Mbps
9014 12:14:33.551156 CH 0, Rank 0
9015 12:14:33.554478 SW Impedance : PASS
9016 12:14:33.554576 DUTY Scan : NO K
9017 12:14:33.558162 ZQ Calibration : PASS
9018 12:14:33.558233 Jitter Meter : NO K
9019 12:14:33.561289 CBT Training : PASS
9020 12:14:33.564342 Write leveling : PASS
9021 12:14:33.564410 RX DQS gating : PASS
9022 12:14:33.567897 RX DQ/DQS(RDDQC) : PASS
9023 12:14:33.570981 TX DQ/DQS : PASS
9024 12:14:33.571051 RX DATLAT : PASS
9025 12:14:33.574087 RX DQ/DQS(Engine): PASS
9026 12:14:33.577700 TX OE : PASS
9027 12:14:33.577773 All Pass.
9028 12:14:33.577858
9029 12:14:33.577931 CH 0, Rank 1
9030 12:14:33.581290 SW Impedance : PASS
9031 12:14:33.584198 DUTY Scan : NO K
9032 12:14:33.584294 ZQ Calibration : PASS
9033 12:14:33.587832 Jitter Meter : NO K
9034 12:14:33.591069 CBT Training : PASS
9035 12:14:33.591136 Write leveling : PASS
9036 12:14:33.594276 RX DQS gating : PASS
9037 12:14:33.597832 RX DQ/DQS(RDDQC) : PASS
9038 12:14:33.597903 TX DQ/DQS : PASS
9039 12:14:33.601038 RX DATLAT : PASS
9040 12:14:33.604487 RX DQ/DQS(Engine): PASS
9041 12:14:33.604555 TX OE : PASS
9042 12:14:33.604615 All Pass.
9043 12:14:33.607775
9044 12:14:33.607841 CH 1, Rank 0
9045 12:14:33.610870 SW Impedance : PASS
9046 12:14:33.610938 DUTY Scan : NO K
9047 12:14:33.614501 ZQ Calibration : PASS
9048 12:14:33.617597 Jitter Meter : NO K
9049 12:14:33.617679 CBT Training : PASS
9050 12:14:33.620679 Write leveling : PASS
9051 12:14:33.620786 RX DQS gating : PASS
9052 12:14:33.624190 RX DQ/DQS(RDDQC) : PASS
9053 12:14:33.627219 TX DQ/DQS : PASS
9054 12:14:33.627301 RX DATLAT : PASS
9055 12:14:33.630506 RX DQ/DQS(Engine): PASS
9056 12:14:33.633833 TX OE : PASS
9057 12:14:33.633917 All Pass.
9058 12:14:33.633985
9059 12:14:33.634051 CH 1, Rank 1
9060 12:14:33.637175 SW Impedance : PASS
9061 12:14:33.640435 DUTY Scan : NO K
9062 12:14:33.640518 ZQ Calibration : PASS
9063 12:14:33.643865 Jitter Meter : NO K
9064 12:14:33.647237 CBT Training : PASS
9065 12:14:33.647320 Write leveling : PASS
9066 12:14:33.650445 RX DQS gating : PASS
9067 12:14:33.653930 RX DQ/DQS(RDDQC) : PASS
9068 12:14:33.654012 TX DQ/DQS : PASS
9069 12:14:33.657399 RX DATLAT : PASS
9070 12:14:33.660374 RX DQ/DQS(Engine): PASS
9071 12:14:33.660456 TX OE : PASS
9072 12:14:33.663527 All Pass.
9073 12:14:33.663610
9074 12:14:33.663674 DramC Write-DBI on
9075 12:14:33.667076 PER_BANK_REFRESH: Hybrid Mode
9076 12:14:33.667158 TX_TRACKING: ON
9077 12:14:33.677242 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9078 12:14:33.686876 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9079 12:14:33.693560 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9080 12:14:33.696689 [FAST_K] Save calibration result to emmc
9081 12:14:33.699773 sync common calibartion params.
9082 12:14:33.699847 sync cbt_mode0:1, 1:1
9083 12:14:33.703375 dram_init: ddr_geometry: 2
9084 12:14:33.706593 dram_init: ddr_geometry: 2
9085 12:14:33.709637 dram_init: ddr_geometry: 2
9086 12:14:33.709722 0:dram_rank_size:100000000
9087 12:14:33.713249 1:dram_rank_size:100000000
9088 12:14:33.719917 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9089 12:14:33.720001 DFS_SHUFFLE_HW_MODE: ON
9090 12:14:33.723067 dramc_set_vcore_voltage set vcore to 725000
9091 12:14:33.726676 Read voltage for 1600, 0
9092 12:14:33.726748 Vio18 = 0
9093 12:14:33.729685 Vcore = 725000
9094 12:14:33.729760 Vdram = 0
9095 12:14:33.729823 Vddq = 0
9096 12:14:33.733317 Vmddr = 0
9097 12:14:33.733414 switch to 3200 Mbps bootup
9098 12:14:33.736574 [DramcRunTimeConfig]
9099 12:14:33.736644 PHYPLL
9100 12:14:33.739486 DPM_CONTROL_AFTERK: ON
9101 12:14:33.739553 PER_BANK_REFRESH: ON
9102 12:14:33.742884 REFRESH_OVERHEAD_REDUCTION: ON
9103 12:14:33.746229 CMD_PICG_NEW_MODE: OFF
9104 12:14:33.746295 XRTWTW_NEW_MODE: ON
9105 12:14:33.749624 XRTRTR_NEW_MODE: ON
9106 12:14:33.749695 TX_TRACKING: ON
9107 12:14:33.753083 RDSEL_TRACKING: OFF
9108 12:14:33.756008 DQS Precalculation for DVFS: ON
9109 12:14:33.756082 RX_TRACKING: OFF
9110 12:14:33.759776 HW_GATING DBG: ON
9111 12:14:33.759861 ZQCS_ENABLE_LP4: ON
9112 12:14:33.763107 RX_PICG_NEW_MODE: ON
9113 12:14:33.763186 TX_PICG_NEW_MODE: ON
9114 12:14:33.766115 ENABLE_RX_DCM_DPHY: ON
9115 12:14:33.769734 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9116 12:14:33.772903 DUMMY_READ_FOR_TRACKING: OFF
9117 12:14:33.775860 !!! SPM_CONTROL_AFTERK: OFF
9118 12:14:33.775945 !!! SPM could not control APHY
9119 12:14:33.779515 IMPEDANCE_TRACKING: ON
9120 12:14:33.779584 TEMP_SENSOR: ON
9121 12:14:33.782690 HW_SAVE_FOR_SR: OFF
9122 12:14:33.785792 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9123 12:14:33.789323 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9124 12:14:33.792701 Read ODT Tracking: ON
9125 12:14:33.792809 Refresh Rate DeBounce: ON
9126 12:14:33.795711 DFS_NO_QUEUE_FLUSH: ON
9127 12:14:33.799300 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9128 12:14:33.802422 ENABLE_DFS_RUNTIME_MRW: OFF
9129 12:14:33.802498 DDR_RESERVE_NEW_MODE: ON
9130 12:14:33.805409 MR_CBT_SWITCH_FREQ: ON
9131 12:14:33.809136 =========================
9132 12:14:33.826760 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9133 12:14:33.829882 dram_init: ddr_geometry: 2
9134 12:14:33.848469 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9135 12:14:33.851767 dram_init: dram init end (result: 0)
9136 12:14:33.858169 DRAM-K: Full calibration passed in 24468 msecs
9137 12:14:33.861617 MRC: failed to locate region type 0.
9138 12:14:33.861707 DRAM rank0 size:0x100000000,
9139 12:14:33.864658 DRAM rank1 size=0x100000000
9140 12:14:33.874530 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9141 12:14:33.881277 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9142 12:14:33.888036 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9143 12:14:33.894497 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9144 12:14:33.898093 DRAM rank0 size:0x100000000,
9145 12:14:33.901146 DRAM rank1 size=0x100000000
9146 12:14:33.901229 CBMEM:
9147 12:14:33.904695 IMD: root @ 0xfffff000 254 entries.
9148 12:14:33.907798 IMD: root @ 0xffffec00 62 entries.
9149 12:14:33.911000 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9150 12:14:33.917552 WARNING: RO_VPD is uninitialized or empty.
9151 12:14:33.920738 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9152 12:14:33.928191 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9153 12:14:33.940888 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9154 12:14:33.952363 BS: romstage times (exec / console): total (unknown) / 23971 ms
9155 12:14:33.952444
9156 12:14:33.952509
9157 12:14:33.962531 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9158 12:14:33.965485 ARM64: Exception handlers installed.
9159 12:14:33.968846 ARM64: Testing exception
9160 12:14:33.972247 ARM64: Done test exception
9161 12:14:33.972325 Enumerating buses...
9162 12:14:33.975570 Show all devs... Before device enumeration.
9163 12:14:33.978908 Root Device: enabled 1
9164 12:14:33.982334 CPU_CLUSTER: 0: enabled 1
9165 12:14:33.982407 CPU: 00: enabled 1
9166 12:14:33.985245 Compare with tree...
9167 12:14:33.985316 Root Device: enabled 1
9168 12:14:33.988880 CPU_CLUSTER: 0: enabled 1
9169 12:14:33.992047 CPU: 00: enabled 1
9170 12:14:33.992120 Root Device scanning...
9171 12:14:33.995299 scan_static_bus for Root Device
9172 12:14:33.998501 CPU_CLUSTER: 0 enabled
9173 12:14:34.002060 scan_static_bus for Root Device done
9174 12:14:34.005205 scan_bus: bus Root Device finished in 8 msecs
9175 12:14:34.005289 done
9176 12:14:34.011905 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9177 12:14:34.015101 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9178 12:14:34.021653 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9179 12:14:34.025423 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9180 12:14:34.028546 Allocating resources...
9181 12:14:34.031535 Reading resources...
9182 12:14:34.035245 Root Device read_resources bus 0 link: 0
9183 12:14:34.038297 DRAM rank0 size:0x100000000,
9184 12:14:34.038380 DRAM rank1 size=0x100000000
9185 12:14:34.041830 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9186 12:14:34.044744 CPU: 00 missing read_resources
9187 12:14:34.051844 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9188 12:14:34.054889 Root Device read_resources bus 0 link: 0 done
9189 12:14:34.054964 Done reading resources.
9190 12:14:34.061513 Show resources in subtree (Root Device)...After reading.
9191 12:14:34.065033 Root Device child on link 0 CPU_CLUSTER: 0
9192 12:14:34.068472 CPU_CLUSTER: 0 child on link 0 CPU: 00
9193 12:14:34.078010 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9194 12:14:34.078089 CPU: 00
9195 12:14:34.081474 Root Device assign_resources, bus 0 link: 0
9196 12:14:34.084761 CPU_CLUSTER: 0 missing set_resources
9197 12:14:34.091321 Root Device assign_resources, bus 0 link: 0 done
9198 12:14:34.091396 Done setting resources.
9199 12:14:34.097964 Show resources in subtree (Root Device)...After assigning values.
9200 12:14:34.101402 Root Device child on link 0 CPU_CLUSTER: 0
9201 12:14:34.104454 CPU_CLUSTER: 0 child on link 0 CPU: 00
9202 12:14:34.114722 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9203 12:14:34.114806 CPU: 00
9204 12:14:34.117787 Done allocating resources.
9205 12:14:34.124338 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9206 12:14:34.124421 Enabling resources...
9207 12:14:34.124487 done.
9208 12:14:34.131037 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9209 12:14:34.131121 Initializing devices...
9210 12:14:34.134567 Root Device init
9211 12:14:34.137605 init hardware done!
9212 12:14:34.137688 0x00000018: ctrlr->caps
9213 12:14:34.141204 52.000 MHz: ctrlr->f_max
9214 12:14:34.144061 0.400 MHz: ctrlr->f_min
9215 12:14:34.144150 0x40ff8080: ctrlr->voltages
9216 12:14:34.147682 sclk: 390625
9217 12:14:34.147764 Bus Width = 1
9218 12:14:34.147842 sclk: 390625
9219 12:14:34.150684 Bus Width = 1
9220 12:14:34.150760 Early init status = 3
9221 12:14:34.157171 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9222 12:14:34.160748 in-header: 03 fc 00 00 01 00 00 00
9223 12:14:34.163963 in-data: 00
9224 12:14:34.167187 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9225 12:14:34.171122 in-header: 03 fd 00 00 00 00 00 00
9226 12:14:34.174477 in-data:
9227 12:14:34.178056 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9228 12:14:34.181244 in-header: 03 fc 00 00 01 00 00 00
9229 12:14:34.184654 in-data: 00
9230 12:14:34.187626 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9231 12:14:34.192374 in-header: 03 fd 00 00 00 00 00 00
9232 12:14:34.195862 in-data:
9233 12:14:34.199175 [SSUSB] Setting up USB HOST controller...
9234 12:14:34.202354 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9235 12:14:34.205856 [SSUSB] phy power-on done.
9236 12:14:34.209153 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9237 12:14:34.215401 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9238 12:14:34.218683 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9239 12:14:34.225486 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9240 12:14:34.231954 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9241 12:14:34.238563 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9242 12:14:34.245262 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9243 12:14:34.251787 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9244 12:14:34.255014 SPM: binary array size = 0x9dc
9245 12:14:34.258488 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9246 12:14:34.265232 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9247 12:14:34.271723 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9248 12:14:34.278235 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9249 12:14:34.281529 configure_display: Starting display init
9250 12:14:34.315875 anx7625_power_on_init: Init interface.
9251 12:14:34.318917 anx7625_disable_pd_protocol: Disabled PD feature.
9252 12:14:34.322167 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9253 12:14:34.350075 anx7625_start_dp_work: Secure OCM version=00
9254 12:14:34.353548 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9255 12:14:34.368266 sp_tx_get_edid_block: EDID Block = 1
9256 12:14:34.470885 Extracted contents:
9257 12:14:34.474024 header: 00 ff ff ff ff ff ff 00
9258 12:14:34.477466 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9259 12:14:34.481042 version: 01 04
9260 12:14:34.484136 basic params: 95 1f 11 78 0a
9261 12:14:34.487140 chroma info: 76 90 94 55 54 90 27 21 50 54
9262 12:14:34.490502 established: 00 00 00
9263 12:14:34.497114 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9264 12:14:34.500621 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9265 12:14:34.507249 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9266 12:14:34.513889 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9267 12:14:34.520170 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9268 12:14:34.523732 extensions: 00
9269 12:14:34.523814 checksum: fb
9270 12:14:34.523880
9271 12:14:34.526765 Manufacturer: IVO Model 57d Serial Number 0
9272 12:14:34.530372 Made week 0 of 2020
9273 12:14:34.530450 EDID version: 1.4
9274 12:14:34.533590 Digital display
9275 12:14:34.537173 6 bits per primary color channel
9276 12:14:34.537256 DisplayPort interface
9277 12:14:34.540325 Maximum image size: 31 cm x 17 cm
9278 12:14:34.543364 Gamma: 220%
9279 12:14:34.543441 Check DPMS levels
9280 12:14:34.546542 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9281 12:14:34.553321 First detailed timing is preferred timing
9282 12:14:34.553405 Established timings supported:
9283 12:14:34.556361 Standard timings supported:
9284 12:14:34.559990 Detailed timings
9285 12:14:34.563079 Hex of detail: 383680a07038204018303c0035ae10000019
9286 12:14:34.569638 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9287 12:14:34.573241 0780 0798 07c8 0820 hborder 0
9288 12:14:34.576303 0438 043b 0447 0458 vborder 0
9289 12:14:34.580015 -hsync -vsync
9290 12:14:34.580098 Did detailed timing
9291 12:14:34.586212 Hex of detail: 000000000000000000000000000000000000
9292 12:14:34.589792 Manufacturer-specified data, tag 0
9293 12:14:34.592990 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9294 12:14:34.596493 ASCII string: InfoVision
9295 12:14:34.599438 Hex of detail: 000000fe00523134304e574635205248200a
9296 12:14:34.602894 ASCII string: R140NWF5 RH
9297 12:14:34.602973 Checksum
9298 12:14:34.606243 Checksum: 0xfb (valid)
9299 12:14:34.609635 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9300 12:14:34.612644 DSI data_rate: 832800000 bps
9301 12:14:34.619445 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9302 12:14:34.622719 anx7625_parse_edid: pixelclock(138800).
9303 12:14:34.626062 hactive(1920), hsync(48), hfp(24), hbp(88)
9304 12:14:34.629053 vactive(1080), vsync(12), vfp(3), vbp(17)
9305 12:14:34.632494 anx7625_dsi_config: config dsi.
9306 12:14:34.639239 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9307 12:14:34.652740 anx7625_dsi_config: success to config DSI
9308 12:14:34.656008 anx7625_dp_start: MIPI phy setup OK.
9309 12:14:34.659551 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9310 12:14:34.663000 mtk_ddp_mode_set invalid vrefresh 60
9311 12:14:34.666130 main_disp_path_setup
9312 12:14:34.666211 ovl_layer_smi_id_en
9313 12:14:34.669238 ovl_layer_smi_id_en
9314 12:14:34.669319 ccorr_config
9315 12:14:34.669383 aal_config
9316 12:14:34.672645 gamma_config
9317 12:14:34.672752 postmask_config
9318 12:14:34.676146 dither_config
9319 12:14:34.679247 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9320 12:14:34.685909 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9321 12:14:34.689074 Root Device init finished in 551 msecs
9322 12:14:34.692675 CPU_CLUSTER: 0 init
9323 12:14:34.699004 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9324 12:14:34.705779 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9325 12:14:34.705858 APU_MBOX 0x190000b0 = 0x10001
9326 12:14:34.708758 APU_MBOX 0x190001b0 = 0x10001
9327 12:14:34.712096 APU_MBOX 0x190005b0 = 0x10001
9328 12:14:34.715806 APU_MBOX 0x190006b0 = 0x10001
9329 12:14:34.721885 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9330 12:14:34.731775 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9331 12:14:34.744266 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9332 12:14:34.751082 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9333 12:14:34.762374 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9334 12:14:34.771542 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9335 12:14:34.775068 CPU_CLUSTER: 0 init finished in 81 msecs
9336 12:14:34.778295 Devices initialized
9337 12:14:34.781780 Show all devs... After init.
9338 12:14:34.781868 Root Device: enabled 1
9339 12:14:34.784859 CPU_CLUSTER: 0: enabled 1
9340 12:14:34.788032 CPU: 00: enabled 1
9341 12:14:34.791648 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9342 12:14:34.794740 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9343 12:14:34.797876 ELOG: NV offset 0x57f000 size 0x1000
9344 12:14:34.804744 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9345 12:14:34.811708 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9346 12:14:34.814578 ELOG: Event(17) added with size 13 at 2023-06-06 12:14:37 UTC
9347 12:14:34.821104 out: cmd=0x121: 03 db 21 01 00 00 00 00
9348 12:14:34.824491 in-header: 03 53 00 00 2c 00 00 00
9349 12:14:34.838089 in-data: 0c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9350 12:14:34.841025 ELOG: Event(A1) added with size 10 at 2023-06-06 12:14:37 UTC
9351 12:14:34.847697 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9352 12:14:34.854620 ELOG: Event(A0) added with size 9 at 2023-06-06 12:14:37 UTC
9353 12:14:34.857564 elog_add_boot_reason: Logged dev mode boot
9354 12:14:34.864334 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9355 12:14:34.864418 Finalize devices...
9356 12:14:34.867435 Devices finalized
9357 12:14:34.870991 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9358 12:14:34.874404 Writing coreboot table at 0xffe64000
9359 12:14:34.880975 0. 000000000010a000-0000000000113fff: RAMSTAGE
9360 12:14:34.884028 1. 0000000040000000-00000000400fffff: RAM
9361 12:14:34.887588 2. 0000000040100000-000000004032afff: RAMSTAGE
9362 12:14:34.890719 3. 000000004032b000-00000000545fffff: RAM
9363 12:14:34.894263 4. 0000000054600000-000000005465ffff: BL31
9364 12:14:34.897444 5. 0000000054660000-00000000ffe63fff: RAM
9365 12:14:34.904194 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9366 12:14:34.907271 7. 0000000100000000-000000023fffffff: RAM
9367 12:14:34.910770 Passing 5 GPIOs to payload:
9368 12:14:34.914182 NAME | PORT | POLARITY | VALUE
9369 12:14:34.920817 EC in RW | 0x000000aa | low | undefined
9370 12:14:34.924061 EC interrupt | 0x00000005 | low | undefined
9371 12:14:34.930775 TPM interrupt | 0x000000ab | high | undefined
9372 12:14:34.934202 SD card detect | 0x00000011 | high | undefined
9373 12:14:34.937458 speaker enable | 0x00000093 | high | undefined
9374 12:14:34.940811 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9375 12:14:34.944115 in-header: 03 f9 00 00 02 00 00 00
9376 12:14:34.947618 in-data: 02 00
9377 12:14:34.950786 ADC[4]: Raw value=902139 ID=7
9378 12:14:34.953847 ADC[3]: Raw value=213179 ID=1
9379 12:14:34.953931 RAM Code: 0x71
9380 12:14:34.957461 ADC[6]: Raw value=74870 ID=0
9381 12:14:34.960575 ADC[5]: Raw value=212072 ID=1
9382 12:14:34.960658 SKU Code: 0x1
9383 12:14:34.967266 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9384 12:14:34.967350 coreboot table: 964 bytes.
9385 12:14:34.970814 IMD ROOT 0. 0xfffff000 0x00001000
9386 12:14:34.973907 IMD SMALL 1. 0xffffe000 0x00001000
9387 12:14:34.977474 RO MCACHE 2. 0xffffc000 0x00001104
9388 12:14:34.980455 CONSOLE 3. 0xfff7c000 0x00080000
9389 12:14:34.984117 FMAP 4. 0xfff7b000 0x00000452
9390 12:14:34.986908 TIME STAMP 5. 0xfff7a000 0x00000910
9391 12:14:34.990409 VBOOT WORK 6. 0xfff66000 0x00014000
9392 12:14:34.993423 RAMOOPS 7. 0xffe66000 0x00100000
9393 12:14:34.997115 COREBOOT 8. 0xffe64000 0x00002000
9394 12:14:35.000206 IMD small region:
9395 12:14:35.003956 IMD ROOT 0. 0xffffec00 0x00000400
9396 12:14:35.007036 VPD 1. 0xffffeba0 0x0000004c
9397 12:14:35.010222 MMC STATUS 2. 0xffffeb80 0x00000004
9398 12:14:35.013336 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9399 12:14:35.016982 Probing TPM: done!
9400 12:14:35.020538 Connected to device vid:did:rid of 1ae0:0028:00
9401 12:14:35.031625 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9402 12:14:35.034997 Initialized TPM device CR50 revision 0
9403 12:14:35.038332 Checking cr50 for pending updates
9404 12:14:35.042087 Reading cr50 TPM mode
9405 12:14:35.051249 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9406 12:14:35.057361 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9407 12:14:35.097900 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9408 12:14:35.101008 Checking segment from ROM address 0x40100000
9409 12:14:35.104051 Checking segment from ROM address 0x4010001c
9410 12:14:35.110752 Loading segment from ROM address 0x40100000
9411 12:14:35.110862 code (compression=0)
9412 12:14:35.121021 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9413 12:14:35.127541 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9414 12:14:35.127644 it's not compressed!
9415 12:14:35.134072 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9416 12:14:35.140669 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9417 12:14:35.158255 Loading segment from ROM address 0x4010001c
9418 12:14:35.158367 Entry Point 0x80000000
9419 12:14:35.161360 Loaded segments
9420 12:14:35.165076 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9421 12:14:35.171229 Jumping to boot code at 0x80000000(0xffe64000)
9422 12:14:35.178069 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9423 12:14:35.184626 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9424 12:14:35.192795 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9425 12:14:35.195783 Checking segment from ROM address 0x40100000
9426 12:14:35.199310 Checking segment from ROM address 0x4010001c
9427 12:14:35.205585 Loading segment from ROM address 0x40100000
9428 12:14:35.205672 code (compression=1)
9429 12:14:35.212257 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9430 12:14:35.222332 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9431 12:14:35.222440 using LZMA
9432 12:14:35.231097 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9433 12:14:35.237329 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9434 12:14:35.241214 Loading segment from ROM address 0x4010001c
9435 12:14:35.241317 Entry Point 0x54601000
9436 12:14:35.244232 Loaded segments
9437 12:14:35.247497 NOTICE: MT8192 bl31_setup
9438 12:14:35.254416 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9439 12:14:35.257727 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9440 12:14:35.261209 WARNING: region 0:
9441 12:14:35.264432 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 12:14:35.264553 WARNING: region 1:
9443 12:14:35.270943 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9444 12:14:35.274564 WARNING: region 2:
9445 12:14:35.277747 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9446 12:14:35.281319 WARNING: region 3:
9447 12:14:35.284509 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9448 12:14:35.287470 WARNING: region 4:
9449 12:14:35.294404 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9450 12:14:35.294515 WARNING: region 5:
9451 12:14:35.297452 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 12:14:35.300772 WARNING: region 6:
9453 12:14:35.304301 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 12:14:35.307465 WARNING: region 7:
9455 12:14:35.311119 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 12:14:35.317819 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9457 12:14:35.320997 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9458 12:14:35.324094 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9459 12:14:35.330977 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9460 12:14:35.334037 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9461 12:14:35.337586 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9462 12:14:35.344297 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9463 12:14:35.347402 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9464 12:14:35.354169 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9465 12:14:35.357510 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9466 12:14:35.360902 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9467 12:14:35.367403 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9468 12:14:35.370678 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9469 12:14:35.374025 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9470 12:14:35.380705 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9471 12:14:35.384021 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9472 12:14:35.390976 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9473 12:14:35.393949 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9474 12:14:35.397458 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9475 12:14:35.404088 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9476 12:14:35.407142 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9477 12:14:35.414015 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9478 12:14:35.417015 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9479 12:14:35.420580 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9480 12:14:35.427397 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9481 12:14:35.430529 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9482 12:14:35.437265 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9483 12:14:35.440287 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9484 12:14:35.443503 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9485 12:14:35.450592 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9486 12:14:35.453610 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9487 12:14:35.460350 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9488 12:14:35.463663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9489 12:14:35.467148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9490 12:14:35.470446 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9491 12:14:35.473810 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9492 12:14:35.480469 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9493 12:14:35.483436 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9494 12:14:35.487040 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9495 12:14:35.490494 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9496 12:14:35.497231 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9497 12:14:35.500646 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9498 12:14:35.503812 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9499 12:14:35.507301 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9500 12:14:35.513933 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9501 12:14:35.516961 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9502 12:14:35.520143 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9503 12:14:35.526922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9504 12:14:35.530494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9505 12:14:35.533680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9506 12:14:35.540354 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9507 12:14:35.543504 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9508 12:14:35.550143 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9509 12:14:35.553719 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9510 12:14:35.560393 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9511 12:14:35.563403 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9512 12:14:35.566725 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9513 12:14:35.573546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9514 12:14:35.576801 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9515 12:14:35.583505 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9516 12:14:35.586739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9517 12:14:35.593287 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9518 12:14:35.596773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9519 12:14:35.599920 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9520 12:14:35.606883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9521 12:14:35.610036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9522 12:14:35.616635 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9523 12:14:35.619704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9524 12:14:35.626391 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9525 12:14:35.629950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9526 12:14:35.636161 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9527 12:14:35.639860 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9528 12:14:35.643181 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9529 12:14:35.649883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9530 12:14:35.652988 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9531 12:14:35.659549 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9532 12:14:35.663159 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9533 12:14:35.669820 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9534 12:14:35.673121 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9535 12:14:35.679760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9536 12:14:35.683156 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9537 12:14:35.686089 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9538 12:14:35.692794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9539 12:14:35.696067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9540 12:14:35.703161 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9541 12:14:35.706244 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9542 12:14:35.713137 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9543 12:14:35.716250 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9544 12:14:35.719717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9545 12:14:35.725894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9546 12:14:35.729527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9547 12:14:35.736196 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9548 12:14:35.739256 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9549 12:14:35.745932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9550 12:14:35.749613 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9551 12:14:35.755771 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9552 12:14:35.759270 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9553 12:14:35.762506 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9554 12:14:35.766080 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9555 12:14:35.772373 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9556 12:14:35.775854 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9557 12:14:35.779246 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9558 12:14:35.786077 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9559 12:14:35.789264 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9560 12:14:35.792612 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9561 12:14:35.799317 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9562 12:14:35.802410 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9563 12:14:35.809006 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9564 12:14:35.812441 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9565 12:14:35.815815 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9566 12:14:35.822344 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9567 12:14:35.825981 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9568 12:14:35.832266 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9569 12:14:35.836011 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9570 12:14:35.839123 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9571 12:14:35.845918 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9572 12:14:35.849003 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9573 12:14:35.852119 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9574 12:14:35.858835 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9575 12:14:35.862497 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9576 12:14:35.865520 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9577 12:14:35.869364 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9578 12:14:35.875326 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9579 12:14:35.878900 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9580 12:14:35.882230 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9581 12:14:35.889040 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9582 12:14:35.891991 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9583 12:14:35.898478 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9584 12:14:35.901675 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9585 12:14:35.905153 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9586 12:14:35.912066 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9587 12:14:35.915291 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9588 12:14:35.918595 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9589 12:14:35.925415 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9590 12:14:35.928721 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9591 12:14:35.935527 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9592 12:14:35.938451 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9593 12:14:35.942083 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9594 12:14:35.948279 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9595 12:14:35.951839 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9596 12:14:35.958722 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9597 12:14:35.961817 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9598 12:14:35.964946 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9599 12:14:35.971537 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9600 12:14:35.975267 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9601 12:14:35.981945 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9602 12:14:35.985007 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9603 12:14:35.988498 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9604 12:14:35.995211 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9605 12:14:35.998248 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9606 12:14:36.004687 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9607 12:14:36.008007 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9608 12:14:36.011281 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9609 12:14:36.017951 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9610 12:14:36.021686 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9611 12:14:36.025045 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9612 12:14:36.031661 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9613 12:14:36.034972 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9614 12:14:36.041243 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9615 12:14:36.044865 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9616 12:14:36.048079 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9617 12:14:36.054370 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9618 12:14:36.058058 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9619 12:14:36.064200 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9620 12:14:36.067948 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9621 12:14:36.070924 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9622 12:14:36.077613 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9623 12:14:36.081159 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9624 12:14:36.087871 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9625 12:14:36.090728 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9626 12:14:36.094403 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9627 12:14:36.101066 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9628 12:14:36.103996 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9629 12:14:36.110431 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9630 12:14:36.113798 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9631 12:14:36.117092 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9632 12:14:36.123756 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9633 12:14:36.127084 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9634 12:14:36.133618 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9635 12:14:36.137128 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9636 12:14:36.140492 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9637 12:14:36.147004 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9638 12:14:36.150516 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9639 12:14:36.156687 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9640 12:14:36.160234 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9641 12:14:36.163357 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9642 12:14:36.170047 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9643 12:14:36.173579 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9644 12:14:36.180266 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9645 12:14:36.183253 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9646 12:14:36.190063 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9647 12:14:36.193210 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9648 12:14:36.196662 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9649 12:14:36.203322 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9650 12:14:36.206417 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9651 12:14:36.213134 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9652 12:14:36.216138 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9653 12:14:36.219547 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9654 12:14:36.226260 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9655 12:14:36.229716 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9656 12:14:36.236291 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9657 12:14:36.239482 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9658 12:14:36.246278 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9659 12:14:36.249525 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9660 12:14:36.252968 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9661 12:14:36.259515 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9662 12:14:36.262683 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9663 12:14:36.269220 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9664 12:14:36.272377 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9665 12:14:36.279178 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9666 12:14:36.282618 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9667 12:14:36.285682 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9668 12:14:36.292507 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9669 12:14:36.295720 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9670 12:14:36.302313 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9671 12:14:36.305975 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9672 12:14:36.309014 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9673 12:14:36.315555 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9674 12:14:36.319227 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9675 12:14:36.325532 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9676 12:14:36.328635 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9677 12:14:36.335278 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9678 12:14:36.338554 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9679 12:14:36.342048 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9680 12:14:36.348664 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9681 12:14:36.352144 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9682 12:14:36.358318 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9683 12:14:36.361948 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9684 12:14:36.368153 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9685 12:14:36.371749 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9686 12:14:36.374926 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9687 12:14:36.378515 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9688 12:14:36.381661 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9689 12:14:36.388249 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9690 12:14:36.391395 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9691 12:14:36.394989 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9692 12:14:36.401197 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9693 12:14:36.404696 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9694 12:14:36.411288 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9695 12:14:36.414789 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9696 12:14:36.417803 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9697 12:14:36.424537 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9698 12:14:36.428074 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9699 12:14:36.431078 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9700 12:14:36.437758 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9701 12:14:36.441086 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9702 12:14:36.447546 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9703 12:14:36.451116 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9704 12:14:36.454505 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9705 12:14:36.460968 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9706 12:14:36.464148 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9707 12:14:36.467635 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9708 12:14:36.473991 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9709 12:14:36.477590 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9710 12:14:36.480713 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9711 12:14:36.487302 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9712 12:14:36.490423 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9713 12:14:36.497240 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9714 12:14:36.500412 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9715 12:14:36.504166 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9716 12:14:36.510720 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9717 12:14:36.513693 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9718 12:14:36.520292 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9719 12:14:36.523992 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9720 12:14:36.526874 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9721 12:14:36.533488 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9722 12:14:36.537131 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9723 12:14:36.540272 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9724 12:14:36.546673 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9725 12:14:36.550271 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9726 12:14:36.553394 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9727 12:14:36.556687 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9728 12:14:36.563352 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9729 12:14:36.566663 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9730 12:14:36.569633 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9731 12:14:36.573197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9732 12:14:36.579822 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9733 12:14:36.582911 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9734 12:14:36.586362 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9735 12:14:36.589390 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9736 12:14:36.595904 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9737 12:14:36.599421 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9738 12:14:36.603042 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9739 12:14:36.609257 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9740 12:14:36.612661 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9741 12:14:36.619501 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9742 12:14:36.622475 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9743 12:14:36.629362 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9744 12:14:36.632459 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9745 12:14:36.635999 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9746 12:14:36.642652 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9747 12:14:36.645749 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9748 12:14:36.652197 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9749 12:14:36.655692 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9750 12:14:36.659165 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9751 12:14:36.665539 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9752 12:14:36.668962 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9753 12:14:36.675424 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9754 12:14:36.678850 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9755 12:14:36.685057 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9756 12:14:36.688663 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9757 12:14:36.691716 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9758 12:14:36.698277 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9759 12:14:36.701941 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9760 12:14:36.708587 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9761 12:14:36.711482 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9762 12:14:36.714821 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9763 12:14:36.721406 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9764 12:14:36.724942 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9765 12:14:36.731394 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9766 12:14:36.735038 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9767 12:14:36.741629 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9768 12:14:36.744713 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9769 12:14:36.748338 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9770 12:14:36.754680 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9771 12:14:36.758257 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9772 12:14:36.764772 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9773 12:14:36.768125 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9774 12:14:36.771315 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9775 12:14:36.777589 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9776 12:14:36.781129 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9777 12:14:36.787730 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9778 12:14:36.791413 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9779 12:14:36.794480 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9780 12:14:36.801151 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9781 12:14:36.804253 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9782 12:14:36.810904 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9783 12:14:36.814069 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9784 12:14:36.820633 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9785 12:14:36.824209 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9786 12:14:36.827191 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9787 12:14:36.834148 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9788 12:14:36.837211 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9789 12:14:36.843654 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9790 12:14:36.847187 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9791 12:14:36.853904 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9792 12:14:36.857259 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9793 12:14:36.860214 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9794 12:14:36.867001 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9795 12:14:36.870471 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9796 12:14:36.876673 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9797 12:14:36.880035 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9798 12:14:36.883474 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9799 12:14:36.889943 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9800 12:14:36.893408 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9801 12:14:36.900277 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9802 12:14:36.903328 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9803 12:14:36.906774 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9804 12:14:36.913567 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9805 12:14:36.916594 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9806 12:14:36.923151 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9807 12:14:36.926713 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9808 12:14:36.933301 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9809 12:14:36.936316 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9810 12:14:36.939663 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9811 12:14:36.946473 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9812 12:14:36.949925 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9813 12:14:36.956205 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9814 12:14:36.959605 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9815 12:14:36.966145 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9816 12:14:36.969421 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9817 12:14:36.973061 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9818 12:14:36.979242 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9819 12:14:36.982562 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9820 12:14:36.989613 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9821 12:14:36.992508 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9822 12:14:36.999095 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9823 12:14:37.002810 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9824 12:14:37.009207 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9825 12:14:37.012618 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9826 12:14:37.015739 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9827 12:14:37.022663 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9828 12:14:37.025714 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9829 12:14:37.032258 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9830 12:14:37.035449 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9831 12:14:37.042085 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9832 12:14:37.045594 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9833 12:14:37.048776 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9834 12:14:37.055616 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9835 12:14:37.058756 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9836 12:14:37.065731 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9837 12:14:37.068817 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9838 12:14:37.075645 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9839 12:14:37.078657 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9840 12:14:37.085356 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9841 12:14:37.088564 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9842 12:14:37.092095 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9843 12:14:37.098557 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9844 12:14:37.101982 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9845 12:14:37.108249 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9846 12:14:37.111797 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9847 12:14:37.118457 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9848 12:14:37.121482 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9849 12:14:37.124678 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9850 12:14:37.131362 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9851 12:14:37.134932 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9852 12:14:37.141709 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9853 12:14:37.144635 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9854 12:14:37.151208 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9855 12:14:37.154726 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9856 12:14:37.161458 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9857 12:14:37.164471 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9858 12:14:37.168157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9859 12:14:37.174513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9860 12:14:37.177645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9861 12:14:37.184325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9862 12:14:37.187771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9863 12:14:37.194097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9864 12:14:37.197767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9865 12:14:37.204147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9866 12:14:37.207370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9867 12:14:37.214038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9868 12:14:37.217255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9869 12:14:37.223929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9870 12:14:37.227035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9871 12:14:37.233749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9872 12:14:37.237252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9873 12:14:37.243658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9874 12:14:37.247294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9875 12:14:37.253750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9876 12:14:37.256953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9877 12:14:37.263339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9878 12:14:37.266899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9879 12:14:37.273304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9880 12:14:37.276892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9881 12:14:37.283726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9882 12:14:37.286903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9883 12:14:37.293223 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9884 12:14:37.296810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9885 12:14:37.303444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9886 12:14:37.306427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9887 12:14:37.313216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9888 12:14:37.316647 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9889 12:14:37.323136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9890 12:14:37.326343 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9891 12:14:37.329620 INFO: [APUAPC] vio 0
9892 12:14:37.333371 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9893 12:14:37.336339 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9894 12:14:37.339948 INFO: [APUAPC] D0_APC_0: 0x400510
9895 12:14:37.343278 INFO: [APUAPC] D0_APC_1: 0x0
9896 12:14:37.346465 INFO: [APUAPC] D0_APC_2: 0x1540
9897 12:14:37.349426 INFO: [APUAPC] D0_APC_3: 0x0
9898 12:14:37.353104 INFO: [APUAPC] D1_APC_0: 0xffffffff
9899 12:14:37.356137 INFO: [APUAPC] D1_APC_1: 0xffffffff
9900 12:14:37.359774 INFO: [APUAPC] D1_APC_2: 0x3fffff
9901 12:14:37.362882 INFO: [APUAPC] D1_APC_3: 0x0
9902 12:14:37.366274 INFO: [APUAPC] D2_APC_0: 0xffffffff
9903 12:14:37.369397 INFO: [APUAPC] D2_APC_1: 0xffffffff
9904 12:14:37.372606 INFO: [APUAPC] D2_APC_2: 0x3fffff
9905 12:14:37.376287 INFO: [APUAPC] D2_APC_3: 0x0
9906 12:14:37.379228 INFO: [APUAPC] D3_APC_0: 0xffffffff
9907 12:14:37.382773 INFO: [APUAPC] D3_APC_1: 0xffffffff
9908 12:14:37.385903 INFO: [APUAPC] D3_APC_2: 0x3fffff
9909 12:14:37.389575 INFO: [APUAPC] D3_APC_3: 0x0
9910 12:14:37.392608 INFO: [APUAPC] D4_APC_0: 0xffffffff
9911 12:14:37.396201 INFO: [APUAPC] D4_APC_1: 0xffffffff
9912 12:14:37.399331 INFO: [APUAPC] D4_APC_2: 0x3fffff
9913 12:14:37.402369 INFO: [APUAPC] D4_APC_3: 0x0
9914 12:14:37.405918 INFO: [APUAPC] D5_APC_0: 0xffffffff
9915 12:14:37.409011 INFO: [APUAPC] D5_APC_1: 0xffffffff
9916 12:14:37.412707 INFO: [APUAPC] D5_APC_2: 0x3fffff
9917 12:14:37.415585 INFO: [APUAPC] D5_APC_3: 0x0
9918 12:14:37.419183 INFO: [APUAPC] D6_APC_0: 0xffffffff
9919 12:14:37.422237 INFO: [APUAPC] D6_APC_1: 0xffffffff
9920 12:14:37.425596 INFO: [APUAPC] D6_APC_2: 0x3fffff
9921 12:14:37.428941 INFO: [APUAPC] D6_APC_3: 0x0
9922 12:14:37.432191 INFO: [APUAPC] D7_APC_0: 0xffffffff
9923 12:14:37.435500 INFO: [APUAPC] D7_APC_1: 0xffffffff
9924 12:14:37.438536 INFO: [APUAPC] D7_APC_2: 0x3fffff
9925 12:14:37.442175 INFO: [APUAPC] D7_APC_3: 0x0
9926 12:14:37.445286 INFO: [APUAPC] D8_APC_0: 0xffffffff
9927 12:14:37.448428 INFO: [APUAPC] D8_APC_1: 0xffffffff
9928 12:14:37.451989 INFO: [APUAPC] D8_APC_2: 0x3fffff
9929 12:14:37.455192 INFO: [APUAPC] D8_APC_3: 0x0
9930 12:14:37.458769 INFO: [APUAPC] D9_APC_0: 0xffffffff
9931 12:14:37.461948 INFO: [APUAPC] D9_APC_1: 0xffffffff
9932 12:14:37.465475 INFO: [APUAPC] D9_APC_2: 0x3fffff
9933 12:14:37.468612 INFO: [APUAPC] D9_APC_3: 0x0
9934 12:14:37.472006 INFO: [APUAPC] D10_APC_0: 0xffffffff
9935 12:14:37.475113 INFO: [APUAPC] D10_APC_1: 0xffffffff
9936 12:14:37.478158 INFO: [APUAPC] D10_APC_2: 0x3fffff
9937 12:14:37.481529 INFO: [APUAPC] D10_APC_3: 0x0
9938 12:14:37.485165 INFO: [APUAPC] D11_APC_0: 0xffffffff
9939 12:14:37.488236 INFO: [APUAPC] D11_APC_1: 0xffffffff
9940 12:14:37.491517 INFO: [APUAPC] D11_APC_2: 0x3fffff
9941 12:14:37.495167 INFO: [APUAPC] D11_APC_3: 0x0
9942 12:14:37.498286 INFO: [APUAPC] D12_APC_0: 0xffffffff
9943 12:14:37.501381 INFO: [APUAPC] D12_APC_1: 0xffffffff
9944 12:14:37.504873 INFO: [APUAPC] D12_APC_2: 0x3fffff
9945 12:14:37.507919 INFO: [APUAPC] D12_APC_3: 0x0
9946 12:14:37.511602 INFO: [APUAPC] D13_APC_0: 0xffffffff
9947 12:14:37.514651 INFO: [APUAPC] D13_APC_1: 0xffffffff
9948 12:14:37.518099 INFO: [APUAPC] D13_APC_2: 0x3fffff
9949 12:14:37.521149 INFO: [APUAPC] D13_APC_3: 0x0
9950 12:14:37.524618 INFO: [APUAPC] D14_APC_0: 0xffffffff
9951 12:14:37.528165 INFO: [APUAPC] D14_APC_1: 0xffffffff
9952 12:14:37.531500 INFO: [APUAPC] D14_APC_2: 0x3fffff
9953 12:14:37.534556 INFO: [APUAPC] D14_APC_3: 0x0
9954 12:14:37.538083 INFO: [APUAPC] D15_APC_0: 0xffffffff
9955 12:14:37.541342 INFO: [APUAPC] D15_APC_1: 0xffffffff
9956 12:14:37.544607 INFO: [APUAPC] D15_APC_2: 0x3fffff
9957 12:14:37.548077 INFO: [APUAPC] D15_APC_3: 0x0
9958 12:14:37.551544 INFO: [APUAPC] APC_CON: 0x4
9959 12:14:37.551630 INFO: [NOCDAPC] D0_APC_0: 0x0
9960 12:14:37.554507 INFO: [NOCDAPC] D0_APC_1: 0x0
9961 12:14:37.557871 INFO: [NOCDAPC] D1_APC_0: 0x0
9962 12:14:37.561458 INFO: [NOCDAPC] D1_APC_1: 0xfff
9963 12:14:37.564456 INFO: [NOCDAPC] D2_APC_0: 0x0
9964 12:14:37.568068 INFO: [NOCDAPC] D2_APC_1: 0xfff
9965 12:14:37.571216 INFO: [NOCDAPC] D3_APC_0: 0x0
9966 12:14:37.574627 INFO: [NOCDAPC] D3_APC_1: 0xfff
9967 12:14:37.577667 INFO: [NOCDAPC] D4_APC_0: 0x0
9968 12:14:37.581303 INFO: [NOCDAPC] D4_APC_1: 0xfff
9969 12:14:37.584256 INFO: [NOCDAPC] D5_APC_0: 0x0
9970 12:14:37.584357 INFO: [NOCDAPC] D5_APC_1: 0xfff
9971 12:14:37.587783 INFO: [NOCDAPC] D6_APC_0: 0x0
9972 12:14:37.590954 INFO: [NOCDAPC] D6_APC_1: 0xfff
9973 12:14:37.594599 INFO: [NOCDAPC] D7_APC_0: 0x0
9974 12:14:37.597693 INFO: [NOCDAPC] D7_APC_1: 0xfff
9975 12:14:37.601302 INFO: [NOCDAPC] D8_APC_0: 0x0
9976 12:14:37.604548 INFO: [NOCDAPC] D8_APC_1: 0xfff
9977 12:14:37.607574 INFO: [NOCDAPC] D9_APC_0: 0x0
9978 12:14:37.611231 INFO: [NOCDAPC] D9_APC_1: 0xfff
9979 12:14:37.614239 INFO: [NOCDAPC] D10_APC_0: 0x0
9980 12:14:37.617653 INFO: [NOCDAPC] D10_APC_1: 0xfff
9981 12:14:37.621226 INFO: [NOCDAPC] D11_APC_0: 0x0
9982 12:14:37.621330 INFO: [NOCDAPC] D11_APC_1: 0xfff
9983 12:14:37.624175 INFO: [NOCDAPC] D12_APC_0: 0x0
9984 12:14:37.627180 INFO: [NOCDAPC] D12_APC_1: 0xfff
9985 12:14:37.630820 INFO: [NOCDAPC] D13_APC_0: 0x0
9986 12:14:37.633885 INFO: [NOCDAPC] D13_APC_1: 0xfff
9987 12:14:37.637460 INFO: [NOCDAPC] D14_APC_0: 0x0
9988 12:14:37.640453 INFO: [NOCDAPC] D14_APC_1: 0xfff
9989 12:14:37.644057 INFO: [NOCDAPC] D15_APC_0: 0x0
9990 12:14:37.647438 INFO: [NOCDAPC] D15_APC_1: 0xfff
9991 12:14:37.650337 INFO: [NOCDAPC] APC_CON: 0x4
9992 12:14:37.653554 INFO: [APUAPC] set_apusys_apc done
9993 12:14:37.657175 INFO: [DEVAPC] devapc_init done
9994 12:14:37.660129 INFO: GICv3 without legacy support detected.
9995 12:14:37.663682 INFO: ARM GICv3 driver initialized in EL3
9996 12:14:37.666719 INFO: Maximum SPI INTID supported: 639
9997 12:14:37.673358 INFO: BL31: Initializing runtime services
9998 12:14:37.676906 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9999 12:14:37.680202 INFO: SPM: enable CPC mode
10000 12:14:37.686925 INFO: mcdi ready for mcusys-off-idle and system suspend
10001 12:14:37.690292 INFO: BL31: Preparing for EL3 exit to normal world
10002 12:14:37.693358 INFO: Entry point address = 0x80000000
10003 12:14:37.696417 INFO: SPSR = 0x8
10004 12:14:37.702062
10005 12:14:37.702169
10006 12:14:37.702263
10007 12:14:37.705719 Starting depthcharge on Spherion...
10008 12:14:37.705801
10009 12:14:37.705866 Wipe memory regions:
10010 12:14:37.705926
10011 12:14:37.706540 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10012 12:14:37.706640 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10013 12:14:37.706726 Setting prompt string to ['asurada:']
10014 12:14:37.706805 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10015 12:14:37.708724 [0x00000040000000, 0x00000054600000)
10016 12:14:37.831325
10017 12:14:37.831454 [0x00000054660000, 0x00000080000000)
10018 12:14:38.091747
10019 12:14:38.091898 [0x000000821a7280, 0x000000ffe64000)
10020 12:14:38.836388
10021 12:14:38.836570 [0x00000100000000, 0x00000240000000)
10022 12:14:40.727097
10023 12:14:40.730244 Initializing XHCI USB controller at 0x11200000.
10024 12:14:41.768426
10025 12:14:41.771391 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10026 12:14:41.771482
10027 12:14:41.771548
10028 12:14:41.771608
10029 12:14:41.771887 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10031 12:14:41.872221 asurada: tftpboot 192.168.201.1 10605413/tftp-deploy-wfkue_y5/kernel/image.itb 10605413/tftp-deploy-wfkue_y5/kernel/cmdline
10032 12:14:41.872390 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10033 12:14:41.872518 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10034 12:14:41.876514 tftpboot 192.168.201.1 10605413/tftp-deploy-wfkue_y5/kernel/image.itp-deploy-wfkue_y5/kernel/cmdline
10035 12:14:41.876628
10036 12:14:41.876722 Waiting for link
10037 12:14:42.037249
10038 12:14:42.037391 R8152: Initializing
10039 12:14:42.037460
10040 12:14:42.040050 Version 9 (ocp_data = 6010)
10041 12:14:42.040134
10042 12:14:42.043336 R8152: Done initializing
10043 12:14:42.043420
10044 12:14:42.043486 Adding net device
10045 12:14:43.989705
10046 12:14:43.989863 done.
10047 12:14:43.989965
10048 12:14:43.990046 MAC: 00:e0:4c:72:2d:d6
10049 12:14:43.990124
10050 12:14:43.993202 Sending DHCP discover... done.
10051 12:14:43.993287
10052 12:14:43.996178 Waiting for reply... done.
10053 12:14:43.996305
10054 12:14:43.999328 Sending DHCP request... done.
10055 12:14:43.999430
10056 12:14:43.999517 Waiting for reply... done.
10057 12:14:43.999595
10058 12:14:44.002968 My ip is 192.168.201.21
10059 12:14:44.003056
10060 12:14:44.006090 The DHCP server ip is 192.168.201.1
10061 12:14:44.006170
10062 12:14:44.009236 TFTP server IP predefined by user: 192.168.201.1
10063 12:14:44.009310
10064 12:14:44.015898 Bootfile predefined by user: 10605413/tftp-deploy-wfkue_y5/kernel/image.itb
10065 12:14:44.015977
10066 12:14:44.018925 Sending tftp read request... done.
10067 12:14:44.019002
10068 12:14:44.022589 Waiting for the transfer...
10069 12:14:44.022670
10070 12:14:44.297726 00000000 ################################################################
10071 12:14:44.297880
10072 12:14:44.580950 00080000 ################################################################
10073 12:14:44.581090
10074 12:14:44.849895 00100000 ################################################################
10075 12:14:44.850043
10076 12:14:45.116284 00180000 ################################################################
10077 12:14:45.116445
10078 12:14:45.397272 00200000 ################################################################
10079 12:14:45.397422
10080 12:14:45.681726 00280000 ################################################################
10081 12:14:45.681904
10082 12:14:45.953914 00300000 ################################################################
10083 12:14:45.954093
10084 12:14:46.232214 00380000 ################################################################
10085 12:14:46.232438
10086 12:14:46.499069 00400000 ################################################################
10087 12:14:46.499246
10088 12:14:46.781690 00480000 ################################################################
10089 12:14:46.781845
10090 12:14:47.075276 00500000 ################################################################
10091 12:14:47.075429
10092 12:14:47.357862 00580000 ################################################################
10093 12:14:47.358009
10094 12:14:47.629603 00600000 ################################################################
10095 12:14:47.629756
10096 12:14:47.903570 00680000 ################################################################
10097 12:14:47.903718
10098 12:14:48.172709 00700000 ################################################################
10099 12:14:48.172890
10100 12:14:48.460668 00780000 ################################################################
10101 12:14:48.460844
10102 12:14:48.726981 00800000 ################################################################
10103 12:14:48.727133
10104 12:14:48.991773 00880000 ################################################################
10105 12:14:48.991930
10106 12:14:49.275091 00900000 ################################################################
10107 12:14:49.275272
10108 12:14:49.572640 00980000 ################################################################
10109 12:14:49.572843
10110 12:14:49.836811 00a00000 ################################################################
10111 12:14:49.836961
10112 12:14:50.117018 00a80000 ################################################################
10113 12:14:50.117176
10114 12:14:50.388209 00b00000 ################################################################
10115 12:14:50.388361
10116 12:14:50.653955 00b80000 ################################################################
10117 12:14:50.654105
10118 12:14:50.929564 00c00000 ################################################################
10119 12:14:50.929745
10120 12:14:51.222140 00c80000 ################################################################
10121 12:14:51.222290
10122 12:14:51.494876 00d00000 ################################################################
10123 12:14:51.495028
10124 12:14:51.757845 00d80000 ################################################################
10125 12:14:51.758020
10126 12:14:52.025022 00e00000 ################################################################
10127 12:14:52.025182
10128 12:14:52.311534 00e80000 ################################################################
10129 12:14:52.311706
10130 12:14:52.596039 00f00000 ################################################################
10131 12:14:52.596183
10132 12:14:52.867094 00f80000 ################################################################
10133 12:14:52.867233
10134 12:14:53.135339 01000000 ################################################################
10135 12:14:53.135489
10136 12:14:53.396943 01080000 ################################################################
10137 12:14:53.397090
10138 12:14:53.661373 01100000 ################################################################
10139 12:14:53.661522
10140 12:14:53.922701 01180000 ################################################################
10141 12:14:53.922875
10142 12:14:54.192052 01200000 ################################################################
10143 12:14:54.192227
10144 12:14:54.459182 01280000 ################################################################
10145 12:14:54.459359
10146 12:14:54.742028 01300000 ################################################################
10147 12:14:54.742200
10148 12:14:55.007757 01380000 ################################################################
10149 12:14:55.007932
10150 12:14:55.295523 01400000 ################################################################
10151 12:14:55.295666
10152 12:14:55.576394 01480000 ################################################################
10153 12:14:55.576568
10154 12:14:55.845862 01500000 ################################################################
10155 12:14:55.846014
10156 12:14:56.143707 01580000 ################################################################
10157 12:14:56.143857
10158 12:14:56.423287 01600000 ################################################################
10159 12:14:56.423446
10160 12:14:56.700644 01680000 ################################################################
10161 12:14:56.700787
10162 12:14:56.967015 01700000 ################################################################
10163 12:14:56.967184
10164 12:14:57.237005 01780000 ################################################################
10165 12:14:57.237145
10166 12:14:57.498802 01800000 ################################################################
10167 12:14:57.498965
10168 12:14:57.766396 01880000 ################################################################
10169 12:14:57.766533
10170 12:14:58.049990 01900000 ################################################################
10171 12:14:58.050168
10172 12:14:58.320461 01980000 ################################################################
10173 12:14:58.320598
10174 12:14:58.594383 01a00000 ################################################################
10175 12:14:58.594556
10176 12:14:58.856273 01a80000 ################################################################
10177 12:14:58.856414
10178 12:14:59.131362 01b00000 ################################################################
10179 12:14:59.131524
10180 12:14:59.394815 01b80000 ################################################################
10181 12:14:59.394951
10182 12:14:59.659171 01c00000 ################################################################
10183 12:14:59.659347
10184 12:14:59.925444 01c80000 ################################################################
10185 12:14:59.925586
10186 12:15:00.191655 01d00000 ################################################################
10187 12:15:00.191801
10188 12:15:00.453996 01d80000 ################################################################
10189 12:15:00.454154
10190 12:15:00.715208 01e00000 ################################################################
10191 12:15:00.715341
10192 12:15:00.976267 01e80000 ################################################################
10193 12:15:00.976432
10194 12:15:01.237887 01f00000 ################################################################
10195 12:15:01.238054
10196 12:15:01.504904 01f80000 ################################################################
10197 12:15:01.505080
10198 12:15:01.779003 02000000 ################################################################
10199 12:15:01.779139
10200 12:15:02.051458 02080000 ################################################################
10201 12:15:02.051621
10202 12:15:02.315310 02100000 ################################################################
10203 12:15:02.315456
10204 12:15:02.588332 02180000 ################################################################
10205 12:15:02.588500
10206 12:15:02.861746 02200000 ################################################################
10207 12:15:02.861897
10208 12:15:03.128558 02280000 ################################################################
10209 12:15:03.128690
10210 12:15:03.399018 02300000 ################################################################
10211 12:15:03.399154
10212 12:15:03.670998 02380000 ################################################################
10213 12:15:03.671135
10214 12:15:03.939660 02400000 ################################################################
10215 12:15:03.939819
10216 12:15:04.206480 02480000 ################################################################
10217 12:15:04.206615
10218 12:15:04.469413 02500000 ################################################################
10219 12:15:04.469553
10220 12:15:04.741114 02580000 ################################################################
10221 12:15:04.741250
10222 12:15:05.013549 02600000 ################################################################
10223 12:15:05.013700
10224 12:15:05.296124 02680000 ################################################################
10225 12:15:05.296268
10226 12:15:05.563323 02700000 ################################################################
10227 12:15:05.563491
10228 12:15:05.833861 02780000 ################################################################
10229 12:15:05.833999
10230 12:15:06.106925 02800000 ################################################################
10231 12:15:06.107057
10232 12:15:06.381656 02880000 ################################################################
10233 12:15:06.381815
10234 12:15:06.661271 02900000 ################################################################
10235 12:15:06.661424
10236 12:15:06.933503 02980000 ################################################################
10237 12:15:06.933637
10238 12:15:07.219872 02a00000 ################################################################
10239 12:15:07.220003
10240 12:15:07.493930 02a80000 ################################################################
10241 12:15:07.494065
10242 12:15:07.762425 02b00000 ################################################################
10243 12:15:07.762572
10244 12:15:08.028221 02b80000 ################################################################
10245 12:15:08.028351
10246 12:15:08.299148 02c00000 ################################################################
10247 12:15:08.299278
10248 12:15:08.560530 02c80000 ################################################################
10249 12:15:08.560670
10250 12:15:08.827173 02d00000 ################################################################
10251 12:15:08.827306
10252 12:15:09.093542 02d80000 ################################################################
10253 12:15:09.093673
10254 12:15:09.375842 02e00000 ################################################################
10255 12:15:09.375985
10256 12:15:09.652131 02e80000 ################################################################
10257 12:15:09.652272
10258 12:15:09.914228 02f00000 ################################################################
10259 12:15:09.914391
10260 12:15:10.147296 02f80000 ########################################################## done.
10261 12:15:10.147474
10262 12:15:10.150528 The bootfile was 50281990 bytes long.
10263 12:15:10.150641
10264 12:15:10.154236 Sending tftp read request... done.
10265 12:15:10.154341
10266 12:15:10.154439 Waiting for the transfer...
10267 12:15:10.154530
10268 12:15:10.157278 00000000 # done.
10269 12:15:10.157392
10270 12:15:10.163838 Command line loaded dynamically from TFTP file: 10605413/tftp-deploy-wfkue_y5/kernel/cmdline
10271 12:15:10.163927
10272 12:15:10.177095 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10273 12:15:10.177184
10274 12:15:10.177257 Loading FIT.
10275 12:15:10.177338
10276 12:15:10.180524 Image ramdisk-1 has 40138410 bytes.
10277 12:15:10.180628
10278 12:15:10.183672 Image fdt-1 has 46924 bytes.
10279 12:15:10.183778
10280 12:15:10.187406 Image kernel-1 has 10094623 bytes.
10281 12:15:10.187511
10282 12:15:10.194021 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10283 12:15:10.197177
10284 12:15:10.213795 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10285 12:15:10.213915
10286 12:15:10.217340 Choosing best match conf-1 for compat google,spherion-rev2.
10287 12:15:10.222517
10288 12:15:10.226270 Connected to device vid:did:rid of 1ae0:0028:00
10289 12:15:10.233712
10290 12:15:10.237088 tpm_get_response: command 0x17b, return code 0x0
10291 12:15:10.237192
10292 12:15:10.243823 ec_init: CrosEC protocol v3 supported (256, 248)
10293 12:15:10.243930
10294 12:15:10.246889 tpm_cleanup: add release locality here.
10295 12:15:10.246991
10296 12:15:10.250428 Shutting down all USB controllers.
10297 12:15:10.250527
10298 12:15:10.253637 Removing current net device
10299 12:15:10.253735
10300 12:15:10.257214 Exiting depthcharge with code 4 at timestamp: 61819751
10301 12:15:10.260396
10302 12:15:10.263925 LZMA decompressing kernel-1 to 0x821a6718
10303 12:15:10.264029
10304 12:15:10.266881 LZMA decompressing kernel-1 to 0x40000000
10305 12:15:11.534719
10306 12:15:11.534889 jumping to kernel
10307 12:15:11.535606 end: 2.2.4 bootloader-commands (duration 00:00:34) [common]
10308 12:15:11.535743 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
10309 12:15:11.535851 Setting prompt string to ['Linux version [0-9]']
10310 12:15:11.535949 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10311 12:15:11.536083 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10312 12:15:11.616365
10313 12:15:11.619709 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10314 12:15:11.622859 start: 2.2.5.1 login-action (timeout 00:03:51) [common]
10315 12:15:11.622976 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10316 12:15:11.623091 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10317 12:15:11.623202 Using line separator: #'\n'#
10318 12:15:11.623291 No login prompt set.
10319 12:15:11.623385 Parsing kernel messages
10320 12:15:11.623471 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10321 12:15:11.623643 [login-action] Waiting for messages, (timeout 00:03:51)
10322 12:15:11.642513 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
10323 12:15:11.646064 [ 0.000000] random: crng init done
10324 12:15:11.652659 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10325 12:15:11.652762 [ 0.000000] efi: UEFI not found.
10326 12:15:11.662678 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10327 12:15:11.669275 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10328 12:15:11.679179 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10329 12:15:11.689019 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10330 12:15:11.695459 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10331 12:15:11.701933 [ 0.000000] printk: bootconsole [mtk8250] enabled
10332 12:15:11.708788 [ 0.000000] NUMA: No NUMA configuration found
10333 12:15:11.715076 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10334 12:15:11.718626 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10335 12:15:11.721705 [ 0.000000] Zone ranges:
10336 12:15:11.728510 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10337 12:15:11.731541 [ 0.000000] DMA32 empty
10338 12:15:11.738499 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10339 12:15:11.741524 [ 0.000000] Movable zone start for each node
10340 12:15:11.744919 [ 0.000000] Early memory node ranges
10341 12:15:11.751630 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10342 12:15:11.757863 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10343 12:15:11.764753 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10344 12:15:11.771563 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10345 12:15:11.777972 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10346 12:15:11.784640 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10347 12:15:11.840594 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10348 12:15:11.847036 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10349 12:15:11.853855 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10350 12:15:11.856709 [ 0.000000] psci: probing for conduit method from DT.
10351 12:15:11.863293 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10352 12:15:11.867011 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10353 12:15:11.873240 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10354 12:15:11.876575 [ 0.000000] psci: SMC Calling Convention v1.2
10355 12:15:11.882934 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10356 12:15:11.886485 [ 0.000000] Detected VIPT I-cache on CPU0
10357 12:15:11.893184 [ 0.000000] CPU features: detected: GIC system register CPU interface
10358 12:15:11.899959 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10359 12:15:11.906214 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10360 12:15:11.912602 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10361 12:15:11.922999 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10362 12:15:11.929225 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10363 12:15:11.932835 [ 0.000000] alternatives: applying boot alternatives
10364 12:15:11.939270 [ 0.000000] Fallback order for Node 0: 0
10365 12:15:11.946113 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10366 12:15:11.949099 [ 0.000000] Policy zone: Normal
10367 12:15:11.959242 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10368 12:15:11.969146 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10369 12:15:11.982317 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10370 12:15:11.992081 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10371 12:15:11.998740 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10372 12:15:12.001857 <6>[ 0.000000] software IO TLB: area num 8.
10373 12:15:12.058898 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10374 12:15:12.207712 <6>[ 0.000000] Memory: 7933744K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419024K reserved, 32768K cma-reserved)
10375 12:15:12.214848 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10376 12:15:12.220954 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10377 12:15:12.224391 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10378 12:15:12.230843 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10379 12:15:12.237545 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10380 12:15:12.241216 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10381 12:15:12.251063 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10382 12:15:12.257353 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10383 12:15:12.264041 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10384 12:15:12.270695 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10385 12:15:12.273727 <6>[ 0.000000] GICv3: 608 SPIs implemented
10386 12:15:12.277788 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10387 12:15:12.283771 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10388 12:15:12.287215 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10389 12:15:12.293836 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10390 12:15:12.306664 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10391 12:15:12.319990 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10392 12:15:12.326791 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10393 12:15:12.334440 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10394 12:15:12.347662 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10395 12:15:12.354336 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10396 12:15:12.361022 <6>[ 0.009176] Console: colour dummy device 80x25
10397 12:15:12.371116 <6>[ 0.013903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10398 12:15:12.377696 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10399 12:15:12.380677 <6>[ 0.029217] LSM: Security Framework initializing
10400 12:15:12.387349 <6>[ 0.034184] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10401 12:15:12.397468 <6>[ 0.041998] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10402 12:15:12.406944 <6>[ 0.051430] cblist_init_generic: Setting adjustable number of callback queues.
10403 12:15:12.410136 <6>[ 0.058884] cblist_init_generic: Setting shift to 3 and lim to 1.
10404 12:15:12.416851 <6>[ 0.065224] cblist_init_generic: Setting shift to 3 and lim to 1.
10405 12:15:12.423458 <6>[ 0.071629] rcu: Hierarchical SRCU implementation.
10406 12:15:12.430028 <6>[ 0.076673] rcu: Max phase no-delay instances is 1000.
10407 12:15:12.436703 <6>[ 0.083730] EFI services will not be available.
10408 12:15:12.440056 <6>[ 0.088699] smp: Bringing up secondary CPUs ...
10409 12:15:12.447887 <6>[ 0.093751] Detected VIPT I-cache on CPU1
10410 12:15:12.454691 <6>[ 0.093822] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10411 12:15:12.461308 <6>[ 0.093853] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10412 12:15:12.464403 <6>[ 0.094184] Detected VIPT I-cache on CPU2
10413 12:15:12.471105 <6>[ 0.094232] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10414 12:15:12.480924 <6>[ 0.094246] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10415 12:15:12.484537 <6>[ 0.094503] Detected VIPT I-cache on CPU3
10416 12:15:12.490800 <6>[ 0.094549] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10417 12:15:12.497524 <6>[ 0.094563] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10418 12:15:12.500899 <6>[ 0.094866] CPU features: detected: Spectre-v4
10419 12:15:12.507686 <6>[ 0.094873] CPU features: detected: Spectre-BHB
10420 12:15:12.511012 <6>[ 0.094879] Detected PIPT I-cache on CPU4
10421 12:15:12.517205 <6>[ 0.094936] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10422 12:15:12.523797 <6>[ 0.094953] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10423 12:15:12.530460 <6>[ 0.095248] Detected PIPT I-cache on CPU5
10424 12:15:12.537003 <6>[ 0.095312] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10425 12:15:12.543755 <6>[ 0.095329] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10426 12:15:12.546838 <6>[ 0.095612] Detected PIPT I-cache on CPU6
10427 12:15:12.553451 <6>[ 0.095678] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10428 12:15:12.563426 <6>[ 0.095694] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10429 12:15:12.566601 <6>[ 0.095996] Detected PIPT I-cache on CPU7
10430 12:15:12.573332 <6>[ 0.096060] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10431 12:15:12.579619 <6>[ 0.096076] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10432 12:15:12.583130 <6>[ 0.096123] smp: Brought up 1 node, 8 CPUs
10433 12:15:12.589678 <6>[ 0.237459] SMP: Total of 8 processors activated.
10434 12:15:12.592903 <6>[ 0.242379] CPU features: detected: 32-bit EL0 Support
10435 12:15:12.603026 <6>[ 0.247776] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10436 12:15:12.609746 <6>[ 0.256630] CPU features: detected: Common not Private translations
10437 12:15:12.616122 <6>[ 0.263106] CPU features: detected: CRC32 instructions
10438 12:15:12.622672 <6>[ 0.268491] CPU features: detected: RCpc load-acquire (LDAPR)
10439 12:15:12.625797 <6>[ 0.274487] CPU features: detected: LSE atomic instructions
10440 12:15:12.632523 <6>[ 0.280269] CPU features: detected: Privileged Access Never
10441 12:15:12.639237 <6>[ 0.286048] CPU features: detected: RAS Extension Support
10442 12:15:12.645473 <6>[ 0.291657] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10443 12:15:12.649004 <6>[ 0.298879] CPU: All CPU(s) started at EL2
10444 12:15:12.655714 <6>[ 0.303222] alternatives: applying system-wide alternatives
10445 12:15:12.665714 <6>[ 0.313947] devtmpfs: initialized
10446 12:15:12.678069 <6>[ 0.322750] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10447 12:15:12.687806 <6>[ 0.332712] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10448 12:15:12.694517 <6>[ 0.340899] pinctrl core: initialized pinctrl subsystem
10449 12:15:12.697749 <6>[ 0.347559] DMI not present or invalid.
10450 12:15:12.704337 <6>[ 0.351971] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10451 12:15:12.713902 <6>[ 0.358841] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10452 12:15:12.720891 <6>[ 0.366422] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10453 12:15:12.730456 <6>[ 0.374641] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10454 12:15:12.733975 <6>[ 0.382883] audit: initializing netlink subsys (disabled)
10455 12:15:12.743794 <5>[ 0.388563] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10456 12:15:12.750511 <6>[ 0.389286] thermal_sys: Registered thermal governor 'step_wise'
10457 12:15:12.757166 <6>[ 0.396526] thermal_sys: Registered thermal governor 'power_allocator'
10458 12:15:12.760353 <6>[ 0.402785] cpuidle: using governor menu
10459 12:15:12.767215 <6>[ 0.413754] NET: Registered PF_QIPCRTR protocol family
10460 12:15:12.773559 <6>[ 0.419272] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10461 12:15:12.780205 <6>[ 0.426374] ASID allocator initialised with 32768 entries
10462 12:15:12.783218 <6>[ 0.432923] Serial: AMBA PL011 UART driver
10463 12:15:12.793358 <4>[ 0.441568] Trying to register duplicate clock ID: 134
10464 12:15:12.847009 <6>[ 0.498698] KASLR enabled
10465 12:15:12.861243 <6>[ 0.506361] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10466 12:15:12.867887 <6>[ 0.513372] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10467 12:15:12.874572 <6>[ 0.519860] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10468 12:15:12.881355 <6>[ 0.526863] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10469 12:15:12.887775 <6>[ 0.533349] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10470 12:15:12.894468 <6>[ 0.540353] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10471 12:15:12.900909 <6>[ 0.546841] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10472 12:15:12.907732 <6>[ 0.553845] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10473 12:15:12.910687 <6>[ 0.561317] ACPI: Interpreter disabled.
10474 12:15:12.919577 <6>[ 0.567749] iommu: Default domain type: Translated
10475 12:15:12.925903 <6>[ 0.572865] iommu: DMA domain TLB invalidation policy: strict mode
10476 12:15:12.929384 <5>[ 0.579527] SCSI subsystem initialized
10477 12:15:12.935929 <6>[ 0.583790] usbcore: registered new interface driver usbfs
10478 12:15:12.942309 <6>[ 0.589520] usbcore: registered new interface driver hub
10479 12:15:12.945840 <6>[ 0.595069] usbcore: registered new device driver usb
10480 12:15:12.953209 <6>[ 0.601166] pps_core: LinuxPPS API ver. 1 registered
10481 12:15:12.962821 <6>[ 0.606359] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10482 12:15:12.966437 <6>[ 0.615701] PTP clock support registered
10483 12:15:12.969608 <6>[ 0.619940] EDAC MC: Ver: 3.0.0
10484 12:15:12.976896 <6>[ 0.625128] FPGA manager framework
10485 12:15:12.979938 <6>[ 0.628806] Advanced Linux Sound Architecture Driver Initialized.
10486 12:15:12.984124 <6>[ 0.635565] vgaarb: loaded
10487 12:15:12.990460 <6>[ 0.638721] clocksource: Switched to clocksource arch_sys_counter
10488 12:15:12.997319 <5>[ 0.645159] VFS: Disk quotas dquot_6.6.0
10489 12:15:13.003982 <6>[ 0.649344] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10490 12:15:13.007135 <6>[ 0.656511] pnp: PnP ACPI: disabled
10491 12:15:13.015081 <6>[ 0.663167] NET: Registered PF_INET protocol family
10492 12:15:13.024938 <6>[ 0.668743] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10493 12:15:13.036181 <6>[ 0.681032] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10494 12:15:13.045997 <6>[ 0.689839] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10495 12:15:13.052334 <6>[ 0.697808] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10496 12:15:13.062125 <6>[ 0.706507] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10497 12:15:13.069005 <6>[ 0.716246] TCP: Hash tables configured (established 65536 bind 65536)
10498 12:15:13.075753 <6>[ 0.723105] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10499 12:15:13.085262 <6>[ 0.730302] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10500 12:15:13.092070 <6>[ 0.738005] NET: Registered PF_UNIX/PF_LOCAL protocol family
10501 12:15:13.098494 <6>[ 0.744167] RPC: Registered named UNIX socket transport module.
10502 12:15:13.101687 <6>[ 0.750321] RPC: Registered udp transport module.
10503 12:15:13.108273 <6>[ 0.755253] RPC: Registered tcp transport module.
10504 12:15:13.115094 <6>[ 0.760184] RPC: Registered tcp NFSv4.1 backchannel transport module.
10505 12:15:13.118232 <6>[ 0.766853] PCI: CLS 0 bytes, default 64
10506 12:15:13.121334 <6>[ 0.771237] Unpacking initramfs...
10507 12:15:13.131652 <6>[ 0.775031] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10508 12:15:13.138100 <6>[ 0.783666] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10509 12:15:13.144622 <6>[ 0.792498] kvm [1]: IPA Size Limit: 40 bits
10510 12:15:13.147934 <6>[ 0.797025] kvm [1]: GICv3: no GICV resource entry
10511 12:15:13.154648 <6>[ 0.802047] kvm [1]: disabling GICv2 emulation
10512 12:15:13.158006 <6>[ 0.806730] kvm [1]: GIC system register CPU interface enabled
10513 12:15:13.164632 <6>[ 0.812893] kvm [1]: vgic interrupt IRQ18
10514 12:15:13.167614 <6>[ 0.817248] kvm [1]: VHE mode initialized successfully
10515 12:15:13.175210 <5>[ 0.823664] Initialise system trusted keyrings
10516 12:15:13.181949 <6>[ 0.828452] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10517 12:15:13.189838 <6>[ 0.838455] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10518 12:15:13.196680 <5>[ 0.844830] NFS: Registering the id_resolver key type
10519 12:15:13.200223 <5>[ 0.850139] Key type id_resolver registered
10520 12:15:13.206432 <5>[ 0.854552] Key type id_legacy registered
10521 12:15:13.213490 <6>[ 0.858832] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10522 12:15:13.219742 <6>[ 0.865754] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10523 12:15:13.226471 <6>[ 0.873461] 9p: Installing v9fs 9p2000 file system support
10524 12:15:13.262968 <5>[ 0.911250] Key type asymmetric registered
10525 12:15:13.266768 <5>[ 0.915581] Asymmetric key parser 'x509' registered
10526 12:15:13.276204 <6>[ 0.920721] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10527 12:15:13.279286 <6>[ 0.928336] io scheduler mq-deadline registered
10528 12:15:13.282918 <6>[ 0.933094] io scheduler kyber registered
10529 12:15:13.301176 <6>[ 0.949776] EINJ: ACPI disabled.
10530 12:15:13.333177 <4>[ 0.974851] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10531 12:15:13.343221 <4>[ 0.985491] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10532 12:15:13.357716 <6>[ 1.006139] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10533 12:15:13.365546 <6>[ 1.014127] printk: console [ttyS0] disabled
10534 12:15:13.393671 <6>[ 1.038770] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10535 12:15:13.400464 <6>[ 1.048246] printk: console [ttyS0] enabled
10536 12:15:13.403511 <6>[ 1.048246] printk: console [ttyS0] enabled
10537 12:15:13.410141 <6>[ 1.057143] printk: bootconsole [mtk8250] disabled
10538 12:15:13.413682 <6>[ 1.057143] printk: bootconsole [mtk8250] disabled
10539 12:15:13.420352 <6>[ 1.068329] SuperH (H)SCI(F) driver initialized
10540 12:15:13.423421 <6>[ 1.073597] msm_serial: driver initialized
10541 12:15:13.437461 <6>[ 1.082503] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10542 12:15:13.447445 <6>[ 1.091051] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10543 12:15:13.454122 <6>[ 1.099592] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10544 12:15:13.463756 <6>[ 1.108220] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10545 12:15:13.474102 <6>[ 1.116926] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10546 12:15:13.480332 <6>[ 1.125646] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10547 12:15:13.490287 <6>[ 1.134187] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10548 12:15:13.496980 <6>[ 1.143007] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10549 12:15:13.506842 <6>[ 1.151553] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10550 12:15:13.519446 <6>[ 1.167901] loop: module loaded
10551 12:15:13.526044 <6>[ 1.173897] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10552 12:15:13.549039 <4>[ 1.197173] mtk-pmic-keys: Failed to locate of_node [id: -1]
10553 12:15:13.555375 <6>[ 1.203931] megasas: 07.719.03.00-rc1
10554 12:15:13.564869 <6>[ 1.213422] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10555 12:15:13.577786 <6>[ 1.226104] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10556 12:15:13.593788 <6>[ 1.242121] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10557 12:15:13.653922 <6>[ 1.295481] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10558 12:15:14.741495 <6>[ 2.390101] Freeing initrd memory: 39192K
10559 12:15:14.751747 <6>[ 2.400460] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10560 12:15:14.763165 <6>[ 2.411555] tun: Universal TUN/TAP device driver, 1.6
10561 12:15:14.766171 <6>[ 2.417612] thunder_xcv, ver 1.0
10562 12:15:14.769479 <6>[ 2.421116] thunder_bgx, ver 1.0
10563 12:15:14.772717 <6>[ 2.424612] nicpf, ver 1.0
10564 12:15:14.783501 <6>[ 2.428629] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10565 12:15:14.786815 <6>[ 2.436104] hns3: Copyright (c) 2017 Huawei Corporation.
10566 12:15:14.793406 <6>[ 2.441692] hclge is initializing
10567 12:15:14.796836 <6>[ 2.445274] e1000: Intel(R) PRO/1000 Network Driver
10568 12:15:14.803342 <6>[ 2.450404] e1000: Copyright (c) 1999-2006 Intel Corporation.
10569 12:15:14.806643 <6>[ 2.456417] e1000e: Intel(R) PRO/1000 Network Driver
10570 12:15:14.813381 <6>[ 2.461633] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10571 12:15:14.819745 <6>[ 2.467821] igb: Intel(R) Gigabit Ethernet Network Driver
10572 12:15:14.826501 <6>[ 2.473472] igb: Copyright (c) 2007-2014 Intel Corporation.
10573 12:15:14.833091 <6>[ 2.479308] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10574 12:15:14.839751 <6>[ 2.485825] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10575 12:15:14.842819 <6>[ 2.492286] sky2: driver version 1.30
10576 12:15:14.849341 <6>[ 2.497265] VFIO - User Level meta-driver version: 0.3
10577 12:15:14.857192 <6>[ 2.505459] usbcore: registered new interface driver usb-storage
10578 12:15:14.863338 <6>[ 2.511907] usbcore: registered new device driver onboard-usb-hub
10579 12:15:14.872396 <6>[ 2.521023] mt6397-rtc mt6359-rtc: registered as rtc0
10580 12:15:14.882557 <6>[ 2.526491] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:15:17 UTC (1686053717)
10581 12:15:14.885430 <6>[ 2.536068] i2c_dev: i2c /dev entries driver
10582 12:15:14.902494 <6>[ 2.547828] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10583 12:15:14.909893 <6>[ 2.558048] sdhci: Secure Digital Host Controller Interface driver
10584 12:15:14.916143 <6>[ 2.564487] sdhci: Copyright(c) Pierre Ossman
10585 12:15:14.922957 <6>[ 2.569873] Synopsys Designware Multimedia Card Interface Driver
10586 12:15:14.926014 <6>[ 2.576486] mmc0: CQHCI version 5.10
10587 12:15:14.932572 <6>[ 2.577033] sdhci-pltfm: SDHCI platform and OF driver helper
10588 12:15:14.939643 <6>[ 2.588348] ledtrig-cpu: registered to indicate activity on CPUs
10589 12:15:14.950236 <6>[ 2.595652] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10590 12:15:14.957025 <6>[ 2.603053] usbcore: registered new interface driver usbhid
10591 12:15:14.960266 <6>[ 2.608882] usbhid: USB HID core driver
10592 12:15:14.967031 <6>[ 2.613130] spi_master spi0: will run message pump with realtime priority
10593 12:15:15.011769 <6>[ 2.653951] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10594 12:15:15.030634 <6>[ 2.669017] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10595 12:15:15.034133 <6>[ 2.682591] mmc0: Command Queue Engine enabled
10596 12:15:15.040657 <6>[ 2.687369] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10597 12:15:15.047363 <6>[ 2.694543] cros-ec-spi spi0.0: Chrome EC device registered
10598 12:15:15.050265 <6>[ 2.694801] mmcblk0: mmc0:0001 DA4128 116 GiB
10599 12:15:15.061582 <6>[ 2.710060] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10600 12:15:15.069270 <6>[ 2.717607] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10601 12:15:15.075545 <6>[ 2.723734] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10602 12:15:15.082236 <6>[ 2.729749] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10603 12:15:15.101101 <6>[ 2.746140] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10604 12:15:15.109112 <6>[ 2.757554] NET: Registered PF_PACKET protocol family
10605 12:15:15.115587 <6>[ 2.763015] 9pnet: Installing 9P2000 support
10606 12:15:15.118828 <5>[ 2.767597] Key type dns_resolver registered
10607 12:15:15.122077 <6>[ 2.772746] registered taskstats version 1
10608 12:15:15.128918 <5>[ 2.777172] Loading compiled-in X.509 certificates
10609 12:15:15.162478 <4>[ 2.804370] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 12:15:15.172243 <4>[ 2.815113] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 12:15:15.182338 <3>[ 2.827799] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10612 12:15:15.194579 <6>[ 2.843333] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10613 12:15:15.201578 <6>[ 2.850088] xhci-mtk 11200000.usb: xHCI Host Controller
10614 12:15:15.208279 <6>[ 2.855586] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10615 12:15:15.218071 <6>[ 2.863434] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10616 12:15:15.224753 <6>[ 2.872869] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10617 12:15:15.231764 <6>[ 2.879120] xhci-mtk 11200000.usb: xHCI Host Controller
10618 12:15:15.238009 <6>[ 2.884619] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10619 12:15:15.244674 <6>[ 2.892319] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10620 12:15:15.251632 <6>[ 2.900232] hub 1-0:1.0: USB hub found
10621 12:15:15.255157 <6>[ 2.904267] hub 1-0:1.0: 1 port detected
10622 12:15:15.264909 <6>[ 2.908605] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10623 12:15:15.268141 <6>[ 2.917412] hub 2-0:1.0: USB hub found
10624 12:15:15.271117 <6>[ 2.921448] hub 2-0:1.0: 1 port detected
10625 12:15:15.279978 <6>[ 2.928785] mtk-msdc 11f70000.mmc: Got CD GPIO
10626 12:15:15.297497 <6>[ 2.942966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10627 12:15:15.304247 <6>[ 2.951167] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10628 12:15:15.314125 <4>[ 2.959224] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10629 12:15:15.324261 <6>[ 2.968889] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10630 12:15:15.330736 <6>[ 2.976975] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10631 12:15:15.340621 <6>[ 2.985019] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10632 12:15:15.347043 <6>[ 2.992937] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10633 12:15:15.353616 <6>[ 3.000758] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10634 12:15:15.363711 <6>[ 3.008579] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10635 12:15:15.373946 <6>[ 3.019341] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10636 12:15:15.383804 <6>[ 3.027715] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10637 12:15:15.390561 <6>[ 3.036062] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10638 12:15:15.400770 <6>[ 3.044404] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10639 12:15:15.407087 <6>[ 3.052748] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10640 12:15:15.417270 <6>[ 3.061092] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10641 12:15:15.423918 <6>[ 3.069444] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10642 12:15:15.433653 <6>[ 3.077793] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10643 12:15:15.440425 <6>[ 3.086136] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10644 12:15:15.450242 <6>[ 3.094479] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10645 12:15:15.457068 <6>[ 3.102823] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10646 12:15:15.466838 <6>[ 3.111166] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10647 12:15:15.473394 <6>[ 3.119513] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10648 12:15:15.483213 <6>[ 3.127857] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10649 12:15:15.489955 <6>[ 3.136201] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10650 12:15:15.496386 <6>[ 3.145104] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10651 12:15:15.503968 <6>[ 3.152507] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10652 12:15:15.511095 <6>[ 3.159546] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10653 12:15:15.521393 <6>[ 3.166650] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10654 12:15:15.527994 <6>[ 3.173942] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10655 12:15:15.537703 <6>[ 3.180842] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10656 12:15:15.544544 <6>[ 3.189982] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10657 12:15:15.554254 <6>[ 3.199113] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10658 12:15:15.564390 <6>[ 3.208416] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10659 12:15:15.573935 <6>[ 3.217891] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10660 12:15:15.583995 <6>[ 3.227365] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10661 12:15:15.593834 <6>[ 3.236493] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10662 12:15:15.600312 <6>[ 3.245991] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10663 12:15:15.610178 <6>[ 3.255118] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10664 12:15:15.619949 <6>[ 3.264420] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10665 12:15:15.630167 <6>[ 3.274587] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10666 12:15:15.641253 <6>[ 3.286580] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10667 12:15:15.661925 <6>[ 3.307039] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10668 12:15:15.689040 <6>[ 3.337558] hub 2-1:1.0: USB hub found
10669 12:15:15.692147 <6>[ 3.341962] hub 2-1:1.0: 3 ports detected
10670 12:15:15.813418 <6>[ 3.458997] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10671 12:15:15.967545 <6>[ 3.616361] hub 1-1:1.0: USB hub found
10672 12:15:15.971047 <6>[ 3.620816] hub 1-1:1.0: 4 ports detected
10673 12:15:16.050031 <6>[ 3.695244] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10674 12:15:16.293445 <6>[ 3.939023] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10675 12:15:16.426749 <6>[ 4.075227] hub 1-1.4:1.0: USB hub found
10676 12:15:16.429700 <6>[ 4.079908] hub 1-1.4:1.0: 2 ports detected
10677 12:15:16.725533 <6>[ 4.370996] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10678 12:15:16.917723 <6>[ 4.563001] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10679 12:15:27.942113 <6>[ 15.595549] ALSA device list:
10680 12:15:27.948622 <6>[ 15.598806] No soundcards found.
10681 12:15:27.961479 <6>[ 15.611226] Freeing unused kernel memory: 8384K
10682 12:15:27.964505 <6>[ 15.616139] Run /init as init process
10683 12:15:27.994574 <6>[ 15.644761] NET: Registered PF_INET6 protocol family
10684 12:15:28.001012 <6>[ 15.651278] Segment Routing with IPv6
10685 12:15:28.004703 <6>[ 15.655237] In-situ OAM (IOAM) with IPv6
10686 12:15:28.039183 <30>[ 15.669643] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10687 12:15:28.042664 <30>[ 15.693706] systemd[1]: Detected architecture arm64.
10688 12:15:28.046079
10689 12:15:28.049414 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10690 12:15:28.049494
10691 12:15:28.064817 <30>[ 15.715104] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10692 12:15:28.209445 <30>[ 15.856430] systemd[1]: Queued start job for default target Graphical Interface.
10693 12:15:28.242126 <30>[ 15.892319] systemd[1]: Created slice system-getty.slice.
10694 12:15:28.248626 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10695 12:15:28.265586 <30>[ 15.915606] systemd[1]: Created slice system-modprobe.slice.
10696 12:15:28.272249 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10697 12:15:28.292615 <30>[ 15.939557] systemd[1]: Created slice system-serial\x2dgetty.slice.
10698 12:15:28.299323 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10699 12:15:28.313872 <30>[ 15.964035] systemd[1]: Created slice User and Session Slice.
10700 12:15:28.320539 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10701 12:15:28.340530 <30>[ 15.987531] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10702 12:15:28.350777 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10703 12:15:28.368946 <30>[ 16.015513] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10704 12:15:28.375428 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10705 12:15:28.395764 <30>[ 16.039091] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10706 12:15:28.401963 <30>[ 16.051125] systemd[1]: Reached target Local Encrypted Volumes.
10707 12:15:28.408530 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10708 12:15:28.425137 <30>[ 16.075357] systemd[1]: Reached target Paths.
10709 12:15:28.428660 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10710 12:15:28.444979 <30>[ 16.095029] systemd[1]: Reached target Remote File Systems.
10711 12:15:28.451591 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10712 12:15:28.464890 <30>[ 16.115017] systemd[1]: Reached target Slices.
10713 12:15:28.471507 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10714 12:15:28.484692 <30>[ 16.135044] systemd[1]: Reached target Swap.
10715 12:15:28.488051 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10716 12:15:28.508254 <30>[ 16.155346] systemd[1]: Listening on initctl Compatibility Named Pipe.
10717 12:15:28.515293 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10718 12:15:28.521531 <30>[ 16.170074] systemd[1]: Listening on Journal Audit Socket.
10719 12:15:28.528223 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10720 12:15:28.541115 <30>[ 16.191298] systemd[1]: Listening on Journal Socket (/dev/log).
10721 12:15:28.547859 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10722 12:15:28.565195 <30>[ 16.215311] systemd[1]: Listening on Journal Socket.
10723 12:15:28.571981 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10724 12:15:28.588628 <30>[ 16.235338] systemd[1]: Listening on Network Service Netlink Socket.
10725 12:15:28.594813 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10726 12:15:28.609465 <30>[ 16.259778] systemd[1]: Listening on udev Control Socket.
10727 12:15:28.616040 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10728 12:15:28.633415 <30>[ 16.283706] systemd[1]: Listening on udev Kernel Socket.
10729 12:15:28.640169 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10730 12:15:28.677230 <30>[ 16.327226] systemd[1]: Mounting Huge Pages File System...
10731 12:15:28.683798 Mounting [0;1;39mHuge Pages File System[0m...
10732 12:15:28.698781 <30>[ 16.348879] systemd[1]: Mounting POSIX Message Queue File System...
10733 12:15:28.705717 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10734 12:15:28.756916 <30>[ 16.407157] systemd[1]: Mounting Kernel Debug File System...
10735 12:15:28.763481 Mounting [0;1;39mKernel Debug File System[0m...
10736 12:15:28.780374 <30>[ 16.427209] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10737 12:15:28.791340 <30>[ 16.438020] systemd[1]: Starting Create list of static device nodes for the current kernel...
10738 12:15:28.797787 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10739 12:15:28.814966 <30>[ 16.465088] systemd[1]: Starting Load Kernel Module configfs...
10740 12:15:28.821514 Starting [0;1;39mLoad Kernel Module configfs[0m...
10741 12:15:28.839065 <30>[ 16.489196] systemd[1]: Starting Load Kernel Module drm...
10742 12:15:28.845315 Starting [0;1;39mLoad Kernel Module drm[0m...
10743 12:15:28.864561 <30>[ 16.511178] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10744 12:15:28.874617 <30>[ 16.524782] systemd[1]: Starting Journal Service...
10745 12:15:28.878066 Starting [0;1;39mJournal Service[0m...
10746 12:15:28.895291 <30>[ 16.545545] systemd[1]: Starting Load Kernel Modules...
10747 12:15:28.901770 Starting [0;1;39mLoad Kernel Modules[0m...
10748 12:15:28.922893 <30>[ 16.569607] systemd[1]: Starting Remount Root and Kernel File Systems...
10749 12:15:28.929033 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10750 12:15:28.943149 <30>[ 16.593469] systemd[1]: Starting Coldplug All udev Devices...
10751 12:15:28.949892 Starting [0;1;39mColdplug All udev Devices[0m...
10752 12:15:28.967755 <30>[ 16.617625] systemd[1]: Mounted Huge Pages File System.
10753 12:15:28.974292 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10754 12:15:28.989662 <30>[ 16.639668] systemd[1]: Started Journal Service.
10755 12:15:28.995796 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10756 12:15:29.010902 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10757 12:15:29.025796 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10758 12:15:29.045436 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10759 12:15:29.062565 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10760 12:15:29.078768 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10761 12:15:29.094166 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10762 12:15:29.113848 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10763 12:15:29.129149 See 'systemctl status systemd-remount-fs.service' for details.
10764 12:15:29.186016 Mounting [0;1;39mKernel Configuration File System[0m...
10765 12:15:29.203279 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10766 12:15:29.220491 <46>[ 16.867658] systemd-journald[176]: Received client request to flush runtime journal.
10767 12:15:29.229479 Starting [0;1;39mLoad/Save Random Seed[0m...
10768 12:15:29.251676 Starting [0;1;39mApply Kernel Variables[0m...
10769 12:15:29.272137 Starting [0;1;39mCreate System Users[0m...
10770 12:15:29.294101 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10771 12:15:29.317410 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10772 12:15:29.330114 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10773 12:15:29.345907 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10774 12:15:29.361683 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10775 12:15:29.381689 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10776 12:15:29.437632 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10777 12:15:29.459863 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10778 12:15:29.473525 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10779 12:15:29.493038 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10780 12:15:29.533527 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10781 12:15:29.556531 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10782 12:15:29.577870 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10783 12:15:29.600920 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10784 12:15:29.646312 Starting [0;1;39mNetwork Service[0m...
10785 12:15:29.670032 Starting [0;1;39mNetwork Time Synchronization[0m...
10786 12:15:29.688709 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10787 12:15:29.723146 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10788 12:15:29.752710 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10789 12:15:29.787353 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10790 12:15:29.808741 <6>[ 17.455638] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10791 12:15:29.821279 <6>[ 17.471671] remoteproc remoteproc0: scp is available
10792 12:15:29.827944 <6>[ 17.477872] remoteproc remoteproc0: powering up scp
10793 12:15:29.838089 <6>[ 17.483273] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10794 12:15:29.841274 <6>[ 17.491789] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10795 12:15:29.851321 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10796 12:15:29.861567 <3>[ 17.508558] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10797 12:15:29.868272 <3>[ 17.516712] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10798 12:15:29.877992 <3>[ 17.524962] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10799 12:15:29.884811 <6>[ 17.533670] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10800 12:15:29.894577 <6>[ 17.541289] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10801 12:15:29.904293 <3>[ 17.549914] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10802 12:15:29.911143 <6>[ 17.550134] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10803 12:15:29.920745 <3>[ 17.558143] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10804 12:15:29.927456 <6>[ 17.565638] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10805 12:15:29.937608 <4>[ 17.580572] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10806 12:15:29.940646 <4>[ 17.580572] Fallback method does not support PEC.
10807 12:15:29.950697 <3>[ 17.582567] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10808 12:15:29.954224 <6>[ 17.602333] mc: Linux media interface: v0.10
10809 12:15:29.960925 <3>[ 17.604376] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10810 12:15:29.971000 <3>[ 17.612243] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10811 12:15:29.977302 <3>[ 17.617035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10812 12:15:29.987152 <6>[ 17.622954] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10813 12:15:29.993811 <6>[ 17.622958] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10814 12:15:30.000516 <6>[ 17.622962] remoteproc remoteproc0: remote processor scp is now up
10815 12:15:30.007124 <6>[ 17.627397] videodev: Linux video capture interface: v2.00
10816 12:15:30.014286 <3>[ 17.635052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 12:15:30.021388 <4>[ 17.635209] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10818 12:15:30.027517 <4>[ 17.635412] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10819 12:15:30.034273 <6>[ 17.664133] usbcore: registered new interface driver r8152
10820 12:15:30.044164 <3>[ 17.676203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10821 12:15:30.050847 <3>[ 17.685283] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10822 12:15:30.060629 <3>[ 17.690630] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 12:15:30.067391 <3>[ 17.698795] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10824 12:15:30.077266 <3>[ 17.707376] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10825 12:15:30.084037 <6>[ 17.719134] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10826 12:15:30.090442 <3>[ 17.735027] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10827 12:15:30.097784 <3>[ 17.741868] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10828 12:15:30.104316 <6>[ 17.743647] pci_bus 0000:00: root bus resource [bus 00-ff]
10829 12:15:30.111049 <6>[ 17.743656] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10830 12:15:30.120757 <6>[ 17.743661] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10831 12:15:30.127310 <6>[ 17.743709] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10832 12:15:30.134314 <6>[ 17.743730] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10833 12:15:30.140922 <6>[ 17.743817] pci 0000:00:00.0: supports D1 D2
10834 12:15:30.147358 <6>[ 17.743821] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10835 12:15:30.154118 <6>[ 17.746162] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10836 12:15:30.164014 <3>[ 17.751828] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 12:15:30.170222 <3>[ 17.753820] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 12:15:30.180106 <3>[ 17.753835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 12:15:30.186809 <3>[ 17.753847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10840 12:15:30.197362 <3>[ 17.753858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10841 12:15:30.206967 <6>[ 17.771307] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10842 12:15:30.214006 <3>[ 17.790315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10843 12:15:30.220717 <6>[ 17.795357] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10844 12:15:30.230566 <6>[ 17.796497] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10845 12:15:30.237106 <6>[ 17.803678] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10846 12:15:30.246865 <6>[ 17.810509] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10847 12:15:30.253834 <6>[ 17.815140] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10848 12:15:30.260723 <6>[ 17.821147] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10849 12:15:30.267238 <6>[ 17.827353] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10850 12:15:30.277114 <4>[ 17.837922] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10851 12:15:30.283775 <6>[ 17.843521] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10852 12:15:30.290429 <3>[ 17.843796] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10853 12:15:30.300151 <4>[ 17.851612] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10854 12:15:30.306951 <3>[ 17.859195] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10855 12:15:30.313633 <6>[ 17.861788] pci 0000:01:00.0: supports D1 D2
10856 12:15:30.320135 <3>[ 17.872808] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 12:15:30.326634 <6>[ 17.876043] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10858 12:15:30.337405 <3>[ 17.914989] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 12:15:30.343659 <3>[ 17.919119] power_supply sbs-5-000b: driver failed to report `energy_full' property: -6
10860 12:15:30.347342 <6>[ 17.926873] r8152 2-1.3:1.0 eth0: v1.12.13
10861 12:15:30.357385 <6>[ 17.932828] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10862 12:15:30.360870 <3>[ 17.951106] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10863 12:15:30.371110 <6>[ 17.954841] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10864 12:15:30.377501 <3>[ 17.963404] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10865 12:15:30.384520 <6>[ 17.967308] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10866 12:15:30.394723 <6>[ 17.976357] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10867 12:15:30.401543 <6>[ 17.983109] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10868 12:15:30.412112 <3>[ 18.007104] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 12:15:30.418775 <6>[ 18.011291] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10870 12:15:30.424967 <6>[ 18.018380] usbcore: registered new interface driver cdc_ether
10871 12:15:30.435147 <3>[ 18.021887] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 12:15:30.442167 <6>[ 18.025857] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10873 12:15:30.448629 <6>[ 18.025883] pci 0000:00:00.0: PCI bridge to [bus 01]
10874 12:15:30.452304 <6>[ 18.027334] Bluetooth: Core ver 2.22
10875 12:15:30.458508 <6>[ 18.027464] NET: Registered PF_BLUETOOTH protocol family
10876 12:15:30.462112 <6>[ 18.027471] Bluetooth: HCI device and connection manager initialized
10877 12:15:30.468907 <6>[ 18.027523] Bluetooth: HCI socket layer initialized
10878 12:15:30.475410 <6>[ 18.027535] Bluetooth: L2CAP socket layer initialized
10879 12:15:30.479020 <6>[ 18.027553] Bluetooth: SCO socket layer initialized
10880 12:15:30.485735 <6>[ 18.041273] usbcore: registered new interface driver r8153_ecm
10881 12:15:30.492550 <6>[ 18.042521] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10882 12:15:30.506153 <6>[ 18.044427] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10883 12:15:30.509800 <6>[ 18.044566] usbcore: registered new interface driver uvcvideo
10884 12:15:30.519614 <6>[ 18.049961] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10885 12:15:30.526362 <6>[ 18.050300] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10886 12:15:30.532853 <6>[ 18.069103] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10887 12:15:30.536360 <6>[ 18.071218] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10888 12:15:30.542683 <6>[ 18.076506] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10889 12:15:30.549262 <6>[ 18.081898] usbcore: registered new interface driver btusb
10890 12:15:30.558942 <4>[ 18.082391] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10891 12:15:30.565541 <3>[ 18.082406] Bluetooth: hci0: Failed to load firmware file (-2)
10892 12:15:30.572415 <3>[ 18.082409] Bluetooth: hci0: Failed to set up firmware (-2)
10893 12:15:30.582316 <4>[ 18.082413] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10894 12:15:30.588784 <6>[ 18.090196] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10895 12:15:30.595532 Starting [0;1;39mNetwork Name Resolution[0m...
10896 12:15:30.610895 <5>[ 18.258122] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10897 12:15:30.617723 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10898 12:15:30.632451 <5>[ 18.279647] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10899 12:15:30.642648 [[0;32m OK [<4>[ 18.288471] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10900 12:15:30.649078 0m] Started [0;<6>[ 18.298282] cfg80211: failed to load regulatory.db
10901 12:15:30.652476 1;39mNetwork Name Resolution[0m.
10902 12:15:30.674464 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10903 12:15:30.692579 <6>[ 18.339675] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10904 12:15:30.699407 <6>[ 18.347223] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10905 12:15:30.702524 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10906 12:15:30.723730 <6>[ 18.374026] mt7921e 0000:01:00.0: ASIC revision: 79610010
10907 12:15:30.830627 <4>[ 18.474455] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10908 12:15:30.876421 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10909 12:15:30.897057 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10910 12:15:30.915823 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10911 12:15:30.931843 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10912 12:15:30.949358 <4>[ 18.593164] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10913 12:15:30.955973 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10914 12:15:30.963520 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10915 12:15:30.970029 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10916 12:15:30.988693 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10917 12:15:31.000892 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10918 12:15:31.020314 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10919 12:15:31.033061 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10920 12:15:31.048589 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10921 12:15:31.069579 <4>[ 18.713288] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10922 12:15:31.079368 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10923 12:15:31.121121 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10924 12:15:31.147398 Starting [0;1;39mUser Login Management[0m...
10925 12:15:31.162830 Starting [0;1;39mPermit User Sessions[0m...
10926 12:15:31.193304 Startin<4>[ 18.837909] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10927 12:15:31.199708 g [0;1;39mLoad/Save RF Kill Switch Status[0m...
10928 12:15:31.207616 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10929 12:15:31.215713 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10930 12:15:31.239823 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10931 12:15:31.259428 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10932 12:15:31.280827 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10933 12:15:31.303862 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10934 12:15:31.321385 <4>[ 18.965488] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10935 12:15:31.328962 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10936 12:15:31.348864 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10937 12:15:31.392576 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10938 12:15:31.416579 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10939 12:15:31.442954 <4>[ 19.086937] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10940 12:15:31.443053
10941 12:15:31.443124
10942 12:15:31.450002 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10943 12:15:31.450088
10944 12:15:31.453115 debian-bullseye-arm64 login: root (automatic login)
10945 12:15:31.453201
10946 12:15:31.453272
10947 12:15:31.476001 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023 aarch64
10948 12:15:31.476095
10949 12:15:31.482680 The programs included with the Debian GNU/Linux system are free software;
10950 12:15:31.488991 the exact distribution terms for each program are described in the
10951 12:15:31.492491 individual files in /usr/share/doc/*/copyright.
10952 12:15:31.492574
10953 12:15:31.499114 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10954 12:15:31.502239 permitted by applicable law.
10955 12:15:31.502579 Matched prompt #10: / #
10957 12:15:31.502852 Setting prompt string to ['/ #']
10958 12:15:31.502954 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10960 12:15:31.503154 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10961 12:15:31.503240 start: 2.2.6 expect-shell-connection (timeout 00:03:31) [common]
10962 12:15:31.503313 Setting prompt string to ['/ #']
10963 12:15:31.503376 Forcing a shell prompt, looking for ['/ #']
10965 12:15:31.553568 / #
10966 12:15:31.553704 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10967 12:15:31.553817 Waiting using forced prompt support (timeout 00:02:30)
10968 12:15:31.565553 <4>[ 19.209367] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10969 12:15:31.565640
10970 12:15:31.569274 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10971 12:15:31.569383 start: 2.2.7 export-device-env (timeout 00:03:31) [common]
10972 12:15:31.569482 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10973 12:15:31.569572 end: 2.2 depthcharge-retry (duration 00:01:29) [common]
10974 12:15:31.569659 end: 2 depthcharge-action (duration 00:01:29) [common]
10975 12:15:31.569747 start: 3 lava-test-retry (timeout 00:08:11) [common]
10976 12:15:31.569832 start: 3.1 lava-test-shell (timeout 00:08:11) [common]
10977 12:15:31.569905 Using namespace: common
10979 12:15:31.670187 / # #
10980 12:15:31.670338 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10981 12:15:31.674988 #
10982 12:15:31.684729 <4>[ 19.329515] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10983 12:15:31.685012 Using /lava-10605413
10985 12:15:31.785318 / # export SHELL=/bin/sh
10986 12:15:31.790597 export SHELL=/bin/sh
10988 12:15:31.891058 / # . /lava-10605413/environment
10989 12:15:31.891221 <4>[ 19.448976] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10990 12:15:31.896274 . /lava-10605413/environment
10992 12:15:31.996792 / # /lava-10605413/bin/lava-test-runner /lava-10605413/0
10993 12:15:31.997009 Test shell timeout: 10s (minimum of the action and connection timeout)
10994 12:15:31.997439 <6>[ 19.562013] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
10995 12:15:31.997525 <4>[ 19.569997] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10996 12:15:31.997608 <6>[ 19.570286] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10997 12:15:32.001800 /lava-10605413/bin/lava-test-runner /lava-10605413/0
10998 12:15:32.044875 + export TESTRUN_ID=0_v4l2-compliance-uvc
10999 12:15:32.044994 + cd /lava-10605413/0/tests/0_v4l2-compliance-uvc
11000 12:15:32.045066 + cat uuid
11001 12:15:32.045130 + UUID=10605413_1.5.2.3.1
11002 12:15:32.045192 + set +x
11003 12:15:32.045429 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 10605413_1.5.2.3.1>
11004 12:15:32.045494 + <3>[ 19.692242] mt7921e 0000:01:00.0: hardware init failed
11005 12:15:32.045741 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 10605413_1.5.2.3.1
11006 12:15:32.045816 Starting test lava.0_v4l2-compliance-uvc (10605413_1.5.2.3.1)
11007 12:15:32.045899 Skipping test definition patterns.
11008 12:15:32.046898 /usr/bin/v4l2-parser.sh -d uvcvideo
11009 12:15:32.050157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11010 12:15:32.050424 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11012 12:15:32.053031 device: /dev/video0
11013 12:15:36.123017 <4>[ 23.774029] ------------[ cut here ]------------
11014 12:15:36.129868 <4>[ 23.778926] get_vaddr_frames() cannot follow VM_IO mapping
11015 12:15:36.139548 <4>[ 23.779071] WARNING: CPU: 6 PID: 308 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11016 12:15:36.189057 <4>[ 23.797172] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 btusb btintel mtk_vcodec_enc btmtk mtk_vcodec_common btrtl r8153_ecm btbcm uvcvideo mtk_vpu v4l2_mem2mem videobuf2_vmalloc videobuf2_dma_contig bluetooth videobuf2_memops cdc_ether usbnet videobuf2_v4l2 ecdh_generic cros_ec_rpmsg ecc videobuf2_common elan_i2c rfkill r8152 crct10dif_ce elants_i2c videodev mc cros_ec_chardev pcie_mediatek_gen3 hid_google_hammer cros_ec_typec sbs_battery hid_vivaldi_common mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11017 12:15:36.198742 <4>[ 23.846560] CPU: 6 PID: 308 Comm: v4l2-compliance Not tainted 6.1.31 #1
11018 12:15:36.202283 <4>[ 23.853426] Hardware name: Google Spherion (rev0 - 3) (DT)
11019 12:15:36.208645 <4>[ 23.859161] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11020 12:15:36.215446 <4>[ 23.866375] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11021 12:15:36.222241 <4>[ 23.872473] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11022 12:15:36.225459 <4>[ 23.878568] sp : ffff800009133810
11023 12:15:36.232363 <4>[ 23.882133] x29: ffff800009133810 x28: ffffc6d6756de000 x27: ffffc6d6756da238
11024 12:15:36.242020 <4>[ 23.889522] x26: 0000000000000000 x25: ffffc6d6756de4c0 x24: ffff19e20b968538
11025 12:15:36.248775 <4>[ 23.896910] x23: 00000000001c2000 x22: 0000000000000000 x21: 0000000000000000
11026 12:15:36.255314 <4>[ 23.904298] x20: 00000000fffffff2 x19: ffff19e20e1b5000 x18: fffffffffffe9630
11027 12:15:36.261610 <4>[ 23.911685] x17: 0000000000000000 x16: ffffc6d6c268bb60 x15: 0000000000000038
11028 12:15:36.271858 <4>[ 23.919073] x14: ffffc6d6c4dc34a8 x13: 0000000000000642 x12: 0000000000000216
11029 12:15:36.278204 <4>[ 23.926461] x11: fffffffffffe9630 x10: fffffffffffe95f8 x9 : 00000000fffff216
11030 12:15:36.284923 <4>[ 23.933848] x8 : ffffc6d6c4dc34a8 x7 : ffffc6d6c4e1b4a8 x6 : 0000000000001908
11031 12:15:36.291375 <4>[ 23.941234] x5 : ffff19e33ef90a18 x4 : 00000000fffff216 x3 : ffff530c7a88d000
11032 12:15:36.301686 <4>[ 23.948621] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff19e20e750ec0
11033 12:15:36.301770 <4>[ 23.956009] Call trace:
11034 12:15:36.308156 <4>[ 23.958705] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11035 12:15:36.314874 <4>[ 23.964454] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11036 12:15:36.321304 <4>[ 23.970460] vb2_vmalloc_get_userptr+0x60/0x1a0 [videobuf2_vmalloc]
11037 12:15:36.328051 <4>[ 23.976988] __prepare_userptr+0x280/0x410 [videobuf2_common]
11038 12:15:36.331205 <4>[ 23.982998] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11039 12:15:36.337928 <4>[ 23.988660] vb2_core_qbuf+0x3c8/0x5e0 [videobuf2_common]
11040 12:15:36.344413 <4>[ 23.994322] vb2_qbuf+0x90/0xf0 [videobuf2_v4l2]
11041 12:15:36.348026 <4>[ 23.999212] uvc_queue_buffer+0x3c/0x60 [uvcvideo]
11042 12:15:36.354291 <4>[ 24.004281] uvc_ioctl_qbuf+0x2c/0x40 [uvcvideo]
11043 12:15:36.357783 <4>[ 24.009163] v4l_qbuf+0x48/0x60 [videodev]
11044 12:15:36.364428 <4>[ 24.013586] __video_do_ioctl+0x184/0x3d0 [videodev]
11045 12:15:36.367534 <4>[ 24.018837] video_usercopy+0x358/0x680 [videodev]
11046 12:15:36.374445 <4>[ 24.023914] video_ioctl2+0x18/0x30 [videodev]
11047 12:15:36.377315 <4>[ 24.028642] v4l2_ioctl+0x40/0x60 [videodev]
11048 12:15:36.380991 <4>[ 24.033198] __arm64_sys_ioctl+0xa8/0xf0
11049 12:15:36.384194 <4>[ 24.037379] invoke_syscall+0x48/0x114
11050 12:15:36.390716 <4>[ 24.041386] el0_svc_common.constprop.0+0x44/0xec
11051 12:15:36.394197 <4>[ 24.046344] do_el0_svc+0x2c/0xd0
11052 12:15:36.397218 <4>[ 24.049913] el0_svc+0x2c/0x84
11053 12:15:36.400583 <4>[ 24.053226] el0t_64_sync_handler+0xb8/0xc0
11054 12:15:36.403948 <4>[ 24.057661] el0t_64_sync+0x18c/0x190
11055 12:15:36.410460 <4>[ 24.061576] ---[ end trace 0000000000000000 ]---
11056 12:15:38.830363 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11057 12:15:38.840517 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11058 12:15:38.845592
11059 12:15:38.857387 Compliance test for uvcvideo device /dev/video0:
11060 12:15:38.863663
11061 12:15:38.872743 Driver Info:
11062 12:15:38.882927 Driver name : uvcvideo
11063 12:15:38.895503 Card type : HD User Facing: HD User Facing
11064 12:15:38.904611 Bus info : usb-11200000.usb-1.4.1
11065 12:15:38.910668 Driver version : 6.1.31
11066 12:15:38.921200 Capabilities : 0x84a00001
11067 12:15:38.932611 Metadata Capture
11068 12:15:38.942566 Streaming
11069 12:15:38.952630 Extended Pix Format
11070 12:15:38.962268 Device Capabilities
11071 12:15:38.972507 Device Caps : 0x04200001
11072 12:15:38.983210 Streaming
11073 12:15:38.993468 Extended Pix Format
11074 12:15:39.003279 Media Driver Info:
11075 12:15:39.012598 Driver name : uvcvideo
11076 12:15:39.024761 Model : HD User Facing: HD User Facing
11077 12:15:39.031107 Serial : 200901010001
11078 12:15:39.043844 Bus info : usb-11200000.usb-1.4.1
11079 12:15:39.049762 Media version : 6.1.31
11080 12:15:39.062786 Hardware revision: 0x00009758 (38744)
11081 12:15:39.069363 Driver version : 6.1.31
11082 12:15:39.079683 Interface Info:
11083 12:15:39.093814 <LAVA_SIGNAL_TESTSET START Interface-Info>
11084 12:15:39.093899 ID : 0x03000002
11085 12:15:39.094166 Received signal: <TESTSET> START Interface-Info
11086 12:15:39.094246 Starting test_set Interface-Info
11087 12:15:39.104046 Type : V4L Video
11088 12:15:39.114755 Entity Info:
11089 12:15:39.121777 <LAVA_SIGNAL_TESTSET STOP>
11090 12:15:39.122031 Received signal: <TESTSET> STOP
11091 12:15:39.122106 Closing test_set Interface-Info
11092 12:15:39.131486 <LAVA_SIGNAL_TESTSET START Entity-Info>
11093 12:15:39.131741 Received signal: <TESTSET> START Entity-Info
11094 12:15:39.131814 Starting test_set Entity-Info
11095 12:15:39.134340 ID : 0x00000001 (1)
11096 12:15:39.144464 Name : HD User Facing: HD User Facing
11097 12:15:39.151087 Function : V4L2 I/O
11098 12:15:39.160955 Flags : default
11099 12:15:39.170554 Pad 0x01000007 : 0: Sink
11100 12:15:39.189827 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11101 12:15:39.189912
11102 12:15:39.199241 Required ioctls:
11103 12:15:39.205968 <LAVA_SIGNAL_TESTSET STOP>
11104 12:15:39.206223 Received signal: <TESTSET> STOP
11105 12:15:39.206293 Closing test_set Entity-Info
11106 12:15:39.214753 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11107 12:15:39.215006 Received signal: <TESTSET> START Required-ioctls
11108 12:15:39.215077 Starting test_set Required-ioctls
11109 12:15:39.218365 test MC information (see 'Media Driver Info' above): OK
11110 12:15:39.242598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11111 12:15:39.242866 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11113 12:15:39.245961 test VIDIOC_QUERYCAP: OK
11114 12:15:39.263085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11115 12:15:39.263355 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11117 12:15:39.265986 test invalid ioctls: OK
11118 12:15:39.286560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11119 12:15:39.286644
11120 12:15:39.286877 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11122 12:15:39.296653 Allow for multiple opens:
11123 12:15:39.303983 <LAVA_SIGNAL_TESTSET STOP>
11124 12:15:39.304250 Received signal: <TESTSET> STOP
11125 12:15:39.304334 Closing test_set Required-ioctls
11126 12:15:39.313265 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11127 12:15:39.313515 Received signal: <TESTSET> START Allow-for-multiple-opens
11128 12:15:39.313583 Starting test_set Allow-for-multiple-opens
11129 12:15:39.316758 test second /dev/video0 open: OK
11130 12:15:39.338294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11131 12:15:39.338605 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11133 12:15:39.341466 test VIDIOC_QUERYCAP: OK
11134 12:15:39.361919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11135 12:15:39.362234 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11137 12:15:39.365288 test VIDIOC_G/S_PRIORITY: OK
11138 12:15:39.386453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11139 12:15:39.386706 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11141 12:15:39.390088 test for unlimited opens: OK
11142 12:15:39.410304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11143 12:15:39.410388
11144 12:15:39.410636 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11146 12:15:39.420544 Debug ioctls:
11147 12:15:39.427889 <LAVA_SIGNAL_TESTSET STOP>
11148 12:15:39.428140 Received signal: <TESTSET> STOP
11149 12:15:39.428213 Closing test_set Allow-for-multiple-opens
11150 12:15:39.437511 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11151 12:15:39.437762 Received signal: <TESTSET> START Debug-ioctls
11152 12:15:39.437831 Starting test_set Debug-ioctls
11153 12:15:39.440920 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11154 12:15:39.461926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11155 12:15:39.462178 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11157 12:15:39.468259 test VIDIOC_LOG_STATUS: OK (Not Supported)
11158 12:15:39.485078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11159 12:15:39.485161
11160 12:15:39.485393 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11162 12:15:39.495354 Input ioctls:
11163 12:15:39.502581 <LAVA_SIGNAL_TESTSET STOP>
11164 12:15:39.502835 Received signal: <TESTSET> STOP
11165 12:15:39.502909 Closing test_set Debug-ioctls
11166 12:15:39.511125 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11167 12:15:39.511380 Received signal: <TESTSET> START Input-ioctls
11168 12:15:39.511456 Starting test_set Input-ioctls
11169 12:15:39.514228 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11170 12:15:39.538787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11171 12:15:39.539043 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11173 12:15:39.542194 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11174 12:15:39.559196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11175 12:15:39.559451 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11177 12:15:39.565337 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11178 12:15:39.582879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11179 12:15:39.583135 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11181 12:15:39.589176 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11182 12:15:39.606990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11183 12:15:39.607243 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11185 12:15:39.610154 test VIDIOC_G/S/ENUMINPUT: OK
11186 12:15:39.632898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11187 12:15:39.633150 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11189 12:15:39.636004 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11190 12:15:39.657491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11191 12:15:39.657758 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11193 12:15:39.661032 Inputs: 1 Audio Inputs: 0 Tuners: 0
11194 12:15:39.668203
11195 12:15:39.684508 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11196 12:15:39.705671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11197 12:15:39.705926 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11199 12:15:39.712369 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11200 12:15:39.729812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11201 12:15:39.730065 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11203 12:15:39.736059 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11204 12:15:39.754322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11205 12:15:39.754575 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11207 12:15:39.761017 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11208 12:15:39.778204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11209 12:15:39.778458 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11211 12:15:39.784736 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11212 12:15:39.802127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11213 12:15:39.802229
11214 12:15:39.802495 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11216 12:15:39.821608 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11217 12:15:39.842170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11218 12:15:39.842422 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11220 12:15:39.848670 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11221 12:15:39.870014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11222 12:15:39.870269 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11224 12:15:39.873678 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11225 12:15:39.892422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11226 12:15:39.892675 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11228 12:15:39.895464 test VIDIOC_G/S_EDID: OK (Not Supported)
11229 12:15:39.916975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11230 12:15:39.917061
11231 12:15:39.917294 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11233 12:15:39.926740 Control ioctls (Input 0):
11234 12:15:39.933982 <LAVA_SIGNAL_TESTSET STOP>
11235 12:15:39.934235 Received signal: <TESTSET> STOP
11236 12:15:39.934307 Closing test_set Input-ioctls
11237 12:15:39.942975 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11238 12:15:39.943255 Received signal: <TESTSET> START Control-ioctls-Input-0
11239 12:15:39.943352 Starting test_set Control-ioctls-Input-0
11240 12:15:39.946471 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11241 12:15:39.969668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11242 12:15:39.969770 test VIDIOC_QUERYCTRL: OK
11243 12:15:39.970016 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11245 12:15:39.990801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11246 12:15:39.991054 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11248 12:15:39.994012 test VIDIOC_G/S_CTRL: OK
11249 12:15:40.013878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11250 12:15:40.014163 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11252 12:15:40.017460 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11253 12:15:40.037372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11254 12:15:40.037626 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11256 12:15:40.043583 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11257 12:15:40.063763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11258 12:15:40.064023 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11260 12:15:40.066954 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11261 12:15:40.086414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11262 12:15:40.086669 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11264 12:15:40.089740 Standard Controls: 16 Private Controls: 0
11265 12:15:40.097307
11266 12:15:40.107158 Format ioctls (Input 0):
11267 12:15:40.114617 <LAVA_SIGNAL_TESTSET STOP>
11268 12:15:40.114899 Received signal: <TESTSET> STOP
11269 12:15:40.115005 Closing test_set Control-ioctls-Input-0
11270 12:15:40.124072 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11271 12:15:40.124323 Received signal: <TESTSET> START Format-ioctls-Input-0
11272 12:15:40.124484 Starting test_set Format-ioctls-Input-0
11273 12:15:40.127431 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11274 12:15:40.153027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11275 12:15:40.153287 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11277 12:15:40.155868 test VIDIOC_G/S_PARM: OK
11278 12:15:40.173732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11279 12:15:40.174010 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11281 12:15:40.177266 test VIDIOC_G_FBUF: OK (Not Supported)
11282 12:15:40.198675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11283 12:15:40.198955 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11285 12:15:40.201857 test VIDIOC_G_FMT: OK
11286 12:15:40.224045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11287 12:15:40.224296 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11289 12:15:40.227300 test VIDIOC_TRY_FMT: OK
11290 12:15:40.249545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11291 12:15:40.249797 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11293 12:15:40.255686 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11294 12:15:40.260308 test VIDIOC_S_FMT: OK
11295 12:15:40.284976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11296 12:15:40.285228 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11298 12:15:40.288101 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11299 12:15:40.309825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11300 12:15:40.310104 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11302 12:15:40.313588 test Cropping: OK (Not Supported)
11303 12:15:40.333379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11304 12:15:40.333655 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11306 12:15:40.336771 test Composing: OK (Not Supported)
11307 12:15:40.357460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11308 12:15:40.357738 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11310 12:15:40.360913 test Scaling: OK (Not Supported)
11311 12:15:40.381842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11312 12:15:40.381963
11313 12:15:40.382228 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11315 12:15:40.393169 Codec ioctls (Input 0):
11316 12:15:40.400695 <LAVA_SIGNAL_TESTSET STOP>
11317 12:15:40.400981 Received signal: <TESTSET> STOP
11318 12:15:40.401051 Closing test_set Format-ioctls-Input-0
11319 12:15:40.410358 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11320 12:15:40.410632 Received signal: <TESTSET> START Codec-ioctls-Input-0
11321 12:15:40.410728 Starting test_set Codec-ioctls-Input-0
11322 12:15:40.413571 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11323 12:15:40.435353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11324 12:15:40.435641 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11326 12:15:40.442163 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11327 12:15:40.460453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11328 12:15:40.460730 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11330 12:15:40.466660 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11331 12:15:40.485136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11332 12:15:40.485232
11333 12:15:40.485470 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11335 12:15:40.495279 Buffer ioctls (Input 0):
11336 12:15:40.502516 <LAVA_SIGNAL_TESTSET STOP>
11337 12:15:40.502790 Received signal: <TESTSET> STOP
11338 12:15:40.502884 Closing test_set Codec-ioctls-Input-0
11339 12:15:40.511633 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11340 12:15:40.511907 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11341 12:15:40.512002 Starting test_set Buffer-ioctls-Input-0
11342 12:15:40.514739 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11343 12:15:40.538214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11344 12:15:40.538292 test VIDIOC_EXPBUF: OK
11345 12:15:40.538530 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11347 12:15:40.558280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11348 12:15:40.558530 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11350 12:15:40.561696 test Requests: OK (Not Supported)
11351 12:15:40.583901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11352 12:15:40.583987
11353 12:15:40.584221 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11355 12:15:40.593101 Test input 0:
11356 12:15:40.601739
11357 12:15:40.611370 Streaming ioctls:
11358 12:15:40.616978 <LAVA_SIGNAL_TESTSET STOP>
11359 12:15:40.617225 Received signal: <TESTSET> STOP
11360 12:15:40.617298 Closing test_set Buffer-ioctls-Input-0
11361 12:15:40.626304 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11362 12:15:40.626551 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11363 12:15:40.626627 Starting test_set Streaming-ioctls_Test-input-0
11364 12:15:40.629893 test read/write: OK (Not Supported)
11365 12:15:40.650861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11366 12:15:40.651140 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11368 12:15:40.653807 test blocking wait: OK
11369 12:15:40.674531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11370 12:15:40.674788 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11372 12:15:40.684372 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11373 12:15:40.687733 test MMAP (no poll): FAIL
11374 12:15:40.706632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11375 12:15:40.706883 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11377 12:15:40.716419 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11378 12:15:40.716524 test MMAP (select): FAIL
11379 12:15:40.741553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11380 12:15:40.741831 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11382 12:15:40.751450 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11383 12:15:40.751556 test MMAP (epoll): FAIL
11384 12:15:40.774480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11385 12:15:40.774587
11386 12:15:40.774860 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11388 12:15:40.786285
11389 12:15:40.946432
11390 12:15:40.953283 test USERPTR (no poll): OK
11391 12:15:40.977333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11392 12:15:40.977442
11393 12:15:40.977711 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11395 12:15:40.990860
11396 12:15:41.153675
11397 12:15:41.160313 test USERPTR (select): OK
11398 12:15:41.184613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11399 12:15:41.184921 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11401 12:15:41.191153 test DMABUF: Cannot test, specify --expbuf-device
11402 12:15:41.194408
11403 12:15:41.212389 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11404 12:15:41.215252 <LAVA_TEST_RUNNER EXIT>
11405 12:15:41.215525 ok: lava_test_shell seems to have completed
11406 12:15:41.215622 Marking unfinished test run as failed
11408 12:15:41.216922 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11409 12:15:41.217052 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11410 12:15:41.217138 end: 3 lava-test-retry (duration 00:00:10) [common]
11411 12:15:41.217231 start: 4 finalize (timeout 00:08:02) [common]
11412 12:15:41.217323 start: 4.1 power-off (timeout 00:00:30) [common]
11413 12:15:41.217486 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11414 12:15:41.291156 >> Command sent successfully.
11415 12:15:41.293558 Returned 0 in 0 seconds
11416 12:15:41.393939 end: 4.1 power-off (duration 00:00:00) [common]
11418 12:15:41.394384 start: 4.2 read-feedback (timeout 00:08:02) [common]
11419 12:15:41.394679 Listened to connection for namespace 'common' for up to 1s
11420 12:15:42.395635 Finalising connection for namespace 'common'
11421 12:15:42.395824 Disconnecting from shell: Finalise
11422 12:15:42.395912 / #
11423 12:15:42.496211 end: 4.2 read-feedback (duration 00:00:01) [common]
11424 12:15:42.496410 end: 4 finalize (duration 00:00:01) [common]
11425 12:15:42.496556 Cleaning after the job
11426 12:15:42.496682 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/ramdisk
11427 12:15:42.500965 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/kernel
11428 12:15:42.511641 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/dtb
11429 12:15:42.511837 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605413/tftp-deploy-wfkue_y5/modules
11430 12:15:42.516913 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605413
11431 12:15:42.573663 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605413
11432 12:15:42.573845 Job finished correctly