Boot log: qemu_arm64-virt-gicv3
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
- Errors: 0
1 13:36:45.545239 lava-dispatcher, installed at version: 2023.01
2 13:36:45.545425 start: 0 validate
3 13:36:45.545536 Start time: 2023-06-22 13:36:45.545530+00:00 (UTC)
4 13:36:45.546621 Validating that http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.31-61-g32a95f5a4e3b/arm64/defconfig/gcc-10/kernel/Image exists
5 13:36:45.915074 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/rootfs.cpio.gz exists
6 13:36:46.086183 cmd: ['docker', 'pull', 'kernelci/qemu']
7 13:36:46.086454 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 13:36:46.249137 >> Using default tag: latest
9 13:36:47.521361 >> latest: Pulling from kernelci/qemu
10 13:36:47.703458 >> Digest: sha256:89417f77b9e36ef1123db2a628e130c9901c22da31489be871c6c7baa349f1d8
11 13:36:47.703754 >> Status: Image is up to date for kernelci/qemu:latest
12 13:36:47.845099 >> docker.io/kernelci/qemu:latest
13 13:36:47.848072 Returned 0 in 1 seconds
14 13:36:47.986018 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 13:36:47.986396 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 13:36:50.792616 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 13:36:50.792979 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 13:36:51.980289 Returned 0 in 3 seconds
19 13:36:52.081580 validate duration: 6.54
21 13:36:52.082170 start: 1 deployimages (timeout 00:03:00) [common]
22 13:36:52.082354 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 13:36:52.082864 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8
24 13:36:52.083134 makedir: /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin
25 13:36:52.083355 makedir: /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/tests
26 13:36:52.083559 makedir: /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/results
27 13:36:52.083774 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-add-keys
28 13:36:52.084051 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-add-sources
29 13:36:52.084303 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-background-process-start
30 13:36:52.084548 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-background-process-stop
31 13:36:52.084785 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-common-functions
32 13:36:52.085021 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-echo-ipv4
33 13:36:52.085259 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-install-packages
34 13:36:52.085494 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-installed-packages
35 13:36:52.085732 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-os-build
36 13:36:52.085972 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-probe-channel
37 13:36:52.086204 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-probe-ip
38 13:36:52.086437 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-target-ip
39 13:36:52.086669 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-target-mac
40 13:36:52.086902 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-target-storage
41 13:36:52.087140 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-test-case
42 13:36:52.087373 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-test-event
43 13:36:52.087606 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-test-feedback
44 13:36:52.087838 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-test-raise
45 13:36:52.088075 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-test-reference
46 13:36:52.088306 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-test-runner
47 13:36:52.088536 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-test-set
48 13:36:52.088766 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-test-shell
49 13:36:52.089004 Updating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-install-packages (oe)
50 13:36:52.089304 Updating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/bin/lava-installed-packages (oe)
51 13:36:52.089556 Creating /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/environment
52 13:36:52.089773 LAVA metadata
53 13:36:52.089916 - LAVA_JOB_ID=652449
54 13:36:52.090049 - LAVA_DISPATCHER_IP=172.27.0.2
55 13:36:52.090259 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 13:36:52.090396 skipped lava-vland-overlay
57 13:36:52.090546 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 13:36:52.090711 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 13:36:52.090839 skipped lava-multinode-overlay
60 13:36:52.090984 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 13:36:52.091139 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 13:36:52.091294 Loading test definitions
63 13:36:52.091480 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 13:36:52.091630 Using /lava-652449 at stage 0
65 13:36:52.092245 uuid=652449_1.1.3.1 testdef=None
66 13:36:52.092429 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 13:36:52.092590 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 13:36:52.093500 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 13:36:52.093994 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 13:36:52.095121 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 13:36:52.095615 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 13:36:52.096679 runner path: /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/0/tests/0_timesync-off test_uuid 652449_1.1.3.1
75 13:36:52.096971 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 13:36:52.097449 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 13:36:52.097589 Using /lava-652449 at stage 0
79 13:36:52.097796 Fetching tests from https://github.com/kernelci/test-definitions.git
80 13:36:52.097950 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/0/tests/1_kselftest-arm64_qemu'
81 13:36:55.829488 Running '/usr/bin/git checkout kernelci.org
82 13:36:56.002270 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 13:36:56.003444 uuid=652449_1.1.3.5 testdef=None
84 13:36:56.003713 end: 1.1.3.5 git-repo-action (duration 00:00:04) [common]
86 13:36:56.004253 start: 1.1.3.6 test-overlay (timeout 00:02:56) [common]
87 13:36:56.005916 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 13:36:56.006458 start: 1.1.3.7 test-install-overlay (timeout 00:02:56) [common]
90 13:36:56.008681 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 13:36:56.009248 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:56) [common]
93 13:36:56.011420 runner path: /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/0/tests/1_kselftest-arm64_qemu test_uuid 652449_1.1.3.5
94 13:36:56.011612 BOARD='qemu_arm64-virt-gicv3'
95 13:36:56.011764 BRANCH='cip-gitlab'
96 13:36:56.011913 SKIPFILE='/dev/null'
97 13:36:56.012062 SKIP_INSTALL='True'
98 13:36:56.012209 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.31-61-g32a95f5a4e3b/arm64/defconfig/gcc-10/kselftest.tar.xz'
99 13:36:56.012358 TST_CASENAME=''
100 13:36:56.012503 TST_CMDFILES='arm64'
101 13:36:56.012824 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 13:36:56.013336 Creating lava-test-runner.conf files
104 13:36:56.013493 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/652449/lava-overlay-dez0flg8/lava-652449/0 for stage 0
105 13:36:56.013721 - 0_timesync-off
106 13:36:56.013881 - 1_kselftest-arm64_qemu
107 13:36:56.014103 end: 1.1.3 test-definition (duration 00:00:04) [common]
108 13:36:56.014301 start: 1.1.4 compress-overlay (timeout 00:02:56) [common]
109 13:37:04.895137 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 13:37:04.895329 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:47) [common]
111 13:37:04.895421 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 13:37:04.895529 end: 1.1 lava-overlay (duration 00:00:13) [common]
113 13:37:04.895619 start: 1.2 apply-overlay-guest (timeout 00:02:47) [common]
114 13:37:04.895697 Overlay: /var/lib/lava/dispatcher/tmp/652449/compress-overlay-_1ul934e/overlay-1.1.4.tar.gz
115 13:37:21.231620 end: 1.2 apply-overlay-guest (duration 00:00:16) [common]
117 13:37:21.232280 start: 1.3 deploy-device-env (timeout 00:02:31) [common]
118 13:37:21.232467 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 13:37:21.232611 start: 1.4 download-retry (timeout 00:02:31) [common]
120 13:37:21.232748 start: 1.4.1 http-download (timeout 00:02:31) [common]
121 13:37:21.233030 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.31-61-g32a95f5a4e3b/arm64/defconfig/gcc-10/kernel/Image
122 13:37:21.233156 saving as /var/lib/lava/dispatcher/tmp/652449/deployimages-p3_52l4y/kernel/Image
123 13:37:21.233258 total size: 37358080 (35MB)
124 13:37:21.233352 No compression specified
125 13:37:21.575750 progress 0% (0MB)
126 13:37:22.590116 progress 5% (1MB)
127 13:37:22.759508 progress 10% (3MB)
128 13:37:22.943916 progress 15% (5MB)
129 13:37:22.952533 progress 20% (7MB)
130 13:37:23.294512 progress 25% (8MB)
131 13:37:23.459321 progress 30% (10MB)
132 13:37:23.625602 progress 35% (12MB)
133 13:37:23.848425 progress 40% (14MB)
134 13:37:23.864551 progress 45% (16MB)
135 13:37:24.035174 progress 50% (17MB)
136 13:37:24.204928 progress 55% (19MB)
137 13:37:24.374840 progress 60% (21MB)
138 13:37:24.543918 progress 65% (23MB)
139 13:37:24.712080 progress 70% (24MB)
140 13:37:24.880506 progress 75% (26MB)
141 13:37:25.043314 progress 80% (28MB)
142 13:37:25.209704 progress 85% (30MB)
143 13:37:25.378004 progress 90% (32MB)
144 13:37:25.546234 progress 95% (33MB)
145 13:37:25.713933 progress 100% (35MB)
146 13:37:25.714193 35MB downloaded in 4.48s (7.95MB/s)
147 13:37:25.714504 end: 1.4.1 http-download (duration 00:00:04) [common]
149 13:37:25.715014 end: 1.4 download-retry (duration 00:00:04) [common]
150 13:37:25.715179 start: 1.5 download-retry (timeout 00:02:26) [common]
151 13:37:25.715337 start: 1.5.1 http-download (timeout 00:02:26) [common]
152 13:37:25.715553 Not decompressing ramdisk as can be used compressed.
153 13:37:25.715715 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/rootfs.cpio.gz
154 13:37:25.715838 saving as /var/lib/lava/dispatcher/tmp/652449/deployimages-p3_52l4y/ramdisk/rootfs.cpio.gz
155 13:37:25.715957 total size: 88950412 (84MB)
156 13:37:25.716074 No compression specified
157 13:37:25.889161 progress 0% (0MB)
158 13:37:26.232293 progress 5% (4MB)
159 13:37:26.574704 progress 10% (8MB)
160 13:37:26.916291 progress 15% (12MB)
161 13:37:27.257247 progress 20% (16MB)
162 13:37:27.598029 progress 25% (21MB)
163 13:37:27.938287 progress 30% (25MB)
164 13:37:28.278380 progress 35% (29MB)
165 13:37:28.619176 progress 40% (33MB)
166 13:37:29.103588 progress 45% (38MB)
167 13:37:29.447081 progress 50% (42MB)
168 13:37:29.786451 progress 55% (46MB)
169 13:37:30.125359 progress 60% (50MB)
170 13:37:30.464492 progress 65% (55MB)
171 13:37:30.803636 progress 70% (59MB)
172 13:37:31.142309 progress 75% (63MB)
173 13:37:31.481484 progress 80% (67MB)
174 13:37:31.820543 progress 85% (72MB)
175 13:37:32.159617 progress 90% (76MB)
176 13:37:32.658101 progress 95% (80MB)
177 13:37:33.010773 progress 100% (84MB)
178 13:37:33.011127 84MB downloaded in 7.30s (11.63MB/s)
179 13:37:33.011331 end: 1.5.1 http-download (duration 00:00:07) [common]
181 13:37:33.011710 end: 1.5 download-retry (duration 00:00:07) [common]
182 13:37:33.011834 end: 1 deployimages (duration 00:00:41) [common]
183 13:37:33.011958 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 13:37:33.012079 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 13:37:33.012201 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 13:37:33.012496 Extending command line for qcow2 test overlay
187 13:37:33.012960 Pulling docker image
188 13:37:33.013073 cmd: ['docker', 'pull', 'kernelci/qemu']
189 13:37:33.013182 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 13:37:33.172940 >> Using default tag: latest
191 13:37:34.314165 >> latest: Pulling from kernelci/qemu
192 13:37:34.499482 >> Digest: sha256:89417f77b9e36ef1123db2a628e130c9901c22da31489be871c6c7baa349f1d8
193 13:37:34.499754 >> Status: Image is up to date for kernelci/qemu:latest
194 13:37:34.607782 >> docker.io/kernelci/qemu:latest
195 13:37:34.610520 Returned 0 in 1 seconds
196 13:37:34.744298 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-652449-2.1.1-lpin87rpdl --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/652449/deployimages-p3_52l4y/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/652449/deployimages-p3_52l4y/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/652449/apply-overlay-guest-tdpn4bh7/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 13:37:34.868166 started a shell command
198 13:37:34.868659 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 13:37:34.868788 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 13:37:34.868902 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 13:37:34.869017 Setting prompt string to ['Linux version [0-9]']
202 13:37:34.869104 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 13:37:36.745350 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 13:37:36.748484 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j77215-arm64-gcc-10-defconfig-zzm88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 22 12:09:38 UTC 2023
205 13:37:36.748748 [ 0.000000] random: crng init done
206 13:37:36.748932 [ 0.000000] Machine model: linux,dummy-virt
207 13:37:36.749100 [ 0.000000] efi: UEFI not found.
208 13:37:36.749273 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
209 13:37:36.749500 [ 0.000000] printk: bootconsole [pl11] enabled
210 13:37:36.750048 start: 2.2.1 login-action (timeout 00:04:56) [common]
211 13:37:36.750270 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
212 13:37:36.750505 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
213 13:37:36.750723 Using line separator: #'\n'#
214 13:37:36.750906 No login prompt set.
215 13:37:36.751093 Parsing kernel messages
216 13:37:36.751260 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
217 13:37:36.751588 [login-action] Waiting for messages, (timeout 00:04:56)
218 13:37:36.753381 [ 0.000000] NUMA: No NUMA configuration found
219 13:37:36.753586 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 13:37:36.753782 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf2a00-0x7fdf4fff]
221 13:37:36.754565 [ 0.000000] Zone ranges:
222 13:37:36.755561 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 13:37:36.755770 [ 0.000000] DMA32 empty
224 13:37:36.755988 [ 0.000000] Normal empty
225 13:37:36.756231 [ 0.000000] Movable zone start for each node
226 13:37:36.756614 [ 0.000000] Early memory node ranges
227 13:37:36.756791 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 13:37:36.756992 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 13:37:36.771983 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 13:37:36.773269 [ 0.000000] psci: probing for conduit method from DT.
231 13:37:36.773500 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 13:37:36.773735 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 13:37:36.773830 [ 0.000000] psci: Trusted OS migration not required
234 13:37:36.773919 [ 0.000000] psci: SMC Calling Convention v1.0
235 13:37:36.776127 [ 0.000000] percpu: Embedded 20 pages/cpu s44840 r8192 d28888 u81920
236 13:37:36.776700 [ 0.000000] pcpu-alloc: s44840 r8192 d28888 u81920 alloc=20*4096
237 13:37:36.777027 [ 0.000000] pcpu-alloc: [0] 0
238 13:37:36.778427 [ 0.000000] Detected PIPT I-cache on CPU0
239 13:37:36.784243 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 13:37:36.785163 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 13:37:36.785625 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 13:37:36.785802 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 13:37:36.786096 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 13:37:36.786198 [ 0.000000] CPU features: detected: Spectre-v4
245 13:37:36.790105 [ 0.000000] alternatives: applying boot alternatives
246 13:37:36.793223 [ 0.000000] Fallback order for Node 0: 0
247 13:37:36.793363 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 13:37:36.793458 [ 0.000000] Policy zone: DMA
249 13:37:36.793959 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 13:37:36.796435 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 13:37:36.799093 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 13:37:36.799615 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 13:37:36.800146 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 13:37:36.809825 <6>[ 0.000000] Memory: 870696K/1048576K available (16192K kernel code, 3714K rwdata, 8860K rodata, 7552K init, 609K bss, 145112K reserved, 32768K cma-reserved)
255 13:37:36.816005 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 13:37:36.823116 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 13:37:36.823881 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 13:37:36.824282 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 13:37:36.824449 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 13:37:36.824558 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 13:37:36.824671 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 13:37:36.824768 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 13:37:36.825394 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 13:37:36.832755 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 13:37:36.833200 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 13:37:36.834644 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 13:37:36.835030 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 13:37:36.835800 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 13:37:36.840832 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 13:37:36.842432 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @42830000 (indirect, esz 8, psz 64K, shr 1)
271 13:37:36.842908 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @42840000 (flat, esz 8, psz 64K, shr 1)
272 13:37:36.843261 <6>[ 0.000000] GICv3: using LPI property table @0x0000000042850000
273 13:37:36.844461 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000042860000
274 13:37:36.846104 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 13:37:36.854932 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 13:37:36.855446 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 13:37:36.856363 <6>[ 0.000095] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 13:37:36.874347 <6>[ 0.015502] Console: colour dummy device 80x25
279 13:37:36.879268 <6>[ 0.021972] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 13:37:36.879399 <6>[ 0.023283] pid_max: default: 32768 minimum: 301
281 13:37:36.880854 <6>[ 0.024717] LSM: Security Framework initializing
282 13:37:36.885943 <6>[ 0.029474] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 13:37:36.886118 <6>[ 0.029830] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 13:37:36.919011 <4>[ 0.062982] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 13:37:36.925340 <6>[ 0.069128] cblist_init_generic: Setting adjustable number of callback queues.
286 13:37:36.925724 <6>[ 0.069527] cblist_init_generic: Setting shift to 0 and lim to 1.
287 13:37:36.926339 <6>[ 0.070248] cblist_init_generic: Setting shift to 0 and lim to 1.
288 13:37:36.928119 <6>[ 0.072009] rcu: Hierarchical SRCU implementation.
289 13:37:36.928475 <6>[ 0.072204] rcu: Max phase no-delay instances is 1000.
290 13:37:36.933920 <6>[ 0.077830] Platform MSI: its@8080000 domain created
291 13:37:36.934788 <6>[ 0.078483] PCI/MSI: /intc@8000000/its@8080000 domain created
292 13:37:36.935118 <6>[ 0.079146] fsl-mc MSI: its@8080000 domain created
293 13:37:36.938342 <6>[ 0.082321] EFI services will not be available.
294 13:37:36.939676 <6>[ 0.083447] smp: Bringing up secondary CPUs ...
295 13:37:36.939959 <6>[ 0.083736] smp: Brought up 1 node, 1 CPU
296 13:37:36.940082 <6>[ 0.083972] SMP: Total of 1 processors activated.
297 13:37:36.940766 <6>[ 0.084499] CPU features: detected: Branch Target Identification
298 13:37:36.940931 <6>[ 0.084851] CPU features: detected: 32-bit EL0 Support
299 13:37:36.941382 <6>[ 0.085205] CPU features: detected: 32-bit EL1 Support
300 13:37:36.941505 <6>[ 0.085403] CPU features: detected: ARMv8.4 Translation Table Level
301 13:37:36.941834 <6>[ 0.085647] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 13:37:36.942269 <6>[ 0.086047] CPU features: detected: Common not Private translations
303 13:37:36.942379 <6>[ 0.086289] CPU features: detected: CRC32 instructions
304 13:37:36.942491 <6>[ 0.086456] CPU features: detected: E0PD
305 13:37:36.943053 <6>[ 0.086710] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 13:37:36.943233 <6>[ 0.086972] CPU features: detected: RCpc load-acquire (LDAPR)
307 13:37:36.943655 <6>[ 0.087232] CPU features: detected: LSE atomic instructions
308 13:37:36.943762 <6>[ 0.087476] CPU features: detected: Privileged Access Never
309 13:37:36.943870 <6>[ 0.087698] CPU features: detected: RAS Extension Support
310 13:37:36.944351 <6>[ 0.087914] CPU features: detected: Random Number Generator
311 13:37:36.944459 <6>[ 0.088120] CPU features: detected: Speculation barrier (SB)
312 13:37:36.944553 <6>[ 0.088349] CPU features: detected: Stage-2 Force Write-Back
313 13:37:36.944658 <6>[ 0.088537] CPU features: detected: TLB range maintenance instructions
314 13:37:36.944988 <6>[ 0.088820] CPU features: detected: Scalable Matrix Extension
315 13:37:36.945097 <6>[ 0.089040] CPU features: detected: FA64
316 13:37:36.945422 <6>[ 0.089196] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 13:37:36.945782 <6>[ 0.089633] CPU features: detected: Scalable Vector Extension
318 13:37:36.957339 <6>[ 0.098616] SVE: maximum available vector length 256 bytes per vector
319 13:37:36.957921 <6>[ 0.101961] SVE: default vector length 64 bytes per vector
320 13:37:36.960011 <6>[ 0.103804] SME: minimum available vector length 16 bytes per vector
321 13:37:36.960199 <6>[ 0.104024] SME: maximum available vector length 256 bytes per vector
322 13:37:36.960359 <6>[ 0.104221] SME: default vector length 32 bytes per vector
323 13:37:36.960823 <6>[ 0.104647] CPU: All CPU(s) started at EL1
324 13:37:36.961015 <6>[ 0.105005] alternatives: applying system-wide alternatives
325 13:37:37.014549 <6>[ 0.158427] devtmpfs: initialized
326 13:37:37.034644 <6>[ 0.178269] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 13:37:37.035214 <6>[ 0.179131] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 13:37:37.041519 <6>[ 0.185380] pinctrl core: initialized pinctrl subsystem
329 13:37:37.054527 <6>[ 0.198273] DMI not present or invalid.
330 13:37:37.068252 <6>[ 0.211799] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 13:37:37.081655 <6>[ 0.225131] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 13:37:37.082213 <6>[ 0.226125] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 13:37:37.082955 <6>[ 0.226743] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 13:37:37.083433 <6>[ 0.227327] audit: initializing netlink subsys (disabled)
335 13:37:37.089430 <5>[ 0.233308] audit: type=2000 audit(0.192:1): state=initialized audit_enabled=0 res=1
336 13:37:37.091870 <6>[ 0.235686] thermal_sys: Registered thermal governor 'step_wise'
337 13:37:37.092653 <6>[ 0.235757] thermal_sys: Registered thermal governor 'power_allocator'
338 13:37:37.093014 <6>[ 0.236499] cpuidle: using governor menu
339 13:37:37.094801 <6>[ 0.238577] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
340 13:37:37.095146 <6>[ 0.239236] ASID allocator initialised with 65536 entries
341 13:37:37.101765 <6>[ 0.245845] Serial: AMBA PL011 UART driver
342 13:37:37.154768 <6>[ 0.298675] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
343 13:37:37.156786 <6>[ 0.300480] printk: console [ttyAMA0] enabled
344 13:37:37.156894 <6>[ 0.300480] printk: console [ttyAMA0] enabled
345 13:37:37.157240 <6>[ 0.301113] printk: bootconsole [pl11] disabled
346 13:37:37.157330 <6>[ 0.301113] printk: bootconsole [pl11] disabled
347 13:37:37.170007 <6>[ 0.314136] KASLR enabled
348 13:37:37.210368 <6>[ 0.354007] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
349 13:37:37.210696 <6>[ 0.354219] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
350 13:37:37.210902 <6>[ 0.354370] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
351 13:37:37.211083 <6>[ 0.354517] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
352 13:37:37.211250 <6>[ 0.354658] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
353 13:37:37.211382 <6>[ 0.354814] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
354 13:37:37.211529 <6>[ 0.355023] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
355 13:37:37.211656 <6>[ 0.355244] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
356 13:37:37.222508 <6>[ 0.366325] ACPI: Interpreter disabled.
357 13:37:37.231886 <6>[ 0.375754] iommu: Default domain type: Translated
358 13:37:37.232484 <6>[ 0.376003] iommu: DMA domain TLB invalidation policy: strict mode
359 13:37:37.233550 <5>[ 0.377650] SCSI subsystem initialized
360 13:37:37.234418 <7>[ 0.378510] libata version 3.00 loaded.
361 13:37:37.236474 <6>[ 0.380481] usbcore: registered new interface driver usbfs
362 13:37:37.237189 <6>[ 0.381029] usbcore: registered new interface driver hub
363 13:37:37.237495 <6>[ 0.381456] usbcore: registered new device driver usb
364 13:37:37.242092 <6>[ 0.385850] pps_core: LinuxPPS API ver. 1 registered
365 13:37:37.242328 <6>[ 0.386025] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
366 13:37:37.242679 <6>[ 0.386373] PTP clock support registered
367 13:37:37.243037 <6>[ 0.387110] EDAC MC: Ver: 3.0.0
368 13:37:37.249955 <6>[ 0.393980] FPGA manager framework
369 13:37:37.251055 <6>[ 0.394911] Advanced Linux Sound Architecture Driver Initialized.
370 13:37:37.262342 <6>[ 0.406409] vgaarb: loaded
371 13:37:37.266891 <6>[ 0.410747] clocksource: Switched to clocksource arch_sys_counter
372 13:37:37.268484 <5>[ 0.412375] VFS: Disk quotas dquot_6.6.0
373 13:37:37.268856 <6>[ 0.412720] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
374 13:37:37.272136 <6>[ 0.416019] pnp: PnP ACPI: disabled
375 13:37:37.292063 <6>[ 0.436149] NET: Registered PF_INET protocol family
376 13:37:37.294536 <6>[ 0.438387] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
377 13:37:37.299970 <6>[ 0.443820] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
378 13:37:37.300140 <6>[ 0.444115] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
379 13:37:37.300287 <6>[ 0.444340] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
380 13:37:37.300706 <6>[ 0.444723] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
381 13:37:37.301402 <6>[ 0.445304] TCP: Hash tables configured (established 8192 bind 8192)
382 13:37:37.302519 <6>[ 0.446579] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
383 13:37:37.303002 <6>[ 0.447000] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
384 13:37:37.304293 <6>[ 0.448141] NET: Registered PF_UNIX/PF_LOCAL protocol family
385 13:37:37.306561 <6>[ 0.450395] RPC: Registered named UNIX socket transport module.
386 13:37:37.306792 <6>[ 0.450760] RPC: Registered udp transport module.
387 13:37:37.306989 <6>[ 0.450903] RPC: Registered tcp transport module.
388 13:37:37.307152 <6>[ 0.451066] RPC: Registered tcp NFSv4.1 backchannel transport module.
389 13:37:37.307329 <6>[ 0.451321] PCI: CLS 0 bytes, default 64
390 13:37:37.312266 <6>[ 0.456314] Unpacking initramfs...
391 13:37:37.319310 <6>[ 0.463011] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
392 13:37:37.319896 <6>[ 0.463753] kvm [1]: HYP mode not available
393 13:37:37.329773 <5>[ 0.473762] Initialise system trusted keyrings
394 13:37:37.335846 <6>[ 0.479638] workingset: timestamp_bits=42 max_order=18 bucket_order=0
395 13:37:37.376677 <6>[ 0.520567] squashfs: version 4.0 (2009/01/31) Phillip Lougher
396 13:37:37.383935 <5>[ 0.527969] NFS: Registering the id_resolver key type
397 13:37:37.384458 <5>[ 0.528375] Key type id_resolver registered
398 13:37:37.384575 <5>[ 0.528517] Key type id_legacy registered
399 13:37:37.385068 <6>[ 0.529125] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
400 13:37:37.385404 <6>[ 0.529405] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
401 13:37:37.390688 <6>[ 0.534698] 9p: Installing v9fs 9p2000 file system support
402 13:37:37.453296 <5>[ 0.597259] Key type asymmetric registered
403 13:37:37.453753 <5>[ 0.597480] Asymmetric key parser 'x509' registered
404 13:37:37.454112 <6>[ 0.597987] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
405 13:37:37.454466 <6>[ 0.598326] io scheduler mq-deadline registered
406 13:37:37.458667 <6>[ 0.602680] io scheduler kyber registered
407 13:37:37.539304 <6>[ 0.683155] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
408 13:37:37.549805 <6>[ 0.693739] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
409 13:37:37.555179 <6>[ 0.698894] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
410 13:37:37.555949 <6>[ 0.699747] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
411 13:37:37.556166 <6>[ 0.700030] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
412 13:37:37.557216 <4>[ 0.700964] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
413 13:37:37.558171 <6>[ 0.701741] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
414 13:37:37.563744 <6>[ 0.707556] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
415 13:37:37.563937 <6>[ 0.707999] pci_bus 0000:00: root bus resource [bus 00-ff]
416 13:37:37.564499 <6>[ 0.708282] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
417 13:37:37.564620 <6>[ 0.708575] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
418 13:37:37.564964 <6>[ 0.708847] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
419 13:37:37.571195 <6>[ 0.714993] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
420 13:37:37.579158 <6>[ 0.722812] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
421 13:37:37.579529 <6>[ 0.723340] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
422 13:37:37.579741 <6>[ 0.723611] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
423 13:37:37.580323 <6>[ 0.723924] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
424 13:37:37.580496 <6>[ 0.724270] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
425 13:37:37.581086 <6>[ 0.725026] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
426 13:37:37.581677 <6>[ 0.725261] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
427 13:37:37.581890 <6>[ 0.725474] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
428 13:37:37.582105 <6>[ 0.725769] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
429 13:37:37.589058 <6>[ 0.732853] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
430 13:37:37.589677 <6>[ 0.733392] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
431 13:37:37.589927 <6>[ 0.733766] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
432 13:37:37.590175 <6>[ 0.734099] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
433 13:37:37.590382 <6>[ 0.734355] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
434 13:37:37.594596 <6>[ 0.738633] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
435 13:37:37.595112 <6>[ 0.738870] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
436 13:37:37.607582 <6>[ 0.751643] EINJ: ACPI disabled.
437 13:37:37.710674 <6>[ 0.850413] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
438 13:37:37.713910 <6>[ 0.857726] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
439 13:37:37.751685 <6>[ 0.895635] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
440 13:37:37.768206 <6>[ 0.912179] SuperH (H)SCI(F) driver initialized
441 13:37:37.769516 <6>[ 0.913635] msm_serial: driver initialized
442 13:37:37.778884 <4>[ 0.922920] cacheinfo: Unable to detect cache hierarchy for CPU 0
443 13:37:37.814068 <6>[ 0.958029] loop: module loaded
444 13:37:37.819364 <6>[ 0.963360] virtio_blk virtio1: 1/0/0 default/read/poll queues
445 13:37:37.836725 <5>[ 0.980633] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
446 13:37:37.872804 <6>[ 1.016665] megasas: 07.719.03.00-rc1
447 13:37:37.887739 <5>[ 1.031585] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
448 13:37:37.889596 <6>[ 1.033231] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
449 13:37:37.890218 <6>[ 1.033992] Intel/Sharp Extended Query Table at 0x0031
450 13:37:37.895321 <6>[ 1.039276] Using buffer write method
451 13:37:37.895821 <7>[ 1.039847] erase region 0: offset=0x0,size=0x40000,blocks=256
452 13:37:37.896318 <5>[ 1.040307] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
453 13:37:37.897195 <6>[ 1.041061] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
454 13:37:37.897552 <6>[ 1.041403] Intel/Sharp Extended Query Table at 0x0031
455 13:37:37.898347 <6>[ 1.042227] Using buffer write method
456 13:37:37.898472 <7>[ 1.042412] erase region 0: offset=0x0,size=0x40000,blocks=256
457 13:37:37.902972 <5>[ 1.046815] Concatenating MTD devices:
458 13:37:37.903148 <5>[ 1.047014] (0): \"0.flash\"
459 13:37:37.903261 <5>[ 1.047151] (1): \"0.flash\"
460 13:37:37.903354 <5>[ 1.047276] into device \"0.flash\"
461 13:37:42.946323 <6>[ 6.090281] Freeing initrd memory: 86864K
462 13:37:43.075782 <6>[ 6.219666] tun: Universal TUN/TAP device driver, 1.6
463 13:37:43.085865 <6>[ 6.229914] thunder_xcv, ver 1.0
464 13:37:43.086311 <6>[ 6.230181] thunder_bgx, ver 1.0
465 13:37:43.086432 <6>[ 6.230437] nicpf, ver 1.0
466 13:37:43.089965 <6>[ 6.233792] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
467 13:37:43.090091 <6>[ 6.234033] hns3: Copyright (c) 2017 Huawei Corporation.
468 13:37:43.090430 <6>[ 6.234506] hclge is initializing
469 13:37:43.090815 <6>[ 6.234756] e1000: Intel(R) PRO/1000 Network Driver
470 13:37:43.090933 <6>[ 6.234908] e1000: Copyright (c) 1999-2006 Intel Corporation.
471 13:37:43.091270 <6>[ 6.235260] e1000e: Intel(R) PRO/1000 Network Driver
472 13:37:43.091406 <6>[ 6.235441] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
473 13:37:43.091759 <6>[ 6.235800] igb: Intel(R) Gigabit Ethernet Network Driver
474 13:37:43.092104 <6>[ 6.236017] igb: Copyright (c) 2007-2014 Intel Corporation.
475 13:37:43.092466 <6>[ 6.236345] igbvf: Intel(R) Gigabit Virtual Function Network Driver
476 13:37:43.092590 <6>[ 6.236556] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
477 13:37:43.093990 <6>[ 6.237931] sky2: driver version 1.30
478 13:37:43.097038 <6>[ 6.240947] VFIO - User Level meta-driver version: 0.3
479 13:37:43.106789 <6>[ 6.250771] usbcore: registered new interface driver usb-storage
480 13:37:43.116404 <6>[ 6.260361] rtc-pl031 9010000.pl031: registered as rtc0
481 13:37:43.117843 <6>[ 6.261282] rtc-pl031 9010000.pl031: setting system clock to 2023-06-22T13:37:43 UTC (1687441063)
482 13:37:43.120641 <6>[ 6.264491] i2c_dev: i2c /dev entries driver
483 13:37:43.137413 <6>[ 6.281157] sdhci: Secure Digital Host Controller Interface driver
484 13:37:43.137676 <6>[ 6.281381] sdhci: Copyright(c) Pierre Ossman
485 13:37:43.139589 <6>[ 6.283427] Synopsys Designware Multimedia Card Interface Driver
486 13:37:43.141738 <6>[ 6.285766] sdhci-pltfm: SDHCI platform and OF driver helper
487 13:37:43.146808 <6>[ 6.290691] ledtrig-cpu: registered to indicate activity on CPUs
488 13:37:43.152546 <6>[ 6.296466] usbcore: registered new interface driver usbhid
489 13:37:43.152635 <6>[ 6.296620] usbhid: USB HID core driver
490 13:37:43.171214 <6>[ 6.315233] NET: Registered PF_PACKET protocol family
491 13:37:43.172734 <6>[ 6.316562] 9pnet: Installing 9P2000 support
492 13:37:43.173012 <5>[ 6.316935] Key type dns_resolver registered
493 13:37:43.174105 <6>[ 6.318162] registered taskstats version 1
494 13:37:43.174617 <5>[ 6.318665] Loading compiled-in X.509 certificates
495 13:37:43.199119 <6>[ 6.343076] input: gpio-keys as /devices/platform/gpio-keys/input/input0
496 13:37:43.206220 <6>[ 6.350315] ALSA device list:
497 13:37:43.206613 <6>[ 6.350572] No soundcards found.
498 13:37:43.209119 <6>[ 6.353197] uart-pl011 9000000.pl011: no DMA platform data
499 13:37:43.268162 <6>[ 6.412060] Freeing unused kernel memory: 7552K
500 13:37:43.269079 <6>[ 6.413168] Run /init as init process
501 13:37:43.269437 <7>[ 6.413292] with arguments:
502 13:37:43.269562 <7>[ 6.413384] /init
503 13:37:43.269667 <7>[ 6.413453] verbose
504 13:37:43.269757 <7>[ 6.413519] with environment:
505 13:37:43.269846 <7>[ 6.413598] HOME=/
506 13:37:43.269939 <7>[ 6.413661] TERM=linux
507 13:37:43.416134 <30>[ 6.559776] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
508 13:37:43.416870 <31>[ 6.560946] systemd[1]: No virtualization found in DMI
509 13:37:43.417868 <31>[ 6.561908] systemd[1]: UML virtualization not found in /proc/cpuinfo.
510 13:37:43.418313 <31>[ 6.562182] systemd[1]: No virtualization found in CPUID
511 13:37:43.418830 <31>[ 6.562751] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
512 13:37:43.420245 <31>[ 6.564013] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
513 13:37:43.420450 <31>[ 6.564357] systemd[1]: Found VM virtualization qemu
514 13:37:43.420645 <30>[ 6.564604] systemd[1]: Detected virtualization qemu.
515 13:37:43.421062 <30>[ 6.564945] systemd[1]: Detected architecture arm64.
516 13:37:43.421528 <31>[ 6.565295] systemd[1]: Detected initialized system, this is not the first boot.
517 13:37:43.425659
518 13:37:43.426172 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
519 13:37:43.426327
520 13:37:43.428374 <30>[ 6.572218] systemd[1]: Set hostname to <debian-bullseye-arm64>.
521 13:37:43.448237 <31>[ 6.592199] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
522 13:37:43.449765 <31>[ 6.593543] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
523 13:37:43.449926 <31>[ 6.594006] systemd[1]: Successfully brought loopback interface up
524 13:37:43.455530 <31>[ 6.599392] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
525 13:37:43.468845 <31>[ 6.612761] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
526 13:37:43.469392 <31>[ 6.613028] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
527 13:37:43.511485 <31>[ 6.655133] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
528 13:37:43.514261 <31>[ 6.656842] systemd[1]: Controller 'cpu' supported: yes
529 13:37:43.514412 <31>[ 6.657060] systemd[1]: Controller 'cpuacct' supported: no
530 13:37:43.514508 <31>[ 6.657247] systemd[1]: Controller 'cpuset' supported: yes
531 13:37:43.514601 <31>[ 6.657472] systemd[1]: Controller 'io' supported: yes
532 13:37:43.514695 <31>[ 6.657669] systemd[1]: Controller 'blkio' supported: no
533 13:37:43.514784 <31>[ 6.657892] systemd[1]: Controller 'memory' supported: yes
534 13:37:43.514875 <31>[ 6.658124] systemd[1]: Controller 'devices' supported: no
535 13:37:43.515228 <31>[ 6.658304] systemd[1]: Controller 'pids' supported: yes
536 13:37:43.515335 <31>[ 6.658895] systemd[1]: Controller 'bpf-firewall' supported: yes
537 13:37:43.515428 <31>[ 6.659192] systemd[1]: Controller 'bpf-devices' supported: yes
538 13:37:43.516666 <31>[ 6.660689] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
539 13:37:43.517284 <31>[ 6.661180] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
540 13:37:43.518022 <31>[ 6.661830] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
541 13:37:43.526144 <31>[ 6.669846] systemd[1]: Enabling (yes) showing of status (commandline).
542 13:37:43.534120 <31>[ 6.677984] systemd[1]: Successfully forked off '(sd-executor)' as PID 94.
543 13:37:43.544704 <31>[ 6.688613] systemd[94]: Successfully forked off '(direxec)' as PID 95.
544 13:37:43.547347 <31>[ 6.691199] systemd[94]: Successfully forked off '(direxec)' as PID 96.
545 13:37:43.549957 <31>[ 6.693636] systemd[94]: Successfully forked off '(direxec)' as PID 97.
546 13:37:43.564587 <31>[ 6.708254] systemd[94]: Successfully forked off '(direxec)' as PID 98.
547 13:37:43.587627 <31>[ 6.731292] systemd[94]: Successfully forked off '(direxec)' as PID 99.
548 13:37:43.740090 <31>[ 6.883857] systemd-bless-boot-generator[95]: Skipping generator, not an EFI boot.
549 13:37:43.744376 <31>[ 6.888354] systemd-fstab-generator[96]: Parsing /etc/fstab...
550 13:37:43.755667 <31>[ 6.899344] systemd-getty-generator[97]: Automatically adding serial getty for /dev/ttyAMA0.
551 13:37:43.757399 <31>[ 6.901348] systemd-getty-generator[97]: SELinux enabled state cached to: disabled
552 13:37:43.763631 <31>[ 6.907152] systemd-fstab-generator[96]: Found entry what=/dev/disk/by-uuid/e8944c3c-78ff-4c74-a97d-ff60ed2bed2f where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
553 13:37:43.781374 <31>[ 6.925064] systemd-fstab-generator[96]: Checking was requested for /dev/disk/by-uuid/e8944c3c-78ff-4c74-a97d-ff60ed2bed2f, but fsck.ext4 does not exist.
554 13:37:43.794496 <31>[ 6.938166] systemd-fstab-generator[96]: SELinux enabled state cached to: disabled
555 13:37:43.808179 <31>[ 6.952020] systemd[94]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
556 13:37:43.808870 <31>[ 6.952776] systemd[94]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
557 13:37:43.809436 <31>[ 6.953226] systemd[94]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
558 13:37:43.809764 <31>[ 6.953686] systemd[94]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
559 13:37:43.810352 <31>[ 6.954133] systemd[94]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
560 13:37:43.815469 <31>[ 6.959215] systemd[1]: (sd-executor) succeeded.
561 13:37:43.817364 <31>[ 6.961246] systemd[1]: Looking for unit files in (higher priority first):
562 13:37:43.817510 <31>[ 6.961527] systemd[1]: /etc/systemd/system.control
563 13:37:43.817861 <31>[ 6.961736] systemd[1]: /run/systemd/system.control
564 13:37:43.817984 <31>[ 6.961935] systemd[1]: /run/systemd/transient
565 13:37:43.818095 <31>[ 6.962138] systemd[1]: /run/systemd/generator.early
566 13:37:43.818437 <31>[ 6.962344] systemd[1]: /etc/systemd/system
567 13:37:43.819094 <31>[ 6.963077] systemd[1]: /etc/systemd/system.attached
568 13:37:43.819552 <31>[ 6.963346] systemd[1]: /run/systemd/system
569 13:37:43.819663 <31>[ 6.963546] systemd[1]: /run/systemd/system.attached
570 13:37:43.819768 <31>[ 6.963755] systemd[1]: /run/systemd/generator
571 13:37:43.819871 <31>[ 6.963935] systemd[1]: /usr/local/lib/systemd/system
572 13:37:43.820212 <31>[ 6.964142] systemd[1]: /lib/systemd/system
573 13:37:43.820334 <31>[ 6.964323] systemd[1]: /usr/lib/systemd/system
574 13:37:43.820442 <31>[ 6.964518] systemd[1]: /run/systemd/generator.late
575 13:37:43.866580 <31>[ 7.010273] systemd[1]: Modification times have changed, need to update cache.
576 13:37:43.869243 <31>[ 7.012876] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
577 13:37:43.870452 <31>[ 7.013984] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
578 13:37:43.871738 <31>[ 7.015529] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
579 13:37:43.872880 <31>[ 7.016710] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
580 13:37:43.874405 <31>[ 7.018148] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/autovt@.service → getty@.service
581 13:37:43.875176 <31>[ 7.019096] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
582 13:37:43.875968 <31>[ 7.019467] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub@.service
583 13:37:43.876501 <31>[ 7.019940] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
584 13:37:43.877271 <31>[ 7.020371] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
585 13:37:43.877388 <31>[ 7.020844] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
586 13:37:43.877501 <31>[ 7.021230] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
587 13:37:43.877856 <31>[ 7.021608] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
588 13:37:43.879145 <31>[ 7.023038] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
589 13:37:43.879947 <31>[ 7.023522] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
590 13:37:43.880192 <31>[ 7.023925] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
591 13:37:43.880647 <31>[ 7.024260] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sysinit.target
592 13:37:43.880789 <31>[ 7.024561] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
593 13:37:43.881160 <31>[ 7.024884] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
594 13:37:43.881941 <31>[ 7.025757] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
595 13:37:43.883496 <31>[ 7.026986] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
596 13:37:43.883942 <31>[ 7.027383] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/swap.target
597 13:37:43.884545 <31>[ 7.027776] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
598 13:37:43.884653 <31>[ 7.028246] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
599 13:37:43.885163 <31>[ 7.028763] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
600 13:37:43.885404 <31>[ 7.029202] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
601 13:37:43.886186 <31>[ 7.029771] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
602 13:37:43.887050 <31>[ 7.030837] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
603 13:37:43.887444 <31>[ 7.031330] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
604 13:37:43.888019 <31>[ 7.031780] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
605 13:37:43.888406 <31>[ 7.032191] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
606 13:37:43.888735 <31>[ 7.032576] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
607 13:37:43.889035 <31>[ 7.032860] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
608 13:37:43.889130 <31>[ 7.033131] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
609 13:37:43.889831 <31>[ 7.033802] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel6.target → reboot.target
610 13:37:43.891290 <31>[ 7.034974] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/ctrl-alt-del.target → reboot.target
611 13:37:43.891526 <31>[ 7.035279] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
612 13:37:43.891649 <31>[ 7.035606] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
613 13:37:43.892005 <31>[ 7.035970] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rc-local.service
614 13:37:43.892390 <31>[ 7.036300] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
615 13:37:43.892787 <31>[ 7.036683] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
616 13:37:43.893165 <31>[ 7.037104] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
617 13:37:43.893546 <31>[ 7.037439] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
618 13:37:43.893936 <31>[ 7.037823] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
619 13:37:43.894325 <31>[ 7.038138] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
620 13:37:43.894961 <31>[ 7.038781] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
621 13:37:43.895331 <31>[ 7.039199] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.mount
622 13:37:43.895714 <31>[ 7.039529] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs.target
623 13:37:43.896096 <31>[ 7.039922] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hostnamed.service
624 13:37:43.896517 <31>[ 7.040279] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-remount-fs.service
625 13:37:43.896909 <31>[ 7.040815] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/final.target
626 13:37:43.897473 <31>[ 7.041209] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
627 13:37:43.897929 <31>[ 7.041608] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.service
628 13:37:43.898153 <31>[ 7.041946] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
629 13:37:43.899097 <31>[ 7.042931] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
630 13:37:43.899533 <31>[ 7.043368] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
631 13:37:43.900102 <31>[ 7.043890] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
632 13:37:43.900364 <31>[ 7.044307] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
633 13:37:43.900928 <31>[ 7.044653] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs.target
634 13:37:43.901153 <31>[ 7.045001] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
635 13:37:43.901757 <31>[ 7.045346] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
636 13:37:43.901945 <31>[ 7.045717] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
637 13:37:43.902474 <31>[ 7.046385] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel0.target → poweroff.target
638 13:37:43.903077 <31>[ 7.046975] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
639 13:37:43.903565 <31>[ 7.047341] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/debug-shell.service
640 13:37:43.903937 <31>[ 7.047744] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
641 13:37:43.904320 <31>[ 7.048199] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
642 13:37:43.905207 <31>[ 7.048971] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
643 13:37:43.905607 <31>[ 7.049308] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
644 13:37:43.906010 <31>[ 7.049684] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
645 13:37:43.906136 <31>[ 7.050059] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
646 13:37:43.907019 <31>[ 7.050445] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
647 13:37:43.907426 <31>[ 7.051131] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
648 13:37:43.907824 <31>[ 7.051563] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
649 13:37:43.908298 <31>[ 7.051912] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
650 13:37:43.908443 <31>[ 7.052384] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
651 13:37:43.908849 <31>[ 7.052722] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
652 13:37:43.909768 <31>[ 7.053438] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
653 13:37:43.910224 <31>[ 7.053826] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
654 13:37:43.910592 <31>[ 7.054225] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_fail@.service
655 13:37:43.911660 <31>[ 7.055401] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
656 13:37:43.912370 <31>[ 7.056042] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
657 13:37:43.913402 <31>[ 7.057045] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
658 13:37:43.913789 <31>[ 7.057556] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-localed.service
659 13:37:43.914852 <31>[ 7.058863] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
660 13:37:43.915265 <31>[ 7.059158] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
661 13:37:43.915741 <31>[ 7.059508] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.path
662 13:37:43.915915 <31>[ 7.059853] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.service
663 13:37:43.916418 <31>[ 7.060213] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/shutdown.target
664 13:37:43.916597 <31>[ 7.060554] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
665 13:37:43.917069 <31>[ 7.060853] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-check-no-failures.service
666 13:37:43.917460 <31>[ 7.061244] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
667 13:37:43.917854 <31>[ 7.061633] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
668 13:37:43.918324 <31>[ 7.062011] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
669 13:37:43.918910 <31>[ 7.062724] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
670 13:37:43.919255 <31>[ 7.063156] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
671 13:37:43.919631 <31>[ 7.063553] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-exit.service
672 13:37:43.920030 <31>[ 7.063898] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsckd.service
673 13:37:43.920663 <31>[ 7.064416] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
674 13:37:43.921041 <31>[ 7.064849] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
675 13:37:43.921415 <31>[ 7.065198] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
676 13:37:43.921754 <31>[ 7.065572] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
677 13:37:43.921982 <31>[ 7.065907] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
678 13:37:43.922599 <31>[ 7.066321] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
679 13:37:43.923377 <31>[ 7.067084] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
680 13:37:43.923821 <31>[ 7.067763] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
681 13:37:43.924224 <31>[ 7.068137] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.service
682 13:37:43.924874 <31>[ 7.068686] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
683 13:37:43.925290 <31>[ 7.069068] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
684 13:37:43.925693 <31>[ 7.069444] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-sync.target
685 13:37:43.926166 <31>[ 7.069842] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-user-lookup.target
686 13:37:43.926383 <31>[ 7.070193] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
687 13:37:43.927068 <31>[ 7.070856] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
688 13:37:43.927564 <31>[ 7.071261] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.socket
689 13:37:43.927873 <31>[ 7.071674] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
690 13:37:43.928427 <31>[ 7.072075] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
691 13:37:43.928824 <31>[ 7.072534] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
692 13:37:43.929195 <31>[ 7.072936] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
693 13:37:43.929670 <31>[ 7.073346] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/first-boot-complete.target
694 13:37:43.930059 <31>[ 7.073711] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
695 13:37:43.930417 <31>[ 7.074087] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
696 13:37:43.931045 <31>[ 7.074826] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
697 13:37:43.931435 <31>[ 7.075185] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
698 13:37:43.931781 <31>[ 7.075545] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
699 13:37:43.932650 <31>[ 7.076327] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
700 13:37:43.932776 <31>[ 7.076703] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
701 13:37:43.933162 <31>[ 7.077032] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-mqueue.mount
702 13:37:43.933522 <31>[ 7.077468] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
703 13:37:43.933954 <31>[ 7.077823] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
704 13:37:43.934383 <31>[ 7.078227] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
705 13:37:43.935286 <31>[ 7.078950] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-config.mount
706 13:37:43.935503 <31>[ 7.079364] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
707 13:37:43.936227 <31>[ 7.079797] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
708 13:37:43.936609 <31>[ 7.080163] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
709 13:37:43.937175 <31>[ 7.080593] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/container-getty@.service
710 13:37:43.937379 <31>[ 7.081037] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
711 13:37:43.937638 <31>[ 7.081473] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
712 13:37:43.938221 <31>[ 7.081908] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-trigger.service
713 13:37:43.938449 <31>[ 7.082261] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
714 13:37:43.938988 <31>[ 7.082827] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
715 13:37:43.939462 <31>[ 7.083265] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
716 13:37:43.940344 <31>[ 7.084003] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
717 13:37:43.940595 <31>[ 7.084413] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
718 13:37:43.941229 <31>[ 7.084858] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
719 13:37:43.941395 <31>[ 7.085237] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
720 13:37:43.941755 <31>[ 7.085599] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
721 13:37:43.942138 <31>[ 7.086003] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/smartcard.target
722 13:37:43.942550 <31>[ 7.086396] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
723 13:37:43.943440 <31>[ 7.087185] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
724 13:37:43.943880 <31>[ 7.087574] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
725 13:37:43.944298 <31>[ 7.087970] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
726 13:37:43.944669 <31>[ 7.088413] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
727 13:37:44.441991 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
728 13:37:44.447984 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
729 13:37:44.452625 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
730 13:37:44.458038 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
731 13:37:44.463698 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
732 13:37:44.466205 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
733 13:37:44.469817 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
734 13:37:44.471829 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
735 13:37:44.472893 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
736 13:37:44.474083 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
737 13:37:44.475597 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
738 13:37:44.481242 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
739 13:37:44.485790 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
740 13:37:44.488945 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
741 13:37:44.491577 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
742 13:37:44.494081 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
743 13:37:44.497433 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
744 13:37:44.499997 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
745 13:37:44.529018 Mounting [0;1;39mHuge Pages File System[0m...
746 13:37:44.572466 Mounting [0;1;39mPOSIX Message Queue File System[0m...
747 13:37:44.616331 Mounting [0;1;39mKernel Debug File System[0m...
748 13:37:44.680940 Starting [0;1;39mLoad Kernel Module configfs[0m...
749 13:37:44.728268 Starting [0;1;39mLoad Kernel Module drm[0m...
750 13:37:44.792200 Starting [0;1;39mJournal Service[0m...
751 13:37:44.828805 Starting [0;1;39mLoad Kernel Modules[0m...
752 13:37:44.868922 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
753 13:37:44.936290 Starting [0;1;39mColdplug All udev Devices[0m...
754 13:37:45.044555 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
755 13:37:45.061860 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
756 13:37:45.077089 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
757 13:37:45.125814 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
758 13:37:45.180426 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
759 13:37:45.215560 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
760 13:37:45.296828 Mounting [0;1;39mKernel Configuration File System[0m...
761 13:37:45.432949 Starting [0;1;39mApply Kernel Variables[0m...
762 13:37:45.512247 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
763 13:37:45.636443 <47>[ 8.780373] systemd-journald[105]: SELinux enabled state cached to: disabled
764 13:37:45.638556 <47>[ 8.782363] systemd-journald[105]: Auditing in kernel turned off.
765 13:37:45.667854 <47>[ 8.811521] systemd-journald[105]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
766 13:37:45.713277 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
767 13:37:45.713743 See 'systemctl status systemd-remount-fs.service' for details.
768 13:37:45.732168 <47>[ 8.875972] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
769 13:37:45.742416 <47>[ 8.886345] systemd-journald[105]: Fixed min_use=3.8M max_use=19.4M max_size=2.4M min_size=512.0K keep_free=9.7M n_max_files=100
770 13:37:45.748460 <47>[ 8.892497] systemd-journald[105]: Reserving 333 entries in field hash table.
771 13:37:45.753043 Starting [0;1;39mLoad/Save Random Seed[0m...
772 13:37:45.778369 <47>[ 8.922326] systemd-journald[105]: Reserving 4437 entries in data hash table.
773 13:37:45.796805 <47>[ 8.940686] systemd-journald[105]: Vacuuming...
774 13:37:45.797451 <47>[ 8.941372] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
775 13:37:45.797958 <47>[ 8.942061] systemd-journald[105]: Flushing /dev/kmsg...
776 13:37:45.828707 Starting [0;1;39mCreate System Users[0m...
777 13:37:45.868418 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
778 13:37:46.003608 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
779 13:37:46.184949 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
780 13:37:46.224695 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
781 13:37:46.397282 <47>[ 9.540909] systemd-journald[105]: systemd-journald running as PID 105 for the system.
782 13:37:46.411175 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
783 13:37:46.422891 <47>[ 9.566873] systemd-journald[105]: Sent READY=1 notification.
784 13:37:46.423451 <47>[ 9.567342] systemd-journald[105]: Sent WATCHDOG=1 notification.
785 13:37:46.464324 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
786 13:37:46.468646 <47>[ 9.612376] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
787 13:37:46.503363 <47>[ 9.646807] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
788 13:37:46.517226 <47>[ 9.660888] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
789 13:37:46.534928 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
790 13:37:46.544114 <47>[ 9.687865] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
791 13:37:46.557995 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
792 13:37:46.568870 <47>[ 9.712452] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
793 13:37:46.572527 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
794 13:37:46.590099 <47>[ 9.733740] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
795 13:37:46.616405 <47>[ 9.760056] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
796 13:37:46.647723 <47>[ 9.791340] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
797 13:37:46.650220 <47>[ 9.793965] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
798 13:37:46.665463 <47>[ 9.809123] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
799 13:37:46.683656 <47>[ 9.827602] systemd-journald[105]: n/a: New incoming connection.
800 13:37:46.684467 <47>[ 9.828335] systemd-journald[105]: varlink-18: varlink: setting state idle-server
801 13:37:46.686236 <47>[ 9.830097] systemd-journald[105]: varlink-18: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
802 13:37:46.692720 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
803 13:37:46.704971 <47>[ 9.848656] systemd-journald[105]: varlink-18: varlink: changing state idle-server → processing-method
804 13:37:46.705231 <46>[ 9.849106] systemd-journald[105]: Received client request to flush runtime journal.
805 13:37:46.705843 <47>[ 9.849642] systemd-journald[105]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
806 13:37:46.718885 <47>[ 9.862824] systemd-journald[105]: Vacuuming...
807 13:37:46.719442 <47>[ 9.863415] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
808 13:37:46.721007 <47>[ 9.864844] systemd-journald[105]: varlink-18: Sending message: {\"parameters\":{}}
809 13:37:46.721166 <47>[ 9.865103] systemd-journald[105]: varlink-18: varlink: changing state processing-method → processed-method
810 13:37:46.721739 <47>[ 9.865550] systemd-journald[105]: varlink-18: varlink: changing state processed-method → idle-server
811 13:37:46.743249 <47>[ 9.886931] systemd-journald[105]: varlink-18: varlink: changing state idle-server → pending-disconnect
812 13:37:46.743516 <47>[ 9.887305] systemd-journald[105]: varlink-18: varlink: changing state pending-disconnect → processing-disconnect
813 13:37:46.743878 <47>[ 9.887640] systemd-journald[105]: varlink-18: varlink: changing state processing-disconnect → disconnected
814 13:37:46.745922 <47>[ 9.889755] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
815 13:37:46.760155 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
816 13:37:46.791074 <47>[ 9.934995] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
817 13:37:46.811247 <47>[ 9.955146] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
818 13:37:46.813712 <47>[ 9.957696] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
819 13:37:46.825542 <47>[ 9.969476] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
820 13:37:46.832545 Starting [0;1;39mCreate Volatile Files and Directories[0m...
821 13:37:46.852406 <47>[ 9.996100] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
822 13:37:47.401837 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
823 13:37:47.489486 Starting [0;1;39mNetwork Service[0m...
824 13:37:47.501425 <47>[ 10.645230] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
825 13:37:47.523745 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
826 13:37:47.620339 Starting [0;1;39mNetwork Time Synchronization[0m...
827 13:37:47.640963 <47>[ 10.784823] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
828 13:37:47.693168 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
829 13:37:47.705048 <47>[ 10.848733] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
830 13:37:48.194232 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
831 13:37:49.463796 <47>[ 12.606880] systemd-journald[105]: Data hash table of /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal has a fill level at 75.0 (3329 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
832 13:37:49.464327 <47>[ 12.607726] systemd-journald[105]: /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal: Journal header limits reached or header out-of-date, rotating.
833 13:37:49.464445 <47>[ 12.608268] systemd-journald[105]: Rotating...
834 13:37:49.465496 <47>[ 12.609283] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
835 13:37:49.479494 <47>[ 12.623421] systemd-journald[105]: Reserving 333 entries in field hash table.
836 13:37:49.530201 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
837 13:37:49.535172 <47>[ 12.678911] systemd-journald[105]: Reserving 4437 entries in data hash table.
838 13:37:49.538360 <47>[ 12.682095] systemd-journald[105]: Vacuuming...
839 13:37:49.574161 <47>[ 12.717595] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
840 13:37:49.625016 Starting [0;1;39mNetwork Name Resolution[0m...
841 13:37:49.693685 <47>[ 12.837178] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
842 13:37:49.791199 <47>[ 12.934737] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
843 13:37:50.001285 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
844 13:37:50.004293 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
845 13:37:50.024259 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
846 13:37:51.252952 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
847 13:37:51.267902 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
848 13:37:51.290219 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
849 13:37:51.311044 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
850 13:37:51.321814 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
851 13:37:51.333050 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
852 13:37:51.360512 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
853 13:37:51.361557 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
854 13:37:51.362052 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
855 13:37:51.440731 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
856 13:37:51.449223 <47>[ 14.592878] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
857 13:37:51.599829 <47>[ 14.743740] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
858 13:37:51.602086 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
859 13:37:51.832534 Starting [0;1;39mUser Login Management[0m...
860 13:37:51.840866 <47>[ 14.984629] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
861 13:37:52.430509 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
862 13:37:52.432403 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
863 13:37:52.435322 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
864 13:37:52.526474 <47>[ 15.670110] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
865 13:37:52.527407 Starting [0;1;39mPermit User Sessions[0m...
866 13:37:52.633587 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
867 13:37:52.739959 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
868 13:37:52.803965 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
869 13:37:53.118752 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
870 13:37:55.198242 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
871 13:37:55.276728 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
872 13:37:55.295745 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
873 13:37:55.312625 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
874 13:37:55.327098 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
875 13:37:55.392235 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
876 13:37:55.399817 <47>[ 18.543589] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
877 13:37:55.608962 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
878 13:37:55.661688 <47>[ 18.805538] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
879 13:37:55.672951 <47>[ 18.816611] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
880 13:37:55.734062
881 13:37:55.734246 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
882 13:37:55.734347
883 13:37:55.739265 debian-bullseye-arm64 login: root (automatic login)
884 13:37:55.739640
885 13:37:55.761894 <6>[ 18.905844] virtio_net virtio0 enp0s1: renamed from eth0
886 13:37:55.969912 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 22 12:09:38 UTC 2023 aarch64
887 13:37:55.970643
888 13:37:55.970852 The programs included with the Debian GNU/Linux system are free software;
889 13:37:55.970999 the exact distribution terms for each program are described in the
890 13:37:55.971115 individual files in /usr/share/doc/*/copyright.
891 13:37:55.971209
892 13:37:55.971573 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
893 13:37:55.971685 permitted by applicable law.
894 13:37:56.557891 <47>[ 19.701759] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
895 13:37:56.629112 <47>[ 19.772477] systemd-journald[105]: Data hash table of /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal has a fill level at 75.0 (3329 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
896 13:37:56.629499 <47>[ 19.773092] systemd-journald[105]: /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal: Journal header limits reached or header out-of-date, rotating.
897 13:37:56.629677 <47>[ 19.773548] systemd-journald[105]: Rotating...
898 13:37:56.639164 <47>[ 19.783113] systemd-journald[105]: Reserving 333 entries in field hash table.
899 13:37:56.666613 <47>[ 19.810260] systemd-journald[105]: Reserving 4437 entries in data hash table.
900 13:37:56.673584 <47>[ 19.817348] systemd-journald[105]: Vacuuming...
901 13:37:56.690000 <47>[ 19.833581] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
902 13:37:56.833800 <47>[ 19.977440] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
903 13:37:58.704529 <47>[ 21.848122] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
904 13:37:59.013013 Matched prompt #10: / #
906 13:37:59.013625 Setting prompt string to ['/ #']
907 13:37:59.013842 end: 2.2.1 login-action (duration 00:00:22) [common]
909 13:37:59.014300 end: 2.2 auto-login-action (duration 00:00:24) [common]
910 13:37:59.014480 start: 2.3 expect-shell-connection (timeout 00:04:34) [common]
911 13:37:59.014631 Setting prompt string to ['/ #']
912 13:37:59.014764 Forcing a shell prompt, looking for ['/ #']
914 13:37:59.065316 / #
915 13:37:59.065484 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
916 13:37:59.065635 Waiting using forced prompt support (timeout 00:02:30)
917 13:37:59.068290
918 13:37:59.076814 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
919 13:37:59.077015 start: 2.4 export-device-env (timeout 00:04:34) [common]
920 13:37:59.077180 end: 2.4 export-device-env (duration 00:00:00) [common]
921 13:37:59.077333 end: 2 boot-image-retry (duration 00:00:26) [common]
922 13:37:59.077489 start: 3 lava-test-retry (timeout 00:08:53) [common]
923 13:37:59.077643 start: 3.1 lava-test-shell (timeout 00:08:53) [common]
924 13:37:59.077795 Using namespace: common
926 13:37:59.178608 / # #
927 13:37:59.178802 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
928 13:37:59.179405 #
930 13:37:59.287834 / # mkdir /lava-652449
931 13:37:59.288622 mkdir /lava-652449
933 13:37:59.405999 / # mount /dev/disk/by-uuid/b8be8985-65a1-480f-85c6-d205c2651ff9 -t ext2 /lava-652449
934 13:37:59.407032 mount /dev/disk/by-uuid/b8be8985-65a1-480f-85c6-d205c2651ff9 -t ext2 /lava-652449
935 13:37:59.438565 <4>[ 22.582074] ext2 filesystem being mounted at /lava-652449 supports timestamps until 2038 (0x7fffffff)
937 13:37:59.578057 / # ls -la /lava-652449/bin/lava-test-runner
938 13:37:59.579029 ls -la /lava-652449/bin/lava-test-runner
939 13:37:59.617714 -rwxr-xr-x 1 root root 1039 Jun 22 13:36 /lava-652449/bin/lava-test-runner
940 13:37:59.631158 Using /lava-652449
942 13:37:59.732325 / # export SHELL=/bin/sh
943 13:37:59.733209 export SHELL=/bin/sh
945 13:37:59.842079 / # . /lava-652449/environment
946 13:37:59.842959 . /lava-652449/environment
948 13:37:59.953675 / # /lava-652449/bin/lava-test-runner /lava-652449/0
949 13:37:59.953894 Test shell timeout: 10s (minimum of the action and connection timeout)
950 13:37:59.954651 /lava-652449/bin/lava-test-runner /lava-652449/0
951 13:38:00.112893 + export TESTRUN_ID=0_timesync-off
952 13:38:00.113218 + cd /lava-652449/0/tests/0_timesync-off
953 13:38:00.115342 + cat uuid
954 13:38:00.123191 + UUID=652449_1.1.3.1
955 13:38:00.123640 + set +x
956 13:38:00.123869 <LAVA_SIGNAL_STARTRUN 0_timesync-off 652449_1.1.3.1>
957 13:38:00.124111 + systemctl stop systemd-timesyncd
958 13:38:00.124488 Received signal: <STARTRUN> 0_timesync-off 652449_1.1.3.1
959 13:38:00.124643 Starting test lava.0_timesync-off (652449_1.1.3.1)
960 13:38:00.124837 Skipping test definition patterns.
961 13:38:00.357208 + set +x
962 13:38:00.357757 <LAVA_SIGNAL_ENDRUN 0_timesync-off 652449_1.1.3.1>
963 13:38:00.358099 Received signal: <ENDRUN> 0_timesync-off 652449_1.1.3.1
964 13:38:00.358259 Ending use of test pattern.
965 13:38:00.358382 Ending test lava.0_timesync-off (652449_1.1.3.1), duration 0.23
967 13:38:00.399254 + export TESTRUN_ID=1_kselftest-arm64_qemu
968 13:38:00.399508 + cd /lava-652449/0/tests/1_kselftest-arm64_qemu
969 13:38:00.401951 + cat uuid
970 13:38:00.409968 + UUID=652449_1.1.3.5
971 13:38:00.410170 + set +x
972 13:38:00.410495 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 652449_1.1.3.5>
973 13:38:00.410612 + cd ./automated/linux/kselftest/
974 13:38:00.410898 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 652449_1.1.3.5
975 13:38:00.411001 Starting test lava.1_kselftest-arm64_qemu (652449_1.1.3.5)
976 13:38:00.411121 Skipping test definition patterns.
977 13:38:00.415617 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.31-61-g32a95f5a4e3b/arm64/defconfig/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip-gitlab -e -p /opt/kselftests/mainline/ -n 1 -i 1
978 13:38:00.511959 INFO: install_deps skipped
979 13:38:00.545877 --2023-06-22 13:38:00-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.31-61-g32a95f5a4e3b/arm64/defconfig/gcc-10/kselftest.tar.xz
980 13:38:00.716830 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
981 13:38:00.915845 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
982 13:38:01.105684 HTTP request sent, awaiting response... 200 OK
983 13:38:01.108700 Length: 2699392 (2.6M) [application/octet-stream]
984 13:38:01.110138 Saving to: 'kselftest.tar.xz'
985 13:38:01.111619
986 13:38:02.336347 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 161KB/s kselftest.tar.xz 8%[> ] 219.84K 344KB/s kselftest.tar.xz 34%[=====> ] 898.59K 934KB/s kselftest.tar.xz 89%[================> ] 2.31M 1.99MB/s kselftest.tar.xz 100%[===================>] 2.57M 2.19MB/s in 1.2s
987 13:38:02.336652
988 13:38:02.341289 2023-06-22 13:38:02 (2.19 MB/s) - 'kselftest.tar.xz' saved [2699392/2699392]
989 13:38:02.341452
990 13:38:05.450561 skiplist:
991 13:38:05.450820 ========================================
992 13:38:05.451511 ========================================
993 13:38:05.504959 arm64:tags_test
994 13:38:05.505280 arm64:run_tags_test.sh
995 13:38:05.505679 arm64:fake_sigreturn_bad_magic
996 13:38:05.505887 arm64:fake_sigreturn_bad_size
997 13:38:05.506060 arm64:fake_sigreturn_bad_size_for_magic0
998 13:38:05.506200 arm64:fake_sigreturn_duplicated_fpsimd
999 13:38:05.506412 arm64:fake_sigreturn_misaligned_sp
1000 13:38:05.506583 arm64:fake_sigreturn_missing_fpsimd
1001 13:38:05.506744 arm64:fake_sigreturn_sme_change_vl
1002 13:38:05.506904 arm64:fake_sigreturn_sve_change_vl
1003 13:38:05.507105 arm64:mangle_pstate_invalid_compat_toggle
1004 13:38:05.507269 arm64:mangle_pstate_invalid_daif_bits
1005 13:38:05.507440 arm64:mangle_pstate_invalid_mode_el1h
1006 13:38:05.507582 arm64:mangle_pstate_invalid_mode_el1t
1007 13:38:05.507712 arm64:mangle_pstate_invalid_mode_el2h
1008 13:38:05.507848 arm64:mangle_pstate_invalid_mode_el2t
1009 13:38:05.508063 arm64:mangle_pstate_invalid_mode_el3h
1010 13:38:05.508261 arm64:mangle_pstate_invalid_mode_el3t
1011 13:38:05.508434 arm64:sme_trap_no_sm
1012 13:38:05.508581 arm64:sme_trap_non_streaming
1013 13:38:05.508699 arm64:sme_trap_za
1014 13:38:05.508815 arm64:sme_vl
1015 13:38:05.508928 arm64:ssve_regs
1016 13:38:05.509042 arm64:sve_regs
1017 13:38:05.509157 arm64:sve_vl
1018 13:38:05.509301 arm64:za_no_regs
1019 13:38:05.509422 arm64:za_regs
1020 13:38:05.509537 arm64:pac
1021 13:38:05.509676 arm64:fp-stress
1022 13:38:05.509885 arm64:sve-ptrace
1023 13:38:05.510072 arm64:sve-probe-vls
1024 13:38:05.510238 arm64:vec-syscfg
1025 13:38:05.510394 arm64:za-fork
1026 13:38:05.510540 arm64:za-ptrace
1027 13:38:05.510681 arm64:check_buffer_fill
1028 13:38:05.510823 arm64:check_child_memory
1029 13:38:05.510965 arm64:check_gcr_el1_cswitch
1030 13:38:05.511107 arm64:check_ksm_options
1031 13:38:05.511249 arm64:check_mmap_options
1032 13:38:05.511389 arm64:check_prctl
1033 13:38:05.511530 arm64:check_tags_inclusion
1034 13:38:05.511669 arm64:check_user_mem
1035 13:38:05.511808 arm64:btitest
1036 13:38:05.511949 arm64:nobtitest
1037 13:38:05.512091 arm64:hwcap
1038 13:38:05.512238 arm64:ptrace
1039 13:38:05.512378 arm64:syscall-abi
1040 13:38:05.512518 arm64:tpidr2
1041 13:38:05.520668 ============== Tests to run ===============
1042 13:38:05.525363 arm64:tags_test
1043 13:38:05.525830 arm64:run_tags_test.sh
1044 13:38:05.525994 arm64:fake_sigreturn_bad_magic
1045 13:38:05.526172 arm64:fake_sigreturn_bad_size
1046 13:38:05.526343 arm64:fake_sigreturn_bad_size_for_magic0
1047 13:38:05.526479 arm64:fake_sigreturn_duplicated_fpsimd
1048 13:38:05.526624 arm64:fake_sigreturn_misaligned_sp
1049 13:38:05.526749 arm64:fake_sigreturn_missing_fpsimd
1050 13:38:05.526868 arm64:fake_sigreturn_sme_change_vl
1051 13:38:05.527042 arm64:fake_sigreturn_sve_change_vl
1052 13:38:05.527193 arm64:mangle_pstate_invalid_compat_toggle
1053 13:38:05.527333 arm64:mangle_pstate_invalid_daif_bits
1054 13:38:05.527543 arm64:mangle_pstate_invalid_mode_el1h
1055 13:38:05.527744 arm64:mangle_pstate_invalid_mode_el1t
1056 13:38:05.527948 arm64:mangle_pstate_invalid_mode_el2h
1057 13:38:05.528098 arm64:mangle_pstate_invalid_mode_el2t
1058 13:38:05.528265 arm64:mangle_pstate_invalid_mode_el3h
1059 13:38:05.528414 arm64:mangle_pstate_invalid_mode_el3t
1060 13:38:05.528550 arm64:sme_trap_no_sm
1061 13:38:05.528685 arm64:sme_trap_non_streaming
1062 13:38:05.528817 arm64:sme_trap_za
1063 13:38:05.528932 arm64:sme_vl
1064 13:38:05.529044 arm64:ssve_regs
1065 13:38:05.529192 arm64:sve_regs
1066 13:38:05.529320 arm64:sve_vl
1067 13:38:05.529433 arm64:za_no_regs
1068 13:38:05.529546 arm64:za_regs
1069 13:38:05.529677 arm64:pac
1070 13:38:05.529794 arm64:fp-stress
1071 13:38:05.529906 arm64:sve-ptrace
1072 13:38:05.530018 arm64:sve-probe-vls
1073 13:38:05.530135 arm64:vec-syscfg
1074 13:38:05.530300 arm64:za-fork
1075 13:38:05.530462 arm64:za-ptrace
1076 13:38:05.530585 arm64:check_buffer_fill
1077 13:38:05.530702 arm64:check_child_memory
1078 13:38:05.530815 arm64:check_gcr_el1_cswitch
1079 13:38:05.530930 arm64:check_ksm_options
1080 13:38:05.531045 arm64:check_mmap_options
1081 13:38:05.531159 arm64:check_prctl
1082 13:38:05.531275 arm64:check_tags_inclusion
1083 13:38:05.531391 arm64:check_user_mem
1084 13:38:05.531507 arm64:btitest
1085 13:38:05.531621 arm64:nobtitest
1086 13:38:05.531734 arm64:hwcap
1087 13:38:05.531848 arm64:ptrace
1088 13:38:05.531963 arm64:syscall-abi
1089 13:38:05.532078 arm64:tpidr2
1090 13:38:05.532220 ===========End Tests to run ===============
1091 13:38:06.429003 <12>[ 29.572946] kselftest: Running tests in arm64
1092 13:38:06.457500 TAP version 13
1093 13:38:06.475510 1..48
1094 13:38:06.522918 # selftests: arm64: tags_test
1095 13:38:06.574750 ok 1 selftests: arm64: tags_test
1096 13:38:06.620629 # selftests: arm64: run_tags_test.sh
1097 13:38:06.671679 # --------------------
1098 13:38:06.671945 # running tags test
1099 13:38:06.672073 # --------------------
1100 13:38:06.672192 # [PASS]
1101 13:38:06.679154 ok 2 selftests: arm64: run_tags_test.sh
1102 13:38:06.723064 # selftests: arm64: fake_sigreturn_bad_magic
1103 13:38:06.772340 # Registered handlers for all signals.
1104 13:38:06.772663 # Detected MINSTKSIGSZ:10000
1105 13:38:06.772839 # Testcase initialized.
1106 13:38:06.772988 # uc context validated.
1107 13:38:06.773126 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1108 13:38:06.773470 # Handled SIG_COPYCTX
1109 13:38:06.773601 # Available space:3536
1110 13:38:06.773735 # Using badly built context - ERR: BAD MAGIC !
1111 13:38:06.773855 # SIG_OK -- SP:0xFFFFE1025A00 si_addr@:0xffffe1025a00 si_code:2 token@:0xffffe10247a0 offset:-4704
1112 13:38:06.773996 # ==>> completed. PASS(1)
1113 13:38:06.774156 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1114 13:38:06.774280 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE10247A0
1115 13:38:06.780852 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1116 13:38:06.825349 # selftests: arm64: fake_sigreturn_bad_size
1117 13:38:06.873066 # Registered handlers for all signals.
1118 13:38:06.873379 # Detected MINSTKSIGSZ:10000
1119 13:38:06.873527 # Testcase initialized.
1120 13:38:06.873662 # uc context validated.
1121 13:38:06.873787 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1122 13:38:06.873906 # Handled SIG_COPYCTX
1123 13:38:06.874026 # Available space:3536
1124 13:38:06.874143 # uc context validated.
1125 13:38:06.874260 # Using badly built context - ERR: Bad size for esr_context
1126 13:38:06.874597 # SIG_OK -- SP:0xFFFFD40DC0D0 si_addr@:0xffffd40dc0d0 si_code:2 token@:0xffffd40dae70 offset:-4704
1127 13:38:06.874731 # ==>> completed. PASS(1)
1128 13:38:06.874850 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1129 13:38:06.874969 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD40DAE70
1130 13:38:06.881514 ok 4 selftests: arm64: fake_sigreturn_bad_size
1131 13:38:06.924937 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1132 13:38:06.974723 # Registered handlers for all signals.
1133 13:38:06.975034 # Detected MINSTKSIGSZ:10000
1134 13:38:06.975196 # Testcase initialized.
1135 13:38:06.975412 # uc context validated.
1136 13:38:06.975803 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1137 13:38:06.975940 # Handled SIG_COPYCTX
1138 13:38:06.976061 # Available space:3536
1139 13:38:06.976178 # Using badly built context - ERR: Bad size for terminator
1140 13:38:06.976294 # SIG_OK -- SP:0xFFFFCA078CA0 si_addr@:0xffffca078ca0 si_code:2 token@:0xffffca077a40 offset:-4704
1141 13:38:06.976412 # ==>> completed. PASS(1)
1142 13:38:06.976529 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1143 13:38:06.976646 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCA077A40
1144 13:38:06.984476 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1145 13:38:07.027363 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1146 13:38:07.076007 # Registered handlers for all signals.
1147 13:38:07.076223 # Detected MINSTKSIGSZ:10000
1148 13:38:07.076328 # Testcase initialized.
1149 13:38:07.076416 # uc context validated.
1150 13:38:07.076484 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1151 13:38:07.076548 # Handled SIG_COPYCTX
1152 13:38:07.076606 # Available space:3536
1153 13:38:07.076667 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1154 13:38:07.085373 # SIG_OK -- SP:0xFFFFD70AF4C0 si_addr@:0xffffd70af4c0 si_code:2 token@:0xffffd70ae260 offset:-4704
1155 13:38:07.085567 # ==>> completed. PASS(1)
1156 13:38:07.085676 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1157 13:38:07.085757 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD70AE260
1158 13:38:07.086025 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1159 13:38:07.138198 # selftests: arm64: fake_sigreturn_misaligned_sp
1160 13:38:07.186018 # Registered handlers for all signals.
1161 13:38:07.186317 # Detected MINSTKSIGSZ:10000
1162 13:38:07.186457 # Testcase initialized.
1163 13:38:07.186579 # uc context validated.
1164 13:38:07.186916 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1165 13:38:07.188030 # Handled SIG_COPYCTX
1166 13:38:07.188491 # SIG_OK -- SP:0xFFFFE3DC5073 si_addr@:0xffffe3dc5073 si_code:2 token@:0xffffe3dc5073 offset:0
1167 13:38:07.188669 # ==>> completed. PASS(1)
1168 13:38:07.188816 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1169 13:38:07.188937 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE3DC5073
1170 13:38:07.195197 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1171 13:38:07.238125 # selftests: arm64: fake_sigreturn_missing_fpsimd
1172 13:38:07.288071 # Registered handlers for all signals.
1173 13:38:07.288329 # Detected MINSTKSIGSZ:10000
1174 13:38:07.289947 # Testcase initialized.
1175 13:38:07.290278 # uc context validated.
1176 13:38:07.290401 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1177 13:38:07.290501 # Handled SIG_COPYCTX
1178 13:38:07.290616 # Mangling template header. Spare space:4096
1179 13:38:07.290721 # Using badly built context - ERR: Missing FPSIMD
1180 13:38:07.290833 # SIG_OK -- SP:0xFFFFDEAAA7D0 si_addr@:0xffffdeaaa7d0 si_code:2 token@:0xffffdeaa9570 offset:-4704
1181 13:38:07.290921 # ==>> completed. PASS(1)
1182 13:38:07.291048 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1183 13:38:07.291177 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDEAA9570
1184 13:38:07.298064 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1185 13:38:07.341971 # selftests: arm64: fake_sigreturn_sme_change_vl
1186 13:38:07.390960 # Registered handlers for all signals.
1187 13:38:07.391265 # Detected MINSTKSIGSZ:10000
1188 13:38:07.391450 # Required Features: [ SME ] supported
1189 13:38:07.391606 # Incompatible Features: [] absent
1190 13:38:07.391776 # Testcase initialized.
1191 13:38:07.391919 # uc context validated.
1192 13:38:07.392286 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1193 13:38:07.392426 # Handled SIG_COPYCTX
1194 13:38:07.392567 # Attempting to change VL from 16 to 256
1195 13:38:07.392705 # SIG_OK -- SP:0xFFFFCDA30CB0 si_addr@:0xffffcda30cb0 si_code:2 token@:0xffffcda2fa50 offset:-4704
1196 13:38:07.392846 # ==>> completed. PASS(1)
1197 13:38:07.392982 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1198 13:38:07.393121 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCDA2FA50
1199 13:38:07.399372 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1200 13:38:07.445110 # selftests: arm64: fake_sigreturn_sve_change_vl
1201 13:38:07.496375 # Registered handlers for all signals.
1202 13:38:07.496839 # Detected MINSTKSIGSZ:10000
1203 13:38:07.497116 # Required Features: [ SVE ] supported
1204 13:38:07.497288 # Incompatible Features: [] absent
1205 13:38:07.497410 # Testcase initialized.
1206 13:38:07.497523 # uc context validated.
1207 13:38:07.497633 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1208 13:38:07.497835 # Handled SIG_COPYCTX
1209 13:38:07.498031 # Attempting to change VL from 16 to 256
1210 13:38:07.498168 # SIG_OK -- SP:0xFFFFCDCFA3E0 si_addr@:0xffffcdcfa3e0 si_code:2 token@:0xffffcdcf9180 offset:-4704
1211 13:38:07.498311 # ==>> completed. PASS(1)
1212 13:38:07.498449 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1213 13:38:07.498588 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCDCF9180
1214 13:38:07.506019 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1215 13:38:07.549546 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1216 13:38:07.598600 # Registered handlers for all signals.
1217 13:38:07.599074 # Detected MINSTKSIGSZ:10000
1218 13:38:07.599242 # Testcase initialized.
1219 13:38:07.599364 # uc context validated.
1220 13:38:07.599479 # Handled SIG_TRIG
1221 13:38:07.599593 # SIG_OK -- SP:0xFFFFFFD03C70 si_addr@:0xffffffd03c70 si_code:2 token@:(nil) offset:-281474973580400
1222 13:38:07.599708 # ==>> completed. PASS(1)
1223 13:38:07.599846 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1224 13:38:07.606571 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1225 13:38:07.651589 # selftests: arm64: mangle_pstate_invalid_daif_bits
1226 13:38:07.699138 # Registered handlers for all signals.
1227 13:38:07.699328 # Detected MINSTKSIGSZ:10000
1228 13:38:07.699634 # Testcase initialized.
1229 13:38:07.699723 # uc context validated.
1230 13:38:07.699814 # Handled SIG_TRIG
1231 13:38:07.699892 # SIG_OK -- SP:0xFFFFCA1122C0 si_addr@:0xffffca1122c0 si_code:2 token@:(nil) offset:-281474071864000
1232 13:38:07.699967 # ==>> completed. PASS(1)
1233 13:38:07.701342 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1234 13:38:07.707324 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1235 13:38:07.750878 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1236 13:38:07.800106 # Registered handlers for all signals.
1237 13:38:07.800295 # Detected MINSTKSIGSZ:10000
1238 13:38:07.800460 # Testcase initialized.
1239 13:38:07.800815 # uc context validated.
1240 13:38:07.800945 # Handled SIG_TRIG
1241 13:38:07.801064 # SIG_OK -- SP:0xFFFFC42F5280 si_addr@:0xffffc42f5280 si_code:2 token@:(nil) offset:-281473973179008
1242 13:38:07.801182 # ==>> completed. PASS(1)
1243 13:38:07.801297 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1244 13:38:07.806700 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1245 13:38:07.853859 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1246 13:38:07.900057 # Registered handlers for all signals.
1247 13:38:07.900173 # Detected MINSTKSIGSZ:10000
1248 13:38:07.900469 # Testcase initialized.
1249 13:38:07.900567 # uc context validated.
1250 13:38:07.900670 # Handled SIG_TRIG
1251 13:38:07.900811 # SIG_OK -- SP:0xFFFFE7EA8180 si_addr@:0xffffe7ea8180 si_code:2 token@:(nil) offset:-281474572648832
1252 13:38:07.900932 # ==>> completed. PASS(1)
1253 13:38:07.901050 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1254 13:38:07.908713 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1255 13:38:07.954588 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1256 13:38:08.004661 # Registered handlers for all signals.
1257 13:38:08.004785 # Detected MINSTKSIGSZ:10000
1258 13:38:08.005096 # Testcase initialized.
1259 13:38:08.005217 # uc context validated.
1260 13:38:08.005328 # Handled SIG_TRIG
1261 13:38:08.005459 # SIG_OK -- SP:0xFFFFCD544CA0 si_addr@:0xffffcd544ca0 si_code:2 token@:(nil) offset:-281474126597280
1262 13:38:08.005576 # ==>> completed. PASS(1)
1263 13:38:08.007013 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1264 13:38:08.012840 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1265 13:38:08.057238 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1266 13:38:08.109490 # Registered handlers for all signals.
1267 13:38:08.109923 # Detected MINSTKSIGSZ:10000
1268 13:38:08.110117 # Testcase initialized.
1269 13:38:08.110309 # uc context validated.
1270 13:38:08.110453 # Handled SIG_TRIG
1271 13:38:08.110605 # SIG_OK -- SP:0xFFFFD37E9CD0 si_addr@:0xffffd37e9cd0 si_code:2 token@:(nil) offset:-281474230033616
1272 13:38:08.110734 # ==>> completed. PASS(1)
1273 13:38:08.110859 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1274 13:38:08.118921 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1275 13:38:08.166249 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1276 13:38:08.212280 # Registered handlers for all signals.
1277 13:38:08.212730 # Detected MINSTKSIGSZ:10000
1278 13:38:08.212890 # Testcase initialized.
1279 13:38:08.213041 # uc context validated.
1280 13:38:08.213184 # Handled SIG_TRIG
1281 13:38:08.214222 # SIG_OK -- SP:0xFFFFFB0F1500 si_addr@:0xfffffb0f1500 si_code:2 token@:(nil) offset:-281474893812992
1282 13:38:08.214623 # ==>> completed. PASS(1)
1283 13:38:08.214778 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1284 13:38:08.220315 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1285 13:38:08.268428 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1286 13:38:08.321286 # Registered handlers for all signals.
1287 13:38:08.321597 # Detected MINSTKSIGSZ:10000
1288 13:38:08.322002 # Testcase initialized.
1289 13:38:08.322141 # uc context validated.
1290 13:38:08.322262 # Handled SIG_TRIG
1291 13:38:08.322425 # SIG_OK -- SP:0xFFFFFB463640 si_addr@:0xfffffb463640 si_code:2 token@:(nil) offset:-281474897425984
1292 13:38:08.322567 # ==>> completed. PASS(1)
1293 13:38:08.322686 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1294 13:38:08.329167 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1295 13:38:08.371794 # selftests: arm64: sme_trap_no_sm
1296 13:38:08.492593 # Registered handlers for all signals.
1297 13:38:08.492842 # Detected MINSTKSIGSZ:10000
1298 13:38:08.492932 # Required Features: [ SME ] supported
1299 13:38:08.493021 # Incompatible Features: [] absent
1300 13:38:08.493108 # Testcase initialized.
1301 13:38:08.493410 # SIG_OK -- SP:0xFFFFD3153600 si_addr@:0xaaaab14f2514 si_code:1 token@:(nil) offset:-187650095916308
1302 13:38:08.493519 # ==>> completed. PASS(1)
1303 13:38:08.493610 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1304 13:38:08.510209 ok 19 selftests: arm64: sme_trap_no_sm
1305 13:38:08.604157 # selftests: arm64: sme_trap_non_streaming
1306 13:38:08.670449 # Registered handlers for all signals.
1307 13:38:08.670785 # Detected MINSTKSIGSZ:10000
1308 13:38:08.671171 # Required Features: [] NOT supported
1309 13:38:08.671313 # Incompatible Features: [] supported
1310 13:38:08.671433 # ==>> completed. SKIP.
1311 13:38:08.671548 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1312 13:38:08.678967 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1313 13:38:08.726969 # selftests: arm64: sme_trap_za
1314 13:38:08.781405 # Registered handlers for all signals.
1315 13:38:08.781623 # Detected MINSTKSIGSZ:10000
1316 13:38:08.781843 # Testcase initialized.
1317 13:38:08.782201 # SIG_OK -- SP:0xFFFFCA8590B0 si_addr@:0xaaaab4262510 si_code:1 token@:(nil) offset:-187650143560976
1318 13:38:08.782357 # ==>> completed. PASS(1)
1319 13:38:08.782479 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1320 13:38:08.790225 ok 21 selftests: arm64: sme_trap_za
1321 13:38:08.841727 # selftests: arm64: sme_vl
1322 13:38:08.892473 # Registered handlers for all signals.
1323 13:38:08.892842 # Detected MINSTKSIGSZ:10000
1324 13:38:08.893043 # Required Features: [ SME ] supported
1325 13:38:08.893234 # Incompatible Features: [] absent
1326 13:38:08.893668 # Testcase initialized.
1327 13:38:08.893830 # uc context validated.
1328 13:38:08.894013 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1329 13:38:08.894191 # Handled SIG_COPYCTX
1330 13:38:08.894380 # got expected VL 32
1331 13:38:08.894567 # ==>> completed. PASS(1)
1332 13:38:08.894755 # # SME VL :: Check that we get the right SME VL reported
1333 13:38:08.901163 ok 22 selftests: arm64: sme_vl
1334 13:38:08.950895 # selftests: arm64: ssve_regs
1335 13:38:09.139960 # Registered handlers for all signals.
1336 13:38:09.140311 # Detected MINSTKSIGSZ:10000
1337 13:38:09.140748 # Required Features: [ SME FA64 ] supported
1338 13:38:09.140940 # Incompatible Features: [] absent
1339 13:38:09.141089 # Testcase initialized.
1340 13:38:09.141243 # Testing VL 256
1341 13:38:09.141387 # Validating EXTRA...
1342 13:38:09.141521 # uc context validated.
1343 13:38:09.141668 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1344 13:38:09.141870 # Handled SIG_COPYCTX
1345 13:38:09.142023 # Got expected size 8752 and VL 256
1346 13:38:09.142165 # Testing VL 128
1347 13:38:09.142305 # Validating EXTRA...
1348 13:38:09.142442 # uc context validated.
1349 13:38:09.142579 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1350 13:38:09.142760 # Handled SIG_COPYCTX
1351 13:38:09.142890 # Got expected size 4384 and VL 128
1352 13:38:09.143028 # Testing VL 64
1353 13:38:09.143166 # uc context validated.
1354 13:38:09.143304 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1355 13:38:09.143442 # Handled SIG_COPYCTX
1356 13:38:09.143578 # Got expected size 2208 and VL 64
1357 13:38:09.143715 # Testing VL 32
1358 13:38:09.143851 # uc context validated.
1359 13:38:09.143988 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1360 13:38:09.144125 # Handled SIG_COPYCTX
1361 13:38:09.144261 # Got expected size 1120 and VL 32
1362 13:38:09.144400 # Testing VL 16
1363 13:38:09.144537 # uc context validated.
1364 13:38:09.144672 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1365 13:38:09.144811 # Handled SIG_COPYCTX
1366 13:38:09.144949 # Got expected size 576 and VL 16
1367 13:38:09.145086 # ==>> completed. PASS(1)
1368 13:38:09.145223 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1369 13:38:09.151445 ok 23 selftests: arm64: ssve_regs
1370 13:38:09.196833 # selftests: arm64: sve_regs
1371 13:38:09.608664 # Registered handlers for all signals.
1372 13:38:09.609160 # Detected MINSTKSIGSZ:10000
1373 13:38:09.609351 # Required Features: [ SVE ] supported
1374 13:38:09.609521 # Incompatible Features: [] absent
1375 13:38:09.609701 # Testcase initialized.
1376 13:38:09.609890 # Testing VL 256
1377 13:38:09.610195 # Validating EXTRA...
1378 13:38:09.610348 # uc context validated.
1379 13:38:09.610501 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1380 13:38:09.610623 # Handled SIG_COPYCTX
1381 13:38:09.610738 # Got expected size 8752 and VL 256
1382 13:38:09.610851 # Testing VL 240
1383 13:38:09.610966 # Validating EXTRA...
1384 13:38:09.611078 # uc context validated.
1385 13:38:09.611190 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1386 13:38:09.611302 # Handled SIG_COPYCTX
1387 13:38:09.611413 # Got expected size 8208 and VL 240
1388 13:38:09.611524 # Testing VL 224
1389 13:38:09.611635 # Validating EXTRA...
1390 13:38:09.611746 # uc context validated.
1391 13:38:09.617823 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1392 13:38:09.618078 # Handled SIG_COPYCTX
1393 13:38:09.618470 # Got expected size 7664 and VL 224
1394 13:38:09.618633 # Testing VL 208
1395 13:38:09.618803 # Validating EXTRA...
1396 13:38:09.618947 # uc context validated.
1397 13:38:09.619088 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1398 13:38:09.619238 # Handled SIG_COPYCTX
1399 13:38:09.619464 # Got expected size 7120 and VL 208
1400 13:38:09.619637 # Testing VL 192
1401 13:38:09.619794 # Validating EXTRA...
1402 13:38:09.619983 # uc context validated.
1403 13:38:09.620145 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1404 13:38:09.620300 # Handled SIG_COPYCTX
1405 13:38:09.620453 # Got expected size 6576 and VL 192
1406 13:38:09.620607 # Testing VL 176
1407 13:38:09.620760 # Validating EXTRA...
1408 13:38:09.620916 # uc context validated.
1409 13:38:09.621104 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1410 13:38:09.621265 # Handled SIG_COPYCTX
1411 13:38:09.621420 # Got expected size 6032 and VL 176
1412 13:38:09.621571 # Testing VL 160
1413 13:38:09.622167 # Validating EXTRA...
1414 13:38:09.622329 # uc context validated.
1415 13:38:09.622459 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1416 13:38:09.622577 # Handled SIG_COPYCTX
1417 13:38:09.622689 # Got expected size 5488 and VL 160
1418 13:38:09.622802 # Testing VL 144
1419 13:38:09.622917 # Validating EXTRA...
1420 13:38:09.623028 # uc context validated.
1421 13:38:09.623138 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1422 13:38:09.623250 # Handled SIG_COPYCTX
1423 13:38:09.623361 # Got expected size 4944 and VL 144
1424 13:38:09.623473 # Testing VL 128
1425 13:38:09.623584 # Validating EXTRA...
1426 13:38:09.623695 # uc context validated.
1427 13:38:09.623843 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1428 13:38:09.623971 # Handled SIG_COPYCTX
1429 13:38:09.624085 # Got expected size 4384 and VL 128
1430 13:38:09.624198 # Testing VL 112
1431 13:38:09.624310 # Validating EXTRA...
1432 13:38:09.624422 # uc context validated.
1433 13:38:09.624534 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1434 13:38:09.624647 # Handled SIG_COPYCTX
1435 13:38:09.624759 # Got expected size 3840 and VL 112
1436 13:38:09.624874 # Testing VL 96
1437 13:38:09.624992 # uc context validated.
1438 13:38:09.625107 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1439 13:38:09.625219 # Handled SIG_COPYCTX
1440 13:38:09.625330 # Got expected size 3296 and VL 96
1441 13:38:09.625443 # Testing VL 80
1442 13:38:09.625554 # uc context validated.
1443 13:38:09.625717 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1444 13:38:09.625926 # Handled SIG_COPYCTX
1445 13:38:09.626959 # Got expected size 2752 and VL 80
1446 13:38:09.627147 # Testing VL 64
1447 13:38:09.627317 # uc context validated.
1448 13:38:09.627489 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1449 13:38:09.627689 # Handled SIG_COPYCTX
1450 13:38:09.627826 # Got expected size 2208 and VL 64
1451 13:38:09.627950 # Testing VL 48
1452 13:38:09.628072 # uc context validated.
1453 13:38:09.628190 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1454 13:38:09.628312 # Handled SIG_COPYCTX
1455 13:38:09.628434 # Got expected size 1664 and VL 48
1456 13:38:09.628615 # Testing VL 32
1457 13:38:09.628743 # uc context validated.
1458 13:38:09.628900 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1459 13:38:09.629081 # Handled SIG_COPYCTX
1460 13:38:09.629224 # Got expected size 1120 and VL 32
1461 13:38:09.629343 # Testing VL 16
1462 13:38:09.629456 # uc context validated.
1463 13:38:09.629569 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1464 13:38:09.629697 # Handled SIG_COPYCTX
1465 13:38:09.629817 # Got expected size 576 and VL 16
1466 13:38:09.629960 # ==>> completed. PASS(1)
1467 13:38:09.630074 # # SVE registers :: Check that we get the right SVE registers reported
1468 13:38:09.630187 ok 24 selftests: arm64: sve_regs
1469 13:38:09.671653 # selftests: arm64: sve_vl
1470 13:38:09.722059 # Registered handlers for all signals.
1471 13:38:09.722301 # Detected MINSTKSIGSZ:10000
1472 13:38:09.722422 # Required Features: [ SVE ] supported
1473 13:38:09.722538 # Incompatible Features: [] absent
1474 13:38:09.722652 # Testcase initialized.
1475 13:38:09.722789 # uc context validated.
1476 13:38:09.722906 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1477 13:38:09.723020 # Handled SIG_COPYCTX
1478 13:38:09.723137 # got expected VL 64
1479 13:38:09.723250 # ==>> completed. PASS(1)
1480 13:38:09.723362 # # SVE VL :: Check that we get the right SVE VL reported
1481 13:38:09.730172 ok 25 selftests: arm64: sve_vl
1482 13:38:09.777247 # selftests: arm64: za_no_regs
1483 13:38:09.837589 # Registered handlers for all signals.
1484 13:38:09.837859 # Detected MINSTKSIGSZ:10000
1485 13:38:09.838049 # Required Features: [ SME ] supported
1486 13:38:09.839071 # Incompatible Features: [] absent
1487 13:38:09.839241 # Testcase initialized.
1488 13:38:09.839683 # Testing VL 256
1489 13:38:09.839859 # uc context validated.
1490 13:38:09.840040 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1491 13:38:09.840221 # Handled SIG_COPYCTX
1492 13:38:09.840375 # Got expected size 16 and VL 256
1493 13:38:09.840535 # Testing VL 128
1494 13:38:09.840682 # uc context validated.
1495 13:38:09.840839 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1496 13:38:09.840983 # Handled SIG_COPYCTX
1497 13:38:09.841106 # Got expected size 16 and VL 128
1498 13:38:09.841261 # Testing VL 64
1499 13:38:09.841393 # uc context validated.
1500 13:38:09.841518 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1501 13:38:09.841639 # Handled SIG_COPYCTX
1502 13:38:09.841775 # Got expected size 16 and VL 64
1503 13:38:09.841899 # Testing VL 32
1504 13:38:09.842019 # uc context validated.
1505 13:38:09.842139 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1506 13:38:09.842257 # Handled SIG_COPYCTX
1507 13:38:09.842376 # Got expected size 16 and VL 32
1508 13:38:09.842491 # Testing VL 16
1509 13:38:09.842606 # uc context validated.
1510 13:38:09.842720 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1511 13:38:09.842834 # Handled SIG_COPYCTX
1512 13:38:09.842946 # Got expected size 16 and VL 16
1513 13:38:09.843063 # ==>> completed. PASS(1)
1514 13:38:09.843176 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1515 13:38:09.848046 ok 26 selftests: arm64: za_no_regs
1516 13:38:09.894991 # selftests: arm64: za_regs
1517 13:38:10.073064 # Registered handlers for all signals.
1518 13:38:10.073321 # Detected MINSTKSIGSZ:10000
1519 13:38:10.073737 # Required Features: [ SME ] supported
1520 13:38:10.073869 # Incompatible Features: [] absent
1521 13:38:10.073981 # Testcase initialized.
1522 13:38:10.074070 # Testing VL 256
1523 13:38:10.074160 # Validating EXTRA...
1524 13:38:10.074246 # uc context validated.
1525 13:38:10.074350 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1526 13:38:10.074441 # Handled SIG_COPYCTX
1527 13:38:10.074560 # Got expected size 65552 and VL 256
1528 13:38:10.074651 # Testing VL 128
1529 13:38:10.074762 # Validating EXTRA...
1530 13:38:10.074848 # uc context validated.
1531 13:38:10.074956 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1532 13:38:10.075041 # Handled SIG_COPYCTX
1533 13:38:10.075152 # Got expected size 16400 and VL 128
1534 13:38:10.075239 # Testing VL 64
1535 13:38:10.075349 # Validating EXTRA...
1536 13:38:10.075455 # uc context validated.
1537 13:38:10.075569 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1538 13:38:10.075653 # Handled SIG_COPYCTX
1539 13:38:10.075759 # Got expected size 4112 and VL 64
1540 13:38:10.075844 # Testing VL 32
1541 13:38:10.075955 # uc context validated.
1542 13:38:10.076039 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1543 13:38:10.076148 # Handled SIG_COPYCTX
1544 13:38:10.076229 # Got expected size 1040 and VL 32
1545 13:38:10.076359 # Testing VL 16
1546 13:38:10.076473 # uc context validated.
1547 13:38:10.076567 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1548 13:38:10.076681 # Handled SIG_COPYCTX
1549 13:38:10.076770 # Got expected size 272 and VL 16
1550 13:38:10.076888 # ==>> completed. PASS(1)
1551 13:38:10.076971 # # ZA register :: Check that we get the right ZA registers reported
1552 13:38:10.088697 ok 27 selftests: arm64: za_regs
1553 13:38:10.135740 # selftests: arm64: pac
1554 13:38:10.338842 # TAP version 13
1555 13:38:10.339173 # 1..7
1556 13:38:10.339359 # # Starting 7 tests from 1 test cases.
1557 13:38:10.339735 # # RUN global.corrupt_pac ...
1558 13:38:10.339883 # # OK global.corrupt_pac
1559 13:38:10.340075 # ok 1 global.corrupt_pac
1560 13:38:10.340250 # # RUN global.pac_instructions_not_nop ...
1561 13:38:10.340424 # # OK global.pac_instructions_not_nop
1562 13:38:10.340590 # ok 2 global.pac_instructions_not_nop
1563 13:38:10.340751 # # RUN global.pac_instructions_not_nop_generic ...
1564 13:38:10.340920 # # OK global.pac_instructions_not_nop_generic
1565 13:38:10.341087 # ok 3 global.pac_instructions_not_nop_generic
1566 13:38:10.341290 # # RUN global.single_thread_different_keys ...
1567 13:38:10.341462 # # OK global.single_thread_different_keys
1568 13:38:10.349973 # ok 4 global.single_thread_different_keys
1569 13:38:10.350213 # # RUN global.exec_changed_keys ...
1570 13:38:10.350589 # # OK global.exec_changed_keys
1571 13:38:10.350747 # ok 5 global.exec_changed_keys
1572 13:38:10.350896 # # RUN global.context_switch_keep_keys ...
1573 13:38:10.351039 # # OK global.context_switch_keep_keys
1574 13:38:10.351181 # ok 6 global.context_switch_keep_keys
1575 13:38:10.351320 # # RUN global.context_switch_keep_keys_generic ...
1576 13:38:10.351495 # # OK global.context_switch_keep_keys_generic
1577 13:38:10.351629 # ok 7 global.context_switch_keep_keys_generic
1578 13:38:10.351769 # # PASSED: 7 / 7 tests passed.
1579 13:38:10.351910 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1580 13:38:10.352050 ok 28 selftests: arm64: pac
1581 13:38:10.397296 # selftests: arm64: fp-stress
1582 13:38:26.117982 # TAP version 13
1583 13:38:26.118399 # 1..27
1584 13:38:26.118559 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1585 13:38:26.118722 # # Will run for 10s
1586 13:38:26.118854 # # Started FPSIMD-0-0
1587 13:38:26.118982 # # Started SVE-VL-256-0
1588 13:38:26.119110 # # Started SVE-VL-240-0
1589 13:38:26.119262 # # Started SVE-VL-224-0
1590 13:38:26.119390 # # Started SVE-VL-208-0
1591 13:38:26.119518 # # Started SVE-VL-192-0
1592 13:38:26.119649 # # Started SVE-VL-176-0
1593 13:38:26.119814 # # Started SVE-VL-160-0
1594 13:38:26.119948 # # Started SVE-VL-144-0
1595 13:38:26.120100 # # Started SVE-VL-128-0
1596 13:38:26.120232 # # Started SVE-VL-112-0
1597 13:38:26.120358 # # Started SVE-VL-96-0
1598 13:38:26.120482 # # Started SVE-VL-80-0
1599 13:38:26.120599 # # Started SVE-VL-64-0
1600 13:38:26.120735 # # Started SVE-VL-48-0
1601 13:38:26.120854 # # Started SVE-VL-32-0
1602 13:38:26.126294 # # Started SVE-VL-16-0
1603 13:38:26.126538 # # Started SSVE-VL-256-0
1604 13:38:26.126634 # # Started ZA-VL-256-0
1605 13:38:26.126720 # # Started SSVE-VL-128-0
1606 13:38:26.126805 # # Started ZA-VL-128-0
1607 13:38:26.126892 # # Started SSVE-VL-64-0
1608 13:38:26.126977 # # Started ZA-VL-64-0
1609 13:38:26.127061 # # Started SSVE-VL-32-0
1610 13:38:26.127146 # # Started ZA-VL-32-0
1611 13:38:26.127442 # # Started SSVE-VL-16-0
1612 13:38:26.127533 # # Started ZA-VL-16-0
1613 13:38:26.127619 # # SVE-VL-256-0: Vector length: 2048 bits
1614 13:38:26.127704 # # SVE-VL-256-0: PID: 909
1615 13:38:26.127789 # # SVE-VL-224-0: Vector length: 1792 bits
1616 13:38:26.127874 # # SVE-VL-224-0: PID: 911
1617 13:38:26.127959 # # SVE-VL-192-0: Vector length: 1536 bits
1618 13:38:26.128040 # # SVE-VL-192-0: PID: 913
1619 13:38:26.128124 # # SVE-VL-240-0: Vector length: 1920 bits
1620 13:38:26.128209 # # SVE-VL-240-0: PID: 910
1621 13:38:26.128292 # # SVE-VL-208-0: Vector length: 1664 bits
1622 13:38:26.128408 # # FPSIMD-0-0: Vector length: 128 bits
1623 13:38:26.128499 # # FPSIMD-0-0: PID: 908
1624 13:38:26.128576 # # SVE-VL-208-0: PID: 912
1625 13:38:26.128653 # # SVE-VL-48-0: Vector length: 384 bits
1626 13:38:26.128728 # # SVE-VL-48-0: PID: 922
1627 13:38:26.128805 # # SVE-VL-160-0: Vector length: 1280 bits
1628 13:38:26.128879 # # SVE-VL-160-0: PID: 915
1629 13:38:26.131187 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1630 13:38:26.131310 # # SSVE-VL-256-0: PID: 925
1631 13:38:26.131379 # # SVE-VL-80-0: Vector length: 640 bits
1632 13:38:26.131461 # # SVE-VL-80-0: PID: 920
1633 13:38:26.131541 # # SVE-VL-176-0: Vector length: 1408 bits
1634 13:38:26.131607 # # SVE-VL-176-0: PID: 914
1635 13:38:26.131670 # # SVE-VL-64-0: Vector length: 512 bits
1636 13:38:26.131745 # # SVE-VL-64-0: PID: 921
1637 13:38:26.131810 # # SVE-VL-112-0: Vector length: 896 bits
1638 13:38:26.131872 # # SVE-VL-112-0: PID: 918
1639 13:38:26.131945 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1640 13:38:26.132009 # # SSVE-VL-128-0: PID: 927
1641 13:38:26.132082 # # SVE-VL-32-0: Vector length: 256 bits
1642 13:38:26.132146 # # SVE-VL-32-0: PID: 923
1643 13:38:26.132224 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1644 13:38:26.132287 # # ZA-VL-128-0: PID: 928
1645 13:38:26.132358 # # SVE-VL-96-0: Vector length: 768 bits
1646 13:38:26.148828 # # SVE-VL-96-0: PID: 919
1647 13:38:26.149208 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1648 13:38:26.149299 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1649 13:38:26.149379 # # SSVE-VL-16-0: PID: 933
1650 13:38:26.149446 # # SVE-VL-128-0: Vector length: 1024 bits
1651 13:38:26.149521 # # SVE-VL-128-0: PID: 917
1652 13:38:26.149598 # # SSVE-VL-32-0: PID: 931
1653 13:38:26.149853 # # SVE-VL-16-0: Vector length: 128 bits
1654 13:38:26.149924 # # SVE-VL-16-0: PID: 924
1655 13:38:26.149989 # # SVE-VL-144-0: Vector length: 1152 bits
1656 13:38:26.150064 # # SVE-VL-144-0: PID: 916
1657 13:38:26.150131 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1658 13:38:26.150209 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1659 13:38:26.150275 # # ZA-VL-64-0: PID: 930
1660 13:38:26.150351 # # ZA-VL-32-0: PID: 932
1661 13:38:26.150429 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1662 13:38:26.150496 # # ZA-VL-256-0: PID: 926
1663 13:38:26.150749 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1664 13:38:26.150819 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1665 13:38:26.150895 # # ZA-VL-16-0: PID: 934
1666 13:38:26.150960 # # SSVE-VL-64-0: PID: 929
1667 13:38:26.151030 # # Finishing up...
1668 13:38:26.151094 # ok 1 FPSIMD-0-0
1669 13:38:26.151171 # ok 2 SVE-VL-256-0
1670 13:38:26.151237 # ok 3 SVE-VL-240-0
1671 13:38:26.151300 # ok 4 SVE-VL-224-0
1672 13:38:26.151362 # ok 5 SVE-VL-208-0
1673 13:38:26.151428 # ok 6 SVE-VL-192-0
1674 13:38:26.151505 # ok 7 SVE-VL-176-0
1675 13:38:26.151573 # ok 8 SVE-VL-160-0
1676 13:38:26.151636 # ok 9 SVE-VL-144-0
1677 13:38:26.151697 # ok 10 SVE-VL-128-0
1678 13:38:26.151760 # ok 11 SVE-VL-112-0
1679 13:38:26.151824 # ok 12 SVE-VL-96-0
1680 13:38:26.151887 # ok 13 SVE-VL-80-0
1681 13:38:26.151949 # ok 14 SVE-VL-64-0
1682 13:38:26.152025 # ok 15 SVE-VL-48-0
1683 13:38:26.152090 # ok 16 SVE-VL-32-0
1684 13:38:26.152153 # ok 17 SVE-VL-16-0
1685 13:38:26.152219 # ok 18 SSVE-VL-256-0
1686 13:38:26.152282 # ok 19 ZA-VL-256-0
1687 13:38:26.152345 # ok 20 SSVE-VL-128-0
1688 13:38:26.152408 # ok 21 ZA-VL-128-0
1689 13:38:26.152472 # ok 22 SSVE-VL-64-0
1690 13:38:26.152535 # ok 23 ZA-VL-64-0
1691 13:38:26.152595 # ok 24 SSVE-VL-32-0
1692 13:38:26.152669 # ok 25 ZA-VL-32-0
1693 13:38:26.152731 # ok 26 SSVE-VL-16-0
1694 13:38:26.152792 # ok 27 ZA-VL-16-0
1695 13:38:26.152852 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=4354, signals=9
1696 13:38:26.161498 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=3469, signals=9
1697 13:38:26.161808 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=6429, signals=9
1698 13:38:26.161895 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=2651, signals=9
1699 13:38:26.161986 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=3687, signals=9
1700 13:38:26.162082 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=3062, signals=9
1701 13:38:26.162352 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=170, signals=9
1702 13:38:26.162429 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=3183, signals=9
1703 13:38:26.162504 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=730, signals=9
1704 13:38:26.220609 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=2932, signals=9
1705 13:38:26.237512 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=5627, signals=9
1706 13:38:26.237960 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=11838, signals=9
1707 13:38:26.238063 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=4167, signals=9
1708 13:38:26.238137 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=2652, signals=9
1709 13:38:26.238241 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=9611, signals=9
1710 13:38:26.238351 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=12077, signals=9
1711 13:38:26.238458 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=1798, signals=9
1712 13:38:26.238775 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=1308, signals=9
1713 13:38:26.238905 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=7730, signals=9
1714 13:38:26.239003 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=5412, signals=9
1715 13:38:26.239133 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=5024, signals=9
1716 13:38:26.239454 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=9280, signals=9
1717 13:38:26.239588 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=3283, signals=9
1718 13:38:26.239702 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=2614, signals=9
1719 13:38:26.239812 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=1826, signals=9
1720 13:38:26.240142 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=2581, signals=9
1721 13:38:26.240266 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=3594, signals=9
1722 13:38:26.240362 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1723 13:38:26.245117 ok 29 selftests: arm64: fp-stress
1724 13:38:26.349483 # selftests: arm64: sve-ptrace
1725 13:38:26.460637 # TAP version 13
1726 13:38:26.460986 # 1..4104
1727 13:38:26.461375 # # Parent is 951, child is 952
1728 13:38:26.461474 # ok 1 SVE FPSIMD set via SVE: 0
1729 13:38:26.461557 # ok 2 SVE get_fpsimd() gave same state
1730 13:38:26.461632 # ok 3 SVE SVE_PT_VL_INHERIT set
1731 13:38:26.461717 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1732 13:38:26.461815 # ok 5 Set SVE VL 16
1733 13:38:26.461896 # ok 6 Set and get SVE data for VL 16
1734 13:38:26.461969 # ok 7 Set and get FPSIMD data for SVE VL 16
1735 13:38:26.462042 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1736 13:38:26.462133 # ok 9 Set SVE VL 32
1737 13:38:26.462213 # ok 10 Set and get SVE data for VL 32
1738 13:38:26.462287 # ok 11 Set and get FPSIMD data for SVE VL 32
1739 13:38:26.462360 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1740 13:38:26.462433 # ok 13 Set SVE VL 48
1741 13:38:26.462504 # ok 14 Set and get SVE data for VL 48
1742 13:38:26.462576 # ok 15 Set and get FPSIMD data for SVE VL 48
1743 13:38:26.462649 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1744 13:38:26.462720 # ok 17 Set SVE VL 64
1745 13:38:26.462808 # ok 18 Set and get SVE data for VL 64
1746 13:38:26.462882 # ok 19 Set and get FPSIMD data for SVE VL 64
1747 13:38:26.462955 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1748 13:38:26.463027 # ok 21 Set SVE VL 80
1749 13:38:26.463099 # ok 22 Set and get SVE data for VL 80
1750 13:38:26.463171 # ok 23 Set and get FPSIMD data for SVE VL 80
1751 13:38:26.463243 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1752 13:38:26.463886 # ok 25 Set SVE VL 96
1753 13:38:26.464108 # ok 26 Set and get SVE data for VL 96
1754 13:38:26.464285 # ok 27 Set and get FPSIMD data for SVE VL 96
1755 13:38:26.464458 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1756 13:38:26.464693 # ok 29 Set SVE VL 112
1757 13:38:26.464930 # ok 30 Set and get SVE data for VL 112
1758 13:38:26.465102 # ok 31 Set and get FPSIMD data for SVE VL 112
1759 13:38:26.465251 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1760 13:38:26.465395 # ok 33 Set SVE VL 128
1761 13:38:26.465537 # ok 34 Set and get SVE data for VL 128
1762 13:38:26.465694 # ok 35 Set and get FPSIMD data for SVE VL 128
1763 13:38:26.465840 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1764 13:38:26.465982 # ok 37 Set SVE VL 144
1765 13:38:26.466126 # ok 38 Set and get SVE data for VL 144
1766 13:38:26.466269 # ok 39 Set and get FPSIMD data for SVE VL 144
1767 13:38:26.466412 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1768 13:38:26.466555 # ok 41 Set SVE VL 160
1769 13:38:26.466697 # ok 42 Set and get SVE data for VL 160
1770 13:38:26.467063 # ok 43 Set and get FPSIMD data for SVE VL 160
1771 13:38:26.467207 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1772 13:38:26.467354 # ok 45 Set SVE VL 176
1773 13:38:26.467499 # ok 46 Set and get SVE data for VL 176
1774 13:38:26.467643 # ok 47 Set and get FPSIMD data for SVE VL 176
1775 13:38:26.467786 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1776 13:38:26.467932 # ok 49 Set SVE VL 192
1777 13:38:26.468075 # ok 50 Set and get SVE data for VL 192
1778 13:38:26.468218 # ok 51 Set and get FPSIMD data for SVE VL 192
1779 13:38:26.468361 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1780 13:38:26.468550 # ok 53 Set SVE VL 208
1781 13:38:26.468742 # ok 54 Set and get SVE data for VL 208
1782 13:38:26.468965 # ok 55 Set and get FPSIMD data for SVE VL 208
1783 13:38:26.469159 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1784 13:38:26.469360 # ok 57 Set SVE VL 224
1785 13:38:26.469625 # ok 58 Set and get SVE data for VL 224
1786 13:38:26.469831 # ok 59 Set and get FPSIMD data for SVE VL 224
1787 13:38:26.470061 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1788 13:38:26.470276 # ok 61 Set SVE VL 240
1789 13:38:26.470479 # ok 62 Set and get SVE data for VL 240
1790 13:38:26.470703 # ok 63 Set and get FPSIMD data for SVE VL 240
1791 13:38:26.470888 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1792 13:38:26.471071 # ok 65 Set SVE VL 256
1793 13:38:26.471245 # ok 66 Set and get SVE data for VL 256
1794 13:38:26.471444 # ok 67 Set and get FPSIMD data for SVE VL 256
1795 13:38:26.471595 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1796 13:38:26.471762 # ok 69 Set SVE VL 272
1797 13:38:26.471930 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1798 13:38:26.472061 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1799 13:38:26.472177 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1800 13:38:26.472345 # ok 73 Set SVE VL 288
1801 13:38:26.472529 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1802 13:38:26.472715 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1803 13:38:26.472897 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1804 13:38:26.473097 # ok 77 Set SVE VL 304
1805 13:38:26.473245 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1806 13:38:26.473364 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1807 13:38:26.473481 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1808 13:38:26.473596 # ok 81 Set SVE VL 320
1809 13:38:26.473802 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1810 13:38:26.474001 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1811 13:38:26.474186 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1812 13:38:26.474370 # ok 85 Set SVE VL 336
1813 13:38:26.474554 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1814 13:38:26.474738 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1815 13:38:26.474911 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1816 13:38:26.475055 # ok 89 Set SVE VL 352
1817 13:38:26.475422 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1818 13:38:26.475562 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1819 13:38:26.475708 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1820 13:38:26.475852 # ok 93 Set SVE VL 368
1821 13:38:26.475994 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1822 13:38:26.476137 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1823 13:38:26.476280 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1824 13:38:26.476422 # ok 97 Set SVE VL 384
1825 13:38:26.476564 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1826 13:38:26.476706 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1827 13:38:26.476849 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1828 13:38:26.476992 # ok 101 Set SVE VL 400
1829 13:38:26.477133 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1830 13:38:26.477274 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1831 13:38:26.477417 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1832 13:38:26.477559 # ok 105 Set SVE VL 416
1833 13:38:26.477715 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1834 13:38:26.477861 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1835 13:38:26.478004 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1836 13:38:26.478145 # ok 109 Set SVE VL 432
1837 13:38:26.478322 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1838 13:38:26.478757 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1839 13:38:26.478982 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1840 13:38:26.479161 # ok 113 Set SVE VL 448
1841 13:38:26.479326 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1842 13:38:26.479487 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1843 13:38:26.479695 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1844 13:38:26.479847 # ok 117 Set SVE VL 464
1845 13:38:26.480066 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1846 13:38:26.480301 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1847 13:38:26.480533 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1848 13:38:26.480754 # ok 121 Set SVE VL 480
1849 13:38:26.481352 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1850 13:38:26.481544 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1851 13:38:26.481771 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1852 13:38:26.481996 # ok 125 Set SVE VL 496
1853 13:38:26.482211 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1854 13:38:26.482433 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1855 13:38:26.482646 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1856 13:38:26.482842 # ok 129 Set SVE VL 512
1857 13:38:26.483088 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1858 13:38:26.483284 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1859 13:38:26.483486 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1860 13:38:26.483687 # ok 133 Set SVE VL 528
1861 13:38:26.483887 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1862 13:38:26.484076 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1863 13:38:26.484241 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1864 13:38:26.484400 # ok 137 Set SVE VL 544
1865 13:38:26.484568 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1866 13:38:26.484737 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1867 13:38:26.484937 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1868 13:38:26.485084 # ok 141 Set SVE VL 560
1869 13:38:26.485201 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1870 13:38:26.485316 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1871 13:38:26.485431 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1872 13:38:26.485546 # ok 145 Set SVE VL 576
1873 13:38:26.485674 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1874 13:38:26.485793 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1875 13:38:26.485915 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1876 13:38:26.486032 # ok 149 Set SVE VL 592
1877 13:38:26.486148 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1878 13:38:26.486264 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1879 13:38:26.486381 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1880 13:38:26.486497 # ok 153 Set SVE VL 608
1881 13:38:26.486614 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1882 13:38:26.486731 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1883 13:38:26.487081 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1884 13:38:26.487213 # ok 157 Set SVE VL 624
1885 13:38:26.487331 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1886 13:38:26.487464 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1887 13:38:26.487612 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1888 13:38:26.487733 # ok 161 Set SVE VL 640
1889 13:38:26.487848 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1890 13:38:26.487966 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1891 13:38:26.488082 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1892 13:38:26.488198 # ok 165 Set SVE VL 656
1893 13:38:26.488315 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1894 13:38:26.488431 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1895 13:38:26.488547 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1896 13:38:26.488664 # ok 169 Set SVE VL 672
1897 13:38:26.488782 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1898 13:38:26.488950 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1899 13:38:26.489087 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1900 13:38:26.489205 # ok 173 Set SVE VL 688
1901 13:38:26.489321 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1902 13:38:26.489438 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1903 13:38:26.489556 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1904 13:38:26.489683 # ok 177 Set SVE VL 704
1905 13:38:26.489801 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1906 13:38:26.489918 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1907 13:38:26.490034 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1908 13:38:26.490150 # ok 181 Set SVE VL 720
1909 13:38:26.490266 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1910 13:38:26.490382 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1911 13:38:26.490499 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1912 13:38:26.490615 # ok 185 Set SVE VL 736
1913 13:38:26.490728 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1914 13:38:26.490843 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1915 13:38:26.490961 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1916 13:38:26.491077 # ok 189 Set SVE VL 752
1917 13:38:26.491192 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1918 13:38:26.491309 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1919 13:38:26.491424 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1920 13:38:26.491539 # ok 193 Set SVE VL 768
1921 13:38:26.491654 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1922 13:38:26.491768 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1923 13:38:26.493966 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1924 13:38:26.494165 # ok 197 Set SVE VL 784
1925 13:38:26.494324 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1926 13:38:26.494734 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1927 13:38:26.494939 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1928 13:38:26.495175 # ok 201 Set SVE VL 800
1929 13:38:26.495395 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1930 13:38:26.495603 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1931 13:38:26.495821 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1932 13:38:26.496034 # ok 205 Set SVE VL 816
1933 13:38:26.496254 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1934 13:38:26.496515 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1935 13:38:26.496744 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1936 13:38:26.496998 # ok 209 Set SVE VL 832
1937 13:38:26.497204 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1938 13:38:26.497343 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1939 13:38:26.497461 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1940 13:38:26.497615 # ok 213 Set SVE VL 848
1941 13:38:26.497829 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1942 13:38:26.498027 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1943 13:38:26.498215 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1944 13:38:26.498366 # ok 217 Set SVE VL 864
1945 13:38:26.498509 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1946 13:38:26.498650 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1947 13:38:26.498792 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1948 13:38:26.498978 # ok 221 Set SVE VL 880
1949 13:38:26.499118 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1950 13:38:26.499260 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1951 13:38:26.499401 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1952 13:38:26.499542 # ok 225 Set SVE VL 896
1953 13:38:26.499683 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1954 13:38:26.499824 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1955 13:38:26.499965 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1956 13:38:26.500106 # ok 229 Set SVE VL 912
1957 13:38:26.500245 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1958 13:38:26.500386 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1959 13:38:26.500527 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1960 13:38:26.500669 # ok 233 Set SVE VL 928
1961 13:38:26.500810 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1962 13:38:26.500955 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1963 13:38:26.501097 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1964 13:38:26.501238 # ok 237 Set SVE VL 944
1965 13:38:26.502294 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1966 13:38:26.502494 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1967 13:38:26.502867 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1968 13:38:26.502968 # ok 241 Set SVE VL 960
1969 13:38:26.503045 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1970 13:38:26.503121 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1971 13:38:26.503198 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1972 13:38:26.503272 # ok 245 Set SVE VL 976
1973 13:38:26.503345 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1974 13:38:26.503433 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1975 13:38:26.503508 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1976 13:38:26.503582 # ok 249 Set SVE VL 992
1977 13:38:26.503654 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1978 13:38:26.503727 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1979 13:38:26.503814 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1980 13:38:26.503889 # ok 253 Set SVE VL 1008
1981 13:38:26.503962 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1982 13:38:26.504035 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1983 13:38:26.504122 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1984 13:38:26.504197 # ok 257 Set SVE VL 1024
1985 13:38:26.504269 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1986 13:38:26.504342 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1987 13:38:26.504416 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1988 13:38:26.504502 # ok 261 Set SVE VL 1040
1989 13:38:26.504578 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1990 13:38:26.504651 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1991 13:38:26.504738 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1992 13:38:26.504813 # ok 265 Set SVE VL 1056
1993 13:38:26.504886 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1994 13:38:26.504964 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1995 13:38:26.505036 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
1996 13:38:26.505109 # ok 269 Set SVE VL 1072
1997 13:38:26.505194 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
1998 13:38:26.505272 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
1999 13:38:26.505356 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2000 13:38:26.505431 # ok 273 Set SVE VL 1088
2001 13:38:26.505504 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2002 13:38:26.505587 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2003 13:38:26.505682 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2004 13:38:26.505758 # ok 277 Set SVE VL 1104
2005 13:38:26.505832 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2006 13:38:26.505905 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2007 13:38:26.505990 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2008 13:38:26.506069 # ok 281 Set SVE VL 1120
2009 13:38:26.506142 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2010 13:38:26.506228 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2011 13:38:26.506857 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2012 13:38:26.506955 # ok 285 Set SVE VL 1136
2013 13:38:26.507032 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2014 13:38:26.507107 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2015 13:38:26.507181 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2016 13:38:26.507255 # ok 289 Set SVE VL 1152
2017 13:38:26.507328 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2018 13:38:26.507403 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2019 13:38:26.507492 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2020 13:38:26.507581 # ok 293 Set SVE VL 1168
2021 13:38:26.507668 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2022 13:38:26.507754 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2023 13:38:26.508045 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2024 13:38:26.508142 # ok 297 Set SVE VL 1184
2025 13:38:26.508419 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2026 13:38:26.508516 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2027 13:38:26.508594 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2028 13:38:26.508668 # ok 301 Set SVE VL 1200
2029 13:38:26.508741 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2030 13:38:26.508828 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2031 13:38:26.508904 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2032 13:38:26.508978 # ok 305 Set SVE VL 1216
2033 13:38:26.509064 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2034 13:38:26.509140 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2035 13:38:26.509213 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2036 13:38:26.509286 # ok 309 Set SVE VL 1232
2037 13:38:26.517635 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2038 13:38:26.518144 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2039 13:38:26.518341 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2040 13:38:26.518507 # ok 313 Set SVE VL 1248
2041 13:38:26.518673 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2042 13:38:26.518837 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2043 13:38:26.519040 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2044 13:38:26.519191 # ok 317 Set SVE VL 1264
2045 13:38:26.519321 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2046 13:38:26.519460 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2047 13:38:26.519628 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2048 13:38:26.519774 # ok 321 Set SVE VL 1280
2049 13:38:26.519923 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2050 13:38:26.520081 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2051 13:38:26.520207 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2052 13:38:26.520363 # ok 325 Set SVE VL 1296
2053 13:38:26.520564 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2054 13:38:26.520729 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2055 13:38:26.520900 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2056 13:38:26.521050 # ok 329 Set SVE VL 1312
2057 13:38:26.521167 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2058 13:38:26.521283 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2059 13:38:26.521398 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2060 13:38:26.521512 # ok 333 Set SVE VL 1328
2061 13:38:26.521628 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2062 13:38:26.521881 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2063 13:38:26.522080 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2064 13:38:26.522267 # ok 337 Set SVE VL 1344
2065 13:38:26.522450 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2066 13:38:26.522594 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2067 13:38:26.522775 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2068 13:38:26.522913 # ok 341 Set SVE VL 1360
2069 13:38:26.523059 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2070 13:38:26.523203 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2071 13:38:26.523345 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2072 13:38:26.529218 # ok 345 Set SVE VL 1376
2073 13:38:26.529738 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2074 13:38:26.529913 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2075 13:38:26.530080 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2076 13:38:26.530256 # ok 349 Set SVE VL 1392
2077 13:38:26.530405 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2078 13:38:26.530591 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2079 13:38:26.530751 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2080 13:38:26.530938 # ok 353 Set SVE VL 1408
2081 13:38:26.531112 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2082 13:38:26.531259 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2083 13:38:26.531405 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2084 13:38:26.531549 # ok 357 Set SVE VL 1424
2085 13:38:26.531691 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2086 13:38:26.531834 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2087 13:38:26.531980 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2088 13:38:26.532124 # ok 361 Set SVE VL 1440
2089 13:38:26.532309 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2090 13:38:26.532446 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2091 13:38:26.532592 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2092 13:38:26.532736 # ok 365 Set SVE VL 1456
2093 13:38:26.532880 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2094 13:38:26.533025 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2095 13:38:26.533171 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2096 13:38:26.533315 # ok 369 Set SVE VL 1472
2097 13:38:26.533457 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2098 13:38:26.533600 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2099 13:38:26.533760 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2100 13:38:26.533906 # ok 373 Set SVE VL 1488
2101 13:38:26.534093 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2102 13:38:26.534230 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2103 13:38:26.534374 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2104 13:38:26.534517 # ok 377 Set SVE VL 1504
2105 13:38:26.534660 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2106 13:38:26.534803 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2107 13:38:26.534947 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2108 13:38:26.535092 # ok 381 Set SVE VL 1520
2109 13:38:26.535235 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2110 13:38:26.535377 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2111 13:38:26.535520 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2112 13:38:26.535663 # ok 385 Set SVE VL 1536
2113 13:38:26.535805 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2114 13:38:26.535946 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2115 13:38:26.536089 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2116 13:38:26.536843 # ok 389 Set SVE VL 1552
2117 13:38:26.537044 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2118 13:38:26.537207 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2119 13:38:26.537356 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2120 13:38:26.537535 # ok 393 Set SVE VL 1568
2121 13:38:26.537685 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2122 13:38:26.537855 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2123 13:38:26.538049 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2124 13:38:26.538212 # ok 397 Set SVE VL 1584
2125 13:38:26.538475 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2126 13:38:26.538656 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2127 13:38:26.538799 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2128 13:38:26.539006 # ok 401 Set SVE VL 1600
2129 13:38:26.539182 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2130 13:38:26.539329 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2131 13:38:26.539478 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2132 13:38:26.539622 # ok 405 Set SVE VL 1616
2133 13:38:26.539765 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2134 13:38:26.539952 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2135 13:38:26.540120 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2136 13:38:26.540316 # ok 409 Set SVE VL 1632
2137 13:38:26.540510 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2138 13:38:26.540710 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2139 13:38:26.540893 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2140 13:38:26.541042 # ok 413 Set SVE VL 1648
2141 13:38:26.541188 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2142 13:38:26.541332 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2143 13:38:26.541477 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2144 13:38:26.541620 # ok 417 Set SVE VL 1664
2145 13:38:26.541774 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2146 13:38:26.541917 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2147 13:38:26.542063 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2148 13:38:26.542206 # ok 421 Set SVE VL 1680
2149 13:38:26.542347 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2150 13:38:26.542530 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2151 13:38:26.542667 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2152 13:38:26.542812 # ok 425 Set SVE VL 1696
2153 13:38:26.542955 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2154 13:38:26.543100 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2155 13:38:26.543242 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2156 13:38:26.543385 # ok 429 Set SVE VL 1712
2157 13:38:26.543527 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2158 13:38:26.543670 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2159 13:38:26.543813 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2160 13:38:26.544168 # ok 433 Set SVE VL 1728
2161 13:38:26.545213 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2162 13:38:26.545525 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2163 13:38:26.545626 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2164 13:38:26.545722 # ok 437 Set SVE VL 1744
2165 13:38:26.545829 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2166 13:38:26.545920 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2167 13:38:26.546023 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2168 13:38:26.546114 # ok 441 Set SVE VL 1760
2169 13:38:26.546202 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2170 13:38:26.546307 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2171 13:38:26.546398 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2172 13:38:26.546502 # ok 445 Set SVE VL 1776
2173 13:38:26.546593 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2174 13:38:26.546695 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2175 13:38:26.546804 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2176 13:38:26.546908 # ok 449 Set SVE VL 1792
2177 13:38:26.547012 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2178 13:38:26.547118 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2179 13:38:26.547412 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2180 13:38:26.547504 # ok 453 Set SVE VL 1808
2181 13:38:26.547591 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2182 13:38:26.547692 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2183 13:38:26.547796 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2184 13:38:26.547899 # ok 457 Set SVE VL 1824
2185 13:38:26.548000 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2186 13:38:26.548102 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2187 13:38:26.548392 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2188 13:38:26.548486 # ok 461 Set SVE VL 1840
2189 13:38:26.548587 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2190 13:38:26.548689 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2191 13:38:26.548777 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2192 13:38:26.548877 # ok 465 Set SVE VL 1856
2193 13:38:26.548977 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2194 13:38:26.553292 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2195 13:38:26.553639 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2196 13:38:26.553860 # ok 469 Set SVE VL 1872
2197 13:38:26.554043 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2198 13:38:26.554212 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2199 13:38:26.554388 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2200 13:38:26.554518 # ok 473 Set SVE VL 1888
2201 13:38:26.554638 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2202 13:38:26.554757 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2203 13:38:26.554875 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2204 13:38:26.554993 # ok 477 Set SVE VL 1904
2205 13:38:26.555112 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2206 13:38:26.555232 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2207 13:38:26.555825 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2208 13:38:26.555994 # ok 481 Set SVE VL 1920
2209 13:38:26.556154 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2210 13:38:26.556347 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2211 13:38:26.556511 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2212 13:38:26.556656 # ok 485 Set SVE VL 1936
2213 13:38:26.556795 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2214 13:38:26.556998 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2215 13:38:26.557183 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2216 13:38:26.557396 # ok 489 Set SVE VL 1952
2217 13:38:26.557574 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2218 13:38:26.557753 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2219 13:38:26.557919 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2220 13:38:26.558074 # ok 493 Set SVE VL 1968
2221 13:38:26.558230 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2222 13:38:26.558385 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2223 13:38:26.558529 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2224 13:38:26.558676 # ok 497 Set SVE VL 1984
2225 13:38:26.558796 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2226 13:38:26.558939 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2227 13:38:26.559155 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2228 13:38:26.559341 # ok 501 Set SVE VL 2000
2229 13:38:26.559505 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2230 13:38:26.559671 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2231 13:38:26.559826 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2232 13:38:26.559984 # ok 505 Set SVE VL 2016
2233 13:38:26.560143 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2234 13:38:26.560300 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2235 13:38:26.560436 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2236 13:38:26.560569 # ok 509 Set SVE VL 2032
2237 13:38:26.560717 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2238 13:38:26.560870 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2239 13:38:26.561023 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2240 13:38:26.561150 # ok 513 Set SVE VL 2048
2241 13:38:26.561266 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2242 13:38:26.561383 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2243 13:38:26.561497 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2244 13:38:26.561613 # ok 517 Set SVE VL 2064
2245 13:38:26.561837 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2246 13:38:26.562032 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2247 13:38:26.562205 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2248 13:38:26.562349 # ok 521 Set SVE VL 2080
2249 13:38:26.562489 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2250 13:38:26.562617 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2251 13:38:26.562931 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2252 13:38:26.563036 # ok 525 Set SVE VL 2096
2253 13:38:26.563147 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2254 13:38:26.563255 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2255 13:38:26.563363 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2256 13:38:26.563471 # ok 529 Set SVE VL 2112
2257 13:38:26.563579 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2258 13:38:26.563687 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2259 13:38:26.563795 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2260 13:38:26.563903 # ok 533 Set SVE VL 2128
2261 13:38:26.564010 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2262 13:38:26.564118 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2263 13:38:26.564225 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2264 13:38:26.564332 # ok 537 Set SVE VL 2144
2265 13:38:26.564439 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2266 13:38:26.569163 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2267 13:38:26.569525 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2268 13:38:26.569726 # ok 541 Set SVE VL 2160
2269 13:38:26.569933 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2270 13:38:26.570098 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2271 13:38:26.570292 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2272 13:38:26.570461 # ok 545 Set SVE VL 2176
2273 13:38:26.570619 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2274 13:38:26.570807 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2275 13:38:26.570964 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2276 13:38:26.571105 # ok 549 Set SVE VL 2192
2277 13:38:26.571267 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2278 13:38:26.571491 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2279 13:38:26.571702 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2280 13:38:26.571907 # ok 553 Set SVE VL 2208
2281 13:38:26.572095 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2282 13:38:26.572257 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2283 13:38:26.572386 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2284 13:38:26.572531 # ok 557 Set SVE VL 2224
2285 13:38:26.572715 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2286 13:38:26.572879 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2287 13:38:26.573037 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2288 13:38:26.573165 # ok 561 Set SVE VL 2240
2289 13:38:26.573281 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2290 13:38:26.573430 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2291 13:38:26.573554 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2292 13:38:26.573689 # ok 565 Set SVE VL 2256
2293 13:38:26.573808 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2294 13:38:26.573924 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2295 13:38:26.574044 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2296 13:38:26.574148 # ok 569 Set SVE VL 2272
2297 13:38:26.574238 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2298 13:38:26.574327 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2299 13:38:26.574416 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2300 13:38:26.574505 # ok 573 Set SVE VL 2288
2301 13:38:26.574593 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2302 13:38:26.574682 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2303 13:38:26.574772 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2304 13:38:26.574862 # ok 577 Set SVE VL 2304
2305 13:38:26.574950 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2306 13:38:26.577292 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2307 13:38:26.577701 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2308 13:38:26.577862 # ok 581 Set SVE VL 2320
2309 13:38:26.578047 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2310 13:38:26.578281 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2311 13:38:26.578449 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2312 13:38:26.578627 # ok 585 Set SVE VL 2336
2313 13:38:26.578783 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2314 13:38:26.578952 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2315 13:38:26.579182 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2316 13:38:26.579307 # ok 589 Set SVE VL 2352
2317 13:38:26.579449 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2318 13:38:26.579569 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2319 13:38:26.579699 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2320 13:38:26.579834 # ok 593 Set SVE VL 2368
2321 13:38:26.579952 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2322 13:38:26.580084 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2323 13:38:26.580221 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2324 13:38:26.580384 # ok 597 Set SVE VL 2384
2325 13:38:26.580552 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2326 13:38:26.580678 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2327 13:38:26.580789 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2328 13:38:26.580928 # ok 601 Set SVE VL 2400
2329 13:38:26.581041 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2330 13:38:26.581133 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2331 13:38:26.581224 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2332 13:38:26.581310 # ok 605 Set SVE VL 2416
2333 13:38:26.581394 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2334 13:38:26.581478 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2335 13:38:26.581585 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2336 13:38:26.581739 # ok 609 Set SVE VL 2432
2337 13:38:26.581894 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2338 13:38:26.582034 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2339 13:38:26.582154 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2340 13:38:26.582259 # ok 613 Set SVE VL 2448
2341 13:38:26.582353 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2342 13:38:26.585312 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2343 13:38:26.585632 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2344 13:38:26.585746 # ok 617 Set SVE VL 2464
2345 13:38:26.585835 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2346 13:38:26.585936 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2347 13:38:26.586022 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2348 13:38:26.586104 # ok 621 Set SVE VL 2480
2349 13:38:26.586202 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2350 13:38:26.586304 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2351 13:38:26.586413 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2352 13:38:26.586514 # ok 625 Set SVE VL 2496
2353 13:38:26.586615 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2354 13:38:26.586943 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2355 13:38:26.587047 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2356 13:38:26.587150 # ok 629 Set SVE VL 2512
2357 13:38:26.587250 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2358 13:38:26.587550 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2359 13:38:26.587656 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2360 13:38:26.587743 # ok 633 Set SVE VL 2528
2361 13:38:26.587845 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2362 13:38:26.587947 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2363 13:38:26.588050 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2364 13:38:26.588339 # ok 637 Set SVE VL 2544
2365 13:38:26.588441 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2366 13:38:26.588545 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2367 13:38:26.588634 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2368 13:38:26.588735 # ok 641 Set SVE VL 2560
2369 13:38:26.588836 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2370 13:38:26.588936 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2371 13:38:26.589033 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2372 13:38:26.592714 # ok 645 Set SVE VL 2576
2373 13:38:26.593052 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2374 13:38:26.593233 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2375 13:38:26.593403 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2376 13:38:26.593622 # ok 649 Set SVE VL 2592
2377 13:38:26.593827 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2378 13:38:26.593999 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2379 13:38:26.594131 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2380 13:38:26.594300 # ok 653 Set SVE VL 2608
2381 13:38:26.594435 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2382 13:38:26.594554 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2383 13:38:26.594692 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2384 13:38:26.594819 # ok 657 Set SVE VL 2624
2385 13:38:26.594924 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2386 13:38:26.595077 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2387 13:38:26.595207 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2388 13:38:26.595337 # ok 661 Set SVE VL 2640
2389 13:38:26.595460 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2390 13:38:26.595559 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2391 13:38:26.595669 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2392 13:38:26.595761 # ok 665 Set SVE VL 2656
2393 13:38:26.595849 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2394 13:38:26.600748 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2395 13:38:26.601075 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2396 13:38:26.601170 # ok 669 Set SVE VL 2672
2397 13:38:26.601236 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2398 13:38:26.601313 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2399 13:38:26.601399 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2400 13:38:26.601522 # ok 673 Set SVE VL 2688
2401 13:38:26.601627 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2402 13:38:26.601761 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2403 13:38:26.601846 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2404 13:38:26.601966 # ok 677 Set SVE VL 2704
2405 13:38:26.602083 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2406 13:38:26.602175 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2407 13:38:26.602273 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2408 13:38:26.602366 # ok 681 Set SVE VL 2720
2409 13:38:26.602456 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2410 13:38:26.602554 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2411 13:38:26.602648 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2412 13:38:26.602746 # ok 685 Set SVE VL 2736
2413 13:38:26.602841 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2414 13:38:26.602931 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2415 13:38:26.603220 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2416 13:38:26.603321 # ok 689 Set SVE VL 2752
2417 13:38:26.603419 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2418 13:38:26.603528 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2419 13:38:26.603600 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2420 13:38:26.603675 # ok 693 Set SVE VL 2768
2421 13:38:26.603764 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2422 13:38:26.603836 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2423 13:38:26.603926 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2424 13:38:26.604012 # ok 697 Set SVE VL 2784
2425 13:38:26.604097 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2426 13:38:26.604189 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2427 13:38:26.604274 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2428 13:38:26.604350 # ok 701 Set SVE VL 2800
2429 13:38:26.604462 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2430 13:38:26.604561 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2431 13:38:26.604665 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2432 13:38:26.604748 # ok 705 Set SVE VL 2816
2433 13:38:26.604869 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2434 13:38:26.604973 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2435 13:38:26.605094 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2436 13:38:26.605197 # ok 709 Set SVE VL 2832
2437 13:38:26.605306 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2438 13:38:26.605422 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2439 13:38:26.605539 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2440 13:38:26.605640 # ok 713 Set SVE VL 2848
2441 13:38:26.605750 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2442 13:38:26.605857 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2443 13:38:26.605961 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2444 13:38:26.606069 # ok 717 Set SVE VL 2864
2445 13:38:26.606184 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2446 13:38:26.606274 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2447 13:38:26.606561 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2448 13:38:26.606669 # ok 721 Set SVE VL 2880
2449 13:38:26.606774 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2450 13:38:26.606863 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2451 13:38:26.606965 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2452 13:38:26.607053 # ok 725 Set SVE VL 2896
2453 13:38:26.607156 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2454 13:38:26.607254 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2455 13:38:26.607355 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2456 13:38:26.607454 # ok 729 Set SVE VL 2912
2457 13:38:26.607800 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2458 13:38:26.608002 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2459 13:38:26.608229 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2460 13:38:26.608400 # ok 733 Set SVE VL 2928
2461 13:38:26.608556 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2462 13:38:26.608745 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2463 13:38:26.608907 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2464 13:38:26.609056 # ok 737 Set SVE VL 2944
2465 13:38:26.609176 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2466 13:38:26.609302 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2467 13:38:26.609473 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2468 13:38:26.609602 # ok 741 Set SVE VL 2960
2469 13:38:26.609735 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2470 13:38:26.609871 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2471 13:38:26.609985 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2472 13:38:26.610109 # ok 745 Set SVE VL 2976
2473 13:38:26.610260 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2474 13:38:26.610339 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2475 13:38:26.610432 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2476 13:38:26.610521 # ok 749 Set SVE VL 2992
2477 13:38:26.610611 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2478 13:38:26.610679 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2479 13:38:26.610755 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2480 13:38:26.610852 # ok 753 Set SVE VL 3008
2481 13:38:26.610933 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2482 13:38:26.611010 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2483 13:38:26.611081 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2484 13:38:26.611148 # ok 757 Set SVE VL 3024
2485 13:38:26.611210 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2486 13:38:26.611299 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2487 13:38:26.611379 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2488 13:38:26.611456 # ok 761 Set SVE VL 3040
2489 13:38:26.611532 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2490 13:38:26.611635 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2491 13:38:26.611731 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2492 13:38:26.611815 # ok 765 Set SVE VL 3056
2493 13:38:26.611892 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2494 13:38:26.611982 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2495 13:38:26.612072 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2496 13:38:26.612154 # ok 769 Set SVE VL 3072
2497 13:38:26.612257 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2498 13:38:26.612336 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2499 13:38:26.612431 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2500 13:38:26.612539 # ok 773 Set SVE VL 3088
2501 13:38:26.613301 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2502 13:38:26.613396 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2503 13:38:26.613476 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2504 13:38:26.613555 # ok 777 Set SVE VL 3104
2505 13:38:26.613657 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2506 13:38:26.613726 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2507 13:38:26.613805 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2508 13:38:26.613891 # ok 781 Set SVE VL 3120
2509 13:38:26.613969 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2510 13:38:26.614051 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2511 13:38:26.614146 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2512 13:38:26.614232 # ok 785 Set SVE VL 3136
2513 13:38:26.614317 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2514 13:38:26.614410 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2515 13:38:26.614505 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2516 13:38:26.614596 # ok 789 Set SVE VL 3152
2517 13:38:26.614682 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2518 13:38:26.614759 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2519 13:38:26.614835 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2520 13:38:26.614904 # ok 793 Set SVE VL 3168
2521 13:38:26.614982 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2522 13:38:26.615101 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2523 13:38:26.615379 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2524 13:38:26.615537 # ok 797 Set SVE VL 3184
2525 13:38:26.615639 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2526 13:38:26.615767 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2527 13:38:26.615894 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2528 13:38:26.615983 # ok 801 Set SVE VL 3200
2529 13:38:26.616084 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2530 13:38:26.616191 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2531 13:38:26.616307 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2532 13:38:26.616408 # ok 805 Set SVE VL 3216
2533 13:38:26.616510 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2534 13:38:26.616615 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2535 13:38:26.616707 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2536 13:38:26.616816 # ok 809 Set SVE VL 3232
2537 13:38:26.617172 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2538 13:38:26.617272 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2539 13:38:26.617365 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2540 13:38:26.617443 # ok 813 Set SVE VL 3248
2541 13:38:26.617536 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2542 13:38:26.617636 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2543 13:38:26.617740 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2544 13:38:26.617847 # ok 817 Set SVE VL 3264
2545 13:38:26.617960 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2546 13:38:26.618065 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2547 13:38:26.618178 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2548 13:38:26.618258 # ok 821 Set SVE VL 3280
2549 13:38:26.618334 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2550 13:38:26.618432 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2551 13:38:26.618520 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2552 13:38:26.618622 # ok 825 Set SVE VL 3296
2553 13:38:26.618693 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2554 13:38:26.618766 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2555 13:38:26.618844 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2556 13:38:26.618918 # ok 829 Set SVE VL 3312
2557 13:38:26.618995 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2558 13:38:26.619266 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2559 13:38:26.619361 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2560 13:38:26.619454 # ok 833 Set SVE VL 3328
2561 13:38:26.619581 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2562 13:38:26.619676 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2563 13:38:26.619782 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2564 13:38:26.619892 # ok 837 Set SVE VL 3344
2565 13:38:26.619974 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2566 13:38:26.620058 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2567 13:38:26.620151 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2568 13:38:26.620235 # ok 841 Set SVE VL 3360
2569 13:38:26.620313 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2570 13:38:26.620409 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2571 13:38:26.620502 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2572 13:38:26.620573 # ok 845 Set SVE VL 3376
2573 13:38:26.620665 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2574 13:38:26.620759 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2575 13:38:26.620858 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2576 13:38:26.620953 # ok 849 Set SVE VL 3392
2577 13:38:26.621048 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2578 13:38:26.621374 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2579 13:38:26.621698 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2580 13:38:26.621813 # ok 853 Set SVE VL 3408
2581 13:38:26.622054 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2582 13:38:26.632803 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2583 13:38:26.632941 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2584 13:38:26.633034 # ok 857 Set SVE VL 3424
2585 13:38:26.633135 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2586 13:38:26.633558 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2587 13:38:26.633875 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2588 13:38:26.633976 # ok 861 Set SVE VL 3440
2589 13:38:26.634061 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2590 13:38:26.634310 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2591 13:38:26.634378 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2592 13:38:26.634440 # ok 865 Set SVE VL 3456
2593 13:38:26.634517 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2594 13:38:26.634582 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2595 13:38:26.634834 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2596 13:38:26.634902 # ok 869 Set SVE VL 3472
2597 13:38:26.634979 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2598 13:38:26.635225 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2599 13:38:26.635300 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2600 13:38:26.635363 # ok 873 Set SVE VL 3488
2601 13:38:26.635439 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2602 13:38:26.635505 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2603 13:38:26.635579 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2604 13:38:26.635645 # ok 877 Set SVE VL 3504
2605 13:38:26.635724 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2606 13:38:26.635991 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2607 13:38:26.636240 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2608 13:38:26.636310 # ok 881 Set SVE VL 3520
2609 13:38:26.636372 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2610 13:38:26.636445 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2611 13:38:26.636519 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2612 13:38:26.636584 # ok 885 Set SVE VL 3536
2613 13:38:26.636660 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2614 13:38:26.636912 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2615 13:38:26.636983 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2616 13:38:26.637056 # ok 889 Set SVE VL 3552
2617 13:38:26.637131 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2618 13:38:26.637375 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2619 13:38:26.637461 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2620 13:38:26.637676 # ok 893 Set SVE VL 3568
2621 13:38:26.637755 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2622 13:38:26.638008 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2623 13:38:26.638080 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2624 13:38:26.638155 # ok 897 Set SVE VL 3584
2625 13:38:26.638219 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2626 13:38:26.638472 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2627 13:38:26.638542 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2628 13:38:26.638616 # ok 901 Set SVE VL 3600
2629 13:38:26.638691 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2630 13:38:26.638769 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2631 13:38:26.639023 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2632 13:38:26.639103 # ok 905 Set SVE VL 3616
2633 13:38:26.639353 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2634 13:38:26.639421 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2635 13:38:26.639498 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2636 13:38:26.639564 # ok 909 Set SVE VL 3632
2637 13:38:26.639816 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2638 13:38:26.639883 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2639 13:38:26.639963 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2640 13:38:26.640029 # ok 913 Set SVE VL 3648
2641 13:38:26.640102 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2642 13:38:26.640178 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2643 13:38:26.640423 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2644 13:38:26.640491 # ok 917 Set SVE VL 3664
2645 13:38:26.640761 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2646 13:38:26.640831 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2647 13:38:26.641073 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2648 13:38:26.641141 # ok 921 Set SVE VL 3680
2649 13:38:26.641214 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2650 13:38:26.641277 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2651 13:38:26.641354 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2652 13:38:26.641599 # ok 925 Set SVE VL 3696
2653 13:38:26.641684 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2654 13:38:26.641763 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2655 13:38:26.642016 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2656 13:38:26.642085 # ok 929 Set SVE VL 3712
2657 13:38:26.642149 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2658 13:38:26.642230 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2659 13:38:26.642492 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2660 13:38:26.642577 # ok 933 Set SVE VL 3728
2661 13:38:26.642658 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2662 13:38:26.642905 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2663 13:38:26.642972 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2664 13:38:26.643032 # ok 937 Set SVE VL 3744
2665 13:38:26.643091 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2666 13:38:26.645350 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2667 13:38:26.645444 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2668 13:38:26.645526 # ok 941 Set SVE VL 3760
2669 13:38:26.645607 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2670 13:38:26.645693 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2671 13:38:26.645756 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2672 13:38:26.645815 # ok 945 Set SVE VL 3776
2673 13:38:26.645875 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2674 13:38:26.645934 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2675 13:38:26.645993 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2676 13:38:26.646071 # ok 949 Set SVE VL 3792
2677 13:38:26.646147 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2678 13:38:26.646213 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2679 13:38:26.646272 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2680 13:38:26.646332 # ok 953 Set SVE VL 3808
2681 13:38:26.646404 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2682 13:38:26.646484 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2683 13:38:26.646564 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2684 13:38:26.646642 # ok 957 Set SVE VL 3824
2685 13:38:26.646723 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2686 13:38:26.646800 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2687 13:38:26.646873 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2688 13:38:26.646947 # ok 961 Set SVE VL 3840
2689 13:38:26.647020 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2690 13:38:26.647095 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2691 13:38:26.647174 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2692 13:38:26.647256 # ok 965 Set SVE VL 3856
2693 13:38:26.647334 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2694 13:38:26.647611 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2695 13:38:26.647695 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2696 13:38:26.647773 # ok 969 Set SVE VL 3872
2697 13:38:26.647849 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2698 13:38:26.647925 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2699 13:38:26.648006 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2700 13:38:26.648075 # ok 973 Set SVE VL 3888
2701 13:38:26.648135 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2702 13:38:26.648199 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2703 13:38:26.648258 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2704 13:38:26.648317 # ok 977 Set SVE VL 3904
2705 13:38:26.648376 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2706 13:38:26.648436 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2707 13:38:26.648495 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2708 13:38:26.648555 # ok 981 Set SVE VL 3920
2709 13:38:26.648619 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2710 13:38:26.648703 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2711 13:38:26.648779 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2712 13:38:26.648859 # ok 985 Set SVE VL 3936
2713 13:38:26.648937 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2714 13:38:26.649019 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2715 13:38:26.649102 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2716 13:38:26.649185 # ok 989 Set SVE VL 3952
2717 13:38:26.649263 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2718 13:38:26.649342 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2719 13:38:26.649424 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2720 13:38:26.649510 # ok 993 Set SVE VL 3968
2721 13:38:26.649593 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2722 13:38:26.649706 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2723 13:38:26.649794 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2724 13:38:26.649877 # ok 997 Set SVE VL 3984
2725 13:38:26.649962 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2726 13:38:26.650045 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2727 13:38:26.650132 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2728 13:38:26.650227 # ok 1001 Set SVE VL 4000
2729 13:38:26.650321 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2730 13:38:26.650403 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2731 13:38:26.650474 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2732 13:38:26.650550 # ok 1005 Set SVE VL 4016
2733 13:38:26.650625 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2734 13:38:26.650721 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2735 13:38:26.650815 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2736 13:38:26.650910 # ok 1009 Set SVE VL 4032
2737 13:38:26.650994 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2738 13:38:26.651273 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2739 13:38:26.651379 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2740 13:38:26.651469 # ok 1013 Set SVE VL 4048
2741 13:38:26.651555 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2742 13:38:26.651639 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2743 13:38:26.651723 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2744 13:38:26.651802 # ok 1017 Set SVE VL 4064
2745 13:38:26.651878 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2746 13:38:26.651952 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2747 13:38:26.652025 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2748 13:38:26.652095 # ok 1021 Set SVE VL 4080
2749 13:38:26.652166 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2750 13:38:26.652243 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2751 13:38:26.652318 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2752 13:38:26.652395 # ok 1025 Set SVE VL 4096
2753 13:38:26.652476 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2754 13:38:26.652559 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2755 13:38:26.652634 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2756 13:38:26.652709 # ok 1029 Set SVE VL 4112
2757 13:38:26.652784 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2758 13:38:26.652860 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2759 13:38:26.652935 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2760 13:38:26.653011 # ok 1033 Set SVE VL 4128
2761 13:38:26.653089 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2762 13:38:26.653167 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2763 13:38:26.653250 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2764 13:38:26.653344 # ok 1037 Set SVE VL 4144
2765 13:38:26.653425 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2766 13:38:26.653510 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2767 13:38:26.653592 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2768 13:38:26.659535 # ok 1041 Set SVE VL 4160
2769 13:38:26.659848 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2770 13:38:26.659950 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2771 13:38:26.660056 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2772 13:38:26.660157 # ok 1045 Set SVE VL 4176
2773 13:38:26.660256 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2774 13:38:26.660373 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2775 13:38:26.660483 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2776 13:38:26.660772 # ok 1049 Set SVE VL 4192
2777 13:38:26.660860 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2778 13:38:26.660958 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2779 13:38:26.661057 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2780 13:38:26.661141 # ok 1053 Set SVE VL 4208
2781 13:38:26.661443 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2782 13:38:26.661556 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2783 13:38:26.661854 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2784 13:38:26.661946 # ok 1057 Set SVE VL 4224
2785 13:38:26.662032 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2786 13:38:26.662132 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2787 13:38:26.662219 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2788 13:38:26.662319 # ok 1061 Set SVE VL 4240
2789 13:38:26.662420 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2790 13:38:26.662696 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2791 13:38:26.662784 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2792 13:38:26.662868 # ok 1065 Set SVE VL 4256
2793 13:38:26.662965 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2794 13:38:26.663050 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2795 13:38:26.663147 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2796 13:38:26.663245 # ok 1069 Set SVE VL 4272
2797 13:38:26.663328 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2798 13:38:26.663609 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2799 13:38:26.663699 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2800 13:38:26.663782 # ok 1073 Set SVE VL 4288
2801 13:38:26.663878 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2802 13:38:26.663963 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2803 13:38:26.664244 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2804 13:38:26.664332 # ok 1077 Set SVE VL 4304
2805 13:38:26.664431 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2806 13:38:26.664516 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2807 13:38:26.664598 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2808 13:38:26.664696 # ok 1081 Set SVE VL 4320
2809 13:38:26.664779 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2810 13:38:26.664878 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2811 13:38:26.664961 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2812 13:38:26.665057 # ok 1085 Set SVE VL 4336
2813 13:38:26.665156 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2814 13:38:26.665443 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2815 13:38:26.665550 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2816 13:38:26.665655 # ok 1089 Set SVE VL 4352
2817 13:38:26.665755 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2818 13:38:26.666036 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2819 13:38:26.666125 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2820 13:38:26.666222 # ok 1093 Set SVE VL 4368
2821 13:38:26.666306 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2822 13:38:26.666403 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2823 13:38:26.666500 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2824 13:38:26.666599 # ok 1097 Set SVE VL 4384
2825 13:38:26.666881 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2826 13:38:26.666968 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2827 13:38:26.667065 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2828 13:38:26.667149 # ok 1101 Set SVE VL 4400
2829 13:38:26.667250 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2830 13:38:26.667348 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2831 13:38:26.667622 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2832 13:38:26.667708 # ok 1105 Set SVE VL 4416
2833 13:38:26.667805 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2834 13:38:26.667890 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2835 13:38:26.667989 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2836 13:38:26.668073 # ok 1109 Set SVE VL 4432
2837 13:38:26.668170 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2838 13:38:26.668254 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2839 13:38:26.668351 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2840 13:38:26.668898 # ok 1113 Set SVE VL 4448
2841 13:38:26.668989 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2842 13:38:26.669071 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2843 13:38:26.669155 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2844 13:38:26.669237 # ok 1117 Set SVE VL 4464
2845 13:38:26.669321 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2846 13:38:26.669595 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2847 13:38:26.669695 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2848 13:38:26.669779 # ok 1121 Set SVE VL 4480
2849 13:38:26.669862 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2850 13:38:26.669944 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2851 13:38:26.670043 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2852 13:38:26.670128 # ok 1125 Set SVE VL 4496
2853 13:38:26.670212 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2854 13:38:26.670309 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2855 13:38:26.670394 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2856 13:38:26.670477 # ok 1129 Set SVE VL 4512
2857 13:38:26.670574 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2858 13:38:26.670687 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2859 13:38:26.670788 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2860 13:38:26.670885 # ok 1133 Set SVE VL 4528
2861 13:38:26.671161 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2862 13:38:26.671255 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2863 13:38:26.671352 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2864 13:38:26.671437 # ok 1137 Set SVE VL 4544
2865 13:38:26.671534 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2866 13:38:26.671806 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2867 13:38:26.671894 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2868 13:38:26.671992 # ok 1141 Set SVE VL 4560
2869 13:38:26.672075 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2870 13:38:26.672174 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2871 13:38:26.672461 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2872 13:38:26.672550 # ok 1145 Set SVE VL 4576
2873 13:38:26.672634 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2874 13:38:26.672903 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2875 13:38:26.672992 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2876 13:38:26.673078 # ok 1149 Set SVE VL 4592
2877 13:38:26.673176 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2878 13:38:26.673266 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2879 13:38:26.673357 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2880 13:38:26.673444 # ok 1153 Set SVE VL 4608
2881 13:38:26.673545 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2882 13:38:26.673635 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2883 13:38:26.673745 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2884 13:38:26.673834 # ok 1157 Set SVE VL 4624
2885 13:38:26.674121 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2886 13:38:26.674213 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2887 13:38:26.674315 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2888 13:38:26.674402 # ok 1161 Set SVE VL 4640
2889 13:38:26.674486 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2890 13:38:26.674587 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2891 13:38:26.674689 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2892 13:38:26.674791 # ok 1165 Set SVE VL 4656
2893 13:38:26.674891 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2894 13:38:26.675204 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2895 13:38:26.675296 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2896 13:38:26.675383 # ok 1169 Set SVE VL 4672
2897 13:38:26.675655 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2898 13:38:26.675747 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2899 13:38:26.675850 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2900 13:38:26.675939 # ok 1173 Set SVE VL 4688
2901 13:38:26.676025 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2902 13:38:26.676127 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2903 13:38:26.676218 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2904 13:38:26.676303 # ok 1177 Set SVE VL 4704
2905 13:38:26.676403 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2906 13:38:26.676490 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2907 13:38:26.676590 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2908 13:38:26.676691 # ok 1181 Set SVE VL 4720
2909 13:38:26.676791 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2910 13:38:26.677078 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2911 13:38:26.677170 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2912 13:38:26.677258 # ok 1185 Set SVE VL 4736
2913 13:38:26.677361 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2914 13:38:26.677460 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2915 13:38:26.677743 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2916 13:38:26.677833 # ok 1189 Set SVE VL 4752
2917 13:38:26.677933 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2918 13:38:26.678033 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2919 13:38:26.678133 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2920 13:38:26.678232 # ok 1193 Set SVE VL 4768
2921 13:38:26.678516 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2922 13:38:26.678606 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2923 13:38:26.678703 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2924 13:38:26.678788 # ok 1197 Set SVE VL 4784
2925 13:38:26.678886 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2926 13:38:26.678985 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2927 13:38:26.679268 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2928 13:38:26.679371 # ok 1201 Set SVE VL 4800
2929 13:38:26.679455 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2930 13:38:26.679553 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2931 13:38:26.679653 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2932 13:38:26.679738 # ok 1205 Set SVE VL 4816
2933 13:38:26.680022 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2934 13:38:26.680111 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2935 13:38:26.680210 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2936 13:38:26.680295 # ok 1209 Set SVE VL 4832
2937 13:38:26.680393 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2938 13:38:26.680491 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2939 13:38:26.680591 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2940 13:38:26.680876 # ok 1213 Set SVE VL 4848
2941 13:38:26.680964 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2942 13:38:26.681063 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2943 13:38:26.681164 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2944 13:38:26.681250 # ok 1217 Set SVE VL 4864
2945 13:38:26.681538 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2946 13:38:26.681628 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2947 13:38:26.681733 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2948 13:38:26.681819 # ok 1221 Set SVE VL 4880
2949 13:38:26.681917 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2950 13:38:26.682016 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2951 13:38:26.687871 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2952 13:38:26.688010 # ok 1225 Set SVE VL 4896
2953 13:38:26.688098 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2954 13:38:26.688200 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2955 13:38:26.688287 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2956 13:38:26.688385 # ok 1229 Set SVE VL 4912
2957 13:38:26.688483 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2958 13:38:26.688782 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2959 13:38:26.688883 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2960 13:38:26.688969 # ok 1233 Set SVE VL 4928
2961 13:38:26.689068 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2962 13:38:26.689168 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2963 13:38:26.689779 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2964 13:38:26.690077 # ok 1237 Set SVE VL 4944
2965 13:38:26.690171 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2966 13:38:26.690271 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2967 13:38:26.690406 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2968 13:38:26.690596 # ok 1241 Set SVE VL 4960
2969 13:38:26.690795 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2970 13:38:26.690983 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2971 13:38:26.691158 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2972 13:38:26.691298 # ok 1245 Set SVE VL 4976
2973 13:38:26.691475 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2974 13:38:26.691619 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2975 13:38:26.691766 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2976 13:38:26.691921 # ok 1249 Set SVE VL 4992
2977 13:38:26.692049 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2978 13:38:26.692183 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2979 13:38:26.692344 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2980 13:38:26.692500 # ok 1253 Set SVE VL 5008
2981 13:38:26.692677 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2982 13:38:26.692827 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2983 13:38:26.692989 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2984 13:38:26.693152 # ok 1257 Set SVE VL 5024
2985 13:38:26.693297 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2986 13:38:26.693421 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2987 13:38:26.693540 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2988 13:38:26.693709 # ok 1261 Set SVE VL 5040
2989 13:38:26.693873 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2990 13:38:26.694040 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2991 13:38:26.694226 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2992 13:38:26.694385 # ok 1265 Set SVE VL 5056
2993 13:38:26.694545 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2994 13:38:26.694685 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2995 13:38:26.694833 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
2996 13:38:26.694974 # ok 1269 Set SVE VL 5072
2997 13:38:26.695106 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
2998 13:38:26.695252 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
2999 13:38:26.695395 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3000 13:38:26.695546 # ok 1273 Set SVE VL 5088
3001 13:38:26.695708 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3002 13:38:26.695902 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3003 13:38:26.696070 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3004 13:38:26.696231 # ok 1277 Set SVE VL 5104
3005 13:38:26.696393 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3006 13:38:26.696556 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3007 13:38:26.696985 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3008 13:38:26.697172 # ok 1281 Set SVE VL 5120
3009 13:38:26.697297 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3010 13:38:26.697415 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3011 13:38:26.697558 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3012 13:38:26.697731 # ok 1285 Set SVE VL 5136
3013 13:38:26.697860 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3014 13:38:26.697997 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3015 13:38:26.698143 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3016 13:38:26.698261 # ok 1289 Set SVE VL 5152
3017 13:38:26.698378 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3018 13:38:26.698489 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3019 13:38:26.698603 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3020 13:38:26.698712 # ok 1293 Set SVE VL 5168
3021 13:38:26.698823 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3022 13:38:26.698934 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3023 13:38:26.699055 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3024 13:38:26.699178 # ok 1297 Set SVE VL 5184
3025 13:38:26.699299 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3026 13:38:26.699420 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3027 13:38:26.699566 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3028 13:38:26.699687 # ok 1301 Set SVE VL 5200
3029 13:38:26.699807 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3030 13:38:26.699928 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3031 13:38:26.700050 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3032 13:38:26.700168 # ok 1305 Set SVE VL 5216
3033 13:38:26.700289 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3034 13:38:26.700410 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3035 13:38:26.700525 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3036 13:38:26.700648 # ok 1309 Set SVE VL 5232
3037 13:38:26.700768 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3038 13:38:26.700889 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3039 13:38:26.701003 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3040 13:38:26.701115 # ok 1313 Set SVE VL 5248
3041 13:38:26.701228 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3042 13:38:26.701334 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3043 13:38:26.701441 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3044 13:38:26.701544 # ok 1317 Set SVE VL 5264
3045 13:38:26.701638 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3046 13:38:26.701759 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3047 13:38:26.701911 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3048 13:38:26.702093 # ok 1321 Set SVE VL 5280
3049 13:38:26.702245 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3050 13:38:26.702611 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3051 13:38:26.702753 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3052 13:38:26.702864 # ok 1325 Set SVE VL 5296
3053 13:38:26.702974 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3054 13:38:26.703069 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3055 13:38:26.703162 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3056 13:38:26.703255 # ok 1329 Set SVE VL 5312
3057 13:38:26.703332 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3058 13:38:26.703393 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3059 13:38:26.703453 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3060 13:38:26.703515 # ok 1333 Set SVE VL 5328
3061 13:38:26.703578 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3062 13:38:26.703639 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3063 13:38:26.703699 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3064 13:38:26.703761 # ok 1337 Set SVE VL 5344
3065 13:38:26.703822 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3066 13:38:26.703884 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3067 13:38:26.703945 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3068 13:38:26.704011 # ok 1341 Set SVE VL 5360
3069 13:38:26.704299 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3070 13:38:26.704413 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3071 13:38:26.704513 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3072 13:38:26.704604 # ok 1345 Set SVE VL 5376
3073 13:38:26.704688 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3074 13:38:26.704786 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3075 13:38:26.704889 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3076 13:38:26.704981 # ok 1349 Set SVE VL 5392
3077 13:38:26.705078 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3078 13:38:26.705180 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3079 13:38:26.705280 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3080 13:38:26.705370 # ok 1353 Set SVE VL 5408
3081 13:38:26.705466 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3082 13:38:26.705549 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3083 13:38:26.705624 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3084 13:38:26.705720 # ok 1357 Set SVE VL 5424
3085 13:38:26.705800 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3086 13:38:26.705896 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3087 13:38:26.706000 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3088 13:38:26.706117 # ok 1361 Set SVE VL 5440
3089 13:38:26.706227 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3090 13:38:26.706345 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3091 13:38:26.706461 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3092 13:38:26.706572 # ok 1365 Set SVE VL 5456
3093 13:38:26.706706 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3094 13:38:26.706821 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3095 13:38:26.706920 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3096 13:38:26.707023 # ok 1369 Set SVE VL 5472
3097 13:38:26.707096 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3098 13:38:26.707172 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3099 13:38:26.707275 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3100 13:38:26.707359 # ok 1373 Set SVE VL 5488
3101 13:38:26.707450 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3102 13:38:26.707532 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3103 13:38:26.707639 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3104 13:38:26.707760 # ok 1377 Set SVE VL 5504
3105 13:38:26.707859 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3106 13:38:26.707969 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3107 13:38:26.708312 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3108 13:38:26.708413 # ok 1381 Set SVE VL 5520
3109 13:38:26.708503 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3110 13:38:26.708600 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3111 13:38:26.708704 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3112 13:38:26.708813 # ok 1385 Set SVE VL 5536
3113 13:38:26.708898 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3114 13:38:26.709001 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3115 13:38:26.709091 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3116 13:38:26.709202 # ok 1389 Set SVE VL 5552
3117 13:38:26.709300 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3118 13:38:26.709610 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3119 13:38:26.709739 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3120 13:38:26.709836 # ok 1393 Set SVE VL 5568
3121 13:38:26.709933 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3122 13:38:26.710032 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3123 13:38:26.710129 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3124 13:38:26.710228 # ok 1397 Set SVE VL 5584
3125 13:38:26.710511 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3126 13:38:26.710614 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3127 13:38:26.710717 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3128 13:38:26.710820 # ok 1401 Set SVE VL 5600
3129 13:38:26.710934 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3130 13:38:26.711036 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3131 13:38:26.711151 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3132 13:38:26.711243 # ok 1405 Set SVE VL 5616
3133 13:38:26.711341 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3134 13:38:26.727832 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3135 13:38:26.728316 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3136 13:38:26.728433 # ok 1409 Set SVE VL 5632
3137 13:38:26.728513 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3138 13:38:26.728599 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3139 13:38:26.728687 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3140 13:38:26.728786 # ok 1413 Set SVE VL 5648
3141 13:38:26.728872 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3142 13:38:26.728956 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3143 13:38:26.729040 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3144 13:38:26.729123 # ok 1417 Set SVE VL 5664
3145 13:38:26.729216 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3146 13:38:26.729292 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3147 13:38:26.729357 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3148 13:38:26.729436 # ok 1421 Set SVE VL 5680
3149 13:38:26.730384 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3150 13:38:26.730701 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3151 13:38:26.730794 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3152 13:38:26.730902 # ok 1425 Set SVE VL 5696
3153 13:38:26.731002 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3154 13:38:26.731099 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3155 13:38:26.731192 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3156 13:38:26.731271 # ok 1429 Set SVE VL 5712
3157 13:38:26.731351 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3158 13:38:26.731433 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3159 13:38:26.731502 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3160 13:38:26.731578 # ok 1433 Set SVE VL 5728
3161 13:38:26.731667 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3162 13:38:26.731750 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3163 13:38:26.731842 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3164 13:38:26.731935 # ok 1437 Set SVE VL 5744
3165 13:38:26.732017 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3166 13:38:26.732129 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3167 13:38:26.732236 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3168 13:38:26.732354 # ok 1441 Set SVE VL 5760
3169 13:38:26.732462 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3170 13:38:26.732564 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3171 13:38:26.732641 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3172 13:38:26.732732 # ok 1445 Set SVE VL 5776
3173 13:38:26.732846 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3174 13:38:26.733160 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3175 13:38:26.733266 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3176 13:38:26.733361 # ok 1449 Set SVE VL 5792
3177 13:38:26.733449 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3178 13:38:26.734044 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3179 13:38:26.734354 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3180 13:38:26.734462 # ok 1453 Set SVE VL 5808
3181 13:38:26.734551 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3182 13:38:26.734654 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3183 13:38:26.734742 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3184 13:38:26.734840 # ok 1457 Set SVE VL 5824
3185 13:38:26.734939 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3186 13:38:26.735041 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3187 13:38:26.735345 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3188 13:38:26.735452 # ok 1461 Set SVE VL 5840
3189 13:38:26.735561 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3190 13:38:26.735664 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3191 13:38:26.735766 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3192 13:38:26.735870 # ok 1465 Set SVE VL 5856
3193 13:38:26.735972 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3194 13:38:26.736318 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3195 13:38:26.736509 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3196 13:38:26.736687 # ok 1469 Set SVE VL 5872
3197 13:38:26.736945 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3198 13:38:26.737137 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3199 13:38:26.737347 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3200 13:38:26.737483 # ok 1473 Set SVE VL 5888
3201 13:38:26.737604 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3202 13:38:26.737835 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3203 13:38:26.738060 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3204 13:38:26.738263 # ok 1477 Set SVE VL 5904
3205 13:38:26.738496 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3206 13:38:26.738665 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3207 13:38:26.738814 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3208 13:38:26.739008 # ok 1481 Set SVE VL 5920
3209 13:38:26.739200 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3210 13:38:26.739392 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3211 13:38:26.739606 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3212 13:38:26.739859 # ok 1485 Set SVE VL 5936
3213 13:38:26.740034 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3214 13:38:26.740183 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3215 13:38:26.740348 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3216 13:38:26.740458 # ok 1489 Set SVE VL 5952
3217 13:38:26.740571 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3218 13:38:26.740716 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3219 13:38:26.740856 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3220 13:38:26.741000 # ok 1493 Set SVE VL 5968
3221 13:38:26.741129 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3222 13:38:26.741244 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3223 13:38:26.741341 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3224 13:38:26.741471 # ok 1497 Set SVE VL 5984
3225 13:38:26.741620 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3226 13:38:26.742114 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3227 13:38:26.742261 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3228 13:38:26.742407 # ok 1501 Set SVE VL 6000
3229 13:38:26.742506 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3230 13:38:26.742580 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3231 13:38:26.742649 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3232 13:38:26.742723 # ok 1505 Set SVE VL 6016
3233 13:38:26.742787 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3234 13:38:26.742875 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3235 13:38:26.742953 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3236 13:38:26.743046 # ok 1509 Set SVE VL 6032
3237 13:38:26.743368 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3238 13:38:26.743493 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3239 13:38:26.743586 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3240 13:38:26.743685 # ok 1513 Set SVE VL 6048
3241 13:38:26.743786 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3242 13:38:26.743893 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3243 13:38:26.743996 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3244 13:38:26.744083 # ok 1517 Set SVE VL 6064
3245 13:38:26.744185 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3246 13:38:26.744286 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3247 13:38:26.744373 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3248 13:38:26.744479 # ok 1521 Set SVE VL 6080
3249 13:38:26.744601 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3250 13:38:26.744690 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3251 13:38:26.744774 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3252 13:38:26.744881 # ok 1525 Set SVE VL 6096
3253 13:38:26.744986 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3254 13:38:26.745109 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3255 13:38:26.745207 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3256 13:38:26.745310 # ok 1529 Set SVE VL 6112
3257 13:38:26.745383 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3258 13:38:26.745458 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3259 13:38:26.745534 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3260 13:38:26.745603 # ok 1533 Set SVE VL 6128
3261 13:38:26.745705 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3262 13:38:26.745808 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3263 13:38:26.745903 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3264 13:38:26.746001 # ok 1537 Set SVE VL 6144
3265 13:38:26.746083 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3266 13:38:26.746166 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3267 13:38:26.746246 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3268 13:38:26.746321 # ok 1541 Set SVE VL 6160
3269 13:38:26.746415 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3270 13:38:26.746515 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3271 13:38:26.746617 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3272 13:38:26.746720 # ok 1545 Set SVE VL 6176
3273 13:38:26.746826 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3274 13:38:26.746924 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3275 13:38:26.747020 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3276 13:38:26.747120 # ok 1549 Set SVE VL 6192
3277 13:38:26.747219 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3278 13:38:26.747315 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3279 13:38:26.747422 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3280 13:38:26.748117 # ok 1553 Set SVE VL 6208
3281 13:38:26.748222 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3282 13:38:26.748315 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3283 13:38:26.748401 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3284 13:38:26.748485 # ok 1557 Set SVE VL 6224
3285 13:38:26.748586 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3286 13:38:26.748703 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3287 13:38:26.748806 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3288 13:38:26.748905 # ok 1561 Set SVE VL 6240
3289 13:38:26.749002 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3290 13:38:26.749108 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3291 13:38:26.749207 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3292 13:38:26.749294 # ok 1565 Set SVE VL 6256
3293 13:38:26.749375 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3294 13:38:26.749443 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3295 13:38:26.749510 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3296 13:38:26.749597 # ok 1569 Set SVE VL 6272
3297 13:38:26.749700 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3298 13:38:26.749794 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3299 13:38:26.749877 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3300 13:38:26.749963 # ok 1573 Set SVE VL 6288
3301 13:38:26.750053 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3302 13:38:26.750164 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3303 13:38:26.750266 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3304 13:38:26.750345 # ok 1577 Set SVE VL 6304
3305 13:38:26.750443 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3306 13:38:26.750540 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3307 13:38:26.750634 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3308 13:38:26.750709 # ok 1581 Set SVE VL 6320
3309 13:38:26.750824 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3310 13:38:26.750931 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3311 13:38:26.751034 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3312 13:38:26.751119 # ok 1585 Set SVE VL 6336
3313 13:38:26.751186 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3314 13:38:26.751247 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3315 13:38:26.751321 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3316 13:38:26.751389 # ok 1589 Set SVE VL 6352
3317 13:38:26.752674 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3318 13:38:26.752771 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3319 13:38:26.752872 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3320 13:38:26.752972 # ok 1593 Set SVE VL 6368
3321 13:38:26.753054 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3322 13:38:26.753154 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3323 13:38:26.753256 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3324 13:38:26.753537 # ok 1597 Set SVE VL 6384
3325 13:38:26.753644 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3326 13:38:26.753747 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3327 13:38:26.754021 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3328 13:38:26.754113 # ok 1601 Set SVE VL 6400
3329 13:38:26.754206 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3330 13:38:26.754274 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3331 13:38:26.754353 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3332 13:38:26.754453 # ok 1605 Set SVE VL 6416
3333 13:38:26.754751 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3334 13:38:26.754847 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3335 13:38:26.754929 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3336 13:38:26.754996 # ok 1609 Set SVE VL 6432
3337 13:38:26.755093 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3338 13:38:26.755167 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3339 13:38:26.755262 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3340 13:38:26.755348 # ok 1613 Set SVE VL 6448
3341 13:38:26.755448 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3342 13:38:26.755727 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3343 13:38:26.755818 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3344 13:38:26.755921 # ok 1617 Set SVE VL 6464
3345 13:38:26.756052 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3346 13:38:26.756141 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3347 13:38:26.756223 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3348 13:38:26.756314 # ok 1621 Set SVE VL 6480
3349 13:38:26.756396 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3350 13:38:26.756491 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3351 13:38:26.756575 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3352 13:38:26.756664 # ok 1625 Set SVE VL 6496
3353 13:38:26.756756 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3354 13:38:26.756852 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3355 13:38:26.756947 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3356 13:38:26.757220 # ok 1629 Set SVE VL 6512
3357 13:38:26.757318 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3358 13:38:26.757404 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3359 13:38:26.757692 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3360 13:38:26.757796 # ok 1633 Set SVE VL 6528
3361 13:38:26.757900 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3362 13:38:26.757988 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3363 13:38:26.758088 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3364 13:38:26.758189 # ok 1637 Set SVE VL 6544
3365 13:38:26.758286 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3366 13:38:26.758597 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3367 13:38:26.758696 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3368 13:38:26.758799 # ok 1641 Set SVE VL 6560
3369 13:38:26.758878 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3370 13:38:26.758972 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3371 13:38:26.759059 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3372 13:38:26.759196 # ok 1645 Set SVE VL 6576
3373 13:38:26.759323 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3374 13:38:26.759424 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3375 13:38:26.759546 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3376 13:38:26.759662 # ok 1649 Set SVE VL 6592
3377 13:38:26.759774 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3378 13:38:26.759863 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3379 13:38:26.759977 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3380 13:38:26.760069 # ok 1653 Set SVE VL 6608
3381 13:38:26.760156 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3382 13:38:26.760238 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3383 13:38:26.760506 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3384 13:38:26.760615 # ok 1657 Set SVE VL 6624
3385 13:38:26.760702 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3386 13:38:26.760797 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3387 13:38:26.760876 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3388 13:38:26.760944 # ok 1661 Set SVE VL 6640
3389 13:38:26.761032 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3390 13:38:26.761111 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3391 13:38:26.761200 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3392 13:38:26.761276 # ok 1665 Set SVE VL 6656
3393 13:38:26.761532 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3394 13:38:26.761800 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3395 13:38:26.762081 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3396 13:38:26.762173 # ok 1669 Set SVE VL 6672
3397 13:38:26.762271 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3398 13:38:26.762574 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3399 13:38:26.762680 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3400 13:38:26.762947 # ok 1673 Set SVE VL 6688
3401 13:38:26.763043 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3402 13:38:26.763139 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3403 13:38:26.763260 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3404 13:38:26.763379 # ok 1677 Set SVE VL 6704
3405 13:38:26.763505 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3406 13:38:26.763822 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3407 13:38:26.763938 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3408 13:38:26.764023 # ok 1681 Set SVE VL 6720
3409 13:38:26.764313 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3410 13:38:26.764423 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3411 13:38:26.764511 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3412 13:38:26.764597 # ok 1685 Set SVE VL 6736
3413 13:38:26.764862 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3414 13:38:26.764944 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3415 13:38:26.765204 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3416 13:38:26.765273 # ok 1689 Set SVE VL 6752
3417 13:38:26.765350 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3418 13:38:26.765600 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3419 13:38:26.765679 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3420 13:38:26.765769 # ok 1693 Set SVE VL 6768
3421 13:38:26.765842 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3422 13:38:26.765918 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3423 13:38:26.765981 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3424 13:38:26.766057 # ok 1697 Set SVE VL 6784
3425 13:38:26.766137 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3426 13:38:26.766214 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3427 13:38:26.766294 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3428 13:38:26.766367 # ok 1701 Set SVE VL 6800
3429 13:38:26.766480 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3430 13:38:26.766573 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3431 13:38:26.766838 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3432 13:38:26.766924 # ok 1705 Set SVE VL 6816
3433 13:38:26.766987 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3434 13:38:26.767059 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3435 13:38:26.767122 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3436 13:38:26.767195 # ok 1709 Set SVE VL 6832
3437 13:38:26.767259 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3438 13:38:26.767331 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3439 13:38:26.767394 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3440 13:38:26.767664 # ok 1713 Set SVE VL 6848
3441 13:38:26.767862 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3442 13:38:26.768038 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3443 13:38:26.768202 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3444 13:38:26.768402 # ok 1717 Set SVE VL 6864
3445 13:38:26.768570 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3446 13:38:26.768709 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3447 13:38:26.768818 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3448 13:38:26.768933 # ok 1721 Set SVE VL 6880
3449 13:38:26.769053 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3450 13:38:26.769184 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3451 13:38:26.769360 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3452 13:38:26.769504 # ok 1725 Set SVE VL 6896
3453 13:38:26.769630 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3454 13:38:26.769797 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3455 13:38:26.769945 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3456 13:38:26.770089 # ok 1729 Set SVE VL 6912
3457 13:38:26.770226 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3458 13:38:26.770353 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3459 13:38:26.770461 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3460 13:38:26.770555 # ok 1733 Set SVE VL 6928
3461 13:38:26.770637 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3462 13:38:26.770702 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3463 13:38:26.770782 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3464 13:38:26.770863 # ok 1737 Set SVE VL 6944
3465 13:38:26.770946 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3466 13:38:26.771047 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3467 13:38:26.771149 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3468 13:38:26.771246 # ok 1741 Set SVE VL 6960
3469 13:38:26.771331 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3470 13:38:26.771435 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3471 13:38:26.771523 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3472 13:38:26.771618 # ok 1745 Set SVE VL 6976
3473 13:38:26.771726 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3474 13:38:26.771839 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3475 13:38:26.771943 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3476 13:38:26.772039 # ok 1749 Set SVE VL 6992
3477 13:38:26.772146 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3478 13:38:26.772250 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3479 13:38:26.772346 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3480 13:38:26.772429 # ok 1753 Set SVE VL 7008
3481 13:38:26.772513 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3482 13:38:26.772591 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3483 13:38:26.772908 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3484 13:38:26.773010 # ok 1757 Set SVE VL 7024
3485 13:38:26.773129 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3486 13:38:26.773215 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3487 13:38:26.773289 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3488 13:38:26.773378 # ok 1761 Set SVE VL 7040
3489 13:38:26.773475 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3490 13:38:26.773565 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3491 13:38:26.773675 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3492 13:38:26.773808 # ok 1765 Set SVE VL 7056
3493 13:38:26.773897 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3494 13:38:26.773962 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3495 13:38:26.774023 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3496 13:38:26.774085 # ok 1769 Set SVE VL 7072
3497 13:38:26.774145 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3498 13:38:26.774206 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3499 13:38:26.774280 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3500 13:38:26.774964 # ok 1773 Set SVE VL 7088
3501 13:38:26.775263 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3502 13:38:26.775352 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3503 13:38:26.775446 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3504 13:38:26.775528 # ok 1777 Set SVE VL 7104
3505 13:38:26.775608 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3506 13:38:26.775879 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3507 13:38:26.775980 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3508 13:38:26.776069 # ok 1781 Set SVE VL 7120
3509 13:38:26.776163 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3510 13:38:26.776236 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3511 13:38:26.776355 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3512 13:38:26.776471 # ok 1785 Set SVE VL 7136
3513 13:38:26.776596 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3514 13:38:26.776711 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3515 13:38:26.776829 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3516 13:38:26.776949 # ok 1789 Set SVE VL 7152
3517 13:38:26.777045 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3518 13:38:26.777315 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3519 13:38:26.777595 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3520 13:38:26.777697 # ok 1793 Set SVE VL 7168
3521 13:38:26.777792 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3522 13:38:26.777872 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3523 13:38:26.777967 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3524 13:38:26.778097 # ok 1797 Set SVE VL 7184
3525 13:38:26.778221 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3526 13:38:26.778351 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3527 13:38:26.778474 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3528 13:38:26.778584 # ok 1801 Set SVE VL 7200
3529 13:38:26.778916 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3530 13:38:26.779013 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3531 13:38:26.779119 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3532 13:38:26.779222 # ok 1805 Set SVE VL 7216
3533 13:38:26.779323 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3534 13:38:26.779435 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3535 13:38:26.779563 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3536 13:38:26.779654 # ok 1809 Set SVE VL 7232
3537 13:38:26.779742 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3538 13:38:26.779848 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3539 13:38:26.779936 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3540 13:38:26.780020 # ok 1813 Set SVE VL 7248
3541 13:38:26.780140 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3542 13:38:26.780231 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3543 13:38:26.780335 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3544 13:38:26.780423 # ok 1817 Set SVE VL 7264
3545 13:38:26.780519 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3546 13:38:26.780604 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3547 13:38:26.780701 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3548 13:38:26.780784 # ok 1821 Set SVE VL 7280
3549 13:38:26.780892 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3550 13:38:26.781219 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3551 13:38:26.781335 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3552 13:38:26.781425 # ok 1825 Set SVE VL 7296
3553 13:38:26.781530 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3554 13:38:26.781604 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3555 13:38:26.781687 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3556 13:38:26.781761 # ok 1829 Set SVE VL 7312
3557 13:38:26.781835 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3558 13:38:26.781913 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3559 13:38:26.782010 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3560 13:38:26.782126 # ok 1833 Set SVE VL 7328
3561 13:38:26.782250 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3562 13:38:26.782359 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3563 13:38:26.782489 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3564 13:38:26.782629 # ok 1837 Set SVE VL 7344
3565 13:38:26.782768 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3566 13:38:26.782928 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3567 13:38:26.783280 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3568 13:38:26.783391 # ok 1841 Set SVE VL 7360
3569 13:38:26.783552 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3570 13:38:26.783737 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3571 13:38:26.783914 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3572 13:38:26.784067 # ok 1845 Set SVE VL 7376
3573 13:38:26.784250 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3574 13:38:26.784435 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3575 13:38:26.784589 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3576 13:38:26.784741 # ok 1849 Set SVE VL 7392
3577 13:38:26.784890 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3578 13:38:26.785047 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3579 13:38:26.785192 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3580 13:38:26.785377 # ok 1853 Set SVE VL 7408
3581 13:38:26.785692 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3582 13:38:26.785810 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3583 13:38:26.785916 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3584 13:38:26.786024 # ok 1857 Set SVE VL 7424
3585 13:38:26.786124 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3586 13:38:26.786223 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3587 13:38:26.786532 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3588 13:38:26.786633 # ok 1861 Set SVE VL 7440
3589 13:38:26.786737 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3590 13:38:26.786819 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3591 13:38:26.786915 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3592 13:38:26.787012 # ok 1865 Set SVE VL 7456
3593 13:38:26.787131 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3594 13:38:26.787248 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3595 13:38:26.787349 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3596 13:38:26.787456 # ok 1869 Set SVE VL 7472
3597 13:38:26.787561 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3598 13:38:26.787867 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3599 13:38:26.787952 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3600 13:38:26.788034 # ok 1873 Set SVE VL 7488
3601 13:38:26.788101 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3602 13:38:26.788180 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3603 13:38:26.788470 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3604 13:38:26.788568 # ok 1877 Set SVE VL 7504
3605 13:38:26.788646 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3606 13:38:26.788730 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3607 13:38:26.788838 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3608 13:38:26.788943 # ok 1881 Set SVE VL 7520
3609 13:38:26.789038 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3610 13:38:26.789312 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3611 13:38:26.789420 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3612 13:38:26.789540 # ok 1885 Set SVE VL 7536
3613 13:38:26.789654 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3614 13:38:26.789756 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3615 13:38:26.790042 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3616 13:38:26.790137 # ok 1889 Set SVE VL 7552
3617 13:38:26.790226 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3618 13:38:26.790297 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3619 13:38:26.790385 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3620 13:38:26.790482 # ok 1893 Set SVE VL 7568
3621 13:38:26.790602 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3622 13:38:26.790728 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3623 13:38:26.791064 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3624 13:38:26.791174 # ok 1897 Set SVE VL 7584
3625 13:38:26.791266 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3626 13:38:26.791375 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3627 13:38:26.791461 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3628 13:38:26.791561 # ok 1901 Set SVE VL 7600
3629 13:38:26.791645 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3630 13:38:26.791742 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3631 13:38:26.791838 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3632 13:38:26.791930 # ok 1905 Set SVE VL 7616
3633 13:38:26.792025 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3634 13:38:26.792130 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3635 13:38:26.792427 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3636 13:38:26.792535 # ok 1909 Set SVE VL 7632
3637 13:38:26.792636 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3638 13:38:26.792947 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3639 13:38:26.793153 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3640 13:38:26.793333 # ok 1913 Set SVE VL 7648
3641 13:38:26.793523 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3642 13:38:26.793703 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3643 13:38:26.793867 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3644 13:38:26.794047 # ok 1917 Set SVE VL 7664
3645 13:38:26.794260 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3646 13:38:26.794430 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3647 13:38:26.794570 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3648 13:38:26.794732 # ok 1921 Set SVE VL 7680
3649 13:38:26.794862 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3650 13:38:26.794958 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3651 13:38:26.795102 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3652 13:38:26.795224 # ok 1925 Set SVE VL 7696
3653 13:38:26.795341 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3654 13:38:26.795465 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3655 13:38:26.795599 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3656 13:38:26.795747 # ok 1929 Set SVE VL 7712
3657 13:38:26.795860 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3658 13:38:26.795980 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3659 13:38:26.796107 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3660 13:38:26.796246 # ok 1933 Set SVE VL 7728
3661 13:38:26.796378 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3662 13:38:26.796503 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3663 13:38:26.796645 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3664 13:38:26.796768 # ok 1937 Set SVE VL 7744
3665 13:38:26.796870 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3666 13:38:26.797021 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3667 13:38:26.797163 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3668 13:38:26.797303 # ok 1941 Set SVE VL 7760
3669 13:38:26.797451 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3670 13:38:26.797567 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3671 13:38:26.797715 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3672 13:38:26.797848 # ok 1945 Set SVE VL 7776
3673 13:38:26.797944 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3674 13:38:26.798033 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3675 13:38:26.798143 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3676 13:38:26.798235 # ok 1949 Set SVE VL 7792
3677 13:38:26.798324 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3678 13:38:26.798410 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3679 13:38:26.798485 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3680 13:38:26.798545 # ok 1953 Set SVE VL 7808
3681 13:38:26.799069 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3682 13:38:26.799142 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3683 13:38:26.799586 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3684 13:38:26.799687 # ok 1957 Set SVE VL 7824
3685 13:38:26.799782 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3686 13:38:26.799876 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3687 13:38:26.799959 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3688 13:38:26.800051 # ok 1961 Set SVE VL 7840
3689 13:38:26.800146 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3690 13:38:26.800273 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3691 13:38:26.800406 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3692 13:38:26.800517 # ok 1965 Set SVE VL 7856
3693 13:38:26.800633 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3694 13:38:26.800743 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3695 13:38:26.800830 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3696 13:38:26.800941 # ok 1969 Set SVE VL 7872
3697 13:38:26.801076 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3698 13:38:26.801175 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3699 13:38:26.801280 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3700 13:38:26.801589 # ok 1973 Set SVE VL 7888
3701 13:38:26.801910 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3702 13:38:26.802007 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3703 13:38:26.802107 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3704 13:38:26.802187 # ok 1977 Set SVE VL 7904
3705 13:38:26.802286 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3706 13:38:26.802437 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3707 13:38:26.802589 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3708 13:38:26.802711 # ok 1981 Set SVE VL 7920
3709 13:38:26.802831 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3710 13:38:26.803171 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3711 13:38:26.803299 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3712 13:38:26.803404 # ok 1985 Set SVE VL 7936
3713 13:38:26.803497 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3714 13:38:26.803594 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3715 13:38:26.803691 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3716 13:38:26.803809 # ok 1989 Set SVE VL 7952
3717 13:38:26.803913 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3718 13:38:26.804172 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3719 13:38:26.804290 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3720 13:38:26.804397 # ok 1993 Set SVE VL 7968
3721 13:38:26.804483 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3722 13:38:26.804577 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3723 13:38:26.804672 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3724 13:38:26.804764 # ok 1997 Set SVE VL 7984
3725 13:38:26.804860 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3726 13:38:26.804962 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3727 13:38:26.805253 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3728 13:38:26.805347 # ok 2001 Set SVE VL 8000
3729 13:38:26.805443 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3730 13:38:26.805575 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3731 13:38:26.805858 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3732 13:38:26.805981 # ok 2005 Set SVE VL 8016
3733 13:38:26.806084 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3734 13:38:26.806171 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3735 13:38:26.806281 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3736 13:38:26.806379 # ok 2009 Set SVE VL 8032
3737 13:38:26.806487 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3738 13:38:26.806607 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3739 13:38:26.806726 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3740 13:38:26.806821 # ok 2013 Set SVE VL 8048
3741 13:38:26.806927 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3742 13:38:26.807019 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3743 13:38:26.807117 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3744 13:38:26.807203 # ok 2017 Set SVE VL 8064
3745 13:38:26.807314 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3746 13:38:26.807415 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3747 13:38:26.807540 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3748 13:38:26.807645 # ok 2021 Set SVE VL 8080
3749 13:38:26.807936 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3750 13:38:26.808040 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3751 13:38:26.808142 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3752 13:38:26.808242 # ok 2025 Set SVE VL 8096
3753 13:38:26.808340 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3754 13:38:26.808438 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3755 13:38:26.808538 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3756 13:38:26.808655 # ok 2029 Set SVE VL 8112
3757 13:38:26.808958 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3758 13:38:26.809061 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3759 13:38:26.809163 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3760 13:38:26.809248 # ok 2033 Set SVE VL 8128
3761 13:38:26.809343 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3762 13:38:26.809640 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3763 13:38:26.809944 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3764 13:38:26.810038 # ok 2037 Set SVE VL 8144
3765 13:38:26.810114 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3766 13:38:26.810197 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3767 13:38:26.810268 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3768 13:38:26.810354 # ok 2041 Set SVE VL 8160
3769 13:38:26.810468 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3770 13:38:26.810561 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3771 13:38:26.810656 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3772 13:38:26.810785 # ok 2045 Set SVE VL 8176
3773 13:38:26.810914 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3774 13:38:26.811030 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3775 13:38:26.811158 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3776 13:38:26.811272 # ok 2049 Set SVE VL 8192
3777 13:38:26.811382 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3778 13:38:26.811714 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3779 13:38:26.811808 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3780 13:38:26.811914 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3781 13:38:26.812015 # ok 2054 Streaming SVE get_fpsimd() gave same state
3782 13:38:26.812096 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3783 13:38:26.812205 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3784 13:38:26.812326 # ok 2057 Set Streaming SVE VL 16
3785 13:38:26.812428 # ok 2058 Set and get Streaming SVE data for VL 16
3786 13:38:26.812552 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3787 13:38:26.812662 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3788 13:38:26.812779 # ok 2061 Set Streaming SVE VL 32
3789 13:38:26.812866 # ok 2062 Set and get Streaming SVE data for VL 32
3790 13:38:26.812959 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3791 13:38:26.813250 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3792 13:38:26.813336 # ok 2065 Set Streaming SVE VL 48
3793 13:38:26.813432 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3794 13:38:26.813534 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3795 13:38:26.813635 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3796 13:38:26.813739 # ok 2069 Set Streaming SVE VL 64
3797 13:38:26.813822 # ok 2070 Set and get Streaming SVE data for VL 64
3798 13:38:26.814108 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3799 13:38:26.814205 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3800 13:38:26.814302 # ok 2073 Set Streaming SVE VL 80
3801 13:38:26.814386 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3802 13:38:26.814478 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3803 13:38:26.814577 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3804 13:38:26.814694 # ok 2077 Set Streaming SVE VL 96
3805 13:38:26.814995 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3806 13:38:26.815108 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3807 13:38:26.815207 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3808 13:38:26.815330 # ok 2081 Set Streaming SVE VL 112
3809 13:38:26.815445 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3810 13:38:26.815565 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3811 13:38:26.815917 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3812 13:38:26.816021 # ok 2085 Set Streaming SVE VL 128
3813 13:38:26.816137 # ok 2086 Set and get Streaming SVE data for VL 128
3814 13:38:26.816223 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3815 13:38:26.816320 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3816 13:38:26.816414 # ok 2089 Set Streaming SVE VL 144
3817 13:38:26.816683 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3818 13:38:26.816787 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3819 13:38:26.816878 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3820 13:38:26.816973 # ok 2093 Set Streaming SVE VL 160
3821 13:38:26.817237 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3822 13:38:26.817338 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3823 13:38:26.817468 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3824 13:38:26.817587 # ok 2097 Set Streaming SVE VL 176
3825 13:38:26.817885 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3826 13:38:26.817988 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3827 13:38:26.818094 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3828 13:38:26.818178 # ok 2101 Set Streaming SVE VL 192
3829 13:38:26.818274 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3830 13:38:26.818376 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3831 13:38:26.818667 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3832 13:38:26.818759 # ok 2105 Set Streaming SVE VL 208
3833 13:38:26.818847 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3834 13:38:26.818958 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3835 13:38:26.819113 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3836 13:38:26.819221 # ok 2109 Set Streaming SVE VL 224
3837 13:38:26.819511 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3838 13:38:26.819613 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3839 13:38:26.819721 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3840 13:38:26.819843 # ok 2113 Set Streaming SVE VL 240
3841 13:38:26.819967 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3842 13:38:26.820085 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3843 13:38:26.820426 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3844 13:38:26.820545 # ok 2117 Set Streaming SVE VL 256
3845 13:38:26.820666 # ok 2118 Set and get Streaming SVE data for VL 256
3846 13:38:26.820771 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3847 13:38:26.820874 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3848 13:38:26.820985 # ok 2121 Set Streaming SVE VL 272
3849 13:38:26.821095 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3850 13:38:26.821253 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3851 13:38:26.821552 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3852 13:38:26.821670 # ok 2125 Set Streaming SVE VL 288
3853 13:38:26.824043 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3854 13:38:26.824376 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3855 13:38:26.824496 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3856 13:38:26.824603 # ok 2129 Set Streaming SVE VL 304
3857 13:38:26.824687 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3858 13:38:26.824784 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3859 13:38:26.824885 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3860 13:38:26.824978 # ok 2133 Set Streaming SVE VL 320
3861 13:38:26.825283 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3862 13:38:26.825401 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3863 13:38:26.825671 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3864 13:38:26.825795 # ok 2137 Set Streaming SVE VL 336
3865 13:38:26.825923 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3866 13:38:26.826036 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3867 13:38:26.826133 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3868 13:38:26.826231 # ok 2141 Set Streaming SVE VL 352
3869 13:38:26.826541 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3870 13:38:26.826644 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3871 13:38:26.826751 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3872 13:38:26.827041 # ok 2145 Set Streaming SVE VL 368
3873 13:38:26.827139 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3874 13:38:26.827442 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3875 13:38:26.827563 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3876 13:38:26.827664 # ok 2149 Set Streaming SVE VL 384
3877 13:38:26.827773 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3878 13:38:26.827859 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3879 13:38:26.827936 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3880 13:38:26.828027 # ok 2153 Set Streaming SVE VL 400
3881 13:38:26.828124 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3882 13:38:26.828223 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3883 13:38:26.828542 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3884 13:38:26.828644 # ok 2157 Set Streaming SVE VL 416
3885 13:38:26.828740 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3886 13:38:26.828834 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3887 13:38:26.829151 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3888 13:38:26.829245 # ok 2161 Set Streaming SVE VL 432
3889 13:38:26.829334 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3890 13:38:26.829406 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3891 13:38:26.829679 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3892 13:38:26.829769 # ok 2165 Set Streaming SVE VL 448
3893 13:38:26.829868 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3894 13:38:26.829951 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3895 13:38:26.830047 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3896 13:38:26.830144 # ok 2169 Set Streaming SVE VL 464
3897 13:38:26.830402 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3898 13:38:26.830513 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3899 13:38:26.830614 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3900 13:38:26.830707 # ok 2173 Set Streaming SVE VL 480
3901 13:38:26.830804 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3902 13:38:26.830908 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3903 13:38:26.831037 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3904 13:38:26.831138 # ok 2177 Set Streaming SVE VL 496
3905 13:38:26.831424 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3906 13:38:26.831540 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3907 13:38:26.831633 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3908 13:38:26.831720 # ok 2181 Set Streaming SVE VL 512
3909 13:38:26.831815 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3910 13:38:26.831924 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3911 13:38:26.832210 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3912 13:38:26.832309 # ok 2185 Set Streaming SVE VL 528
3913 13:38:26.832406 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3914 13:38:26.832516 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3915 13:38:26.832624 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3916 13:38:26.832736 # ok 2189 Set Streaming SVE VL 544
3917 13:38:26.832860 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3918 13:38:26.833167 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3919 13:38:26.833272 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3920 13:38:26.833395 # ok 2193 Set Streaming SVE VL 560
3921 13:38:26.833493 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3922 13:38:26.833780 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3923 13:38:26.833882 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3924 13:38:26.833982 # ok 2197 Set Streaming SVE VL 576
3925 13:38:26.834080 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3926 13:38:26.834182 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3927 13:38:26.834312 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3928 13:38:26.834622 # ok 2201 Set Streaming SVE VL 592
3929 13:38:26.834748 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3930 13:38:26.834884 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3931 13:38:26.834986 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3932 13:38:26.835095 # ok 2205 Set Streaming SVE VL 608
3933 13:38:26.835182 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3934 13:38:26.835280 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3935 13:38:26.835379 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3936 13:38:26.835482 # ok 2209 Set Streaming SVE VL 624
3937 13:38:26.835783 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3938 13:38:26.835876 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3939 13:38:26.835971 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3940 13:38:26.836059 # ok 2213 Set Streaming SVE VL 640
3941 13:38:26.836154 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3942 13:38:26.836434 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3943 13:38:26.836553 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3944 13:38:26.836659 # ok 2217 Set Streaming SVE VL 656
3945 13:38:26.836787 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3946 13:38:26.836908 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3947 13:38:26.837266 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3948 13:38:26.837373 # ok 2221 Set Streaming SVE VL 672
3949 13:38:26.837484 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3950 13:38:26.837759 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3951 13:38:26.837857 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3952 13:38:26.837975 # ok 2225 Set Streaming SVE VL 688
3953 13:38:26.838099 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3954 13:38:26.838207 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3955 13:38:26.838321 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3956 13:38:26.838446 # ok 2229 Set Streaming SVE VL 704
3957 13:38:26.838595 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3958 13:38:26.838936 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3959 13:38:26.839028 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3960 13:38:26.839127 # ok 2233 Set Streaming SVE VL 720
3961 13:38:26.839246 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3962 13:38:26.839366 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3963 13:38:26.839480 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3964 13:38:26.839576 # ok 2237 Set Streaming SVE VL 736
3965 13:38:26.839665 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3966 13:38:26.839937 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3967 13:38:26.840039 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3968 13:38:26.840146 # ok 2241 Set Streaming SVE VL 752
3969 13:38:26.840230 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3970 13:38:26.840329 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3971 13:38:26.840426 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3972 13:38:26.840748 # ok 2245 Set Streaming SVE VL 768
3973 13:38:26.840857 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3974 13:38:26.840966 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3975 13:38:26.841071 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3976 13:38:26.841169 # ok 2249 Set Streaming SVE VL 784
3977 13:38:26.841464 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3978 13:38:26.841767 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3979 13:38:26.841879 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3980 13:38:26.841980 # ok 2253 Set Streaming SVE VL 800
3981 13:38:26.842076 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3982 13:38:26.842185 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3983 13:38:26.842451 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3984 13:38:26.842550 # ok 2257 Set Streaming SVE VL 816
3985 13:38:26.842650 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3986 13:38:26.842934 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3987 13:38:26.843062 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3988 13:38:26.843174 # ok 2261 Set Streaming SVE VL 832
3989 13:38:26.843311 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3990 13:38:26.843616 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3991 13:38:26.843750 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3992 13:38:26.843871 # ok 2265 Set Streaming SVE VL 848
3993 13:38:26.844204 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3994 13:38:26.844349 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3995 13:38:26.844451 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
3996 13:38:26.844577 # ok 2269 Set Streaming SVE VL 864
3997 13:38:26.844684 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
3998 13:38:26.844982 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
3999 13:38:26.845104 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4000 13:38:26.845217 # ok 2273 Set Streaming SVE VL 880
4001 13:38:26.845548 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4002 13:38:26.845856 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4003 13:38:26.845965 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4004 13:38:26.846090 # ok 2277 Set Streaming SVE VL 896
4005 13:38:26.846210 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4006 13:38:26.848311 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4007 13:38:26.848445 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4008 13:38:26.848570 # ok 2281 Set Streaming SVE VL 912
4009 13:38:26.848691 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4010 13:38:26.849038 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4011 13:38:26.849142 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4012 13:38:26.849238 # ok 2285 Set Streaming SVE VL 928
4013 13:38:26.849366 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4014 13:38:26.849471 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4015 13:38:26.849769 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4016 13:38:26.849870 # ok 2289 Set Streaming SVE VL 944
4017 13:38:26.849980 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4018 13:38:26.850292 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4019 13:38:26.850409 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4020 13:38:26.850528 # ok 2293 Set Streaming SVE VL 960
4021 13:38:26.850661 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4022 13:38:26.850783 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4023 13:38:26.850889 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4024 13:38:26.850995 # ok 2297 Set Streaming SVE VL 976
4025 13:38:26.851300 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4026 13:38:26.851408 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4027 13:38:26.851513 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4028 13:38:26.851615 # ok 2301 Set Streaming SVE VL 992
4029 13:38:26.851927 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4030 13:38:26.852029 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4031 13:38:26.852132 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4032 13:38:26.852232 # ok 2305 Set Streaming SVE VL 1008
4033 13:38:26.852612 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4034 13:38:26.852731 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4035 13:38:26.852823 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4036 13:38:26.852924 # ok 2309 Set Streaming SVE VL 1024
4037 13:38:26.853026 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4038 13:38:26.853217 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4039 13:38:26.853541 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4040 13:38:26.853670 # ok 2313 Set Streaming SVE VL 1040
4041 13:38:26.853774 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4042 13:38:26.854078 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4043 13:38:26.854197 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4044 13:38:26.854301 # ok 2317 Set Streaming SVE VL 1056
4045 13:38:26.854601 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4046 13:38:26.854729 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4047 13:38:26.854820 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4048 13:38:26.854922 # ok 2321 Set Streaming SVE VL 1072
4049 13:38:26.855023 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4050 13:38:26.855320 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4051 13:38:26.855436 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4052 13:38:26.855523 # ok 2325 Set Streaming SVE VL 1088
4053 13:38:26.855619 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4054 13:38:26.855717 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4055 13:38:26.855851 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4056 13:38:26.856159 # ok 2329 Set Streaming SVE VL 1104
4057 13:38:26.856259 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4058 13:38:26.856344 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4059 13:38:26.856427 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4060 13:38:26.856518 # ok 2333 Set Streaming SVE VL 1120
4061 13:38:26.856809 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4062 13:38:26.856923 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4063 13:38:26.857024 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4064 13:38:26.857117 # ok 2337 Set Streaming SVE VL 1136
4065 13:38:26.857410 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4066 13:38:26.857502 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4067 13:38:26.857767 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4068 13:38:26.857871 # ok 2341 Set Streaming SVE VL 1152
4069 13:38:26.857988 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4070 13:38:26.858090 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4071 13:38:26.858201 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4072 13:38:26.858299 # ok 2345 Set Streaming SVE VL 1168
4073 13:38:26.858410 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4074 13:38:26.858522 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4075 13:38:26.858841 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4076 13:38:26.858950 # ok 2349 Set Streaming SVE VL 1184
4077 13:38:26.859075 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4078 13:38:26.859196 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4079 13:38:26.859503 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4080 13:38:26.859588 # ok 2353 Set Streaming SVE VL 1200
4081 13:38:26.859658 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4082 13:38:26.859761 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4083 13:38:26.859860 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4084 13:38:26.859961 # ok 2357 Set Streaming SVE VL 1216
4085 13:38:26.860239 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4086 13:38:26.860342 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4087 13:38:26.860442 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4088 13:38:26.860542 # ok 2361 Set Streaming SVE VL 1232
4089 13:38:26.860843 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4090 13:38:26.860959 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4091 13:38:26.861260 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4092 13:38:26.861353 # ok 2365 Set Streaming SVE VL 1248
4093 13:38:26.861449 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4094 13:38:26.861708 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4095 13:38:26.861849 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4096 13:38:26.861964 # ok 2369 Set Streaming SVE VL 1264
4097 13:38:26.862248 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4098 13:38:26.862350 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4099 13:38:26.862449 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4100 13:38:26.862543 # ok 2373 Set Streaming SVE VL 1280
4101 13:38:26.862834 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4102 13:38:26.862928 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4103 13:38:26.863042 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4104 13:38:26.863146 # ok 2377 Set Streaming SVE VL 1296
4105 13:38:26.863260 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4106 13:38:26.863375 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4107 13:38:26.863668 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4108 13:38:26.863762 # ok 2381 Set Streaming SVE VL 1312
4109 13:38:26.863855 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4110 13:38:26.863969 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4111 13:38:26.864075 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4112 13:38:26.864193 # ok 2385 Set Streaming SVE VL 1328
4113 13:38:26.864306 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4114 13:38:26.864637 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4115 13:38:26.864734 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4116 13:38:26.864835 # ok 2389 Set Streaming SVE VL 1344
4117 13:38:26.864931 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4118 13:38:26.865222 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4119 13:38:26.865335 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4120 13:38:26.865445 # ok 2393 Set Streaming SVE VL 1360
4121 13:38:26.865767 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4122 13:38:26.865868 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4123 13:38:26.865981 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4124 13:38:26.866080 # ok 2397 Set Streaming SVE VL 1376
4125 13:38:26.866367 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4126 13:38:26.866457 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4127 13:38:26.866544 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4128 13:38:26.866664 # ok 2401 Set Streaming SVE VL 1392
4129 13:38:26.866774 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4130 13:38:26.866864 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4131 13:38:26.866972 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4132 13:38:26.867255 # ok 2405 Set Streaming SVE VL 1408
4133 13:38:26.867341 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4134 13:38:26.867455 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4135 13:38:26.867554 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4136 13:38:26.867878 # ok 2409 Set Streaming SVE VL 1424
4137 13:38:26.868006 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4138 13:38:26.868117 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4139 13:38:26.868206 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4140 13:38:26.868294 # ok 2413 Set Streaming SVE VL 1440
4141 13:38:26.868566 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4142 13:38:26.868667 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4143 13:38:26.868945 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4144 13:38:26.869026 # ok 2417 Set Streaming SVE VL 1456
4145 13:38:26.869284 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4146 13:38:26.869383 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4147 13:38:26.869487 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4148 13:38:26.869562 # ok 2421 Set Streaming SVE VL 1472
4149 13:38:26.869662 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4150 13:38:26.869804 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4151 13:38:26.870127 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4152 13:38:26.870242 # ok 2425 Set Streaming SVE VL 1488
4153 13:38:26.870555 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4154 13:38:26.870653 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4155 13:38:26.870742 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4156 13:38:26.871805 # ok 2429 Set Streaming SVE VL 1504
4157 13:38:26.872110 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4158 13:38:26.872192 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4159 13:38:26.872282 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4160 13:38:26.872375 # ok 2433 Set Streaming SVE VL 1520
4161 13:38:26.872664 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4162 13:38:26.872768 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4163 13:38:26.872907 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4164 13:38:26.873001 # ok 2437 Set Streaming SVE VL 1536
4165 13:38:26.873103 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4166 13:38:26.873402 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4167 13:38:26.873524 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4168 13:38:26.873812 # ok 2441 Set Streaming SVE VL 1552
4169 13:38:26.874125 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4170 13:38:26.874229 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4171 13:38:26.874330 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4172 13:38:26.874437 # ok 2445 Set Streaming SVE VL 1568
4173 13:38:26.874746 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4174 13:38:26.874860 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4175 13:38:26.875182 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4176 13:38:26.875306 # ok 2449 Set Streaming SVE VL 1584
4177 13:38:26.875426 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4178 13:38:26.875522 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4179 13:38:26.875626 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4180 13:38:26.875755 # ok 2453 Set Streaming SVE VL 1600
4181 13:38:26.875868 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4182 13:38:26.876172 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4183 13:38:26.876298 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4184 13:38:26.876604 # ok 2457 Set Streaming SVE VL 1616
4185 13:38:26.876735 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4186 13:38:26.876835 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4187 13:38:26.876957 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4188 13:38:26.877058 # ok 2461 Set Streaming SVE VL 1632
4189 13:38:26.877322 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4190 13:38:26.877441 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4191 13:38:26.877759 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4192 13:38:26.877880 # ok 2465 Set Streaming SVE VL 1648
4193 13:38:26.878002 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4194 13:38:26.878114 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4195 13:38:26.878221 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4196 13:38:26.878318 # ok 2469 Set Streaming SVE VL 1664
4197 13:38:26.878612 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4198 13:38:26.878733 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4199 13:38:26.878846 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4200 13:38:26.878956 # ok 2473 Set Streaming SVE VL 1680
4201 13:38:26.879072 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4202 13:38:26.879392 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4203 13:38:26.879485 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4204 13:38:26.879586 # ok 2477 Set Streaming SVE VL 1696
4205 13:38:26.879702 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4206 13:38:26.879809 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4207 13:38:26.880102 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4208 13:38:26.880202 # ok 2481 Set Streaming SVE VL 1712
4209 13:38:26.880290 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4210 13:38:26.880370 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4211 13:38:26.880457 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4212 13:38:26.880541 # ok 2485 Set Streaming SVE VL 1728
4213 13:38:26.880631 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4214 13:38:26.880903 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4215 13:38:26.880992 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4216 13:38:26.881089 # ok 2489 Set Streaming SVE VL 1744
4217 13:38:26.881186 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4218 13:38:26.881284 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4219 13:38:26.881381 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4220 13:38:26.881474 # ok 2493 Set Streaming SVE VL 1760
4221 13:38:26.881770 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4222 13:38:26.881889 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4223 13:38:26.881991 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4224 13:38:26.882294 # ok 2497 Set Streaming SVE VL 1776
4225 13:38:26.882442 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4226 13:38:26.882614 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4227 13:38:26.882738 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4228 13:38:26.883130 # ok 2501 Set Streaming SVE VL 1792
4229 13:38:26.883235 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4230 13:38:26.883343 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4231 13:38:26.883436 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4232 13:38:26.883536 # ok 2505 Set Streaming SVE VL 1808
4233 13:38:26.883641 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4234 13:38:26.883914 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4235 13:38:26.884026 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4236 13:38:26.884120 # ok 2509 Set Streaming SVE VL 1824
4237 13:38:26.884216 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4238 13:38:26.884407 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4239 13:38:26.884712 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4240 13:38:26.884811 # ok 2513 Set Streaming SVE VL 1840
4241 13:38:26.884906 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4242 13:38:26.885008 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4243 13:38:26.885215 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4244 13:38:26.885316 # ok 2517 Set Streaming SVE VL 1856
4245 13:38:26.885419 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4246 13:38:26.885704 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4247 13:38:26.885839 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4248 13:38:26.885969 # ok 2521 Set Streaming SVE VL 1872
4249 13:38:26.886068 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4250 13:38:26.886166 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4251 13:38:26.886466 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4252 13:38:26.886583 # ok 2525 Set Streaming SVE VL 1888
4253 13:38:26.886686 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4254 13:38:26.886781 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4255 13:38:26.886886 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4256 13:38:26.886980 # ok 2529 Set Streaming SVE VL 1904
4257 13:38:26.887183 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4258 13:38:26.887295 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4259 13:38:26.887605 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4260 13:38:26.887711 # ok 2533 Set Streaming SVE VL 1920
4261 13:38:26.887826 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4262 13:38:26.887939 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4263 13:38:26.888063 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4264 13:38:26.888153 # ok 2537 Set Streaming SVE VL 1936
4265 13:38:26.888445 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4266 13:38:26.888533 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4267 13:38:26.888653 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4268 13:38:26.888750 # ok 2541 Set Streaming SVE VL 1952
4269 13:38:26.888860 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4270 13:38:26.888969 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4271 13:38:26.889071 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4272 13:38:26.889359 # ok 2545 Set Streaming SVE VL 1968
4273 13:38:26.889452 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4274 13:38:26.889696 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4275 13:38:26.889832 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4276 13:38:26.889963 # ok 2549 Set Streaming SVE VL 1984
4277 13:38:26.890070 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4278 13:38:26.890183 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4279 13:38:26.890500 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4280 13:38:26.890619 # ok 2553 Set Streaming SVE VL 2000
4281 13:38:26.890744 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4282 13:38:26.890863 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4283 13:38:26.890969 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4284 13:38:26.891073 # ok 2557 Set Streaming SVE VL 2016
4285 13:38:26.891189 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4286 13:38:26.891303 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4287 13:38:26.891603 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4288 13:38:26.891732 # ok 2561 Set Streaming SVE VL 2032
4289 13:38:26.891861 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4290 13:38:26.891976 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4291 13:38:26.892295 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4292 13:38:26.892399 # ok 2565 Set Streaming SVE VL 2048
4293 13:38:26.892507 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4294 13:38:26.892610 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4295 13:38:26.892720 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4296 13:38:26.892824 # ok 2569 Set Streaming SVE VL 2064
4297 13:38:26.892920 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4298 13:38:26.893198 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4299 13:38:26.893321 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4300 13:38:26.893436 # ok 2573 Set Streaming SVE VL 2080
4301 13:38:26.893537 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4302 13:38:26.893830 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4303 13:38:26.893945 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4304 13:38:26.894047 # ok 2577 Set Streaming SVE VL 2096
4305 13:38:26.894150 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4306 13:38:26.895734 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4307 13:38:26.895858 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4308 13:38:26.895964 # ok 2581 Set Streaming SVE VL 2112
4309 13:38:26.896067 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4310 13:38:26.896372 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4311 13:38:26.896491 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4312 13:38:26.896579 # ok 2585 Set Streaming SVE VL 2128
4313 13:38:26.896680 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4314 13:38:26.896969 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4315 13:38:26.897075 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4316 13:38:26.897175 # ok 2589 Set Streaming SVE VL 2144
4317 13:38:26.897277 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4318 13:38:26.897446 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4319 13:38:26.897967 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4320 13:38:26.898090 # ok 2593 Set Streaming SVE VL 2160
4321 13:38:26.898199 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4322 13:38:26.898440 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4323 13:38:26.898557 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4324 13:38:26.898636 # ok 2597 Set Streaming SVE VL 2176
4325 13:38:26.898730 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4326 13:38:26.899041 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4327 13:38:26.899138 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4328 13:38:26.899259 # ok 2601 Set Streaming SVE VL 2192
4329 13:38:26.899354 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4330 13:38:26.899479 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4331 13:38:26.899604 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4332 13:38:26.899702 # ok 2605 Set Streaming SVE VL 2208
4333 13:38:26.899813 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4334 13:38:26.899927 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4335 13:38:26.900224 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4336 13:38:26.900336 # ok 2609 Set Streaming SVE VL 2224
4337 13:38:26.900446 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4338 13:38:26.900559 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4339 13:38:26.900690 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4340 13:38:26.900798 # ok 2613 Set Streaming SVE VL 2240
4341 13:38:26.901122 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4342 13:38:26.901221 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4343 13:38:26.901310 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4344 13:38:26.901592 # ok 2617 Set Streaming SVE VL 2256
4345 13:38:26.901708 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4346 13:38:26.902007 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4347 13:38:26.902103 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4348 13:38:26.902192 # ok 2621 Set Streaming SVE VL 2272
4349 13:38:26.902281 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4350 13:38:26.902601 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4351 13:38:26.902698 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4352 13:38:26.902791 # ok 2625 Set Streaming SVE VL 2288
4353 13:38:26.902867 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4354 13:38:26.902952 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4355 13:38:26.903234 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4356 13:38:26.903332 # ok 2629 Set Streaming SVE VL 2304
4357 13:38:26.903423 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4358 13:38:26.903510 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4359 13:38:26.903596 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4360 13:38:26.903682 # ok 2633 Set Streaming SVE VL 2320
4361 13:38:26.903969 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4362 13:38:26.904065 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4363 13:38:26.904155 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4364 13:38:26.904233 # ok 2637 Set Streaming SVE VL 2336
4365 13:38:26.904318 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4366 13:38:26.904412 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4367 13:38:26.904666 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4368 13:38:26.904821 # ok 2641 Set Streaming SVE VL 2352
4369 13:38:26.904976 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4370 13:38:26.905077 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4371 13:38:26.905155 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4372 13:38:26.905240 # ok 2645 Set Streaming SVE VL 2368
4373 13:38:26.905326 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4374 13:38:26.905419 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4375 13:38:26.905704 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4376 13:38:26.905815 # ok 2649 Set Streaming SVE VL 2384
4377 13:38:26.905905 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4378 13:38:26.906177 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4379 13:38:26.906290 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4380 13:38:26.906378 # ok 2653 Set Streaming SVE VL 2400
4381 13:38:26.906464 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4382 13:38:26.906754 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4383 13:38:26.906862 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4384 13:38:26.906949 # ok 2657 Set Streaming SVE VL 2416
4385 13:38:26.907035 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4386 13:38:26.907317 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4387 13:38:26.907420 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4388 13:38:26.907521 # ok 2661 Set Streaming SVE VL 2432
4389 13:38:26.907625 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4390 13:38:26.907926 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4391 13:38:26.908047 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4392 13:38:26.908155 # ok 2665 Set Streaming SVE VL 2448
4393 13:38:26.908257 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4394 13:38:26.908558 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4395 13:38:26.908685 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4396 13:38:26.908780 # ok 2669 Set Streaming SVE VL 2464
4397 13:38:26.908898 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4398 13:38:26.909203 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4399 13:38:26.909318 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4400 13:38:26.909445 # ok 2673 Set Streaming SVE VL 2480
4401 13:38:26.909551 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4402 13:38:26.909835 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4403 13:38:26.909964 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4404 13:38:26.910050 # ok 2677 Set Streaming SVE VL 2496
4405 13:38:26.910137 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4406 13:38:26.910419 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4407 13:38:26.910515 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4408 13:38:26.910607 # ok 2681 Set Streaming SVE VL 2512
4409 13:38:26.910914 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4410 13:38:26.911014 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4411 13:38:26.911104 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4412 13:38:26.911198 # ok 2685 Set Streaming SVE VL 2528
4413 13:38:26.911506 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4414 13:38:26.911603 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4415 13:38:26.911697 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4416 13:38:26.911803 # ok 2689 Set Streaming SVE VL 2544
4417 13:38:26.911917 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4418 13:38:26.912018 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4419 13:38:26.912118 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4420 13:38:26.912220 # ok 2693 Set Streaming SVE VL 2560
4421 13:38:26.912330 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4422 13:38:26.912429 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4423 13:38:26.912529 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4424 13:38:26.912628 # ok 2697 Set Streaming SVE VL 2576
4425 13:38:26.912724 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4426 13:38:26.913021 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4427 13:38:26.913114 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4428 13:38:26.913214 # ok 2701 Set Streaming SVE VL 2592
4429 13:38:26.913298 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4430 13:38:26.913599 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4431 13:38:26.913697 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4432 13:38:26.913806 # ok 2705 Set Streaming SVE VL 2608
4433 13:38:26.913941 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4434 13:38:26.914089 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4435 13:38:26.914206 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4436 13:38:26.914345 # ok 2709 Set Streaming SVE VL 2624
4437 13:38:26.914470 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4438 13:38:26.914618 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4439 13:38:26.914747 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4440 13:38:26.914882 # ok 2713 Set Streaming SVE VL 2640
4441 13:38:26.915206 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4442 13:38:26.915307 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4443 13:38:26.915423 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4444 13:38:26.915533 # ok 2717 Set Streaming SVE VL 2656
4445 13:38:26.915658 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4446 13:38:26.915785 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4447 13:38:26.916106 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4448 13:38:26.916206 # ok 2721 Set Streaming SVE VL 2672
4449 13:38:26.916293 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4450 13:38:26.916390 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4451 13:38:26.916465 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4452 13:38:26.916590 # ok 2725 Set Streaming SVE VL 2688
4453 13:38:26.916713 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4454 13:38:26.916819 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4455 13:38:26.918534 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4456 13:38:26.918615 # ok 2729 Set Streaming SVE VL 2704
4457 13:38:26.918693 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4458 13:38:26.918771 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4459 13:38:26.919026 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4460 13:38:26.919097 # ok 2733 Set Streaming SVE VL 2720
4461 13:38:26.919173 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4462 13:38:26.919240 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4463 13:38:26.919316 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4464 13:38:26.919393 # ok 2737 Set Streaming SVE VL 2736
4465 13:38:26.919647 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4466 13:38:26.919718 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4467 13:38:26.919795 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4468 13:38:26.920045 # ok 2741 Set Streaming SVE VL 2752
4469 13:38:26.920115 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4470 13:38:26.920194 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4471 13:38:26.920262 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4472 13:38:26.920338 # ok 2745 Set Streaming SVE VL 2768
4473 13:38:26.920415 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4474 13:38:26.920672 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4475 13:38:26.920747 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4476 13:38:26.920824 # ok 2749 Set Streaming SVE VL 2784
4477 13:38:26.920891 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4478 13:38:26.920967 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4479 13:38:26.921228 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4480 13:38:26.921298 # ok 2753 Set Streaming SVE VL 2800
4481 13:38:26.921376 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4482 13:38:26.921455 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4483 13:38:26.921537 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4484 13:38:26.921783 # ok 2757 Set Streaming SVE VL 2816
4485 13:38:26.922041 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4486 13:38:26.922113 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4487 13:38:26.922189 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4488 13:38:26.922268 # ok 2761 Set Streaming SVE VL 2832
4489 13:38:26.922345 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4490 13:38:26.922596 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4491 13:38:26.922669 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4492 13:38:26.922750 # ok 2765 Set Streaming SVE VL 2848
4493 13:38:26.922827 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4494 13:38:26.923078 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4495 13:38:26.923149 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4496 13:38:26.923226 # ok 2769 Set Streaming SVE VL 2864
4497 13:38:26.923303 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4498 13:38:26.923380 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4499 13:38:26.923481 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4500 13:38:26.923737 # ok 2773 Set Streaming SVE VL 2880
4501 13:38:26.923807 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4502 13:38:26.923884 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4503 13:38:26.924137 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4504 13:38:26.924207 # ok 2777 Set Streaming SVE VL 2896
4505 13:38:26.924282 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4506 13:38:26.924348 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4507 13:38:26.924423 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4508 13:38:26.924676 # ok 2781 Set Streaming SVE VL 2912
4509 13:38:26.924747 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4510 13:38:26.924823 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4511 13:38:26.924899 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4512 13:38:26.924975 # ok 2785 Set Streaming SVE VL 2928
4513 13:38:26.925050 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4514 13:38:26.925319 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4515 13:38:26.925389 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4516 13:38:26.925467 # ok 2789 Set Streaming SVE VL 2944
4517 13:38:26.925544 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4518 13:38:26.925798 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4519 13:38:26.925882 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4520 13:38:26.925959 # ok 2793 Set Streaming SVE VL 2960
4521 13:38:26.926213 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4522 13:38:26.926283 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4523 13:38:26.926361 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4524 13:38:26.926427 # ok 2797 Set Streaming SVE VL 2976
4525 13:38:26.926506 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4526 13:38:26.926596 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4527 13:38:26.926709 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4528 13:38:26.926829 # ok 2801 Set Streaming SVE VL 2992
4529 13:38:26.927126 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4530 13:38:26.927236 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4531 13:38:26.927344 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4532 13:38:26.927465 # ok 2805 Set Streaming SVE VL 3008
4533 13:38:26.927574 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4534 13:38:26.927673 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4535 13:38:26.927984 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4536 13:38:26.928083 # ok 2809 Set Streaming SVE VL 3024
4537 13:38:26.928175 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4538 13:38:26.928267 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4539 13:38:26.928359 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4540 13:38:26.928438 # ok 2813 Set Streaming SVE VL 3040
4541 13:38:26.928711 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4542 13:38:26.928793 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4543 13:38:26.928882 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4544 13:38:26.929031 # ok 2817 Set Streaming SVE VL 3056
4545 13:38:26.929144 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4546 13:38:26.929234 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4547 13:38:26.929338 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4548 13:38:26.929437 # ok 2821 Set Streaming SVE VL 3072
4549 13:38:26.929695 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4550 13:38:26.930017 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4551 13:38:26.930125 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4552 13:38:26.930207 # ok 2825 Set Streaming SVE VL 3088
4553 13:38:26.930298 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4554 13:38:26.930427 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4555 13:38:26.930735 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4556 13:38:26.930837 # ok 2829 Set Streaming SVE VL 3104
4557 13:38:26.930960 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4558 13:38:26.931068 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4559 13:38:26.931177 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4560 13:38:26.931301 # ok 2833 Set Streaming SVE VL 3120
4561 13:38:26.931596 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4562 13:38:26.931685 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4563 13:38:26.931823 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4564 13:38:26.931916 # ok 2837 Set Streaming SVE VL 3136
4565 13:38:26.932050 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4566 13:38:26.932167 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4567 13:38:26.932265 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4568 13:38:26.932369 # ok 2841 Set Streaming SVE VL 3152
4569 13:38:26.932666 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4570 13:38:26.932770 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4571 13:38:26.932881 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4572 13:38:26.932979 # ok 2845 Set Streaming SVE VL 3168
4573 13:38:26.933078 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4574 13:38:26.933402 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4575 13:38:26.933512 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4576 13:38:26.933595 # ok 2849 Set Streaming SVE VL 3184
4577 13:38:26.933889 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4578 13:38:26.933999 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4579 13:38:26.934285 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4580 13:38:26.934382 # ok 2853 Set Streaming SVE VL 3200
4581 13:38:26.934474 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4582 13:38:26.934756 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4583 13:38:26.934865 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4584 13:38:26.934943 # ok 2857 Set Streaming SVE VL 3216
4585 13:38:26.935029 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4586 13:38:26.935313 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4587 13:38:26.935419 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4588 13:38:26.935509 # ok 2861 Set Streaming SVE VL 3232
4589 13:38:26.935602 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4590 13:38:26.935911 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4591 13:38:26.936017 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4592 13:38:26.936106 # ok 2865 Set Streaming SVE VL 3248
4593 13:38:26.936193 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4594 13:38:26.936559 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4595 13:38:26.936659 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4596 13:38:26.936749 # ok 2869 Set Streaming SVE VL 3264
4597 13:38:26.936836 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4598 13:38:26.937131 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4599 13:38:26.937269 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4600 13:38:26.937345 # ok 2873 Set Streaming SVE VL 3280
4601 13:38:26.937431 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4602 13:38:26.937892 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4603 13:38:26.937993 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4604 13:38:26.938082 # ok 2877 Set Streaming SVE VL 3296
4605 13:38:26.943532 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4606 13:38:26.943768 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4607 13:38:26.943839 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4608 13:38:26.943914 # ok 2881 Set Streaming SVE VL 3312
4609 13:38:26.943982 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4610 13:38:26.944259 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4611 13:38:26.944340 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4612 13:38:26.944414 # ok 2885 Set Streaming SVE VL 3328
4613 13:38:26.944717 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4614 13:38:26.944881 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4615 13:38:26.944997 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4616 13:38:26.945105 # ok 2889 Set Streaming SVE VL 3344
4617 13:38:26.945405 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4618 13:38:26.945503 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4619 13:38:26.945607 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4620 13:38:26.956320 # ok 2893 Set Streaming SVE VL 3360
4621 13:38:26.956495 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4622 13:38:26.956587 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4623 13:38:26.956675 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4624 13:38:26.956761 # ok 2897 Set Streaming SVE VL 3376
4625 13:38:26.957011 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4626 13:38:26.957076 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4627 13:38:26.957318 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4628 13:38:26.957565 # ok 2901 Set Streaming SVE VL 3392
4629 13:38:26.957628 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4630 13:38:26.962914 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4631 13:38:26.963281 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4632 13:38:26.963361 # ok 2905 Set Streaming SVE VL 3408
4633 13:38:26.963435 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4634 13:38:26.963520 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4635 13:38:26.963607 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4636 13:38:26.963694 # ok 2909 Set Streaming SVE VL 3424
4637 13:38:26.963777 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4638 13:38:26.964026 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4639 13:38:26.964107 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4640 13:38:26.964199 # ok 2913 Set Streaming SVE VL 3440
4641 13:38:26.964445 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4642 13:38:26.964686 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4643 13:38:26.964761 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4644 13:38:26.964844 # ok 2917 Set Streaming SVE VL 3456
4645 13:38:26.965089 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4646 13:38:26.965335 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4647 13:38:26.965581 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4648 13:38:26.965658 # ok 2921 Set Streaming SVE VL 3472
4649 13:38:26.970297 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4650 13:38:26.970696 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4651 13:38:26.970798 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4652 13:38:26.970860 # ok 2925 Set Streaming SVE VL 3488
4653 13:38:26.970930 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4654 13:38:26.971001 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4655 13:38:26.971249 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4656 13:38:26.971323 # ok 2929 Set Streaming SVE VL 3504
4657 13:38:26.971393 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4658 13:38:26.971636 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4659 13:38:26.971731 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4660 13:38:26.971811 # ok 2933 Set Streaming SVE VL 3520
4661 13:38:26.972053 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4662 13:38:26.972312 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4663 13:38:26.972401 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4664 13:38:26.972490 # ok 2937 Set Streaming SVE VL 3536
4665 13:38:26.972578 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4666 13:38:26.972859 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4667 13:38:26.973002 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4668 13:38:26.973102 # ok 2941 Set Streaming SVE VL 3552
4669 13:38:26.973226 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4670 13:38:26.973349 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4671 13:38:26.973480 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4672 13:38:26.973693 # ok 2945 Set Streaming SVE VL 3568
4673 13:38:26.976356 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4674 13:38:26.976733 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4675 13:38:26.976816 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4676 13:38:26.976897 # ok 2949 Set Streaming SVE VL 3584
4677 13:38:26.976989 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4678 13:38:26.977087 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4679 13:38:26.977183 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4680 13:38:26.977269 # ok 2953 Set Streaming SVE VL 3600
4681 13:38:26.977543 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4682 13:38:26.977656 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4683 13:38:26.978313 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4684 13:38:26.978605 # ok 2957 Set Streaming SVE VL 3616
4685 13:38:26.978703 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4686 13:38:26.978793 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4687 13:38:26.978910 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4688 13:38:26.979018 # ok 2961 Set Streaming SVE VL 3632
4689 13:38:26.979122 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4690 13:38:26.979229 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4691 13:38:26.979519 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4692 13:38:26.979620 # ok 2965 Set Streaming SVE VL 3648
4693 13:38:26.979719 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4694 13:38:26.979813 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4695 13:38:26.979926 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4696 13:38:26.980021 # ok 2969 Set Streaming SVE VL 3664
4697 13:38:26.980297 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4698 13:38:26.980394 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4699 13:38:26.980486 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4700 13:38:26.980577 # ok 2973 Set Streaming SVE VL 3680
4701 13:38:26.980668 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4702 13:38:26.980968 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4703 13:38:26.981067 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4704 13:38:26.981165 # ok 2977 Set Streaming SVE VL 3696
4705 13:38:26.981238 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4706 13:38:26.981318 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4707 13:38:26.981590 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4708 13:38:26.981686 # ok 2981 Set Streaming SVE VL 3712
4709 13:38:26.984145 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4710 13:38:26.984506 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4711 13:38:26.984600 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4712 13:38:26.984696 # ok 2985 Set Streaming SVE VL 3728
4713 13:38:26.984800 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4714 13:38:26.984876 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4715 13:38:26.985134 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4716 13:38:26.985211 # ok 2989 Set Streaming SVE VL 3744
4717 13:38:26.985498 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4718 13:38:26.985604 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4719 13:38:26.988925 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4720 13:38:26.989311 # ok 2993 Set Streaming SVE VL 3760
4721 13:38:26.989421 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4722 13:38:26.989522 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4723 13:38:26.989679 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4724 13:38:26.989771 # ok 2997 Set Streaming SVE VL 3776
4725 13:38:26.989859 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4726 13:38:26.990581 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4727 13:38:26.990691 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4728 13:38:26.990797 # ok 3001 Set Streaming SVE VL 3792
4729 13:38:26.991116 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4730 13:38:26.991219 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4731 13:38:26.991316 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4732 13:38:26.991410 # ok 3005 Set Streaming SVE VL 3808
4733 13:38:26.991687 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4734 13:38:26.991783 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4735 13:38:26.991882 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4736 13:38:26.991980 # ok 3009 Set Streaming SVE VL 3824
4737 13:38:26.992267 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4738 13:38:26.992361 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4739 13:38:26.992632 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4740 13:38:26.992714 # ok 3013 Set Streaming SVE VL 3840
4741 13:38:26.992799 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4742 13:38:26.992891 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4743 13:38:26.993179 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4744 13:38:26.993258 # ok 3017 Set Streaming SVE VL 3856
4745 13:38:26.993343 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4746 13:38:26.993610 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4747 13:38:26.993712 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4748 13:38:26.998522 # ok 3021 Set Streaming SVE VL 3872
4749 13:38:26.998973 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4750 13:38:26.999075 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4751 13:38:26.999160 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4752 13:38:26.999237 # ok 3025 Set Streaming SVE VL 3888
4753 13:38:26.999327 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4754 13:38:27.000312 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4755 13:38:27.000509 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4756 13:38:27.000680 # ok 3029 Set Streaming SVE VL 3904
4757 13:38:27.000862 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4758 13:38:27.000985 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4759 13:38:27.001111 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4760 13:38:27.001231 # ok 3033 Set Streaming SVE VL 3920
4761 13:38:27.001376 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4762 13:38:27.001480 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4763 13:38:27.001587 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4764 13:38:27.001767 # ok 3037 Set Streaming SVE VL 3936
4765 13:38:27.001870 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4766 13:38:27.010458 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4767 13:38:27.010908 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4768 13:38:27.011019 # ok 3041 Set Streaming SVE VL 3952
4769 13:38:27.011114 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4770 13:38:27.011206 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4771 13:38:27.011314 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4772 13:38:27.011404 # ok 3045 Set Streaming SVE VL 3968
4773 13:38:27.011501 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4774 13:38:27.011597 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4775 13:38:27.011693 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4776 13:38:27.011781 # ok 3049 Set Streaming SVE VL 3984
4777 13:38:27.012108 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4778 13:38:27.012250 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4779 13:38:27.012394 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4780 13:38:27.012533 # ok 3053 Set Streaming SVE VL 4000
4781 13:38:27.012683 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4782 13:38:27.012808 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4783 13:38:27.012944 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4784 13:38:27.013061 # ok 3057 Set Streaming SVE VL 4016
4785 13:38:27.013205 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4786 13:38:27.013330 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4787 13:38:27.013473 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4788 13:38:27.013606 # ok 3061 Set Streaming SVE VL 4032
4789 13:38:27.013784 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4790 13:38:27.013904 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4791 13:38:27.017405 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4792 13:38:27.017830 # ok 3065 Set Streaming SVE VL 4048
4793 13:38:27.017990 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4794 13:38:27.018338 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4795 13:38:27.018653 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4796 13:38:27.018759 # ok 3069 Set Streaming SVE VL 4064
4797 13:38:27.018867 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4798 13:38:27.019259 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4799 13:38:27.019365 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4800 13:38:27.019457 # ok 3073 Set Streaming SVE VL 4080
4801 13:38:27.019547 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4802 13:38:27.019652 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4803 13:38:27.019743 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4804 13:38:27.019833 # ok 3077 Set Streaming SVE VL 4096
4805 13:38:27.019926 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4806 13:38:27.020032 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4807 13:38:27.020123 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4808 13:38:27.020225 # ok 3081 Set Streaming SVE VL 4112
4809 13:38:27.020316 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4810 13:38:27.020418 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4811 13:38:27.020527 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4812 13:38:27.020632 # ok 3085 Set Streaming SVE VL 4128
4813 13:38:27.020990 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4814 13:38:27.021175 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4815 13:38:27.021345 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4816 13:38:27.021548 # ok 3089 Set Streaming SVE VL 4144
4817 13:38:27.021770 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4818 13:38:27.021921 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4819 13:38:27.022040 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4820 13:38:27.022155 # ok 3093 Set Streaming SVE VL 4160
4821 13:38:27.022296 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4822 13:38:27.022417 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4823 13:38:27.023966 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4824 13:38:27.024309 # ok 3097 Set Streaming SVE VL 4176
4825 13:38:27.024420 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4826 13:38:27.024516 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4827 13:38:27.024814 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4828 13:38:27.024926 # ok 3101 Set Streaming SVE VL 4192
4829 13:38:27.025021 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4830 13:38:27.025131 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4831 13:38:27.025228 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4832 13:38:27.025321 # ok 3105 Set Streaming SVE VL 4208
4833 13:38:27.025415 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4834 13:38:27.025525 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4835 13:38:27.025620 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4836 13:38:27.025740 # ok 3109 Set Streaming SVE VL 4224
4837 13:38:27.025850 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4838 13:38:27.025946 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4839 13:38:27.028862 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4840 13:38:27.029005 # ok 3113 Set Streaming SVE VL 4240
4841 13:38:27.029129 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4842 13:38:27.029269 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4843 13:38:27.029386 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4844 13:38:27.029523 # ok 3117 Set Streaming SVE VL 4256
4845 13:38:27.029631 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4846 13:38:27.029770 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4847 13:38:27.029863 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4848 13:38:27.030263 # ok 3121 Set Streaming SVE VL 4272
4849 13:38:27.030578 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4850 13:38:27.030678 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4851 13:38:27.030796 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4852 13:38:27.030885 # ok 3125 Set Streaming SVE VL 4288
4853 13:38:27.030971 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4854 13:38:27.031054 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4855 13:38:27.031146 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4856 13:38:27.031234 # ok 3129 Set Streaming SVE VL 4304
4857 13:38:27.031521 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4858 13:38:27.031655 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4859 13:38:27.031783 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4860 13:38:27.031881 # ok 3133 Set Streaming SVE VL 4320
4861 13:38:27.031990 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4862 13:38:27.032085 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4863 13:38:27.032194 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4864 13:38:27.032289 # ok 3137 Set Streaming SVE VL 4336
4865 13:38:27.032397 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4866 13:38:27.032508 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4867 13:38:27.032812 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4868 13:38:27.032927 # ok 3141 Set Streaming SVE VL 4352
4869 13:38:27.033065 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4870 13:38:27.033184 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4871 13:38:27.033299 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4872 13:38:27.033417 # ok 3145 Set Streaming SVE VL 4368
4873 13:38:27.033552 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4874 13:38:27.033688 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4875 13:38:27.033813 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4876 13:38:27.033905 # ok 3149 Set Streaming SVE VL 4384
4877 13:38:27.038234 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4878 13:38:27.038523 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4879 13:38:27.038624 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4880 13:38:27.038750 # ok 3153 Set Streaming SVE VL 4400
4881 13:38:27.038859 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4882 13:38:27.038948 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4883 13:38:27.039040 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4884 13:38:27.039133 # ok 3157 Set Streaming SVE VL 4416
4885 13:38:27.039226 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4886 13:38:27.039525 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4887 13:38:27.039635 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4888 13:38:27.039920 # ok 3161 Set Streaming SVE VL 4432
4889 13:38:27.040012 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4890 13:38:27.040129 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4891 13:38:27.040215 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4892 13:38:27.040511 # ok 3165 Set Streaming SVE VL 4448
4893 13:38:27.040612 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4894 13:38:27.040894 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4895 13:38:27.040990 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4896 13:38:27.041074 # ok 3169 Set Streaming SVE VL 4464
4897 13:38:27.041153 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4898 13:38:27.041254 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4899 13:38:27.041344 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4900 13:38:27.041424 # ok 3173 Set Streaming SVE VL 4480
4901 13:38:27.041711 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4902 13:38:27.058572 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4903 13:38:27.058856 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4904 13:38:27.059454 # ok 3177 Set Streaming SVE VL 4496
4905 13:38:27.059554 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4906 13:38:27.059659 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4907 13:38:27.059780 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4908 13:38:27.059888 # ok 3181 Set Streaming SVE VL 4512
4909 13:38:27.060014 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4910 13:38:27.060113 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4911 13:38:27.060398 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4912 13:38:27.060493 # ok 3185 Set Streaming SVE VL 4528
4913 13:38:27.060586 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4914 13:38:27.060670 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4915 13:38:27.060765 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4916 13:38:27.060850 # ok 3189 Set Streaming SVE VL 4544
4917 13:38:27.061104 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4918 13:38:27.061180 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4919 13:38:27.061272 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4920 13:38:27.061541 # ok 3193 Set Streaming SVE VL 4560
4921 13:38:27.061625 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4922 13:38:27.061739 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4923 13:38:27.074329 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4924 13:38:27.074635 # ok 3197 Set Streaming SVE VL 4576
4925 13:38:27.074727 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4926 13:38:27.074819 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4927 13:38:27.074911 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4928 13:38:27.075021 # ok 3201 Set Streaming SVE VL 4592
4929 13:38:27.075115 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4930 13:38:27.075228 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4931 13:38:27.075504 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4932 13:38:27.075601 # ok 3205 Set Streaming SVE VL 4608
4933 13:38:27.075694 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4934 13:38:27.075779 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4935 13:38:27.075892 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4936 13:38:27.075997 # ok 3209 Set Streaming SVE VL 4624
4937 13:38:27.076083 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4938 13:38:27.076179 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4939 13:38:27.076420 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4940 13:38:27.076517 # ok 3213 Set Streaming SVE VL 4640
4941 13:38:27.076611 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4942 13:38:27.076903 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4943 13:38:27.076999 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4944 13:38:27.077076 # ok 3217 Set Streaming SVE VL 4656
4945 13:38:27.077179 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4946 13:38:27.077447 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4947 13:38:27.077587 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4948 13:38:27.077686 # ok 3221 Set Streaming SVE VL 4672
4949 13:38:27.077793 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4950 13:38:27.086596 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4951 13:38:27.086942 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4952 13:38:27.087146 # ok 3225 Set Streaming SVE VL 4688
4953 13:38:27.087349 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4954 13:38:27.087573 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4955 13:38:27.087733 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4956 13:38:27.087927 # ok 3229 Set Streaming SVE VL 4704
4957 13:38:27.088102 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4958 13:38:27.088271 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4959 13:38:27.088435 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4960 13:38:27.088601 # ok 3233 Set Streaming SVE VL 4720
4961 13:38:27.088807 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4962 13:38:27.089018 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4963 13:38:27.089198 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4964 13:38:27.089397 # ok 3237 Set Streaming SVE VL 4736
4965 13:38:27.089598 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4966 13:38:27.089837 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4967 13:38:27.089982 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4968 13:38:27.090105 # ok 3241 Set Streaming SVE VL 4752
4969 13:38:27.090221 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4970 13:38:27.090336 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4971 13:38:27.090450 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4972 13:38:27.090564 # ok 3245 Set Streaming SVE VL 4768
4973 13:38:27.090704 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4974 13:38:27.090837 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4975 13:38:27.091026 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4976 13:38:27.091186 # ok 3249 Set Streaming SVE VL 4784
4977 13:38:27.091395 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4978 13:38:27.091565 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4979 13:38:27.091717 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4980 13:38:27.091903 # ok 3253 Set Streaming SVE VL 4800
4981 13:38:27.092071 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4982 13:38:27.092236 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4983 13:38:27.092394 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4984 13:38:27.092531 # ok 3257 Set Streaming SVE VL 4816
4985 13:38:27.092712 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4986 13:38:27.093088 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4987 13:38:27.093188 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4988 13:38:27.093274 # ok 3261 Set Streaming SVE VL 4832
4989 13:38:27.093355 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4990 13:38:27.093436 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4991 13:38:27.093517 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4992 13:38:27.093595 # ok 3265 Set Streaming SVE VL 4848
4993 13:38:27.093699 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4994 13:38:27.093785 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4995 13:38:27.093871 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
4996 13:38:27.093955 # ok 3269 Set Streaming SVE VL 4864
4997 13:38:27.094021 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
4998 13:38:27.094096 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
4999 13:38:27.099597 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5000 13:38:27.099933 # ok 3273 Set Streaming SVE VL 4880
5001 13:38:27.100029 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5002 13:38:27.100114 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5003 13:38:27.100230 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5004 13:38:27.100304 # ok 3277 Set Streaming SVE VL 4896
5005 13:38:27.100394 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5006 13:38:27.100499 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5007 13:38:27.100618 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5008 13:38:27.100723 # ok 3281 Set Streaming SVE VL 4912
5009 13:38:27.100991 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5010 13:38:27.101108 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5011 13:38:27.101182 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5012 13:38:27.101273 # ok 3285 Set Streaming SVE VL 4928
5013 13:38:27.101373 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5014 13:38:27.101493 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5015 13:38:27.101596 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5016 13:38:27.101704 # ok 3289 Set Streaming SVE VL 4944
5017 13:38:27.106863 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5018 13:38:27.107187 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5019 13:38:27.107402 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5020 13:38:27.107586 # ok 3293 Set Streaming SVE VL 4960
5021 13:38:27.107818 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5022 13:38:27.107992 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5023 13:38:27.108159 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5024 13:38:27.108315 # ok 3297 Set Streaming SVE VL 4976
5025 13:38:27.108509 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5026 13:38:27.108760 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5027 13:38:27.108965 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5028 13:38:27.109174 # ok 3301 Set Streaming SVE VL 4992
5029 13:38:27.109369 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5030 13:38:27.109541 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5031 13:38:27.109723 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5032 13:38:27.109886 # ok 3305 Set Streaming SVE VL 5008
5033 13:38:27.110079 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5034 13:38:27.110231 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5035 13:38:27.110353 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5036 13:38:27.110472 # ok 3309 Set Streaming SVE VL 5024
5037 13:38:27.110588 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5038 13:38:27.110704 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5039 13:38:27.110821 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5040 13:38:27.110938 # ok 3313 Set Streaming SVE VL 5040
5041 13:38:27.111055 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5042 13:38:27.111172 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5043 13:38:27.114547 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5044 13:38:27.114989 # ok 3317 Set Streaming SVE VL 5056
5045 13:38:27.115193 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5046 13:38:27.115364 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5047 13:38:27.115536 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5048 13:38:27.115713 # ok 3321 Set Streaming SVE VL 5072
5049 13:38:27.115834 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5050 13:38:27.115949 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5051 13:38:27.116062 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5052 13:38:27.116176 # ok 3325 Set Streaming SVE VL 5088
5053 13:38:27.116301 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5054 13:38:27.116484 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5055 13:38:27.116674 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5056 13:38:27.117185 # ok 3329 Set Streaming SVE VL 5104
5057 13:38:27.117388 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5058 13:38:27.117609 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5059 13:38:27.117819 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5060 13:38:27.117992 # ok 3333 Set Streaming SVE VL 5120
5061 13:38:27.118148 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5062 13:38:27.118272 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5063 13:38:27.118389 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5064 13:38:27.118504 # ok 3337 Set Streaming SVE VL 5136
5065 13:38:27.118618 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5066 13:38:27.120309 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5067 13:38:27.120702 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5068 13:38:27.120888 # ok 3341 Set Streaming SVE VL 5152
5069 13:38:27.121098 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5070 13:38:27.121282 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5071 13:38:27.121457 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5072 13:38:27.121607 # ok 3345 Set Streaming SVE VL 5168
5073 13:38:27.121824 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5074 13:38:27.122015 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5075 13:38:27.122152 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5076 13:38:27.122269 # ok 3349 Set Streaming SVE VL 5184
5077 13:38:27.122383 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5078 13:38:27.122524 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5079 13:38:27.124418 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5080 13:38:27.124732 # ok 3353 Set Streaming SVE VL 5200
5081 13:38:27.124869 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5082 13:38:27.124970 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5083 13:38:27.125084 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5084 13:38:27.125161 # ok 3357 Set Streaming SVE VL 5216
5085 13:38:27.125263 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5086 13:38:27.125385 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5087 13:38:27.125480 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5088 13:38:27.125563 # ok 3361 Set Streaming SVE VL 5232
5089 13:38:27.125654 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5090 13:38:27.125758 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5091 13:38:27.125860 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5092 13:38:27.128933 # ok 3365 Set Streaming SVE VL 5248
5093 13:38:27.129381 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5094 13:38:27.129577 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5095 13:38:27.129756 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5096 13:38:27.129909 # ok 3369 Set Streaming SVE VL 5264
5097 13:38:27.130053 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5098 13:38:27.130170 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5099 13:38:27.130284 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5100 13:38:27.130399 # ok 3373 Set Streaming SVE VL 5280
5101 13:38:27.130584 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5102 13:38:27.130744 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5103 13:38:27.130937 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5104 13:38:27.131133 # ok 3377 Set Streaming SVE VL 5296
5105 13:38:27.131324 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5106 13:38:27.131491 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5107 13:38:27.131656 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5108 13:38:27.131845 # ok 3381 Set Streaming SVE VL 5312
5109 13:38:27.132012 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5110 13:38:27.132179 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5111 13:38:27.132374 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5112 13:38:27.132541 # ok 3385 Set Streaming SVE VL 5328
5113 13:38:27.132701 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5114 13:38:27.132863 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5115 13:38:27.133058 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5116 13:38:27.133228 # ok 3389 Set Streaming SVE VL 5344
5117 13:38:27.133392 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5118 13:38:27.133552 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5119 13:38:27.134283 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5120 13:38:27.134387 # ok 3393 Set Streaming SVE VL 5360
5121 13:38:27.134501 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5122 13:38:27.134595 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5123 13:38:27.134687 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5124 13:38:27.134777 # ok 3397 Set Streaming SVE VL 5376
5125 13:38:27.134865 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5126 13:38:27.134952 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5127 13:38:27.136667 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5128 13:38:27.137090 # ok 3401 Set Streaming SVE VL 5392
5129 13:38:27.137290 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5130 13:38:27.137467 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5131 13:38:27.137681 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5132 13:38:27.137876 # ok 3405 Set Streaming SVE VL 5408
5133 13:38:27.138047 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5134 13:38:27.138185 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5135 13:38:27.138304 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5136 13:38:27.138448 # ok 3409 Set Streaming SVE VL 5424
5137 13:38:27.142358 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5138 13:38:27.142780 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5139 13:38:27.142884 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5140 13:38:27.142970 # ok 3413 Set Streaming SVE VL 5440
5141 13:38:27.143049 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5142 13:38:27.143149 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5143 13:38:27.143230 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5144 13:38:27.143308 # ok 3417 Set Streaming SVE VL 5456
5145 13:38:27.143396 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5146 13:38:27.143488 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5147 13:38:27.143777 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5148 13:38:27.143879 # ok 3421 Set Streaming SVE VL 5472
5149 13:38:27.143971 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5150 13:38:27.144067 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5151 13:38:27.144166 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5152 13:38:27.144264 # ok 3425 Set Streaming SVE VL 5488
5153 13:38:27.144533 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5154 13:38:27.144628 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5155 13:38:27.144721 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5156 13:38:27.145006 # ok 3429 Set Streaming SVE VL 5504
5157 13:38:27.145102 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5158 13:38:27.145192 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5159 13:38:27.145284 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5160 13:38:27.145378 # ok 3433 Set Streaming SVE VL 5520
5161 13:38:27.145661 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5162 13:38:27.145765 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5163 13:38:27.145849 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5164 13:38:27.150877 # ok 3437 Set Streaming SVE VL 5536
5165 13:38:27.151183 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5166 13:38:27.151291 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5167 13:38:27.151392 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5168 13:38:27.151491 # ok 3441 Set Streaming SVE VL 5552
5169 13:38:27.151590 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5170 13:38:27.151688 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5171 13:38:27.151985 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5172 13:38:27.152082 # ok 3445 Set Streaming SVE VL 5568
5173 13:38:27.152176 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5174 13:38:27.152255 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5175 13:38:27.152349 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5176 13:38:27.152444 # ok 3449 Set Streaming SVE VL 5584
5177 13:38:27.152741 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5178 13:38:27.152835 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5179 13:38:27.152931 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5180 13:38:27.153013 # ok 3453 Set Streaming SVE VL 5600
5181 13:38:27.153106 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5182 13:38:27.153212 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5183 13:38:27.153511 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5184 13:38:27.153595 # ok 3457 Set Streaming SVE VL 5616
5185 13:38:27.153709 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5186 13:38:27.153791 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5187 13:38:27.153885 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5188 13:38:27.158483 # ok 3461 Set Streaming SVE VL 5632
5189 13:38:27.158570 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5190 13:38:27.158666 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5191 13:38:27.158763 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5192 13:38:27.159045 # ok 3465 Set Streaming SVE VL 5648
5193 13:38:27.159138 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5194 13:38:27.159283 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5195 13:38:27.159427 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5196 13:38:27.159539 # ok 3469 Set Streaming SVE VL 5664
5197 13:38:27.159683 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5198 13:38:27.159804 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5199 13:38:27.159947 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5200 13:38:27.160073 # ok 3473 Set Streaming SVE VL 5680
5201 13:38:27.160197 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5202 13:38:27.160290 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5203 13:38:27.160847 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5204 13:38:27.161315 # ok 3477 Set Streaming SVE VL 5696
5205 13:38:27.161534 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5206 13:38:27.161734 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5207 13:38:27.161943 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5208 13:38:27.162087 # ok 3481 Set Streaming SVE VL 5712
5209 13:38:27.162222 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5210 13:38:27.162358 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5211 13:38:27.162487 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5212 13:38:27.170302 # ok 3485 Set Streaming SVE VL 5728
5213 13:38:27.170784 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5214 13:38:27.171008 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5215 13:38:27.171197 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5216 13:38:27.171378 # ok 3489 Set Streaming SVE VL 5744
5217 13:38:27.171595 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5218 13:38:27.171779 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5219 13:38:27.171961 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5220 13:38:27.172139 # ok 3493 Set Streaming SVE VL 5760
5221 13:38:27.172318 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5222 13:38:27.172497 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5223 13:38:27.172713 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5224 13:38:27.172895 # ok 3497 Set Streaming SVE VL 5776
5225 13:38:27.173069 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5226 13:38:27.173221 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5227 13:38:27.173395 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5228 13:38:27.173561 # ok 3501 Set Streaming SVE VL 5792
5229 13:38:27.173729 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5230 13:38:27.173890 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5231 13:38:27.174053 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5232 13:38:27.174191 # ok 3505 Set Streaming SVE VL 5808
5233 13:38:27.174321 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5234 13:38:27.174451 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5235 13:38:27.174581 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5236 13:38:27.174712 # ok 3509 Set Streaming SVE VL 5824
5237 13:38:27.174842 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5238 13:38:27.174973 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5239 13:38:27.175103 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5240 13:38:27.175231 # ok 3513 Set Streaming SVE VL 5840
5241 13:38:27.182547 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5242 13:38:27.182714 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5243 13:38:27.182860 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5244 13:38:27.182968 # ok 3517 Set Streaming SVE VL 5856
5245 13:38:27.183089 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5246 13:38:27.183219 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5247 13:38:27.183362 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5248 13:38:27.183544 # ok 3521 Set Streaming SVE VL 5872
5249 13:38:27.183677 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5250 13:38:27.183810 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5251 13:38:27.183951 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5252 13:38:27.184081 # ok 3525 Set Streaming SVE VL 5888
5253 13:38:27.184199 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5254 13:38:27.184318 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5255 13:38:27.184411 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5256 13:38:27.184547 # ok 3529 Set Streaming SVE VL 5904
5257 13:38:27.184668 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5258 13:38:27.184807 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5259 13:38:27.184930 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5260 13:38:27.185058 # ok 3533 Set Streaming SVE VL 5920
5261 13:38:27.185196 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5262 13:38:27.185297 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5263 13:38:27.185431 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5264 13:38:27.185552 # ok 3537 Set Streaming SVE VL 5936
5265 13:38:27.185692 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5266 13:38:27.185924 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5267 13:38:27.186081 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5268 13:38:27.186192 # ok 3541 Set Streaming SVE VL 5952
5269 13:38:27.198778 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5270 13:38:27.199020 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5271 13:38:27.199252 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5272 13:38:27.199432 # ok 3545 Set Streaming SVE VL 5968
5273 13:38:27.199613 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5274 13:38:27.199804 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5275 13:38:27.200037 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5276 13:38:27.200250 # ok 3549 Set Streaming SVE VL 5984
5277 13:38:27.200451 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5278 13:38:27.200671 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5279 13:38:27.200870 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5280 13:38:27.201060 # ok 3553 Set Streaming SVE VL 6000
5281 13:38:27.201277 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5282 13:38:27.201481 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5283 13:38:27.201715 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5284 13:38:27.201950 # ok 3557 Set Streaming SVE VL 6016
5285 13:38:27.202142 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5286 13:38:27.202298 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5287 13:38:27.202430 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5288 13:38:27.202559 # ok 3561 Set Streaming SVE VL 6032
5289 13:38:27.202687 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5290 13:38:27.202813 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5291 13:38:27.202976 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5292 13:38:27.203114 # ok 3565 Set Streaming SVE VL 6048
5293 13:38:27.203244 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5294 13:38:27.203374 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5295 13:38:27.203503 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5296 13:38:27.206721 # ok 3569 Set Streaming SVE VL 6064
5297 13:38:27.206939 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5298 13:38:27.207205 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5299 13:38:27.207433 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5300 13:38:27.207651 # ok 3573 Set Streaming SVE VL 6080
5301 13:38:27.207867 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5302 13:38:27.208127 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5303 13:38:27.208329 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5304 13:38:27.208509 # ok 3577 Set Streaming SVE VL 6096
5305 13:38:27.208670 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5306 13:38:27.208833 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5307 13:38:27.209007 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5308 13:38:27.209181 # ok 3581 Set Streaming SVE VL 6112
5309 13:38:27.209361 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5310 13:38:27.209539 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5311 13:38:27.209794 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5312 13:38:27.210028 # ok 3585 Set Streaming SVE VL 6128
5313 13:38:27.210236 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5314 13:38:27.210429 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5315 13:38:27.210590 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5316 13:38:27.210747 # ok 3589 Set Streaming SVE VL 6144
5317 13:38:27.210904 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5318 13:38:27.211062 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5319 13:38:27.211219 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5320 13:38:27.211377 # ok 3593 Set Streaming SVE VL 6160
5321 13:38:27.211535 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5322 13:38:27.211691 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5323 13:38:27.211848 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5324 13:38:27.212007 # ok 3597 Set Streaming SVE VL 6176
5325 13:38:27.212203 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5326 13:38:27.212357 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5327 13:38:27.214951 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5328 13:38:27.215696 # ok 3601 Set Streaming SVE VL 6192
5329 13:38:27.215840 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5330 13:38:27.215963 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5331 13:38:27.216104 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5332 13:38:27.216229 # ok 3605 Set Streaming SVE VL 6208
5333 13:38:27.216350 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5334 13:38:27.216469 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5335 13:38:27.216612 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5336 13:38:27.216737 # ok 3609 Set Streaming SVE VL 6224
5337 13:38:27.216856 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5338 13:38:27.216968 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5339 13:38:27.217086 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5340 13:38:27.217200 # ok 3613 Set Streaming SVE VL 6240
5341 13:38:27.217340 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5342 13:38:27.217451 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5343 13:38:27.217562 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5344 13:38:27.217671 # ok 3617 Set Streaming SVE VL 6256
5345 13:38:27.217778 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5346 13:38:27.217872 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5347 13:38:27.217964 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5348 13:38:27.218078 # ok 3621 Set Streaming SVE VL 6272
5349 13:38:27.218174 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5350 13:38:27.218266 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5351 13:38:27.218359 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5352 13:38:27.218450 # ok 3625 Set Streaming SVE VL 6288
5353 13:38:27.226887 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5354 13:38:27.227367 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5355 13:38:27.227581 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5356 13:38:27.227821 # ok 3629 Set Streaming SVE VL 6304
5357 13:38:27.228016 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5358 13:38:27.228269 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5359 13:38:27.228444 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5360 13:38:27.228634 # ok 3633 Set Streaming SVE VL 6320
5361 13:38:27.228873 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5362 13:38:27.229078 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5363 13:38:27.229305 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5364 13:38:27.229596 # ok 3637 Set Streaming SVE VL 6336
5365 13:38:27.229828 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5366 13:38:27.230059 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5367 13:38:27.230224 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5368 13:38:27.230358 # ok 3641 Set Streaming SVE VL 6352
5369 13:38:27.230488 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5370 13:38:27.230619 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5371 13:38:27.230801 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5372 13:38:27.230948 # ok 3645 Set Streaming SVE VL 6368
5373 13:38:27.231077 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5374 13:38:27.231236 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5375 13:38:27.231376 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5376 13:38:27.232960 # ok 3649 Set Streaming SVE VL 6384
5377 13:38:27.233513 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5378 13:38:27.233752 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5379 13:38:27.233997 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5380 13:38:27.234176 # ok 3653 Set Streaming SVE VL 6400
5381 13:38:27.234341 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5382 13:38:27.234478 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5383 13:38:27.234611 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5384 13:38:27.234741 # ok 3657 Set Streaming SVE VL 6416
5385 13:38:27.245552 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5386 13:38:27.246033 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5387 13:38:27.246206 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5388 13:38:27.246343 # ok 3661 Set Streaming SVE VL 6432
5389 13:38:27.255720 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5390 13:38:27.256192 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5391 13:38:27.256334 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5392 13:38:27.256458 # ok 3665 Set Streaming SVE VL 6448
5393 13:38:27.256599 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5394 13:38:27.256749 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5395 13:38:27.256905 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5396 13:38:27.257085 # ok 3669 Set Streaming SVE VL 6464
5397 13:38:27.257233 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5398 13:38:27.257366 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5399 13:38:27.257490 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5400 13:38:27.257637 # ok 3673 Set Streaming SVE VL 6480
5401 13:38:27.257790 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5402 13:38:27.257943 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5403 13:38:27.258149 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5404 13:38:27.258297 # ok 3677 Set Streaming SVE VL 6496
5405 13:38:27.258428 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5406 13:38:27.258538 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5407 13:38:27.262474 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5408 13:38:27.262930 # ok 3681 Set Streaming SVE VL 6512
5409 13:38:27.263088 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5410 13:38:27.263262 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5411 13:38:27.263436 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5412 13:38:27.263581 # ok 3685 Set Streaming SVE VL 6528
5413 13:38:27.263731 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5414 13:38:27.263886 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5415 13:38:27.264067 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5416 13:38:27.264206 # ok 3689 Set Streaming SVE VL 6544
5417 13:38:27.264328 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5418 13:38:27.264442 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5419 13:38:27.264562 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5420 13:38:27.264709 # ok 3693 Set Streaming SVE VL 6560
5421 13:38:27.264819 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5422 13:38:27.264927 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5423 13:38:27.265045 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5424 13:38:27.265157 # ok 3697 Set Streaming SVE VL 6576
5425 13:38:27.265295 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5426 13:38:27.265400 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5427 13:38:27.265492 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5428 13:38:27.265584 # ok 3701 Set Streaming SVE VL 6592
5429 13:38:27.265703 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5430 13:38:27.265827 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5431 13:38:27.265984 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5432 13:38:27.266116 # ok 3705 Set Streaming SVE VL 6608
5433 13:38:27.266228 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5434 13:38:27.266337 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5435 13:38:27.266429 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5436 13:38:27.266517 # ok 3709 Set Streaming SVE VL 6624
5437 13:38:27.270014 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5438 13:38:27.270552 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5439 13:38:27.270748 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5440 13:38:27.270902 # ok 3713 Set Streaming SVE VL 6640
5441 13:38:27.271030 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5442 13:38:27.271165 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5443 13:38:27.271316 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5444 13:38:27.271442 # ok 3717 Set Streaming SVE VL 6656
5445 13:38:27.271554 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5446 13:38:27.271697 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5447 13:38:27.271862 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5448 13:38:27.272051 # ok 3721 Set Streaming SVE VL 6672
5449 13:38:27.272190 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5450 13:38:27.272343 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5451 13:38:27.272484 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5452 13:38:27.272613 # ok 3725 Set Streaming SVE VL 6688
5453 13:38:27.272726 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5454 13:38:27.272819 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5455 13:38:27.272923 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5456 13:38:27.273040 # ok 3729 Set Streaming SVE VL 6704
5457 13:38:27.273149 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5458 13:38:27.273277 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5459 13:38:27.273404 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5460 13:38:27.273506 # ok 3733 Set Streaming SVE VL 6720
5461 13:38:27.273629 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5462 13:38:27.273773 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5463 13:38:27.273910 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5464 13:38:27.274051 # ok 3737 Set Streaming SVE VL 6736
5465 13:38:27.274185 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5466 13:38:27.274281 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5467 13:38:27.276021 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5468 13:38:27.276341 # ok 3741 Set Streaming SVE VL 6752
5469 13:38:27.276476 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5470 13:38:27.276600 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5471 13:38:27.276809 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5472 13:38:27.276991 # ok 3745 Set Streaming SVE VL 6768
5473 13:38:27.277165 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5474 13:38:27.277331 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5475 13:38:27.277522 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5476 13:38:27.277698 # ok 3749 Set Streaming SVE VL 6784
5477 13:38:27.277848 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5478 13:38:27.277983 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5479 13:38:27.278185 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5480 13:38:27.278342 # ok 3753 Set Streaming SVE VL 6800
5481 13:38:27.278487 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5482 13:38:27.278618 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5483 13:38:27.278748 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5484 13:38:27.278876 # ok 3757 Set Streaming SVE VL 6816
5485 13:38:27.280924 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5486 13:38:27.281342 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5487 13:38:27.281527 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5488 13:38:27.281704 # ok 3761 Set Streaming SVE VL 6832
5489 13:38:27.281901 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5490 13:38:27.282072 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5491 13:38:27.282241 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5492 13:38:27.282421 # ok 3765 Set Streaming SVE VL 6848
5493 13:38:27.282613 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5494 13:38:27.282782 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5495 13:38:27.282949 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5496 13:38:27.283149 # ok 3769 Set Streaming SVE VL 6864
5497 13:38:27.283324 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5498 13:38:27.283495 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5499 13:38:27.283693 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5500 13:38:27.283865 # ok 3773 Set Streaming SVE VL 6880
5501 13:38:27.284034 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5502 13:38:27.284233 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5503 13:38:27.284404 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5504 13:38:27.284566 # ok 3777 Set Streaming SVE VL 6896
5505 13:38:27.284758 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5506 13:38:27.284926 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5507 13:38:27.285084 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5508 13:38:27.285275 # ok 3781 Set Streaming SVE VL 6912
5509 13:38:27.285448 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5510 13:38:27.285608 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5511 13:38:27.285781 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5512 13:38:27.285978 # ok 3785 Set Streaming SVE VL 6928
5513 13:38:27.286147 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5514 13:38:27.286309 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5515 13:38:27.286471 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5516 13:38:27.286634 # ok 3789 Set Streaming SVE VL 6944
5517 13:38:27.290512 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5518 13:38:27.290963 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5519 13:38:27.291149 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5520 13:38:27.291322 # ok 3793 Set Streaming SVE VL 6960
5521 13:38:27.291491 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5522 13:38:27.291686 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5523 13:38:27.291857 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5524 13:38:27.292052 # ok 3797 Set Streaming SVE VL 6976
5525 13:38:27.292261 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5526 13:38:27.292449 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5527 13:38:27.292599 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5528 13:38:27.292766 # ok 3801 Set Streaming SVE VL 6992
5529 13:38:27.292897 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5530 13:38:27.293021 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5531 13:38:27.293171 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5532 13:38:27.293292 # ok 3805 Set Streaming SVE VL 7008
5533 13:38:27.293414 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5534 13:38:27.293564 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5535 13:38:27.293709 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5536 13:38:27.293864 # ok 3809 Set Streaming SVE VL 7024
5537 13:38:27.294004 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5538 13:38:27.294118 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5539 13:38:27.294226 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5540 13:38:27.294334 # ok 3813 Set Streaming SVE VL 7040
5541 13:38:27.294445 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5542 13:38:27.294580 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5543 13:38:27.294685 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5544 13:38:27.294794 # ok 3817 Set Streaming SVE VL 7056
5545 13:38:27.298529 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5546 13:38:27.298786 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5547 13:38:27.298903 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5548 13:38:27.299004 # ok 3821 Set Streaming SVE VL 7072
5549 13:38:27.299094 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5550 13:38:27.299203 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5551 13:38:27.299323 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5552 13:38:27.299438 # ok 3825 Set Streaming SVE VL 7088
5553 13:38:27.299552 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5554 13:38:27.299663 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5555 13:38:27.299773 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5556 13:38:27.299890 # ok 3829 Set Streaming SVE VL 7104
5557 13:38:27.300010 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5558 13:38:27.300129 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5559 13:38:27.300431 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5560 13:38:27.300536 # ok 3833 Set Streaming SVE VL 7120
5561 13:38:27.300645 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5562 13:38:27.300728 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5563 13:38:27.300834 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5564 13:38:27.300940 # ok 3837 Set Streaming SVE VL 7136
5565 13:38:27.301048 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5566 13:38:27.301157 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5567 13:38:27.301275 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5568 13:38:27.301398 # ok 3841 Set Streaming SVE VL 7152
5569 13:38:27.301527 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5570 13:38:27.301627 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5571 13:38:27.301894 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5572 13:38:27.301989 # ok 3845 Set Streaming SVE VL 7168
5573 13:38:27.302082 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5574 13:38:27.304124 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5575 13:38:27.304419 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5576 13:38:27.304503 # ok 3849 Set Streaming SVE VL 7184
5577 13:38:27.304598 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5578 13:38:27.304684 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5579 13:38:27.304960 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5580 13:38:27.305051 # ok 3853 Set Streaming SVE VL 7200
5581 13:38:27.305164 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5582 13:38:27.305267 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5583 13:38:27.305382 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5584 13:38:27.305484 # ok 3857 Set Streaming SVE VL 7216
5585 13:38:27.305580 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5586 13:38:27.305692 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5587 13:38:27.305795 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5588 13:38:27.305898 # ok 3861 Set Streaming SVE VL 7232
5589 13:38:27.306045 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5590 13:38:27.310293 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5591 13:38:27.310621 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5592 13:38:27.310723 # ok 3865 Set Streaming SVE VL 7248
5593 13:38:27.310811 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5594 13:38:27.310908 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5595 13:38:27.310994 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5596 13:38:27.311070 # ok 3869 Set Streaming SVE VL 7264
5597 13:38:27.311154 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5598 13:38:27.311261 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5599 13:38:27.311353 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5600 13:38:27.311477 # ok 3873 Set Streaming SVE VL 7280
5601 13:38:27.311573 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5602 13:38:27.311696 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5603 13:38:27.311802 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5604 13:38:27.311916 # ok 3877 Set Streaming SVE VL 7296
5605 13:38:27.312031 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5606 13:38:27.312157 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5607 13:38:27.312449 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5608 13:38:27.312596 # ok 3881 Set Streaming SVE VL 7312
5609 13:38:27.312743 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5610 13:38:27.312870 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5611 13:38:27.313018 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5612 13:38:27.313145 # ok 3885 Set Streaming SVE VL 7328
5613 13:38:27.313286 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5614 13:38:27.313410 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5615 13:38:27.313560 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5616 13:38:27.313701 # ok 3889 Set Streaming SVE VL 7344
5617 13:38:27.313874 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5618 13:38:27.314003 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5619 13:38:27.314142 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5620 13:38:27.314276 # ok 3893 Set Streaming SVE VL 7360
5621 13:38:27.323069 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5622 13:38:27.323538 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5623 13:38:27.323687 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5624 13:38:27.323813 # ok 3897 Set Streaming SVE VL 7376
5625 13:38:27.323939 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5626 13:38:27.324060 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5627 13:38:27.324176 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5628 13:38:27.324295 # ok 3901 Set Streaming SVE VL 7392
5629 13:38:27.324386 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5630 13:38:27.324508 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5631 13:38:27.324615 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5632 13:38:27.324731 # ok 3905 Set Streaming SVE VL 7408
5633 13:38:27.324852 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5634 13:38:27.324954 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5635 13:38:27.325051 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5636 13:38:27.325197 # ok 3909 Set Streaming SVE VL 7424
5637 13:38:27.325324 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5638 13:38:27.325443 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5639 13:38:27.325572 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5640 13:38:27.325751 # ok 3913 Set Streaming SVE VL 7440
5641 13:38:27.325862 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5642 13:38:27.325961 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5643 13:38:27.326093 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5644 13:38:27.326192 # ok 3917 Set Streaming SVE VL 7456
5645 13:38:27.326281 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5646 13:38:27.334768 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5647 13:38:27.334982 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5648 13:38:27.335109 # ok 3921 Set Streaming SVE VL 7472
5649 13:38:27.335235 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5650 13:38:27.335338 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5651 13:38:27.335446 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5652 13:38:27.335746 # ok 3925 Set Streaming SVE VL 7488
5653 13:38:27.335884 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5654 13:38:27.336031 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5655 13:38:27.336222 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5656 13:38:27.336378 # ok 3929 Set Streaming SVE VL 7504
5657 13:38:27.336687 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5658 13:38:27.336824 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5659 13:38:27.336947 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5660 13:38:27.337086 # ok 3933 Set Streaming SVE VL 7520
5661 13:38:27.337219 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5662 13:38:27.337372 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5663 13:38:27.337495 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5664 13:38:27.337633 # ok 3937 Set Streaming SVE VL 7536
5665 13:38:27.337782 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5666 13:38:27.337910 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5667 13:38:27.338243 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5668 13:38:27.338348 # ok 3941 Set Streaming SVE VL 7552
5669 13:38:27.338439 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5670 13:38:27.338528 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5671 13:38:27.345105 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5672 13:38:27.345409 # ok 3945 Set Streaming SVE VL 7568
5673 13:38:27.345515 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5674 13:38:27.345604 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5675 13:38:27.345743 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5676 13:38:27.345829 # ok 3949 Set Streaming SVE VL 7584
5677 13:38:27.345936 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5678 13:38:27.346040 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5679 13:38:27.346140 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5680 13:38:27.349280 # ok 3953 Set Streaming SVE VL 7600
5681 13:38:27.349588 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5682 13:38:27.349697 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5683 13:38:27.349774 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5684 13:38:27.349854 # ok 3957 Set Streaming SVE VL 7616
5685 13:38:27.349943 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5686 13:38:27.350040 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5687 13:38:27.350988 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5688 13:38:27.351146 # ok 3961 Set Streaming SVE VL 7632
5689 13:38:27.351423 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5690 13:38:27.351505 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5691 13:38:27.351584 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5692 13:38:27.351648 # ok 3965 Set Streaming SVE VL 7648
5693 13:38:27.351728 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5694 13:38:27.352011 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5695 13:38:27.352107 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5696 13:38:27.352231 # ok 3969 Set Streaming SVE VL 7664
5697 13:38:27.352322 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5698 13:38:27.352426 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5699 13:38:27.352532 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5700 13:38:27.352658 # ok 3973 Set Streaming SVE VL 7680
5701 13:38:27.352753 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5702 13:38:27.352859 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5703 13:38:27.353164 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5704 13:38:27.353274 # ok 3977 Set Streaming SVE VL 7696
5705 13:38:27.353380 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5706 13:38:27.353500 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5707 13:38:27.353604 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5708 13:38:27.353713 # ok 3981 Set Streaming SVE VL 7712
5709 13:38:27.353843 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5710 13:38:27.353942 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5711 13:38:27.354059 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5712 13:38:27.354143 # ok 3985 Set Streaming SVE VL 7728
5713 13:38:27.358469 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5714 13:38:27.358821 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5715 13:38:27.358934 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5716 13:38:27.359034 # ok 3989 Set Streaming SVE VL 7744
5717 13:38:27.359147 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5718 13:38:27.359244 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5719 13:38:27.359357 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5720 13:38:27.359453 # ok 3993 Set Streaming SVE VL 7760
5721 13:38:27.359570 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5722 13:38:27.359667 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5723 13:38:27.359778 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5724 13:38:27.359894 # ok 3997 Set Streaming SVE VL 7776
5725 13:38:27.360005 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5726 13:38:27.360399 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5727 13:38:27.360509 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5728 13:38:27.360606 # ok 4001 Set Streaming SVE VL 7792
5729 13:38:27.360871 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5730 13:38:27.360990 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5731 13:38:27.361089 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5732 13:38:27.361204 # ok 4005 Set Streaming SVE VL 7808
5733 13:38:27.361322 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5734 13:38:27.361415 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5735 13:38:27.361528 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5736 13:38:27.361627 # ok 4009 Set Streaming SVE VL 7824
5737 13:38:27.361747 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5738 13:38:27.361852 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5739 13:38:27.361955 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5740 13:38:27.362048 # ok 4013 Set Streaming SVE VL 7840
5741 13:38:27.362128 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5742 13:38:27.362194 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5743 13:38:27.365378 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5744 13:38:27.365689 # ok 4017 Set Streaming SVE VL 7856
5745 13:38:27.365792 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5746 13:38:27.365930 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5747 13:38:27.366041 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5748 13:38:27.366142 # ok 4021 Set Streaming SVE VL 7872
5749 13:38:27.366269 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5750 13:38:27.366359 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5751 13:38:27.368287 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5752 13:38:27.368623 # ok 4025 Set Streaming SVE VL 7888
5753 13:38:27.368778 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5754 13:38:27.368905 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5755 13:38:27.369044 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5756 13:38:27.369167 # ok 4029 Set Streaming SVE VL 7904
5757 13:38:27.369288 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5758 13:38:27.369433 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5759 13:38:27.369563 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5760 13:38:27.369711 # ok 4033 Set Streaming SVE VL 7920
5761 13:38:27.369870 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5762 13:38:27.369997 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5763 13:38:27.370159 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5764 13:38:27.370318 # ok 4037 Set Streaming SVE VL 7936
5765 13:38:27.370423 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5766 13:38:27.372008 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5767 13:38:27.372353 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5768 13:38:27.372480 # ok 4041 Set Streaming SVE VL 7952
5769 13:38:27.372668 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5770 13:38:27.372789 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5771 13:38:27.372926 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5772 13:38:27.373039 # ok 4045 Set Streaming SVE VL 7968
5773 13:38:27.373155 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5774 13:38:27.373293 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5775 13:38:27.373413 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5776 13:38:27.373531 # ok 4049 Set Streaming SVE VL 7984
5777 13:38:27.373865 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5778 13:38:27.373993 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5779 13:38:27.374111 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5780 13:38:27.374212 # ok 4053 Set Streaming SVE VL 8000
5781 13:38:27.374321 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5782 13:38:27.374414 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5783 13:38:27.377127 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5784 13:38:27.377477 # ok 4057 Set Streaming SVE VL 8016
5785 13:38:27.377656 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5786 13:38:27.377800 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5787 13:38:27.377924 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5788 13:38:27.378052 # ok 4061 Set Streaming SVE VL 8032
5789 13:38:27.378179 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5790 13:38:27.378276 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5791 13:38:27.378580 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5792 13:38:27.378676 # ok 4065 Set Streaming SVE VL 8048
5793 13:38:27.378769 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5794 13:38:27.378857 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5795 13:38:27.379133 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5796 13:38:27.379231 # ok 4069 Set Streaming SVE VL 8064
5797 13:38:27.379319 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5798 13:38:27.379417 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5799 13:38:27.379681 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5800 13:38:27.379762 # ok 4073 Set Streaming SVE VL 8080
5801 13:38:27.379853 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5802 13:38:27.380346 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5803 13:38:27.380433 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5804 13:38:27.380520 # ok 4077 Set Streaming SVE VL 8096
5805 13:38:27.380628 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5806 13:38:27.380887 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5807 13:38:27.380976 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5808 13:38:27.381049 # ok 4081 Set Streaming SVE VL 8112
5809 13:38:27.381339 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5810 13:38:27.381435 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5811 13:38:27.381529 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5812 13:38:27.381607 # ok 4085 Set Streaming SVE VL 8128
5813 13:38:27.381719 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5814 13:38:27.381838 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5815 13:38:27.381949 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5816 13:38:27.382048 # ok 4089 Set Streaming SVE VL 8144
5817 13:38:27.382149 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5818 13:38:27.388534 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5819 13:38:27.388953 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5820 13:38:27.389067 # ok 4093 Set Streaming SVE VL 8160
5821 13:38:27.389153 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5822 13:38:27.389238 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5823 13:38:27.389343 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5824 13:38:27.389435 # ok 4097 Set Streaming SVE VL 8176
5825 13:38:27.389541 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5826 13:38:27.389612 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5827 13:38:27.389681 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5828 13:38:27.389765 # ok 4101 Set Streaming SVE VL 8192
5829 13:38:27.389834 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5830 13:38:27.389911 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5831 13:38:27.390168 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5832 13:38:27.395008 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5833 13:38:27.395301 ok 30 selftests: arm64: sve-ptrace
5834 13:38:27.395499 # selftests: arm64: sve-probe-vls
5835 13:38:27.395668 # TAP version 13
5836 13:38:27.395831 # 1..2
5837 13:38:27.396018 # ok 1 Enumerated 16 vector lengths
5838 13:38:27.396162 # ok 2 All vector lengths valid
5839 13:38:27.396283 # # 16
5840 13:38:27.396401 # # 32
5841 13:38:27.396518 # # 48
5842 13:38:27.396634 # # 64
5843 13:38:27.396749 # # 80
5844 13:38:27.396864 # # 96
5845 13:38:27.396977 # # 112
5846 13:38:27.397090 # # 128
5847 13:38:27.397203 # # 144
5848 13:38:27.397317 # # 160
5849 13:38:27.397429 # # 176
5850 13:38:27.397542 # # 192
5851 13:38:27.397670 # # 208
5852 13:38:27.397787 # # 224
5853 13:38:27.397900 # # 240
5854 13:38:27.398014 # # 256
5855 13:38:27.398128 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5856 13:38:27.398269 ok 31 selftests: arm64: sve-probe-vls
5857 13:38:27.398390 # selftests: arm64: vec-syscfg
5858 13:38:27.842850 # TAP version 13
5859 13:38:27.848586 # 1..20
5860 13:38:27.848872 # ok 1 SVE default vector length 64
5861 13:38:27.849037 # ok 2 SVE minimum vector length 16
5862 13:38:27.849202 # ok 3 SVE maximum vector length 256
5863 13:38:27.849350 # ok 4 SVE current VL is 64
5864 13:38:27.849776 # ok 5 SVE set VL 64 and have VL 64
5865 13:38:27.849962 # ok 6 SVE prctl() set min/max
5866 13:38:27.850098 # ok 7 SVE vector length used default
5867 13:38:27.850226 # ok 8 SVE vector length was inherited
5868 13:38:27.850351 # ok 9 SVE vector length set on exec
5869 13:38:27.850470 # ok 10 SVE prctl() set all VLs, 0 errors
5870 13:38:27.850587 # ok 11 SME default vector length 32
5871 13:38:27.850729 # ok 12 SME minimum vector length 16
5872 13:38:27.850873 # ok 13 SME maximum vector length 256
5873 13:38:27.851006 # ok 14 SME current VL is 32
5874 13:38:27.851125 # ok 15 SME set VL 32 and have VL 32
5875 13:38:27.851242 # ok 16 SME prctl() set min/max
5876 13:38:27.851387 # ok 17 SME vector length used default
5877 13:38:27.851513 # ok 18 SME vector length was inherited
5878 13:38:27.851632 # ok 19 SME vector length set on exec
5879 13:38:27.851749 # ok 20 SME prctl() set all VLs, 0 errors
5880 13:38:27.851867 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5881 13:38:27.861242 ok 32 selftests: arm64: vec-syscfg
5882 13:38:27.939860 # selftests: arm64: za-fork
5883 13:38:28.095808 # TAP version 13
5884 13:38:28.096346 # 1..1
5885 13:38:28.096506 # # PID: 1015
5886 13:38:28.096639 # ok 1 fork_test
5887 13:38:28.096765 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5888 13:38:28.110673 ok 33 selftests: arm64: za-fork
5889 13:38:28.209447 # selftests: arm64: za-ptrace
5890 13:38:28.316179 # TAP version 13
5891 13:38:28.316523 # 1..1536
5892 13:38:28.316734 # # Parent is 1033, child is 1034
5893 13:38:28.316918 # ok 1 Set VL 16
5894 13:38:28.317367 # ok 2 Disabled ZA for VL 16
5895 13:38:28.317597 # ok 3 Data match for VL 16
5896 13:38:28.317809 # ok 4 Set VL 32
5897 13:38:28.317987 # ok 5 Disabled ZA for VL 32
5898 13:38:28.318158 # ok 6 Data match for VL 32
5899 13:38:28.318394 # ok 7 Set VL 48
5900 13:38:28.318615 # ok 8 # SKIP Disabled ZA for VL 48
5901 13:38:28.318836 # ok 9 # SKIP Get and set data for VL 48
5902 13:38:28.319093 # ok 10 Set VL 64
5903 13:38:28.319301 # ok 11 Disabled ZA for VL 64
5904 13:38:28.319447 # ok 12 Data match for VL 64
5905 13:38:28.319566 # ok 13 Set VL 80
5906 13:38:28.319694 # ok 14 # SKIP Disabled ZA for VL 80
5907 13:38:28.319812 # ok 15 # SKIP Get and set data for VL 80
5908 13:38:28.319928 # ok 16 Set VL 96
5909 13:38:28.320078 # ok 17 # SKIP Disabled ZA for VL 96
5910 13:38:28.320201 # ok 18 # SKIP Get and set data for VL 96
5911 13:38:28.320317 # ok 19 Set VL 112
5912 13:38:28.320437 # ok 20 # SKIP Disabled ZA for VL 112
5913 13:38:28.320552 # ok 21 # SKIP Get and set data for VL 112
5914 13:38:28.320667 # ok 22 Set VL 128
5915 13:38:28.320779 # ok 23 Disabled ZA for VL 128
5916 13:38:28.320894 # ok 24 Data match for VL 128
5917 13:38:28.321008 # ok 25 Set VL 144
5918 13:38:28.321123 # ok 26 # SKIP Disabled ZA for VL 144
5919 13:38:28.321239 # ok 27 # SKIP Get and set data for VL 144
5920 13:38:28.321357 # ok 28 Set VL 160
5921 13:38:28.321472 # ok 29 # SKIP Disabled ZA for VL 160
5922 13:38:28.321585 # ok 30 # SKIP Get and set data for VL 160
5923 13:38:28.321786 # ok 31 Set VL 176
5924 13:38:28.321985 # ok 32 # SKIP Disabled ZA for VL 176
5925 13:38:28.322170 # ok 33 # SKIP Get and set data for VL 176
5926 13:38:28.322357 # ok 34 Set VL 192
5927 13:38:28.322542 # ok 35 # SKIP Disabled ZA for VL 192
5928 13:38:28.322726 # ok 36 # SKIP Get and set data for VL 192
5929 13:38:28.322895 # ok 37 Set VL 208
5930 13:38:28.323831 # ok 38 # SKIP Disabled ZA for VL 208
5931 13:38:28.324340 # ok 39 # SKIP Get and set data for VL 208
5932 13:38:28.324549 # ok 40 Set VL 224
5933 13:38:28.324759 # ok 41 # SKIP Disabled ZA for VL 224
5934 13:38:28.324979 # ok 42 # SKIP Get and set data for VL 224
5935 13:38:28.325141 # ok 43 Set VL 240
5936 13:38:28.325321 # ok 44 # SKIP Disabled ZA for VL 240
5937 13:38:28.325559 # ok 45 # SKIP Get and set data for VL 240
5938 13:38:28.325787 # ok 46 Set VL 256
5939 13:38:28.326030 # ok 47 Disabled ZA for VL 256
5940 13:38:28.326267 # ok 48 Data match for VL 256
5941 13:38:28.326483 # ok 49 Set VL 272
5942 13:38:28.326727 # ok 50 # SKIP Disabled ZA for VL 272
5943 13:38:28.326911 # ok 51 # SKIP Get and set data for VL 272
5944 13:38:28.327075 # ok 52 Set VL 288
5945 13:38:28.327244 # ok 53 # SKIP Disabled ZA for VL 288
5946 13:38:28.327416 # ok 54 # SKIP Get and set data for VL 288
5947 13:38:28.327603 # ok 55 Set VL 304
5948 13:38:28.327737 # ok 56 # SKIP Disabled ZA for VL 304
5949 13:38:28.327915 # ok 57 # SKIP Get and set data for VL 304
5950 13:38:28.328080 # ok 58 Set VL 320
5951 13:38:28.328227 # ok 59 # SKIP Disabled ZA for VL 320
5952 13:38:28.328418 # ok 60 # SKIP Get and set data for VL 320
5953 13:38:28.328598 # ok 61 Set VL 336
5954 13:38:28.328767 # ok 62 # SKIP Disabled ZA for VL 336
5955 13:38:28.328943 # ok 63 # SKIP Get and set data for VL 336
5956 13:38:28.329165 # ok 64 Set VL 352
5957 13:38:28.329353 # ok 65 # SKIP Disabled ZA for VL 352
5958 13:38:28.329526 # ok 66 # SKIP Get and set data for VL 352
5959 13:38:28.329712 # ok 67 Set VL 368
5960 13:38:28.329893 # ok 68 # SKIP Disabled ZA for VL 368
5961 13:38:28.330076 # ok 69 # SKIP Get and set data for VL 368
5962 13:38:28.330257 # ok 70 Set VL 384
5963 13:38:28.330441 # ok 71 # SKIP Disabled ZA for VL 384
5964 13:38:28.330621 # ok 72 # SKIP Get and set data for VL 384
5965 13:38:28.333612 # ok 73 Set VL 400
5966 13:38:28.334093 # ok 74 # SKIP Disabled ZA for VL 400
5967 13:38:28.334272 # ok 75 # SKIP Get and set data for VL 400
5968 13:38:28.334440 # ok 76 Set VL 416
5969 13:38:28.334581 # ok 77 # SKIP Disabled ZA for VL 416
5970 13:38:28.334730 # ok 78 # SKIP Get and set data for VL 416
5971 13:38:28.334896 # ok 79 Set VL 432
5972 13:38:28.335124 # ok 80 # SKIP Disabled ZA for VL 432
5973 13:38:28.335299 # ok 81 # SKIP Get and set data for VL 432
5974 13:38:28.335470 # ok 82 Set VL 448
5975 13:38:28.335640 # ok 83 # SKIP Disabled ZA for VL 448
5976 13:38:28.335823 # ok 84 # SKIP Get and set data for VL 448
5977 13:38:28.336013 # ok 85 Set VL 464
5978 13:38:28.336149 # ok 86 # SKIP Disabled ZA for VL 464
5979 13:38:28.336289 # ok 87 # SKIP Get and set data for VL 464
5980 13:38:28.336483 # ok 88 Set VL 480
5981 13:38:28.336649 # ok 89 # SKIP Disabled ZA for VL 480
5982 13:38:28.336824 # ok 90 # SKIP Get and set data for VL 480
5983 13:38:28.337029 # ok 91 Set VL 496
5984 13:38:28.337203 # ok 92 # SKIP Disabled ZA for VL 496
5985 13:38:28.337366 # ok 93 # SKIP Get and set data for VL 496
5986 13:38:28.337527 # ok 94 Set VL 512
5987 13:38:28.337698 # ok 95 # SKIP Disabled ZA for VL 512
5988 13:38:28.337845 # ok 96 # SKIP Get and set data for VL 512
5989 13:38:28.338014 # ok 97 Set VL 528
5990 13:38:28.338177 # ok 98 # SKIP Disabled ZA for VL 528
5991 13:38:28.338341 # ok 99 # SKIP Get and set data for VL 528
5992 13:38:28.338505 # ok 100 Set VL 544
5993 13:38:28.338630 # ok 101 # SKIP Disabled ZA for VL 544
5994 13:38:28.338748 # ok 102 # SKIP Get and set data for VL 544
5995 13:38:28.338864 # ok 103 Set VL 560
5996 13:38:28.338980 # ok 104 # SKIP Disabled ZA for VL 560
5997 13:38:28.339096 # ok 105 # SKIP Get and set data for VL 560
5998 13:38:28.339213 # ok 106 Set VL 576
5999 13:38:28.339412 # ok 107 # SKIP Disabled ZA for VL 576
6000 13:38:28.339553 # ok 108 # SKIP Get and set data for VL 576
6001 13:38:28.339674 # ok 109 Set VL 592
6002 13:38:28.339792 # ok 110 # SKIP Disabled ZA for VL 592
6003 13:38:28.339909 # ok 111 # SKIP Get and set data for VL 592
6004 13:38:28.340027 # ok 112 Set VL 608
6005 13:38:28.340144 # ok 113 # SKIP Disabled ZA for VL 608
6006 13:38:28.340262 # ok 114 # SKIP Get and set data for VL 608
6007 13:38:28.340380 # ok 115 Set VL 624
6008 13:38:28.340501 # ok 116 # SKIP Disabled ZA for VL 624
6009 13:38:28.340621 # ok 117 # SKIP Get and set data for VL 624
6010 13:38:28.340738 # ok 118 Set VL 640
6011 13:38:28.340856 # ok 119 # SKIP Disabled ZA for VL 640
6012 13:38:28.340973 # ok 120 # SKIP Get and set data for VL 640
6013 13:38:28.341090 # ok 121 Set VL 656
6014 13:38:28.341207 # ok 122 # SKIP Disabled ZA for VL 656
6015 13:38:28.341324 # ok 123 # SKIP Get and set data for VL 656
6016 13:38:28.341444 # ok 124 Set VL 672
6017 13:38:28.350194 # ok 125 # SKIP Disabled ZA for VL 672
6018 13:38:28.350744 # ok 126 # SKIP Get and set data for VL 672
6019 13:38:28.350855 # ok 127 Set VL 688
6020 13:38:28.350947 # ok 128 # SKIP Disabled ZA for VL 688
6021 13:38:28.351037 # ok 129 # SKIP Get and set data for VL 688
6022 13:38:28.351122 # ok 130 Set VL 704
6023 13:38:28.351207 # ok 131 # SKIP Disabled ZA for VL 704
6024 13:38:28.351291 # ok 132 # SKIP Get and set data for VL 704
6025 13:38:28.351374 # ok 133 Set VL 720
6026 13:38:28.351481 # ok 134 # SKIP Disabled ZA for VL 720
6027 13:38:28.351570 # ok 135 # SKIP Get and set data for VL 720
6028 13:38:28.351655 # ok 136 Set VL 736
6029 13:38:28.351738 # ok 137 # SKIP Disabled ZA for VL 736
6030 13:38:28.351821 # ok 138 # SKIP Get and set data for VL 736
6031 13:38:28.361033 # ok 139 Set VL 752
6032 13:38:28.361247 # ok 140 # SKIP Disabled ZA for VL 752
6033 13:38:28.361678 # ok 141 # SKIP Get and set data for VL 752
6034 13:38:28.361863 # ok 142 Set VL 768
6035 13:38:28.362025 # ok 143 # SKIP Disabled ZA for VL 768
6036 13:38:28.362198 # ok 144 # SKIP Get and set data for VL 768
6037 13:38:28.362397 # ok 145 Set VL 784
6038 13:38:28.362549 # ok 146 # SKIP Disabled ZA for VL 784
6039 13:38:28.362725 # ok 147 # SKIP Get and set data for VL 784
6040 13:38:28.362895 # ok 148 Set VL 800
6041 13:38:28.363061 # ok 149 # SKIP Disabled ZA for VL 800
6042 13:38:28.363275 # ok 150 # SKIP Get and set data for VL 800
6043 13:38:28.363447 # ok 151 Set VL 816
6044 13:38:28.363569 # ok 152 # SKIP Disabled ZA for VL 816
6045 13:38:28.363714 # ok 153 # SKIP Get and set data for VL 816
6046 13:38:28.363871 # ok 154 Set VL 832
6047 13:38:28.364025 # ok 155 # SKIP Disabled ZA for VL 832
6048 13:38:28.364166 # ok 156 # SKIP Get and set data for VL 832
6049 13:38:28.364292 # ok 157 Set VL 848
6050 13:38:28.364443 # ok 158 # SKIP Disabled ZA for VL 848
6051 13:38:28.364588 # ok 159 # SKIP Get and set data for VL 848
6052 13:38:28.364745 # ok 160 Set VL 864
6053 13:38:28.364898 # ok 161 # SKIP Disabled ZA for VL 864
6054 13:38:28.365053 # ok 162 # SKIP Get and set data for VL 864
6055 13:38:28.365210 # ok 163 Set VL 880
6056 13:38:28.365371 # ok 164 # SKIP Disabled ZA for VL 880
6057 13:38:28.365513 # ok 165 # SKIP Get and set data for VL 880
6058 13:38:28.366163 # ok 166 Set VL 896
6059 13:38:28.366347 # ok 167 # SKIP Disabled ZA for VL 896
6060 13:38:28.366520 # ok 168 # SKIP Get and set data for VL 896
6061 13:38:28.366680 # ok 169 Set VL 912
6062 13:38:28.366843 # ok 170 # SKIP Disabled ZA for VL 912
6063 13:38:28.367007 # ok 171 # SKIP Get and set data for VL 912
6064 13:38:28.367168 # ok 172 Set VL 928
6065 13:38:28.367327 # ok 173 # SKIP Disabled ZA for VL 928
6066 13:38:28.367457 # ok 174 # SKIP Get and set data for VL 928
6067 13:38:28.367571 # ok 175 Set VL 944
6068 13:38:28.367683 # ok 176 # SKIP Disabled ZA for VL 944
6069 13:38:28.367798 # ok 177 # SKIP Get and set data for VL 944
6070 13:38:28.367910 # ok 178 Set VL 960
6071 13:38:28.368022 # ok 179 # SKIP Disabled ZA for VL 960
6072 13:38:28.368167 # ok 180 # SKIP Get and set data for VL 960
6073 13:38:28.368288 # ok 181 Set VL 976
6074 13:38:28.368403 # ok 182 # SKIP Disabled ZA for VL 976
6075 13:38:28.368521 # ok 183 # SKIP Get and set data for VL 976
6076 13:38:28.368635 # ok 184 Set VL 992
6077 13:38:28.368747 # ok 185 # SKIP Disabled ZA for VL 992
6078 13:38:28.368861 # ok 186 # SKIP Get and set data for VL 992
6079 13:38:28.368975 # ok 187 Set VL 1008
6080 13:38:28.369089 # ok 188 # SKIP Disabled ZA for VL 1008
6081 13:38:28.369205 # ok 189 # SKIP Get and set data for VL 1008
6082 13:38:28.369318 # ok 190 Set VL 1024
6083 13:38:28.369433 # ok 191 # SKIP Disabled ZA for VL 1024
6084 13:38:28.369549 # ok 192 # SKIP Get and set data for VL 1024
6085 13:38:28.369680 # ok 193 Set VL 1040
6086 13:38:28.369799 # ok 194 # SKIP Disabled ZA for VL 1040
6087 13:38:28.370129 # ok 195 # SKIP Get and set data for VL 1040
6088 13:38:28.370259 # ok 196 Set VL 1056
6089 13:38:28.370377 # ok 197 # SKIP Disabled ZA for VL 1056
6090 13:38:28.370494 # ok 198 # SKIP Get and set data for VL 1056
6091 13:38:28.370610 # ok 199 Set VL 1072
6092 13:38:28.370726 # ok 200 # SKIP Disabled ZA for VL 1072
6093 13:38:28.370841 # ok 201 # SKIP Get and set data for VL 1072
6094 13:38:28.370955 # ok 202 Set VL 1088
6095 13:38:28.371069 # ok 203 # SKIP Disabled ZA for VL 1088
6096 13:38:28.371185 # ok 204 # SKIP Get and set data for VL 1088
6097 13:38:28.371300 # ok 205 Set VL 1104
6098 13:38:28.371416 # ok 206 # SKIP Disabled ZA for VL 1104
6099 13:38:28.371531 # ok 207 # SKIP Get and set data for VL 1104
6100 13:38:28.371646 # ok 208 Set VL 1120
6101 13:38:28.376740 # ok 209 # SKIP Disabled ZA for VL 1120
6102 13:38:28.377176 # ok 210 # SKIP Get and set data for VL 1120
6103 13:38:28.377345 # ok 211 Set VL 1136
6104 13:38:28.377516 # ok 212 # SKIP Disabled ZA for VL 1136
6105 13:38:28.377690 # ok 213 # SKIP Get and set data for VL 1136
6106 13:38:28.377883 # ok 214 Set VL 1152
6107 13:38:28.378046 # ok 215 # SKIP Disabled ZA for VL 1152
6108 13:38:28.378203 # ok 216 # SKIP Get and set data for VL 1152
6109 13:38:28.378368 # ok 217 Set VL 1168
6110 13:38:28.378527 # ok 218 # SKIP Disabled ZA for VL 1168
6111 13:38:28.378657 # ok 219 # SKIP Get and set data for VL 1168
6112 13:38:28.378801 # ok 220 Set VL 1184
6113 13:38:28.378956 # ok 221 # SKIP Disabled ZA for VL 1184
6114 13:38:28.379101 # ok 222 # SKIP Get and set data for VL 1184
6115 13:38:28.379259 # ok 223 Set VL 1200
6116 13:38:28.379419 # ok 224 # SKIP Disabled ZA for VL 1200
6117 13:38:28.379563 # ok 225 # SKIP Get and set data for VL 1200
6118 13:38:28.379684 # ok 226 Set VL 1216
6119 13:38:28.379798 # ok 227 # SKIP Disabled ZA for VL 1216
6120 13:38:28.379913 # ok 228 # SKIP Get and set data for VL 1216
6121 13:38:28.380067 # ok 229 Set VL 1232
6122 13:38:28.380232 # ok 230 # SKIP Disabled ZA for VL 1232
6123 13:38:28.380390 # ok 231 # SKIP Get and set data for VL 1232
6124 13:38:28.380548 # ok 232 Set VL 1248
6125 13:38:28.380700 # ok 233 # SKIP Disabled ZA for VL 1248
6126 13:38:28.380857 # ok 234 # SKIP Get and set data for VL 1248
6127 13:38:28.381015 # ok 235 Set VL 1264
6128 13:38:28.381177 # ok 236 # SKIP Disabled ZA for VL 1264
6129 13:38:28.381330 # ok 237 # SKIP Get and set data for VL 1264
6130 13:38:28.381482 # ok 238 Set VL 1280
6131 13:38:28.381637 # ok 239 # SKIP Disabled ZA for VL 1280
6132 13:38:28.381881 # ok 240 # SKIP Get and set data for VL 1280
6133 13:38:28.382071 # ok 241 Set VL 1296
6134 13:38:28.382304 # ok 242 # SKIP Disabled ZA for VL 1296
6135 13:38:28.382497 # ok 243 # SKIP Get and set data for VL 1296
6136 13:38:28.382680 # ok 244 Set VL 1312
6137 13:38:28.382855 # ok 245 # SKIP Disabled ZA for VL 1312
6138 13:38:28.383000 # ok 246 # SKIP Get and set data for VL 1312
6139 13:38:28.383143 # ok 247 Set VL 1328
6140 13:38:28.383285 # ok 248 # SKIP Disabled ZA for VL 1328
6141 13:38:28.383432 # ok 249 # SKIP Get and set data for VL 1328
6142 13:38:28.383577 # ok 250 Set VL 1344
6143 13:38:28.383718 # ok 251 # SKIP Disabled ZA for VL 1344
6144 13:38:28.383859 # ok 252 # SKIP Get and set data for VL 1344
6145 13:38:28.384001 # ok 253 Set VL 1360
6146 13:38:28.384143 # ok 254 # SKIP Disabled ZA for VL 1360
6147 13:38:28.384284 # ok 255 # SKIP Get and set data for VL 1360
6148 13:38:28.384426 # ok 256 Set VL 1376
6149 13:38:28.384572 # ok 257 # SKIP Disabled ZA for VL 1376
6150 13:38:28.384714 # ok 258 # SKIP Get and set data for VL 1376
6151 13:38:28.384856 # ok 259 Set VL 1392
6152 13:38:28.384999 # ok 260 # SKIP Disabled ZA for VL 1392
6153 13:38:28.385140 # ok 261 # SKIP Get and set data for VL 1392
6154 13:38:28.385282 # ok 262 Set VL 1408
6155 13:38:28.385424 # ok 263 # SKIP Disabled ZA for VL 1408
6156 13:38:28.385804 # ok 264 # SKIP Get and set data for VL 1408
6157 13:38:28.385963 # ok 265 Set VL 1424
6158 13:38:28.386113 # ok 266 # SKIP Disabled ZA for VL 1424
6159 13:38:28.386260 # ok 267 # SKIP Get and set data for VL 1424
6160 13:38:28.386402 # ok 268 Set VL 1440
6161 13:38:28.386545 # ok 269 # SKIP Disabled ZA for VL 1440
6162 13:38:28.386688 # ok 270 # SKIP Get and set data for VL 1440
6163 13:38:28.386831 # ok 271 Set VL 1456
6164 13:38:28.386972 # ok 272 # SKIP Disabled ZA for VL 1456
6165 13:38:28.387115 # ok 273 # SKIP Get and set data for VL 1456
6166 13:38:28.387258 # ok 274 Set VL 1472
6167 13:38:28.387399 # ok 275 # SKIP Disabled ZA for VL 1472
6168 13:38:28.387544 # ok 276 # SKIP Get and set data for VL 1472
6169 13:38:28.387685 # ok 277 Set VL 1488
6170 13:38:28.387825 # ok 278 # SKIP Disabled ZA for VL 1488
6171 13:38:28.387967 # ok 279 # SKIP Get and set data for VL 1488
6172 13:38:28.388108 # ok 280 Set VL 1504
6173 13:38:28.388250 # ok 281 # SKIP Disabled ZA for VL 1504
6174 13:38:28.388392 # ok 282 # SKIP Get and set data for VL 1504
6175 13:38:28.388536 # ok 283 Set VL 1520
6176 13:38:28.388677 # ok 284 # SKIP Disabled ZA for VL 1520
6177 13:38:28.388818 # ok 285 # SKIP Get and set data for VL 1520
6178 13:38:28.388960 # ok 286 Set VL 1536
6179 13:38:28.389101 # ok 287 # SKIP Disabled ZA for VL 1536
6180 13:38:28.389243 # ok 288 # SKIP Get and set data for VL 1536
6181 13:38:28.392045 # ok 289 Set VL 1552
6182 13:38:28.392374 # ok 290 # SKIP Disabled ZA for VL 1552
6183 13:38:28.392485 # ok 291 # SKIP Get and set data for VL 1552
6184 13:38:28.392576 # ok 292 Set VL 1568
6185 13:38:28.392661 # ok 293 # SKIP Disabled ZA for VL 1568
6186 13:38:28.392765 # ok 294 # SKIP Get and set data for VL 1568
6187 13:38:28.392856 # ok 295 Set VL 1584
6188 13:38:28.392942 # ok 296 # SKIP Disabled ZA for VL 1584
6189 13:38:28.393025 # ok 297 # SKIP Get and set data for VL 1584
6190 13:38:28.393128 # ok 298 Set VL 1600
6191 13:38:28.393213 # ok 299 # SKIP Disabled ZA for VL 1600
6192 13:38:28.393298 # ok 300 # SKIP Get and set data for VL 1600
6193 13:38:28.393399 # ok 301 Set VL 1616
6194 13:38:28.393491 # ok 302 # SKIP Disabled ZA for VL 1616
6195 13:38:28.393597 # ok 303 # SKIP Get and set data for VL 1616
6196 13:38:28.393707 # ok 304 Set VL 1632
6197 13:38:28.393795 # ok 305 # SKIP Disabled ZA for VL 1632
6198 13:38:28.393897 # ok 306 # SKIP Get and set data for VL 1632
6199 13:38:28.393985 # ok 307 Set VL 1648
6200 13:38:28.394086 # ok 308 # SKIP Disabled ZA for VL 1648
6201 13:38:28.394189 # ok 309 # SKIP Get and set data for VL 1648
6202 13:38:28.394290 # ok 310 Set VL 1664
6203 13:38:28.394377 # ok 311 # SKIP Disabled ZA for VL 1664
6204 13:38:28.394480 # ok 312 # SKIP Get and set data for VL 1664
6205 13:38:28.394584 # ok 313 Set VL 1680
6206 13:38:28.394682 # ok 314 # SKIP Disabled ZA for VL 1680
6207 13:38:28.394784 # ok 315 # SKIP Get and set data for VL 1680
6208 13:38:28.394887 # ok 316 Set VL 1696
6209 13:38:28.394988 # ok 317 # SKIP Disabled ZA for VL 1696
6210 13:38:28.395492 # ok 318 # SKIP Get and set data for VL 1696
6211 13:38:28.395593 # ok 319 Set VL 1712
6212 13:38:28.395679 # ok 320 # SKIP Disabled ZA for VL 1712
6213 13:38:28.397038 # ok 321 # SKIP Get and set data for VL 1712
6214 13:38:28.397482 # ok 322 Set VL 1728
6215 13:38:28.397689 # ok 323 # SKIP Disabled ZA for VL 1728
6216 13:38:28.397854 # ok 324 # SKIP Get and set data for VL 1728
6217 13:38:28.398023 # ok 325 Set VL 1744
6218 13:38:28.398215 # ok 326 # SKIP Disabled ZA for VL 1744
6219 13:38:28.398361 # ok 327 # SKIP Get and set data for VL 1744
6220 13:38:28.398481 # ok 328 Set VL 1760
6221 13:38:28.398663 # ok 329 # SKIP Disabled ZA for VL 1760
6222 13:38:28.398812 # ok 330 # SKIP Get and set data for VL 1760
6223 13:38:28.398965 # ok 331 Set VL 1776
6224 13:38:28.399152 # ok 332 # SKIP Disabled ZA for VL 1776
6225 13:38:28.399318 # ok 333 # SKIP Get and set data for VL 1776
6226 13:38:28.399479 # ok 334 Set VL 1792
6227 13:38:28.399609 # ok 335 # SKIP Disabled ZA for VL 1792
6228 13:38:28.399727 # ok 336 # SKIP Get and set data for VL 1792
6229 13:38:28.399842 # ok 337 Set VL 1808
6230 13:38:28.399956 # ok 338 # SKIP Disabled ZA for VL 1808
6231 13:38:28.400073 # ok 339 # SKIP Get and set data for VL 1808
6232 13:38:28.400188 # ok 340 Set VL 1824
6233 13:38:28.400337 # ok 341 # SKIP Disabled ZA for VL 1824
6234 13:38:28.400462 # ok 342 # SKIP Get and set data for VL 1824
6235 13:38:28.400582 # ok 343 Set VL 1840
6236 13:38:28.400697 # ok 344 # SKIP Disabled ZA for VL 1840
6237 13:38:28.400813 # ok 345 # SKIP Get and set data for VL 1840
6238 13:38:28.400928 # ok 346 Set VL 1856
6239 13:38:28.401044 # ok 347 # SKIP Disabled ZA for VL 1856
6240 13:38:28.401159 # ok 348 # SKIP Get and set data for VL 1856
6241 13:38:28.401274 # ok 349 Set VL 1872
6242 13:38:28.448064 # ok 350 # SKIP Disabled ZA for VL 1872
6243 13:38:28.448421 # ok 351 # SKIP Get and set data for VL 1872
6244 13:38:28.448852 # ok 352 Set VL 1888
6245 13:38:28.449016 # ok 353 # SKIP Disabled ZA for VL 1888
6246 13:38:28.449192 # ok 354 # SKIP Get and set data for VL 1888
6247 13:38:28.449393 # ok 355 Set VL 1904
6248 13:38:28.449577 # ok 356 # SKIP Disabled ZA for VL 1904
6249 13:38:28.449762 # ok 357 # SKIP Get and set data for VL 1904
6250 13:38:28.449930 # ok 358 Set VL 1920
6251 13:38:28.450134 # ok 359 # SKIP Disabled ZA for VL 1920
6252 13:38:28.450314 # ok 360 # SKIP Get and set data for VL 1920
6253 13:38:28.450485 # ok 361 Set VL 1936
6254 13:38:28.450655 # ok 362 # SKIP Disabled ZA for VL 1936
6255 13:38:28.450825 # ok 363 # SKIP Get and set data for VL 1936
6256 13:38:28.451035 # ok 364 Set VL 1952
6257 13:38:28.451207 # ok 365 # SKIP Disabled ZA for VL 1952
6258 13:38:28.451368 # ok 366 # SKIP Get and set data for VL 1952
6259 13:38:28.451524 # ok 367 Set VL 1968
6260 13:38:28.451654 # ok 368 # SKIP Disabled ZA for VL 1968
6261 13:38:28.451770 # ok 369 # SKIP Get and set data for VL 1968
6262 13:38:28.451884 # ok 370 Set VL 1984
6263 13:38:28.451998 # ok 371 # SKIP Disabled ZA for VL 1984
6264 13:38:28.452111 # ok 372 # SKIP Get and set data for VL 1984
6265 13:38:28.452225 # ok 373 Set VL 2000
6266 13:38:28.452339 # ok 374 # SKIP Disabled ZA for VL 2000
6267 13:38:28.452453 # ok 375 # SKIP Get and set data for VL 2000
6268 13:38:28.452568 # ok 376 Set VL 2016
6269 13:38:28.452708 # ok 377 # SKIP Disabled ZA for VL 2016
6270 13:38:28.452828 # ok 378 # SKIP Get and set data for VL 2016
6271 13:38:28.452944 # ok 379 Set VL 2032
6272 13:38:28.453057 # ok 380 # SKIP Disabled ZA for VL 2032
6273 13:38:28.464974 # ok 381 # SKIP Get and set data for VL 2032
6274 13:38:28.465215 # ok 382 Set VL 2048
6275 13:38:28.465561 # ok 383 # SKIP Disabled ZA for VL 2048
6276 13:38:28.465778 # ok 384 # SKIP Get and set data for VL 2048
6277 13:38:28.465946 # ok 385 Set VL 2064
6278 13:38:28.466132 # ok 386 # SKIP Disabled ZA for VL 2064
6279 13:38:28.466360 # ok 387 # SKIP Get and set data for VL 2064
6280 13:38:28.466577 # ok 388 Set VL 2080
6281 13:38:28.466821 # ok 389 # SKIP Disabled ZA for VL 2080
6282 13:38:28.467030 # ok 390 # SKIP Get and set data for VL 2080
6283 13:38:28.467245 # ok 391 Set VL 2096
6284 13:38:28.467467 # ok 392 # SKIP Disabled ZA for VL 2096
6285 13:38:28.467628 # ok 393 # SKIP Get and set data for VL 2096
6286 13:38:28.467751 # ok 394 Set VL 2112
6287 13:38:28.467864 # ok 395 # SKIP Disabled ZA for VL 2112
6288 13:38:28.467977 # ok 396 # SKIP Get and set data for VL 2112
6289 13:38:28.468133 # ok 397 Set VL 2128
6290 13:38:28.468260 # ok 398 # SKIP Disabled ZA for VL 2128
6291 13:38:28.468375 # ok 399 # SKIP Get and set data for VL 2128
6292 13:38:28.468487 # ok 400 Set VL 2144
6293 13:38:28.468600 # ok 401 # SKIP Disabled ZA for VL 2144
6294 13:38:28.468745 # ok 402 # SKIP Get and set data for VL 2144
6295 13:38:28.468868 # ok 403 Set VL 2160
6296 13:38:28.468983 # ok 404 # SKIP Disabled ZA for VL 2160
6297 13:38:28.469095 # ok 405 # SKIP Get and set data for VL 2160
6298 13:38:28.469208 # ok 406 Set VL 2176
6299 13:38:28.469319 # ok 407 # SKIP Disabled ZA for VL 2176
6300 13:38:28.469430 # ok 408 # SKIP Get and set data for VL 2176
6301 13:38:28.469541 # ok 409 Set VL 2192
6302 13:38:28.472470 # ok 410 # SKIP Disabled ZA for VL 2192
6303 13:38:28.472715 # ok 411 # SKIP Get and set data for VL 2192
6304 13:38:28.473196 # ok 412 Set VL 2208
6305 13:38:28.473420 # ok 413 # SKIP Disabled ZA for VL 2208
6306 13:38:28.473693 # ok 414 # SKIP Get and set data for VL 2208
6307 13:38:28.473891 # ok 415 Set VL 2224
6308 13:38:28.474105 # ok 416 # SKIP Disabled ZA for VL 2224
6309 13:38:28.474335 # ok 417 # SKIP Get and set data for VL 2224
6310 13:38:28.474544 # ok 418 Set VL 2240
6311 13:38:28.474792 # ok 419 # SKIP Disabled ZA for VL 2240
6312 13:38:28.475000 # ok 420 # SKIP Get and set data for VL 2240
6313 13:38:28.475220 # ok 421 Set VL 2256
6314 13:38:28.475435 # ok 422 # SKIP Disabled ZA for VL 2256
6315 13:38:28.475637 # ok 423 # SKIP Get and set data for VL 2256
6316 13:38:28.475774 # ok 424 Set VL 2272
6317 13:38:28.475893 # ok 425 # SKIP Disabled ZA for VL 2272
6318 13:38:28.476008 # ok 426 # SKIP Get and set data for VL 2272
6319 13:38:28.476123 # ok 427 Set VL 2288
6320 13:38:28.476239 # ok 428 # SKIP Disabled ZA for VL 2288
6321 13:38:28.476421 # ok 429 # SKIP Get and set data for VL 2288
6322 13:38:28.476556 # ok 430 Set VL 2304
6323 13:38:28.476671 # ok 431 # SKIP Disabled ZA for VL 2304
6324 13:38:28.476783 # ok 432 # SKIP Get and set data for VL 2304
6325 13:38:28.476893 # ok 433 Set VL 2320
6326 13:38:28.477004 # ok 434 # SKIP Disabled ZA for VL 2320
6327 13:38:28.477144 # ok 435 # SKIP Get and set data for VL 2320
6328 13:38:28.477265 # ok 436 Set VL 2336
6329 13:38:28.477379 # ok 437 # SKIP Disabled ZA for VL 2336
6330 13:38:28.477491 # ok 438 # SKIP Get and set data for VL 2336
6331 13:38:28.477604 # ok 439 Set VL 2352
6332 13:38:28.477825 # ok 440 # SKIP Disabled ZA for VL 2352
6333 13:38:28.478023 # ok 441 # SKIP Get and set data for VL 2352
6334 13:38:28.478209 # ok 442 Set VL 2368
6335 13:38:28.478393 # ok 443 # SKIP Disabled ZA for VL 2368
6336 13:38:28.478576 # ok 444 # SKIP Get and set data for VL 2368
6337 13:38:28.480747 # ok 445 Set VL 2384
6338 13:38:28.480863 # ok 446 # SKIP Disabled ZA for VL 2384
6339 13:38:28.480985 # ok 447 # SKIP Get and set data for VL 2384
6340 13:38:28.481062 # ok 448 Set VL 2400
6341 13:38:28.481162 # ok 449 # SKIP Disabled ZA for VL 2400
6342 13:38:28.481268 # ok 450 # SKIP Get and set data for VL 2400
6343 13:38:28.481370 # ok 451 Set VL 2416
6344 13:38:28.481468 # ok 452 # SKIP Disabled ZA for VL 2416
6345 13:38:28.481782 # ok 453 # SKIP Get and set data for VL 2416
6346 13:38:28.481875 # ok 454 Set VL 2432
6347 13:38:28.481994 # ok 455 # SKIP Disabled ZA for VL 2432
6348 13:38:28.482091 # ok 456 # SKIP Get and set data for VL 2432
6349 13:38:28.482197 # ok 457 Set VL 2448
6350 13:38:28.482507 # ok 458 # SKIP Disabled ZA for VL 2448
6351 13:38:28.482608 # ok 459 # SKIP Get and set data for VL 2448
6352 13:38:28.482712 # ok 460 Set VL 2464
6353 13:38:28.482806 # ok 461 # SKIP Disabled ZA for VL 2464
6354 13:38:28.482887 # ok 462 # SKIP Get and set data for VL 2464
6355 13:38:28.482956 # ok 463 Set VL 2480
6356 13:38:28.483053 # ok 464 # SKIP Disabled ZA for VL 2480
6357 13:38:28.483137 # ok 465 # SKIP Get and set data for VL 2480
6358 13:38:28.483238 # ok 466 Set VL 2496
6359 13:38:28.483317 # ok 467 # SKIP Disabled ZA for VL 2496
6360 13:38:28.483414 # ok 468 # SKIP Get and set data for VL 2496
6361 13:38:28.483510 # ok 469 Set VL 2512
6362 13:38:28.483592 # ok 470 # SKIP Disabled ZA for VL 2512
6363 13:38:28.488818 # ok 471 # SKIP Get and set data for VL 2512
6364 13:38:28.488992 # ok 472 Set VL 2528
6365 13:38:28.489081 # ok 473 # SKIP Disabled ZA for VL 2528
6366 13:38:28.489181 # ok 474 # SKIP Get and set data for VL 2528
6367 13:38:28.489269 # ok 475 Set VL 2544
6368 13:38:28.489352 # ok 476 # SKIP Disabled ZA for VL 2544
6369 13:38:28.489449 # ok 477 # SKIP Get and set data for VL 2544
6370 13:38:28.489538 # ok 478 Set VL 2560
6371 13:38:28.489614 # ok 479 # SKIP Disabled ZA for VL 2560
6372 13:38:28.489724 # ok 480 # SKIP Get and set data for VL 2560
6373 13:38:28.489805 # ok 481 Set VL 2576
6374 13:38:28.489905 # ok 482 # SKIP Disabled ZA for VL 2576
6375 13:38:28.489990 # ok 483 # SKIP Get and set data for VL 2576
6376 13:38:28.490072 # ok 484 Set VL 2592
6377 13:38:28.490156 # ok 485 # SKIP Disabled ZA for VL 2592
6378 13:38:28.490223 # ok 486 # SKIP Get and set data for VL 2592
6379 13:38:28.490285 # ok 487 Set VL 2608
6380 13:38:28.490375 # ok 488 # SKIP Disabled ZA for VL 2608
6381 13:38:28.490451 # ok 489 # SKIP Get and set data for VL 2608
6382 13:38:28.490533 # ok 490 Set VL 2624
6383 13:38:28.490618 # ok 491 # SKIP Disabled ZA for VL 2624
6384 13:38:28.490705 # ok 492 # SKIP Get and set data for VL 2624
6385 13:38:28.490805 # ok 493 Set VL 2640
6386 13:38:28.490886 # ok 494 # SKIP Disabled ZA for VL 2640
6387 13:38:28.490983 # ok 495 # SKIP Get and set data for VL 2640
6388 13:38:28.491062 # ok 496 Set VL 2656
6389 13:38:28.491150 # ok 497 # SKIP Disabled ZA for VL 2656
6390 13:38:28.491229 # ok 498 # SKIP Get and set data for VL 2656
6391 13:38:28.491324 # ok 499 Set VL 2672
6392 13:38:28.491402 # ok 500 # SKIP Disabled ZA for VL 2672
6393 13:38:28.491509 # ok 501 # SKIP Get and set data for VL 2672
6394 13:38:28.491579 # ok 502 Set VL 2688
6395 13:38:28.491639 # ok 503 # SKIP Disabled ZA for VL 2688
6396 13:38:28.495044 # ok 504 # SKIP Get and set data for VL 2688
6397 13:38:28.495205 # ok 505 Set VL 2704
6398 13:38:28.495309 # ok 506 # SKIP Disabled ZA for VL 2704
6399 13:38:28.495501 # ok 507 # SKIP Get and set data for VL 2704
6400 13:38:28.495620 # ok 508 Set VL 2720
6401 13:38:28.495764 # ok 509 # SKIP Disabled ZA for VL 2720
6402 13:38:28.495909 # ok 510 # SKIP Get and set data for VL 2720
6403 13:38:28.496051 # ok 511 Set VL 2736
6404 13:38:28.496225 # ok 512 # SKIP Disabled ZA for VL 2736
6405 13:38:28.498383 # ok 513 # SKIP Get and set data for VL 2736
6406 13:38:28.498841 # ok 514 Set VL 2752
6407 13:38:28.499040 # ok 515 # SKIP Disabled ZA for VL 2752
6408 13:38:28.499205 # ok 516 # SKIP Get and set data for VL 2752
6409 13:38:28.499374 # ok 517 Set VL 2768
6410 13:38:28.499537 # ok 518 # SKIP Disabled ZA for VL 2768
6411 13:38:28.499705 # ok 519 # SKIP Get and set data for VL 2768
6412 13:38:28.499829 # ok 520 Set VL 2784
6413 13:38:28.499945 # ok 521 # SKIP Disabled ZA for VL 2784
6414 13:38:28.500059 # ok 522 # SKIP Get and set data for VL 2784
6415 13:38:28.500173 # ok 523 Set VL 2800
6416 13:38:28.500288 # ok 524 # SKIP Disabled ZA for VL 2800
6417 13:38:28.503207 # ok 525 # SKIP Get and set data for VL 2800
6418 13:38:28.503500 # ok 526 Set VL 2816
6419 13:38:28.503889 # ok 527 # SKIP Disabled ZA for VL 2816
6420 13:38:28.504052 # ok 528 # SKIP Get and set data for VL 2816
6421 13:38:28.504181 # ok 529 Set VL 2832
6422 13:38:28.504326 # ok 530 # SKIP Disabled ZA for VL 2832
6423 13:38:28.504539 # ok 531 # SKIP Get and set data for VL 2832
6424 13:38:28.504753 # ok 532 Set VL 2848
6425 13:38:28.504965 # ok 533 # SKIP Disabled ZA for VL 2848
6426 13:38:28.505175 # ok 534 # SKIP Get and set data for VL 2848
6427 13:38:28.505362 # ok 535 Set VL 2864
6428 13:38:28.505553 # ok 536 # SKIP Disabled ZA for VL 2864
6429 13:38:28.505752 # ok 537 # SKIP Get and set data for VL 2864
6430 13:38:28.505932 # ok 538 Set VL 2880
6431 13:38:28.506162 # ok 539 # SKIP Disabled ZA for VL 2880
6432 13:38:28.506356 # ok 540 # SKIP Get and set data for VL 2880
6433 13:38:28.506545 # ok 541 Set VL 2896
6434 13:38:28.506727 # ok 542 # SKIP Disabled ZA for VL 2896
6435 13:38:28.506908 # ok 543 # SKIP Get and set data for VL 2896
6436 13:38:28.507094 # ok 544 Set VL 2912
6437 13:38:28.507278 # ok 545 # SKIP Disabled ZA for VL 2912
6438 13:38:28.507459 # ok 546 # SKIP Get and set data for VL 2912
6439 13:38:28.507639 # ok 547 Set VL 2928
6440 13:38:28.507799 # ok 548 # SKIP Disabled ZA for VL 2928
6441 13:38:28.507931 # ok 549 # SKIP Get and set data for VL 2928
6442 13:38:28.508046 # ok 550 Set VL 2944
6443 13:38:28.508160 # ok 551 # SKIP Disabled ZA for VL 2944
6444 13:38:28.508278 # ok 552 # SKIP Get and set data for VL 2944
6445 13:38:28.508432 # ok 553 Set VL 2960
6446 13:38:28.508655 # ok 554 # SKIP Disabled ZA for VL 2960
6447 13:38:28.508849 # ok 555 # SKIP Get and set data for VL 2960
6448 13:38:28.509036 # ok 556 Set VL 2976
6449 13:38:28.509223 # ok 557 # SKIP Disabled ZA for VL 2976
6450 13:38:28.509408 # ok 558 # SKIP Get and set data for VL 2976
6451 13:38:28.509574 # ok 559 Set VL 2992
6452 13:38:28.510822 # ok 560 # SKIP Disabled ZA for VL 2992
6453 13:38:28.511029 # ok 561 # SKIP Get and set data for VL 2992
6454 13:38:28.511221 # ok 562 Set VL 3008
6455 13:38:28.511411 # ok 563 # SKIP Disabled ZA for VL 3008
6456 13:38:28.511604 # ok 564 # SKIP Get and set data for VL 3008
6457 13:38:28.511796 # ok 565 Set VL 3024
6458 13:38:28.511986 # ok 566 # SKIP Disabled ZA for VL 3024
6459 13:38:28.512169 # ok 567 # SKIP Get and set data for VL 3024
6460 13:38:28.512342 # ok 568 Set VL 3040
6461 13:38:28.512529 # ok 569 # SKIP Disabled ZA for VL 3040
6462 13:38:28.512668 # ok 570 # SKIP Get and set data for VL 3040
6463 13:38:28.512842 # ok 571 Set VL 3056
6464 13:38:28.512981 # ok 572 # SKIP Disabled ZA for VL 3056
6465 13:38:28.513123 # ok 573 # SKIP Get and set data for VL 3056
6466 13:38:28.513296 # ok 574 Set VL 3072
6467 13:38:28.513433 # ok 575 # SKIP Disabled ZA for VL 3072
6468 13:38:28.513577 # ok 576 # SKIP Get and set data for VL 3072
6469 13:38:28.513763 # ok 577 Set VL 3088
6470 13:38:28.513954 # ok 578 # SKIP Disabled ZA for VL 3088
6471 13:38:28.514158 # ok 579 # SKIP Get and set data for VL 3088
6472 13:38:28.514521 # ok 580 Set VL 3104
6473 13:38:28.514662 # ok 581 # SKIP Disabled ZA for VL 3104
6474 13:38:28.514807 # ok 582 # SKIP Get and set data for VL 3104
6475 13:38:28.514951 # ok 583 Set VL 3120
6476 13:38:28.515093 # ok 584 # SKIP Disabled ZA for VL 3120
6477 13:38:28.515249 # ok 585 # SKIP Get and set data for VL 3120
6478 13:38:28.515414 # ok 586 Set VL 3136
6479 13:38:28.515579 # ok 587 # SKIP Disabled ZA for VL 3136
6480 13:38:28.515713 # ok 588 # SKIP Get and set data for VL 3136
6481 13:38:28.515832 # ok 589 Set VL 3152
6482 13:38:28.515976 # ok 590 # SKIP Disabled ZA for VL 3152
6483 13:38:28.516101 # ok 591 # SKIP Get and set data for VL 3152
6484 13:38:28.516220 # ok 592 Set VL 3168
6485 13:38:28.516336 # ok 593 # SKIP Disabled ZA for VL 3168
6486 13:38:28.516454 # ok 594 # SKIP Get and set data for VL 3168
6487 13:38:28.520601 # ok 595 Set VL 3184
6488 13:38:28.521001 # ok 596 # SKIP Disabled ZA for VL 3184
6489 13:38:28.521170 # ok 597 # SKIP Get and set data for VL 3184
6490 13:38:28.521311 # ok 598 Set VL 3200
6491 13:38:28.521437 # ok 599 # SKIP Disabled ZA for VL 3200
6492 13:38:28.521591 # ok 600 # SKIP Get and set data for VL 3200
6493 13:38:28.521759 # ok 601 Set VL 3216
6494 13:38:28.521905 # ok 602 # SKIP Disabled ZA for VL 3216
6495 13:38:28.522071 # ok 603 # SKIP Get and set data for VL 3216
6496 13:38:28.522213 # ok 604 Set VL 3232
6497 13:38:28.522343 # ok 605 # SKIP Disabled ZA for VL 3232
6498 13:38:28.522469 # ok 606 # SKIP Get and set data for VL 3232
6499 13:38:28.522595 # ok 607 Set VL 3248
6500 13:38:28.522755 # ok 608 # SKIP Disabled ZA for VL 3248
6501 13:38:28.522890 # ok 609 # SKIP Get and set data for VL 3248
6502 13:38:28.523017 # ok 610 Set VL 3264
6503 13:38:28.523148 # ok 611 # SKIP Disabled ZA for VL 3264
6504 13:38:28.523323 # ok 612 # SKIP Get and set data for VL 3264
6505 13:38:28.523474 # ok 613 Set VL 3280
6506 13:38:28.523645 # ok 614 # SKIP Disabled ZA for VL 3280
6507 13:38:28.523791 # ok 615 # SKIP Get and set data for VL 3280
6508 13:38:28.523934 # ok 616 Set VL 3296
6509 13:38:28.524075 # ok 617 # SKIP Disabled ZA for VL 3296
6510 13:38:28.524216 # ok 618 # SKIP Get and set data for VL 3296
6511 13:38:28.524357 # ok 619 Set VL 3312
6512 13:38:28.524536 # ok 620 # SKIP Disabled ZA for VL 3312
6513 13:38:28.524674 # ok 621 # SKIP Get and set data for VL 3312
6514 13:38:28.524820 # ok 622 Set VL 3328
6515 13:38:28.524963 # ok 623 # SKIP Disabled ZA for VL 3328
6516 13:38:28.525105 # ok 624 # SKIP Get and set data for VL 3328
6517 13:38:28.525246 # ok 625 Set VL 3344
6518 13:38:28.525388 # ok 626 # SKIP Disabled ZA for VL 3344
6519 13:38:28.525530 # ok 627 # SKIP Get and set data for VL 3344
6520 13:38:28.528389 # ok 628 Set VL 3360
6521 13:38:28.528789 # ok 629 # SKIP Disabled ZA for VL 3360
6522 13:38:28.528942 # ok 630 # SKIP Get and set data for VL 3360
6523 13:38:28.529079 # ok 631 Set VL 3376
6524 13:38:28.529238 # ok 632 # SKIP Disabled ZA for VL 3376
6525 13:38:28.529375 # ok 633 # SKIP Get and set data for VL 3376
6526 13:38:28.529509 # ok 634 Set VL 3392
6527 13:38:28.529655 # ok 635 # SKIP Disabled ZA for VL 3392
6528 13:38:28.529864 # ok 636 # SKIP Get and set data for VL 3392
6529 13:38:28.530043 # ok 637 Set VL 3408
6530 13:38:28.530177 # ok 638 # SKIP Disabled ZA for VL 3408
6531 13:38:28.530311 # ok 639 # SKIP Get and set data for VL 3408
6532 13:38:28.530487 # ok 640 Set VL 3424
6533 13:38:28.530631 # ok 641 # SKIP Disabled ZA for VL 3424
6534 13:38:28.530774 # ok 642 # SKIP Get and set data for VL 3424
6535 13:38:28.530918 # ok 643 Set VL 3440
6536 13:38:28.531060 # ok 644 # SKIP Disabled ZA for VL 3440
6537 13:38:28.531240 # ok 645 # SKIP Get and set data for VL 3440
6538 13:38:28.531377 # ok 646 Set VL 3456
6539 13:38:28.531521 # ok 647 # SKIP Disabled ZA for VL 3456
6540 13:38:28.531665 # ok 648 # SKIP Get and set data for VL 3456
6541 13:38:28.531809 # ok 649 Set VL 3472
6542 13:38:28.531950 # ok 650 # SKIP Disabled ZA for VL 3472
6543 13:38:28.532091 # ok 651 # SKIP Get and set data for VL 3472
6544 13:38:28.532231 # ok 652 Set VL 3488
6545 13:38:28.532371 # ok 653 # SKIP Disabled ZA for VL 3488
6546 13:38:28.532512 # ok 654 # SKIP Get and set data for VL 3488
6547 13:38:28.532652 # ok 655 Set VL 3504
6548 13:38:28.532838 # ok 656 # SKIP Disabled ZA for VL 3504
6549 13:38:28.533062 # ok 657 # SKIP Get and set data for VL 3504
6550 13:38:28.533249 # ok 658 Set VL 3520
6551 13:38:28.533426 # ok 659 # SKIP Disabled ZA for VL 3520
6552 13:38:28.533591 # ok 660 # SKIP Get and set data for VL 3520
6553 13:38:28.535009 # ok 661 Set VL 3536
6554 13:38:28.535352 # ok 662 # SKIP Disabled ZA for VL 3536
6555 13:38:28.535522 # ok 663 # SKIP Get and set data for VL 3536
6556 13:38:28.535700 # ok 664 Set VL 3552
6557 13:38:28.535859 # ok 665 # SKIP Disabled ZA for VL 3552
6558 13:38:28.535987 # ok 666 # SKIP Get and set data for VL 3552
6559 13:38:28.536108 # ok 667 Set VL 3568
6560 13:38:28.536455 # ok 668 # SKIP Disabled ZA for VL 3568
6561 13:38:28.536637 # ok 669 # SKIP Get and set data for VL 3568
6562 13:38:28.536782 # ok 670 Set VL 3584
6563 13:38:28.536938 # ok 671 # SKIP Disabled ZA for VL 3584
6564 13:38:28.537075 # ok 672 # SKIP Get and set data for VL 3584
6565 13:38:28.537206 # ok 673 Set VL 3600
6566 13:38:28.537360 # ok 674 # SKIP Disabled ZA for VL 3600
6567 13:38:28.537492 # ok 675 # SKIP Get and set data for VL 3600
6568 13:38:28.537619 # ok 676 Set VL 3616
6569 13:38:28.537765 # ok 677 # SKIP Disabled ZA for VL 3616
6570 13:38:28.537919 # ok 678 # SKIP Get and set data for VL 3616
6571 13:38:28.538054 # ok 679 Set VL 3632
6572 13:38:28.538182 # ok 680 # SKIP Disabled ZA for VL 3632
6573 13:38:28.538333 # ok 681 # SKIP Get and set data for VL 3632
6574 13:38:28.538464 # ok 682 Set VL 3648
6575 13:38:28.538590 # ok 683 # SKIP Disabled ZA for VL 3648
6576 13:38:28.538718 # ok 684 # SKIP Get and set data for VL 3648
6577 13:38:28.538848 # ok 685 Set VL 3664
6578 13:38:28.539000 # ok 686 # SKIP Disabled ZA for VL 3664
6579 13:38:28.539135 # ok 687 # SKIP Get and set data for VL 3664
6580 13:38:28.539260 # ok 688 Set VL 3680
6581 13:38:28.539387 # ok 689 # SKIP Disabled ZA for VL 3680
6582 13:38:28.539511 # ok 690 # SKIP Get and set data for VL 3680
6583 13:38:28.539638 # ok 691 Set VL 3696
6584 13:38:28.539758 # ok 692 # SKIP Disabled ZA for VL 3696
6585 13:38:28.539898 # ok 693 # SKIP Get and set data for VL 3696
6586 13:38:28.540017 # ok 694 Set VL 3712
6587 13:38:28.540131 # ok 695 # SKIP Disabled ZA for VL 3712
6588 13:38:28.540243 # ok 696 # SKIP Get and set data for VL 3712
6589 13:38:28.540356 # ok 697 Set VL 3728
6590 13:38:28.540468 # ok 698 # SKIP Disabled ZA for VL 3728
6591 13:38:28.540581 # ok 699 # SKIP Get and set data for VL 3728
6592 13:38:28.544298 # ok 700 Set VL 3744
6593 13:38:28.544759 # ok 701 # SKIP Disabled ZA for VL 3744
6594 13:38:28.544904 # ok 702 # SKIP Get and set data for VL 3744
6595 13:38:28.545034 # ok 703 Set VL 3760
6596 13:38:28.545161 # ok 704 # SKIP Disabled ZA for VL 3760
6597 13:38:28.545312 # ok 705 # SKIP Get and set data for VL 3760
6598 13:38:28.545441 # ok 706 Set VL 3776
6599 13:38:28.545566 # ok 707 # SKIP Disabled ZA for VL 3776
6600 13:38:28.545745 # ok 708 # SKIP Get and set data for VL 3776
6601 13:38:28.545889 # ok 709 Set VL 3792
6602 13:38:28.546037 # ok 710 # SKIP Disabled ZA for VL 3792
6603 13:38:28.546160 # ok 711 # SKIP Get and set data for VL 3792
6604 13:38:28.546275 # ok 712 Set VL 3808
6605 13:38:28.546388 # ok 713 # SKIP Disabled ZA for VL 3808
6606 13:38:28.546503 # ok 714 # SKIP Get and set data for VL 3808
6607 13:38:28.546616 # ok 715 Set VL 3824
6608 13:38:28.546726 # ok 716 # SKIP Disabled ZA for VL 3824
6609 13:38:28.546840 # ok 717 # SKIP Get and set data for VL 3824
6610 13:38:28.546953 # ok 718 Set VL 3840
6611 13:38:28.547094 # ok 719 # SKIP Disabled ZA for VL 3840
6612 13:38:28.547213 # ok 720 # SKIP Get and set data for VL 3840
6613 13:38:28.547327 # ok 721 Set VL 3856
6614 13:38:28.547462 # ok 722 # SKIP Disabled ZA for VL 3856
6615 13:38:28.547607 # ok 723 # SKIP Get and set data for VL 3856
6616 13:38:28.547726 # ok 724 Set VL 3872
6617 13:38:28.547843 # ok 725 # SKIP Disabled ZA for VL 3872
6618 13:38:28.547959 # ok 726 # SKIP Get and set data for VL 3872
6619 13:38:28.548073 # ok 727 Set VL 3888
6620 13:38:28.548186 # ok 728 # SKIP Disabled ZA for VL 3888
6621 13:38:28.548300 # ok 729 # SKIP Get and set data for VL 3888
6622 13:38:28.548444 # ok 730 Set VL 3904
6623 13:38:28.548588 # ok 731 # SKIP Disabled ZA for VL 3904
6624 13:38:28.548710 # ok 732 # SKIP Get and set data for VL 3904
6625 13:38:28.548870 # ok 733 Set VL 3920
6626 13:38:28.549004 # ok 734 # SKIP Disabled ZA for VL 3920
6627 13:38:28.549121 # ok 735 # SKIP Get and set data for VL 3920
6628 13:38:28.565477 # ok 736 Set VL 3936
6629 13:38:28.565789 # ok 737 # SKIP Disabled ZA for VL 3936
6630 13:38:28.565957 # ok 738 # SKIP Get and set data for VL 3936
6631 13:38:28.566114 # ok 739 Set VL 3952
6632 13:38:28.566488 # ok 740 # SKIP Disabled ZA for VL 3952
6633 13:38:28.566655 # ok 741 # SKIP Get and set data for VL 3952
6634 13:38:28.566819 # ok 742 Set VL 3968
6635 13:38:28.566968 # ok 743 # SKIP Disabled ZA for VL 3968
6636 13:38:28.567131 # ok 744 # SKIP Get and set data for VL 3968
6637 13:38:28.567286 # ok 745 Set VL 3984
6638 13:38:28.567446 # ok 746 # SKIP Disabled ZA for VL 3984
6639 13:38:28.567607 # ok 747 # SKIP Get and set data for VL 3984
6640 13:38:28.567758 # ok 748 Set VL 4000
6641 13:38:28.567880 # ok 749 # SKIP Disabled ZA for VL 4000
6642 13:38:28.567998 # ok 750 # SKIP Get and set data for VL 4000
6643 13:38:28.568115 # ok 751 Set VL 4016
6644 13:38:28.568228 # ok 752 # SKIP Disabled ZA for VL 4016
6645 13:38:28.568342 # ok 753 # SKIP Get and set data for VL 4016
6646 13:38:28.568457 # ok 754 Set VL 4032
6647 13:38:28.568570 # ok 755 # SKIP Disabled ZA for VL 4032
6648 13:38:28.568684 # ok 756 # SKIP Get and set data for VL 4032
6649 13:38:28.568800 # ok 757 Set VL 4048
6650 13:38:28.568914 # ok 758 # SKIP Disabled ZA for VL 4048
6651 13:38:28.569029 # ok 759 # SKIP Get and set data for VL 4048
6652 13:38:28.580607 # ok 760 Set VL 4064
6653 13:38:28.581035 # ok 761 # SKIP Disabled ZA for VL 4064
6654 13:38:28.581223 # ok 762 # SKIP Get and set data for VL 4064
6655 13:38:28.581450 # ok 763 Set VL 4080
6656 13:38:28.581699 # ok 764 # SKIP Disabled ZA for VL 4080
6657 13:38:28.581938 # ok 765 # SKIP Get and set data for VL 4080
6658 13:38:28.582120 # ok 766 Set VL 4096
6659 13:38:28.582287 # ok 767 # SKIP Disabled ZA for VL 4096
6660 13:38:28.582456 # ok 768 # SKIP Get and set data for VL 4096
6661 13:38:28.582606 # ok 769 Set VL 4112
6662 13:38:28.582734 # ok 770 # SKIP Disabled ZA for VL 4112
6663 13:38:28.582939 # ok 771 # SKIP Get and set data for VL 4112
6664 13:38:28.583123 # ok 772 Set VL 4128
6665 13:38:28.583348 # ok 773 # SKIP Disabled ZA for VL 4128
6666 13:38:28.583545 # ok 774 # SKIP Get and set data for VL 4128
6667 13:38:28.583715 # ok 775 Set VL 4144
6668 13:38:28.583843 # ok 776 # SKIP Disabled ZA for VL 4144
6669 13:38:28.583961 # ok 777 # SKIP Get and set data for VL 4144
6670 13:38:28.584077 # ok 778 Set VL 4160
6671 13:38:28.584193 # ok 779 # SKIP Disabled ZA for VL 4160
6672 13:38:28.584309 # ok 780 # SKIP Get and set data for VL 4160
6673 13:38:28.584427 # ok 781 Set VL 4176
6674 13:38:28.584542 # ok 782 # SKIP Disabled ZA for VL 4176
6675 13:38:28.584656 # ok 783 # SKIP Get and set data for VL 4176
6676 13:38:28.584773 # ok 784 Set VL 4192
6677 13:38:28.584887 # ok 785 # SKIP Disabled ZA for VL 4192
6678 13:38:28.585029 # ok 786 # SKIP Get and set data for VL 4192
6679 13:38:28.585152 # ok 787 Set VL 4208
6680 13:38:28.585269 # ok 788 # SKIP Disabled ZA for VL 4208
6681 13:38:28.585384 # ok 789 # SKIP Get and set data for VL 4208
6682 13:38:28.597634 # ok 790 Set VL 4224
6683 13:38:28.597877 # ok 791 # SKIP Disabled ZA for VL 4224
6684 13:38:28.598266 # ok 792 # SKIP Get and set data for VL 4224
6685 13:38:28.598391 # ok 793 Set VL 4240
6686 13:38:28.598517 # ok 794 # SKIP Disabled ZA for VL 4240
6687 13:38:28.598618 # ok 795 # SKIP Get and set data for VL 4240
6688 13:38:28.598722 # ok 796 Set VL 4256
6689 13:38:28.598807 # ok 797 # SKIP Disabled ZA for VL 4256
6690 13:38:28.598900 # ok 798 # SKIP Get and set data for VL 4256
6691 13:38:28.598990 # ok 799 Set VL 4272
6692 13:38:28.599077 # ok 800 # SKIP Disabled ZA for VL 4272
6693 13:38:28.599148 # ok 801 # SKIP Get and set data for VL 4272
6694 13:38:28.599212 # ok 802 Set VL 4288
6695 13:38:28.599273 # ok 803 # SKIP Disabled ZA for VL 4288
6696 13:38:28.599335 # ok 804 # SKIP Get and set data for VL 4288
6697 13:38:28.599414 # ok 805 Set VL 4304
6698 13:38:28.599497 # ok 806 # SKIP Disabled ZA for VL 4304
6699 13:38:28.599570 # ok 807 # SKIP Get and set data for VL 4304
6700 13:38:28.599640 # ok 808 Set VL 4320
6701 13:38:28.599704 # ok 809 # SKIP Disabled ZA for VL 4320
6702 13:38:28.599802 # ok 810 # SKIP Get and set data for VL 4320
6703 13:38:28.599881 # ok 811 Set VL 4336
6704 13:38:28.599949 # ok 812 # SKIP Disabled ZA for VL 4336
6705 13:38:28.613432 # ok 813 # SKIP Get and set data for VL 4336
6706 13:38:28.613557 # ok 814 Set VL 4352
6707 13:38:28.613877 # ok 815 # SKIP Disabled ZA for VL 4352
6708 13:38:28.613981 # ok 816 # SKIP Get and set data for VL 4352
6709 13:38:28.614066 # ok 817 Set VL 4368
6710 13:38:28.614130 # ok 818 # SKIP Disabled ZA for VL 4368
6711 13:38:28.614191 # ok 819 # SKIP Get and set data for VL 4368
6712 13:38:28.614263 # ok 820 Set VL 4384
6713 13:38:28.614325 # ok 821 # SKIP Disabled ZA for VL 4384
6714 13:38:28.615411 # ok 822 # SKIP Get and set data for VL 4384
6715 13:38:28.615750 # ok 823 Set VL 4400
6716 13:38:28.615913 # ok 824 # SKIP Disabled ZA for VL 4400
6717 13:38:28.616035 # ok 825 # SKIP Get and set data for VL 4400
6718 13:38:28.628816 # ok 826 Set VL 4416
6719 13:38:28.628934 # ok 827 # SKIP Disabled ZA for VL 4416
6720 13:38:28.629218 # ok 828 # SKIP Get and set data for VL 4416
6721 13:38:28.629319 # ok 829 Set VL 4432
6722 13:38:28.629388 # ok 830 # SKIP Disabled ZA for VL 4432
6723 13:38:28.629464 # ok 831 # SKIP Get and set data for VL 4432
6724 13:38:28.629542 # ok 832 Set VL 4448
6725 13:38:28.629620 # ok 833 # SKIP Disabled ZA for VL 4448
6726 13:38:28.629721 # ok 834 # SKIP Get and set data for VL 4448
6727 13:38:28.629802 # ok 835 Set VL 4464
6728 13:38:28.629886 # ok 836 # SKIP Disabled ZA for VL 4464
6729 13:38:28.629984 # ok 837 # SKIP Get and set data for VL 4464
6730 13:38:28.630055 # ok 838 Set VL 4480
6731 13:38:28.630134 # ok 839 # SKIP Disabled ZA for VL 4480
6732 13:38:28.630199 # ok 840 # SKIP Get and set data for VL 4480
6733 13:38:28.630262 # ok 841 Set VL 4496
6734 13:38:28.630325 # ok 842 # SKIP Disabled ZA for VL 4496
6735 13:38:28.630399 # ok 843 # SKIP Get and set data for VL 4496
6736 13:38:28.630464 # ok 844 Set VL 4512
6737 13:38:28.630537 # ok 845 # SKIP Disabled ZA for VL 4512
6738 13:38:28.630785 # ok 846 # SKIP Get and set data for VL 4512
6739 13:38:28.630883 # ok 847 Set VL 4528
6740 13:38:28.630976 # ok 848 # SKIP Disabled ZA for VL 4528
6741 13:38:28.631065 # ok 849 # SKIP Get and set data for VL 4528
6742 13:38:28.631144 # ok 850 Set VL 4544
6743 13:38:28.631208 # ok 851 # SKIP Disabled ZA for VL 4544
6744 13:38:28.631298 # ok 852 # SKIP Get and set data for VL 4544
6745 13:38:28.631370 # ok 853 Set VL 4560
6746 13:38:28.631440 # ok 854 # SKIP Disabled ZA for VL 4560
6747 13:38:28.631514 # ok 855 # SKIP Get and set data for VL 4560
6748 13:38:28.631593 # ok 856 Set VL 4576
6749 13:38:28.631661 # ok 857 # SKIP Disabled ZA for VL 4576
6750 13:38:28.631737 # ok 858 # SKIP Get and set data for VL 4576
6751 13:38:28.645114 # ok 859 Set VL 4592
6752 13:38:28.645281 # ok 860 # SKIP Disabled ZA for VL 4592
6753 13:38:28.645698 # ok 861 # SKIP Get and set data for VL 4592
6754 13:38:28.645950 # ok 862 Set VL 4608
6755 13:38:28.646133 # ok 863 # SKIP Disabled ZA for VL 4608
6756 13:38:28.646299 # ok 864 # SKIP Get and set data for VL 4608
6757 13:38:28.646467 # ok 865 Set VL 4624
6758 13:38:28.646636 # ok 866 # SKIP Disabled ZA for VL 4624
6759 13:38:28.646833 # ok 867 # SKIP Get and set data for VL 4624
6760 13:38:28.647042 # ok 868 Set VL 4640
6761 13:38:28.647226 # ok 869 # SKIP Disabled ZA for VL 4640
6762 13:38:28.647405 # ok 870 # SKIP Get and set data for VL 4640
6763 13:38:28.647609 # ok 871 Set VL 4656
6764 13:38:28.647808 # ok 872 # SKIP Disabled ZA for VL 4656
6765 13:38:28.647989 # ok 873 # SKIP Get and set data for VL 4656
6766 13:38:28.648158 # ok 874 Set VL 4672
6767 13:38:28.648323 # ok 875 # SKIP Disabled ZA for VL 4672
6768 13:38:28.648487 # ok 876 # SKIP Get and set data for VL 4672
6769 13:38:28.648662 # ok 877 Set VL 4688
6770 13:38:28.648836 # ok 878 # SKIP Disabled ZA for VL 4688
6771 13:38:28.649009 # ok 879 # SKIP Get and set data for VL 4688
6772 13:38:28.649222 # ok 880 Set VL 4704
6773 13:38:28.649402 # ok 881 # SKIP Disabled ZA for VL 4704
6774 13:38:28.649573 # ok 882 # SKIP Get and set data for VL 4704
6775 13:38:28.649752 # ok 883 Set VL 4720
6776 13:38:28.649884 # ok 884 # SKIP Disabled ZA for VL 4720
6777 13:38:28.650001 # ok 885 # SKIP Get and set data for VL 4720
6778 13:38:28.650119 # ok 886 Set VL 4736
6779 13:38:28.650232 # ok 887 # SKIP Disabled ZA for VL 4736
6780 13:38:28.650350 # ok 888 # SKIP Get and set data for VL 4736
6781 13:38:28.650466 # ok 889 Set VL 4752
6782 13:38:28.657747 # ok 890 # SKIP Disabled ZA for VL 4752
6783 13:38:28.658156 # ok 891 # SKIP Get and set data for VL 4752
6784 13:38:28.658312 # ok 892 Set VL 4768
6785 13:38:28.658434 # ok 893 # SKIP Disabled ZA for VL 4768
6786 13:38:28.658558 # ok 894 # SKIP Get and set data for VL 4768
6787 13:38:28.658685 # ok 895 Set VL 4784
6788 13:38:28.658803 # ok 896 # SKIP Disabled ZA for VL 4784
6789 13:38:28.658946 # ok 897 # SKIP Get and set data for VL 4784
6790 13:38:28.659071 # ok 898 Set VL 4800
6791 13:38:28.659187 # ok 899 # SKIP Disabled ZA for VL 4800
6792 13:38:28.659302 # ok 900 # SKIP Get and set data for VL 4800
6793 13:38:28.659446 # ok 901 Set VL 4816
6794 13:38:28.659588 # ok 902 # SKIP Disabled ZA for VL 4816
6795 13:38:28.659713 # ok 903 # SKIP Get and set data for VL 4816
6796 13:38:28.659856 # ok 904 Set VL 4832
6797 13:38:28.659976 # ok 905 # SKIP Disabled ZA for VL 4832
6798 13:38:28.660092 # ok 906 # SKIP Get and set data for VL 4832
6799 13:38:28.660206 # ok 907 Set VL 4848
6800 13:38:28.660322 # ok 908 # SKIP Disabled ZA for VL 4848
6801 13:38:28.660436 # ok 909 # SKIP Get and set data for VL 4848
6802 13:38:28.660553 # ok 910 Set VL 4864
6803 13:38:28.662521 # ok 911 # SKIP Disabled ZA for VL 4864
6804 13:38:28.663014 # ok 912 # SKIP Get and set data for VL 4864
6805 13:38:28.663211 # ok 913 Set VL 4880
6806 13:38:28.663394 # ok 914 # SKIP Disabled ZA for VL 4880
6807 13:38:28.663592 # ok 915 # SKIP Get and set data for VL 4880
6808 13:38:28.663751 # ok 916 Set VL 4896
6809 13:38:28.663900 # ok 917 # SKIP Disabled ZA for VL 4896
6810 13:38:28.664022 # ok 918 # SKIP Get and set data for VL 4896
6811 13:38:28.664139 # ok 919 Set VL 4912
6812 13:38:28.664254 # ok 920 # SKIP Disabled ZA for VL 4912
6813 13:38:28.664368 # ok 921 # SKIP Get and set data for VL 4912
6814 13:38:28.664482 # ok 922 Set VL 4928
6815 13:38:28.664597 # ok 923 # SKIP Disabled ZA for VL 4928
6816 13:38:28.664710 # ok 924 # SKIP Get and set data for VL 4928
6817 13:38:28.664823 # ok 925 Set VL 4944
6818 13:38:28.664938 # ok 926 # SKIP Disabled ZA for VL 4944
6819 13:38:28.665054 # ok 927 # SKIP Get and set data for VL 4944
6820 13:38:28.667172 # ok 928 Set VL 4960
6821 13:38:28.667619 # ok 929 # SKIP Disabled ZA for VL 4960
6822 13:38:28.667806 # ok 930 # SKIP Get and set data for VL 4960
6823 13:38:28.667931 # ok 931 Set VL 4976
6824 13:38:28.668051 # ok 932 # SKIP Disabled ZA for VL 4976
6825 13:38:28.668173 # ok 933 # SKIP Get and set data for VL 4976
6826 13:38:28.668290 # ok 934 Set VL 4992
6827 13:38:28.668431 # ok 935 # SKIP Disabled ZA for VL 4992
6828 13:38:28.672642 # ok 936 # SKIP Get and set data for VL 4992
6829 13:38:28.673031 # ok 937 Set VL 5008
6830 13:38:28.673172 # ok 938 # SKIP Disabled ZA for VL 5008
6831 13:38:28.673335 # ok 939 # SKIP Get and set data for VL 5008
6832 13:38:28.673478 # ok 940 Set VL 5024
6833 13:38:28.673635 # ok 941 # SKIP Disabled ZA for VL 5024
6834 13:38:28.673788 # ok 942 # SKIP Get and set data for VL 5024
6835 13:38:28.673918 # ok 943 Set VL 5040
6836 13:38:28.674045 # ok 944 # SKIP Disabled ZA for VL 5040
6837 13:38:28.674171 # ok 945 # SKIP Get and set data for VL 5040
6838 13:38:28.674300 # ok 946 Set VL 5056
6839 13:38:28.674427 # ok 947 # SKIP Disabled ZA for VL 5056
6840 13:38:28.674586 # ok 948 # SKIP Get and set data for VL 5056
6841 13:38:28.674717 # ok 949 Set VL 5072
6842 13:38:28.674846 # ok 950 # SKIP Disabled ZA for VL 5072
6843 13:38:28.674975 # ok 951 # SKIP Get and set data for VL 5072
6844 13:38:28.675105 # ok 952 Set VL 5088
6845 13:38:28.675232 # ok 953 # SKIP Disabled ZA for VL 5088
6846 13:38:28.675358 # ok 954 # SKIP Get and set data for VL 5088
6847 13:38:28.675489 # ok 955 Set VL 5104
6848 13:38:28.675617 # ok 956 # SKIP Disabled ZA for VL 5104
6849 13:38:28.675779 # ok 957 # SKIP Get and set data for VL 5104
6850 13:38:28.675913 # ok 958 Set VL 5120
6851 13:38:28.676034 # ok 959 # SKIP Disabled ZA for VL 5120
6852 13:38:28.676152 # ok 960 # SKIP Get and set data for VL 5120
6853 13:38:28.676269 # ok 961 Set VL 5136
6854 13:38:28.676386 # ok 962 # SKIP Disabled ZA for VL 5136
6855 13:38:28.676503 # ok 963 # SKIP Get and set data for VL 5136
6856 13:38:28.676621 # ok 964 Set VL 5152
6857 13:38:28.676738 # ok 965 # SKIP Disabled ZA for VL 5152
6858 13:38:28.676856 # ok 966 # SKIP Get and set data for VL 5152
6859 13:38:28.676973 # ok 967 Set VL 5168
6860 13:38:28.677093 # ok 968 # SKIP Disabled ZA for VL 5168
6861 13:38:28.680782 # ok 969 # SKIP Get and set data for VL 5168
6862 13:38:28.681181 # ok 970 Set VL 5184
6863 13:38:28.681331 # ok 971 # SKIP Disabled ZA for VL 5184
6864 13:38:28.681508 # ok 972 # SKIP Get and set data for VL 5184
6865 13:38:28.681666 # ok 973 Set VL 5200
6866 13:38:28.681847 # ok 974 # SKIP Disabled ZA for VL 5200
6867 13:38:28.681984 # ok 975 # SKIP Get and set data for VL 5200
6868 13:38:28.682129 # ok 976 Set VL 5216
6869 13:38:28.682272 # ok 977 # SKIP Disabled ZA for VL 5216
6870 13:38:28.682414 # ok 978 # SKIP Get and set data for VL 5216
6871 13:38:28.682555 # ok 979 Set VL 5232
6872 13:38:28.682695 # ok 980 # SKIP Disabled ZA for VL 5232
6873 13:38:28.682835 # ok 981 # SKIP Get and set data for VL 5232
6874 13:38:28.683012 # ok 982 Set VL 5248
6875 13:38:28.683147 # ok 983 # SKIP Disabled ZA for VL 5248
6876 13:38:28.683306 # ok 984 # SKIP Get and set data for VL 5248
6877 13:38:28.683497 # ok 985 Set VL 5264
6878 13:38:28.683680 # ok 986 # SKIP Disabled ZA for VL 5264
6879 13:38:28.683865 # ok 987 # SKIP Get and set data for VL 5264
6880 13:38:28.684013 # ok 988 Set VL 5280
6881 13:38:28.684158 # ok 989 # SKIP Disabled ZA for VL 5280
6882 13:38:28.684298 # ok 990 # SKIP Get and set data for VL 5280
6883 13:38:28.684440 # ok 991 Set VL 5296
6884 13:38:28.684581 # ok 992 # SKIP Disabled ZA for VL 5296
6885 13:38:28.684759 # ok 993 # SKIP Get and set data for VL 5296
6886 13:38:28.684896 # ok 994 Set VL 5312
6887 13:38:28.685038 # ok 995 # SKIP Disabled ZA for VL 5312
6888 13:38:28.685179 # ok 996 # SKIP Get and set data for VL 5312
6889 13:38:28.685322 # ok 997 Set VL 5328
6890 13:38:28.685463 # ok 998 # SKIP Disabled ZA for VL 5328
6891 13:38:28.685605 # ok 999 # SKIP Get and set data for VL 5328
6892 13:38:28.688985 # ok 1000 Set VL 5344
6893 13:38:28.689558 # ok 1001 # SKIP Disabled ZA for VL 5344
6894 13:38:28.689769 # ok 1002 # SKIP Get and set data for VL 5344
6895 13:38:28.689925 # ok 1003 Set VL 5360
6896 13:38:28.690074 # ok 1004 # SKIP Disabled ZA for VL 5360
6897 13:38:28.690221 # ok 1005 # SKIP Get and set data for VL 5360
6898 13:38:28.690369 # ok 1006 Set VL 5376
6899 13:38:28.690517 # ok 1007 # SKIP Disabled ZA for VL 5376
6900 13:38:28.690700 # ok 1008 # SKIP Get and set data for VL 5376
6901 13:38:28.690855 # ok 1009 Set VL 5392
6902 13:38:28.691004 # ok 1010 # SKIP Disabled ZA for VL 5392
6903 13:38:28.691156 # ok 1011 # SKIP Get and set data for VL 5392
6904 13:38:28.691302 # ok 1012 Set VL 5408
6905 13:38:28.691451 # ok 1013 # SKIP Disabled ZA for VL 5408
6906 13:38:28.691600 # ok 1014 # SKIP Get and set data for VL 5408
6907 13:38:28.691747 # ok 1015 Set VL 5424
6908 13:38:28.691892 # ok 1016 # SKIP Disabled ZA for VL 5424
6909 13:38:28.692038 # ok 1017 # SKIP Get and set data for VL 5424
6910 13:38:28.692184 # ok 1018 Set VL 5440
6911 13:38:28.692329 # ok 1019 # SKIP Disabled ZA for VL 5440
6912 13:38:28.692476 # ok 1020 # SKIP Get and set data for VL 5440
6913 13:38:28.692623 # ok 1021 Set VL 5456
6914 13:38:28.692807 # ok 1022 # SKIP Disabled ZA for VL 5456
6915 13:38:28.692960 # ok 1023 # SKIP Get and set data for VL 5456
6916 13:38:28.693108 # ok 1024 Set VL 5472
6917 13:38:28.693254 # ok 1025 # SKIP Disabled ZA for VL 5472
6918 13:38:28.693401 # ok 1026 # SKIP Get and set data for VL 5472
6919 13:38:28.693547 # ok 1027 Set VL 5488
6920 13:38:28.694269 # ok 1028 # SKIP Disabled ZA for VL 5488
6921 13:38:28.694414 # ok 1029 # SKIP Get and set data for VL 5488
6922 13:38:28.694530 # ok 1030 Set VL 5504
6923 13:38:28.694669 # ok 1031 # SKIP Disabled ZA for VL 5504
6924 13:38:28.694824 # ok 1032 # SKIP Get and set data for VL 5504
6925 13:38:28.694991 # ok 1033 Set VL 5520
6926 13:38:28.695166 # ok 1034 # SKIP Disabled ZA for VL 5520
6927 13:38:28.695379 # ok 1035 # SKIP Get and set data for VL 5520
6928 13:38:28.695552 # ok 1036 Set VL 5536
6929 13:38:28.695704 # ok 1037 # SKIP Disabled ZA for VL 5536
6930 13:38:28.695849 # ok 1038 # SKIP Get and set data for VL 5536
6931 13:38:28.695993 # ok 1039 Set VL 5552
6932 13:38:28.696139 # ok 1040 # SKIP Disabled ZA for VL 5552
6933 13:38:28.696281 # ok 1041 # SKIP Get and set data for VL 5552
6934 13:38:28.696424 # ok 1042 Set VL 5568
6935 13:38:28.696596 # ok 1043 # SKIP Disabled ZA for VL 5568
6936 13:38:28.696745 # ok 1044 # SKIP Get and set data for VL 5568
6937 13:38:28.696890 # ok 1045 Set VL 5584
6938 13:38:28.697033 # ok 1046 # SKIP Disabled ZA for VL 5584
6939 13:38:28.697176 # ok 1047 # SKIP Get and set data for VL 5584
6940 13:38:28.697319 # ok 1048 Set VL 5600
6941 13:38:28.697460 # ok 1049 # SKIP Disabled ZA for VL 5600
6942 13:38:28.697629 # ok 1050 # SKIP Get and set data for VL 5600
6943 13:38:28.698324 # ok 1051 Set VL 5616
6944 13:38:28.698492 # ok 1052 # SKIP Disabled ZA for VL 5616
6945 13:38:28.698923 # ok 1053 # SKIP Get and set data for VL 5616
6946 13:38:28.699088 # ok 1054 Set VL 5632
6947 13:38:28.699298 # ok 1055 # SKIP Disabled ZA for VL 5632
6948 13:38:28.699519 # ok 1056 # SKIP Get and set data for VL 5632
6949 13:38:28.699697 # ok 1057 Set VL 5648
6950 13:38:28.699905 # ok 1058 # SKIP Disabled ZA for VL 5648
6951 13:38:28.700073 # ok 1059 # SKIP Get and set data for VL 5648
6952 13:38:28.700225 # ok 1060 Set VL 5664
6953 13:38:28.700369 # ok 1061 # SKIP Disabled ZA for VL 5664
6954 13:38:28.700513 # ok 1062 # SKIP Get and set data for VL 5664
6955 13:38:28.700658 # ok 1063 Set VL 5680
6956 13:38:28.700802 # ok 1064 # SKIP Disabled ZA for VL 5680
6957 13:38:28.700948 # ok 1065 # SKIP Get and set data for VL 5680
6958 13:38:28.701093 # ok 1066 Set VL 5696
6959 13:38:28.701241 # ok 1067 # SKIP Disabled ZA for VL 5696
6960 13:38:28.701387 # ok 1068 # SKIP Get and set data for VL 5696
6961 13:38:28.701533 # ok 1069 Set VL 5712
6962 13:38:28.702334 # ok 1070 # SKIP Disabled ZA for VL 5712
6963 13:38:28.702742 # ok 1071 # SKIP Get and set data for VL 5712
6964 13:38:28.702939 # ok 1072 Set VL 5728
6965 13:38:28.703135 # ok 1073 # SKIP Disabled ZA for VL 5728
6966 13:38:28.703321 # ok 1074 # SKIP Get and set data for VL 5728
6967 13:38:28.703541 # ok 1075 Set VL 5744
6968 13:38:28.703686 # ok 1076 # SKIP Disabled ZA for VL 5744
6969 13:38:28.703814 # ok 1077 # SKIP Get and set data for VL 5744
6970 13:38:28.703931 # ok 1078 Set VL 5760
6971 13:38:28.704046 # ok 1079 # SKIP Disabled ZA for VL 5760
6972 13:38:28.704160 # ok 1080 # SKIP Get and set data for VL 5760
6973 13:38:28.704280 # ok 1081 Set VL 5776
6974 13:38:28.704394 # ok 1082 # SKIP Disabled ZA for VL 5776
6975 13:38:28.704510 # ok 1083 # SKIP Get and set data for VL 5776
6976 13:38:28.704624 # ok 1084 Set VL 5792
6977 13:38:28.704763 # ok 1085 # SKIP Disabled ZA for VL 5792
6978 13:38:28.704884 # ok 1086 # SKIP Get and set data for VL 5792
6979 13:38:28.705000 # ok 1087 Set VL 5808
6980 13:38:28.707800 # ok 1088 # SKIP Disabled ZA for VL 5808
6981 13:38:28.707960 # ok 1089 # SKIP Get and set data for VL 5808
6982 13:38:28.708624 # ok 1090 Set VL 5824
6983 13:38:28.709066 # ok 1091 # SKIP Disabled ZA for VL 5824
6984 13:38:28.709265 # ok 1092 # SKIP Get and set data for VL 5824
6985 13:38:28.709437 # ok 1093 Set VL 5840
6986 13:38:28.709614 # ok 1094 # SKIP Disabled ZA for VL 5840
6987 13:38:28.709819 # ok 1095 # SKIP Get and set data for VL 5840
6988 13:38:28.710026 # ok 1096 Set VL 5856
6989 13:38:28.710192 # ok 1097 # SKIP Disabled ZA for VL 5856
6990 13:38:28.710362 # ok 1098 # SKIP Get and set data for VL 5856
6991 13:38:28.710525 # ok 1099 Set VL 5872
6992 13:38:28.710685 # ok 1100 # SKIP Disabled ZA for VL 5872
6993 13:38:28.710830 # ok 1101 # SKIP Get and set data for VL 5872
6994 13:38:28.710948 # ok 1102 Set VL 5888
6995 13:38:28.711096 # ok 1103 # SKIP Disabled ZA for VL 5888
6996 13:38:28.711254 # ok 1104 # SKIP Get and set data for VL 5888
6997 13:38:28.711396 # ok 1105 Set VL 5904
6998 13:38:28.711553 # ok 1106 # SKIP Disabled ZA for VL 5904
6999 13:38:28.711749 # ok 1107 # SKIP Get and set data for VL 5904
7000 13:38:28.711878 # ok 1108 Set VL 5920
7001 13:38:28.711994 # ok 1109 # SKIP Disabled ZA for VL 5920
7002 13:38:28.712110 # ok 1110 # SKIP Get and set data for VL 5920
7003 13:38:28.712227 # ok 1111 Set VL 5936
7004 13:38:28.712341 # ok 1112 # SKIP Disabled ZA for VL 5936
7005 13:38:28.712456 # ok 1113 # SKIP Get and set data for VL 5936
7006 13:38:28.712571 # ok 1114 Set VL 5952
7007 13:38:28.712685 # ok 1115 # SKIP Disabled ZA for VL 5952
7008 13:38:28.712799 # ok 1116 # SKIP Get and set data for VL 5952
7009 13:38:28.712914 # ok 1117 Set VL 5968
7010 13:38:28.713028 # ok 1118 # SKIP Disabled ZA for VL 5968
7011 13:38:28.713144 # ok 1119 # SKIP Get and set data for VL 5968
7012 13:38:28.713259 # ok 1120 Set VL 5984
7013 13:38:28.713372 # ok 1121 # SKIP Disabled ZA for VL 5984
7014 13:38:28.713487 # ok 1122 # SKIP Get and set data for VL 5984
7015 13:38:28.713601 # ok 1123 Set VL 6000
7016 13:38:28.713729 # ok 1124 # SKIP Disabled ZA for VL 6000
7017 13:38:28.713844 # ok 1125 # SKIP Get and set data for VL 6000
7018 13:38:28.713959 # ok 1126 Set VL 6016
7019 13:38:28.715462 # ok 1127 # SKIP Disabled ZA for VL 6016
7020 13:38:28.715820 # ok 1128 # SKIP Get and set data for VL 6016
7021 13:38:28.715952 # ok 1129 Set VL 6032
7022 13:38:28.716071 # ok 1130 # SKIP Disabled ZA for VL 6032
7023 13:38:28.716666 # ok 1131 # SKIP Get and set data for VL 6032
7024 13:38:28.717017 # ok 1132 Set VL 6048
7025 13:38:28.717151 # ok 1133 # SKIP Disabled ZA for VL 6048
7026 13:38:28.717282 # ok 1134 # SKIP Get and set data for VL 6048
7027 13:38:28.717430 # ok 1135 Set VL 6064
7028 13:38:28.717558 # ok 1136 # SKIP Disabled ZA for VL 6064
7029 13:38:28.717692 # ok 1137 # SKIP Get and set data for VL 6064
7030 13:38:28.717827 # ok 1138 Set VL 6080
7031 13:38:28.717951 # ok 1139 # SKIP Disabled ZA for VL 6080
7032 13:38:28.718136 # ok 1140 # SKIP Get and set data for VL 6080
7033 13:38:28.718307 # ok 1141 Set VL 6096
7034 13:38:28.718470 # ok 1142 # SKIP Disabled ZA for VL 6096
7035 13:38:28.718634 # ok 1143 # SKIP Get and set data for VL 6096
7036 13:38:28.718797 # ok 1144 Set VL 6112
7037 13:38:28.718960 # ok 1145 # SKIP Disabled ZA for VL 6112
7038 13:38:28.719098 # ok 1146 # SKIP Get and set data for VL 6112
7039 13:38:28.719217 # ok 1147 Set VL 6128
7040 13:38:28.719363 # ok 1148 # SKIP Disabled ZA for VL 6128
7041 13:38:28.719487 # ok 1149 # SKIP Get and set data for VL 6128
7042 13:38:28.719610 # ok 1150 Set VL 6144
7043 13:38:28.719728 # ok 1151 # SKIP Disabled ZA for VL 6144
7044 13:38:28.719844 # ok 1152 # SKIP Get and set data for VL 6144
7045 13:38:28.719961 # ok 1153 Set VL 6160
7046 13:38:28.720075 # ok 1154 # SKIP Disabled ZA for VL 6160
7047 13:38:28.720192 # ok 1155 # SKIP Get and set data for VL 6160
7048 13:38:28.720314 # ok 1156 Set VL 6176
7049 13:38:28.720431 # ok 1157 # SKIP Disabled ZA for VL 6176
7050 13:38:28.720548 # ok 1158 # SKIP Get and set data for VL 6176
7051 13:38:28.720666 # ok 1159 Set VL 6192
7052 13:38:28.720781 # ok 1160 # SKIP Disabled ZA for VL 6192
7053 13:38:28.720924 # ok 1161 # SKIP Get and set data for VL 6192
7054 13:38:28.721047 # ok 1162 Set VL 6208
7055 13:38:28.721163 # ok 1163 # SKIP Disabled ZA for VL 6208
7056 13:38:28.721279 # ok 1164 # SKIP Get and set data for VL 6208
7057 13:38:28.724354 # ok 1165 Set VL 6224
7058 13:38:28.724660 # ok 1166 # SKIP Disabled ZA for VL 6224
7059 13:38:28.724768 # ok 1167 # SKIP Get and set data for VL 6224
7060 13:38:28.724845 # ok 1168 Set VL 6240
7061 13:38:28.724931 # ok 1169 # SKIP Disabled ZA for VL 6240
7062 13:38:28.725009 # ok 1170 # SKIP Get and set data for VL 6240
7063 13:38:28.725113 # ok 1171 Set VL 6256
7064 13:38:28.725222 # ok 1172 # SKIP Disabled ZA for VL 6256
7065 13:38:28.725295 # ok 1173 # SKIP Get and set data for VL 6256
7066 13:38:28.725370 # ok 1174 Set VL 6272
7067 13:38:28.725445 # ok 1175 # SKIP Disabled ZA for VL 6272
7068 13:38:28.725535 # ok 1176 # SKIP Get and set data for VL 6272
7069 13:38:28.725620 # ok 1177 Set VL 6288
7070 13:38:28.725718 # ok 1178 # SKIP Disabled ZA for VL 6288
7071 13:38:28.725836 # ok 1179 # SKIP Get and set data for VL 6288
7072 13:38:28.725929 # ok 1180 Set VL 6304
7073 13:38:28.726022 # ok 1181 # SKIP Disabled ZA for VL 6304
7074 13:38:28.726118 # ok 1182 # SKIP Get and set data for VL 6304
7075 13:38:28.726231 # ok 1183 Set VL 6320
7076 13:38:28.726308 # ok 1184 # SKIP Disabled ZA for VL 6320
7077 13:38:28.726400 # ok 1185 # SKIP Get and set data for VL 6320
7078 13:38:28.726480 # ok 1186 Set VL 6336
7079 13:38:28.726578 # ok 1187 # SKIP Disabled ZA for VL 6336
7080 13:38:28.726659 # ok 1188 # SKIP Get and set data for VL 6336
7081 13:38:28.726746 # ok 1189 Set VL 6352
7082 13:38:28.726841 # ok 1190 # SKIP Disabled ZA for VL 6352
7083 13:38:28.726966 # ok 1191 # SKIP Get and set data for VL 6352
7084 13:38:28.727064 # ok 1192 Set VL 6368
7085 13:38:28.727156 # ok 1193 # SKIP Disabled ZA for VL 6368
7086 13:38:28.727250 # ok 1194 # SKIP Get and set data for VL 6368
7087 13:38:28.727345 # ok 1195 Set VL 6384
7088 13:38:28.727462 # ok 1196 # SKIP Disabled ZA for VL 6384
7089 13:38:28.727545 # ok 1197 # SKIP Get and set data for VL 6384
7090 13:38:28.727621 # ok 1198 Set VL 6400
7091 13:38:28.727696 # ok 1199 # SKIP Disabled ZA for VL 6400
7092 13:38:28.727770 # ok 1200 # SKIP Get and set data for VL 6400
7093 13:38:28.727846 # ok 1201 Set VL 6416
7094 13:38:28.727939 # ok 1202 # SKIP Disabled ZA for VL 6416
7095 13:38:28.728010 # ok 1203 # SKIP Get and set data for VL 6416
7096 13:38:28.728083 # ok 1204 Set VL 6432
7097 13:38:28.728157 # ok 1205 # SKIP Disabled ZA for VL 6432
7098 13:38:28.732147 # ok 1206 # SKIP Get and set data for VL 6432
7099 13:38:28.732430 # ok 1207 Set VL 6448
7100 13:38:28.732541 # ok 1208 # SKIP Disabled ZA for VL 6448
7101 13:38:28.732651 # ok 1209 # SKIP Get and set data for VL 6448
7102 13:38:28.732778 # ok 1210 Set VL 6464
7103 13:38:28.732878 # ok 1211 # SKIP Disabled ZA for VL 6464
7104 13:38:28.732966 # ok 1212 # SKIP Get and set data for VL 6464
7105 13:38:28.733057 # ok 1213 Set VL 6480
7106 13:38:28.733165 # ok 1214 # SKIP Disabled ZA for VL 6480
7107 13:38:28.733258 # ok 1215 # SKIP Get and set data for VL 6480
7108 13:38:28.733362 # ok 1216 Set VL 6496
7109 13:38:28.733451 # ok 1217 # SKIP Disabled ZA for VL 6496
7110 13:38:28.733544 # ok 1218 # SKIP Get and set data for VL 6496
7111 13:38:28.733630 # ok 1219 Set VL 6512
7112 13:38:28.733739 # ok 1220 # SKIP Disabled ZA for VL 6512
7113 13:38:28.733850 # ok 1221 # SKIP Get and set data for VL 6512
7114 13:38:28.733960 # ok 1222 Set VL 6528
7115 13:38:28.734048 # ok 1223 # SKIP Disabled ZA for VL 6528
7116 13:38:28.734157 # ok 1224 # SKIP Get and set data for VL 6528
7117 13:38:28.734266 # ok 1225 Set VL 6544
7118 13:38:28.734343 # ok 1226 # SKIP Disabled ZA for VL 6544
7119 13:38:28.734441 # ok 1227 # SKIP Get and set data for VL 6544
7120 13:38:28.734514 # ok 1228 Set VL 6560
7121 13:38:28.734595 # ok 1229 # SKIP Disabled ZA for VL 6560
7122 13:38:28.734676 # ok 1230 # SKIP Get and set data for VL 6560
7123 13:38:28.734776 # ok 1231 Set VL 6576
7124 13:38:28.734862 # ok 1232 # SKIP Disabled ZA for VL 6576
7125 13:38:28.734962 # ok 1233 # SKIP Get and set data for VL 6576
7126 13:38:28.735040 # ok 1234 Set VL 6592
7127 13:38:28.735115 # ok 1235 # SKIP Disabled ZA for VL 6592
7128 13:38:28.735183 # ok 1236 # SKIP Get and set data for VL 6592
7129 13:38:28.735246 # ok 1237 Set VL 6608
7130 13:38:28.735314 # ok 1238 # SKIP Disabled ZA for VL 6608
7131 13:38:28.735424 # ok 1239 # SKIP Get and set data for VL 6608
7132 13:38:28.735499 # ok 1240 Set VL 6624
7133 13:38:28.735584 # ok 1241 # SKIP Disabled ZA for VL 6624
7134 13:38:28.735666 # ok 1242 # SKIP Get and set data for VL 6624
7135 13:38:28.735737 # ok 1243 Set VL 6640
7136 13:38:28.735816 # ok 1244 # SKIP Disabled ZA for VL 6640
7137 13:38:28.735878 # ok 1245 # SKIP Get and set data for VL 6640
7138 13:38:28.735938 # ok 1246 Set VL 6656
7139 13:38:28.735997 # ok 1247 # SKIP Disabled ZA for VL 6656
7140 13:38:28.740408 # ok 1248 # SKIP Get and set data for VL 6656
7141 13:38:28.740522 # ok 1249 Set VL 6672
7142 13:38:28.740840 # ok 1250 # SKIP Disabled ZA for VL 6672
7143 13:38:28.741051 # ok 1251 # SKIP Get and set data for VL 6672
7144 13:38:28.741208 # ok 1252 Set VL 6688
7145 13:38:28.741332 # ok 1253 # SKIP Disabled ZA for VL 6688
7146 13:38:28.741528 # ok 1254 # SKIP Get and set data for VL 6688
7147 13:38:28.741768 # ok 1255 Set VL 6704
7148 13:38:28.741912 # ok 1256 # SKIP Disabled ZA for VL 6704
7149 13:38:28.742044 # ok 1257 # SKIP Get and set data for VL 6704
7150 13:38:28.742178 # ok 1258 Set VL 6720
7151 13:38:28.742373 # ok 1259 # SKIP Disabled ZA for VL 6720
7152 13:38:28.742567 # ok 1260 # SKIP Get and set data for VL 6720
7153 13:38:28.742756 # ok 1261 Set VL 6736
7154 13:38:28.742931 # ok 1262 # SKIP Disabled ZA for VL 6736
7155 13:38:28.743120 # ok 1263 # SKIP Get and set data for VL 6736
7156 13:38:28.743260 # ok 1264 Set VL 6752
7157 13:38:28.743420 # ok 1265 # SKIP Disabled ZA for VL 6752
7158 13:38:28.743613 # ok 1266 # SKIP Get and set data for VL 6752
7159 13:38:28.743784 # ok 1267 Set VL 6768
7160 13:38:28.743929 # ok 1268 # SKIP Disabled ZA for VL 6768
7161 13:38:28.744072 # ok 1269 # SKIP Get and set data for VL 6768
7162 13:38:28.744216 # ok 1270 Set VL 6784
7163 13:38:28.744357 # ok 1271 # SKIP Disabled ZA for VL 6784
7164 13:38:28.744500 # ok 1272 # SKIP Get and set data for VL 6784
7165 13:38:28.744642 # ok 1273 Set VL 6800
7166 13:38:28.744784 # ok 1274 # SKIP Disabled ZA for VL 6800
7167 13:38:28.744927 # ok 1275 # SKIP Get and set data for VL 6800
7168 13:38:28.745067 # ok 1276 Set VL 6816
7169 13:38:28.745209 # ok 1277 # SKIP Disabled ZA for VL 6816
7170 13:38:28.745393 # ok 1278 # SKIP Get and set data for VL 6816
7171 13:38:28.745531 # ok 1279 Set VL 6832
7172 13:38:28.745684 # ok 1280 # SKIP Disabled ZA for VL 6832
7173 13:38:28.745830 # ok 1281 # SKIP Get and set data for VL 6832
7174 13:38:28.745972 # ok 1282 Set VL 6848
7175 13:38:28.756905 # ok 1283 # SKIP Disabled ZA for VL 6848
7176 13:38:28.757257 # ok 1284 # SKIP Get and set data for VL 6848
7177 13:38:28.757448 # ok 1285 Set VL 6864
7178 13:38:28.757644 # ok 1286 # SKIP Disabled ZA for VL 6864
7179 13:38:28.757815 # ok 1287 # SKIP Get and set data for VL 6864
7180 13:38:28.757991 # ok 1288 Set VL 6880
7181 13:38:28.758199 # ok 1289 # SKIP Disabled ZA for VL 6880
7182 13:38:28.758413 # ok 1290 # SKIP Get and set data for VL 6880
7183 13:38:28.758595 # ok 1291 Set VL 6896
7184 13:38:28.758783 # ok 1292 # SKIP Disabled ZA for VL 6896
7185 13:38:28.758918 # ok 1293 # SKIP Get and set data for VL 6896
7186 13:38:28.759097 # ok 1294 Set VL 6912
7187 13:38:28.759297 # ok 1295 # SKIP Disabled ZA for VL 6912
7188 13:38:28.759469 # ok 1296 # SKIP Get and set data for VL 6912
7189 13:38:28.759657 # ok 1297 Set VL 6928
7190 13:38:28.759826 # ok 1298 # SKIP Disabled ZA for VL 6928
7191 13:38:28.759972 # ok 1299 # SKIP Get and set data for VL 6928
7192 13:38:28.760092 # ok 1300 Set VL 6944
7193 13:38:28.760209 # ok 1301 # SKIP Disabled ZA for VL 6944
7194 13:38:28.760326 # ok 1302 # SKIP Get and set data for VL 6944
7195 13:38:28.760441 # ok 1303 Set VL 6960
7196 13:38:28.760556 # ok 1304 # SKIP Disabled ZA for VL 6960
7197 13:38:28.760671 # ok 1305 # SKIP Get and set data for VL 6960
7198 13:38:28.760786 # ok 1306 Set VL 6976
7199 13:38:28.760902 # ok 1307 # SKIP Disabled ZA for VL 6976
7200 13:38:28.761018 # ok 1308 # SKIP Get and set data for VL 6976
7201 13:38:28.761134 # ok 1309 Set VL 6992
7202 13:38:28.761248 # ok 1310 # SKIP Disabled ZA for VL 6992
7203 13:38:28.761370 # ok 1311 # SKIP Get and set data for VL 6992
7204 13:38:28.761487 # ok 1312 Set VL 7008
7205 13:38:28.761601 # ok 1313 # SKIP Disabled ZA for VL 7008
7206 13:38:28.761734 # ok 1314 # SKIP Get and set data for VL 7008
7207 13:38:28.761851 # ok 1315 Set VL 7024
7208 13:38:28.761967 # ok 1316 # SKIP Disabled ZA for VL 7024
7209 13:38:28.762109 # ok 1317 # SKIP Get and set data for VL 7024
7210 13:38:28.762232 # ok 1318 Set VL 7040
7211 13:38:28.768580 # ok 1319 # SKIP Disabled ZA for VL 7040
7212 13:38:28.769086 # ok 1320 # SKIP Get and set data for VL 7040
7213 13:38:28.769280 # ok 1321 Set VL 7056
7214 13:38:28.769421 # ok 1322 # SKIP Disabled ZA for VL 7056
7215 13:38:28.769566 # ok 1323 # SKIP Get and set data for VL 7056
7216 13:38:28.769723 # ok 1324 Set VL 7072
7217 13:38:28.769856 # ok 1325 # SKIP Disabled ZA for VL 7072
7218 13:38:28.769991 # ok 1326 # SKIP Get and set data for VL 7072
7219 13:38:28.770144 # ok 1327 Set VL 7088
7220 13:38:28.770307 # ok 1328 # SKIP Disabled ZA for VL 7088
7221 13:38:28.770437 # ok 1329 # SKIP Get and set data for VL 7088
7222 13:38:28.770559 # ok 1330 Set VL 7104
7223 13:38:28.770672 # ok 1331 # SKIP Disabled ZA for VL 7104
7224 13:38:28.770796 # ok 1332 # SKIP Get and set data for VL 7104
7225 13:38:28.770921 # ok 1333 Set VL 7120
7226 13:38:28.771048 # ok 1334 # SKIP Disabled ZA for VL 7120
7227 13:38:28.771159 # ok 1335 # SKIP Get and set data for VL 7120
7228 13:38:28.771265 # ok 1336 Set VL 7136
7229 13:38:28.771331 # ok 1337 # SKIP Disabled ZA for VL 7136
7230 13:38:28.771404 # ok 1338 # SKIP Get and set data for VL 7136
7231 13:38:28.771483 # ok 1339 Set VL 7152
7232 13:38:28.771562 # ok 1340 # SKIP Disabled ZA for VL 7152
7233 13:38:28.771662 # ok 1341 # SKIP Get and set data for VL 7152
7234 13:38:28.771743 # ok 1342 Set VL 7168
7235 13:38:28.771845 # ok 1343 # SKIP Disabled ZA for VL 7168
7236 13:38:28.771917 # ok 1344 # SKIP Get and set data for VL 7168
7237 13:38:28.771977 # ok 1345 Set VL 7184
7238 13:38:28.772036 # ok 1346 # SKIP Disabled ZA for VL 7184
7239 13:38:28.772114 # ok 1347 # SKIP Get and set data for VL 7184
7240 13:38:28.772183 # ok 1348 Set VL 7200
7241 13:38:28.772245 # ok 1349 # SKIP Disabled ZA for VL 7200
7242 13:38:28.772308 # ok 1350 # SKIP Get and set data for VL 7200
7243 13:38:28.772367 # ok 1351 Set VL 7216
7244 13:38:28.772426 # ok 1352 # SKIP Disabled ZA for VL 7216
7245 13:38:28.772485 # ok 1353 # SKIP Get and set data for VL 7216
7246 13:38:28.772544 # ok 1354 Set VL 7232
7247 13:38:28.772603 # ok 1355 # SKIP Disabled ZA for VL 7232
7248 13:38:28.772661 # ok 1356 # SKIP Get and set data for VL 7232
7249 13:38:28.772736 # ok 1357 Set VL 7248
7250 13:38:28.772808 # ok 1358 # SKIP Disabled ZA for VL 7248
7251 13:38:28.780934 # ok 1359 # SKIP Get and set data for VL 7248
7252 13:38:28.781263 # ok 1360 Set VL 7264
7253 13:38:28.781702 # ok 1361 # SKIP Disabled ZA for VL 7264
7254 13:38:28.781907 # ok 1362 # SKIP Get and set data for VL 7264
7255 13:38:28.782086 # ok 1363 Set VL 7280
7256 13:38:28.782257 # ok 1364 # SKIP Disabled ZA for VL 7280
7257 13:38:28.782426 # ok 1365 # SKIP Get and set data for VL 7280
7258 13:38:28.782588 # ok 1366 Set VL 7296
7259 13:38:28.782748 # ok 1367 # SKIP Disabled ZA for VL 7296
7260 13:38:28.782896 # ok 1368 # SKIP Get and set data for VL 7296
7261 13:38:28.783061 # ok 1369 Set VL 7312
7262 13:38:28.783261 # ok 1370 # SKIP Disabled ZA for VL 7312
7263 13:38:28.783432 # ok 1371 # SKIP Get and set data for VL 7312
7264 13:38:28.783587 # ok 1372 Set VL 7328
7265 13:38:28.783723 # ok 1373 # SKIP Disabled ZA for VL 7328
7266 13:38:28.783911 # ok 1374 # SKIP Get and set data for VL 7328
7267 13:38:28.784050 # ok 1375 Set VL 7344
7268 13:38:28.784211 # ok 1376 # SKIP Disabled ZA for VL 7344
7269 13:38:28.784351 # ok 1377 # SKIP Get and set data for VL 7344
7270 13:38:28.784496 # ok 1378 Set VL 7360
7271 13:38:28.784614 # ok 1379 # SKIP Disabled ZA for VL 7360
7272 13:38:28.784730 # ok 1380 # SKIP Get and set data for VL 7360
7273 13:38:28.784844 # ok 1381 Set VL 7376
7274 13:38:28.784959 # ok 1382 # SKIP Disabled ZA for VL 7376
7275 13:38:28.785075 # ok 1383 # SKIP Get and set data for VL 7376
7276 13:38:28.785190 # ok 1384 Set VL 7392
7277 13:38:28.785304 # ok 1385 # SKIP Disabled ZA for VL 7392
7278 13:38:28.785419 # ok 1386 # SKIP Get and set data for VL 7392
7279 13:38:28.785563 # ok 1387 Set VL 7408
7280 13:38:28.785736 # ok 1388 # SKIP Disabled ZA for VL 7408
7281 13:38:28.785940 # ok 1389 # SKIP Get and set data for VL 7408
7282 13:38:28.786124 # ok 1390 Set VL 7424
7283 13:38:28.786308 # ok 1391 # SKIP Disabled ZA for VL 7424
7284 13:38:28.786489 # ok 1392 # SKIP Get and set data for VL 7424
7285 13:38:28.790033 # ok 1393 Set VL 7440
7286 13:38:28.790366 # ok 1394 # SKIP Disabled ZA for VL 7440
7287 13:38:28.790534 # ok 1395 # SKIP Get and set data for VL 7440
7288 13:38:28.790684 # ok 1396 Set VL 7456
7289 13:38:28.790838 # ok 1397 # SKIP Disabled ZA for VL 7456
7290 13:38:28.790996 # ok 1398 # SKIP Get and set data for VL 7456
7291 13:38:28.791158 # ok 1399 Set VL 7472
7292 13:38:28.791556 # ok 1400 # SKIP Disabled ZA for VL 7472
7293 13:38:28.791736 # ok 1401 # SKIP Get and set data for VL 7472
7294 13:38:28.791888 # ok 1402 Set VL 7488
7295 13:38:28.792034 # ok 1403 # SKIP Disabled ZA for VL 7488
7296 13:38:28.792182 # ok 1404 # SKIP Get and set data for VL 7488
7297 13:38:28.793197 # ok 1405 Set VL 7504
7298 13:38:28.793388 # ok 1406 # SKIP Disabled ZA for VL 7504
7299 13:38:28.793563 # ok 1407 # SKIP Get and set data for VL 7504
7300 13:38:28.793729 # ok 1408 Set VL 7520
7301 13:38:28.793875 # ok 1409 # SKIP Disabled ZA for VL 7520
7302 13:38:28.794017 # ok 1410 # SKIP Get and set data for VL 7520
7303 13:38:28.794160 # ok 1411 Set VL 7536
7304 13:38:28.794305 # ok 1412 # SKIP Disabled ZA for VL 7536
7305 13:38:28.794448 # ok 1413 # SKIP Get and set data for VL 7536
7306 13:38:28.794592 # ok 1414 Set VL 7552
7307 13:38:28.794733 # ok 1415 # SKIP Disabled ZA for VL 7552
7308 13:38:28.794874 # ok 1416 # SKIP Get and set data for VL 7552
7309 13:38:28.795025 # ok 1417 Set VL 7568
7310 13:38:28.795212 # ok 1418 # SKIP Disabled ZA for VL 7568
7311 13:38:28.795338 # ok 1419 # SKIP Get and set data for VL 7568
7312 13:38:28.795457 # ok 1420 Set VL 7584
7313 13:38:28.795574 # ok 1421 # SKIP Disabled ZA for VL 7584
7314 13:38:28.795690 # ok 1422 # SKIP Get and set data for VL 7584
7315 13:38:28.795828 # ok 1423 Set VL 7600
7316 13:38:28.796990 # ok 1424 # SKIP Disabled ZA for VL 7600
7317 13:38:28.797530 # ok 1425 # SKIP Get and set data for VL 7600
7318 13:38:28.797771 # ok 1426 Set VL 7616
7319 13:38:28.797978 # ok 1427 # SKIP Disabled ZA for VL 7616
7320 13:38:28.798142 # ok 1428 # SKIP Get and set data for VL 7616
7321 13:38:28.798303 # ok 1429 Set VL 7632
7322 13:38:28.798459 # ok 1430 # SKIP Disabled ZA for VL 7632
7323 13:38:28.798640 # ok 1431 # SKIP Get and set data for VL 7632
7324 13:38:28.798779 # ok 1432 Set VL 7648
7325 13:38:28.800455 # ok 1433 # SKIP Disabled ZA for VL 7648
7326 13:38:28.800541 # ok 1434 # SKIP Get and set data for VL 7648
7327 13:38:28.800604 # ok 1435 Set VL 7664
7328 13:38:28.800666 # ok 1436 # SKIP Disabled ZA for VL 7664
7329 13:38:28.800726 # ok 1437 # SKIP Get and set data for VL 7664
7330 13:38:28.800787 # ok 1438 Set VL 7680
7331 13:38:28.800847 # ok 1439 # SKIP Disabled ZA for VL 7680
7332 13:38:28.800907 # ok 1440 # SKIP Get and set data for VL 7680
7333 13:38:28.800967 # ok 1441 Set VL 7696
7334 13:38:28.801045 # ok 1442 # SKIP Disabled ZA for VL 7696
7335 13:38:28.801110 # ok 1443 # SKIP Get and set data for VL 7696
7336 13:38:28.801172 # ok 1444 Set VL 7712
7337 13:38:28.801233 # ok 1445 # SKIP Disabled ZA for VL 7712
7338 13:38:28.801293 # ok 1446 # SKIP Get and set data for VL 7712
7339 13:38:28.801353 # ok 1447 Set VL 7728
7340 13:38:28.801413 # ok 1448 # SKIP Disabled ZA for VL 7728
7341 13:38:28.801474 # ok 1449 # SKIP Get and set data for VL 7728
7342 13:38:28.801534 # ok 1450 Set VL 7744
7343 13:38:28.801594 # ok 1451 # SKIP Disabled ZA for VL 7744
7344 13:38:28.801663 # ok 1452 # SKIP Get and set data for VL 7744
7345 13:38:28.804813 # ok 1453 Set VL 7760
7346 13:38:28.805146 # ok 1454 # SKIP Disabled ZA for VL 7760
7347 13:38:28.805275 # ok 1455 # SKIP Get and set data for VL 7760
7348 13:38:28.805385 # ok 1456 Set VL 7776
7349 13:38:28.805472 # ok 1457 # SKIP Disabled ZA for VL 7776
7350 13:38:28.805575 # ok 1458 # SKIP Get and set data for VL 7776
7351 13:38:28.805675 # ok 1459 Set VL 7792
7352 13:38:28.805794 # ok 1460 # SKIP Disabled ZA for VL 7792
7353 13:38:28.805925 # ok 1461 # SKIP Get and set data for VL 7792
7354 13:38:28.806063 # ok 1462 Set VL 7808
7355 13:38:28.806191 # ok 1463 # SKIP Disabled ZA for VL 7808
7356 13:38:28.806318 # ok 1464 # SKIP Get and set data for VL 7808
7357 13:38:28.806421 # ok 1465 Set VL 7824
7358 13:38:28.806516 # ok 1466 # SKIP Disabled ZA for VL 7824
7359 13:38:28.806638 # ok 1467 # SKIP Get and set data for VL 7824
7360 13:38:28.806734 # ok 1468 Set VL 7840
7361 13:38:28.806847 # ok 1469 # SKIP Disabled ZA for VL 7840
7362 13:38:28.806977 # ok 1470 # SKIP Get and set data for VL 7840
7363 13:38:28.807090 # ok 1471 Set VL 7856
7364 13:38:28.807215 # ok 1472 # SKIP Disabled ZA for VL 7856
7365 13:38:28.807353 # ok 1473 # SKIP Get and set data for VL 7856
7366 13:38:28.807467 # ok 1474 Set VL 7872
7367 13:38:28.807578 # ok 1475 # SKIP Disabled ZA for VL 7872
7368 13:38:28.807709 # ok 1476 # SKIP Get and set data for VL 7872
7369 13:38:28.807815 # ok 1477 Set VL 7888
7370 13:38:28.807920 # ok 1478 # SKIP Disabled ZA for VL 7888
7371 13:38:28.807995 # ok 1479 # SKIP Get and set data for VL 7888
7372 13:38:28.808078 # ok 1480 Set VL 7904
7373 13:38:28.808160 # ok 1481 # SKIP Disabled ZA for VL 7904
7374 13:38:28.827142 # ok 1482 # SKIP Get and set data for VL 7904
7375 13:38:28.827383 # ok 1483 Set VL 7920
7376 13:38:28.827684 # ok 1484 # SKIP Disabled ZA for VL 7920
7377 13:38:28.827786 # ok 1485 # SKIP Get and set data for VL 7920
7378 13:38:28.827870 # ok 1486 Set VL 7936
7379 13:38:28.827933 # ok 1487 # SKIP Disabled ZA for VL 7936
7380 13:38:28.827993 # ok 1488 # SKIP Get and set data for VL 7936
7381 13:38:28.828053 # ok 1489 Set VL 7952
7382 13:38:28.828124 # ok 1490 # SKIP Disabled ZA for VL 7952
7383 13:38:28.828186 # ok 1491 # SKIP Get and set data for VL 7952
7384 13:38:28.828448 # ok 1492 Set VL 7968
7385 13:38:28.828546 # ok 1493 # SKIP Disabled ZA for VL 7968
7386 13:38:28.828646 # ok 1494 # SKIP Get and set data for VL 7968
7387 13:38:28.828733 # ok 1495 Set VL 7984
7388 13:38:28.828834 # ok 1496 # SKIP Disabled ZA for VL 7984
7389 13:38:28.828920 # ok 1497 # SKIP Get and set data for VL 7984
7390 13:38:28.829022 # ok 1498 Set VL 8000
7391 13:38:28.829112 # ok 1499 # SKIP Disabled ZA for VL 8000
7392 13:38:28.829201 # ok 1500 # SKIP Get and set data for VL 8000
7393 13:38:28.829289 # ok 1501 Set VL 8016
7394 13:38:28.829373 # ok 1502 # SKIP Disabled ZA for VL 8016
7395 13:38:28.830367 # ok 1503 # SKIP Get and set data for VL 8016
7396 13:38:28.830495 # ok 1504 Set VL 8032
7397 13:38:28.830598 # ok 1505 # SKIP Disabled ZA for VL 8032
7398 13:38:28.830710 # ok 1506 # SKIP Get and set data for VL 8032
7399 13:38:28.830810 # ok 1507 Set VL 8048
7400 13:38:28.830896 # ok 1508 # SKIP Disabled ZA for VL 8048
7401 13:38:28.830986 # ok 1509 # SKIP Get and set data for VL 8048
7402 13:38:28.831068 # ok 1510 Set VL 8064
7403 13:38:28.831165 # ok 1511 # SKIP Disabled ZA for VL 8064
7404 13:38:28.831265 # ok 1512 # SKIP Get and set data for VL 8064
7405 13:38:28.831355 # ok 1513 Set VL 8080
7406 13:38:28.831456 # ok 1514 # SKIP Disabled ZA for VL 8080
7407 13:38:28.831559 # ok 1515 # SKIP Get and set data for VL 8080
7408 13:38:28.831641 # ok 1516 Set VL 8096
7409 13:38:28.831753 # ok 1517 # SKIP Disabled ZA for VL 8096
7410 13:38:28.831874 # ok 1518 # SKIP Get and set data for VL 8096
7411 13:38:28.831948 # ok 1519 Set VL 8112
7412 13:38:28.832010 # ok 1520 # SKIP Disabled ZA for VL 8112
7413 13:38:28.832102 # ok 1521 # SKIP Get and set data for VL 8112
7414 13:38:28.832237 # ok 1522 Set VL 8128
7415 13:38:28.832381 # ok 1523 # SKIP Disabled ZA for VL 8128
7416 13:38:28.832516 # ok 1524 # SKIP Get and set data for VL 8128
7417 13:38:28.832644 # ok 1525 Set VL 8144
7418 13:38:28.832777 # ok 1526 # SKIP Disabled ZA for VL 8144
7419 13:38:28.832884 # ok 1527 # SKIP Get and set data for VL 8144
7420 13:38:28.832990 # ok 1528 Set VL 8160
7421 13:38:28.833111 # ok 1529 # SKIP Disabled ZA for VL 8160
7422 13:38:28.833206 # ok 1530 # SKIP Get and set data for VL 8160
7423 13:38:28.833290 # ok 1531 Set VL 8176
7424 13:38:28.833386 # ok 1532 # SKIP Disabled ZA for VL 8176
7425 13:38:28.833490 # ok 1533 # SKIP Get and set data for VL 8176
7426 13:38:28.833579 # ok 1534 Set VL 8192
7427 13:38:28.834036 # ok 1535 # SKIP Disabled ZA for VL 8192
7428 13:38:28.834127 # ok 1536 # SKIP Get and set data for VL 8192
7429 13:38:28.834192 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7430 13:38:28.834254 ok 34 selftests: arm64: za-ptrace
7431 13:38:28.834316 # selftests: arm64: check_buffer_fill
7432 13:38:29.149398 # 1..20
7433 13:38:29.149918 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7434 13:38:29.150144 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7435 13:38:29.150360 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7436 13:38:29.150587 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7437 13:38:29.150755 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7438 13:38:29.150900 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7439 13:38:29.151032 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7440 13:38:29.151204 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7441 13:38:29.151340 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7442 13:38:29.151497 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7443 13:38:29.151678 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7444 13:38:29.151813 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7445 13:38:29.151993 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7446 13:38:29.152254 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7447 13:38:29.152441 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7448 13:38:29.152584 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7449 13:38:29.157456 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7450 13:38:29.157938 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7451 13:38:29.158105 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7452 13:38:29.158463 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7453 13:38:29.158623 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7454 13:38:29.168467 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7455 13:38:29.257931 # selftests: arm64: check_child_memory
7456 13:38:29.842886 # 1..12
7457 13:38:29.843489 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7458 13:38:29.843672 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7459 13:38:29.843806 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7460 13:38:29.843928 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7461 13:38:29.844072 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7462 13:38:29.844192 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7463 13:38:29.844332 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7464 13:38:29.844471 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7465 13:38:29.844810 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7466 13:38:29.844937 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7467 13:38:29.851908 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7468 13:38:29.852472 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7469 13:38:29.852684 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7470 13:38:29.868183 not ok 36 selftests: arm64: check_child_memory # exit=1
7471 13:38:29.986588 # selftests: arm64: check_gcr_el1_cswitch
7472 13:39:15.714326 <47>[ 98.855811] systemd-journald[105]: Data hash table of /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal has a fill level at 75.0 (3329 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
7473 13:39:15.715450 <47>[ 98.859287] systemd-journald[105]: /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal: Journal header limits reached or header out-of-date, rotating.
7474 13:39:15.715698 <47>[ 98.859720] systemd-journald[105]: Rotating...
7475 13:39:15.755785 <47>[ 98.899361] systemd-journald[105]: Reserving 333 entries in field hash table.
7476 13:39:15.799002 <47>[ 98.942931] systemd-journald[105]: Reserving 4437 entries in data hash table.
7477 13:39:15.810891 <47>[ 98.954887] systemd-journald[105]: Vacuuming...
7478 13:39:15.823481 <47>[ 98.967238] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
7479 13:39:16.068820 <47>[ 99.212741] systemd-journald[105]: Sent WATCHDOG=1 notification.
7480 13:39:17.033104 # 1..1
7481 13:39:17.033353 # 1..1
7482 13:39:17.033449 # 1..1
7483 13:39:17.033545 # 1..1
7484 13:39:17.033636 # 1..1
7485 13:39:17.033951 # 1..1
7486 13:39:17.034058 # 1..1
7487 13:39:17.034147 # 1..1
7488 13:39:17.034232 # 1..1
7489 13:39:17.034319 # 1..1
7490 13:39:17.034405 # 1..1
7491 13:39:17.034491 # 1..1
7492 13:39:17.034574 # 1..1
7493 13:39:17.034658 # 1..1
7494 13:39:17.034743 # 1..1
7495 13:39:17.034829 # 1..1
7496 13:39:17.034914 # 1..1
7497 13:39:17.034999 # 1..1
7498 13:39:17.035084 # 1..1
7499 13:39:17.035168 # 1..1
7500 13:39:17.035251 # 1..1
7501 13:39:17.035336 # 1..1
7502 13:39:17.035421 # 1..1
7503 13:39:17.035507 # 1..1
7504 13:39:17.035591 # 1..1
7505 13:39:17.035676 # 1..1
7506 13:39:17.035761 # 1..1
7507 13:39:17.035845 # 1..1
7508 13:39:17.035930 # 1..1
7509 13:39:17.036015 # 1..1
7510 13:39:17.036095 # 1..1
7511 13:39:17.036171 # 1..1
7512 13:39:17.036245 # 1..1
7513 13:39:17.036319 # 1..1
7514 13:39:17.036394 # 1..1
7515 13:39:17.036471 # 1..1
7516 13:39:17.036570 # 1..1
7517 13:39:17.036647 # 1..1
7518 13:39:17.036726 # 1..1
7519 13:39:17.036807 # 1..1
7520 13:39:17.036883 # 1..1
7521 13:39:17.036961 # 1..1
7522 13:39:17.037036 # 1..1
7523 13:39:17.037114 # 1..1
7524 13:39:17.037191 # 1..1
7525 13:39:17.037270 # 1..1
7526 13:39:17.037347 # 1..1
7527 13:39:17.037424 # 1..1
7528 13:39:17.037505 # 1..1
7529 13:39:17.037583 # 1..1
7530 13:39:17.038280 # 1..1
7531 13:39:17.038376 # 1..1
7532 13:39:17.038458 # 1..1
7533 13:39:17.038540 # 1..1
7534 13:39:17.038620 # 1..1
7535 13:39:17.038701 # 1..1
7536 13:39:17.038785 # 1..1
7537 13:39:17.038868 # 1..1
7538 13:39:17.038953 # 1..1
7539 13:39:17.039037 # 1..1
7540 13:39:17.039121 # 1..1
7541 13:39:17.039204 # 1..1
7542 13:39:17.039286 # 1..1
7543 13:39:17.039367 # 1..1
7544 13:39:17.039451 # 1..1
7545 13:39:17.039531 # 1..1
7546 13:39:17.039610 # 1..1
7547 13:39:17.039685 # 1..1
7548 13:39:17.039765 # 1..1
7549 13:39:17.039841 # 1..1
7550 13:39:17.039922 # 1..1
7551 13:39:17.040005 # 1..1
7552 13:39:17.040085 # 1..1
7553 13:39:17.040161 # 1..1
7554 13:39:17.040235 # 1..1
7555 13:39:17.040312 # 1..1
7556 13:39:17.040387 # 1..1
7557 13:39:17.040463 # 1..1
7558 13:39:17.040541 # 1..1
7559 13:39:17.040621 # 1..1
7560 13:39:17.040702 # 1..1
7561 13:39:17.040781 # 1..1
7562 13:39:17.040860 # 1..1
7563 13:39:17.040942 # 1..1
7564 13:39:17.041024 # 1..1
7565 13:39:17.041105 # 1..1
7566 13:39:17.041185 # 1..1
7567 13:39:17.041263 # 1..1
7568 13:39:17.041341 # 1..1
7569 13:39:17.041423 # 1..1
7570 13:39:17.041506 # 1..1
7571 13:39:17.041586 # 1..1
7572 13:39:17.041675 # 1..1
7573 13:39:17.041759 # 1..1
7574 13:39:17.041840 # 1..1
7575 13:39:17.041920 # 1..1
7576 13:39:17.041998 # 1..1
7577 13:39:17.088232 # 1..1
7578 13:39:17.088731 # 1..1
7579 13:39:17.088945 # 1..1
7580 13:39:17.089133 # 1..1
7581 13:39:17.089344 # 1..1
7582 13:39:17.089521 # 1..1
7583 13:39:17.089755 # 1..1
7584 13:39:17.089933 # 1..1
7585 13:39:17.090105 # 1..1
7586 13:39:17.090315 # 1..1
7587 13:39:17.090526 # 1..1
7588 13:39:17.090742 # 1..1
7589 13:39:17.090937 # 1..1
7590 13:39:17.091101 # 1..1
7591 13:39:17.091301 # 1..1
7592 13:39:17.091503 # 1..1
7593 13:39:17.091689 # 1..1
7594 13:39:17.091880 # 1..1
7595 13:39:17.092104 # 1..1
7596 13:39:17.092278 # 1..1
7597 13:39:17.092407 # 1..1
7598 13:39:17.092521 # 1..1
7599 13:39:17.092681 # 1..1
7600 13:39:17.092803 # 1..1
7601 13:39:17.092918 # 1..1
7602 13:39:17.093032 # 1..1
7603 13:39:17.093146 # 1..1
7604 13:39:17.093259 # 1..1
7605 13:39:17.093372 # 1..1
7606 13:39:17.093484 # 1..1
7607 13:39:17.093596 # 1..1
7608 13:39:17.093802 # 1..1
7609 13:39:17.093998 # 1..1
7610 13:39:17.094179 # 1..1
7611 13:39:17.094359 # 1..1
7612 13:39:17.094539 # 1..1
7613 13:39:17.094718 # 1..1
7614 13:39:17.094860 # 1..1
7615 13:39:17.095001 # 1..1
7616 13:39:17.095140 # 1..1
7617 13:39:17.095279 # 1..1
7618 13:39:17.095419 # 1..1
7619 13:39:17.095557 # 1..1
7620 13:39:17.095696 # 1..1
7621 13:39:17.095834 # 1..1
7622 13:39:17.095975 # 1..1
7623 13:39:17.096122 # 1..1
7624 13:39:17.096262 # 1..1
7625 13:39:17.096401 # 1..1
7626 13:39:17.096542 # 1..1
7627 13:39:17.096682 # 1..1
7628 13:39:17.096822 # 1..1
7629 13:39:17.096963 # 1..1
7630 13:39:17.097101 # 1..1
7631 13:39:17.097241 # 1..1
7632 13:39:17.097379 # 1..1
7633 13:39:17.097518 # 1..1
7634 13:39:17.097667 # 1..1
7635 13:39:17.097808 # 1..1
7636 13:39:17.097949 # 1..1
7637 13:39:17.098093 # 1..1
7638 13:39:17.098234 # 1..1
7639 13:39:17.098374 # 1..1
7640 13:39:17.098513 # 1..1
7641 13:39:17.098655 # 1..1
7642 13:39:17.098794 # 1..1
7643 13:39:17.098935 # 1..1
7644 13:39:17.099073 # 1..1
7645 13:39:17.099212 # 1..1
7646 13:39:17.099351 # 1..1
7647 13:39:17.099491 # 1..1
7648 13:39:17.099629 # 1..1
7649 13:39:17.099769 # 1..1
7650 13:39:17.099910 # 1..1
7651 13:39:17.100054 # 1..1
7652 13:39:17.100194 # 1..1
7653 13:39:17.100335 # 1..1
7654 13:39:17.100473 # 1..1
7655 13:39:17.100615 # 1..1
7656 13:39:17.100755 # 1..1
7657 13:39:17.100895 # 1..1
7658 13:39:17.101035 # 1..1
7659 13:39:17.101175 # 1..1
7660 13:39:17.101315 # 1..1
7661 13:39:17.101454 # 1..1
7662 13:39:17.101592 # 1..1
7663 13:39:17.101744 # 1..1
7664 13:39:17.101884 # 1..1
7665 13:39:17.102028 # 1..1
7666 13:39:17.102169 # 1..1
7667 13:39:17.102310 # 1..1
7668 13:39:17.102449 # 1..1
7669 13:39:17.102589 # 1..1
7670 13:39:17.102727 # 1..1
7671 13:39:17.102868 # 1..1
7672 13:39:17.103008 # 1..1
7673 13:39:17.103148 # 1..1
7674 13:39:17.103287 # 1..1
7675 13:39:17.103431 # 1..1
7676 13:39:17.103572 # 1..1
7677 13:39:17.103713 # 1..1
7678 13:39:17.103852 # 1..1
7679 13:39:17.103992 # 1..1
7680 13:39:17.104132 # 1..1
7681 13:39:17.104271 # 1..1
7682 13:39:17.104411 # 1..1
7683 13:39:17.104551 # 1..1
7684 13:39:17.104690 # 1..1
7685 13:39:17.104830 # 1..1
7686 13:39:17.109365 # 1..1
7687 13:39:17.109628 # 1..1
7688 13:39:17.109823 # 1..1
7689 13:39:17.109999 # 1..1
7690 13:39:17.110203 # 1..1
7691 13:39:17.110636 # 1..1
7692 13:39:17.110827 # 1..1
7693 13:39:17.110999 # 1..1
7694 13:39:17.111167 # 1..1
7695 13:39:17.111322 # 1..1
7696 13:39:17.111468 # 1..1
7697 13:39:17.111598 # 1..1
7698 13:39:17.111718 # 1..1
7699 13:39:17.111838 # 1..1
7700 13:39:17.111961 # 1..1
7701 13:39:17.112081 # 1..1
7702 13:39:17.112194 # 1..1
7703 13:39:17.112309 # 1..1
7704 13:39:17.112422 # 1..1
7705 13:39:17.112536 # 1..1
7706 13:39:17.112650 # 1..1
7707 13:39:17.112764 # 1..1
7708 13:39:17.112877 # 1..1
7709 13:39:17.112993 # 1..1
7710 13:39:17.113110 # 1..1
7711 13:39:17.113224 # 1..1
7712 13:39:17.113339 # 1..1
7713 13:39:17.113454 # 1..1
7714 13:39:17.113567 # 1..1
7715 13:39:17.113695 # 1..1
7716 13:39:17.113813 # 1..1
7717 13:39:17.113931 # 1..1
7718 13:39:17.114044 # 1..1
7719 13:39:17.114158 # 1..1
7720 13:39:17.114271 # 1..1
7721 13:39:17.114386 # 1..1
7722 13:39:17.114500 # 1..1
7723 13:39:17.114614 # 1..1
7724 13:39:17.114728 # 1..1
7725 13:39:17.114842 # 1..1
7726 13:39:17.114955 # 1..1
7727 13:39:17.115069 # 1..1
7728 13:39:17.115183 # 1..1
7729 13:39:17.115297 # 1..1
7730 13:39:17.115409 # 1..1
7731 13:39:17.115525 # 1..1
7732 13:39:17.115639 # 1..1
7733 13:39:17.115753 # 1..1
7734 13:39:17.115865 # 1..1
7735 13:39:17.115980 # 1..1
7736 13:39:17.116094 # 1..1
7737 13:39:17.116250 # 1..1
7738 13:39:17.116370 # 1..1
7739 13:39:17.116486 # 1..1
7740 13:39:17.116600 # 1..1
7741 13:39:17.116714 # 1..1
7742 13:39:17.116828 # 1..1
7743 13:39:17.116944 # 1..1
7744 13:39:17.117062 # 1..1
7745 13:39:17.117175 # 1..1
7746 13:39:17.117290 # 1..1
7747 13:39:17.117403 # 1..1
7748 13:39:17.117518 # 1..1
7749 13:39:17.117632 # 1..1
7750 13:39:17.117759 # 1..1
7751 13:39:17.117872 # 1..1
7752 13:39:17.117984 # 1..1
7753 13:39:17.118095 # 1..1
7754 13:39:17.118205 # 1..1
7755 13:39:17.118316 # 1..1
7756 13:39:17.118427 # 1..1
7757 13:39:17.118538 # 1..1
7758 13:39:17.118650 # 1..1
7759 13:39:17.118761 # 1..1
7760 13:39:17.118872 # 1..1
7761 13:39:17.118983 # 1..1
7762 13:39:17.119094 # 1..1
7763 13:39:17.119206 # 1..1
7764 13:39:17.119318 # 1..1
7765 13:39:17.119430 # 1..1
7766 13:39:17.119542 # 1..1
7767 13:39:17.119653 # 1..1
7768 13:39:17.119764 # 1..1
7769 13:39:17.119875 # 1..1
7770 13:39:17.119988 # 1..1
7771 13:39:17.120099 # 1..1
7772 13:39:17.120209 # 1..1
7773 13:39:17.120320 # 1..1
7774 13:39:17.120430 # 1..1
7775 13:39:17.120541 # 1..1
7776 13:39:17.120651 # 1..1
7777 13:39:17.120762 # 1..1
7778 13:39:17.120873 # 1..1
7779 13:39:17.120983 # 1..1
7780 13:39:17.121099 # 1..1
7781 13:39:17.121210 # 1..1
7782 13:39:17.121320 # 1..1
7783 13:39:17.121430 # 1..1
7784 13:39:17.121540 # 1..1
7785 13:39:17.121658 # 1..1
7786 13:39:17.121771 # 1..1
7787 13:39:17.121881 # 1..1
7788 13:39:17.121993 # 1..1
7789 13:39:17.122103 # 1..1
7790 13:39:17.122214 # 1..1
7791 13:39:17.122326 # 1..1
7792 13:39:17.122436 # 1..1
7793 13:39:17.122546 # 1..1
7794 13:39:17.129351 # 1..1
7795 13:39:17.129629 # 1..1
7796 13:39:17.129833 # 1..1
7797 13:39:17.130010 # 1..1
7798 13:39:17.130149 # 1..1
7799 13:39:17.130289 # 1..1
7800 13:39:17.130420 # 1..1
7801 13:39:17.130544 # 1..1
7802 13:39:17.130674 # 1..1
7803 13:39:17.130857 # 1..1
7804 13:39:17.131055 # 1..1
7805 13:39:17.131250 # 1..1
7806 13:39:17.131400 # 1..1
7807 13:39:17.131567 # 1..1
7808 13:39:17.131709 # 1..1
7809 13:39:17.131849 # 1..1
7810 13:39:17.131988 # 1..1
7811 13:39:17.132132 # 1..1
7812 13:39:17.132271 # 1..1
7813 13:39:17.132452 # 1..1
7814 13:39:17.132623 # 1..1
7815 13:39:17.132766 # 1..1
7816 13:39:17.132909 # 1..1
7817 13:39:17.133051 # 1..1
7818 13:39:17.133191 # 1..1
7819 13:39:17.133329 # 1..1
7820 13:39:17.133467 # 1..1
7821 13:39:17.133607 # 1..1
7822 13:39:17.133758 # 1..1
7823 13:39:17.133898 # 1..1
7824 13:39:17.134038 # 1..1
7825 13:39:17.134176 # 1..1
7826 13:39:17.134316 # 1..1
7827 13:39:17.134456 # 1..1
7828 13:39:17.134596 # 1..1
7829 13:39:17.134734 # 1..1
7830 13:39:17.134874 # 1..1
7831 13:39:17.135012 # 1..1
7832 13:39:17.135151 # 1..1
7833 13:39:17.135290 # 1..1
7834 13:39:17.135430 # 1..1
7835 13:39:17.135569 # 1..1
7836 13:39:17.135708 # 1..1
7837 13:39:17.135846 # 1..1
7838 13:39:17.135986 # 1..1
7839 13:39:17.136125 # 1..1
7840 13:39:17.136264 # 1..1
7841 13:39:17.136405 # 1..1
7842 13:39:17.136545 # 1..1
7843 13:39:17.136684 # 1..1
7844 13:39:17.136823 # 1..1
7845 13:39:17.136965 # 1..1
7846 13:39:17.137107 # 1..1
7847 13:39:17.137249 # 1..1
7848 13:39:17.137389 # 1..1
7849 13:39:17.137529 # 1..1
7850 13:39:17.137679 # 1..1
7851 13:39:17.137821 # 1..1
7852 13:39:17.137961 # 1..1
7853 13:39:17.138102 # 1..1
7854 13:39:17.138240 # 1..1
7855 13:39:17.138380 # 1..1
7856 13:39:17.138518 # 1..1
7857 13:39:17.138658 # 1..1
7858 13:39:17.138795 # 1..1
7859 13:39:17.138933 # 1..1
7860 13:39:17.139078 # 1..1
7861 13:39:17.139217 # 1..1
7862 13:39:17.139357 # 1..1
7863 13:39:17.139497 # 1..1
7864 13:39:17.139635 # 1..1
7865 13:39:17.139776 # 1..1
7866 13:39:17.139917 # 1..1
7867 13:39:17.140057 # 1..1
7868 13:39:17.140196 # 1..1
7869 13:39:17.140334 # 1..1
7870 13:39:17.140473 # 1..1
7871 13:39:17.140611 # 1..1
7872 13:39:17.140749 # 1..1
7873 13:39:17.140888 # 1..1
7874 13:39:17.141027 # 1..1
7875 13:39:17.141170 # 1..1
7876 13:39:17.141365 # 1..1
7877 13:39:17.141500 # 1..1
7878 13:39:17.141640 # 1..1
7879 13:39:17.141792 # 1..1
7880 13:39:17.141931 # 1..1
7881 13:39:17.142071 # 1..1
7882 13:39:17.142211 # 1..1
7883 13:39:17.142350 # 1..1
7884 13:39:17.142489 # 1..1
7885 13:39:17.142628 # 1..1
7886 13:39:17.142767 # 1..1
7887 13:39:17.142907 # 1..1
7888 13:39:17.143048 # 1..1
7889 13:39:17.143187 # 1..1
7890 13:39:17.143325 # 1..1
7891 13:39:17.143464 # 1..1
7892 13:39:17.143603 # 1..1
7893 13:39:17.143740 # 1..1
7894 13:39:17.143878 # 1..1
7895 13:39:17.144015 # 1..1
7896 13:39:17.144154 # 1..1
7897 13:39:17.144293 # 1..1
7898 13:39:17.144432 # 1..1
7899 13:39:17.144571 # 1..1
7900 13:39:17.144709 # 1..1
7901 13:39:17.144846 # 1..1
7902 13:39:17.144987 # 1..1
7903 13:39:17.145126 # 1..1
7904 13:39:17.145264 # 1..1
7905 13:39:17.145402 # 1..1
7906 13:39:17.145540 # 1..1
7907 13:39:17.145689 # 1..1
7908 13:39:17.145829 # 1..1
7909 13:39:17.145968 # 1..1
7910 13:39:17.146106 # 1..1
7911 13:39:17.146245 # 1..1
7912 13:39:17.146384 # 1..1
7913 13:39:17.146522 # 1..1
7914 13:39:17.146660 # 1..1
7915 13:39:17.146797 # 1..1
7916 13:39:17.146936 # 1..1
7917 13:39:17.147075 # 1..1
7918 13:39:17.147213 # 1..1
7919 13:39:17.147352 # 1..1
7920 13:39:17.147489 # 1..1
7921 13:39:17.147626 # 1..1
7922 13:39:17.155196 # 1..1
7923 13:39:17.155455 # 1..1
7924 13:39:17.155637 # 1..1
7925 13:39:17.155823 # 1..1
7926 13:39:17.155981 # 1..1
7927 13:39:17.156397 # 1..1
7928 13:39:17.156550 # 1..1
7929 13:39:17.156725 # 1..1
7930 13:39:17.156880 # 1..1
7931 13:39:17.157024 # 1..1
7932 13:39:17.157163 # 1..1
7933 13:39:17.157288 # 1..1
7934 13:39:17.157408 # 1..1
7935 13:39:17.157530 # 1..1
7936 13:39:17.157665 # 1..1
7937 13:39:17.157792 # 1..1
7938 13:39:17.157925 # 1..1
7939 13:39:17.158100 # 1..1
7940 13:39:17.158243 # 1..1
7941 13:39:17.158383 # 1..1
7942 13:39:17.158522 # 1..1
7943 13:39:17.158660 # 1..1
7944 13:39:17.158798 # 1..1
7945 13:39:17.158977 # 1..1
7946 13:39:17.159146 # 1..1
7947 13:39:17.159287 # 1..1
7948 13:39:17.159426 # 1..1
7949 13:39:17.159563 # 1..1
7950 13:39:17.159701 # 1..1
7951 13:39:17.159839 # 1..1
7952 13:39:17.159978 # 1..1
7953 13:39:17.160120 # 1..1
7954 13:39:17.160259 # 1..1
7955 13:39:17.160396 # 1..1
7956 13:39:17.160534 # 1..1
7957 13:39:17.160673 # 1..1
7958 13:39:17.160811 # 1..1
7959 13:39:17.160949 # 1..1
7960 13:39:17.161091 # 1..1
7961 13:39:17.161231 # 1..1
7962 13:39:17.161369 # 1..1
7963 13:39:17.161509 # 1..1
7964 13:39:17.161657 # 1..1
7965 13:39:17.161799 # 1..1
7966 13:39:17.161937 # 1..1
7967 13:39:17.162080 # 1..1
7968 13:39:17.162220 # 1..1
7969 13:39:17.162414 # 1..1
7970 13:39:17.162549 # 1..1
7971 13:39:17.162690 # 1..1
7972 13:39:17.162830 # 1..1
7973 13:39:17.162971 # 1..1
7974 13:39:17.163111 # 1..1
7975 13:39:17.163249 # 1..1
7976 13:39:17.163387 # 1..1
7977 13:39:17.163525 # 1..1
7978 13:39:17.163664 # 1..1
7979 13:39:17.163801 # 1..1
7980 13:39:17.163940 # 1..1
7981 13:39:17.164082 # 1..1
7982 13:39:17.164221 # 1..1
7983 13:39:17.164360 # 1..1
7984 13:39:17.164497 # 1..1
7985 13:39:17.164636 # 1..1
7986 13:39:17.164775 # 1..1
7987 13:39:17.164914 # 1..1
7988 13:39:17.165053 # 1..1
7989 13:39:17.165197 # 1..1
7990 13:39:17.165337 # 1..1
7991 13:39:17.165477 # 1..1
7992 13:39:17.165616 # 1..1
7993 13:39:17.165769 # 1..1
7994 13:39:17.165910 # 1..1
7995 13:39:17.166051 # 1..1
7996 13:39:17.166189 # 1..1
7997 13:39:17.166327 # 1..1
7998 13:39:17.166466 # 1..1
7999 13:39:17.166606 # 1..1
8000 13:39:17.166745 # 1..1
8001 13:39:17.166885 # 1..1
8002 13:39:17.167023 # 1..1
8003 13:39:17.167161 # 1..1
8004 13:39:17.167299 # 1..1
8005 13:39:17.167438 # 1..1
8006 13:39:17.167577 # 1..1
8007 13:39:17.167715 # 1..1
8008 13:39:17.167853 # 1..1
8009 13:39:17.167991 # 1..1
8010 13:39:17.168133 # 1..1
8011 13:39:17.168271 # 1..1
8012 13:39:17.168412 # 1..1
8013 13:39:17.168551 # 1..1
8014 13:39:17.168690 # 1..1
8015 13:39:17.168829 # 1..1
8016 13:39:17.168967 # 1..1
8017 13:39:17.169107 # 1..1
8018 13:39:17.169246 # 1..1
8019 13:39:17.169384 # 1..1
8020 13:39:17.169522 # 1..1
8021 13:39:17.169687 # 1..1
8022 13:39:17.169830 # 1..1
8023 13:39:17.169969 # 1..1
8024 13:39:17.170109 # 1..1
8025 13:39:17.170250 # 1..1
8026 13:39:17.170389 # 1..1
8027 13:39:17.170528 # 1..1
8028 13:39:17.170668 # 1..1
8029 13:39:17.170807 # 1..1
8030 13:39:17.170946 # 1..1
8031 13:39:17.171085 # 1..1
8032 13:39:17.171225 # 1..1
8033 13:39:17.171365 #
8034 13:39:17.171505 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
8035 13:39:17.379136 # selftests: arm64: check_ksm_options
8036 13:39:17.669611 # 1..4
8037 13:39:17.669919 # # Invalid MTE synchronous exception caught!
8038 13:39:17.712017 not ok 38 selftests: arm64: check_ksm_options # exit=1
8039 13:39:17.958588 # selftests: arm64: check_mmap_options
8040 13:39:18.695806 # 1..22
8041 13:39:18.696401 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
8042 13:39:18.696583 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
8043 13:39:18.703652 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
8044 13:39:18.704252 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
8045 13:39:18.704415 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
8046 13:39:18.711516 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8047 13:39:18.712046 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
8048 13:39:18.712246 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8049 13:39:18.712387 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
8050 13:39:18.743218 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8051 13:39:18.743739 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
8052 13:39:18.743951 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8053 13:39:18.744204 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
8054 13:39:18.744391 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8055 13:39:18.767444 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
8056 13:39:18.767930 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8057 13:39:18.768121 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
8058 13:39:18.768307 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8059 13:39:18.769006 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
8060 13:39:18.769423 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8061 13:39:18.769563 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
8062 13:39:18.769928 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
8063 13:39:18.770080 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
8064 13:39:18.770668 not ok 39 selftests: arm64: check_mmap_options # exit=1
8065 13:39:19.010594 # selftests: arm64: check_prctl
8066 13:39:19.275198 # TAP version 13
8067 13:39:19.275485 # 1..5
8068 13:39:19.275890 # ok 1 check_basic_read
8069 13:39:19.276033 # ok 2 NONE
8070 13:39:19.276179 # ok 3 SYNC
8071 13:39:19.276321 # ok 4 ASYNC
8072 13:39:19.276461 # ok 5 SYNC+ASYNC
8073 13:39:19.276602 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8074 13:39:19.313032 ok 40 selftests: arm64: check_prctl
8075 13:39:19.548297 # selftests: arm64: check_tags_inclusion
8076 13:39:19.752141 # 1..4
8077 13:39:19.752359 # # Unexpected fault recorded for 0x200ffffabe73000-0x200ffffabe73050 in mode 1
8078 13:39:19.752538 # not ok 1 Check an included tag value with sync mode
8079 13:39:19.755446 # # Unexpected fault recorded for 0x600ffffabe73000-0x600ffffabe73050 in mode 1
8080 13:39:19.755897 # not ok 2 Check different included tags value with sync mode
8081 13:39:19.756065 # ok 3 Check none included tags value with sync mode
8082 13:39:19.756203 # # Unexpected fault recorded for 0xb00ffffabe73000-0xb00ffffabe73050 in mode 1
8083 13:39:19.756350 # not ok 4 Check all included tags value with sync mode
8084 13:39:19.757569 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
8085 13:39:19.767693 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
8086 13:39:19.849609 # selftests: arm64: check_user_mem
8087 13:39:27.942256 # 1..64
8088 13:39:27.942603 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8089 13:39:27.942974 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8090 13:39:27.943084 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8091 13:39:27.943173 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8092 13:39:27.943263 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8093 13:39:27.943353 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8094 13:39:27.943464 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8095 13:39:27.943558 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8096 13:39:27.943666 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8097 13:39:27.943767 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8098 13:39:27.944058 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8099 13:39:27.945177 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8100 13:39:27.945636 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8101 13:39:27.946127 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8102 13:39:27.946369 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8103 13:39:27.946587 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8104 13:39:27.946826 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8105 13:39:27.947071 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8106 13:39:27.947302 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8107 13:39:27.947466 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8108 13:39:27.947695 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8109 13:39:27.947912 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8110 13:39:27.948534 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8111 13:39:27.953443 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8112 13:39:27.953852 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8113 13:39:27.954040 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8114 13:39:27.954229 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8115 13:39:27.954394 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8116 13:39:27.954581 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8117 13:39:27.954732 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8118 13:39:27.954947 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8119 13:39:27.955131 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8120 13:39:27.955326 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8121 13:39:27.955489 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8122 13:39:27.955652 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8123 13:39:27.956058 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8124 13:39:27.956214 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8125 13:39:27.956345 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8126 13:39:27.961314 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8127 13:39:27.961735 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8128 13:39:27.961929 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8129 13:39:27.962159 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8130 13:39:27.962324 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8131 13:39:27.962548 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8132 13:39:27.962704 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8133 13:39:27.962896 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8134 13:39:27.963057 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8135 13:39:27.963245 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8136 13:39:27.963427 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8137 13:39:27.963868 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8138 13:39:27.964034 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8139 13:39:29.605817 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8140 13:39:29.606389 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8141 13:39:29.606551 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8142 13:39:29.606722 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8143 13:39:29.606918 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8144 13:39:29.607147 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8145 13:39:29.607321 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8146 13:39:29.607535 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8147 13:39:29.607751 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8148 13:39:29.607958 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8149 13:39:29.608090 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8150 13:39:29.608209 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8151 13:39:29.608325 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8152 13:39:29.608464 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
8153 13:39:29.630468 ok 42 selftests: arm64: check_user_mem
8154 13:39:29.733948 # selftests: arm64: btitest
8155 13:39:29.880118 # TAP version 13
8156 13:39:29.880409 # 1..18
8157 13:39:29.880555 # # HWCAP_PACA present
8158 13:39:29.880697 # # HWCAP2_BTI present
8159 13:39:29.880838 # # Test binary built for BTI
8160 13:39:29.883267 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
8161 13:39:29.883378 # ok 1 nohint_func/call_using_br_x0
8162 13:39:29.883495 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
8163 13:39:29.883588 # ok 2 nohint_func/call_using_br_x16
8164 13:39:29.883889 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
8165 13:39:29.883991 # ok 3 nohint_func/call_using_blr
8166 13:39:29.884093 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
8167 13:39:29.884195 # ok 4 bti_none_func/call_using_br_x0
8168 13:39:29.888155 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
8169 13:39:29.888343 # ok 5 bti_none_func/call_using_br_x16
8170 13:39:29.889348 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
8171 13:39:29.889532 # ok 6 bti_none_func/call_using_blr
8172 13:39:29.889737 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
8173 13:39:29.889901 # ok 7 bti_c_func/call_using_br_x0
8174 13:39:29.890045 # ok 8 bti_c_func/call_using_br_x16
8175 13:39:29.890182 # ok 9 bti_c_func/call_using_blr
8176 13:39:29.890321 # ok 10 bti_j_func/call_using_br_x0
8177 13:39:29.890512 # ok 11 bti_j_func/call_using_br_x16
8178 13:39:29.890708 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
8179 13:39:29.890891 # ok 12 bti_j_func/call_using_blr
8180 13:39:29.891032 # ok 13 bti_jc_func/call_using_br_x0
8181 13:39:29.891153 # ok 14 bti_jc_func/call_using_br_x16
8182 13:39:29.891343 # ok 15 bti_jc_func/call_using_blr
8183 13:39:29.891511 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
8184 13:39:29.891638 # ok 16 paciasp_func/call_using_br_x0
8185 13:39:29.891755 # ok 17 paciasp_func/call_using_br_x16
8186 13:39:29.891871 # ok 18 paciasp_func/call_using_blr
8187 13:39:29.891986 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8188 13:39:29.910882 ok 43 selftests: arm64: btitest
8189 13:39:30.019121 # selftests: arm64: nobtitest
8190 13:39:30.120068 # TAP version 13
8191 13:39:30.120283 # 1..18
8192 13:39:30.120384 # # HWCAP_PACA present
8193 13:39:30.122952 # # HWCAP2_BTI present
8194 13:39:30.123557 # # Test binary not built for BTI
8195 13:39:30.123753 # ok 1 nohint_func/call_using_br_x0
8196 13:39:30.123916 # ok 2 nohint_func/call_using_br_x16
8197 13:39:30.124071 # ok 3 nohint_func/call_using_blr
8198 13:39:30.124233 # ok 4 bti_none_func/call_using_br_x0
8199 13:39:30.124366 # ok 5 bti_none_func/call_using_br_x16
8200 13:39:30.124513 # ok 6 bti_none_func/call_using_blr
8201 13:39:30.124637 # ok 7 bti_c_func/call_using_br_x0
8202 13:39:30.124754 # ok 8 bti_c_func/call_using_br_x16
8203 13:39:30.124871 # ok 9 bti_c_func/call_using_blr
8204 13:39:30.124986 # ok 10 bti_j_func/call_using_br_x0
8205 13:39:30.125101 # ok 11 bti_j_func/call_using_br_x16
8206 13:39:30.125218 # ok 12 bti_j_func/call_using_blr
8207 13:39:30.125403 # ok 13 bti_jc_func/call_using_br_x0
8208 13:39:30.125594 # ok 14 bti_jc_func/call_using_br_x16
8209 13:39:30.125800 # ok 15 bti_jc_func/call_using_blr
8210 13:39:30.125998 # ok 16 paciasp_func/call_using_br_x0
8211 13:39:30.126223 # ok 17 paciasp_func/call_using_br_x16
8212 13:39:30.126377 # ok 18 paciasp_func/call_using_blr
8213 13:39:30.126522 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8214 13:39:30.146150 ok 44 selftests: arm64: nobtitest
8215 13:39:30.233770 # selftests: arm64: hwcap
8216 13:39:30.362162 # TAP version 13
8217 13:39:30.362480 # 1..28
8218 13:39:30.362847 # # RNG present
8219 13:39:30.362945 # ok 1 cpuinfo_match_RNG
8220 13:39:30.363027 # ok 2 sigill_RNG
8221 13:39:30.363112 # # SME present
8222 13:39:30.363194 # ok 3 cpuinfo_match_SME
8223 13:39:30.363273 # ok 4 sigill_SME
8224 13:39:30.363336 # # SVE present
8225 13:39:30.363396 # ok 5 cpuinfo_match_SVE
8226 13:39:30.363460 # ok 6 sigill_SVE
8227 13:39:30.363522 # # SVE 2 present
8228 13:39:30.363584 # ok 7 cpuinfo_match_SVE 2
8229 13:39:30.363644 # ok 8 sigill_SVE 2
8230 13:39:30.363707 # # SVE AES present
8231 13:39:30.363784 # ok 9 cpuinfo_match_SVE AES
8232 13:39:30.363850 # ok 10 sigill_SVE AES
8233 13:39:30.363911 # # SVE2 PMULL present
8234 13:39:30.363972 # ok 11 cpuinfo_match_SVE2 PMULL
8235 13:39:30.364034 # ok 12 sigill_SVE2 PMULL
8236 13:39:30.364102 # # SVE2 BITPERM present
8237 13:39:30.364163 # ok 13 cpuinfo_match_SVE2 BITPERM
8238 13:39:30.364222 # ok 14 sigill_SVE2 BITPERM
8239 13:39:30.364290 # # SVE2 SHA3 present
8240 13:39:30.364365 # ok 15 cpuinfo_match_SVE2 SHA3
8241 13:39:30.364432 # ok 16 sigill_SVE2 SHA3
8242 13:39:30.364508 # # SVE2 SM4 present
8243 13:39:30.364570 # ok 17 cpuinfo_match_SVE2 SM4
8244 13:39:30.364629 # ok 18 sigill_SVE2 SM4
8245 13:39:30.364687 # # SVE2 I8MM present
8246 13:39:30.364745 # ok 19 cpuinfo_match_SVE2 I8MM
8247 13:39:30.364804 # ok 20 sigill_SVE2 I8MM
8248 13:39:30.371885 # # SVE2 F32MM present
8249 13:39:30.372345 # ok 21 cpuinfo_match_SVE2 F32MM
8250 13:39:30.372499 # ok 22 sigill_SVE2 F32MM
8251 13:39:30.372626 # # SVE2 F64MM present
8252 13:39:30.382290 # ok 23 cpuinfo_match_SVE2 F64MM
8253 13:39:30.382505 # ok 24 sigill_SVE2 F64MM
8254 13:39:30.382713 # # SVE2 BF16 present
8255 13:39:30.383100 # ok 25 cpuinfo_match_SVE2 BF16
8256 13:39:30.383242 # ok 26 sigill_SVE2 BF16
8257 13:39:30.383385 # ok 27 cpuinfo_match_SVE2 EBF16
8258 13:39:30.383527 # ok 28 # SKIP sigill_SVE2 EBF16
8259 13:39:30.383668 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
8260 13:39:30.390044 ok 45 selftests: arm64: hwcap
8261 13:39:30.506466 # selftests: arm64: ptrace
8262 13:39:30.637271 # TAP version 13
8263 13:39:30.637610 # 1..7
8264 13:39:30.637783 # # Parent is 4587, child is 4588
8265 13:39:30.638179 # ok 1 read_tpidr_one
8266 13:39:30.638317 # ok 2 write_tpidr_one
8267 13:39:30.638435 # ok 3 verify_tpidr_one
8268 13:39:30.638556 # ok 4 count_tpidrs
8269 13:39:30.638680 # ok 5 tpidr2_write
8270 13:39:30.638854 # ok 6 tpidr2_read
8271 13:39:30.638998 # ok 7 write_tpidr_only
8272 13:39:30.639140 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
8273 13:39:30.657428 ok 46 selftests: arm64: ptrace
8274 13:39:30.740144 # selftests: arm64: syscall-abi
8275 13:39:33.332831 # TAP version 13
8276 13:39:33.333118 # 1..514
8277 13:39:33.333540 # # SME with FA64
8278 13:39:33.333724 # ok 1 getpid() FPSIMD
8279 13:39:33.333853 # ok 2 getpid() SVE VL 256
8280 13:39:33.333970 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
8281 13:39:33.334087 # ok 4 getpid() SVE VL 256/SME VL 256 SM
8282 13:39:33.334212 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
8283 13:39:33.334330 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
8284 13:39:33.334474 # ok 7 getpid() SVE VL 256/SME VL 128 SM
8285 13:39:33.334594 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
8286 13:39:33.334722 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
8287 13:39:33.334889 # ok 10 getpid() SVE VL 256/SME VL 64 SM
8288 13:39:33.335021 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
8289 13:39:33.335146 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
8290 13:39:33.335299 # ok 13 getpid() SVE VL 256/SME VL 32 SM
8291 13:39:33.335477 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
8292 13:39:33.335633 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
8293 13:39:33.335840 # ok 16 getpid() SVE VL 256/SME VL 16 SM
8294 13:39:33.336021 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
8295 13:39:33.336229 # ok 18 getpid() SVE VL 240
8296 13:39:33.336405 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
8297 13:39:33.336542 # ok 20 getpid() SVE VL 240/SME VL 256 SM
8298 13:39:33.336661 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
8299 13:39:33.336776 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
8300 13:39:33.336893 # ok 23 getpid() SVE VL 240/SME VL 128 SM
8301 13:39:33.337008 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8302 13:39:33.337125 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8303 13:39:33.337240 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8304 13:39:33.337356 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8305 13:39:33.337472 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8306 13:39:33.337615 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8307 13:39:33.337755 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8308 13:39:33.337874 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8309 13:39:33.341238 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8310 13:39:33.341708 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8311 13:39:33.341910 # ok 34 getpid() SVE VL 224
8312 13:39:33.342085 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8313 13:39:33.342256 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8314 13:39:33.342401 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8315 13:39:33.342600 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8316 13:39:33.342732 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8317 13:39:33.342858 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8318 13:39:33.343025 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8319 13:39:33.343190 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8320 13:39:33.343356 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8321 13:39:33.343500 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8322 13:39:33.343617 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8323 13:39:33.343734 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8324 13:39:33.343855 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8325 13:39:33.343976 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8326 13:39:33.344136 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8327 13:39:33.344258 # ok 50 getpid() SVE VL 208
8328 13:39:33.344374 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8329 13:39:33.344488 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8330 13:39:33.344603 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8331 13:39:33.344716 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8332 13:39:33.344830 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8333 13:39:33.344944 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8334 13:39:33.345058 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8335 13:39:33.345173 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8336 13:39:33.345285 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8337 13:39:33.345397 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8338 13:39:33.345510 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8339 13:39:33.345624 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8340 13:39:33.345850 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8341 13:39:33.348539 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8342 13:39:33.348863 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8343 13:39:33.349328 # ok 66 getpid() SVE VL 192
8344 13:39:33.349549 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8345 13:39:33.349810 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8346 13:39:33.350016 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8347 13:39:33.350221 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8348 13:39:33.350430 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8349 13:39:33.350668 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8350 13:39:33.350843 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8351 13:39:33.351012 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8352 13:39:33.351191 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8353 13:39:33.351402 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8354 13:39:33.351601 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8355 13:39:33.351788 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8356 13:39:33.352003 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8357 13:39:33.352175 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8358 13:39:33.352323 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8359 13:39:33.352465 # ok 82 getpid() SVE VL 176
8360 13:39:33.352608 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8361 13:39:33.352754 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8362 13:39:33.352939 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8363 13:39:33.353075 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8364 13:39:33.353220 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8365 13:39:33.353364 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8366 13:39:33.353507 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8367 13:39:33.353685 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8368 13:39:33.353858 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8369 13:39:33.354003 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8370 13:39:33.354147 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8371 13:39:33.354291 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8372 13:39:33.354432 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8373 13:39:33.354573 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8374 13:39:33.354713 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8375 13:39:33.354854 # ok 98 getpid() SVE VL 160
8376 13:39:36.082721 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8377 13:39:36.082974 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8378 13:39:36.085789 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8379 13:39:36.086132 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8380 13:39:36.086324 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8381 13:39:36.086517 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8382 13:39:36.086708 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8383 13:39:36.086861 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8384 13:39:36.087044 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8385 13:39:36.087227 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8386 13:39:36.087407 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8387 13:39:36.087535 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8388 13:39:36.087652 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8389 13:39:36.087768 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8390 13:39:36.087885 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8391 13:39:36.088013 # ok 114 getpid() SVE VL 144
8392 13:39:36.088170 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8393 13:39:36.088302 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8394 13:39:36.088420 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8395 13:39:36.088535 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8396 13:39:36.088650 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8397 13:39:36.088763 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8398 13:39:36.088880 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8399 13:39:36.089042 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8400 13:39:36.089166 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8401 13:39:36.089282 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8402 13:39:36.089396 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8403 13:39:36.089512 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8404 13:39:36.089626 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8405 13:39:36.089759 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8406 13:39:36.089874 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8407 13:39:36.089993 # ok 130 getpid() SVE VL 128
8408 13:39:36.090107 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8409 13:39:36.090222 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8410 13:39:36.090336 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8411 13:39:36.090450 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8412 13:39:36.090565 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8413 13:39:36.090680 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8414 13:39:36.090798 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8415 13:39:36.090916 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8416 13:39:36.091031 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8417 13:39:36.091145 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8418 13:39:36.091273 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8419 13:39:36.091432 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8420 13:39:36.091566 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8421 13:39:36.091684 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8422 13:39:36.092038 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8423 13:39:36.092817 # ok 146 getpid() SVE VL 112
8424 13:39:36.093198 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8425 13:39:36.093400 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8426 13:39:36.093613 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8427 13:39:36.093794 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8428 13:39:36.093940 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8429 13:39:36.094125 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8430 13:39:36.094264 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8431 13:39:36.094467 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8432 13:39:36.094621 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8433 13:39:36.094779 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8434 13:39:36.094935 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8435 13:39:36.095149 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8436 13:39:36.095340 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8437 13:39:36.095468 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8438 13:39:36.095586 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8439 13:39:36.095702 # ok 162 getpid() SVE VL 96
8440 13:39:36.095819 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8441 13:39:36.095937 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8442 13:39:36.096091 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8443 13:39:36.096259 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8444 13:39:36.096382 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8445 13:39:36.096499 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8446 13:39:36.096690 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8447 13:39:36.096878 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8448 13:39:36.097053 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8449 13:39:36.097231 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8450 13:39:36.097415 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8451 13:39:36.097585 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8452 13:39:36.097743 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8453 13:39:36.100728 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8454 13:39:36.101173 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8455 13:39:36.101374 # ok 178 getpid() SVE VL 80
8456 13:39:36.101537 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8457 13:39:36.101730 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8458 13:39:36.101911 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8459 13:39:36.102087 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8460 13:39:36.102297 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8461 13:39:36.102469 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8462 13:39:36.102646 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8463 13:39:36.102822 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8464 13:39:36.103000 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8465 13:39:36.103175 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8466 13:39:36.103348 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8467 13:39:36.103518 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8468 13:39:36.103693 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8469 13:39:36.103867 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8470 13:39:36.104042 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8471 13:39:36.104216 # ok 194 getpid() SVE VL 64
8472 13:39:36.104384 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8473 13:39:38.399905 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8474 13:39:38.400244 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8475 13:39:38.400683 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8476 13:39:38.400844 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8477 13:39:38.400967 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8478 13:39:38.401234 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8479 13:39:38.401440 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8480 13:39:38.401668 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8481 13:39:38.401848 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8482 13:39:38.402013 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8483 13:39:38.402185 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8484 13:39:38.402354 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8485 13:39:38.402521 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8486 13:39:38.402729 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8487 13:39:38.402894 # ok 210 getpid() SVE VL 48
8488 13:39:38.403058 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8489 13:39:38.403239 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8490 13:39:38.403437 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8491 13:39:38.403646 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8492 13:39:38.403848 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8493 13:39:38.404029 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8494 13:39:38.404192 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8495 13:39:38.404323 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8496 13:39:38.404447 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8497 13:39:38.404569 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8498 13:39:38.404691 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8499 13:39:38.404810 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8500 13:39:38.404931 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8501 13:39:38.405090 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8502 13:39:38.405221 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8503 13:39:38.405340 # ok 226 getpid() SVE VL 32
8504 13:39:38.405460 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8505 13:39:38.405576 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8506 13:39:38.405708 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8507 13:39:38.405823 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8508 13:39:38.405935 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8509 13:39:38.406054 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8510 13:39:38.406168 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8511 13:39:38.406285 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8512 13:39:38.406399 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8513 13:39:38.406515 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8514 13:39:38.406630 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8515 13:39:38.406749 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8516 13:39:38.406864 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8517 13:39:38.406977 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8518 13:39:38.407090 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8519 13:39:38.408361 # ok 242 getpid() SVE VL 16
8520 13:39:38.408846 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8521 13:39:38.409029 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8522 13:39:38.409198 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8523 13:39:38.409372 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8524 13:39:38.409520 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8525 13:39:38.409680 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8526 13:39:38.409805 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8527 13:39:38.409925 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8528 13:39:38.410077 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8529 13:39:38.410204 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8530 13:39:38.410327 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8531 13:39:38.410446 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8532 13:39:38.410564 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8533 13:39:38.410682 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8534 13:39:38.410800 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8535 13:39:38.410950 # ok 258 sched_yield() FPSIMD
8536 13:39:38.411100 # ok 259 sched_yield() SVE VL 256
8537 13:39:38.411260 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8538 13:39:38.411433 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8539 13:39:38.411599 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8540 13:39:38.411764 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8541 13:39:38.411923 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8542 13:39:38.412073 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8543 13:39:38.412201 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8544 13:39:38.412320 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8545 13:39:38.412439 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8546 13:39:38.412564 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8547 13:39:38.412682 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8548 13:39:38.412800 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8549 13:39:38.412916 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8550 13:39:38.413032 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8551 13:39:38.413149 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8552 13:39:38.413267 # ok 275 sched_yield() SVE VL 240
8553 13:39:38.413395 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8554 13:39:38.413513 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8555 13:39:38.413629 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8556 13:39:38.413761 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8557 13:39:38.413879 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8558 13:39:38.414021 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8559 13:39:38.414145 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8560 13:39:38.414263 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8561 13:39:38.416409 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8562 13:39:38.416606 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8563 13:39:38.416981 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8564 13:39:38.417116 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8565 13:39:38.417236 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8566 13:39:38.417355 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8567 13:39:40.420747 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8568 13:39:40.421175 # ok 291 sched_yield() SVE VL 224
8569 13:39:40.421285 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8570 13:39:40.421374 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8571 13:39:40.421460 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8572 13:39:40.421566 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8573 13:39:40.421661 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8574 13:39:40.421748 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8575 13:39:40.421849 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8576 13:39:40.421953 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8577 13:39:40.422041 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8578 13:39:40.422147 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8579 13:39:40.422446 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8580 13:39:40.422547 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8581 13:39:40.422648 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8582 13:39:40.422735 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8583 13:39:40.422835 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8584 13:39:40.423116 # ok 307 sched_yield() SVE VL 208
8585 13:39:40.423206 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8586 13:39:40.423306 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8587 13:39:40.423391 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8588 13:39:40.423489 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8589 13:39:40.423574 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8590 13:39:40.423673 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8591 13:39:40.423958 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8592 13:39:40.424050 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8593 13:39:40.424138 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8594 13:39:40.424240 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8595 13:39:40.432635 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8596 13:39:40.432836 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8597 13:39:40.432931 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8598 13:39:40.433038 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8599 13:39:40.433130 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8600 13:39:40.433217 # ok 323 sched_yield() SVE VL 192
8601 13:39:40.433306 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8602 13:39:40.433412 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8603 13:39:40.433500 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8604 13:39:40.433585 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8605 13:39:40.433677 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8606 13:39:40.433766 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8607 13:39:40.433873 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8608 13:39:40.433961 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8609 13:39:40.434052 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8610 13:39:40.434155 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8611 13:39:40.434243 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8612 13:39:40.434327 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8613 13:39:40.434415 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8614 13:39:40.434502 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8615 13:39:40.434609 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8616 13:39:40.434701 # ok 339 sched_yield() SVE VL 176
8617 13:39:40.434787 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8618 13:39:40.434876 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8619 13:39:40.434980 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8620 13:39:40.435072 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8621 13:39:40.435157 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8622 13:39:40.435241 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8623 13:39:40.435341 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8624 13:39:40.435426 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8625 13:39:40.435510 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8626 13:39:40.435612 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8627 13:39:40.435699 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8628 13:39:40.435783 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8629 13:39:40.435868 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8630 13:39:40.435952 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8631 13:39:40.436053 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8632 13:39:40.436142 # ok 355 sched_yield() SVE VL 160
8633 13:39:40.436227 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8634 13:39:40.436310 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8635 13:39:40.436394 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8636 13:39:40.436917 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8637 13:39:40.437136 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8638 13:39:40.437328 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8639 13:39:40.437490 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8640 13:39:40.437644 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8641 13:39:40.437786 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8642 13:39:40.437903 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8643 13:39:40.438020 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8644 13:39:40.438168 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8645 13:39:40.438292 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8646 13:39:40.438410 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8647 13:39:40.438525 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8648 13:39:40.438640 # ok 371 sched_yield() SVE VL 144
8649 13:39:40.438756 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8650 13:39:40.438871 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8651 13:39:40.438987 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8652 13:39:40.439100 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8653 13:39:40.439215 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8654 13:39:42.497868 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8655 13:39:42.498297 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8656 13:39:42.498394 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8657 13:39:42.498483 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8658 13:39:42.498585 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8659 13:39:42.498672 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8660 13:39:42.498756 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8661 13:39:42.498854 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8662 13:39:42.498955 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8663 13:39:42.499046 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8664 13:39:42.499143 # ok 387 sched_yield() SVE VL 128
8665 13:39:42.499436 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8666 13:39:42.499550 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8667 13:39:42.499636 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8668 13:39:42.499733 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8669 13:39:42.499831 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8670 13:39:42.499927 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8671 13:39:42.500236 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8672 13:39:42.506828 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8673 13:39:42.507156 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8674 13:39:42.507623 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8675 13:39:42.507815 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8676 13:39:42.507984 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8677 13:39:42.508146 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8678 13:39:42.508276 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8679 13:39:42.508392 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8680 13:39:42.508510 # ok 403 sched_yield() SVE VL 112
8681 13:39:42.508660 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8682 13:39:42.508847 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8683 13:39:42.509002 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8684 13:39:42.509149 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8685 13:39:42.509304 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8686 13:39:42.509461 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8687 13:39:42.509606 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8688 13:39:42.509769 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8689 13:39:42.509888 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8690 13:39:42.510040 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8691 13:39:42.510178 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8692 13:39:42.510302 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8693 13:39:42.510423 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8694 13:39:42.510545 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8695 13:39:42.510666 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8696 13:39:42.510789 # ok 419 sched_yield() SVE VL 96
8697 13:39:42.510942 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8698 13:39:42.511068 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8699 13:39:42.511191 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8700 13:39:42.511311 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8701 13:39:42.511430 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8702 13:39:42.511553 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8703 13:39:42.511674 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8704 13:39:42.511823 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8705 13:39:42.511952 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8706 13:39:42.512074 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8707 13:39:42.512189 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8708 13:39:42.512303 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8709 13:39:42.512415 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8710 13:39:42.512527 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8711 13:39:42.512666 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8712 13:39:42.512783 # ok 435 sched_yield() SVE VL 80
8713 13:39:42.512909 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8714 13:39:42.513061 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8715 13:39:42.516655 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8716 13:39:42.516904 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8717 13:39:42.517093 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8718 13:39:42.517264 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8719 13:39:42.517408 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8720 13:39:42.517605 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8721 13:39:42.517771 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8722 13:39:42.517932 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8723 13:39:42.518123 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8724 13:39:42.518278 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8725 13:39:42.518440 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8726 13:39:42.518583 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8727 13:39:42.518751 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8728 13:39:42.518931 # ok 451 sched_yield() SVE VL 64
8729 13:39:42.519095 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8730 13:39:42.519252 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8731 13:39:42.519437 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8732 13:39:42.519601 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8733 13:39:42.519746 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8734 13:39:42.519912 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8735 13:39:42.520061 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8736 13:39:42.520215 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8737 13:39:42.520374 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8738 13:39:42.520516 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8739 13:39:42.520681 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8740 13:39:42.520827 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8741 13:39:43.187459 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8742 13:39:43.187782 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8743 13:39:43.188232 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8744 13:39:43.188435 # ok 467 sched_yield() SVE VL 48
8745 13:39:43.188575 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8746 13:39:43.188697 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8747 13:39:43.188814 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8748 13:39:43.189788 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8749 13:39:43.191156 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8750 13:39:43.191495 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8751 13:39:43.191608 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8752 13:39:43.191696 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8753 13:39:43.191981 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8754 13:39:43.192112 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8755 13:39:43.198609 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8756 13:39:43.199035 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8757 13:39:43.199152 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8758 13:39:43.199224 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8759 13:39:43.199300 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8760 13:39:43.199389 # ok 483 sched_yield() SVE VL 32
8761 13:39:43.199507 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8762 13:39:43.199609 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8763 13:39:43.199726 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8764 13:39:43.199829 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8765 13:39:43.199945 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8766 13:39:43.200055 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8767 13:39:43.200135 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8768 13:39:43.200515 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8769 13:39:43.200828 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8770 13:39:43.200979 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8771 13:39:43.201090 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8772 13:39:43.201178 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8773 13:39:43.201308 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8774 13:39:43.201398 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8775 13:39:43.201521 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8776 13:39:43.201661 # ok 499 sched_yield() SVE VL 16
8777 13:39:43.201755 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8778 13:39:43.201883 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8779 13:39:43.201986 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8780 13:39:43.202113 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8781 13:39:43.202240 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8782 13:39:43.202529 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8783 13:39:43.202646 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8784 13:39:43.202734 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8785 13:39:43.202866 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8786 13:39:43.202952 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8787 13:39:43.203075 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8788 13:39:43.203422 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8789 13:39:43.203529 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8790 13:39:43.203645 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8791 13:39:43.203773 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8792 13:39:43.203863 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8793 13:39:43.203994 ok 47 selftests: arm64: syscall-abi
8794 13:39:43.248643 # selftests: arm64: tpidr2
8795 13:39:43.401073 # TAP version 13
8796 13:39:43.401302 # 1..5
8797 13:39:43.401599 # # PID: 4622
8798 13:39:43.401702 # ok 1 default_value
8799 13:39:43.401791 # ok 2 write_read
8800 13:39:43.401878 # ok 3 write_sleep_read
8801 13:39:43.401981 # ok 4 write_fork_read
8802 13:39:43.402071 # ok 5 write_clone_read
8803 13:39:43.402157 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8804 13:39:43.416895 ok 48 selftests: arm64: tpidr2
8805 13:39:43.891296 arm64_tags_test pass
8806 13:39:43.891847 arm64_run_tags_test_sh pass
8807 13:39:43.892009 arm64_fake_sigreturn_bad_magic pass
8808 13:39:43.892146 arm64_fake_sigreturn_bad_size pass
8809 13:39:43.892271 arm64_fake_sigreturn_bad_size_for_magic0 pass
8810 13:39:43.892402 arm64_fake_sigreturn_duplicated_fpsimd pass
8811 13:39:43.892518 arm64_fake_sigreturn_misaligned_sp pass
8812 13:39:43.892659 arm64_fake_sigreturn_missing_fpsimd pass
8813 13:39:43.892789 arm64_fake_sigreturn_sme_change_vl pass
8814 13:39:43.892950 arm64_fake_sigreturn_sve_change_vl pass
8815 13:39:43.893080 arm64_mangle_pstate_invalid_compat_toggle pass
8816 13:39:43.893209 arm64_mangle_pstate_invalid_daif_bits pass
8817 13:39:43.893332 arm64_mangle_pstate_invalid_mode_el1h pass
8818 13:39:43.893455 arm64_mangle_pstate_invalid_mode_el1t pass
8819 13:39:43.893643 arm64_mangle_pstate_invalid_mode_el2h pass
8820 13:39:43.893786 arm64_mangle_pstate_invalid_mode_el2t pass
8821 13:39:43.893919 arm64_mangle_pstate_invalid_mode_el3h pass
8822 13:39:43.894043 arm64_mangle_pstate_invalid_mode_el3t pass
8823 13:39:43.894183 arm64_sme_trap_no_sm pass
8824 13:39:43.894335 arm64_sme_trap_non_streaming skip
8825 13:39:43.894510 arm64_sme_trap_za pass
8826 13:39:43.894661 arm64_sme_vl pass
8827 13:39:43.894813 arm64_ssve_regs pass
8828 13:39:43.894961 arm64_sve_regs pass
8829 13:39:43.895128 arm64_sve_vl pass
8830 13:39:43.895340 arm64_za_no_regs pass
8831 13:39:43.895503 arm64_za_regs pass
8832 13:39:43.895659 arm64_pac_global_corrupt_pac pass
8833 13:39:43.895809 arm64_pac_global_pac_instructions_not_nop pass
8834 13:39:43.895956 arm64_pac_global_pac_instructions_not_nop_generic pass
8835 13:39:43.896099 arm64_pac_global_single_thread_different_keys pass
8836 13:39:43.896218 arm64_pac_global_exec_changed_keys pass
8837 13:39:43.896329 arm64_pac_global_context_switch_keep_keys pass
8838 13:39:43.896441 arm64_pac_global_context_switch_keep_keys_generic pass
8839 13:39:43.896556 arm64_pac pass
8840 13:39:43.896669 arm64_fp-stress_FPSIMD-0-0 pass
8841 13:39:43.896784 arm64_fp-stress_SVE-VL-256-0 pass
8842 13:39:43.896896 arm64_fp-stress_SVE-VL-240-0 pass
8843 13:39:43.897008 arm64_fp-stress_SVE-VL-224-0 pass
8844 13:39:43.897120 arm64_fp-stress_SVE-VL-208-0 pass
8845 13:39:43.897233 arm64_fp-stress_SVE-VL-192-0 pass
8846 13:39:43.897344 arm64_fp-stress_SVE-VL-176-0 pass
8847 13:39:43.897457 arm64_fp-stress_SVE-VL-160-0 pass
8848 13:39:43.897569 arm64_fp-stress_SVE-VL-144-0 pass
8849 13:39:43.897696 arm64_fp-stress_SVE-VL-128-0 pass
8850 13:39:43.897839 arm64_fp-stress_SVE-VL-112-0 pass
8851 13:39:43.897958 arm64_fp-stress_SVE-VL-96-0 pass
8852 13:39:43.898071 arm64_fp-stress_SVE-VL-80-0 pass
8853 13:39:43.898184 arm64_fp-stress_SVE-VL-64-0 pass
8854 13:39:43.898296 arm64_fp-stress_SVE-VL-48-0 pass
8855 13:39:43.898408 arm64_fp-stress_SVE-VL-32-0 pass
8856 13:39:43.898520 arm64_fp-stress_SVE-VL-16-0 pass
8857 13:39:43.898631 arm64_fp-stress_SSVE-VL-256-0 pass
8858 13:39:43.898745 arm64_fp-stress_ZA-VL-256-0 pass
8859 13:39:43.900297 arm64_fp-stress_SSVE-VL-128-0 pass
8860 13:39:43.900684 arm64_fp-stress_ZA-VL-128-0 pass
8861 13:39:43.900882 arm64_fp-stress_SSVE-VL-64-0 pass
8862 13:39:43.901059 arm64_fp-stress_ZA-VL-64-0 pass
8863 13:39:43.901274 arm64_fp-stress_SSVE-VL-32-0 pass
8864 13:39:43.901523 arm64_fp-stress_ZA-VL-32-0 pass
8865 13:39:43.901725 arm64_fp-stress_SSVE-VL-16-0 pass
8866 13:39:43.901880 arm64_fp-stress_ZA-VL-16-0 pass
8867 13:39:43.902014 arm64_fp-stress pass
8868 13:39:43.902164 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8869 13:39:43.902325 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8870 13:39:43.902475 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8871 13:39:43.902633 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8872 13:39:43.902794 arm64_sve-ptrace_Set_SVE_VL_16 pass
8873 13:39:43.902985 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8874 13:39:43.903123 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8875 13:39:43.903276 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8876 13:39:43.903428 arm64_sve-ptrace_Set_SVE_VL_32 pass
8877 13:39:43.903572 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8878 13:39:43.903716 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8879 13:39:43.903855 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8880 13:39:43.904013 arm64_sve-ptrace_Set_SVE_VL_48 pass
8881 13:39:43.904149 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8882 13:39:43.904263 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8883 13:39:43.904377 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8884 13:39:43.904489 arm64_sve-ptrace_Set_SVE_VL_64 pass
8885 13:39:43.904600 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8886 13:39:43.904711 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8887 13:39:43.904852 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8888 13:39:43.904970 arm64_sve-ptrace_Set_SVE_VL_80 pass
8889 13:39:43.905083 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8890 13:39:43.905195 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8891 13:39:43.905306 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8892 13:39:43.905419 arm64_sve-ptrace_Set_SVE_VL_96 pass
8893 13:39:43.905530 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8894 13:39:43.905640 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8895 13:39:43.905885 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8896 13:39:43.908284 arm64_sve-ptrace_Set_SVE_VL_112 pass
8897 13:39:43.908737 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8898 13:39:43.908912 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8899 13:39:43.909110 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8900 13:39:43.909328 arm64_sve-ptrace_Set_SVE_VL_128 pass
8901 13:39:43.909519 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8902 13:39:43.909755 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8903 13:39:43.909934 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8904 13:39:43.910092 arm64_sve-ptrace_Set_SVE_VL_144 pass
8905 13:39:43.910251 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8906 13:39:43.910447 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8907 13:39:43.910587 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8908 13:39:43.910725 arm64_sve-ptrace_Set_SVE_VL_160 pass
8909 13:39:43.910884 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8910 13:39:43.911073 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8911 13:39:43.911248 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8912 13:39:43.911410 arm64_sve-ptrace_Set_SVE_VL_176 pass
8913 13:39:43.911547 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8914 13:39:43.911688 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8915 13:39:43.911830 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8916 13:39:43.911993 arm64_sve-ptrace_Set_SVE_VL_192 pass
8917 13:39:43.912134 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8918 13:39:43.912255 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8919 13:39:43.912369 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8920 13:39:43.912481 arm64_sve-ptrace_Set_SVE_VL_208 pass
8921 13:39:43.912595 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8922 13:39:43.912738 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8923 13:39:43.912858 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8924 13:39:43.912972 arm64_sve-ptrace_Set_SVE_VL_224 pass
8925 13:39:43.913084 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8926 13:39:43.913198 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8927 13:39:43.913311 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8928 13:39:43.913425 arm64_sve-ptrace_Set_SVE_VL_240 pass
8929 13:39:43.913537 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8930 13:39:43.916346 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8931 13:39:43.916879 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8932 13:39:43.917086 arm64_sve-ptrace_Set_SVE_VL_256 pass
8933 13:39:43.917260 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8934 13:39:43.917423 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8935 13:39:43.917587 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8936 13:39:43.917797 arm64_sve-ptrace_Set_SVE_VL_272 pass
8937 13:39:43.917973 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8938 13:39:43.918137 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8939 13:39:43.918296 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
8940 13:39:43.918460 arm64_sve-ptrace_Set_SVE_VL_288 pass
8941 13:39:43.918614 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
8942 13:39:43.918775 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
8943 13:39:43.918990 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
8944 13:39:43.919169 arm64_sve-ptrace_Set_SVE_VL_304 pass
8945 13:39:43.919301 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
8946 13:39:43.919471 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
8947 13:39:43.919617 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
8948 13:39:43.919756 arm64_sve-ptrace_Set_SVE_VL_320 pass
8949 13:39:43.919907 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
8950 13:39:43.920050 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
8951 13:39:43.920186 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
8952 13:39:43.920303 arm64_sve-ptrace_Set_SVE_VL_336 pass
8953 13:39:43.920448 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
8954 13:39:43.920569 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
8955 13:39:43.920684 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
8956 13:39:43.920801 arm64_sve-ptrace_Set_SVE_VL_352 pass
8957 13:39:43.920912 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
8958 13:39:43.921025 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
8959 13:39:43.921138 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
8960 13:39:43.921250 arm64_sve-ptrace_Set_SVE_VL_368 pass
8961 13:39:43.921363 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
8962 13:39:43.921475 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
8963 13:39:43.924508 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
8964 13:39:43.924747 arm64_sve-ptrace_Set_SVE_VL_384 pass
8965 13:39:43.925004 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
8966 13:39:43.925196 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
8967 13:39:43.925368 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
8968 13:39:43.925580 arm64_sve-ptrace_Set_SVE_VL_400 pass
8969 13:39:43.925779 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
8970 13:39:43.926031 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
8971 13:39:43.926236 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
8972 13:39:43.926419 arm64_sve-ptrace_Set_SVE_VL_416 pass
8973 13:39:43.926587 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
8974 13:39:43.926743 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
8975 13:39:43.926869 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
8976 13:39:43.926985 arm64_sve-ptrace_Set_SVE_VL_432 pass
8977 13:39:43.927099 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
8978 13:39:43.927260 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
8979 13:39:43.927385 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
8980 13:39:43.927501 arm64_sve-ptrace_Set_SVE_VL_448 pass
8981 13:39:43.927615 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
8982 13:39:43.927729 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
8983 13:39:43.942984 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
8984 13:39:43.943178 arm64_sve-ptrace_Set_SVE_VL_464 pass
8985 13:39:43.943274 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
8986 13:39:43.943590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
8987 13:39:43.943697 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
8988 13:39:43.943787 arm64_sve-ptrace_Set_SVE_VL_480 pass
8989 13:39:43.943880 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
8990 13:39:43.944169 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
8991 13:39:43.944274 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
8992 13:39:43.944363 arm64_sve-ptrace_Set_SVE_VL_496 pass
8993 13:39:43.944453 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
8994 13:39:43.944557 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
8995 13:39:43.944646 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
8996 13:39:43.944748 arm64_sve-ptrace_Set_SVE_VL_512 pass
8997 13:39:43.944850 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
8998 13:39:43.944952 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
8999 13:39:43.945243 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
9000 13:39:43.945335 arm64_sve-ptrace_Set_SVE_VL_528 pass
9001 13:39:43.945435 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
9002 13:39:43.945535 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
9003 13:39:43.945823 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
9004 13:39:43.945918 arm64_sve-ptrace_Set_SVE_VL_544 pass
9005 13:39:43.946018 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
9006 13:39:43.946119 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
9007 13:39:43.946220 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
9008 13:39:43.946306 arm64_sve-ptrace_Set_SVE_VL_560 pass
9009 13:39:43.946406 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
9010 13:39:43.946689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
9011 13:39:43.946794 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
9012 13:39:43.946888 arm64_sve-ptrace_Set_SVE_VL_576 pass
9013 13:39:43.946989 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
9014 13:39:43.947276 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
9015 13:39:43.947368 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
9016 13:39:43.947467 arm64_sve-ptrace_Set_SVE_VL_592 pass
9017 13:39:43.947555 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
9018 13:39:43.947653 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
9019 13:39:43.947770 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
9020 13:39:43.947873 arm64_sve-ptrace_Set_SVE_VL_608 pass
9021 13:39:43.948171 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
9022 13:39:43.952435 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
9023 13:39:43.952538 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
9024 13:39:43.952818 arm64_sve-ptrace_Set_SVE_VL_624 pass
9025 13:39:43.952908 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
9026 13:39:43.952993 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
9027 13:39:43.953078 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
9028 13:39:43.953180 arm64_sve-ptrace_Set_SVE_VL_640 pass
9029 13:39:43.953267 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
9030 13:39:43.953368 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
9031 13:39:43.953471 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
9032 13:39:43.953572 arm64_sve-ptrace_Set_SVE_VL_656 pass
9033 13:39:43.953680 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
9034 13:39:43.953969 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
9035 13:39:43.954074 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
9036 13:39:43.954161 arm64_sve-ptrace_Set_SVE_VL_672 pass
9037 13:39:43.954261 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
9038 13:39:43.954363 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
9039 13:39:43.954650 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
9040 13:39:43.954741 arm64_sve-ptrace_Set_SVE_VL_688 pass
9041 13:39:43.954843 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
9042 13:39:43.954947 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
9043 13:39:43.955242 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
9044 13:39:43.955344 arm64_sve-ptrace_Set_SVE_VL_704 pass
9045 13:39:43.955445 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
9046 13:39:43.955533 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
9047 13:39:43.955632 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
9048 13:39:43.955731 arm64_sve-ptrace_Set_SVE_VL_720 pass
9049 13:39:43.955833 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
9050 13:39:43.956128 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
9051 13:39:43.960375 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
9052 13:39:43.960475 arm64_sve-ptrace_Set_SVE_VL_736 pass
9053 13:39:43.960760 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
9054 13:39:43.960858 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
9055 13:39:43.960944 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
9056 13:39:43.961043 arm64_sve-ptrace_Set_SVE_VL_752 pass
9057 13:39:43.961129 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
9058 13:39:43.961230 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
9059 13:39:43.961331 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
9060 13:39:43.961433 arm64_sve-ptrace_Set_SVE_VL_768 pass
9061 13:39:43.961537 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
9062 13:39:43.961731 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
9063 13:39:43.962073 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
9064 13:39:43.962276 arm64_sve-ptrace_Set_SVE_VL_784 pass
9065 13:39:43.962471 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
9066 13:39:43.962635 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
9067 13:39:43.962766 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
9068 13:39:43.962943 arm64_sve-ptrace_Set_SVE_VL_800 pass
9069 13:39:43.963119 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
9070 13:39:43.963268 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
9071 13:39:43.963456 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
9072 13:39:43.963613 arm64_sve-ptrace_Set_SVE_VL_816 pass
9073 13:39:43.963761 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
9074 13:39:43.963925 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
9075 13:39:43.964098 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
9076 13:39:43.964307 arm64_sve-ptrace_Set_SVE_VL_832 pass
9077 13:39:43.964436 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
9078 13:39:43.964554 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
9079 13:39:43.964671 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
9080 13:39:43.964786 arm64_sve-ptrace_Set_SVE_VL_848 pass
9081 13:39:43.968317 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
9082 13:39:43.968765 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
9083 13:39:43.968975 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
9084 13:39:43.969156 arm64_sve-ptrace_Set_SVE_VL_864 pass
9085 13:39:43.969336 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
9086 13:39:43.969539 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
9087 13:39:43.969783 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
9088 13:39:43.970026 arm64_sve-ptrace_Set_SVE_VL_880 pass
9089 13:39:43.970249 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
9090 13:39:43.970477 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
9091 13:39:43.970730 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
9092 13:39:43.970955 arm64_sve-ptrace_Set_SVE_VL_896 pass
9093 13:39:43.971146 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
9094 13:39:43.971321 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
9095 13:39:43.971478 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
9096 13:39:43.971674 arm64_sve-ptrace_Set_SVE_VL_912 pass
9097 13:39:43.971868 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
9098 13:39:43.972046 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
9099 13:39:43.972245 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
9100 13:39:43.972415 arm64_sve-ptrace_Set_SVE_VL_928 pass
9101 13:39:43.972540 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
9102 13:39:43.972657 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
9103 13:39:43.972773 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
9104 13:39:43.972891 arm64_sve-ptrace_Set_SVE_VL_944 pass
9105 13:39:43.973006 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
9106 13:39:43.973122 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
9107 13:39:43.973235 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
9108 13:39:43.973350 arm64_sve-ptrace_Set_SVE_VL_960 pass
9109 13:39:43.973465 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
9110 13:39:43.973580 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
9111 13:39:43.973775 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
9112 13:39:43.973979 arm64_sve-ptrace_Set_SVE_VL_976 pass
9113 13:39:43.974164 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
9114 13:39:43.976586 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
9115 13:39:43.976804 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
9116 13:39:43.977011 arm64_sve-ptrace_Set_SVE_VL_992 pass
9117 13:39:43.977261 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
9118 13:39:43.977447 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
9119 13:39:43.977666 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
9120 13:39:43.977877 arm64_sve-ptrace_Set_SVE_VL_1008 pass
9121 13:39:43.978055 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
9122 13:39:43.978265 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
9123 13:39:43.978428 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
9124 13:39:43.978592 arm64_sve-ptrace_Set_SVE_VL_1024 pass
9125 13:39:43.978749 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
9126 13:39:43.978916 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
9127 13:39:43.979054 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
9128 13:39:43.979180 arm64_sve-ptrace_Set_SVE_VL_1040 pass
9129 13:39:43.979303 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
9130 13:39:43.979481 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
9131 13:39:43.979644 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
9132 13:39:43.979811 arm64_sve-ptrace_Set_SVE_VL_1056 pass
9133 13:39:43.979968 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
9134 13:39:43.980135 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
9135 13:39:43.980276 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
9136 13:39:43.980393 arm64_sve-ptrace_Set_SVE_VL_1072 pass
9137 13:39:43.980508 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
9138 13:39:43.980625 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
9139 13:39:43.980739 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
9140 13:39:43.980883 arm64_sve-ptrace_Set_SVE_VL_1088 pass
9141 13:39:43.981005 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
9142 13:39:43.981121 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
9143 13:39:43.981236 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
9144 13:39:43.981349 arm64_sve-ptrace_Set_SVE_VL_1104 pass
9145 13:39:43.996439 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
9146 13:39:43.996660 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
9147 13:39:43.997115 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
9148 13:39:43.997314 arm64_sve-ptrace_Set_SVE_VL_1120 pass
9149 13:39:43.997479 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
9150 13:39:43.997629 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
9151 13:39:43.997816 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
9152 13:39:43.998066 arm64_sve-ptrace_Set_SVE_VL_1136 pass
9153 13:39:43.998224 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
9154 13:39:43.998422 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
9155 13:39:43.998620 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
9156 13:39:43.998792 arm64_sve-ptrace_Set_SVE_VL_1152 pass
9157 13:39:43.998967 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
9158 13:39:43.999137 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
9159 13:39:43.999335 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
9160 13:39:43.999488 arm64_sve-ptrace_Set_SVE_VL_1168 pass
9161 13:39:43.999655 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
9162 13:39:43.999798 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
9163 13:39:43.999954 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
9164 13:39:44.000124 arm64_sve-ptrace_Set_SVE_VL_1184 pass
9165 13:39:44.000250 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
9166 13:39:44.000364 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
9167 13:39:44.000476 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
9168 13:39:44.000588 arm64_sve-ptrace_Set_SVE_VL_1200 pass
9169 13:39:44.000699 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
9170 13:39:44.000839 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
9171 13:39:44.000956 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
9172 13:39:44.001073 arm64_sve-ptrace_Set_SVE_VL_1216 pass
9173 13:39:44.001186 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
9174 13:39:44.001298 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
9175 13:39:44.001411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
9176 13:39:44.001524 arm64_sve-ptrace_Set_SVE_VL_1232 pass
9177 13:39:44.004325 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
9178 13:39:44.004752 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
9179 13:39:44.004972 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
9180 13:39:44.005165 arm64_sve-ptrace_Set_SVE_VL_1248 pass
9181 13:39:44.005360 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
9182 13:39:44.005568 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
9183 13:39:44.005774 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
9184 13:39:44.005986 arm64_sve-ptrace_Set_SVE_VL_1264 pass
9185 13:39:44.006182 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
9186 13:39:44.006374 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
9187 13:39:44.006521 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
9188 13:39:44.006725 arm64_sve-ptrace_Set_SVE_VL_1280 pass
9189 13:39:44.006893 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
9190 13:39:44.007068 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
9191 13:39:44.007255 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
9192 13:39:44.007464 arm64_sve-ptrace_Set_SVE_VL_1296 pass
9193 13:39:44.007674 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
9194 13:39:44.007868 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
9195 13:39:44.008062 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
9196 13:39:44.008230 arm64_sve-ptrace_Set_SVE_VL_1312 pass
9197 13:39:44.008407 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
9198 13:39:44.008533 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
9199 13:39:44.008650 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
9200 13:39:44.008764 arm64_sve-ptrace_Set_SVE_VL_1328 pass
9201 13:39:44.008879 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
9202 13:39:44.008997 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
9203 13:39:44.009114 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
9204 13:39:44.009229 arm64_sve-ptrace_Set_SVE_VL_1344 pass
9205 13:39:44.009345 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
9206 13:39:44.009460 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
9207 13:39:44.009575 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
9208 13:39:44.012321 arm64_sve-ptrace_Set_SVE_VL_1360 pass
9209 13:39:44.012800 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
9210 13:39:44.013024 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
9211 13:39:44.013227 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
9212 13:39:44.013427 arm64_sve-ptrace_Set_SVE_VL_1376 pass
9213 13:39:44.013629 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
9214 13:39:44.013862 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
9215 13:39:44.014042 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
9216 13:39:44.014254 arm64_sve-ptrace_Set_SVE_VL_1392 pass
9217 13:39:44.014478 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
9218 13:39:44.014653 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
9219 13:39:44.014859 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
9220 13:39:44.015100 arm64_sve-ptrace_Set_SVE_VL_1408 pass
9221 13:39:44.015345 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
9222 13:39:44.015587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
9223 13:39:44.015786 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
9224 13:39:44.016022 arm64_sve-ptrace_Set_SVE_VL_1424 pass
9225 13:39:44.016194 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
9226 13:39:44.016328 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
9227 13:39:44.016446 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
9228 13:39:44.016563 arm64_sve-ptrace_Set_SVE_VL_1440 pass
9229 13:39:44.016688 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
9230 13:39:44.016805 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
9231 13:39:44.016920 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
9232 13:39:44.017036 arm64_sve-ptrace_Set_SVE_VL_1456 pass
9233 13:39:44.017151 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
9234 13:39:44.017266 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
9235 13:39:44.017381 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
9236 13:39:44.017522 arm64_sve-ptrace_Set_SVE_VL_1472 pass
9237 13:39:44.017644 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
9238 13:39:44.020507 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
9239 13:39:44.020687 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
9240 13:39:44.020915 arm64_sve-ptrace_Set_SVE_VL_1488 pass
9241 13:39:44.021112 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
9242 13:39:44.021305 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
9243 13:39:44.021536 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
9244 13:39:44.021745 arm64_sve-ptrace_Set_SVE_VL_1504 pass
9245 13:39:44.021940 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
9246 13:39:44.022124 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
9247 13:39:44.022287 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
9248 13:39:44.022531 arm64_sve-ptrace_Set_SVE_VL_1520 pass
9249 13:39:44.022721 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
9250 13:39:44.022900 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
9251 13:39:44.023098 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
9252 13:39:44.023314 arm64_sve-ptrace_Set_SVE_VL_1536 pass
9253 13:39:44.023486 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
9254 13:39:44.023628 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
9255 13:39:44.023832 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
9256 13:39:44.024030 arm64_sve-ptrace_Set_SVE_VL_1552 pass
9257 13:39:44.024184 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
9258 13:39:44.024304 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
9259 13:39:44.024419 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
9260 13:39:44.024533 arm64_sve-ptrace_Set_SVE_VL_1568 pass
9261 13:39:44.024646 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
9262 13:39:44.024759 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
9263 13:39:44.024873 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
9264 13:39:44.024989 arm64_sve-ptrace_Set_SVE_VL_1584 pass
9265 13:39:44.025130 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
9266 13:39:44.025251 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
9267 13:39:44.028340 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
9268 13:39:44.028510 arm64_sve-ptrace_Set_SVE_VL_1600 pass
9269 13:39:44.028912 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
9270 13:39:44.029187 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
9271 13:39:44.029364 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
9272 13:39:44.029527 arm64_sve-ptrace_Set_SVE_VL_1616 pass
9273 13:39:44.029697 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
9274 13:39:44.029948 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
9275 13:39:44.030170 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
9276 13:39:44.030395 arm64_sve-ptrace_Set_SVE_VL_1632 pass
9277 13:39:44.030618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
9278 13:39:44.030815 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
9279 13:39:44.031063 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
9280 13:39:44.031276 arm64_sve-ptrace_Set_SVE_VL_1648 pass
9281 13:39:44.031548 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
9282 13:39:44.031788 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
9283 13:39:44.031977 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
9284 13:39:44.032181 arm64_sve-ptrace_Set_SVE_VL_1664 pass
9285 13:39:44.032337 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
9286 13:39:44.032459 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
9287 13:39:44.032577 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
9288 13:39:44.032695 arm64_sve-ptrace_Set_SVE_VL_1680 pass
9289 13:39:44.032810 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
9290 13:39:44.032929 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
9291 13:39:44.033049 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
9292 13:39:44.033165 arm64_sve-ptrace_Set_SVE_VL_1696 pass
9293 13:39:44.033313 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
9294 13:39:44.033437 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
9295 13:39:44.033555 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
9296 13:39:44.033729 arm64_sve-ptrace_Set_SVE_VL_1712 pass
9297 13:39:44.033940 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
9298 13:39:44.036290 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
9299 13:39:44.036686 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
9300 13:39:44.036833 arm64_sve-ptrace_Set_SVE_VL_1728 pass
9301 13:39:44.036939 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9302 13:39:44.037050 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9303 13:39:44.037116 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9304 13:39:44.037178 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9305 13:39:44.049068 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9306 13:39:44.049382 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9307 13:39:44.049488 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9308 13:39:44.049577 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9309 13:39:44.049682 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9310 13:39:44.049768 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9311 13:39:44.049868 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9312 13:39:44.049967 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9313 13:39:44.050070 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9314 13:39:44.050332 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9315 13:39:44.050633 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9316 13:39:44.050734 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9317 13:39:44.050858 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9318 13:39:44.050960 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9319 13:39:44.051077 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9320 13:39:44.051191 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9321 13:39:44.051311 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9322 13:39:44.051580 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9323 13:39:44.051687 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9324 13:39:44.051802 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9325 13:39:44.051896 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9326 13:39:44.052022 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9327 13:39:44.056340 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9328 13:39:44.056476 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9329 13:39:44.056797 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9330 13:39:44.056926 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9331 13:39:44.057027 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9332 13:39:44.057127 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9333 13:39:44.057222 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9334 13:39:44.057322 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9335 13:39:44.057439 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9336 13:39:44.057538 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9337 13:39:44.057660 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9338 13:39:44.057762 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9339 13:39:44.057876 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9340 13:39:44.057996 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9341 13:39:44.058118 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9342 13:39:44.058239 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9343 13:39:44.058365 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9344 13:39:44.058481 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9345 13:39:44.058785 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9346 13:39:44.058882 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9347 13:39:44.058989 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9348 13:39:44.059083 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9349 13:39:44.059200 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9350 13:39:44.059310 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9351 13:39:44.059422 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9352 13:39:44.059500 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9353 13:39:44.059592 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9354 13:39:44.059705 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9355 13:39:44.059814 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9356 13:39:44.059909 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9357 13:39:44.060002 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9358 13:39:44.064294 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9359 13:39:44.064610 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9360 13:39:44.064729 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9361 13:39:44.064860 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9362 13:39:44.065011 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9363 13:39:44.065109 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9364 13:39:44.065182 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9365 13:39:44.065276 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9366 13:39:44.065356 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9367 13:39:44.065446 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9368 13:39:44.065526 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9369 13:39:44.065643 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9370 13:39:44.065765 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9371 13:39:44.065864 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9372 13:39:44.065976 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9373 13:39:44.066088 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9374 13:39:44.066206 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9375 13:39:44.066547 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9376 13:39:44.066747 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9377 13:39:44.066977 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9378 13:39:44.067173 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9379 13:39:44.067392 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9380 13:39:44.067562 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9381 13:39:44.067763 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9382 13:39:44.067934 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9383 13:39:44.068120 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9384 13:39:44.068254 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9385 13:39:44.068370 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9386 13:39:44.068484 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9387 13:39:44.068625 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9388 13:39:44.068746 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9389 13:39:44.068861 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9390 13:39:44.072583 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9391 13:39:44.073033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9392 13:39:44.073271 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9393 13:39:44.073506 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9394 13:39:44.073711 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9395 13:39:44.073914 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9396 13:39:44.074089 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9397 13:39:44.074285 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9398 13:39:44.074502 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9399 13:39:44.074708 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9400 13:39:44.074906 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9401 13:39:44.075104 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9402 13:39:44.075283 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9403 13:39:44.075489 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9404 13:39:44.075660 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9405 13:39:44.075801 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9406 13:39:44.075962 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9407 13:39:44.076094 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9408 13:39:44.076221 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9409 13:39:44.076339 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9410 13:39:44.076456 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9411 13:39:44.076573 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9412 13:39:44.076688 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9413 13:39:44.076804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9414 13:39:44.076919 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9415 13:39:44.077034 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9416 13:39:44.077179 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9417 13:39:44.077300 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9418 13:39:44.077418 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9419 13:39:44.077534 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9420 13:39:44.077678 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9421 13:39:44.080356 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9422 13:39:44.080564 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9423 13:39:44.080980 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9424 13:39:44.081093 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9425 13:39:44.081168 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9426 13:39:44.081276 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9427 13:39:44.081394 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9428 13:39:44.081489 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9429 13:39:44.081576 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9430 13:39:44.081669 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9431 13:39:44.081776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9432 13:39:44.081873 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9433 13:39:44.081954 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9434 13:39:44.082046 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9435 13:39:44.082135 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9436 13:39:44.082255 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9437 13:39:44.082374 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9438 13:39:44.082473 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9439 13:39:44.082600 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9440 13:39:44.082698 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9441 13:39:44.082798 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9442 13:39:44.082902 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9443 13:39:44.083023 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9444 13:39:44.083141 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9445 13:39:44.083249 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9446 13:39:44.083525 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9447 13:39:44.083636 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9448 13:39:44.083738 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9449 13:39:44.083860 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9450 13:39:44.083968 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9451 13:39:44.084196 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9452 13:39:44.088305 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9453 13:39:44.088607 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9454 13:39:44.088702 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9455 13:39:44.088804 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9456 13:39:44.088890 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9457 13:39:44.088989 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9458 13:39:44.089322 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9459 13:39:44.089423 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9460 13:39:44.089524 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9461 13:39:44.089621 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9462 13:39:44.089725 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9463 13:39:44.090020 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9464 13:39:44.090123 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9465 13:39:44.102171 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9466 13:39:44.102534 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9467 13:39:44.102763 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9468 13:39:44.103034 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9469 13:39:44.103216 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9470 13:39:44.103402 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9471 13:39:44.103589 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9472 13:39:44.103841 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9473 13:39:44.104039 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9474 13:39:44.104204 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9475 13:39:44.104351 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9476 13:39:44.104537 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9477 13:39:44.104697 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9478 13:39:44.104876 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9479 13:39:44.105026 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9480 13:39:44.105192 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9481 13:39:44.105353 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9482 13:39:44.105505 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9483 13:39:44.106113 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9484 13:39:44.106281 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9485 13:39:44.106526 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9486 13:39:44.106712 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9487 13:39:44.106869 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9488 13:39:44.107009 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9489 13:39:44.107145 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9490 13:39:44.107299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9491 13:39:44.107463 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9492 13:39:44.107684 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9493 13:39:44.107896 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9494 13:39:44.108105 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9495 13:39:44.108257 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9496 13:39:44.108377 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9497 13:39:44.108523 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9498 13:39:44.108649 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9499 13:39:44.108768 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9500 13:39:44.108885 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9501 13:39:44.109001 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9502 13:39:44.109120 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9503 13:39:44.109238 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9504 13:39:44.109565 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9505 13:39:44.109704 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9506 13:39:44.109822 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9507 13:39:44.109937 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9508 13:39:44.110052 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9509 13:39:44.112531 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9510 13:39:44.112650 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9511 13:39:44.112739 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9512 13:39:44.112835 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9513 13:39:44.112941 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9514 13:39:44.113234 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9515 13:39:44.113354 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9516 13:39:44.113457 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9517 13:39:44.113554 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9518 13:39:44.113858 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9519 13:39:44.113974 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9520 13:39:44.114072 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9521 13:39:44.114236 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9522 13:39:44.114378 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9523 13:39:44.114709 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9524 13:39:44.114845 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9525 13:39:44.115165 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9526 13:39:44.115503 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9527 13:39:44.115701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9528 13:39:44.115911 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9529 13:39:44.116108 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9530 13:39:44.116321 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9531 13:39:44.116463 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9532 13:39:44.116608 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9533 13:39:44.116795 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9534 13:39:44.116950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9535 13:39:44.120352 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9536 13:39:44.120532 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9537 13:39:44.120959 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9538 13:39:44.121117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9539 13:39:44.121254 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9540 13:39:44.121469 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9541 13:39:44.121742 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9542 13:39:44.121958 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9543 13:39:44.122184 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9544 13:39:44.122387 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9545 13:39:44.122597 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9546 13:39:44.122792 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9547 13:39:44.122966 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9548 13:39:44.123141 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9549 13:39:44.123305 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9550 13:39:44.123489 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9551 13:39:44.123671 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9552 13:39:44.123834 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9553 13:39:44.124028 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9554 13:39:44.124241 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9555 13:39:44.124442 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9556 13:39:44.124577 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9557 13:39:44.124695 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9558 13:39:44.124810 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9559 13:39:44.124924 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9560 13:39:44.125039 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9561 13:39:44.125154 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9562 13:39:44.125269 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9563 13:39:44.125383 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9564 13:39:44.125499 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9565 13:39:44.128326 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9566 13:39:44.128795 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9567 13:39:44.129003 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9568 13:39:44.129221 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9569 13:39:44.129443 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9570 13:39:44.129681 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9571 13:39:44.129855 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9572 13:39:44.130022 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9573 13:39:44.130170 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9574 13:39:44.130327 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9575 13:39:44.130492 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9576 13:39:44.130705 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9577 13:39:44.130885 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9578 13:39:44.131026 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9579 13:39:44.131185 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9580 13:39:44.131344 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9581 13:39:44.131515 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9582 13:39:44.131715 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9583 13:39:44.131925 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9584 13:39:44.132111 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9585 13:39:44.132285 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9586 13:39:44.132419 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9587 13:39:44.132535 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9588 13:39:44.132651 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9589 13:39:44.132770 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9590 13:39:44.132897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9591 13:39:44.133013 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9592 13:39:44.133128 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9593 13:39:44.133270 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9594 13:39:44.136436 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9595 13:39:44.136835 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9596 13:39:44.136943 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9597 13:39:44.137031 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9598 13:39:44.137115 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9599 13:39:44.137214 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9600 13:39:44.137313 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9601 13:39:44.137400 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9602 13:39:44.137499 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9603 13:39:44.137600 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9604 13:39:44.137705 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9605 13:39:44.137815 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9606 13:39:44.138133 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9607 13:39:44.138302 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9608 13:39:44.138429 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9609 13:39:44.138588 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9610 13:39:44.138787 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9611 13:39:44.138935 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9612 13:39:44.139063 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9613 13:39:44.139183 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9614 13:39:44.139307 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9615 13:39:44.139456 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9616 13:39:44.139598 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9617 13:39:44.139757 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9618 13:39:44.139915 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9619 13:39:44.140077 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9620 13:39:44.140180 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9621 13:39:44.140272 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9622 13:39:44.144299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9623 13:39:44.144627 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9624 13:39:44.144735 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9625 13:39:44.157292 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9626 13:39:44.157722 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9627 13:39:44.157868 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9628 13:39:44.158023 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9629 13:39:44.158179 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9630 13:39:44.158312 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9631 13:39:44.158487 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9632 13:39:44.158609 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9633 13:39:44.158774 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9634 13:39:44.158928 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9635 13:39:44.159095 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9636 13:39:44.159303 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9637 13:39:44.159448 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9638 13:39:44.159584 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9639 13:39:44.159728 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9640 13:39:44.159851 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9641 13:39:44.159988 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9642 13:39:44.160113 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9643 13:39:44.160235 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9644 13:39:44.160336 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9645 13:39:44.160427 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9646 13:39:44.160517 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9647 13:39:44.160607 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9648 13:39:44.160696 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9649 13:39:44.164292 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9650 13:39:44.164646 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9651 13:39:44.164755 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9652 13:39:44.164856 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9653 13:39:44.164946 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9654 13:39:44.165075 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9655 13:39:44.165193 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9656 13:39:44.165294 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9657 13:39:44.165620 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9658 13:39:44.165765 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9659 13:39:44.165922 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9660 13:39:44.166057 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9661 13:39:44.166216 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9662 13:39:44.166339 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9663 13:39:44.166442 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9664 13:39:44.166541 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9665 13:39:44.166876 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9666 13:39:44.167006 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9667 13:39:44.167112 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9668 13:39:44.167211 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9669 13:39:44.167310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9670 13:39:44.167607 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9671 13:39:44.167719 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9672 13:39:44.167804 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9673 13:39:44.168092 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9674 13:39:44.168194 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9675 13:39:44.172336 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9676 13:39:44.172439 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9677 13:39:44.172794 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9678 13:39:44.172993 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9679 13:39:44.173155 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9680 13:39:44.173339 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9681 13:39:44.173497 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9682 13:39:44.173668 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9683 13:39:44.173826 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9684 13:39:44.174010 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9685 13:39:44.174169 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9686 13:39:44.174327 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9687 13:39:44.174483 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9688 13:39:44.174637 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9689 13:39:44.174820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9690 13:39:44.174981 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9691 13:39:44.175136 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9692 13:39:44.175289 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9693 13:39:44.175444 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9694 13:39:44.175598 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9695 13:39:44.175783 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9696 13:39:44.175942 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9697 13:39:44.176096 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9698 13:39:44.176253 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9699 13:39:44.176406 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9700 13:39:44.176559 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9701 13:39:44.176711 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9702 13:39:44.176892 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9703 13:39:44.177050 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9704 13:39:44.177204 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9705 13:39:44.180299 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9706 13:39:44.180573 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9707 13:39:44.180675 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9708 13:39:44.180774 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9709 13:39:44.180859 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9710 13:39:44.180989 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9711 13:39:44.181392 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9712 13:39:44.181499 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9713 13:39:44.181585 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9714 13:39:44.181897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9715 13:39:44.182002 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9716 13:39:44.182088 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9717 13:39:44.182172 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9718 13:39:44.182273 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9719 13:39:44.182357 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9720 13:39:44.182457 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9721 13:39:44.182544 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9722 13:39:44.182641 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9723 13:39:44.182741 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9724 13:39:44.182843 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9725 13:39:44.183147 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9726 13:39:44.183276 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9727 13:39:44.183383 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9728 13:39:44.183481 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9729 13:39:44.183601 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9730 13:39:44.183710 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9731 13:39:44.184011 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9732 13:39:44.184126 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9733 13:39:44.188296 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9734 13:39:44.188595 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9735 13:39:44.188694 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9736 13:39:44.188778 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9737 13:39:44.188877 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9738 13:39:44.188978 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9739 13:39:44.189086 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9740 13:39:44.189187 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9741 13:39:44.189493 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9742 13:39:44.189713 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9743 13:39:44.189877 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9744 13:39:44.190032 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9745 13:39:44.190260 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9746 13:39:44.190444 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9747 13:39:44.190575 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9748 13:39:44.190692 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9749 13:39:44.190832 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9750 13:39:44.190951 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9751 13:39:44.191065 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9752 13:39:44.191179 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9753 13:39:44.191296 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9754 13:39:44.191410 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9755 13:39:44.191594 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9756 13:39:44.191740 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9757 13:39:44.191893 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9758 13:39:44.192066 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9759 13:39:44.192213 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9760 13:39:44.192333 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9761 13:39:44.192447 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9762 13:39:44.192590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9763 13:39:44.192712 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9764 13:39:44.192827 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9765 13:39:44.192941 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9766 13:39:44.196294 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9767 13:39:44.196628 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9768 13:39:44.196727 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9769 13:39:44.196824 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9770 13:39:44.196907 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9771 13:39:44.197197 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9772 13:39:44.197302 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9773 13:39:44.197403 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9774 13:39:44.197742 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9775 13:39:44.197849 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9776 13:39:44.197934 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9777 13:39:44.198016 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9778 13:39:44.198294 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9779 13:39:44.198396 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9780 13:39:44.198481 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9781 13:39:44.198762 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9782 13:39:44.198860 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9783 13:39:44.198943 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9784 13:39:44.199025 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9785 13:39:44.211727 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9786 13:39:44.212066 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9787 13:39:44.212148 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9788 13:39:44.212210 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9789 13:39:44.212494 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9790 13:39:44.212664 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9791 13:39:44.212852 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9792 13:39:44.212961 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9793 13:39:44.213347 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9794 13:39:44.213534 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9795 13:39:44.213674 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9796 13:39:44.213822 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9797 13:39:44.213948 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9798 13:39:44.214077 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9799 13:39:44.214222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9800 13:39:44.214361 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9801 13:39:44.214543 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9802 13:39:44.214675 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9803 13:39:44.214822 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9804 13:39:44.214952 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9805 13:39:44.215079 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9806 13:39:44.215203 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9807 13:39:44.215329 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9808 13:39:44.215471 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9809 13:39:44.215591 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9810 13:39:44.215709 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9811 13:39:44.215829 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9812 13:39:44.215947 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9813 13:39:44.216069 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9814 13:39:44.216203 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9815 13:39:44.216297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9816 13:39:44.216389 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9817 13:39:44.216475 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9818 13:39:44.216562 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9819 13:39:44.220297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9820 13:39:44.220612 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9821 13:39:44.220706 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9822 13:39:44.220807 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9823 13:39:44.220906 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9824 13:39:44.221005 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9825 13:39:44.221362 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9826 13:39:44.221591 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9827 13:39:44.221832 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9828 13:39:44.222015 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9829 13:39:44.222142 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9830 13:39:44.222262 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9831 13:39:44.222435 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9832 13:39:44.222594 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9833 13:39:44.222760 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9834 13:39:44.222926 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9835 13:39:44.223086 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9836 13:39:44.223273 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9837 13:39:44.223440 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9838 13:39:44.223611 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9839 13:39:44.223777 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9840 13:39:44.223934 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9841 13:39:44.224097 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9842 13:39:44.224226 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9843 13:39:44.224377 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9844 13:39:44.224498 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9845 13:39:44.224619 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9846 13:39:44.224735 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9847 13:39:44.224849 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9848 13:39:44.224968 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9849 13:39:44.228396 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9850 13:39:44.228605 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9851 13:39:44.229053 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9852 13:39:44.229263 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9853 13:39:44.229482 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9854 13:39:44.229664 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9855 13:39:44.229827 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9856 13:39:44.229960 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9857 13:39:44.230102 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9858 13:39:44.230258 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9859 13:39:44.230409 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9860 13:39:44.230553 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9861 13:39:44.230740 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9862 13:39:44.230905 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9863 13:39:44.231065 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9864 13:39:44.231227 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9865 13:39:44.231384 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9866 13:39:44.231548 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9867 13:39:44.231751 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9868 13:39:44.231944 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9869 13:39:44.232153 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9870 13:39:44.232287 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9871 13:39:44.232433 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9872 13:39:44.232556 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9873 13:39:44.232669 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9874 13:39:44.232781 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9875 13:39:44.232893 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9876 13:39:44.233004 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9877 13:39:44.233115 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9878 13:39:44.233227 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9879 13:39:44.233371 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9880 13:39:44.233562 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9881 13:39:44.236357 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9882 13:39:44.236915 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9883 13:39:44.237131 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9884 13:39:44.237320 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9885 13:39:44.237504 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9886 13:39:44.237738 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9887 13:39:44.237934 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9888 13:39:44.238124 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9889 13:39:44.238309 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9890 13:39:44.238495 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9891 13:39:44.238679 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9892 13:39:44.238863 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9893 13:39:44.239087 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9894 13:39:44.239275 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9895 13:39:44.239463 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9896 13:39:44.239646 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9897 13:39:44.239828 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9898 13:39:44.240012 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9899 13:39:44.240196 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9900 13:39:44.240372 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9901 13:39:44.240517 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9902 13:39:44.240696 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9903 13:39:44.240833 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9904 13:39:44.240978 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9905 13:39:44.241120 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9906 13:39:44.241263 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9907 13:39:44.241409 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9908 13:39:44.241551 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9909 13:39:44.241703 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9910 13:39:44.244353 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9911 13:39:44.244798 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9912 13:39:44.244899 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9913 13:39:44.244990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9914 13:39:44.245072 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9915 13:39:44.245173 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9916 13:39:44.245260 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9917 13:39:44.245349 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9918 13:39:44.245448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9919 13:39:44.245535 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9920 13:39:44.245635 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9921 13:39:44.245751 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9922 13:39:44.245854 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9923 13:39:44.246183 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9924 13:39:44.246273 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9925 13:39:44.246533 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9926 13:39:44.246614 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9927 13:39:44.246678 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9928 13:39:44.246752 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9929 13:39:44.246818 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9930 13:39:44.246893 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9931 13:39:44.246970 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9932 13:39:44.247046 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9933 13:39:44.247313 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9934 13:39:44.247598 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9935 13:39:44.247690 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9936 13:39:44.247780 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9937 13:39:44.247877 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9938 13:39:44.248151 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9939 13:39:44.252262 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
9940 13:39:44.252628 arm64_sve-ptrace_Set_SVE_VL_4288 pass
9941 13:39:44.252732 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
9942 13:39:44.252821 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
9943 13:39:44.252922 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
9944 13:39:44.253011 arm64_sve-ptrace_Set_SVE_VL_4304 pass
9945 13:39:44.265988 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
9946 13:39:44.266340 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
9947 13:39:44.266436 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
9948 13:39:44.266524 arm64_sve-ptrace_Set_SVE_VL_4320 pass
9949 13:39:44.266626 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
9950 13:39:44.266717 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
9951 13:39:44.266819 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
9952 13:39:44.266905 arm64_sve-ptrace_Set_SVE_VL_4336 pass
9953 13:39:44.267006 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
9954 13:39:44.267094 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
9955 13:39:44.267194 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
9956 13:39:44.267296 arm64_sve-ptrace_Set_SVE_VL_4352 pass
9957 13:39:44.267397 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
9958 13:39:44.267500 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
9959 13:39:44.267623 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
9960 13:39:44.267929 arm64_sve-ptrace_Set_SVE_VL_4368 pass
9961 13:39:44.268034 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
9962 13:39:44.268137 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
9963 13:39:44.268255 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
9964 13:39:44.268360 arm64_sve-ptrace_Set_SVE_VL_4384 pass
9965 13:39:44.268465 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
9966 13:39:44.268569 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
9967 13:39:44.268699 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
9968 13:39:44.268795 arm64_sve-ptrace_Set_SVE_VL_4400 pass
9969 13:39:44.268885 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
9970 13:39:44.269172 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
9971 13:39:44.269271 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
9972 13:39:44.269370 arm64_sve-ptrace_Set_SVE_VL_4416 pass
9973 13:39:44.269457 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
9974 13:39:44.269544 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
9975 13:39:44.269824 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
9976 13:39:44.269921 arm64_sve-ptrace_Set_SVE_VL_4432 pass
9977 13:39:44.270043 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
9978 13:39:44.270148 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
9979 13:39:44.270261 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
9980 13:39:44.270359 arm64_sve-ptrace_Set_SVE_VL_4448 pass
9981 13:39:44.270455 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
9982 13:39:44.270544 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
9983 13:39:44.270637 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
9984 13:39:44.270821 arm64_sve-ptrace_Set_SVE_VL_4464 pass
9985 13:39:44.270927 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
9986 13:39:44.271020 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
9987 13:39:44.271116 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
9988 13:39:44.271216 arm64_sve-ptrace_Set_SVE_VL_4480 pass
9989 13:39:44.271488 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
9990 13:39:44.271584 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
9991 13:39:44.271683 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
9992 13:39:44.271766 arm64_sve-ptrace_Set_SVE_VL_4496 pass
9993 13:39:44.271863 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
9994 13:39:44.271950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
9995 13:39:44.272041 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
9996 13:39:44.272294 arm64_sve-ptrace_Set_SVE_VL_4512 pass
9997 13:39:44.276485 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
9998 13:39:44.276581 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
9999 13:39:44.276698 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
10000 13:39:44.276775 arm64_sve-ptrace_Set_SVE_VL_4528 pass
10001 13:39:44.276888 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
10002 13:39:44.277012 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
10003 13:39:44.277291 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
10004 13:39:44.277377 arm64_sve-ptrace_Set_SVE_VL_4544 pass
10005 13:39:44.277457 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
10006 13:39:44.277541 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
10007 13:39:44.277799 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
10008 13:39:44.277878 arm64_sve-ptrace_Set_SVE_VL_4560 pass
10009 13:39:44.278120 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
10010 13:39:44.278185 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
10011 13:39:44.278432 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
10012 13:39:44.278499 arm64_sve-ptrace_Set_SVE_VL_4576 pass
10013 13:39:44.278560 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
10014 13:39:44.278637 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
10015 13:39:44.278895 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
10016 13:39:44.278972 arm64_sve-ptrace_Set_SVE_VL_4592 pass
10017 13:39:44.279064 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
10018 13:39:44.279322 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
10019 13:39:44.279390 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
10020 13:39:44.279463 arm64_sve-ptrace_Set_SVE_VL_4608 pass
10021 13:39:44.279712 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
10022 13:39:44.279778 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
10023 13:39:44.280025 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
10024 13:39:44.280091 arm64_sve-ptrace_Set_SVE_VL_4624 pass
10025 13:39:44.280163 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
10026 13:39:44.284360 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
10027 13:39:44.284624 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
10028 13:39:44.284700 arm64_sve-ptrace_Set_SVE_VL_4640 pass
10029 13:39:44.284762 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
10030 13:39:44.284832 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
10031 13:39:44.285078 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
10032 13:39:44.285143 arm64_sve-ptrace_Set_SVE_VL_4656 pass
10033 13:39:44.285214 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
10034 13:39:44.285458 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
10035 13:39:44.285523 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
10036 13:39:44.285593 arm64_sve-ptrace_Set_SVE_VL_4672 pass
10037 13:39:44.285858 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
10038 13:39:44.285950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
10039 13:39:44.286026 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
10040 13:39:44.286275 arm64_sve-ptrace_Set_SVE_VL_4688 pass
10041 13:39:44.286348 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
10042 13:39:44.286429 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
10043 13:39:44.286679 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
10044 13:39:44.286759 arm64_sve-ptrace_Set_SVE_VL_4704 pass
10045 13:39:44.287012 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
10046 13:39:44.287288 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
10047 13:39:44.287378 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
10048 13:39:44.287478 arm64_sve-ptrace_Set_SVE_VL_4720 pass
10049 13:39:44.287562 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
10050 13:39:44.287659 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
10051 13:39:44.287954 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
10052 13:39:44.288043 arm64_sve-ptrace_Set_SVE_VL_4736 pass
10053 13:39:44.288133 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
10054 13:39:44.296280 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
10055 13:39:44.296664 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
10056 13:39:44.296852 arm64_sve-ptrace_Set_SVE_VL_4752 pass
10057 13:39:44.297037 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
10058 13:39:44.297284 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
10059 13:39:44.297441 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
10060 13:39:44.297608 arm64_sve-ptrace_Set_SVE_VL_4768 pass
10061 13:39:44.297762 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
10062 13:39:44.297897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
10063 13:39:44.298102 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
10064 13:39:44.298254 arm64_sve-ptrace_Set_SVE_VL_4784 pass
10065 13:39:44.298388 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
10066 13:39:44.298517 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
10067 13:39:44.298646 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
10068 13:39:44.298772 arm64_sve-ptrace_Set_SVE_VL_4800 pass
10069 13:39:44.298900 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
10070 13:39:44.299054 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
10071 13:39:44.299188 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
10072 13:39:44.299315 arm64_sve-ptrace_Set_SVE_VL_4816 pass
10073 13:39:44.299445 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
10074 13:39:44.299573 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
10075 13:39:44.299703 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
10076 13:39:44.299829 arm64_sve-ptrace_Set_SVE_VL_4832 pass
10077 13:39:44.299984 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
10078 13:39:44.300118 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
10079 13:39:44.300246 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
10080 13:39:44.300417 arm64_sve-ptrace_Set_SVE_VL_4848 pass
10081 13:39:44.300554 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
10082 13:39:44.300673 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
10083 13:39:44.300791 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
10084 13:39:44.300908 arm64_sve-ptrace_Set_SVE_VL_4864 pass
10085 13:39:44.301052 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
10086 13:39:44.304276 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
10087 13:39:44.304598 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
10088 13:39:44.304704 arm64_sve-ptrace_Set_SVE_VL_4880 pass
10089 13:39:44.304792 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
10090 13:39:44.304894 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
10091 13:39:44.304980 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
10092 13:39:44.305062 arm64_sve-ptrace_Set_SVE_VL_4896 pass
10093 13:39:44.305161 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
10094 13:39:44.305248 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
10095 13:39:44.305349 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
10096 13:39:44.305438 arm64_sve-ptrace_Set_SVE_VL_4912 pass
10097 13:39:44.305538 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
10098 13:39:44.305636 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
10099 13:39:44.305746 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
10100 13:39:44.305846 arm64_sve-ptrace_Set_SVE_VL_4928 pass
10101 13:39:44.305946 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
10102 13:39:44.306056 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
10103 13:39:44.306158 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
10104 13:39:44.306259 arm64_sve-ptrace_Set_SVE_VL_4944 pass
10105 13:39:44.318994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
10106 13:39:44.319359 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
10107 13:39:44.319451 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
10108 13:39:44.319532 arm64_sve-ptrace_Set_SVE_VL_4960 pass
10109 13:39:44.319647 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
10110 13:39:44.319733 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
10111 13:39:44.319836 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
10112 13:39:44.319922 arm64_sve-ptrace_Set_SVE_VL_4976 pass
10113 13:39:44.320006 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
10114 13:39:44.320092 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
10115 13:39:44.320367 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
10116 13:39:44.320475 arm64_sve-ptrace_Set_SVE_VL_4992 pass
10117 13:39:44.320764 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
10118 13:39:44.320852 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
10119 13:39:44.320945 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
10120 13:39:44.321035 arm64_sve-ptrace_Set_SVE_VL_5008 pass
10121 13:39:44.321125 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
10122 13:39:44.321233 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
10123 13:39:44.321357 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
10124 13:39:44.321486 arm64_sve-ptrace_Set_SVE_VL_5024 pass
10125 13:39:44.321603 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
10126 13:39:44.321763 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
10127 13:39:44.321884 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
10128 13:39:44.321993 arm64_sve-ptrace_Set_SVE_VL_5040 pass
10129 13:39:44.322089 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
10130 13:39:44.322208 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
10131 13:39:44.322320 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
10132 13:39:44.322405 arm64_sve-ptrace_Set_SVE_VL_5056 pass
10133 13:39:44.322507 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
10134 13:39:44.322803 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
10135 13:39:44.322911 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
10136 13:39:44.323006 arm64_sve-ptrace_Set_SVE_VL_5072 pass
10137 13:39:44.323112 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
10138 13:39:44.323217 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
10139 13:39:44.323304 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
10140 13:39:44.323405 arm64_sve-ptrace_Set_SVE_VL_5088 pass
10141 13:39:44.323509 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
10142 13:39:44.323602 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
10143 13:39:44.323702 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
10144 13:39:44.323803 arm64_sve-ptrace_Set_SVE_VL_5104 pass
10145 13:39:44.323904 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
10146 13:39:44.324003 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
10147 13:39:44.328273 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
10148 13:39:44.328605 arm64_sve-ptrace_Set_SVE_VL_5120 pass
10149 13:39:44.328707 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
10150 13:39:44.328795 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
10151 13:39:44.328899 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
10152 13:39:44.328986 arm64_sve-ptrace_Set_SVE_VL_5136 pass
10153 13:39:44.329085 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
10154 13:39:44.329186 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
10155 13:39:44.329286 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
10156 13:39:44.329388 arm64_sve-ptrace_Set_SVE_VL_5152 pass
10157 13:39:44.329488 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
10158 13:39:44.329588 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
10159 13:39:44.329695 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
10160 13:39:44.329794 arm64_sve-ptrace_Set_SVE_VL_5168 pass
10161 13:39:44.329892 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
10162 13:39:44.329976 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
10163 13:39:44.330073 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
10164 13:39:44.330157 arm64_sve-ptrace_Set_SVE_VL_5184 pass
10165 13:39:44.330257 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
10166 13:39:44.330358 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
10167 13:39:44.330692 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
10168 13:39:44.330878 arm64_sve-ptrace_Set_SVE_VL_5200 pass
10169 13:39:44.331061 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
10170 13:39:44.331217 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
10171 13:39:44.331350 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
10172 13:39:44.331521 arm64_sve-ptrace_Set_SVE_VL_5216 pass
10173 13:39:44.331670 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
10174 13:39:44.331820 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
10175 13:39:44.332007 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
10176 13:39:44.332172 arm64_sve-ptrace_Set_SVE_VL_5232 pass
10177 13:39:44.332318 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
10178 13:39:44.332437 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
10179 13:39:44.332578 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
10180 13:39:44.336305 arm64_sve-ptrace_Set_SVE_VL_5248 pass
10181 13:39:44.336772 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
10182 13:39:44.336970 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
10183 13:39:44.337139 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
10184 13:39:44.337300 arm64_sve-ptrace_Set_SVE_VL_5264 pass
10185 13:39:44.337495 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
10186 13:39:44.337672 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
10187 13:39:44.337835 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
10188 13:39:44.337996 arm64_sve-ptrace_Set_SVE_VL_5280 pass
10189 13:39:44.338153 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
10190 13:39:44.338306 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
10191 13:39:44.338428 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
10192 13:39:44.338560 arm64_sve-ptrace_Set_SVE_VL_5296 pass
10193 13:39:44.338704 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
10194 13:39:44.338828 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
10195 13:39:44.338950 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
10196 13:39:44.339074 arm64_sve-ptrace_Set_SVE_VL_5312 pass
10197 13:39:44.339235 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
10198 13:39:44.339375 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
10199 13:39:44.339502 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
10200 13:39:44.339649 arm64_sve-ptrace_Set_SVE_VL_5328 pass
10201 13:39:44.339792 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
10202 13:39:44.339940 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
10203 13:39:44.340092 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
10204 13:39:44.340241 arm64_sve-ptrace_Set_SVE_VL_5344 pass
10205 13:39:44.340363 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
10206 13:39:44.340482 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
10207 13:39:44.340602 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
10208 13:39:44.340728 arm64_sve-ptrace_Set_SVE_VL_5360 pass
10209 13:39:44.340889 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
10210 13:39:44.344342 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
10211 13:39:44.344787 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
10212 13:39:44.344967 arm64_sve-ptrace_Set_SVE_VL_5376 pass
10213 13:39:44.345122 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
10214 13:39:44.345251 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
10215 13:39:44.345430 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
10216 13:39:44.345589 arm64_sve-ptrace_Set_SVE_VL_5392 pass
10217 13:39:44.345761 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
10218 13:39:44.345942 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
10219 13:39:44.346087 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
10220 13:39:44.346231 arm64_sve-ptrace_Set_SVE_VL_5408 pass
10221 13:39:44.346412 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
10222 13:39:44.346605 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
10223 13:39:44.346819 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
10224 13:39:44.346979 arm64_sve-ptrace_Set_SVE_VL_5424 pass
10225 13:39:44.347173 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
10226 13:39:44.347346 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
10227 13:39:44.347530 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
10228 13:39:44.347786 arm64_sve-ptrace_Set_SVE_VL_5440 pass
10229 13:39:44.347996 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
10230 13:39:44.348157 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
10231 13:39:44.348289 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
10232 13:39:44.348462 arm64_sve-ptrace_Set_SVE_VL_5456 pass
10233 13:39:44.348610 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
10234 13:39:44.348754 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
10235 13:39:44.348895 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
10236 13:39:44.349037 arm64_sve-ptrace_Set_SVE_VL_5472 pass
10237 13:39:44.349177 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
10238 13:39:44.349319 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
10239 13:39:44.349461 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
10240 13:39:44.349605 arm64_sve-ptrace_Set_SVE_VL_5488 pass
10241 13:39:44.349791 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
10242 13:39:44.349928 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
10243 13:39:44.352300 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
10244 13:39:44.352513 arm64_sve-ptrace_Set_SVE_VL_5504 pass
10245 13:39:44.352958 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
10246 13:39:44.353136 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
10247 13:39:44.353350 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
10248 13:39:44.353541 arm64_sve-ptrace_Set_SVE_VL_5520 pass
10249 13:39:44.353727 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
10250 13:39:44.353911 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
10251 13:39:44.354059 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
10252 13:39:44.354203 arm64_sve-ptrace_Set_SVE_VL_5536 pass
10253 13:39:44.354329 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
10254 13:39:44.354484 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
10255 13:39:44.354633 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
10256 13:39:44.354778 arm64_sve-ptrace_Set_SVE_VL_5552 pass
10257 13:39:44.354909 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
10258 13:39:44.355046 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
10259 13:39:44.355163 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
10260 13:39:44.355276 arm64_sve-ptrace_Set_SVE_VL_5568 pass
10261 13:39:44.355386 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
10262 13:39:44.355498 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
10263 13:39:44.355609 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
10264 13:39:44.355720 arm64_sve-ptrace_Set_SVE_VL_5584 pass
10265 13:39:44.372458 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
10266 13:39:44.373060 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
10267 13:39:44.373251 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
10268 13:39:44.373443 arm64_sve-ptrace_Set_SVE_VL_5600 pass
10269 13:39:44.373619 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
10270 13:39:44.373791 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
10271 13:39:44.373949 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
10272 13:39:44.374110 arm64_sve-ptrace_Set_SVE_VL_5616 pass
10273 13:39:44.374299 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
10274 13:39:44.374465 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
10275 13:39:44.374609 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
10276 13:39:44.374744 arm64_sve-ptrace_Set_SVE_VL_5632 pass
10277 13:39:44.374886 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
10278 13:39:44.375008 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
10279 13:39:44.375155 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
10280 13:39:44.375301 arm64_sve-ptrace_Set_SVE_VL_5648 pass
10281 13:39:44.375485 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
10282 13:39:44.375669 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
10283 13:39:44.375852 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
10284 13:39:44.376074 arm64_sve-ptrace_Set_SVE_VL_5664 pass
10285 13:39:44.376215 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
10286 13:39:44.376342 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
10287 13:39:44.376459 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
10288 13:39:44.376575 arm64_sve-ptrace_Set_SVE_VL_5680 pass
10289 13:39:44.376689 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
10290 13:39:44.376804 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
10291 13:39:44.376918 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
10292 13:39:44.377033 arm64_sve-ptrace_Set_SVE_VL_5696 pass
10293 13:39:44.377149 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
10294 13:39:44.377263 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
10295 13:39:44.377378 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
10296 13:39:44.377492 arm64_sve-ptrace_Set_SVE_VL_5712 pass
10297 13:39:44.377607 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
10298 13:39:44.377863 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
10299 13:39:44.378062 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
10300 13:39:44.380313 arm64_sve-ptrace_Set_SVE_VL_5728 pass
10301 13:39:44.380718 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10302 13:39:44.380824 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10303 13:39:44.380908 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10304 13:39:44.380992 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10305 13:39:44.381090 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10306 13:39:44.381176 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10307 13:39:44.381257 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10308 13:39:44.381355 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10309 13:39:44.381443 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10310 13:39:44.381539 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10311 13:39:44.381631 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10312 13:39:44.381746 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10313 13:39:44.381849 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10314 13:39:44.381936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10315 13:39:44.382034 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10316 13:39:44.382135 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10317 13:39:44.382482 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10318 13:39:44.382670 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10319 13:39:44.382860 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10320 13:39:44.383025 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10321 13:39:44.383222 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10322 13:39:44.383418 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10323 13:39:44.383621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10324 13:39:44.383794 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10325 13:39:44.383954 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10326 13:39:44.384130 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10327 13:39:44.384256 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10328 13:39:44.384372 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10329 13:39:44.384487 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10330 13:39:44.384604 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10331 13:39:44.384721 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10332 13:39:44.384835 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10333 13:39:44.384950 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10334 13:39:44.388297 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10335 13:39:44.388749 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10336 13:39:44.388944 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10337 13:39:44.389124 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10338 13:39:44.389308 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10339 13:39:44.389476 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10340 13:39:44.389638 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10341 13:39:44.389808 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10342 13:39:44.390018 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10343 13:39:44.390179 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10344 13:39:44.390332 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10345 13:39:44.390495 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10346 13:39:44.390636 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10347 13:39:44.390790 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10348 13:39:44.390909 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10349 13:39:44.391060 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10350 13:39:44.391253 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10351 13:39:44.391409 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10352 13:39:44.391559 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10353 13:39:44.391689 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10354 13:39:44.391816 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10355 13:39:44.392001 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10356 13:39:44.392141 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10357 13:39:44.392259 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10358 13:39:44.392447 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10359 13:39:44.392619 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10360 13:39:44.392780 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10361 13:39:44.392926 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10362 13:39:44.393096 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10363 13:39:44.393250 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10364 13:39:44.393396 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10365 13:39:44.396324 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10366 13:39:44.396769 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10367 13:39:44.396956 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10368 13:39:44.397136 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10369 13:39:44.397314 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10370 13:39:44.397478 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10371 13:39:44.397631 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10372 13:39:44.397793 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10373 13:39:44.397986 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10374 13:39:44.398149 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10375 13:39:44.398301 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10376 13:39:44.398490 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10377 13:39:44.398701 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10378 13:39:44.398937 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10379 13:39:44.399105 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10380 13:39:44.399270 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10381 13:39:44.399412 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10382 13:39:44.399577 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10383 13:39:44.399728 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10384 13:39:44.399880 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10385 13:39:44.400077 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10386 13:39:44.400229 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10387 13:39:44.400397 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10388 13:39:44.400540 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10389 13:39:44.400701 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10390 13:39:44.400853 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10391 13:39:44.400998 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10392 13:39:44.401166 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10393 13:39:44.401307 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10394 13:39:44.401468 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10395 13:39:44.404407 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10396 13:39:44.404627 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10397 13:39:44.405074 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10398 13:39:44.405258 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10399 13:39:44.405473 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10400 13:39:44.405689 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10401 13:39:44.405874 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10402 13:39:44.406062 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10403 13:39:44.406292 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10404 13:39:44.406495 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10405 13:39:44.406706 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10406 13:39:44.406839 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10407 13:39:44.406990 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10408 13:39:44.407109 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10409 13:39:44.407219 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10410 13:39:44.407336 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10411 13:39:44.407446 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10412 13:39:44.407562 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10413 13:39:44.407675 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10414 13:39:44.407738 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10415 13:39:44.407798 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10416 13:39:44.407867 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10417 13:39:44.407952 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10418 13:39:44.408014 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10419 13:39:44.408073 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10420 13:39:44.408132 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10421 13:39:44.408191 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10422 13:39:44.408250 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10423 13:39:44.408309 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10424 13:39:44.408368 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10425 13:39:44.424012 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10426 13:39:44.424506 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10427 13:39:44.424698 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10428 13:39:44.424866 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10429 13:39:44.425035 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10430 13:39:44.425329 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10431 13:39:44.425522 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10432 13:39:44.425714 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10433 13:39:44.425893 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10434 13:39:44.426089 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10435 13:39:44.426269 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10436 13:39:44.426398 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10437 13:39:44.426629 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10438 13:39:44.426783 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10439 13:39:44.426942 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10440 13:39:44.427101 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10441 13:39:44.427261 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10442 13:39:44.427418 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10443 13:39:44.427575 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10444 13:39:44.427738 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10445 13:39:44.427897 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10446 13:39:44.428056 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10447 13:39:44.428203 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10448 13:39:44.428354 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10449 13:39:44.428530 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10450 13:39:44.428657 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10451 13:39:44.428776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10452 13:39:44.428891 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10453 13:39:44.429007 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10454 13:39:44.429121 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10455 13:39:44.429236 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10456 13:39:44.429352 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10457 13:39:44.429466 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10458 13:39:44.429580 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10459 13:39:44.429780 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10460 13:39:44.429980 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10461 13:39:44.432311 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10462 13:39:44.432730 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10463 13:39:44.432954 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10464 13:39:44.433159 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10465 13:39:44.433362 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10466 13:39:44.433582 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10467 13:39:44.433807 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10468 13:39:44.434005 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10469 13:39:44.434153 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10470 13:39:44.434338 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10471 13:39:44.434471 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10472 13:39:44.434632 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10473 13:39:44.434791 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10474 13:39:44.434937 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10475 13:39:44.435071 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10476 13:39:44.435207 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10477 13:39:44.435351 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10478 13:39:44.435543 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10479 13:39:44.435700 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10480 13:39:44.435885 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10481 13:39:44.436066 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10482 13:39:44.436208 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10483 13:39:44.436361 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10484 13:39:44.436502 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10485 13:39:44.436620 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10486 13:39:44.436737 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10487 13:39:44.436855 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10488 13:39:44.436971 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10489 13:39:44.437114 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10490 13:39:44.437237 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10491 13:39:44.437354 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10492 13:39:44.437471 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10493 13:39:44.440292 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10494 13:39:44.440718 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10495 13:39:44.440923 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10496 13:39:44.441101 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10497 13:39:44.441306 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10498 13:39:44.441540 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10499 13:39:44.441734 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10500 13:39:44.441888 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10501 13:39:44.442046 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10502 13:39:44.442201 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10503 13:39:44.442338 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10504 13:39:44.442494 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10505 13:39:44.442703 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10506 13:39:44.442897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10507 13:39:44.443065 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10508 13:39:44.443236 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10509 13:39:44.443416 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10510 13:39:44.443623 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10511 13:39:44.443793 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10512 13:39:44.443995 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10513 13:39:44.444176 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10514 13:39:44.444338 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10515 13:39:44.444463 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10516 13:39:44.444581 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10517 13:39:44.444697 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10518 13:39:44.444815 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10519 13:39:44.444929 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10520 13:39:44.445045 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10521 13:39:44.445160 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10522 13:39:44.445275 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10523 13:39:44.445389 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10524 13:39:44.445502 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10525 13:39:44.445616 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10526 13:39:44.448276 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10527 13:39:44.448673 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10528 13:39:44.448788 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10529 13:39:44.448880 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10530 13:39:44.448983 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10531 13:39:44.449087 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10532 13:39:44.449174 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10533 13:39:44.449258 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10534 13:39:44.449359 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10535 13:39:44.449444 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10536 13:39:44.449527 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10537 13:39:44.449627 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10538 13:39:44.449724 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10539 13:39:44.449824 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10540 13:39:44.449924 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10541 13:39:44.450234 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10542 13:39:44.450334 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10543 13:39:44.450419 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10544 13:39:44.450506 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10545 13:39:44.450605 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10546 13:39:44.450706 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10547 13:39:44.450801 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10548 13:39:44.450898 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10549 13:39:44.450983 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10550 13:39:44.451080 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10551 13:39:44.451169 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10552 13:39:44.451270 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10553 13:39:44.451358 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10554 13:39:44.451457 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10555 13:39:44.451560 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10556 13:39:44.451664 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10557 13:39:44.451770 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10558 13:39:44.451873 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10559 13:39:44.452179 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10560 13:39:44.452287 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10561 13:39:44.456384 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10562 13:39:44.456707 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10563 13:39:44.456851 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10564 13:39:44.456960 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10565 13:39:44.457064 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10566 13:39:44.457353 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10567 13:39:44.457460 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10568 13:39:44.457548 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10569 13:39:44.457655 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10570 13:39:44.457761 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10571 13:39:44.457870 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10572 13:39:44.458176 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10573 13:39:44.458284 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10574 13:39:44.458388 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10575 13:39:44.458495 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10576 13:39:44.458584 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10577 13:39:44.458684 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10578 13:39:44.458773 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10579 13:39:44.458872 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10580 13:39:44.458958 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10581 13:39:44.459058 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10582 13:39:44.459159 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10583 13:39:44.459259 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10584 13:39:44.459358 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10585 13:39:44.477896 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10586 13:39:44.478319 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10587 13:39:44.478436 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10588 13:39:44.478530 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10589 13:39:44.478610 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10590 13:39:44.478724 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10591 13:39:44.478812 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10592 13:39:44.478889 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10593 13:39:44.478962 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10594 13:39:44.479047 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10595 13:39:44.479126 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10596 13:39:44.479216 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10597 13:39:44.479317 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10598 13:39:44.479419 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10599 13:39:44.479537 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10600 13:39:44.479634 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10601 13:39:44.479712 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10602 13:39:44.479803 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10603 13:39:44.479899 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10604 13:39:44.479973 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10605 13:39:44.480273 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10606 13:39:44.480547 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10607 13:39:44.480626 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10608 13:39:44.480700 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10609 13:39:44.480799 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10610 13:39:44.481088 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10611 13:39:44.481189 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10612 13:39:44.481309 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10613 13:39:44.481420 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10614 13:39:44.481520 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10615 13:39:44.481820 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10616 13:39:44.481928 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10617 13:39:44.482023 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10618 13:39:44.482117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10619 13:39:44.482234 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10620 13:39:44.482309 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10621 13:39:44.482422 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10622 13:39:44.482508 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10623 13:39:44.482584 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10624 13:39:44.482667 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10625 13:39:44.482943 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10626 13:39:44.483052 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10627 13:39:44.483174 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10628 13:39:44.483279 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10629 13:39:44.483383 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10630 13:39:44.483466 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10631 13:39:44.483760 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10632 13:39:44.483873 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10633 13:39:44.483960 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10634 13:39:44.484062 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10635 13:39:44.484151 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10636 13:39:44.484254 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10637 13:39:44.488259 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10638 13:39:44.488580 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10639 13:39:44.488685 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10640 13:39:44.488777 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10641 13:39:44.488880 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10642 13:39:44.488966 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10643 13:39:44.489064 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10644 13:39:44.489162 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10645 13:39:44.489245 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10646 13:39:44.489343 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10647 13:39:44.489441 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10648 13:39:44.489540 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10649 13:39:44.489833 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10650 13:39:44.489935 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10651 13:39:44.490037 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10652 13:39:44.490125 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10653 13:39:44.490229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10654 13:39:44.490330 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10655 13:39:44.490432 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10656 13:39:44.490532 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10657 13:39:44.490818 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10658 13:39:44.490923 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10659 13:39:44.491024 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10660 13:39:44.491109 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10661 13:39:44.491429 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10662 13:39:44.491636 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10663 13:39:44.491814 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10664 13:39:44.491954 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10665 13:39:44.492112 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10666 13:39:44.492243 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10667 13:39:44.492360 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10668 13:39:44.492476 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10669 13:39:44.492591 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10670 13:39:44.492727 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10671 13:39:44.496322 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10672 13:39:44.496529 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10673 13:39:44.496956 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10674 13:39:44.497116 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10675 13:39:44.497248 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10676 13:39:44.497375 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10677 13:39:44.497499 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10678 13:39:44.497664 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10679 13:39:44.497798 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10680 13:39:44.497922 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10681 13:39:44.498046 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10682 13:39:44.498168 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10683 13:39:44.498321 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10684 13:39:44.498449 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10685 13:39:44.498574 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10686 13:39:44.498700 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10687 13:39:44.498827 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10688 13:39:44.498979 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10689 13:39:44.499111 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10690 13:39:44.499291 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10691 13:39:44.499495 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10692 13:39:44.499649 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10693 13:39:44.499779 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10694 13:39:44.499937 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10695 13:39:44.500072 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10696 13:39:44.500201 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10697 13:39:44.500346 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10698 13:39:44.500493 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10699 13:39:44.500610 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10700 13:39:44.500727 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10701 13:39:44.500841 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10702 13:39:44.500955 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10703 13:39:44.501129 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10704 13:39:44.504305 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10705 13:39:44.504741 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10706 13:39:44.504895 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10707 13:39:44.505054 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10708 13:39:44.505192 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10709 13:39:44.505343 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10710 13:39:44.505473 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10711 13:39:44.505641 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10712 13:39:44.505843 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10713 13:39:44.506082 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10714 13:39:44.506294 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10715 13:39:44.506475 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10716 13:39:44.506642 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10717 13:39:44.506795 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10718 13:39:44.506954 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10719 13:39:44.507140 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10720 13:39:44.507300 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10721 13:39:44.508498 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10722 13:39:44.508661 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10723 13:39:44.508782 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10724 13:39:44.508872 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10725 13:39:44.508960 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10726 13:39:44.509046 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10727 13:39:44.509132 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10728 13:39:44.509218 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10729 13:39:44.509304 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10730 13:39:44.509390 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10731 13:39:44.509476 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10732 13:39:44.509561 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10733 13:39:44.509659 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10734 13:39:44.509748 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10735 13:39:44.509835 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10736 13:39:44.509912 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10737 13:39:44.509971 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10738 13:39:44.510029 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10739 13:39:44.516382 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10740 13:39:44.516619 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10741 13:39:44.516909 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10742 13:39:44.516979 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10743 13:39:44.517042 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10744 13:39:44.517108 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10745 13:39:44.529611 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10746 13:39:44.530041 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10747 13:39:44.530151 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10748 13:39:44.530236 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10749 13:39:44.530339 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10750 13:39:44.530422 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10751 13:39:44.530518 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10752 13:39:44.530602 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10753 13:39:44.530690 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10754 13:39:44.530790 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10755 13:39:44.530898 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10756 13:39:44.531005 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10757 13:39:44.531111 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10758 13:39:44.531229 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10759 13:39:44.531338 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10760 13:39:44.531636 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10761 13:39:44.531733 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10762 13:39:44.531839 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10763 13:39:44.531949 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10764 13:39:44.532057 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10765 13:39:44.532349 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10766 13:39:44.532643 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10767 13:39:44.532737 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10768 13:39:44.532833 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10769 13:39:44.532946 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10770 13:39:44.533053 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10771 13:39:44.533166 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10772 13:39:44.533463 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10773 13:39:44.533560 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10774 13:39:44.533675 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10775 13:39:44.533781 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10776 13:39:44.533890 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10777 13:39:44.533996 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10778 13:39:44.534104 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10779 13:39:44.534208 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10780 13:39:44.534501 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10781 13:39:44.534598 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10782 13:39:44.534703 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10783 13:39:44.534809 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10784 13:39:44.534906 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10785 13:39:44.535193 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10786 13:39:44.535288 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10787 13:39:44.535393 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10788 13:39:44.535500 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10789 13:39:44.535604 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10790 13:39:44.535710 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10791 13:39:44.535816 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10792 13:39:44.535924 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10793 13:39:44.536027 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10794 13:39:44.540288 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10795 13:39:44.540634 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10796 13:39:44.540734 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10797 13:39:44.540812 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10798 13:39:44.540902 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10799 13:39:44.540974 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10800 13:39:44.541062 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10801 13:39:44.541138 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10802 13:39:44.541409 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10803 13:39:44.541680 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10804 13:39:44.541757 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10805 13:39:44.541853 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10806 13:39:44.541932 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10807 13:39:44.542026 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10808 13:39:44.542099 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10809 13:39:44.542189 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10810 13:39:44.542263 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10811 13:39:44.542540 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10812 13:39:44.542631 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10813 13:39:44.542720 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10814 13:39:44.542806 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10815 13:39:44.542883 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10816 13:39:44.542967 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10817 13:39:44.543050 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10818 13:39:44.543318 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10819 13:39:44.543413 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10820 13:39:44.543489 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10821 13:39:44.543576 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10822 13:39:44.543667 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10823 13:39:44.543759 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10824 13:39:44.543862 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10825 13:39:44.544149 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10826 13:39:44.552296 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10827 13:39:44.552718 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10828 13:39:44.552819 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10829 13:39:44.552911 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10830 13:39:44.553014 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10831 13:39:44.553115 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10832 13:39:44.553201 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10833 13:39:44.553301 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10834 13:39:44.553633 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10835 13:39:44.553866 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10836 13:39:44.554101 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10837 13:39:44.554305 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10838 13:39:44.554513 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10839 13:39:44.554742 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10840 13:39:44.555018 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10841 13:39:44.555225 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10842 13:39:44.555399 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10843 13:39:44.555577 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10844 13:39:44.555754 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10845 13:39:44.555923 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10846 13:39:44.556151 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10847 13:39:44.556319 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10848 13:39:44.556484 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10849 13:39:44.556617 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10850 13:39:44.556736 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10851 13:39:44.556852 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10852 13:39:44.556967 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10853 13:39:44.557083 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10854 13:39:44.560379 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10855 13:39:44.560831 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10856 13:39:44.561022 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10857 13:39:44.561160 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10858 13:39:44.561291 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10859 13:39:44.561478 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10860 13:39:44.561630 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10861 13:39:44.561921 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10862 13:39:44.562071 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10863 13:39:44.562276 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10864 13:39:44.562422 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10865 13:39:44.562573 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10866 13:39:44.562729 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10867 13:39:44.562885 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10868 13:39:44.563080 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10869 13:39:44.563221 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10870 13:39:44.563361 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10871 13:39:44.563495 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10872 13:39:44.563629 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10873 13:39:44.563764 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10874 13:39:44.563892 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10875 13:39:44.564060 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10876 13:39:44.564201 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10877 13:39:44.564320 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10878 13:39:44.564413 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10879 13:39:44.564502 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10880 13:39:44.564589 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10881 13:39:44.564676 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10882 13:39:44.564762 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10883 13:39:44.568301 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10884 13:39:44.568605 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10885 13:39:44.568708 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10886 13:39:44.568811 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10887 13:39:44.568897 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10888 13:39:44.568997 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10889 13:39:44.569097 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10890 13:39:44.569411 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10891 13:39:44.569570 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10892 13:39:44.569759 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10893 13:39:44.569892 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10894 13:39:44.570016 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10895 13:39:44.570161 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10896 13:39:44.570287 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10897 13:39:44.570416 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10898 13:39:44.570531 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10899 13:39:44.570668 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10900 13:39:44.570788 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10901 13:39:44.570936 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10902 13:39:44.571063 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10903 13:39:44.571204 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10904 13:39:44.571322 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10905 13:39:44.581571 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10906 13:39:44.581961 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10907 13:39:44.582164 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10908 13:39:44.582332 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10909 13:39:44.582530 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10910 13:39:44.582701 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10911 13:39:44.582867 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10912 13:39:44.583029 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10913 13:39:44.583190 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10914 13:39:44.583394 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10915 13:39:44.583568 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10916 13:39:44.583731 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10917 13:39:44.583892 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10918 13:39:44.584055 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10919 13:39:44.584185 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10920 13:39:44.584356 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10921 13:39:44.584532 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10922 13:39:44.584691 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10923 13:39:44.584845 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10924 13:39:44.585005 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10925 13:39:44.585248 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10926 13:39:44.585437 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10927 13:39:44.585617 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10928 13:39:44.586334 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10929 13:39:44.586519 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10930 13:39:44.586731 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10931 13:39:44.586914 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10932 13:39:44.587084 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10933 13:39:44.587259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10934 13:39:44.587474 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10935 13:39:44.587670 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10936 13:39:44.587835 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10937 13:39:44.588030 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10938 13:39:44.588237 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10939 13:39:44.588412 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
10940 13:39:44.588779 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
10941 13:39:44.588918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
10942 13:39:44.589063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
10943 13:39:44.589212 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
10944 13:39:44.589356 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
10945 13:39:44.589499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
10946 13:39:44.589642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
10947 13:39:44.589800 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
10948 13:39:44.589944 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
10949 13:39:44.590089 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
10950 13:39:44.590231 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
10951 13:39:44.592356 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
10952 13:39:44.592550 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
10953 13:39:44.592951 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
10954 13:39:44.593151 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
10955 13:39:44.593320 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
10956 13:39:44.593470 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
10957 13:39:44.593661 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
10958 13:39:44.593803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
10959 13:39:44.593953 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
10960 13:39:44.594117 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
10961 13:39:44.594279 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
10962 13:39:44.594448 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
10963 13:39:44.594593 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
10964 13:39:44.594751 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
10965 13:39:44.594892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
10966 13:39:44.595091 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
10967 13:39:44.595267 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
10968 13:39:44.595416 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
10969 13:39:44.595560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
10970 13:39:44.595703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
10971 13:39:44.595880 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
10972 13:39:44.596139 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
10973 13:39:44.596317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
10974 13:39:44.596490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
10975 13:39:44.596635 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
10976 13:39:44.596777 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
10977 13:39:44.596920 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
10978 13:39:44.597062 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
10979 13:39:44.597208 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
10980 13:39:44.597351 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
10981 13:39:44.597492 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
10982 13:39:44.604239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
10983 13:39:44.604561 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
10984 13:39:44.604693 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
10985 13:39:44.604839 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
10986 13:39:44.604997 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
10987 13:39:44.605203 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
10988 13:39:44.605374 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
10989 13:39:44.605585 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
10990 13:39:44.605784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
10991 13:39:44.605942 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
10992 13:39:44.606128 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
10993 13:39:44.606357 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
10994 13:39:44.606525 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
10995 13:39:44.606671 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
10996 13:39:44.606829 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
10997 13:39:44.606998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
10998 13:39:44.607212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
10999 13:39:44.607384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
11000 13:39:44.607540 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
11001 13:39:44.607697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
11002 13:39:44.607859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
11003 13:39:44.608032 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
11004 13:39:44.608182 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
11005 13:39:44.608307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
11006 13:39:44.608453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
11007 13:39:44.608575 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
11008 13:39:44.608692 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
11009 13:39:44.608807 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
11010 13:39:44.608921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
11011 13:39:44.609037 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
11012 13:39:44.609153 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
11013 13:39:44.612275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
11014 13:39:44.612692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
11015 13:39:44.612899 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
11016 13:39:44.613149 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
11017 13:39:44.613321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
11018 13:39:44.613532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
11019 13:39:44.613687 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
11020 13:39:44.613931 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
11021 13:39:44.614126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
11022 13:39:44.614322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
11023 13:39:44.614531 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
11024 13:39:44.614738 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
11025 13:39:44.614981 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
11026 13:39:44.615160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
11027 13:39:44.615336 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
11028 13:39:44.615544 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
11029 13:39:44.615716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
11030 13:39:44.615876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
11031 13:39:44.616090 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
11032 13:39:44.616264 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
11033 13:39:44.616389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
11034 13:39:44.616506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
11035 13:39:44.616622 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
11036 13:39:44.616738 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
11037 13:39:44.616853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
11038 13:39:44.616968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
11039 13:39:44.617085 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
11040 13:39:44.620314 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
11041 13:39:44.620705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
11042 13:39:44.630864 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
11043 13:39:44.631329 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
11044 13:39:44.631549 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
11045 13:39:44.631766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
11046 13:39:44.631996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
11047 13:39:44.632173 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
11048 13:39:44.632319 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
11049 13:39:44.632447 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
11050 13:39:44.632571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
11051 13:39:44.632723 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
11052 13:39:44.632881 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
11053 13:39:44.633068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
11054 13:39:44.633277 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
11055 13:39:44.633443 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
11056 13:39:44.633680 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
11057 13:39:44.633867 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
11058 13:39:44.634035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
11059 13:39:44.634189 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
11060 13:39:44.634359 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
11061 13:39:44.634550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
11062 13:39:44.634758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
11063 13:39:44.634926 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
11064 13:39:44.635095 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
11065 13:39:44.635301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
11066 13:39:44.635511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
11067 13:39:44.635677 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
11068 13:39:44.635844 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
11069 13:39:44.636007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
11070 13:39:44.636174 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
11071 13:39:44.636295 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
11072 13:39:44.636409 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
11073 13:39:44.636522 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
11074 13:39:44.636634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
11075 13:39:44.636973 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
11076 13:39:44.637131 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
11077 13:39:44.637255 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
11078 13:39:44.637375 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
11079 13:39:44.637493 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
11080 13:39:44.640555 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
11081 13:39:44.640751 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
11082 13:39:44.640932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
11083 13:39:44.641119 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
11084 13:39:44.641274 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
11085 13:39:44.641453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
11086 13:39:44.641614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
11087 13:39:44.641788 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
11088 13:39:44.641973 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
11089 13:39:44.642131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
11090 13:39:44.642265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
11091 13:39:44.642443 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
11092 13:39:44.642606 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
11093 13:39:44.642762 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
11094 13:39:44.642945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
11095 13:39:44.643106 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
11096 13:39:44.643242 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
11097 13:39:44.643386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
11098 13:39:44.643574 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
11099 13:39:44.643731 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
11100 13:39:44.643885 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
11101 13:39:44.644020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
11102 13:39:44.644179 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
11103 13:39:44.644306 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
11104 13:39:44.644422 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
11105 13:39:44.644545 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
11106 13:39:44.648314 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
11107 13:39:44.648727 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
11108 13:39:44.648832 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
11109 13:39:44.648918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
11110 13:39:44.649020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
11111 13:39:44.649109 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
11112 13:39:44.649207 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
11113 13:39:44.649496 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
11114 13:39:44.649600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
11115 13:39:44.649710 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
11116 13:39:44.649822 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
11117 13:39:44.650108 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
11118 13:39:44.650200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
11119 13:39:44.650300 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
11120 13:39:44.650587 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
11121 13:39:44.650678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
11122 13:39:44.650777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
11123 13:39:44.651062 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
11124 13:39:44.651152 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
11125 13:39:44.651253 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
11126 13:39:44.651539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
11127 13:39:44.651641 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
11128 13:39:44.651726 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
11129 13:39:44.651826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
11130 13:39:44.652127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
11131 13:39:44.652238 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
11132 13:39:44.656454 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
11133 13:39:44.656572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
11134 13:39:44.656678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
11135 13:39:44.656976 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
11136 13:39:44.657080 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
11137 13:39:44.657178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
11138 13:39:44.657511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
11139 13:39:44.657753 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
11140 13:39:44.657926 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
11141 13:39:44.658113 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
11142 13:39:44.658283 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
11143 13:39:44.658434 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
11144 13:39:44.658621 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
11145 13:39:44.658777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
11146 13:39:44.658967 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
11147 13:39:44.659169 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
11148 13:39:44.659343 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
11149 13:39:44.659505 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
11150 13:39:44.659727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
11151 13:39:44.659898 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
11152 13:39:44.660081 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
11153 13:39:44.660273 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
11154 13:39:44.660465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
11155 13:39:44.660597 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
11156 13:39:44.660716 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
11157 13:39:44.664347 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
11158 13:39:44.664750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
11159 13:39:44.664923 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
11160 13:39:44.665132 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
11161 13:39:44.665361 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
11162 13:39:44.665532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
11163 13:39:44.665734 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
11164 13:39:44.665909 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
11165 13:39:44.666119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
11166 13:39:44.666306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
11167 13:39:44.666517 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
11168 13:39:44.666716 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
11169 13:39:44.666932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
11170 13:39:44.667151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
11171 13:39:44.667335 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
11172 13:39:44.667508 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
11173 13:39:44.667658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
11174 13:39:44.667777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
11175 13:39:44.667891 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
11176 13:39:44.668012 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
11177 13:39:44.668129 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
11178 13:39:44.681372 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
11179 13:39:44.681795 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
11180 13:39:44.681969 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
11181 13:39:44.682158 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
11182 13:39:44.682424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
11183 13:39:44.682611 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
11184 13:39:44.682747 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
11185 13:39:44.682883 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
11186 13:39:44.683052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
11187 13:39:44.683204 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
11188 13:39:44.683396 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
11189 13:39:44.683562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
11190 13:39:44.683729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
11191 13:39:44.683910 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
11192 13:39:44.684106 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
11193 13:39:44.684281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
11194 13:39:44.684415 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
11195 13:39:44.684532 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
11196 13:39:44.684649 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
11197 13:39:44.684791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
11198 13:39:44.684914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
11199 13:39:44.688305 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
11200 13:39:44.688758 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
11201 13:39:44.688948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
11202 13:39:44.689112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
11203 13:39:44.689346 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
11204 13:39:44.689508 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
11205 13:39:44.689690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
11206 13:39:44.689912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
11207 13:39:44.690092 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
11208 13:39:44.690293 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
11209 13:39:44.690466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
11210 13:39:44.690661 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
11211 13:39:44.690873 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
11212 13:39:44.691107 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
11213 13:39:44.691322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
11214 13:39:44.691587 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
11215 13:39:44.691772 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
11216 13:39:44.691930 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
11217 13:39:44.692111 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
11218 13:39:44.692256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
11219 13:39:44.692377 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
11220 13:39:44.692491 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
11221 13:39:44.692633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
11222 13:39:44.692753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
11223 13:39:44.692870 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
11224 13:39:44.696348 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
11225 13:39:44.696772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
11226 13:39:44.697009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
11227 13:39:44.697239 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
11228 13:39:44.697439 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
11229 13:39:44.697657 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
11230 13:39:44.697843 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
11231 13:39:44.698051 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
11232 13:39:44.698236 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
11233 13:39:44.698392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
11234 13:39:44.698563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
11235 13:39:44.698767 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
11236 13:39:44.698936 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
11237 13:39:44.699130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
11238 13:39:44.699344 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
11239 13:39:44.699514 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
11240 13:39:44.699689 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
11241 13:39:44.699915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
11242 13:39:44.700117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
11243 13:39:44.700250 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
11244 13:39:44.700370 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
11245 13:39:44.700489 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
11246 13:39:44.700607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
11247 13:39:44.700723 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
11248 13:39:44.700838 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
11249 13:39:44.700954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
11250 13:39:44.701070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
11251 13:39:44.701185 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
11252 13:39:44.704321 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
11253 13:39:44.704738 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
11254 13:39:44.704913 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
11255 13:39:44.705049 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
11256 13:39:44.705250 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
11257 13:39:44.705485 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
11258 13:39:44.705672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
11259 13:39:44.705853 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
11260 13:39:44.706051 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
11261 13:39:44.706239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
11262 13:39:44.706427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
11263 13:39:44.706654 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
11264 13:39:44.706846 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
11265 13:39:44.707047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
11266 13:39:44.707239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
11267 13:39:44.707407 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
11268 13:39:44.707574 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
11269 13:39:44.707731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
11270 13:39:44.707892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
11271 13:39:44.708090 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
11272 13:39:44.708237 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
11273 13:39:44.708356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
11274 13:39:44.708472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
11275 13:39:44.708592 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
11276 13:39:44.708709 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
11277 13:39:44.708824 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
11278 13:39:44.708940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
11279 13:39:44.709057 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
11280 13:39:44.709174 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
11281 13:39:44.712317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
11282 13:39:44.712621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
11283 13:39:44.712747 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
11284 13:39:44.712855 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
11285 13:39:44.712968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
11286 13:39:44.713066 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
11287 13:39:44.713187 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
11288 13:39:44.713302 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
11289 13:39:44.713480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
11290 13:39:44.713660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
11291 13:39:44.713841 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
11292 13:39:44.714001 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
11293 13:39:44.714195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
11294 13:39:44.714367 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
11295 13:39:44.714559 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
11296 13:39:44.714714 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
11297 13:39:44.714860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
11298 13:39:44.715053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
11299 13:39:44.715220 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
11300 13:39:44.715386 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
11301 13:39:44.715553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11302 13:39:44.715718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11303 13:39:44.715901 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11304 13:39:44.716083 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11305 13:39:44.716268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11306 13:39:44.716404 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11307 13:39:44.716547 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11308 13:39:44.716670 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11309 13:39:44.716849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11310 13:39:44.720359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11311 13:39:44.720764 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11312 13:39:44.731849 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11313 13:39:44.732055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11314 13:39:44.732541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11315 13:39:44.732744 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11316 13:39:44.732988 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11317 13:39:44.733203 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11318 13:39:44.733406 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11319 13:39:44.733635 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11320 13:39:44.733865 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11321 13:39:44.734056 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11322 13:39:44.734214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11323 13:39:44.734451 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11324 13:39:44.734632 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11325 13:39:44.734789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11326 13:39:44.734951 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11327 13:39:44.735117 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11328 13:39:44.735275 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11329 13:39:44.735439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11330 13:39:44.735602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11331 13:39:44.735791 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11332 13:39:44.735962 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11333 13:39:44.736143 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11334 13:39:44.736310 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11335 13:39:44.736433 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11336 13:39:44.736549 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11337 13:39:44.736665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11338 13:39:44.736781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11339 13:39:44.736894 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11340 13:39:44.737007 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11341 13:39:44.740323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11342 13:39:44.740780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11343 13:39:44.740971 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11344 13:39:44.741112 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11345 13:39:44.741280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11346 13:39:44.741418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11347 13:39:44.741537 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11348 13:39:44.741669 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11349 13:39:44.741932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11350 13:39:44.742140 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11351 13:39:44.742346 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11352 13:39:44.742518 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11353 13:39:44.742750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11354 13:39:44.742976 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11355 13:39:44.743131 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11356 13:39:44.743328 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11357 13:39:44.743524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11358 13:39:44.743729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11359 13:39:44.743911 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11360 13:39:44.744081 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11361 13:39:44.744247 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11362 13:39:44.744410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11363 13:39:44.744533 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11364 13:39:44.744650 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11365 13:39:44.744764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11366 13:39:44.744879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11367 13:39:44.744993 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11368 13:39:44.745106 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11369 13:39:44.745219 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11370 13:39:44.745421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11371 13:39:44.748384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11372 13:39:44.748824 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11373 13:39:44.749062 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11374 13:39:44.749271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11375 13:39:44.749490 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11376 13:39:44.749711 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11377 13:39:44.749919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11378 13:39:44.750138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11379 13:39:44.750398 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11380 13:39:44.750599 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11381 13:39:44.750806 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11382 13:39:44.750972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11383 13:39:44.751168 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11384 13:39:44.751367 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11385 13:39:44.751551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11386 13:39:44.751711 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11387 13:39:44.751889 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11388 13:39:44.752069 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11389 13:39:44.752208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11390 13:39:44.752330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11391 13:39:44.752444 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11392 13:39:44.752558 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11393 13:39:44.752699 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11394 13:39:44.752821 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11395 13:39:44.752936 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11396 13:39:44.753051 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11397 13:39:44.756335 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11398 13:39:44.756803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11399 13:39:44.756975 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11400 13:39:44.757127 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11401 13:39:44.757330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11402 13:39:44.757493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11403 13:39:44.757674 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11404 13:39:44.757832 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11405 13:39:44.758054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11406 13:39:44.758247 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11407 13:39:44.758413 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11408 13:39:44.758588 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11409 13:39:44.758814 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11410 13:39:44.759030 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11411 13:39:44.759234 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11412 13:39:44.759456 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11413 13:39:44.759695 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11414 13:39:44.759966 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11415 13:39:44.760152 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11416 13:39:44.760286 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11417 13:39:44.760405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11418 13:39:44.760519 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11419 13:39:44.760633 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11420 13:39:44.760759 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11421 13:39:44.760930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11422 13:39:44.761057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11423 13:39:44.764591 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11424 13:39:44.764789 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11425 13:39:44.764961 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11426 13:39:44.765121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11427 13:39:44.765332 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11428 13:39:44.765509 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11429 13:39:44.765741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11430 13:39:44.766010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11431 13:39:44.766239 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11432 13:39:44.766467 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11433 13:39:44.766675 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11434 13:39:44.766953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11435 13:39:44.767174 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11436 13:39:44.767351 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11437 13:39:44.767506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11438 13:39:44.767628 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11439 13:39:44.767744 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11440 13:39:44.767896 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11441 13:39:44.768025 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11442 13:39:44.768234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11443 13:39:44.768372 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11444 13:39:44.768518 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11445 13:39:44.768659 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11446 13:39:44.781299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11447 13:39:44.781744 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11448 13:39:44.781950 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11449 13:39:44.782121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11450 13:39:44.782304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11451 13:39:44.782458 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11452 13:39:44.782659 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11453 13:39:44.782861 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11454 13:39:44.783084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11455 13:39:44.783284 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11456 13:39:44.783502 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11457 13:39:44.783721 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11458 13:39:44.783935 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11459 13:39:44.784172 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11460 13:39:44.784355 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11461 13:39:44.784482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11462 13:39:44.784601 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11463 13:39:44.784718 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11464 13:39:44.784835 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11465 13:39:44.784950 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11466 13:39:44.785066 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11467 13:39:44.788327 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11468 13:39:44.788780 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11469 13:39:44.788996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11470 13:39:44.789206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11471 13:39:44.789465 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11472 13:39:44.789693 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11473 13:39:44.789879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11474 13:39:44.790079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11475 13:39:44.790324 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11476 13:39:44.790523 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11477 13:39:44.790727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11478 13:39:44.790884 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11479 13:39:44.791016 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11480 13:39:44.791182 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11481 13:39:44.791399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11482 13:39:44.791558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11483 13:39:44.791719 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11484 13:39:44.791849 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11485 13:39:44.791986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11486 13:39:44.792127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11487 13:39:44.792247 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11488 13:39:44.792365 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11489 13:39:44.792480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11490 13:39:44.792594 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11491 13:39:44.792709 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11492 13:39:44.792823 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11493 13:39:44.792963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11494 13:39:44.793081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11495 13:39:44.796277 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11496 13:39:44.796695 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11497 13:39:44.796888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11498 13:39:44.797087 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11499 13:39:44.797331 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11500 13:39:44.797508 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11501 13:39:44.797668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11502 13:39:44.797828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11503 13:39:44.797983 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11504 13:39:44.798191 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11505 13:39:44.798426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11506 13:39:44.798636 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11507 13:39:44.798809 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11508 13:39:44.799002 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11509 13:39:44.799166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11510 13:39:44.799362 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11511 13:39:44.799529 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11512 13:39:44.799688 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11513 13:39:44.799846 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11514 13:39:44.800032 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11515 13:39:44.800219 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11516 13:39:44.800363 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11517 13:39:44.800482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11518 13:39:44.800626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11519 13:39:44.800749 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11520 13:39:44.800866 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11521 13:39:44.800981 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11522 13:39:44.801098 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11523 13:39:44.804327 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11524 13:39:44.804778 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11525 13:39:44.804977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11526 13:39:44.805157 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11527 13:39:44.805361 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11528 13:39:44.805537 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11529 13:39:44.805718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11530 13:39:44.805879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11531 13:39:44.806074 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11532 13:39:44.806240 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11533 13:39:44.806430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11534 13:39:44.806626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11535 13:39:44.806837 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11536 13:39:44.807042 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11537 13:39:44.807240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11538 13:39:44.807456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11539 13:39:44.807661 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11540 13:39:44.807885 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11541 13:39:44.808054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11542 13:39:44.808211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11543 13:39:44.808331 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11544 13:39:44.808449 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11545 13:39:44.808563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11546 13:39:44.808677 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11547 13:39:44.808791 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11548 13:39:44.808929 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11549 13:39:44.809046 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11550 13:39:44.812303 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11551 13:39:44.812734 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11552 13:39:44.812927 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11553 13:39:44.813084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11554 13:39:44.813254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11555 13:39:44.813421 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11556 13:39:44.813582 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11557 13:39:44.813758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11558 13:39:44.813955 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11559 13:39:44.814125 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11560 13:39:44.814294 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11561 13:39:44.814452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11562 13:39:44.814643 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11563 13:39:44.814809 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11564 13:39:44.814971 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11565 13:39:44.815120 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11566 13:39:44.815267 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11567 13:39:44.815421 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11568 13:39:44.815578 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11569 13:39:44.815767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11570 13:39:44.815931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11571 13:39:44.816054 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11572 13:39:44.816171 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11573 13:39:44.816288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11574 13:39:44.816405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11575 13:39:44.816521 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11576 13:39:44.816638 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11577 13:39:44.816777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11578 13:39:44.816897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11579 13:39:44.817012 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11580 13:39:44.830056 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11581 13:39:44.830444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11582 13:39:44.830632 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11583 13:39:44.830801 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11584 13:39:44.831004 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11585 13:39:44.831180 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11586 13:39:44.831397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11587 13:39:44.831620 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11588 13:39:44.831846 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11589 13:39:44.832015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11590 13:39:44.832161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11591 13:39:44.832355 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11592 13:39:44.832552 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11593 13:39:44.832785 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11594 13:39:44.833016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11595 13:39:44.833212 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11596 13:39:44.833381 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11597 13:39:44.833505 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11598 13:39:44.833623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11599 13:39:44.833780 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11600 13:39:44.833970 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11601 13:39:44.834130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11602 13:39:44.834300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11603 13:39:44.834465 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11604 13:39:44.834606 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11605 13:39:44.834795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11606 13:39:44.835076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11607 13:39:44.835294 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11608 13:39:44.835495 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11609 13:39:44.835664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11610 13:39:44.835818 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11611 13:39:44.835963 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11612 13:39:44.836127 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11613 13:39:44.836501 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11614 13:39:44.836661 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11615 13:39:44.836784 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11616 13:39:44.836902 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11617 13:39:44.837019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11618 13:39:44.837135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11619 13:39:44.837252 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11620 13:39:44.837368 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11621 13:39:44.837485 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11622 13:39:44.837605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11623 13:39:44.837736 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11624 13:39:44.837854 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11625 13:39:44.840328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11626 13:39:44.840772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11627 13:39:44.840964 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11628 13:39:44.841128 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11629 13:39:44.841285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11630 13:39:44.841446 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11631 13:39:44.841591 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11632 13:39:44.841779 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11633 13:39:44.841963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11634 13:39:44.842119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11635 13:39:44.842356 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11636 13:39:44.842513 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11637 13:39:44.842651 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11638 13:39:44.842835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11639 13:39:44.843008 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11640 13:39:44.843191 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11641 13:39:44.843328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11642 13:39:44.843493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11643 13:39:44.843671 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11644 13:39:44.843841 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11645 13:39:44.843990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11646 13:39:44.844154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11647 13:39:44.844278 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11648 13:39:44.844395 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11649 13:39:44.844513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11650 13:39:44.844628 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11651 13:39:44.844742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11652 13:39:44.848286 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11653 13:39:44.848698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11654 13:39:44.848854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11655 13:39:44.848979 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11656 13:39:44.849109 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11657 13:39:44.849204 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11658 13:39:44.849309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11659 13:39:44.849401 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11660 13:39:44.849502 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11661 13:39:44.849575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11662 13:39:44.849832 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11663 13:39:44.850086 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11664 13:39:44.850152 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11665 13:39:44.850223 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11666 13:39:44.850472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11667 13:39:44.850724 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11668 13:39:44.850789 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11669 13:39:44.851063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11670 13:39:44.851141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11671 13:39:44.851390 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11672 13:39:44.851455 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11673 13:39:44.851531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11674 13:39:44.851804 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11675 13:39:44.851912 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11676 13:39:44.852006 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11677 13:39:44.852291 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11678 13:39:44.852402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11679 13:39:44.852498 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11680 13:39:44.852764 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11681 13:39:44.852856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11682 13:39:44.852928 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11683 13:39:44.853192 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11684 13:39:44.853268 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11685 13:39:44.853513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11686 13:39:44.853595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11687 13:39:44.853883 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11688 13:39:44.853983 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11689 13:39:44.854240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11690 13:39:44.854341 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11691 13:39:44.854620 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11692 13:39:44.854700 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11693 13:39:44.854791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11694 13:39:44.855053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11695 13:39:44.855158 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11696 13:39:44.855264 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11697 13:39:44.855540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11698 13:39:44.855627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11699 13:39:44.855704 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11700 13:39:44.855977 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11701 13:39:44.856066 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11702 13:39:44.856330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11703 13:39:44.856419 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11704 13:39:44.856540 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11705 13:39:44.856636 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11706 13:39:44.856949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11707 13:39:44.857054 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11708 13:39:44.857152 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11709 13:39:44.857426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11710 13:39:44.857518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11711 13:39:44.857618 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11712 13:39:44.857715 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11713 13:39:44.857832 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11714 13:39:44.879891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11715 13:39:44.880084 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11716 13:39:44.880374 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11717 13:39:44.880465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11718 13:39:44.880569 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11719 13:39:44.880664 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11720 13:39:44.880762 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11721 13:39:44.880861 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11722 13:39:44.881152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11723 13:39:44.881251 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11724 13:39:44.881329 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11725 13:39:44.881407 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11726 13:39:44.881709 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11727 13:39:44.881846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11728 13:39:44.881999 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11729 13:39:44.882138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11730 13:39:44.882324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11731 13:39:44.882473 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11732 13:39:44.882595 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11733 13:39:44.882689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11734 13:39:44.882800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11735 13:39:44.882883 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11736 13:39:44.882962 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11737 13:39:44.883059 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11738 13:39:44.883354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11739 13:39:44.883458 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11740 13:39:44.883564 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11741 13:39:44.883665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11742 13:39:44.883964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11743 13:39:44.884078 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11744 13:39:44.888284 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11745 13:39:44.888576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11746 13:39:44.888679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11747 13:39:44.888765 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11748 13:39:44.889047 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11749 13:39:44.889136 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11750 13:39:44.889234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11751 13:39:44.889318 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11752 13:39:44.889422 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11753 13:39:44.889678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11754 13:39:44.889779 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11755 13:39:44.890060 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11756 13:39:44.890160 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11757 13:39:44.890243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11758 13:39:44.890340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11759 13:39:44.890636 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11760 13:39:44.890735 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11761 13:39:44.890832 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11762 13:39:44.891115 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11763 13:39:44.891216 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11764 13:39:44.891301 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11765 13:39:44.891581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11766 13:39:44.891683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11767 13:39:44.891771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11768 13:39:44.892050 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11769 13:39:44.892150 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11770 13:39:44.892235 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11771 13:39:44.896289 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11772 13:39:44.896580 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11773 13:39:44.896673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11774 13:39:44.896762 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11775 13:39:44.896842 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11776 13:39:44.897128 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11777 13:39:44.897211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11778 13:39:44.897296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11779 13:39:44.897375 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11780 13:39:44.897464 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11781 13:39:44.897557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11782 13:39:44.897845 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11783 13:39:44.897936 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11784 13:39:44.898035 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11785 13:39:44.898157 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11786 13:39:44.898296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11787 13:39:44.898425 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11788 13:39:44.898681 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11789 13:39:44.898790 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11790 13:39:44.899064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11791 13:39:44.899148 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11792 13:39:44.899241 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11793 13:39:44.899332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11794 13:39:44.899426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11795 13:39:44.899711 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11796 13:39:44.899802 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11797 13:39:44.899899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11798 13:39:44.900013 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11799 13:39:44.904262 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11800 13:39:44.904598 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11801 13:39:44.904703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11802 13:39:44.904805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11803 13:39:44.904904 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11804 13:39:44.905179 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11805 13:39:44.905268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11806 13:39:44.905365 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11807 13:39:44.905932 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11808 13:39:44.906038 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11809 13:39:44.906124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11810 13:39:44.906208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11811 13:39:44.906471 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11812 13:39:44.906549 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11813 13:39:44.906630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11814 13:39:44.906714 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11815 13:39:44.906778 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11816 13:39:44.907087 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11817 13:39:44.907156 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11818 13:39:44.907216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11819 13:39:44.907528 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11820 13:39:44.907629 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11821 13:39:44.907726 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11822 13:39:44.907805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11823 13:39:44.907897 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11824 13:39:44.907971 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11825 13:39:44.908055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11826 13:39:44.912319 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11827 13:39:44.912626 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11828 13:39:44.912706 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11829 13:39:44.912783 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11830 13:39:44.912869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11831 13:39:44.912947 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11832 13:39:44.913027 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11833 13:39:44.913123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11834 13:39:44.913452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11835 13:39:44.913543 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11836 13:39:44.913632 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11837 13:39:44.913919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11838 13:39:44.913997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11839 13:39:44.914089 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11840 13:39:44.914186 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11841 13:39:44.914278 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11842 13:39:44.914542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11843 13:39:44.914748 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11844 13:39:44.914914 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11845 13:39:44.915096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11846 13:39:44.915234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11847 13:39:44.915375 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11848 13:39:44.929211 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11849 13:39:44.929423 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11850 13:39:44.929783 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11851 13:39:44.929887 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11852 13:39:44.929994 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11853 13:39:44.930103 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11854 13:39:44.930201 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11855 13:39:44.930277 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11856 13:39:44.930375 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11857 13:39:44.930451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11858 13:39:44.930532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11859 13:39:44.930786 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11860 13:39:44.930862 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11861 13:39:44.930931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11862 13:39:44.931010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11863 13:39:44.931081 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11864 13:39:44.931176 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11865 13:39:44.931461 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11866 13:39:44.931562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11867 13:39:44.931661 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11868 13:39:44.931758 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11869 13:39:44.932029 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11870 13:39:44.932131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11871 13:39:44.936321 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11872 13:39:44.936727 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11873 13:39:44.936931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11874 13:39:44.937141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11875 13:39:44.937336 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11876 13:39:44.937572 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11877 13:39:44.937745 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11878 13:39:44.937927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11879 13:39:44.938119 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11880 13:39:44.938301 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11881 13:39:44.938475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11882 13:39:44.938679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11883 13:39:44.938866 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11884 13:39:44.939047 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11885 13:39:44.939186 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11886 13:39:44.939339 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11887 13:39:44.939499 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11888 13:39:44.939658 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11889 13:39:44.939811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11890 13:39:44.940009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11891 13:39:44.940186 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11892 13:39:44.940318 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11893 13:39:44.940433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11894 13:39:44.940547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11895 13:39:44.940659 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11896 13:39:44.940777 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11897 13:39:44.940890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11898 13:39:44.941005 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11899 13:39:44.941119 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11900 13:39:44.941232 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11901 13:39:44.944356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11902 13:39:44.944655 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11903 13:39:44.944756 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11904 13:39:44.944860 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11905 13:39:44.944947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11906 13:39:44.945047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11907 13:39:44.945158 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11908 13:39:44.945459 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11909 13:39:44.945560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11910 13:39:44.945672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11911 13:39:44.945774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11912 13:39:44.946084 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11913 13:39:44.946176 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11914 13:39:44.946278 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11915 13:39:44.946572 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11916 13:39:44.946764 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11917 13:39:44.946966 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11918 13:39:44.947136 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11919 13:39:44.947331 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11920 13:39:44.947491 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11921 13:39:44.947694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11922 13:39:44.947902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11923 13:39:44.948063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11924 13:39:44.948194 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11925 13:39:44.948311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11926 13:39:44.948448 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11927 13:39:44.952341 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11928 13:39:44.952534 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11929 13:39:44.952965 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11930 13:39:44.953153 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11931 13:39:44.953324 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11932 13:39:44.953511 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11933 13:39:44.953727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11934 13:39:44.953895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11935 13:39:44.954063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11936 13:39:44.954192 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11937 13:39:44.954342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11938 13:39:44.954528 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11939 13:39:44.954681 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
11940 13:39:44.954845 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
11941 13:39:44.955001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
11942 13:39:44.955161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
11943 13:39:44.955324 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
11944 13:39:44.955485 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
11945 13:39:44.955682 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
11946 13:39:44.955847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
11947 13:39:44.956008 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
11948 13:39:44.956149 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
11949 13:39:44.956263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
11950 13:39:44.956376 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
11951 13:39:44.956487 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
11952 13:39:44.956597 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
11953 13:39:44.956735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
11954 13:39:44.956851 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
11955 13:39:44.956962 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
11956 13:39:44.960296 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
11957 13:39:44.960675 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
11958 13:39:44.960776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
11959 13:39:44.960877 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
11960 13:39:44.960962 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
11961 13:39:44.961058 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
11962 13:39:44.961351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
11963 13:39:44.961465 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
11964 13:39:44.961564 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
11965 13:39:44.961873 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
11966 13:39:44.961972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
11967 13:39:44.962071 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
11968 13:39:44.962399 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
11969 13:39:44.962627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
11970 13:39:44.962951 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
11971 13:39:44.963155 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
11972 13:39:44.963335 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
11973 13:39:44.963524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
11974 13:39:44.963745 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
11975 13:39:44.963887 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
11976 13:39:44.964082 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
11977 13:39:44.964217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
11978 13:39:44.964334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
11979 13:39:44.964475 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
11980 13:39:44.964596 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
11981 13:39:44.964711 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
11982 13:39:44.978106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
11983 13:39:44.978535 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
11984 13:39:44.978737 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
11985 13:39:44.978944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
11986 13:39:44.979159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
11987 13:39:44.979328 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
11988 13:39:44.979488 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
11989 13:39:44.979647 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
11990 13:39:44.979872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
11991 13:39:44.980056 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
11992 13:39:44.980213 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
11993 13:39:44.980371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
11994 13:39:44.980516 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
11995 13:39:44.980676 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
11996 13:39:44.980881 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
11997 13:39:44.981094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
11998 13:39:44.981288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
11999 13:39:44.981454 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
12000 13:39:44.981699 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
12001 13:39:44.981884 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
12002 13:39:44.982052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
12003 13:39:44.982206 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
12004 13:39:44.982400 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
12005 13:39:44.982563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
12006 13:39:44.982693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
12007 13:39:44.982852 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
12008 13:39:44.982984 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
12009 13:39:44.983110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
12010 13:39:44.983276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
12011 13:39:44.983451 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
12012 13:39:44.983609 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
12013 13:39:44.983772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
12014 13:39:44.983930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
12015 13:39:44.984336 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
12016 13:39:44.984530 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
12017 13:39:44.984700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
12018 13:39:44.984845 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
12019 13:39:44.984975 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
12020 13:39:44.985107 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
12021 13:39:44.985237 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
12022 13:39:44.985366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
12023 13:39:44.985495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
12024 13:39:44.988436 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
12025 13:39:44.988879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
12026 13:39:44.989092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
12027 13:39:44.989279 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
12028 13:39:44.989470 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
12029 13:39:44.989689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
12030 13:39:44.989866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
12031 13:39:44.990035 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
12032 13:39:44.990192 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
12033 13:39:44.990358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
12034 13:39:44.990530 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
12035 13:39:44.990731 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
12036 13:39:44.990906 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
12037 13:39:44.991078 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
12038 13:39:44.991230 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
12039 13:39:44.991391 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
12040 13:39:44.991561 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
12041 13:39:44.991769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
12042 13:39:44.992009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
12043 13:39:44.992180 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
12044 13:39:44.992302 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
12045 13:39:44.992418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
12046 13:39:44.992534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
12047 13:39:44.992649 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
12048 13:39:44.992765 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
12049 13:39:44.992881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
12050 13:39:44.992996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
12051 13:39:44.993110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
12052 13:39:44.993249 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
12053 13:39:44.996516 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
12054 13:39:44.996762 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
12055 13:39:44.996948 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
12056 13:39:44.997174 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
12057 13:39:44.997354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
12058 13:39:44.997550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
12059 13:39:44.997806 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
12060 13:39:44.998007 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
12061 13:39:44.998187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
12062 13:39:44.998386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
12063 13:39:44.998554 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
12064 13:39:44.998718 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
12065 13:39:44.998890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
12066 13:39:44.999053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
12067 13:39:44.999264 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
12068 13:39:44.999473 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
12069 13:39:44.999658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
12070 13:39:44.999826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
12071 13:39:45.000025 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
12072 13:39:45.000238 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
12073 13:39:45.000370 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
12074 13:39:45.000487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
12075 13:39:45.000603 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
12076 13:39:45.000719 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
12077 13:39:45.000834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
12078 13:39:45.004311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
12079 13:39:45.004716 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
12080 13:39:45.004900 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
12081 13:39:45.005109 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
12082 13:39:45.005287 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
12083 13:39:45.005495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
12084 13:39:45.005702 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
12085 13:39:45.005885 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
12086 13:39:45.006121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
12087 13:39:45.006347 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
12088 13:39:45.006538 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
12089 13:39:45.006744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
12090 13:39:45.006957 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
12091 13:39:45.007188 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
12092 13:39:45.007371 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
12093 13:39:45.007531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
12094 13:39:45.007692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
12095 13:39:45.007855 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
12096 13:39:45.008007 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
12097 13:39:45.008170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
12098 13:39:45.008293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
12099 13:39:45.008408 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
12100 13:39:45.008524 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
12101 13:39:45.008638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
12102 13:39:45.008754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
12103 13:39:45.012308 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
12104 13:39:45.012730 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
12105 13:39:45.012835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
12106 13:39:45.012926 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
12107 13:39:45.013215 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
12108 13:39:45.013319 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
12109 13:39:45.013405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
12110 13:39:45.013506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
12111 13:39:45.013593 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
12112 13:39:45.013699 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
12113 13:39:45.013801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
12114 13:39:45.014117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
12115 13:39:45.014235 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
12116 13:39:45.029979 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
12117 13:39:45.030323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
12118 13:39:45.030528 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
12119 13:39:45.030770 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
12120 13:39:45.030942 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
12121 13:39:45.031160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
12122 13:39:45.031386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
12123 13:39:45.031627 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
12124 13:39:45.031796 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
12125 13:39:45.031950 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
12126 13:39:45.032149 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
12127 13:39:45.032347 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
12128 13:39:45.032559 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
12129 13:39:45.032728 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
12130 13:39:45.032892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
12131 13:39:45.033024 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
12132 13:39:45.033147 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
12133 13:39:45.033292 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
12134 13:39:45.033422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
12135 13:39:45.033569 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
12136 13:39:45.034063 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
12137 13:39:45.034160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
12138 13:39:45.034262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
12139 13:39:45.034366 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
12140 13:39:45.034467 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
12141 13:39:45.034571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
12142 13:39:45.034868 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
12143 13:39:45.034994 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
12144 13:39:45.035297 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
12145 13:39:45.035400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
12146 13:39:45.035506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
12147 13:39:45.035834 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
12148 13:39:45.036005 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
12149 13:39:45.036396 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
12150 13:39:45.036554 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
12151 13:39:45.040446 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
12152 13:39:45.040671 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
12153 13:39:45.041065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
12154 13:39:45.041279 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
12155 13:39:45.041479 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
12156 13:39:45.041712 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
12157 13:39:45.041895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
12158 13:39:45.042132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
12159 13:39:45.042346 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
12160 13:39:45.042569 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
12161 13:39:45.042758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
12162 13:39:45.042959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
12163 13:39:45.043147 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
12164 13:39:45.043317 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
12165 13:39:45.043515 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
12166 13:39:45.043672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
12167 13:39:45.043822 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
12168 13:39:45.043976 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
12169 13:39:45.044172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
12170 13:39:45.044308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
12171 13:39:45.044425 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
12172 13:39:45.044540 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
12173 13:39:45.044656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
12174 13:39:45.044770 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
12175 13:39:45.044916 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
12176 13:39:45.045038 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
12177 13:39:45.045152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
12178 13:39:45.045267 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
12179 13:39:45.048360 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
12180 13:39:45.048851 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
12181 13:39:45.049045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
12182 13:39:45.049236 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
12183 13:39:45.049447 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
12184 13:39:45.049622 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
12185 13:39:45.049801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
12186 13:39:45.050033 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
12187 13:39:45.050224 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
12188 13:39:45.050403 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
12189 13:39:45.050575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
12190 13:39:45.050744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
12191 13:39:45.050942 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
12192 13:39:45.051113 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
12193 13:39:45.051290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
12194 13:39:45.051511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
12195 13:39:45.051723 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
12196 13:39:45.051929 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
12197 13:39:45.052111 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
12198 13:39:45.052292 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
12199 13:39:45.052418 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
12200 13:39:45.052534 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
12201 13:39:45.052655 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
12202 13:39:45.052775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
12203 13:39:45.052894 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
12204 13:39:45.053010 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
12205 13:39:45.053133 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
12206 13:39:45.060295 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
12207 13:39:45.060733 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
12208 13:39:45.060925 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
12209 13:39:45.061082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
12210 13:39:45.061256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
12211 13:39:45.061410 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
12212 13:39:45.061622 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
12213 13:39:45.061840 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
12214 13:39:45.062019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
12215 13:39:45.062236 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
12216 13:39:45.062410 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
12217 13:39:45.062583 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
12218 13:39:45.062751 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
12219 13:39:45.062911 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
12220 13:39:45.063074 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
12221 13:39:45.063223 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
12222 13:39:45.063374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
12223 13:39:45.063500 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
12224 13:39:45.063619 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
12225 13:39:45.063737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
12226 13:39:45.063855 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
12227 13:39:45.063976 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
12228 13:39:45.064144 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
12229 13:39:45.064281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
12230 13:39:45.064402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
12231 13:39:45.064521 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
12232 13:39:45.064638 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
12233 13:39:45.064757 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
12234 13:39:45.064874 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
12235 13:39:45.064995 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
12236 13:39:45.065113 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
12237 13:39:45.065230 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
12238 13:39:45.068307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
12239 13:39:45.068716 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
12240 13:39:45.068824 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
12241 13:39:45.068911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
12242 13:39:45.069012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
12243 13:39:45.069115 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
12244 13:39:45.069215 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
12245 13:39:45.069319 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
12246 13:39:45.069736 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
12247 13:39:45.069931 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
12248 13:39:45.070094 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
12249 13:39:45.070221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
12250 13:39:45.080438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
12251 13:39:45.080833 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
12252 13:39:45.081032 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
12253 13:39:45.081198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
12254 13:39:45.081393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
12255 13:39:45.081553 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
12256 13:39:45.081721 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
12257 13:39:45.081876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
12258 13:39:45.082072 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
12259 13:39:45.082258 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
12260 13:39:45.082425 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
12261 13:39:45.082576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
12262 13:39:45.082765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
12263 13:39:45.082930 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
12264 13:39:45.083092 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
12265 13:39:45.083234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
12266 13:39:45.083405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
12267 13:39:45.083587 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
12268 13:39:45.083759 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
12269 13:39:45.083959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
12270 13:39:45.084124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
12271 13:39:45.084274 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
12272 13:39:45.084397 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
12273 13:39:45.084515 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
12274 13:39:45.084630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
12275 13:39:45.088312 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
12276 13:39:45.088678 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
12277 13:39:45.088782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
12278 13:39:45.088869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
12279 13:39:45.088972 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
12280 13:39:45.089072 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
12281 13:39:45.089170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
12282 13:39:45.089518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
12283 13:39:45.089754 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
12284 13:39:45.089924 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
12285 13:39:45.090153 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
12286 13:39:45.090330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
12287 13:39:45.090494 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
12288 13:39:45.090674 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
12289 13:39:45.090841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
12290 13:39:45.091002 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
12291 13:39:45.091193 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
12292 13:39:45.091354 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
12293 13:39:45.091537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
12294 13:39:45.091717 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
12295 13:39:45.091885 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
12296 13:39:45.092083 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
12297 13:39:45.092251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
12298 13:39:45.092375 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
12299 13:39:45.092495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
12300 13:39:45.092612 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
12301 13:39:45.092728 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12302 13:39:45.096388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12303 13:39:45.096835 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12304 13:39:45.097033 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12305 13:39:45.097163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12306 13:39:45.097337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12307 13:39:45.097500 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12308 13:39:45.097674 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12309 13:39:45.097886 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12310 13:39:45.098125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12311 13:39:45.098287 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12312 13:39:45.098428 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12313 13:39:45.098588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12314 13:39:45.098746 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12315 13:39:45.098897 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12316 13:39:45.099085 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12317 13:39:45.099240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12318 13:39:45.099381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12319 13:39:45.099558 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12320 13:39:45.099745 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12321 13:39:45.099922 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12322 13:39:45.100147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12323 13:39:45.100307 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12324 13:39:45.100434 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12325 13:39:45.100555 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12326 13:39:45.100672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12327 13:39:45.100788 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12328 13:39:45.100907 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12329 13:39:45.101024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12330 13:39:45.101141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12331 13:39:45.101281 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12332 13:39:45.104605 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12333 13:39:45.104829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12334 13:39:45.105045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12335 13:39:45.105305 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12336 13:39:45.105544 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12337 13:39:45.105816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12338 13:39:45.106044 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12339 13:39:45.106249 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12340 13:39:45.106443 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12341 13:39:45.106614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12342 13:39:45.106808 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12343 13:39:45.106975 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12344 13:39:45.107169 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12345 13:39:45.107334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12346 13:39:45.107492 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12347 13:39:45.107685 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12348 13:39:45.107851 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12349 13:39:45.108016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12350 13:39:45.108192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12351 13:39:45.108378 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12352 13:39:45.108509 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12353 13:39:45.112329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12354 13:39:45.112784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12355 13:39:45.113001 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12356 13:39:45.113196 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12357 13:39:45.113358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12358 13:39:45.113556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12359 13:39:45.113735 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12360 13:39:45.113893 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12361 13:39:45.114061 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12362 13:39:45.114227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12363 13:39:45.114416 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12364 13:39:45.114577 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12365 13:39:45.114737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12366 13:39:45.114888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12367 13:39:45.115039 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12368 13:39:45.115195 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12369 13:39:45.115377 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12370 13:39:45.115590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12371 13:39:45.115771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12372 13:39:45.115968 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12373 13:39:45.116555 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12374 13:39:45.116683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12375 13:39:45.116878 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12376 13:39:45.117085 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12377 13:39:45.117253 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12378 13:39:45.117379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12379 13:39:45.117499 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12380 13:39:45.117617 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12381 13:39:45.120435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12382 13:39:45.120612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12383 13:39:45.120956 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12384 13:39:45.133177 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12385 13:39:45.133621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12386 13:39:45.133820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12387 13:39:45.133997 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12388 13:39:45.134208 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12389 13:39:45.134439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12390 13:39:45.134650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12391 13:39:45.134865 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12392 13:39:45.135099 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12393 13:39:45.135318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12394 13:39:45.135524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12395 13:39:45.135716 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12396 13:39:45.135898 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12397 13:39:45.136062 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12398 13:39:45.136257 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12399 13:39:45.136384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12400 13:39:45.136501 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12401 13:39:45.136616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12402 13:39:45.136731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12403 13:39:45.136846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12404 13:39:45.136960 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12405 13:39:45.137074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12406 13:39:45.140313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12407 13:39:45.140717 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12408 13:39:45.140823 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12409 13:39:45.140908 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12410 13:39:45.141007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12411 13:39:45.141094 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12412 13:39:45.141191 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12413 13:39:45.141485 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12414 13:39:45.141602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12415 13:39:45.141936 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12416 13:39:45.142127 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12417 13:39:45.142337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12418 13:39:45.142500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12419 13:39:45.142682 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12420 13:39:45.142821 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12421 13:39:45.143011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12422 13:39:45.143248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12423 13:39:45.143425 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12424 13:39:45.143602 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12425 13:39:45.143764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12426 13:39:45.143957 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12427 13:39:45.144124 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12428 13:39:45.144244 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12429 13:39:45.144357 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12430 13:39:45.144470 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12431 13:39:45.144604 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12432 13:39:45.148294 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12433 13:39:45.148696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12434 13:39:45.148803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12435 13:39:45.148906 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12436 13:39:45.148997 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12437 13:39:45.149096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12438 13:39:45.149204 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12439 13:39:45.149515 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12440 13:39:45.149618 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12441 13:39:45.149726 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12442 13:39:45.150027 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12443 13:39:45.150147 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12444 13:39:45.150236 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12445 13:39:45.150537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12446 13:39:45.150639 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12447 13:39:45.150740 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12448 13:39:45.150843 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12449 13:39:45.151164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12450 13:39:45.151283 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12451 13:39:45.151392 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12452 13:39:45.151493 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12453 13:39:45.151791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12454 13:39:45.151896 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12455 13:39:45.151997 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12456 13:39:45.152296 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12457 13:39:45.156281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12458 13:39:45.156595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12459 13:39:45.156713 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12460 13:39:45.156800 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12461 13:39:45.156897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12462 13:39:45.157204 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12463 13:39:45.157327 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12464 13:39:45.157429 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12465 13:39:45.157736 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12466 13:39:45.157983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12467 13:39:45.158181 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12468 13:39:45.158386 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12469 13:39:45.158557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12470 13:39:45.158780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12471 13:39:45.158957 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12472 13:39:45.159133 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12473 13:39:45.159351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12474 13:39:45.159499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12475 13:39:45.159648 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12476 13:39:45.159797 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12477 13:39:45.159984 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12478 13:39:45.160124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12479 13:39:45.160243 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12480 13:39:45.160359 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12481 13:39:45.160475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12482 13:39:45.164307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12483 13:39:45.164809 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12484 13:39:45.164998 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12485 13:39:45.165154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12486 13:39:45.165353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12487 13:39:45.165573 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12488 13:39:45.165788 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12489 13:39:45.165989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12490 13:39:45.166178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12491 13:39:45.166360 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12492 13:39:45.166572 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12493 13:39:45.166766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12494 13:39:45.166932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12495 13:39:45.167092 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12496 13:39:45.167304 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12497 13:39:45.167536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12498 13:39:45.167749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12499 13:39:45.167966 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12500 13:39:45.168146 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12501 13:39:45.168281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12502 13:39:45.168398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12503 13:39:45.168515 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12504 13:39:45.168629 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12505 13:39:45.168744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12506 13:39:45.168858 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12507 13:39:45.168974 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12508 13:39:45.169088 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12509 13:39:45.169204 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12510 13:39:45.172302 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12511 13:39:45.172729 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12512 13:39:45.172921 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12513 13:39:45.173119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12514 13:39:45.173278 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12515 13:39:45.173408 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12516 13:39:45.173563 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12517 13:39:45.173698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12518 13:39:45.183985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12519 13:39:45.184289 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12520 13:39:45.184408 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12521 13:39:45.184706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12522 13:39:45.184824 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12523 13:39:45.184926 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12524 13:39:45.185026 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12525 13:39:45.185133 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12526 13:39:45.185471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12527 13:39:45.185691 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12528 13:39:45.185871 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12529 13:39:45.186128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12530 13:39:45.186297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12531 13:39:45.186461 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12532 13:39:45.186617 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12533 13:39:45.186814 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12534 13:39:45.186972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12535 13:39:45.187181 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12536 13:39:45.187386 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12537 13:39:45.187586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12538 13:39:45.187755 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12539 13:39:45.187919 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12540 13:39:45.188116 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12541 13:39:45.188281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12542 13:39:45.188401 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12543 13:39:45.188544 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12544 13:39:45.188665 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12545 13:39:45.192321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12546 13:39:45.192740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12547 13:39:45.192949 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12548 13:39:45.193152 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12549 13:39:45.193322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12550 13:39:45.193486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12551 13:39:45.193692 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12552 13:39:45.193869 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12553 13:39:45.194039 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12554 13:39:45.194207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12555 13:39:45.194423 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12556 13:39:45.194593 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12557 13:39:45.194742 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12558 13:39:45.194873 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12559 13:39:45.195021 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12560 13:39:45.195169 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12561 13:39:45.195344 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12562 13:39:45.195508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12563 13:39:45.195662 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12564 13:39:45.195819 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12565 13:39:45.195980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12566 13:39:45.196627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12567 13:39:45.196787 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12568 13:39:45.196932 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12569 13:39:45.197076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12570 13:39:45.197225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12571 13:39:45.197368 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12572 13:39:45.200313 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12573 13:39:45.200740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12574 13:39:45.200934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12575 13:39:45.201100 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12576 13:39:45.201283 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12577 13:39:45.201446 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12578 13:39:45.201617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12579 13:39:45.201793 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12580 13:39:45.201973 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12581 13:39:45.202151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12582 13:39:45.202347 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12583 13:39:45.202541 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12584 13:39:45.202735 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12585 13:39:45.202959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12586 13:39:45.203137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12587 13:39:45.203331 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12588 13:39:45.203534 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12589 13:39:45.203705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12590 13:39:45.203862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12591 13:39:45.204007 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12592 13:39:45.204126 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12593 13:39:45.204276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12594 13:39:45.204398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12595 13:39:45.204516 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12596 13:39:45.204631 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12597 13:39:45.204748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12598 13:39:45.204865 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12599 13:39:45.204979 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12600 13:39:45.208307 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12601 13:39:45.208734 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12602 13:39:45.208919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12603 13:39:45.209088 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12604 13:39:45.209275 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12605 13:39:45.209434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12606 13:39:45.209602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12607 13:39:45.209774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12608 13:39:45.209972 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12609 13:39:45.210145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12610 13:39:45.210308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12611 13:39:45.210467 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12612 13:39:45.210621 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12613 13:39:45.210805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12614 13:39:45.210973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12615 13:39:45.211132 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12616 13:39:45.211277 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12617 13:39:45.211446 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12618 13:39:45.211616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12619 13:39:45.211777 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12620 13:39:45.211970 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12621 13:39:45.212219 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12622 13:39:45.212419 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12623 13:39:45.212555 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12624 13:39:45.212673 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12625 13:39:45.212789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12626 13:39:45.212904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12627 13:39:45.216396 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12628 13:39:45.216558 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12629 13:39:45.216906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12630 13:39:45.217053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12631 13:39:45.217176 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12632 13:39:45.217309 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12633 13:39:45.217392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12634 13:39:45.217470 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12635 13:39:45.217549 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12636 13:39:45.217627 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12637 13:39:45.217744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12638 13:39:45.217859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12639 13:39:45.217966 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12640 13:39:45.218286 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12641 13:39:45.218477 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12642 13:39:45.218653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12643 13:39:45.218859 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12644 13:39:45.219028 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12645 13:39:45.219187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12646 13:39:45.219405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12647 13:39:45.219576 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12648 13:39:45.219723 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12649 13:39:45.219881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12650 13:39:45.220062 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12651 13:39:45.220189 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12652 13:39:45.233755 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12653 13:39:45.234228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12654 13:39:45.234431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12655 13:39:45.234599 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12656 13:39:45.234811 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12657 13:39:45.234979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12658 13:39:45.235135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12659 13:39:45.235295 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12660 13:39:45.235460 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12661 13:39:45.235648 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12662 13:39:45.235808 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12663 13:39:45.235970 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12664 13:39:45.236124 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12665 13:39:45.236252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12666 13:39:45.236445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12667 13:39:45.236644 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12668 13:39:45.236805 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12669 13:39:45.236967 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12670 13:39:45.237129 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12671 13:39:45.237288 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12672 13:39:45.237455 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12673 13:39:45.241675 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12674 13:39:45.241837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12675 13:39:45.241956 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12676 13:39:45.242069 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12677 13:39:45.242182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12678 13:39:45.242297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12679 13:39:45.242409 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12680 13:39:45.242549 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12681 13:39:45.242668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12682 13:39:45.242782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12683 13:39:45.242896 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12684 13:39:45.243008 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12685 13:39:45.243342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12686 13:39:45.243468 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12687 13:39:45.243583 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12688 13:39:45.243696 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12689 13:39:45.243809 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12690 13:39:45.243922 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12691 13:39:45.244035 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12692 13:39:45.244147 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12693 13:39:45.244304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12694 13:39:45.244453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12695 13:39:45.244592 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12696 13:39:45.244730 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12697 13:39:45.244913 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12698 13:39:45.245054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12699 13:39:45.245194 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12700 13:39:45.245340 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12701 13:39:45.245491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12702 13:39:45.245683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12703 13:39:45.245811 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12704 13:39:45.245928 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12705 13:39:45.246041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12706 13:39:45.246155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12707 13:39:45.246293 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12708 13:39:45.246411 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12709 13:39:45.246524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12710 13:39:45.246638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12711 13:39:45.246751 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12712 13:39:45.246863 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12713 13:39:45.246998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12714 13:39:45.247114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12715 13:39:45.247228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12716 13:39:45.247585 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12717 13:39:45.247768 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12718 13:39:45.247936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12719 13:39:45.248090 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12720 13:39:45.248210 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12721 13:39:45.248327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12722 13:39:45.248441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12723 13:39:45.248579 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12724 13:39:45.248696 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12725 13:39:45.248809 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12726 13:39:45.248921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12727 13:39:45.252428 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12728 13:39:45.252533 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12729 13:39:45.252812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12730 13:39:45.252906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12731 13:39:45.252991 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12732 13:39:45.253091 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12733 13:39:45.253190 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12734 13:39:45.253293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12735 13:39:45.253623 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12736 13:39:45.253845 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12737 13:39:45.254055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12738 13:39:45.254237 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12739 13:39:45.254451 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12740 13:39:45.254645 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12741 13:39:45.254842 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12742 13:39:45.254992 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12743 13:39:45.255146 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12744 13:39:45.255323 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12745 13:39:45.255495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12746 13:39:45.255646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12747 13:39:45.255820 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12748 13:39:45.255974 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12749 13:39:45.256116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12750 13:39:45.256300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12751 13:39:45.256453 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12752 13:39:45.256602 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12753 13:39:45.256786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12754 13:39:45.256934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12755 13:39:45.257089 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12756 13:39:45.257277 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12757 13:39:45.257433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12758 13:39:45.257558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12759 13:39:45.257709 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12760 13:39:45.257830 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12761 13:39:45.264587 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12762 13:39:45.264795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12763 13:39:45.264991 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12764 13:39:45.265155 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12765 13:39:45.265315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12766 13:39:45.265499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12767 13:39:45.265633 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12768 13:39:45.265781 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12769 13:39:45.265938 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12770 13:39:45.266123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12771 13:39:45.266282 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12772 13:39:45.266440 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12773 13:39:45.266633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12774 13:39:45.266796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12775 13:39:45.266953 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12776 13:39:45.267147 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12777 13:39:45.267312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12778 13:39:45.267474 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12779 13:39:45.267666 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12780 13:39:45.267819 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12781 13:39:45.267977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12782 13:39:45.268104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12783 13:39:45.268246 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12784 13:39:45.268415 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12785 13:39:45.268549 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12786 13:39:45.292731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12787 13:39:45.293260 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12788 13:39:45.293422 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12789 13:39:45.293547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12790 13:39:45.293748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12791 13:39:45.293915 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12792 13:39:45.294079 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12793 13:39:45.294240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12794 13:39:45.294394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12795 13:39:45.294551 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12796 13:39:45.294741 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12797 13:39:45.294910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12798 13:39:45.295085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12799 13:39:45.295309 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12800 13:39:45.295495 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12801 13:39:45.295648 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12802 13:39:45.295842 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12803 13:39:45.296013 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12804 13:39:45.296222 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12805 13:39:45.296424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12806 13:39:45.300413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12807 13:39:45.300844 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12808 13:39:45.301038 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12809 13:39:45.301240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12810 13:39:45.301409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12811 13:39:45.301592 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12812 13:39:45.301775 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12813 13:39:45.301973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12814 13:39:45.302149 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12815 13:39:45.302346 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12816 13:39:45.302535 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12817 13:39:45.302701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12818 13:39:45.302911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12819 13:39:45.303106 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12820 13:39:45.303340 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12821 13:39:45.303523 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12822 13:39:45.303762 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12823 13:39:45.303995 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12824 13:39:45.304192 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12825 13:39:45.304395 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12826 13:39:45.304527 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12827 13:39:45.308383 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12828 13:39:45.308799 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12829 13:39:45.308989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12830 13:39:45.309187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12831 13:39:45.309359 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12832 13:39:45.309523 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12833 13:39:45.309721 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12834 13:39:45.309849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12835 13:39:45.311128 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12836 13:39:45.311326 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12837 13:39:45.311492 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12838 13:39:45.311655 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12839 13:39:45.311818 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12840 13:39:45.311982 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12841 13:39:45.312369 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12842 13:39:45.312495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12843 13:39:45.312612 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12844 13:39:45.312940 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12845 13:39:45.313068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12846 13:39:45.313186 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12847 13:39:45.313301 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12848 13:39:45.313420 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12849 13:39:45.316521 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12850 13:39:45.317014 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12851 13:39:45.317236 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12852 13:39:45.317453 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12853 13:39:45.317668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12854 13:39:45.317905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12855 13:39:45.318155 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12856 13:39:45.318341 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12857 13:39:45.318507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12858 13:39:45.318673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12859 13:39:45.320744 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12860 13:39:45.320858 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12861 13:39:45.320952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12862 13:39:45.321044 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12863 13:39:45.321136 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12864 13:39:45.321227 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12865 13:39:45.321316 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12866 13:39:45.321412 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12867 13:39:45.321501 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12868 13:39:45.321589 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12869 13:39:45.321689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12870 13:39:45.321785 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12871 13:39:45.321874 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12872 13:39:45.321964 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12873 13:39:45.322055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12874 13:39:45.322150 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12875 13:39:45.322240 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12876 13:39:45.322332 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12877 13:39:45.322429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12878 13:39:45.322520 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12879 13:39:45.324320 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12880 13:39:45.324636 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12881 13:39:45.324740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12882 13:39:45.324840 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12883 13:39:45.325156 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12884 13:39:45.325273 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12885 13:39:45.325366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12886 13:39:45.325673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12887 13:39:45.325790 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12888 13:39:45.325891 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12889 13:39:45.326175 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12890 13:39:45.326292 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12891 13:39:45.326590 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12892 13:39:45.326694 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12893 13:39:45.326793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12894 13:39:45.327089 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12895 13:39:45.327265 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12896 13:39:45.327367 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12897 13:39:45.327675 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12898 13:39:45.327792 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12899 13:39:45.327969 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12900 13:39:45.328111 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12901 13:39:45.332279 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12902 13:39:45.332574 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12903 13:39:45.332690 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12904 13:39:45.332798 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12905 13:39:45.333098 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12906 13:39:45.333200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12907 13:39:45.333301 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12908 13:39:45.333406 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12909 13:39:45.333732 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12910 13:39:45.333927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12911 13:39:45.334139 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12912 13:39:45.334321 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12913 13:39:45.334501 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12914 13:39:45.334694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12915 13:39:45.334855 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12916 13:39:45.334977 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12917 13:39:45.335094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12918 13:39:45.335232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12919 13:39:45.335373 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12920 13:39:45.354744 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12921 13:39:45.355196 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12922 13:39:45.355358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12923 13:39:45.355494 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12924 13:39:45.355653 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12925 13:39:45.355862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12926 13:39:45.356017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12927 13:39:45.356177 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12928 13:39:45.356344 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12929 13:39:45.356497 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12930 13:39:45.356709 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12931 13:39:45.356903 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12932 13:39:45.357122 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12933 13:39:45.357333 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12934 13:39:45.357517 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12935 13:39:45.357847 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12936 13:39:45.358048 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12937 13:39:45.358184 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12938 13:39:45.358377 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12939 13:39:45.358552 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
12940 13:39:45.358711 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
12941 13:39:45.358870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
12942 13:39:45.359025 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
12943 13:39:45.359188 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
12944 13:39:45.359383 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
12945 13:39:45.359544 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
12946 13:39:45.359730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
12947 13:39:45.359902 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
12948 13:39:45.360046 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
12949 13:39:45.360177 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
12950 13:39:45.360292 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
12951 13:39:45.360406 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
12952 13:39:45.360523 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
12953 13:39:45.360869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
12954 13:39:45.361026 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
12955 13:39:45.361148 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
12956 13:39:45.361267 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
12957 13:39:45.361384 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
12958 13:39:45.361500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
12959 13:39:45.361617 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
12960 13:39:45.364364 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
12961 13:39:45.364763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
12962 13:39:45.364866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
12963 13:39:45.364953 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
12964 13:39:45.365052 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
12965 13:39:45.365152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
12966 13:39:45.365482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
12967 13:39:45.365726 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
12968 13:39:45.365980 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
12969 13:39:45.366165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
12970 13:39:45.366329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
12971 13:39:45.366513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
12972 13:39:45.366709 arm64_sve-ptrace pass
12973 13:39:45.366900 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
12974 13:39:45.367085 arm64_sve-probe-vls_All_vector_lengths_valid pass
12975 13:39:45.367275 arm64_sve-probe-vls pass
12976 13:39:45.367487 arm64_vec-syscfg_SVE_default_vector_length_64 pass
12977 13:39:45.367663 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
12978 13:39:45.367839 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
12979 13:39:45.368013 arm64_vec-syscfg_SVE_current_VL_is_64 pass
12980 13:39:45.368189 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
12981 13:39:45.368358 arm64_vec-syscfg_SVE_prctl_set_min_max pass
12982 13:39:45.368530 arm64_vec-syscfg_SVE_vector_length_used_default pass
12983 13:39:45.368745 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
12984 13:39:45.368928 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
12985 13:39:45.369107 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
12986 13:39:45.369279 arm64_vec-syscfg_SME_default_vector_length_32 pass
12987 13:39:45.369452 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
12988 13:39:45.369612 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
12989 13:39:45.370434 arm64_vec-syscfg_SME_current_VL_is_32 pass
12990 13:39:45.372313 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
12991 13:39:45.372702 arm64_vec-syscfg_SME_prctl_set_min_max pass
12992 13:39:45.372874 arm64_vec-syscfg_SME_vector_length_used_default pass
12993 13:39:45.373034 arm64_vec-syscfg_SME_vector_length_was_inherited pass
12994 13:39:45.373209 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
12995 13:39:45.373376 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
12996 13:39:45.373553 arm64_vec-syscfg pass
12997 13:39:45.373736 arm64_za-fork_fork_test pass
12998 13:39:45.373948 arm64_za-fork pass
12999 13:39:45.374158 arm64_za-ptrace_Set_VL_16 pass
13000 13:39:45.374393 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
13001 13:39:45.374571 arm64_za-ptrace_Data_match_for_VL_16 pass
13002 13:39:45.374755 arm64_za-ptrace_Set_VL_32 pass
13003 13:39:45.374926 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
13004 13:39:45.375089 arm64_za-ptrace_Data_match_for_VL_32 pass
13005 13:39:45.375252 arm64_za-ptrace_Set_VL_48 pass
13006 13:39:45.375410 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
13007 13:39:45.375566 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
13008 13:39:45.375706 arm64_za-ptrace_Set_VL_64 pass
13009 13:39:45.375853 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
13010 13:39:45.375991 arm64_za-ptrace_Data_match_for_VL_64 pass
13011 13:39:45.376111 arm64_za-ptrace_Set_VL_80 pass
13012 13:39:45.376225 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
13013 13:39:45.376339 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
13014 13:39:45.376453 arm64_za-ptrace_Set_VL_96 pass
13015 13:39:45.376569 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
13016 13:39:45.376716 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
13017 13:39:45.376837 arm64_za-ptrace_Set_VL_112 pass
13018 13:39:45.376954 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
13019 13:39:45.377069 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
13020 13:39:45.377184 arm64_za-ptrace_Set_VL_128 pass
13021 13:39:45.377298 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
13022 13:39:45.377413 arm64_za-ptrace_Data_match_for_VL_128 pass
13023 13:39:45.377531 arm64_za-ptrace_Set_VL_144 pass
13024 13:39:45.377673 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
13025 13:39:45.377894 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
13026 13:39:45.378082 arm64_za-ptrace_Set_VL_160 pass
13027 13:39:45.378267 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
13028 13:39:45.378453 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
13029 13:39:45.378642 arm64_za-ptrace_Set_VL_176 pass
13030 13:39:45.378787 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
13031 13:39:45.378931 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
13032 13:39:45.379073 arm64_za-ptrace_Set_VL_192 pass
13033 13:39:45.380419 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
13034 13:39:45.380873 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
13035 13:39:45.381063 arm64_za-ptrace_Set_VL_208 pass
13036 13:39:45.381254 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
13037 13:39:45.381445 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
13038 13:39:45.381615 arm64_za-ptrace_Set_VL_224 pass
13039 13:39:45.381835 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
13040 13:39:45.382036 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
13041 13:39:45.382232 arm64_za-ptrace_Set_VL_240 pass
13042 13:39:45.382488 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
13043 13:39:45.382690 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
13044 13:39:45.382897 arm64_za-ptrace_Set_VL_256 pass
13045 13:39:45.383092 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
13046 13:39:45.383261 arm64_za-ptrace_Data_match_for_VL_256 pass
13047 13:39:45.383425 arm64_za-ptrace_Set_VL_272 pass
13048 13:39:45.383588 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
13049 13:39:45.383751 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
13050 13:39:45.383912 arm64_za-ptrace_Set_VL_288 pass
13051 13:39:45.384062 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
13052 13:39:45.384213 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
13053 13:39:45.384334 arm64_za-ptrace_Set_VL_304 pass
13054 13:39:45.384449 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
13055 13:39:45.384562 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
13056 13:39:45.384681 arm64_za-ptrace_Set_VL_320 pass
13057 13:39:45.384796 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
13058 13:39:45.384910 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
13059 13:39:45.385025 arm64_za-ptrace_Set_VL_336 pass
13060 13:39:45.385140 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
13061 13:39:45.385255 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
13062 13:39:45.385369 arm64_za-ptrace_Set_VL_352 pass
13063 13:39:45.385483 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
13064 13:39:45.385599 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
13065 13:39:45.385810 arm64_za-ptrace_Set_VL_368 pass
13066 13:39:45.388718 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
13067 13:39:45.388930 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
13068 13:39:45.389130 arm64_za-ptrace_Set_VL_384 pass
13069 13:39:45.389301 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
13070 13:39:45.389459 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
13071 13:39:45.389660 arm64_za-ptrace_Set_VL_400 pass
13072 13:39:45.389820 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
13073 13:39:45.389967 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
13074 13:39:45.390157 arm64_za-ptrace_Set_VL_416 pass
13075 13:39:45.390301 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
13076 13:39:45.390435 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
13077 13:39:45.390547 arm64_za-ptrace_Set_VL_432 pass
13078 13:39:45.390625 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
13079 13:39:45.390698 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
13080 13:39:45.390804 arm64_za-ptrace_Set_VL_448 pass
13081 13:39:45.390895 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
13082 13:39:45.390990 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
13083 13:39:45.391081 arm64_za-ptrace_Set_VL_464 pass
13084 13:39:45.391177 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
13085 13:39:45.391271 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
13086 13:39:45.391347 arm64_za-ptrace_Set_VL_480 pass
13087 13:39:45.391423 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
13088 13:39:45.391510 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
13089 13:39:45.391603 arm64_za-ptrace_Set_VL_496 pass
13090 13:39:45.391701 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
13091 13:39:45.427096 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
13092 13:39:45.427326 arm64_za-ptrace_Set_VL_512 pass
13093 13:39:45.427753 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
13094 13:39:45.428024 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
13095 13:39:45.428207 arm64_za-ptrace_Set_VL_528 pass
13096 13:39:45.428374 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
13097 13:39:45.428546 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
13098 13:39:45.428713 arm64_za-ptrace_Set_VL_544 pass
13099 13:39:45.428910 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
13100 13:39:45.429079 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
13101 13:39:45.429246 arm64_za-ptrace_Set_VL_560 pass
13102 13:39:45.429409 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
13103 13:39:45.429572 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
13104 13:39:45.429753 arm64_za-ptrace_Set_VL_576 pass
13105 13:39:45.429974 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
13106 13:39:45.430215 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
13107 13:39:45.430422 arm64_za-ptrace_Set_VL_592 pass
13108 13:39:45.430655 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
13109 13:39:45.430930 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
13110 13:39:45.431193 arm64_za-ptrace_Set_VL_608 pass
13111 13:39:45.431385 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
13112 13:39:45.431532 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
13113 13:39:45.431704 arm64_za-ptrace_Set_VL_624 pass
13114 13:39:45.431875 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
13115 13:39:45.432018 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
13116 13:39:45.432184 arm64_za-ptrace_Set_VL_640 pass
13117 13:39:45.432309 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
13118 13:39:45.432427 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
13119 13:39:45.432545 arm64_za-ptrace_Set_VL_656 pass
13120 13:39:45.432659 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
13121 13:39:45.432773 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
13122 13:39:45.432885 arm64_za-ptrace_Set_VL_672 pass
13123 13:39:45.432997 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
13124 13:39:45.433109 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
13125 13:39:45.433221 arm64_za-ptrace_Set_VL_688 pass
13126 13:39:45.433331 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
13127 13:39:45.433443 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
13128 13:39:45.433555 arm64_za-ptrace_Set_VL_704 pass
13129 13:39:45.433718 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
13130 13:39:45.433929 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
13131 13:39:45.436471 arm64_za-ptrace_Set_VL_720 pass
13132 13:39:45.436904 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
13133 13:39:45.437095 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
13134 13:39:45.437355 arm64_za-ptrace_Set_VL_736 pass
13135 13:39:45.437513 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
13136 13:39:45.437676 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
13137 13:39:45.437808 arm64_za-ptrace_Set_VL_752 pass
13138 13:39:45.437967 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
13139 13:39:45.438163 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
13140 13:39:45.438318 arm64_za-ptrace_Set_VL_768 pass
13141 13:39:45.438496 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
13142 13:39:45.438654 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
13143 13:39:45.438807 arm64_za-ptrace_Set_VL_784 pass
13144 13:39:45.438988 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
13145 13:39:45.439147 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
13146 13:39:45.439298 arm64_za-ptrace_Set_VL_800 pass
13147 13:39:45.439446 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
13148 13:39:45.439573 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
13149 13:39:45.439701 arm64_za-ptrace_Set_VL_816 pass
13150 13:39:45.439828 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
13151 13:39:45.439981 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
13152 13:39:45.440124 arm64_za-ptrace_Set_VL_832 pass
13153 13:39:45.440244 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
13154 13:39:45.440361 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
13155 13:39:45.440479 arm64_za-ptrace_Set_VL_848 pass
13156 13:39:45.440622 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
13157 13:39:45.440744 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
13158 13:39:45.444296 arm64_za-ptrace_Set_VL_864 pass
13159 13:39:45.444636 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
13160 13:39:45.444771 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
13161 13:39:45.444896 arm64_za-ptrace_Set_VL_880 pass
13162 13:39:45.445014 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
13163 13:39:45.445184 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
13164 13:39:45.445342 arm64_za-ptrace_Set_VL_896 pass
13165 13:39:45.445493 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
13166 13:39:45.445663 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
13167 13:39:45.445820 arm64_za-ptrace_Set_VL_912 pass
13168 13:39:45.445966 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
13169 13:39:45.446114 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
13170 13:39:45.446305 arm64_za-ptrace_Set_VL_928 pass
13171 13:39:45.446463 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
13172 13:39:45.446600 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
13173 13:39:45.446736 arm64_za-ptrace_Set_VL_944 pass
13174 13:39:45.446882 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
13175 13:39:45.447033 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
13176 13:39:45.447191 arm64_za-ptrace_Set_VL_960 pass
13177 13:39:45.447348 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
13178 13:39:45.447502 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
13179 13:39:45.447625 arm64_za-ptrace_Set_VL_976 pass
13180 13:39:45.447744 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
13181 13:39:45.447874 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
13182 13:39:45.448065 arm64_za-ptrace_Set_VL_992 pass
13183 13:39:45.448223 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
13184 13:39:45.448369 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
13185 13:39:45.448512 arm64_za-ptrace_Set_VL_1008 pass
13186 13:39:45.448656 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
13187 13:39:45.448798 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
13188 13:39:45.448940 arm64_za-ptrace_Set_VL_1024 pass
13189 13:39:45.449082 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
13190 13:39:45.449224 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
13191 13:39:45.449366 arm64_za-ptrace_Set_VL_1040 pass
13192 13:39:45.449506 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
13193 13:39:45.449655 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
13194 13:39:45.449801 arm64_za-ptrace_Set_VL_1056 pass
13195 13:39:45.449943 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
13196 13:39:45.450084 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
13197 13:39:45.450226 arm64_za-ptrace_Set_VL_1072 pass
13198 13:39:45.450367 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
13199 13:39:45.450544 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
13200 13:39:45.450679 arm64_za-ptrace_Set_VL_1088 pass
13201 13:39:45.452459 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
13202 13:39:45.452677 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
13203 13:39:45.453055 arm64_za-ptrace_Set_VL_1104 pass
13204 13:39:45.453149 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
13205 13:39:45.453239 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
13206 13:39:45.453316 arm64_za-ptrace_Set_VL_1120 pass
13207 13:39:45.453409 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
13208 13:39:45.453482 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
13209 13:39:45.453556 arm64_za-ptrace_Set_VL_1136 pass
13210 13:39:45.453630 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
13211 13:39:45.453928 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
13212 13:39:45.454002 arm64_za-ptrace_Set_VL_1152 pass
13213 13:39:45.454078 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
13214 13:39:45.454153 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
13215 13:39:45.454226 arm64_za-ptrace_Set_VL_1168 pass
13216 13:39:45.454300 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
13217 13:39:45.454557 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
13218 13:39:45.454634 arm64_za-ptrace_Set_VL_1184 pass
13219 13:39:45.454722 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
13220 13:39:45.454813 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
13221 13:39:45.454888 arm64_za-ptrace_Set_VL_1200 pass
13222 13:39:45.454960 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
13223 13:39:45.455047 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
13224 13:39:45.455124 arm64_za-ptrace_Set_VL_1216 pass
13225 13:39:45.455198 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
13226 13:39:45.455294 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
13227 13:39:45.455377 arm64_za-ptrace_Set_VL_1232 pass
13228 13:39:45.455459 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
13229 13:39:45.455541 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
13230 13:39:45.455617 arm64_za-ptrace_Set_VL_1248 pass
13231 13:39:45.455706 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
13232 13:39:45.455773 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
13233 13:39:45.455834 arm64_za-ptrace_Set_VL_1264 pass
13234 13:39:45.455897 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
13235 13:39:45.455976 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
13236 13:39:45.456070 arm64_za-ptrace_Set_VL_1280 pass
13237 13:39:45.456173 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
13238 13:39:45.456261 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
13239 13:39:45.456329 arm64_za-ptrace_Set_VL_1296 pass
13240 13:39:45.456389 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
13241 13:39:45.460308 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
13242 13:39:45.460406 arm64_za-ptrace_Set_VL_1312 pass
13243 13:39:45.460700 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
13244 13:39:45.460888 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
13245 13:39:45.461055 arm64_za-ptrace_Set_VL_1328 pass
13246 13:39:45.461214 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
13247 13:39:45.461423 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
13248 13:39:45.461578 arm64_za-ptrace_Set_VL_1344 pass
13249 13:39:45.461772 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
13250 13:39:45.461921 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
13251 13:39:45.462078 arm64_za-ptrace_Set_VL_1360 pass
13252 13:39:45.462237 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
13253 13:39:45.462393 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
13254 13:39:45.462560 arm64_za-ptrace_Set_VL_1376 pass
13255 13:39:45.462693 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
13256 13:39:45.462819 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
13257 13:39:45.462944 arm64_za-ptrace_Set_VL_1392 pass
13258 13:39:45.463077 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
13259 13:39:45.463210 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
13260 13:39:45.463332 arm64_za-ptrace_Set_VL_1408 pass
13261 13:39:45.463448 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
13262 13:39:45.463576 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
13263 13:39:45.463721 arm64_za-ptrace_Set_VL_1424 pass
13264 13:39:45.463841 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
13265 13:39:45.464006 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
13266 13:39:45.464186 arm64_za-ptrace_Set_VL_1440 pass
13267 13:39:45.464357 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
13268 13:39:45.464486 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
13269 13:39:45.464622 arm64_za-ptrace_Set_VL_1456 pass
13270 13:39:45.464751 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
13271 13:39:45.464869 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
13272 13:39:45.464985 arm64_za-ptrace_Set_VL_1472 pass
13273 13:39:45.465100 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
13274 13:39:45.465216 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
13275 13:39:45.465331 arm64_za-ptrace_Set_VL_1488 pass
13276 13:39:45.465448 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
13277 13:39:45.465564 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
13278 13:39:45.465694 arm64_za-ptrace_Set_VL_1504 pass
13279 13:39:45.465812 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
13280 13:39:45.465958 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
13281 13:39:45.466082 arm64_za-ptrace_Set_VL_1520 pass
13282 13:39:45.466200 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
13283 13:39:45.466317 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
13284 13:39:45.468593 arm64_za-ptrace_Set_VL_1536 pass
13285 13:39:45.469016 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
13286 13:39:45.487733 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
13287 13:39:45.487955 arm64_za-ptrace_Set_VL_1552 pass
13288 13:39:45.488250 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
13289 13:39:45.488347 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
13290 13:39:45.488434 arm64_za-ptrace_Set_VL_1568 pass
13291 13:39:45.488534 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
13292 13:39:45.488621 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
13293 13:39:45.488721 arm64_za-ptrace_Set_VL_1584 pass
13294 13:39:45.488823 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
13295 13:39:45.488911 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
13296 13:39:45.489010 arm64_za-ptrace_Set_VL_1600 pass
13297 13:39:45.489119 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
13298 13:39:45.489221 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
13299 13:39:45.489323 arm64_za-ptrace_Set_VL_1616 pass
13300 13:39:45.489610 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
13301 13:39:45.489728 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13302 13:39:45.489815 arm64_za-ptrace_Set_VL_1632 pass
13303 13:39:45.489915 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13304 13:39:45.490000 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13305 13:39:45.490100 arm64_za-ptrace_Set_VL_1648 pass
13306 13:39:45.490186 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13307 13:39:45.490285 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13308 13:39:45.490385 arm64_za-ptrace_Set_VL_1664 pass
13309 13:39:45.490661 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13310 13:39:45.490752 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13311 13:39:45.490858 arm64_za-ptrace_Set_VL_1680 pass
13312 13:39:45.490944 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13313 13:39:45.491043 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13314 13:39:45.491130 arm64_za-ptrace_Set_VL_1696 pass
13315 13:39:45.491229 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13316 13:39:45.491330 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13317 13:39:45.491615 arm64_za-ptrace_Set_VL_1712 pass
13318 13:39:45.491707 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13319 13:39:45.491810 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13320 13:39:45.491896 arm64_za-ptrace_Set_VL_1728 pass
13321 13:39:45.491994 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13322 13:39:45.492096 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13323 13:39:45.496396 arm64_za-ptrace_Set_VL_1744 pass
13324 13:39:45.496779 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13325 13:39:45.496926 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13326 13:39:45.497075 arm64_za-ptrace_Set_VL_1760 pass
13327 13:39:45.497230 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13328 13:39:45.497359 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13329 13:39:45.497542 arm64_za-ptrace_Set_VL_1776 pass
13330 13:39:45.497665 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13331 13:39:45.497778 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13332 13:39:45.497888 arm64_za-ptrace_Set_VL_1792 pass
13333 13:39:45.497996 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13334 13:39:45.498131 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13335 13:39:45.498234 arm64_za-ptrace_Set_VL_1808 pass
13336 13:39:45.498357 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13337 13:39:45.498502 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13338 13:39:45.498634 arm64_za-ptrace_Set_VL_1824 pass
13339 13:39:45.498777 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13340 13:39:45.498899 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13341 13:39:45.499032 arm64_za-ptrace_Set_VL_1840 pass
13342 13:39:45.499140 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13343 13:39:45.499250 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13344 13:39:45.499356 arm64_za-ptrace_Set_VL_1856 pass
13345 13:39:45.499463 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13346 13:39:45.499599 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13347 13:39:45.499704 arm64_za-ptrace_Set_VL_1872 pass
13348 13:39:45.499816 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13349 13:39:45.499924 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13350 13:39:45.500056 arm64_za-ptrace_Set_VL_1888 pass
13351 13:39:45.500186 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13352 13:39:45.500297 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13353 13:39:45.500404 arm64_za-ptrace_Set_VL_1904 pass
13354 13:39:45.500509 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13355 13:39:45.500644 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13356 13:39:45.500750 arm64_za-ptrace_Set_VL_1920 pass
13357 13:39:45.500858 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13358 13:39:45.500966 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13359 13:39:45.501072 arm64_za-ptrace_Set_VL_1936 pass
13360 13:39:45.501179 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13361 13:39:45.504339 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13362 13:39:45.504644 arm64_za-ptrace_Set_VL_1952 pass
13363 13:39:45.504748 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13364 13:39:45.504884 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13365 13:39:45.504989 arm64_za-ptrace_Set_VL_1968 pass
13366 13:39:45.505098 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13367 13:39:45.505207 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13368 13:39:45.505315 arm64_za-ptrace_Set_VL_1984 pass
13369 13:39:45.505449 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13370 13:39:45.505551 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13371 13:39:45.505668 arm64_za-ptrace_Set_VL_2000 pass
13372 13:39:45.505778 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13373 13:39:45.505891 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13374 13:39:45.506000 arm64_za-ptrace_Set_VL_2016 pass
13375 13:39:45.506135 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13376 13:39:45.506239 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13377 13:39:45.506347 arm64_za-ptrace_Set_VL_2032 pass
13378 13:39:45.506456 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13379 13:39:45.506564 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13380 13:39:45.506672 arm64_za-ptrace_Set_VL_2048 pass
13381 13:39:45.506780 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13382 13:39:45.506889 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13383 13:39:45.507023 arm64_za-ptrace_Set_VL_2064 pass
13384 13:39:45.507126 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13385 13:39:45.507234 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13386 13:39:45.507341 arm64_za-ptrace_Set_VL_2080 pass
13387 13:39:45.507449 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13388 13:39:45.507557 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13389 13:39:45.507665 arm64_za-ptrace_Set_VL_2096 pass
13390 13:39:45.507830 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13391 13:39:45.507959 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13392 13:39:45.508070 arm64_za-ptrace_Set_VL_2112 pass
13393 13:39:45.508200 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13394 13:39:45.508361 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13395 13:39:45.508468 arm64_za-ptrace_Set_VL_2128 pass
13396 13:39:45.508577 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13397 13:39:45.508685 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13398 13:39:45.512377 arm64_za-ptrace_Set_VL_2144 pass
13399 13:39:45.512814 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13400 13:39:45.512922 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13401 13:39:45.513020 arm64_za-ptrace_Set_VL_2160 pass
13402 13:39:45.513137 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13403 13:39:45.513235 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13404 13:39:45.513319 arm64_za-ptrace_Set_VL_2176 pass
13405 13:39:45.513417 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13406 13:39:45.513501 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13407 13:39:45.513577 arm64_za-ptrace_Set_VL_2192 pass
13408 13:39:45.513670 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13409 13:39:45.513765 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13410 13:39:45.513865 arm64_za-ptrace_Set_VL_2208 pass
13411 13:39:45.513959 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13412 13:39:45.514323 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13413 13:39:45.514433 arm64_za-ptrace_Set_VL_2224 pass
13414 13:39:45.514518 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13415 13:39:45.514623 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13416 13:39:45.514717 arm64_za-ptrace_Set_VL_2240 pass
13417 13:39:45.514815 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13418 13:39:45.514906 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13419 13:39:45.514984 arm64_za-ptrace_Set_VL_2256 pass
13420 13:39:45.515080 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13421 13:39:45.515185 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13422 13:39:45.515273 arm64_za-ptrace_Set_VL_2272 pass
13423 13:39:45.515590 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13424 13:39:45.515704 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13425 13:39:45.515790 arm64_za-ptrace_Set_VL_2288 pass
13426 13:39:45.515887 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13427 13:39:45.515977 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13428 13:39:45.520367 arm64_za-ptrace_Set_VL_2304 pass
13429 13:39:45.520699 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13430 13:39:45.520794 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13431 13:39:45.520868 arm64_za-ptrace_Set_VL_2320 pass
13432 13:39:45.520951 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13433 13:39:45.521065 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13434 13:39:45.521145 arm64_za-ptrace_Set_VL_2336 pass
13435 13:39:45.521252 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13436 13:39:45.521353 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13437 13:39:45.521620 arm64_za-ptrace_Set_VL_2352 pass
13438 13:39:45.521702 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13439 13:39:45.521779 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13440 13:39:45.521864 arm64_za-ptrace_Set_VL_2368 pass
13441 13:39:45.522120 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13442 13:39:45.522190 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13443 13:39:45.522267 arm64_za-ptrace_Set_VL_2384 pass
13444 13:39:45.522519 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13445 13:39:45.522599 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13446 13:39:45.522675 arm64_za-ptrace_Set_VL_2400 pass
13447 13:39:45.522927 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13448 13:39:45.523008 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13449 13:39:45.523075 arm64_za-ptrace_Set_VL_2416 pass
13450 13:39:45.523149 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13451 13:39:45.523399 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13452 13:39:45.523469 arm64_za-ptrace_Set_VL_2432 pass
13453 13:39:45.523544 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13454 13:39:45.523624 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13455 13:39:45.523876 arm64_za-ptrace_Set_VL_2448 pass
13456 13:39:45.523944 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13457 13:39:45.524042 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13458 13:39:45.524150 arm64_za-ptrace_Set_VL_2464 pass
13459 13:39:45.528609 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13460 13:39:45.528821 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13461 13:39:45.529119 arm64_za-ptrace_Set_VL_2480 pass
13462 13:39:45.529313 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13463 13:39:45.529483 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13464 13:39:45.529737 arm64_za-ptrace_Set_VL_2496 pass
13465 13:39:45.529973 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13466 13:39:45.530174 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13467 13:39:45.530372 arm64_za-ptrace_Set_VL_2512 pass
13468 13:39:45.530540 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13469 13:39:45.530706 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13470 13:39:45.530852 arm64_za-ptrace_Set_VL_2528 pass
13471 13:39:45.531002 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13472 13:39:45.531127 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13473 13:39:45.531244 arm64_za-ptrace_Set_VL_2544 pass
13474 13:39:45.531359 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13475 13:39:45.531484 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13476 13:39:45.531634 arm64_za-ptrace_Set_VL_2560 pass
13477 13:39:45.531768 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13478 13:39:45.531912 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13479 13:39:45.555770 arm64_za-ptrace_Set_VL_2576 pass
13480 13:39:45.556066 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13481 13:39:45.556466 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13482 13:39:45.556587 arm64_za-ptrace_Set_VL_2592 pass
13483 13:39:45.556685 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13484 13:39:45.556795 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13485 13:39:45.556895 arm64_za-ptrace_Set_VL_2608 pass
13486 13:39:45.556988 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13487 13:39:45.557081 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13488 13:39:45.557191 arm64_za-ptrace_Set_VL_2624 pass
13489 13:39:45.557302 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13490 13:39:45.557396 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13491 13:39:45.557489 arm64_za-ptrace_Set_VL_2640 pass
13492 13:39:45.557598 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13493 13:39:45.557698 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13494 13:39:45.557790 arm64_za-ptrace_Set_VL_2656 pass
13495 13:39:45.557900 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13496 13:39:45.558010 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13497 13:39:45.558113 arm64_za-ptrace_Set_VL_2672 pass
13498 13:39:45.558221 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13499 13:39:45.558330 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13500 13:39:45.558420 arm64_za-ptrace_Set_VL_2688 pass
13501 13:39:45.558520 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13502 13:39:45.558626 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13503 13:39:45.559095 arm64_za-ptrace_Set_VL_2704 pass
13504 13:39:45.559204 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13505 13:39:45.559296 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13506 13:39:45.559383 arm64_za-ptrace_Set_VL_2720 pass
13507 13:39:45.559486 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13508 13:39:45.559577 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13509 13:39:45.559665 arm64_za-ptrace_Set_VL_2736 pass
13510 13:39:45.559767 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13511 13:39:45.559877 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13512 13:39:45.559969 arm64_za-ptrace_Set_VL_2752 pass
13513 13:39:45.560074 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13514 13:39:45.560168 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13515 13:39:45.560272 arm64_za-ptrace_Set_VL_2768 pass
13516 13:39:45.560375 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13517 13:39:45.560468 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13518 13:39:45.560576 arm64_za-ptrace_Set_VL_2784 pass
13519 13:39:45.560897 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13520 13:39:45.561055 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13521 13:39:45.564387 arm64_za-ptrace_Set_VL_2800 pass
13522 13:39:45.564852 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13523 13:39:45.564972 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13524 13:39:45.565065 arm64_za-ptrace_Set_VL_2816 pass
13525 13:39:45.565151 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13526 13:39:45.565251 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13527 13:39:45.565344 arm64_za-ptrace_Set_VL_2832 pass
13528 13:39:45.565428 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13529 13:39:45.565529 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13530 13:39:45.565618 arm64_za-ptrace_Set_VL_2848 pass
13531 13:39:45.565727 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13532 13:39:45.565831 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13533 13:39:45.565921 arm64_za-ptrace_Set_VL_2864 pass
13534 13:39:45.566022 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13535 13:39:45.566124 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13536 13:39:45.566225 arm64_za-ptrace_Set_VL_2880 pass
13537 13:39:45.566335 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13538 13:39:45.566437 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13539 13:39:45.566856 arm64_za-ptrace_Set_VL_2896 pass
13540 13:39:45.566961 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13541 13:39:45.567070 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13542 13:39:45.567159 arm64_za-ptrace_Set_VL_2912 pass
13543 13:39:45.567259 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13544 13:39:45.567365 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13545 13:39:45.567712 arm64_za-ptrace_Set_VL_2928 pass
13546 13:39:45.567821 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13547 13:39:45.567909 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13548 13:39:45.568015 arm64_za-ptrace_Set_VL_2944 pass
13549 13:39:45.568101 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13550 13:39:45.568192 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13551 13:39:45.572355 arm64_za-ptrace_Set_VL_2960 pass
13552 13:39:45.572697 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13553 13:39:45.572806 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13554 13:39:45.572894 arm64_za-ptrace_Set_VL_2976 pass
13555 13:39:45.573000 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13556 13:39:45.573092 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13557 13:39:45.573198 arm64_za-ptrace_Set_VL_2992 pass
13558 13:39:45.573287 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13559 13:39:45.573393 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13560 13:39:45.573483 arm64_za-ptrace_Set_VL_3008 pass
13561 13:39:45.573587 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13562 13:39:45.573699 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13563 13:39:45.573806 arm64_za-ptrace_Set_VL_3024 pass
13564 13:39:45.573908 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13565 13:39:45.574233 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13566 13:39:45.574342 arm64_za-ptrace_Set_VL_3040 pass
13567 13:39:45.574445 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13568 13:39:45.574551 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13569 13:39:45.574652 arm64_za-ptrace_Set_VL_3056 pass
13570 13:39:45.574756 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13571 13:39:45.574858 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13572 13:39:45.575176 arm64_za-ptrace_Set_VL_3072 pass
13573 13:39:45.575410 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13574 13:39:45.575620 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13575 13:39:45.575804 arm64_za-ptrace_Set_VL_3088 pass
13576 13:39:45.576061 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13577 13:39:45.576233 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13578 13:39:45.576359 arm64_za-ptrace_Set_VL_3104 pass
13579 13:39:45.576479 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13580 13:39:45.576621 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13581 13:39:45.576746 arm64_za-ptrace_Set_VL_3120 pass
13582 13:39:45.580742 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13583 13:39:45.580965 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13584 13:39:45.581182 arm64_za-ptrace_Set_VL_3136 pass
13585 13:39:45.581377 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13586 13:39:45.581631 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13587 13:39:45.581863 arm64_za-ptrace_Set_VL_3152 pass
13588 13:39:45.582069 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13589 13:39:45.582250 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13590 13:39:45.582420 arm64_za-ptrace_Set_VL_3168 pass
13591 13:39:45.582579 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13592 13:39:45.582740 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13593 13:39:45.582896 arm64_za-ptrace_Set_VL_3184 pass
13594 13:39:45.583114 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13595 13:39:45.583310 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13596 13:39:45.583490 arm64_za-ptrace_Set_VL_3200 pass
13597 13:39:45.583649 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13598 13:39:45.583795 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13599 13:39:45.583946 arm64_za-ptrace_Set_VL_3216 pass
13600 13:39:45.584104 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13601 13:39:45.584226 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13602 13:39:45.584342 arm64_za-ptrace_Set_VL_3232 pass
13603 13:39:45.584458 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13604 13:39:45.584572 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13605 13:39:45.584686 arm64_za-ptrace_Set_VL_3248 pass
13606 13:39:45.584829 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13607 13:39:45.584951 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13608 13:39:45.585068 arm64_za-ptrace_Set_VL_3264 pass
13609 13:39:45.585184 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13610 13:39:45.585299 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13611 13:39:45.585414 arm64_za-ptrace_Set_VL_3280 pass
13612 13:39:45.585529 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13613 13:39:45.585643 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13614 13:39:45.588536 arm64_za-ptrace_Set_VL_3296 pass
13615 13:39:45.588732 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13616 13:39:45.588926 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13617 13:39:45.589340 arm64_za-ptrace_Set_VL_3312 pass
13618 13:39:45.589515 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13619 13:39:45.589677 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13620 13:39:45.589881 arm64_za-ptrace_Set_VL_3328 pass
13621 13:39:45.590043 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13622 13:39:45.590187 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13623 13:39:45.590368 arm64_za-ptrace_Set_VL_3344 pass
13624 13:39:45.590635 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13625 13:39:45.590846 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13626 13:39:45.591048 arm64_za-ptrace_Set_VL_3360 pass
13627 13:39:45.591210 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13628 13:39:45.591367 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13629 13:39:45.591495 arm64_za-ptrace_Set_VL_3376 pass
13630 13:39:45.591611 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13631 13:39:45.591749 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13632 13:39:45.591909 arm64_za-ptrace_Set_VL_3392 pass
13633 13:39:45.592062 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13634 13:39:45.592216 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13635 13:39:45.592339 arm64_za-ptrace_Set_VL_3408 pass
13636 13:39:45.592456 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13637 13:39:45.592571 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13638 13:39:45.592686 arm64_za-ptrace_Set_VL_3424 pass
13639 13:39:45.592801 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13640 13:39:45.592914 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13641 13:39:45.593029 arm64_za-ptrace_Set_VL_3440 pass
13642 13:39:45.593142 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13643 13:39:45.593257 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13644 13:39:45.593371 arm64_za-ptrace_Set_VL_3456 pass
13645 13:39:45.593497 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13646 13:39:45.594099 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13647 13:39:45.594257 arm64_za-ptrace_Set_VL_3472 pass
13648 13:39:45.594379 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13649 13:39:45.594499 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13650 13:39:45.596312 arm64_za-ptrace_Set_VL_3488 pass
13651 13:39:45.596641 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13652 13:39:45.596753 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13653 13:39:45.596876 arm64_za-ptrace_Set_VL_3504 pass
13654 13:39:45.596994 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13655 13:39:45.597083 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13656 13:39:45.597167 arm64_za-ptrace_Set_VL_3520 pass
13657 13:39:45.597264 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13658 13:39:45.597402 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13659 13:39:45.597755 arm64_za-ptrace_Set_VL_3536 pass
13660 13:39:45.597988 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13661 13:39:45.598216 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13662 13:39:45.598501 arm64_za-ptrace_Set_VL_3552 pass
13663 13:39:45.598742 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13664 13:39:45.598916 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13665 13:39:45.599046 arm64_za-ptrace_Set_VL_3568 pass
13666 13:39:45.599204 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13667 13:39:45.599385 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13668 13:39:45.599516 arm64_za-ptrace_Set_VL_3584 pass
13669 13:39:45.599632 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13670 13:39:45.599744 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13671 13:39:45.617598 arm64_za-ptrace_Set_VL_3600 pass
13672 13:39:45.617869 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13673 13:39:45.618064 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13674 13:39:45.618464 arm64_za-ptrace_Set_VL_3616 pass
13675 13:39:45.618647 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13676 13:39:45.618780 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13677 13:39:45.618899 arm64_za-ptrace_Set_VL_3632 pass
13678 13:39:45.619018 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13679 13:39:45.619132 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13680 13:39:45.619248 arm64_za-ptrace_Set_VL_3648 pass
13681 13:39:45.619362 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13682 13:39:45.619492 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13683 13:39:45.619613 arm64_za-ptrace_Set_VL_3664 pass
13684 13:39:45.619767 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13685 13:39:45.619935 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13686 13:39:45.620097 arm64_za-ptrace_Set_VL_3680 pass
13687 13:39:45.620247 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13688 13:39:45.620366 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13689 13:39:45.620484 arm64_za-ptrace_Set_VL_3696 pass
13690 13:39:45.620600 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13691 13:39:45.620714 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13692 13:39:45.620829 arm64_za-ptrace_Set_VL_3712 pass
13693 13:39:45.620944 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13694 13:39:45.621092 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13695 13:39:45.621214 arm64_za-ptrace_Set_VL_3728 pass
13696 13:39:45.621331 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13697 13:39:45.621448 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13698 13:39:45.621563 arm64_za-ptrace_Set_VL_3744 pass
13699 13:39:45.621692 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13700 13:39:45.621807 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13701 13:39:45.621921 arm64_za-ptrace_Set_VL_3760 pass
13702 13:39:45.622035 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13703 13:39:45.622147 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13704 13:39:45.622259 arm64_za-ptrace_Set_VL_3776 pass
13705 13:39:45.624412 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13706 13:39:45.624517 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13707 13:39:45.624607 arm64_za-ptrace_Set_VL_3792 pass
13708 13:39:45.624882 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13709 13:39:45.624973 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13710 13:39:45.625063 arm64_za-ptrace_Set_VL_3808 pass
13711 13:39:45.625164 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13712 13:39:45.625251 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13713 13:39:45.625336 arm64_za-ptrace_Set_VL_3824 pass
13714 13:39:45.625419 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13715 13:39:45.625517 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13716 13:39:45.625619 arm64_za-ptrace_Set_VL_3840 pass
13717 13:39:45.625766 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13718 13:39:45.625869 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13719 13:39:45.625970 arm64_za-ptrace_Set_VL_3856 pass
13720 13:39:45.626060 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13721 13:39:45.626157 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13722 13:39:45.626256 arm64_za-ptrace_Set_VL_3872 pass
13723 13:39:45.628203 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13724 13:39:45.628305 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13725 13:39:45.628398 arm64_za-ptrace_Set_VL_3888 pass
13726 13:39:45.628502 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13727 13:39:45.628593 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13728 13:39:45.628684 arm64_za-ptrace_Set_VL_3904 pass
13729 13:39:45.628773 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13730 13:39:45.628864 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13731 13:39:45.628956 arm64_za-ptrace_Set_VL_3920 pass
13732 13:39:45.629053 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13733 13:39:45.629143 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13734 13:39:45.629235 arm64_za-ptrace_Set_VL_3936 pass
13735 13:39:45.629325 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13736 13:39:45.629416 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13737 13:39:45.629507 arm64_za-ptrace_Set_VL_3952 pass
13738 13:39:45.629596 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13739 13:39:45.629694 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13740 13:39:45.629786 arm64_za-ptrace_Set_VL_3968 pass
13741 13:39:45.629877 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13742 13:39:45.629967 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13743 13:39:45.630062 arm64_za-ptrace_Set_VL_3984 pass
13744 13:39:45.630151 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13745 13:39:45.632291 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13746 13:39:45.632591 arm64_za-ptrace_Set_VL_4000 pass
13747 13:39:45.632714 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13748 13:39:45.632805 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13749 13:39:45.632905 arm64_za-ptrace_Set_VL_4016 pass
13750 13:39:45.632991 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13751 13:39:45.633097 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13752 13:39:45.633182 arm64_za-ptrace_Set_VL_4032 pass
13753 13:39:45.633280 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13754 13:39:45.633380 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13755 13:39:45.633479 arm64_za-ptrace_Set_VL_4048 pass
13756 13:39:45.633767 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13757 13:39:45.634184 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13758 13:39:45.634276 arm64_za-ptrace_Set_VL_4064 pass
13759 13:39:45.634360 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13760 13:39:45.634445 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13761 13:39:45.634529 arm64_za-ptrace_Set_VL_4080 pass
13762 13:39:45.634612 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13763 13:39:45.634888 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13764 13:39:45.634978 arm64_za-ptrace_Set_VL_4096 pass
13765 13:39:45.635066 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13766 13:39:45.635150 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13767 13:39:45.635426 arm64_za-ptrace_Set_VL_4112 pass
13768 13:39:45.635515 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13769 13:39:45.635600 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13770 13:39:45.635685 arm64_za-ptrace_Set_VL_4128 pass
13771 13:39:45.635767 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13772 13:39:45.635851 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13773 13:39:45.635935 arm64_za-ptrace_Set_VL_4144 pass
13774 13:39:45.636037 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13775 13:39:45.636128 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13776 13:39:45.636217 arm64_za-ptrace_Set_VL_4160 pass
13777 13:39:45.636305 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13778 13:39:45.636394 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13779 13:39:45.640272 arm64_za-ptrace_Set_VL_4176 pass
13780 13:39:45.640613 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13781 13:39:45.640725 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13782 13:39:45.640826 arm64_za-ptrace_Set_VL_4192 pass
13783 13:39:45.640947 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13784 13:39:45.641047 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13785 13:39:45.641116 arm64_za-ptrace_Set_VL_4208 pass
13786 13:39:45.641203 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13787 13:39:45.641289 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13788 13:39:45.641383 arm64_za-ptrace_Set_VL_4224 pass
13789 13:39:45.641469 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13790 13:39:45.641588 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13791 13:39:45.641711 arm64_za-ptrace_Set_VL_4240 pass
13792 13:39:45.642002 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13793 13:39:45.642121 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13794 13:39:45.642229 arm64_za-ptrace_Set_VL_4256 pass
13795 13:39:45.642346 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13796 13:39:45.642471 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13797 13:39:45.642579 arm64_za-ptrace_Set_VL_4272 pass
13798 13:39:45.642681 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13799 13:39:45.642812 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13800 13:39:45.642921 arm64_za-ptrace_Set_VL_4288 pass
13801 13:39:45.643031 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13802 13:39:45.643141 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13803 13:39:45.643274 arm64_za-ptrace_Set_VL_4304 pass
13804 13:39:45.643368 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13805 13:39:45.643477 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13806 13:39:45.643582 arm64_za-ptrace_Set_VL_4320 pass
13807 13:39:45.643684 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13808 13:39:45.643806 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13809 13:39:45.643910 arm64_za-ptrace_Set_VL_4336 pass
13810 13:39:45.644021 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13811 13:39:45.644113 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13812 13:39:45.644192 arm64_za-ptrace_Set_VL_4352 pass
13813 13:39:45.644256 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13814 13:39:45.648305 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13815 13:39:45.648760 arm64_za-ptrace_Set_VL_4368 pass
13816 13:39:45.648919 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13817 13:39:45.649049 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13818 13:39:45.649203 arm64_za-ptrace_Set_VL_4384 pass
13819 13:39:45.649326 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13820 13:39:45.649449 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13821 13:39:45.649574 arm64_za-ptrace_Set_VL_4400 pass
13822 13:39:45.649727 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13823 13:39:45.649857 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13824 13:39:45.649984 arm64_za-ptrace_Set_VL_4416 pass
13825 13:39:45.650131 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13826 13:39:45.650262 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13827 13:39:45.650400 arm64_za-ptrace_Set_VL_4432 pass
13828 13:39:45.650547 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13829 13:39:45.650665 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13830 13:39:45.650782 arm64_za-ptrace_Set_VL_4448 pass
13831 13:39:45.650897 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13832 13:39:45.651015 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13833 13:39:45.651162 arm64_za-ptrace_Set_VL_4464 pass
13834 13:39:45.651316 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13835 13:39:45.651482 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13836 13:39:45.651639 arm64_za-ptrace_Set_VL_4480 pass
13837 13:39:45.651792 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13838 13:39:45.651985 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13839 13:39:45.652177 arm64_za-ptrace_Set_VL_4496 pass
13840 13:39:45.652314 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13841 13:39:45.652431 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13842 13:39:45.652547 arm64_za-ptrace_Set_VL_4512 pass
13843 13:39:45.652663 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13844 13:39:45.652776 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13845 13:39:45.652893 arm64_za-ptrace_Set_VL_4528 pass
13846 13:39:45.653037 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13847 13:39:45.653156 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13848 13:39:45.653270 arm64_za-ptrace_Set_VL_4544 pass
13849 13:39:45.653384 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13850 13:39:45.653501 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13851 13:39:45.653616 arm64_za-ptrace_Set_VL_4560 pass
13852 13:39:45.653776 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13853 13:39:45.653900 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13854 13:39:45.654018 arm64_za-ptrace_Set_VL_4576 pass
13855 13:39:45.654137 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13856 13:39:45.654252 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13857 13:39:45.654367 arm64_za-ptrace_Set_VL_4592 pass
13858 13:39:45.654482 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13859 13:39:45.656330 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13860 13:39:45.656771 arm64_za-ptrace_Set_VL_4608 pass
13861 13:39:45.657054 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13862 13:39:45.657229 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13863 13:39:45.657408 arm64_za-ptrace_Set_VL_4624 pass
13864 13:39:45.674448 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13865 13:39:45.674556 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13866 13:39:45.674680 arm64_za-ptrace_Set_VL_4640 pass
13867 13:39:45.674795 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13868 13:39:45.674905 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13869 13:39:45.674995 arm64_za-ptrace_Set_VL_4656 pass
13870 13:39:45.675089 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13871 13:39:45.675190 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13872 13:39:45.675302 arm64_za-ptrace_Set_VL_4672 pass
13873 13:39:45.675418 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13874 13:39:45.675525 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13875 13:39:45.675599 arm64_za-ptrace_Set_VL_4688 pass
13876 13:39:45.675689 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13877 13:39:45.675982 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13878 13:39:45.676077 arm64_za-ptrace_Set_VL_4704 pass
13879 13:39:45.676155 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13880 13:39:45.676275 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13881 13:39:45.676622 arm64_za-ptrace_Set_VL_4720 pass
13882 13:39:45.676831 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13883 13:39:45.677037 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13884 13:39:45.677212 arm64_za-ptrace_Set_VL_4736 pass
13885 13:39:45.677380 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13886 13:39:45.677573 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13887 13:39:45.677761 arm64_za-ptrace_Set_VL_4752 pass
13888 13:39:45.677934 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13889 13:39:45.678179 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13890 13:39:45.678401 arm64_za-ptrace_Set_VL_4768 pass
13891 13:39:45.678630 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13892 13:39:45.678816 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13893 13:39:45.678981 arm64_za-ptrace_Set_VL_4784 pass
13894 13:39:45.679152 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13895 13:39:45.679319 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13896 13:39:45.679489 arm64_za-ptrace_Set_VL_4800 pass
13897 13:39:45.679656 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13898 13:39:45.679826 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13899 13:39:45.680016 arm64_za-ptrace_Set_VL_4816 pass
13900 13:39:45.680234 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13901 13:39:45.680368 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13902 13:39:45.680485 arm64_za-ptrace_Set_VL_4832 pass
13903 13:39:45.680599 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13904 13:39:45.680713 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13905 13:39:45.680827 arm64_za-ptrace_Set_VL_4848 pass
13906 13:39:45.680941 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13907 13:39:45.681054 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13908 13:39:45.681210 arm64_za-ptrace_Set_VL_4864 pass
13909 13:39:45.681339 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13910 13:39:45.681455 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13911 13:39:45.684303 arm64_za-ptrace_Set_VL_4880 pass
13912 13:39:45.684719 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13913 13:39:45.684845 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13914 13:39:45.684938 arm64_za-ptrace_Set_VL_4896 pass
13915 13:39:45.685017 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13916 13:39:45.685107 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13917 13:39:45.685173 arm64_za-ptrace_Set_VL_4912 pass
13918 13:39:45.685235 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13919 13:39:45.685310 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13920 13:39:45.685386 arm64_za-ptrace_Set_VL_4928 pass
13921 13:39:45.685631 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13922 13:39:45.685708 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13923 13:39:45.685783 arm64_za-ptrace_Set_VL_4944 pass
13924 13:39:45.685848 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13925 13:39:45.686099 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13926 13:39:45.686172 arm64_za-ptrace_Set_VL_4960 pass
13927 13:39:45.686245 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13928 13:39:45.686310 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13929 13:39:45.686383 arm64_za-ptrace_Set_VL_4976 pass
13930 13:39:45.686459 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13931 13:39:45.686711 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13932 13:39:45.686789 arm64_za-ptrace_Set_VL_4992 pass
13933 13:39:45.687038 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13934 13:39:45.687106 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13935 13:39:45.687182 arm64_za-ptrace_Set_VL_5008 pass
13936 13:39:45.687256 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13937 13:39:45.687505 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13938 13:39:45.687583 arm64_za-ptrace_Set_VL_5024 pass
13939 13:39:45.687833 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
13940 13:39:45.687899 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
13941 13:39:45.688142 arm64_za-ptrace_Set_VL_5040 pass
13942 13:39:45.688208 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
13943 13:39:45.692266 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
13944 13:39:45.692534 arm64_za-ptrace_Set_VL_5056 pass
13945 13:39:45.692615 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
13946 13:39:45.692705 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
13947 13:39:45.692829 arm64_za-ptrace_Set_VL_5072 pass
13948 13:39:45.692947 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
13949 13:39:45.693032 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
13950 13:39:45.693126 arm64_za-ptrace_Set_VL_5088 pass
13951 13:39:45.693195 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
13952 13:39:45.693271 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
13953 13:39:45.693553 arm64_za-ptrace_Set_VL_5104 pass
13954 13:39:45.693626 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
13955 13:39:45.693879 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
13956 13:39:45.693951 arm64_za-ptrace_Set_VL_5120 pass
13957 13:39:45.694016 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
13958 13:39:45.694095 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
13959 13:39:45.694163 arm64_za-ptrace_Set_VL_5136 pass
13960 13:39:45.694239 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
13961 13:39:45.694492 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
13962 13:39:45.694561 arm64_za-ptrace_Set_VL_5152 pass
13963 13:39:45.694637 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
13964 13:39:45.694720 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
13965 13:39:45.694815 arm64_za-ptrace_Set_VL_5168 pass
13966 13:39:45.694902 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
13967 13:39:45.694998 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
13968 13:39:45.695086 arm64_za-ptrace_Set_VL_5184 pass
13969 13:39:45.695367 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
13970 13:39:45.695454 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
13971 13:39:45.695542 arm64_za-ptrace_Set_VL_5200 pass
13972 13:39:45.695615 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
13973 13:39:45.695700 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
13974 13:39:45.695793 arm64_za-ptrace_Set_VL_5216 pass
13975 13:39:45.695882 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
13976 13:39:45.696159 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
13977 13:39:45.700262 arm64_za-ptrace_Set_VL_5232 pass
13978 13:39:45.700605 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
13979 13:39:45.700708 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
13980 13:39:45.700811 arm64_za-ptrace_Set_VL_5248 pass
13981 13:39:45.700935 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
13982 13:39:45.701251 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
13983 13:39:45.701390 arm64_za-ptrace_Set_VL_5264 pass
13984 13:39:45.701484 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
13985 13:39:45.701569 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
13986 13:39:45.701660 arm64_za-ptrace_Set_VL_5280 pass
13987 13:39:45.701761 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
13988 13:39:45.701851 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
13989 13:39:45.701935 arm64_za-ptrace_Set_VL_5296 pass
13990 13:39:45.702020 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
13991 13:39:45.702122 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
13992 13:39:45.702212 arm64_za-ptrace_Set_VL_5312 pass
13993 13:39:45.702297 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
13994 13:39:45.702394 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
13995 13:39:45.702479 arm64_za-ptrace_Set_VL_5328 pass
13996 13:39:45.702563 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
13997 13:39:45.702663 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
13998 13:39:45.702749 arm64_za-ptrace_Set_VL_5344 pass
13999 13:39:45.703039 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
14000 13:39:45.703146 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
14001 13:39:45.703232 arm64_za-ptrace_Set_VL_5360 pass
14002 13:39:45.703315 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
14003 13:39:45.703413 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
14004 13:39:45.703498 arm64_za-ptrace_Set_VL_5376 pass
14005 13:39:45.703580 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
14006 13:39:45.703677 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
14007 13:39:45.703762 arm64_za-ptrace_Set_VL_5392 pass
14008 13:39:45.703859 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
14009 13:39:45.703953 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
14010 13:39:45.704039 arm64_za-ptrace_Set_VL_5408 pass
14011 13:39:45.704346 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
14012 13:39:45.708310 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
14013 13:39:45.708711 arm64_za-ptrace_Set_VL_5424 pass
14014 13:39:45.708870 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
14015 13:39:45.708997 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
14016 13:39:45.709116 arm64_za-ptrace_Set_VL_5440 pass
14017 13:39:45.709257 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
14018 13:39:45.709379 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
14019 13:39:45.709497 arm64_za-ptrace_Set_VL_5456 pass
14020 13:39:45.709637 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
14021 13:39:45.709772 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
14022 13:39:45.709888 arm64_za-ptrace_Set_VL_5472 pass
14023 13:39:45.710002 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
14024 13:39:45.710116 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
14025 13:39:45.710254 arm64_za-ptrace_Set_VL_5488 pass
14026 13:39:45.710372 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
14027 13:39:45.710488 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
14028 13:39:45.710602 arm64_za-ptrace_Set_VL_5504 pass
14029 13:39:45.710716 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
14030 13:39:45.710829 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
14031 13:39:45.710967 arm64_za-ptrace_Set_VL_5520 pass
14032 13:39:45.711084 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
14033 13:39:45.711198 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
14034 13:39:45.711312 arm64_za-ptrace_Set_VL_5536 pass
14035 13:39:45.711425 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
14036 13:39:45.711560 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
14037 13:39:45.711678 arm64_za-ptrace_Set_VL_5552 pass
14038 13:39:45.711792 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
14039 13:39:45.711906 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
14040 13:39:45.712018 arm64_za-ptrace_Set_VL_5568 pass
14041 13:39:45.712155 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
14042 13:39:45.712274 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
14043 13:39:45.712388 arm64_za-ptrace_Set_VL_5584 pass
14044 13:39:45.712500 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
14045 13:39:45.716296 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
14046 13:39:45.716762 arm64_za-ptrace_Set_VL_5600 pass
14047 13:39:45.717049 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
14048 13:39:45.717255 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
14049 13:39:45.717440 arm64_za-ptrace_Set_VL_5616 pass
14050 13:39:45.717618 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
14051 13:39:45.717868 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
14052 13:39:45.718051 arm64_za-ptrace_Set_VL_5632 pass
14053 13:39:45.718177 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
14054 13:39:45.718294 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
14055 13:39:45.718409 arm64_za-ptrace_Set_VL_5648 pass
14056 13:39:45.733867 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
14057 13:39:45.734343 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
14058 13:39:45.734507 arm64_za-ptrace_Set_VL_5664 pass
14059 13:39:45.734617 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
14060 13:39:45.734705 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
14061 13:39:45.734791 arm64_za-ptrace_Set_VL_5680 pass
14062 13:39:45.734876 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
14063 13:39:45.734980 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
14064 13:39:45.735067 arm64_za-ptrace_Set_VL_5696 pass
14065 13:39:45.735158 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
14066 13:39:45.735244 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
14067 13:39:45.735330 arm64_za-ptrace_Set_VL_5712 pass
14068 13:39:45.735414 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
14069 13:39:45.735515 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
14070 13:39:45.735602 arm64_za-ptrace_Set_VL_5728 pass
14071 13:39:45.735685 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
14072 13:39:45.735767 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
14073 13:39:45.735849 arm64_za-ptrace_Set_VL_5744 pass
14074 13:39:45.735949 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
14075 13:39:45.736031 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
14076 13:39:45.736113 arm64_za-ptrace_Set_VL_5760 pass
14077 13:39:45.736196 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
14078 13:39:45.736293 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
14079 13:39:45.736380 arm64_za-ptrace_Set_VL_5776 pass
14080 13:39:45.736840 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
14081 13:39:45.736944 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
14082 13:39:45.737042 arm64_za-ptrace_Set_VL_5792 pass
14083 13:39:45.737123 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
14084 13:39:45.737226 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
14085 13:39:45.737313 arm64_za-ptrace_Set_VL_5808 pass
14086 13:39:45.737409 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
14087 13:39:45.737733 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
14088 13:39:45.737907 arm64_za-ptrace_Set_VL_5824 pass
14089 13:39:45.738118 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
14090 13:39:45.738262 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
14091 13:39:45.738406 arm64_za-ptrace_Set_VL_5840 pass
14092 13:39:45.738549 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
14093 13:39:45.738724 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
14094 13:39:45.738861 arm64_za-ptrace_Set_VL_5856 pass
14095 13:39:45.739003 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
14096 13:39:45.739145 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
14097 13:39:45.739291 arm64_za-ptrace_Set_VL_5872 pass
14098 13:39:45.739433 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
14099 13:39:45.739614 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
14100 13:39:45.739790 arm64_za-ptrace_Set_VL_5888 pass
14101 13:39:45.739980 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
14102 13:39:45.740127 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
14103 13:39:45.740300 arm64_za-ptrace_Set_VL_5904 pass
14104 13:39:45.740448 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
14105 13:39:45.740600 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
14106 13:39:45.740762 arm64_za-ptrace_Set_VL_5920 pass
14107 13:39:45.740902 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
14108 13:39:45.741069 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
14109 13:39:45.741253 arm64_za-ptrace_Set_VL_5936 pass
14110 13:39:45.741420 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
14111 13:39:45.741576 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
14112 13:39:45.741740 arm64_za-ptrace_Set_VL_5952 pass
14113 13:39:45.741914 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
14114 13:39:45.742060 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
14115 13:39:45.744319 arm64_za-ptrace_Set_VL_5968 pass
14116 13:39:45.744804 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
14117 13:39:45.744964 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
14118 13:39:45.745117 arm64_za-ptrace_Set_VL_5984 pass
14119 13:39:45.745302 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
14120 13:39:45.745466 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
14121 13:39:45.745616 arm64_za-ptrace_Set_VL_6000 pass
14122 13:39:45.745822 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
14123 13:39:45.745982 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
14124 13:39:45.746126 arm64_za-ptrace_Set_VL_6016 pass
14125 13:39:45.746263 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
14126 13:39:45.746385 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
14127 13:39:45.746509 arm64_za-ptrace_Set_VL_6032 pass
14128 13:39:45.746630 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
14129 13:39:45.746757 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
14130 13:39:45.746919 arm64_za-ptrace_Set_VL_6048 pass
14131 13:39:45.747083 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
14132 13:39:45.747254 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
14133 13:39:45.747433 arm64_za-ptrace_Set_VL_6064 pass
14134 13:39:45.747608 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
14135 13:39:45.747753 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
14136 13:39:45.747912 arm64_za-ptrace_Set_VL_6080 pass
14137 13:39:45.748070 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
14138 13:39:45.748214 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
14139 13:39:45.748381 arm64_za-ptrace_Set_VL_6096 pass
14140 13:39:45.748527 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
14141 13:39:45.748715 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
14142 13:39:45.748844 arm64_za-ptrace_Set_VL_6112 pass
14143 13:39:45.748968 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
14144 13:39:45.749097 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
14145 13:39:45.749221 arm64_za-ptrace_Set_VL_6128 pass
14146 13:39:45.749379 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
14147 13:39:45.749521 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
14148 13:39:45.749807 arm64_za-ptrace_Set_VL_6144 pass
14149 13:39:45.749984 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
14150 13:39:45.750150 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
14151 13:39:45.750290 arm64_za-ptrace_Set_VL_6160 pass
14152 13:39:45.750412 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
14153 13:39:45.752272 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
14154 13:39:45.752657 arm64_za-ptrace_Set_VL_6176 pass
14155 13:39:45.752821 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
14156 13:39:45.752990 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
14157 13:39:45.753156 arm64_za-ptrace_Set_VL_6192 pass
14158 13:39:45.753317 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
14159 13:39:45.753469 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
14160 13:39:45.753642 arm64_za-ptrace_Set_VL_6208 pass
14161 13:39:45.753836 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
14162 13:39:45.754016 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
14163 13:39:45.754164 arm64_za-ptrace_Set_VL_6224 pass
14164 13:39:45.754325 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
14165 13:39:45.754500 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
14166 13:39:45.754677 arm64_za-ptrace_Set_VL_6240 pass
14167 13:39:45.754827 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
14168 13:39:45.755029 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
14169 13:39:45.755182 arm64_za-ptrace_Set_VL_6256 pass
14170 13:39:45.755351 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
14171 13:39:45.755497 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
14172 13:39:45.755650 arm64_za-ptrace_Set_VL_6272 pass
14173 13:39:45.755809 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
14174 13:39:45.755951 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
14175 13:39:45.756117 arm64_za-ptrace_Set_VL_6288 pass
14176 13:39:45.756261 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
14177 13:39:45.756415 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
14178 13:39:45.756569 arm64_za-ptrace_Set_VL_6304 pass
14179 13:39:45.756751 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
14180 13:39:45.756887 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
14181 13:39:45.757001 arm64_za-ptrace_Set_VL_6320 pass
14182 13:39:45.757115 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
14183 13:39:45.757230 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
14184 13:39:45.757344 arm64_za-ptrace_Set_VL_6336 pass
14185 13:39:45.757458 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
14186 13:39:45.757573 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
14187 13:39:45.757737 arm64_za-ptrace_Set_VL_6352 pass
14188 13:39:45.757940 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
14189 13:39:45.760274 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
14190 13:39:45.760676 arm64_za-ptrace_Set_VL_6368 pass
14191 13:39:45.760855 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
14192 13:39:45.761003 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
14193 13:39:45.761147 arm64_za-ptrace_Set_VL_6384 pass
14194 13:39:45.761323 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
14195 13:39:45.761461 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
14196 13:39:45.761604 arm64_za-ptrace_Set_VL_6400 pass
14197 13:39:45.761762 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
14198 13:39:45.761907 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
14199 13:39:45.762084 arm64_za-ptrace_Set_VL_6416 pass
14200 13:39:45.762221 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
14201 13:39:45.762366 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
14202 13:39:45.762508 arm64_za-ptrace_Set_VL_6432 pass
14203 13:39:45.762649 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
14204 13:39:45.762790 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
14205 13:39:45.762933 arm64_za-ptrace_Set_VL_6448 pass
14206 13:39:45.763111 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
14207 13:39:45.763247 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
14208 13:39:45.763390 arm64_za-ptrace_Set_VL_6464 pass
14209 13:39:45.763532 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
14210 13:39:45.763673 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
14211 13:39:45.763814 arm64_za-ptrace_Set_VL_6480 pass
14212 13:39:45.763957 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
14213 13:39:45.764098 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
14214 13:39:45.764239 arm64_za-ptrace_Set_VL_6496 pass
14215 13:39:45.764418 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
14216 13:39:45.764553 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
14217 13:39:45.764696 arm64_za-ptrace_Set_VL_6512 pass
14218 13:39:45.764837 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
14219 13:39:45.764980 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
14220 13:39:45.765122 arm64_za-ptrace_Set_VL_6528 pass
14221 13:39:45.765265 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
14222 13:39:45.765407 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
14223 13:39:45.765549 arm64_za-ptrace_Set_VL_6544 pass
14224 13:39:45.768652 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
14225 13:39:45.768792 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
14226 13:39:45.769145 arm64_za-ptrace_Set_VL_6560 pass
14227 13:39:45.769282 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
14228 13:39:45.769428 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
14229 13:39:45.769605 arm64_za-ptrace_Set_VL_6576 pass
14230 13:39:45.769757 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
14231 13:39:45.769903 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
14232 13:39:45.770046 arm64_za-ptrace_Set_VL_6592 pass
14233 13:39:45.770189 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
14234 13:39:45.770372 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
14235 13:39:45.770509 arm64_za-ptrace_Set_VL_6608 pass
14236 13:39:45.770654 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
14237 13:39:45.770798 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
14238 13:39:45.770942 arm64_za-ptrace_Set_VL_6624 pass
14239 13:39:45.771087 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
14240 13:39:45.771230 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
14241 13:39:45.771410 arm64_za-ptrace_Set_VL_6640 pass
14242 13:39:45.771545 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
14243 13:39:45.771689 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
14244 13:39:45.771832 arm64_za-ptrace_Set_VL_6656 pass
14245 13:39:45.771974 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
14246 13:39:45.772118 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
14247 13:39:45.772263 arm64_za-ptrace_Set_VL_6672 pass
14248 13:39:45.772438 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
14249 13:39:45.791444 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
14250 13:39:45.791690 arm64_za-ptrace_Set_VL_6688 pass
14251 13:39:45.791860 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
14252 13:39:45.792029 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
14253 13:39:45.792172 arm64_za-ptrace_Set_VL_6704 pass
14254 13:39:45.792307 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
14255 13:39:45.792503 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
14256 13:39:45.792697 arm64_za-ptrace_Set_VL_6720 pass
14257 13:39:45.792991 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
14258 13:39:45.793177 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
14259 13:39:45.793349 arm64_za-ptrace_Set_VL_6736 pass
14260 13:39:45.793531 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
14261 13:39:45.793709 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
14262 13:39:45.793874 arm64_za-ptrace_Set_VL_6752 pass
14263 13:39:45.794034 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
14264 13:39:45.794188 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
14265 13:39:45.794317 arm64_za-ptrace_Set_VL_6768 pass
14266 13:39:45.794456 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
14267 13:39:45.794574 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
14268 13:39:45.794683 arm64_za-ptrace_Set_VL_6784 pass
14269 13:39:45.794796 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
14270 13:39:45.794901 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
14271 13:39:45.795016 arm64_za-ptrace_Set_VL_6800 pass
14272 13:39:45.795131 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
14273 13:39:45.795247 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
14274 13:39:45.795365 arm64_za-ptrace_Set_VL_6816 pass
14275 13:39:45.795481 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
14276 13:39:45.795614 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
14277 13:39:45.795758 arm64_za-ptrace_Set_VL_6832 pass
14278 13:39:45.795907 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
14279 13:39:45.796038 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
14280 13:39:45.796162 arm64_za-ptrace_Set_VL_6848 pass
14281 13:39:45.796253 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
14282 13:39:45.796377 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
14283 13:39:45.796499 arm64_za-ptrace_Set_VL_6864 pass
14284 13:39:45.796591 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
14285 13:39:45.796677 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
14286 13:39:45.796763 arm64_za-ptrace_Set_VL_6880 pass
14287 13:39:45.796848 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
14288 13:39:45.796935 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
14289 13:39:45.797022 arm64_za-ptrace_Set_VL_6896 pass
14290 13:39:45.797107 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
14291 13:39:45.797192 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
14292 13:39:45.797279 arm64_za-ptrace_Set_VL_6912 pass
14293 13:39:45.797365 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
14294 13:39:45.797693 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
14295 13:39:45.797851 arm64_za-ptrace_Set_VL_6928 pass
14296 13:39:45.797972 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
14297 13:39:45.798091 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
14298 13:39:45.798208 arm64_za-ptrace_Set_VL_6944 pass
14299 13:39:45.798305 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
14300 13:39:45.798393 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
14301 13:39:45.798482 arm64_za-ptrace_Set_VL_6960 pass
14302 13:39:45.800249 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14303 13:39:45.800560 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14304 13:39:45.800697 arm64_za-ptrace_Set_VL_6976 pass
14305 13:39:45.800853 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14306 13:39:45.801057 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14307 13:39:45.801225 arm64_za-ptrace_Set_VL_6992 pass
14308 13:39:45.801378 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14309 13:39:45.801509 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14310 13:39:45.801631 arm64_za-ptrace_Set_VL_7008 pass
14311 13:39:45.801786 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14312 13:39:45.801919 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14313 13:39:45.802052 arm64_za-ptrace_Set_VL_7024 pass
14314 13:39:45.802185 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14315 13:39:45.802305 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14316 13:39:45.802438 arm64_za-ptrace_Set_VL_7040 pass
14317 13:39:45.802553 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14318 13:39:45.802663 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14319 13:39:45.802810 arm64_za-ptrace_Set_VL_7056 pass
14320 13:39:45.802981 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14321 13:39:45.803118 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14322 13:39:45.803274 arm64_za-ptrace_Set_VL_7072 pass
14323 13:39:45.803393 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14324 13:39:45.803506 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14325 13:39:45.803621 arm64_za-ptrace_Set_VL_7088 pass
14326 13:39:45.803734 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14327 13:39:45.803841 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14328 13:39:45.803951 arm64_za-ptrace_Set_VL_7104 pass
14329 13:39:45.804055 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14330 13:39:45.804156 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14331 13:39:45.804244 arm64_za-ptrace_Set_VL_7120 pass
14332 13:39:45.804368 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14333 13:39:45.804461 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14334 13:39:45.804549 arm64_za-ptrace_Set_VL_7136 pass
14335 13:39:45.804635 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14336 13:39:45.804724 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14337 13:39:45.804812 arm64_za-ptrace_Set_VL_7152 pass
14338 13:39:45.804929 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14339 13:39:45.805071 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14340 13:39:45.805192 arm64_za-ptrace_Set_VL_7168 pass
14341 13:39:45.805312 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14342 13:39:45.805415 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14343 13:39:45.805505 arm64_za-ptrace_Set_VL_7184 pass
14344 13:39:45.805592 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14345 13:39:45.805733 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14346 13:39:45.808305 arm64_za-ptrace_Set_VL_7200 pass
14347 13:39:45.808676 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14348 13:39:45.808841 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14349 13:39:45.808973 arm64_za-ptrace_Set_VL_7216 pass
14350 13:39:45.809086 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14351 13:39:45.809227 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14352 13:39:45.809354 arm64_za-ptrace_Set_VL_7232 pass
14353 13:39:45.809473 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14354 13:39:45.809591 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14355 13:39:45.809721 arm64_za-ptrace_Set_VL_7248 pass
14356 13:39:45.809838 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14357 13:39:45.809979 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14358 13:39:45.810098 arm64_za-ptrace_Set_VL_7264 pass
14359 13:39:45.810213 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14360 13:39:45.810326 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14361 13:39:45.810445 arm64_za-ptrace_Set_VL_7280 pass
14362 13:39:45.810559 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14363 13:39:45.810689 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14364 13:39:45.810787 arm64_za-ptrace_Set_VL_7296 pass
14365 13:39:45.810894 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14366 13:39:45.811017 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14367 13:39:45.811123 arm64_za-ptrace_Set_VL_7312 pass
14368 13:39:45.811247 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14369 13:39:45.811373 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14370 13:39:45.811510 arm64_za-ptrace_Set_VL_7328 pass
14371 13:39:45.811637 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14372 13:39:45.811743 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14373 13:39:45.811883 arm64_za-ptrace_Set_VL_7344 pass
14374 13:39:45.812000 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14375 13:39:45.812105 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14376 13:39:45.812200 arm64_za-ptrace_Set_VL_7360 pass
14377 13:39:45.812286 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14378 13:39:45.812373 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14379 13:39:45.812459 arm64_za-ptrace_Set_VL_7376 pass
14380 13:39:45.812545 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14381 13:39:45.812630 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14382 13:39:45.812716 arm64_za-ptrace_Set_VL_7392 pass
14383 13:39:45.812800 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14384 13:39:45.812902 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14385 13:39:45.812995 arm64_za-ptrace_Set_VL_7408 pass
14386 13:39:45.816410 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14387 13:39:45.816887 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14388 13:39:45.817093 arm64_za-ptrace_Set_VL_7424 pass
14389 13:39:45.817325 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14390 13:39:45.817554 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14391 13:39:45.817760 arm64_za-ptrace_Set_VL_7440 pass
14392 13:39:45.817972 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14393 13:39:45.818139 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14394 13:39:45.818299 arm64_za-ptrace_Set_VL_7456 pass
14395 13:39:45.818462 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14396 13:39:45.818619 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14397 13:39:45.818790 arm64_za-ptrace_Set_VL_7472 pass
14398 13:39:45.818951 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14399 13:39:45.819117 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14400 13:39:45.819253 arm64_za-ptrace_Set_VL_7488 pass
14401 13:39:45.819411 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14402 13:39:45.819559 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14403 13:39:45.819717 arm64_za-ptrace_Set_VL_7504 pass
14404 13:39:45.819997 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14405 13:39:45.820201 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14406 13:39:45.820337 arm64_za-ptrace_Set_VL_7520 pass
14407 13:39:45.820458 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14408 13:39:45.820574 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14409 13:39:45.820689 arm64_za-ptrace_Set_VL_7536 pass
14410 13:39:45.820843 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14411 13:39:45.821017 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14412 13:39:45.821141 arm64_za-ptrace_Set_VL_7552 pass
14413 13:39:45.821257 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14414 13:39:45.821373 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14415 13:39:45.821488 arm64_za-ptrace_Set_VL_7568 pass
14416 13:39:45.821604 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14417 13:39:45.821818 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14418 13:39:45.822016 arm64_za-ptrace_Set_VL_7584 pass
14419 13:39:45.822201 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14420 13:39:45.822378 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14421 13:39:45.822517 arm64_za-ptrace_Set_VL_7600 pass
14422 13:39:45.822655 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14423 13:39:45.822785 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14424 13:39:45.822894 arm64_za-ptrace_Set_VL_7616 pass
14425 13:39:45.823000 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14426 13:39:45.823139 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14427 13:39:45.823241 arm64_za-ptrace_Set_VL_7632 pass
14428 13:39:45.823349 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14429 13:39:45.824288 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14430 13:39:45.824459 arm64_za-ptrace_Set_VL_7648 pass
14431 13:39:45.824840 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14432 13:39:45.824943 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14433 13:39:45.825051 arm64_za-ptrace_Set_VL_7664 pass
14434 13:39:45.825137 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14435 13:39:45.825227 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14436 13:39:45.825332 arm64_za-ptrace_Set_VL_7680 pass
14437 13:39:45.825473 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14438 13:39:45.825658 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14439 13:39:45.825804 arm64_za-ptrace_Set_VL_7696 pass
14440 13:39:45.825923 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14441 13:39:45.855515 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14442 13:39:45.856020 arm64_za-ptrace_Set_VL_7712 pass
14443 13:39:45.856218 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14444 13:39:45.856412 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14445 13:39:45.856592 arm64_za-ptrace_Set_VL_7728 pass
14446 13:39:45.856801 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14447 13:39:45.857008 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14448 13:39:45.857188 arm64_za-ptrace_Set_VL_7744 pass
14449 13:39:45.857403 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14450 13:39:45.857589 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14451 13:39:45.857807 arm64_za-ptrace_Set_VL_7760 pass
14452 13:39:45.857990 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14453 13:39:45.858207 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14454 13:39:45.858412 arm64_za-ptrace_Set_VL_7776 pass
14455 13:39:45.858628 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14456 13:39:45.858788 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14457 13:39:45.858950 arm64_za-ptrace_Set_VL_7792 pass
14458 13:39:45.859102 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14459 13:39:45.859251 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14460 13:39:45.859429 arm64_za-ptrace_Set_VL_7808 pass
14461 13:39:45.859668 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14462 13:39:45.859879 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14463 13:39:45.860054 arm64_za-ptrace_Set_VL_7824 pass
14464 13:39:45.860203 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14465 13:39:45.860323 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14466 13:39:45.860489 arm64_za-ptrace_Set_VL_7840 pass
14467 13:39:45.860622 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14468 13:39:45.860741 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14469 13:39:45.860857 arm64_za-ptrace_Set_VL_7856 pass
14470 13:39:45.860974 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14471 13:39:45.861091 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14472 13:39:45.861241 arm64_za-ptrace_Set_VL_7872 pass
14473 13:39:45.861367 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14474 13:39:45.861488 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14475 13:39:45.861605 arm64_za-ptrace_Set_VL_7888 pass
14476 13:39:45.861734 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14477 13:39:45.861853 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14478 13:39:45.861971 arm64_za-ptrace_Set_VL_7904 pass
14479 13:39:45.862088 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14480 13:39:45.862205 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14481 13:39:45.862322 arm64_za-ptrace_Set_VL_7920 pass
14482 13:39:45.862442 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14483 13:39:45.862557 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14484 13:39:45.862673 arm64_za-ptrace_Set_VL_7936 pass
14485 13:39:45.862790 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14486 13:39:45.862905 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14487 13:39:45.864276 arm64_za-ptrace_Set_VL_7952 pass
14488 13:39:45.864584 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14489 13:39:45.864688 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14490 13:39:45.864775 arm64_za-ptrace_Set_VL_7968 pass
14491 13:39:45.864873 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14492 13:39:45.864959 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14493 13:39:45.865040 arm64_za-ptrace_Set_VL_7984 pass
14494 13:39:45.865133 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14495 13:39:45.865214 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14496 13:39:45.865293 arm64_za-ptrace_Set_VL_8000 pass
14497 13:39:45.865388 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14498 13:39:45.865470 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14499 13:39:45.865564 arm64_za-ptrace_Set_VL_8016 pass
14500 13:39:45.865853 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14501 13:39:45.865952 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14502 13:39:45.866038 arm64_za-ptrace_Set_VL_8032 pass
14503 13:39:45.866138 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14504 13:39:45.866223 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14505 13:39:45.866321 arm64_za-ptrace_Set_VL_8048 pass
14506 13:39:45.866411 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14507 13:39:45.866516 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14508 13:39:45.866605 arm64_za-ptrace_Set_VL_8064 pass
14509 13:39:45.866705 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14510 13:39:45.866790 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14511 13:39:45.866873 arm64_za-ptrace_Set_VL_8080 pass
14512 13:39:45.866971 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14513 13:39:45.867058 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14514 13:39:45.867142 arm64_za-ptrace_Set_VL_8096 pass
14515 13:39:45.867239 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14516 13:39:45.867325 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14517 13:39:45.867407 arm64_za-ptrace_Set_VL_8112 pass
14518 13:39:45.867506 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14519 13:39:45.867589 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14520 13:39:45.867671 arm64_za-ptrace_Set_VL_8128 pass
14521 13:39:45.867768 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14522 13:39:45.867853 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14523 13:39:45.867936 arm64_za-ptrace_Set_VL_8144 pass
14524 13:39:45.868032 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14525 13:39:45.868116 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14526 13:39:45.868199 arm64_za-ptrace_Set_VL_8160 pass
14527 13:39:45.872292 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14528 13:39:45.872718 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14529 13:39:45.872888 arm64_za-ptrace_Set_VL_8176 pass
14530 13:39:45.873033 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14531 13:39:45.873188 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14532 13:39:45.873328 arm64_za-ptrace_Set_VL_8192 pass
14533 13:39:45.873481 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14534 13:39:45.873607 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14535 13:39:45.873749 arm64_za-ptrace pass
14536 13:39:45.873871 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14537 13:39:45.874026 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14538 13:39:45.874155 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14539 13:39:45.874319 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14540 13:39:45.874488 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14541 13:39:45.874700 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14542 13:39:45.874930 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14543 13:39:45.875128 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14544 13:39:45.875301 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14545 13:39:45.875483 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14546 13:39:45.875676 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14547 13:39:45.875897 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14548 13:39:45.876096 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14549 13:39:45.880356 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14550 13:39:45.880760 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14551 13:39:45.880958 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14552 13:39:45.881205 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14553 13:39:45.881451 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14554 13:39:45.881634 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14555 13:39:45.881828 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14556 13:39:45.881996 arm64_check_buffer_fill fail
14557 13:39:45.882377 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14558 13:39:45.882644 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14559 13:39:45.882867 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14560 13:39:45.883084 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14561 13:39:45.883316 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14562 13:39:45.883541 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14563 13:39:45.883758 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14564 13:39:45.883968 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14565 13:39:45.884206 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14566 13:39:45.888525 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14567 13:39:45.888743 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14568 13:39:45.888933 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14569 13:39:45.889090 arm64_check_child_memory fail
14570 13:39:45.889289 arm64_check_gcr_el1_cswitch fail
14571 13:39:45.889435 arm64_check_ksm_options fail
14572 13:39:45.889640 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14573 13:39:45.889849 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14574 13:39:45.890040 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14575 13:39:45.890228 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14576 13:39:45.890660 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14577 13:39:45.898144 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14578 13:39:45.898766 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14579 13:39:45.899025 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14580 13:39:45.899271 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14581 13:39:45.899455 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14582 13:39:45.899661 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14583 13:39:45.899847 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14584 13:39:45.900095 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14585 13:39:45.900254 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14586 13:39:45.900427 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14587 13:39:45.900618 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14588 13:39:45.900810 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14589 13:39:45.901051 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14590 13:39:45.901276 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14591 13:39:45.901946 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14592 13:39:45.902171 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14593 13:39:45.902384 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14594 13:39:45.902543 arm64_check_mmap_options fail
14595 13:39:45.902729 arm64_check_prctl_check_basic_read pass
14596 13:39:45.902898 arm64_check_prctl_NONE pass
14597 13:39:45.903046 arm64_check_prctl_SYNC pass
14598 13:39:45.903227 arm64_check_prctl_ASYNC pass
14599 13:39:45.903391 arm64_check_prctl_SYNC_ASYNC pass
14600 13:39:45.903536 arm64_check_prctl pass
14601 13:39:45.903692 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14602 13:39:45.903873 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14603 13:39:45.904047 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14604 13:39:45.904176 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14605 13:39:45.904320 arm64_check_tags_inclusion fail
14606 13:39:45.904441 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14607 13:39:45.904578 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14608 13:39:45.904768 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14609 13:39:45.904908 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14610 13:39:45.908483 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14611 13:39:45.908826 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14612 13:39:45.908948 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14613 13:39:45.909050 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14614 13:39:45.909329 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14615 13:39:45.909493 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14616 13:39:45.909637 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14617 13:39:45.910060 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14618 13:39:45.910317 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14619 13:39:45.910537 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14620 13:39:45.910696 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14621 13:39:45.910892 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14622 13:39:45.911043 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14623 13:39:45.911241 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14624 13:39:45.911391 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14625 13:39:45.911588 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14626 13:39:45.911742 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14627 13:39:45.911900 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14628 13:39:45.912091 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14629 13:39:45.912245 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14630 13:39:45.916357 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14631 13:39:45.916765 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14632 13:39:45.916958 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14633 13:39:45.917169 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14634 13:39:45.917831 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14635 13:39:45.918029 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14636 13:39:45.918221 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14637 13:39:45.918419 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14638 13:39:45.918858 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14639 13:39:45.919045 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14640 13:39:45.919235 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14641 13:39:45.919415 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14642 13:39:45.919609 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14643 13:39:45.919782 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14644 13:39:45.920005 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14645 13:39:45.920165 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14646 13:39:45.920286 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14647 13:39:45.920400 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14648 13:39:45.920512 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14649 13:39:45.920627 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14650 13:39:45.920740 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14651 13:39:45.924354 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14652 13:39:45.924880 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14653 13:39:45.925076 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14654 13:39:45.925266 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14655 13:39:45.925494 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14656 13:39:45.925664 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14657 13:39:45.925862 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14658 13:39:45.926073 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14659 13:39:45.926322 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14660 13:39:45.926508 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14661 13:39:45.926719 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14662 13:39:45.927012 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14663 13:39:45.927351 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14664 13:39:45.927588 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14665 13:39:45.927778 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14666 13:39:45.927963 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14667 13:39:45.928178 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14668 13:39:45.947838 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14669 13:39:45.948254 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14670 13:39:45.948355 arm64_check_user_mem pass
14671 13:39:45.948440 arm64_btitest_nohint_func_call_using_br_x0 pass
14672 13:39:45.948542 arm64_btitest_nohint_func_call_using_br_x16 pass
14673 13:39:45.948630 arm64_btitest_nohint_func_call_using_blr pass
14674 13:39:45.948732 arm64_btitest_bti_none_func_call_using_br_x0 pass
14675 13:39:45.948816 arm64_btitest_bti_none_func_call_using_br_x16 pass
14676 13:39:45.948916 arm64_btitest_bti_none_func_call_using_blr pass
14677 13:39:45.949002 arm64_btitest_bti_c_func_call_using_br_x0 pass
14678 13:39:45.949101 arm64_btitest_bti_c_func_call_using_br_x16 pass
14679 13:39:45.949200 arm64_btitest_bti_c_func_call_using_blr pass
14680 13:39:45.949301 arm64_btitest_bti_j_func_call_using_br_x0 pass
14681 13:39:45.949401 arm64_btitest_bti_j_func_call_using_br_x16 pass
14682 13:39:45.949739 arm64_btitest_bti_j_func_call_using_blr pass
14683 13:39:45.949910 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14684 13:39:45.951182 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14685 13:39:45.951375 arm64_btitest_bti_jc_func_call_using_blr pass
14686 13:39:45.951530 arm64_btitest_paciasp_func_call_using_br_x0 pass
14687 13:39:45.951690 arm64_btitest_paciasp_func_call_using_br_x16 pass
14688 13:39:45.951842 arm64_btitest_paciasp_func_call_using_blr pass
14689 13:39:45.951988 arm64_btitest pass
14690 13:39:45.952135 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14691 13:39:45.952262 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14692 13:39:45.952425 arm64_nobtitest_nohint_func_call_using_blr pass
14693 13:39:45.952557 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14694 13:39:45.952673 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14695 13:39:45.952790 arm64_nobtitest_bti_none_func_call_using_blr pass
14696 13:39:45.952904 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14697 13:39:45.953020 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14698 13:39:45.953136 arm64_nobtitest_bti_c_func_call_using_blr pass
14699 13:39:45.953249 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14700 13:39:45.953580 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14701 13:39:45.953726 arm64_nobtitest_bti_j_func_call_using_blr pass
14702 13:39:45.953845 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14703 13:39:45.953963 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14704 13:39:45.954079 arm64_nobtitest_bti_jc_func_call_using_blr pass
14705 13:39:45.954194 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14706 13:39:45.954308 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14707 13:39:45.954425 arm64_nobtitest_paciasp_func_call_using_blr pass
14708 13:39:45.956384 arm64_nobtitest pass
14709 13:39:45.956499 arm64_hwcap_cpuinfo_match_RNG pass
14710 13:39:45.956590 arm64_hwcap_sigill_RNG pass
14711 13:39:45.956871 arm64_hwcap_cpuinfo_match_SME pass
14712 13:39:45.956972 arm64_hwcap_sigill_SME pass
14713 13:39:45.957057 arm64_hwcap_cpuinfo_match_SVE pass
14714 13:39:45.957139 arm64_hwcap_sigill_SVE pass
14715 13:39:45.957220 arm64_hwcap_cpuinfo_match_SVE_2 pass
14716 13:39:45.957322 arm64_hwcap_sigill_SVE_2 pass
14717 13:39:45.957408 arm64_hwcap_cpuinfo_match_SVE_AES pass
14718 13:39:45.957491 arm64_hwcap_sigill_SVE_AES pass
14719 13:39:45.957573 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14720 13:39:45.957663 arm64_hwcap_sigill_SVE2_PMULL pass
14721 13:39:45.957763 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14722 13:39:45.957846 arm64_hwcap_sigill_SVE2_BITPERM pass
14723 13:39:45.957931 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14724 13:39:45.958011 arm64_hwcap_sigill_SVE2_SHA3 pass
14725 13:39:45.958091 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14726 13:39:45.958188 arm64_hwcap_sigill_SVE2_SM4 pass
14727 13:39:45.958271 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14728 13:39:45.958352 arm64_hwcap_sigill_SVE2_I8MM pass
14729 13:39:45.958434 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14730 13:39:45.958515 arm64_hwcap_sigill_SVE2_F32MM pass
14731 13:39:45.958619 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14732 13:39:45.958703 arm64_hwcap_sigill_SVE2_F64MM pass
14733 13:39:45.958783 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14734 13:39:45.958865 arm64_hwcap_sigill_SVE2_BF16 pass
14735 13:39:45.958945 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14736 13:39:45.959041 arm64_hwcap_sigill_SVE2_EBF16 skip
14737 13:39:45.959122 arm64_hwcap pass
14738 13:39:45.959204 arm64_ptrace_read_tpidr_one pass
14739 13:39:45.959288 arm64_ptrace_write_tpidr_one pass
14740 13:39:45.959387 arm64_ptrace_verify_tpidr_one pass
14741 13:39:45.959471 arm64_ptrace_count_tpidrs pass
14742 13:39:45.959554 arm64_ptrace_tpidr2_write pass
14743 13:39:45.959635 arm64_ptrace_tpidr2_read pass
14744 13:39:45.959733 arm64_ptrace_write_tpidr_only pass
14745 13:39:45.959819 arm64_ptrace pass
14746 13:39:45.959898 arm64_syscall-abi_getpid_FPSIMD pass
14747 13:39:45.959979 arm64_syscall-abi_getpid_SVE_VL_256 pass
14748 13:39:45.960073 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14749 13:39:45.960158 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14750 13:39:45.960239 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14751 13:39:45.964268 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14752 13:39:45.964681 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14753 13:39:45.964821 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14754 13:39:45.964968 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14755 13:39:45.965098 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14756 13:39:45.965245 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14757 13:39:45.965398 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14758 13:39:45.965548 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14759 13:39:45.965716 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14760 13:39:45.965871 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14761 13:39:45.966003 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14762 13:39:45.966150 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14763 13:39:45.966279 arm64_syscall-abi_getpid_SVE_VL_240 pass
14764 13:39:45.966430 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14765 13:39:45.966558 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14766 13:39:45.966707 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14767 13:39:45.967020 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14768 13:39:45.967204 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14769 13:39:45.967379 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14770 13:39:45.967532 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14771 13:39:45.967655 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14772 13:39:45.967794 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14773 13:39:45.967915 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14774 13:39:45.968031 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14775 13:39:45.968170 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14776 13:39:45.972312 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14777 13:39:45.972773 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14778 13:39:45.972934 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14779 13:39:45.973081 arm64_syscall-abi_getpid_SVE_VL_224 pass
14780 13:39:45.973279 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14781 13:39:45.973455 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14782 13:39:45.973605 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14783 13:39:45.973766 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14784 13:39:45.973947 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14785 13:39:45.974095 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14786 13:39:45.974246 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14787 13:39:45.974401 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14788 13:39:45.974554 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14789 13:39:45.974751 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14790 13:39:45.974924 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14791 13:39:45.975080 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14792 13:39:45.975488 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14793 13:39:45.975673 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14794 13:39:45.975828 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14795 13:39:45.975973 arm64_syscall-abi_getpid_SVE_VL_208 pass
14796 13:39:45.976099 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14797 13:39:45.976214 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14798 13:39:45.976329 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14799 13:39:45.976443 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14800 13:39:45.976556 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14801 13:39:45.976672 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14802 13:39:45.976786 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14803 13:39:45.976900 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14804 13:39:45.977040 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14805 13:39:45.977159 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14806 13:39:45.977274 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14807 13:39:45.977387 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14808 13:39:45.980307 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14809 13:39:45.980708 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14810 13:39:45.980876 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14811 13:39:45.981025 arm64_syscall-abi_getpid_SVE_VL_192 pass
14812 13:39:45.981176 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14813 13:39:45.981356 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14814 13:39:45.981514 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14815 13:39:45.981677 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14816 13:39:45.981817 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14817 13:39:45.982000 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14818 13:39:45.982144 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14819 13:39:45.982266 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14820 13:39:45.982382 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14821 13:39:45.982507 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14822 13:39:45.982657 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14823 13:39:45.982787 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14824 13:39:45.982909 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14825 13:39:45.983030 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14826 13:39:45.983160 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14827 13:39:45.983306 arm64_syscall-abi_getpid_SVE_VL_176 pass
14828 13:39:45.983438 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14829 13:39:45.983558 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14830 13:39:45.983683 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14831 13:39:45.983801 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14832 13:39:45.983956 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14833 13:39:45.984092 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14834 13:39:45.984218 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14835 13:39:45.984334 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14836 13:39:45.984472 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14837 13:39:45.988891 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14838 13:39:45.998998 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14839 13:39:45.999280 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14840 13:39:45.999444 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14841 13:39:45.999588 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14842 13:39:45.999714 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14843 13:39:45.999853 arm64_syscall-abi_getpid_SVE_VL_160 pass
14844 13:39:45.999972 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14845 13:39:46.000088 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14846 13:39:46.000202 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14847 13:39:46.000342 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14848 13:39:46.000469 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14849 13:39:46.000617 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14850 13:39:46.000747 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14851 13:39:46.000893 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14852 13:39:46.001020 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14853 13:39:46.001171 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14854 13:39:46.001297 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14855 13:39:46.001442 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14856 13:39:46.001570 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14857 13:39:46.001790 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14858 13:39:46.001927 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14859 13:39:46.002076 arm64_syscall-abi_getpid_SVE_VL_144 pass
14860 13:39:46.002225 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14861 13:39:46.002372 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14862 13:39:46.002504 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14863 13:39:46.002658 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14864 13:39:46.002809 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14865 13:39:46.002936 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14866 13:39:46.003081 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14867 13:39:46.003230 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14868 13:39:46.003585 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14869 13:39:46.003724 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14870 13:39:46.003851 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14871 13:39:46.003997 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14872 13:39:46.004124 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14873 13:39:46.004248 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14874 13:39:46.004438 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14875 13:39:46.008327 arm64_syscall-abi_getpid_SVE_VL_128 pass
14876 13:39:46.008849 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14877 13:39:46.009016 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14878 13:39:46.009173 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14879 13:39:46.009322 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14880 13:39:46.009492 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14881 13:39:46.009654 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14882 13:39:46.009797 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14883 13:39:46.009954 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14884 13:39:46.010084 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14885 13:39:46.010237 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14886 13:39:46.010389 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14887 13:39:46.010513 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14888 13:39:46.010653 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14889 13:39:46.010791 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14890 13:39:46.010938 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14891 13:39:46.011074 arm64_syscall-abi_getpid_SVE_VL_112 pass
14892 13:39:46.011253 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14893 13:39:46.011422 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14894 13:39:46.011565 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14895 13:39:46.011694 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14896 13:39:46.011831 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14897 13:39:46.011959 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14898 13:39:46.012083 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14899 13:39:46.012233 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14900 13:39:46.012392 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14901 13:39:46.012533 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14902 13:39:46.012651 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14903 13:39:46.012766 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14904 13:39:46.012880 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14905 13:39:46.012993 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14906 13:39:46.016378 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14907 13:39:46.016673 arm64_syscall-abi_getpid_SVE_VL_96 pass
14908 13:39:46.017093 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14909 13:39:46.017286 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14910 13:39:46.017442 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14911 13:39:46.017592 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14912 13:39:46.017755 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14913 13:39:46.017898 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14914 13:39:46.018072 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14915 13:39:46.018221 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14916 13:39:46.018363 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14917 13:39:46.018508 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14918 13:39:46.018648 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14919 13:39:46.018793 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14920 13:39:46.018932 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14921 13:39:46.019073 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14922 13:39:46.019248 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14923 13:39:46.019393 arm64_syscall-abi_getpid_SVE_VL_80 pass
14924 13:39:46.019535 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14925 13:39:46.019689 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14926 13:39:46.019829 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14927 13:39:46.019972 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14928 13:39:46.020114 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14929 13:39:46.020255 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14930 13:39:46.020396 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14931 13:39:46.020545 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14932 13:39:46.020732 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14933 13:39:46.020888 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14934 13:39:46.021036 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14935 13:39:46.021185 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14936 13:39:46.021333 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14937 13:39:46.021485 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14938 13:39:46.021636 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14939 13:39:46.024363 arm64_syscall-abi_getpid_SVE_VL_64 pass
14940 13:39:46.024871 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
14941 13:39:46.025066 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
14942 13:39:46.025225 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
14943 13:39:46.025373 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
14944 13:39:46.025523 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
14945 13:39:46.025720 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
14946 13:39:46.025873 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
14947 13:39:46.026025 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
14948 13:39:46.026174 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
14949 13:39:46.026325 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
14950 13:39:46.026472 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
14951 13:39:46.026654 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
14952 13:39:46.026788 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
14953 13:39:46.026898 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
14954 13:39:46.027009 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
14955 13:39:46.027120 arm64_syscall-abi_getpid_SVE_VL_48 pass
14956 13:39:46.027229 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
14957 13:39:46.027339 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
14958 13:39:46.027451 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
14959 13:39:46.027586 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
14960 13:39:46.027705 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
14961 13:39:46.027816 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
14962 13:39:46.027922 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
14963 13:39:46.028031 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
14964 13:39:46.028140 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
14965 13:39:46.028250 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
14966 13:39:46.028384 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
14967 13:39:46.028497 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
14968 13:39:46.028598 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
14969 13:39:46.028695 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
14970 13:39:46.032421 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
14971 13:39:46.032743 arm64_syscall-abi_getpid_SVE_VL_32 pass
14972 13:39:46.033211 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
14973 13:39:46.033477 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
14974 13:39:46.033708 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
14975 13:39:46.033892 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
14976 13:39:46.034073 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
14977 13:39:46.034292 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
14978 13:39:46.034478 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
14979 13:39:46.034653 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
14980 13:39:46.034784 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
14981 13:39:46.034929 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
14982 13:39:46.035049 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
14983 13:39:46.035165 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
14984 13:39:46.035280 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
14985 13:39:46.035395 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
14986 13:39:46.035510 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
14987 13:39:46.035624 arm64_syscall-abi_getpid_SVE_VL_16 pass
14988 13:39:46.035737 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
14989 13:39:46.035849 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
14990 13:39:46.045581 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
14991 13:39:46.046080 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
14992 13:39:46.046231 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
14993 13:39:46.046382 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
14994 13:39:46.046564 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
14995 13:39:46.046718 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
14996 13:39:46.046926 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
14997 13:39:46.047093 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
14998 13:39:46.047249 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
14999 13:39:46.047486 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
15000 13:39:46.047657 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
15001 13:39:46.047803 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
15002 13:39:46.047944 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
15003 13:39:46.048089 arm64_syscall-abi_sched_yield_FPSIMD pass
15004 13:39:46.048224 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
15005 13:39:46.048408 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
15006 13:39:46.048677 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
15007 13:39:46.048894 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
15008 13:39:46.049113 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
15009 13:39:46.049338 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
15010 13:39:46.049514 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
15011 13:39:46.049727 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
15012 13:39:46.049942 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
15013 13:39:46.050139 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
15014 13:39:46.050425 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
15015 13:39:46.050625 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
15016 13:39:46.050818 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
15017 13:39:46.050954 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
15018 13:39:46.051152 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
15019 13:39:46.051364 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
15020 13:39:46.051519 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
15021 13:39:46.051691 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
15022 13:39:46.051862 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
15023 13:39:46.051999 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
15024 13:39:46.052156 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
15025 13:39:46.052512 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
15026 13:39:46.052642 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
15027 13:39:46.052759 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
15028 13:39:46.052877 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
15029 13:39:46.052991 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
15030 13:39:46.053106 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
15031 13:39:46.053222 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
15032 13:39:46.053337 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
15033 13:39:46.053454 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
15034 13:39:46.053569 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
15035 13:39:46.053703 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
15036 13:39:46.053824 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
15037 13:39:46.053939 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
15038 13:39:46.054056 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
15039 13:39:46.054172 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
15040 13:39:46.056296 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
15041 13:39:46.056634 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
15042 13:39:46.056744 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
15043 13:39:46.056861 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
15044 13:39:46.056972 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
15045 13:39:46.057083 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
15046 13:39:46.057191 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
15047 13:39:46.057301 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
15048 13:39:46.057599 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
15049 13:39:46.057898 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
15050 13:39:46.057996 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
15051 13:39:46.058104 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
15052 13:39:46.058198 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
15053 13:39:46.058306 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
15054 13:39:46.058416 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
15055 13:39:46.058525 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
15056 13:39:46.058841 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
15057 13:39:46.058989 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
15058 13:39:46.059114 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
15059 13:39:46.059225 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
15060 13:39:46.059334 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
15061 13:39:46.059443 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
15062 13:39:46.059750 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
15063 13:39:46.059895 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
15064 13:39:46.060062 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
15065 13:39:46.060195 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
15066 13:39:46.060313 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
15067 13:39:46.068442 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
15068 13:39:46.068664 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
15069 13:39:46.068974 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
15070 13:39:46.069073 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
15071 13:39:46.069163 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
15072 13:39:46.069233 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
15073 13:39:46.069308 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
15074 13:39:46.069372 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
15075 13:39:46.069434 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
15076 13:39:46.069505 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
15077 13:39:46.069770 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
15078 13:39:46.069851 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
15079 13:39:46.069927 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
15080 13:39:46.070022 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
15081 13:39:46.070290 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
15082 13:39:46.070370 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
15083 13:39:46.070682 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
15084 13:39:46.070781 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
15085 13:39:46.070895 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
15086 13:39:46.070981 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
15087 13:39:46.071093 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
15088 13:39:46.071384 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
15089 13:39:46.071471 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
15090 13:39:46.071790 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
15091 13:39:46.071975 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
15092 13:39:46.072119 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
15093 13:39:46.072276 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
15094 13:39:46.072405 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
15095 13:39:46.076593 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
15096 13:39:46.076927 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
15097 13:39:46.077147 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
15098 13:39:46.077333 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
15099 13:39:46.077504 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
15100 13:39:46.077686 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
15101 13:39:46.077856 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
15102 13:39:46.078036 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
15103 13:39:46.078175 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
15104 13:39:46.078336 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
15105 13:39:46.078513 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
15106 13:39:46.078707 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
15107 13:39:46.078874 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
15108 13:39:46.079047 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
15109 13:39:46.079211 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
15110 13:39:46.079345 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
15111 13:39:46.079584 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
15112 13:39:46.079726 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
15113 13:39:46.079887 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
15114 13:39:46.080061 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
15115 13:39:46.080192 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
15116 13:39:46.080342 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
15117 13:39:46.080488 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
15118 13:39:46.080658 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
15119 13:39:46.080810 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
15120 13:39:46.084246 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
15121 13:39:46.084559 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
15122 13:39:46.084655 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
15123 13:39:46.084745 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
15124 13:39:46.085044 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
15125 13:39:46.085129 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
15126 13:39:46.085230 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
15127 13:39:46.085528 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
15128 13:39:46.085636 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
15129 13:39:46.085748 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
15130 13:39:46.093879 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
15131 13:39:46.094239 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
15132 13:39:46.094337 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
15133 13:39:46.094454 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
15134 13:39:46.094531 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
15135 13:39:46.094631 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
15136 13:39:46.094719 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
15137 13:39:46.094804 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
15138 13:39:46.095072 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
15139 13:39:46.095143 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
15140 13:39:46.095234 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
15141 13:39:46.095343 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
15142 13:39:46.095635 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
15143 13:39:46.095738 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
15144 13:39:46.095832 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
15145 13:39:46.095938 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
15146 13:39:46.096039 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
15147 13:39:46.096338 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
15148 13:39:46.096441 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
15149 13:39:46.096559 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
15150 13:39:46.096657 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
15151 13:39:46.096937 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
15152 13:39:46.097133 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
15153 13:39:46.097331 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
15154 13:39:46.097498 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
15155 13:39:46.097753 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
15156 13:39:46.097975 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
15157 13:39:46.098152 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
15158 13:39:46.098335 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
15159 13:39:46.098492 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
15160 13:39:46.098655 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
15161 13:39:46.098850 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
15162 13:39:46.099065 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
15163 13:39:46.099241 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
15164 13:39:46.099407 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
15165 13:39:46.099572 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
15166 13:39:46.099735 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
15167 13:39:46.099898 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
15168 13:39:46.100095 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
15169 13:39:46.100246 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
15170 13:39:46.100417 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
15171 13:39:46.100552 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
15172 13:39:46.100679 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
15173 13:39:46.100805 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
15174 13:39:46.100932 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
15175 13:39:46.104266 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
15176 13:39:46.104673 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
15177 13:39:46.104828 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
15178 13:39:46.104958 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
15179 13:39:46.105106 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
15180 13:39:46.105236 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
15181 13:39:46.105389 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
15182 13:39:46.105540 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
15183 13:39:46.105702 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
15184 13:39:46.105880 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
15185 13:39:46.106047 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
15186 13:39:46.106208 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
15187 13:39:46.106377 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
15188 13:39:46.106501 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
15189 13:39:46.106621 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
15190 13:39:46.106756 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
15191 13:39:46.106921 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
15192 13:39:46.107074 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
15193 13:39:46.107216 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
15194 13:39:46.107395 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
15195 13:39:46.107557 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
15196 13:39:46.107714 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
15197 13:39:46.107869 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
15198 13:39:46.108051 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
15199 13:39:46.108205 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
15200 13:39:46.108363 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
15201 13:39:46.108534 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
15202 13:39:46.108660 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
15203 13:39:46.112311 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
15204 13:39:46.112715 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
15205 13:39:46.112837 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
15206 13:39:46.112943 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
15207 13:39:46.113049 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
15208 13:39:46.113133 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
15209 13:39:46.113227 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
15210 13:39:46.113319 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
15211 13:39:46.113425 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
15212 13:39:46.113512 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
15213 13:39:46.113611 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
15214 13:39:46.113720 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
15215 13:39:46.114012 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
15216 13:39:46.114102 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
15217 13:39:46.114187 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
15218 13:39:46.114264 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
15219 13:39:46.114565 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
15220 13:39:46.114648 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
15221 13:39:46.114738 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
15222 13:39:46.114869 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
15223 13:39:46.114996 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
15224 13:39:46.115114 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
15225 13:39:46.115465 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
15226 13:39:46.115654 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
15227 13:39:46.115857 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
15228 13:39:46.116018 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
15229 13:39:46.116147 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
15230 13:39:46.116289 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
15231 13:39:46.116639 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
15232 13:39:46.124333 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
15233 13:39:46.124705 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
15234 13:39:46.124812 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
15235 13:39:46.124934 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
15236 13:39:46.125041 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
15237 13:39:46.125137 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
15238 13:39:46.125222 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
15239 13:39:46.125292 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
15240 13:39:46.125374 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
15241 13:39:46.125463 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
15242 13:39:46.125556 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
15243 13:39:46.125863 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
15244 13:39:46.126060 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
15245 13:39:46.126255 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
15246 13:39:46.126438 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
15247 13:39:46.126633 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
15248 13:39:46.126780 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
15249 13:39:46.126954 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
15250 13:39:46.127125 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
15251 13:39:46.127260 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
15252 13:39:46.127385 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
15253 13:39:46.127535 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
15254 13:39:46.127664 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
15255 13:39:46.127788 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
15256 13:39:46.127940 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
15257 13:39:46.128073 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
15258 13:39:46.128200 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
15259 13:39:46.132411 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
15260 13:39:46.132576 arm64_syscall-abi pass
15261 13:39:46.132723 arm64_tpidr2_default_value pass
15262 13:39:46.133024 arm64_tpidr2_write_read pass
15263 13:39:46.133125 arm64_tpidr2_write_sleep_read pass
15264 13:39:46.133217 arm64_tpidr2_write_fork_read pass
15265 13:39:46.133308 arm64_tpidr2_write_clone_read pass
15266 13:39:46.133401 arm64_tpidr2 pass
15267 13:39:46.142822 + ../../utils/send-to-lava.sh ./output/result.txt
15268 13:39:46.186071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
15270 13:39:46.186637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
15271 13:39:46.216654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
15272 13:39:46.217173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
15274 13:39:46.248176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
15275 13:39:46.248691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
15277 13:39:46.280986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
15279 13:39:46.281526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
15280 13:39:46.313022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
15281 13:39:46.313423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
15283 13:39:46.344961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
15284 13:39:46.345310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
15286 13:39:46.376917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
15287 13:39:46.377368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
15289 13:39:46.413389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
15291 13:39:46.413874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
15292 13:39:46.447314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
15293 13:39:46.447696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
15295 13:39:46.479987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
15296 13:39:46.480468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
15298 13:39:46.514464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
15299 13:39:46.514927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
15301 13:39:46.546685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15302 13:39:46.547112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15304 13:39:46.577363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15305 13:39:46.577768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15307 13:39:46.608316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15309 13:39:46.608760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15310 13:39:46.639004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15311 13:39:46.639374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15313 13:39:46.669989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15314 13:39:46.670382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15316 13:39:46.700643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15317 13:39:46.701047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15319 13:39:46.730997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15320 13:39:46.731373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15322 13:39:46.762567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15324 13:39:46.763138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15325 13:39:46.794319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15326 13:39:46.794753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15328 13:39:46.824948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15329 13:39:46.825348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15331 13:39:46.855681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15333 13:39:46.856255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15334 13:39:46.886309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15335 13:39:46.886766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15337 13:39:46.917049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15338 13:39:46.917508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15340 13:39:46.948093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15342 13:39:46.948648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15343 13:39:46.978937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15345 13:39:46.979456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15346 13:39:47.010433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15347 13:39:47.010887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15349 13:39:47.041588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15351 13:39:47.042136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15352 13:39:47.072499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15354 13:39:47.072881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15355 13:39:47.103237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15357 13:39:47.103662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15358 13:39:47.133930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15360 13:39:47.134319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15361 13:39:47.164183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15362 13:39:47.164517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15364 13:39:47.194407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15365 13:39:47.194801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15367 13:39:47.225079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15368 13:39:47.225494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15370 13:39:47.255062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15371 13:39:47.255500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15373 13:39:47.285667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15374 13:39:47.286113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15376 13:39:47.315590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15377 13:39:47.316055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15379 13:39:47.346294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15380 13:39:47.346718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15382 13:39:47.376020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15383 13:39:47.376451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15385 13:39:47.406122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15387 13:39:47.406705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15388 13:39:47.436646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15390 13:39:47.437289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15391 13:39:47.467229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15393 13:39:47.467829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15394 13:39:47.497916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15395 13:39:47.498361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15397 13:39:47.527911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15399 13:39:47.528517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15400 13:39:47.557955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15402 13:39:47.558468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15403 13:39:47.589299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15404 13:39:47.589758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15406 13:39:47.620967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15408 13:39:47.621519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15409 13:39:47.651157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15410 13:39:47.651606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15412 13:39:47.681528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15414 13:39:47.682068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15415 13:39:47.711862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15416 13:39:47.712286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15418 13:39:47.742964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15419 13:39:47.743457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15421 13:39:47.775082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15423 13:39:47.775759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15424 13:39:47.807224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15426 13:39:47.807692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15427 13:39:47.839988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15428 13:39:47.840389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15430 13:39:47.870686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15431 13:39:47.871087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15433 13:39:47.903296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15434 13:39:47.903774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15436 13:39:47.940239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15437 13:39:47.940645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15439 13:39:47.974798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15440 13:39:47.975170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15442 13:39:48.005992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15444 13:39:48.006560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15445 13:39:48.037047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15447 13:39:48.037414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15448 13:39:48.067783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15450 13:39:48.068350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15451 13:39:48.098618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15453 13:39:48.099168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15454 13:39:48.129622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15456 13:39:48.130178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15457 13:39:48.160890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15458 13:39:48.161351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15460 13:39:48.191668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15461 13:39:48.192108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15463 13:39:48.222214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15464 13:39:48.222658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15466 13:39:48.253971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15467 13:39:48.254439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15469 13:39:48.285117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15470 13:39:48.285574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15472 13:39:48.316876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15473 13:39:48.317295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15475 13:39:48.348001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15476 13:39:48.348461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15478 13:39:48.378564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15479 13:39:48.379008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15481 13:39:48.409300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15482 13:39:48.409763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15484 13:39:48.439979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15485 13:39:48.440395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15487 13:39:48.470686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15489 13:39:48.471114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15490 13:39:48.502038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15491 13:39:48.502486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15493 13:39:48.532203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15494 13:39:48.532614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15496 13:39:48.563086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15497 13:39:48.563521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15499 13:39:48.593692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15501 13:39:48.594144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15502 13:39:48.624592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15504 13:39:48.625010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15505 13:39:48.654789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15507 13:39:48.655192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15508 13:39:48.685488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15509 13:39:48.685907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15511 13:39:48.716620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15513 13:39:48.717194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15514 13:39:48.748616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15516 13:39:48.749191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15517 13:39:48.779982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15518 13:39:48.780537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15520 13:39:48.813184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15521 13:39:48.813676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15523 13:39:48.843648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15524 13:39:48.844064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15526 13:39:48.874637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15527 13:39:48.875051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15529 13:39:48.905932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15531 13:39:48.906534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15532 13:39:48.937959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15533 13:39:48.938516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15535 13:39:48.969619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15537 13:39:48.970088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15538 13:39:49.002160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15540 13:39:49.002626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15541 13:39:49.033282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15542 13:39:49.033690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15544 13:39:49.064265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15545 13:39:49.064684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15547 13:39:49.095618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15548 13:39:49.096037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15550 13:39:49.126764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15551 13:39:49.127184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15553 13:39:49.159947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15554 13:39:49.160409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15556 13:39:49.192677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15558 13:39:49.193130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15559 13:39:49.225897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15561 13:39:49.226457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15562 13:39:49.257692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15564 13:39:49.258333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15565 13:39:49.288113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15567 13:39:49.288526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15568 13:39:49.318655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15569 13:39:49.319143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15571 13:39:49.349396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15572 13:39:49.349866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15574 13:39:49.380145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15575 13:39:49.380555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15577 13:39:49.410725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15579 13:39:49.411114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15580 13:39:49.441275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15581 13:39:49.441692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15583 13:39:49.471854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15584 13:39:49.472296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15586 13:39:49.503332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15587 13:39:49.503794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15589 13:39:49.533693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15590 13:39:49.534164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15592 13:39:49.564108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15593 13:39:49.564654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15595 13:39:49.594665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15597 13:39:49.595201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15598 13:39:49.625472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15600 13:39:49.626044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15601 13:39:49.655518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15602 13:39:49.655953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15604 13:39:49.686002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15605 13:39:49.686338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15607 13:39:49.717143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15608 13:39:49.717493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15610 13:39:49.747905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15611 13:39:49.748288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15613 13:39:49.778564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15614 13:39:49.778907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15616 13:39:49.809375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15617 13:39:49.809929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15619 13:39:49.839911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15621 13:39:49.840672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15622 13:39:49.870326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15623 13:39:49.870804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15625 13:39:49.901425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15627 13:39:49.901986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15628 13:39:49.932679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15629 13:39:49.933131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15631 13:39:49.963174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15632 13:39:49.963588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15634 13:39:49.994772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15636 13:39:49.995325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15637 13:39:50.025956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15639 13:39:50.026410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15640 13:39:50.057478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15641 13:39:50.057932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15643 13:39:50.087921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15645 13:39:50.088479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15646 13:39:50.119665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15647 13:39:50.120115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15649 13:39:50.150425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15650 13:39:50.150904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15652 13:39:50.181518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15653 13:39:50.181990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15655 13:39:50.214227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15656 13:39:50.214769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15658 13:39:50.251101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15659 13:39:50.251671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15661 13:39:50.288597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15663 13:39:50.289186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15664 13:39:50.322217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15666 13:39:50.322700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15667 13:39:50.353919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15668 13:39:50.354330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15670 13:39:50.387158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15671 13:39:50.387596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15673 13:39:50.420397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15675 13:39:50.420854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15676 13:39:50.452199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15677 13:39:50.452620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15679 13:39:50.484306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15681 13:39:50.484768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15682 13:39:50.516232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15684 13:39:50.516610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15685 13:39:50.547191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15686 13:39:50.547658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15688 13:39:50.577874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15689 13:39:50.578270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15691 13:39:50.609347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15692 13:39:50.609759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15694 13:39:50.641026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15695 13:39:50.641438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15697 13:39:50.671858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15698 13:39:50.672274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15700 13:39:50.704727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15701 13:39:50.705164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15703 13:39:50.738723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15705 13:39:50.739177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15706 13:39:50.771691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15708 13:39:50.772143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15709 13:39:50.803645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15710 13:39:50.804092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15712 13:39:50.837444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15714 13:39:50.837911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15715 13:39:50.869607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15716 13:39:50.870028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15718 13:39:50.901114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15719 13:39:50.901543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15721 13:39:50.931869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15722 13:39:50.932259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15724 13:39:50.962396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15725 13:39:50.962719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15727 13:39:50.996692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15729 13:39:50.997302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15730 13:39:51.031430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15732 13:39:51.031799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15733 13:39:51.062659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15735 13:39:51.063105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15736 13:39:51.095166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15737 13:39:51.095542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15739 13:39:51.125932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15740 13:39:51.126294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15742 13:39:51.157341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15744 13:39:51.157955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15745 13:39:51.189620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15747 13:39:51.190224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15748 13:39:51.220016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15749 13:39:51.220477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15751 13:39:51.250868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15752 13:39:51.251326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15754 13:39:51.282885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15756 13:39:51.283453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15757 13:39:51.314628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15758 13:39:51.315108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15760 13:39:51.345728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15762 13:39:51.346365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15763 13:39:51.377296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15764 13:39:51.377767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15766 13:39:51.407612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15767 13:39:51.408087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15769 13:39:51.438333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15771 13:39:51.438872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15772 13:39:51.470353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15774 13:39:51.470983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15775 13:39:51.503001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15777 13:39:51.503571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15778 13:39:51.535135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15779 13:39:51.535616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15781 13:39:51.566818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15783 13:39:51.567405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15784 13:39:51.598578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15786 13:39:51.599128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15787 13:39:51.629491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15789 13:39:51.630049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15790 13:39:51.664425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15792 13:39:51.665011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15793 13:39:51.695407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15794 13:39:51.695867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15796 13:39:51.726641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15797 13:39:51.727067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15799 13:39:51.757053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15800 13:39:51.757483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15802 13:39:51.788841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15804 13:39:51.789383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15805 13:39:51.819648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15806 13:39:51.820115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15808 13:39:51.850441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15809 13:39:51.850887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15811 13:39:51.881723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15812 13:39:51.882191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15814 13:39:51.912353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15816 13:39:51.912980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15817 13:39:51.942765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15818 13:39:51.943233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15820 13:39:51.974275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15821 13:39:51.974741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15823 13:39:52.006100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15824 13:39:52.006514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15826 13:39:52.037616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15827 13:39:52.038022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15829 13:39:52.068138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15831 13:39:52.068571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15832 13:39:52.100902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15833 13:39:52.101330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15835 13:39:52.131729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15837 13:39:52.132276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15838 13:39:52.161644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15840 13:39:52.162210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15841 13:39:52.192866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15842 13:39:52.193287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15844 13:39:52.224580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15846 13:39:52.225026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15847 13:39:52.256144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15849 13:39:52.256587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15850 13:39:52.288503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15852 13:39:52.288937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15853 13:39:52.319437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15855 13:39:52.319873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15856 13:39:52.349964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15857 13:39:52.350486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15859 13:39:52.381297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15861 13:39:52.381890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15862 13:39:52.412997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15864 13:39:52.413554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15865 13:39:52.444052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15867 13:39:52.444618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15868 13:39:52.475459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15869 13:39:52.475930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15871 13:39:52.506294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15873 13:39:52.506824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15874 13:39:52.537916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15875 13:39:52.538360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15877 13:39:52.568321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15879 13:39:52.568812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15880 13:39:52.599084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15882 13:39:52.599615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15883 13:39:52.630928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15884 13:39:52.631365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15886 13:39:52.663598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15888 13:39:52.664104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15889 13:39:52.695010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15890 13:39:52.695472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15892 13:39:52.726490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15894 13:39:52.727011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15895 13:39:52.757107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15896 13:39:52.757458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15898 13:39:52.787931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15899 13:39:52.788340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15901 13:39:52.819312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15903 13:39:52.819939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15904 13:39:52.850933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15905 13:39:52.851376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15907 13:39:52.881954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15908 13:39:52.882342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15910 13:39:52.913485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15911 13:39:52.913861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15913 13:39:52.946783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15915 13:39:52.947354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15916 13:39:52.981047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15917 13:39:52.981528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15919 13:39:53.013708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15921 13:39:53.014165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15922 13:39:53.047060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15923 13:39:53.047482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15925 13:39:53.077669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15927 13:39:53.078203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15928 13:39:53.110688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15930 13:39:53.111195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15931 13:39:53.143799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15932 13:39:53.144139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15934 13:39:53.175227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15936 13:39:53.175630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15937 13:39:53.208987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15939 13:39:53.209434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
15940 13:39:53.240339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
15941 13:39:53.240747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
15943 13:39:53.272151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
15944 13:39:53.272611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
15946 13:39:53.303907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
15947 13:39:53.304381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
15949 13:39:53.335717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
15950 13:39:53.336163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
15952 13:39:53.368959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
15953 13:39:53.369459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
15955 13:39:53.401717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
15957 13:39:53.402428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
15958 13:39:53.434775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
15959 13:39:53.435228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
15961 13:39:53.467256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
15963 13:39:53.467810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
15964 13:39:53.501307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
15965 13:39:53.501773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
15967 13:39:53.533729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
15968 13:39:53.534258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
15970 13:39:53.570780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
15972 13:39:53.571353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
15973 13:39:53.602024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
15975 13:39:53.602484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
15976 13:39:53.633029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
15977 13:39:53.633451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
15979 13:39:53.664938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
15981 13:39:53.665384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
15982 13:39:53.695725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
15983 13:39:53.696114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
15985 13:39:53.726400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
15986 13:39:53.726810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
15988 13:39:53.758664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
15990 13:39:53.759123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
15991 13:39:53.789509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
15992 13:39:53.789915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
15994 13:39:53.821675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
15995 13:39:53.822180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
15997 13:39:53.853249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
15999 13:39:53.853847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
16000 13:39:53.883889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
16001 13:39:53.884315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
16003 13:39:53.915528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
16005 13:39:53.916122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
16006 13:39:53.946606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
16007 13:39:53.947079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
16009 13:39:53.978865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
16011 13:39:53.979403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
16012 13:39:54.010312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
16014 13:39:54.010875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
16015 13:39:54.041324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
16017 13:39:54.041931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
16018 13:39:54.073438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
16019 13:39:54.073912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
16021 13:39:54.105269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
16022 13:39:54.105692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
16024 13:39:54.139051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
16026 13:39:54.139617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
16027 13:39:54.172561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
16029 13:39:54.172918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
16030 13:39:54.204043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
16031 13:39:54.204429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
16033 13:39:54.236273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
16035 13:39:54.236834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
16036 13:39:54.268214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
16037 13:39:54.268767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
16039 13:39:54.299585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
16040 13:39:54.300085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
16042 13:39:54.331375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
16043 13:39:54.331760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
16045 13:39:54.363044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
16046 13:39:54.363427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
16048 13:39:54.395150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
16049 13:39:54.395522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
16051 13:39:54.426499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
16053 13:39:54.427053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
16054 13:39:54.457130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
16055 13:39:54.457563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
16057 13:39:54.491073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
16058 13:39:54.491504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
16060 13:39:54.523671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
16061 13:39:54.524086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
16063 13:39:54.554299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
16064 13:39:54.554767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
16066 13:39:54.586859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
16068 13:39:54.587432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
16069 13:39:54.619107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
16070 13:39:54.619591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
16072 13:39:54.653668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
16074 13:39:54.654135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
16075 13:39:54.687146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
16076 13:39:54.687605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
16078 13:39:54.719441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
16079 13:39:54.719911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
16081 13:39:54.752639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
16083 13:39:54.753184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
16084 13:39:54.785762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
16085 13:39:54.786135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
16087 13:39:54.817369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
16088 13:39:54.817745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
16090 13:39:54.856243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
16092 13:39:54.856723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
16093 13:39:54.904443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
16095 13:39:54.904912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
16096 13:39:54.946274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
16098 13:39:54.946741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
16099 13:39:54.978584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
16101 13:39:54.979186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
16102 13:39:55.009664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
16103 13:39:55.010127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
16105 13:39:55.040509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
16107 13:39:55.041068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
16108 13:39:55.071886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
16110 13:39:55.072468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
16111 13:39:55.102348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
16112 13:39:55.102743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
16114 13:39:55.135110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
16116 13:39:55.135554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
16117 13:39:55.167748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
16118 13:39:55.168180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
16120 13:39:55.200110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
16121 13:39:55.200525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
16123 13:39:55.233284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
16125 13:39:55.233752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
16126 13:39:55.266699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
16127 13:39:55.267118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
16129 13:39:55.299326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
16130 13:39:55.299895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
16132 13:39:55.333411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
16134 13:39:55.333914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
16135 13:39:55.367268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
16136 13:39:55.367708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
16138 13:39:55.402287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
16139 13:39:55.402659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
16141 13:39:55.436999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
16142 13:39:55.437393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
16144 13:39:55.469491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
16146 13:39:55.469852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
16147 13:39:55.501441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
16148 13:39:55.501776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
16150 13:39:55.533728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
16151 13:39:55.534177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
16153 13:39:55.565824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
16154 13:39:55.566227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
16156 13:39:55.597517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
16158 13:39:55.597972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
16159 13:39:55.629453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
16161 13:39:55.630046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
16162 13:39:55.662245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
16163 13:39:55.662695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
16165 13:39:55.694345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
16167 13:39:55.694750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
16168 13:39:55.725936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
16169 13:39:55.726407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
16171 13:39:55.757418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
16173 13:39:55.757872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
16174 13:39:55.789432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
16175 13:39:55.789834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
16177 13:39:55.823421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
16179 13:39:55.823979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
16180 13:39:55.855068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
16182 13:39:55.855616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
16183 13:39:55.885839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
16185 13:39:55.886414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
16186 13:39:55.917503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
16187 13:39:55.917969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
16189 13:39:55.950358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
16191 13:39:55.950916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
16192 13:39:55.982557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
16194 13:39:55.983113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
16195 13:39:56.014152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
16197 13:39:56.014712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
16198 13:39:56.045935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
16200 13:39:56.046398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
16201 13:39:56.076383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
16203 13:39:56.076822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
16204 13:39:56.108020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
16206 13:39:56.108475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
16207 13:39:56.139682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
16208 13:39:56.140119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
16210 13:39:56.170589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
16212 13:39:56.171034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
16213 13:39:56.201979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
16214 13:39:56.202458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
16216 13:39:56.233296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
16217 13:39:56.233748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
16219 13:39:56.265155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
16220 13:39:56.265618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
16222 13:39:56.295879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
16224 13:39:56.296413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
16225 13:39:56.326826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
16227 13:39:56.327362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
16228 13:39:56.358665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
16229 13:39:56.359102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
16231 13:39:56.391369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
16233 13:39:56.391937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
16234 13:39:56.422476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
16235 13:39:56.422891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
16237 13:39:56.454552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
16239 13:39:56.455000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
16240 13:39:56.486031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
16241 13:39:56.486438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
16243 13:39:56.517356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
16244 13:39:56.517754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
16246 13:39:56.548574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
16248 13:39:56.549272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
16249 13:39:56.580069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
16251 13:39:56.580509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
16252 13:39:56.611547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
16253 13:39:56.611963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
16255 13:39:56.643552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
16256 13:39:56.643994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
16258 13:39:56.675120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
16259 13:39:56.675585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
16261 13:39:56.706811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
16262 13:39:56.707273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
16264 13:39:56.738804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
16266 13:39:56.739364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
16267 13:39:56.771668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
16269 13:39:56.772240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
16270 13:39:56.803297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
16271 13:39:56.803780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
16273 13:39:56.835385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
16274 13:39:56.835858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
16276 13:39:56.867201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
16278 13:39:56.867757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
16279 13:39:56.898829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
16280 13:39:56.899273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
16282 13:39:56.930925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
16283 13:39:56.931366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
16285 13:39:56.964075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
16286 13:39:56.964544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
16288 13:39:56.998043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
16289 13:39:56.998485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
16291 13:39:57.030128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
16292 13:39:57.030583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
16294 13:39:57.061369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
16296 13:39:57.061923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
16297 13:39:57.093373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
16298 13:39:57.093849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
16300 13:39:57.126911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16302 13:39:57.127442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
16303 13:39:57.160612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16305 13:39:57.161111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16306 13:39:57.193926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16307 13:39:57.194376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16309 13:39:57.227826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16310 13:39:57.228296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16312 13:39:57.259702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16313 13:39:57.260156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16315 13:39:57.291492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16316 13:39:57.291897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16318 13:39:57.322066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16319 13:39:57.322494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16321 13:39:57.352896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16322 13:39:57.353300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16324 13:39:57.385381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16325 13:39:57.385794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16327 13:39:57.417206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16329 13:39:57.417658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16330 13:39:57.447937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16332 13:39:57.448388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16333 13:39:57.479944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16334 13:39:57.480345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16336 13:39:57.512091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16338 13:39:57.512654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16339 13:39:57.543203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16340 13:39:57.543605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16342 13:39:57.574672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16344 13:39:57.575219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16345 13:39:57.605440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16347 13:39:57.605993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16348 13:39:57.635973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16350 13:39:57.636400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16351 13:39:57.666948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16352 13:39:57.667400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16354 13:39:57.697808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16356 13:39:57.698341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16357 13:39:57.730210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16358 13:39:57.730599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16360 13:39:57.761261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16361 13:39:57.761690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16363 13:39:57.791721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16365 13:39:57.792265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16366 13:39:57.822862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16367 13:39:57.823314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16369 13:39:57.853710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16371 13:39:57.854230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16372 13:39:57.883931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16373 13:39:57.884369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16375 13:39:57.915835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16376 13:39:57.916246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16378 13:39:57.947453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16379 13:39:57.947917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16381 13:39:57.979139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16382 13:39:57.979530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16384 13:39:58.011035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16385 13:39:58.011541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16387 13:39:58.043664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16389 13:39:58.044378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16390 13:39:58.077156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16391 13:39:58.077663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16393 13:39:58.108109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16394 13:39:58.108500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16396 13:39:58.140553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16398 13:39:58.141094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16399 13:39:58.171429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16400 13:39:58.171848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16402 13:39:58.203760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16403 13:39:58.204182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16405 13:39:58.236218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16407 13:39:58.236665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16408 13:39:58.267286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16410 13:39:58.267722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16411 13:39:58.298874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16412 13:39:58.299282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16414 13:39:58.330204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16415 13:39:58.330656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16417 13:39:58.361220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16418 13:39:58.361603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16420 13:39:58.393275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16421 13:39:58.393693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16423 13:39:58.426866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16425 13:39:58.427485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16426 13:39:58.457631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16428 13:39:58.458210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16429 13:39:58.489025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16431 13:39:58.489461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16432 13:39:58.525441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16433 13:39:58.525809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16435 13:39:58.557375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16436 13:39:58.557724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16438 13:39:58.588990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16439 13:39:58.589350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16441 13:39:58.621465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16442 13:39:58.621985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16444 13:39:58.659075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16445 13:39:58.659478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16447 13:39:58.691212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16448 13:39:58.691653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16450 13:39:58.723565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16451 13:39:58.724014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16453 13:39:58.755288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16455 13:39:58.755815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16456 13:39:58.786159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16457 13:39:58.786586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16459 13:39:58.817796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16460 13:39:58.818205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16462 13:39:58.849270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16463 13:39:58.849640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16465 13:39:58.880391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16467 13:39:58.880837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16468 13:39:58.912372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16470 13:39:58.912944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16471 13:39:58.944253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16472 13:39:58.944697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16474 13:39:58.975951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16475 13:39:58.976416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16477 13:39:59.008382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16479 13:39:59.008936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16480 13:39:59.039594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16482 13:39:59.040136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16483 13:39:59.071173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16484 13:39:59.071620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16486 13:39:59.102918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16487 13:39:59.103366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16489 13:39:59.134072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16490 13:39:59.134505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16492 13:39:59.166535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16494 13:39:59.166972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16495 13:39:59.198219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16496 13:39:59.198519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16498 13:39:59.230726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16499 13:39:59.231181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16501 13:39:59.262477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16503 13:39:59.262858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16504 13:39:59.293603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16505 13:39:59.293989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16507 13:39:59.324516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16509 13:39:59.324887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16510 13:39:59.355357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16511 13:39:59.355734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16513 13:39:59.386508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16515 13:39:59.386919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16516 13:39:59.417548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16517 13:39:59.417939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16519 13:39:59.449341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16521 13:39:59.449769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16522 13:39:59.480935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16523 13:39:59.481328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16525 13:39:59.512169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16527 13:39:59.512579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16528 13:39:59.543156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16529 13:39:59.543543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16531 13:39:59.574740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16532 13:39:59.575142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16534 13:39:59.606172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16535 13:39:59.606546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16537 13:39:59.637442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16538 13:39:59.637930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16540 13:39:59.671336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16542 13:39:59.671918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16543 13:39:59.705101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16544 13:39:59.705564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16546 13:39:59.738036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16547 13:39:59.738532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16549 13:39:59.770549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16551 13:39:59.771174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16552 13:39:59.802773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16553 13:39:59.803251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16555 13:39:59.836993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16557 13:39:59.837683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16558 13:39:59.870365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16559 13:39:59.870748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16561 13:39:59.902631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16562 13:39:59.903072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16564 13:39:59.933756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16565 13:39:59.934135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16567 13:39:59.965381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16568 13:39:59.965804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16570 13:39:59.997722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16572 13:39:59.998293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16573 13:40:00.033852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16574 13:40:00.034246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16576 13:40:00.066370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16577 13:40:00.066829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16579 13:40:00.099349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16580 13:40:00.099802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16582 13:40:00.131254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16584 13:40:00.131864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16585 13:40:00.162387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16587 13:40:00.162957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16588 13:40:00.193858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16590 13:40:00.194446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16591 13:40:00.225532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16593 13:40:00.226092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16594 13:40:00.258094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16595 13:40:00.258566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16597 13:40:00.290364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16598 13:40:00.290835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16600 13:40:00.323689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16602 13:40:00.324255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16603 13:40:00.355411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16604 13:40:00.355794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16606 13:40:00.387570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16608 13:40:00.388121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16609 13:40:00.419325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16610 13:40:00.419786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16612 13:40:00.450972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16613 13:40:00.451370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16615 13:40:00.482900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16616 13:40:00.483283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16618 13:40:00.514840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16619 13:40:00.515260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16621 13:40:00.546405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16623 13:40:00.546819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16624 13:40:00.578256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16626 13:40:00.578878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16627 13:40:00.610126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16628 13:40:00.610607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16630 13:40:00.642562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16631 13:40:00.643037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16633 13:40:00.673662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16634 13:40:00.674144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16636 13:40:00.704609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16638 13:40:00.705232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16639 13:40:00.736192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16640 13:40:00.736638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16642 13:40:00.768168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16643 13:40:00.768575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16645 13:40:00.800307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16646 13:40:00.800761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16648 13:40:00.833207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16650 13:40:00.833660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16651 13:40:00.864827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16652 13:40:00.865228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16654 13:40:00.896906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16655 13:40:00.897338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16657 13:40:00.928953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16658 13:40:00.929427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16660 13:40:00.959988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16661 13:40:00.960444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16663 13:40:00.991321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16664 13:40:00.991749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16666 13:40:01.022507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16668 13:40:01.022929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16669 13:40:01.054461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16670 13:40:01.054873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16672 13:40:01.086726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16673 13:40:01.087147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16675 13:40:01.117708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16677 13:40:01.118134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16678 13:40:01.149568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16680 13:40:01.150124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16681 13:40:01.179970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16682 13:40:01.180369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16684 13:40:01.211274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16686 13:40:01.211877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16687 13:40:01.243106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16688 13:40:01.243570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16690 13:40:01.274208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16691 13:40:01.274629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16693 13:40:01.306010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16694 13:40:01.306466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16696 13:40:01.337693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16698 13:40:01.338109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16699 13:40:01.369301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16701 13:40:01.369848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16702 13:40:01.399926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16703 13:40:01.400361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16705 13:40:01.431197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16706 13:40:01.431597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16708 13:40:01.462664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16710 13:40:01.463282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16711 13:40:01.495894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16712 13:40:01.496369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16714 13:40:01.527946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16716 13:40:01.528465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16717 13:40:01.559100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16718 13:40:01.559571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16720 13:40:01.590198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16722 13:40:01.590742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16723 13:40:01.621617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16724 13:40:01.622092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16726 13:40:01.653315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16727 13:40:01.653757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16729 13:40:01.684421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16731 13:40:01.685063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16732 13:40:01.716415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16734 13:40:01.716846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16735 13:40:01.748954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16737 13:40:01.749377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16738 13:40:01.781253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16739 13:40:01.781673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16741 13:40:01.815065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16743 13:40:01.815515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16744 13:40:01.846560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16745 13:40:01.846967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16747 13:40:01.878378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16748 13:40:01.878807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16750 13:40:01.909610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16752 13:40:01.910201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16753 13:40:01.940043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16755 13:40:01.940562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16756 13:40:01.972061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16757 13:40:01.972499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16759 13:40:02.003569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16760 13:40:02.004028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16762 13:40:02.034750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16763 13:40:02.035170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16765 13:40:02.068553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16767 13:40:02.068983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16768 13:40:02.101393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16769 13:40:02.101832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16771 13:40:02.133344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16773 13:40:02.133962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16774 13:40:02.165359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16775 13:40:02.165824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16777 13:40:02.199894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16779 13:40:02.200478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16780 13:40:02.232375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16782 13:40:02.232986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16783 13:40:02.266500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16784 13:40:02.266877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16786 13:40:02.301774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16787 13:40:02.302206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16789 13:40:02.335484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16790 13:40:02.335936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16792 13:40:02.369192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16793 13:40:02.369636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16795 13:40:02.405959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16796 13:40:02.406398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16798 13:40:02.443784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16799 13:40:02.444178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16801 13:40:02.489630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16802 13:40:02.491078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16804 13:40:02.533159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16805 13:40:02.533537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16807 13:40:02.577828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16808 13:40:02.578255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16810 13:40:02.622204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16811 13:40:02.622634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16813 13:40:02.665691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16814 13:40:02.666139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16816 13:40:02.715335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16817 13:40:02.715757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16819 13:40:02.758912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16820 13:40:02.759352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16822 13:40:02.797873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16823 13:40:02.798255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16825 13:40:02.833459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16827 13:40:02.834195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16828 13:40:02.870959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16830 13:40:02.871678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16831 13:40:02.905403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16832 13:40:02.905772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16834 13:40:02.941668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16835 13:40:02.942185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16837 13:40:02.983521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16839 13:40:02.983978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16840 13:40:03.031727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16841 13:40:03.032161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16843 13:40:03.078573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16844 13:40:03.079037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16846 13:40:03.114015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16847 13:40:03.114441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16849 13:40:03.154422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16850 13:40:03.154836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16852 13:40:03.190842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16853 13:40:03.191257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16855 13:40:03.228502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16857 13:40:03.228970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16858 13:40:03.263244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16859 13:40:03.263697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16861 13:40:03.298344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16862 13:40:03.298788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16864 13:40:03.332530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16866 13:40:03.333172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16867 13:40:03.366665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16869 13:40:03.367311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16870 13:40:03.400554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16872 13:40:03.401008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16873 13:40:03.435351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16874 13:40:03.435784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16876 13:40:03.469981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16877 13:40:03.470401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16879 13:40:03.503290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16880 13:40:03.503736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16882 13:40:03.536477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16884 13:40:03.536956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16885 13:40:03.570358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16887 13:40:03.570815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16888 13:40:03.603501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16890 13:40:03.603952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16891 13:40:03.637325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16892 13:40:03.637739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16894 13:40:03.670894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16896 13:40:03.671534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16897 13:40:03.703796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16898 13:40:03.704319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16900 13:40:03.737890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16901 13:40:03.738393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16903 13:40:03.783862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16905 13:40:03.784344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16906 13:40:03.820592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16908 13:40:03.821093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16909 13:40:03.855483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16910 13:40:03.855880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16912 13:40:03.888948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16913 13:40:03.889342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16915 13:40:03.922067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16917 13:40:03.922472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16918 13:40:03.955619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16919 13:40:03.956106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16921 13:40:03.989289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16923 13:40:03.989945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16924 13:40:04.022048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16926 13:40:04.022500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16927 13:40:04.055853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16928 13:40:04.056279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16930 13:40:04.088546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16932 13:40:04.089002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16933 13:40:04.121862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16934 13:40:04.122303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16936 13:40:04.154783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16937 13:40:04.155215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16939 13:40:04.187956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
16941 13:40:04.188413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
16942 13:40:04.221716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
16944 13:40:04.222163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
16945 13:40:04.254710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
16946 13:40:04.255125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
16948 13:40:04.288114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
16950 13:40:04.288753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
16951 13:40:04.321514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
16952 13:40:04.321942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
16954 13:40:04.355418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
16955 13:40:04.355837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
16957 13:40:04.389476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
16958 13:40:04.389922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
16960 13:40:04.422434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
16962 13:40:04.422885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
16963 13:40:04.455749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
16964 13:40:04.456193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
16966 13:40:04.489809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
16968 13:40:04.490445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
16969 13:40:04.523189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
16971 13:40:04.523622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
16972 13:40:04.555921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
16973 13:40:04.556337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
16975 13:40:04.589333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
16977 13:40:04.589807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
16978 13:40:04.622731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
16979 13:40:04.623209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
16981 13:40:04.657052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
16982 13:40:04.657547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
16984 13:40:04.690240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
16986 13:40:04.690830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
16987 13:40:04.723742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
16988 13:40:04.724204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
16990 13:40:04.757517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
16991 13:40:04.757988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
16993 13:40:04.789977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
16994 13:40:04.790459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
16996 13:40:04.823291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
16997 13:40:04.823767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
16999 13:40:04.857479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
17000 13:40:04.857924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
17002 13:40:04.891472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
17004 13:40:04.891926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
17005 13:40:04.924928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
17007 13:40:04.925380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
17008 13:40:04.958415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
17009 13:40:04.958862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
17011 13:40:04.992164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
17012 13:40:04.992588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
17014 13:40:05.025992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
17015 13:40:05.026404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
17017 13:40:05.059430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
17018 13:40:05.059822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
17020 13:40:05.093291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
17021 13:40:05.093678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
17023 13:40:05.126153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
17024 13:40:05.126553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
17026 13:40:05.159588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
17028 13:40:05.160132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
17029 13:40:05.193636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
17031 13:40:05.194217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
17032 13:40:05.226743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
17033 13:40:05.227172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
17035 13:40:05.262451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
17037 13:40:05.263176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
17038 13:40:05.296431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
17040 13:40:05.297167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
17041 13:40:05.329742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
17042 13:40:05.330188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
17044 13:40:05.371075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
17046 13:40:05.371575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
17047 13:40:05.404228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
17048 13:40:05.404643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
17050 13:40:05.437632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
17052 13:40:05.438077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
17053 13:40:05.471034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
17054 13:40:05.471460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
17056 13:40:05.503735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
17057 13:40:05.504140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
17059 13:40:05.537222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
17061 13:40:05.537658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
17062 13:40:05.569846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
17063 13:40:05.570244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
17065 13:40:05.603375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
17067 13:40:05.604004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
17068 13:40:05.637051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
17069 13:40:05.637510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
17071 13:40:05.669956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
17072 13:40:05.670337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
17074 13:40:05.703260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
17075 13:40:05.703649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
17077 13:40:05.737318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
17079 13:40:05.737763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
17080 13:40:05.769925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
17081 13:40:05.770289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
17083 13:40:05.802113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
17084 13:40:05.802536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
17086 13:40:05.835296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
17088 13:40:05.835722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
17089 13:40:05.867719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
17091 13:40:05.868142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
17092 13:40:05.900137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
17093 13:40:05.900538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
17095 13:40:05.934671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
17097 13:40:05.935103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
17098 13:40:05.967564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
17099 13:40:05.967950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
17101 13:40:06.000449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
17103 13:40:06.000855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
17104 13:40:06.033833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
17106 13:40:06.034246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
17107 13:40:06.066590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
17109 13:40:06.067051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
17110 13:40:06.100522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
17112 13:40:06.100931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
17113 13:40:06.134728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
17115 13:40:06.135117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
17116 13:40:06.167939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
17117 13:40:06.168310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
17119 13:40:06.201893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
17121 13:40:06.202498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
17122 13:40:06.235530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
17123 13:40:06.235952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
17125 13:40:06.269354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
17126 13:40:06.269675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
17128 13:40:06.302445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
17129 13:40:06.302878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
17131 13:40:06.336108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
17133 13:40:06.336495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
17134 13:40:06.369712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
17135 13:40:06.370115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
17137 13:40:06.402706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
17139 13:40:06.403113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
17140 13:40:06.436171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
17142 13:40:06.436580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
17143 13:40:06.470042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
17145 13:40:06.470799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
17146 13:40:06.504359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
17147 13:40:06.504774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
17149 13:40:06.538609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
17151 13:40:06.539037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
17152 13:40:06.572215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
17154 13:40:06.572665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
17155 13:40:06.607393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
17156 13:40:06.607862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
17158 13:40:06.641180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
17160 13:40:06.641773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
17161 13:40:06.675169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
17162 13:40:06.675605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
17164 13:40:06.709714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
17165 13:40:06.710137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
17167 13:40:06.742976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
17168 13:40:06.743357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
17170 13:40:06.777323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
17171 13:40:06.777681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
17173 13:40:06.810911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
17175 13:40:06.811266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
17176 13:40:06.845507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
17178 13:40:06.845982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
17179 13:40:06.879076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
17180 13:40:06.879515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
17182 13:40:06.912284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
17183 13:40:06.912719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
17185 13:40:06.945347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
17187 13:40:06.945813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
17188 13:40:06.978379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
17190 13:40:06.978956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
17191 13:40:07.011398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
17192 13:40:07.011901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
17194 13:40:07.045085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
17195 13:40:07.045554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
17197 13:40:07.078645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
17198 13:40:07.079116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
17200 13:40:07.112914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
17201 13:40:07.113393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
17203 13:40:07.146330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
17205 13:40:07.146878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
17206 13:40:07.179953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
17207 13:40:07.180437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
17209 13:40:07.212925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
17210 13:40:07.213367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
17212 13:40:07.245778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
17213 13:40:07.246204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
17215 13:40:07.278641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
17217 13:40:07.279098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
17218 13:40:07.311775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
17219 13:40:07.312188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
17221 13:40:07.346518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
17222 13:40:07.347009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
17224 13:40:07.380412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
17226 13:40:07.380992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
17227 13:40:07.413953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
17228 13:40:07.414422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
17230 13:40:07.447560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
17232 13:40:07.448118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
17233 13:40:07.481351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
17234 13:40:07.481854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
17236 13:40:07.514854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
17238 13:40:07.515413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
17239 13:40:07.547750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
17241 13:40:07.548304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
17242 13:40:07.581296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
17243 13:40:07.581765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
17245 13:40:07.615092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
17246 13:40:07.615504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
17248 13:40:07.648059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
17249 13:40:07.648488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
17251 13:40:07.681609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
17253 13:40:07.682065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
17254 13:40:07.715101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
17256 13:40:07.715732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
17257 13:40:07.748049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
17259 13:40:07.748674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
17260 13:40:07.781720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
17262 13:40:07.782314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
17263 13:40:07.813702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
17264 13:40:07.814171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
17266 13:40:07.846264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
17267 13:40:07.846657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
17269 13:40:07.879364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
17271 13:40:07.879959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
17272 13:40:07.912439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
17274 13:40:07.913037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
17275 13:40:07.945678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
17276 13:40:07.946166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
17278 13:40:07.978794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
17280 13:40:07.979351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
17281 13:40:08.011741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
17282 13:40:08.012229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
17284 13:40:08.044611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
17286 13:40:08.045216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
17287 13:40:08.077894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
17289 13:40:08.078465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
17290 13:40:08.110890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
17292 13:40:08.111476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
17293 13:40:08.143390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
17294 13:40:08.143831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
17296 13:40:08.176300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
17297 13:40:08.176727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
17299 13:40:08.209543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17301 13:40:08.210168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
17302 13:40:08.242388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17304 13:40:08.242964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17305 13:40:08.275413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17307 13:40:08.275971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17308 13:40:08.309515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17309 13:40:08.309957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17311 13:40:08.343652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17312 13:40:08.344072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17314 13:40:08.377884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17315 13:40:08.378414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17317 13:40:08.414067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17318 13:40:08.414514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17320 13:40:08.448269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17321 13:40:08.448752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17323 13:40:08.483383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17325 13:40:08.483854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17326 13:40:08.517587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17327 13:40:08.518113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17329 13:40:08.550872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17331 13:40:08.551520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17332 13:40:08.584252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17334 13:40:08.584727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17335 13:40:08.617610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17336 13:40:08.618050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17338 13:40:08.651064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17339 13:40:08.651467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17341 13:40:08.684904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17343 13:40:08.685344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17344 13:40:08.718314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17346 13:40:08.718782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17347 13:40:08.754672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17348 13:40:08.755137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17350 13:40:08.789071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17352 13:40:08.789768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17353 13:40:08.822597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17355 13:40:08.823190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17356 13:40:08.856254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17357 13:40:08.856709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17359 13:40:08.890083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17360 13:40:08.890527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17362 13:40:08.924483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17364 13:40:08.925088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17365 13:40:08.958997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17367 13:40:08.959451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17368 13:40:08.993414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17369 13:40:08.993896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17371 13:40:09.027027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17373 13:40:09.027627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17374 13:40:09.061398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17375 13:40:09.061889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17377 13:40:09.095137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17378 13:40:09.095600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17380 13:40:09.129217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17382 13:40:09.129777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17383 13:40:09.163761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17385 13:40:09.164322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17386 13:40:09.197952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17387 13:40:09.198426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17389 13:40:09.231908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17390 13:40:09.232428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17392 13:40:09.265969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17393 13:40:09.266436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17395 13:40:09.299885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17397 13:40:09.300360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17398 13:40:09.333881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17399 13:40:09.334300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17401 13:40:09.367296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17402 13:40:09.367740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17404 13:40:09.400977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17405 13:40:09.401439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17407 13:40:09.434795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17409 13:40:09.435376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17410 13:40:09.469235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17412 13:40:09.469849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17413 13:40:09.505267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17415 13:40:09.505896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17416 13:40:09.539333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17418 13:40:09.539795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17419 13:40:09.574606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17420 13:40:09.575081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17422 13:40:09.608899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17423 13:40:09.609289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17425 13:40:09.643140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17426 13:40:09.643554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17428 13:40:09.677725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17429 13:40:09.678181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17431 13:40:09.711579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17433 13:40:09.712041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17434 13:40:09.745502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17436 13:40:09.746098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17437 13:40:09.779912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17438 13:40:09.780380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17440 13:40:09.813633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17442 13:40:09.814208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17443 13:40:09.847384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17445 13:40:09.847898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17446 13:40:09.881223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17447 13:40:09.881683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17449 13:40:09.914480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17451 13:40:09.915071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17452 13:40:09.948170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17454 13:40:09.948761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17455 13:40:09.982308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17456 13:40:09.982852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17458 13:40:10.015741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17460 13:40:10.016436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17461 13:40:10.049516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17462 13:40:10.050013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17464 13:40:10.083615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17466 13:40:10.084068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17467 13:40:10.117328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17468 13:40:10.117756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17470 13:40:10.150635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17472 13:40:10.151088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17473 13:40:10.184025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17474 13:40:10.184482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17476 13:40:10.218096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17478 13:40:10.218646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17479 13:40:10.252881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17481 13:40:10.253420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17482 13:40:10.286385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17483 13:40:10.286945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17485 13:40:10.319680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17486 13:40:10.320131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17488 13:40:10.353692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17489 13:40:10.354134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17491 13:40:10.390841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17492 13:40:10.391309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17494 13:40:10.429608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17495 13:40:10.430048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17497 13:40:10.465188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17498 13:40:10.465607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17500 13:40:10.499627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17502 13:40:10.500242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17503 13:40:10.533439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17504 13:40:10.533933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17506 13:40:10.566467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17507 13:40:10.566926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17509 13:40:10.598916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17510 13:40:10.599353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17512 13:40:10.631938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17514 13:40:10.632371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17515 13:40:10.664827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17516 13:40:10.665262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17518 13:40:10.701443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17520 13:40:10.701862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17521 13:40:10.739769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17522 13:40:10.740199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17524 13:40:10.777252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17525 13:40:10.777690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17527 13:40:10.813009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17528 13:40:10.813511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17530 13:40:10.848873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17532 13:40:10.849310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17533 13:40:10.887316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17534 13:40:10.887725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17536 13:40:10.924345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17538 13:40:10.924787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17539 13:40:10.961345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17540 13:40:10.961838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17542 13:40:10.997151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17543 13:40:10.997656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17545 13:40:11.045270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17546 13:40:11.045822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17548 13:40:11.081721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17549 13:40:11.082182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17551 13:40:11.119577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17552 13:40:11.120070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17554 13:40:11.158128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17556 13:40:11.158764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17557 13:40:11.196060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17559 13:40:11.196754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17560 13:40:11.234243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17561 13:40:11.234766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17563 13:40:11.272571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17565 13:40:11.273142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17566 13:40:11.309208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17567 13:40:11.309655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17569 13:40:11.348053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17570 13:40:11.348508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17572 13:40:11.393038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17573 13:40:11.393508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17575 13:40:11.444257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17577 13:40:11.445013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17578 13:40:11.481298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17579 13:40:11.481873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17581 13:40:11.518619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17582 13:40:11.519046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17584 13:40:11.559921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17585 13:40:11.560312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17587 13:40:11.605898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17589 13:40:11.606329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17590 13:40:11.653323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17592 13:40:11.653699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17593 13:40:11.687603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17594 13:40:11.688103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17596 13:40:11.729634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17598 13:40:11.730344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17599 13:40:11.774254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17600 13:40:11.774714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17602 13:40:11.822832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17603 13:40:11.823230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17605 13:40:11.859147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17607 13:40:11.859629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17608 13:40:11.893410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17610 13:40:11.893906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17611 13:40:11.927616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17613 13:40:11.928214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17614 13:40:11.962309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17616 13:40:11.962897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17617 13:40:11.997392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17618 13:40:11.997833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17620 13:40:12.033518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17621 13:40:12.033973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17623 13:40:12.069713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17625 13:40:12.070196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17626 13:40:12.104990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17628 13:40:12.105638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17629 13:40:12.141632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17631 13:40:12.142112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17632 13:40:12.182307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17633 13:40:12.182786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17635 13:40:12.218906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17637 13:40:12.219491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17638 13:40:12.255091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17640 13:40:12.255706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17641 13:40:12.289716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17642 13:40:12.290159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17644 13:40:12.325282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17645 13:40:12.325685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17647 13:40:12.360931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17649 13:40:12.361388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17650 13:40:12.395932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17652 13:40:12.396540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17653 13:40:12.431514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17654 13:40:12.432022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17656 13:40:12.468573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17658 13:40:12.469039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17659 13:40:12.505521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17660 13:40:12.505955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17662 13:40:12.542002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17664 13:40:12.542580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17665 13:40:12.577382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17666 13:40:12.577819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17668 13:40:12.622333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17670 13:40:12.622796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17671 13:40:12.678096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17672 13:40:12.678575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17674 13:40:12.724304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17675 13:40:12.724752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17677 13:40:12.758006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17678 13:40:12.758398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17680 13:40:12.794048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17681 13:40:12.794471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17683 13:40:12.830819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17684 13:40:12.831263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17686 13:40:12.866782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17687 13:40:12.867215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17689 13:40:12.907915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17691 13:40:12.908574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17692 13:40:12.954409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17694 13:40:12.955051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17695 13:40:12.990958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17696 13:40:12.991522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17698 13:40:13.047153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17699 13:40:13.047597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17701 13:40:13.102273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17703 13:40:13.102741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17704 13:40:13.141478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17705 13:40:13.141917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17707 13:40:13.187410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17708 13:40:13.187843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17710 13:40:13.233763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17711 13:40:13.234192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17713 13:40:13.290355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17714 13:40:13.290813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17716 13:40:13.348719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17718 13:40:13.349267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17719 13:40:13.402354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17720 13:40:13.402786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17722 13:40:13.454220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17723 13:40:13.454664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17725 13:40:13.499782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17727 13:40:13.500268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17728 13:40:13.550628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17729 13:40:13.551057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17731 13:40:13.590487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17733 13:40:13.590956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17734 13:40:13.629009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17735 13:40:13.629466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17737 13:40:13.678462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17738 13:40:13.678894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17740 13:40:13.719067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17741 13:40:13.719523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17743 13:40:13.765426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17745 13:40:13.765908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17746 13:40:13.822311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17747 13:40:13.822776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17749 13:40:13.882091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17751 13:40:13.882570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17752 13:40:13.930078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17754 13:40:13.930565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17755 13:40:13.970857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17756 13:40:13.971287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17758 13:40:14.018637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17760 13:40:14.019112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17761 13:40:14.053791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17763 13:40:14.054365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17764 13:40:14.100709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17766 13:40:14.101395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17767 13:40:14.138416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17768 13:40:14.138831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17770 13:40:14.193563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17771 13:40:14.193976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17773 13:40:14.242317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17775 13:40:14.242751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17776 13:40:14.281987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17777 13:40:14.282369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17779 13:40:14.321379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17780 13:40:14.321827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17782 13:40:14.353593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17784 13:40:14.354070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17785 13:40:14.385673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17786 13:40:14.386117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17788 13:40:14.421254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17789 13:40:14.421690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17791 13:40:14.455964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17792 13:40:14.456423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17794 13:40:14.497318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17795 13:40:14.497760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17797 13:40:14.542907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17799 13:40:14.543571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17800 13:40:14.583713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17801 13:40:14.584160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17803 13:40:14.634761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17804 13:40:14.635193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17806 13:40:14.675946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17807 13:40:14.676380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17809 13:40:14.710712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17810 13:40:14.711153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17812 13:40:14.746008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17813 13:40:14.746457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17815 13:40:14.781591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17816 13:40:14.782036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17818 13:40:14.815401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17819 13:40:14.815852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17821 13:40:14.849370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17822 13:40:14.849823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17824 13:40:14.884336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17826 13:40:14.884855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17827 13:40:14.922114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17829 13:40:14.922609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17830 13:40:14.956152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17831 13:40:14.956575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17833 13:40:15.001565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17835 13:40:15.002061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17836 13:40:15.057534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17837 13:40:15.057937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17839 13:40:15.094847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17840 13:40:15.095269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17842 13:40:15.137457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17843 13:40:15.137892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17845 13:40:15.194793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17846 13:40:15.195185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17848 13:40:15.233739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17850 13:40:15.234166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17851 13:40:15.271016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17853 13:40:15.271600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17854 13:40:15.314403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17855 13:40:15.314833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17857 13:40:15.360010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17858 13:40:15.360472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17860 13:40:15.404610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17862 13:40:15.405770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17863 13:40:15.445421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17864 13:40:15.445884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17866 13:40:15.497911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17867 13:40:15.498359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17869 13:40:15.541417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17871 13:40:15.541906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17872 13:40:15.594663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17873 13:40:15.595172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17875 13:40:15.650580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17876 13:40:15.650986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17878 13:40:15.706222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17879 13:40:15.706674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17881 13:40:15.762192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17882 13:40:15.762623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17884 13:40:15.818744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17885 13:40:15.819340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17887 13:40:15.871329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17888 13:40:15.871796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17890 13:40:15.926086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17892 13:40:15.926564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17893 13:40:15.980370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17895 13:40:15.980892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17896 13:40:16.034216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17897 13:40:16.034664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17899 13:40:16.081217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17901 13:40:16.081863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17902 13:40:16.122745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17903 13:40:16.123200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17905 13:40:16.164138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17906 13:40:16.164539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17908 13:40:16.197620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17910 13:40:16.198088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17911 13:40:16.232543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17913 13:40:16.233025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17914 13:40:16.268952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17916 13:40:16.269432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17917 13:40:16.304866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17919 13:40:16.305337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17920 13:40:16.339627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17921 13:40:16.340051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17923 13:40:16.371325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17924 13:40:16.371744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17926 13:40:16.404271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17928 13:40:16.404634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17929 13:40:16.437903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17931 13:40:16.438291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17932 13:40:16.471917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17933 13:40:16.472357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17935 13:40:16.506016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17937 13:40:16.506556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17938 13:40:16.542053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17939 13:40:16.542523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
17941 13:40:16.579182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
17942 13:40:16.579648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
17944 13:40:16.612204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
17945 13:40:16.612629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
17947 13:40:16.648280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
17948 13:40:16.648706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
17950 13:40:16.682687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
17952 13:40:16.683148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
17953 13:40:16.716163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
17954 13:40:16.716641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
17956 13:40:16.750342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
17957 13:40:16.750784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
17959 13:40:16.785045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
17960 13:40:16.785464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
17962 13:40:16.818398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
17964 13:40:16.818908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
17965 13:40:16.852757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
17967 13:40:16.853225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
17968 13:40:16.888506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
17970 13:40:16.888978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
17971 13:40:16.923895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
17973 13:40:16.924364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
17974 13:40:16.959840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
17976 13:40:16.960287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
17977 13:40:16.997539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
17978 13:40:16.997988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
17980 13:40:17.033692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
17982 13:40:17.034253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
17983 13:40:17.069391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
17984 13:40:17.069856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
17986 13:40:17.104302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
17988 13:40:17.104796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
17989 13:40:17.139492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
17990 13:40:17.139918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
17992 13:40:17.177406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
17993 13:40:17.177868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
17995 13:40:17.234734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
17996 13:40:17.235172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
17998 13:40:17.280643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
18000 13:40:17.281132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
18001 13:40:17.329938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
18002 13:40:17.330380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
18004 13:40:17.383277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
18005 13:40:17.384059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
18007 13:40:17.431623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
18008 13:40:17.432084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
18010 13:40:17.476550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
18012 13:40:17.477045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
18013 13:40:17.518716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
18014 13:40:17.519208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
18016 13:40:17.562114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
18017 13:40:17.562537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
18019 13:40:17.614052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
18020 13:40:17.614469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
18022 13:40:17.655164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
18023 13:40:17.655612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
18025 13:40:17.695908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
18027 13:40:17.696387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
18028 13:40:17.733891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
18030 13:40:17.734365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
18031 13:40:17.778823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
18033 13:40:17.779481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
18034 13:40:17.833722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
18035 13:40:17.834220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
18037 13:40:17.873793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
18038 13:40:17.874227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
18040 13:40:17.913406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
18041 13:40:17.913937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
18043 13:40:17.970665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
18044 13:40:17.971116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
18046 13:40:18.012017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
18047 13:40:18.012496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
18049 13:40:18.065795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
18051 13:40:18.066258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
18052 13:40:18.105518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
18053 13:40:18.105977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
18055 13:40:18.146784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
18057 13:40:18.147267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
18058 13:40:18.193449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
18060 13:40:18.193950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
18061 13:40:18.233299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
18062 13:40:18.233760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
18064 13:40:18.274414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
18066 13:40:18.275004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
18067 13:40:18.315450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
18068 13:40:18.315926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
18070 13:40:18.361694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
18071 13:40:18.362142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
18073 13:40:18.418863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
18074 13:40:18.419408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
18076 13:40:18.469264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
18077 13:40:18.469760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
18079 13:40:18.506140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
18080 13:40:18.506571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
18082 13:40:18.564258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
18083 13:40:18.564729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
18085 13:40:18.602990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
18086 13:40:18.603458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
18088 13:40:18.644388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
18089 13:40:18.644911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
18091 13:40:18.690040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
18093 13:40:18.690536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
18094 13:40:18.739397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
18095 13:40:18.739841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
18097 13:40:18.787978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
18099 13:40:18.788440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
18100 13:40:18.833967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
18101 13:40:18.834401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
18103 13:40:18.874698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
18104 13:40:18.875129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
18106 13:40:18.914808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
18108 13:40:18.915270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
18109 13:40:18.953359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
18110 13:40:18.953832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
18112 13:40:18.991138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
18113 13:40:18.991559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
18115 13:40:19.041702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
18117 13:40:19.042432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
18118 13:40:19.090473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
18119 13:40:19.090940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
18121 13:40:19.146674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
18122 13:40:19.147113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
18124 13:40:19.193643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
18125 13:40:19.194085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
18127 13:40:19.235715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
18129 13:40:19.236192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
18130 13:40:19.277173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
18131 13:40:19.277590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
18133 13:40:19.315947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
18134 13:40:19.316373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
18136 13:40:19.356156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
18137 13:40:19.356725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
18139 13:40:19.397525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
18140 13:40:19.398224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
18142 13:40:19.438968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
18143 13:40:19.439466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
18145 13:40:19.487296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
18147 13:40:19.488436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
18148 13:40:19.546855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
18149 13:40:19.547290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
18151 13:40:19.597993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
18152 13:40:19.598454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
18154 13:40:19.636117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
18155 13:40:19.636560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
18157 13:40:19.681511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
18158 13:40:19.682068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
18160 13:40:19.727038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
18161 13:40:19.727477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
18163 13:40:19.766387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
18165 13:40:19.766867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
18166 13:40:19.805931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
18168 13:40:19.806312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
18169 13:40:19.853027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
18171 13:40:19.853787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
18172 13:40:19.886809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
18173 13:40:19.887310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
18175 13:40:19.921402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
18177 13:40:19.922179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
18178 13:40:19.957599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
18179 13:40:19.958164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
18181 13:40:19.997359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
18182 13:40:19.997913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
18184 13:40:20.036596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
18186 13:40:20.037124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
18187 13:40:20.075197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
18188 13:40:20.075589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
18190 13:40:20.112804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
18191 13:40:20.113250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
18193 13:40:20.147426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
18195 13:40:20.147885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
18196 13:40:20.189535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
18197 13:40:20.189975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
18199 13:40:20.228968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
18200 13:40:20.229474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
18202 13:40:20.265761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
18203 13:40:20.266142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
18205 13:40:20.307064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
18206 13:40:20.307473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
18208 13:40:20.348027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
18209 13:40:20.348490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
18211 13:40:20.402723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
18212 13:40:20.403109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
18214 13:40:20.455676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
18215 13:40:20.456119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
18217 13:40:20.498553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
18218 13:40:20.498992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
18220 13:40:20.536261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
18222 13:40:20.536726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
18223 13:40:20.575700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
18225 13:40:20.576154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
18226 13:40:20.609756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
18227 13:40:20.610301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
18229 13:40:20.649447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
18230 13:40:20.649946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
18232 13:40:20.688188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
18234 13:40:20.688759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
18235 13:40:20.726977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
18237 13:40:20.727728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
18238 13:40:20.761318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
18240 13:40:20.762031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
18241 13:40:20.798522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
18243 13:40:20.799099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
18244 13:40:20.833077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
18246 13:40:20.833479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
18247 13:40:20.867228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
18248 13:40:20.867776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
18250 13:40:20.901378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
18251 13:40:20.901944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
18253 13:40:20.936456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
18255 13:40:20.936936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
18256 13:40:20.974565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
18257 13:40:20.975029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
18259 13:40:21.019902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
18260 13:40:21.020372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
18262 13:40:21.054796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
18264 13:40:21.055464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
18265 13:40:21.088827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
18266 13:40:21.089280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
18268 13:40:21.131920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
18270 13:40:21.132496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
18271 13:40:21.172271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
18273 13:40:21.172815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
18274 13:40:21.211490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
18275 13:40:21.211871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
18277 13:40:21.250792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
18279 13:40:21.251361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
18280 13:40:21.285546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
18281 13:40:21.286006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
18283 13:40:21.321414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
18285 13:40:21.321878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
18286 13:40:21.355075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
18287 13:40:21.355486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
18289 13:40:21.395352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
18290 13:40:21.395787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
18292 13:40:21.430351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
18293 13:40:21.430792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
18295 13:40:21.463412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
18296 13:40:21.463879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
18298 13:40:21.497820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
18299 13:40:21.498208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
18301 13:40:21.530664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18302 13:40:21.531152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18304 13:40:21.563558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18306 13:40:21.563951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18307 13:40:21.594440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18308 13:40:21.594830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18310 13:40:21.630209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18312 13:40:21.630782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18313 13:40:21.662897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18315 13:40:21.663346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18316 13:40:21.700308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18318 13:40:21.700774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18319 13:40:21.734425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18320 13:40:21.734849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18322 13:40:21.768665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18323 13:40:21.769151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18325 13:40:21.806149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18326 13:40:21.806630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18328 13:40:21.840403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18329 13:40:21.840823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18331 13:40:21.875650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18332 13:40:21.876133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18334 13:40:21.908573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18336 13:40:21.909238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18337 13:40:21.942419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18338 13:40:21.942794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18340 13:40:21.974832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18341 13:40:21.975299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18343 13:40:22.009328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18344 13:40:22.009875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18346 13:40:22.042464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18347 13:40:22.042930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18349 13:40:22.076196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18351 13:40:22.076853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18352 13:40:22.108980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18353 13:40:22.109427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18355 13:40:22.141786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18356 13:40:22.142338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18358 13:40:22.178976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18359 13:40:22.179473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18361 13:40:22.218268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18362 13:40:22.218709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18364 13:40:22.262105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18365 13:40:22.262592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18367 13:40:22.297521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18368 13:40:22.298020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18370 13:40:22.338446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18371 13:40:22.338971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18373 13:40:22.378743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18374 13:40:22.379284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18376 13:40:22.416539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18378 13:40:22.417212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18379 13:40:22.450086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18380 13:40:22.450468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18382 13:40:22.484172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18384 13:40:22.484745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18385 13:40:22.521780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18387 13:40:22.522230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18388 13:40:22.559079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18389 13:40:22.559533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18391 13:40:22.597305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18392 13:40:22.597755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18394 13:40:22.637525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18395 13:40:22.638059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18397 13:40:22.675638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18399 13:40:22.676292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18400 13:40:22.714464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18401 13:40:22.714900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18403 13:40:22.757264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18405 13:40:22.757945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18406 13:40:22.790920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18408 13:40:22.791388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18409 13:40:22.823561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18411 13:40:22.823910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18412 13:40:22.857494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18413 13:40:22.858016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18415 13:40:22.895095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18416 13:40:22.895575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18418 13:40:22.930679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18419 13:40:22.931096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18421 13:40:22.968531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18423 13:40:22.969133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18424 13:40:23.005799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18425 13:40:23.006259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18427 13:40:23.048694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18429 13:40:23.049141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18430 13:40:23.083987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18431 13:40:23.084483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18433 13:40:23.127023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18435 13:40:23.127753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18436 13:40:23.170270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18438 13:40:23.170873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18439 13:40:23.207250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18440 13:40:23.207779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18442 13:40:23.242178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18443 13:40:23.242647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18445 13:40:23.278506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18447 13:40:23.279075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18448 13:40:23.319958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18450 13:40:23.320386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18451 13:40:23.374913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18452 13:40:23.375292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18454 13:40:23.412804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18455 13:40:23.413150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18457 13:40:23.450208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18458 13:40:23.450582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18460 13:40:23.486686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18462 13:40:23.487363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18463 13:40:23.525713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18464 13:40:23.526133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18466 13:40:23.559221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18468 13:40:23.559947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18469 13:40:23.593780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18470 13:40:23.594238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18472 13:40:23.628969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18474 13:40:23.629608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18475 13:40:23.686617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18476 13:40:23.687038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18478 13:40:23.723237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18480 13:40:23.723703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18481 13:40:23.759418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18482 13:40:23.759859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18484 13:40:23.795487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18485 13:40:23.795983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18487 13:40:23.831264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18489 13:40:23.831729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18490 13:40:23.867596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18492 13:40:23.868163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18493 13:40:23.902280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18494 13:40:23.902721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18496 13:40:23.936701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18498 13:40:23.937154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18499 13:40:23.971687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18501 13:40:23.972142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18502 13:40:24.006686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18503 13:40:24.007153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18505 13:40:24.043387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18506 13:40:24.043767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18508 13:40:24.077600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18509 13:40:24.077958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18511 13:40:24.112500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18513 13:40:24.112894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18514 13:40:24.147164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18515 13:40:24.147646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18517 13:40:24.181443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18519 13:40:24.182050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18520 13:40:24.216339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18521 13:40:24.216821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18523 13:40:24.252154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18525 13:40:24.252741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18526 13:40:24.285596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18527 13:40:24.285984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18529 13:40:24.317384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18530 13:40:24.317872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18532 13:40:24.353730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18533 13:40:24.354201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18535 13:40:24.389015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18536 13:40:24.389503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18538 13:40:24.421612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18540 13:40:24.422198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18541 13:40:24.465753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18542 13:40:24.466509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18544 13:40:24.503486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18546 13:40:24.504186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18547 13:40:24.550384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18548 13:40:24.550802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18550 13:40:24.585060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18552 13:40:24.585512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18553 13:40:24.618232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18554 13:40:24.618664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18556 13:40:24.657433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18557 13:40:24.657837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18559 13:40:24.689949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18560 13:40:24.690404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18562 13:40:24.721387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18563 13:40:24.721829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18565 13:40:24.753411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18567 13:40:24.754148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18568 13:40:24.795106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18569 13:40:24.795657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18571 13:40:24.834692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18572 13:40:24.835089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18574 13:40:24.874184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18575 13:40:24.874610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18577 13:40:24.919364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18578 13:40:24.919812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18580 13:40:24.956991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18582 13:40:24.957448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18583 13:40:24.999524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18584 13:40:24.999965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18586 13:40:25.044298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18588 13:40:25.044665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18589 13:40:25.093080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18590 13:40:25.093517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18592 13:40:25.135718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18593 13:40:25.136142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18595 13:40:25.177712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18596 13:40:25.178150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18598 13:40:25.225122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18599 13:40:25.225659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18601 13:40:25.266648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18603 13:40:25.267244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18604 13:40:25.310645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18606 13:40:25.311332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18607 13:40:25.349819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18608 13:40:25.350232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18610 13:40:25.394903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18611 13:40:25.395362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18613 13:40:25.435259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18615 13:40:25.435620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18616 13:40:25.477959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18617 13:40:25.478742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18619 13:40:25.525096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18620 13:40:25.525565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18622 13:40:25.565923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18623 13:40:25.566355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18625 13:40:25.601005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18626 13:40:25.601458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18628 13:40:25.636181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18629 13:40:25.636659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18631 13:40:25.673395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18633 13:40:25.673865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18634 13:40:25.713615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18635 13:40:25.714000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18637 13:40:25.748838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18638 13:40:25.749220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18640 13:40:25.783473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18641 13:40:25.783997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18643 13:40:25.817739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18645 13:40:25.818683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18646 13:40:25.852588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18648 13:40:25.853051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18649 13:40:25.884674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18650 13:40:25.885067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18652 13:40:25.916430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18654 13:40:25.917002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18655 13:40:25.947949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18656 13:40:25.948374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18658 13:40:25.979517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18659 13:40:25.979968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18661 13:40:26.015196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18663 13:40:26.015674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18664 13:40:26.056393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18665 13:40:26.056817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18667 13:40:26.102212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18668 13:40:26.102608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18670 13:40:26.139896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18671 13:40:26.140340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18673 13:40:26.186110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18675 13:40:26.186560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18676 13:40:26.222040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18678 13:40:26.222614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18679 13:40:26.259624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18681 13:40:26.260196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18682 13:40:26.299161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18683 13:40:26.299604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18685 13:40:26.341313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18686 13:40:26.341785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18688 13:40:26.378647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18689 13:40:26.379089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18691 13:40:26.412755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18692 13:40:26.413199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18694 13:40:26.446598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18695 13:40:26.447034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18697 13:40:26.482858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18698 13:40:26.483354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18700 13:40:26.524272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18701 13:40:26.524701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18703 13:40:26.560202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18705 13:40:26.560682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18706 13:40:26.599692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18708 13:40:26.600147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18709 13:40:26.642951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18710 13:40:26.643373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18712 13:40:26.677507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18713 13:40:26.677952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18715 13:40:26.721178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18716 13:40:26.721726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18718 13:40:26.772190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18720 13:40:26.772821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18721 13:40:26.813264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18723 13:40:26.813722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18724 13:40:26.849273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18726 13:40:26.849941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18727 13:40:26.885392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18729 13:40:26.886052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18730 13:40:26.920189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18731 13:40:26.920717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18733 13:40:26.954511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18734 13:40:26.955075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18736 13:40:26.987485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18738 13:40:26.988057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18739 13:40:27.021373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18740 13:40:27.021950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18742 13:40:27.056738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18744 13:40:27.057485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18745 13:40:27.089952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18747 13:40:27.090407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18748 13:40:27.125150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18750 13:40:27.125608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18751 13:40:27.159332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18753 13:40:27.159789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18754 13:40:27.193929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18755 13:40:27.194345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18757 13:40:27.229713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18759 13:40:27.230172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18760 13:40:27.264957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18761 13:40:27.265451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18763 13:40:27.299541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18765 13:40:27.300230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18766 13:40:27.339864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18767 13:40:27.340273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18769 13:40:27.391598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18770 13:40:27.392066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18772 13:40:27.433736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18773 13:40:27.434228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18775 13:40:27.468558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18777 13:40:27.469134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18778 13:40:27.503396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18780 13:40:27.503958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18781 13:40:27.542875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18782 13:40:27.543319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18784 13:40:27.585720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18785 13:40:27.586200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18787 13:40:27.619624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18788 13:40:27.620031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18790 13:40:27.653867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18792 13:40:27.654358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18793 13:40:27.687420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18794 13:40:27.687849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18796 13:40:27.720942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18798 13:40:27.721506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18799 13:40:27.755795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18800 13:40:27.756275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18802 13:40:27.789169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18803 13:40:27.789714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18805 13:40:27.821089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18807 13:40:27.821813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18808 13:40:27.854052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18809 13:40:27.854419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18811 13:40:27.893417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18813 13:40:27.893794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18814 13:40:27.926654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18815 13:40:27.926951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18817 13:40:27.961390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18819 13:40:27.961914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18820 13:40:27.995637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18821 13:40:27.996022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18823 13:40:28.030470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18824 13:40:28.030886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18826 13:40:28.065376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18827 13:40:28.065781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18829 13:40:28.109419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18830 13:40:28.109829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18832 13:40:28.145515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18833 13:40:28.145959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18835 13:40:28.177503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18836 13:40:28.177961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18838 13:40:28.208933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18839 13:40:28.209410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18841 13:40:28.239442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18843 13:40:28.239902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18844 13:40:28.275031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18846 13:40:28.275774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18847 13:40:28.320932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18848 13:40:28.321341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18850 13:40:28.360682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18852 13:40:28.361311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18853 13:40:28.399382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18855 13:40:28.400013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18856 13:40:28.439943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18857 13:40:28.440417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18859 13:40:28.474307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18861 13:40:28.474981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18862 13:40:28.511336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18863 13:40:28.511894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18865 13:40:28.547761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18866 13:40:28.548350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18868 13:40:28.582035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18869 13:40:28.582491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18871 13:40:28.619338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18873 13:40:28.619936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18874 13:40:28.650398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18876 13:40:28.650979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18877 13:40:28.681608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18878 13:40:28.682084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18880 13:40:28.713523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18882 13:40:28.713989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18883 13:40:28.747060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18885 13:40:28.747520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18886 13:40:28.793632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18887 13:40:28.794130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18889 13:40:28.834902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18890 13:40:28.835391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18892 13:40:28.866299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18894 13:40:28.866852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18895 13:40:28.897556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18897 13:40:28.898124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18898 13:40:28.929474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18899 13:40:28.929937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18901 13:40:28.961183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18903 13:40:28.961755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18904 13:40:28.992529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18906 13:40:28.993152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18907 13:40:29.024529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18909 13:40:29.025107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18910 13:40:29.057882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18911 13:40:29.058344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18913 13:40:29.094780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18915 13:40:29.095345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18916 13:40:29.131741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18918 13:40:29.132365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18919 13:40:29.167955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18920 13:40:29.168444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18922 13:40:29.206758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18923 13:40:29.207216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18925 13:40:29.242915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18926 13:40:29.243350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18928 13:40:29.281429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18929 13:40:29.281871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18931 13:40:29.321391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18932 13:40:29.321822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18934 13:40:29.362486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18935 13:40:29.362926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18937 13:40:29.398984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
18938 13:40:29.399535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18940 13:40:29.437773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
18941 13:40:29.438203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
18943 13:40:29.473732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
18945 13:40:29.474546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
18946 13:40:29.509291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
18947 13:40:29.509683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
18949 13:40:29.553507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
18951 13:40:29.554146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
18952 13:40:29.588600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
18954 13:40:29.589245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
18955 13:40:29.626898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
18957 13:40:29.627651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
18958 13:40:29.662888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
18959 13:40:29.663359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
18961 13:40:29.714783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
18962 13:40:29.715173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
18964 13:40:29.750347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
18966 13:40:29.750768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
18967 13:40:29.786736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
18969 13:40:29.787390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
18970 13:40:29.821773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
18971 13:40:29.822194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
18973 13:40:29.865885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
18974 13:40:29.866295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
18976 13:40:29.909717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
18977 13:40:29.910140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
18979 13:40:29.948090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
18980 13:40:29.948514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
18982 13:40:29.989617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
18984 13:40:29.990251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
18985 13:40:30.023020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
18987 13:40:30.023630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
18988 13:40:30.057807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
18990 13:40:30.058353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
18991 13:40:30.093412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
18993 13:40:30.093886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
18994 13:40:30.127941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
18995 13:40:30.128360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
18997 13:40:30.163146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
18999 13:40:30.163607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
19000 13:40:30.197819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
19001 13:40:30.198238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
19003 13:40:30.233302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
19004 13:40:30.233738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
19006 13:40:30.269593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
19007 13:40:30.270009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
19009 13:40:30.304235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
19010 13:40:30.304769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
19012 13:40:30.338549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
19014 13:40:30.339257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
19015 13:40:30.374866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
19017 13:40:30.375239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
19018 13:40:30.410305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
19019 13:40:30.410710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
19021 13:40:30.445570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
19022 13:40:30.445964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
19024 13:40:30.481617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
19026 13:40:30.482117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
19027 13:40:30.516901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
19028 13:40:30.517322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
19030 13:40:30.550757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
19032 13:40:30.551233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
19033 13:40:30.584938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
19034 13:40:30.585378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
19036 13:40:30.618240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
19037 13:40:30.618681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
19039 13:40:30.651996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
19041 13:40:30.652466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
19042 13:40:30.686345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
19044 13:40:30.686803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
19045 13:40:30.719655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
19047 13:40:30.720109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
19048 13:40:30.750730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
19049 13:40:30.751150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
19051 13:40:30.783064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
19052 13:40:30.783498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
19054 13:40:30.814618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
19055 13:40:30.815082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
19057 13:40:30.845389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
19059 13:40:30.845945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
19060 13:40:30.877236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
19062 13:40:30.877695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
19063 13:40:30.909775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
19065 13:40:30.910365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
19066 13:40:30.941721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
19068 13:40:30.942273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
19069 13:40:30.974253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
19071 13:40:30.974820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
19072 13:40:31.006275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
19074 13:40:31.006704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
19075 13:40:31.038207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
19077 13:40:31.038656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
19078 13:40:31.069911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
19080 13:40:31.070484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
19081 13:40:31.101916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
19082 13:40:31.102350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
19084 13:40:31.133544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
19086 13:40:31.134104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
19087 13:40:31.164927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
19088 13:40:31.165359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
19090 13:40:31.197151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
19092 13:40:31.197679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
19093 13:40:31.229064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
19094 13:40:31.229462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
19096 13:40:31.262592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
19097 13:40:31.263033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
19099 13:40:31.306416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
19100 13:40:31.306889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
19102 13:40:31.343823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
19103 13:40:31.344303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
19105 13:40:31.376001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
19106 13:40:31.376550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
19108 13:40:31.407147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
19109 13:40:31.407527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
19111 13:40:31.439750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
19112 13:40:31.440217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
19114 13:40:31.472029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
19115 13:40:31.472457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
19117 13:40:31.503562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
19119 13:40:31.504016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
19120 13:40:31.535928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
19122 13:40:31.536394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
19123 13:40:31.567801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
19125 13:40:31.568247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
19126 13:40:31.599916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
19128 13:40:31.600378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
19129 13:40:31.631522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
19130 13:40:31.632001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
19132 13:40:31.662648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
19134 13:40:31.663098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
19135 13:40:31.694339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
19137 13:40:31.694919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
19138 13:40:31.725933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
19140 13:40:31.726522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
19141 13:40:31.758141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
19143 13:40:31.758681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
19144 13:40:31.789499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
19145 13:40:31.789945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
19147 13:40:31.821584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
19148 13:40:31.822048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
19150 13:40:31.853037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
19151 13:40:31.853534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
19153 13:40:31.884059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
19154 13:40:31.884499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
19156 13:40:31.915831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
19157 13:40:31.916255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
19159 13:40:31.947208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
19161 13:40:31.947741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
19162 13:40:31.978093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
19164 13:40:31.978619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
19165 13:40:32.010384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
19166 13:40:32.010823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
19168 13:40:32.043382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
19170 13:40:32.044121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
19171 13:40:32.074380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
19172 13:40:32.074797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
19174 13:40:32.105794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
19175 13:40:32.106210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
19177 13:40:32.137428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
19178 13:40:32.137881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
19180 13:40:32.169027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
19181 13:40:32.169522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
19183 13:40:32.199933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
19184 13:40:32.200390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
19186 13:40:32.239089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
19187 13:40:32.239576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
19189 13:40:32.280778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
19191 13:40:32.281522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
19192 13:40:32.315081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
19193 13:40:32.315449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
19195 13:40:32.349506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
19196 13:40:32.350013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
19198 13:40:32.391619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
19199 13:40:32.392158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
19201 13:40:32.425156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
19202 13:40:32.425641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
19204 13:40:32.458820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
19205 13:40:32.459293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
19207 13:40:32.493738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
19208 13:40:32.494192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
19210 13:40:32.526385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
19211 13:40:32.526805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
19213 13:40:32.558487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
19214 13:40:32.558912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
19216 13:40:32.590379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
19217 13:40:32.590883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
19219 13:40:32.622705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
19220 13:40:32.623167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
19222 13:40:32.654441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
19224 13:40:32.654895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
19225 13:40:32.686399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
19227 13:40:32.686847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
19228 13:40:32.727200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
19230 13:40:32.727939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
19231 13:40:32.776066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
19232 13:40:32.776516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
19234 13:40:32.813716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
19235 13:40:32.814125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
19237 13:40:32.848769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
19238 13:40:32.849195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
19240 13:40:32.881437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
19241 13:40:32.881868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
19243 13:40:32.913430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
19244 13:40:32.913812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
19246 13:40:32.945493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
19247 13:40:32.945894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
19249 13:40:32.977707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
19250 13:40:32.978103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
19252 13:40:33.009555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
19253 13:40:33.009956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
19255 13:40:33.041304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
19257 13:40:33.041728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
19258 13:40:33.074024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
19259 13:40:33.074444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
19261 13:40:33.106887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
19262 13:40:33.107365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
19264 13:40:33.138687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
19265 13:40:33.139105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
19267 13:40:33.170475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
19269 13:40:33.170982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
19270 13:40:33.201763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
19272 13:40:33.202201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
19273 13:40:33.232811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
19274 13:40:33.233193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
19276 13:40:33.263551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
19277 13:40:33.263961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
19279 13:40:33.295374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
19280 13:40:33.295766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
19282 13:40:33.326685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
19283 13:40:33.327050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
19285 13:40:33.361066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
19287 13:40:33.361493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
19288 13:40:33.392744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
19289 13:40:33.393152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
19291 13:40:33.424223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
19292 13:40:33.424599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
19294 13:40:33.455662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
19295 13:40:33.456095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
19297 13:40:33.487307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
19298 13:40:33.487711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
19300 13:40:33.518715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19301 13:40:33.519101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19303 13:40:33.550762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19304 13:40:33.551161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19306 13:40:33.582446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19308 13:40:33.583039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19309 13:40:33.613481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19311 13:40:33.614038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19312 13:40:33.643994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19313 13:40:33.644424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19315 13:40:33.674840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19316 13:40:33.675266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19318 13:40:33.706351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19320 13:40:33.706947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19321 13:40:33.737384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19323 13:40:33.737977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19324 13:40:33.767989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19325 13:40:33.768423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19327 13:40:33.799111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19329 13:40:33.799704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19330 13:40:33.832503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19332 13:40:33.833122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19333 13:40:33.866982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19335 13:40:33.867550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19336 13:40:33.913864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19337 13:40:33.914272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19339 13:40:33.956822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19340 13:40:33.957258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19342 13:40:33.989249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19343 13:40:33.989688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19345 13:40:34.021696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19346 13:40:34.022138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19348 13:40:34.054363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19349 13:40:34.054798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19351 13:40:34.086997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19352 13:40:34.087366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19354 13:40:34.118783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19356 13:40:34.119136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19357 13:40:34.154578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19358 13:40:34.155055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19360 13:40:34.189335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19361 13:40:34.189813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19363 13:40:34.221730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19364 13:40:34.222184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19366 13:40:34.268021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19368 13:40:34.268531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19369 13:40:34.300179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19370 13:40:34.300606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19372 13:40:34.333524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19374 13:40:34.334063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19375 13:40:34.364224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19376 13:40:34.364619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19378 13:40:34.395817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19380 13:40:34.396348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19381 13:40:34.427109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19382 13:40:34.427505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19384 13:40:34.458606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19386 13:40:34.459054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19387 13:40:34.494307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19388 13:40:34.494708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19390 13:40:34.526959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19392 13:40:34.527431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19393 13:40:34.567275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19394 13:40:34.567708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19396 13:40:34.599069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19397 13:40:34.599506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19399 13:40:34.633016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19400 13:40:34.633502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19402 13:40:34.667704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19404 13:40:34.668070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19405 13:40:34.700921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19406 13:40:34.701407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19408 13:40:34.733896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19409 13:40:34.734365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19411 13:40:34.770304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19412 13:40:34.770809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19414 13:40:34.810119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19416 13:40:34.810574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19417 13:40:34.841992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19418 13:40:34.842377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19420 13:40:34.874614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19421 13:40:34.875020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19423 13:40:34.906984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19424 13:40:34.907397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19426 13:40:34.939680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19427 13:40:34.940089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19429 13:40:34.972150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19430 13:40:34.972630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19432 13:40:35.005074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19433 13:40:35.005570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19435 13:40:35.036068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19436 13:40:35.036491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19438 13:40:35.068286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19439 13:40:35.068708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19441 13:40:35.100426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19442 13:40:35.100968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19444 13:40:35.133852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19445 13:40:35.134315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19447 13:40:35.166452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19448 13:40:35.166897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19450 13:40:35.199650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19451 13:40:35.200116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19453 13:40:35.232739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19454 13:40:35.233208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19456 13:40:35.267341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19458 13:40:35.267768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19459 13:40:35.298793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19461 13:40:35.299156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19462 13:40:35.329972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19463 13:40:35.330428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19465 13:40:35.361296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19466 13:40:35.361774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19468 13:40:35.393985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19470 13:40:35.394562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19471 13:40:35.425727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19473 13:40:35.426286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19474 13:40:35.460734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19476 13:40:35.461284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19477 13:40:35.496123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19478 13:40:35.496596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19480 13:40:35.532182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19481 13:40:35.532719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19483 13:40:35.567250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19485 13:40:35.567900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19486 13:40:35.599903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19488 13:40:35.600537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19489 13:40:35.631445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19490 13:40:35.631923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19492 13:40:35.663766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19494 13:40:35.664507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19495 13:40:35.697308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19496 13:40:35.697787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19498 13:40:35.729731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19499 13:40:35.730164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19501 13:40:35.761822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19503 13:40:35.762368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19504 13:40:35.794427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19506 13:40:35.795105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19507 13:40:35.825632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19509 13:40:35.826213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19510 13:40:35.857434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19511 13:40:35.857923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19513 13:40:35.889703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19514 13:40:35.890154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19516 13:40:35.921550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19518 13:40:35.922133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19519 13:40:35.953355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19520 13:40:35.953824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19522 13:40:35.985890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19524 13:40:35.986518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19525 13:40:36.017909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19526 13:40:36.018388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19528 13:40:36.049596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19530 13:40:36.050152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19531 13:40:36.081715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19533 13:40:36.082291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19534 13:40:36.114423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19536 13:40:36.114876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19537 13:40:36.146011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19538 13:40:36.146484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19540 13:40:36.177922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19542 13:40:36.178527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19543 13:40:36.222723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19544 13:40:36.223270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19546 13:40:36.255682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19547 13:40:36.256155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19549 13:40:36.289320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19550 13:40:36.289831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19552 13:40:36.321802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19554 13:40:36.322401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19555 13:40:36.354031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19557 13:40:36.354605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19558 13:40:36.386185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19559 13:40:36.386677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19561 13:40:36.419877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19562 13:40:36.420345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19564 13:40:36.452141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19566 13:40:36.452693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19567 13:40:36.484281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19569 13:40:36.484893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19570 13:40:36.517264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19571 13:40:36.517826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19573 13:40:36.550190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19574 13:40:36.550673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19576 13:40:36.583586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19577 13:40:36.584014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19579 13:40:36.617365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19581 13:40:36.617918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19582 13:40:36.650609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19583 13:40:36.651046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19585 13:40:36.683468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19586 13:40:36.683880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19588 13:40:36.717012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19590 13:40:36.717436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19591 13:40:36.749347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19593 13:40:36.749916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19594 13:40:36.780199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19596 13:40:36.780740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19597 13:40:36.811143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19599 13:40:36.811662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19600 13:40:36.841659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19602 13:40:36.842217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19603 13:40:36.872459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19605 13:40:36.872999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19606 13:40:36.903302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19607 13:40:36.903726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19609 13:40:36.934476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19611 13:40:36.934986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19612 13:40:36.965457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19613 13:40:36.965894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19615 13:40:36.995981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19616 13:40:36.996463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19618 13:40:37.029112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19620 13:40:37.029583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19621 13:40:37.060466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19623 13:40:37.060902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19624 13:40:37.091300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19626 13:40:37.091705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19627 13:40:37.122603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19628 13:40:37.122969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19630 13:40:37.153954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19631 13:40:37.154347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19633 13:40:37.184610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19635 13:40:37.185047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19636 13:40:37.215290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19638 13:40:37.215688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19639 13:40:37.246523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19640 13:40:37.246898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19642 13:40:37.277203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19643 13:40:37.277573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19645 13:40:37.308114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19647 13:40:37.308674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19648 13:40:37.339548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19650 13:40:37.340175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19651 13:40:37.370077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19652 13:40:37.370498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19654 13:40:37.400748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19656 13:40:37.401309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19657 13:40:37.431839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19658 13:40:37.432278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19660 13:40:37.463008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19662 13:40:37.463573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19663 13:40:37.493710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19664 13:40:37.494151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19666 13:40:37.525373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19667 13:40:37.525823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19669 13:40:37.557245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19670 13:40:37.557701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19672 13:40:37.588150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19673 13:40:37.588613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19675 13:40:37.618912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19677 13:40:37.619480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19678 13:40:37.650588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19680 13:40:37.651161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19681 13:40:37.681661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19683 13:40:37.682119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19684 13:40:37.713030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19685 13:40:37.713391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19687 13:40:37.745037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19688 13:40:37.745476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19690 13:40:37.776043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19691 13:40:37.776414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19693 13:40:37.806171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19695 13:40:37.806579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19696 13:40:37.836904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19698 13:40:37.837521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19699 13:40:37.867965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19700 13:40:37.868422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19702 13:40:37.898722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19703 13:40:37.899153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19705 13:40:37.929691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19707 13:40:37.930428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19708 13:40:37.962798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19710 13:40:37.963491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19711 13:40:37.994986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19712 13:40:37.995479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19714 13:40:38.026138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19715 13:40:38.026585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19717 13:40:38.057658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19718 13:40:38.058115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19720 13:40:38.089283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19721 13:40:38.089689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19723 13:40:38.120584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19725 13:40:38.121124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19726 13:40:38.151861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19728 13:40:38.152406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19729 13:40:38.182998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19730 13:40:38.183461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19732 13:40:38.213981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19734 13:40:38.214539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19735 13:40:38.244633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19737 13:40:38.245061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19738 13:40:38.275506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19739 13:40:38.275890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19741 13:40:38.306541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19742 13:40:38.306906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19744 13:40:38.337430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19746 13:40:38.337916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19747 13:40:38.368623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19749 13:40:38.369064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19750 13:40:38.400424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19752 13:40:38.400918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19753 13:40:38.431882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19755 13:40:38.432292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19756 13:40:38.462466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19758 13:40:38.463050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19759 13:40:38.494231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19761 13:40:38.494796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19762 13:40:38.527086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19764 13:40:38.527655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19765 13:40:38.558627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19767 13:40:38.559071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19768 13:40:38.590236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19769 13:40:38.590647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19771 13:40:38.621625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19772 13:40:38.622038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19774 13:40:38.653415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19775 13:40:38.653894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19777 13:40:38.687626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19778 13:40:38.688107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19780 13:40:38.720679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19782 13:40:38.721305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19783 13:40:38.752913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19784 13:40:38.753371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19786 13:40:38.784923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19788 13:40:38.785548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19789 13:40:38.815652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19791 13:40:38.816263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19792 13:40:38.846469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19793 13:40:38.847002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19795 13:40:38.877513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19797 13:40:38.878085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19798 13:40:38.908696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19800 13:40:38.909242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19801 13:40:38.942308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19802 13:40:38.942738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19804 13:40:38.973640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19805 13:40:38.974020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19807 13:40:39.005461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19809 13:40:39.006041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19810 13:40:39.055474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19812 13:40:39.056026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19813 13:40:39.086950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19815 13:40:39.087490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19816 13:40:39.118522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19817 13:40:39.118998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19819 13:40:39.149794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19820 13:40:39.150259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19822 13:40:39.182545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19824 13:40:39.183266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19825 13:40:39.213813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19827 13:40:39.214358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19828 13:40:39.244871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19830 13:40:39.245426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19831 13:40:39.275521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19832 13:40:39.275989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19834 13:40:39.306314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19835 13:40:39.306737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19837 13:40:39.337504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19838 13:40:39.338011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19840 13:40:39.367889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19841 13:40:39.368322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19843 13:40:39.398536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19844 13:40:39.398961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19846 13:40:39.429607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19847 13:40:39.430067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19849 13:40:39.459749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19850 13:40:39.460201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19852 13:40:39.490514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19853 13:40:39.490953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19855 13:40:39.521407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19856 13:40:39.521906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19858 13:40:39.552386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19860 13:40:39.552936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19861 13:40:39.583492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19863 13:40:39.584072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19864 13:40:39.613877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19866 13:40:39.614455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19867 13:40:39.644977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19869 13:40:39.645538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19870 13:40:39.675591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19872 13:40:39.676162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19873 13:40:39.707579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19875 13:40:39.708150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19876 13:40:39.740584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19878 13:40:39.741134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19879 13:40:39.777060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19880 13:40:39.777535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19882 13:40:39.810739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19883 13:40:39.811186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19885 13:40:39.843934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19886 13:40:39.844406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19888 13:40:39.877536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19890 13:40:39.878132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19891 13:40:39.911907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19892 13:40:39.912343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19894 13:40:39.947313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19896 13:40:39.948035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19897 13:40:39.982601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19898 13:40:39.982976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19900 13:40:40.015226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19901 13:40:40.015615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19903 13:40:40.047436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19904 13:40:40.047926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19906 13:40:40.081346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19908 13:40:40.082005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19909 13:40:40.115650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19910 13:40:40.116128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19912 13:40:40.149731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19913 13:40:40.150195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19915 13:40:40.183731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19916 13:40:40.184169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19918 13:40:40.220853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19919 13:40:40.221282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19921 13:40:40.253850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19922 13:40:40.254245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19924 13:40:40.286529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19926 13:40:40.287061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19927 13:40:40.320288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19929 13:40:40.320712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19930 13:40:40.353938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19932 13:40:40.354439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19933 13:40:40.387382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19934 13:40:40.387773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19936 13:40:40.430737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19938 13:40:40.431320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19939 13:40:40.485174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
19941 13:40:40.485772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
19942 13:40:40.520518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
19944 13:40:40.521043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
19945 13:40:40.558589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
19946 13:40:40.559039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
19948 13:40:40.602111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
19949 13:40:40.602608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
19951 13:40:40.635614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
19952 13:40:40.636042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
19954 13:40:40.669411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
19956 13:40:40.669861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
19957 13:40:40.702219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
19958 13:40:40.702669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
19960 13:40:40.733316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
19961 13:40:40.733818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
19963 13:40:40.763960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
19964 13:40:40.764377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
19966 13:40:40.794787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
19968 13:40:40.795516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
19969 13:40:40.826609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
19970 13:40:40.827157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
19972 13:40:40.858445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
19973 13:40:40.858880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
19975 13:40:40.891734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
19977 13:40:40.892189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
19978 13:40:40.924145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
19980 13:40:40.924777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
19981 13:40:40.957769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
19982 13:40:40.958307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
19984 13:40:40.991652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
19985 13:40:40.992199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
19987 13:40:41.025248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
19988 13:40:41.025707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
19990 13:40:41.058868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
19991 13:40:41.059334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
19993 13:40:41.093798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
19994 13:40:41.094258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
19996 13:40:41.126368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
19997 13:40:41.126841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
19999 13:40:41.159585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
20000 13:40:41.160059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
20002 13:40:41.193261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
20003 13:40:41.193773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
20005 13:40:41.226400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
20006 13:40:41.226831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
20008 13:40:41.258593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
20010 13:40:41.259049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
20011 13:40:41.292053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
20012 13:40:41.292439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
20014 13:40:41.325113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
20015 13:40:41.325548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
20017 13:40:41.357269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
20018 13:40:41.357689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
20020 13:40:41.389043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
20021 13:40:41.389542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
20023 13:40:41.421449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
20024 13:40:41.421941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
20026 13:40:41.451800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
20028 13:40:41.452320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
20029 13:40:41.482887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
20030 13:40:41.483304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
20032 13:40:41.515876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
20033 13:40:41.516294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
20035 13:40:41.547357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
20037 13:40:41.547796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
20038 13:40:41.578359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
20039 13:40:41.578751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
20041 13:40:41.609343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
20042 13:40:41.609681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
20044 13:40:41.639693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
20045 13:40:41.640134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
20047 13:40:41.670340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
20048 13:40:41.670768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
20050 13:40:41.701859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
20052 13:40:41.702441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
20053 13:40:41.733957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
20055 13:40:41.734554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
20056 13:40:41.765848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
20057 13:40:41.766317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
20059 13:40:41.797105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
20060 13:40:41.797532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
20062 13:40:41.828189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
20064 13:40:41.828778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
20065 13:40:41.859266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
20067 13:40:41.859805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
20068 13:40:41.890298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
20070 13:40:41.890731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
20071 13:40:41.923423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
20072 13:40:41.923852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
20074 13:40:41.955156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
20075 13:40:41.955551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
20077 13:40:41.985953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
20079 13:40:41.986376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
20080 13:40:42.017908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
20082 13:40:42.018460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
20083 13:40:42.049386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
20085 13:40:42.049969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
20086 13:40:42.080224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
20087 13:40:42.080691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
20089 13:40:42.111836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
20091 13:40:42.112423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
20092 13:40:42.143087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
20093 13:40:42.143546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
20095 13:40:42.174503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
20096 13:40:42.174971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
20098 13:40:42.205598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
20100 13:40:42.206124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
20101 13:40:42.237549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
20103 13:40:42.238088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
20104 13:40:42.269340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
20106 13:40:42.269867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
20107 13:40:42.301082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
20109 13:40:42.301563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
20110 13:40:42.332915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
20111 13:40:42.333328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
20113 13:40:42.362994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
20114 13:40:42.363367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
20116 13:40:42.393558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
20117 13:40:42.394033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
20119 13:40:42.425001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
20120 13:40:42.425453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
20122 13:40:42.456261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
20124 13:40:42.456719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
20125 13:40:42.487812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
20127 13:40:42.488283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
20128 13:40:42.518566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
20129 13:40:42.518971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
20131 13:40:42.550357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
20133 13:40:42.550986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
20134 13:40:42.584099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
20136 13:40:42.584737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
20137 13:40:42.616768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
20138 13:40:42.617244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
20140 13:40:42.648565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
20142 13:40:42.649152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
20143 13:40:42.679995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
20145 13:40:42.680609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
20146 13:40:42.711706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
20147 13:40:42.712157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
20149 13:40:42.743915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
20151 13:40:42.744546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
20152 13:40:42.775339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
20154 13:40:42.775966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
20155 13:40:42.806058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
20156 13:40:42.806506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
20158 13:40:42.837788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
20160 13:40:42.838408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
20161 13:40:42.869185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
20162 13:40:42.869671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
20164 13:40:42.901512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
20165 13:40:42.901993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
20167 13:40:42.934051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
20168 13:40:42.934505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
20170 13:40:42.965704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
20171 13:40:42.966140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
20173 13:40:42.996245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
20175 13:40:42.996766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
20176 13:40:43.027463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
20178 13:40:43.027952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
20179 13:40:43.058738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
20181 13:40:43.059364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
20182 13:40:43.089705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
20183 13:40:43.090106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
20185 13:40:43.120997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
20187 13:40:43.121503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
20188 13:40:43.151863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
20189 13:40:43.152290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
20191 13:40:43.183196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
20193 13:40:43.183691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
20194 13:40:43.214664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
20195 13:40:43.215065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
20197 13:40:43.245494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
20198 13:40:43.245996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
20200 13:40:43.277126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
20202 13:40:43.277657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
20203 13:40:43.309048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
20205 13:40:43.309582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
20206 13:40:43.340204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
20208 13:40:43.340744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
20209 13:40:43.370722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
20210 13:40:43.371209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
20212 13:40:43.401464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
20213 13:40:43.401958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
20215 13:40:43.434923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
20216 13:40:43.435400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
20218 13:40:43.467804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
20219 13:40:43.468282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
20221 13:40:43.502510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
20223 13:40:43.502969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
20224 13:40:43.535816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
20225 13:40:43.536296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
20227 13:40:43.570251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
20228 13:40:43.570676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
20230 13:40:43.604006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
20231 13:40:43.604395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
20233 13:40:43.638950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
20235 13:40:43.639409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
20236 13:40:43.673278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
20238 13:40:43.673740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
20239 13:40:43.719457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
20240 13:40:43.719907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
20242 13:40:43.763908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
20243 13:40:43.764399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
20245 13:40:43.797694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
20246 13:40:43.798156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
20248 13:40:43.837801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
20249 13:40:43.838287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
20251 13:40:43.875608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
20253 13:40:43.876177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
20254 13:40:43.907430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
20255 13:40:43.907859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
20257 13:40:43.938291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
20258 13:40:43.938724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
20260 13:40:43.969250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
20262 13:40:43.969681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
20263 13:40:44.001503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
20265 13:40:44.002092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
20266 13:40:44.032710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
20268 13:40:44.033254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
20269 13:40:44.063358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
20271 13:40:44.063930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
20272 13:40:44.097706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
20274 13:40:44.098079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
20275 13:40:44.129450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
20276 13:40:44.129849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
20278 13:40:44.176975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
20280 13:40:44.177518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
20281 13:40:44.207962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
20283 13:40:44.208468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
20284 13:40:44.238891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
20285 13:40:44.239304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
20287 13:40:44.269635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
20288 13:40:44.270072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
20290 13:40:44.301442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
20291 13:40:44.301889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
20293 13:40:44.331819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
20295 13:40:44.332226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
20296 13:40:44.362678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
20298 13:40:44.363085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
20299 13:40:44.393495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
20300 13:40:44.393868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20302 13:40:44.424214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20303 13:40:44.424592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20305 13:40:44.454578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20306 13:40:44.454941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20308 13:40:44.485437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20309 13:40:44.485823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20311 13:40:44.516847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20312 13:40:44.517260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20314 13:40:44.547421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20315 13:40:44.547818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20317 13:40:44.578499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20319 13:40:44.579023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20320 13:40:44.609427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20321 13:40:44.609856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20323 13:40:44.640085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20324 13:40:44.640528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20326 13:40:44.670664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20328 13:40:44.671222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20329 13:40:44.701454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20331 13:40:44.702007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20332 13:40:44.732684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20334 13:40:44.733294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20335 13:40:44.763026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20336 13:40:44.763454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20338 13:40:44.793732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20339 13:40:44.794165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20341 13:40:44.825699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20343 13:40:44.826286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20344 13:40:44.855894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20346 13:40:44.856476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20347 13:40:44.886100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20349 13:40:44.886656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20350 13:40:44.917522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20352 13:40:44.918160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20353 13:40:44.948176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20355 13:40:44.948730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20356 13:40:44.978725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20358 13:40:44.979256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20359 13:40:45.010352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20360 13:40:45.010800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20362 13:40:45.042116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20364 13:40:45.042662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20365 13:40:45.072725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20366 13:40:45.073145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20368 13:40:45.103712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20369 13:40:45.104188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20371 13:40:45.135671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20372 13:40:45.136091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20374 13:40:45.169088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20375 13:40:45.169425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20377 13:40:45.200059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20379 13:40:45.200618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20380 13:40:45.231109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20381 13:40:45.231563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20383 13:40:45.263011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20384 13:40:45.263470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20386 13:40:45.294061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20387 13:40:45.294465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20389 13:40:45.325912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20391 13:40:45.326476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20392 13:40:45.358447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20393 13:40:45.358903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20395 13:40:45.393343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20397 13:40:45.393913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20398 13:40:45.429724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20399 13:40:45.430190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20401 13:40:45.461368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20402 13:40:45.461852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20404 13:40:45.492940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20405 13:40:45.493358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20407 13:40:45.524584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20409 13:40:45.525117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20410 13:40:45.560092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20411 13:40:45.560481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20413 13:40:45.593806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20414 13:40:45.594190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20416 13:40:45.625682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20417 13:40:45.626135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20419 13:40:45.657442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20420 13:40:45.657938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20422 13:40:45.688278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20423 13:40:45.688743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20425 13:40:45.719491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20426 13:40:45.719920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20428 13:40:45.753784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20429 13:40:45.754163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20431 13:40:45.786300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20432 13:40:45.786775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20434 13:40:45.817925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20435 13:40:45.818364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20437 13:40:45.850185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20438 13:40:45.850604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20440 13:40:45.881522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20442 13:40:45.881974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20443 13:40:45.911848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20444 13:40:45.912273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20446 13:40:45.943947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20448 13:40:45.944506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20449 13:40:45.975347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20450 13:40:45.975825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20452 13:40:46.007114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20454 13:40:46.007671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20455 13:40:46.039073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20457 13:40:46.039529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20458 13:40:46.070778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20459 13:40:46.071241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20461 13:40:46.102473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20463 13:40:46.103023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20464 13:40:46.134343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20466 13:40:46.134934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20467 13:40:46.166308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20468 13:40:46.166760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20470 13:40:46.199448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20471 13:40:46.199895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20473 13:40:46.230819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20474 13:40:46.231292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20476 13:40:46.262258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20477 13:40:46.262695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20479 13:40:46.293740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20480 13:40:46.294214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20482 13:40:46.325007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20483 13:40:46.325407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20485 13:40:46.355798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20486 13:40:46.356231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20488 13:40:46.388132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20490 13:40:46.388590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20491 13:40:46.419836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20492 13:40:46.420261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20494 13:40:46.451445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20495 13:40:46.451846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20497 13:40:46.482758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20498 13:40:46.483241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20500 13:40:46.515567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20502 13:40:46.516208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20503 13:40:46.547199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20505 13:40:46.547820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20506 13:40:46.578734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20508 13:40:46.579283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20509 13:40:46.611994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20510 13:40:46.612418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20512 13:40:46.646221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20513 13:40:46.646639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20515 13:40:46.678005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20516 13:40:46.678414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20518 13:40:46.711261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20520 13:40:46.711829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20521 13:40:46.742875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20522 13:40:46.743337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20524 13:40:46.775564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20525 13:40:46.775975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20527 13:40:46.807423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20528 13:40:46.807877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20530 13:40:46.839667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20532 13:40:46.840228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20533 13:40:46.871510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20534 13:40:46.871967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20536 13:40:46.903383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20538 13:40:46.903937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20539 13:40:46.935059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20541 13:40:46.935634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20542 13:40:46.967100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20543 13:40:46.967504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20545 13:40:46.998515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20546 13:40:46.998987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20548 13:40:47.030938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20550 13:40:47.031566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20551 13:40:47.063644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20553 13:40:47.064228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20554 13:40:47.094550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20556 13:40:47.095089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20557 13:40:47.126278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20558 13:40:47.126743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20560 13:40:47.157860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20562 13:40:47.158294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20563 13:40:47.189523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20564 13:40:47.189938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20566 13:40:47.222033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20567 13:40:47.222440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20569 13:40:47.253941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20571 13:40:47.254514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20572 13:40:47.286154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20573 13:40:47.286622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20575 13:40:47.318022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20577 13:40:47.318574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20578 13:40:47.349428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20579 13:40:47.349907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20581 13:40:47.379748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20582 13:40:47.380204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20584 13:40:47.410760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20586 13:40:47.411327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20587 13:40:47.441513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20588 13:40:47.441975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20590 13:40:47.474076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20592 13:40:47.474647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20593 13:40:47.504001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20594 13:40:47.504442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20596 13:40:47.535873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20598 13:40:47.536420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20599 13:40:47.566344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20600 13:40:47.566775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20602 13:40:47.597326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20604 13:40:47.597867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20605 13:40:47.628474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20607 13:40:47.629027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20608 13:40:47.660561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20610 13:40:47.661143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20611 13:40:47.692922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20612 13:40:47.693332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20614 13:40:47.725296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20616 13:40:47.725891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20617 13:40:47.756802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20618 13:40:47.757288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20620 13:40:47.787841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20622 13:40:47.788455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20623 13:40:47.818920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20625 13:40:47.819479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20626 13:40:47.850487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20627 13:40:47.850941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20629 13:40:47.883021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20630 13:40:47.883508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20632 13:40:47.914446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20634 13:40:47.914893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20635 13:40:47.946425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20637 13:40:47.946992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20638 13:40:47.978119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20639 13:40:47.978614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20641 13:40:48.010838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20642 13:40:48.011292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20644 13:40:48.042495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20645 13:40:48.042962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20647 13:40:48.074478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20648 13:40:48.074950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20650 13:40:48.106480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20652 13:40:48.107125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20653 13:40:48.137718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20654 13:40:48.138199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20656 13:40:48.169723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20658 13:40:48.170359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20659 13:40:48.201449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20661 13:40:48.202051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20662 13:40:48.233561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20663 13:40:48.233987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20665 13:40:48.265585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20666 13:40:48.266005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20668 13:40:48.302025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20670 13:40:48.302607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20671 13:40:48.336062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20672 13:40:48.336556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20674 13:40:48.376598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20676 13:40:48.377183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20677 13:40:48.417590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20678 13:40:48.418155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20680 13:40:48.460754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20682 13:40:48.461519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20683 13:40:48.499430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20684 13:40:48.499912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20686 13:40:48.537248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20687 13:40:48.537673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20689 13:40:48.572729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20690 13:40:48.573221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20692 13:40:48.604193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20694 13:40:48.604778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20695 13:40:48.637523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20696 13:40:48.638036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20698 13:40:48.675354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20699 13:40:48.675762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20701 13:40:48.709816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20702 13:40:48.710231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20704 13:40:48.743443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20705 13:40:48.743857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20707 13:40:48.779989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20708 13:40:48.780407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20710 13:40:48.813081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20711 13:40:48.813498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20713 13:40:48.845485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20714 13:40:48.845904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20716 13:40:48.879630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20717 13:40:48.880046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20719 13:40:48.913945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20720 13:40:48.914338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20722 13:40:48.945678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20723 13:40:48.946128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20725 13:40:48.977786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20726 13:40:48.978223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20728 13:40:49.009165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20730 13:40:49.009632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20731 13:40:49.039776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20732 13:40:49.040211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20734 13:40:49.070762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20735 13:40:49.071240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20737 13:40:49.102606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20739 13:40:49.103043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20740 13:40:49.133828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20742 13:40:49.134295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20743 13:40:49.165910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20745 13:40:49.166365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20746 13:40:49.197546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20747 13:40:49.197977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20749 13:40:49.229708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20751 13:40:49.230160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20752 13:40:49.278504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20753 13:40:49.278925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20755 13:40:49.315911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20756 13:40:49.316336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20758 13:40:49.348139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20759 13:40:49.348562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20761 13:40:49.378454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20762 13:40:49.378939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20764 13:40:49.409717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20766 13:40:49.410350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20767 13:40:49.440347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20769 13:40:49.440800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20770 13:40:49.471270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20772 13:40:49.471737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20773 13:40:49.501591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20774 13:40:49.502074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20776 13:40:49.532956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20777 13:40:49.533405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20779 13:40:49.564155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20780 13:40:49.564593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20782 13:40:49.595324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20783 13:40:49.595788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20785 13:40:49.626115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20787 13:40:49.626680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20788 13:40:49.657271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20789 13:40:49.657705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20791 13:40:49.688210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20793 13:40:49.688662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20794 13:40:49.719440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20795 13:40:49.719932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20797 13:40:49.751730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20799 13:40:49.752352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20800 13:40:49.782497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20802 13:40:49.782931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20803 13:40:49.814369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20805 13:40:49.814831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20806 13:40:49.845619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20808 13:40:49.846060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20809 13:40:49.876873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20811 13:40:49.877311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20812 13:40:49.907820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20813 13:40:49.908293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20815 13:40:49.939969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20817 13:40:49.940607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20818 13:40:49.972640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20820 13:40:49.973223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20821 13:40:50.004940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20822 13:40:50.005520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20824 13:40:50.038804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20825 13:40:50.039295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20827 13:40:50.071278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20828 13:40:50.071771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20830 13:40:50.105335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20832 13:40:50.105990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20833 13:40:50.139948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20834 13:40:50.140439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20836 13:40:50.173813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20837 13:40:50.174228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20839 13:40:50.209843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20840 13:40:50.210264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20842 13:40:50.243894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20843 13:40:50.244341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20845 13:40:50.277702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20846 13:40:50.278116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20848 13:40:50.313948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20850 13:40:50.314407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20851 13:40:50.352222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20852 13:40:50.352641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20854 13:40:50.387004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20855 13:40:50.387560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20857 13:40:50.428978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20858 13:40:50.429472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20860 13:40:50.463908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20861 13:40:50.464412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20863 13:40:50.498502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20865 13:40:50.498952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20866 13:40:50.534988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20867 13:40:50.535393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20869 13:40:50.569734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20871 13:40:50.570350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20872 13:40:50.603094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20873 13:40:50.603567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20875 13:40:50.635233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20876 13:40:50.635709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20878 13:40:50.667097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20880 13:40:50.667555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20881 13:40:50.697521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20882 13:40:50.698025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20884 13:40:50.729339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20886 13:40:50.729913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20887 13:40:50.761559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20888 13:40:50.762048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20890 13:40:50.793589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20891 13:40:50.794061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20893 13:40:50.825794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20894 13:40:50.826251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20896 13:40:50.857427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20897 13:40:50.857863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20899 13:40:50.888939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20901 13:40:50.889376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20902 13:40:50.919280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20903 13:40:50.919698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20905 13:40:50.950908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20906 13:40:50.951342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20908 13:40:50.982785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20910 13:40:50.983249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20911 13:40:51.013722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20913 13:40:51.014336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20914 13:40:51.044583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20916 13:40:51.045151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20917 13:40:51.076770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20918 13:40:51.077242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20920 13:40:51.107517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20921 13:40:51.107933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20923 13:40:51.139020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20925 13:40:51.139472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20926 13:40:51.170218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20927 13:40:51.170698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20929 13:40:51.201621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20931 13:40:51.202179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20932 13:40:51.232535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20934 13:40:51.233120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20935 13:40:51.264648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20936 13:40:51.265089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20938 13:40:51.296247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
20940 13:40:51.296701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
20941 13:40:51.327513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
20943 13:40:51.327955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
20944 13:40:51.359474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
20946 13:40:51.359913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
20947 13:40:51.391514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
20949 13:40:51.391961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
20950 13:40:51.423457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
20951 13:40:51.423877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
20953 13:40:51.454921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
20954 13:40:51.455338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
20956 13:40:51.487323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
20957 13:40:51.487814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
20959 13:40:51.518662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
20961 13:40:51.519289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
20962 13:40:51.551209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
20963 13:40:51.551639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
20965 13:40:51.583272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
20967 13:40:51.583722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
20968 13:40:51.614860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
20970 13:40:51.615327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
20971 13:40:51.646668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
20973 13:40:51.647124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
20974 13:40:51.678366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
20975 13:40:51.678862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
20977 13:40:51.713425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
20978 13:40:51.713912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
20980 13:40:51.745484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
20981 13:40:51.745946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
20983 13:40:51.777604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
20985 13:40:51.778165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
20986 13:40:51.809234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
20987 13:40:51.809685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
20989 13:40:51.841513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
20990 13:40:51.842020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
20992 13:40:51.874400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
20994 13:40:51.874860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
20995 13:40:51.907840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
20997 13:40:51.908303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
20998 13:40:51.939606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
20999 13:40:51.940022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
21001 13:40:51.971196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
21002 13:40:51.971622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
21004 13:40:52.004065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
21005 13:40:52.004509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
21007 13:40:52.038017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
21009 13:40:52.038583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
21010 13:40:52.069898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
21011 13:40:52.070345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
21013 13:40:52.102219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
21015 13:40:52.102771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
21016 13:40:52.133675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
21017 13:40:52.134070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
21019 13:40:52.165763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
21021 13:40:52.166207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
21022 13:40:52.197671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
21023 13:40:52.198095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
21025 13:40:52.229072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
21027 13:40:52.229535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
21028 13:40:52.259661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
21029 13:40:52.260072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
21031 13:40:52.291538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
21033 13:40:52.292117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
21034 13:40:52.323254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
21036 13:40:52.323809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
21037 13:40:52.354986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
21038 13:40:52.355413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
21040 13:40:52.386763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
21042 13:40:52.387199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
21043 13:40:52.419339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
21044 13:40:52.419767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
21046 13:40:52.453144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
21047 13:40:52.453634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
21049 13:40:52.485397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
21051 13:40:52.485875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
21052 13:40:52.516869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
21054 13:40:52.517327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
21055 13:40:52.548597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
21057 13:40:52.549058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
21058 13:40:52.579772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
21059 13:40:52.580205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
21061 13:40:52.610410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
21062 13:40:52.610914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
21064 13:40:52.641668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
21066 13:40:52.642128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
21067 13:40:52.673494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
21068 13:40:52.673914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
21070 13:40:52.704792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
21071 13:40:52.705214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
21073 13:40:52.735735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
21075 13:40:52.736177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
21076 13:40:52.767230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
21077 13:40:52.767660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
21079 13:40:52.797974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
21080 13:40:52.798408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
21082 13:40:52.832057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
21083 13:40:52.832540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
21085 13:40:52.864061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
21086 13:40:52.864544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
21088 13:40:52.895931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
21090 13:40:52.896495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
21091 13:40:52.927499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
21092 13:40:52.927954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
21094 13:40:52.959043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
21095 13:40:52.959489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
21097 13:40:52.990338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
21099 13:40:52.990787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
21100 13:40:53.021870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
21102 13:40:53.022316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
21103 13:40:53.053632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
21105 13:40:53.054087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
21106 13:40:53.085724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
21107 13:40:53.086172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
21109 13:40:53.117446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
21111 13:40:53.117983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
21112 13:40:53.149721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
21114 13:40:53.150275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
21115 13:40:53.181626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
21116 13:40:53.182089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
21118 13:40:53.215029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
21119 13:40:53.215501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
21121 13:40:53.246470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
21122 13:40:53.246967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
21124 13:40:53.278145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
21125 13:40:53.278623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
21127 13:40:53.309918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
21128 13:40:53.310390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
21130 13:40:53.342071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
21131 13:40:53.342544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
21133 13:40:53.374180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
21134 13:40:53.374650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
21136 13:40:53.405947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
21138 13:40:53.406410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
21139 13:40:53.437221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
21140 13:40:53.437634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
21142 13:40:53.469261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
21143 13:40:53.469678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
21145 13:40:53.501157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
21146 13:40:53.501678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
21148 13:40:53.533325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
21149 13:40:53.533841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
21151 13:40:53.567935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
21152 13:40:53.568400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
21154 13:40:53.601777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
21155 13:40:53.602216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
21157 13:40:53.636033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
21159 13:40:53.636757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
21160 13:40:53.671582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
21162 13:40:53.672035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
21163 13:40:53.705971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
21165 13:40:53.706439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
21166 13:40:53.739946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
21167 13:40:53.740410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
21169 13:40:53.772400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
21171 13:40:53.773134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
21172 13:40:53.810427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
21174 13:40:53.810885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
21175 13:40:53.844930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
21176 13:40:53.845416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
21178 13:40:53.887836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
21179 13:40:53.888302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
21181 13:40:53.926499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
21182 13:40:53.927009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
21184 13:40:53.969640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
21185 13:40:53.970090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
21187 13:40:54.003968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
21189 13:40:54.004532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
21190 13:40:54.047538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
21192 13:40:54.048093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
21193 13:40:54.081013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
21195 13:40:54.081472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
21196 13:40:54.114129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
21198 13:40:54.114566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
21199 13:40:54.147676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
21201 13:40:54.148121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
21202 13:40:54.181450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
21203 13:40:54.181897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
21205 13:40:54.215753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
21207 13:40:54.216225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
21208 13:40:54.250139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
21209 13:40:54.250633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
21211 13:40:54.286479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
21212 13:40:54.286906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
21214 13:40:54.320342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
21216 13:40:54.320814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
21217 13:40:54.354027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
21218 13:40:54.354501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
21220 13:40:54.409529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
21221 13:40:54.409956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
21223 13:40:54.445153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
21224 13:40:54.445707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
21226 13:40:54.478810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
21227 13:40:54.479297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
21229 13:40:54.513723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
21230 13:40:54.514195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
21232 13:40:54.548165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
21233 13:40:54.548635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
21235 13:40:54.583709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
21237 13:40:54.584181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
21238 13:40:54.618822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
21239 13:40:54.619265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
21241 13:40:54.651115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
21242 13:40:54.651507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
21244 13:40:54.687033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
21245 13:40:54.687469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
21247 13:40:54.726544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
21248 13:40:54.726925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
21250 13:40:54.759935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
21251 13:40:54.760428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
21253 13:40:54.795843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
21255 13:40:54.796263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
21256 13:40:54.834071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
21258 13:40:54.834535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
21259 13:40:54.880160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
21260 13:40:54.880552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
21262 13:40:54.918942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
21263 13:40:54.919436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
21265 13:40:54.951938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
21266 13:40:54.952435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
21268 13:40:54.984927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
21269 13:40:54.985483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
21271 13:40:55.019047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
21272 13:40:55.019481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
21274 13:40:55.064961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
21275 13:40:55.065393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
21277 13:40:55.099679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
21279 13:40:55.100120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
21280 13:40:55.134665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
21282 13:40:55.135328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
21283 13:40:55.169220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
21284 13:40:55.169687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
21286 13:40:55.207645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
21287 13:40:55.208060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
21289 13:40:55.245804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
21290 13:40:55.246219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
21292 13:40:55.279699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
21293 13:40:55.280137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
21295 13:40:55.314233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
21296 13:40:55.314659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
21298 13:40:55.354781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
21299 13:40:55.355203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21301 13:40:55.391212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21302 13:40:55.391644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21304 13:40:55.424611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21306 13:40:55.425254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21307 13:40:55.457532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21308 13:40:55.458040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21310 13:40:55.492112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21311 13:40:55.492591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21313 13:40:55.526321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21314 13:40:55.526804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21316 13:40:55.561571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21317 13:40:55.562044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21319 13:40:55.595927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21321 13:40:55.596508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21322 13:40:55.630954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21323 13:40:55.631379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21325 13:40:55.667506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21327 13:40:55.667978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21328 13:40:55.698841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21329 13:40:55.699273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21331 13:40:55.730286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21332 13:40:55.730700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21334 13:40:55.762217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21335 13:40:55.762647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21337 13:40:55.793128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21338 13:40:55.793558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21340 13:40:55.823772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21341 13:40:55.824171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21343 13:40:55.854603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21344 13:40:55.855074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21346 13:40:55.886184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21347 13:40:55.886645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21349 13:40:55.916891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21350 13:40:55.917339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21352 13:40:55.948028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21353 13:40:55.948503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21355 13:40:55.979231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21356 13:40:55.979655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21358 13:40:56.010158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21360 13:40:56.010625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21361 13:40:56.041167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21363 13:40:56.041747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21364 13:40:56.072549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21366 13:40:56.073106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21367 13:40:56.103714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21368 13:40:56.104183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21370 13:40:56.134446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21371 13:40:56.134911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21373 13:40:56.166819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21374 13:40:56.167256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21376 13:40:56.198064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21377 13:40:56.198524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21379 13:40:56.229420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21381 13:40:56.229988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21382 13:40:56.261076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21384 13:40:56.261661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21385 13:40:56.292109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21386 13:40:56.292602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21388 13:40:56.323315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21389 13:40:56.323796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21391 13:40:56.354490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21393 13:40:56.355134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21394 13:40:56.385554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21395 13:40:56.386039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21397 13:40:56.417437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21398 13:40:56.417933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21400 13:40:56.447903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21401 13:40:56.448397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21403 13:40:56.479285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21404 13:40:56.479777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21406 13:40:56.510333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21407 13:40:56.510834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21409 13:40:56.541624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21411 13:40:56.542185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21412 13:40:56.573257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21414 13:40:56.573889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21415 13:40:56.605623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21417 13:40:56.606184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21418 13:40:56.636858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21419 13:40:56.637281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21421 13:40:56.667595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21423 13:40:56.668044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21424 13:40:56.698899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21425 13:40:56.699310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21427 13:40:56.730502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21428 13:40:56.730947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21430 13:40:56.762819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21431 13:40:56.763267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21433 13:40:56.796888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21435 13:40:56.797343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21436 13:40:56.829135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21437 13:40:56.829553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21439 13:40:56.862153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21441 13:40:56.862618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21442 13:40:56.895372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21443 13:40:56.895842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21445 13:40:56.927138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21447 13:40:56.927704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21448 13:40:56.959612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21449 13:40:56.960076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21451 13:40:56.993431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21452 13:40:56.993871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21454 13:40:57.025498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21455 13:40:57.025957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21457 13:40:57.057728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21459 13:40:57.058292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21460 13:40:57.089606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21462 13:40:57.090204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21463 13:40:57.121857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21465 13:40:57.122425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21466 13:40:57.155244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21467 13:40:57.155724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21469 13:40:57.187291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21470 13:40:57.187757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21472 13:40:57.219067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21473 13:40:57.219538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21475 13:40:57.251021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21477 13:40:57.251578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21478 13:40:57.282451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21479 13:40:57.282871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21481 13:40:57.314172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21482 13:40:57.314642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21484 13:40:57.346172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21485 13:40:57.346643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21487 13:40:57.377570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21488 13:40:57.377977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21490 13:40:57.409816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21491 13:40:57.410266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21493 13:40:57.441847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21494 13:40:57.442325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21496 13:40:57.473246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21497 13:40:57.473698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21499 13:40:57.505506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21500 13:40:57.505975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21502 13:40:57.537086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21503 13:40:57.537566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21505 13:40:57.570466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21507 13:40:57.571095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21508 13:40:57.605498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21509 13:40:57.606070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21511 13:40:57.638936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21513 13:40:57.639406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21514 13:40:57.674748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21515 13:40:57.675345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21517 13:40:57.714654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21518 13:40:57.715028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21520 13:40:57.758205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21522 13:40:57.758914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21523 13:40:57.797694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21524 13:40:57.798165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21526 13:40:57.837229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21527 13:40:57.837694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21529 13:40:57.870773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21530 13:40:57.871346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21532 13:40:57.906220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21534 13:40:57.906699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21535 13:40:57.941372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21536 13:40:57.941805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21538 13:40:57.978025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21540 13:40:57.978498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21541 13:40:58.017365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21543 13:40:58.018017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21544 13:40:58.052713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21546 13:40:58.053178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21547 13:40:58.086718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21549 13:40:58.087172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21550 13:40:58.121870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21552 13:40:58.122338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21553 13:40:58.156365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21555 13:40:58.156836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21556 13:40:58.189925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21557 13:40:58.190346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21559 13:40:58.224676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21560 13:40:58.225103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21562 13:40:58.258836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21564 13:40:58.259298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21565 13:40:58.293809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21567 13:40:58.294264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21568 13:40:58.329244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21569 13:40:58.329677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21571 13:40:58.372863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21573 13:40:58.373321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21574 13:40:58.405362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21576 13:40:58.405832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21577 13:40:58.439711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21578 13:40:58.440143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21580 13:40:58.472935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21581 13:40:58.473362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21583 13:40:58.506532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21584 13:40:58.506977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21586 13:40:58.540066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21588 13:40:58.540531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21589 13:40:58.584453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21591 13:40:58.584916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21592 13:40:58.617889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21593 13:40:58.618442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21595 13:40:58.650287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21596 13:40:58.650777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21598 13:40:58.682498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21599 13:40:58.682961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21601 13:40:58.714491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21603 13:40:58.715071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21604 13:40:58.746813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21605 13:40:58.747256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21607 13:40:58.782031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21608 13:40:58.782520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21610 13:40:58.814513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21612 13:40:58.815111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21613 13:40:58.846823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21615 13:40:58.847381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21616 13:40:58.878880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21617 13:40:58.879344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21619 13:40:58.910755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21621 13:40:58.911292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21622 13:40:58.943202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21623 13:40:58.943672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21625 13:40:58.976113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21626 13:40:58.976588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21628 13:40:59.008993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21630 13:40:59.009550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21631 13:40:59.040977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21632 13:40:59.041429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21634 13:40:59.073292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21635 13:40:59.073760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21637 13:40:59.105313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21638 13:40:59.105756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21640 13:40:59.137582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21642 13:40:59.138154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21643 13:40:59.169573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21644 13:40:59.170052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21646 13:40:59.201689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21647 13:40:59.202138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21649 13:40:59.233024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21651 13:40:59.233572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21652 13:40:59.265491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21654 13:40:59.265961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21655 13:40:59.297539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21656 13:40:59.297970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21658 13:40:59.331110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21659 13:40:59.331532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21661 13:40:59.363926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21663 13:40:59.364381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21664 13:40:59.396215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21665 13:40:59.396620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21667 13:40:59.429482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21668 13:40:59.429959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21670 13:40:59.461564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21671 13:40:59.462041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21673 13:40:59.493377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21674 13:40:59.493867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21676 13:40:59.547618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21677 13:40:59.548028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21679 13:40:59.579612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21680 13:40:59.580042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21682 13:40:59.611801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21683 13:40:59.612190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21685 13:40:59.644211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21687 13:40:59.644677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21688 13:40:59.675684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21690 13:40:59.676141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21691 13:40:59.707363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21692 13:40:59.707790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21694 13:40:59.738449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21695 13:40:59.738870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21697 13:40:59.770041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21698 13:40:59.770455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21700 13:40:59.801544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21701 13:40:59.801975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21703 13:40:59.833956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21704 13:40:59.834375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21706 13:40:59.865816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21708 13:40:59.866283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21709 13:40:59.898566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21711 13:40:59.899031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21712 13:40:59.929972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21713 13:40:59.930435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21715 13:40:59.961718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21717 13:40:59.962261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21718 13:40:59.994197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21719 13:40:59.994610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21721 13:41:00.025997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21722 13:41:00.026460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21724 13:41:00.057378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21725 13:41:00.057824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21727 13:41:00.088938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21729 13:41:00.089505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21730 13:41:00.121081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21731 13:41:00.121528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21733 13:41:00.152881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21734 13:41:00.153341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21736 13:41:00.184231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21738 13:41:00.184861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21739 13:41:00.216336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21740 13:41:00.216812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21742 13:41:00.248099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21743 13:41:00.248518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21745 13:41:00.279843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21747 13:41:00.280472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21748 13:41:00.312039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21749 13:41:00.312524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21751 13:41:00.344656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21753 13:41:00.345232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21754 13:41:00.376489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21756 13:41:00.376959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21757 13:41:00.409277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21758 13:41:00.409772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21760 13:41:00.440971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21761 13:41:00.441442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21763 13:41:00.473085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21765 13:41:00.473665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21766 13:41:00.505463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21767 13:41:00.505909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21769 13:41:00.537514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21771 13:41:00.538093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21772 13:41:00.569017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21773 13:41:00.569479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21775 13:41:00.601163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21776 13:41:00.601643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21778 13:41:00.633785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21779 13:41:00.634248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21781 13:41:00.666867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21783 13:41:00.667424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21784 13:41:00.700903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21785 13:41:00.701321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21787 13:41:00.733773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21788 13:41:00.734146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21790 13:41:00.765962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21791 13:41:00.766380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21793 13:41:00.798118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21795 13:41:00.798577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21796 13:41:00.830221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21797 13:41:00.830639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21799 13:41:00.862795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21800 13:41:00.863217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21802 13:41:00.894146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21803 13:41:00.894630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21805 13:41:00.925258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21806 13:41:00.925710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21808 13:41:00.956998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21809 13:41:00.957483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21811 13:41:00.988226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21812 13:41:00.988666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21814 13:41:01.020265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21815 13:41:01.020724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21817 13:41:01.052025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21819 13:41:01.052495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21820 13:41:01.083669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21821 13:41:01.084070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21823 13:41:01.115224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21824 13:41:01.115681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21826 13:41:01.147254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21827 13:41:01.147722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21829 13:41:01.178980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21831 13:41:01.179598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21832 13:41:01.210875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21834 13:41:01.211420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21835 13:41:01.242442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21837 13:41:01.242983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21838 13:41:01.274241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21839 13:41:01.274705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21841 13:41:01.305443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21842 13:41:01.305898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21844 13:41:01.336778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21845 13:41:01.337239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21847 13:41:01.368655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21849 13:41:01.369257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21850 13:41:01.399812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21851 13:41:01.400292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21853 13:41:01.431436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21854 13:41:01.431915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21856 13:41:01.462830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21857 13:41:01.463313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21859 13:41:01.493835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21861 13:41:01.494299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21862 13:41:01.525106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21863 13:41:01.525530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21865 13:41:01.555952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21866 13:41:01.556377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21868 13:41:01.587839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21869 13:41:01.588270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21871 13:41:01.619227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21872 13:41:01.619645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21874 13:41:01.653679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21875 13:41:01.654163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21877 13:41:01.688211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21878 13:41:01.688726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21880 13:41:01.722074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21881 13:41:01.722574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21883 13:41:01.755981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21884 13:41:01.756477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21886 13:41:01.790051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21888 13:41:01.790512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21889 13:41:01.823896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21890 13:41:01.824341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21892 13:41:01.858383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21894 13:41:01.858844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21895 13:41:01.893560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21896 13:41:01.894000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21898 13:41:01.930454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21899 13:41:01.930889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21901 13:41:01.965759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21902 13:41:01.966241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21904 13:41:01.999509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21905 13:41:01.999953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21907 13:41:02.032620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21909 13:41:02.033090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21910 13:41:02.067404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21911 13:41:02.067867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21913 13:41:02.109015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21914 13:41:02.109527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21916 13:41:02.142041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21917 13:41:02.142473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21919 13:41:02.175043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21921 13:41:02.175512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21922 13:41:02.210092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21923 13:41:02.210514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21925 13:41:02.247717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21926 13:41:02.248143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21928 13:41:02.298396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21929 13:41:02.298793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21931 13:41:02.335429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21932 13:41:02.335893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21934 13:41:02.373616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21935 13:41:02.374172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21937 13:41:02.410740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
21938 13:41:02.411308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
21940 13:41:02.451182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
21941 13:41:02.451655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
21943 13:41:02.490239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
21944 13:41:02.490718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
21946 13:41:02.528203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
21948 13:41:02.528802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
21949 13:41:02.565791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
21950 13:41:02.566279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
21952 13:41:02.602872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
21953 13:41:02.603370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
21955 13:41:02.639074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
21957 13:41:02.639825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
21958 13:41:02.675371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
21960 13:41:02.676030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
21961 13:41:02.715124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
21962 13:41:02.715610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
21964 13:41:02.751188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
21965 13:41:02.751648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
21967 13:41:02.797099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
21968 13:41:02.797619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
21970 13:41:02.833276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
21971 13:41:02.833685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
21973 13:41:02.869885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
21974 13:41:02.870290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
21976 13:41:02.906115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
21977 13:41:02.906540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
21979 13:41:02.942801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
21981 13:41:02.943375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
21982 13:41:02.978970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
21983 13:41:02.979395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
21985 13:41:03.014646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
21987 13:41:03.015117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
21988 13:41:03.050795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
21989 13:41:03.051290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
21991 13:41:03.087006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
21993 13:41:03.087461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
21994 13:41:03.123692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
21996 13:41:03.124119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
21997 13:41:03.165786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
21998 13:41:03.166239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
22000 13:41:03.202206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
22001 13:41:03.202583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
22003 13:41:03.239763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
22005 13:41:03.240363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
22006 13:41:03.276376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
22008 13:41:03.276974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
22009 13:41:03.313361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
22010 13:41:03.313905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
22012 13:41:03.350598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
22013 13:41:03.351084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
22015 13:41:03.388539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
22017 13:41:03.389296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
22018 13:41:03.429450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
22019 13:41:03.430004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
22021 13:41:03.468197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
22022 13:41:03.468664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
22024 13:41:03.504274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
22026 13:41:03.504845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
22027 13:41:03.539168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
22028 13:41:03.539609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
22030 13:41:03.577995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
22031 13:41:03.578480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
22033 13:41:03.613337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
22034 13:41:03.613763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
22036 13:41:03.648567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
22038 13:41:03.648956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
22039 13:41:03.683390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
22040 13:41:03.683812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
22042 13:41:03.717613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
22043 13:41:03.718103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
22045 13:41:03.751505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
22047 13:41:03.752095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
22048 13:41:03.786783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
22050 13:41:03.787395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
22051 13:41:03.822015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
22052 13:41:03.822466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
22054 13:41:03.857325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
22055 13:41:03.857878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
22057 13:41:03.891291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
22058 13:41:03.891779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
22060 13:41:03.926291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
22062 13:41:03.926765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
22063 13:41:03.960128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
22064 13:41:03.960549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
22066 13:41:03.994300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
22067 13:41:03.994774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
22069 13:41:04.029352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
22071 13:41:04.029926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
22072 13:41:04.063144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
22073 13:41:04.063660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
22075 13:41:04.097822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
22076 13:41:04.098374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
22078 13:41:04.133579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
22080 13:41:04.134051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
22081 13:41:04.170871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
22082 13:41:04.171376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
22084 13:41:04.205941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
22085 13:41:04.206364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
22087 13:41:04.240967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
22088 13:41:04.241397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
22090 13:41:04.274342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
22091 13:41:04.274762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
22093 13:41:04.308859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
22094 13:41:04.309298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
22096 13:41:04.344371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
22098 13:41:04.344852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
22099 13:41:04.379613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
22100 13:41:04.380034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
22102 13:41:04.414824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
22104 13:41:04.415283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
22105 13:41:04.450348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
22107 13:41:04.450810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
22108 13:41:04.488264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
22109 13:41:04.488752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
22111 13:41:04.537727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
22112 13:41:04.538216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
22114 13:41:04.572264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
22115 13:41:04.572759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
22117 13:41:04.607831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
22118 13:41:04.608285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
22120 13:41:04.677699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
22121 13:41:04.678123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
22123 13:41:04.713771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
22124 13:41:04.714241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
22126 13:41:04.749172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
22127 13:41:04.749586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
22129 13:41:04.784187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
22131 13:41:04.784922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
22132 13:41:04.820174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
22133 13:41:04.820609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
22135 13:41:04.856709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
22137 13:41:04.857089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
22138 13:41:04.893665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
22139 13:41:04.894112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
22141 13:41:04.931486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
22142 13:41:04.931950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
22144 13:41:04.969991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
22146 13:41:04.970572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
22147 13:41:05.008080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
22148 13:41:05.008511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
22150 13:41:05.043603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
22152 13:41:05.044063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
22153 13:41:05.079111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
22154 13:41:05.079598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
22156 13:41:05.114719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
22158 13:41:05.115173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
22159 13:41:05.149788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
22160 13:41:05.150225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
22162 13:41:05.185660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
22163 13:41:05.186111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
22165 13:41:05.222156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
22166 13:41:05.222592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
22168 13:41:05.257717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
22170 13:41:05.258340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
22171 13:41:05.293048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
22172 13:41:05.293522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
22174 13:41:05.327879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
22175 13:41:05.328439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
22177 13:41:05.363024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
22178 13:41:05.363487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
22180 13:41:05.411128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
22181 13:41:05.411610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
22183 13:41:05.457915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
22184 13:41:05.458401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
22186 13:41:05.492898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
22187 13:41:05.493355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
22189 13:41:05.541593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
22190 13:41:05.542045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
22192 13:41:05.575719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
22194 13:41:05.576178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
22195 13:41:05.610094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
22197 13:41:05.610556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
22198 13:41:05.645248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
22199 13:41:05.645691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
22201 13:41:05.678357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
22202 13:41:05.678849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
22204 13:41:05.709308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
22205 13:41:05.709788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
22207 13:41:05.740540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
22209 13:41:05.741165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
22210 13:41:05.771308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
22212 13:41:05.771901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
22213 13:41:05.801996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
22214 13:41:05.802485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
22216 13:41:05.833254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
22217 13:41:05.833704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
22219 13:41:05.863921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
22220 13:41:05.864433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
22222 13:41:05.894923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
22223 13:41:05.895396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
22225 13:41:05.926252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
22226 13:41:05.926716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
22228 13:41:05.957709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
22229 13:41:05.958153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
22231 13:41:05.989179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
22233 13:41:05.989744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
22234 13:41:06.020247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
22235 13:41:06.020710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
22237 13:41:06.052532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
22239 13:41:06.053129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
22240 13:41:06.084097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
22241 13:41:06.084564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
22243 13:41:06.115460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
22244 13:41:06.115920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
22246 13:41:06.146862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
22248 13:41:06.147331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
22249 13:41:06.177774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
22251 13:41:06.178247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
22252 13:41:06.208688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
22254 13:41:06.209316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
22255 13:41:06.239935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
22256 13:41:06.240357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
22258 13:41:06.271996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
22259 13:41:06.272422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
22261 13:41:06.303560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
22262 13:41:06.304023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
22264 13:41:06.334950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
22265 13:41:06.335410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
22267 13:41:06.366735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
22268 13:41:06.367147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
22270 13:41:06.400035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
22271 13:41:06.400477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
22273 13:41:06.431619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
22275 13:41:06.432177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
22276 13:41:06.462743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
22278 13:41:06.463349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
22279 13:41:06.494440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
22280 13:41:06.494875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
22282 13:41:06.528062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
22284 13:41:06.528528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
22285 13:41:06.560789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
22286 13:41:06.561281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
22288 13:41:06.593681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
22289 13:41:06.594169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
22291 13:41:06.625427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
22292 13:41:06.625915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
22294 13:41:06.658442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
22295 13:41:06.658938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
22297 13:41:06.690042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
22298 13:41:06.690530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
22300 13:41:06.721984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22302 13:41:06.722537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22303 13:41:06.754125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22304 13:41:06.754575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22306 13:41:06.785719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22307 13:41:06.786142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22309 13:41:06.817589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22310 13:41:06.818013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22312 13:41:06.849666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22314 13:41:06.850255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22315 13:41:06.881887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22317 13:41:06.882439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22318 13:41:06.913644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22319 13:41:06.914109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22321 13:41:06.945247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22322 13:41:06.945695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22324 13:41:06.977177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22325 13:41:06.977623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22327 13:41:07.009004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22328 13:41:07.009427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22330 13:41:07.040384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22332 13:41:07.040956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22333 13:41:07.072663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22335 13:41:07.073253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22336 13:41:07.104225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22338 13:41:07.104774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22339 13:41:07.135952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22340 13:41:07.136401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22342 13:41:07.169460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22343 13:41:07.169981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22345 13:41:07.202442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22346 13:41:07.202949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22348 13:41:07.233969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22349 13:41:07.234384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22351 13:41:07.265718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22352 13:41:07.266194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22354 13:41:07.297541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22356 13:41:07.298131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22357 13:41:07.329357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22358 13:41:07.329834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22360 13:41:07.361314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22362 13:41:07.361854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22363 13:41:07.393484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22365 13:41:07.394039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22366 13:41:07.425274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22367 13:41:07.425758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22369 13:41:07.456757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22370 13:41:07.457247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22372 13:41:07.488422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22374 13:41:07.488996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22375 13:41:07.521263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22377 13:41:07.521846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22378 13:41:07.553027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22379 13:41:07.553445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22381 13:41:07.585101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22383 13:41:07.585552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22384 13:41:07.617396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22386 13:41:07.618025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22387 13:41:07.649059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22388 13:41:07.649470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22390 13:41:07.681289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22392 13:41:07.681798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22393 13:41:07.713386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22394 13:41:07.713869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22396 13:41:07.745371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22397 13:41:07.745789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22399 13:41:07.777403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22401 13:41:07.778035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22402 13:41:07.809603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22403 13:41:07.810098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22405 13:41:07.841409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22406 13:41:07.841894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22408 13:41:07.873494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22409 13:41:07.873949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22411 13:41:07.905634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22413 13:41:07.906196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22414 13:41:07.937398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22415 13:41:07.937849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22417 13:41:07.971590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22418 13:41:07.972025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22420 13:41:08.004554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22422 13:41:08.004941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22423 13:41:08.036891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22424 13:41:08.037364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22426 13:41:08.067921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22428 13:41:08.068476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22429 13:41:08.101074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22431 13:41:08.101644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22432 13:41:08.133291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22433 13:41:08.133752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22435 13:41:08.165404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22436 13:41:08.165858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22438 13:41:08.198317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22439 13:41:08.198790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22441 13:41:08.232517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22443 13:41:08.233088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22444 13:41:08.263791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22445 13:41:08.264262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22447 13:41:08.295303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22448 13:41:08.295776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22450 13:41:08.328297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22452 13:41:08.328888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22453 13:41:08.360308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22455 13:41:08.360783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22456 13:41:08.391938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22458 13:41:08.392408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22459 13:41:08.427117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22460 13:41:08.427631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22462 13:41:08.479996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22463 13:41:08.480480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22465 13:41:08.533740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22466 13:41:08.534295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22468 13:41:08.569394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22469 13:41:08.569850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22471 13:41:08.605297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22472 13:41:08.605845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22474 13:41:08.638508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22476 13:41:08.639086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22477 13:41:08.676293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22479 13:41:08.676779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22480 13:41:08.709382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22481 13:41:08.709832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22483 13:41:08.741966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22485 13:41:08.742448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22486 13:41:08.777631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22487 13:41:08.778049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22489 13:41:08.811184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22490 13:41:08.811625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22492 13:41:08.843554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22493 13:41:08.843989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22495 13:41:08.875553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22496 13:41:08.876024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22498 13:41:08.908956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22499 13:41:08.909481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22501 13:41:08.945412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22502 13:41:08.945823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22504 13:41:08.981956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22505 13:41:08.982422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22507 13:41:09.018365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22508 13:41:09.018774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22510 13:41:09.054979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22511 13:41:09.055333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22513 13:41:09.091166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22515 13:41:09.091631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22516 13:41:09.126496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22518 13:41:09.127101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22519 13:41:09.160449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22521 13:41:09.160919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22522 13:41:09.193726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22524 13:41:09.194310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22525 13:41:09.227420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22526 13:41:09.227985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22528 13:41:09.260381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22530 13:41:09.260954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22531 13:41:09.293010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22532 13:41:09.293494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22534 13:41:09.325859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22535 13:41:09.326275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22537 13:41:09.359431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22539 13:41:09.359888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22540 13:41:09.391939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22541 13:41:09.392361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22543 13:41:09.423993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22544 13:41:09.424416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22546 13:41:09.455669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22547 13:41:09.456130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22549 13:41:09.487741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22550 13:41:09.488177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22552 13:41:09.518990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22553 13:41:09.519425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22555 13:41:09.550385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22557 13:41:09.550990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22558 13:41:09.581642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22559 13:41:09.582059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22561 13:41:09.612603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22563 13:41:09.613046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22564 13:41:09.643749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22565 13:41:09.644209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22567 13:41:09.675976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22568 13:41:09.676464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22570 13:41:09.708047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22572 13:41:09.708523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22573 13:41:09.750651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22575 13:41:09.751131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22576 13:41:09.798586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22578 13:41:09.799048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22579 13:41:09.831297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22580 13:41:09.831729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22582 13:41:09.864124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22583 13:41:09.864584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22585 13:41:09.896426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22587 13:41:09.896996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22588 13:41:09.929243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22589 13:41:09.929693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22591 13:41:09.961565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22592 13:41:09.962053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22594 13:41:09.994100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22596 13:41:09.994731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22597 13:41:10.025723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22598 13:41:10.026198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22600 13:41:10.057675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22601 13:41:10.058143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22603 13:41:10.089719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22604 13:41:10.090188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22606 13:41:10.121696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22608 13:41:10.122316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22609 13:41:10.153342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22610 13:41:10.153791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22612 13:41:10.185425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22613 13:41:10.185899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22615 13:41:10.217713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22617 13:41:10.218185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22618 13:41:10.249390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22619 13:41:10.249835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22621 13:41:10.281548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22622 13:41:10.281989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22624 13:41:10.313579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22625 13:41:10.314002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22627 13:41:10.345658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22629 13:41:10.346223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22630 13:41:10.377497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22631 13:41:10.377962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22633 13:41:10.409480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22635 13:41:10.410039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22636 13:41:10.441453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22638 13:41:10.442004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22639 13:41:10.473362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22640 13:41:10.473811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22642 13:41:10.505476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22643 13:41:10.505938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22645 13:41:10.540017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22646 13:41:10.540466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22648 13:41:10.578826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22649 13:41:10.579254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22651 13:41:10.613718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22652 13:41:10.614196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22654 13:41:10.649479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22656 13:41:10.650031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22657 13:41:10.684710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22659 13:41:10.685317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22660 13:41:10.720828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22661 13:41:10.721310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22663 13:41:10.758656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22665 13:41:10.759226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22666 13:41:10.790515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22668 13:41:10.791118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22669 13:41:10.821511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22670 13:41:10.822000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22672 13:41:10.852869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22673 13:41:10.853359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22675 13:41:10.883975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22677 13:41:10.884531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22678 13:41:10.915988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22679 13:41:10.916452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22681 13:41:10.947392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22682 13:41:10.947851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22684 13:41:10.978279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22685 13:41:10.978707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22687 13:41:11.009593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22688 13:41:11.010084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22690 13:41:11.040966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22691 13:41:11.041440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22693 13:41:11.071866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22694 13:41:11.072355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22696 13:41:11.103498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22697 13:41:11.103971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22699 13:41:11.136671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22701 13:41:11.137374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22702 13:41:11.169600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22703 13:41:11.170090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22705 13:41:11.201340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22707 13:41:11.201799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22708 13:41:11.233539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22710 13:41:11.234022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22711 13:41:11.265631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22713 13:41:11.266211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22714 13:41:11.297210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22716 13:41:11.297796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22717 13:41:11.330112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22719 13:41:11.330578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22720 13:41:11.363213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22721 13:41:11.363651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22723 13:41:11.395162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22724 13:41:11.395597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22726 13:41:11.427693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22727 13:41:11.428113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22729 13:41:11.461054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22731 13:41:11.461528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22732 13:41:11.495210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22733 13:41:11.495631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22735 13:41:11.527586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22736 13:41:11.528012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22738 13:41:11.560567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22740 13:41:11.561029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22741 13:41:11.594058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22742 13:41:11.594477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22744 13:41:11.626661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22745 13:41:11.627117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22747 13:41:11.659742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22748 13:41:11.660203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22750 13:41:11.692707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22752 13:41:11.693336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22753 13:41:11.725914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22755 13:41:11.726500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22756 13:41:11.758175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22757 13:41:11.758606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22759 13:41:11.791304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22760 13:41:11.791780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22762 13:41:11.824252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22764 13:41:11.824718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22765 13:41:11.857187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22767 13:41:11.857652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22768 13:41:11.889521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22769 13:41:11.889962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22771 13:41:11.921888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22772 13:41:11.922306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22774 13:41:11.954854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22776 13:41:11.955318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22777 13:41:11.986790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22778 13:41:11.987270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22780 13:41:12.019020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22782 13:41:12.019565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22783 13:41:12.051100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22784 13:41:12.051546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22786 13:41:12.083010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22787 13:41:12.083478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22789 13:41:12.115211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22791 13:41:12.115839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22792 13:41:12.147194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22794 13:41:12.147752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22795 13:41:12.179405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22796 13:41:12.179882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22798 13:41:12.211987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22800 13:41:12.212445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22801 13:41:12.244275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22803 13:41:12.244745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22804 13:41:12.277273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22805 13:41:12.277686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22807 13:41:12.311739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22808 13:41:12.312242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22810 13:41:12.344560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22812 13:41:12.345149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22813 13:41:12.377838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22815 13:41:12.378397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22816 13:41:12.410171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22818 13:41:12.410728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22819 13:41:12.442198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22820 13:41:12.442645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22822 13:41:12.474844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22823 13:41:12.475306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22825 13:41:12.506382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22826 13:41:12.506851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22828 13:41:12.538695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22830 13:41:12.539164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22831 13:41:12.570715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22832 13:41:12.571148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22834 13:41:12.605039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22835 13:41:12.605510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22837 13:41:12.637628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22839 13:41:12.638192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22840 13:41:12.669509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22841 13:41:12.669934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22843 13:41:12.701785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22844 13:41:12.702205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22846 13:41:12.733712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22847 13:41:12.734133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22849 13:41:12.765792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22851 13:41:12.766436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22852 13:41:12.798220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22853 13:41:12.798690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22855 13:41:12.831983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22856 13:41:12.832393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22858 13:41:12.864470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22860 13:41:12.864909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22861 13:41:12.896041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22863 13:41:12.896653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22864 13:41:12.927868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22866 13:41:12.928506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22867 13:41:12.960029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22869 13:41:12.960655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22870 13:41:12.994482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22872 13:41:12.995289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22873 13:41:13.027316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22874 13:41:13.027802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22876 13:41:13.059369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22878 13:41:13.059936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22879 13:41:13.091444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22881 13:41:13.092008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22882 13:41:13.123006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22884 13:41:13.123564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22885 13:41:13.154099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22886 13:41:13.154544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22888 13:41:13.185470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22889 13:41:13.185919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22891 13:41:13.216962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22892 13:41:13.217436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22894 13:41:13.248932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22896 13:41:13.249498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22897 13:41:13.279470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22898 13:41:13.279942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22900 13:41:13.311071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22901 13:41:13.311523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22903 13:41:13.342724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22904 13:41:13.343183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22906 13:41:13.373944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22908 13:41:13.374485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22909 13:41:13.405524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22910 13:41:13.406038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22912 13:41:13.437463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22914 13:41:13.437948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22915 13:41:13.468413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22917 13:41:13.468882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22918 13:41:13.499189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22920 13:41:13.499745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22921 13:41:13.530647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22922 13:41:13.531117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22924 13:41:13.562491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22926 13:41:13.563105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22927 13:41:13.593709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22929 13:41:13.594146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22930 13:41:13.625426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22931 13:41:13.625845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22933 13:41:13.657995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22934 13:41:13.658392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22936 13:41:13.691061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22938 13:41:13.691520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
22939 13:41:13.727416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
22940 13:41:13.727823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
22942 13:41:13.760515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
22944 13:41:13.760947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
22945 13:41:13.793075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
22946 13:41:13.793503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
22948 13:41:13.825288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
22949 13:41:13.825691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
22951 13:41:13.857960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
22953 13:41:13.858419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
22954 13:41:13.889743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
22955 13:41:13.890222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
22957 13:41:13.921265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
22959 13:41:13.921922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
22960 13:41:13.953708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
22961 13:41:13.954137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
22963 13:41:13.986218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
22964 13:41:13.986641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
22966 13:41:14.018834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
22967 13:41:14.019271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
22969 13:41:14.051286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
22971 13:41:14.052023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
22972 13:41:14.082859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
22974 13:41:14.083501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
22975 13:41:14.114346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
22977 13:41:14.114945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
22978 13:41:14.146613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
22980 13:41:14.147193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
22981 13:41:14.180684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
22983 13:41:14.181137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
22984 13:41:14.216129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
22986 13:41:14.216592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
22987 13:41:14.249055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
22989 13:41:14.249506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
22990 13:41:14.281445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
22992 13:41:14.281893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
22993 13:41:14.313358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
22994 13:41:14.313789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
22996 13:41:14.345639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
22998 13:41:14.346268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
22999 13:41:14.378009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
23000 13:41:14.378407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
23002 13:41:14.409634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
23003 13:41:14.410097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
23005 13:41:14.441819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
23007 13:41:14.442397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
23008 13:41:14.473488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
23009 13:41:14.473979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
23011 13:41:14.504965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
23013 13:41:14.505576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
23014 13:41:14.535743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
23015 13:41:14.536218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
23017 13:41:14.566643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
23018 13:41:14.567132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
23020 13:41:14.597619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
23022 13:41:14.598088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
23023 13:41:14.629478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
23024 13:41:14.629945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
23026 13:41:14.660664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
23028 13:41:14.661211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
23029 13:41:14.692159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
23030 13:41:14.692633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
23032 13:41:14.723734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
23033 13:41:14.724207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
23035 13:41:14.755261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
23037 13:41:14.755815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
23038 13:41:14.786930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
23039 13:41:14.787388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
23041 13:41:14.819240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
23043 13:41:14.819793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
23044 13:41:14.850167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
23045 13:41:14.850648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
23047 13:41:14.902664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
23048 13:41:14.903134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
23050 13:41:14.935228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
23052 13:41:14.935914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
23053 13:41:14.966626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
23054 13:41:14.967115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
23056 13:41:15.000904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
23057 13:41:15.001377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
23059 13:41:15.033509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
23061 13:41:15.033982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
23062 13:41:15.066366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
23063 13:41:15.066809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
23065 13:41:15.098917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
23066 13:41:15.099375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
23068 13:41:15.131850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
23069 13:41:15.132245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
23071 13:41:15.163954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
23072 13:41:15.164349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
23074 13:41:15.196572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
23076 13:41:15.197046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
23077 13:41:15.228108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
23078 13:41:15.228533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
23080 13:41:15.259961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
23081 13:41:15.260386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
23083 13:41:15.292054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
23085 13:41:15.292515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
23086 13:41:15.324289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
23088 13:41:15.324751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
23089 13:41:15.357155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
23090 13:41:15.357580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
23092 13:41:15.389294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
23093 13:41:15.389683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
23095 13:41:15.422210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
23096 13:41:15.422633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
23098 13:41:15.454798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
23099 13:41:15.455272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
23101 13:41:15.487494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
23102 13:41:15.487898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
23104 13:41:15.519340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
23105 13:41:15.519765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
23107 13:41:15.553425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
23108 13:41:15.553852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
23110 13:41:15.586707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
23111 13:41:15.587182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
23113 13:41:15.621690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
23115 13:41:15.622247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
23116 13:41:15.656251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
23117 13:41:15.656710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
23119 13:41:15.691230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
23121 13:41:15.691767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
23122 13:41:15.725712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
23123 13:41:15.726167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
23125 13:41:15.758958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
23126 13:41:15.759431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
23128 13:41:15.790340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
23129 13:41:15.790768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
23131 13:41:15.822341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
23132 13:41:15.822804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
23134 13:41:15.854519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
23136 13:41:15.855058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
23137 13:41:15.885895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
23138 13:41:15.886307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
23140 13:41:15.919033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
23142 13:41:15.919636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
23143 13:41:15.952039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
23145 13:41:15.952507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
23146 13:41:15.984212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
23147 13:41:15.984634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
23149 13:41:16.016041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
23151 13:41:16.016502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
23152 13:41:16.047803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
23154 13:41:16.048455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
23155 13:41:16.079545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
23157 13:41:16.080135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
23158 13:41:16.111718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
23159 13:41:16.112201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
23161 13:41:16.143591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
23163 13:41:16.144225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
23164 13:41:16.175324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
23165 13:41:16.175786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
23167 13:41:16.207156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
23169 13:41:16.207723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
23170 13:41:16.238991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
23171 13:41:16.239445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
23173 13:41:16.277990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
23175 13:41:16.278542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
23176 13:41:16.310400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
23177 13:41:16.310860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
23179 13:41:16.342697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
23180 13:41:16.343150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
23182 13:41:16.374641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
23184 13:41:16.375196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
23185 13:41:16.406155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
23186 13:41:16.406604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
23188 13:41:16.437796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
23189 13:41:16.438270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
23191 13:41:16.469606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
23192 13:41:16.470084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
23194 13:41:16.501461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
23195 13:41:16.501887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
23197 13:41:16.533521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
23198 13:41:16.533923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
23200 13:41:16.565709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
23202 13:41:16.566277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
23203 13:41:16.597515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
23204 13:41:16.597969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
23206 13:41:16.629746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
23207 13:41:16.630195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
23209 13:41:16.661527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
23210 13:41:16.662052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
23212 13:41:16.693485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
23214 13:41:16.693976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
23215 13:41:16.725490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
23216 13:41:16.725958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
23218 13:41:16.757709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
23219 13:41:16.758118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
23221 13:41:16.790241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
23223 13:41:16.790690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
23224 13:41:16.822005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
23225 13:41:16.822407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
23227 13:41:16.853627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
23228 13:41:16.854063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
23230 13:41:16.885549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
23232 13:41:16.886122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
23233 13:41:16.916490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
23235 13:41:16.917082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
23236 13:41:16.948080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
23238 13:41:16.948673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
23239 13:41:16.981826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
23241 13:41:16.982389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
23242 13:41:17.013930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
23243 13:41:17.014381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
23245 13:41:17.045243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
23247 13:41:17.045682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
23248 13:41:17.077477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
23249 13:41:17.077897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
23251 13:41:17.109234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
23253 13:41:17.109679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
23254 13:41:17.141601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
23255 13:41:17.142081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
23257 13:41:17.173512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
23259 13:41:17.174153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
23260 13:41:17.204799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
23261 13:41:17.205249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
23263 13:41:17.236184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
23265 13:41:17.236748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
23266 13:41:17.267283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
23267 13:41:17.267719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
23269 13:41:17.298165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
23271 13:41:17.298727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
23272 13:41:17.329136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
23273 13:41:17.329610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
23275 13:41:17.360182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
23276 13:41:17.360638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
23278 13:41:17.391429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
23279 13:41:17.391845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
23281 13:41:17.422256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
23282 13:41:17.422757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
23284 13:41:17.455988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
23285 13:41:17.456490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
23287 13:41:17.489964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
23289 13:41:17.490704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
23290 13:41:17.523548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
23292 13:41:17.524125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
23293 13:41:17.557212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
23295 13:41:17.557915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
23296 13:41:17.589905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
23297 13:41:17.590373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
23299 13:41:17.625819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23301 13:41:17.626548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23302 13:41:17.662211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23303 13:41:17.662677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23305 13:41:17.699964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23307 13:41:17.700637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23308 13:41:17.732618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23310 13:41:17.733098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23311 13:41:17.768016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23313 13:41:17.768608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23314 13:41:17.806315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23315 13:41:17.806797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23317 13:41:17.842428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23318 13:41:17.842870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23320 13:41:17.875133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23321 13:41:17.875617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23323 13:41:17.907096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23325 13:41:17.907650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23326 13:41:17.951950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23327 13:41:17.952444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23329 13:41:17.983963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23331 13:41:17.984605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23332 13:41:18.016407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23334 13:41:18.017043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23335 13:41:18.048930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23336 13:41:18.049387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23338 13:41:18.079921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23339 13:41:18.080376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23341 13:41:18.111540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23342 13:41:18.112006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23344 13:41:18.143925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23345 13:41:18.144380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23347 13:41:18.175361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23349 13:41:18.175934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23350 13:41:18.207578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23352 13:41:18.208212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23353 13:41:18.239056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23354 13:41:18.239516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23356 13:41:18.270465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23358 13:41:18.271050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23359 13:41:18.302591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23361 13:41:18.303200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23362 13:41:18.334502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23363 13:41:18.334961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23365 13:41:18.365504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23366 13:41:18.365974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23368 13:41:18.397330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23370 13:41:18.397892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23371 13:41:18.429337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23372 13:41:18.429822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23374 13:41:18.461270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23376 13:41:18.461836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23377 13:41:18.492226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23379 13:41:18.492819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23380 13:41:18.524078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23381 13:41:18.524555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23383 13:41:18.555475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23384 13:41:18.555948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23386 13:41:18.587110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23388 13:41:18.587757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23389 13:41:18.619448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23390 13:41:18.619874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23392 13:41:18.651324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23393 13:41:18.651804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23395 13:41:18.683022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23396 13:41:18.683493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23398 13:41:18.714421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23399 13:41:18.714935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23401 13:41:18.745739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23402 13:41:18.746218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23404 13:41:18.778061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23405 13:41:18.778474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23407 13:41:18.810422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23408 13:41:18.810830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23410 13:41:18.844465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23412 13:41:18.844898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23413 13:41:18.877106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23414 13:41:18.877591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23416 13:41:18.909021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23418 13:41:18.909601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23419 13:41:18.941047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23420 13:41:18.941516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23422 13:41:18.972509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23424 13:41:18.973115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23425 13:41:19.004809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23426 13:41:19.005268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23428 13:41:19.036891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23429 13:41:19.037347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23431 13:41:19.069562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23432 13:41:19.070059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23434 13:41:19.101801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23436 13:41:19.102349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23437 13:41:19.133798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23438 13:41:19.134225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23440 13:41:19.166554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23441 13:41:19.167006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23443 13:41:19.198798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23445 13:41:19.199384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23446 13:41:19.231407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23448 13:41:19.232038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23449 13:41:19.263262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23450 13:41:19.263752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23452 13:41:19.295366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23453 13:41:19.295839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23455 13:41:19.327420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23456 13:41:19.327872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23458 13:41:19.360048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23460 13:41:19.360706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23461 13:41:19.392161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23462 13:41:19.392584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23464 13:41:19.424007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23465 13:41:19.424425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23467 13:41:19.456290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23469 13:41:19.456754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23470 13:41:19.488259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23472 13:41:19.488718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23473 13:41:19.519768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23475 13:41:19.520237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23476 13:41:19.551595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23478 13:41:19.552064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23479 13:41:19.583586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23480 13:41:19.584042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23482 13:41:19.615143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23483 13:41:19.615578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23485 13:41:19.647563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23487 13:41:19.648020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23488 13:41:19.679500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23489 13:41:19.679963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23491 13:41:19.711325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23492 13:41:19.711750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23494 13:41:19.742891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23495 13:41:19.743321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23497 13:41:19.774956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23498 13:41:19.775437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23500 13:41:19.807258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23502 13:41:19.807791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23503 13:41:19.839268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23505 13:41:19.839799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23506 13:41:19.871143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23507 13:41:19.871607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23509 13:41:19.903945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23511 13:41:19.904516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23512 13:41:19.935728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23514 13:41:19.936192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23515 13:41:19.967806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23517 13:41:19.968455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23518 13:41:20.025924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23519 13:41:20.026424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23521 13:41:20.057367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23522 13:41:20.057872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23524 13:41:20.089326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23525 13:41:20.089745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23527 13:41:20.121381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23529 13:41:20.121854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23530 13:41:20.152991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23532 13:41:20.153463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23533 13:41:20.185109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23535 13:41:20.185766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23536 13:41:20.216258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23538 13:41:20.216858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23539 13:41:20.247739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23540 13:41:20.248204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23542 13:41:20.279872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23543 13:41:20.280348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23545 13:41:20.311393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23547 13:41:20.311955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23548 13:41:20.342688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23549 13:41:20.343156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23551 13:41:20.374008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23553 13:41:20.374450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23554 13:41:20.405842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23555 13:41:20.406299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23557 13:41:20.437122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23558 13:41:20.437570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23560 13:41:20.468338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23562 13:41:20.468878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23563 13:41:20.499938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23564 13:41:20.500381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23566 13:41:20.533002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23568 13:41:20.533537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23569 13:41:20.566050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23570 13:41:20.566496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23572 13:41:20.599170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23573 13:41:20.599649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23575 13:41:20.632035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23577 13:41:20.632491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23578 13:41:20.664679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23580 13:41:20.665134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23581 13:41:20.698162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23583 13:41:20.698621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23584 13:41:20.731469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23585 13:41:20.731889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23587 13:41:20.763630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23588 13:41:20.764010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23590 13:41:20.795702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23591 13:41:20.796123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23593 13:41:20.827799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23594 13:41:20.828215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23596 13:41:20.859259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23597 13:41:20.859677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23599 13:41:20.891840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23600 13:41:20.892258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23602 13:41:20.924547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23604 13:41:20.925020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23605 13:41:20.956186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23607 13:41:20.956650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23608 13:41:20.987716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23609 13:41:20.988184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23611 13:41:21.019494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23613 13:41:21.019963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23614 13:41:21.050528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23615 13:41:21.050946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23617 13:41:21.081693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23619 13:41:21.082161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23620 13:41:21.113809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23622 13:41:21.114388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23623 13:41:21.146192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23624 13:41:21.146658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23626 13:41:21.177771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23627 13:41:21.178246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23629 13:41:21.209224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23631 13:41:21.209858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23632 13:41:21.241001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23634 13:41:21.241626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23635 13:41:21.272421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23637 13:41:21.273072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23638 13:41:21.305575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23639 13:41:21.306062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23641 13:41:21.337751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23642 13:41:21.338224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23644 13:41:21.369766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23646 13:41:21.370376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23647 13:41:21.402221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23648 13:41:21.402660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23650 13:41:21.433932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23652 13:41:21.434558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23653 13:41:21.466420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23655 13:41:21.466989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23656 13:41:21.498115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23658 13:41:21.498589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23659 13:41:21.529379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23660 13:41:21.529867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23662 13:41:21.561489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23664 13:41:21.561951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23665 13:41:21.592534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23667 13:41:21.592983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23668 13:41:21.623640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23669 13:41:21.624062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23671 13:41:21.655072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23672 13:41:21.655538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23674 13:41:21.686530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23675 13:41:21.686994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23677 13:41:21.718185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23678 13:41:21.718659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23680 13:41:21.750219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23682 13:41:21.750864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23683 13:41:21.781608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23684 13:41:21.782022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23686 13:41:21.813640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23688 13:41:21.814097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23689 13:41:21.845461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23690 13:41:21.845932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23692 13:41:21.877529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23694 13:41:21.878092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23695 13:41:21.909347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23696 13:41:21.909786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23698 13:41:21.943448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23699 13:41:21.943910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23701 13:41:21.977315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23703 13:41:21.977913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23704 13:41:22.011605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23705 13:41:22.012104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23707 13:41:22.044493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23709 13:41:22.044976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23710 13:41:22.077683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23711 13:41:22.078101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23713 13:41:22.111743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23714 13:41:22.112164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23716 13:41:22.143044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23718 13:41:22.143631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23719 13:41:22.175797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23720 13:41:22.176259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23722 13:41:22.207038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23723 13:41:22.207494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23725 13:41:22.238269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23726 13:41:22.238733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23728 13:41:22.270097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23730 13:41:22.270562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23731 13:41:22.302394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23733 13:41:22.302857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23734 13:41:22.334553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23735 13:41:22.334973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23737 13:41:22.365768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23739 13:41:22.366223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23740 13:41:22.396869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23741 13:41:22.397305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23743 13:41:22.429025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23745 13:41:22.429497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23746 13:41:22.461062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23748 13:41:22.461521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23749 13:41:22.492013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23750 13:41:22.492433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23752 13:41:22.523253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23753 13:41:22.523679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23755 13:41:22.554513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23756 13:41:22.554923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23758 13:41:22.586592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23759 13:41:22.587005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23761 13:41:22.617707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23762 13:41:22.618109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23764 13:41:22.649550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23765 13:41:22.650040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23767 13:41:22.681307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23769 13:41:22.681884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23770 13:41:22.713337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23771 13:41:22.713806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23773 13:41:22.746138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23774 13:41:22.746632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23776 13:41:22.778603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23777 13:41:22.779069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23779 13:41:22.810643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23780 13:41:22.811141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23782 13:41:22.842462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23783 13:41:22.842925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23785 13:41:22.873742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23786 13:41:22.874256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23788 13:41:22.905873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23789 13:41:22.906332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23791 13:41:22.937930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23792 13:41:22.938320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23794 13:41:22.970712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23796 13:41:22.971243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23797 13:41:23.003937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23799 13:41:23.004489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23800 13:41:23.036107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23801 13:41:23.036559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23803 13:41:23.067550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23805 13:41:23.068101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23806 13:41:23.099359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23808 13:41:23.099921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23809 13:41:23.130500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23810 13:41:23.130905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23812 13:41:23.162814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23813 13:41:23.163223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23815 13:41:23.195606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23816 13:41:23.196017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23818 13:41:23.227349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23820 13:41:23.227971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23821 13:41:23.258680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23823 13:41:23.259300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23824 13:41:23.289621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23825 13:41:23.290095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23827 13:41:23.321402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23828 13:41:23.321904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23830 13:41:23.354020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23831 13:41:23.354494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23833 13:41:23.385289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23835 13:41:23.385901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23836 13:41:23.416754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23838 13:41:23.417344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23839 13:41:23.447825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23840 13:41:23.448241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23842 13:41:23.478804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23844 13:41:23.479246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23845 13:41:23.509858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23847 13:41:23.510320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23848 13:41:23.541396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23850 13:41:23.542022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23851 13:41:23.572246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23853 13:41:23.572721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23854 13:41:23.603155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23856 13:41:23.603620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23857 13:41:23.634427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23858 13:41:23.634928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23860 13:41:23.666630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23861 13:41:23.667104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23863 13:41:23.697802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23864 13:41:23.698225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23866 13:41:23.729570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23868 13:41:23.730136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23869 13:41:23.761875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23870 13:41:23.762353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23872 13:41:23.793143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23873 13:41:23.793638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23875 13:41:23.824868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23877 13:41:23.825332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23878 13:41:23.856348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23880 13:41:23.856817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23881 13:41:23.887181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23882 13:41:23.887621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23884 13:41:23.918456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23885 13:41:23.918877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23887 13:41:23.950628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23888 13:41:23.951053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23890 13:41:23.981658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23891 13:41:23.982134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23893 13:41:24.014062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23894 13:41:24.014524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23896 13:41:24.046485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23897 13:41:24.046941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23899 13:41:24.077784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23901 13:41:24.078337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23902 13:41:24.109175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23903 13:41:24.109633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23905 13:41:24.141029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23906 13:41:24.141485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23908 13:41:24.173280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23909 13:41:24.173682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23911 13:41:24.205272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23912 13:41:24.205683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23914 13:41:24.236929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23915 13:41:24.237316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23917 13:41:24.268945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23918 13:41:24.269345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23920 13:41:24.301280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23922 13:41:24.301717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23923 13:41:24.333459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23925 13:41:24.334032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23926 13:41:24.366131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23927 13:41:24.366600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23929 13:41:24.398083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23931 13:41:24.398706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23932 13:41:24.429573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23933 13:41:24.429985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23935 13:41:24.461575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23937 13:41:24.462017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23938 13:41:24.493932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
23939 13:41:24.494327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
23941 13:41:24.525626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
23943 13:41:24.526201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
23944 13:41:24.558533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
23945 13:41:24.558980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
23947 13:41:24.590022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
23949 13:41:24.590638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
23950 13:41:24.621312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
23952 13:41:24.621931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
23953 13:41:24.652494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
23955 13:41:24.653120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
23956 13:41:24.683947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
23957 13:41:24.684419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
23959 13:41:24.715561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
23960 13:41:24.716032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
23962 13:41:24.747039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
23964 13:41:24.747659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
23965 13:41:24.779682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
23966 13:41:24.780143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
23968 13:41:24.811949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
23969 13:41:24.812426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
23971 13:41:24.843320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
23972 13:41:24.843783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
23974 13:41:24.875021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
23975 13:41:24.875473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
23977 13:41:24.906633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
23978 13:41:24.907127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
23980 13:41:24.938193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
23981 13:41:24.938679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
23983 13:41:24.970084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
23985 13:41:24.970549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
23986 13:41:25.001694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
23988 13:41:25.002159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
23989 13:41:25.033364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
23990 13:41:25.033838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
23992 13:41:25.065768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
23994 13:41:25.066228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
23995 13:41:25.106105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
23996 13:41:25.106563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
23998 13:41:25.121154 <47>[ 228.264898] systemd-journald[105]: Sent WATCHDOG=1 notification.
23999 13:41:25.158499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
24000 13:41:25.158958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
24002 13:41:25.190795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
24003 13:41:25.191201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
24005 13:41:25.223393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
24007 13:41:25.223864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
24008 13:41:25.255307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
24010 13:41:25.255902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
24011 13:41:25.287468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
24012 13:41:25.287869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
24014 13:41:25.319449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
24016 13:41:25.319917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
24017 13:41:25.351848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
24019 13:41:25.352319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
24020 13:41:25.383106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
24021 13:41:25.383524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
24023 13:41:25.417174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
24025 13:41:25.417658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
24026 13:41:25.450037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
24027 13:41:25.450453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
24029 13:41:25.481415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
24030 13:41:25.481838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
24032 13:41:25.513044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
24033 13:41:25.513466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
24035 13:41:25.544077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
24036 13:41:25.544495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
24038 13:41:25.578010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
24040 13:41:25.578462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
24041 13:41:25.611603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
24043 13:41:25.612076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
24044 13:41:25.646637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
24046 13:41:25.647212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
24047 13:41:25.681833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
24048 13:41:25.682263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
24050 13:41:25.718163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
24051 13:41:25.718548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
24053 13:41:25.752242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
24054 13:41:25.752617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
24056 13:41:25.785137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
24057 13:41:25.785579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
24059 13:41:25.818060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
24060 13:41:25.818510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
24062 13:41:25.850872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
24064 13:41:25.851493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
24065 13:41:25.882302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
24066 13:41:25.882790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
24068 13:41:25.914424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
24069 13:41:25.914888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
24071 13:41:25.946379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
24072 13:41:25.946859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
24074 13:41:25.978381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
24075 13:41:25.978847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
24077 13:41:26.010929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
24079 13:41:26.011413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
24080 13:41:26.042719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
24082 13:41:26.043185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
24083 13:41:26.074396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
24084 13:41:26.074830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
24086 13:41:26.107251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
24088 13:41:26.107970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
24089 13:41:26.139542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
24090 13:41:26.139952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
24092 13:41:26.171581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
24093 13:41:26.172005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
24095 13:41:26.203137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
24096 13:41:26.203557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
24098 13:41:26.235515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
24099 13:41:26.235946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
24101 13:41:26.268494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
24103 13:41:26.268969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
24104 13:41:26.302063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
24105 13:41:26.302478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
24107 13:41:26.334025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
24108 13:41:26.334442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
24110 13:41:26.367369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
24111 13:41:26.367758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
24113 13:41:26.399622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
24114 13:41:26.400026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
24116 13:41:26.431579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
24117 13:41:26.432058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
24119 13:41:26.464144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
24120 13:41:26.464610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
24122 13:41:26.495821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
24124 13:41:26.496391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
24125 13:41:26.528009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
24126 13:41:26.528461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
24128 13:41:26.562746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
24129 13:41:26.563200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
24131 13:41:26.597738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
24132 13:41:26.598210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
24134 13:41:26.632086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
24135 13:41:26.632523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
24137 13:41:26.665500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
24138 13:41:26.665939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
24140 13:41:26.698012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
24141 13:41:26.698429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
24143 13:41:26.730643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
24144 13:41:26.731146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
24146 13:41:26.762474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
24147 13:41:26.762900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
24149 13:41:26.793716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
24150 13:41:26.794148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
24152 13:41:26.825873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
24153 13:41:26.826300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
24155 13:41:26.858062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
24156 13:41:26.858523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
24158 13:41:26.889948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
24159 13:41:26.890396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
24161 13:41:26.921733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
24162 13:41:26.922175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
24164 13:41:26.955755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
24166 13:41:26.956329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
24167 13:41:26.988289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
24168 13:41:26.988753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
24170 13:41:27.021542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
24171 13:41:27.021974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
24173 13:41:27.054741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
24174 13:41:27.055237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
24176 13:41:27.087562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
24177 13:41:27.088034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
24179 13:41:27.120095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
24181 13:41:27.120686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
24182 13:41:27.153460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
24183 13:41:27.153947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
24185 13:41:27.186217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
24187 13:41:27.186686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
24188 13:41:27.218456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
24189 13:41:27.218927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
24191 13:41:27.250232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
24193 13:41:27.250780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
24194 13:41:27.284428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
24196 13:41:27.285005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
24197 13:41:27.316593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
24199 13:41:27.317141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
24200 13:41:27.349702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
24201 13:41:27.350169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
24203 13:41:27.382037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
24204 13:41:27.382487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
24206 13:41:27.413409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
24207 13:41:27.413834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
24209 13:41:27.445823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
24210 13:41:27.446254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
24212 13:41:27.477907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
24213 13:41:27.478386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
24215 13:41:27.509402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
24216 13:41:27.509820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
24218 13:41:27.540658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
24220 13:41:27.541110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
24221 13:41:27.572488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
24223 13:41:27.572947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
24224 13:41:27.603332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
24225 13:41:27.603779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
24227 13:41:27.634203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
24228 13:41:27.634623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
24230 13:41:27.665629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
24232 13:41:27.666103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
24233 13:41:27.697254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
24234 13:41:27.697684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
24236 13:41:27.728218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
24237 13:41:27.728692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
24239 13:41:27.760212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
24241 13:41:27.760829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
24242 13:41:27.792306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
24244 13:41:27.792880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
24245 13:41:27.829448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
24246 13:41:27.829942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
24248 13:41:27.866452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
24250 13:41:27.867011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
24251 13:41:27.900349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
24252 13:41:27.900774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
24254 13:41:27.933143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
24255 13:41:27.933605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
24257 13:41:27.965265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
24258 13:41:27.965691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
24260 13:41:27.997784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
24261 13:41:27.998220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
24263 13:41:28.032710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
24265 13:41:28.033283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
24266 13:41:28.064940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
24268 13:41:28.065489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
24269 13:41:28.097095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
24270 13:41:28.097499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
24272 13:41:28.128954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
24273 13:41:28.129412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
24275 13:41:28.160853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
24277 13:41:28.161444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
24278 13:41:28.194049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
24279 13:41:28.194471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
24281 13:41:28.225709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
24282 13:41:28.226132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
24284 13:41:28.257291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
24285 13:41:28.257682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
24287 13:41:28.289464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
24288 13:41:28.289901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
24290 13:41:28.321684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
24292 13:41:28.322318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
24293 13:41:28.355516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
24294 13:41:28.355989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
24296 13:41:28.390876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
24298 13:41:28.391336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
24299 13:41:28.425452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24301 13:41:28.426093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
24302 13:41:28.458917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24303 13:41:28.459397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24305 13:41:28.493520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24307 13:41:28.494164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24308 13:41:28.527832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24310 13:41:28.528301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24311 13:41:28.568559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24313 13:41:28.569017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24314 13:41:28.608761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24315 13:41:28.609198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24317 13:41:28.641421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24319 13:41:28.642050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24320 13:41:28.673041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24321 13:41:28.673481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24323 13:41:28.703869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24324 13:41:28.704310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24326 13:41:28.735086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24327 13:41:28.735580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24329 13:41:28.766744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24330 13:41:28.767168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24332 13:41:28.798448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24333 13:41:28.798877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24335 13:41:28.830614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24336 13:41:28.831013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24338 13:41:28.862437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24340 13:41:28.862858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24341 13:41:28.893914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24343 13:41:28.894349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24344 13:41:28.925686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24345 13:41:28.926067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24347 13:41:28.958346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24348 13:41:28.958811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24350 13:41:28.990588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24351 13:41:28.991005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24353 13:41:29.021884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24354 13:41:29.022309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24356 13:41:29.053557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24357 13:41:29.054010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24359 13:41:29.084786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24360 13:41:29.085205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24362 13:41:29.116085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24364 13:41:29.116549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24365 13:41:29.147216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24366 13:41:29.147636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24368 13:41:29.178180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24370 13:41:29.178830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24371 13:41:29.209347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24373 13:41:29.209965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24374 13:41:29.241771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24376 13:41:29.242347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24377 13:41:29.273621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24378 13:41:29.274115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24380 13:41:29.304844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24381 13:41:29.305321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24383 13:41:29.336040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24384 13:41:29.336530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24386 13:41:29.368129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24387 13:41:29.368615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24389 13:41:29.400198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24390 13:41:29.400598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24392 13:41:29.433234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24393 13:41:29.433663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24395 13:41:29.465424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24396 13:41:29.465836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24398 13:41:29.497137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24400 13:41:29.497596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24401 13:41:29.528292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24402 13:41:29.528781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24404 13:41:29.563001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24405 13:41:29.563473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24407 13:41:29.595755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24408 13:41:29.596190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24410 13:41:29.626957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24411 13:41:29.627404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24413 13:41:29.659164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24414 13:41:29.659596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24416 13:41:29.691026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24417 13:41:29.691450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24419 13:41:29.722176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24420 13:41:29.722598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24422 13:41:29.754399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24424 13:41:29.754867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24425 13:41:29.787136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24426 13:41:29.787628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24428 13:41:29.819012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24430 13:41:29.819654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24431 13:41:29.853048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24432 13:41:29.853508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24434 13:41:29.885327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24436 13:41:29.885766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24437 13:41:29.917575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24438 13:41:29.917973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24440 13:41:29.949344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24441 13:41:29.949741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24443 13:41:29.981760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24444 13:41:29.982204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24446 13:41:30.014781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24448 13:41:30.015254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24449 13:41:30.046378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24450 13:41:30.046816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24452 13:41:30.091017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24453 13:41:30.091496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24455 13:41:30.143834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24457 13:41:30.144347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24458 13:41:30.187684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24459 13:41:30.188166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24461 13:41:30.238010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24462 13:41:30.238472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24464 13:41:30.282502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24465 13:41:30.282999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24467 13:41:30.317455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24468 13:41:30.317871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24470 13:41:30.353122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24471 13:41:30.353483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24473 13:41:30.387703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24474 13:41:30.388169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24476 13:41:30.422992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24477 13:41:30.423417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24479 13:41:30.458792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24481 13:41:30.459260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24482 13:41:30.493926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24483 13:41:30.494339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24485 13:41:30.529968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24486 13:41:30.530388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24488 13:41:30.566770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24490 13:41:30.567249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24491 13:41:30.604542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24493 13:41:30.605002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24494 13:41:30.643727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24495 13:41:30.644144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24497 13:41:30.684698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24499 13:41:30.685164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24500 13:41:30.723021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24501 13:41:30.723431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24503 13:41:30.761325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24504 13:41:30.761736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24506 13:41:30.796928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24508 13:41:30.797514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24509 13:41:30.832251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24511 13:41:30.832714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24512 13:41:30.867793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24514 13:41:30.868370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24515 13:41:30.902444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24517 13:41:30.902914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24518 13:41:30.937805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24519 13:41:30.938244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24521 13:41:30.974651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24522 13:41:30.975131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24524 13:41:31.009780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24525 13:41:31.010205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24527 13:41:31.043977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24528 13:41:31.044429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24530 13:41:31.080571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24532 13:41:31.081040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24533 13:41:31.116020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24534 13:41:31.116444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24536 13:41:31.152313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24537 13:41:31.152772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24539 13:41:31.187422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24540 13:41:31.187895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24542 13:41:31.222832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24543 13:41:31.223269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24545 13:41:31.258618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24547 13:41:31.259290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24548 13:41:31.293219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24549 13:41:31.293663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24551 13:41:31.329162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24553 13:41:31.329713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24554 13:41:31.363676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24556 13:41:31.364270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24557 13:41:31.397942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24558 13:41:31.398323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24560 13:41:31.432234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24561 13:41:31.432691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24563 13:41:31.465936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24564 13:41:31.466354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24566 13:41:31.500144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24568 13:41:31.500725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24569 13:41:31.534472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24570 13:41:31.534946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24572 13:41:31.568583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24574 13:41:31.569046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24575 13:41:31.603706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24577 13:41:31.604366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24578 13:41:31.637945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24580 13:41:31.638542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24581 13:41:31.672973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24582 13:41:31.673391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24584 13:41:31.707118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24585 13:41:31.707558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24587 13:41:31.741698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24588 13:41:31.742128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24590 13:41:31.775750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24591 13:41:31.776180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24593 13:41:31.810198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24595 13:41:31.810797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24596 13:41:31.844401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24598 13:41:31.844955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24599 13:41:31.879510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24600 13:41:31.879952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24602 13:41:31.913567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24603 13:41:31.913996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24605 13:41:31.948085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24607 13:41:31.948666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24608 13:41:31.982784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24610 13:41:31.983348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24611 13:41:32.017607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24612 13:41:32.018037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24614 13:41:32.052249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24616 13:41:32.052829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24617 13:41:32.086506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24618 13:41:32.086948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24620 13:41:32.120681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24622 13:41:32.121240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24623 13:41:32.155464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24624 13:41:32.155911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24626 13:41:32.189450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24627 13:41:32.189841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24629 13:41:32.224562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24631 13:41:32.224999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24632 13:41:32.259640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24633 13:41:32.260047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24635 13:41:32.294295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24636 13:41:32.294785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24638 13:41:32.329635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24640 13:41:32.330157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24641 13:41:32.364123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24642 13:41:32.364635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24644 13:41:32.398554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24645 13:41:32.398991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24647 13:41:32.433052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24649 13:41:32.433519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24650 13:41:32.467417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24652 13:41:32.467871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24653 13:41:32.501925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24654 13:41:32.502342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24656 13:41:32.536838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24657 13:41:32.537282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24659 13:41:32.571226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24660 13:41:32.571622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24662 13:41:32.605878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24663 13:41:32.606250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24665 13:41:32.640215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24666 13:41:32.640602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24668 13:41:32.674658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24670 13:41:32.675108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24671 13:41:32.709716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24672 13:41:32.710132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24674 13:41:32.743942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24676 13:41:32.744415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24677 13:41:32.778890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24678 13:41:32.779303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24680 13:41:32.814052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24681 13:41:32.814463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24683 13:41:32.848949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24685 13:41:32.849419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24686 13:41:32.882888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24687 13:41:32.883329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24689 13:41:32.917477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24690 13:41:32.917958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24692 13:41:32.952209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24694 13:41:32.952667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24695 13:41:32.987764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24696 13:41:32.988180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24698 13:41:33.022242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24700 13:41:33.022812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24701 13:41:33.057719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24702 13:41:33.058144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24704 13:41:33.092277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24706 13:41:33.092799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24707 13:41:33.126986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24708 13:41:33.127468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24710 13:41:33.161211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24712 13:41:33.161689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24713 13:41:33.199052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24714 13:41:33.199427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24716 13:41:33.234781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24717 13:41:33.235212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24719 13:41:33.270138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24720 13:41:33.270563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24722 13:41:33.309900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24724 13:41:33.310653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24725 13:41:33.345809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24726 13:41:33.346338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24728 13:41:33.383018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24730 13:41:33.383489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24731 13:41:33.418249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24732 13:41:33.418670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24734 13:41:33.454295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24735 13:41:33.454725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24737 13:41:33.489841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24738 13:41:33.490265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24740 13:41:33.526596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24742 13:41:33.527169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24743 13:41:33.561962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24744 13:41:33.562430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24746 13:41:33.598031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24747 13:41:33.598512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24749 13:41:33.633229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24750 13:41:33.633742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24752 13:41:33.667983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24753 13:41:33.668452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24755 13:41:33.706569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24756 13:41:33.706981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24758 13:41:33.744452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24760 13:41:33.745196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24761 13:41:33.780633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24763 13:41:33.781098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24764 13:41:33.816566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24766 13:41:33.816947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24767 13:41:33.851956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24768 13:41:33.852402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24770 13:41:33.886627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24771 13:41:33.887071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24773 13:41:33.922993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24774 13:41:33.923408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24776 13:41:33.960719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24778 13:41:33.961326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24779 13:41:33.997779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24781 13:41:33.998321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24782 13:41:34.033846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24783 13:41:34.034377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24785 13:41:34.069329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24786 13:41:34.069750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24788 13:41:34.119537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24789 13:41:34.119967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24791 13:41:34.155832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24792 13:41:34.156258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24794 13:41:34.192231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24796 13:41:34.192984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24797 13:41:34.228951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24798 13:41:34.229496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24800 13:41:34.265717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24801 13:41:34.266146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24803 13:41:34.303053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24804 13:41:34.303542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24806 13:41:34.346387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24807 13:41:34.346802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24809 13:41:34.379506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24811 13:41:34.379971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24812 13:41:34.412972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24814 13:41:34.413441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24815 13:41:34.445810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24816 13:41:34.446207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24818 13:41:34.478853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24819 13:41:34.479294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24821 13:41:34.513120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24823 13:41:34.513579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24824 13:41:34.547376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24826 13:41:34.548020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24827 13:41:34.587129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24828 13:41:34.587572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24830 13:41:34.621975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24831 13:41:34.622413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24833 13:41:34.657609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24834 13:41:34.658058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24836 13:41:34.692213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24838 13:41:34.692786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24839 13:41:34.725941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24841 13:41:34.726503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24842 13:41:34.760105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24844 13:41:34.760673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24845 13:41:34.794663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24847 13:41:34.795273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24848 13:41:34.829042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24850 13:41:34.829599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24851 13:41:34.862611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24852 13:41:34.863010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24854 13:41:34.897730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24855 13:41:34.898192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24857 13:41:34.932188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24858 13:41:34.932657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24860 13:41:34.966290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24861 13:41:34.966735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24863 13:41:35.001377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24865 13:41:35.001834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24866 13:41:35.036418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24867 13:41:35.036937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24869 13:41:35.070824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24870 13:41:35.071388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24872 13:41:35.106023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24874 13:41:35.106624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24875 13:41:35.150681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24876 13:41:35.151083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24878 13:41:35.184106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24879 13:41:35.184495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24881 13:41:35.219445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24883 13:41:35.220186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24884 13:41:35.253827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24885 13:41:35.254288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24887 13:41:35.297432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24888 13:41:35.297835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24890 13:41:35.333070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24891 13:41:35.333482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24893 13:41:35.389444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24895 13:41:35.390094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24896 13:41:35.423731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24898 13:41:35.424353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24899 13:41:35.458604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24900 13:41:35.459099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24902 13:41:35.492169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24903 13:41:35.492658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24905 13:41:35.526833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24906 13:41:35.527305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24908 13:41:35.560946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24909 13:41:35.561434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24911 13:41:35.598389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24912 13:41:35.598781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24914 13:41:35.634103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24915 13:41:35.634516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24917 13:41:35.668099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24918 13:41:35.668549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24920 13:41:35.701591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24921 13:41:35.702029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24923 13:41:35.747709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24924 13:41:35.748130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24926 13:41:35.785810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24927 13:41:35.786253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24929 13:41:35.821392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24930 13:41:35.821812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24932 13:41:35.856128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24933 13:41:35.856544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24935 13:41:35.893276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24936 13:41:35.893713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24938 13:41:35.929213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24939 13:41:35.929605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
24941 13:41:35.964840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
24942 13:41:35.965288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
24944 13:41:35.999571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
24945 13:41:36.000007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
24947 13:41:36.037312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
24948 13:41:36.037750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
24950 13:41:36.071621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
24952 13:41:36.072197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
24953 13:41:36.105723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
24954 13:41:36.106199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
24956 13:41:36.139371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
24957 13:41:36.139798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
24959 13:41:36.175126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
24960 13:41:36.175559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
24962 13:41:36.208372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
24964 13:41:36.208829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
24965 13:41:36.252674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
24967 13:41:36.253142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
24968 13:41:36.295762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
24969 13:41:36.296221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
24971 13:41:36.331156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
24973 13:41:36.331716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
24974 13:41:36.367005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
24975 13:41:36.367436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
24977 13:41:36.402142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
24978 13:41:36.402624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
24980 13:41:36.435610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
24981 13:41:36.436097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
24983 13:41:36.470551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
24984 13:41:36.471028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
24986 13:41:36.514058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
24987 13:41:36.514508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
24989 13:41:36.547301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
24990 13:41:36.547747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
24992 13:41:36.579820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
24993 13:41:36.580266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
24995 13:41:36.614082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
24996 13:41:36.614571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
24998 13:41:36.647153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
24999 13:41:36.647616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
25001 13:41:36.682589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
25002 13:41:36.683058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
25004 13:41:36.717643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
25006 13:41:36.718134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
25007 13:41:36.754904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
25008 13:41:36.755374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
25010 13:41:36.789395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
25012 13:41:36.790055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
25013 13:41:36.834900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
25014 13:41:36.835454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
25016 13:41:36.869480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
25017 13:41:36.869973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
25019 13:41:36.902835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
25020 13:41:36.903309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
25022 13:41:36.937393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
25023 13:41:36.937817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
25025 13:41:36.971319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
25027 13:41:36.971956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
25028 13:41:37.003430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
25030 13:41:37.003892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
25031 13:41:37.034985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
25033 13:41:37.035426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
25034 13:41:37.073987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
25035 13:41:37.074407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
25037 13:41:37.113252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
25038 13:41:37.113673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
25040 13:41:37.146550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
25042 13:41:37.147125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
25043 13:41:37.179541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
25044 13:41:37.179967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
25046 13:41:37.213314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
25047 13:41:37.213760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
25049 13:41:37.251307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
25050 13:41:37.251732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
25052 13:41:37.282997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
25053 13:41:37.283421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
25055 13:41:37.314436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
25056 13:41:37.314852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
25058 13:41:37.345509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
25059 13:41:37.345964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
25061 13:41:37.380113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
25062 13:41:37.380593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
25064 13:41:37.414271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
25065 13:41:37.414736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
25067 13:41:37.447259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
25068 13:41:37.447743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
25070 13:41:37.479923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
25071 13:41:37.480403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
25073 13:41:37.513286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
25075 13:41:37.513885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
25076 13:41:37.548019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
25077 13:41:37.548468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
25079 13:41:37.582742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
25080 13:41:37.583237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
25082 13:41:37.616401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
25084 13:41:37.617004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
25085 13:41:37.650752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
25086 13:41:37.651178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
25088 13:41:37.683927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
25090 13:41:37.684386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
25091 13:41:37.717804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
25092 13:41:37.718246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
25094 13:41:37.751279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
25096 13:41:37.751744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
25097 13:41:37.785976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
25098 13:41:37.786400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
25100 13:41:37.819189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
25101 13:41:37.819624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
25103 13:41:37.851915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
25105 13:41:37.852379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
25106 13:41:37.885423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
25107 13:41:37.885922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
25109 13:41:37.919125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
25110 13:41:37.919610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
25112 13:41:37.952565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
25114 13:41:37.953172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
25115 13:41:37.985747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
25116 13:41:37.986233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
25118 13:41:38.018799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
25119 13:41:38.019273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
25121 13:41:38.051513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
25122 13:41:38.051934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
25124 13:41:38.083028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
25125 13:41:38.083472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
25127 13:41:38.114906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
25128 13:41:38.115330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
25130 13:41:38.145685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
25131 13:41:38.146125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
25133 13:41:38.177523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
25135 13:41:38.177996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
25136 13:41:38.210238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
25137 13:41:38.210682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
25139 13:41:38.242583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
25140 13:41:38.243027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
25142 13:41:38.274969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
25143 13:41:38.275468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
25145 13:41:38.308380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
25147 13:41:38.308999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
25148 13:41:38.342185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
25149 13:41:38.342639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
25151 13:41:38.374662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
25153 13:41:38.375261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
25154 13:41:38.405657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
25156 13:41:38.406359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
25157 13:41:38.437716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
25159 13:41:38.438271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
25160 13:41:38.473747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
25161 13:41:38.474232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
25163 13:41:38.507200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
25164 13:41:38.507692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
25166 13:41:38.538462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
25167 13:41:38.538942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
25169 13:41:38.571474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
25171 13:41:38.572064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
25172 13:41:38.602973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
25174 13:41:38.603547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
25175 13:41:38.634546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
25176 13:41:38.635023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
25178 13:41:38.666250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
25179 13:41:38.666723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
25181 13:41:38.698009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
25183 13:41:38.698602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
25184 13:41:38.733277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
25185 13:41:38.733739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
25187 13:41:38.764741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
25188 13:41:38.765228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
25190 13:41:38.795936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
25192 13:41:38.796554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
25193 13:41:38.826959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
25194 13:41:38.827365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
25196 13:41:38.858216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
25197 13:41:38.858632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
25199 13:41:38.889703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
25201 13:41:38.890152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
25202 13:41:38.921344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
25203 13:41:38.921814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
25205 13:41:38.954023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
25207 13:41:38.954653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
25208 13:41:38.985574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
25209 13:41:38.986044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
25211 13:41:39.017690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
25212 13:41:39.018135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
25214 13:41:39.050240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
25216 13:41:39.050790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
25217 13:41:39.081430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
25219 13:41:39.081866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
25220 13:41:39.113290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
25221 13:41:39.113689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
25223 13:41:39.145169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
25225 13:41:39.145601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
25226 13:41:39.176473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
25228 13:41:39.176930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
25229 13:41:39.208084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
25230 13:41:39.208523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
25232 13:41:39.239750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
25234 13:41:39.240220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
25235 13:41:39.270789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
25236 13:41:39.271211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
25238 13:41:39.302445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
25240 13:41:39.302898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
25241 13:41:39.333916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
25243 13:41:39.334349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
25244 13:41:39.365712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
25245 13:41:39.366125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
25247 13:41:39.397904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
25248 13:41:39.398308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
25250 13:41:39.429461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
25252 13:41:39.430113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
25253 13:41:39.460187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
25254 13:41:39.460662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
25256 13:41:39.492056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
25257 13:41:39.492526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
25259 13:41:39.523239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
25260 13:41:39.523698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
25262 13:41:39.554223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
25264 13:41:39.554768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
25265 13:41:39.585619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
25266 13:41:39.586086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
25268 13:41:39.617336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
25269 13:41:39.617749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
25271 13:41:39.649510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
25272 13:41:39.649999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
25274 13:41:39.681549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
25275 13:41:39.682046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
25277 13:41:39.713048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
25278 13:41:39.713473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
25280 13:41:39.743748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
25281 13:41:39.744171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
25283 13:41:39.774894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
25284 13:41:39.775339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
25286 13:41:39.805884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
25288 13:41:39.806418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
25289 13:41:39.837194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
25290 13:41:39.837688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
25292 13:41:39.868003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
25293 13:41:39.868489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
25295 13:41:39.899518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
25296 13:41:39.899944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
25298 13:41:39.930304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
25299 13:41:39.930717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25301 13:41:39.961497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25303 13:41:39.962147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25304 13:41:39.992168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25306 13:41:39.992732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25307 13:41:40.023274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25309 13:41:40.023819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25310 13:41:40.055020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25312 13:41:40.055481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25313 13:41:40.088982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25314 13:41:40.089401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25316 13:41:40.122942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25318 13:41:40.123585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25319 13:41:40.157893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25320 13:41:40.158349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25322 13:41:40.191142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25323 13:41:40.191585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25325 13:41:40.228943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25326 13:41:40.229488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25328 13:41:40.262953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25329 13:41:40.263493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25331 13:41:40.295851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25332 13:41:40.296347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25334 13:41:40.332953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25335 13:41:40.333446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25337 13:41:40.367644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25338 13:41:40.368165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25340 13:41:40.401942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25341 13:41:40.402479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25343 13:41:40.435217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25344 13:41:40.435713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25346 13:41:40.493602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25348 13:41:40.494075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25349 13:41:40.526262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25350 13:41:40.526673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25352 13:41:40.560387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25354 13:41:40.561144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25355 13:41:40.602308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25357 13:41:40.602902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25358 13:41:40.635733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25360 13:41:40.636307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25361 13:41:40.667364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25363 13:41:40.667936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25364 13:41:40.699217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25366 13:41:40.699789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25367 13:41:40.731114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25368 13:41:40.731547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25370 13:41:40.764976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25371 13:41:40.765428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25373 13:41:40.799890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25374 13:41:40.800290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25376 13:41:40.835083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25377 13:41:40.835539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25379 13:41:40.866216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25381 13:41:40.866691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25382 13:41:40.897533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25383 13:41:40.897974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25385 13:41:40.929529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25386 13:41:40.929956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25388 13:41:40.961555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25390 13:41:40.962032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25391 13:41:40.993629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25393 13:41:40.994239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25394 13:41:41.026738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25395 13:41:41.027209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25397 13:41:41.060585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25399 13:41:41.061238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25400 13:41:41.096578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25402 13:41:41.097325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25403 13:41:41.129708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25404 13:41:41.130267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25406 13:41:41.164148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25407 13:41:41.164624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25409 13:41:41.198573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25411 13:41:41.199035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25412 13:41:41.232952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25414 13:41:41.233525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25415 13:41:41.267140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25417 13:41:41.267883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25418 13:41:41.300589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25420 13:41:41.301058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25421 13:41:41.334401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25423 13:41:41.334960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25424 13:41:41.367759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25425 13:41:41.368216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25427 13:41:41.401724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25428 13:41:41.402178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25430 13:41:41.436096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25431 13:41:41.436647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25433 13:41:41.469014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25435 13:41:41.469760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25436 13:41:41.505105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25437 13:41:41.505556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25439 13:41:41.540125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25440 13:41:41.540589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25442 13:41:41.573861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25443 13:41:41.574315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25445 13:41:41.606079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25446 13:41:41.606554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25448 13:41:41.639405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25449 13:41:41.639866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25451 13:41:41.670577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25452 13:41:41.671038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25454 13:41:41.702254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25455 13:41:41.702698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25457 13:41:41.733803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25458 13:41:41.734267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25460 13:41:41.766398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25462 13:41:41.766984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25463 13:41:41.799349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25464 13:41:41.799895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25466 13:41:41.834182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25468 13:41:41.834755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25469 13:41:41.867003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25470 13:41:41.867476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25472 13:41:41.899684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25473 13:41:41.900123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25475 13:41:41.933660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25477 13:41:41.934114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25478 13:41:41.966639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25479 13:41:41.967098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25481 13:41:41.999079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25482 13:41:41.999545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25484 13:41:42.031065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25485 13:41:42.031489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25487 13:41:42.062261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25488 13:41:42.062742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25490 13:41:42.094681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25492 13:41:42.095258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25493 13:41:42.127395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25494 13:41:42.127846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25496 13:41:42.159359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25497 13:41:42.159815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25499 13:41:42.191210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25500 13:41:42.191682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25502 13:41:42.223877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25504 13:41:42.224471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25505 13:41:42.256075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25506 13:41:42.256541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25508 13:41:42.288155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25509 13:41:42.288598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25511 13:41:42.320400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25513 13:41:42.320864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25514 13:41:42.352624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25515 13:41:42.353054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25517 13:41:42.383947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25519 13:41:42.384415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25520 13:41:42.415897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25521 13:41:42.416325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25523 13:41:42.448902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25524 13:41:42.449316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25526 13:41:42.480628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25528 13:41:42.481084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25529 13:41:42.511761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25531 13:41:42.512402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25532 13:41:42.543409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25533 13:41:42.543890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25535 13:41:42.574736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25537 13:41:42.575383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25538 13:41:42.605676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25540 13:41:42.606311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25541 13:41:42.637765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25542 13:41:42.638189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25544 13:41:42.670518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25546 13:41:42.671010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25547 13:41:42.702887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25549 13:41:42.703528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25550 13:41:42.734447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25551 13:41:42.734930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25553 13:41:42.766753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25554 13:41:42.767246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25556 13:41:42.798639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25558 13:41:42.799104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25559 13:41:42.830964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25560 13:41:42.831380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25562 13:41:42.862753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25563 13:41:42.863197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25565 13:41:42.895690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25567 13:41:42.896162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25568 13:41:42.927919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25569 13:41:42.928358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25571 13:41:42.959912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25572 13:41:42.960356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25574 13:41:42.992687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25576 13:41:42.993147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25577 13:41:43.024579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25579 13:41:43.025056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25580 13:41:43.056660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25582 13:41:43.057129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25583 13:41:43.089390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25584 13:41:43.089845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25586 13:41:43.122135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25588 13:41:43.122765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25589 13:41:43.154237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25590 13:41:43.154721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25592 13:41:43.188918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25594 13:41:43.189552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25595 13:41:43.220020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25596 13:41:43.220489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25598 13:41:43.251222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25599 13:41:43.251666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25601 13:41:43.282294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25602 13:41:43.282706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25604 13:41:43.314159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25605 13:41:43.314597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25607 13:41:43.346848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25609 13:41:43.347295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25610 13:41:43.378503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25611 13:41:43.378939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25613 13:41:43.410620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25615 13:41:43.411084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25616 13:41:43.441976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25617 13:41:43.442395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25619 13:41:43.473652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25620 13:41:43.474069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25622 13:41:43.506123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25624 13:41:43.506572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25625 13:41:43.537737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25626 13:41:43.538203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25628 13:41:43.569724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25630 13:41:43.570299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25631 13:41:43.601669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25633 13:41:43.602134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25634 13:41:43.633371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25635 13:41:43.633795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25637 13:41:43.665480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25639 13:41:43.666043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25640 13:41:43.698515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25641 13:41:43.698929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25643 13:41:43.730676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25644 13:41:43.731087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25646 13:41:43.762618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25648 13:41:43.763071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25649 13:41:43.794909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25650 13:41:43.795319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25652 13:41:43.827186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25653 13:41:43.827599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25655 13:41:43.859598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25656 13:41:43.860075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25658 13:41:43.891463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25659 13:41:43.891901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25661 13:41:43.923678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25662 13:41:43.924143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25664 13:41:43.955195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25665 13:41:43.955655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25667 13:41:43.987679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25668 13:41:43.988150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25670 13:41:44.019705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25672 13:41:44.020350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25673 13:41:44.051386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25674 13:41:44.051864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25676 13:41:44.083230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25677 13:41:44.083715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25679 13:41:44.115535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25680 13:41:44.116054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25682 13:41:44.148222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25684 13:41:44.148865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25685 13:41:44.179947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25686 13:41:44.180366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25688 13:41:44.212099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25689 13:41:44.212517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25691 13:41:44.243911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25692 13:41:44.244372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25694 13:41:44.275960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25695 13:41:44.276412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25697 13:41:44.308199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25698 13:41:44.308657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25700 13:41:44.339454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25701 13:41:44.339907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25703 13:41:44.371119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25704 13:41:44.371579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25706 13:41:44.402751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25707 13:41:44.403243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25709 13:41:44.435240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25711 13:41:44.435812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25712 13:41:44.467909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25713 13:41:44.468392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25715 13:41:44.500235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25717 13:41:44.500789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25718 13:41:44.533038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25719 13:41:44.533502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25721 13:41:44.565608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25722 13:41:44.566023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25724 13:41:44.598412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25725 13:41:44.598846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25727 13:41:44.634887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25729 13:41:44.635353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25730 13:41:44.669175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25732 13:41:44.669662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25733 13:41:44.703408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25734 13:41:44.703837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25736 13:41:44.737596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25737 13:41:44.738046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25739 13:41:44.772434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25741 13:41:44.772916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25742 13:41:44.805660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25743 13:41:44.806092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25745 13:41:44.841026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25746 13:41:44.841574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25748 13:41:44.875618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25750 13:41:44.876276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25751 13:41:44.910012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25752 13:41:44.910413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25754 13:41:44.942563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25755 13:41:44.943028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25757 13:41:44.974818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25758 13:41:44.975232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25760 13:41:45.007530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25761 13:41:45.007950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25763 13:41:45.039348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25765 13:41:45.039877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25766 13:41:45.070173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25767 13:41:45.070590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25769 13:41:45.101768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25770 13:41:45.102174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25772 13:41:45.135021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25773 13:41:45.135488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25775 13:41:45.167614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25776 13:41:45.168050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25778 13:41:45.199706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25779 13:41:45.200149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25781 13:41:45.232521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25783 13:41:45.233139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25784 13:41:45.265366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25786 13:41:45.265820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25787 13:41:45.298269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25788 13:41:45.298686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25790 13:41:45.333811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25792 13:41:45.334405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25793 13:41:45.368177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25795 13:41:45.368912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25796 13:41:45.403075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25797 13:41:45.403644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25799 13:41:45.437686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25800 13:41:45.438139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25802 13:41:45.470811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25804 13:41:45.471221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25805 13:41:45.502491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25806 13:41:45.502907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25808 13:41:45.535265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25809 13:41:45.535748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25811 13:41:45.569454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25812 13:41:45.569963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25814 13:41:45.623282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25815 13:41:45.623786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25817 13:41:45.657181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25819 13:41:45.657765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25820 13:41:45.689214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25822 13:41:45.689783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25823 13:41:45.721553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25824 13:41:45.722024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25826 13:41:45.753548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25828 13:41:45.754119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25829 13:41:45.786102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25830 13:41:45.786567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25832 13:41:45.820563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25834 13:41:45.821195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25835 13:41:45.854224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25836 13:41:45.854685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25838 13:41:45.886044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25839 13:41:45.886434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25841 13:41:45.918373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25843 13:41:45.918810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25844 13:41:45.950389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25845 13:41:45.950847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25847 13:41:45.982582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25849 13:41:45.983220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25850 13:41:46.013987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25852 13:41:46.014640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25853 13:41:46.045396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25854 13:41:46.045880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25856 13:41:46.076950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25857 13:41:46.077439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25859 13:41:46.108136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25861 13:41:46.108791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25862 13:41:46.138924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25863 13:41:46.139400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25865 13:41:46.169719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25867 13:41:46.170354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25868 13:41:46.201630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25869 13:41:46.202103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25871 13:41:46.233295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25872 13:41:46.233742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25874 13:41:46.263939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25875 13:41:46.264445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25877 13:41:46.295437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25879 13:41:46.296053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25880 13:41:46.326160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25881 13:41:46.326636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25883 13:41:46.357487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25884 13:41:46.357958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25886 13:41:46.389102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25887 13:41:46.389587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25889 13:41:46.421237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25890 13:41:46.421692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25892 13:41:46.452522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25894 13:41:46.453096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25895 13:41:46.483839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25896 13:41:46.484262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25898 13:41:46.514970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25899 13:41:46.515386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25901 13:41:46.545910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25902 13:41:46.546336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25904 13:41:46.579328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25905 13:41:46.579751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25907 13:41:46.611514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25908 13:41:46.611999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25910 13:41:46.645739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25912 13:41:46.646309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25913 13:41:46.677543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25915 13:41:46.678123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25916 13:41:46.709543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25917 13:41:46.709965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25919 13:41:46.741098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25921 13:41:46.741553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25922 13:41:46.771682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25924 13:41:46.772150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25925 13:41:46.802639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25926 13:41:46.803099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25928 13:41:46.834737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25929 13:41:46.835153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25931 13:41:46.866014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25932 13:41:46.866422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25934 13:41:46.896833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25935 13:41:46.897258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25937 13:41:46.928294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
25938 13:41:46.928712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25940 13:41:46.959369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
25941 13:41:46.959776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
25943 13:41:46.991313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
25944 13:41:46.991769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
25946 13:41:47.022327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
25947 13:41:47.022801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
25949 13:41:47.053920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
25950 13:41:47.054375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
25952 13:41:47.085069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
25954 13:41:47.085622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
25955 13:41:47.116545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
25957 13:41:47.117193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
25958 13:41:47.148211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
25960 13:41:47.148679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
25961 13:41:47.179306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
25963 13:41:47.179767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
25964 13:41:47.211459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
25965 13:41:47.211940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
25967 13:41:47.243250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
25969 13:41:47.243889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
25970 13:41:47.274534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
25972 13:41:47.275104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
25973 13:41:47.306246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
25974 13:41:47.306659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
25976 13:41:47.338258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
25978 13:41:47.338808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
25979 13:41:47.369692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
25980 13:41:47.370143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
25982 13:41:47.401666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
25984 13:41:47.402208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
25985 13:41:47.433128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
25986 13:41:47.433591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
25988 13:41:47.464704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
25990 13:41:47.465246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
25991 13:41:47.496015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
25993 13:41:47.496469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
25994 13:41:47.527391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
25995 13:41:47.527818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
25997 13:41:47.559303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
25998 13:41:47.559708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
26000 13:41:47.591265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
26001 13:41:47.591714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
26003 13:41:47.623848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
26005 13:41:47.624309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
26006 13:41:47.657053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
26007 13:41:47.657501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
26009 13:41:47.690658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
26010 13:41:47.691086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
26012 13:41:47.723195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
26014 13:41:47.723652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
26015 13:41:47.757242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
26016 13:41:47.757663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
26018 13:41:47.791110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
26019 13:41:47.791593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
26021 13:41:47.826174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
26023 13:41:47.826856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
26024 13:41:47.861718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
26025 13:41:47.862180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
26027 13:41:47.898002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
26028 13:41:47.898463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
26030 13:41:47.931330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
26031 13:41:47.931779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
26033 13:41:47.964967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
26034 13:41:47.965453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
26036 13:41:47.998825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
26038 13:41:47.999386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
26039 13:41:48.033596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
26040 13:41:48.034021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
26042 13:41:48.075567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
26043 13:41:48.076024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
26045 13:41:48.110127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
26046 13:41:48.110563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
26048 13:41:48.143288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
26050 13:41:48.143847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
26051 13:41:48.175834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
26053 13:41:48.176389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
26054 13:41:48.211276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
26055 13:41:48.211733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
26057 13:41:48.256647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
26059 13:41:48.257207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
26060 13:41:48.297777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
26062 13:41:48.298255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
26063 13:41:48.334345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
26064 13:41:48.334783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
26066 13:41:48.373456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
26067 13:41:48.373979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
26069 13:41:48.414759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
26070 13:41:48.415180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
26072 13:41:48.467156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
26073 13:41:48.467562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
26075 13:41:48.503189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
26077 13:41:48.503668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
26078 13:41:48.540049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
26079 13:41:48.540444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
26081 13:41:48.587700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
26082 13:41:48.588258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
26084 13:41:48.621730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
26086 13:41:48.622299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
26087 13:41:48.653436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
26089 13:41:48.654003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
26090 13:41:48.687903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
26091 13:41:48.688381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
26093 13:41:48.724127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
26095 13:41:48.724729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
26096 13:41:48.764226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
26097 13:41:48.764789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
26099 13:41:48.802921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
26101 13:41:48.803507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
26102 13:41:48.835973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
26104 13:41:48.836451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
26105 13:41:48.867659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
26107 13:41:48.868105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
26108 13:41:48.903310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
26110 13:41:48.903778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
26111 13:41:48.937721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
26113 13:41:48.938487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
26114 13:41:48.970969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
26116 13:41:48.971615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
26117 13:41:49.005204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
26119 13:41:49.005688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
26120 13:41:49.040201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
26121 13:41:49.040622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
26123 13:41:49.074305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
26125 13:41:49.074774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
26126 13:41:49.105593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
26127 13:41:49.106096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
26129 13:41:49.137705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
26130 13:41:49.138178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
26132 13:41:49.169293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
26133 13:41:49.169777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
26135 13:41:49.201712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
26136 13:41:49.202159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
26138 13:41:49.233397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
26139 13:41:49.233904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
26141 13:41:49.266048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
26142 13:41:49.266470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
26144 13:41:49.308656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
26146 13:41:49.309309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
26147 13:41:49.342584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
26149 13:41:49.343264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
26150 13:41:49.375404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
26151 13:41:49.375859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
26153 13:41:49.409239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
26154 13:41:49.409678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
26156 13:41:49.443431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
26157 13:41:49.443860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
26159 13:41:49.477853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
26160 13:41:49.478338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
26162 13:41:49.511411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
26164 13:41:49.511906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
26165 13:41:49.548126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
26166 13:41:49.548552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
26168 13:41:49.582152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
26169 13:41:49.582636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
26171 13:41:49.617514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
26172 13:41:49.617945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
26174 13:41:49.651162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
26176 13:41:49.651625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
26177 13:41:49.696566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
26179 13:41:49.697028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
26180 13:41:49.731441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
26181 13:41:49.731928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
26183 13:41:49.765063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
26184 13:41:49.765509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
26186 13:41:49.800006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
26188 13:41:49.800480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
26189 13:41:49.833150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
26190 13:41:49.833601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
26192 13:41:49.865927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
26193 13:41:49.866378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
26195 13:41:49.904783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
26197 13:41:49.905547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
26198 13:41:49.953162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
26199 13:41:49.953714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
26201 13:41:49.989171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
26202 13:41:49.989699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
26204 13:41:50.021879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
26205 13:41:50.022426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
26207 13:41:50.055585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
26209 13:41:50.056158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
26210 13:41:50.088237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
26212 13:41:50.088790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
26213 13:41:50.121342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
26214 13:41:50.121790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
26216 13:41:50.158791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
26217 13:41:50.159220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
26219 13:41:50.191379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
26221 13:41:50.191821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
26222 13:41:50.223290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
26224 13:41:50.224046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
26225 13:41:50.255174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
26226 13:41:50.255589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
26228 13:41:50.291293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
26229 13:41:50.291711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
26231 13:41:50.327998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
26232 13:41:50.328429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
26234 13:41:50.364278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
26235 13:41:50.364704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
26237 13:41:50.399746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
26238 13:41:50.400237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
26240 13:41:50.434877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
26241 13:41:50.435438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
26243 13:41:50.470771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
26244 13:41:50.471318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
26246 13:41:50.506378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
26248 13:41:50.506850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
26249 13:41:50.542697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
26250 13:41:50.543254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
26252 13:41:50.579597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
26253 13:41:50.580101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
26255 13:41:50.615952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
26257 13:41:50.616599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
26258 13:41:50.652311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
26260 13:41:50.652782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
26261 13:41:50.691220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
26262 13:41:50.691642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
26264 13:41:50.764204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
26265 13:41:50.764583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
26267 13:41:50.807045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
26268 13:41:50.807437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
26270 13:41:50.847209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
26271 13:41:50.847687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
26273 13:41:50.883514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
26275 13:41:50.883996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
26276 13:41:50.919872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
26278 13:41:50.920437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
26279 13:41:50.955443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
26280 13:41:50.955911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
26282 13:41:50.990972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
26284 13:41:50.991439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
26285 13:41:51.025771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
26287 13:41:51.026236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
26288 13:41:51.061475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
26289 13:41:51.061941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
26291 13:41:51.097333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
26293 13:41:51.097911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
26294 13:41:51.133344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
26295 13:41:51.133765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
26297 13:41:51.169401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
26298 13:41:51.169882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
26300 13:41:51.205183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26302 13:41:51.205751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26303 13:41:51.241087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26304 13:41:51.241576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26306 13:41:51.277062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26308 13:41:51.277533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26309 13:41:51.313909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26310 13:41:51.314370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26312 13:41:51.350922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26313 13:41:51.351338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26315 13:41:51.386138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26316 13:41:51.386573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26318 13:41:51.421338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26319 13:41:51.421819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26321 13:41:51.457216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26323 13:41:51.457800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26324 13:41:51.493132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26325 13:41:51.493554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26327 13:41:51.529611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26329 13:41:51.530212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26330 13:41:51.565013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26331 13:41:51.565585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26333 13:41:51.601031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26335 13:41:51.601537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26336 13:41:51.635827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26337 13:41:51.636307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26339 13:41:51.670802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26340 13:41:51.671227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26342 13:41:51.705950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26343 13:41:51.706390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26345 13:41:51.741162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26346 13:41:51.741584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26348 13:41:51.775613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26349 13:41:51.776046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26351 13:41:51.811086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26352 13:41:51.811548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26354 13:41:51.846908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26355 13:41:51.847399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26357 13:41:51.883343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26359 13:41:51.883900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26360 13:41:51.920071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26361 13:41:51.920548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26363 13:41:51.955964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26364 13:41:51.956440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26366 13:41:51.992165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26367 13:41:51.992625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26369 13:41:52.028618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26371 13:41:52.029087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26372 13:41:52.064577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26374 13:41:52.065035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26375 13:41:52.102835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26376 13:41:52.103259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26378 13:41:52.153143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26379 13:41:52.153588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26381 13:41:52.205200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26382 13:41:52.205634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26384 13:41:52.241576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26385 13:41:52.242067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26387 13:41:52.277676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26389 13:41:52.278244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26390 13:41:52.313687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26391 13:41:52.314096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26393 13:41:52.349361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26395 13:41:52.349882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26396 13:41:52.385594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26397 13:41:52.386012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26399 13:41:52.422763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26400 13:41:52.423183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26402 13:41:52.467378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26404 13:41:52.467746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26405 13:41:52.509498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26406 13:41:52.509990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26408 13:41:52.542283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26409 13:41:52.542749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26411 13:41:52.573555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26412 13:41:52.573964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26414 13:41:52.605000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26416 13:41:52.605432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26417 13:41:52.636250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26418 13:41:52.636703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26420 13:41:52.667337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26421 13:41:52.667773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26423 13:41:52.698679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26424 13:41:52.699118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26426 13:41:52.730050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26428 13:41:52.730617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26429 13:41:52.761442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26430 13:41:52.761915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26432 13:41:52.792472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26434 13:41:52.793101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26435 13:41:52.823678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26437 13:41:52.824250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26438 13:41:52.854227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26439 13:41:52.854643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26441 13:41:52.885375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26442 13:41:52.885807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26444 13:41:52.916659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26446 13:41:52.917193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26447 13:41:52.949679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26449 13:41:52.950242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26450 13:41:52.980204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26452 13:41:52.980702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26453 13:41:53.011303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26454 13:41:53.011715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26456 13:41:53.043073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26457 13:41:53.043530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26459 13:41:53.074147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26460 13:41:53.074602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26462 13:41:53.106139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26464 13:41:53.106632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26465 13:41:53.137463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26467 13:41:53.137979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26468 13:41:53.168324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26470 13:41:53.168816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26471 13:41:53.199346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26472 13:41:53.199754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26474 13:41:53.230974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26476 13:41:53.231417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26477 13:41:53.262518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26478 13:41:53.262921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26480 13:41:53.294085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26482 13:41:53.294635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26483 13:41:53.325232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26484 13:41:53.325636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26486 13:41:53.357596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26488 13:41:53.358056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26489 13:41:53.389272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26491 13:41:53.389854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26492 13:41:53.420179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26494 13:41:53.420789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26495 13:41:53.451490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26496 13:41:53.451936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26498 13:41:53.482339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26499 13:41:53.482817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26501 13:41:53.513723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26503 13:41:53.514297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26504 13:41:53.546202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26505 13:41:53.546605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26507 13:41:53.577993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26508 13:41:53.578422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26510 13:41:53.609591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26511 13:41:53.610045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26513 13:41:53.641299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26514 13:41:53.641739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26516 13:41:53.673349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26517 13:41:53.673824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26519 13:41:53.705549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26520 13:41:53.706002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26522 13:41:53.737459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26523 13:41:53.737951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26525 13:41:53.768970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26527 13:41:53.769534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26528 13:41:53.800225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26530 13:41:53.800784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26531 13:41:53.831177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26533 13:41:53.831733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26534 13:41:53.862436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26536 13:41:53.863000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26537 13:41:53.893713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26539 13:41:53.894268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26540 13:41:53.925223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26541 13:41:53.925690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26543 13:41:53.960523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26545 13:41:53.961077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26546 13:41:53.992015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26548 13:41:53.992572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26549 13:41:54.023577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26550 13:41:54.024025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26552 13:41:54.054705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26553 13:41:54.055155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26555 13:41:54.086085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26556 13:41:54.086540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26558 13:41:54.118146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26559 13:41:54.118618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26561 13:41:54.149640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26562 13:41:54.150099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26564 13:41:54.185576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26565 13:41:54.186070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26567 13:41:54.223407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26569 13:41:54.223959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26570 13:41:54.255356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26572 13:41:54.255948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26573 13:41:54.286190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26574 13:41:54.286620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26576 13:41:54.317126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26577 13:41:54.317562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26579 13:41:54.347988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26580 13:41:54.348431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26582 13:41:54.379706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26584 13:41:54.380296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26585 13:41:54.411281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26587 13:41:54.411725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26588 13:41:54.442687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26589 13:41:54.443142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26591 13:41:54.474561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26592 13:41:54.475012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26594 13:41:54.506058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26596 13:41:54.506608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26597 13:41:54.537522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26598 13:41:54.537982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26600 13:41:54.570197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26602 13:41:54.570834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26603 13:41:54.601702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26604 13:41:54.602116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26606 13:41:54.634065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26607 13:41:54.634560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26609 13:41:54.666341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26611 13:41:54.666816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26612 13:41:54.698755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26614 13:41:54.699125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26615 13:41:54.731279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26616 13:41:54.731653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26618 13:41:54.763561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26619 13:41:54.763978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26621 13:41:54.798640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26622 13:41:54.799058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26624 13:41:54.832066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26626 13:41:54.832537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26627 13:41:54.864048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26629 13:41:54.864505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26630 13:41:54.897140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26631 13:41:54.897558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26633 13:41:54.929858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26635 13:41:54.930315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26636 13:41:54.962346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26638 13:41:54.962930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26639 13:41:55.001702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26640 13:41:55.002081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26642 13:41:55.038647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26643 13:41:55.039092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26645 13:41:55.071975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26646 13:41:55.072411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26648 13:41:55.103523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26650 13:41:55.103996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26651 13:41:55.134655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26652 13:41:55.135067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26654 13:41:55.166328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26655 13:41:55.166729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26657 13:41:55.198067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26658 13:41:55.198485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26660 13:41:55.229394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26662 13:41:55.229909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26663 13:41:55.260857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26664 13:41:55.261250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26666 13:41:55.292053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26668 13:41:55.292558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26669 13:41:55.323075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26671 13:41:55.323631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26672 13:41:55.354603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26673 13:41:55.355048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26675 13:41:55.386028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26676 13:41:55.386468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26678 13:41:55.417846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26680 13:41:55.418307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26681 13:41:55.448962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26682 13:41:55.449341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26684 13:41:55.479797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26685 13:41:55.480233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26687 13:41:55.510584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26688 13:41:55.511011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26690 13:41:55.541600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26691 13:41:55.542043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26693 13:41:55.573403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26694 13:41:55.573765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26696 13:41:55.604886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26698 13:41:55.605287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26699 13:41:55.635401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26700 13:41:55.635835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26702 13:41:55.665776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26703 13:41:55.666202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26705 13:41:55.698076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26706 13:41:55.698551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26708 13:41:55.730722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26710 13:41:55.731288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26711 13:41:55.763398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26713 13:41:55.763984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26714 13:41:55.794932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26715 13:41:55.795413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26717 13:41:55.849961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26718 13:41:55.850410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26720 13:41:55.886932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26721 13:41:55.887292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26723 13:41:55.922860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26724 13:41:55.923250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26726 13:41:55.957441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26727 13:41:55.957791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26729 13:41:55.991817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26730 13:41:55.992176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26732 13:41:56.026688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26733 13:41:56.027050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26735 13:41:56.061342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26736 13:41:56.061686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26738 13:41:56.095474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26739 13:41:56.095855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26741 13:41:56.127383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26742 13:41:56.127779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26744 13:41:56.159028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26745 13:41:56.159399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26747 13:41:56.190594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26748 13:41:56.190998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26750 13:41:56.222775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26751 13:41:56.223184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26753 13:41:56.254545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26754 13:41:56.254910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26756 13:41:56.286047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26757 13:41:56.286495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26759 13:41:56.317521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26760 13:41:56.317932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26762 13:41:56.350470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26763 13:41:56.350875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26765 13:41:56.384207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26767 13:41:56.384760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26768 13:41:56.418243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26770 13:41:56.418761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26771 13:41:56.452714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26773 13:41:56.453208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26774 13:41:56.487698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26775 13:41:56.488114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26777 13:41:56.521890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26778 13:41:56.522370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26780 13:41:56.556579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26782 13:41:56.557204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26783 13:41:56.591168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26784 13:41:56.591637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26786 13:41:56.625083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26787 13:41:56.625561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26789 13:41:56.658689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26791 13:41:56.659253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26792 13:41:56.693340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26793 13:41:56.693802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26795 13:41:56.725240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26796 13:41:56.725684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26798 13:41:56.757129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26800 13:41:56.757672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26801 13:41:56.788884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26803 13:41:56.789417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26804 13:41:56.820923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26806 13:41:56.821463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26807 13:41:56.853359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26809 13:41:56.853956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26810 13:41:56.886602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26811 13:41:56.887075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26813 13:41:56.918647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26814 13:41:56.919078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26816 13:41:56.950700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26817 13:41:56.951202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26819 13:41:56.982800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26820 13:41:56.983244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26822 13:41:57.014812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26824 13:41:57.015351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26825 13:41:57.046666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26826 13:41:57.047094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26828 13:41:57.078686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26829 13:41:57.079135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26831 13:41:57.111202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26833 13:41:57.111751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26834 13:41:57.143000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26836 13:41:57.143543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26837 13:41:57.175062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26838 13:41:57.175498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26840 13:41:57.207049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26842 13:41:57.207599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26843 13:41:57.239267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26844 13:41:57.239708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26846 13:41:57.271524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26847 13:41:57.271928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26849 13:41:57.303724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26851 13:41:57.304166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26852 13:41:57.335531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26854 13:41:57.336076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26855 13:41:57.367552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26856 13:41:57.367954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26858 13:41:57.398955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26859 13:41:57.399355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26861 13:41:57.431118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26863 13:41:57.431602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26864 13:41:57.462945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26865 13:41:57.463428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26867 13:41:57.494967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26869 13:41:57.495469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26870 13:41:57.527024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26871 13:41:57.527428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26873 13:41:57.559039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26874 13:41:57.559447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26876 13:41:57.590958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26877 13:41:57.591358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26879 13:41:57.623287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26881 13:41:57.623815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26882 13:41:57.654873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26883 13:41:57.655280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26885 13:41:57.687955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26886 13:41:57.688417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26888 13:41:57.721387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26889 13:41:57.721814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26891 13:41:57.753483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26892 13:41:57.753895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26894 13:41:57.785359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26895 13:41:57.785761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26897 13:41:57.817395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26898 13:41:57.817826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26900 13:41:57.849323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26901 13:41:57.849776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26903 13:41:57.882251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26905 13:41:57.882742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26906 13:41:57.913980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26907 13:41:57.914377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26909 13:41:57.946402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26911 13:41:57.946904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26912 13:41:57.978462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26913 13:41:57.978904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26915 13:41:58.010711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26916 13:41:58.011164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26918 13:41:58.042862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26920 13:41:58.043390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26921 13:41:58.074636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26922 13:41:58.075077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26924 13:41:58.106794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26925 13:41:58.107236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26927 13:41:58.139336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26929 13:41:58.139877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26930 13:41:58.172020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26931 13:41:58.172481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26933 13:41:58.204145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26934 13:41:58.204590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26936 13:41:58.236535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26938 13:41:58.237063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26939 13:41:58.268894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
26940 13:41:58.269358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
26942 13:41:58.301381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
26943 13:41:58.301766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
26945 13:41:58.333489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
26946 13:41:58.333929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
26948 13:41:58.365550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
26949 13:41:58.365998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
26951 13:41:58.397260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
26952 13:41:58.397697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
26954 13:41:58.429227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
26955 13:41:58.429672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
26957 13:41:58.461415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
26958 13:41:58.461889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
26960 13:41:58.493694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
26961 13:41:58.494156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
26963 13:41:58.525798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
26964 13:41:58.526202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
26966 13:41:58.558764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
26968 13:41:58.559209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
26969 13:41:58.590930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
26970 13:41:58.591376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
26972 13:41:58.623040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
26973 13:41:58.623490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
26975 13:41:58.655307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
26976 13:41:58.655750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
26978 13:41:58.687583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
26979 13:41:58.688036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
26981 13:41:58.719731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
26982 13:41:58.720200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
26984 13:41:58.754205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
26986 13:41:58.754674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
26987 13:41:58.786639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
26989 13:41:58.787093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
26990 13:41:58.818104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
26992 13:41:58.818694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
26993 13:41:58.849697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
26995 13:41:58.850212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
26996 13:41:58.881615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
26997 13:41:58.882067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
26999 13:41:58.914126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
27000 13:41:58.914517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
27002 13:41:58.945719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
27003 13:41:58.946129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
27005 13:41:58.977582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
27007 13:41:58.978104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
27008 13:41:59.017626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
27009 13:41:59.018031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
27011 13:41:59.061830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
27012 13:41:59.062264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
27014 13:41:59.101993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
27015 13:41:59.102448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
27017 13:41:59.134870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
27019 13:41:59.135419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
27020 13:41:59.165518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
27021 13:41:59.165947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
27023 13:41:59.196620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
27025 13:41:59.197065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
27026 13:41:59.227505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
27028 13:41:59.228057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
27029 13:41:59.258189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
27031 13:41:59.258696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
27032 13:41:59.289303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
27034 13:41:59.289855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
27035 13:41:59.319911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
27036 13:41:59.320300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
27038 13:41:59.351085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
27040 13:41:59.351584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
27041 13:41:59.381971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
27042 13:41:59.382399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
27044 13:41:59.412937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
27045 13:41:59.413325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
27047 13:41:59.443458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
27048 13:41:59.443918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
27050 13:41:59.474370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
27051 13:41:59.474844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
27053 13:41:59.505817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
27055 13:41:59.506444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
27056 13:41:59.537320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
27058 13:41:59.537963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
27059 13:41:59.568829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
27060 13:41:59.569282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
27062 13:41:59.600445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
27064 13:41:59.601042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
27065 13:41:59.632445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
27067 13:41:59.633040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
27068 13:41:59.664039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
27070 13:41:59.664654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
27071 13:41:59.695336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
27072 13:41:59.695792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
27074 13:41:59.726493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
27076 13:41:59.727136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
27077 13:41:59.757203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
27078 13:41:59.757620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
27080 13:41:59.788935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
27082 13:41:59.789486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
27083 13:41:59.819941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
27085 13:41:59.820482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
27086 13:41:59.850686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
27088 13:41:59.851195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
27089 13:41:59.881808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
27091 13:41:59.882351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
27092 13:41:59.912905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
27093 13:41:59.913282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
27095 13:41:59.944128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
27096 13:41:59.944496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
27098 13:41:59.975153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
27099 13:41:59.975521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
27101 13:42:00.006673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
27102 13:42:00.007088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
27104 13:42:00.039182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
27105 13:42:00.039584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
27107 13:42:00.070745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
27108 13:42:00.071198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
27110 13:42:00.101217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
27111 13:42:00.101697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
27113 13:42:00.132801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
27115 13:42:00.133422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
27116 13:42:00.163657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
27117 13:42:00.164127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
27119 13:42:00.194686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
27120 13:42:00.195160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
27122 13:42:00.225405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
27124 13:42:00.225976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
27125 13:42:00.257570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
27127 13:42:00.258150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
27128 13:42:00.288518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
27130 13:42:00.289067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
27131 13:42:00.319287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
27132 13:42:00.319730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
27134 13:42:00.350857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
27136 13:42:00.351445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
27137 13:42:00.381986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
27138 13:42:00.382446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
27140 13:42:00.413535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
27141 13:42:00.413956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
27143 13:42:00.445644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
27144 13:42:00.446069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
27146 13:42:00.476993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
27148 13:42:00.477431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
27149 13:42:00.507897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
27150 13:42:00.508303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
27152 13:42:00.539572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
27153 13:42:00.539979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
27155 13:42:00.570957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
27157 13:42:00.571552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
27158 13:42:00.603379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
27160 13:42:00.603828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
27161 13:42:00.635087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
27162 13:42:00.635491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
27164 13:42:00.666757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
27165 13:42:00.667211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
27167 13:42:00.699915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
27168 13:42:00.700399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
27170 13:42:00.732557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
27172 13:42:00.733112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
27173 13:42:00.766330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
27174 13:42:00.766756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
27176 13:42:00.801424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
27178 13:42:00.801996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
27179 13:42:00.835359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
27180 13:42:00.835832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
27182 13:42:00.868036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
27183 13:42:00.868499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
27185 13:42:00.900163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
27187 13:42:00.900701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
27188 13:42:00.931989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
27189 13:42:00.932404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
27191 13:42:00.986437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
27192 13:42:00.986915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
27194 13:42:01.017792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
27196 13:42:01.018368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
27197 13:42:01.050666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
27199 13:42:01.051223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
27200 13:42:01.084198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
27202 13:42:01.084802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
27203 13:42:01.115887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
27205 13:42:01.116440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
27206 13:42:01.146644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
27207 13:42:01.147109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
27209 13:42:01.177737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
27210 13:42:01.178205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
27212 13:42:01.209098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
27213 13:42:01.209559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
27215 13:42:01.239963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
27217 13:42:01.240540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
27218 13:42:01.270996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
27219 13:42:01.271452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
27221 13:42:01.301795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
27223 13:42:01.302289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
27224 13:42:01.332757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
27225 13:42:01.333174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
27227 13:42:01.363414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
27229 13:42:01.363928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
27230 13:42:01.394439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
27232 13:42:01.394932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
27233 13:42:01.425473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
27234 13:42:01.425890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
27236 13:42:01.457086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
27237 13:42:01.457496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
27239 13:42:01.490837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
27240 13:42:01.491376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
27242 13:42:01.522286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
27243 13:42:01.522740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
27245 13:42:01.554092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
27246 13:42:01.554546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
27248 13:42:01.585520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
27250 13:42:01.586048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
27251 13:42:01.617077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
27253 13:42:01.617591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
27254 13:42:01.647880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
27255 13:42:01.648318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
27257 13:42:01.679424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
27258 13:42:01.679854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
27260 13:42:01.710287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
27261 13:42:01.710682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
27263 13:42:01.741165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
27264 13:42:01.741578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
27266 13:42:01.771838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
27268 13:42:01.772343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
27269 13:42:01.802626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
27270 13:42:01.803031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
27272 13:42:01.834325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
27274 13:42:01.834870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
27275 13:42:01.865458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
27277 13:42:01.865925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
27278 13:42:01.897068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
27280 13:42:01.897619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
27281 13:42:01.928162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
27282 13:42:01.928612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
27284 13:42:01.958772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
27285 13:42:01.959221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
27287 13:42:01.990739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
27288 13:42:01.991199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
27290 13:42:02.021534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
27291 13:42:02.021957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
27293 13:42:02.052586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
27295 13:42:02.053016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
27296 13:42:02.083756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
27298 13:42:02.084199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
27299 13:42:02.114991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27300 13:42:02.115446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27302 13:42:02.145767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27303 13:42:02.146174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27305 13:42:02.176987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27306 13:42:02.177377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27308 13:42:02.208168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27310 13:42:02.208618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27311 13:42:02.239439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27313 13:42:02.239870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27314 13:42:02.270266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27315 13:42:02.270658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27317 13:42:02.301542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27318 13:42:02.301973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27320 13:42:02.337769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27322 13:42:02.338222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27323 13:42:02.369581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27324 13:42:02.369979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27326 13:42:02.401432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27327 13:42:02.401883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27329 13:42:02.433000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27331 13:42:02.433529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27332 13:42:02.463578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27333 13:42:02.463966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27335 13:42:02.494697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27336 13:42:02.495153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27338 13:42:02.525520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27340 13:42:02.526062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27341 13:42:02.557595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27342 13:42:02.558016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27344 13:42:02.591506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27346 13:42:02.591958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27347 13:42:02.623456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27348 13:42:02.623863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27350 13:42:02.655696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27352 13:42:02.656132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27353 13:42:02.687264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27354 13:42:02.687804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27356 13:42:02.720000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27357 13:42:02.720542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27359 13:42:02.753986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27360 13:42:02.754445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27362 13:42:02.791682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27364 13:42:02.792316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27365 13:42:02.825571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27366 13:42:02.826013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27368 13:42:02.859404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27370 13:42:02.859912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27371 13:42:02.893095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27373 13:42:02.893601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27374 13:42:02.925762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27376 13:42:02.926304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27377 13:42:02.959012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27378 13:42:02.959431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27380 13:42:02.992472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27382 13:42:02.992995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27383 13:42:03.026616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27385 13:42:03.027155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27386 13:42:03.059586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27387 13:42:03.060010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27389 13:42:03.090718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27391 13:42:03.091228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27392 13:42:03.121713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27393 13:42:03.122145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27395 13:42:03.153241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27396 13:42:03.153610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27398 13:42:03.183826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27400 13:42:03.184261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27401 13:42:03.214212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27402 13:42:03.214582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27404 13:42:03.245762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27406 13:42:03.246195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27407 13:42:03.276491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27409 13:42:03.276993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27410 13:42:03.306890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27412 13:42:03.307436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27413 13:42:03.337714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27415 13:42:03.338230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27416 13:42:03.368683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27418 13:42:03.369241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27419 13:42:03.399601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27421 13:42:03.400156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27422 13:42:03.434274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27424 13:42:03.434861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27425 13:42:03.465500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27426 13:42:03.465922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27428 13:42:03.496128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27429 13:42:03.496562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27431 13:42:03.527064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27433 13:42:03.527631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27434 13:42:03.557510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27435 13:42:03.557947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27437 13:42:03.588628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27439 13:42:03.589056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27440 13:42:03.619569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27442 13:42:03.620112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27443 13:42:03.650946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27444 13:42:03.651382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27446 13:42:03.682474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27447 13:42:03.682902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27449 13:42:03.713309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27450 13:42:03.713690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27452 13:42:03.744166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27453 13:42:03.744588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27455 13:42:03.775709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27457 13:42:03.776338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27458 13:42:03.805998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27459 13:42:03.806401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27461 13:42:03.837252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27462 13:42:03.837620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27464 13:42:03.869230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27466 13:42:03.869811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27467 13:42:03.899823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27469 13:42:03.900410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27470 13:42:03.930227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27472 13:42:03.930738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27473 13:42:03.961136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27474 13:42:03.961522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27476 13:42:03.991934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27477 13:42:03.992360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27479 13:42:04.023766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27480 13:42:04.024193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27482 13:42:04.056555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27484 13:42:04.057155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27485 13:42:04.087455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27487 13:42:04.088062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27488 13:42:04.118512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27489 13:42:04.119037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27491 13:42:04.150510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27492 13:42:04.150970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27494 13:42:04.181813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27495 13:42:04.182251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27497 13:42:04.213320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27498 13:42:04.213781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27500 13:42:04.244144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27501 13:42:04.244565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27503 13:42:04.275233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27505 13:42:04.275760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27506 13:42:04.305620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27507 13:42:04.306044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27509 13:42:04.336595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27511 13:42:04.337098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27512 13:42:04.367539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27513 13:42:04.367959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27515 13:42:04.398564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27516 13:42:04.398992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27518 13:42:04.430083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27520 13:42:04.430659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27521 13:42:04.461395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27522 13:42:04.461808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27524 13:42:04.493165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27525 13:42:04.493604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27527 13:42:04.524499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27529 13:42:04.525040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27530 13:42:04.555226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27531 13:42:04.555694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27533 13:42:04.587754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27535 13:42:04.588383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27536 13:42:04.618514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27537 13:42:04.618955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27539 13:42:04.650030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27540 13:42:04.650453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27542 13:42:04.682010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27544 13:42:04.682541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27545 13:42:04.712880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27546 13:42:04.713311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27548 13:42:04.743576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27549 13:42:04.743994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27551 13:42:04.774830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27553 13:42:04.775350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27554 13:42:04.805901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27555 13:42:04.806330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27557 13:42:04.837076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27558 13:42:04.837530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27560 13:42:04.869166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27561 13:42:04.869558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27563 13:42:04.901329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27564 13:42:04.901784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27566 13:42:04.932048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27567 13:42:04.932491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27569 13:42:04.963170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27570 13:42:04.963629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27572 13:42:04.994486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27573 13:42:04.994937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27575 13:42:05.026695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27576 13:42:05.027107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27578 13:42:05.057870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27579 13:42:05.058273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27581 13:42:05.089726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27582 13:42:05.090202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27584 13:42:05.122144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27585 13:42:05.122636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27587 13:42:05.155015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27589 13:42:05.155647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27590 13:42:05.188126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27592 13:42:05.188706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27593 13:42:05.220198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27595 13:42:05.220762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27596 13:42:05.251682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27597 13:42:05.252138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27599 13:42:05.283322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27600 13:42:05.283830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27602 13:42:05.315344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27604 13:42:05.315914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27605 13:42:05.347424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27607 13:42:05.347975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27608 13:42:05.378452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27609 13:42:05.378866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27611 13:42:05.409500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27612 13:42:05.409922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27614 13:42:05.443011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27615 13:42:05.443486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27617 13:42:05.475910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27618 13:42:05.476324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27620 13:42:05.507067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27621 13:42:05.507452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27623 13:42:05.538221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27624 13:42:05.538652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27626 13:42:05.569256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27627 13:42:05.569694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27629 13:42:05.600539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27631 13:42:05.601062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27632 13:42:05.631449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27633 13:42:05.631873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27635 13:42:05.662812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27636 13:42:05.663224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27638 13:42:05.694539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27640 13:42:05.695093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27641 13:42:05.728413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27643 13:42:05.728886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27644 13:42:05.765605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27646 13:42:05.766072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27647 13:42:05.801501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27648 13:42:05.801974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27650 13:42:05.834799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27651 13:42:05.835268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27653 13:42:05.868630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27655 13:42:05.869067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27656 13:42:05.902622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27658 13:42:05.903035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27659 13:42:05.934627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27660 13:42:05.935045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27662 13:42:05.965448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27663 13:42:05.965835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27665 13:42:05.996013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27666 13:42:05.996382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27668 13:42:06.026903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27669 13:42:06.027282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27671 13:42:06.066493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27672 13:42:06.066896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27674 13:42:06.110790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27675 13:42:06.111195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27677 13:42:06.143746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27679 13:42:06.144167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27680 13:42:06.177369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27681 13:42:06.177753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27683 13:42:06.210819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27685 13:42:06.211457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27686 13:42:06.244062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27688 13:42:06.244635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27689 13:42:06.277817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27690 13:42:06.278274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27692 13:42:06.313947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27693 13:42:06.314368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27695 13:42:06.348151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27697 13:42:06.348719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27698 13:42:06.381658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27699 13:42:06.382132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27701 13:42:06.414579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27703 13:42:06.415140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27704 13:42:06.448039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27705 13:42:06.448492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27707 13:42:06.482211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27708 13:42:06.482653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27710 13:42:06.517422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27712 13:42:06.517889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27713 13:42:06.551197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27714 13:42:06.551627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27716 13:42:06.586200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27718 13:42:06.586662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27719 13:42:06.620970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27721 13:42:06.621436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27722 13:42:06.653764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27723 13:42:06.654154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27725 13:42:06.686961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27726 13:42:06.687351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27728 13:42:06.720456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27730 13:42:06.720872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27731 13:42:06.753867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27732 13:42:06.754251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27734 13:42:06.787838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27736 13:42:06.788286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27737 13:42:06.821438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27738 13:42:06.821859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27740 13:42:06.854936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27741 13:42:06.855382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27743 13:42:06.888635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27745 13:42:06.889151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27746 13:42:06.921801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27748 13:42:06.922307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27749 13:42:06.955172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27751 13:42:06.955594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27752 13:42:06.989557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27754 13:42:06.990137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27755 13:42:07.023106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27756 13:42:07.023564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27758 13:42:07.055528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27759 13:42:07.055999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27761 13:42:07.089841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27763 13:42:07.090306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27764 13:42:07.123881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27765 13:42:07.124307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27767 13:42:07.158336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27768 13:42:07.158787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27770 13:42:07.191897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27771 13:42:07.192384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27773 13:42:07.225513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27775 13:42:07.225985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27776 13:42:07.258801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27777 13:42:07.259188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27779 13:42:07.291920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27781 13:42:07.292458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27782 13:42:07.324966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27783 13:42:07.325372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27785 13:42:07.357795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27786 13:42:07.358205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27788 13:42:07.389670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27790 13:42:07.390297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27791 13:42:07.420646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27792 13:42:07.421101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27794 13:42:07.451339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27795 13:42:07.451748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27797 13:42:07.482152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27799 13:42:07.482783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27800 13:42:07.512912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27802 13:42:07.513362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27803 13:42:07.543866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27804 13:42:07.544276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27806 13:42:07.575524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27808 13:42:07.575962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27809 13:42:07.606972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27810 13:42:07.607376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27812 13:42:07.637994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27813 13:42:07.638386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27815 13:42:07.669391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27816 13:42:07.669805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27818 13:42:07.701237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27820 13:42:07.701848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27821 13:42:07.733339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27822 13:42:07.733824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27824 13:42:07.765023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27826 13:42:07.765640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27827 13:42:07.795756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27829 13:42:07.796148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27830 13:42:07.827287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27831 13:42:07.827683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27833 13:42:07.858106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27835 13:42:07.858625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27836 13:42:07.889030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27838 13:42:07.889547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27839 13:42:07.919858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27840 13:42:07.920303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27842 13:42:07.949844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27843 13:42:07.950245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27845 13:42:07.980832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27847 13:42:07.981364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27848 13:42:08.011764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27849 13:42:08.012193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27851 13:42:08.043546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27852 13:42:08.044027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27854 13:42:08.074380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27855 13:42:08.074807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27857 13:42:08.105564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27859 13:42:08.106166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27860 13:42:08.135865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27861 13:42:08.136328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27863 13:42:08.168864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27864 13:42:08.169340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27866 13:42:08.200186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27868 13:42:08.200713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27869 13:42:08.230983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27870 13:42:08.231450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27872 13:42:08.262050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27874 13:42:08.262489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27875 13:42:08.293493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27877 13:42:08.294048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27878 13:42:08.324411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27880 13:42:08.324953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27881 13:42:08.355304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27883 13:42:08.355830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27884 13:42:08.385794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27885 13:42:08.386257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27887 13:42:08.416856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27889 13:42:08.417379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27890 13:42:08.447778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27891 13:42:08.448339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27893 13:42:08.478600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27894 13:42:08.479163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27896 13:42:08.509734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27897 13:42:08.510318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27899 13:42:08.541602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27901 13:42:08.542071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27902 13:42:08.573761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27903 13:42:08.574185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27905 13:42:08.605335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27907 13:42:08.605880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27908 13:42:08.636752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27909 13:42:08.637232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27911 13:42:08.667587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27912 13:42:08.667989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27914 13:42:08.699040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27916 13:42:08.699665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27917 13:42:08.730565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27919 13:42:08.731193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27920 13:42:08.761593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27921 13:42:08.762070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27923 13:42:08.793373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27924 13:42:08.793857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27926 13:42:08.826812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27928 13:42:08.827373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27929 13:42:08.858694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27930 13:42:08.859142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27932 13:42:08.890858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27933 13:42:08.891335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27935 13:42:08.922962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27936 13:42:08.923381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27938 13:42:08.954364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
27940 13:42:08.954916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27941 13:42:08.985421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
27943 13:42:08.985961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
27944 13:42:09.017530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
27945 13:42:09.018003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
27947 13:42:09.048328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
27949 13:42:09.048903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
27950 13:42:09.078905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
27951 13:42:09.079347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
27953 13:42:09.109888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
27955 13:42:09.110343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
27956 13:42:09.141323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
27958 13:42:09.141945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
27959 13:42:09.173022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
27960 13:42:09.173483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
27962 13:42:09.204218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
27964 13:42:09.204825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
27965 13:42:09.234689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
27966 13:42:09.235130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
27968 13:42:09.265459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
27970 13:42:09.266029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
27971 13:42:09.296032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
27972 13:42:09.296489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
27974 13:42:09.327085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
27976 13:42:09.327694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
27977 13:42:09.357705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
27979 13:42:09.358235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
27980 13:42:09.390212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
27982 13:42:09.390750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
27983 13:42:09.422847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
27984 13:42:09.423391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
27986 13:42:09.455317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
27988 13:42:09.455783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
27989 13:42:09.488081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
27990 13:42:09.488520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
27992 13:42:09.521350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
27994 13:42:09.521941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
27995 13:42:09.553769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
27996 13:42:09.554139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
27998 13:42:09.588234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
28000 13:42:09.588667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
28001 13:42:09.621703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
28003 13:42:09.622128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
28004 13:42:09.654460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
28005 13:42:09.654960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
28007 13:42:09.688293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
28009 13:42:09.688898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
28010 13:42:09.721935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
28012 13:42:09.722495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
28013 13:42:09.755244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
28014 13:42:09.755711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
28016 13:42:09.789405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
28017 13:42:09.789881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
28019 13:42:09.823697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
28020 13:42:09.824180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
28022 13:42:09.858072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
28023 13:42:09.858497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
28025 13:42:09.892197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
28027 13:42:09.892667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
28028 13:42:09.926428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
28029 13:42:09.926894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
28031 13:42:09.959639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
28033 13:42:09.960166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
28034 13:42:09.993554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
28036 13:42:09.994216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
28037 13:42:10.026605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
28038 13:42:10.027045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
28040 13:42:10.058742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
28042 13:42:10.059258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
28043 13:42:10.090095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
28045 13:42:10.090612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
28046 13:42:10.121578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
28047 13:42:10.122001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
28049 13:42:10.153066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
28051 13:42:10.153565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
28052 13:42:10.184137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
28053 13:42:10.184569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
28055 13:42:10.216065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
28057 13:42:10.216600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
28058 13:42:10.247219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
28059 13:42:10.247668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
28061 13:42:10.278693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
28062 13:42:10.279089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
28064 13:42:10.310037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
28066 13:42:10.310552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
28067 13:42:10.341437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
28069 13:42:10.341957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
28070 13:42:10.372372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
28072 13:42:10.372946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
28073 13:42:10.403288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
28074 13:42:10.403724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
28076 13:42:10.434432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
28078 13:42:10.435005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
28079 13:42:10.465697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
28081 13:42:10.466220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
28082 13:42:10.497159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
28084 13:42:10.497670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
28085 13:42:10.528385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
28087 13:42:10.528920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
28088 13:42:10.558955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
28089 13:42:10.559373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
28091 13:42:10.591528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
28092 13:42:10.592000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
28094 13:42:10.623325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
28095 13:42:10.623749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
28097 13:42:10.654917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
28099 13:42:10.655494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
28100 13:42:10.686115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
28102 13:42:10.686656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
28103 13:42:10.718175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
28105 13:42:10.718743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
28106 13:42:10.750856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
28108 13:42:10.751399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
28109 13:42:10.781975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
28110 13:42:10.782440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
28112 13:42:10.813864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
28113 13:42:10.814437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
28115 13:42:10.845638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
28116 13:42:10.846076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
28118 13:42:10.879190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
28119 13:42:10.879630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
28121 13:42:10.911527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
28123 13:42:10.911898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
28124 13:42:10.943595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
28125 13:42:10.944050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
28127 13:42:10.974785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
28129 13:42:10.975194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
28130 13:42:11.005819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
28132 13:42:11.006205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
28133 13:42:11.037374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
28134 13:42:11.037825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
28136 13:42:11.070023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
28138 13:42:11.070606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
28139 13:42:11.101808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
28140 13:42:11.102265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
28142 13:42:11.133560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
28143 13:42:11.134045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
28145 13:42:11.165570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
28147 13:42:11.166126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
28148 13:42:11.216012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
28149 13:42:11.216488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
28151 13:42:11.248094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
28153 13:42:11.248639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
28154 13:42:11.278622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
28155 13:42:11.279068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
28157 13:42:11.309691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
28159 13:42:11.310314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
28160 13:42:11.340466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
28162 13:42:11.341126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
28163 13:42:11.371451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
28164 13:42:11.371914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
28166 13:42:11.401983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
28168 13:42:11.402588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
28169 13:42:11.432794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
28171 13:42:11.433398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
28172 13:42:11.463335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
28174 13:42:11.463958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
28175 13:42:11.493944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
28177 13:42:11.494547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
28178 13:42:11.524496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
28180 13:42:11.525124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
28181 13:42:11.555443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
28182 13:42:11.555894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
28184 13:42:11.586231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
28186 13:42:11.586777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
28187 13:42:11.617468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
28189 13:42:11.618023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
28190 13:42:11.649201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
28192 13:42:11.649833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
28193 13:42:11.679780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
28195 13:42:11.680306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
28196 13:42:11.710145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
28197 13:42:11.710615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
28199 13:42:11.741285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
28201 13:42:11.741867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
28202 13:42:11.771660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
28203 13:42:11.772127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
28205 13:42:11.802589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
28206 13:42:11.803030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
28208 13:42:11.833915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
28210 13:42:11.834466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
28211 13:42:11.864876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
28212 13:42:11.865337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
28214 13:42:11.896336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
28216 13:42:11.896906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
28217 13:42:11.927763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
28219 13:42:11.928372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
28220 13:42:11.959265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
28222 13:42:11.959816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
28223 13:42:11.990402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
28225 13:42:11.990997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
28226 13:42:12.021365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
28227 13:42:12.021790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
28229 13:42:12.052877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
28231 13:42:12.053399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
28232 13:42:12.084295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
28234 13:42:12.084716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
28235 13:42:12.115492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
28236 13:42:12.115934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
28238 13:42:12.146047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
28239 13:42:12.146475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
28241 13:42:12.177005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
28243 13:42:12.177519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
28244 13:42:12.207735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
28245 13:42:12.208149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
28247 13:42:12.239173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
28249 13:42:12.239589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
28250 13:42:12.270002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
28251 13:42:12.270374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
28253 13:42:12.300965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
28255 13:42:12.301407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
28256 13:42:12.331668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
28258 13:42:12.332056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
28259 13:42:12.362964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
28261 13:42:12.363450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
28262 13:42:12.394326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
28264 13:42:12.394847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
28265 13:42:12.425418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
28267 13:42:12.425826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
28268 13:42:12.456745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
28270 13:42:12.457134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
28271 13:42:12.488392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
28273 13:42:12.488867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
28274 13:42:12.519657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
28275 13:42:12.520118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
28277 13:42:12.551389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
28279 13:42:12.551945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
28280 13:42:12.582815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
28281 13:42:12.583225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
28283 13:42:12.613958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
28284 13:42:12.614378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
28286 13:42:12.645994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
28287 13:42:12.646390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
28289 13:42:12.677396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
28290 13:42:12.677816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
28292 13:42:12.708808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
28293 13:42:12.709230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
28295 13:42:12.740190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
28297 13:42:12.740684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
28298 13:42:12.772013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
28299 13:42:12.772415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28301 13:42:12.803400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28302 13:42:12.803830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28304 13:42:12.835124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28305 13:42:12.835542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28307 13:42:12.866801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28308 13:42:12.867188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28310 13:42:12.898820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28311 13:42:12.899249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28313 13:42:12.930649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28314 13:42:12.931048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28316 13:42:12.962228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28318 13:42:12.962789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28319 13:42:12.993795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28321 13:42:12.994370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28322 13:42:13.025605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28323 13:42:13.026052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28325 13:42:13.059173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28326 13:42:13.059611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28328 13:42:13.093255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28330 13:42:13.093809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28331 13:42:13.127021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28333 13:42:13.127538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28334 13:42:13.161544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28335 13:42:13.161999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28337 13:42:13.195731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28338 13:42:13.196168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28340 13:42:13.230137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28342 13:42:13.230601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28343 13:42:13.265567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28345 13:42:13.266049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28346 13:42:13.299722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28347 13:42:13.300105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28349 13:42:13.334080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28351 13:42:13.334522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28352 13:42:13.368604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28354 13:42:13.369121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28355 13:42:13.402647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28356 13:42:13.403074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28358 13:42:13.436998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28359 13:42:13.437432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28361 13:42:13.470538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28362 13:42:13.470975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28364 13:42:13.505153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28365 13:42:13.505580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28367 13:42:13.539085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28368 13:42:13.539525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28370 13:42:13.573243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28371 13:42:13.573709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28373 13:42:13.607112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28374 13:42:13.607504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28376 13:42:13.643134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28378 13:42:13.643557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28379 13:42:13.676703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28381 13:42:13.677277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28382 13:42:13.710528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28383 13:42:13.711017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28385 13:42:13.744315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28387 13:42:13.744786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28388 13:42:13.777677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28390 13:42:13.778145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28391 13:42:13.810325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28392 13:42:13.810749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28394 13:42:13.844453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28396 13:42:13.844923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28397 13:42:13.878441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28398 13:42:13.878874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28400 13:42:13.912883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28401 13:42:13.913376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28403 13:42:13.946780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28404 13:42:13.947275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28406 13:42:13.981284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28408 13:42:13.981854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28409 13:42:14.015248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28410 13:42:14.015667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28412 13:42:14.048812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28413 13:42:14.049251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28415 13:42:14.081772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28417 13:42:14.082296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28418 13:42:14.114761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28419 13:42:14.115189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28421 13:42:14.148075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28422 13:42:14.148472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28424 13:42:14.183145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28426 13:42:14.183608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28427 13:42:14.217288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28429 13:42:14.217765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28430 13:42:14.251962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28431 13:42:14.252427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28433 13:42:14.285844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28435 13:42:14.286351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28436 13:42:14.319653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28437 13:42:14.320134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28439 13:42:14.354001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28440 13:42:14.354434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28442 13:42:14.388294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28444 13:42:14.388964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28445 13:42:14.422490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28446 13:42:14.422993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28448 13:42:14.456949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28449 13:42:14.457413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28451 13:42:14.491206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28452 13:42:14.491642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28454 13:42:14.525609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28455 13:42:14.526082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28457 13:42:14.562643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28458 13:42:14.563130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28460 13:42:14.597140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28462 13:42:14.597657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28463 13:42:14.631534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28465 13:42:14.632117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28466 13:42:14.665452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28467 13:42:14.665817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28469 13:42:14.699822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28470 13:42:14.700267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28472 13:42:14.733859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28473 13:42:14.734376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28475 13:42:14.768970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28477 13:42:14.769603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28478 13:42:14.803232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28480 13:42:14.803762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28481 13:42:14.836954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28482 13:42:14.837369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28484 13:42:14.870763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28486 13:42:14.871224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28487 13:42:14.905460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28489 13:42:14.906025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28490 13:42:14.938661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28491 13:42:14.939150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28493 13:42:14.973471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28494 13:42:14.973920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28496 13:42:15.008981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28498 13:42:15.009440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28499 13:42:15.043294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28501 13:42:15.043743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28502 13:42:15.078630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28504 13:42:15.079082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28505 13:42:15.113160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28506 13:42:15.113596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28508 13:42:15.147614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28510 13:42:15.148070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28511 13:42:15.181899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28513 13:42:15.182343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28514 13:42:15.216585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28516 13:42:15.217145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28517 13:42:15.250379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28519 13:42:15.251001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28520 13:42:15.285168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28521 13:42:15.285643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28523 13:42:15.317324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28524 13:42:15.317795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28526 13:42:15.349107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28527 13:42:15.349542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28529 13:42:15.380953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28531 13:42:15.381458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28532 13:42:15.412616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28533 13:42:15.413026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28535 13:42:15.444983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28537 13:42:15.445376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28538 13:42:15.476515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28540 13:42:15.477079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28541 13:42:15.508467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28543 13:42:15.509090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28544 13:42:15.539900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28545 13:42:15.540365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28547 13:42:15.571684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28549 13:42:15.572257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28550 13:42:15.603555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28551 13:42:15.604028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28553 13:42:15.634802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28554 13:42:15.635257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28556 13:42:15.666709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28558 13:42:15.667262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28559 13:42:15.698884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28561 13:42:15.699400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28562 13:42:15.731024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28563 13:42:15.731501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28565 13:42:15.770213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28566 13:42:15.770681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28568 13:42:15.802572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28570 13:42:15.803040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28571 13:42:15.835653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28573 13:42:15.836213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28574 13:42:15.867528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28575 13:42:15.867939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28577 13:42:15.898890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28579 13:42:15.899335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28580 13:42:15.930730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28582 13:42:15.931174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28583 13:42:15.961796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28584 13:42:15.962255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28586 13:42:15.993123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28587 13:42:15.993566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28589 13:42:16.024915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28591 13:42:16.025348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28592 13:42:16.055860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28593 13:42:16.056268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28595 13:42:16.087102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28597 13:42:16.087537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28598 13:42:16.118802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28599 13:42:16.119225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28601 13:42:16.150128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28602 13:42:16.150586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28604 13:42:16.181273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28605 13:42:16.181680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28607 13:42:16.212007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28608 13:42:16.212428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28610 13:42:16.243484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28611 13:42:16.243885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28613 13:42:16.274620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28614 13:42:16.275069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28616 13:42:16.326042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28617 13:42:16.326523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28619 13:42:16.363730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28621 13:42:16.364170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28622 13:42:16.398162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28624 13:42:16.398773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28625 13:42:16.428858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28626 13:42:16.429332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28628 13:42:16.459789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28630 13:42:16.460407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28631 13:42:16.491337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28632 13:42:16.491810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28634 13:42:16.522115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28636 13:42:16.522717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28637 13:42:16.553251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28639 13:42:16.553833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28640 13:42:16.584152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28642 13:42:16.584754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28643 13:42:16.615104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28644 13:42:16.615555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28646 13:42:16.646637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28648 13:42:16.647182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28649 13:42:16.677666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28651 13:42:16.678193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28652 13:42:16.709427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28653 13:42:16.709907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28655 13:42:16.740483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28657 13:42:16.741041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28658 13:42:16.771311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28660 13:42:16.771821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28661 13:42:16.802841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28662 13:42:16.803310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28664 13:42:16.833719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28666 13:42:16.834255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28667 13:42:16.864874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28669 13:42:16.865412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28670 13:42:16.895693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28671 13:42:16.896139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28673 13:42:16.926829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28674 13:42:16.927228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28676 13:42:16.958165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28678 13:42:16.958738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28679 13:42:16.989498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28681 13:42:16.990058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28682 13:42:17.019984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28683 13:42:17.020409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28685 13:42:17.050258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28687 13:42:17.050764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28688 13:42:17.080881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28690 13:42:17.081407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28691 13:42:17.110921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28692 13:42:17.111325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28694 13:42:17.142362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28695 13:42:17.142781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28697 13:42:17.173154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28699 13:42:17.173703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28700 13:42:17.203481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28701 13:42:17.203892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28703 13:42:17.234128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28705 13:42:17.234635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28706 13:42:17.264863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28708 13:42:17.265375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28709 13:42:17.294797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28710 13:42:17.295234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28712 13:42:17.326234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28714 13:42:17.326748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28715 13:42:17.356400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28717 13:42:17.356980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28718 13:42:17.387089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28719 13:42:17.387523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28721 13:42:17.417962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28722 13:42:17.418382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28724 13:42:17.448889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28726 13:42:17.449293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28727 13:42:17.480194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28729 13:42:17.480709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28730 13:42:17.510762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28731 13:42:17.511168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28733 13:42:17.541483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28735 13:42:17.541894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28736 13:42:17.571840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28737 13:42:17.572221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28739 13:42:17.602524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28740 13:42:17.602974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28742 13:42:17.633020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28744 13:42:17.633591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28745 13:42:17.663141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28747 13:42:17.663718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28748 13:42:17.693713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28750 13:42:17.694233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28751 13:42:17.724057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28753 13:42:17.724553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28754 13:42:17.754744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28756 13:42:17.755251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28757 13:42:17.785432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28758 13:42:17.785859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28760 13:42:17.815797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28761 13:42:17.816211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28763 13:42:17.846400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28764 13:42:17.846779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28766 13:42:17.877597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28767 13:42:17.878030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28769 13:42:17.908874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28770 13:42:17.909297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28772 13:42:17.939388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28773 13:42:17.939804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28775 13:42:17.969930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28776 13:42:17.970308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28778 13:42:18.001291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28779 13:42:18.001726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28781 13:42:18.031911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28782 13:42:18.032369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28784 13:42:18.063013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28785 13:42:18.063445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28787 13:42:18.093634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28789 13:42:18.094236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28790 13:42:18.125334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28791 13:42:18.125682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28793 13:42:18.155835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28795 13:42:18.156243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28796 13:42:18.186501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28798 13:42:18.186903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28799 13:42:18.217159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28800 13:42:18.217553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28802 13:42:18.247781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28803 13:42:18.248152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28805 13:42:18.278217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28806 13:42:18.278594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28808 13:42:18.311473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28810 13:42:18.312001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28811 13:42:18.343581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28813 13:42:18.344095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28814 13:42:18.376034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28816 13:42:18.376555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28817 13:42:18.409321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28819 13:42:18.409826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28820 13:42:18.443226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28821 13:42:18.443623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28823 13:42:18.476948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28824 13:42:18.477325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28826 13:42:18.510122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28827 13:42:18.510537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28829 13:42:18.543792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28830 13:42:18.544289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28832 13:42:18.577508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28833 13:42:18.578017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28835 13:42:18.611840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28837 13:42:18.612392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28838 13:42:18.644962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28840 13:42:18.645472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28841 13:42:18.677664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28842 13:42:18.678079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28844 13:42:18.710917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28845 13:42:18.711299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28847 13:42:18.744394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28849 13:42:18.744864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28850 13:42:18.778508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28851 13:42:18.778945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28853 13:42:18.811931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28854 13:42:18.812389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28856 13:42:18.845570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28857 13:42:18.846018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28859 13:42:18.879243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28861 13:42:18.879802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28862 13:42:18.913549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28863 13:42:18.914064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28865 13:42:18.946491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28867 13:42:18.946960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28868 13:42:18.977485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28870 13:42:18.977893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28871 13:42:19.008509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28873 13:42:19.009045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28874 13:42:19.039593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28875 13:42:19.040017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28877 13:42:19.070251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28879 13:42:19.070816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28880 13:42:19.101190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28881 13:42:19.101572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28883 13:42:19.131973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28885 13:42:19.132535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28886 13:42:19.163149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28888 13:42:19.163682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28889 13:42:19.193603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28891 13:42:19.194131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28892 13:42:19.224102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28893 13:42:19.224553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28895 13:42:19.254883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28896 13:42:19.255302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28898 13:42:19.285698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28899 13:42:19.286159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28901 13:42:19.316769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28902 13:42:19.317201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28904 13:42:19.348448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28906 13:42:19.349009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28907 13:42:19.379371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28909 13:42:19.379900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28910 13:42:19.410186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28911 13:42:19.410622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28913 13:42:19.441434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28915 13:42:19.442009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28916 13:42:19.471847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28917 13:42:19.472275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28919 13:42:19.503297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28921 13:42:19.503803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28922 13:42:19.533675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28924 13:42:19.534171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28925 13:42:19.564213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28927 13:42:19.564750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28928 13:42:19.594540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28930 13:42:19.595079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28931 13:42:19.624985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28932 13:42:19.625396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28934 13:42:19.655170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28935 13:42:19.655585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28937 13:42:19.685845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
28938 13:42:19.686232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
28940 13:42:19.716411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
28942 13:42:19.716827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
28943 13:42:19.746796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
28944 13:42:19.747166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
28946 13:42:19.779559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
28948 13:42:19.780014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
28949 13:42:19.810115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
28950 13:42:19.810500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
28952 13:42:19.841026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
28953 13:42:19.841422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
28955 13:42:19.872135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
28957 13:42:19.872724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
28958 13:42:19.904812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
28959 13:42:19.905283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
28961 13:42:19.936432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
28963 13:42:19.936991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
28964 13:42:19.967119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
28965 13:42:19.967504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
28967 13:42:19.997566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
28968 13:42:19.997971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
28970 13:42:20.028012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
28972 13:42:20.028521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
28973 13:42:20.058713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
28975 13:42:20.059161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
28976 13:42:20.089956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
28978 13:42:20.090582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
28979 13:42:20.120909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
28980 13:42:20.121362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
28982 13:42:20.152050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
28983 13:42:20.152485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
28985 13:42:20.183293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
28986 13:42:20.183709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
28988 13:42:20.214354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
28990 13:42:20.214784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
28991 13:42:20.245775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
28993 13:42:20.246319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
28994 13:42:20.277462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
28995 13:42:20.277937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
28997 13:42:20.308640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
28999 13:42:20.309153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
29000 13:42:20.339855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
29001 13:42:20.340296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
29003 13:42:20.370259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
29004 13:42:20.370740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
29006 13:42:20.401412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
29008 13:42:20.402013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
29009 13:42:20.432288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
29011 13:42:20.432863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
29012 13:42:20.462526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
29013 13:42:20.462906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
29015 13:42:20.494087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
29017 13:42:20.494628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
29018 13:42:20.525695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
29019 13:42:20.526155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
29021 13:42:20.556450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
29023 13:42:20.556947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
29024 13:42:20.587608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
29026 13:42:20.588110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
29027 13:42:20.618452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
29028 13:42:20.618880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
29030 13:42:20.649227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
29032 13:42:20.649811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
29033 13:42:20.679652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
29035 13:42:20.680157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
29036 13:42:20.710106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
29037 13:42:20.710570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
29039 13:42:20.741262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
29041 13:42:20.741791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
29042 13:42:20.774241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
29043 13:42:20.774812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
29045 13:42:20.806977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
29046 13:42:20.807414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
29048 13:42:20.839778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
29050 13:42:20.840216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
29051 13:42:20.875535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
29052 13:42:20.876002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
29054 13:42:20.908310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
29056 13:42:20.908770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
29057 13:42:20.939481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
29058 13:42:20.939889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
29060 13:42:20.970667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
29061 13:42:20.971084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
29063 13:42:21.002076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
29065 13:42:21.002517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
29066 13:42:21.033333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
29067 13:42:21.033755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
29069 13:42:21.065305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
29071 13:42:21.065763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
29072 13:42:21.097082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
29074 13:42:21.097635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
29075 13:42:21.127931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
29076 13:42:21.128376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
29078 13:42:21.159964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
29080 13:42:21.160500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
29081 13:42:21.191251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
29083 13:42:21.191777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
29084 13:42:21.223454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
29085 13:42:21.223924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
29087 13:42:21.254435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
29089 13:42:21.254956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
29090 13:42:21.285501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
29092 13:42:21.286036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
29093 13:42:21.316917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
29094 13:42:21.317340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
29096 13:42:21.348120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
29097 13:42:21.348519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
29099 13:42:21.378788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
29101 13:42:21.379324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
29102 13:42:21.409632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
29103 13:42:21.410055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
29105 13:42:21.464732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
29106 13:42:21.465203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
29108 13:42:21.496531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
29110 13:42:21.497085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
29111 13:42:21.529558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
29113 13:42:21.530142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
29114 13:42:21.560883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
29115 13:42:21.561299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
29117 13:42:21.592012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
29118 13:42:21.592434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
29120 13:42:21.623113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
29122 13:42:21.623538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
29123 13:42:21.654172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
29124 13:42:21.654578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
29126 13:42:21.685532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
29128 13:42:21.685969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
29129 13:42:21.717803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
29130 13:42:21.718232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
29132 13:42:21.749565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
29134 13:42:21.750011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
29135 13:42:21.780995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
29137 13:42:21.781435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
29138 13:42:21.811514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
29139 13:42:21.811927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
29141 13:42:21.842518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
29142 13:42:21.842930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
29144 13:42:21.873791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
29146 13:42:21.874225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
29147 13:42:21.904965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
29148 13:42:21.905418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
29150 13:42:21.936351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
29152 13:42:21.936877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
29153 13:42:21.967283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
29154 13:42:21.967748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
29156 13:42:21.997936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
29157 13:42:21.998398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
29159 13:42:22.028781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
29161 13:42:22.029380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
29162 13:42:22.059485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
29163 13:42:22.059950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
29165 13:42:22.090790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
29166 13:42:22.091339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
29168 13:42:22.125256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
29170 13:42:22.125934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
29171 13:42:22.158309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
29172 13:42:22.158801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
29174 13:42:22.192150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
29175 13:42:22.192702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
29177 13:42:22.225274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
29179 13:42:22.225894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
29180 13:42:22.258216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
29182 13:42:22.258676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
29183 13:42:22.290569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
29184 13:42:22.290958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
29186 13:42:22.322616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
29187 13:42:22.323178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
29189 13:42:22.357216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
29190 13:42:22.357703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
29192 13:42:22.390774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
29193 13:42:22.391238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
29195 13:42:22.424419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
29197 13:42:22.424958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
29198 13:42:22.458462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
29200 13:42:22.458947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
29201 13:42:22.490467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
29202 13:42:22.490950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
29204 13:42:22.523157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
29205 13:42:22.523626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
29207 13:42:22.556882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
29208 13:42:22.557322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
29210 13:42:22.590015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
29211 13:42:22.590572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
29213 13:42:22.623231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
29215 13:42:22.623790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
29216 13:42:22.655454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
29217 13:42:22.655878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
29219 13:42:22.689681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
29220 13:42:22.690118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
29222 13:42:22.721572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
29223 13:42:22.722061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
29225 13:42:22.763395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
29226 13:42:22.763857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
29228 13:42:22.795830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
29229 13:42:22.796242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
29231 13:42:22.827511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
29232 13:42:22.828005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
29234 13:42:22.859311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
29235 13:42:22.859869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
29237 13:42:22.891496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
29238 13:42:22.891927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
29240 13:42:22.924933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
29241 13:42:22.925467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
29243 13:42:22.957727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
29244 13:42:22.958165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
29246 13:42:22.989544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
29247 13:42:22.990106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
29249 13:42:23.020954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
29250 13:42:23.021445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
29252 13:42:23.052436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
29254 13:42:23.053082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
29255 13:42:23.083844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
29256 13:42:23.084322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
29258 13:42:23.116193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
29260 13:42:23.116774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
29261 13:42:23.148157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
29262 13:42:23.148628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
29264 13:42:23.179726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
29266 13:42:23.180283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
29267 13:42:23.211382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
29269 13:42:23.211963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
29270 13:42:23.242779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
29272 13:42:23.243372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
29273 13:42:23.274264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
29274 13:42:23.274752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
29276 13:42:23.305548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
29278 13:42:23.306127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
29279 13:42:23.336999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
29280 13:42:23.337487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
29282 13:42:23.368877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
29283 13:42:23.369439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
29285 13:42:23.399845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
29286 13:42:23.400341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
29288 13:42:23.431422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
29289 13:42:23.431894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
29291 13:42:23.463020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
29292 13:42:23.463491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
29294 13:42:23.494181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
29296 13:42:23.494719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
29297 13:42:23.526758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
29299 13:42:23.527465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
29300 13:42:23.561363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29301 13:42:23.561867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29303 13:42:23.594788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29305 13:42:23.595260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29306 13:42:23.630616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29307 13:42:23.631036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29309 13:42:23.662610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29311 13:42:23.663069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29312 13:42:23.694344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29314 13:42:23.694795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29315 13:42:23.727009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29316 13:42:23.727505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29318 13:42:23.760384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29320 13:42:23.761032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29321 13:42:23.794192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29322 13:42:23.794673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29324 13:42:23.828113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29326 13:42:23.828581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29327 13:42:23.862238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29329 13:42:23.862885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29330 13:42:23.895107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29331 13:42:23.895584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29333 13:42:23.929437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29335 13:42:23.930196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29336 13:42:23.962245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29337 13:42:23.962795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29339 13:42:24.005223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29340 13:42:24.005792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29342 13:42:24.041459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29343 13:42:24.041980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29345 13:42:24.074672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29346 13:42:24.075129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29348 13:42:24.107854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29350 13:42:24.108386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29351 13:42:24.140128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29353 13:42:24.140700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29354 13:42:24.173269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29355 13:42:24.173774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29357 13:42:24.206250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29359 13:42:24.206713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29360 13:42:24.239127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29362 13:42:24.239558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29363 13:42:24.271419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29365 13:42:24.271987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29366 13:42:24.303435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29367 13:42:24.303873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29369 13:42:24.334423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29370 13:42:24.334892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29372 13:42:24.365268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29373 13:42:24.365696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29375 13:42:24.396100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29376 13:42:24.396536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29378 13:42:24.427396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29380 13:42:24.427922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29381 13:42:24.458437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29382 13:42:24.458886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29384 13:42:24.490325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29386 13:42:24.490844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29387 13:42:24.521511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29388 13:42:24.521964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29390 13:42:24.552638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29391 13:42:24.553094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29393 13:42:24.583307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29394 13:42:24.583780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29396 13:42:24.614392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29397 13:42:24.614827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29399 13:42:24.646201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29401 13:42:24.646732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29402 13:42:24.677471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29403 13:42:24.677916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29405 13:42:24.708217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29407 13:42:24.708812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29408 13:42:24.738592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29410 13:42:24.739186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29411 13:42:24.769356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29412 13:42:24.769824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29414 13:42:24.800413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29416 13:42:24.801047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29417 13:42:24.831059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29418 13:42:24.831512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29420 13:42:24.862325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29422 13:42:24.862876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29423 13:42:24.893298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29425 13:42:24.893826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29426 13:42:24.923849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29428 13:42:24.924337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29429 13:42:24.954587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29431 13:42:24.955117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29432 13:42:24.985531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29433 13:42:24.985926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29435 13:42:25.016856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29436 13:42:25.017289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29438 13:42:25.049729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29440 13:42:25.050286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29441 13:42:25.081232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29443 13:42:25.081796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29444 13:42:25.112173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29445 13:42:25.112613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29447 13:42:25.143445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29449 13:42:25.144002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29450 13:42:25.174385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29452 13:42:25.174905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29453 13:42:25.205420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29454 13:42:25.205863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29456 13:42:25.235968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29457 13:42:25.236409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29459 13:42:25.266717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29461 13:42:25.267236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29462 13:42:25.297962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29464 13:42:25.298480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29465 13:42:25.328828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29466 13:42:25.329238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29468 13:42:25.359547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29469 13:42:25.359958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29471 13:42:25.390024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29473 13:42:25.390581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29474 13:42:25.420866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29475 13:42:25.421279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29477 13:42:25.454793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29479 13:42:25.455433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29480 13:42:25.487588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29482 13:42:25.488152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29483 13:42:25.518620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29485 13:42:25.519167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29486 13:42:25.549621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29488 13:42:25.550245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29489 13:42:25.580040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29490 13:42:25.580503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29492 13:42:25.611263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29494 13:42:25.611811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29495 13:42:25.643196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29496 13:42:25.643651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29498 13:42:25.674168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29500 13:42:25.674711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29501 13:42:25.706412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29502 13:42:25.706856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29504 13:42:25.737996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29506 13:42:25.738538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29507 13:42:25.769484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29508 13:42:25.769961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29510 13:42:25.802288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29512 13:42:25.802832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29513 13:42:25.837726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29515 13:42:25.838273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29516 13:42:25.871985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29518 13:42:25.872451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29519 13:42:25.905853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29521 13:42:25.906304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29522 13:42:25.939512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29523 13:42:25.939902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29525 13:42:25.972860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29527 13:42:25.973414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29528 13:42:26.002834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29529 13:42:26.003224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29531 13:42:26.033781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29532 13:42:26.034257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29534 13:42:26.065112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29535 13:42:26.065543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29537 13:42:26.096036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29538 13:42:26.096489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29540 13:42:26.126763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29542 13:42:26.127273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29543 13:42:26.157707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29544 13:42:26.158158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29546 13:42:26.188375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29548 13:42:26.188938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29549 13:42:26.219389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29551 13:42:26.219850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29552 13:42:26.249949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29554 13:42:26.250333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29555 13:42:26.280406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29557 13:42:26.280805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29558 13:42:26.311501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29560 13:42:26.311933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29561 13:42:26.342157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29562 13:42:26.342523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29564 13:42:26.372444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29566 13:42:26.372839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29567 13:42:26.403772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29569 13:42:26.404366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29570 13:42:26.434509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29572 13:42:26.435075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29573 13:42:26.465183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29575 13:42:26.465732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29576 13:42:26.496892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29578 13:42:26.497495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29579 13:42:26.527122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29580 13:42:26.527590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29582 13:42:26.579626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29584 13:42:26.580089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29585 13:42:26.611610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29586 13:42:26.612079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29588 13:42:26.642354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29589 13:42:26.642840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29591 13:42:26.674345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29593 13:42:26.674986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29594 13:42:26.705176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29595 13:42:26.705666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29597 13:42:26.735890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29598 13:42:26.736336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29600 13:42:26.766457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29601 13:42:26.766900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29603 13:42:26.798248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29604 13:42:26.798689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29606 13:42:26.829254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29607 13:42:26.829701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29609 13:42:26.860925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29611 13:42:26.861462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29612 13:42:26.891827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29614 13:42:26.892413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29615 13:42:26.922515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29616 13:42:26.922935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29618 13:42:26.953639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29619 13:42:26.954108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29621 13:42:26.986465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29623 13:42:26.986975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29624 13:42:27.019070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29625 13:42:27.019503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29627 13:42:27.052466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29629 13:42:27.052937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29630 13:42:27.086318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29631 13:42:27.086763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29633 13:42:27.119910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29634 13:42:27.120396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29636 13:42:27.153370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29637 13:42:27.153842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29639 13:42:27.187092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29641 13:42:27.187666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29642 13:42:27.220316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29644 13:42:27.220885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29645 13:42:27.254019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29646 13:42:27.254496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29648 13:42:27.287541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29649 13:42:27.288028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29651 13:42:27.321534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29653 13:42:27.322110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29654 13:42:27.353476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29655 13:42:27.353959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29657 13:42:27.387120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29659 13:42:27.387766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29660 13:42:27.418248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29661 13:42:27.418714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29663 13:42:27.449779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29665 13:42:27.450391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29666 13:42:27.481169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29668 13:42:27.481766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29669 13:42:27.511896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29670 13:42:27.512323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29672 13:42:27.544910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29674 13:42:27.545358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29675 13:42:27.576394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29677 13:42:27.576834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29678 13:42:27.607246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29680 13:42:27.607657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29681 13:42:27.637659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29682 13:42:27.638083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29684 13:42:27.668379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29686 13:42:27.669006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29687 13:42:27.699840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29688 13:42:27.700311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29690 13:42:27.731367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29691 13:42:27.731827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29693 13:42:27.762673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29695 13:42:27.763260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29696 13:42:27.793576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29698 13:42:27.794186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29699 13:42:27.824492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29701 13:42:27.825057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29702 13:42:27.855400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29703 13:42:27.855845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29705 13:42:27.886665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29707 13:42:27.887206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29708 13:42:27.917856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29710 13:42:27.918389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29711 13:42:27.949282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29713 13:42:27.949838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29714 13:42:27.980192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29716 13:42:27.980743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29717 13:42:28.011536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29719 13:42:28.011985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29720 13:42:28.042560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29722 13:42:28.042999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29723 13:42:28.073712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29725 13:42:28.074152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29726 13:42:28.105665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29728 13:42:28.106101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29729 13:42:28.138316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29730 13:42:28.138744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29732 13:42:28.169697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29734 13:42:28.170237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29735 13:42:28.201161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29737 13:42:28.201741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29738 13:42:28.231914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29740 13:42:28.232456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29741 13:42:28.262969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29743 13:42:28.263517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29744 13:42:28.293670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29745 13:42:28.294111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29747 13:42:28.324894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29748 13:42:28.325352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29750 13:42:28.355932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29751 13:42:28.356376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29753 13:42:28.386524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29754 13:42:28.386969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29756 13:42:28.417333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29758 13:42:28.417869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29759 13:42:28.447971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29760 13:42:28.448424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29762 13:42:28.478836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29763 13:42:28.479333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29765 13:42:28.509686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29766 13:42:28.510119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29768 13:42:28.541314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29770 13:42:28.542137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29771 13:42:28.572015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29773 13:42:28.572567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29774 13:42:28.602750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29776 13:42:28.603287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29777 13:42:28.633951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29779 13:42:28.634500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29780 13:42:28.664668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29781 13:42:28.665130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29783 13:42:28.695997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29785 13:42:28.696539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29786 13:42:28.726784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29787 13:42:28.727240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29789 13:42:28.758016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29790 13:42:28.758469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29792 13:42:28.789064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29794 13:42:28.789596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29795 13:42:28.821401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29797 13:42:28.821969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29798 13:42:28.855476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29800 13:42:28.856106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29801 13:42:28.886541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29803 13:42:28.887096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29804 13:42:28.917330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29805 13:42:28.917775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29807 13:42:28.948112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29809 13:42:28.948649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29810 13:42:28.978932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29812 13:42:28.979549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29813 13:42:29.009586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29814 13:42:29.010067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29816 13:42:29.040266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29817 13:42:29.040727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29819 13:42:29.071371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29821 13:42:29.071923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29822 13:42:29.102922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29823 13:42:29.103395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29825 13:42:29.133863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29826 13:42:29.134314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29828 13:42:29.164662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29829 13:42:29.165119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29831 13:42:29.195257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29833 13:42:29.195784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29834 13:42:29.226516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29836 13:42:29.227085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29837 13:42:29.257457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29839 13:42:29.258007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29840 13:42:29.288119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29841 13:42:29.288540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29843 13:42:29.318900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29845 13:42:29.319394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29846 13:42:29.350400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29848 13:42:29.350891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29849 13:42:29.381291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29850 13:42:29.381687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29852 13:42:29.412601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29854 13:42:29.413109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29855 13:42:29.443064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29857 13:42:29.443578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29858 13:42:29.473526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29860 13:42:29.474031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29861 13:42:29.503981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29862 13:42:29.504341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29864 13:42:29.537092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29866 13:42:29.537556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29867 13:42:29.567548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29868 13:42:29.567940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29870 13:42:29.598228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29872 13:42:29.598802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29873 13:42:29.629187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29875 13:42:29.629759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29876 13:42:29.659521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29878 13:42:29.660046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29879 13:42:29.690940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29880 13:42:29.691356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29882 13:42:29.722404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29883 13:42:29.722823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29885 13:42:29.753698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29886 13:42:29.754168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29888 13:42:29.786717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29890 13:42:29.787271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29891 13:42:29.821125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29892 13:42:29.821602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29894 13:42:29.852729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29895 13:42:29.853195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29897 13:42:29.883751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29899 13:42:29.884252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29900 13:42:29.914408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29902 13:42:29.914911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29903 13:42:29.944993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29904 13:42:29.945440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29906 13:42:29.975486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29908 13:42:29.976021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29909 13:42:30.006156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29910 13:42:30.006602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29912 13:42:30.037425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29914 13:42:30.037971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29915 13:42:30.068385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29917 13:42:30.068959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29918 13:42:30.099717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29919 13:42:30.100109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29921 13:42:30.130500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29922 13:42:30.130885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29924 13:42:30.161494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29925 13:42:30.161937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29927 13:42:30.192540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29929 13:42:30.193035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29930 13:42:30.223101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29932 13:42:30.223571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29933 13:42:30.253744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29934 13:42:30.254123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29936 13:42:30.284643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
29938 13:42:30.285131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29939 13:42:30.315375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
29941 13:42:30.315884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
29942 13:42:30.346779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
29943 13:42:30.347228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
29945 13:42:30.378322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
29947 13:42:30.378870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
29948 13:42:30.409257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
29949 13:42:30.409703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
29951 13:42:30.440831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
29952 13:42:30.441264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
29954 13:42:30.473424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
29955 13:42:30.473931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
29957 13:42:30.504914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
29959 13:42:30.505350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
29960 13:42:30.536764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
29961 13:42:30.537226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
29963 13:42:30.568624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
29965 13:42:30.569166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
29966 13:42:30.599635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
29968 13:42:30.600066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
29969 13:42:30.630776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
29971 13:42:30.631254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
29972 13:42:30.661542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
29974 13:42:30.662109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
29975 13:42:30.692462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
29977 13:42:30.693014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
29978 13:42:30.723399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
29980 13:42:30.723943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
29981 13:42:30.754106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
29982 13:42:30.754503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
29984 13:42:30.785122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
29986 13:42:30.785670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
29987 13:42:30.817430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
29988 13:42:30.818003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
29990 13:42:30.850051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
29991 13:42:30.850521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
29993 13:42:30.884760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
29994 13:42:30.885332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
29996 13:42:30.918610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
29998 13:42:30.919201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
29999 13:42:30.952122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
30001 13:42:30.952635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
30002 13:42:30.985562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
30003 13:42:30.986023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
30005 13:42:31.016724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
30006 13:42:31.017171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
30008 13:42:31.047314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
30009 13:42:31.047729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
30011 13:42:31.077476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
30012 13:42:31.077954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
30014 13:42:31.109490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
30016 13:42:31.110030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
30017 13:42:31.140934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
30019 13:42:31.141470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
30020 13:42:31.171589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
30022 13:42:31.172127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
30023 13:42:31.202358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
30025 13:42:31.202797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
30026 13:42:31.233883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
30028 13:42:31.234332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
30029 13:42:31.266238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
30030 13:42:31.266670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
30032 13:42:31.297440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
30033 13:42:31.297856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
30035 13:42:31.329269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
30037 13:42:31.329715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
30038 13:42:31.361397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
30039 13:42:31.361850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
30041 13:42:31.392524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
30043 13:42:31.393183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
30044 13:42:31.423149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
30046 13:42:31.423758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
30047 13:42:31.453588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
30048 13:42:31.454008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
30050 13:42:31.484211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
30051 13:42:31.484672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
30053 13:42:31.515427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
30054 13:42:31.515892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
30056 13:42:31.547023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
30058 13:42:31.547577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
30059 13:42:31.578023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
30060 13:42:31.578463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
30062 13:42:31.609270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
30063 13:42:31.609682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
30065 13:42:31.640224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
30066 13:42:31.640633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
30068 13:42:31.699307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
30069 13:42:31.699778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
30071 13:42:31.730758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
30073 13:42:31.731308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
30074 13:42:31.761554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
30076 13:42:31.762155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
30077 13:42:31.792161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
30078 13:42:31.792593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
30080 13:42:31.822505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
30082 13:42:31.822909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
30083 13:42:31.853726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
30085 13:42:31.854294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
30086 13:42:31.884575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
30088 13:42:31.885123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
30089 13:42:31.915350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
30090 13:42:31.915799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
30092 13:42:31.945492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
30093 13:42:31.945965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
30095 13:42:31.976136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
30097 13:42:31.976670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
30098 13:42:32.007384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
30100 13:42:32.007929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
30101 13:42:32.037697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
30102 13:42:32.038166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
30104 13:42:32.068017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
30105 13:42:32.068451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
30107 13:42:32.098865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
30108 13:42:32.099287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
30110 13:42:32.130353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
30112 13:42:32.130923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
30113 13:42:32.161435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
30114 13:42:32.161878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
30116 13:42:32.191965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
30117 13:42:32.192390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
30119 13:42:32.222224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
30120 13:42:32.222696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
30122 13:42:32.252968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
30123 13:42:32.253432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
30125 13:42:32.283906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
30127 13:42:32.284450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
30128 13:42:32.314589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
30130 13:42:32.315111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
30131 13:42:32.346584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
30132 13:42:32.347068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
30134 13:42:32.382171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
30136 13:42:32.382730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
30137 13:42:32.412929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
30139 13:42:32.413460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
30140 13:42:32.443062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
30141 13:42:32.443442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
30143 13:42:32.473567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
30144 13:42:32.473966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
30146 13:42:32.503909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
30147 13:42:32.504274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
30149 13:42:32.534722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
30150 13:42:32.535138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
30152 13:42:32.566437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
30154 13:42:32.567050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
30155 13:42:32.597291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
30157 13:42:32.597831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
30158 13:42:32.627707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
30160 13:42:32.628257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
30161 13:42:32.658034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
30162 13:42:32.658472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
30164 13:42:32.688923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
30166 13:42:32.689464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
30167 13:42:32.721302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
30169 13:42:32.721879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
30170 13:42:32.752244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
30172 13:42:32.752798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
30173 13:42:32.782666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
30174 13:42:32.783114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
30176 13:42:32.813482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
30177 13:42:32.813963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
30179 13:42:32.845006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
30180 13:42:32.845448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
30182 13:42:32.876912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
30183 13:42:32.877352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
30185 13:42:32.907240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
30187 13:42:32.907651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
30188 13:42:32.937693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
30190 13:42:32.938291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
30191 13:42:32.967665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
30192 13:42:32.968095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
30194 13:42:32.998676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
30195 13:42:32.999126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
30197 13:42:33.030108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
30199 13:42:33.030659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
30200 13:42:33.061583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
30201 13:42:33.062042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
30203 13:42:33.092446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
30205 13:42:33.093069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
30206 13:42:33.123950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
30208 13:42:33.124573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
30209 13:42:33.154742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
30210 13:42:33.155202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
30212 13:42:33.185555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
30213 13:42:33.186037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
30215 13:42:33.216486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
30217 13:42:33.216957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
30218 13:42:33.246671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
30219 13:42:33.247061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
30221 13:42:33.277595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
30222 13:42:33.278043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
30224 13:42:33.308548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
30226 13:42:33.309084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
30227 13:42:33.339383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
30228 13:42:33.339798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
30230 13:42:33.370646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
30231 13:42:33.371060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
30233 13:42:33.401548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
30234 13:42:33.402022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
30236 13:42:33.431928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
30237 13:42:33.432330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
30239 13:42:33.462625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
30241 13:42:33.463106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
30242 13:42:33.493401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
30243 13:42:33.493827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
30245 13:42:33.524579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
30247 13:42:33.525095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
30248 13:42:33.555948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
30249 13:42:33.556347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
30251 13:42:33.586580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
30253 13:42:33.587075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
30254 13:42:33.617687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
30256 13:42:33.618195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
30257 13:42:33.648176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
30258 13:42:33.648572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
30260 13:42:33.679011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
30262 13:42:33.679507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
30263 13:42:33.710489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
30264 13:42:33.710912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
30266 13:42:33.742050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
30268 13:42:33.742683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
30269 13:42:33.773395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
30270 13:42:33.773866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
30272 13:42:33.804398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
30274 13:42:33.804968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
30275 13:42:33.835441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
30276 13:42:33.835845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
30278 13:42:33.866809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
30280 13:42:33.867247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
30281 13:42:33.897861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
30283 13:42:33.898305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
30284 13:42:33.928636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
30286 13:42:33.929063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
30287 13:42:33.959303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
30288 13:42:33.959710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
30290 13:42:33.990358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
30291 13:42:33.990770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
30293 13:42:34.022525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
30295 13:42:34.022968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
30296 13:42:34.053662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
30297 13:42:34.054055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
30299 13:42:34.085238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30301 13:42:34.085689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
30302 13:42:34.116831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30303 13:42:34.117251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30305 13:42:34.148035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30306 13:42:34.148499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30308 13:42:34.179429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30309 13:42:34.179888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30311 13:42:34.211341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30313 13:42:34.211927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30314 13:42:34.243469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30315 13:42:34.243921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30317 13:42:34.276439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30319 13:42:34.277029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30320 13:42:34.307050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30321 13:42:34.307484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30323 13:42:34.337689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30324 13:42:34.338078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30326 13:42:34.369058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30327 13:42:34.369467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30329 13:42:34.399716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30330 13:42:34.400073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30332 13:42:34.430603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30333 13:42:34.430976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30335 13:42:34.461270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30337 13:42:34.461794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30338 13:42:34.491926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30339 13:42:34.492407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30341 13:42:34.522884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30343 13:42:34.523436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30344 13:42:34.554412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30346 13:42:34.554951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30347 13:42:34.585436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30348 13:42:34.585915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30350 13:42:34.617094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30351 13:42:34.617534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30353 13:42:34.647557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30355 13:42:34.648091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30356 13:42:34.678078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30357 13:42:34.678535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30359 13:42:34.709987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30360 13:42:34.710428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30362 13:42:34.740861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30364 13:42:34.741467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30365 13:42:34.771677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30367 13:42:34.772232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30368 13:42:34.802610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30370 13:42:34.803166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30371 13:42:34.833511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30373 13:42:34.834084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30374 13:42:34.864339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30376 13:42:34.864912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30377 13:42:34.895042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30378 13:42:34.895458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30380 13:42:34.925875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30381 13:42:34.926342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30383 13:42:34.957026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30384 13:42:34.957470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30386 13:42:34.987957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30387 13:42:34.988443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30389 13:42:35.018773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30390 13:42:35.019230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30392 13:42:35.050105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30394 13:42:35.050692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30395 13:42:35.081305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30397 13:42:35.081937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30398 13:42:35.113056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30400 13:42:35.113691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30401 13:42:35.120921 <47>[ 298.264897] systemd-journald[105]: Sent WATCHDOG=1 notification.
30402 13:42:35.148977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30403 13:42:35.149450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30405 13:42:35.179787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30407 13:42:35.180399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30408 13:42:35.210861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30410 13:42:35.211470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30411 13:42:35.242341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30413 13:42:35.242908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30414 13:42:35.273472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30416 13:42:35.274020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30417 13:42:35.304832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30419 13:42:35.305425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30420 13:42:35.336601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30422 13:42:35.336986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30423 13:42:35.370345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30425 13:42:35.370737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30426 13:42:35.401563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30428 13:42:35.401979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30429 13:42:35.433468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30430 13:42:35.433873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30432 13:42:35.466181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30434 13:42:35.466748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30435 13:42:35.498160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30436 13:42:35.498578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30438 13:42:35.529969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30439 13:42:35.530421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30441 13:42:35.562391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30442 13:42:35.562838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30444 13:42:35.593357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30445 13:42:35.593819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30447 13:42:35.624786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30448 13:42:35.625233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30450 13:42:35.656893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30451 13:42:35.657338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30453 13:42:35.687712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30455 13:42:35.688315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30456 13:42:35.719311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30457 13:42:35.719775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30459 13:42:35.750131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30461 13:42:35.750656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30462 13:42:35.781328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30463 13:42:35.781751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30465 13:42:35.812751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30467 13:42:35.813248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30468 13:42:35.845320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30469 13:42:35.845764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30471 13:42:35.876414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30473 13:42:35.876960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30474 13:42:35.907883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30475 13:42:35.908320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30477 13:42:35.939699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30479 13:42:35.940163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30480 13:42:35.971119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30482 13:42:35.971583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30483 13:42:36.002803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30484 13:42:36.003238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30486 13:42:36.035237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30488 13:42:36.035674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30489 13:42:36.066185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30491 13:42:36.066715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30492 13:42:36.096934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30494 13:42:36.097538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30495 13:42:36.128068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30497 13:42:36.128612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30498 13:42:36.158669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30500 13:42:36.159186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30501 13:42:36.189787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30502 13:42:36.190200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30504 13:42:36.220878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30506 13:42:36.221411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30507 13:42:36.251207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30509 13:42:36.251742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30510 13:42:36.282130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30512 13:42:36.282639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30513 13:42:36.312727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30514 13:42:36.313174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30516 13:42:36.343176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30517 13:42:36.343571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30519 13:42:36.374494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30520 13:42:36.374949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30522 13:42:36.405714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30524 13:42:36.406256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30525 13:42:36.436852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30526 13:42:36.437326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30528 13:42:36.468134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30529 13:42:36.468553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30531 13:42:36.498864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30532 13:42:36.499237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30534 13:42:36.529912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30535 13:42:36.530311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30537 13:42:36.561423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30538 13:42:36.561786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30540 13:42:36.592553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30542 13:42:36.592942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30543 13:42:36.623245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30544 13:42:36.623633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30546 13:42:36.653575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30547 13:42:36.653947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30549 13:42:36.684945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30551 13:42:36.685339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30552 13:42:36.715603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30553 13:42:36.716055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30555 13:42:36.747023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30556 13:42:36.747452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30558 13:42:36.794506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30560 13:42:36.795069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30561 13:42:36.833755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30562 13:42:36.834220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30564 13:42:36.864995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30566 13:42:36.865550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30567 13:42:36.895887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30568 13:42:36.896337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30570 13:42:36.926487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30571 13:42:36.926959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30573 13:42:36.957682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30574 13:42:36.958171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30576 13:42:36.989626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30578 13:42:36.990094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30579 13:42:37.022030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30580 13:42:37.022471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30582 13:42:37.053631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30583 13:42:37.054025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30585 13:42:37.085260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30586 13:42:37.085618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30588 13:42:37.115937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30590 13:42:37.116478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30591 13:42:37.147163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30592 13:42:37.147598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30594 13:42:37.177858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30595 13:42:37.178241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30597 13:42:37.208563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30599 13:42:37.209017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30600 13:42:37.238930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30601 13:42:37.239381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30603 13:42:37.269525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30604 13:42:37.269925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30606 13:42:37.300563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30608 13:42:37.300976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30609 13:42:37.331765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30610 13:42:37.332139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30612 13:42:37.362522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30613 13:42:37.362971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30615 13:42:37.394366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30617 13:42:37.394924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30618 13:42:37.425486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30620 13:42:37.425943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30621 13:42:37.457172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30623 13:42:37.457737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30624 13:42:37.488403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30626 13:42:37.488992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30627 13:42:37.518783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30628 13:42:37.519232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30630 13:42:37.549494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30631 13:42:37.549951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30633 13:42:37.581440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30635 13:42:37.581993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30636 13:42:37.612275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30637 13:42:37.612713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30639 13:42:37.643357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30641 13:42:37.643886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30642 13:42:37.674187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30643 13:42:37.674657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30645 13:42:37.705770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30646 13:42:37.706239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30648 13:42:37.737803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30650 13:42:37.738242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30651 13:42:37.769532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30653 13:42:37.769988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30654 13:42:37.801921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30655 13:42:37.802330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30657 13:42:37.833511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30659 13:42:37.834147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30660 13:42:37.864136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30661 13:42:37.864610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30663 13:42:37.897190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30664 13:42:37.897687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30666 13:42:37.929299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30667 13:42:37.929780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30669 13:42:37.960010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30670 13:42:37.960497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30672 13:42:37.991351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30673 13:42:37.991837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30675 13:42:38.023131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30676 13:42:38.023622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30678 13:42:38.053422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30679 13:42:38.053854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30681 13:42:38.084617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30683 13:42:38.085141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30684 13:42:38.115886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30685 13:42:38.116306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30687 13:42:38.147310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30689 13:42:38.147894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30690 13:42:38.178622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30692 13:42:38.179162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30693 13:42:38.209344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30694 13:42:38.209769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30696 13:42:38.240128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30698 13:42:38.240664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30699 13:42:38.271068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30700 13:42:38.271531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30702 13:42:38.301886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30703 13:42:38.302326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30705 13:42:38.332873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30707 13:42:38.333398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30708 13:42:38.363517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30710 13:42:38.364120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30711 13:42:38.395003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30713 13:42:38.395617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30714 13:42:38.426358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30716 13:42:38.426900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30717 13:42:38.457268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30718 13:42:38.457685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30720 13:42:38.489029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30721 13:42:38.489456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30723 13:42:38.520119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30724 13:42:38.520521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30726 13:42:38.550909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30727 13:42:38.551310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30729 13:42:38.582974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30730 13:42:38.583377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30732 13:42:38.614139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30733 13:42:38.614543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30735 13:42:38.645417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30736 13:42:38.645807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30738 13:42:38.677064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30739 13:42:38.677465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30741 13:42:38.708791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30742 13:42:38.709215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30744 13:42:38.743775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30745 13:42:38.744207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30747 13:42:38.776127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30748 13:42:38.776564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30750 13:42:38.807918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30751 13:42:38.808334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30753 13:42:38.846395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30755 13:42:38.846856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30756 13:42:38.878140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30757 13:42:38.878533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30759 13:42:38.909654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30761 13:42:38.910075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30762 13:42:38.941568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30763 13:42:38.942050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30765 13:42:38.973354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30766 13:42:38.973809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30768 13:42:39.004604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30770 13:42:39.005197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30771 13:42:39.035921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30772 13:42:39.036345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30774 13:42:39.067429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30775 13:42:39.067838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30777 13:42:39.098294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30778 13:42:39.098696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30780 13:42:39.129551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30782 13:42:39.129982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30783 13:42:39.161595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30785 13:42:39.162032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30786 13:42:39.192416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30788 13:42:39.192856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30789 13:42:39.223387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30790 13:42:39.223784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30792 13:42:39.254524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30793 13:42:39.254910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30795 13:42:39.285675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30797 13:42:39.286108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30798 13:42:39.317903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30799 13:42:39.318329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30801 13:42:39.350517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30802 13:42:39.350942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30804 13:42:39.383560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30805 13:42:39.383997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30807 13:42:39.417498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30808 13:42:39.417935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30810 13:42:39.451244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30812 13:42:39.451707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30813 13:42:39.484381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30815 13:42:39.485017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30816 13:42:39.517626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30817 13:42:39.518115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30819 13:42:39.550466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30821 13:42:39.551077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30822 13:42:39.584667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30824 13:42:39.585287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30825 13:42:39.619147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30826 13:42:39.619613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30828 13:42:39.653414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30829 13:42:39.653868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30831 13:42:39.687451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30832 13:42:39.687930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30834 13:42:39.721897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30836 13:42:39.722494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30837 13:42:39.756185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30839 13:42:39.756651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30840 13:42:39.791397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30842 13:42:39.791849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30843 13:42:39.825942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30845 13:42:39.826410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30846 13:42:39.859789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30848 13:42:39.860216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30849 13:42:39.899728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30850 13:42:39.900119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30852 13:42:39.934635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30854 13:42:39.935084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30855 13:42:39.971063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30856 13:42:39.971502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30858 13:42:40.004596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30860 13:42:40.005108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30861 13:42:40.037974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30862 13:42:40.038407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30864 13:42:40.069502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30866 13:42:40.070031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30867 13:42:40.100136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30869 13:42:40.100656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30870 13:42:40.130740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30871 13:42:40.131159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30873 13:42:40.161560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30875 13:42:40.162012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30876 13:42:40.193413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30878 13:42:40.193855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30879 13:42:40.225486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30880 13:42:40.225897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30882 13:42:40.257161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30883 13:42:40.257627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30885 13:42:40.288375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30887 13:42:40.288913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30888 13:42:40.318894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30890 13:42:40.319403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30891 13:42:40.349563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30892 13:42:40.349958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30894 13:42:40.379950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30896 13:42:40.380356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30897 13:42:40.410400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30898 13:42:40.410840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30900 13:42:40.441427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30901 13:42:40.441848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30903 13:42:40.472981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30904 13:42:40.473425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30906 13:42:40.504194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30908 13:42:40.504746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30909 13:42:40.535008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30911 13:42:40.535490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30912 13:42:40.565723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30914 13:42:40.566246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30915 13:42:40.597295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30917 13:42:40.597876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30918 13:42:40.628239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30919 13:42:40.628692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30921 13:42:40.660798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30922 13:42:40.661244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30924 13:42:40.693458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30925 13:42:40.693941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30927 13:42:40.725673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30928 13:42:40.726126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30930 13:42:40.756912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30932 13:42:40.757352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30933 13:42:40.788467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30935 13:42:40.789206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30936 13:42:40.822113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30938 13:42:40.822551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30939 13:42:40.855240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
30940 13:42:40.855675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
30942 13:42:40.887495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
30943 13:42:40.887965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
30945 13:42:40.920246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
30947 13:42:40.920784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
30948 13:42:40.953504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
30950 13:42:40.954015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
30951 13:42:40.986549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
30952 13:42:40.987027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
30954 13:42:41.018462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
30956 13:42:41.019008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
30957 13:42:41.049716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
30958 13:42:41.050170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
30960 13:42:41.081179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
30961 13:42:41.081620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
30963 13:42:41.112877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
30965 13:42:41.113381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
30966 13:42:41.143229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
30967 13:42:41.143659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
30969 13:42:41.174209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
30971 13:42:41.174793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
30972 13:42:41.205617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
30974 13:42:41.206165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
30975 13:42:41.237391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
30976 13:42:41.237881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
30978 13:42:41.268686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
30980 13:42:41.269248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
30981 13:42:41.299566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
30982 13:42:41.300031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
30984 13:42:41.330260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
30986 13:42:41.330780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
30987 13:42:41.361010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
30988 13:42:41.361456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
30990 13:42:41.392628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
30992 13:42:41.393161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
30993 13:42:41.422980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
30994 13:42:41.423436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
30996 13:42:41.453921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
30998 13:42:41.454465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
30999 13:42:41.485614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
31000 13:42:41.486030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
31002 13:42:41.517349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
31004 13:42:41.517798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
31005 13:42:41.549183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
31007 13:42:41.549631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
31008 13:42:41.580229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
31010 13:42:41.580786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
31011 13:42:41.611096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
31012 13:42:41.611536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
31014 13:42:41.641875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
31016 13:42:41.642312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
31017 13:42:41.673638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
31019 13:42:41.674193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
31020 13:42:41.704363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
31022 13:42:41.705036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
31023 13:42:41.734946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
31025 13:42:41.735372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
31026 13:42:41.765572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
31027 13:42:41.765943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
31029 13:42:41.796175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
31031 13:42:41.796573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
31032 13:42:41.826996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
31034 13:42:41.827617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
31035 13:42:41.857917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
31036 13:42:41.858355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
31038 13:42:41.888686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
31039 13:42:41.889109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
31041 13:42:41.942698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
31043 13:42:41.943335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
31044 13:42:41.973676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
31045 13:42:41.974103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
31047 13:42:42.004364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
31049 13:42:42.004992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
31050 13:42:42.035251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
31051 13:42:42.035701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
31053 13:42:42.067681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
31055 13:42:42.068217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
31056 13:42:42.100154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
31058 13:42:42.100688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
31059 13:42:42.133218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
31061 13:42:42.133801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
31062 13:42:42.166188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
31064 13:42:42.166708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
31065 13:42:42.199258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
31067 13:42:42.199773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
31068 13:42:42.231846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
31069 13:42:42.232296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
31071 13:42:42.266327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
31072 13:42:42.266777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
31074 13:42:42.299902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
31076 13:42:42.300456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
31077 13:42:42.333501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
31079 13:42:42.333936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
31080 13:42:42.366509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
31082 13:42:42.367037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
31083 13:42:42.399511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
31084 13:42:42.399998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
31086 13:42:42.433699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
31088 13:42:42.434146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
31089 13:42:42.468622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
31091 13:42:42.469174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
31092 13:42:42.502281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
31093 13:42:42.502763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
31095 13:42:42.537446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
31097 13:42:42.538009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
31098 13:42:42.571208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
31100 13:42:42.571671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
31101 13:42:42.605268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
31103 13:42:42.605748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
31104 13:42:42.638882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
31106 13:42:42.639345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
31107 13:42:42.672926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
31109 13:42:42.673384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
31110 13:42:42.706422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
31111 13:42:42.706858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
31113 13:42:42.740943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
31114 13:42:42.741376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
31116 13:42:42.774927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
31117 13:42:42.775369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
31119 13:42:42.809380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
31121 13:42:42.809842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
31122 13:42:42.842810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
31123 13:42:42.843246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
31125 13:42:42.877366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
31126 13:42:42.877807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
31128 13:42:42.913250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
31129 13:42:42.913692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
31131 13:42:42.947875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
31133 13:42:42.948339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
31134 13:42:42.982430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
31135 13:42:42.982851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
31137 13:42:43.015809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
31138 13:42:43.016246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
31140 13:42:43.049246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
31141 13:42:43.049692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
31143 13:42:43.082151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
31144 13:42:43.082585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
31146 13:42:43.116151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
31147 13:42:43.116640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
31149 13:42:43.149635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
31150 13:42:43.150131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
31152 13:42:43.183168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
31153 13:42:43.183627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
31155 13:42:43.216086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
31156 13:42:43.216511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
31158 13:42:43.249436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
31159 13:42:43.249866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
31161 13:42:43.282543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
31163 13:42:43.283016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
31164 13:42:43.315786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
31166 13:42:43.316247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
31167 13:42:43.349816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
31168 13:42:43.350232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
31170 13:42:43.382976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
31171 13:42:43.383412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
31173 13:42:43.416647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
31174 13:42:43.417087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
31176 13:42:43.450100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
31178 13:42:43.450560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
31179 13:42:43.484014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
31181 13:42:43.484674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
31182 13:42:43.517380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
31184 13:42:43.517950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
31185 13:42:43.550505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
31186 13:42:43.550988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
31188 13:42:43.584877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
31190 13:42:43.585458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
31191 13:42:43.618811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
31192 13:42:43.619242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
31194 13:42:43.651877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
31196 13:42:43.652405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
31197 13:42:43.685150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
31198 13:42:43.685595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
31200 13:42:43.718520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
31202 13:42:43.719117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
31203 13:42:43.751787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
31204 13:42:43.752159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
31206 13:42:43.785412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
31208 13:42:43.785855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
31209 13:42:43.819221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
31211 13:42:43.819740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
31212 13:42:43.851606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
31213 13:42:43.852046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
31215 13:42:43.885183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
31217 13:42:43.885739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
31218 13:42:43.918796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
31219 13:42:43.919245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
31221 13:42:43.952550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
31223 13:42:43.953306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
31224 13:42:43.986867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
31225 13:42:43.987290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
31227 13:42:44.020422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
31229 13:42:44.020880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
31230 13:42:44.054333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
31232 13:42:44.054752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
31233 13:42:44.088039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
31234 13:42:44.088420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
31236 13:42:44.121909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
31237 13:42:44.122335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
31239 13:42:44.156634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
31241 13:42:44.157085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
31242 13:42:44.190568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
31244 13:42:44.190982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
31245 13:42:44.225047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
31246 13:42:44.225499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
31248 13:42:44.259024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
31249 13:42:44.259447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
31251 13:42:44.292863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
31252 13:42:44.293272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
31254 13:42:44.326541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
31255 13:42:44.326978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
31257 13:42:44.360761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
31258 13:42:44.361178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
31260 13:42:44.394685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
31261 13:42:44.395162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
31263 13:42:44.429568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
31264 13:42:44.430040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
31266 13:42:44.463737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
31268 13:42:44.464199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
31269 13:42:44.498100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
31271 13:42:44.498659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
31272 13:42:44.531841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
31274 13:42:44.532395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
31275 13:42:44.565348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
31276 13:42:44.565772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
31278 13:42:44.599313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
31280 13:42:44.599830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
31281 13:42:44.633068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
31282 13:42:44.633506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
31284 13:42:44.667058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
31285 13:42:44.667525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
31287 13:42:44.701780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
31288 13:42:44.702255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
31290 13:42:44.735692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
31291 13:42:44.736127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
31293 13:42:44.769962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
31295 13:42:44.770523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
31296 13:42:44.803644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
31298 13:42:44.804072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
31299 13:42:44.837278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31300 13:42:44.837681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
31302 13:42:44.870834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31304 13:42:44.871296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31305 13:42:44.904195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31306 13:42:44.904631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31308 13:42:44.935472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31310 13:42:44.936006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31311 13:42:44.966773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31312 13:42:44.967192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31314 13:42:44.998763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31315 13:42:44.999148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31317 13:42:45.030378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31319 13:42:45.030788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31320 13:42:45.062228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31322 13:42:45.062666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31323 13:42:45.094036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31325 13:42:45.094604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31326 13:42:45.125700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31328 13:42:45.126231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31329 13:42:45.157848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31330 13:42:45.158317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31332 13:42:45.189561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31334 13:42:45.190107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31335 13:42:45.221102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31336 13:42:45.221535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31338 13:42:45.252926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31340 13:42:45.253468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31341 13:42:45.284160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31343 13:42:45.284694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31344 13:42:45.315090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31346 13:42:45.315635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31347 13:42:45.346024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31349 13:42:45.346631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31350 13:42:45.377202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31351 13:42:45.377674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31353 13:42:45.408203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31355 13:42:45.408815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31356 13:42:45.440374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31357 13:42:45.440907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31359 13:42:45.474385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31361 13:42:45.475038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31362 13:42:45.505702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31363 13:42:45.506119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31365 13:42:45.536824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31367 13:42:45.537286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31368 13:42:45.567741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31370 13:42:45.568293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31371 13:42:45.598794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31373 13:42:45.599344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31374 13:42:45.629903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31375 13:42:45.630354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31377 13:42:45.661008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31379 13:42:45.661606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31380 13:42:45.691870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31382 13:42:45.692395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31383 13:42:45.723974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31384 13:42:45.724408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31386 13:42:45.756221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31387 13:42:45.756665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31389 13:42:45.787071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31391 13:42:45.787598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31392 13:42:45.817490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31393 13:42:45.817874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31395 13:42:45.848450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31397 13:42:45.849028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31398 13:42:45.880926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31399 13:42:45.881395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31401 13:42:45.912481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31403 13:42:45.913043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31404 13:42:45.944537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31406 13:42:45.945122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31407 13:42:45.975764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31409 13:42:45.976319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31410 13:42:46.007245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31411 13:42:46.007734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31413 13:42:46.039616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31414 13:42:46.040102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31416 13:42:46.073328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31417 13:42:46.073794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31419 13:42:46.106079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31421 13:42:46.106445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31422 13:42:46.137296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31423 13:42:46.137662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31425 13:42:46.168619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31426 13:42:46.169091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31428 13:42:46.199844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31430 13:42:46.200429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31431 13:42:46.231128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31432 13:42:46.231592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31434 13:42:46.262007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31435 13:42:46.262480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31437 13:42:46.293465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31439 13:42:46.293918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31440 13:42:46.325001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31442 13:42:46.325431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31443 13:42:46.355956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31445 13:42:46.356402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31446 13:42:46.387123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31447 13:42:46.387523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31449 13:42:46.418248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31450 13:42:46.418660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31452 13:42:46.449438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31454 13:42:46.450095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31455 13:42:46.481521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31457 13:42:46.482093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31458 13:42:46.513679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31460 13:42:46.514235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31461 13:42:46.545937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31463 13:42:46.546484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31464 13:42:46.577573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31465 13:42:46.578043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31467 13:42:46.611453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31469 13:42:46.612010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31470 13:42:46.643736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31471 13:42:46.644210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31473 13:42:46.675189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31475 13:42:46.675723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31476 13:42:46.706339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31477 13:42:46.706808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31479 13:42:46.738169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31481 13:42:46.738686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31482 13:42:46.769526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31483 13:42:46.770000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31485 13:42:46.801245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31486 13:42:46.801691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31488 13:42:46.832126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31490 13:42:46.832718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31491 13:42:46.862923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31492 13:42:46.863353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31494 13:42:46.894448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31495 13:42:46.894884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31497 13:42:46.927608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31498 13:42:46.928100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31500 13:42:46.960259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31502 13:42:46.960729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31503 13:42:46.993802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31504 13:42:46.994236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31506 13:42:47.049492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31507 13:42:47.049974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31509 13:42:47.083233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31510 13:42:47.083660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31512 13:42:47.116989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31514 13:42:47.117602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31515 13:42:47.150006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31516 13:42:47.150447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31518 13:42:47.183750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31520 13:42:47.184309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31521 13:42:47.217308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31523 13:42:47.217873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31524 13:42:47.250565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31525 13:42:47.250961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31527 13:42:47.281954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31529 13:42:47.282362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31530 13:42:47.312969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31531 13:42:47.313452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31533 13:42:47.345169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31534 13:42:47.345644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31536 13:42:47.376177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31538 13:42:47.376738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31539 13:42:47.406880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31540 13:42:47.407293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31542 13:42:47.437666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31544 13:42:47.438273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31545 13:42:47.468211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31547 13:42:47.468785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31548 13:42:47.499170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31550 13:42:47.499760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31551 13:42:47.530286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31552 13:42:47.530724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31554 13:42:47.560934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31555 13:42:47.561366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31557 13:42:47.591826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31558 13:42:47.592252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31560 13:42:47.622578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31562 13:42:47.623097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31563 13:42:47.654362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31565 13:42:47.654814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31566 13:42:47.688198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31568 13:42:47.688837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31569 13:42:47.721172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31571 13:42:47.721626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31572 13:42:47.754492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31573 13:42:47.754920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31575 13:42:47.788941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31577 13:42:47.789569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31578 13:42:47.821947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31580 13:42:47.822721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31581 13:42:47.856753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31582 13:42:47.857237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31584 13:42:47.889881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31585 13:42:47.890306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31587 13:42:47.923009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31589 13:42:47.923519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31590 13:42:47.955925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31592 13:42:47.956459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31593 13:42:47.989606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31595 13:42:47.990130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31596 13:42:48.020666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31597 13:42:48.021101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31599 13:42:48.051282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31600 13:42:48.051725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31602 13:42:48.082086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31603 13:42:48.082511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31605 13:42:48.113136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31607 13:42:48.113697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31608 13:42:48.144142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31610 13:42:48.144605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31611 13:42:48.175458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31612 13:42:48.175882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31614 13:42:48.206860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31616 13:42:48.207416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31617 13:42:48.237840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31618 13:42:48.238300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31620 13:42:48.269318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31622 13:42:48.269791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31623 13:42:48.300078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31624 13:42:48.300508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31626 13:42:48.330957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31627 13:42:48.331328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31629 13:42:48.361913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31631 13:42:48.362366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31632 13:42:48.392484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31634 13:42:48.393100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31635 13:42:48.423447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31637 13:42:48.423997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31638 13:42:48.454753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31639 13:42:48.455201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31641 13:42:48.485757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31642 13:42:48.486253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31644 13:42:48.516894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31646 13:42:48.517492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31647 13:42:48.548307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31649 13:42:48.549031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31650 13:42:48.578787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31651 13:42:48.579262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31653 13:42:48.609789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31654 13:42:48.610268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31656 13:42:48.641195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31658 13:42:48.641795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31659 13:42:48.672290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31661 13:42:48.672847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31662 13:42:48.703661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31663 13:42:48.704125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31665 13:42:48.735069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31667 13:42:48.735620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31668 13:42:48.766308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31669 13:42:48.766714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31671 13:42:48.798588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31673 13:42:48.799029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31674 13:42:48.831292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31675 13:42:48.831726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31677 13:42:48.863849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31679 13:42:48.864299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31680 13:42:48.895178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31682 13:42:48.895615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31683 13:42:48.926595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31685 13:42:48.927141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31686 13:42:48.957611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31687 13:42:48.958049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31689 13:42:48.989292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31690 13:42:48.989696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31692 13:42:49.020833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31693 13:42:49.021282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31695 13:42:49.051554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31697 13:42:49.051981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31698 13:42:49.082339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31699 13:42:49.082748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31701 13:42:49.114375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31702 13:42:49.114845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31704 13:42:49.146335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31705 13:42:49.146788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31707 13:42:49.178092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31709 13:42:49.178840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31710 13:42:49.211164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31711 13:42:49.211639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31713 13:42:49.242169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31714 13:42:49.242652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31716 13:42:49.273287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31718 13:42:49.273843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31719 13:42:49.304011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31721 13:42:49.304573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31722 13:42:49.334663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31724 13:42:49.335157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31725 13:42:49.365569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31726 13:42:49.365953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31728 13:42:49.396579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31730 13:42:49.397057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31731 13:42:49.427577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31733 13:42:49.428101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31734 13:42:49.458067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31736 13:42:49.458579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31737 13:42:49.488862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31738 13:42:49.489265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31740 13:42:49.519184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31741 13:42:49.519617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31743 13:42:49.552125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31744 13:42:49.552609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31746 13:42:49.583165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31747 13:42:49.583633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31749 13:42:49.614064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31751 13:42:49.614604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31752 13:42:49.644935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31754 13:42:49.645455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31755 13:42:49.675710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31756 13:42:49.676162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31758 13:42:49.706729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31759 13:42:49.707174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31761 13:42:49.738059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31763 13:42:49.738600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31764 13:42:49.769255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31766 13:42:49.769743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31767 13:42:49.800941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31769 13:42:49.801487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31770 13:42:49.832578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31772 13:42:49.833149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31773 13:42:49.864901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31775 13:42:49.865336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31776 13:42:49.896159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31778 13:42:49.896602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31779 13:42:49.927052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31780 13:42:49.927461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31782 13:42:49.958097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31783 13:42:49.958494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31785 13:42:49.989466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31786 13:42:49.989902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31788 13:42:50.021709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31790 13:42:50.022142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31791 13:42:50.053498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31793 13:42:50.053941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31794 13:42:50.084609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31796 13:42:50.085036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31797 13:42:50.115831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31799 13:42:50.116270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31800 13:42:50.147575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31802 13:42:50.148008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31803 13:42:50.178670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31804 13:42:50.179080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31806 13:42:50.210340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31807 13:42:50.210768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31809 13:42:50.241696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31811 13:42:50.242304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31812 13:42:50.272843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31813 13:42:50.273322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31815 13:42:50.304125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31817 13:42:50.304736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31818 13:42:50.334553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31820 13:42:50.335066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31821 13:42:50.365373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31823 13:42:50.365915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31824 13:42:50.395909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31826 13:42:50.396369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31827 13:42:50.427054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31828 13:42:50.427445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31830 13:42:50.459155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31831 13:42:50.459590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31833 13:42:50.493069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31834 13:42:50.493479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31836 13:42:50.524352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31838 13:42:50.524803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31839 13:42:50.557344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31841 13:42:50.557951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31842 13:42:50.588034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31843 13:42:50.588477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31845 13:42:50.618776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31847 13:42:50.619327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31848 13:42:50.649176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31849 13:42:50.649642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31851 13:42:50.679733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31852 13:42:50.680208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31854 13:42:50.713542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31855 13:42:50.714024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31857 13:42:50.744980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31858 13:42:50.745413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31860 13:42:50.777968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31861 13:42:50.778441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31863 13:42:50.811624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31864 13:42:50.812092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31866 13:42:50.842943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31867 13:42:50.843357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31869 13:42:50.875058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31870 13:42:50.875517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31872 13:42:50.917697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31874 13:42:50.918251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31875 13:42:50.957557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31877 13:42:50.958024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31878 13:42:50.991862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31879 13:42:50.992408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31881 13:42:51.032246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31882 13:42:51.032640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31884 13:42:51.071430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31885 13:42:51.071799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31887 13:42:51.106051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31889 13:42:51.106585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31890 13:42:51.139488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31892 13:42:51.140027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31893 13:42:51.172446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31895 13:42:51.173003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31896 13:42:51.206303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31898 13:42:51.206925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31899 13:42:51.239224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31900 13:42:51.239674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31902 13:42:51.272111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31903 13:42:51.272592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31905 13:42:51.307148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31906 13:42:51.307625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31908 13:42:51.340778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31909 13:42:51.341251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31911 13:42:51.373917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31913 13:42:51.374464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31914 13:42:51.407194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31916 13:42:51.407747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31917 13:42:51.440572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31919 13:42:51.441110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31920 13:42:51.473491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31921 13:42:51.474001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31923 13:42:51.507637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31925 13:42:51.508107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31926 13:42:51.541292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31927 13:42:51.541700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31929 13:42:51.574221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31930 13:42:51.574658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31932 13:42:51.607660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31933 13:42:51.608099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31935 13:42:51.642322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31937 13:42:51.642966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31938 13:42:51.673697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
31940 13:42:51.674212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
31941 13:42:51.706529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
31943 13:42:51.707145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
31944 13:42:51.738153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
31946 13:42:51.738759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
31947 13:42:51.768980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
31949 13:42:51.769388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
31950 13:42:51.799898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
31951 13:42:51.800350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
31953 13:42:51.831423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
31954 13:42:51.831795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
31956 13:42:51.862124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
31957 13:42:51.862536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
31959 13:42:51.893836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
31961 13:42:51.894361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
31962 13:42:51.925578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
31963 13:42:51.926023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
31965 13:42:51.955960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
31966 13:42:51.956408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
31968 13:42:51.987051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
31969 13:42:51.987414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
31971 13:42:52.018678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
31972 13:42:52.019075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
31974 13:42:52.050390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
31976 13:42:52.050893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
31977 13:42:52.082119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
31978 13:42:52.082536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
31980 13:42:52.113642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
31981 13:42:52.114101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
31983 13:42:52.170201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
31984 13:42:52.170652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
31986 13:42:52.201247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
31987 13:42:52.201633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
31989 13:42:52.233621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
31990 13:42:52.234091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
31992 13:42:52.266017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
31994 13:42:52.266460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
31995 13:42:52.298140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
31997 13:42:52.298703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
31998 13:42:52.330128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
32000 13:42:52.330759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
32001 13:42:52.361443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
32002 13:42:52.361812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
32004 13:42:52.392081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
32005 13:42:52.392403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
32007 13:42:52.423616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
32008 13:42:52.423968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
32010 13:42:52.454437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
32012 13:42:52.454953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
32013 13:42:52.488029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
32015 13:42:52.488621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
32016 13:42:52.519984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
32017 13:42:52.520410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
32019 13:42:52.550684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
32021 13:42:52.551204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
32022 13:42:52.581946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
32024 13:42:52.582490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
32025 13:42:52.613049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
32027 13:42:52.613562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
32028 13:42:52.643792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
32029 13:42:52.644224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
32031 13:42:52.675926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
32033 13:42:52.676382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
32034 13:42:52.707235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
32035 13:42:52.707632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
32037 13:42:52.738377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
32039 13:42:52.738829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
32040 13:42:52.769895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
32041 13:42:52.770295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
32043 13:42:52.801339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
32044 13:42:52.801746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
32046 13:42:52.832833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
32048 13:42:52.833270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
32049 13:42:52.863596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
32050 13:42:52.864001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
32052 13:42:52.895095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
32053 13:42:52.895491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
32055 13:42:52.926489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
32056 13:42:52.926908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
32058 13:42:52.957700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
32059 13:42:52.958109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
32061 13:42:52.989347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
32063 13:42:52.989776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
32064 13:42:53.020333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
32066 13:42:53.020772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
32067 13:42:53.051737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
32068 13:42:53.052138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
32070 13:42:53.082987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
32071 13:42:53.083414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
32073 13:42:53.115084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
32075 13:42:53.115520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
32076 13:42:53.145978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
32078 13:42:53.146562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
32079 13:42:53.177232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
32081 13:42:53.177807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
32082 13:42:53.208667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
32083 13:42:53.209126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
32085 13:42:53.239786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
32087 13:42:53.240325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
32088 13:42:53.271690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
32090 13:42:53.272344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
32091 13:42:53.302879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
32093 13:42:53.303516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
32094 13:42:53.334399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
32095 13:42:53.334886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
32097 13:42:53.365996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
32099 13:42:53.366620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
32100 13:42:53.397271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
32101 13:42:53.397710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
32103 13:42:53.428779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
32104 13:42:53.429252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
32106 13:42:53.459653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
32107 13:42:53.460107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
32109 13:42:53.490085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
32110 13:42:53.490530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
32112 13:42:53.521166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
32113 13:42:53.521634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
32115 13:42:53.553071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
32116 13:42:53.553517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
32118 13:42:53.583817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
32119 13:42:53.584271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
32121 13:42:53.614853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
32123 13:42:53.615392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
32124 13:42:53.645875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
32125 13:42:53.646319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
32127 13:42:53.679947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
32128 13:42:53.680429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
32130 13:42:53.713171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
32131 13:42:53.713640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
32133 13:42:53.746295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
32134 13:42:53.746763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
32136 13:42:53.779807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
32138 13:42:53.780370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
32139 13:42:53.813713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
32140 13:42:53.814140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
32142 13:42:53.848077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
32144 13:42:53.848543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
32145 13:42:53.881442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
32146 13:42:53.881879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
32148 13:42:53.915255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
32150 13:42:53.915810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
32151 13:42:53.950067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
32152 13:42:53.950528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
32154 13:42:53.983290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
32155 13:42:53.983780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
32157 13:42:54.017462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
32158 13:42:54.017965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
32160 13:42:54.051449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
32162 13:42:54.051892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
32163 13:42:54.084823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
32164 13:42:54.085276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
32166 13:42:54.118474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
32167 13:42:54.118951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
32169 13:42:54.153533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
32170 13:42:54.153940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
32172 13:42:54.186981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
32174 13:42:54.187534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
32175 13:42:54.221226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
32177 13:42:54.221683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
32178 13:42:54.256813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
32179 13:42:54.257299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
32181 13:42:54.290406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
32182 13:42:54.290845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
32184 13:42:54.326433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
32186 13:42:54.327008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
32187 13:42:54.360514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
32189 13:42:54.360972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
32190 13:42:54.394587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
32191 13:42:54.395023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
32193 13:42:54.432106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
32195 13:42:54.432674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
32196 13:42:54.467973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
32197 13:42:54.468438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
32199 13:42:54.504025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
32200 13:42:54.504470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
32202 13:42:54.539932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
32203 13:42:54.540378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
32205 13:42:54.576597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
32207 13:42:54.577072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
32208 13:42:54.613208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
32210 13:42:54.613680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
32211 13:42:54.650432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
32213 13:42:54.651090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
32214 13:42:54.685947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
32216 13:42:54.686591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
32217 13:42:54.720328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
32219 13:42:54.720898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
32220 13:42:54.769795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
32221 13:42:54.770242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
32223 13:42:54.803913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
32225 13:42:54.804586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
32226 13:42:54.839384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
32227 13:42:54.839851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
32229 13:42:54.877570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
32231 13:42:54.878023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
32232 13:42:54.910955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
32233 13:42:54.911323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
32235 13:42:54.943775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
32236 13:42:54.944172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
32238 13:42:54.976849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
32239 13:42:54.977233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
32241 13:42:55.010298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
32243 13:42:55.010716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
32244 13:42:55.043788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
32246 13:42:55.044348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
32247 13:42:55.077894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
32249 13:42:55.078359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
32250 13:42:55.111947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
32252 13:42:55.112414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
32253 13:42:55.145661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
32255 13:42:55.146222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
32256 13:42:55.178556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
32257 13:42:55.179020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
32259 13:42:55.211994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
32260 13:42:55.212404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
32262 13:42:55.245560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
32264 13:42:55.246107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
32265 13:42:55.279343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
32267 13:42:55.279876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
32268 13:42:55.312807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
32270 13:42:55.313339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
32271 13:42:55.345886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
32273 13:42:55.346420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
32274 13:42:55.378974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
32276 13:42:55.379447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
32277 13:42:55.414501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
32278 13:42:55.414957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
32280 13:42:55.449187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
32281 13:42:55.449590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
32283 13:42:55.481890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
32284 13:42:55.482260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
32286 13:42:55.515690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
32287 13:42:55.516087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
32289 13:42:55.548671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
32290 13:42:55.549065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
32292 13:42:55.582198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
32293 13:42:55.582582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
32295 13:42:55.615128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
32296 13:42:55.615458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
32298 13:42:55.648139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
32299 13:42:55.648539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
32301 13:42:55.682149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32302 13:42:55.682630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32304 13:42:55.715590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32305 13:42:55.716024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32307 13:42:55.749409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32309 13:42:55.750055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32310 13:42:55.782114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32311 13:42:55.782583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32313 13:42:55.815701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32314 13:42:55.816157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32316 13:42:55.849030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32318 13:42:55.849481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32319 13:42:55.882809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32320 13:42:55.883243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32322 13:42:55.918572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32324 13:42:55.919031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32325 13:42:55.956186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32327 13:42:55.956647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32328 13:42:55.996203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32329 13:42:55.996602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32331 13:42:56.036444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32333 13:42:56.037008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32334 13:42:56.071858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32335 13:42:56.072319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32337 13:42:56.105912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32339 13:42:56.106425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32340 13:42:56.139680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32341 13:42:56.140121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32343 13:42:56.173017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32344 13:42:56.173464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32346 13:42:56.205926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32347 13:42:56.206362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32349 13:42:56.238940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32350 13:42:56.239323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32352 13:42:56.271781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32353 13:42:56.272253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32355 13:42:56.305255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32357 13:42:56.305691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32358 13:42:56.338924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32360 13:42:56.339458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32361 13:42:56.372448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32363 13:42:56.372990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32364 13:42:56.405956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32366 13:42:56.406503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32367 13:42:56.439439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32368 13:42:56.439866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32370 13:42:56.472024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32371 13:42:56.472464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32373 13:42:56.505675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32374 13:42:56.506101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32376 13:42:56.539034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32377 13:42:56.539453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32379 13:42:56.570711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32380 13:42:56.571142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32382 13:42:56.603145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32383 13:42:56.603574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32385 13:42:56.634992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32387 13:42:56.635432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32388 13:42:56.666059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32389 13:42:56.666561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32391 13:42:56.698515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32392 13:42:56.698944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32394 13:42:56.730263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32395 13:42:56.730686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32397 13:42:56.761972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32398 13:42:56.762400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32400 13:42:56.794917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32402 13:42:56.795375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32403 13:42:56.826077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32404 13:42:56.826489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32406 13:42:56.857355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32407 13:42:56.857773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32409 13:42:56.889958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32411 13:42:56.890403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32412 13:42:56.921500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32413 13:42:56.921908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32415 13:42:56.952881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32417 13:42:56.953315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32418 13:42:56.984109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32420 13:42:56.984705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32421 13:42:57.015379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32422 13:42:57.015849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32424 13:42:57.046460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32426 13:42:57.046986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32427 13:42:57.077425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32429 13:42:57.077948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32430 13:42:57.108737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32432 13:42:57.109247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32433 13:42:57.139568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32435 13:42:57.140114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32436 13:42:57.170941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32437 13:42:57.171364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32439 13:42:57.201869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32440 13:42:57.202289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32442 13:42:57.233307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32444 13:42:57.233891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32445 13:42:57.277841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32446 13:42:57.278288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32448 13:42:57.316527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32450 13:42:57.317056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32451 13:42:57.347215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32453 13:42:57.347726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32454 13:42:57.378068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32456 13:42:57.378582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32457 13:42:57.409979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32459 13:42:57.410573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32460 13:42:57.440947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32461 13:42:57.441396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32463 13:42:57.473105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32464 13:42:57.473525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32466 13:42:57.504723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32468 13:42:57.505382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32469 13:42:57.536462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32471 13:42:57.537009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32472 13:42:57.569135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32473 13:42:57.569592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32475 13:42:57.600955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32476 13:42:57.601401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32478 13:42:57.633010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32479 13:42:57.633462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32481 13:42:57.664472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32483 13:42:57.664907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32484 13:42:57.695563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32485 13:42:57.696028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32487 13:42:57.726864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32488 13:42:57.727273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32490 13:42:57.757933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32491 13:42:57.758335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32493 13:42:57.789723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32494 13:42:57.790182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32496 13:42:57.821787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32497 13:42:57.822207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32499 13:42:57.853479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32500 13:42:57.854026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32502 13:42:57.885728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32503 13:42:57.886201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32505 13:42:57.917729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32506 13:42:57.918186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32508 13:42:57.949946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32510 13:42:57.950517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32511 13:42:57.981572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32512 13:42:57.982043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32514 13:42:58.014218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32515 13:42:58.014692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32517 13:42:58.046237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32518 13:42:58.046726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32520 13:42:58.078171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32521 13:42:58.078620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32523 13:42:58.109540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32524 13:42:58.110016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32526 13:42:58.141969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32527 13:42:58.142419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32529 13:42:58.174471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32530 13:42:58.174873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32532 13:42:58.206818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32533 13:42:58.207228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32535 13:42:58.239314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32536 13:42:58.239727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32538 13:42:58.271285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32539 13:42:58.271691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32541 13:42:58.304040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32542 13:42:58.304503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32544 13:42:58.338959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32545 13:42:58.339441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32547 13:42:58.372102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32548 13:42:58.372514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32550 13:42:58.404531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32552 13:42:58.404977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32553 13:42:58.437351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32554 13:42:58.437805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32556 13:42:58.469659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32557 13:42:58.470133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32559 13:42:58.503068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32560 13:42:58.503544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32562 13:42:58.537694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32564 13:42:58.538453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32565 13:42:58.570415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32566 13:42:58.570894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32568 13:42:58.603762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32570 13:42:58.604257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32571 13:42:58.637951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32572 13:42:58.638369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32574 13:42:58.672366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32576 13:42:58.672830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32577 13:42:58.707325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32578 13:42:58.707792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32580 13:42:58.741807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32581 13:42:58.742240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32583 13:42:58.777471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32584 13:42:58.777933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32586 13:42:58.814141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32587 13:42:58.814591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32589 13:42:58.847957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32590 13:42:58.848404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32592 13:42:58.881767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32593 13:42:58.882234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32595 13:42:58.914098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32596 13:42:58.914490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32598 13:42:58.946118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32599 13:42:58.946492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32601 13:42:58.977953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32602 13:42:58.978362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32604 13:42:59.010314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32605 13:42:59.010778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32607 13:42:59.042450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32608 13:42:59.042875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32610 13:42:59.074634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32611 13:42:59.075109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32613 13:42:59.108145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32614 13:42:59.108612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32616 13:42:59.140139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32617 13:42:59.140582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32619 13:42:59.171995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32620 13:42:59.172447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32622 13:42:59.204605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32624 13:42:59.205245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32625 13:42:59.236651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32627 13:42:59.237238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32628 13:42:59.268545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32630 13:42:59.269168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32631 13:42:59.300579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32633 13:42:59.301208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32634 13:42:59.332426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32636 13:42:59.333047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32637 13:42:59.365200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32638 13:42:59.365720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32640 13:42:59.397539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32641 13:42:59.398024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32643 13:42:59.429535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32645 13:42:59.430072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32646 13:42:59.460984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32647 13:42:59.461387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32649 13:42:59.491878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32650 13:42:59.492313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32652 13:42:59.523488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32654 13:42:59.524013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32655 13:42:59.554643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32657 13:42:59.555201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32658 13:42:59.586201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32659 13:42:59.586613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32661 13:42:59.617567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32662 13:42:59.617998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32664 13:42:59.649180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32665 13:42:59.649634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32667 13:42:59.680235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32668 13:42:59.680680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32670 13:42:59.711281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32671 13:42:59.711745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32673 13:42:59.743420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32674 13:42:59.743879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32676 13:42:59.774860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32678 13:42:59.775415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32679 13:42:59.806712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32680 13:42:59.807181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32682 13:42:59.838675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32683 13:42:59.839083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32685 13:42:59.870354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32686 13:42:59.870798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32688 13:42:59.902343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32689 13:42:59.902832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32691 13:42:59.934827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32692 13:42:59.935288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32694 13:42:59.966254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32695 13:42:59.966704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32697 13:42:59.997417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32698 13:42:59.997863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32700 13:43:00.029503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32701 13:43:00.029993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32703 13:43:00.061242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32704 13:43:00.061696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32706 13:43:00.093596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32707 13:43:00.094052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32709 13:43:00.125771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32711 13:43:00.126320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32712 13:43:00.157720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32714 13:43:00.158262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32715 13:43:00.189494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32716 13:43:00.189950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32718 13:43:00.221450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32719 13:43:00.221909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32721 13:43:00.253635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32722 13:43:00.254062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32724 13:43:00.285356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32725 13:43:00.285680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32727 13:43:00.316884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32728 13:43:00.317240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32730 13:43:00.348010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32731 13:43:00.348381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32733 13:43:00.379495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32734 13:43:00.379850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32736 13:43:00.410601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32737 13:43:00.410954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32739 13:43:00.442242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32740 13:43:00.442631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32742 13:43:00.473582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32743 13:43:00.474047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32745 13:43:00.505454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32746 13:43:00.505855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32748 13:43:00.537422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32749 13:43:00.537889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32751 13:43:00.569235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32752 13:43:00.569663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32754 13:43:00.601399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32755 13:43:00.601832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32757 13:43:00.633058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32758 13:43:00.633474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32760 13:43:00.664483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32762 13:43:00.665069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32763 13:43:00.695630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32764 13:43:00.696032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32766 13:43:00.727310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32767 13:43:00.727757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32769 13:43:00.760551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32771 13:43:00.761128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32772 13:43:00.793642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32773 13:43:00.794118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32775 13:43:00.825599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32776 13:43:00.825968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32778 13:43:00.859021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32779 13:43:00.859425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32781 13:43:00.891156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32782 13:43:00.891560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32784 13:43:00.924652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32786 13:43:00.925232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32787 13:43:00.962666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32788 13:43:00.963106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32790 13:43:00.997800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32791 13:43:00.998195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32793 13:43:01.032675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32795 13:43:01.033332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32796 13:43:01.065517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32797 13:43:01.066007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32799 13:43:01.097302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32800 13:43:01.097685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32802 13:43:01.130475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32803 13:43:01.130903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32805 13:43:01.162333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32806 13:43:01.162707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32808 13:43:01.194134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32809 13:43:01.194491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32811 13:43:01.226173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32812 13:43:01.226532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32814 13:43:01.258034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32815 13:43:01.258499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32817 13:43:01.290206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32818 13:43:01.290683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32820 13:43:01.322512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32821 13:43:01.322982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32823 13:43:01.354263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32824 13:43:01.354677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32826 13:43:01.386424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32827 13:43:01.386854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32829 13:43:01.418599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32830 13:43:01.419015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32832 13:43:01.450528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32833 13:43:01.450994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32835 13:43:01.482222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32836 13:43:01.482672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32838 13:43:01.514086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32839 13:43:01.514533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32841 13:43:01.546202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32842 13:43:01.546660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32844 13:43:01.579830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32845 13:43:01.580293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32847 13:43:01.612229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32848 13:43:01.612689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32850 13:43:01.645549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32851 13:43:01.646029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32853 13:43:01.677810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32854 13:43:01.678286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32856 13:43:01.710164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32857 13:43:01.710638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32859 13:43:01.742716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32860 13:43:01.743174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32862 13:43:01.774804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32863 13:43:01.775247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32865 13:43:01.807643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32866 13:43:01.808107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32868 13:43:01.839737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32869 13:43:01.840179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32871 13:43:01.871595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32872 13:43:01.871986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32874 13:43:01.903200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32876 13:43:01.903769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32877 13:43:01.935228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32879 13:43:01.935793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32880 13:43:01.966040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32881 13:43:01.966489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32883 13:43:01.997349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32885 13:43:01.997813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32886 13:43:02.029404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32888 13:43:02.029973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32889 13:43:02.060651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32890 13:43:02.061104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32892 13:43:02.091798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32893 13:43:02.092276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32895 13:43:02.124123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32897 13:43:02.124661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32898 13:43:02.156840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32900 13:43:02.157383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32901 13:43:02.188170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32903 13:43:02.188718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32904 13:43:02.220228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32905 13:43:02.220637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32907 13:43:02.251973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32908 13:43:02.252422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32910 13:43:02.283509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32912 13:43:02.284051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32913 13:43:02.315540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32914 13:43:02.315940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32916 13:43:02.347293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32917 13:43:02.347700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32919 13:43:02.393792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32921 13:43:02.394363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32922 13:43:02.436406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32924 13:43:02.436958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32925 13:43:02.469886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32926 13:43:02.470365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32928 13:43:02.501163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32929 13:43:02.501625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32931 13:43:02.532753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32932 13:43:02.533225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32934 13:43:02.563687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32936 13:43:02.564264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32937 13:43:02.594676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32938 13:43:02.595122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
32940 13:43:02.626367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
32941 13:43:02.626841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
32943 13:43:02.657589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
32944 13:43:02.658042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
32946 13:43:02.689576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
32947 13:43:02.690035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
32949 13:43:02.721015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
32950 13:43:02.721437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
32952 13:43:02.751669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
32953 13:43:02.752162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
32955 13:43:02.782762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
32957 13:43:02.783296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
32958 13:43:02.813716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
32959 13:43:02.814159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
32961 13:43:02.845557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32962 13:43:02.846023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
32964 13:43:02.877177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32965 13:43:02.877631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
32967 13:43:02.908074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
32968 13:43:02.908510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
32970 13:43:02.940060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
32972 13:43:02.940686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
32973 13:43:02.970709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
32974 13:43:02.971068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
32976 13:43:03.001473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
32977 13:43:03.001908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
32979 13:43:03.032194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
32981 13:43:03.032774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
32982 13:43:03.063237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
32984 13:43:03.063733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
32985 13:43:03.093745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
32986 13:43:03.094149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
32988 13:43:03.124437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
32990 13:43:03.124986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
32991 13:43:03.156054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
32992 13:43:03.156414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
32994 13:43:03.187832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
32996 13:43:03.188245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
32997 13:43:03.218487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
32998 13:43:03.218908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
33000 13:43:03.249368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
33002 13:43:03.249960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
33003 13:43:03.279922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
33004 13:43:03.280367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
33006 13:43:03.310759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
33007 13:43:03.311159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
33009 13:43:03.342083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
33010 13:43:03.342633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
33012 13:43:03.375491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
33014 13:43:03.376069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
33015 13:43:03.406461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
33017 13:43:03.407084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
33018 13:43:03.437481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
33019 13:43:03.437969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
33021 13:43:03.470229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
33023 13:43:03.470853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
33024 13:43:03.501612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
33025 13:43:03.502092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
33027 13:43:03.535309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
33029 13:43:03.535934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
33030 13:43:03.567402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
33031 13:43:03.567877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
33033 13:43:03.598826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
33034 13:43:03.599242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
33036 13:43:03.630349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
33037 13:43:03.630757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
33039 13:43:03.662096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
33041 13:43:03.662589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
33042 13:43:03.694401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
33043 13:43:03.694880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
33045 13:43:03.726379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
33047 13:43:03.726966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
33048 13:43:03.758127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
33050 13:43:03.758749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
33051 13:43:03.789983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
33052 13:43:03.790544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
33054 13:43:03.823964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
33056 13:43:03.824541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
33057 13:43:03.856117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
33058 13:43:03.856607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
33060 13:43:03.887695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
33061 13:43:03.888188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
33063 13:43:03.918556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
33064 13:43:03.919035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
33066 13:43:03.949535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
33067 13:43:03.950011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
33069 13:43:03.981212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
33070 13:43:03.981694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
33072 13:43:04.012692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
33074 13:43:04.013235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
33075 13:43:04.044049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
33077 13:43:04.044595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
33078 13:43:04.075407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
33079 13:43:04.075875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
33081 13:43:04.106880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
33082 13:43:04.107351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
33084 13:43:04.138639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
33085 13:43:04.139064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
33087 13:43:04.170402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
33089 13:43:04.171032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
33090 13:43:04.202027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
33091 13:43:04.202499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
33093 13:43:04.233246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
33094 13:43:04.233700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
33096 13:43:04.264263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
33098 13:43:04.264816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
33099 13:43:04.296848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33100 13:43:04.297330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33102 13:43:04.328764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
33104 13:43:04.329328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33105 13:43:04.360622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33107 13:43:04.361252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33108 13:43:04.394511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33110 13:43:04.394957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33111 13:43:04.426520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33112 13:43:04.426929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
33114 13:43:04.457978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33115 13:43:04.458406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33117 13:43:04.490570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33119 13:43:04.491168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33120 13:43:04.525466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33121 13:43:04.525942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
33123 13:43:04.557721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33125 13:43:04.558297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33126 13:43:04.590321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33127 13:43:04.590792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33129 13:43:04.635900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33130 13:43:04.636282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
33132 13:43:04.678737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33133 13:43:04.679152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33135 13:43:04.713565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33136 13:43:04.714047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33138 13:43:04.747577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33139 13:43:04.748045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
33141 13:43:04.780050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33143 13:43:04.780507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33144 13:43:04.812820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
33145 13:43:04.813284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
33147 13:43:04.845880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33148 13:43:04.846299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33150 13:43:04.879256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33151 13:43:04.879734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
33153 13:43:04.914228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33154 13:43:04.914703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33156 13:43:04.947419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33158 13:43:04.948039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33159 13:43:04.981625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
33161 13:43:04.982189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33162 13:43:05.015949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33164 13:43:05.016431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33165 13:43:05.048209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33167 13:43:05.048821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33168 13:43:05.079470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33169 13:43:05.079879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
33171 13:43:05.110575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33173 13:43:05.111138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33174 13:43:05.141817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33175 13:43:05.142225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33177 13:43:05.173233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33178 13:43:05.173701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
33180 13:43:05.204452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33182 13:43:05.205026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33183 13:43:05.239446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33184 13:43:05.239935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33186 13:43:05.271532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33187 13:43:05.271990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
33189 13:43:05.302501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33190 13:43:05.302935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33192 13:43:05.333671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
33193 13:43:05.334154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
33195 13:43:05.364659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33197 13:43:05.365230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33198 13:43:05.395584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33199 13:43:05.396044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
33201 13:43:05.427296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33202 13:43:05.427707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33204 13:43:05.460312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33205 13:43:05.460791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33207 13:43:05.493498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
33209 13:43:05.494062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33210 13:43:05.526140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33211 13:43:05.526604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33213 13:43:05.561514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33214 13:43:05.561992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33216 13:43:05.593017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
33218 13:43:05.593522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33219 13:43:05.623724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33220 13:43:05.624151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33222 13:43:05.654679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33223 13:43:05.655094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33225 13:43:05.686072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33226 13:43:05.686501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
33228 13:43:05.717516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33229 13:43:05.717981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33231 13:43:05.749026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33232 13:43:05.749498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33234 13:43:05.782157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
33236 13:43:05.782744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33237 13:43:05.815977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33239 13:43:05.816621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33240 13:43:05.847189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
33241 13:43:05.847666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
33243 13:43:05.878324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33244 13:43:05.878785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33246 13:43:05.909480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33247 13:43:05.909953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
33249 13:43:05.944283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33251 13:43:05.944845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33252 13:43:05.981602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33253 13:43:05.982073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33255 13:43:06.016487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
33257 13:43:06.016866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33258 13:43:06.050287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33259 13:43:06.050694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33261 13:43:06.083909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33262 13:43:06.084371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33264 13:43:06.117289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33265 13:43:06.117696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
33267 13:43:06.150331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33269 13:43:06.150896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33270 13:43:06.182098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33271 13:43:06.182526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33273 13:43:06.213592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33274 13:43:06.214044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
33276 13:43:06.245296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33278 13:43:06.245853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33279 13:43:06.277334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33281 13:43:06.277875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33282 13:43:06.309838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33283 13:43:06.310258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
33285 13:43:06.341502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33286 13:43:06.341991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33288 13:43:06.373668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
33289 13:43:06.374121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
33291 13:43:06.405601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33292 13:43:06.406071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33294 13:43:06.437314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33295 13:43:06.437681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
33297 13:43:06.469660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33298 13:43:06.470070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33300 13:43:06.501896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33301 13:43:06.502345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33303 13:43:06.533567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33304 13:43:06.534032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33306 13:43:06.565519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33307 13:43:06.565984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33309 13:43:06.599594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33311 13:43:06.600207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33312 13:43:06.632218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33314 13:43:06.632777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33315 13:43:06.664809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33316 13:43:06.665278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33318 13:43:06.696821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33319 13:43:06.697230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33321 13:43:06.727251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33322 13:43:06.727665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33324 13:43:06.758950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33325 13:43:06.759346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33327 13:43:06.790234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33329 13:43:06.790766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33330 13:43:06.821956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33332 13:43:06.822423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33333 13:43:06.852879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33335 13:43:06.853347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33336 13:43:06.884066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33338 13:43:06.884601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33339 13:43:06.914864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33340 13:43:06.915261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33342 13:43:06.946471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33343 13:43:06.946892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33345 13:43:06.978109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33347 13:43:06.978659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33348 13:43:07.009434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33350 13:43:07.009951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33351 13:43:07.040750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33353 13:43:07.041298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33354 13:43:07.072706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33355 13:43:07.073174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33357 13:43:07.105535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33359 13:43:07.106108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33360 13:43:07.138789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33362 13:43:07.139386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33363 13:43:07.173569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33365 13:43:07.173998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33366 13:43:07.207269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33368 13:43:07.207677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33369 13:43:07.241970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33371 13:43:07.242387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33372 13:43:07.277952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33373 13:43:07.278322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33375 13:43:07.313420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33376 13:43:07.313870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33378 13:43:07.346453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33379 13:43:07.346926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33381 13:43:07.378820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33382 13:43:07.379283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33384 13:43:07.412096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33385 13:43:07.412570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33387 13:43:07.445954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33389 13:43:07.446457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33390 13:43:07.479355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33391 13:43:07.479897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33393 13:43:07.535111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33395 13:43:07.535702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33396 13:43:07.569057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33397 13:43:07.569452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33399 13:43:07.602302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33401 13:43:07.602809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33402 13:43:07.636154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33403 13:43:07.636609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33405 13:43:07.670275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33407 13:43:07.670823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33408 13:43:07.703980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33409 13:43:07.704336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33411 13:43:07.738324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33413 13:43:07.738921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33414 13:43:07.771778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33415 13:43:07.772199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33417 13:43:07.805521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33419 13:43:07.806042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33420 13:43:07.841707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33422 13:43:07.842349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33423 13:43:07.875677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33424 13:43:07.876125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33426 13:43:07.910351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33427 13:43:07.910773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33429 13:43:07.943154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33430 13:43:07.943640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33432 13:43:07.977413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33434 13:43:07.978002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33435 13:43:08.010524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33437 13:43:08.011108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33438 13:43:08.044658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33440 13:43:08.045172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33441 13:43:08.079026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33443 13:43:08.079543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33444 13:43:08.122631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33445 13:43:08.123034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33447 13:43:08.161008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33448 13:43:08.161459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33450 13:43:08.193080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33451 13:43:08.193512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33453 13:43:08.224801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33455 13:43:08.225208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33456 13:43:08.255875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33458 13:43:08.256374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33459 13:43:08.287155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33461 13:43:08.287686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33462 13:43:08.318231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33464 13:43:08.318623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33465 13:43:08.349889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33467 13:43:08.350404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33468 13:43:08.381235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33469 13:43:08.381695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33471 13:43:08.412523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33473 13:43:08.412988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33474 13:43:08.445474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33475 13:43:08.445965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33477 13:43:08.477715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33479 13:43:08.478293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33480 13:43:08.509719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33482 13:43:08.510274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33483 13:43:08.541780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33484 13:43:08.542210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33486 13:43:08.573599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33488 13:43:08.574076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33489 13:43:08.605402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33491 13:43:08.605886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33492 13:43:08.637428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33493 13:43:08.637949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33495 13:43:08.669375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33496 13:43:08.669858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33498 13:43:08.701439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33500 13:43:08.701927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33501 13:43:08.733802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33502 13:43:08.734157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33504 13:43:08.766097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33506 13:43:08.766655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33507 13:43:08.798038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33509 13:43:08.798547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33510 13:43:08.829720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33512 13:43:08.830331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33513 13:43:08.861344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33514 13:43:08.861816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33516 13:43:08.892813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33518 13:43:08.893379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33519 13:43:08.923348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33520 13:43:08.923756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33522 13:43:08.954963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33523 13:43:08.955352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33525 13:43:08.985932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33526 13:43:08.986347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33528 13:43:09.017444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33530 13:43:09.017959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33531 13:43:09.048120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33532 13:43:09.048512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33534 13:43:09.079355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33535 13:43:09.079766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33537 13:43:09.110936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33539 13:43:09.111426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33540 13:43:09.142225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33541 13:43:09.142643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33543 13:43:09.173656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33545 13:43:09.174416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33546 13:43:09.205788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33547 13:43:09.206234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33549 13:43:09.237218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33551 13:43:09.237805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33552 13:43:09.267917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33553 13:43:09.268359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33555 13:43:09.299909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33557 13:43:09.300488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33558 13:43:09.331169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33559 13:43:09.331637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33561 13:43:09.362481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33563 13:43:09.363042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33564 13:43:09.393912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33565 13:43:09.394321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33567 13:43:09.425086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33568 13:43:09.425428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33570 13:43:09.456580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33572 13:43:09.456956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33573 13:43:09.487624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33575 13:43:09.488053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33576 13:43:09.518436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33578 13:43:09.518833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33579 13:43:09.549397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33580 13:43:09.549767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33582 13:43:09.580223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33583 13:43:09.580590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33585 13:43:09.611450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33587 13:43:09.611843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33588 13:43:09.642361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33590 13:43:09.642953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33591 13:43:09.673285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33592 13:43:09.673702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33594 13:43:09.704410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33596 13:43:09.704985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33597 13:43:09.736524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33599 13:43:09.737026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33600 13:43:09.767308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33602 13:43:09.767830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33603 13:43:09.798570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33605 13:43:09.799062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33606 13:43:09.829710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33607 13:43:09.830111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33609 13:43:09.860917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33610 13:43:09.861316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33612 13:43:09.891815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33614 13:43:09.892344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33615 13:43:09.922678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33617 13:43:09.923063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33618 13:43:09.954168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33619 13:43:09.954521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33621 13:43:09.985230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33623 13:43:09.985618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33624 13:43:10.016494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33626 13:43:10.017026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33627 13:43:10.047523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33628 13:43:10.047930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33630 13:43:10.078391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33632 13:43:10.078852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33633 13:43:10.110590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33634 13:43:10.111053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33636 13:43:10.141950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33637 13:43:10.142394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33639 13:43:10.173572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33641 13:43:10.174202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33642 13:43:10.205321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33643 13:43:10.205732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33645 13:43:10.237433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33647 13:43:10.237886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33648 13:43:10.269283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33649 13:43:10.269680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33651 13:43:10.301084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33652 13:43:10.301490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33654 13:43:10.333094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33655 13:43:10.333526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33657 13:43:10.364967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33658 13:43:10.365366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33660 13:43:10.396182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33662 13:43:10.396632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33663 13:43:10.428293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33665 13:43:10.428851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33666 13:43:10.459823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33668 13:43:10.460450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33669 13:43:10.492979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33671 13:43:10.493724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33672 13:43:10.525835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33674 13:43:10.526392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33675 13:43:10.558103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33677 13:43:10.558648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33678 13:43:10.589906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33680 13:43:10.590440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33681 13:43:10.621555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33683 13:43:10.622132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33684 13:43:10.652898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33686 13:43:10.653397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33687 13:43:10.683498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33689 13:43:10.683995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33690 13:43:10.714554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33691 13:43:10.714977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33693 13:43:10.747404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33694 13:43:10.747857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33696 13:43:10.779881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33697 13:43:10.780333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33699 13:43:10.811569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33700 13:43:10.812011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33702 13:43:10.843380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33704 13:43:10.844031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33705 13:43:10.874687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33707 13:43:10.875310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33708 13:43:10.906003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33709 13:43:10.906468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33711 13:43:10.937566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33712 13:43:10.938072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33714 13:43:10.971698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33716 13:43:10.972307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33717 13:43:11.003197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33718 13:43:11.003655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33720 13:43:11.034250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33722 13:43:11.034799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33723 13:43:11.065794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33725 13:43:11.066336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33726 13:43:11.097749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33727 13:43:11.098177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33729 13:43:11.130776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33731 13:43:11.131249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33732 13:43:11.163430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33734 13:43:11.163814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33735 13:43:11.194488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33737 13:43:11.194844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33738 13:43:11.226016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33739 13:43:11.226411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33741 13:43:11.257548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33743 13:43:11.258145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33744 13:43:11.288978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33745 13:43:11.289419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33747 13:43:11.319932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33749 13:43:11.320485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33750 13:43:11.351252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33752 13:43:11.351689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33753 13:43:11.382613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33755 13:43:11.383058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33756 13:43:11.413855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33758 13:43:11.414418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33759 13:43:11.445813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33761 13:43:11.446444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33762 13:43:11.478606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33764 13:43:11.479186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33765 13:43:11.510362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33767 13:43:11.510975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33768 13:43:11.541555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33769 13:43:11.542033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33771 13:43:11.573224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33773 13:43:11.573824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33774 13:43:11.604983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33775 13:43:11.605442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33777 13:43:11.636090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33778 13:43:11.636486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33780 13:43:11.667551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33781 13:43:11.667958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33783 13:43:11.698657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33784 13:43:11.699070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33786 13:43:11.729780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33787 13:43:11.730249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33789 13:43:11.762342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33790 13:43:11.762797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33792 13:43:11.793981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33794 13:43:11.794531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33795 13:43:11.824998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33796 13:43:11.825449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33798 13:43:11.856095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33799 13:43:11.856527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33801 13:43:11.887264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33802 13:43:11.887637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33804 13:43:11.917999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33805 13:43:11.918480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33807 13:43:11.949482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33808 13:43:11.949991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33810 13:43:11.984096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33812 13:43:11.984663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33813 13:43:12.016033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33814 13:43:12.016451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33816 13:43:12.047342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33818 13:43:12.047786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33819 13:43:12.079533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33821 13:43:12.080100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33822 13:43:12.112319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33823 13:43:12.112781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33825 13:43:12.144143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33826 13:43:12.144605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33828 13:43:12.176164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33830 13:43:12.176717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33831 13:43:12.208027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33833 13:43:12.208579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33834 13:43:12.239130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33835 13:43:12.239568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33837 13:43:12.270764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33838 13:43:12.271209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33840 13:43:12.302389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33842 13:43:12.302944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33843 13:43:12.333415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33844 13:43:12.333869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33846 13:43:12.364540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33848 13:43:12.364974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33849 13:43:12.396977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33850 13:43:12.397383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33852 13:43:12.429035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33853 13:43:12.429485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33855 13:43:12.460863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33856 13:43:12.461298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33858 13:43:12.493632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33859 13:43:12.494105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33861 13:43:12.526398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33863 13:43:12.526966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33864 13:43:12.558313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33866 13:43:12.558825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33867 13:43:12.590045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33869 13:43:12.590527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33870 13:43:12.633815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33871 13:43:12.634250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33873 13:43:12.674628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33875 13:43:12.675145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33876 13:43:12.706441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33877 13:43:12.706889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33879 13:43:12.737559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33880 13:43:12.737997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33882 13:43:12.768873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33883 13:43:12.769297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33885 13:43:12.800522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33887 13:43:12.801083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33888 13:43:12.832913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33889 13:43:12.833320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33891 13:43:12.864319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33893 13:43:12.864869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33894 13:43:12.895850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33895 13:43:12.896214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33897 13:43:12.927873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33899 13:43:12.928272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33900 13:43:12.959398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33901 13:43:12.959850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33903 13:43:12.991190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33905 13:43:12.991728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33906 13:43:13.023712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33907 13:43:13.024134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33909 13:43:13.055552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33910 13:43:13.055962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33912 13:43:13.087106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33913 13:43:13.087510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33915 13:43:13.118963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33916 13:43:13.119393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33918 13:43:13.151271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33920 13:43:13.151714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33921 13:43:13.183360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33923 13:43:13.183804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33924 13:43:13.215078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33925 13:43:13.215501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33927 13:43:13.246761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33928 13:43:13.247162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33930 13:43:13.278756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33931 13:43:13.279165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33933 13:43:13.310088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33934 13:43:13.310496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33936 13:43:13.342066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33937 13:43:13.342474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33939 13:43:13.373996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
33941 13:43:13.374553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33942 13:43:13.405423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33943 13:43:13.405818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33945 13:43:13.437334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33947 13:43:13.437913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33948 13:43:13.470981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
33950 13:43:13.471535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33951 13:43:13.501922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33953 13:43:13.502359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33954 13:43:13.534425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33956 13:43:13.534904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33957 13:43:13.565614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
33959 13:43:13.566153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33960 13:43:13.596907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33961 13:43:13.597301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33963 13:43:13.627627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
33964 13:43:13.628015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
33966 13:43:13.658475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33968 13:43:13.659030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33969 13:43:13.689395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33970 13:43:13.689806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
33972 13:43:13.721094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33973 13:43:13.721549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33975 13:43:13.752312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33977 13:43:13.752913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33978 13:43:13.783696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
33980 13:43:13.784311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33981 13:43:13.815900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33982 13:43:13.816349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33984 13:43:13.847239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33986 13:43:13.847740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33987 13:43:13.877901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33988 13:43:13.878380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
33990 13:43:13.909254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33991 13:43:13.909662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33993 13:43:13.940119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33994 13:43:13.940580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33996 13:43:13.971264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
33998 13:43:13.971844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33999 13:43:14.003240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
34000 13:43:14.003712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
34002 13:43:14.035729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
34003 13:43:14.036224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
34005 13:43:14.067064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
34007 13:43:14.067645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
34008 13:43:14.098068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
34009 13:43:14.098512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
34011 13:43:14.129269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
34012 13:43:14.129693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
34014 13:43:14.160664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
34016 13:43:14.161249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
34017 13:43:14.192687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
34019 13:43:14.193236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
34020 13:43:14.223741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
34022 13:43:14.224301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
34023 13:43:14.255342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
34025 13:43:14.255908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
34026 13:43:14.286723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
34028 13:43:14.287302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
34029 13:43:14.317644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
34030 13:43:14.318106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
34032 13:43:14.349255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
34033 13:43:14.349692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
34035 13:43:14.381405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
34036 13:43:14.381903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
34038 13:43:14.413249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
34040 13:43:14.413821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
34041 13:43:14.445808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
34042 13:43:14.446272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
34044 13:43:14.477660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
34045 13:43:14.478131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
34047 13:43:14.509029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
34049 13:43:14.509510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
34050 13:43:14.540844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
34051 13:43:14.541232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
34053 13:43:14.571558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
34054 13:43:14.571958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
34056 13:43:14.602760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
34058 13:43:14.603255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
34059 13:43:14.633864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
34061 13:43:14.634314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
34062 13:43:14.665951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
34063 13:43:14.666414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
34065 13:43:14.697667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
34067 13:43:14.698216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
34068 13:43:14.729144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
34069 13:43:14.729557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
34071 13:43:14.760612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
34073 13:43:14.761136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
34074 13:43:14.792230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
34076 13:43:14.792745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
34077 13:43:14.823844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
34078 13:43:14.824225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
34080 13:43:14.855284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
34081 13:43:14.855641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
34083 13:43:14.886234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
34084 13:43:14.886664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
34086 13:43:14.917223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
34087 13:43:14.917752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
34089 13:43:14.948206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
34090 13:43:14.948643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
34092 13:43:14.979407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
34093 13:43:14.979805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
34095 13:43:15.010400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
34097 13:43:15.010909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
34098 13:43:15.042158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
34099 13:43:15.042609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
34101 13:43:15.073493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
34102 13:43:15.073940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
34104 13:43:15.105194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
34105 13:43:15.105678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
34107 13:43:15.136557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
34109 13:43:15.137103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
34110 13:43:15.167880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
34111 13:43:15.168372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
34113 13:43:15.199847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
34115 13:43:15.200307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
34116 13:43:15.231339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
34117 13:43:15.231758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
34119 13:43:15.262666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
34121 13:43:15.263091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
34122 13:43:15.294024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
34124 13:43:15.294569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
34125 13:43:15.325435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
34127 13:43:15.326017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
34128 13:43:15.357221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
34129 13:43:15.357685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
34131 13:43:15.388522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
34133 13:43:15.389060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
34134 13:43:15.419894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
34135 13:43:15.420380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
34137 13:43:15.451191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
34139 13:43:15.451747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
34140 13:43:15.482109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
34141 13:43:15.482555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
34143 13:43:15.514086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
34145 13:43:15.514670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
34146 13:43:15.548044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
34148 13:43:15.548607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
34149 13:43:15.579718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
34150 13:43:15.580204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
34152 13:43:15.611811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
34154 13:43:15.612443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
34155 13:43:15.643011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
34156 13:43:15.643470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
34158 13:43:15.674263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
34160 13:43:15.674874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
34161 13:43:15.705463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
34162 13:43:15.705931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
34164 13:43:15.741132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
34166 13:43:15.741712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
34167 13:43:15.772949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
34169 13:43:15.773576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
34170 13:43:15.804073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
34171 13:43:15.804554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
34173 13:43:15.835799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
34175 13:43:15.836308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
34176 13:43:15.866984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
34178 13:43:15.867430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
34179 13:43:15.898509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
34180 13:43:15.898897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
34182 13:43:15.929990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
34183 13:43:15.930353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
34185 13:43:15.961700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
34186 13:43:15.962177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
34188 13:43:15.995589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
34190 13:43:15.996041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
34191 13:43:16.028589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
34193 13:43:16.029109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
34194 13:43:16.062727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
34196 13:43:16.063271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
34197 13:43:16.095993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
34199 13:43:16.096547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
34200 13:43:16.127591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
34201 13:43:16.127990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
34203 13:43:16.158808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
34205 13:43:16.159210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
34206 13:43:16.190515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
34207 13:43:16.190885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
34209 13:43:16.222925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
34211 13:43:16.223440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
34212 13:43:16.254037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
34214 13:43:16.254670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
34215 13:43:16.285523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
34216 13:43:16.285984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
34218 13:43:16.316929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
34220 13:43:16.317367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
34221 13:43:16.348490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
34223 13:43:16.348949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
34224 13:43:16.380402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
34226 13:43:16.381064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
34227 13:43:16.412738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
34229 13:43:16.413380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
34230 13:43:16.444276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
34231 13:43:16.444733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
34233 13:43:16.475591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
34234 13:43:16.476020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
34236 13:43:16.506909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
34237 13:43:16.507348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
34239 13:43:16.537960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
34240 13:43:16.538400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
34242 13:43:16.570198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
34243 13:43:16.570605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
34245 13:43:16.602088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
34247 13:43:16.602566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
34248 13:43:16.633612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
34250 13:43:16.634163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
34251 13:43:16.665066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
34253 13:43:16.665634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
34254 13:43:16.696098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
34255 13:43:16.696546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
34257 13:43:16.727272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
34259 13:43:16.727824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
34260 13:43:16.758108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
34262 13:43:16.758701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
34263 13:43:16.789296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
34264 13:43:16.789783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
34266 13:43:16.820312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
34268 13:43:16.820855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
34269 13:43:16.851992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
34270 13:43:16.852406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
34272 13:43:16.884058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
34273 13:43:16.884474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
34275 13:43:16.915743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
34276 13:43:16.916192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
34278 13:43:16.946757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
34280 13:43:16.947282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
34281 13:43:16.978089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
34282 13:43:16.978536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
34284 13:43:17.009338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
34285 13:43:17.009783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
34287 13:43:17.040507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
34289 13:43:17.041030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
34290 13:43:17.072490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
34292 13:43:17.073027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
34293 13:43:17.103496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
34295 13:43:17.104035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
34296 13:43:17.134276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
34297 13:43:17.134727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
34299 13:43:17.165469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34301 13:43:17.166047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
34302 13:43:17.196640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34304 13:43:17.197174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34305 13:43:17.227789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34306 13:43:17.228210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34308 13:43:17.258656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34309 13:43:17.259040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34311 13:43:17.289525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34313 13:43:17.290075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34314 13:43:17.320133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34315 13:43:17.320556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34317 13:43:17.350690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34318 13:43:17.351099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34320 13:43:17.382254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34322 13:43:17.382822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34323 13:43:17.413545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34324 13:43:17.413954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34326 13:43:17.444609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34328 13:43:17.445097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34329 13:43:17.475530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34330 13:43:17.475949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34332 13:43:17.506384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34333 13:43:17.506806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34335 13:43:17.537484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34337 13:43:17.538044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34338 13:43:17.569285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34339 13:43:17.569697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34341 13:43:17.600562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34343 13:43:17.601108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34344 13:43:17.631621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34345 13:43:17.632014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34347 13:43:17.662946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34349 13:43:17.663567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34350 13:43:17.694168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34352 13:43:17.694695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34353 13:43:17.725516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34355 13:43:17.726029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34356 13:43:17.776848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34358 13:43:17.777293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34359 13:43:17.807745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34360 13:43:17.808115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34362 13:43:17.838560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34363 13:43:17.838919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34365 13:43:17.870277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34366 13:43:17.870691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34368 13:43:17.901783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34369 13:43:17.902195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34371 13:43:17.933596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34372 13:43:17.934004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34374 13:43:17.964281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34376 13:43:17.964835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34377 13:43:17.997720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34379 13:43:17.998356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34380 13:43:18.029117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34381 13:43:18.029574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34383 13:43:18.059907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34384 13:43:18.060343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34386 13:43:18.093721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34388 13:43:18.094277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34389 13:43:18.125331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34391 13:43:18.125895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34392 13:43:18.156273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34393 13:43:18.156730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34395 13:43:18.187545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34397 13:43:18.188082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34398 13:43:18.218867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34400 13:43:18.219410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34401 13:43:18.250674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34402 13:43:18.251134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34404 13:43:18.281829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34406 13:43:18.282360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34407 13:43:18.313231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34408 13:43:18.313675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34410 13:43:18.344222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34412 13:43:18.344769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34413 13:43:18.375322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34414 13:43:18.375720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34416 13:43:18.406880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34418 13:43:18.407478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34419 13:43:18.438033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34421 13:43:18.438541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34422 13:43:18.469094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34424 13:43:18.469586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34425 13:43:18.499759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34426 13:43:18.500164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34428 13:43:18.531388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34430 13:43:18.531926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34431 13:43:18.562476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34432 13:43:18.562925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34434 13:43:18.594279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34436 13:43:18.594686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34437 13:43:18.625422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34438 13:43:18.625782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34440 13:43:18.656513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34442 13:43:18.656919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34443 13:43:18.686982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34445 13:43:18.687384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34446 13:43:18.717968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34447 13:43:18.718392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34449 13:43:18.749723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34450 13:43:18.750130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34452 13:43:18.782160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34454 13:43:18.782718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34455 13:43:18.815080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34457 13:43:18.815626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34458 13:43:18.845940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34459 13:43:18.846405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34461 13:43:18.877794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34462 13:43:18.878240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34464 13:43:18.909399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34465 13:43:18.909870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34467 13:43:18.941261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34468 13:43:18.941691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34470 13:43:18.972592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34472 13:43:18.973139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34473 13:43:19.003807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34474 13:43:19.004207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34476 13:43:19.034545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34477 13:43:19.034962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34479 13:43:19.066027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34480 13:43:19.066498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34482 13:43:19.097841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34483 13:43:19.098305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34485 13:43:19.128960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34486 13:43:19.129363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34488 13:43:19.159658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34489 13:43:19.160105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34491 13:43:19.190327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34492 13:43:19.190725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34494 13:43:19.221903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34495 13:43:19.222387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34497 13:43:19.253811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34499 13:43:19.254316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34500 13:43:19.284919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34502 13:43:19.285445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34503 13:43:19.315565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34504 13:43:19.315925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34506 13:43:19.346568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34507 13:43:19.346923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34509 13:43:19.377885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34510 13:43:19.378312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34512 13:43:19.408889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34513 13:43:19.409294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34515 13:43:19.439861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34516 13:43:19.440274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34518 13:43:19.471441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34520 13:43:19.471959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34521 13:43:19.502040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34522 13:43:19.502453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34524 13:43:19.533349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34526 13:43:19.533875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34527 13:43:19.564197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34529 13:43:19.564664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34530 13:43:19.596952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34532 13:43:19.597476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34533 13:43:19.628525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34535 13:43:19.629026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34536 13:43:19.659896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34538 13:43:19.660357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34539 13:43:19.691053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34540 13:43:19.691448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34542 13:43:19.721837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34543 13:43:19.722213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34545 13:43:19.753752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34547 13:43:19.754262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34548 13:43:19.785147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34549 13:43:19.785506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34551 13:43:19.816475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34553 13:43:19.816945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34554 13:43:19.847698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34555 13:43:19.848069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34557 13:43:19.879375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34558 13:43:19.879704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34560 13:43:19.910252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34561 13:43:19.910618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34563 13:43:19.941489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34565 13:43:19.941883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34566 13:43:19.972549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34568 13:43:19.973051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34569 13:43:20.004526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34571 13:43:20.005034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34572 13:43:20.035183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34573 13:43:20.035592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34575 13:43:20.065857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34576 13:43:20.066252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34578 13:43:20.097870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34580 13:43:20.098364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34581 13:43:20.129388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34582 13:43:20.129784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34584 13:43:20.161301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34585 13:43:20.161777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34587 13:43:20.192428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34589 13:43:20.193011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34590 13:43:20.224494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34592 13:43:20.225097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34593 13:43:20.257337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34594 13:43:20.257746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34596 13:43:20.289507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34598 13:43:20.290066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34599 13:43:20.321476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34600 13:43:20.321960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34602 13:43:20.352587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34604 13:43:20.353168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34605 13:43:20.384870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34606 13:43:20.385307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34608 13:43:20.415865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34609 13:43:20.416320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34611 13:43:20.447636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34612 13:43:20.448076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34614 13:43:20.478790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34615 13:43:20.479238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34617 13:43:20.510199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34618 13:43:20.510648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34620 13:43:20.542604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34621 13:43:20.543083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34623 13:43:20.574032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34624 13:43:20.574421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34626 13:43:20.605793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34628 13:43:20.606346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34629 13:43:20.637604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34630 13:43:20.638065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34632 13:43:20.669366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34633 13:43:20.669803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34635 13:43:20.700166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34637 13:43:20.700691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34638 13:43:20.731183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34640 13:43:20.731722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34641 13:43:20.762277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34642 13:43:20.762707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34644 13:43:20.793586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34645 13:43:20.794062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34647 13:43:20.825059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34648 13:43:20.825511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34650 13:43:20.856035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34652 13:43:20.856518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34653 13:43:20.886953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34655 13:43:20.887364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34656 13:43:20.889682 + set +x
34657 13:43:20.889812 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 652449_1.1.3.5>
34658 13:43:20.890099 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 652449_1.1.3.5
34659 13:43:20.890215 Ending use of test pattern.
34660 13:43:20.890307 Ending test lava.1_kselftest-arm64_qemu (652449_1.1.3.5), duration 320.48
34662 13:43:20.893124 ok: lava_test_shell seems to have completed
34663 13:43:20.979212 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34664 13:43:20.982623 end: 3.1 lava-test-shell (duration 00:05:22) [common]
34665 13:43:20.982720 end: 3 lava-test-retry (duration 00:05:22) [common]
34666 13:43:20.982812 start: 4 finalize (timeout 00:03:31) [common]
34667 13:43:20.982900 start: 4.1 power-off (timeout 00:00:30) [common]
34668 13:43:20.982981 end: 4.1 power-off (duration 00:00:00) [common]
34669 13:43:20.983061 start: 4.2 read-feedback (timeout 00:03:31) [common]
34671 13:43:20.983514 Listened to connection for namespace 'common' for up to 1s
34672 13:43:21.988295 Finalising connection for namespace 'common'
34674 13:43:22.089319 / # poweroff
34675 13:43:22.089801 Already disconnected
34676 13:43:22.089975 poweroff
34677 13:43:22.190866 end: 4.2 read-feedback (duration 00:00:01) [common]
34678 13:43:22.191145 Already disconnected
34679 13:43:22.191317 end: 4 finalize (duration 00:00:01) [common]
34680 13:43:22.191493 Cleaning after the job
34681 13:43:22.191672 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/652449/deployimages-p3_52l4y/kernel
34682 13:43:22.198741 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/652449/deployimages-p3_52l4y/ramdisk
34683 13:43:22.214561 Stopping the qemu container lava-docker-qemu-652449-2.1.1-lpin87rpdl
34684 13:43:23.204359 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/652449
34685 13:43:23.287826 Job finished correctly