Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 24
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 34
- Errors: 1
1 15:35:01.380823 lava-dispatcher, installed at version: 2023.06
2 15:35:01.381062 start: 0 validate
3 15:35:01.381202 Start time: 2023-08-22 15:35:01.381194+00:00 (UTC)
4 15:35:01.381340 Using caching service: 'http://localhost/cache/?uri=%s'
5 15:35:01.381492 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 15:35:01.651025 Using caching service: 'http://localhost/cache/?uri=%s'
7 15:35:01.651823 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 15:35:01.916736 Using caching service: 'http://localhost/cache/?uri=%s'
9 15:35:01.917489 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 15:35:36.412869 Using caching service: 'http://localhost/cache/?uri=%s'
11 15:35:36.413035 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 15:35:36.935587 validate duration: 35.55
14 15:35:36.935846 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 15:35:36.935945 start: 1.1 download-retry (timeout 00:10:00) [common]
16 15:35:36.936030 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 15:35:36.936156 Not decompressing ramdisk as can be used compressed.
18 15:35:36.936319 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 15:35:36.936423 saving as /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/ramdisk/rootfs.cpio.gz
20 15:35:36.936501 total size: 8181372 (7 MB)
21 15:35:40.649441 progress 0 % (0 MB)
22 15:35:40.661402 progress 5 % (0 MB)
23 15:35:40.672138 progress 10 % (0 MB)
24 15:35:40.681322 progress 15 % (1 MB)
25 15:35:40.686958 progress 20 % (1 MB)
26 15:35:40.691728 progress 25 % (1 MB)
27 15:35:40.695605 progress 30 % (2 MB)
28 15:35:40.699240 progress 35 % (2 MB)
29 15:35:40.702322 progress 40 % (3 MB)
30 15:35:40.705498 progress 45 % (3 MB)
31 15:35:40.708132 progress 50 % (3 MB)
32 15:35:40.710901 progress 55 % (4 MB)
33 15:35:40.713204 progress 60 % (4 MB)
34 15:35:40.715708 progress 65 % (5 MB)
35 15:35:40.717808 progress 70 % (5 MB)
36 15:35:40.720091 progress 75 % (5 MB)
37 15:35:40.722169 progress 80 % (6 MB)
38 15:35:40.724430 progress 85 % (6 MB)
39 15:35:40.726495 progress 90 % (7 MB)
40 15:35:40.728779 progress 95 % (7 MB)
41 15:35:40.730898 progress 100 % (7 MB)
42 15:35:40.731118 7 MB downloaded in 3.79 s (2.06 MB/s)
43 15:35:40.731275 end: 1.1.1 http-download (duration 00:00:04) [common]
45 15:35:40.731519 end: 1.1 download-retry (duration 00:00:04) [common]
46 15:35:40.731606 start: 1.2 download-retry (timeout 00:09:56) [common]
47 15:35:40.731691 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 15:35:40.731840 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 15:35:40.731920 saving as /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/kernel/Image
50 15:35:40.731982 total size: 49220096 (46 MB)
51 15:35:40.732045 No compression specified
52 15:35:40.733531 progress 0 % (0 MB)
53 15:35:40.746716 progress 5 % (2 MB)
54 15:35:40.760738 progress 10 % (4 MB)
55 15:35:40.775127 progress 15 % (7 MB)
56 15:35:40.788344 progress 20 % (9 MB)
57 15:35:40.801418 progress 25 % (11 MB)
58 15:35:40.814486 progress 30 % (14 MB)
59 15:35:40.827779 progress 35 % (16 MB)
60 15:35:40.841077 progress 40 % (18 MB)
61 15:35:40.853942 progress 45 % (21 MB)
62 15:35:40.867296 progress 50 % (23 MB)
63 15:35:40.880386 progress 55 % (25 MB)
64 15:35:40.893547 progress 60 % (28 MB)
65 15:35:40.906689 progress 65 % (30 MB)
66 15:35:40.919609 progress 70 % (32 MB)
67 15:35:40.932671 progress 75 % (35 MB)
68 15:35:40.945614 progress 80 % (37 MB)
69 15:35:40.958589 progress 85 % (39 MB)
70 15:35:40.971789 progress 90 % (42 MB)
71 15:35:40.985154 progress 95 % (44 MB)
72 15:35:40.998409 progress 100 % (46 MB)
73 15:35:40.998570 46 MB downloaded in 0.27 s (176.08 MB/s)
74 15:35:40.998773 end: 1.2.1 http-download (duration 00:00:00) [common]
76 15:35:40.999014 end: 1.2 download-retry (duration 00:00:00) [common]
77 15:35:40.999106 start: 1.3 download-retry (timeout 00:09:56) [common]
78 15:35:40.999192 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 15:35:40.999360 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 15:35:40.999432 saving as /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/dtb/mt8192-asurada-spherion-r0.dtb
81 15:35:40.999495 total size: 47278 (0 MB)
82 15:35:40.999557 No compression specified
83 15:35:41.000790 progress 69 % (0 MB)
84 15:35:41.001070 progress 100 % (0 MB)
85 15:35:41.001227 0 MB downloaded in 0.00 s (26.06 MB/s)
86 15:35:41.001350 end: 1.3.1 http-download (duration 00:00:00) [common]
88 15:35:41.001572 end: 1.3 download-retry (duration 00:00:00) [common]
89 15:35:41.001658 start: 1.4 download-retry (timeout 00:09:56) [common]
90 15:35:41.001741 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 15:35:41.001858 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 15:35:41.001968 saving as /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/modules/modules.tar
93 15:35:41.002029 total size: 8608784 (8 MB)
94 15:35:41.002090 Using unxz to decompress xz
95 15:35:41.006314 progress 0 % (0 MB)
96 15:35:41.027919 progress 5 % (0 MB)
97 15:35:41.050523 progress 10 % (0 MB)
98 15:35:41.076889 progress 15 % (1 MB)
99 15:35:41.103720 progress 20 % (1 MB)
100 15:35:41.130005 progress 25 % (2 MB)
101 15:35:41.156258 progress 30 % (2 MB)
102 15:35:41.181326 progress 35 % (2 MB)
103 15:35:41.209484 progress 40 % (3 MB)
104 15:35:41.234276 progress 45 % (3 MB)
105 15:35:41.261134 progress 50 % (4 MB)
106 15:35:41.286499 progress 55 % (4 MB)
107 15:35:41.311518 progress 60 % (4 MB)
108 15:35:41.334543 progress 65 % (5 MB)
109 15:35:41.360033 progress 70 % (5 MB)
110 15:35:41.386467 progress 75 % (6 MB)
111 15:35:41.414546 progress 80 % (6 MB)
112 15:35:41.445820 progress 85 % (7 MB)
113 15:35:41.472104 progress 90 % (7 MB)
114 15:35:41.496610 progress 95 % (7 MB)
115 15:35:41.520291 progress 100 % (8 MB)
116 15:35:41.526215 8 MB downloaded in 0.52 s (15.66 MB/s)
117 15:35:41.526466 end: 1.4.1 http-download (duration 00:00:01) [common]
119 15:35:41.526780 end: 1.4 download-retry (duration 00:00:01) [common]
120 15:35:41.526875 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 15:35:41.526973 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 15:35:41.527057 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 15:35:41.527144 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 15:35:41.527373 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu
125 15:35:41.527513 makedir: /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin
126 15:35:41.527622 makedir: /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/tests
127 15:35:41.527722 makedir: /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/results
128 15:35:41.527842 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-add-keys
129 15:35:41.527996 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-add-sources
130 15:35:41.528128 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-background-process-start
131 15:35:41.528273 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-background-process-stop
132 15:35:41.528404 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-common-functions
133 15:35:41.528532 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-echo-ipv4
134 15:35:41.528658 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-install-packages
135 15:35:41.528785 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-installed-packages
136 15:35:41.528909 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-os-build
137 15:35:41.529035 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-probe-channel
138 15:35:41.529161 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-probe-ip
139 15:35:41.529286 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-target-ip
140 15:35:41.529411 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-target-mac
141 15:35:41.529538 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-target-storage
142 15:35:41.529669 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-test-case
143 15:35:41.529794 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-test-event
144 15:35:41.529920 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-test-feedback
145 15:35:41.530047 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-test-raise
146 15:35:41.530194 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-test-reference
147 15:35:41.530323 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-test-runner
148 15:35:41.530451 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-test-set
149 15:35:41.530582 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-test-shell
150 15:35:41.530719 Updating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-install-packages (oe)
151 15:35:41.530876 Updating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/bin/lava-installed-packages (oe)
152 15:35:41.531003 Creating /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/environment
153 15:35:41.531104 LAVA metadata
154 15:35:41.531178 - LAVA_JOB_ID=11331363
155 15:35:41.531242 - LAVA_DISPATCHER_IP=192.168.201.1
156 15:35:41.531343 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 15:35:41.531410 skipped lava-vland-overlay
158 15:35:41.531484 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 15:35:41.531566 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 15:35:41.531628 skipped lava-multinode-overlay
161 15:35:41.531703 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 15:35:41.531809 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 15:35:41.531903 Loading test definitions
164 15:35:41.532012 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:55) [common]
165 15:35:41.532095 Using /lava-11331363 at stage 0
166 15:35:41.532415 uuid=11331363_1.5.2.3.1 testdef=None
167 15:35:41.532504 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 15:35:41.532588 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
169 15:35:41.533136 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 15:35:41.533355 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
172 15:35:41.534011 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 15:35:41.534239 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
175 15:35:41.534920 runner path: /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/0/tests/0_dmesg test_uuid 11331363_1.5.2.3.1
176 15:35:41.535078 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 15:35:41.535304 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:55) [common]
179 15:35:41.535376 Using /lava-11331363 at stage 1
180 15:35:41.535698 uuid=11331363_1.5.2.3.5 testdef=None
181 15:35:41.535787 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 15:35:41.535872 start: 1.5.2.3.6 test-overlay (timeout 00:09:55) [common]
183 15:35:41.536345 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 15:35:41.536559 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:55) [common]
186 15:35:41.537721 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 15:35:41.537950 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:55) [common]
189 15:35:41.538693 runner path: /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/1/tests/1_bootrr test_uuid 11331363_1.5.2.3.5
190 15:35:41.538848 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 15:35:41.539056 Creating lava-test-runner.conf files
193 15:35:41.539119 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/0 for stage 0
194 15:35:41.539210 - 0_dmesg
195 15:35:41.539289 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11331363/lava-overlay-u4x80zwu/lava-11331363/1 for stage 1
196 15:35:41.539385 - 1_bootrr
197 15:35:41.539479 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 15:35:41.539562 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
199 15:35:41.547882 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 15:35:41.547998 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
201 15:35:41.548085 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 15:35:41.548172 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 15:35:41.548261 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
204 15:35:41.803377 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 15:35:41.803759 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
206 15:35:41.803880 extracting modules file /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11331363/extract-overlay-ramdisk-ck7cw5_f/ramdisk
207 15:35:42.034072 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 15:35:42.034260 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
209 15:35:42.034404 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11331363/compress-overlay-8bxw5cbn/overlay-1.5.2.4.tar.gz to ramdisk
210 15:35:42.034507 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11331363/compress-overlay-8bxw5cbn/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11331363/extract-overlay-ramdisk-ck7cw5_f/ramdisk
211 15:35:42.043280 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 15:35:42.043402 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
213 15:35:42.043521 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 15:35:42.043607 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
215 15:35:42.043685 Building ramdisk /var/lib/lava/dispatcher/tmp/11331363/extract-overlay-ramdisk-ck7cw5_f/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11331363/extract-overlay-ramdisk-ck7cw5_f/ramdisk
216 15:35:42.443750 >> 145125 blocks
217 15:35:44.848702 rename /var/lib/lava/dispatcher/tmp/11331363/extract-overlay-ramdisk-ck7cw5_f/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/ramdisk/ramdisk.cpio.gz
218 15:35:44.849178 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 15:35:44.849314 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
220 15:35:44.849418 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
221 15:35:44.849542 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/kernel/Image'
222 15:35:57.818012 Returned 0 in 12 seconds
223 15:35:57.918681 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/kernel/image.itb
224 15:35:58.332038 output: FIT description: Kernel Image image with one or more FDT blobs
225 15:35:58.332434 output: Created: Tue Aug 22 16:35:58 2023
226 15:35:58.332547 output: Image 0 (kernel-1)
227 15:35:58.332618 output: Description:
228 15:35:58.332693 output: Created: Tue Aug 22 16:35:58 2023
229 15:35:58.332764 output: Type: Kernel Image
230 15:35:58.332832 output: Compression: lzma compressed
231 15:35:58.332891 output: Data Size: 11035343 Bytes = 10776.70 KiB = 10.52 MiB
232 15:35:58.332963 output: Architecture: AArch64
233 15:35:58.333024 output: OS: Linux
234 15:35:58.333085 output: Load Address: 0x00000000
235 15:35:58.333139 output: Entry Point: 0x00000000
236 15:35:58.333203 output: Hash algo: crc32
237 15:35:58.333259 output: Hash value: fe81bcf6
238 15:35:58.333313 output: Image 1 (fdt-1)
239 15:35:58.333367 output: Description: mt8192-asurada-spherion-r0
240 15:35:58.333431 output: Created: Tue Aug 22 16:35:58 2023
241 15:35:58.333487 output: Type: Flat Device Tree
242 15:35:58.333541 output: Compression: uncompressed
243 15:35:58.333595 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 15:35:58.333655 output: Architecture: AArch64
245 15:35:58.333714 output: Hash algo: crc32
246 15:35:58.333767 output: Hash value: cc4352de
247 15:35:58.333821 output: Image 2 (ramdisk-1)
248 15:35:58.333880 output: Description: unavailable
249 15:35:58.333938 output: Created: Tue Aug 22 16:35:58 2023
250 15:35:58.333995 output: Type: RAMDisk Image
251 15:35:58.334049 output: Compression: Unknown Compression
252 15:35:58.334109 output: Data Size: 21374256 Bytes = 20873.30 KiB = 20.38 MiB
253 15:35:58.334171 output: Architecture: AArch64
254 15:35:58.334229 output: OS: Linux
255 15:35:58.334283 output: Load Address: unavailable
256 15:35:58.334362 output: Entry Point: unavailable
257 15:35:58.334456 output: Hash algo: crc32
258 15:35:58.334540 output: Hash value: d19872d2
259 15:35:58.334635 output: Default Configuration: 'conf-1'
260 15:35:58.334696 output: Configuration 0 (conf-1)
261 15:35:58.334750 output: Description: mt8192-asurada-spherion-r0
262 15:35:58.334804 output: Kernel: kernel-1
263 15:35:58.334864 output: Init Ramdisk: ramdisk-1
264 15:35:58.334921 output: FDT: fdt-1
265 15:35:58.334976 output: Loadables: kernel-1
266 15:35:58.335030 output:
267 15:35:58.335242 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 15:35:58.335347 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 15:35:58.335460 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 15:35:58.335557 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
271 15:35:58.335645 No LXC device requested
272 15:35:58.335732 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 15:35:58.335822 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
274 15:35:58.335912 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 15:35:58.335986 Checking files for TFTP limit of 4294967296 bytes.
276 15:35:58.336571 end: 1 tftp-deploy (duration 00:00:21) [common]
277 15:35:58.336695 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 15:35:58.336820 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 15:35:58.336999 substitutions:
280 15:35:58.337100 - {DTB}: 11331363/tftp-deploy-nz64uxrg/dtb/mt8192-asurada-spherion-r0.dtb
281 15:35:58.337200 - {INITRD}: 11331363/tftp-deploy-nz64uxrg/ramdisk/ramdisk.cpio.gz
282 15:35:58.337291 - {KERNEL}: 11331363/tftp-deploy-nz64uxrg/kernel/Image
283 15:35:58.337388 - {LAVA_MAC}: None
284 15:35:58.337478 - {PRESEED_CONFIG}: None
285 15:35:58.337564 - {PRESEED_LOCAL}: None
286 15:35:58.337657 - {RAMDISK}: 11331363/tftp-deploy-nz64uxrg/ramdisk/ramdisk.cpio.gz
287 15:35:58.337747 - {ROOT_PART}: None
288 15:35:58.337837 - {ROOT}: None
289 15:35:58.337927 - {SERVER_IP}: 192.168.201.1
290 15:35:58.338014 - {TEE}: None
291 15:35:58.338105 Parsed boot commands:
292 15:35:58.338194 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 15:35:58.338441 Parsed boot commands: tftpboot 192.168.201.1 11331363/tftp-deploy-nz64uxrg/kernel/image.itb 11331363/tftp-deploy-nz64uxrg/kernel/cmdline
294 15:35:58.338559 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 15:35:58.338686 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 15:35:58.338784 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 15:35:58.338885 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 15:35:58.338960 Not connected, no need to disconnect.
299 15:35:58.339038 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 15:35:58.339124 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 15:35:58.339199 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
302 15:35:58.343528 Setting prompt string to ['lava-test: # ']
303 15:35:58.343947 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 15:35:58.344071 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 15:35:58.344179 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 15:35:58.344444 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 15:35:58.344757 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
308 15:36:03.479450 >> Command sent successfully.
309 15:36:03.481861 Returned 0 in 5 seconds
310 15:36:03.582285 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 15:36:03.582721 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 15:36:03.582862 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 15:36:03.582992 Setting prompt string to 'Starting depthcharge on Spherion...'
315 15:36:03.583114 Changing prompt to 'Starting depthcharge on Spherion...'
316 15:36:03.583217 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 15:36:03.583530 [Enter `^Ec?' for help]
318 15:36:03.755931
319 15:36:03.756076
320 15:36:03.756186 F0: 102B 0000
321 15:36:03.756252
322 15:36:03.756315 F3: 1001 0000 [0200]
323 15:36:03.756376
324 15:36:03.759684 F3: 1001 0000
325 15:36:03.759781
326 15:36:03.759848 F7: 102D 0000
327 15:36:03.759910
328 15:36:03.763600 F1: 0000 0000
329 15:36:03.763677
330 15:36:03.763744 V0: 0000 0000 [0001]
331 15:36:03.763807
332 15:36:03.763866 00: 0007 8000
333 15:36:03.763995
334 15:36:03.766702 01: 0000 0000
335 15:36:03.766788
336 15:36:03.766855 BP: 0C00 0209 [0000]
337 15:36:03.766917
338 15:36:03.770045 G0: 1182 0000
339 15:36:03.770194
340 15:36:03.770293 EC: 0000 0021 [4000]
341 15:36:03.770386
342 15:36:03.773530 S7: 0000 0000 [0000]
343 15:36:03.773625
344 15:36:03.773736 CC: 0000 0000 [0001]
345 15:36:03.773830
346 15:36:03.776699 T0: 0000 0040 [010F]
347 15:36:03.776779
348 15:36:03.776844 Jump to BL
349 15:36:03.776918
350 15:36:03.802606
351 15:36:03.802753
352 15:36:03.802828
353 15:36:03.810052 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 15:36:03.813964 ARM64: Exception handlers installed.
355 15:36:03.817072 ARM64: Testing exception
356 15:36:03.820539 ARM64: Done test exception
357 15:36:03.827713 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 15:36:03.839326 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 15:36:03.845680 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 15:36:03.852859 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 15:36:03.860213 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 15:36:03.870719 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 15:36:03.880197 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 15:36:03.887062 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 15:36:03.905944 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 15:36:03.908981 WDT: Last reset was cold boot
367 15:36:03.912509 SPI1(PAD0) initialized at 2873684 Hz
368 15:36:03.915607 SPI5(PAD0) initialized at 992727 Hz
369 15:36:03.919219 VBOOT: Loading verstage.
370 15:36:03.925851 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 15:36:03.928927 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 15:36:03.932198 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 15:36:03.935920 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 15:36:03.943081 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 15:36:03.950031 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 15:36:03.960482 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
377 15:36:03.960573
378 15:36:03.960640
379 15:36:03.970713 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 15:36:03.974113 ARM64: Exception handlers installed.
381 15:36:03.977493 ARM64: Testing exception
382 15:36:03.977577 ARM64: Done test exception
383 15:36:03.983838 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 15:36:03.987565 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 15:36:04.001534 Probing TPM: . done!
386 15:36:04.001638 TPM ready after 0 ms
387 15:36:04.008318 Connected to device vid:did:rid of 1ae0:0028:00
388 15:36:04.018596 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
389 15:36:04.056618 Initialized TPM device CR50 revision 0
390 15:36:04.068553 tlcl_send_startup: Startup return code is 0
391 15:36:04.068650 TPM: setup succeeded
392 15:36:04.079899 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 15:36:04.088740 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 15:36:04.095395 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 15:36:04.107362 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 15:36:04.110920 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 15:36:04.114284 in-header: 03 07 00 00 08 00 00 00
398 15:36:04.117205 in-data: aa e4 47 04 13 02 00 00
399 15:36:04.120887 Chrome EC: UHEPI supported
400 15:36:04.127244 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 15:36:04.130454 in-header: 03 ad 00 00 08 00 00 00
402 15:36:04.134212 in-data: 00 20 20 08 00 00 00 00
403 15:36:04.134299 Phase 1
404 15:36:04.137291 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 15:36:04.143923 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 15:36:04.150351 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 15:36:04.153777 Recovery requested (1009000e)
408 15:36:04.157799 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 15:36:04.166406 tlcl_extend: response is 0
410 15:36:04.174459 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 15:36:04.179631 tlcl_extend: response is 0
412 15:36:04.186080 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 15:36:04.207079 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 15:36:04.213295 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 15:36:04.213394
416 15:36:04.213461
417 15:36:04.224426 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 15:36:04.227204 ARM64: Exception handlers installed.
419 15:36:04.227326 ARM64: Testing exception
420 15:36:04.231047 ARM64: Done test exception
421 15:36:04.252424 pmic_efuse_setting: Set efuses in 11 msecs
422 15:36:04.255888 pmwrap_interface_init: Select PMIF_VLD_RDY
423 15:36:04.262841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 15:36:04.266119 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 15:36:04.269791 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 15:36:04.276152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 15:36:04.279814 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 15:36:04.286499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 15:36:04.290206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 15:36:04.296919 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 15:36:04.300561 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 15:36:04.303586 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 15:36:04.310130 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 15:36:04.313728 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 15:36:04.316910 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 15:36:04.324134 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 15:36:04.330490 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 15:36:04.336758 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 15:36:04.340250 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 15:36:04.347218 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 15:36:04.353856 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 15:36:04.357457 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 15:36:04.363811 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 15:36:04.370968 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 15:36:04.374877 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 15:36:04.381845 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 15:36:04.385280 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 15:36:04.392345 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 15:36:04.395772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 15:36:04.402329 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 15:36:04.405856 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 15:36:04.409704 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 15:36:04.416458 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 15:36:04.419804 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 15:36:04.426849 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 15:36:04.430359 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 15:36:04.437478 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 15:36:04.440372 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 15:36:04.447002 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 15:36:04.450305 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 15:36:04.457336 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 15:36:04.460996 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 15:36:04.464803 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 15:36:04.468383 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 15:36:04.471953 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 15:36:04.478392 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 15:36:04.481562 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 15:36:04.484828 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 15:36:04.491344 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 15:36:04.494773 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 15:36:04.498379 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 15:36:04.501671 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 15:36:04.508200 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 15:36:04.514314 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 15:36:04.525044 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 15:36:04.528020 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 15:36:04.537932 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 15:36:04.544740 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 15:36:04.548067 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 15:36:04.554379 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 15:36:04.557822 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 15:36:04.564646 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x26
483 15:36:04.571617 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 15:36:04.575462 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
485 15:36:04.581629 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 15:36:04.589251 [RTC]rtc_get_frequency_meter,154: input=15, output=835
487 15:36:04.599028 [RTC]rtc_get_frequency_meter,154: input=7, output=709
488 15:36:04.608366 [RTC]rtc_get_frequency_meter,154: input=11, output=772
489 15:36:04.618227 [RTC]rtc_get_frequency_meter,154: input=13, output=802
490 15:36:04.627561 [RTC]rtc_get_frequency_meter,154: input=12, output=787
491 15:36:04.637173 [RTC]rtc_get_frequency_meter,154: input=12, output=788
492 15:36:04.646422 [RTC]rtc_get_frequency_meter,154: input=13, output=804
493 15:36:04.649944 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
494 15:36:04.656978 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
495 15:36:04.660417 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 15:36:04.663536 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 15:36:04.670274 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 15:36:04.673619 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 15:36:04.676778 ADC[4]: Raw value=903031 ID=7
500 15:36:04.676862 ADC[3]: Raw value=213282 ID=1
501 15:36:04.680677 RAM Code: 0x71
502 15:36:04.683631 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 15:36:04.689970 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 15:36:04.696828 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 15:36:04.703197 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 15:36:04.706753 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 15:36:04.709698 in-header: 03 07 00 00 08 00 00 00
508 15:36:04.713345 in-data: aa e4 47 04 13 02 00 00
509 15:36:04.716787 Chrome EC: UHEPI supported
510 15:36:04.723135 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 15:36:04.726755 in-header: 03 dd 00 00 08 00 00 00
512 15:36:04.729681 in-data: 90 20 60 08 00 00 00 00
513 15:36:04.733231 MRC: failed to locate region type 0.
514 15:36:04.740251 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 15:36:04.743495 DRAM-K: Running full calibration
516 15:36:04.749655 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 15:36:04.749739 header.status = 0x0
518 15:36:04.753071 header.version = 0x6 (expected: 0x6)
519 15:36:04.757053 header.size = 0xd00 (expected: 0xd00)
520 15:36:04.759734 header.flags = 0x0
521 15:36:04.766816 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 15:36:04.783706 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
523 15:36:04.790130 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 15:36:04.793622 dram_init: ddr_geometry: 2
525 15:36:04.796828 [EMI] MDL number = 2
526 15:36:04.796914 [EMI] Get MDL freq = 0
527 15:36:04.800313 dram_init: ddr_type: 0
528 15:36:04.800397 is_discrete_lpddr4: 1
529 15:36:04.803288 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 15:36:04.803369
531 15:36:04.803452
532 15:36:04.806484 [Bian_co] ETT version 0.0.0.1
533 15:36:04.813736 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 15:36:04.813820
535 15:36:04.816622 dramc_set_vcore_voltage set vcore to 650000
536 15:36:04.820139 Read voltage for 800, 4
537 15:36:04.820282 Vio18 = 0
538 15:36:04.820350 Vcore = 650000
539 15:36:04.823129 Vdram = 0
540 15:36:04.823242 Vddq = 0
541 15:36:04.823309 Vmddr = 0
542 15:36:04.826426 dram_init: config_dvfs: 1
543 15:36:04.829812 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 15:36:04.836635 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 15:36:04.839999 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
546 15:36:04.843158 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
547 15:36:04.846455 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
548 15:36:04.849808 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
549 15:36:04.853483 MEM_TYPE=3, freq_sel=18
550 15:36:04.857059 sv_algorithm_assistance_LP4_1600
551 15:36:04.859875 ============ PULL DRAM RESETB DOWN ============
552 15:36:04.866172 ========== PULL DRAM RESETB DOWN end =========
553 15:36:04.869746 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 15:36:04.873063 ===================================
555 15:36:04.876181 LPDDR4 DRAM CONFIGURATION
556 15:36:04.879711 ===================================
557 15:36:04.879788 EX_ROW_EN[0] = 0x0
558 15:36:04.883187 EX_ROW_EN[1] = 0x0
559 15:36:04.883260 LP4Y_EN = 0x0
560 15:36:04.886055 WORK_FSP = 0x0
561 15:36:04.886125 WL = 0x2
562 15:36:04.889566 RL = 0x2
563 15:36:04.889676 BL = 0x2
564 15:36:04.892832 RPST = 0x0
565 15:36:04.892930 RD_PRE = 0x0
566 15:36:04.896147 WR_PRE = 0x1
567 15:36:04.896244 WR_PST = 0x0
568 15:36:04.899492 DBI_WR = 0x0
569 15:36:04.902778 DBI_RD = 0x0
570 15:36:04.902853 OTF = 0x1
571 15:36:04.906029 ===================================
572 15:36:04.909987 ===================================
573 15:36:04.910092 ANA top config
574 15:36:04.912792 ===================================
575 15:36:04.916587 DLL_ASYNC_EN = 0
576 15:36:04.919669 ALL_SLAVE_EN = 1
577 15:36:04.922670 NEW_RANK_MODE = 1
578 15:36:04.926270 DLL_IDLE_MODE = 1
579 15:36:04.926376 LP45_APHY_COMB_EN = 1
580 15:36:04.929732 TX_ODT_DIS = 1
581 15:36:04.932570 NEW_8X_MODE = 1
582 15:36:04.936016 ===================================
583 15:36:04.939045 ===================================
584 15:36:04.942572 data_rate = 1600
585 15:36:04.946018 CKR = 1
586 15:36:04.946121 DQ_P2S_RATIO = 8
587 15:36:04.949440 ===================================
588 15:36:04.952497 CA_P2S_RATIO = 8
589 15:36:04.956149 DQ_CA_OPEN = 0
590 15:36:04.959228 DQ_SEMI_OPEN = 0
591 15:36:04.962621 CA_SEMI_OPEN = 0
592 15:36:04.966316 CA_FULL_RATE = 0
593 15:36:04.966415 DQ_CKDIV4_EN = 1
594 15:36:04.969156 CA_CKDIV4_EN = 1
595 15:36:04.972517 CA_PREDIV_EN = 0
596 15:36:04.975999 PH8_DLY = 0
597 15:36:04.979350 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 15:36:04.982168 DQ_AAMCK_DIV = 4
599 15:36:04.982266 CA_AAMCK_DIV = 4
600 15:36:04.985991 CA_ADMCK_DIV = 4
601 15:36:04.988992 DQ_TRACK_CA_EN = 0
602 15:36:04.992562 CA_PICK = 800
603 15:36:04.996134 CA_MCKIO = 800
604 15:36:04.999042 MCKIO_SEMI = 0
605 15:36:05.002153 PLL_FREQ = 3068
606 15:36:05.002257 DQ_UI_PI_RATIO = 32
607 15:36:05.005412 CA_UI_PI_RATIO = 0
608 15:36:05.008972 ===================================
609 15:36:05.012183 ===================================
610 15:36:05.015580 memory_type:LPDDR4
611 15:36:05.018965 GP_NUM : 10
612 15:36:05.019046 SRAM_EN : 1
613 15:36:05.022393 MD32_EN : 0
614 15:36:05.025745 ===================================
615 15:36:05.029256 [ANA_INIT] >>>>>>>>>>>>>>
616 15:36:05.029359 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 15:36:05.032156 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 15:36:05.035803 ===================================
619 15:36:05.038660 data_rate = 1600,PCW = 0X7600
620 15:36:05.042134 ===================================
621 15:36:05.045330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 15:36:05.051842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 15:36:05.058410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 15:36:05.061989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 15:36:05.065385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 15:36:05.068347 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 15:36:05.071940 [ANA_INIT] flow start
628 15:36:05.072044 [ANA_INIT] PLL >>>>>>>>
629 15:36:05.074823 [ANA_INIT] PLL <<<<<<<<
630 15:36:05.078301 [ANA_INIT] MIDPI >>>>>>>>
631 15:36:05.082053 [ANA_INIT] MIDPI <<<<<<<<
632 15:36:05.082130 [ANA_INIT] DLL >>>>>>>>
633 15:36:05.084883 [ANA_INIT] flow end
634 15:36:05.088335 ============ LP4 DIFF to SE enter ============
635 15:36:05.091835 ============ LP4 DIFF to SE exit ============
636 15:36:05.095092 [ANA_INIT] <<<<<<<<<<<<<
637 15:36:05.098326 [Flow] Enable top DCM control >>>>>
638 15:36:05.101567 [Flow] Enable top DCM control <<<<<
639 15:36:05.104910 Enable DLL master slave shuffle
640 15:36:05.111295 ==============================================================
641 15:36:05.111375 Gating Mode config
642 15:36:05.118400 ==============================================================
643 15:36:05.118504 Config description:
644 15:36:05.128175 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 15:36:05.134862 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 15:36:05.141347 SELPH_MODE 0: By rank 1: By Phase
647 15:36:05.144317 ==============================================================
648 15:36:05.147845 GAT_TRACK_EN = 1
649 15:36:05.151392 RX_GATING_MODE = 2
650 15:36:05.154171 RX_GATING_TRACK_MODE = 2
651 15:36:05.157650 SELPH_MODE = 1
652 15:36:05.161079 PICG_EARLY_EN = 1
653 15:36:05.164649 VALID_LAT_VALUE = 1
654 15:36:05.167694 ==============================================================
655 15:36:05.174205 Enter into Gating configuration >>>>
656 15:36:05.174314 Exit from Gating configuration <<<<
657 15:36:05.177711 Enter into DVFS_PRE_config >>>>>
658 15:36:05.191148 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 15:36:05.194501 Exit from DVFS_PRE_config <<<<<
660 15:36:05.197360 Enter into PICG configuration >>>>
661 15:36:05.200929 Exit from PICG configuration <<<<
662 15:36:05.201012 [RX_INPUT] configuration >>>>>
663 15:36:05.204469 [RX_INPUT] configuration <<<<<
664 15:36:05.211085 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 15:36:05.214510 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 15:36:05.221581 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 15:36:05.228905 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 15:36:05.232809 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 15:36:05.240439 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 15:36:05.243842 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 15:36:05.247202 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 15:36:05.253622 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 15:36:05.257253 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 15:36:05.260292 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 15:36:05.264223 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 15:36:05.267999 ===================================
677 15:36:05.271625 LPDDR4 DRAM CONFIGURATION
678 15:36:05.275159 ===================================
679 15:36:05.275243 EX_ROW_EN[0] = 0x0
680 15:36:05.278703 EX_ROW_EN[1] = 0x0
681 15:36:05.278786 LP4Y_EN = 0x0
682 15:36:05.282187 WORK_FSP = 0x0
683 15:36:05.282288 WL = 0x2
684 15:36:05.286209 RL = 0x2
685 15:36:05.286322 BL = 0x2
686 15:36:05.289867 RPST = 0x0
687 15:36:05.289954 RD_PRE = 0x0
688 15:36:05.293282 WR_PRE = 0x1
689 15:36:05.293365 WR_PST = 0x0
690 15:36:05.296806 DBI_WR = 0x0
691 15:36:05.296889 DBI_RD = 0x0
692 15:36:05.300903 OTF = 0x1
693 15:36:05.300986 ===================================
694 15:36:05.304474 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 15:36:05.311619 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 15:36:05.315046 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 15:36:05.318778 ===================================
698 15:36:05.322522 LPDDR4 DRAM CONFIGURATION
699 15:36:05.322656 ===================================
700 15:36:05.325880 EX_ROW_EN[0] = 0x10
701 15:36:05.329675 EX_ROW_EN[1] = 0x0
702 15:36:05.329752 LP4Y_EN = 0x0
703 15:36:05.329816 WORK_FSP = 0x0
704 15:36:05.333476 WL = 0x2
705 15:36:05.333575 RL = 0x2
706 15:36:05.336685 BL = 0x2
707 15:36:05.336763 RPST = 0x0
708 15:36:05.340885 RD_PRE = 0x0
709 15:36:05.340969 WR_PRE = 0x1
710 15:36:05.344775 WR_PST = 0x0
711 15:36:05.344876 DBI_WR = 0x0
712 15:36:05.348146 DBI_RD = 0x0
713 15:36:05.348218 OTF = 0x1
714 15:36:05.351910 ===================================
715 15:36:05.359260 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 15:36:05.362627 nWR fixed to 40
717 15:36:05.362706 [ModeRegInit_LP4] CH0 RK0
718 15:36:05.366555 [ModeRegInit_LP4] CH0 RK1
719 15:36:05.370400 [ModeRegInit_LP4] CH1 RK0
720 15:36:05.370483 [ModeRegInit_LP4] CH1 RK1
721 15:36:05.374066 match AC timing 13
722 15:36:05.377601 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 15:36:05.380994 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 15:36:05.384565 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 15:36:05.391334 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 15:36:05.394970 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 15:36:05.398451 [EMI DOE] emi_dcm 0
728 15:36:05.401413 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 15:36:05.401514 ==
730 15:36:05.405001 Dram Type= 6, Freq= 0, CH_0, rank 0
731 15:36:05.408046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 15:36:05.408118 ==
733 15:36:05.412870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 15:36:05.419222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 15:36:05.429287 [CA 0] Center 37 (6~68) winsize 63
736 15:36:05.432529 [CA 1] Center 37 (7~68) winsize 62
737 15:36:05.435971 [CA 2] Center 34 (4~65) winsize 62
738 15:36:05.439304 [CA 3] Center 34 (4~65) winsize 62
739 15:36:05.442833 [CA 4] Center 34 (4~64) winsize 61
740 15:36:05.446444 [CA 5] Center 33 (3~64) winsize 62
741 15:36:05.446548
742 15:36:05.449478 [CmdBusTrainingLP45] Vref(ca) range 1: 32
743 15:36:05.449614
744 15:36:05.452995 [CATrainingPosCal] consider 1 rank data
745 15:36:05.456389 u2DelayCellTimex100 = 270/100 ps
746 15:36:05.460085 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
747 15:36:05.463065 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
748 15:36:05.466806 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
749 15:36:05.469801 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
750 15:36:05.476340 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
751 15:36:05.479578 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 15:36:05.479656
753 15:36:05.482858 CA PerBit enable=1, Macro0, CA PI delay=33
754 15:36:05.482967
755 15:36:05.486288 [CBTSetCACLKResult] CA Dly = 33
756 15:36:05.486387 CS Dly: 7 (0~38)
757 15:36:05.486481 ==
758 15:36:05.489856 Dram Type= 6, Freq= 0, CH_0, rank 1
759 15:36:05.496568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 15:36:05.496649 ==
761 15:36:05.499703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 15:36:05.506503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 15:36:05.515376 [CA 0] Center 37 (6~68) winsize 63
764 15:36:05.518861 [CA 1] Center 37 (7~68) winsize 62
765 15:36:05.521766 [CA 2] Center 34 (4~65) winsize 62
766 15:36:05.525255 [CA 3] Center 34 (4~65) winsize 62
767 15:36:05.528654 [CA 4] Center 33 (3~64) winsize 62
768 15:36:05.532226 [CA 5] Center 33 (2~64) winsize 63
769 15:36:05.532305
770 15:36:05.535395 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 15:36:05.535497
772 15:36:05.538897 [CATrainingPosCal] consider 2 rank data
773 15:36:05.541785 u2DelayCellTimex100 = 270/100 ps
774 15:36:05.545459 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
775 15:36:05.551746 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 15:36:05.555250 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
777 15:36:05.558561 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
778 15:36:05.562466 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
779 15:36:05.565882 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 15:36:05.565960
781 15:36:05.569741 CA PerBit enable=1, Macro0, CA PI delay=33
782 15:36:05.569816
783 15:36:05.573346 [CBTSetCACLKResult] CA Dly = 33
784 15:36:05.573457 CS Dly: 7 (0~39)
785 15:36:05.573551
786 15:36:05.577480 ----->DramcWriteLeveling(PI) begin...
787 15:36:05.577593 ==
788 15:36:05.580676 Dram Type= 6, Freq= 0, CH_0, rank 0
789 15:36:05.584436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 15:36:05.584538 ==
791 15:36:05.587951 Write leveling (Byte 0): 32 => 32
792 15:36:05.591790 Write leveling (Byte 1): 28 => 28
793 15:36:05.594778 DramcWriteLeveling(PI) end<-----
794 15:36:05.594856
795 15:36:05.594919 ==
796 15:36:05.598523 Dram Type= 6, Freq= 0, CH_0, rank 0
797 15:36:05.601516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 15:36:05.601590 ==
799 15:36:05.604975 [Gating] SW mode calibration
800 15:36:05.611478 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 15:36:05.618520 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 15:36:05.621431 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 15:36:05.624990 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
804 15:36:05.631605 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 15:36:05.634806 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 15:36:05.638142 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 15:36:05.641457 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 15:36:05.648134 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 15:36:05.651418 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 15:36:05.657989 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 15:36:05.661121 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 15:36:05.664693 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 15:36:05.667775 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 15:36:05.674644 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 15:36:05.677842 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 15:36:05.681148 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 15:36:05.687652 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 15:36:05.690953 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 15:36:05.694432 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 15:36:05.700843 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
821 15:36:05.704408 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 15:36:05.707482 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 15:36:05.714137 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 15:36:05.718033 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 15:36:05.721218 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 15:36:05.727640 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 15:36:05.730649 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 15:36:05.734385 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
829 15:36:05.740921 0 9 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
830 15:36:05.743966 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 15:36:05.747199 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 15:36:05.753750 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 15:36:05.757366 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 15:36:05.760812 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 15:36:05.767437 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
836 15:36:05.770386 0 10 8 | B1->B0 | 3333 2a2a | 0 1 | (0 0) (1 0)
837 15:36:05.773728 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
838 15:36:05.780682 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 15:36:05.784245 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 15:36:05.786865 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 15:36:05.794020 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 15:36:05.797196 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 15:36:05.800374 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
844 15:36:05.806981 0 11 8 | B1->B0 | 2424 3838 | 0 1 | (0 0) (0 0)
845 15:36:05.810093 0 11 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
846 15:36:05.813404 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 15:36:05.820183 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 15:36:05.823664 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 15:36:05.827027 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 15:36:05.833657 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 15:36:05.836680 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 15:36:05.840037 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
853 15:36:05.846824 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 15:36:05.850233 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 15:36:05.853709 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 15:36:05.856601 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 15:36:05.863493 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 15:36:05.866532 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 15:36:05.870025 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 15:36:05.876497 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 15:36:05.880091 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 15:36:05.883239 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 15:36:05.889972 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 15:36:05.893060 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 15:36:05.896511 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 15:36:05.903410 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 15:36:05.906545 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 15:36:05.909528 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
869 15:36:05.916299 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
870 15:36:05.919785 Total UI for P1: 0, mck2ui 16
871 15:36:05.923345 best dqsien dly found for B0: ( 0, 14, 8)
872 15:36:05.926866 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 15:36:05.929620 Total UI for P1: 0, mck2ui 16
874 15:36:05.933236 best dqsien dly found for B1: ( 0, 14, 10)
875 15:36:05.936569 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
876 15:36:05.939752 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
877 15:36:05.939845
878 15:36:05.943143 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
879 15:36:05.946359 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
880 15:36:05.950020 [Gating] SW calibration Done
881 15:36:05.950102 ==
882 15:36:05.953542 Dram Type= 6, Freq= 0, CH_0, rank 0
883 15:36:05.957076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
884 15:36:05.957182 ==
885 15:36:05.960129 RX Vref Scan: 0
886 15:36:05.960206
887 15:36:05.963568 RX Vref 0 -> 0, step: 1
888 15:36:05.963668
889 15:36:05.963768 RX Delay -130 -> 252, step: 16
890 15:36:05.970192 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
891 15:36:05.973523 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
892 15:36:05.976509 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
893 15:36:05.980097 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
894 15:36:05.986755 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
895 15:36:05.990318 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
896 15:36:05.993079 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
897 15:36:05.996494 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
898 15:36:06.000122 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
899 15:36:06.003300 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
900 15:36:06.009642 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
901 15:36:06.013210 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
902 15:36:06.016863 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
903 15:36:06.020528 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
904 15:36:06.024262 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
905 15:36:06.027644 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
906 15:36:06.031315 ==
907 15:36:06.031396 Dram Type= 6, Freq= 0, CH_0, rank 0
908 15:36:06.038488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
909 15:36:06.038604 ==
910 15:36:06.038673 DQS Delay:
911 15:36:06.041990 DQS0 = 0, DQS1 = 0
912 15:36:06.042063 DQM Delay:
913 15:36:06.042123 DQM0 = 86, DQM1 = 73
914 15:36:06.044934 DQ Delay:
915 15:36:06.045042 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
916 15:36:06.049170 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
917 15:36:06.051889 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
918 15:36:06.055611 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
919 15:36:06.055693
920 15:36:06.055761
921 15:36:06.055820 ==
922 15:36:06.059319 Dram Type= 6, Freq= 0, CH_0, rank 0
923 15:36:06.063473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
924 15:36:06.067166 ==
925 15:36:06.067247
926 15:36:06.067341
927 15:36:06.067453 TX Vref Scan disable
928 15:36:06.070793 == TX Byte 0 ==
929 15:36:06.074399 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
930 15:36:06.078337 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
931 15:36:06.078444 == TX Byte 1 ==
932 15:36:06.084869 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
933 15:36:06.088219 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
934 15:36:06.088290 ==
935 15:36:06.091108 Dram Type= 6, Freq= 0, CH_0, rank 0
936 15:36:06.094519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 15:36:06.094651 ==
938 15:36:06.108936 TX Vref=22, minBit 4, minWin=27, winSum=441
939 15:36:06.112434 TX Vref=24, minBit 8, minWin=27, winSum=443
940 15:36:06.115523 TX Vref=26, minBit 8, minWin=27, winSum=447
941 15:36:06.118549 TX Vref=28, minBit 8, minWin=27, winSum=446
942 15:36:06.122366 TX Vref=30, minBit 11, minWin=26, winSum=442
943 15:36:06.128931 TX Vref=32, minBit 8, minWin=27, winSum=443
944 15:36:06.132124 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 26
945 15:36:06.132205
946 15:36:06.136073 Final TX Range 1 Vref 26
947 15:36:06.136153
948 15:36:06.136218 ==
949 15:36:06.139549 Dram Type= 6, Freq= 0, CH_0, rank 0
950 15:36:06.143143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 15:36:06.143222 ==
952 15:36:06.143285
953 15:36:06.143345
954 15:36:06.146749 TX Vref Scan disable
955 15:36:06.150207 == TX Byte 0 ==
956 15:36:06.153818 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
957 15:36:06.157306 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
958 15:36:06.160202 == TX Byte 1 ==
959 15:36:06.163617 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
960 15:36:06.167130 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
961 15:36:06.167203
962 15:36:06.167265 [DATLAT]
963 15:36:06.170472 Freq=800, CH0 RK0
964 15:36:06.170617
965 15:36:06.170683 DATLAT Default: 0xa
966 15:36:06.173485 0, 0xFFFF, sum = 0
967 15:36:06.176919 1, 0xFFFF, sum = 0
968 15:36:06.176996 2, 0xFFFF, sum = 0
969 15:36:06.180524 3, 0xFFFF, sum = 0
970 15:36:06.180630 4, 0xFFFF, sum = 0
971 15:36:06.184043 5, 0xFFFF, sum = 0
972 15:36:06.184115 6, 0xFFFF, sum = 0
973 15:36:06.187242 7, 0xFFFF, sum = 0
974 15:36:06.187316 8, 0xFFFF, sum = 0
975 15:36:06.190238 9, 0x0, sum = 1
976 15:36:06.190311 10, 0x0, sum = 2
977 15:36:06.193914 11, 0x0, sum = 3
978 15:36:06.193982 12, 0x0, sum = 4
979 15:36:06.194043 best_step = 10
980 15:36:06.194100
981 15:36:06.196847 ==
982 15:36:06.200237 Dram Type= 6, Freq= 0, CH_0, rank 0
983 15:36:06.203884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 15:36:06.203954 ==
985 15:36:06.204015 RX Vref Scan: 1
986 15:36:06.204072
987 15:36:06.206869 Set Vref Range= 32 -> 127
988 15:36:06.206934
989 15:36:06.210293 RX Vref 32 -> 127, step: 1
990 15:36:06.210357
991 15:36:06.213578 RX Delay -95 -> 252, step: 8
992 15:36:06.213646
993 15:36:06.217041 Set Vref, RX VrefLevel [Byte0]: 32
994 15:36:06.220018 [Byte1]: 32
995 15:36:06.220085
996 15:36:06.223103 Set Vref, RX VrefLevel [Byte0]: 33
997 15:36:06.226624 [Byte1]: 33
998 15:36:06.226697
999 15:36:06.230227 Set Vref, RX VrefLevel [Byte0]: 34
1000 15:36:06.233290 [Byte1]: 34
1001 15:36:06.236938
1002 15:36:06.237017 Set Vref, RX VrefLevel [Byte0]: 35
1003 15:36:06.240233 [Byte1]: 35
1004 15:36:06.244661
1005 15:36:06.248187 Set Vref, RX VrefLevel [Byte0]: 36
1006 15:36:06.248263 [Byte1]: 36
1007 15:36:06.252378
1008 15:36:06.252490 Set Vref, RX VrefLevel [Byte0]: 37
1009 15:36:06.255795 [Byte1]: 37
1010 15:36:06.259829
1011 15:36:06.259902 Set Vref, RX VrefLevel [Byte0]: 38
1012 15:36:06.263178 [Byte1]: 38
1013 15:36:06.267291
1014 15:36:06.267362 Set Vref, RX VrefLevel [Byte0]: 39
1015 15:36:06.270463 [Byte1]: 39
1016 15:36:06.275263
1017 15:36:06.275340 Set Vref, RX VrefLevel [Byte0]: 40
1018 15:36:06.278320 [Byte1]: 40
1019 15:36:06.282694
1020 15:36:06.282777 Set Vref, RX VrefLevel [Byte0]: 41
1021 15:36:06.285888 [Byte1]: 41
1022 15:36:06.290391
1023 15:36:06.290459 Set Vref, RX VrefLevel [Byte0]: 42
1024 15:36:06.293904 [Byte1]: 42
1025 15:36:06.297609
1026 15:36:06.297682 Set Vref, RX VrefLevel [Byte0]: 43
1027 15:36:06.301079 [Byte1]: 43
1028 15:36:06.305057
1029 15:36:06.305146 Set Vref, RX VrefLevel [Byte0]: 44
1030 15:36:06.308539 [Byte1]: 44
1031 15:36:06.312720
1032 15:36:06.312795 Set Vref, RX VrefLevel [Byte0]: 45
1033 15:36:06.316490 [Byte1]: 45
1034 15:36:06.320653
1035 15:36:06.320740 Set Vref, RX VrefLevel [Byte0]: 46
1036 15:36:06.323434 [Byte1]: 46
1037 15:36:06.328109
1038 15:36:06.328193 Set Vref, RX VrefLevel [Byte0]: 47
1039 15:36:06.331445 [Byte1]: 47
1040 15:36:06.335563
1041 15:36:06.335662 Set Vref, RX VrefLevel [Byte0]: 48
1042 15:36:06.339004 [Byte1]: 48
1043 15:36:06.343020
1044 15:36:06.343093 Set Vref, RX VrefLevel [Byte0]: 49
1045 15:36:06.346495 [Byte1]: 49
1046 15:36:06.350587
1047 15:36:06.350703 Set Vref, RX VrefLevel [Byte0]: 50
1048 15:36:06.354655 [Byte1]: 50
1049 15:36:06.358513
1050 15:36:06.358612 Set Vref, RX VrefLevel [Byte0]: 51
1051 15:36:06.364912 [Byte1]: 51
1052 15:36:06.364993
1053 15:36:06.368866 Set Vref, RX VrefLevel [Byte0]: 52
1054 15:36:06.372335 [Byte1]: 52
1055 15:36:06.372410
1056 15:36:06.375805 Set Vref, RX VrefLevel [Byte0]: 53
1057 15:36:06.379343 [Byte1]: 53
1058 15:36:06.379431
1059 15:36:06.382865 Set Vref, RX VrefLevel [Byte0]: 54
1060 15:36:06.386264 [Byte1]: 54
1061 15:36:06.386340
1062 15:36:06.390016 Set Vref, RX VrefLevel [Byte0]: 55
1063 15:36:06.393468 [Byte1]: 55
1064 15:36:06.393543
1065 15:36:06.397539 Set Vref, RX VrefLevel [Byte0]: 56
1066 15:36:06.400967 [Byte1]: 56
1067 15:36:06.404238
1068 15:36:06.404322 Set Vref, RX VrefLevel [Byte0]: 57
1069 15:36:06.407374 [Byte1]: 57
1070 15:36:06.411816
1071 15:36:06.411896 Set Vref, RX VrefLevel [Byte0]: 58
1072 15:36:06.415353 [Byte1]: 58
1073 15:36:06.419113
1074 15:36:06.419188 Set Vref, RX VrefLevel [Byte0]: 59
1075 15:36:06.422710 [Byte1]: 59
1076 15:36:06.426641
1077 15:36:06.430247 Set Vref, RX VrefLevel [Byte0]: 60
1078 15:36:06.430348 [Byte1]: 60
1079 15:36:06.434799
1080 15:36:06.434875 Set Vref, RX VrefLevel [Byte0]: 61
1081 15:36:06.438475 [Byte1]: 61
1082 15:36:06.442106
1083 15:36:06.442204 Set Vref, RX VrefLevel [Byte0]: 62
1084 15:36:06.445301 [Byte1]: 62
1085 15:36:06.450148
1086 15:36:06.450245 Set Vref, RX VrefLevel [Byte0]: 63
1087 15:36:06.453421 [Byte1]: 63
1088 15:36:06.457577
1089 15:36:06.457649 Set Vref, RX VrefLevel [Byte0]: 64
1090 15:36:06.460972 [Byte1]: 64
1091 15:36:06.465433
1092 15:36:06.465536 Set Vref, RX VrefLevel [Byte0]: 65
1093 15:36:06.468311 [Byte1]: 65
1094 15:36:06.472730
1095 15:36:06.472835 Set Vref, RX VrefLevel [Byte0]: 66
1096 15:36:06.476115 [Byte1]: 66
1097 15:36:06.480446
1098 15:36:06.480553 Set Vref, RX VrefLevel [Byte0]: 67
1099 15:36:06.483841 [Byte1]: 67
1100 15:36:06.487912
1101 15:36:06.487983 Set Vref, RX VrefLevel [Byte0]: 68
1102 15:36:06.491261 [Byte1]: 68
1103 15:36:06.495211
1104 15:36:06.495285 Set Vref, RX VrefLevel [Byte0]: 69
1105 15:36:06.498731 [Byte1]: 69
1106 15:36:06.502991
1107 15:36:06.503063 Set Vref, RX VrefLevel [Byte0]: 70
1108 15:36:06.506325 [Byte1]: 70
1109 15:36:06.510021
1110 15:36:06.513925 Set Vref, RX VrefLevel [Byte0]: 71
1111 15:36:06.514000 [Byte1]: 71
1112 15:36:06.518302
1113 15:36:06.518383 Set Vref, RX VrefLevel [Byte0]: 72
1114 15:36:06.521764 [Byte1]: 72
1115 15:36:06.526013
1116 15:36:06.526085 Set Vref, RX VrefLevel [Byte0]: 73
1117 15:36:06.529380 [Byte1]: 73
1118 15:36:06.533631
1119 15:36:06.533705 Set Vref, RX VrefLevel [Byte0]: 74
1120 15:36:06.536547 [Byte1]: 74
1121 15:36:06.541412
1122 15:36:06.541486 Set Vref, RX VrefLevel [Byte0]: 75
1123 15:36:06.544334 [Byte1]: 75
1124 15:36:06.548391
1125 15:36:06.548464 Set Vref, RX VrefLevel [Byte0]: 76
1126 15:36:06.551937 [Byte1]: 76
1127 15:36:06.556227
1128 15:36:06.556305 Set Vref, RX VrefLevel [Byte0]: 77
1129 15:36:06.559658 [Byte1]: 77
1130 15:36:06.563879
1131 15:36:06.563968 Set Vref, RX VrefLevel [Byte0]: 78
1132 15:36:06.567103 [Byte1]: 78
1133 15:36:06.571662
1134 15:36:06.571745 Set Vref, RX VrefLevel [Byte0]: 79
1135 15:36:06.574995 [Byte1]: 79
1136 15:36:06.578985
1137 15:36:06.579061 Set Vref, RX VrefLevel [Byte0]: 80
1138 15:36:06.582007 [Byte1]: 80
1139 15:36:06.586223
1140 15:36:06.586321 Set Vref, RX VrefLevel [Byte0]: 81
1141 15:36:06.589707 [Byte1]: 81
1142 15:36:06.594358
1143 15:36:06.594460 Set Vref, RX VrefLevel [Byte0]: 82
1144 15:36:06.597554 [Byte1]: 82
1145 15:36:06.601769
1146 15:36:06.601873 Set Vref, RX VrefLevel [Byte0]: 83
1147 15:36:06.604862 [Byte1]: 83
1148 15:36:06.609444
1149 15:36:06.609513 Set Vref, RX VrefLevel [Byte0]: 84
1150 15:36:06.613175 [Byte1]: 84
1151 15:36:06.616938
1152 15:36:06.620180 Set Vref, RX VrefLevel [Byte0]: 85
1153 15:36:06.623389 [Byte1]: 85
1154 15:36:06.623486
1155 15:36:06.626438 Final RX Vref Byte 0 = 61 to rank0
1156 15:36:06.630381 Final RX Vref Byte 1 = 58 to rank0
1157 15:36:06.633678 Final RX Vref Byte 0 = 61 to rank1
1158 15:36:06.633760 Final RX Vref Byte 1 = 58 to rank1==
1159 15:36:06.637220 Dram Type= 6, Freq= 0, CH_0, rank 0
1160 15:36:06.640995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1161 15:36:06.644347 ==
1162 15:36:06.644419 DQS Delay:
1163 15:36:06.644483 DQS0 = 0, DQS1 = 0
1164 15:36:06.647957 DQM Delay:
1165 15:36:06.648042 DQM0 = 87, DQM1 = 75
1166 15:36:06.648104 DQ Delay:
1167 15:36:06.652100 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1168 15:36:06.655700 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1169 15:36:06.659199 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1170 15:36:06.662567 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1171 15:36:06.662687
1172 15:36:06.662750
1173 15:36:06.670209 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a2c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
1174 15:36:06.673632 CH0 RK0: MR19=606, MR18=4A2C
1175 15:36:06.721285 CH0_RK0: MR19=0x606, MR18=0x4A2C, DQSOSC=391, MR23=63, INC=96, DEC=64
1176 15:36:06.721402
1177 15:36:06.721491 ----->DramcWriteLeveling(PI) begin...
1178 15:36:06.721554 ==
1179 15:36:06.721803 Dram Type= 6, Freq= 0, CH_0, rank 1
1180 15:36:06.721870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 15:36:06.721928 ==
1182 15:36:06.721985 Write leveling (Byte 0): 35 => 35
1183 15:36:06.722040 Write leveling (Byte 1): 31 => 31
1184 15:36:06.722095 DramcWriteLeveling(PI) end<-----
1185 15:36:06.722149
1186 15:36:06.722202 ==
1187 15:36:06.722817 Dram Type= 6, Freq= 0, CH_0, rank 1
1188 15:36:06.723072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 15:36:06.723165 ==
1190 15:36:06.723250 [Gating] SW mode calibration
1191 15:36:06.723540 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1192 15:36:06.765414 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1193 15:36:06.765506 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1194 15:36:06.766013 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1195 15:36:06.766868 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1196 15:36:06.767116 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1197 15:36:06.767180 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 15:36:06.767790 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 15:36:06.768069 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 15:36:06.768315 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 15:36:06.768806 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 15:36:06.768871 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 15:36:06.809877 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 15:36:06.810153 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 15:36:06.810224 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 15:36:06.810482 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 15:36:06.810548 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 15:36:06.811137 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 15:36:06.811421 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 15:36:06.811701 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1211 15:36:06.812243 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1212 15:36:06.812309 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1213 15:36:06.838833 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 15:36:06.839460 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 15:36:06.840051 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 15:36:06.840378 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 15:36:06.840473 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 15:36:06.840751 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 15:36:06.843540 0 9 8 | B1->B0 | 2322 2f2f | 1 1 | (0 0) (0 0)
1220 15:36:06.846825 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1221 15:36:06.850294 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 15:36:06.854039 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 15:36:06.860180 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 15:36:06.863593 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 15:36:06.866734 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1226 15:36:06.873165 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1227 15:36:06.876744 0 10 8 | B1->B0 | 3232 2d2d | 1 1 | (0 0) (0 1)
1228 15:36:06.880222 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1229 15:36:06.886490 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 15:36:06.889952 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 15:36:06.893325 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 15:36:06.899921 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 15:36:06.902915 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 15:36:06.906484 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 15:36:06.913037 0 11 8 | B1->B0 | 2e2e 3d3d | 0 0 | (0 0) (0 0)
1236 15:36:06.916011 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1237 15:36:06.919487 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 15:36:06.926116 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 15:36:06.929603 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 15:36:06.933218 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 15:36:06.939765 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 15:36:06.942697 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1243 15:36:06.946216 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1244 15:36:06.952411 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1245 15:36:06.955899 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 15:36:06.959153 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 15:36:06.965800 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 15:36:06.969315 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 15:36:06.972325 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 15:36:06.979514 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 15:36:06.982405 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 15:36:06.985840 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 15:36:06.992560 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 15:36:06.995849 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 15:36:06.998716 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 15:36:07.005409 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 15:36:07.008491 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 15:36:07.012296 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 15:36:07.018709 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1260 15:36:07.018811 Total UI for P1: 0, mck2ui 16
1261 15:36:07.025026 best dqsien dly found for B0: ( 0, 14, 6)
1262 15:36:07.028321 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 15:36:07.032024 Total UI for P1: 0, mck2ui 16
1264 15:36:07.034978 best dqsien dly found for B1: ( 0, 14, 8)
1265 15:36:07.038496 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1266 15:36:07.041625 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1267 15:36:07.041695
1268 15:36:07.045371 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1269 15:36:07.048202 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1270 15:36:07.051860 [Gating] SW calibration Done
1271 15:36:07.051968 ==
1272 15:36:07.055048 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 15:36:07.058355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 15:36:07.061792 ==
1275 15:36:07.061863 RX Vref Scan: 0
1276 15:36:07.061924
1277 15:36:07.064762 RX Vref 0 -> 0, step: 1
1278 15:36:07.064837
1279 15:36:07.068245 RX Delay -130 -> 252, step: 16
1280 15:36:07.071432 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1281 15:36:07.075053 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1282 15:36:07.078002 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1283 15:36:07.081483 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1284 15:36:07.088219 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1285 15:36:07.091182 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1286 15:36:07.094601 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1287 15:36:07.098058 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1288 15:36:07.101241 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1289 15:36:07.107800 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1290 15:36:07.111153 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1291 15:36:07.114565 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1292 15:36:07.117616 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1293 15:36:07.124589 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1294 15:36:07.127741 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1295 15:36:07.130863 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1296 15:36:07.130958 ==
1297 15:36:07.134231 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 15:36:07.137500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 15:36:07.137572 ==
1300 15:36:07.141079 DQS Delay:
1301 15:36:07.141147 DQS0 = 0, DQS1 = 0
1302 15:36:07.144027 DQM Delay:
1303 15:36:07.144093 DQM0 = 83, DQM1 = 76
1304 15:36:07.144164 DQ Delay:
1305 15:36:07.147626 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1306 15:36:07.151211 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1307 15:36:07.154352 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1308 15:36:07.157595 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1309 15:36:07.157689
1310 15:36:07.157775
1311 15:36:07.161037 ==
1312 15:36:07.161106 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 15:36:07.167399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 15:36:07.167477 ==
1315 15:36:07.167543
1316 15:36:07.167603
1317 15:36:07.167659 TX Vref Scan disable
1318 15:36:07.171412 == TX Byte 0 ==
1319 15:36:07.174782 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1320 15:36:07.181567 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1321 15:36:07.181640 == TX Byte 1 ==
1322 15:36:07.184561 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1323 15:36:07.191042 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1324 15:36:07.191111 ==
1325 15:36:07.194515 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 15:36:07.198130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 15:36:07.198197 ==
1328 15:36:07.210939 TX Vref=22, minBit 2, minWin=27, winSum=443
1329 15:36:07.214391 TX Vref=24, minBit 3, minWin=27, winSum=444
1330 15:36:07.217416 TX Vref=26, minBit 5, minWin=27, winSum=443
1331 15:36:07.220837 TX Vref=28, minBit 9, minWin=27, winSum=444
1332 15:36:07.223834 TX Vref=30, minBit 7, minWin=27, winSum=442
1333 15:36:07.230669 TX Vref=32, minBit 4, minWin=27, winSum=440
1334 15:36:07.234071 [TxChooseVref] Worse bit 3, Min win 27, Win sum 444, Final Vref 24
1335 15:36:07.234149
1336 15:36:07.237157 Final TX Range 1 Vref 24
1337 15:36:07.237238
1338 15:36:07.237301 ==
1339 15:36:07.240355 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 15:36:07.243486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 15:36:07.247176 ==
1342 15:36:07.247245
1343 15:36:07.247304
1344 15:36:07.247359 TX Vref Scan disable
1345 15:36:07.250660 == TX Byte 0 ==
1346 15:36:07.253975 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1347 15:36:07.260708 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1348 15:36:07.260782 == TX Byte 1 ==
1349 15:36:07.264059 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1350 15:36:07.270807 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1351 15:36:07.270894
1352 15:36:07.270957 [DATLAT]
1353 15:36:07.271017 Freq=800, CH0 RK1
1354 15:36:07.271075
1355 15:36:07.274097 DATLAT Default: 0xa
1356 15:36:07.274178 0, 0xFFFF, sum = 0
1357 15:36:07.277167 1, 0xFFFF, sum = 0
1358 15:36:07.277250 2, 0xFFFF, sum = 0
1359 15:36:07.280777 3, 0xFFFF, sum = 0
1360 15:36:07.284002 4, 0xFFFF, sum = 0
1361 15:36:07.284091 5, 0xFFFF, sum = 0
1362 15:36:07.286971 6, 0xFFFF, sum = 0
1363 15:36:07.287053 7, 0xFFFF, sum = 0
1364 15:36:07.290719 8, 0xFFFF, sum = 0
1365 15:36:07.290801 9, 0x0, sum = 1
1366 15:36:07.293974 10, 0x0, sum = 2
1367 15:36:07.294055 11, 0x0, sum = 3
1368 15:36:07.294121 12, 0x0, sum = 4
1369 15:36:07.297289 best_step = 10
1370 15:36:07.297370
1371 15:36:07.297433 ==
1372 15:36:07.300618 Dram Type= 6, Freq= 0, CH_0, rank 1
1373 15:36:07.303890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 15:36:07.303971 ==
1375 15:36:07.307312 RX Vref Scan: 0
1376 15:36:07.307392
1377 15:36:07.307471 RX Vref 0 -> 0, step: 1
1378 15:36:07.310536
1379 15:36:07.310654 RX Delay -111 -> 252, step: 8
1380 15:36:07.317409 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1381 15:36:07.321116 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1382 15:36:07.324544 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1383 15:36:07.327454 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1384 15:36:07.331039 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1385 15:36:07.337219 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1386 15:36:07.340495 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1387 15:36:07.344218 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1388 15:36:07.347232 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1389 15:36:07.350787 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1390 15:36:07.357621 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1391 15:36:07.360633 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1392 15:36:07.363988 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1393 15:36:07.367632 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1394 15:36:07.374476 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1395 15:36:07.377667 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1396 15:36:07.377750 ==
1397 15:36:07.381092 Dram Type= 6, Freq= 0, CH_0, rank 1
1398 15:36:07.384478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 15:36:07.384562 ==
1400 15:36:07.384627 DQS Delay:
1401 15:36:07.387574 DQS0 = 0, DQS1 = 0
1402 15:36:07.387655 DQM Delay:
1403 15:36:07.390801 DQM0 = 85, DQM1 = 76
1404 15:36:07.390882 DQ Delay:
1405 15:36:07.394015 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1406 15:36:07.397330 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1407 15:36:07.401046 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1408 15:36:07.403974 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1409 15:36:07.404057
1410 15:36:07.404122
1411 15:36:07.414192 [DQSOSCAuto] RK1, (LSB)MR18= 0x460c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
1412 15:36:07.414275 CH0 RK1: MR19=606, MR18=460C
1413 15:36:07.420806 CH0_RK1: MR19=0x606, MR18=0x460C, DQSOSC=392, MR23=63, INC=96, DEC=64
1414 15:36:07.424157 [RxdqsGatingPostProcess] freq 800
1415 15:36:07.430451 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1416 15:36:07.434047 Pre-setting of DQS Precalculation
1417 15:36:07.437286 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1418 15:36:07.437368 ==
1419 15:36:07.440212 Dram Type= 6, Freq= 0, CH_1, rank 0
1420 15:36:07.443476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 15:36:07.447240 ==
1422 15:36:07.450585 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1423 15:36:07.456879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1424 15:36:07.465856 [CA 0] Center 36 (6~67) winsize 62
1425 15:36:07.469197 [CA 1] Center 36 (6~67) winsize 62
1426 15:36:07.473203 [CA 2] Center 34 (4~65) winsize 62
1427 15:36:07.476139 [CA 3] Center 34 (3~65) winsize 63
1428 15:36:07.479610 [CA 4] Center 34 (4~65) winsize 62
1429 15:36:07.483025 [CA 5] Center 34 (3~65) winsize 63
1430 15:36:07.483126
1431 15:36:07.485992 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1432 15:36:07.486074
1433 15:36:07.488977 [CATrainingPosCal] consider 1 rank data
1434 15:36:07.492563 u2DelayCellTimex100 = 270/100 ps
1435 15:36:07.495700 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1436 15:36:07.499372 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1437 15:36:07.505764 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 15:36:07.509236 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1439 15:36:07.512437 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1440 15:36:07.515941 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1441 15:36:07.516024
1442 15:36:07.518991 CA PerBit enable=1, Macro0, CA PI delay=34
1443 15:36:07.519074
1444 15:36:07.522490 [CBTSetCACLKResult] CA Dly = 34
1445 15:36:07.522626 CS Dly: 5 (0~36)
1446 15:36:07.526098 ==
1447 15:36:07.526179 Dram Type= 6, Freq= 0, CH_1, rank 1
1448 15:36:07.532540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 15:36:07.532647 ==
1450 15:36:07.535926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 15:36:07.542361 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 15:36:07.552149 [CA 0] Center 36 (6~67) winsize 62
1453 15:36:07.555177 [CA 1] Center 37 (6~68) winsize 63
1454 15:36:07.558516 [CA 2] Center 34 (4~65) winsize 62
1455 15:36:07.562231 [CA 3] Center 34 (3~65) winsize 63
1456 15:36:07.565532 [CA 4] Center 34 (4~65) winsize 62
1457 15:36:07.568613 [CA 5] Center 34 (3~65) winsize 63
1458 15:36:07.568695
1459 15:36:07.572303 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1460 15:36:07.572386
1461 15:36:07.575066 [CATrainingPosCal] consider 2 rank data
1462 15:36:07.578788 u2DelayCellTimex100 = 270/100 ps
1463 15:36:07.581957 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 15:36:07.588256 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 15:36:07.591882 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 15:36:07.595373 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1467 15:36:07.598222 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 15:36:07.601662 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1469 15:36:07.601731
1470 15:36:07.605199 CA PerBit enable=1, Macro0, CA PI delay=34
1471 15:36:07.605274
1472 15:36:07.608215 [CBTSetCACLKResult] CA Dly = 34
1473 15:36:07.608287 CS Dly: 5 (0~37)
1474 15:36:07.611753
1475 15:36:07.614968 ----->DramcWriteLeveling(PI) begin...
1476 15:36:07.615042 ==
1477 15:36:07.618651 Dram Type= 6, Freq= 0, CH_1, rank 0
1478 15:36:07.621646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 15:36:07.621729 ==
1480 15:36:07.625128 Write leveling (Byte 0): 26 => 26
1481 15:36:07.628252 Write leveling (Byte 1): 30 => 30
1482 15:36:07.631510 DramcWriteLeveling(PI) end<-----
1483 15:36:07.631591
1484 15:36:07.631656 ==
1485 15:36:07.635036 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 15:36:07.638106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1487 15:36:07.638187 ==
1488 15:36:07.641527 [Gating] SW mode calibration
1489 15:36:07.648242 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1490 15:36:07.654783 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1491 15:36:07.658106 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1492 15:36:07.661117 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1493 15:36:07.668212 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 15:36:07.671521 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 15:36:07.674771 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 15:36:07.681502 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 15:36:07.684642 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 15:36:07.687586 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 15:36:07.694256 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 15:36:07.697811 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 15:36:07.700968 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 15:36:07.707923 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 15:36:07.710836 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 15:36:07.714245 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 15:36:07.717686 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 15:36:07.724458 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 15:36:07.727835 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1508 15:36:07.731457 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1509 15:36:07.737878 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 15:36:07.740786 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1511 15:36:07.744294 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 15:36:07.750774 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 15:36:07.754285 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 15:36:07.757260 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 15:36:07.763927 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 15:36:07.767243 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 15:36:07.770660 0 9 8 | B1->B0 | 2e2d 2f2f | 1 1 | (1 1) (1 1)
1518 15:36:07.777240 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 15:36:07.780870 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 15:36:07.783814 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 15:36:07.790369 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 15:36:07.793663 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 15:36:07.797037 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1524 15:36:07.804151 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
1525 15:36:07.806807 0 10 8 | B1->B0 | 2c2c 2525 | 1 1 | (1 0) (1 0)
1526 15:36:07.810212 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 15:36:07.817208 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 15:36:07.820178 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 15:36:07.823657 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 15:36:07.830294 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 15:36:07.833322 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 15:36:07.836789 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1533 15:36:07.843114 0 11 8 | B1->B0 | 3d3d 4242 | 0 0 | (1 1) (0 0)
1534 15:36:07.846522 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 15:36:07.850143 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 15:36:07.856652 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 15:36:07.860065 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 15:36:07.862948 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 15:36:07.869491 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 15:36:07.873145 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1541 15:36:07.876214 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 15:36:07.883124 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 15:36:07.886237 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 15:36:07.889564 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 15:36:07.896335 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 15:36:07.899701 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 15:36:07.902829 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 15:36:07.909600 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 15:36:07.913157 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 15:36:07.915882 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 15:36:07.922623 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 15:36:07.926047 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 15:36:07.929440 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 15:36:07.936067 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 15:36:07.939250 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1556 15:36:07.942528 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 15:36:07.946117 Total UI for P1: 0, mck2ui 16
1558 15:36:07.949010 best dqsien dly found for B0: ( 0, 14, 0)
1559 15:36:07.952716 Total UI for P1: 0, mck2ui 16
1560 15:36:07.955940 best dqsien dly found for B1: ( 0, 14, 2)
1561 15:36:07.959078 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1562 15:36:07.962827 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1563 15:36:07.962909
1564 15:36:07.965682 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1565 15:36:07.972833 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1566 15:36:07.972923 [Gating] SW calibration Done
1567 15:36:07.972988 ==
1568 15:36:07.975910 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 15:36:07.982412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 15:36:07.982494 ==
1571 15:36:07.982559 RX Vref Scan: 0
1572 15:36:07.982663
1573 15:36:07.985588 RX Vref 0 -> 0, step: 1
1574 15:36:07.985669
1575 15:36:07.989078 RX Delay -130 -> 252, step: 16
1576 15:36:07.992299 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1577 15:36:07.995866 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1578 15:36:07.998773 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1579 15:36:08.005490 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1580 15:36:08.008887 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1581 15:36:08.012198 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1582 15:36:08.015726 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1583 15:36:08.018798 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1584 15:36:08.025866 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1585 15:36:08.028774 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1586 15:36:08.032268 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1587 15:36:08.035279 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1588 15:36:08.041804 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1589 15:36:08.045426 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1590 15:36:08.048486 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1591 15:36:08.052094 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1592 15:36:08.052176 ==
1593 15:36:08.055174 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 15:36:08.058752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 15:36:08.061782 ==
1596 15:36:08.061863 DQS Delay:
1597 15:36:08.061928 DQS0 = 0, DQS1 = 0
1598 15:36:08.065308 DQM Delay:
1599 15:36:08.065389 DQM0 = 89, DQM1 = 78
1600 15:36:08.068685 DQ Delay:
1601 15:36:08.071786 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1602 15:36:08.075272 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1603 15:36:08.078084 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1604 15:36:08.081537 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1605 15:36:08.081618
1606 15:36:08.081683
1607 15:36:08.081742 ==
1608 15:36:08.085088 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 15:36:08.088148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 15:36:08.088231 ==
1611 15:36:08.088295
1612 15:36:08.088355
1613 15:36:08.091781 TX Vref Scan disable
1614 15:36:08.091862 == TX Byte 0 ==
1615 15:36:08.098261 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1616 15:36:08.101692 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1617 15:36:08.101773 == TX Byte 1 ==
1618 15:36:08.108187 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1619 15:36:08.111659 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1620 15:36:08.111741 ==
1621 15:36:08.114532 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 15:36:08.118078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 15:36:08.118160 ==
1624 15:36:08.132376 TX Vref=22, minBit 10, minWin=26, winSum=442
1625 15:36:08.135845 TX Vref=24, minBit 0, minWin=27, winSum=443
1626 15:36:08.139025 TX Vref=26, minBit 8, minWin=27, winSum=445
1627 15:36:08.142409 TX Vref=28, minBit 10, minWin=27, winSum=451
1628 15:36:08.145899 TX Vref=30, minBit 8, minWin=27, winSum=447
1629 15:36:08.152263 TX Vref=32, minBit 8, minWin=27, winSum=448
1630 15:36:08.155802 [TxChooseVref] Worse bit 10, Min win 27, Win sum 451, Final Vref 28
1631 15:36:08.155884
1632 15:36:08.159611 Final TX Range 1 Vref 28
1633 15:36:08.159692
1634 15:36:08.159757 ==
1635 15:36:08.162463 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 15:36:08.166126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 15:36:08.166208 ==
1638 15:36:08.169048
1639 15:36:08.169128
1640 15:36:08.169193 TX Vref Scan disable
1641 15:36:08.172600 == TX Byte 0 ==
1642 15:36:08.176085 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1643 15:36:08.182446 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1644 15:36:08.182528 == TX Byte 1 ==
1645 15:36:08.186011 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1646 15:36:08.192569 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1647 15:36:08.192650
1648 15:36:08.192714 [DATLAT]
1649 15:36:08.192773 Freq=800, CH1 RK0
1650 15:36:08.192832
1651 15:36:08.195679 DATLAT Default: 0xa
1652 15:36:08.195760 0, 0xFFFF, sum = 0
1653 15:36:08.198898 1, 0xFFFF, sum = 0
1654 15:36:08.202301 2, 0xFFFF, sum = 0
1655 15:36:08.202384 3, 0xFFFF, sum = 0
1656 15:36:08.205857 4, 0xFFFF, sum = 0
1657 15:36:08.205949 5, 0xFFFF, sum = 0
1658 15:36:08.208983 6, 0xFFFF, sum = 0
1659 15:36:08.209066 7, 0xFFFF, sum = 0
1660 15:36:08.212531 8, 0xFFFF, sum = 0
1661 15:36:08.212614 9, 0x0, sum = 1
1662 15:36:08.215963 10, 0x0, sum = 2
1663 15:36:08.216045 11, 0x0, sum = 3
1664 15:36:08.216111 12, 0x0, sum = 4
1665 15:36:08.219291 best_step = 10
1666 15:36:08.219371
1667 15:36:08.219435 ==
1668 15:36:08.222307 Dram Type= 6, Freq= 0, CH_1, rank 0
1669 15:36:08.225827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1670 15:36:08.225909 ==
1671 15:36:08.228859 RX Vref Scan: 1
1672 15:36:08.228940
1673 15:36:08.232370 Set Vref Range= 32 -> 127
1674 15:36:08.232451
1675 15:36:08.232516 RX Vref 32 -> 127, step: 1
1676 15:36:08.232576
1677 15:36:08.235666 RX Delay -95 -> 252, step: 8
1678 15:36:08.235748
1679 15:36:08.238897 Set Vref, RX VrefLevel [Byte0]: 32
1680 15:36:08.242196 [Byte1]: 32
1681 15:36:08.242277
1682 15:36:08.245372 Set Vref, RX VrefLevel [Byte0]: 33
1683 15:36:08.248762 [Byte1]: 33
1684 15:36:08.253030
1685 15:36:08.253132 Set Vref, RX VrefLevel [Byte0]: 34
1686 15:36:08.256486 [Byte1]: 34
1687 15:36:08.260595
1688 15:36:08.263877 Set Vref, RX VrefLevel [Byte0]: 35
1689 15:36:08.266967 [Byte1]: 35
1690 15:36:08.267077
1691 15:36:08.270183 Set Vref, RX VrefLevel [Byte0]: 36
1692 15:36:08.273685 [Byte1]: 36
1693 15:36:08.273782
1694 15:36:08.276735 Set Vref, RX VrefLevel [Byte0]: 37
1695 15:36:08.280264 [Byte1]: 37
1696 15:36:08.280337
1697 15:36:08.283739 Set Vref, RX VrefLevel [Byte0]: 38
1698 15:36:08.287255 [Byte1]: 38
1699 15:36:08.290715
1700 15:36:08.290786 Set Vref, RX VrefLevel [Byte0]: 39
1701 15:36:08.294131 [Byte1]: 39
1702 15:36:08.298733
1703 15:36:08.298818 Set Vref, RX VrefLevel [Byte0]: 40
1704 15:36:08.302264 [Byte1]: 40
1705 15:36:08.306282
1706 15:36:08.306354 Set Vref, RX VrefLevel [Byte0]: 41
1707 15:36:08.309185 [Byte1]: 41
1708 15:36:08.313799
1709 15:36:08.313870 Set Vref, RX VrefLevel [Byte0]: 42
1710 15:36:08.317271 [Byte1]: 42
1711 15:36:08.321086
1712 15:36:08.321172 Set Vref, RX VrefLevel [Byte0]: 43
1713 15:36:08.324810 [Byte1]: 43
1714 15:36:08.328933
1715 15:36:08.329007 Set Vref, RX VrefLevel [Byte0]: 44
1716 15:36:08.332022 [Byte1]: 44
1717 15:36:08.336693
1718 15:36:08.336772 Set Vref, RX VrefLevel [Byte0]: 45
1719 15:36:08.339612 [Byte1]: 45
1720 15:36:08.344026
1721 15:36:08.344106 Set Vref, RX VrefLevel [Byte0]: 46
1722 15:36:08.347748 [Byte1]: 46
1723 15:36:08.351495
1724 15:36:08.351570 Set Vref, RX VrefLevel [Byte0]: 47
1725 15:36:08.354963 [Byte1]: 47
1726 15:36:08.359362
1727 15:36:08.359435 Set Vref, RX VrefLevel [Byte0]: 48
1728 15:36:08.362673 [Byte1]: 48
1729 15:36:08.366976
1730 15:36:08.367075 Set Vref, RX VrefLevel [Byte0]: 49
1731 15:36:08.370229 [Byte1]: 49
1732 15:36:08.374887
1733 15:36:08.374968 Set Vref, RX VrefLevel [Byte0]: 50
1734 15:36:08.378084 [Byte1]: 50
1735 15:36:08.381998
1736 15:36:08.382078 Set Vref, RX VrefLevel [Byte0]: 51
1737 15:36:08.385403 [Byte1]: 51
1738 15:36:08.389448
1739 15:36:08.389528 Set Vref, RX VrefLevel [Byte0]: 52
1740 15:36:08.396608 [Byte1]: 52
1741 15:36:08.396689
1742 15:36:08.399485 Set Vref, RX VrefLevel [Byte0]: 53
1743 15:36:08.402963 [Byte1]: 53
1744 15:36:08.403044
1745 15:36:08.405984 Set Vref, RX VrefLevel [Byte0]: 54
1746 15:36:08.409259 [Byte1]: 54
1747 15:36:08.409339
1748 15:36:08.412512 Set Vref, RX VrefLevel [Byte0]: 55
1749 15:36:08.415777 [Byte1]: 55
1750 15:36:08.420028
1751 15:36:08.420108 Set Vref, RX VrefLevel [Byte0]: 56
1752 15:36:08.423432 [Byte1]: 56
1753 15:36:08.427714
1754 15:36:08.427795 Set Vref, RX VrefLevel [Byte0]: 57
1755 15:36:08.430940 [Byte1]: 57
1756 15:36:08.435012
1757 15:36:08.435093 Set Vref, RX VrefLevel [Byte0]: 58
1758 15:36:08.438511 [Byte1]: 58
1759 15:36:08.442992
1760 15:36:08.443073 Set Vref, RX VrefLevel [Byte0]: 59
1761 15:36:08.446398 [Byte1]: 59
1762 15:36:08.450363
1763 15:36:08.450444 Set Vref, RX VrefLevel [Byte0]: 60
1764 15:36:08.453647 [Byte1]: 60
1765 15:36:08.458128
1766 15:36:08.458209 Set Vref, RX VrefLevel [Byte0]: 61
1767 15:36:08.461773 [Byte1]: 61
1768 15:36:08.465801
1769 15:36:08.465881 Set Vref, RX VrefLevel [Byte0]: 62
1770 15:36:08.468990 [Byte1]: 62
1771 15:36:08.473038
1772 15:36:08.473118 Set Vref, RX VrefLevel [Byte0]: 63
1773 15:36:08.476677 [Byte1]: 63
1774 15:36:08.480890
1775 15:36:08.480970 Set Vref, RX VrefLevel [Byte0]: 64
1776 15:36:08.484000 [Byte1]: 64
1777 15:36:08.488255
1778 15:36:08.488335 Set Vref, RX VrefLevel [Byte0]: 65
1779 15:36:08.495267 [Byte1]: 65
1780 15:36:08.495349
1781 15:36:08.498428 Set Vref, RX VrefLevel [Byte0]: 66
1782 15:36:08.501638 [Byte1]: 66
1783 15:36:08.501718
1784 15:36:08.505265 Set Vref, RX VrefLevel [Byte0]: 67
1785 15:36:08.508186 [Byte1]: 67
1786 15:36:08.508267
1787 15:36:08.511737 Set Vref, RX VrefLevel [Byte0]: 68
1788 15:36:08.514839 [Byte1]: 68
1789 15:36:08.518585
1790 15:36:08.518674 Set Vref, RX VrefLevel [Byte0]: 69
1791 15:36:08.522041 [Byte1]: 69
1792 15:36:08.526751
1793 15:36:08.526832 Set Vref, RX VrefLevel [Byte0]: 70
1794 15:36:08.529636 [Byte1]: 70
1795 15:36:08.533721
1796 15:36:08.533790 Set Vref, RX VrefLevel [Byte0]: 71
1797 15:36:08.537343 [Byte1]: 71
1798 15:36:08.541758
1799 15:36:08.541915 Set Vref, RX VrefLevel [Byte0]: 72
1800 15:36:08.545236 [Byte1]: 72
1801 15:36:08.549285
1802 15:36:08.549366 Set Vref, RX VrefLevel [Byte0]: 73
1803 15:36:08.552710 [Byte1]: 73
1804 15:36:08.556681
1805 15:36:08.556761 Set Vref, RX VrefLevel [Byte0]: 74
1806 15:36:08.559870 [Byte1]: 74
1807 15:36:08.564725
1808 15:36:08.564805 Set Vref, RX VrefLevel [Byte0]: 75
1809 15:36:08.567495 [Byte1]: 75
1810 15:36:08.572327
1811 15:36:08.572407 Set Vref, RX VrefLevel [Byte0]: 76
1812 15:36:08.575234 [Byte1]: 76
1813 15:36:08.579455
1814 15:36:08.579536 Final RX Vref Byte 0 = 56 to rank0
1815 15:36:08.583197 Final RX Vref Byte 1 = 67 to rank0
1816 15:36:08.586279 Final RX Vref Byte 0 = 56 to rank1
1817 15:36:08.589376 Final RX Vref Byte 1 = 67 to rank1==
1818 15:36:08.592799 Dram Type= 6, Freq= 0, CH_1, rank 0
1819 15:36:08.599731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 15:36:08.599813 ==
1821 15:36:08.599878 DQS Delay:
1822 15:36:08.599938 DQS0 = 0, DQS1 = 0
1823 15:36:08.602774 DQM Delay:
1824 15:36:08.602854 DQM0 = 87, DQM1 = 78
1825 15:36:08.606127 DQ Delay:
1826 15:36:08.609575 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1827 15:36:08.612797 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1828 15:36:08.615991 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1829 15:36:08.619491 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1830 15:36:08.619572
1831 15:36:08.619636
1832 15:36:08.625515 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f1b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1833 15:36:08.628837 CH1 RK0: MR19=606, MR18=2F1B
1834 15:36:08.635792 CH1_RK0: MR19=0x606, MR18=0x2F1B, DQSOSC=397, MR23=63, INC=93, DEC=62
1835 15:36:08.635874
1836 15:36:08.638868 ----->DramcWriteLeveling(PI) begin...
1837 15:36:08.638949 ==
1838 15:36:08.642109 Dram Type= 6, Freq= 0, CH_1, rank 1
1839 15:36:08.645265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 15:36:08.645347 ==
1841 15:36:08.648696 Write leveling (Byte 0): 27 => 27
1842 15:36:08.651901 Write leveling (Byte 1): 32 => 32
1843 15:36:08.655395 DramcWriteLeveling(PI) end<-----
1844 15:36:08.655476
1845 15:36:08.655540 ==
1846 15:36:08.658902 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 15:36:08.662268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 15:36:08.665064 ==
1849 15:36:08.665145 [Gating] SW mode calibration
1850 15:36:08.675028 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1851 15:36:08.678750 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1852 15:36:08.681922 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1853 15:36:08.688616 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1854 15:36:08.691604 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 15:36:08.695038 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 15:36:08.702115 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 15:36:08.704905 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 15:36:08.708443 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 15:36:08.714976 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 15:36:08.718145 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 15:36:08.722017 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 15:36:08.728433 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 15:36:08.731561 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 15:36:08.734835 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 15:36:08.741799 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 15:36:08.744698 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 15:36:08.748331 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 15:36:08.755014 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 15:36:08.758006 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1870 15:36:08.761378 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1871 15:36:08.768195 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 15:36:08.771825 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 15:36:08.774822 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 15:36:08.781278 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 15:36:08.784759 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 15:36:08.788347 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 15:36:08.791841 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1878 15:36:08.798491 0 9 8 | B1->B0 | 2e2e 2a2a | 1 1 | (1 1) (1 1)
1879 15:36:08.801146 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 15:36:08.804675 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 15:36:08.811019 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 15:36:08.814564 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 15:36:08.818047 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 15:36:08.824415 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 15:36:08.828356 0 10 4 | B1->B0 | 3030 3131 | 1 1 | (1 0) (1 1)
1886 15:36:08.830975 0 10 8 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (1 0)
1887 15:36:08.838066 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 15:36:08.841123 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 15:36:08.844080 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 15:36:08.850965 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 15:36:08.854438 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 15:36:08.857411 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 15:36:08.864209 0 11 4 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (0 0)
1894 15:36:08.867379 0 11 8 | B1->B0 | 4241 3939 | 1 0 | (0 0) (0 0)
1895 15:36:08.870826 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 15:36:08.877199 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 15:36:08.880656 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 15:36:08.884222 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 15:36:08.890743 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 15:36:08.894187 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 15:36:08.897135 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1902 15:36:08.903794 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1903 15:36:08.906947 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 15:36:08.910209 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 15:36:08.917086 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 15:36:08.920632 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 15:36:08.923621 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 15:36:08.930424 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 15:36:08.933501 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 15:36:08.936934 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 15:36:08.943519 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 15:36:08.947038 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 15:36:08.950162 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 15:36:08.956750 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 15:36:08.960330 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 15:36:08.963419 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 15:36:08.970020 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1918 15:36:08.973123 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 15:36:08.976467 Total UI for P1: 0, mck2ui 16
1920 15:36:08.980321 best dqsien dly found for B0: ( 0, 14, 4)
1921 15:36:08.983199 Total UI for P1: 0, mck2ui 16
1922 15:36:08.986745 best dqsien dly found for B1: ( 0, 14, 4)
1923 15:36:08.989906 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1924 15:36:08.993414 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1925 15:36:08.993495
1926 15:36:08.996747 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1927 15:36:08.999680 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1928 15:36:09.003418 [Gating] SW calibration Done
1929 15:36:09.003499 ==
1930 15:36:09.006313 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 15:36:09.009819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 15:36:09.009916 ==
1933 15:36:09.013169 RX Vref Scan: 0
1934 15:36:09.013249
1935 15:36:09.016451 RX Vref 0 -> 0, step: 1
1936 15:36:09.016533
1937 15:36:09.016597 RX Delay -130 -> 252, step: 16
1938 15:36:09.023518 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1939 15:36:09.026932 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1940 15:36:09.029979 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1941 15:36:09.032996 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1942 15:36:09.036426 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1943 15:36:09.043068 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1944 15:36:09.046555 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1945 15:36:09.049575 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1946 15:36:09.052931 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1947 15:36:09.056231 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1948 15:36:09.062951 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1949 15:36:09.066452 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1950 15:36:09.069604 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1951 15:36:09.072857 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1952 15:36:09.079445 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1953 15:36:09.082829 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1954 15:36:09.082911 ==
1955 15:36:09.086271 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 15:36:09.089299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 15:36:09.089459 ==
1958 15:36:09.092917 DQS Delay:
1959 15:36:09.093028 DQS0 = 0, DQS1 = 0
1960 15:36:09.093124 DQM Delay:
1961 15:36:09.095898 DQM0 = 88, DQM1 = 80
1962 15:36:09.095991 DQ Delay:
1963 15:36:09.099598 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1964 15:36:09.102519 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1965 15:36:09.106234 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1966 15:36:09.109114 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1967 15:36:09.109194
1968 15:36:09.109258
1969 15:36:09.109317 ==
1970 15:36:09.112615 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 15:36:09.119692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 15:36:09.119774 ==
1973 15:36:09.119838
1974 15:36:09.119897
1975 15:36:09.119954 TX Vref Scan disable
1976 15:36:09.123512 == TX Byte 0 ==
1977 15:36:09.126099 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1978 15:36:09.132800 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1979 15:36:09.132910 == TX Byte 1 ==
1980 15:36:09.136466 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1981 15:36:09.142891 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1982 15:36:09.142969 ==
1983 15:36:09.146357 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 15:36:09.149662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 15:36:09.149764 ==
1986 15:36:09.162145 TX Vref=22, minBit 8, minWin=26, winSum=442
1987 15:36:09.165523 TX Vref=24, minBit 1, minWin=27, winSum=448
1988 15:36:09.168984 TX Vref=26, minBit 8, minWin=27, winSum=450
1989 15:36:09.171992 TX Vref=28, minBit 8, minWin=27, winSum=452
1990 15:36:09.175573 TX Vref=30, minBit 8, minWin=27, winSum=449
1991 15:36:09.181940 TX Vref=32, minBit 8, minWin=27, winSum=452
1992 15:36:09.185522 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 28
1993 15:36:09.185630
1994 15:36:09.188229 Final TX Range 1 Vref 28
1995 15:36:09.188311
1996 15:36:09.188376 ==
1997 15:36:09.191701 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 15:36:09.195008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 15:36:09.198788 ==
2000 15:36:09.198860
2001 15:36:09.198920
2002 15:36:09.198977 TX Vref Scan disable
2003 15:36:09.202712 == TX Byte 0 ==
2004 15:36:09.205592 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2005 15:36:09.212094 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2006 15:36:09.212167 == TX Byte 1 ==
2007 15:36:09.215732 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2008 15:36:09.222028 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2009 15:36:09.222101
2010 15:36:09.222162 [DATLAT]
2011 15:36:09.222219 Freq=800, CH1 RK1
2012 15:36:09.222292
2013 15:36:09.225237 DATLAT Default: 0xa
2014 15:36:09.225303 0, 0xFFFF, sum = 0
2015 15:36:09.228567 1, 0xFFFF, sum = 0
2016 15:36:09.232110 2, 0xFFFF, sum = 0
2017 15:36:09.232191 3, 0xFFFF, sum = 0
2018 15:36:09.235138 4, 0xFFFF, sum = 0
2019 15:36:09.235220 5, 0xFFFF, sum = 0
2020 15:36:09.238612 6, 0xFFFF, sum = 0
2021 15:36:09.238710 7, 0xFFFF, sum = 0
2022 15:36:09.242467 8, 0xFFFF, sum = 0
2023 15:36:09.242587 9, 0x0, sum = 1
2024 15:36:09.245266 10, 0x0, sum = 2
2025 15:36:09.245348 11, 0x0, sum = 3
2026 15:36:09.245413 12, 0x0, sum = 4
2027 15:36:09.248824 best_step = 10
2028 15:36:09.248919
2029 15:36:09.248985 ==
2030 15:36:09.251915 Dram Type= 6, Freq= 0, CH_1, rank 1
2031 15:36:09.255211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2032 15:36:09.255307 ==
2033 15:36:09.258500 RX Vref Scan: 0
2034 15:36:09.258645
2035 15:36:09.261354 RX Vref 0 -> 0, step: 1
2036 15:36:09.261442
2037 15:36:09.261526 RX Delay -95 -> 252, step: 8
2038 15:36:09.269204 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2039 15:36:09.272240 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2040 15:36:09.275455 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2041 15:36:09.279175 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2042 15:36:09.282161 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2043 15:36:09.288557 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2044 15:36:09.292050 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2045 15:36:09.295673 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2046 15:36:09.298489 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2047 15:36:09.302311 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2048 15:36:09.308647 iDelay=217, Bit 10, Center 80 (-31 ~ 192) 224
2049 15:36:09.312187 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2050 15:36:09.315579 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2051 15:36:09.318565 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2052 15:36:09.325279 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2053 15:36:09.328857 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2054 15:36:09.328948 ==
2055 15:36:09.331897 Dram Type= 6, Freq= 0, CH_1, rank 1
2056 15:36:09.335384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2057 15:36:09.335498 ==
2058 15:36:09.338254 DQS Delay:
2059 15:36:09.338332 DQS0 = 0, DQS1 = 0
2060 15:36:09.338399 DQM Delay:
2061 15:36:09.341692 DQM0 = 87, DQM1 = 79
2062 15:36:09.341775 DQ Delay:
2063 15:36:09.345165 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2064 15:36:09.348353 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2065 15:36:09.352481 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
2066 15:36:09.355202 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2067 15:36:09.355304
2068 15:36:09.355395
2069 15:36:09.364731 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2070 15:36:09.367945 CH1 RK1: MR19=606, MR18=1D15
2071 15:36:09.371288 CH1_RK1: MR19=0x606, MR18=0x1D15, DQSOSC=402, MR23=63, INC=91, DEC=60
2072 15:36:09.374736 [RxdqsGatingPostProcess] freq 800
2073 15:36:09.381647 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2074 15:36:09.384786 Pre-setting of DQS Precalculation
2075 15:36:09.387987 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2076 15:36:09.398155 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2077 15:36:09.404786 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2078 15:36:09.404895
2079 15:36:09.404988
2080 15:36:09.407816 [Calibration Summary] 1600 Mbps
2081 15:36:09.407898 CH 0, Rank 0
2082 15:36:09.410967 SW Impedance : PASS
2083 15:36:09.411112 DUTY Scan : NO K
2084 15:36:09.414178 ZQ Calibration : PASS
2085 15:36:09.417601 Jitter Meter : NO K
2086 15:36:09.417690 CBT Training : PASS
2087 15:36:09.421126 Write leveling : PASS
2088 15:36:09.424828 RX DQS gating : PASS
2089 15:36:09.424932 RX DQ/DQS(RDDQC) : PASS
2090 15:36:09.427608 TX DQ/DQS : PASS
2091 15:36:09.431181 RX DATLAT : PASS
2092 15:36:09.431307 RX DQ/DQS(Engine): PASS
2093 15:36:09.434498 TX OE : NO K
2094 15:36:09.434583 All Pass.
2095 15:36:09.434689
2096 15:36:09.438030 CH 0, Rank 1
2097 15:36:09.438115 SW Impedance : PASS
2098 15:36:09.441075 DUTY Scan : NO K
2099 15:36:09.441160 ZQ Calibration : PASS
2100 15:36:09.444589 Jitter Meter : NO K
2101 15:36:09.447535 CBT Training : PASS
2102 15:36:09.447617 Write leveling : PASS
2103 15:36:09.451245 RX DQS gating : PASS
2104 15:36:09.454284 RX DQ/DQS(RDDQC) : PASS
2105 15:36:09.454366 TX DQ/DQS : PASS
2106 15:36:09.457603 RX DATLAT : PASS
2107 15:36:09.461441 RX DQ/DQS(Engine): PASS
2108 15:36:09.461523 TX OE : NO K
2109 15:36:09.464131 All Pass.
2110 15:36:09.464213
2111 15:36:09.464278 CH 1, Rank 0
2112 15:36:09.467909 SW Impedance : PASS
2113 15:36:09.467992 DUTY Scan : NO K
2114 15:36:09.470738 ZQ Calibration : PASS
2115 15:36:09.474289 Jitter Meter : NO K
2116 15:36:09.474371 CBT Training : PASS
2117 15:36:09.477524 Write leveling : PASS
2118 15:36:09.480986 RX DQS gating : PASS
2119 15:36:09.481067 RX DQ/DQS(RDDQC) : PASS
2120 15:36:09.484097 TX DQ/DQS : PASS
2121 15:36:09.487476 RX DATLAT : PASS
2122 15:36:09.487557 RX DQ/DQS(Engine): PASS
2123 15:36:09.490927 TX OE : NO K
2124 15:36:09.491009 All Pass.
2125 15:36:09.491074
2126 15:36:09.494390 CH 1, Rank 1
2127 15:36:09.494471 SW Impedance : PASS
2128 15:36:09.497261 DUTY Scan : NO K
2129 15:36:09.497343 ZQ Calibration : PASS
2130 15:36:09.500911 Jitter Meter : NO K
2131 15:36:09.503840 CBT Training : PASS
2132 15:36:09.503939 Write leveling : PASS
2133 15:36:09.507320 RX DQS gating : PASS
2134 15:36:09.510742 RX DQ/DQS(RDDQC) : PASS
2135 15:36:09.510833 TX DQ/DQS : PASS
2136 15:36:09.514161 RX DATLAT : PASS
2137 15:36:09.517291 RX DQ/DQS(Engine): PASS
2138 15:36:09.517379 TX OE : NO K
2139 15:36:09.521169 All Pass.
2140 15:36:09.521259
2141 15:36:09.521327 DramC Write-DBI off
2142 15:36:09.524118 PER_BANK_REFRESH: Hybrid Mode
2143 15:36:09.524201 TX_TRACKING: ON
2144 15:36:09.527849 [GetDramInforAfterCalByMRR] Vendor 6.
2145 15:36:09.534095 [GetDramInforAfterCalByMRR] Revision 606.
2146 15:36:09.537385 [GetDramInforAfterCalByMRR] Revision 2 0.
2147 15:36:09.537473 MR0 0x3b3b
2148 15:36:09.537540 MR8 0x5151
2149 15:36:09.541151 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2150 15:36:09.541234
2151 15:36:09.543948 MR0 0x3b3b
2152 15:36:09.544030 MR8 0x5151
2153 15:36:09.547424 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2154 15:36:09.547532
2155 15:36:09.557424 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2156 15:36:09.561109 [FAST_K] Save calibration result to emmc
2157 15:36:09.563918 [FAST_K] Save calibration result to emmc
2158 15:36:09.567363 dram_init: config_dvfs: 1
2159 15:36:09.571053 dramc_set_vcore_voltage set vcore to 662500
2160 15:36:09.574363 Read voltage for 1200, 2
2161 15:36:09.574473 Vio18 = 0
2162 15:36:09.574569 Vcore = 662500
2163 15:36:09.577199 Vdram = 0
2164 15:36:09.577314 Vddq = 0
2165 15:36:09.577474 Vmddr = 0
2166 15:36:09.583830 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2167 15:36:09.587186 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2168 15:36:09.590815 MEM_TYPE=3, freq_sel=15
2169 15:36:09.594238 sv_algorithm_assistance_LP4_1600
2170 15:36:09.597206 ============ PULL DRAM RESETB DOWN ============
2171 15:36:09.600853 ========== PULL DRAM RESETB DOWN end =========
2172 15:36:09.607339 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2173 15:36:09.610460 ===================================
2174 15:36:09.610580 LPDDR4 DRAM CONFIGURATION
2175 15:36:09.613791 ===================================
2176 15:36:09.617419 EX_ROW_EN[0] = 0x0
2177 15:36:09.620515 EX_ROW_EN[1] = 0x0
2178 15:36:09.620613 LP4Y_EN = 0x0
2179 15:36:09.624004 WORK_FSP = 0x0
2180 15:36:09.624087 WL = 0x4
2181 15:36:09.627443 RL = 0x4
2182 15:36:09.627525 BL = 0x2
2183 15:36:09.630150 RPST = 0x0
2184 15:36:09.630231 RD_PRE = 0x0
2185 15:36:09.633893 WR_PRE = 0x1
2186 15:36:09.633976 WR_PST = 0x0
2187 15:36:09.637410 DBI_WR = 0x0
2188 15:36:09.637497 DBI_RD = 0x0
2189 15:36:09.640376 OTF = 0x1
2190 15:36:09.643719 ===================================
2191 15:36:09.647277 ===================================
2192 15:36:09.647366 ANA top config
2193 15:36:09.650372 ===================================
2194 15:36:09.653918 DLL_ASYNC_EN = 0
2195 15:36:09.656925 ALL_SLAVE_EN = 0
2196 15:36:09.660000 NEW_RANK_MODE = 1
2197 15:36:09.660097 DLL_IDLE_MODE = 1
2198 15:36:09.663616 LP45_APHY_COMB_EN = 1
2199 15:36:09.667220 TX_ODT_DIS = 1
2200 15:36:09.670224 NEW_8X_MODE = 1
2201 15:36:09.673899 ===================================
2202 15:36:09.676929 ===================================
2203 15:36:09.680704 data_rate = 2400
2204 15:36:09.680785 CKR = 1
2205 15:36:09.683645 DQ_P2S_RATIO = 8
2206 15:36:09.686886 ===================================
2207 15:36:09.690095 CA_P2S_RATIO = 8
2208 15:36:09.693624 DQ_CA_OPEN = 0
2209 15:36:09.696799 DQ_SEMI_OPEN = 0
2210 15:36:09.699992 CA_SEMI_OPEN = 0
2211 15:36:09.700075 CA_FULL_RATE = 0
2212 15:36:09.703412 DQ_CKDIV4_EN = 0
2213 15:36:09.706912 CA_CKDIV4_EN = 0
2214 15:36:09.710387 CA_PREDIV_EN = 0
2215 15:36:09.713227 PH8_DLY = 17
2216 15:36:09.716570 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2217 15:36:09.716652 DQ_AAMCK_DIV = 4
2218 15:36:09.720508 CA_AAMCK_DIV = 4
2219 15:36:09.723545 CA_ADMCK_DIV = 4
2220 15:36:09.726888 DQ_TRACK_CA_EN = 0
2221 15:36:09.729903 CA_PICK = 1200
2222 15:36:09.733376 CA_MCKIO = 1200
2223 15:36:09.736150 MCKIO_SEMI = 0
2224 15:36:09.736258 PLL_FREQ = 2366
2225 15:36:09.740101 DQ_UI_PI_RATIO = 32
2226 15:36:09.743034 CA_UI_PI_RATIO = 0
2227 15:36:09.746071 ===================================
2228 15:36:09.749540 ===================================
2229 15:36:09.753030 memory_type:LPDDR4
2230 15:36:09.756129 GP_NUM : 10
2231 15:36:09.756211 SRAM_EN : 1
2232 15:36:09.759552 MD32_EN : 0
2233 15:36:09.762732 ===================================
2234 15:36:09.762814 [ANA_INIT] >>>>>>>>>>>>>>
2235 15:36:09.766334 <<<<<< [CONFIGURE PHASE]: ANA_TX
2236 15:36:09.769609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2237 15:36:09.772547 ===================================
2238 15:36:09.775975 data_rate = 2400,PCW = 0X5b00
2239 15:36:09.779614 ===================================
2240 15:36:09.782631 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2241 15:36:09.789083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2242 15:36:09.795956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2243 15:36:09.799384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2244 15:36:09.802383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2245 15:36:09.805781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2246 15:36:09.809281 [ANA_INIT] flow start
2247 15:36:09.809370 [ANA_INIT] PLL >>>>>>>>
2248 15:36:09.812558 [ANA_INIT] PLL <<<<<<<<
2249 15:36:09.816034 [ANA_INIT] MIDPI >>>>>>>>
2250 15:36:09.816117 [ANA_INIT] MIDPI <<<<<<<<
2251 15:36:09.819267 [ANA_INIT] DLL >>>>>>>>
2252 15:36:09.822480 [ANA_INIT] DLL <<<<<<<<
2253 15:36:09.822587 [ANA_INIT] flow end
2254 15:36:09.829121 ============ LP4 DIFF to SE enter ============
2255 15:36:09.832167 ============ LP4 DIFF to SE exit ============
2256 15:36:09.835753 [ANA_INIT] <<<<<<<<<<<<<
2257 15:36:09.838504 [Flow] Enable top DCM control >>>>>
2258 15:36:09.842238 [Flow] Enable top DCM control <<<<<
2259 15:36:09.842321 Enable DLL master slave shuffle
2260 15:36:09.848640 ==============================================================
2261 15:36:09.851777 Gating Mode config
2262 15:36:09.855283 ==============================================================
2263 15:36:09.859029 Config description:
2264 15:36:09.868800 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2265 15:36:09.875437 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2266 15:36:09.878454 SELPH_MODE 0: By rank 1: By Phase
2267 15:36:09.885266 ==============================================================
2268 15:36:09.888954 GAT_TRACK_EN = 1
2269 15:36:09.892007 RX_GATING_MODE = 2
2270 15:36:09.894979 RX_GATING_TRACK_MODE = 2
2271 15:36:09.898133 SELPH_MODE = 1
2272 15:36:09.901612 PICG_EARLY_EN = 1
2273 15:36:09.901705 VALID_LAT_VALUE = 1
2274 15:36:09.908264 ==============================================================
2275 15:36:09.911857 Enter into Gating configuration >>>>
2276 15:36:09.914732 Exit from Gating configuration <<<<
2277 15:36:09.918075 Enter into DVFS_PRE_config >>>>>
2278 15:36:09.928270 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2279 15:36:09.931525 Exit from DVFS_PRE_config <<<<<
2280 15:36:09.934791 Enter into PICG configuration >>>>
2281 15:36:09.938278 Exit from PICG configuration <<<<
2282 15:36:09.941424 [RX_INPUT] configuration >>>>>
2283 15:36:09.944746 [RX_INPUT] configuration <<<<<
2284 15:36:09.951827 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2285 15:36:09.954926 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2286 15:36:09.961552 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2287 15:36:09.967933 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2288 15:36:09.974885 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2289 15:36:09.981452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2290 15:36:09.984997 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2291 15:36:09.987806 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2292 15:36:09.991457 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2293 15:36:09.997743 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2294 15:36:10.001303 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2295 15:36:10.004659 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2296 15:36:10.008130 ===================================
2297 15:36:10.011423 LPDDR4 DRAM CONFIGURATION
2298 15:36:10.014450 ===================================
2299 15:36:10.014533 EX_ROW_EN[0] = 0x0
2300 15:36:10.017774 EX_ROW_EN[1] = 0x0
2301 15:36:10.017856 LP4Y_EN = 0x0
2302 15:36:10.021270 WORK_FSP = 0x0
2303 15:36:10.024747 WL = 0x4
2304 15:36:10.024829 RL = 0x4
2305 15:36:10.027523 BL = 0x2
2306 15:36:10.027605 RPST = 0x0
2307 15:36:10.030764 RD_PRE = 0x0
2308 15:36:10.030845 WR_PRE = 0x1
2309 15:36:10.034512 WR_PST = 0x0
2310 15:36:10.034601 DBI_WR = 0x0
2311 15:36:10.037866 DBI_RD = 0x0
2312 15:36:10.037948 OTF = 0x1
2313 15:36:10.041366 ===================================
2314 15:36:10.044185 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2315 15:36:10.051394 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2316 15:36:10.054739 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2317 15:36:10.057706 ===================================
2318 15:36:10.061043 LPDDR4 DRAM CONFIGURATION
2319 15:36:10.064085 ===================================
2320 15:36:10.064167 EX_ROW_EN[0] = 0x10
2321 15:36:10.067682 EX_ROW_EN[1] = 0x0
2322 15:36:10.067762 LP4Y_EN = 0x0
2323 15:36:10.071005 WORK_FSP = 0x0
2324 15:36:10.071111 WL = 0x4
2325 15:36:10.074160 RL = 0x4
2326 15:36:10.074240 BL = 0x2
2327 15:36:10.077372 RPST = 0x0
2328 15:36:10.080543 RD_PRE = 0x0
2329 15:36:10.080665 WR_PRE = 0x1
2330 15:36:10.084079 WR_PST = 0x0
2331 15:36:10.084160 DBI_WR = 0x0
2332 15:36:10.087729 DBI_RD = 0x0
2333 15:36:10.087810 OTF = 0x1
2334 15:36:10.091076 ===================================
2335 15:36:10.097804 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2336 15:36:10.097886 ==
2337 15:36:10.100746 Dram Type= 6, Freq= 0, CH_0, rank 0
2338 15:36:10.104093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2339 15:36:10.104174 ==
2340 15:36:10.107701 [Duty_Offset_Calibration]
2341 15:36:10.107822 B0:1 B1:-1 CA:0
2342 15:36:10.110550
2343 15:36:10.113781 [DutyScan_Calibration_Flow] k_type=0
2344 15:36:10.121714
2345 15:36:10.121794 ==CLK 0==
2346 15:36:10.125038 Final CLK duty delay cell = 0
2347 15:36:10.128618 [0] MAX Duty = 5125%(X100), DQS PI = 24
2348 15:36:10.132125 [0] MIN Duty = 4907%(X100), DQS PI = 8
2349 15:36:10.132206 [0] AVG Duty = 5016%(X100)
2350 15:36:10.134987
2351 15:36:10.135069 CH0 CLK Duty spec in!! Max-Min= 218%
2352 15:36:10.142236 [DutyScan_Calibration_Flow] ====Done====
2353 15:36:10.142317
2354 15:36:10.144763 [DutyScan_Calibration_Flow] k_type=1
2355 15:36:10.160094
2356 15:36:10.160175 ==DQS 0 ==
2357 15:36:10.164061 Final DQS duty delay cell = -4
2358 15:36:10.167306 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2359 15:36:10.170356 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2360 15:36:10.173687 [-4] AVG Duty = 4968%(X100)
2361 15:36:10.173768
2362 15:36:10.173833 ==DQS 1 ==
2363 15:36:10.176853 Final DQS duty delay cell = 0
2364 15:36:10.180183 [0] MAX Duty = 5124%(X100), DQS PI = 6
2365 15:36:10.183622 [0] MIN Duty = 5000%(X100), DQS PI = 22
2366 15:36:10.186730 [0] AVG Duty = 5062%(X100)
2367 15:36:10.186811
2368 15:36:10.190167 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2369 15:36:10.190259
2370 15:36:10.193492 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2371 15:36:10.196769 [DutyScan_Calibration_Flow] ====Done====
2372 15:36:10.196849
2373 15:36:10.200229 [DutyScan_Calibration_Flow] k_type=3
2374 15:36:10.218089
2375 15:36:10.218171 ==DQM 0 ==
2376 15:36:10.220990 Final DQM duty delay cell = 0
2377 15:36:10.224297 [0] MAX Duty = 5062%(X100), DQS PI = 22
2378 15:36:10.227455 [0] MIN Duty = 4875%(X100), DQS PI = 8
2379 15:36:10.231008 [0] AVG Duty = 4968%(X100)
2380 15:36:10.231090
2381 15:36:10.231154 ==DQM 1 ==
2382 15:36:10.234255 Final DQM duty delay cell = 4
2383 15:36:10.237607 [4] MAX Duty = 5187%(X100), DQS PI = 14
2384 15:36:10.241245 [4] MIN Duty = 5000%(X100), DQS PI = 24
2385 15:36:10.244175 [4] AVG Duty = 5093%(X100)
2386 15:36:10.244260
2387 15:36:10.247840 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2388 15:36:10.247921
2389 15:36:10.251300 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2390 15:36:10.254130 [DutyScan_Calibration_Flow] ====Done====
2391 15:36:10.254212
2392 15:36:10.257364 [DutyScan_Calibration_Flow] k_type=2
2393 15:36:10.272987
2394 15:36:10.273069 ==DQ 0 ==
2395 15:36:10.276443 Final DQ duty delay cell = -4
2396 15:36:10.279473 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2397 15:36:10.282992 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2398 15:36:10.285776 [-4] AVG Duty = 4969%(X100)
2399 15:36:10.285858
2400 15:36:10.285923 ==DQ 1 ==
2401 15:36:10.289525 Final DQ duty delay cell = -4
2402 15:36:10.292860 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2403 15:36:10.295676 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2404 15:36:10.299383 [-4] AVG Duty = 4938%(X100)
2405 15:36:10.299464
2406 15:36:10.302423 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2407 15:36:10.302505
2408 15:36:10.306164 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2409 15:36:10.309122 [DutyScan_Calibration_Flow] ====Done====
2410 15:36:10.309204 ==
2411 15:36:10.312365 Dram Type= 6, Freq= 0, CH_1, rank 0
2412 15:36:10.315997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2413 15:36:10.316079 ==
2414 15:36:10.319418 [Duty_Offset_Calibration]
2415 15:36:10.322310 B0:-1 B1:1 CA:1
2416 15:36:10.322395
2417 15:36:10.325955 [DutyScan_Calibration_Flow] k_type=0
2418 15:36:10.333795
2419 15:36:10.333876 ==CLK 0==
2420 15:36:10.337375 Final CLK duty delay cell = 0
2421 15:36:10.340296 [0] MAX Duty = 5156%(X100), DQS PI = 4
2422 15:36:10.343273 [0] MIN Duty = 5000%(X100), DQS PI = 28
2423 15:36:10.343355 [0] AVG Duty = 5078%(X100)
2424 15:36:10.347302
2425 15:36:10.350127 CH1 CLK Duty spec in!! Max-Min= 156%
2426 15:36:10.353663 [DutyScan_Calibration_Flow] ====Done====
2427 15:36:10.353745
2428 15:36:10.356712 [DutyScan_Calibration_Flow] k_type=1
2429 15:36:10.372796
2430 15:36:10.372878 ==DQS 0 ==
2431 15:36:10.375841 Final DQS duty delay cell = 0
2432 15:36:10.379665 [0] MAX Duty = 5156%(X100), DQS PI = 16
2433 15:36:10.382854 [0] MIN Duty = 4875%(X100), DQS PI = 40
2434 15:36:10.386090 [0] AVG Duty = 5015%(X100)
2435 15:36:10.386171
2436 15:36:10.386235 ==DQS 1 ==
2437 15:36:10.389291 Final DQS duty delay cell = 0
2438 15:36:10.392331 [0] MAX Duty = 5094%(X100), DQS PI = 44
2439 15:36:10.395970 [0] MIN Duty = 4969%(X100), DQS PI = 26
2440 15:36:10.399481 [0] AVG Duty = 5031%(X100)
2441 15:36:10.399561
2442 15:36:10.403246 CH1 DQS 0 Duty spec in!! Max-Min= 281%
2443 15:36:10.403327
2444 15:36:10.405744 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2445 15:36:10.409499 [DutyScan_Calibration_Flow] ====Done====
2446 15:36:10.409584
2447 15:36:10.412907 [DutyScan_Calibration_Flow] k_type=3
2448 15:36:10.428544
2449 15:36:10.428625 ==DQM 0 ==
2450 15:36:10.432265 Final DQM duty delay cell = -4
2451 15:36:10.435358 [-4] MAX Duty = 5062%(X100), DQS PI = 0
2452 15:36:10.438645 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2453 15:36:10.441958 [-4] AVG Duty = 4969%(X100)
2454 15:36:10.442040
2455 15:36:10.442105 ==DQM 1 ==
2456 15:36:10.445657 Final DQM duty delay cell = 0
2457 15:36:10.448767 [0] MAX Duty = 5187%(X100), DQS PI = 36
2458 15:36:10.451782 [0] MIN Duty = 4969%(X100), DQS PI = 2
2459 15:36:10.455485 [0] AVG Duty = 5078%(X100)
2460 15:36:10.455567
2461 15:36:10.458474 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2462 15:36:10.458573
2463 15:36:10.461848 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2464 15:36:10.464831 [DutyScan_Calibration_Flow] ====Done====
2465 15:36:10.464920
2466 15:36:10.468576 [DutyScan_Calibration_Flow] k_type=2
2467 15:36:10.485694
2468 15:36:10.485777 ==DQ 0 ==
2469 15:36:10.488983 Final DQ duty delay cell = 0
2470 15:36:10.492102 [0] MAX Duty = 5156%(X100), DQS PI = 60
2471 15:36:10.495231 [0] MIN Duty = 4907%(X100), DQS PI = 38
2472 15:36:10.495313 [0] AVG Duty = 5031%(X100)
2473 15:36:10.498901
2474 15:36:10.498982 ==DQ 1 ==
2475 15:36:10.502217 Final DQ duty delay cell = 0
2476 15:36:10.505289 [0] MAX Duty = 5124%(X100), DQS PI = 42
2477 15:36:10.508684 [0] MIN Duty = 4969%(X100), DQS PI = 28
2478 15:36:10.508766 [0] AVG Duty = 5046%(X100)
2479 15:36:10.508831
2480 15:36:10.512181 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2481 15:36:10.515198
2482 15:36:10.518731 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2483 15:36:10.521824 [DutyScan_Calibration_Flow] ====Done====
2484 15:36:10.525306 nWR fixed to 30
2485 15:36:10.525388 [ModeRegInit_LP4] CH0 RK0
2486 15:36:10.528657 [ModeRegInit_LP4] CH0 RK1
2487 15:36:10.532132 [ModeRegInit_LP4] CH1 RK0
2488 15:36:10.532207 [ModeRegInit_LP4] CH1 RK1
2489 15:36:10.535801 match AC timing 7
2490 15:36:10.538441 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2491 15:36:10.542250 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2492 15:36:10.548573 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2493 15:36:10.552108 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2494 15:36:10.558837 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2495 15:36:10.558919 ==
2496 15:36:10.561850 Dram Type= 6, Freq= 0, CH_0, rank 0
2497 15:36:10.565367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 15:36:10.565449 ==
2499 15:36:10.572117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2500 15:36:10.578717 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2501 15:36:10.585822 [CA 0] Center 39 (9~70) winsize 62
2502 15:36:10.588559 [CA 1] Center 39 (9~69) winsize 61
2503 15:36:10.591872 [CA 2] Center 35 (5~66) winsize 62
2504 15:36:10.595361 [CA 3] Center 35 (4~66) winsize 63
2505 15:36:10.598478 [CA 4] Center 33 (4~63) winsize 60
2506 15:36:10.602427 [CA 5] Center 33 (3~63) winsize 61
2507 15:36:10.602566
2508 15:36:10.605401 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2509 15:36:10.605482
2510 15:36:10.608435 [CATrainingPosCal] consider 1 rank data
2511 15:36:10.612006 u2DelayCellTimex100 = 270/100 ps
2512 15:36:10.615140 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2513 15:36:10.621892 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2514 15:36:10.625503 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2515 15:36:10.628515 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2516 15:36:10.631955 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2517 15:36:10.634937 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2518 15:36:10.635019
2519 15:36:10.638464 CA PerBit enable=1, Macro0, CA PI delay=33
2520 15:36:10.638571
2521 15:36:10.641874 [CBTSetCACLKResult] CA Dly = 33
2522 15:36:10.641954 CS Dly: 8 (0~39)
2523 15:36:10.645094 ==
2524 15:36:10.648729 Dram Type= 6, Freq= 0, CH_0, rank 1
2525 15:36:10.651585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 15:36:10.651691 ==
2527 15:36:10.654893 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2528 15:36:10.661454 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2529 15:36:10.670978 [CA 0] Center 39 (9~70) winsize 62
2530 15:36:10.674498 [CA 1] Center 39 (9~70) winsize 62
2531 15:36:10.678018 [CA 2] Center 35 (5~66) winsize 62
2532 15:36:10.681203 [CA 3] Center 34 (4~65) winsize 62
2533 15:36:10.684546 [CA 4] Center 33 (3~64) winsize 62
2534 15:36:10.688146 [CA 5] Center 33 (3~63) winsize 61
2535 15:36:10.688227
2536 15:36:10.691039 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2537 15:36:10.691121
2538 15:36:10.694444 [CATrainingPosCal] consider 2 rank data
2539 15:36:10.698179 u2DelayCellTimex100 = 270/100 ps
2540 15:36:10.701172 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2541 15:36:10.704556 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2542 15:36:10.711020 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2543 15:36:10.714284 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2544 15:36:10.717915 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2545 15:36:10.721055 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2546 15:36:10.721137
2547 15:36:10.724238 CA PerBit enable=1, Macro0, CA PI delay=33
2548 15:36:10.724319
2549 15:36:10.727411 [CBTSetCACLKResult] CA Dly = 33
2550 15:36:10.727493 CS Dly: 9 (0~41)
2551 15:36:10.730565
2552 15:36:10.734039 ----->DramcWriteLeveling(PI) begin...
2553 15:36:10.734131 ==
2554 15:36:10.737730 Dram Type= 6, Freq= 0, CH_0, rank 0
2555 15:36:10.740467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2556 15:36:10.740586 ==
2557 15:36:10.744286 Write leveling (Byte 0): 33 => 33
2558 15:36:10.747056 Write leveling (Byte 1): 30 => 30
2559 15:36:10.750533 DramcWriteLeveling(PI) end<-----
2560 15:36:10.750667
2561 15:36:10.750731 ==
2562 15:36:10.754217 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 15:36:10.757120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 15:36:10.757194 ==
2565 15:36:10.760410 [Gating] SW mode calibration
2566 15:36:10.767076 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2567 15:36:10.774178 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2568 15:36:10.777312 0 15 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2569 15:36:10.780329 0 15 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2570 15:36:10.787001 0 15 8 | B1->B0 | 3433 3434 | 1 1 | (1 1) (1 1)
2571 15:36:10.790358 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 15:36:10.793941 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 15:36:10.800577 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2574 15:36:10.803549 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2575 15:36:10.807125 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
2576 15:36:10.813439 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)
2577 15:36:10.817171 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2578 15:36:10.820455 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 15:36:10.824082 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 15:36:10.830354 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 15:36:10.833684 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 15:36:10.836764 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2583 15:36:10.843961 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2584 15:36:10.847153 1 1 0 | B1->B0 | 2a29 4646 | 1 0 | (0 0) (0 0)
2585 15:36:10.849945 1 1 4 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
2586 15:36:10.856735 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 15:36:10.860404 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 15:36:10.863343 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 15:36:10.870034 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 15:36:10.873366 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 15:36:10.876603 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2592 15:36:10.883298 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2593 15:36:10.886670 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2594 15:36:10.890275 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 15:36:10.896696 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 15:36:10.900230 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 15:36:10.903278 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 15:36:10.910059 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 15:36:10.913161 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 15:36:10.916559 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 15:36:10.922936 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 15:36:10.926473 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 15:36:10.929486 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 15:36:10.936141 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 15:36:10.939576 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 15:36:10.942848 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2607 15:36:10.949372 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2608 15:36:10.952834 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2609 15:36:10.956148 Total UI for P1: 0, mck2ui 16
2610 15:36:10.959570 best dqsien dly found for B0: ( 1, 3, 26)
2611 15:36:10.963146 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2612 15:36:10.969481 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 15:36:10.969590 Total UI for P1: 0, mck2ui 16
2614 15:36:10.976261 best dqsien dly found for B1: ( 1, 4, 2)
2615 15:36:10.979456 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2616 15:36:10.983114 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2617 15:36:10.983196
2618 15:36:10.986101 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2619 15:36:10.989997 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2620 15:36:10.992484 [Gating] SW calibration Done
2621 15:36:10.992566 ==
2622 15:36:10.996199 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 15:36:10.999780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 15:36:10.999861 ==
2625 15:36:11.002362 RX Vref Scan: 0
2626 15:36:11.002443
2627 15:36:11.002526 RX Vref 0 -> 0, step: 1
2628 15:36:11.002588
2629 15:36:11.005995 RX Delay -40 -> 252, step: 8
2630 15:36:11.009503 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2631 15:36:11.015918 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2632 15:36:11.018965 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2633 15:36:11.022384 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2634 15:36:11.025579 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2635 15:36:11.028705 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2636 15:36:11.035300 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2637 15:36:11.038842 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2638 15:36:11.042004 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2639 15:36:11.045246 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2640 15:36:11.049132 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2641 15:36:11.055381 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2642 15:36:11.058744 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2643 15:36:11.061978 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2644 15:36:11.065210 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2645 15:36:11.068414 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2646 15:36:11.071959 ==
2647 15:36:11.075387 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 15:36:11.079029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 15:36:11.079110 ==
2650 15:36:11.079174 DQS Delay:
2651 15:36:11.081822 DQS0 = 0, DQS1 = 0
2652 15:36:11.081911 DQM Delay:
2653 15:36:11.085753 DQM0 = 119, DQM1 = 106
2654 15:36:11.085834 DQ Delay:
2655 15:36:11.088954 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2656 15:36:11.092365 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2657 15:36:11.095297 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2658 15:36:11.098749 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2659 15:36:11.098830
2660 15:36:11.098895
2661 15:36:11.098954 ==
2662 15:36:11.102164 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 15:36:11.108293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 15:36:11.108376 ==
2665 15:36:11.108440
2666 15:36:11.108503
2667 15:36:11.108561 TX Vref Scan disable
2668 15:36:11.112416 == TX Byte 0 ==
2669 15:36:11.115251 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2670 15:36:11.118790 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2671 15:36:11.121738 == TX Byte 1 ==
2672 15:36:11.125281 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2673 15:36:11.132394 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2674 15:36:11.132475 ==
2675 15:36:11.135247 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 15:36:11.138470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 15:36:11.138551 ==
2678 15:36:11.149815 TX Vref=22, minBit 5, minWin=25, winSum=418
2679 15:36:11.153487 TX Vref=24, minBit 0, minWin=26, winSum=426
2680 15:36:11.156897 TX Vref=26, minBit 1, minWin=26, winSum=434
2681 15:36:11.160145 TX Vref=28, minBit 10, minWin=26, winSum=434
2682 15:36:11.163499 TX Vref=30, minBit 8, minWin=26, winSum=433
2683 15:36:11.166754 TX Vref=32, minBit 5, minWin=26, winSum=435
2684 15:36:11.173684 [TxChooseVref] Worse bit 5, Min win 26, Win sum 435, Final Vref 32
2685 15:36:11.173768
2686 15:36:11.176990 Final TX Range 1 Vref 32
2687 15:36:11.177071
2688 15:36:11.177136 ==
2689 15:36:11.180446 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 15:36:11.183519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 15:36:11.183600 ==
2692 15:36:11.183665
2693 15:36:11.186436
2694 15:36:11.186517 TX Vref Scan disable
2695 15:36:11.190050 == TX Byte 0 ==
2696 15:36:11.193148 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2697 15:36:11.196564 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2698 15:36:11.199958 == TX Byte 1 ==
2699 15:36:11.203240 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2700 15:36:11.206502 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2701 15:36:11.206614
2702 15:36:11.210195 [DATLAT]
2703 15:36:11.210276 Freq=1200, CH0 RK0
2704 15:36:11.210341
2705 15:36:11.213248 DATLAT Default: 0xd
2706 15:36:11.213330 0, 0xFFFF, sum = 0
2707 15:36:11.216455 1, 0xFFFF, sum = 0
2708 15:36:11.216537 2, 0xFFFF, sum = 0
2709 15:36:11.219983 3, 0xFFFF, sum = 0
2710 15:36:11.220066 4, 0xFFFF, sum = 0
2711 15:36:11.223109 5, 0xFFFF, sum = 0
2712 15:36:11.223192 6, 0xFFFF, sum = 0
2713 15:36:11.226761 7, 0xFFFF, sum = 0
2714 15:36:11.230210 8, 0xFFFF, sum = 0
2715 15:36:11.230293 9, 0xFFFF, sum = 0
2716 15:36:11.233283 10, 0xFFFF, sum = 0
2717 15:36:11.233364 11, 0xFFFF, sum = 0
2718 15:36:11.236890 12, 0x0, sum = 1
2719 15:36:11.236972 13, 0x0, sum = 2
2720 15:36:11.240049 14, 0x0, sum = 3
2721 15:36:11.240132 15, 0x0, sum = 4
2722 15:36:11.240198 best_step = 13
2723 15:36:11.240258
2724 15:36:11.243496 ==
2725 15:36:11.246506 Dram Type= 6, Freq= 0, CH_0, rank 0
2726 15:36:11.250119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2727 15:36:11.250201 ==
2728 15:36:11.250265 RX Vref Scan: 1
2729 15:36:11.250325
2730 15:36:11.252989 Set Vref Range= 32 -> 127
2731 15:36:11.253071
2732 15:36:11.256410 RX Vref 32 -> 127, step: 1
2733 15:36:11.256491
2734 15:36:11.259677 RX Delay -21 -> 252, step: 4
2735 15:36:11.259757
2736 15:36:11.263281 Set Vref, RX VrefLevel [Byte0]: 32
2737 15:36:11.266492 [Byte1]: 32
2738 15:36:11.266622
2739 15:36:11.269565 Set Vref, RX VrefLevel [Byte0]: 33
2740 15:36:11.273009 [Byte1]: 33
2741 15:36:11.276198
2742 15:36:11.276278 Set Vref, RX VrefLevel [Byte0]: 34
2743 15:36:11.279724 [Byte1]: 34
2744 15:36:11.284099
2745 15:36:11.284204 Set Vref, RX VrefLevel [Byte0]: 35
2746 15:36:11.287289 [Byte1]: 35
2747 15:36:11.292053
2748 15:36:11.292133 Set Vref, RX VrefLevel [Byte0]: 36
2749 15:36:11.295572 [Byte1]: 36
2750 15:36:11.300221
2751 15:36:11.300302 Set Vref, RX VrefLevel [Byte0]: 37
2752 15:36:11.303665 [Byte1]: 37
2753 15:36:11.307744
2754 15:36:11.307824 Set Vref, RX VrefLevel [Byte0]: 38
2755 15:36:11.311425 [Byte1]: 38
2756 15:36:11.316311
2757 15:36:11.316391 Set Vref, RX VrefLevel [Byte0]: 39
2758 15:36:11.319026 [Byte1]: 39
2759 15:36:11.324032
2760 15:36:11.324113 Set Vref, RX VrefLevel [Byte0]: 40
2761 15:36:11.327724 [Byte1]: 40
2762 15:36:11.331995
2763 15:36:11.332076 Set Vref, RX VrefLevel [Byte0]: 41
2764 15:36:11.335530 [Byte1]: 41
2765 15:36:11.339834
2766 15:36:11.339915 Set Vref, RX VrefLevel [Byte0]: 42
2767 15:36:11.343226 [Byte1]: 42
2768 15:36:11.347957
2769 15:36:11.348038 Set Vref, RX VrefLevel [Byte0]: 43
2770 15:36:11.350976 [Byte1]: 43
2771 15:36:11.355655
2772 15:36:11.355735 Set Vref, RX VrefLevel [Byte0]: 44
2773 15:36:11.359160 [Byte1]: 44
2774 15:36:11.363668
2775 15:36:11.363771 Set Vref, RX VrefLevel [Byte0]: 45
2776 15:36:11.369922 [Byte1]: 45
2777 15:36:11.370003
2778 15:36:11.373577 Set Vref, RX VrefLevel [Byte0]: 46
2779 15:36:11.376318 [Byte1]: 46
2780 15:36:11.376400
2781 15:36:11.379940 Set Vref, RX VrefLevel [Byte0]: 47
2782 15:36:11.382932 [Byte1]: 47
2783 15:36:11.387197
2784 15:36:11.387277 Set Vref, RX VrefLevel [Byte0]: 48
2785 15:36:11.390879 [Byte1]: 48
2786 15:36:11.395072
2787 15:36:11.395153 Set Vref, RX VrefLevel [Byte0]: 49
2788 15:36:11.398484 [Byte1]: 49
2789 15:36:11.403414
2790 15:36:11.403495 Set Vref, RX VrefLevel [Byte0]: 50
2791 15:36:11.406542 [Byte1]: 50
2792 15:36:11.411000
2793 15:36:11.411080 Set Vref, RX VrefLevel [Byte0]: 51
2794 15:36:11.414206 [Byte1]: 51
2795 15:36:11.419162
2796 15:36:11.419243 Set Vref, RX VrefLevel [Byte0]: 52
2797 15:36:11.422310 [Byte1]: 52
2798 15:36:11.426931
2799 15:36:11.427009 Set Vref, RX VrefLevel [Byte0]: 53
2800 15:36:11.430382 [Byte1]: 53
2801 15:36:11.434979
2802 15:36:11.435052 Set Vref, RX VrefLevel [Byte0]: 54
2803 15:36:11.437973 [Byte1]: 54
2804 15:36:11.442555
2805 15:36:11.442684 Set Vref, RX VrefLevel [Byte0]: 55
2806 15:36:11.446212 [Byte1]: 55
2807 15:36:11.450693
2808 15:36:11.450768 Set Vref, RX VrefLevel [Byte0]: 56
2809 15:36:11.454318 [Byte1]: 56
2810 15:36:11.458439
2811 15:36:11.458520 Set Vref, RX VrefLevel [Byte0]: 57
2812 15:36:11.461984 [Byte1]: 57
2813 15:36:11.466516
2814 15:36:11.466655 Set Vref, RX VrefLevel [Byte0]: 58
2815 15:36:11.469819 [Byte1]: 58
2816 15:36:11.474260
2817 15:36:11.474340 Set Vref, RX VrefLevel [Byte0]: 59
2818 15:36:11.477933 [Byte1]: 59
2819 15:36:11.482714
2820 15:36:11.482795 Set Vref, RX VrefLevel [Byte0]: 60
2821 15:36:11.485612 [Byte1]: 60
2822 15:36:11.490265
2823 15:36:11.490345 Set Vref, RX VrefLevel [Byte0]: 61
2824 15:36:11.493806 [Byte1]: 61
2825 15:36:11.497968
2826 15:36:11.498048 Set Vref, RX VrefLevel [Byte0]: 62
2827 15:36:11.501496 [Byte1]: 62
2828 15:36:11.506371
2829 15:36:11.506451 Set Vref, RX VrefLevel [Byte0]: 63
2830 15:36:11.509612 [Byte1]: 63
2831 15:36:11.513778
2832 15:36:11.513863 Set Vref, RX VrefLevel [Byte0]: 64
2833 15:36:11.517701 [Byte1]: 64
2834 15:36:11.521903
2835 15:36:11.521983 Set Vref, RX VrefLevel [Byte0]: 65
2836 15:36:11.525330 [Byte1]: 65
2837 15:36:11.529803
2838 15:36:11.529934 Set Vref, RX VrefLevel [Byte0]: 66
2839 15:36:11.533472 [Byte1]: 66
2840 15:36:11.538025
2841 15:36:11.538105 Set Vref, RX VrefLevel [Byte0]: 67
2842 15:36:11.541366 [Byte1]: 67
2843 15:36:11.545752
2844 15:36:11.545832 Set Vref, RX VrefLevel [Byte0]: 68
2845 15:36:11.549001 [Byte1]: 68
2846 15:36:11.553893
2847 15:36:11.553973 Set Vref, RX VrefLevel [Byte0]: 69
2848 15:36:11.557662 [Byte1]: 69
2849 15:36:11.561502
2850 15:36:11.561583 Set Vref, RX VrefLevel [Byte0]: 70
2851 15:36:11.568060 [Byte1]: 70
2852 15:36:11.568141
2853 15:36:11.570992 Set Vref, RX VrefLevel [Byte0]: 71
2854 15:36:11.574342 [Byte1]: 71
2855 15:36:11.574423
2856 15:36:11.577797 Set Vref, RX VrefLevel [Byte0]: 72
2857 15:36:11.581268 [Byte1]: 72
2858 15:36:11.585440
2859 15:36:11.585520 Set Vref, RX VrefLevel [Byte0]: 73
2860 15:36:11.588973 [Byte1]: 73
2861 15:36:11.593046
2862 15:36:11.593126 Set Vref, RX VrefLevel [Byte0]: 74
2863 15:36:11.596762 [Byte1]: 74
2864 15:36:11.601550
2865 15:36:11.601631 Set Vref, RX VrefLevel [Byte0]: 75
2866 15:36:11.604456 [Byte1]: 75
2867 15:36:11.609102
2868 15:36:11.609183 Set Vref, RX VrefLevel [Byte0]: 76
2869 15:36:11.612412 [Byte1]: 76
2870 15:36:11.617491
2871 15:36:11.617573 Set Vref, RX VrefLevel [Byte0]: 77
2872 15:36:11.620364 [Byte1]: 77
2873 15:36:11.624993
2874 15:36:11.625074 Set Vref, RX VrefLevel [Byte0]: 78
2875 15:36:11.628005 [Byte1]: 78
2876 15:36:11.633021
2877 15:36:11.633101 Final RX Vref Byte 0 = 61 to rank0
2878 15:36:11.636372 Final RX Vref Byte 1 = 49 to rank0
2879 15:36:11.639504 Final RX Vref Byte 0 = 61 to rank1
2880 15:36:11.643127 Final RX Vref Byte 1 = 49 to rank1==
2881 15:36:11.646248 Dram Type= 6, Freq= 0, CH_0, rank 0
2882 15:36:11.652875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 15:36:11.652957 ==
2884 15:36:11.653021 DQS Delay:
2885 15:36:11.653082 DQS0 = 0, DQS1 = 0
2886 15:36:11.656564 DQM Delay:
2887 15:36:11.656645 DQM0 = 119, DQM1 = 106
2888 15:36:11.659869 DQ Delay:
2889 15:36:11.663138 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2890 15:36:11.666433 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =126
2891 15:36:11.669347 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2892 15:36:11.672656 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2893 15:36:11.672765
2894 15:36:11.672849
2895 15:36:11.679861 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 402 ps
2896 15:36:11.683077 CH0 RK0: MR19=403, MR18=13FF
2897 15:36:11.689600 CH0_RK0: MR19=0x403, MR18=0x13FF, DQSOSC=402, MR23=63, INC=40, DEC=27
2898 15:36:11.689684
2899 15:36:11.693061 ----->DramcWriteLeveling(PI) begin...
2900 15:36:11.693152 ==
2901 15:36:11.696053 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 15:36:11.699496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 15:36:11.703025 ==
2904 15:36:11.703106 Write leveling (Byte 0): 31 => 31
2905 15:36:11.705934 Write leveling (Byte 1): 31 => 31
2906 15:36:11.709482 DramcWriteLeveling(PI) end<-----
2907 15:36:11.709563
2908 15:36:11.709627 ==
2909 15:36:11.712969 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 15:36:11.719739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 15:36:11.719821 ==
2912 15:36:11.719887 [Gating] SW mode calibration
2913 15:36:11.729237 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2914 15:36:11.732710 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2915 15:36:11.739194 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
2916 15:36:11.742623 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
2917 15:36:11.745866 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 15:36:11.752717 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 15:36:11.755658 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 15:36:11.758928 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 15:36:11.765908 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 15:36:11.768799 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
2923 15:36:11.772135 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2924 15:36:11.779163 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 15:36:11.782021 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 15:36:11.785391 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 15:36:11.791924 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 15:36:11.795459 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 15:36:11.798315 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 15:36:11.805038 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2931 15:36:11.808546 1 1 0 | B1->B0 | 3635 4343 | 1 1 | (0 0) (0 0)
2932 15:36:11.811935 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 15:36:11.818431 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 15:36:11.822050 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 15:36:11.825077 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 15:36:11.828362 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 15:36:11.835403 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 15:36:11.838194 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2939 15:36:11.841936 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2940 15:36:11.848496 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 15:36:11.851899 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 15:36:11.854878 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 15:36:11.861581 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 15:36:11.864808 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 15:36:11.867972 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 15:36:11.874499 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 15:36:11.878228 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 15:36:11.881537 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 15:36:11.888220 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 15:36:11.891572 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 15:36:11.895049 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 15:36:11.901245 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 15:36:11.904749 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2954 15:36:11.908145 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2955 15:36:11.914884 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2956 15:36:11.914966 Total UI for P1: 0, mck2ui 16
2957 15:36:11.921397 best dqsien dly found for B0: ( 1, 3, 26)
2958 15:36:11.921478 Total UI for P1: 0, mck2ui 16
2959 15:36:11.927936 best dqsien dly found for B1: ( 1, 3, 28)
2960 15:36:11.931364 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2961 15:36:11.934341 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2962 15:36:11.934421
2963 15:36:11.938166 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2964 15:36:11.941156 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2965 15:36:11.944378 [Gating] SW calibration Done
2966 15:36:11.944460 ==
2967 15:36:11.947867 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 15:36:11.951066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 15:36:11.951148 ==
2970 15:36:11.954199 RX Vref Scan: 0
2971 15:36:11.954280
2972 15:36:11.954345 RX Vref 0 -> 0, step: 1
2973 15:36:11.954405
2974 15:36:11.957733 RX Delay -40 -> 252, step: 8
2975 15:36:11.961465 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2976 15:36:11.967827 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2977 15:36:11.970791 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2978 15:36:11.974574 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2979 15:36:11.977586 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2980 15:36:11.981136 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2981 15:36:11.987593 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2982 15:36:11.990626 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2983 15:36:11.994137 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2984 15:36:11.997591 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2985 15:36:12.000826 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2986 15:36:12.007759 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2987 15:36:12.010655 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2988 15:36:12.013988 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2989 15:36:12.017462 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2990 15:36:12.021001 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2991 15:36:12.023866 ==
2992 15:36:12.027595 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 15:36:12.031050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 15:36:12.031132 ==
2995 15:36:12.031197 DQS Delay:
2996 15:36:12.034124 DQS0 = 0, DQS1 = 0
2997 15:36:12.034205 DQM Delay:
2998 15:36:12.037465 DQM0 = 116, DQM1 = 108
2999 15:36:12.037546 DQ Delay:
3000 15:36:12.040470 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
3001 15:36:12.043787 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3002 15:36:12.047187 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3003 15:36:12.050466 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3004 15:36:12.050572
3005 15:36:12.050688
3006 15:36:12.050750 ==
3007 15:36:12.053847 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 15:36:12.060861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 15:36:12.060940 ==
3010 15:36:12.061002
3011 15:36:12.061059
3012 15:36:12.061115 TX Vref Scan disable
3013 15:36:12.064362 == TX Byte 0 ==
3014 15:36:12.067328 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3015 15:36:12.073973 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3016 15:36:12.074055 == TX Byte 1 ==
3017 15:36:12.077201 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3018 15:36:12.084118 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3019 15:36:12.084199 ==
3020 15:36:12.087192 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 15:36:12.090399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 15:36:12.090480 ==
3023 15:36:12.102213 TX Vref=22, minBit 4, minWin=25, winSum=416
3024 15:36:12.105626 TX Vref=24, minBit 5, minWin=25, winSum=421
3025 15:36:12.108353 TX Vref=26, minBit 4, minWin=26, winSum=429
3026 15:36:12.111631 TX Vref=28, minBit 1, minWin=26, winSum=432
3027 15:36:12.115184 TX Vref=30, minBit 4, minWin=26, winSum=433
3028 15:36:12.121772 TX Vref=32, minBit 9, minWin=26, winSum=431
3029 15:36:12.125093 [TxChooseVref] Worse bit 4, Min win 26, Win sum 433, Final Vref 30
3030 15:36:12.125175
3031 15:36:12.128346 Final TX Range 1 Vref 30
3032 15:36:12.128427
3033 15:36:12.128491 ==
3034 15:36:12.131602 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 15:36:12.135188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 15:36:12.135269 ==
3037 15:36:12.138152
3038 15:36:12.138232
3039 15:36:12.138296 TX Vref Scan disable
3040 15:36:12.141656 == TX Byte 0 ==
3041 15:36:12.145190 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3042 15:36:12.151841 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3043 15:36:12.151923 == TX Byte 1 ==
3044 15:36:12.155047 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3045 15:36:12.161514 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3046 15:36:12.161606
3047 15:36:12.161671 [DATLAT]
3048 15:36:12.161731 Freq=1200, CH0 RK1
3049 15:36:12.161789
3050 15:36:12.164809 DATLAT Default: 0xd
3051 15:36:12.164890 0, 0xFFFF, sum = 0
3052 15:36:12.168316 1, 0xFFFF, sum = 0
3053 15:36:12.168399 2, 0xFFFF, sum = 0
3054 15:36:12.172081 3, 0xFFFF, sum = 0
3055 15:36:12.174887 4, 0xFFFF, sum = 0
3056 15:36:12.174992 5, 0xFFFF, sum = 0
3057 15:36:12.178270 6, 0xFFFF, sum = 0
3058 15:36:12.178353 7, 0xFFFF, sum = 0
3059 15:36:12.181271 8, 0xFFFF, sum = 0
3060 15:36:12.181353 9, 0xFFFF, sum = 0
3061 15:36:12.185011 10, 0xFFFF, sum = 0
3062 15:36:12.185093 11, 0xFFFF, sum = 0
3063 15:36:12.188219 12, 0x0, sum = 1
3064 15:36:12.188301 13, 0x0, sum = 2
3065 15:36:12.191476 14, 0x0, sum = 3
3066 15:36:12.191559 15, 0x0, sum = 4
3067 15:36:12.191625 best_step = 13
3068 15:36:12.194521
3069 15:36:12.194667 ==
3070 15:36:12.197938 Dram Type= 6, Freq= 0, CH_0, rank 1
3071 15:36:12.201441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 15:36:12.201523 ==
3073 15:36:12.201587 RX Vref Scan: 0
3074 15:36:12.201647
3075 15:36:12.204830 RX Vref 0 -> 0, step: 1
3076 15:36:12.204911
3077 15:36:12.208048 RX Delay -21 -> 252, step: 4
3078 15:36:12.211590 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3079 15:36:12.217665 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3080 15:36:12.221361 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3081 15:36:12.224306 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3082 15:36:12.227835 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3083 15:36:12.230959 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3084 15:36:12.237971 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3085 15:36:12.241377 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3086 15:36:12.244363 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3087 15:36:12.247530 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3088 15:36:12.251187 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3089 15:36:12.257641 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3090 15:36:12.261135 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3091 15:36:12.264515 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3092 15:36:12.267681 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3093 15:36:12.274403 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3094 15:36:12.274486 ==
3095 15:36:12.277739 Dram Type= 6, Freq= 0, CH_0, rank 1
3096 15:36:12.281370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 15:36:12.281452 ==
3098 15:36:12.281516 DQS Delay:
3099 15:36:12.284325 DQS0 = 0, DQS1 = 0
3100 15:36:12.284406 DQM Delay:
3101 15:36:12.287993 DQM0 = 116, DQM1 = 107
3102 15:36:12.288073 DQ Delay:
3103 15:36:12.290648 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3104 15:36:12.294516 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3105 15:36:12.297784 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3106 15:36:12.301109 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3107 15:36:12.301190
3108 15:36:12.301254
3109 15:36:12.311010 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3110 15:36:12.314071 CH0 RK1: MR19=403, MR18=12EC
3111 15:36:12.317730 CH0_RK1: MR19=0x403, MR18=0x12EC, DQSOSC=403, MR23=63, INC=40, DEC=26
3112 15:36:12.320849 [RxdqsGatingPostProcess] freq 1200
3113 15:36:12.327253 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3114 15:36:12.330413 best DQS0 dly(2T, 0.5T) = (0, 11)
3115 15:36:12.333838 best DQS1 dly(2T, 0.5T) = (0, 12)
3116 15:36:12.337319 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3117 15:36:12.340555 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3118 15:36:12.344051 best DQS0 dly(2T, 0.5T) = (0, 11)
3119 15:36:12.347340 best DQS1 dly(2T, 0.5T) = (0, 11)
3120 15:36:12.350510 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3121 15:36:12.353777 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3122 15:36:12.357312 Pre-setting of DQS Precalculation
3123 15:36:12.360383 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3124 15:36:12.360464 ==
3125 15:36:12.363652 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 15:36:12.367170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 15:36:12.367251 ==
3128 15:36:12.373570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3129 15:36:12.380680 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3130 15:36:12.388050 [CA 0] Center 37 (8~67) winsize 60
3131 15:36:12.390987 [CA 1] Center 37 (7~68) winsize 62
3132 15:36:12.394824 [CA 2] Center 34 (4~65) winsize 62
3133 15:36:12.398164 [CA 3] Center 33 (3~64) winsize 62
3134 15:36:12.401000 [CA 4] Center 34 (5~64) winsize 60
3135 15:36:12.404519 [CA 5] Center 33 (3~64) winsize 62
3136 15:36:12.404600
3137 15:36:12.408153 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3138 15:36:12.408234
3139 15:36:12.411461 [CATrainingPosCal] consider 1 rank data
3140 15:36:12.414792 u2DelayCellTimex100 = 270/100 ps
3141 15:36:12.417612 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3142 15:36:12.424549 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3143 15:36:12.427625 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3144 15:36:12.430535 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3145 15:36:12.434294 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3146 15:36:12.437574 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3147 15:36:12.437655
3148 15:36:12.440754 CA PerBit enable=1, Macro0, CA PI delay=33
3149 15:36:12.440835
3150 15:36:12.443837 [CBTSetCACLKResult] CA Dly = 33
3151 15:36:12.447230 CS Dly: 6 (0~37)
3152 15:36:12.447311 ==
3153 15:36:12.450877 Dram Type= 6, Freq= 0, CH_1, rank 1
3154 15:36:12.454248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3155 15:36:12.454330 ==
3156 15:36:12.460455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3157 15:36:12.464038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3158 15:36:12.473683 [CA 0] Center 37 (7~68) winsize 62
3159 15:36:12.476763 [CA 1] Center 38 (8~68) winsize 61
3160 15:36:12.480629 [CA 2] Center 34 (3~65) winsize 63
3161 15:36:12.483413 [CA 3] Center 33 (3~64) winsize 62
3162 15:36:12.487100 [CA 4] Center 34 (3~65) winsize 63
3163 15:36:12.490208 [CA 5] Center 33 (3~64) winsize 62
3164 15:36:12.490288
3165 15:36:12.493624 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3166 15:36:12.493705
3167 15:36:12.497112 [CATrainingPosCal] consider 2 rank data
3168 15:36:12.500031 u2DelayCellTimex100 = 270/100 ps
3169 15:36:12.503371 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3170 15:36:12.510416 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3171 15:36:12.513563 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3172 15:36:12.516753 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3173 15:36:12.520309 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3174 15:36:12.523156 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3175 15:36:12.523237
3176 15:36:12.526336 CA PerBit enable=1, Macro0, CA PI delay=33
3177 15:36:12.526417
3178 15:36:12.529852 [CBTSetCACLKResult] CA Dly = 33
3179 15:36:12.533394 CS Dly: 7 (0~40)
3180 15:36:12.533475
3181 15:36:12.536786 ----->DramcWriteLeveling(PI) begin...
3182 15:36:12.536867 ==
3183 15:36:12.539722 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 15:36:12.543167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 15:36:12.543249 ==
3186 15:36:12.546714 Write leveling (Byte 0): 24 => 24
3187 15:36:12.549687 Write leveling (Byte 1): 27 => 27
3188 15:36:12.553124 DramcWriteLeveling(PI) end<-----
3189 15:36:12.553205
3190 15:36:12.553269 ==
3191 15:36:12.555960 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 15:36:12.559702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 15:36:12.559783 ==
3194 15:36:12.562615 [Gating] SW mode calibration
3195 15:36:12.569596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3196 15:36:12.576213 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3197 15:36:12.579313 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
3198 15:36:12.583161 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 15:36:12.589552 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 15:36:12.592784 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 15:36:12.596204 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 15:36:12.602521 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 15:36:12.605737 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
3204 15:36:12.609356 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3205 15:36:12.615803 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 15:36:12.619030 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 15:36:12.622488 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 15:36:12.628882 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 15:36:12.632451 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 15:36:12.635908 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 15:36:12.641941 1 0 24 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
3212 15:36:12.645456 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3213 15:36:12.648671 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 15:36:12.655247 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 15:36:12.658834 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 15:36:12.662461 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 15:36:12.668712 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 15:36:12.672484 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 15:36:12.675189 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3220 15:36:12.682176 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3221 15:36:12.685563 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 15:36:12.688363 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 15:36:12.695024 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 15:36:12.698189 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 15:36:12.701747 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 15:36:12.708567 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 15:36:12.711804 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 15:36:12.714999 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 15:36:12.721613 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 15:36:12.725132 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 15:36:12.728065 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 15:36:12.734858 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 15:36:12.737988 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 15:36:12.741591 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 15:36:12.748085 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3236 15:36:12.751389 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3237 15:36:12.755008 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 15:36:12.758070 Total UI for P1: 0, mck2ui 16
3239 15:36:12.761054 best dqsien dly found for B0: ( 1, 3, 26)
3240 15:36:12.764621 Total UI for P1: 0, mck2ui 16
3241 15:36:12.768144 best dqsien dly found for B1: ( 1, 3, 28)
3242 15:36:12.771007 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3243 15:36:12.774492 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3244 15:36:12.774573
3245 15:36:12.778107 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3246 15:36:12.784572 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3247 15:36:12.784653 [Gating] SW calibration Done
3248 15:36:12.784717 ==
3249 15:36:12.787669 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 15:36:12.794527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 15:36:12.794614 ==
3252 15:36:12.794679 RX Vref Scan: 0
3253 15:36:12.794738
3254 15:36:12.797412 RX Vref 0 -> 0, step: 1
3255 15:36:12.797493
3256 15:36:12.800613 RX Delay -40 -> 252, step: 8
3257 15:36:12.804125 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3258 15:36:12.807807 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3259 15:36:12.811071 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3260 15:36:12.817674 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3261 15:36:12.820789 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3262 15:36:12.824267 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3263 15:36:12.827610 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3264 15:36:12.830722 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3265 15:36:12.837740 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3266 15:36:12.840620 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3267 15:36:12.844101 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3268 15:36:12.847513 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3269 15:36:12.850472 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3270 15:36:12.857420 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3271 15:36:12.860887 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3272 15:36:12.863755 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3273 15:36:12.863836 ==
3274 15:36:12.867069 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 15:36:12.870740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 15:36:12.870847 ==
3277 15:36:12.873707 DQS Delay:
3278 15:36:12.873788 DQS0 = 0, DQS1 = 0
3279 15:36:12.877190 DQM Delay:
3280 15:36:12.877269 DQM0 = 119, DQM1 = 110
3281 15:36:12.877333 DQ Delay:
3282 15:36:12.883919 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3283 15:36:12.887424 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3284 15:36:12.890227 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =99
3285 15:36:12.893810 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3286 15:36:12.893917
3287 15:36:12.894014
3288 15:36:12.894113 ==
3289 15:36:12.896816 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 15:36:12.900008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 15:36:12.900123 ==
3292 15:36:12.900226
3293 15:36:12.900322
3294 15:36:12.903651 TX Vref Scan disable
3295 15:36:12.906708 == TX Byte 0 ==
3296 15:36:12.910267 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3297 15:36:12.913352 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3298 15:36:12.916911 == TX Byte 1 ==
3299 15:36:12.920286 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3300 15:36:12.923245 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3301 15:36:12.923327 ==
3302 15:36:12.926769 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 15:36:12.930139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 15:36:12.933252 ==
3305 15:36:12.943150 TX Vref=22, minBit 10, minWin=25, winSum=420
3306 15:36:12.946849 TX Vref=24, minBit 10, minWin=25, winSum=425
3307 15:36:12.950386 TX Vref=26, minBit 10, minWin=25, winSum=431
3308 15:36:12.953367 TX Vref=28, minBit 3, minWin=26, winSum=429
3309 15:36:12.957052 TX Vref=30, minBit 9, minWin=26, winSum=429
3310 15:36:12.963488 TX Vref=32, minBit 3, minWin=26, winSum=426
3311 15:36:12.966486 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 28
3312 15:36:12.966568
3313 15:36:12.969928 Final TX Range 1 Vref 28
3314 15:36:12.970009
3315 15:36:12.970077 ==
3316 15:36:12.973174 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 15:36:12.976531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 15:36:12.979485 ==
3319 15:36:12.979565
3320 15:36:12.979629
3321 15:36:12.979688 TX Vref Scan disable
3322 15:36:12.983767 == TX Byte 0 ==
3323 15:36:12.986769 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3324 15:36:12.990133 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3325 15:36:12.993803 == TX Byte 1 ==
3326 15:36:12.997161 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3327 15:36:13.000126 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3328 15:36:13.003101
3329 15:36:13.003199 [DATLAT]
3330 15:36:13.003287 Freq=1200, CH1 RK0
3331 15:36:13.003374
3332 15:36:13.006597 DATLAT Default: 0xd
3333 15:36:13.006678 0, 0xFFFF, sum = 0
3334 15:36:13.010239 1, 0xFFFF, sum = 0
3335 15:36:13.010321 2, 0xFFFF, sum = 0
3336 15:36:13.013239 3, 0xFFFF, sum = 0
3337 15:36:13.016618 4, 0xFFFF, sum = 0
3338 15:36:13.016699 5, 0xFFFF, sum = 0
3339 15:36:13.020233 6, 0xFFFF, sum = 0
3340 15:36:13.020347 7, 0xFFFF, sum = 0
3341 15:36:13.023256 8, 0xFFFF, sum = 0
3342 15:36:13.023338 9, 0xFFFF, sum = 0
3343 15:36:13.026556 10, 0xFFFF, sum = 0
3344 15:36:13.026646 11, 0xFFFF, sum = 0
3345 15:36:13.029913 12, 0x0, sum = 1
3346 15:36:13.029994 13, 0x0, sum = 2
3347 15:36:13.033047 14, 0x0, sum = 3
3348 15:36:13.033156 15, 0x0, sum = 4
3349 15:36:13.033225 best_step = 13
3350 15:36:13.036775
3351 15:36:13.036855 ==
3352 15:36:13.040122 Dram Type= 6, Freq= 0, CH_1, rank 0
3353 15:36:13.043171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3354 15:36:13.043251 ==
3355 15:36:13.043315 RX Vref Scan: 1
3356 15:36:13.043374
3357 15:36:13.046834 Set Vref Range= 32 -> 127
3358 15:36:13.046914
3359 15:36:13.050178 RX Vref 32 -> 127, step: 1
3360 15:36:13.050258
3361 15:36:13.053200 RX Delay -21 -> 252, step: 4
3362 15:36:13.053280
3363 15:36:13.056227 Set Vref, RX VrefLevel [Byte0]: 32
3364 15:36:13.059975 [Byte1]: 32
3365 15:36:13.060056
3366 15:36:13.063287 Set Vref, RX VrefLevel [Byte0]: 33
3367 15:36:13.066651 [Byte1]: 33
3368 15:36:13.069999
3369 15:36:13.070079 Set Vref, RX VrefLevel [Byte0]: 34
3370 15:36:13.073373 [Byte1]: 34
3371 15:36:13.077720
3372 15:36:13.077799 Set Vref, RX VrefLevel [Byte0]: 35
3373 15:36:13.081393 [Byte1]: 35
3374 15:36:13.085734
3375 15:36:13.085840 Set Vref, RX VrefLevel [Byte0]: 36
3376 15:36:13.088716 [Byte1]: 36
3377 15:36:13.093425
3378 15:36:13.093500 Set Vref, RX VrefLevel [Byte0]: 37
3379 15:36:13.096915 [Byte1]: 37
3380 15:36:13.101771
3381 15:36:13.101851 Set Vref, RX VrefLevel [Byte0]: 38
3382 15:36:13.104641 [Byte1]: 38
3383 15:36:13.109411
3384 15:36:13.109486 Set Vref, RX VrefLevel [Byte0]: 39
3385 15:36:13.112911 [Byte1]: 39
3386 15:36:13.117185
3387 15:36:13.120651 Set Vref, RX VrefLevel [Byte0]: 40
3388 15:36:13.123584 [Byte1]: 40
3389 15:36:13.123681
3390 15:36:13.127108 Set Vref, RX VrefLevel [Byte0]: 41
3391 15:36:13.130155 [Byte1]: 41
3392 15:36:13.130225
3393 15:36:13.134187 Set Vref, RX VrefLevel [Byte0]: 42
3394 15:36:13.137314 [Byte1]: 42
3395 15:36:13.141091
3396 15:36:13.141161 Set Vref, RX VrefLevel [Byte0]: 43
3397 15:36:13.144451 [Byte1]: 43
3398 15:36:13.148705
3399 15:36:13.148787 Set Vref, RX VrefLevel [Byte0]: 44
3400 15:36:13.152437 [Byte1]: 44
3401 15:36:13.157113
3402 15:36:13.157194 Set Vref, RX VrefLevel [Byte0]: 45
3403 15:36:13.160343 [Byte1]: 45
3404 15:36:13.164848
3405 15:36:13.164929 Set Vref, RX VrefLevel [Byte0]: 46
3406 15:36:13.168244 [Byte1]: 46
3407 15:36:13.172641
3408 15:36:13.172742 Set Vref, RX VrefLevel [Byte0]: 47
3409 15:36:13.175920 [Byte1]: 47
3410 15:36:13.180754
3411 15:36:13.180854 Set Vref, RX VrefLevel [Byte0]: 48
3412 15:36:13.184169 [Byte1]: 48
3413 15:36:13.189083
3414 15:36:13.189157 Set Vref, RX VrefLevel [Byte0]: 49
3415 15:36:13.191731 [Byte1]: 49
3416 15:36:13.196626
3417 15:36:13.196732 Set Vref, RX VrefLevel [Byte0]: 50
3418 15:36:13.200145 [Byte1]: 50
3419 15:36:13.204154
3420 15:36:13.204235 Set Vref, RX VrefLevel [Byte0]: 51
3421 15:36:13.207886 [Byte1]: 51
3422 15:36:13.212513
3423 15:36:13.212593 Set Vref, RX VrefLevel [Byte0]: 52
3424 15:36:13.215323 [Byte1]: 52
3425 15:36:13.220122
3426 15:36:13.220203 Set Vref, RX VrefLevel [Byte0]: 53
3427 15:36:13.223583 [Byte1]: 53
3428 15:36:13.228516
3429 15:36:13.228613 Set Vref, RX VrefLevel [Byte0]: 54
3430 15:36:13.231481 [Byte1]: 54
3431 15:36:13.236220
3432 15:36:13.236300 Set Vref, RX VrefLevel [Byte0]: 55
3433 15:36:13.239655 [Byte1]: 55
3434 15:36:13.244112
3435 15:36:13.244193 Set Vref, RX VrefLevel [Byte0]: 56
3436 15:36:13.247335 [Byte1]: 56
3437 15:36:13.251844
3438 15:36:13.251921 Set Vref, RX VrefLevel [Byte0]: 57
3439 15:36:13.254999 [Byte1]: 57
3440 15:36:13.259898
3441 15:36:13.260008 Set Vref, RX VrefLevel [Byte0]: 58
3442 15:36:13.263346 [Byte1]: 58
3443 15:36:13.268088
3444 15:36:13.268186 Set Vref, RX VrefLevel [Byte0]: 59
3445 15:36:13.270899 [Byte1]: 59
3446 15:36:13.275723
3447 15:36:13.275804 Set Vref, RX VrefLevel [Byte0]: 60
3448 15:36:13.279049 [Byte1]: 60
3449 15:36:13.283394
3450 15:36:13.283466 Set Vref, RX VrefLevel [Byte0]: 61
3451 15:36:13.286911 [Byte1]: 61
3452 15:36:13.291253
3453 15:36:13.291350 Set Vref, RX VrefLevel [Byte0]: 62
3454 15:36:13.294536 [Byte1]: 62
3455 15:36:13.299773
3456 15:36:13.299874 Set Vref, RX VrefLevel [Byte0]: 63
3457 15:36:13.302971 [Byte1]: 63
3458 15:36:13.307527
3459 15:36:13.307600 Set Vref, RX VrefLevel [Byte0]: 64
3460 15:36:13.311043 [Byte1]: 64
3461 15:36:13.315426
3462 15:36:13.315514 Set Vref, RX VrefLevel [Byte0]: 65
3463 15:36:13.318390 [Byte1]: 65
3464 15:36:13.323044
3465 15:36:13.323142 Set Vref, RX VrefLevel [Byte0]: 66
3466 15:36:13.326470 [Byte1]: 66
3467 15:36:13.330948
3468 15:36:13.331046 Set Vref, RX VrefLevel [Byte0]: 67
3469 15:36:13.334490 [Byte1]: 67
3470 15:36:13.339449
3471 15:36:13.339571 Set Vref, RX VrefLevel [Byte0]: 68
3472 15:36:13.342434 [Byte1]: 68
3473 15:36:13.346727
3474 15:36:13.346818 Final RX Vref Byte 0 = 48 to rank0
3475 15:36:13.350253 Final RX Vref Byte 1 = 53 to rank0
3476 15:36:13.353768 Final RX Vref Byte 0 = 48 to rank1
3477 15:36:13.357089 Final RX Vref Byte 1 = 53 to rank1==
3478 15:36:13.360524 Dram Type= 6, Freq= 0, CH_1, rank 0
3479 15:36:13.366779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 15:36:13.366893 ==
3481 15:36:13.366966 DQS Delay:
3482 15:36:13.367026 DQS0 = 0, DQS1 = 0
3483 15:36:13.370268 DQM Delay:
3484 15:36:13.370365 DQM0 = 117, DQM1 = 112
3485 15:36:13.373520 DQ Delay:
3486 15:36:13.376882 DQ0 =120, DQ1 =112, DQ2 =110, DQ3 =112
3487 15:36:13.379923 DQ4 =116, DQ5 =128, DQ6 =128, DQ7 =114
3488 15:36:13.383430 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =100
3489 15:36:13.387049 DQ12 =120, DQ13 =120, DQ14 =122, DQ15 =120
3490 15:36:13.387131
3491 15:36:13.387195
3492 15:36:13.396840 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3493 15:36:13.396993 CH1 RK0: MR19=403, MR18=3F6
3494 15:36:13.402982 CH1_RK0: MR19=0x403, MR18=0x3F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3495 15:36:13.403068
3496 15:36:13.406307 ----->DramcWriteLeveling(PI) begin...
3497 15:36:13.406381 ==
3498 15:36:13.409734 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 15:36:13.416408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 15:36:13.416511 ==
3501 15:36:13.419649 Write leveling (Byte 0): 24 => 24
3502 15:36:13.419724 Write leveling (Byte 1): 28 => 28
3503 15:36:13.422675 DramcWriteLeveling(PI) end<-----
3504 15:36:13.422772
3505 15:36:13.426077 ==
3506 15:36:13.426173 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 15:36:13.433226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 15:36:13.433326 ==
3509 15:36:13.436138 [Gating] SW mode calibration
3510 15:36:13.442569 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3511 15:36:13.446230 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3512 15:36:13.452558 0 15 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3513 15:36:13.455859 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 15:36:13.458860 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 15:36:13.465690 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 15:36:13.469124 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 15:36:13.472679 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 15:36:13.479059 0 15 24 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 0)
3519 15:36:13.482264 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3520 15:36:13.485534 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 15:36:13.491922 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 15:36:13.495588 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 15:36:13.498882 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 15:36:13.505436 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 15:36:13.508917 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 15:36:13.512036 1 0 24 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
3527 15:36:13.518717 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 15:36:13.522019 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3529 15:36:13.525115 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 15:36:13.531909 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 15:36:13.535304 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 15:36:13.538359 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 15:36:13.545657 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 15:36:13.548429 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3535 15:36:13.552025 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3536 15:36:13.558472 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 15:36:13.561606 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 15:36:13.565023 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 15:36:13.571468 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 15:36:13.574941 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 15:36:13.577817 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 15:36:13.584407 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 15:36:13.587702 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 15:36:13.591344 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 15:36:13.597786 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 15:36:13.601423 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 15:36:13.604439 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 15:36:13.610969 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 15:36:13.614334 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 15:36:13.617798 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3551 15:36:13.624068 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3552 15:36:13.627413 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 15:36:13.630613 Total UI for P1: 0, mck2ui 16
3554 15:36:13.634173 best dqsien dly found for B0: ( 1, 3, 26)
3555 15:36:13.637409 Total UI for P1: 0, mck2ui 16
3556 15:36:13.640691 best dqsien dly found for B1: ( 1, 3, 26)
3557 15:36:13.644054 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3558 15:36:13.647362 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3559 15:36:13.647444
3560 15:36:13.650787 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3561 15:36:13.653808 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3562 15:36:13.657299 [Gating] SW calibration Done
3563 15:36:13.657413 ==
3564 15:36:13.660242 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 15:36:13.663695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 15:36:13.667152 ==
3567 15:36:13.667228 RX Vref Scan: 0
3568 15:36:13.667291
3569 15:36:13.670699 RX Vref 0 -> 0, step: 1
3570 15:36:13.670813
3571 15:36:13.673644 RX Delay -40 -> 252, step: 8
3572 15:36:13.676689 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3573 15:36:13.680217 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3574 15:36:13.683084 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3575 15:36:13.686619 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3576 15:36:13.693234 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3577 15:36:13.696715 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3578 15:36:13.699994 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3579 15:36:13.703148 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3580 15:36:13.706475 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3581 15:36:13.713243 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3582 15:36:13.716119 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3583 15:36:13.719647 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3584 15:36:13.723019 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3585 15:36:13.729391 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3586 15:36:13.732846 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3587 15:36:13.736168 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3588 15:36:13.736264 ==
3589 15:36:13.739645 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 15:36:13.742810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 15:36:13.742914 ==
3592 15:36:13.746126 DQS Delay:
3593 15:36:13.746203 DQS0 = 0, DQS1 = 0
3594 15:36:13.749113 DQM Delay:
3595 15:36:13.749210 DQM0 = 117, DQM1 = 110
3596 15:36:13.752956 DQ Delay:
3597 15:36:13.756022 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3598 15:36:13.759228 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3599 15:36:13.762445 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3600 15:36:13.766301 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3601 15:36:13.766382
3602 15:36:13.766461
3603 15:36:13.766521 ==
3604 15:36:13.769106 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 15:36:13.772185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 15:36:13.772268 ==
3607 15:36:13.772332
3608 15:36:13.772392
3609 15:36:13.775800 TX Vref Scan disable
3610 15:36:13.778675 == TX Byte 0 ==
3611 15:36:13.782221 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3612 15:36:13.785821 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3613 15:36:13.788774 == TX Byte 1 ==
3614 15:36:13.792251 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3615 15:36:13.795365 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3616 15:36:13.795463 ==
3617 15:36:13.798907 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 15:36:13.805118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 15:36:13.805222 ==
3620 15:36:13.816019 TX Vref=22, minBit 0, minWin=26, winSum=425
3621 15:36:13.819346 TX Vref=24, minBit 1, minWin=26, winSum=426
3622 15:36:13.822318 TX Vref=26, minBit 1, minWin=26, winSum=434
3623 15:36:13.825694 TX Vref=28, minBit 0, minWin=27, winSum=433
3624 15:36:13.829399 TX Vref=30, minBit 11, minWin=26, winSum=432
3625 15:36:13.835420 TX Vref=32, minBit 1, minWin=26, winSum=428
3626 15:36:13.838803 [TxChooseVref] Worse bit 0, Min win 27, Win sum 433, Final Vref 28
3627 15:36:13.838885
3628 15:36:13.841987 Final TX Range 1 Vref 28
3629 15:36:13.842069
3630 15:36:13.842137 ==
3631 15:36:13.845429 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 15:36:13.849048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 15:36:13.852362 ==
3634 15:36:13.852475
3635 15:36:13.852542
3636 15:36:13.852605 TX Vref Scan disable
3637 15:36:13.856021 == TX Byte 0 ==
3638 15:36:13.858794 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3639 15:36:13.865721 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3640 15:36:13.865843 == TX Byte 1 ==
3641 15:36:13.869189 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3642 15:36:13.875750 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3643 15:36:13.875840
3644 15:36:13.875904 [DATLAT]
3645 15:36:13.875965 Freq=1200, CH1 RK1
3646 15:36:13.876023
3647 15:36:13.878910 DATLAT Default: 0xd
3648 15:36:13.882259 0, 0xFFFF, sum = 0
3649 15:36:13.882350 1, 0xFFFF, sum = 0
3650 15:36:13.885361 2, 0xFFFF, sum = 0
3651 15:36:13.885437 3, 0xFFFF, sum = 0
3652 15:36:13.888709 4, 0xFFFF, sum = 0
3653 15:36:13.888784 5, 0xFFFF, sum = 0
3654 15:36:13.892205 6, 0xFFFF, sum = 0
3655 15:36:13.892276 7, 0xFFFF, sum = 0
3656 15:36:13.895084 8, 0xFFFF, sum = 0
3657 15:36:13.895153 9, 0xFFFF, sum = 0
3658 15:36:13.898726 10, 0xFFFF, sum = 0
3659 15:36:13.898840 11, 0xFFFF, sum = 0
3660 15:36:13.901731 12, 0x0, sum = 1
3661 15:36:13.901800 13, 0x0, sum = 2
3662 15:36:13.905250 14, 0x0, sum = 3
3663 15:36:13.905333 15, 0x0, sum = 4
3664 15:36:13.908903 best_step = 13
3665 15:36:13.908971
3666 15:36:13.909030 ==
3667 15:36:13.911722 Dram Type= 6, Freq= 0, CH_1, rank 1
3668 15:36:13.914804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3669 15:36:13.914875 ==
3670 15:36:13.918474 RX Vref Scan: 0
3671 15:36:13.918545
3672 15:36:13.918636 RX Vref 0 -> 0, step: 1
3673 15:36:13.918695
3674 15:36:13.921594 RX Delay -21 -> 252, step: 4
3675 15:36:13.928503 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3676 15:36:13.931683 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3677 15:36:13.934801 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3678 15:36:13.938261 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3679 15:36:13.941409 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3680 15:36:13.948171 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3681 15:36:13.951665 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3682 15:36:13.955147 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3683 15:36:13.958224 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3684 15:36:13.961356 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3685 15:36:13.968353 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3686 15:36:13.971654 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3687 15:36:13.974538 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3688 15:36:13.978100 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3689 15:36:13.981615 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3690 15:36:13.987750 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3691 15:36:13.987836 ==
3692 15:36:13.991030 Dram Type= 6, Freq= 0, CH_1, rank 1
3693 15:36:13.994456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3694 15:36:13.994555 ==
3695 15:36:13.994662 DQS Delay:
3696 15:36:13.998327 DQS0 = 0, DQS1 = 0
3697 15:36:13.998407 DQM Delay:
3698 15:36:14.001191 DQM0 = 117, DQM1 = 110
3699 15:36:14.001282 DQ Delay:
3700 15:36:14.004848 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3701 15:36:14.007775 DQ4 =116, DQ5 =128, DQ6 =130, DQ7 =116
3702 15:36:14.011179 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =100
3703 15:36:14.014738 DQ12 =120, DQ13 =118, DQ14 =120, DQ15 =118
3704 15:36:14.014818
3705 15:36:14.017815
3706 15:36:14.024230 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3707 15:36:14.027819 CH1 RK1: MR19=303, MR18=F3EF
3708 15:36:14.034327 CH1_RK1: MR19=0x303, MR18=0xF3EF, DQSOSC=415, MR23=63, INC=38, DEC=25
3709 15:36:14.037617 [RxdqsGatingPostProcess] freq 1200
3710 15:36:14.040902 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3711 15:36:14.043918 best DQS0 dly(2T, 0.5T) = (0, 11)
3712 15:36:14.047452 best DQS1 dly(2T, 0.5T) = (0, 11)
3713 15:36:14.050773 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3714 15:36:14.054329 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3715 15:36:14.057260 best DQS0 dly(2T, 0.5T) = (0, 11)
3716 15:36:14.060797 best DQS1 dly(2T, 0.5T) = (0, 11)
3717 15:36:14.064168 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3718 15:36:14.067428 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3719 15:36:14.070653 Pre-setting of DQS Precalculation
3720 15:36:14.073668 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3721 15:36:14.084198 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3722 15:36:14.090505 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3723 15:36:14.090641
3724 15:36:14.090733
3725 15:36:14.093801 [Calibration Summary] 2400 Mbps
3726 15:36:14.093882 CH 0, Rank 0
3727 15:36:14.096752 SW Impedance : PASS
3728 15:36:14.096834 DUTY Scan : NO K
3729 15:36:14.099986 ZQ Calibration : PASS
3730 15:36:14.103494 Jitter Meter : NO K
3731 15:36:14.103597 CBT Training : PASS
3732 15:36:14.106684 Write leveling : PASS
3733 15:36:14.110322 RX DQS gating : PASS
3734 15:36:14.110403 RX DQ/DQS(RDDQC) : PASS
3735 15:36:14.113184 TX DQ/DQS : PASS
3736 15:36:14.116714 RX DATLAT : PASS
3737 15:36:14.116812 RX DQ/DQS(Engine): PASS
3738 15:36:14.119940 TX OE : NO K
3739 15:36:14.120051 All Pass.
3740 15:36:14.120187
3741 15:36:14.123494 CH 0, Rank 1
3742 15:36:14.123575 SW Impedance : PASS
3743 15:36:14.126901 DUTY Scan : NO K
3744 15:36:14.129840 ZQ Calibration : PASS
3745 15:36:14.129921 Jitter Meter : NO K
3746 15:36:14.132926 CBT Training : PASS
3747 15:36:14.136307 Write leveling : PASS
3748 15:36:14.136387 RX DQS gating : PASS
3749 15:36:14.139955 RX DQ/DQS(RDDQC) : PASS
3750 15:36:14.140036 TX DQ/DQS : PASS
3751 15:36:14.143044 RX DATLAT : PASS
3752 15:36:14.146440 RX DQ/DQS(Engine): PASS
3753 15:36:14.146576 TX OE : NO K
3754 15:36:14.149986 All Pass.
3755 15:36:14.150067
3756 15:36:14.150169 CH 1, Rank 0
3757 15:36:14.153107 SW Impedance : PASS
3758 15:36:14.153229 DUTY Scan : NO K
3759 15:36:14.156362 ZQ Calibration : PASS
3760 15:36:14.159496 Jitter Meter : NO K
3761 15:36:14.159578 CBT Training : PASS
3762 15:36:14.162849 Write leveling : PASS
3763 15:36:14.166025 RX DQS gating : PASS
3764 15:36:14.166107 RX DQ/DQS(RDDQC) : PASS
3765 15:36:14.169701 TX DQ/DQS : PASS
3766 15:36:14.173173 RX DATLAT : PASS
3767 15:36:14.173277 RX DQ/DQS(Engine): PASS
3768 15:36:14.175960 TX OE : NO K
3769 15:36:14.176034 All Pass.
3770 15:36:14.176111
3771 15:36:14.179373 CH 1, Rank 1
3772 15:36:14.179446 SW Impedance : PASS
3773 15:36:14.182624 DUTY Scan : NO K
3774 15:36:14.186196 ZQ Calibration : PASS
3775 15:36:14.186308 Jitter Meter : NO K
3776 15:36:14.189008 CBT Training : PASS
3777 15:36:14.193101 Write leveling : PASS
3778 15:36:14.193202 RX DQS gating : PASS
3779 15:36:14.196015 RX DQ/DQS(RDDQC) : PASS
3780 15:36:14.199718 TX DQ/DQS : PASS
3781 15:36:14.199807 RX DATLAT : PASS
3782 15:36:14.202752 RX DQ/DQS(Engine): PASS
3783 15:36:14.202833 TX OE : NO K
3784 15:36:14.206095 All Pass.
3785 15:36:14.206202
3786 15:36:14.206287 DramC Write-DBI off
3787 15:36:14.209264 PER_BANK_REFRESH: Hybrid Mode
3788 15:36:14.212961 TX_TRACKING: ON
3789 15:36:14.219170 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3790 15:36:14.222577 [FAST_K] Save calibration result to emmc
3791 15:36:14.229455 dramc_set_vcore_voltage set vcore to 650000
3792 15:36:14.229546 Read voltage for 600, 5
3793 15:36:14.229610 Vio18 = 0
3794 15:36:14.232830 Vcore = 650000
3795 15:36:14.232911 Vdram = 0
3796 15:36:14.232976 Vddq = 0
3797 15:36:14.235641 Vmddr = 0
3798 15:36:14.239257 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3799 15:36:14.245760 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3800 15:36:14.248777 MEM_TYPE=3, freq_sel=19
3801 15:36:14.248859 sv_algorithm_assistance_LP4_1600
3802 15:36:14.255226 ============ PULL DRAM RESETB DOWN ============
3803 15:36:14.258772 ========== PULL DRAM RESETB DOWN end =========
3804 15:36:14.262043 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3805 15:36:14.265681 ===================================
3806 15:36:14.269009 LPDDR4 DRAM CONFIGURATION
3807 15:36:14.272073 ===================================
3808 15:36:14.275350 EX_ROW_EN[0] = 0x0
3809 15:36:14.275472 EX_ROW_EN[1] = 0x0
3810 15:36:14.278610 LP4Y_EN = 0x0
3811 15:36:14.278704 WORK_FSP = 0x0
3812 15:36:14.282282 WL = 0x2
3813 15:36:14.282363 RL = 0x2
3814 15:36:14.285271 BL = 0x2
3815 15:36:14.285352 RPST = 0x0
3816 15:36:14.288398 RD_PRE = 0x0
3817 15:36:14.288480 WR_PRE = 0x1
3818 15:36:14.291780 WR_PST = 0x0
3819 15:36:14.295146 DBI_WR = 0x0
3820 15:36:14.295251 DBI_RD = 0x0
3821 15:36:14.298281 OTF = 0x1
3822 15:36:14.301808 ===================================
3823 15:36:14.305513 ===================================
3824 15:36:14.305594 ANA top config
3825 15:36:14.308472 ===================================
3826 15:36:14.311513 DLL_ASYNC_EN = 0
3827 15:36:14.314793 ALL_SLAVE_EN = 1
3828 15:36:14.314875 NEW_RANK_MODE = 1
3829 15:36:14.318053 DLL_IDLE_MODE = 1
3830 15:36:14.321474 LP45_APHY_COMB_EN = 1
3831 15:36:14.324779 TX_ODT_DIS = 1
3832 15:36:14.324860 NEW_8X_MODE = 1
3833 15:36:14.328516 ===================================
3834 15:36:14.331456 ===================================
3835 15:36:14.335062 data_rate = 1200
3836 15:36:14.338218 CKR = 1
3837 15:36:14.341118 DQ_P2S_RATIO = 8
3838 15:36:14.344681 ===================================
3839 15:36:14.348227 CA_P2S_RATIO = 8
3840 15:36:14.351187 DQ_CA_OPEN = 0
3841 15:36:14.351306 DQ_SEMI_OPEN = 0
3842 15:36:14.354964 CA_SEMI_OPEN = 0
3843 15:36:14.357906 CA_FULL_RATE = 0
3844 15:36:14.361559 DQ_CKDIV4_EN = 1
3845 15:36:14.364377 CA_CKDIV4_EN = 1
3846 15:36:14.367969 CA_PREDIV_EN = 0
3847 15:36:14.370888 PH8_DLY = 0
3848 15:36:14.371002 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3849 15:36:14.374376 DQ_AAMCK_DIV = 4
3850 15:36:14.377282 CA_AAMCK_DIV = 4
3851 15:36:14.381127 CA_ADMCK_DIV = 4
3852 15:36:14.384241 DQ_TRACK_CA_EN = 0
3853 15:36:14.387063 CA_PICK = 600
3854 15:36:14.390794 CA_MCKIO = 600
3855 15:36:14.390915 MCKIO_SEMI = 0
3856 15:36:14.393697 PLL_FREQ = 2288
3857 15:36:14.397273 DQ_UI_PI_RATIO = 32
3858 15:36:14.400615 CA_UI_PI_RATIO = 0
3859 15:36:14.403871 ===================================
3860 15:36:14.407485 ===================================
3861 15:36:14.410515 memory_type:LPDDR4
3862 15:36:14.410619 GP_NUM : 10
3863 15:36:14.413855 SRAM_EN : 1
3864 15:36:14.417181 MD32_EN : 0
3865 15:36:14.420484 ===================================
3866 15:36:14.420558 [ANA_INIT] >>>>>>>>>>>>>>
3867 15:36:14.423439 <<<<<< [CONFIGURE PHASE]: ANA_TX
3868 15:36:14.426686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3869 15:36:14.430151 ===================================
3870 15:36:14.433769 data_rate = 1200,PCW = 0X5800
3871 15:36:14.436605 ===================================
3872 15:36:14.440177 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3873 15:36:14.446509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3874 15:36:14.450170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3875 15:36:14.456647 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3876 15:36:14.459562 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3877 15:36:14.463205 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3878 15:36:14.466145 [ANA_INIT] flow start
3879 15:36:14.466256 [ANA_INIT] PLL >>>>>>>>
3880 15:36:14.469646 [ANA_INIT] PLL <<<<<<<<
3881 15:36:14.472713 [ANA_INIT] MIDPI >>>>>>>>
3882 15:36:14.472794 [ANA_INIT] MIDPI <<<<<<<<
3883 15:36:14.476115 [ANA_INIT] DLL >>>>>>>>
3884 15:36:14.479699 [ANA_INIT] flow end
3885 15:36:14.483213 ============ LP4 DIFF to SE enter ============
3886 15:36:14.486038 ============ LP4 DIFF to SE exit ============
3887 15:36:14.489645 [ANA_INIT] <<<<<<<<<<<<<
3888 15:36:14.493005 [Flow] Enable top DCM control >>>>>
3889 15:36:14.496370 [Flow] Enable top DCM control <<<<<
3890 15:36:14.499277 Enable DLL master slave shuffle
3891 15:36:14.502919 ==============================================================
3892 15:36:14.505950 Gating Mode config
3893 15:36:14.512799 ==============================================================
3894 15:36:14.512912 Config description:
3895 15:36:14.528312 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3896 15:36:14.529208 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3897 15:36:14.532624 SELPH_MODE 0: By rank 1: By Phase
3898 15:36:14.539167 ==============================================================
3899 15:36:14.542567 GAT_TRACK_EN = 1
3900 15:36:14.545635 RX_GATING_MODE = 2
3901 15:36:14.548835 RX_GATING_TRACK_MODE = 2
3902 15:36:14.552223 SELPH_MODE = 1
3903 15:36:14.555497 PICG_EARLY_EN = 1
3904 15:36:14.559048 VALID_LAT_VALUE = 1
3905 15:36:14.561966 ==============================================================
3906 15:36:14.565500 Enter into Gating configuration >>>>
3907 15:36:14.568879 Exit from Gating configuration <<<<
3908 15:36:14.571909 Enter into DVFS_PRE_config >>>>>
3909 15:36:14.585433 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3910 15:36:14.588811 Exit from DVFS_PRE_config <<<<<
3911 15:36:14.591842 Enter into PICG configuration >>>>
3912 15:36:14.591917 Exit from PICG configuration <<<<
3913 15:36:14.595451 [RX_INPUT] configuration >>>>>
3914 15:36:14.598810 [RX_INPUT] configuration <<<<<
3915 15:36:14.604968 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3916 15:36:14.608367 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3917 15:36:14.614982 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3918 15:36:14.621575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3919 15:36:14.628340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3920 15:36:14.634708 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3921 15:36:14.638145 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3922 15:36:14.641508 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3923 15:36:14.648221 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3924 15:36:14.651167 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3925 15:36:14.655146 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3926 15:36:14.657736 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3927 15:36:14.661095 ===================================
3928 15:36:14.664331 LPDDR4 DRAM CONFIGURATION
3929 15:36:14.667877 ===================================
3930 15:36:14.670965 EX_ROW_EN[0] = 0x0
3931 15:36:14.671066 EX_ROW_EN[1] = 0x0
3932 15:36:14.675129 LP4Y_EN = 0x0
3933 15:36:14.675275 WORK_FSP = 0x0
3934 15:36:14.677763 WL = 0x2
3935 15:36:14.677837 RL = 0x2
3936 15:36:14.680916 BL = 0x2
3937 15:36:14.681051 RPST = 0x0
3938 15:36:14.683995 RD_PRE = 0x0
3939 15:36:14.687234 WR_PRE = 0x1
3940 15:36:14.687419 WR_PST = 0x0
3941 15:36:14.690913 DBI_WR = 0x0
3942 15:36:14.690989 DBI_RD = 0x0
3943 15:36:14.693813 OTF = 0x1
3944 15:36:14.697696 ===================================
3945 15:36:14.700962 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3946 15:36:14.704249 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3947 15:36:14.707347 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3948 15:36:14.711008 ===================================
3949 15:36:14.713824 LPDDR4 DRAM CONFIGURATION
3950 15:36:14.717429 ===================================
3951 15:36:14.720940 EX_ROW_EN[0] = 0x10
3952 15:36:14.721023 EX_ROW_EN[1] = 0x0
3953 15:36:14.723742 LP4Y_EN = 0x0
3954 15:36:14.723823 WORK_FSP = 0x0
3955 15:36:14.727619 WL = 0x2
3956 15:36:14.727702 RL = 0x2
3957 15:36:14.730261 BL = 0x2
3958 15:36:14.730342 RPST = 0x0
3959 15:36:14.733887 RD_PRE = 0x0
3960 15:36:14.733968 WR_PRE = 0x1
3961 15:36:14.737246 WR_PST = 0x0
3962 15:36:14.740627 DBI_WR = 0x0
3963 15:36:14.740712 DBI_RD = 0x0
3964 15:36:14.743533 OTF = 0x1
3965 15:36:14.747284 ===================================
3966 15:36:14.750458 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3967 15:36:14.755457 nWR fixed to 30
3968 15:36:14.758736 [ModeRegInit_LP4] CH0 RK0
3969 15:36:14.758819 [ModeRegInit_LP4] CH0 RK1
3970 15:36:14.762178 [ModeRegInit_LP4] CH1 RK0
3971 15:36:14.765602 [ModeRegInit_LP4] CH1 RK1
3972 15:36:14.765686 match AC timing 17
3973 15:36:14.772168 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3974 15:36:14.775337 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3975 15:36:14.779006 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3976 15:36:14.785204 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3977 15:36:14.788675 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3978 15:36:14.788780 ==
3979 15:36:14.791790 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 15:36:14.795148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 15:36:14.795237 ==
3982 15:36:14.801760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3983 15:36:14.808687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3984 15:36:14.811723 [CA 0] Center 36 (6~66) winsize 61
3985 15:36:14.815184 [CA 1] Center 36 (6~66) winsize 61
3986 15:36:14.818278 [CA 2] Center 34 (4~64) winsize 61
3987 15:36:14.822100 [CA 3] Center 34 (3~65) winsize 63
3988 15:36:14.824727 [CA 4] Center 33 (3~64) winsize 62
3989 15:36:14.828161 [CA 5] Center 33 (3~64) winsize 62
3990 15:36:14.828406
3991 15:36:14.831526 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3992 15:36:14.831726
3993 15:36:14.834819 [CATrainingPosCal] consider 1 rank data
3994 15:36:14.838249 u2DelayCellTimex100 = 270/100 ps
3995 15:36:14.841836 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3996 15:36:14.844954 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3997 15:36:14.848106 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3998 15:36:14.851488 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3999 15:36:14.857698 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4000 15:36:14.861033 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 15:36:14.861146
4002 15:36:14.864292 CA PerBit enable=1, Macro0, CA PI delay=33
4003 15:36:14.864389
4004 15:36:14.868054 [CBTSetCACLKResult] CA Dly = 33
4005 15:36:14.868130 CS Dly: 6 (0~37)
4006 15:36:14.868197 ==
4007 15:36:14.870930 Dram Type= 6, Freq= 0, CH_0, rank 1
4008 15:36:14.878089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 15:36:14.878195 ==
4010 15:36:14.880877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4011 15:36:14.887784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4012 15:36:14.890893 [CA 0] Center 36 (6~66) winsize 61
4013 15:36:14.894756 [CA 1] Center 36 (6~67) winsize 62
4014 15:36:14.897424 [CA 2] Center 34 (3~65) winsize 63
4015 15:36:14.900750 [CA 3] Center 34 (3~65) winsize 63
4016 15:36:14.904104 [CA 4] Center 33 (3~64) winsize 62
4017 15:36:14.907582 [CA 5] Center 33 (3~64) winsize 62
4018 15:36:14.907664
4019 15:36:14.910894 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4020 15:36:14.910967
4021 15:36:14.913922 [CATrainingPosCal] consider 2 rank data
4022 15:36:14.916995 u2DelayCellTimex100 = 270/100 ps
4023 15:36:14.920289 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4024 15:36:14.927495 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4025 15:36:14.930310 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4026 15:36:14.934061 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4027 15:36:14.937322 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4028 15:36:14.940427 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4029 15:36:14.940511
4030 15:36:14.944159 CA PerBit enable=1, Macro0, CA PI delay=33
4031 15:36:14.944256
4032 15:36:14.947006 [CBTSetCACLKResult] CA Dly = 33
4033 15:36:14.950230 CS Dly: 5 (0~36)
4034 15:36:14.950303
4035 15:36:14.953566 ----->DramcWriteLeveling(PI) begin...
4036 15:36:14.953665 ==
4037 15:36:14.957034 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 15:36:14.960090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 15:36:14.960186 ==
4040 15:36:14.963521 Write leveling (Byte 0): 32 => 32
4041 15:36:14.966831 Write leveling (Byte 1): 29 => 29
4042 15:36:14.970066 DramcWriteLeveling(PI) end<-----
4043 15:36:14.970162
4044 15:36:14.970251 ==
4045 15:36:14.973589 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 15:36:14.976960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 15:36:14.977057 ==
4048 15:36:14.980395 [Gating] SW mode calibration
4049 15:36:14.986925 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4050 15:36:14.993218 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4051 15:36:14.996669 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 15:36:14.999867 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4053 15:36:15.006405 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4054 15:36:15.009704 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4055 15:36:15.012865 0 9 16 | B1->B0 | 2d2d 2626 | 1 1 | (1 1) (1 0)
4056 15:36:15.019863 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 15:36:15.023077 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 15:36:15.026163 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 15:36:15.033066 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 15:36:15.036093 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 15:36:15.039595 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 15:36:15.045810 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4063 15:36:15.049500 0 10 16 | B1->B0 | 3737 4242 | 0 0 | (0 0) (0 0)
4064 15:36:15.052651 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 15:36:15.059551 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 15:36:15.062187 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 15:36:15.065605 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 15:36:15.072213 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 15:36:15.075683 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 15:36:15.078957 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 15:36:15.085917 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4072 15:36:15.089309 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 15:36:15.092159 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 15:36:15.099273 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 15:36:15.102428 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 15:36:15.105599 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 15:36:15.111870 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 15:36:15.115647 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 15:36:15.118570 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 15:36:15.125233 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 15:36:15.128755 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 15:36:15.131707 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 15:36:15.138451 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 15:36:15.142132 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 15:36:15.145407 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4086 15:36:15.151672 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4087 15:36:15.154980 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 15:36:15.158339 Total UI for P1: 0, mck2ui 16
4089 15:36:15.161309 best dqsien dly found for B0: ( 0, 13, 10)
4090 15:36:15.165086 Total UI for P1: 0, mck2ui 16
4091 15:36:15.168218 best dqsien dly found for B1: ( 0, 13, 12)
4092 15:36:15.171658 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4093 15:36:15.175095 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4094 15:36:15.175176
4095 15:36:15.177840 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4096 15:36:15.181444 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4097 15:36:15.185024 [Gating] SW calibration Done
4098 15:36:15.185105 ==
4099 15:36:15.187742 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 15:36:15.194676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 15:36:15.194758 ==
4102 15:36:15.194822 RX Vref Scan: 0
4103 15:36:15.194883
4104 15:36:15.197579 RX Vref 0 -> 0, step: 1
4105 15:36:15.197661
4106 15:36:15.200812 RX Delay -230 -> 252, step: 16
4107 15:36:15.204043 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4108 15:36:15.207625 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4109 15:36:15.214007 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4110 15:36:15.217516 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4111 15:36:15.220431 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4112 15:36:15.223962 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4113 15:36:15.227047 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4114 15:36:15.233722 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4115 15:36:15.236929 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4116 15:36:15.240181 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4117 15:36:15.243658 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4118 15:36:15.250140 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4119 15:36:15.253450 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4120 15:36:15.256974 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4121 15:36:15.260210 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4122 15:36:15.266627 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4123 15:36:15.266710 ==
4124 15:36:15.269881 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 15:36:15.273428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 15:36:15.273510 ==
4127 15:36:15.273592 DQS Delay:
4128 15:36:15.276429 DQS0 = 0, DQS1 = 0
4129 15:36:15.276510 DQM Delay:
4130 15:36:15.280285 DQM0 = 41, DQM1 = 29
4131 15:36:15.280383 DQ Delay:
4132 15:36:15.283185 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4133 15:36:15.286734 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4134 15:36:15.290011 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4135 15:36:15.292912 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4136 15:36:15.292994
4137 15:36:15.293098
4138 15:36:15.293159 ==
4139 15:36:15.296658 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 15:36:15.299688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 15:36:15.303125 ==
4142 15:36:15.303227
4143 15:36:15.303329
4144 15:36:15.303422 TX Vref Scan disable
4145 15:36:15.306541 == TX Byte 0 ==
4146 15:36:15.309856 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4147 15:36:15.313155 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4148 15:36:15.316750 == TX Byte 1 ==
4149 15:36:15.319735 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4150 15:36:15.323304 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4151 15:36:15.326633 ==
4152 15:36:15.326716 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 15:36:15.333224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 15:36:15.333328 ==
4155 15:36:15.333410
4156 15:36:15.333471
4157 15:36:15.336240 TX Vref Scan disable
4158 15:36:15.336322 == TX Byte 0 ==
4159 15:36:15.342958 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4160 15:36:15.346525 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4161 15:36:15.346669 == TX Byte 1 ==
4162 15:36:15.353530 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4163 15:36:15.356566 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4164 15:36:15.356649
4165 15:36:15.356753 [DATLAT]
4166 15:36:15.359937 Freq=600, CH0 RK0
4167 15:36:15.360019
4168 15:36:15.360122 DATLAT Default: 0x9
4169 15:36:15.362935 0, 0xFFFF, sum = 0
4170 15:36:15.363019 1, 0xFFFF, sum = 0
4171 15:36:15.366343 2, 0xFFFF, sum = 0
4172 15:36:15.369583 3, 0xFFFF, sum = 0
4173 15:36:15.369670 4, 0xFFFF, sum = 0
4174 15:36:15.373047 5, 0xFFFF, sum = 0
4175 15:36:15.373131 6, 0xFFFF, sum = 0
4176 15:36:15.375858 7, 0xFFFF, sum = 0
4177 15:36:15.375941 8, 0x0, sum = 1
4178 15:36:15.379197 9, 0x0, sum = 2
4179 15:36:15.379280 10, 0x0, sum = 3
4180 15:36:15.379347 11, 0x0, sum = 4
4181 15:36:15.382774 best_step = 9
4182 15:36:15.382857
4183 15:36:15.382921 ==
4184 15:36:15.386087 Dram Type= 6, Freq= 0, CH_0, rank 0
4185 15:36:15.389324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 15:36:15.389405 ==
4187 15:36:15.392919 RX Vref Scan: 1
4188 15:36:15.392995
4189 15:36:15.393059 RX Vref 0 -> 0, step: 1
4190 15:36:15.395608
4191 15:36:15.395682 RX Delay -195 -> 252, step: 8
4192 15:36:15.395743
4193 15:36:15.399089 Set Vref, RX VrefLevel [Byte0]: 61
4194 15:36:15.402609 [Byte1]: 49
4195 15:36:15.406734
4196 15:36:15.406811 Final RX Vref Byte 0 = 61 to rank0
4197 15:36:15.410041 Final RX Vref Byte 1 = 49 to rank0
4198 15:36:15.413228 Final RX Vref Byte 0 = 61 to rank1
4199 15:36:15.416548 Final RX Vref Byte 1 = 49 to rank1==
4200 15:36:15.419878 Dram Type= 6, Freq= 0, CH_0, rank 0
4201 15:36:15.426262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 15:36:15.426340 ==
4203 15:36:15.426404 DQS Delay:
4204 15:36:15.430141 DQS0 = 0, DQS1 = 0
4205 15:36:15.430211 DQM Delay:
4206 15:36:15.430271 DQM0 = 43, DQM1 = 32
4207 15:36:15.433190 DQ Delay:
4208 15:36:15.436286 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4209 15:36:15.439601 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =48
4210 15:36:15.443273 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4211 15:36:15.446766 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4212 15:36:15.446848
4213 15:36:15.446912
4214 15:36:15.452896 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4215 15:36:15.456553 CH0 RK0: MR19=808, MR18=6C43
4216 15:36:15.463072 CH0_RK0: MR19=0x808, MR18=0x6C43, DQSOSC=389, MR23=63, INC=173, DEC=115
4217 15:36:15.463150
4218 15:36:15.466373 ----->DramcWriteLeveling(PI) begin...
4219 15:36:15.466472 ==
4220 15:36:15.469725 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 15:36:15.473156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 15:36:15.473238 ==
4223 15:36:15.475965 Write leveling (Byte 0): 33 => 33
4224 15:36:15.479277 Write leveling (Byte 1): 34 => 34
4225 15:36:15.482650 DramcWriteLeveling(PI) end<-----
4226 15:36:15.482731
4227 15:36:15.482795 ==
4228 15:36:15.486275 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 15:36:15.489243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 15:36:15.492486 ==
4231 15:36:15.492567 [Gating] SW mode calibration
4232 15:36:15.502506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4233 15:36:15.505566 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4234 15:36:15.508916 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 15:36:15.515841 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 15:36:15.518634 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4237 15:36:15.522016 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4238 15:36:15.528963 0 9 16 | B1->B0 | 3131 2b2b | 0 0 | (1 1) (1 1)
4239 15:36:15.532215 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 15:36:15.535451 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 15:36:15.541698 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 15:36:15.545105 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 15:36:15.548303 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 15:36:15.555290 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 15:36:15.558767 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4246 15:36:15.561461 0 10 16 | B1->B0 | 3737 4040 | 1 0 | (0 0) (0 0)
4247 15:36:15.568175 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 15:36:15.571338 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 15:36:15.574787 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 15:36:15.581772 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 15:36:15.584582 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 15:36:15.588112 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 15:36:15.594704 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4254 15:36:15.598120 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4255 15:36:15.601080 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 15:36:15.607963 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 15:36:15.610877 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 15:36:15.614740 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 15:36:15.620792 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 15:36:15.624243 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 15:36:15.627329 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 15:36:15.634032 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 15:36:15.637376 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 15:36:15.641080 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 15:36:15.647396 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 15:36:15.650863 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 15:36:15.654432 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 15:36:15.660748 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 15:36:15.663954 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4270 15:36:15.667007 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 15:36:15.670773 Total UI for P1: 0, mck2ui 16
4272 15:36:15.674126 best dqsien dly found for B0: ( 0, 13, 12)
4273 15:36:15.677604 Total UI for P1: 0, mck2ui 16
4274 15:36:15.680392 best dqsien dly found for B1: ( 0, 13, 14)
4275 15:36:15.683954 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4276 15:36:15.687327 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4277 15:36:15.690209
4278 15:36:15.693299 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4279 15:36:15.696885 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4280 15:36:15.700383 [Gating] SW calibration Done
4281 15:36:15.700456 ==
4282 15:36:15.703649 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 15:36:15.706756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 15:36:15.706858 ==
4285 15:36:15.710221 RX Vref Scan: 0
4286 15:36:15.710326
4287 15:36:15.710417 RX Vref 0 -> 0, step: 1
4288 15:36:15.710506
4289 15:36:15.713327 RX Delay -230 -> 252, step: 16
4290 15:36:15.716437 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4291 15:36:15.723391 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4292 15:36:15.726301 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4293 15:36:15.729896 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4294 15:36:15.732988 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4295 15:36:15.739330 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4296 15:36:15.743014 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4297 15:36:15.746799 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4298 15:36:15.749473 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4299 15:36:15.752731 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4300 15:36:15.759533 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4301 15:36:15.762411 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4302 15:36:15.766482 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4303 15:36:15.769581 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4304 15:36:15.776190 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4305 15:36:15.779242 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4306 15:36:15.779325 ==
4307 15:36:15.782739 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 15:36:15.785982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 15:36:15.786076 ==
4310 15:36:15.789391 DQS Delay:
4311 15:36:15.789466 DQS0 = 0, DQS1 = 0
4312 15:36:15.792254 DQM Delay:
4313 15:36:15.792329 DQM0 = 44, DQM1 = 35
4314 15:36:15.792393 DQ Delay:
4315 15:36:15.795531 DQ0 =41, DQ1 =57, DQ2 =33, DQ3 =33
4316 15:36:15.799160 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4317 15:36:15.802499 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4318 15:36:15.805758 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4319 15:36:15.805828
4320 15:36:15.805895
4321 15:36:15.808795 ==
4322 15:36:15.812766 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 15:36:15.815529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 15:36:15.815617 ==
4325 15:36:15.815682
4326 15:36:15.815743
4327 15:36:15.818979 TX Vref Scan disable
4328 15:36:15.819086 == TX Byte 0 ==
4329 15:36:15.825405 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4330 15:36:15.828408 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4331 15:36:15.828489 == TX Byte 1 ==
4332 15:36:15.835302 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4333 15:36:15.838477 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4334 15:36:15.838575 ==
4335 15:36:15.841739 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 15:36:15.845371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 15:36:15.845452 ==
4338 15:36:15.845517
4339 15:36:15.845577
4340 15:36:15.848194 TX Vref Scan disable
4341 15:36:15.851605 == TX Byte 0 ==
4342 15:36:15.855180 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4343 15:36:15.858449 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4344 15:36:15.861654 == TX Byte 1 ==
4345 15:36:15.865112 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4346 15:36:15.868154 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4347 15:36:15.868235
4348 15:36:15.871943 [DATLAT]
4349 15:36:15.872024 Freq=600, CH0 RK1
4350 15:36:15.872088
4351 15:36:15.874764 DATLAT Default: 0x9
4352 15:36:15.874847 0, 0xFFFF, sum = 0
4353 15:36:15.878035 1, 0xFFFF, sum = 0
4354 15:36:15.878118 2, 0xFFFF, sum = 0
4355 15:36:15.881743 3, 0xFFFF, sum = 0
4356 15:36:15.881825 4, 0xFFFF, sum = 0
4357 15:36:15.884701 5, 0xFFFF, sum = 0
4358 15:36:15.884820 6, 0xFFFF, sum = 0
4359 15:36:15.888337 7, 0xFFFF, sum = 0
4360 15:36:15.888419 8, 0x0, sum = 1
4361 15:36:15.891316 9, 0x0, sum = 2
4362 15:36:15.891397 10, 0x0, sum = 3
4363 15:36:15.895189 11, 0x0, sum = 4
4364 15:36:15.895271 best_step = 9
4365 15:36:15.895336
4366 15:36:15.895395 ==
4367 15:36:15.898330 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 15:36:15.904711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 15:36:15.904793 ==
4370 15:36:15.904857 RX Vref Scan: 0
4371 15:36:15.904917
4372 15:36:15.908390 RX Vref 0 -> 0, step: 1
4373 15:36:15.908470
4374 15:36:15.911090 RX Delay -179 -> 252, step: 8
4375 15:36:15.914799 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4376 15:36:15.921233 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4377 15:36:15.924504 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4378 15:36:15.927896 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4379 15:36:15.931508 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4380 15:36:15.934720 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4381 15:36:15.941370 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4382 15:36:15.944569 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4383 15:36:15.948028 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4384 15:36:15.950809 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4385 15:36:15.957521 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4386 15:36:15.961029 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4387 15:36:15.964251 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4388 15:36:15.967467 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4389 15:36:15.974060 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4390 15:36:15.977499 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4391 15:36:15.977581 ==
4392 15:36:15.980705 Dram Type= 6, Freq= 0, CH_0, rank 1
4393 15:36:15.984035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 15:36:15.984144 ==
4395 15:36:15.987380 DQS Delay:
4396 15:36:15.987461 DQS0 = 0, DQS1 = 0
4397 15:36:15.990216 DQM Delay:
4398 15:36:15.990355 DQM0 = 40, DQM1 = 34
4399 15:36:15.990449 DQ Delay:
4400 15:36:15.994005 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4401 15:36:15.996792 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4402 15:36:16.000505 DQ8 =24, DQ9 =20, DQ10 =40, DQ11 =24
4403 15:36:16.004037 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4404 15:36:16.004117
4405 15:36:16.004181
4406 15:36:16.013809 [DQSOSCAuto] RK1, (LSB)MR18= 0x6315, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4407 15:36:16.017039 CH0 RK1: MR19=808, MR18=6315
4408 15:36:16.023770 CH0_RK1: MR19=0x808, MR18=0x6315, DQSOSC=391, MR23=63, INC=171, DEC=114
4409 15:36:16.023848 [RxdqsGatingPostProcess] freq 600
4410 15:36:16.030104 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4411 15:36:16.033426 Pre-setting of DQS Precalculation
4412 15:36:16.037003 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4413 15:36:16.040192 ==
4414 15:36:16.043233 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 15:36:16.046849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 15:36:16.046921 ==
4417 15:36:16.049678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 15:36:16.056476 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4419 15:36:16.060469 [CA 0] Center 35 (5~66) winsize 62
4420 15:36:16.063604 [CA 1] Center 35 (5~66) winsize 62
4421 15:36:16.067137 [CA 2] Center 34 (4~65) winsize 62
4422 15:36:16.070501 [CA 3] Center 33 (3~64) winsize 62
4423 15:36:16.073740 [CA 4] Center 34 (4~64) winsize 61
4424 15:36:16.076986 [CA 5] Center 33 (3~64) winsize 62
4425 15:36:16.077064
4426 15:36:16.079993 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4427 15:36:16.080094
4428 15:36:16.083245 [CATrainingPosCal] consider 1 rank data
4429 15:36:16.086441 u2DelayCellTimex100 = 270/100 ps
4430 15:36:16.093329 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4431 15:36:16.096530 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4432 15:36:16.100082 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 15:36:16.103261 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 15:36:16.106502 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4435 15:36:16.109338 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 15:36:16.109433
4437 15:36:16.113044 CA PerBit enable=1, Macro0, CA PI delay=33
4438 15:36:16.113143
4439 15:36:16.116140 [CBTSetCACLKResult] CA Dly = 33
4440 15:36:16.119354 CS Dly: 4 (0~35)
4441 15:36:16.119429 ==
4442 15:36:16.122775 Dram Type= 6, Freq= 0, CH_1, rank 1
4443 15:36:16.126017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 15:36:16.126145 ==
4445 15:36:16.132673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 15:36:16.139064 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4447 15:36:16.142601 [CA 0] Center 35 (5~66) winsize 62
4448 15:36:16.145792 [CA 1] Center 36 (6~66) winsize 61
4449 15:36:16.149338 [CA 2] Center 34 (4~65) winsize 62
4450 15:36:16.152325 [CA 3] Center 34 (4~65) winsize 62
4451 15:36:16.155765 [CA 4] Center 34 (3~65) winsize 63
4452 15:36:16.158882 [CA 5] Center 34 (3~65) winsize 63
4453 15:36:16.158959
4454 15:36:16.162130 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4455 15:36:16.162232
4456 15:36:16.165804 [CATrainingPosCal] consider 2 rank data
4457 15:36:16.169044 u2DelayCellTimex100 = 270/100 ps
4458 15:36:16.172747 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4459 15:36:16.175907 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4460 15:36:16.178755 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4461 15:36:16.182277 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4462 15:36:16.185206 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4463 15:36:16.189206 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 15:36:16.189284
4465 15:36:16.195289 CA PerBit enable=1, Macro0, CA PI delay=33
4466 15:36:16.195367
4467 15:36:16.195435 [CBTSetCACLKResult] CA Dly = 33
4468 15:36:16.198789 CS Dly: 5 (0~37)
4469 15:36:16.198861
4470 15:36:16.201567 ----->DramcWriteLeveling(PI) begin...
4471 15:36:16.201636 ==
4472 15:36:16.205227 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 15:36:16.208231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 15:36:16.208301 ==
4475 15:36:16.211629 Write leveling (Byte 0): 29 => 29
4476 15:36:16.214796 Write leveling (Byte 1): 29 => 29
4477 15:36:16.218146 DramcWriteLeveling(PI) end<-----
4478 15:36:16.218217
4479 15:36:16.218282 ==
4480 15:36:16.221473 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 15:36:16.228531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 15:36:16.228609 ==
4483 15:36:16.228677 [Gating] SW mode calibration
4484 15:36:16.238050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4485 15:36:16.241430 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4486 15:36:16.244754 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 15:36:16.251179 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 15:36:16.254539 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 15:36:16.257855 0 9 12 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 0)
4490 15:36:16.264598 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 15:36:16.267973 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 15:36:16.271138 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 15:36:16.277761 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 15:36:16.281036 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 15:36:16.284121 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 15:36:16.291110 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4497 15:36:16.294460 0 10 12 | B1->B0 | 3131 3838 | 0 0 | (0 0) (0 0)
4498 15:36:16.298149 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4499 15:36:16.304324 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 15:36:16.307569 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 15:36:16.310587 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 15:36:16.317339 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 15:36:16.321215 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 15:36:16.323885 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 15:36:16.330751 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4506 15:36:16.333696 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 15:36:16.337270 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 15:36:16.343910 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 15:36:16.347106 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 15:36:16.350551 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 15:36:16.357299 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 15:36:16.360686 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 15:36:16.363614 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 15:36:16.370359 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 15:36:16.373749 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 15:36:16.376819 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 15:36:16.383337 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 15:36:16.386530 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 15:36:16.390057 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 15:36:16.396880 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4521 15:36:16.399883 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4522 15:36:16.403352 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 15:36:16.406767 Total UI for P1: 0, mck2ui 16
4524 15:36:16.409823 best dqsien dly found for B0: ( 0, 13, 10)
4525 15:36:16.412851 Total UI for P1: 0, mck2ui 16
4526 15:36:16.416253 best dqsien dly found for B1: ( 0, 13, 12)
4527 15:36:16.419574 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4528 15:36:16.423066 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4529 15:36:16.426504
4530 15:36:16.429369 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4531 15:36:16.432867 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4532 15:36:16.436087 [Gating] SW calibration Done
4533 15:36:16.436158 ==
4534 15:36:16.439723 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 15:36:16.443143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 15:36:16.443245 ==
4537 15:36:16.443336 RX Vref Scan: 0
4538 15:36:16.443430
4539 15:36:16.446145 RX Vref 0 -> 0, step: 1
4540 15:36:16.446245
4541 15:36:16.449513 RX Delay -230 -> 252, step: 16
4542 15:36:16.452509 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4543 15:36:16.459374 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4544 15:36:16.462838 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4545 15:36:16.466204 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4546 15:36:16.469498 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4547 15:36:16.472426 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4548 15:36:16.479546 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4549 15:36:16.482450 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4550 15:36:16.485971 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4551 15:36:16.489090 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4552 15:36:16.495569 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4553 15:36:16.498936 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4554 15:36:16.502416 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4555 15:36:16.505801 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4556 15:36:16.512164 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4557 15:36:16.515729 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4558 15:36:16.515805 ==
4559 15:36:16.518805 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 15:36:16.522372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 15:36:16.522446 ==
4562 15:36:16.525627 DQS Delay:
4563 15:36:16.525707 DQS0 = 0, DQS1 = 0
4564 15:36:16.525770 DQM Delay:
4565 15:36:16.528976 DQM0 = 46, DQM1 = 35
4566 15:36:16.529068 DQ Delay:
4567 15:36:16.531811 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4568 15:36:16.535509 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4569 15:36:16.538938 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4570 15:36:16.542239 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4571 15:36:16.542314
4572 15:36:16.542407
4573 15:36:16.542494 ==
4574 15:36:16.545410 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 15:36:16.552335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 15:36:16.552416 ==
4577 15:36:16.552480
4578 15:36:16.552544
4579 15:36:16.552603 TX Vref Scan disable
4580 15:36:16.555768 == TX Byte 0 ==
4581 15:36:16.558858 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4582 15:36:16.562557 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4583 15:36:16.566102 == TX Byte 1 ==
4584 15:36:16.569160 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4585 15:36:16.575777 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4586 15:36:16.575854 ==
4587 15:36:16.579048 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 15:36:16.582471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 15:36:16.582568 ==
4590 15:36:16.582696
4591 15:36:16.582762
4592 15:36:16.585373 TX Vref Scan disable
4593 15:36:16.588705 == TX Byte 0 ==
4594 15:36:16.592318 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4595 15:36:16.595565 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4596 15:36:16.598824 == TX Byte 1 ==
4597 15:36:16.601909 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4598 15:36:16.605531 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4599 15:36:16.605606
4600 15:36:16.605697 [DATLAT]
4601 15:36:16.608459 Freq=600, CH1 RK0
4602 15:36:16.608530
4603 15:36:16.611905 DATLAT Default: 0x9
4604 15:36:16.611972 0, 0xFFFF, sum = 0
4605 15:36:16.615454 1, 0xFFFF, sum = 0
4606 15:36:16.615530 2, 0xFFFF, sum = 0
4607 15:36:16.618320 3, 0xFFFF, sum = 0
4608 15:36:16.618391 4, 0xFFFF, sum = 0
4609 15:36:16.621795 5, 0xFFFF, sum = 0
4610 15:36:16.621864 6, 0xFFFF, sum = 0
4611 15:36:16.625290 7, 0xFFFF, sum = 0
4612 15:36:16.625385 8, 0x0, sum = 1
4613 15:36:16.628513 9, 0x0, sum = 2
4614 15:36:16.628583 10, 0x0, sum = 3
4615 15:36:16.631543 11, 0x0, sum = 4
4616 15:36:16.631615 best_step = 9
4617 15:36:16.631675
4618 15:36:16.631754 ==
4619 15:36:16.634968 Dram Type= 6, Freq= 0, CH_1, rank 0
4620 15:36:16.638210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 15:36:16.638310 ==
4622 15:36:16.641671 RX Vref Scan: 1
4623 15:36:16.641774
4624 15:36:16.644781 RX Vref 0 -> 0, step: 1
4625 15:36:16.644852
4626 15:36:16.644912 RX Delay -195 -> 252, step: 8
4627 15:36:16.644971
4628 15:36:16.648165 Set Vref, RX VrefLevel [Byte0]: 48
4629 15:36:16.651721 [Byte1]: 53
4630 15:36:16.656335
4631 15:36:16.656416 Final RX Vref Byte 0 = 48 to rank0
4632 15:36:16.659321 Final RX Vref Byte 1 = 53 to rank0
4633 15:36:16.663224 Final RX Vref Byte 0 = 48 to rank1
4634 15:36:16.666157 Final RX Vref Byte 1 = 53 to rank1==
4635 15:36:16.669309 Dram Type= 6, Freq= 0, CH_1, rank 0
4636 15:36:16.676062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 15:36:16.676139 ==
4638 15:36:16.676202 DQS Delay:
4639 15:36:16.679486 DQS0 = 0, DQS1 = 0
4640 15:36:16.679563 DQM Delay:
4641 15:36:16.679626 DQM0 = 47, DQM1 = 38
4642 15:36:16.682745 DQ Delay:
4643 15:36:16.686054 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4644 15:36:16.689389 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4645 15:36:16.692867 DQ8 =24, DQ9 =28, DQ10 =40, DQ11 =28
4646 15:36:16.695939 DQ12 =48, DQ13 =40, DQ14 =48, DQ15 =48
4647 15:36:16.696035
4648 15:36:16.696125
4649 15:36:16.702432 [DQSOSCAuto] RK0, (LSB)MR18= 0x553a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 393 ps
4650 15:36:16.705819 CH1 RK0: MR19=808, MR18=553A
4651 15:36:16.712134 CH1_RK0: MR19=0x808, MR18=0x553A, DQSOSC=393, MR23=63, INC=169, DEC=113
4652 15:36:16.712245
4653 15:36:16.715896 ----->DramcWriteLeveling(PI) begin...
4654 15:36:16.715977 ==
4655 15:36:16.718954 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 15:36:16.722130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 15:36:16.722212 ==
4658 15:36:16.725834 Write leveling (Byte 0): 31 => 31
4659 15:36:16.728535 Write leveling (Byte 1): 31 => 31
4660 15:36:16.732174 DramcWriteLeveling(PI) end<-----
4661 15:36:16.732247
4662 15:36:16.732309 ==
4663 15:36:16.735206 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 15:36:16.738669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 15:36:16.742057 ==
4666 15:36:16.742139 [Gating] SW mode calibration
4667 15:36:16.751841 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4668 15:36:16.754861 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4669 15:36:16.758247 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4670 15:36:16.765098 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 15:36:16.768216 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4672 15:36:16.771463 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 1) (0 0)
4673 15:36:16.778254 0 9 16 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
4674 15:36:16.781366 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 15:36:16.784501 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 15:36:16.791341 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 15:36:16.794543 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 15:36:16.797958 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 15:36:16.805157 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 15:36:16.807765 0 10 12 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
4681 15:36:16.811243 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4682 15:36:16.817982 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 15:36:16.821428 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 15:36:16.824389 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 15:36:16.831172 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 15:36:16.834622 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 15:36:16.837540 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 15:36:16.844190 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4689 15:36:16.847669 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 15:36:16.851010 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 15:36:16.857114 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 15:36:16.860977 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 15:36:16.863867 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 15:36:16.870718 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 15:36:16.874527 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 15:36:16.877485 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 15:36:16.883925 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 15:36:16.887308 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 15:36:16.890312 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 15:36:16.896939 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 15:36:16.900596 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 15:36:16.903533 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 15:36:16.909943 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4704 15:36:16.913751 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 15:36:16.916720 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 15:36:16.920146 Total UI for P1: 0, mck2ui 16
4707 15:36:16.923204 best dqsien dly found for B0: ( 0, 13, 14)
4708 15:36:16.926407 Total UI for P1: 0, mck2ui 16
4709 15:36:16.929965 best dqsien dly found for B1: ( 0, 13, 14)
4710 15:36:16.932901 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4711 15:36:16.936185 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4712 15:36:16.939754
4713 15:36:16.942968 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4714 15:36:16.946757 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4715 15:36:16.949949 [Gating] SW calibration Done
4716 15:36:16.950031 ==
4717 15:36:16.953011 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 15:36:16.955943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 15:36:16.956025 ==
4720 15:36:16.959585 RX Vref Scan: 0
4721 15:36:16.959665
4722 15:36:16.959729 RX Vref 0 -> 0, step: 1
4723 15:36:16.959788
4724 15:36:16.962913 RX Delay -230 -> 252, step: 16
4725 15:36:16.965862 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4726 15:36:16.972621 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4727 15:36:16.976212 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4728 15:36:16.979112 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4729 15:36:16.982396 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4730 15:36:16.989304 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4731 15:36:16.992361 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4732 15:36:16.995916 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4733 15:36:16.999367 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4734 15:36:17.002185 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4735 15:36:17.009246 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4736 15:36:17.012618 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4737 15:36:17.015986 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4738 15:36:17.019136 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4739 15:36:17.025685 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4740 15:36:17.028685 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4741 15:36:17.028761 ==
4742 15:36:17.032342 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 15:36:17.035269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 15:36:17.035341 ==
4745 15:36:17.038772 DQS Delay:
4746 15:36:17.038845 DQS0 = 0, DQS1 = 0
4747 15:36:17.042082 DQM Delay:
4748 15:36:17.042183 DQM0 = 42, DQM1 = 38
4749 15:36:17.042273 DQ Delay:
4750 15:36:17.045218 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4751 15:36:17.048752 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4752 15:36:17.051923 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4753 15:36:17.055459 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4754 15:36:17.055559
4755 15:36:17.055651
4756 15:36:17.058309 ==
4757 15:36:17.058407 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 15:36:17.065318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 15:36:17.065420 ==
4760 15:36:17.065510
4761 15:36:17.065600
4762 15:36:17.068130 TX Vref Scan disable
4763 15:36:17.068236 == TX Byte 0 ==
4764 15:36:17.071848 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4765 15:36:17.078532 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4766 15:36:17.078656 == TX Byte 1 ==
4767 15:36:17.081472 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4768 15:36:17.088006 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4769 15:36:17.088105 ==
4770 15:36:17.091446 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 15:36:17.094887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 15:36:17.094958 ==
4773 15:36:17.095019
4774 15:36:17.095076
4775 15:36:17.097980 TX Vref Scan disable
4776 15:36:17.101590 == TX Byte 0 ==
4777 15:36:17.104431 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4778 15:36:17.108179 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4779 15:36:17.111341 == TX Byte 1 ==
4780 15:36:17.114557 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4781 15:36:17.118172 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4782 15:36:17.118245
4783 15:36:17.120840 [DATLAT]
4784 15:36:17.120910 Freq=600, CH1 RK1
4785 15:36:17.120972
4786 15:36:17.124116 DATLAT Default: 0x9
4787 15:36:17.124210 0, 0xFFFF, sum = 0
4788 15:36:17.127903 1, 0xFFFF, sum = 0
4789 15:36:17.127977 2, 0xFFFF, sum = 0
4790 15:36:17.131162 3, 0xFFFF, sum = 0
4791 15:36:17.131248 4, 0xFFFF, sum = 0
4792 15:36:17.134019 5, 0xFFFF, sum = 0
4793 15:36:17.134115 6, 0xFFFF, sum = 0
4794 15:36:17.137691 7, 0xFFFF, sum = 0
4795 15:36:17.137775 8, 0x0, sum = 1
4796 15:36:17.140727 9, 0x0, sum = 2
4797 15:36:17.140811 10, 0x0, sum = 3
4798 15:36:17.144289 11, 0x0, sum = 4
4799 15:36:17.144373 best_step = 9
4800 15:36:17.144459
4801 15:36:17.144539 ==
4802 15:36:17.147207 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 15:36:17.154136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 15:36:17.154221 ==
4805 15:36:17.154320 RX Vref Scan: 0
4806 15:36:17.154419
4807 15:36:17.157266 RX Vref 0 -> 0, step: 1
4808 15:36:17.157384
4809 15:36:17.160673 RX Delay -195 -> 252, step: 8
4810 15:36:17.164106 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4811 15:36:17.170930 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4812 15:36:17.174051 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4813 15:36:17.177404 iDelay=213, Bit 3, Center 44 (-99 ~ 188) 288
4814 15:36:17.180856 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4815 15:36:17.183977 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4816 15:36:17.190557 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4817 15:36:17.194207 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4818 15:36:17.197021 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4819 15:36:17.200287 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4820 15:36:17.207276 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4821 15:36:17.210312 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4822 15:36:17.213620 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4823 15:36:17.217098 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4824 15:36:17.223203 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4825 15:36:17.226544 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4826 15:36:17.226670 ==
4827 15:36:17.230091 Dram Type= 6, Freq= 0, CH_1, rank 1
4828 15:36:17.233216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4829 15:36:17.233309 ==
4830 15:36:17.236692 DQS Delay:
4831 15:36:17.236790 DQS0 = 0, DQS1 = 0
4832 15:36:17.236881 DQM Delay:
4833 15:36:17.239872 DQM0 = 46, DQM1 = 37
4834 15:36:17.239940 DQ Delay:
4835 15:36:17.243538 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4836 15:36:17.246480 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4837 15:36:17.249803 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4838 15:36:17.253131 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4839 15:36:17.253229
4840 15:36:17.253318
4841 15:36:17.263017 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4842 15:36:17.266612 CH1 RK1: MR19=808, MR18=2E23
4843 15:36:17.270004 CH1_RK1: MR19=0x808, MR18=0x2E23, DQSOSC=401, MR23=63, INC=163, DEC=108
4844 15:36:17.273003 [RxdqsGatingPostProcess] freq 600
4845 15:36:17.279794 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4846 15:36:17.283039 Pre-setting of DQS Precalculation
4847 15:36:17.285951 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4848 15:36:17.295866 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4849 15:36:17.302675 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4850 15:36:17.302749
4851 15:36:17.302812
4852 15:36:17.305986 [Calibration Summary] 1200 Mbps
4853 15:36:17.306079 CH 0, Rank 0
4854 15:36:17.309517 SW Impedance : PASS
4855 15:36:17.309588 DUTY Scan : NO K
4856 15:36:17.312417 ZQ Calibration : PASS
4857 15:36:17.315497 Jitter Meter : NO K
4858 15:36:17.315597 CBT Training : PASS
4859 15:36:17.318810 Write leveling : PASS
4860 15:36:17.322327 RX DQS gating : PASS
4861 15:36:17.322419 RX DQ/DQS(RDDQC) : PASS
4862 15:36:17.325458 TX DQ/DQS : PASS
4863 15:36:17.328967 RX DATLAT : PASS
4864 15:36:17.329038 RX DQ/DQS(Engine): PASS
4865 15:36:17.332272 TX OE : NO K
4866 15:36:17.332339 All Pass.
4867 15:36:17.332402
4868 15:36:17.335827 CH 0, Rank 1
4869 15:36:17.335896 SW Impedance : PASS
4870 15:36:17.338736 DUTY Scan : NO K
4871 15:36:17.342008 ZQ Calibration : PASS
4872 15:36:17.342106 Jitter Meter : NO K
4873 15:36:17.345777 CBT Training : PASS
4874 15:36:17.349034 Write leveling : PASS
4875 15:36:17.349135 RX DQS gating : PASS
4876 15:36:17.352192 RX DQ/DQS(RDDQC) : PASS
4877 15:36:17.352286 TX DQ/DQS : PASS
4878 15:36:17.355344 RX DATLAT : PASS
4879 15:36:17.358780 RX DQ/DQS(Engine): PASS
4880 15:36:17.358857 TX OE : NO K
4881 15:36:17.362052 All Pass.
4882 15:36:17.362155
4883 15:36:17.362258 CH 1, Rank 0
4884 15:36:17.365352 SW Impedance : PASS
4885 15:36:17.365448 DUTY Scan : NO K
4886 15:36:17.368822 ZQ Calibration : PASS
4887 15:36:17.372097 Jitter Meter : NO K
4888 15:36:17.372178 CBT Training : PASS
4889 15:36:17.375410 Write leveling : PASS
4890 15:36:17.378737 RX DQS gating : PASS
4891 15:36:17.378818 RX DQ/DQS(RDDQC) : PASS
4892 15:36:17.381616 TX DQ/DQS : PASS
4893 15:36:17.385041 RX DATLAT : PASS
4894 15:36:17.385122 RX DQ/DQS(Engine): PASS
4895 15:36:17.388188 TX OE : NO K
4896 15:36:17.388294 All Pass.
4897 15:36:17.388386
4898 15:36:17.391899 CH 1, Rank 1
4899 15:36:17.391980 SW Impedance : PASS
4900 15:36:17.395179 DUTY Scan : NO K
4901 15:36:17.398025 ZQ Calibration : PASS
4902 15:36:17.398106 Jitter Meter : NO K
4903 15:36:17.401586 CBT Training : PASS
4904 15:36:17.405122 Write leveling : PASS
4905 15:36:17.405207 RX DQS gating : PASS
4906 15:36:17.408224 RX DQ/DQS(RDDQC) : PASS
4907 15:36:17.411771 TX DQ/DQS : PASS
4908 15:36:17.411877 RX DATLAT : PASS
4909 15:36:17.414558 RX DQ/DQS(Engine): PASS
4910 15:36:17.418175 TX OE : NO K
4911 15:36:17.418259 All Pass.
4912 15:36:17.418323
4913 15:36:17.418382 DramC Write-DBI off
4914 15:36:17.421700 PER_BANK_REFRESH: Hybrid Mode
4915 15:36:17.425263 TX_TRACKING: ON
4916 15:36:17.431320 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4917 15:36:17.434458 [FAST_K] Save calibration result to emmc
4918 15:36:17.441336 dramc_set_vcore_voltage set vcore to 662500
4919 15:36:17.441417 Read voltage for 933, 3
4920 15:36:17.444693 Vio18 = 0
4921 15:36:17.444773 Vcore = 662500
4922 15:36:17.444837 Vdram = 0
4923 15:36:17.447829 Vddq = 0
4924 15:36:17.447928 Vmddr = 0
4925 15:36:17.451111 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4926 15:36:17.457487 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4927 15:36:17.460931 MEM_TYPE=3, freq_sel=17
4928 15:36:17.464257 sv_algorithm_assistance_LP4_1600
4929 15:36:17.467751 ============ PULL DRAM RESETB DOWN ============
4930 15:36:17.471017 ========== PULL DRAM RESETB DOWN end =========
4931 15:36:17.474505 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4932 15:36:17.477447 ===================================
4933 15:36:17.480826 LPDDR4 DRAM CONFIGURATION
4934 15:36:17.484317 ===================================
4935 15:36:17.487411 EX_ROW_EN[0] = 0x0
4936 15:36:17.487486 EX_ROW_EN[1] = 0x0
4937 15:36:17.490908 LP4Y_EN = 0x0
4938 15:36:17.490984 WORK_FSP = 0x0
4939 15:36:17.494028 WL = 0x3
4940 15:36:17.494110 RL = 0x3
4941 15:36:17.497575 BL = 0x2
4942 15:36:17.497655 RPST = 0x0
4943 15:36:17.500509 RD_PRE = 0x0
4944 15:36:17.504369 WR_PRE = 0x1
4945 15:36:17.504450 WR_PST = 0x0
4946 15:36:17.506996 DBI_WR = 0x0
4947 15:36:17.507076 DBI_RD = 0x0
4948 15:36:17.510460 OTF = 0x1
4949 15:36:17.513677 ===================================
4950 15:36:17.517197 ===================================
4951 15:36:17.517278 ANA top config
4952 15:36:17.520596 ===================================
4953 15:36:17.524019 DLL_ASYNC_EN = 0
4954 15:36:17.526966 ALL_SLAVE_EN = 1
4955 15:36:17.527041 NEW_RANK_MODE = 1
4956 15:36:17.530448 DLL_IDLE_MODE = 1
4957 15:36:17.533463 LP45_APHY_COMB_EN = 1
4958 15:36:17.536827 TX_ODT_DIS = 1
4959 15:36:17.536926 NEW_8X_MODE = 1
4960 15:36:17.540231 ===================================
4961 15:36:17.543828 ===================================
4962 15:36:17.546725 data_rate = 1866
4963 15:36:17.550141 CKR = 1
4964 15:36:17.553771 DQ_P2S_RATIO = 8
4965 15:36:17.556676 ===================================
4966 15:36:17.560188 CA_P2S_RATIO = 8
4967 15:36:17.563388 DQ_CA_OPEN = 0
4968 15:36:17.563469 DQ_SEMI_OPEN = 0
4969 15:36:17.566857 CA_SEMI_OPEN = 0
4970 15:36:17.570085 CA_FULL_RATE = 0
4971 15:36:17.573661 DQ_CKDIV4_EN = 1
4972 15:36:17.577109 CA_CKDIV4_EN = 1
4973 15:36:17.579998 CA_PREDIV_EN = 0
4974 15:36:17.583284 PH8_DLY = 0
4975 15:36:17.583366 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4976 15:36:17.586579 DQ_AAMCK_DIV = 4
4977 15:36:17.590019 CA_AAMCK_DIV = 4
4978 15:36:17.593293 CA_ADMCK_DIV = 4
4979 15:36:17.596487 DQ_TRACK_CA_EN = 0
4980 15:36:17.600125 CA_PICK = 933
4981 15:36:17.600205 CA_MCKIO = 933
4982 15:36:17.603062 MCKIO_SEMI = 0
4983 15:36:17.606390 PLL_FREQ = 3732
4984 15:36:17.609531 DQ_UI_PI_RATIO = 32
4985 15:36:17.613191 CA_UI_PI_RATIO = 0
4986 15:36:17.616253 ===================================
4987 15:36:17.619415 ===================================
4988 15:36:17.623009 memory_type:LPDDR4
4989 15:36:17.623090 GP_NUM : 10
4990 15:36:17.626308 SRAM_EN : 1
4991 15:36:17.626388 MD32_EN : 0
4992 15:36:17.629376 ===================================
4993 15:36:17.632752 [ANA_INIT] >>>>>>>>>>>>>>
4994 15:36:17.636233 <<<<<< [CONFIGURE PHASE]: ANA_TX
4995 15:36:17.639530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4996 15:36:17.642468 ===================================
4997 15:36:17.645808 data_rate = 1866,PCW = 0X8f00
4998 15:36:17.649467 ===================================
4999 15:36:17.652718 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5000 15:36:17.659347 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 15:36:17.662662 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 15:36:17.669153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5003 15:36:17.672586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5004 15:36:17.675712 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5005 15:36:17.675794 [ANA_INIT] flow start
5006 15:36:17.678983 [ANA_INIT] PLL >>>>>>>>
5007 15:36:17.682040 [ANA_INIT] PLL <<<<<<<<
5008 15:36:17.685416 [ANA_INIT] MIDPI >>>>>>>>
5009 15:36:17.685497 [ANA_INIT] MIDPI <<<<<<<<
5010 15:36:17.688744 [ANA_INIT] DLL >>>>>>>>
5011 15:36:17.692492 [ANA_INIT] flow end
5012 15:36:17.695334 ============ LP4 DIFF to SE enter ============
5013 15:36:17.698997 ============ LP4 DIFF to SE exit ============
5014 15:36:17.702066 [ANA_INIT] <<<<<<<<<<<<<
5015 15:36:17.705384 [Flow] Enable top DCM control >>>>>
5016 15:36:17.708892 [Flow] Enable top DCM control <<<<<
5017 15:36:17.711725 Enable DLL master slave shuffle
5018 15:36:17.715639 ==============================================================
5019 15:36:17.718261 Gating Mode config
5020 15:36:17.724708 ==============================================================
5021 15:36:17.724790 Config description:
5022 15:36:17.735219 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5023 15:36:17.741658 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5024 15:36:17.745148 SELPH_MODE 0: By rank 1: By Phase
5025 15:36:17.751250 ==============================================================
5026 15:36:17.755023 GAT_TRACK_EN = 1
5027 15:36:17.757894 RX_GATING_MODE = 2
5028 15:36:17.761126 RX_GATING_TRACK_MODE = 2
5029 15:36:17.764526 SELPH_MODE = 1
5030 15:36:17.767972 PICG_EARLY_EN = 1
5031 15:36:17.771169 VALID_LAT_VALUE = 1
5032 15:36:17.774902 ==============================================================
5033 15:36:17.778342 Enter into Gating configuration >>>>
5034 15:36:17.780951 Exit from Gating configuration <<<<
5035 15:36:17.784429 Enter into DVFS_PRE_config >>>>>
5036 15:36:17.797608 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5037 15:36:17.801048 Exit from DVFS_PRE_config <<<<<
5038 15:36:17.804455 Enter into PICG configuration >>>>
5039 15:36:17.804538 Exit from PICG configuration <<<<
5040 15:36:17.807327 [RX_INPUT] configuration >>>>>
5041 15:36:17.810525 [RX_INPUT] configuration <<<<<
5042 15:36:17.817238 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5043 15:36:17.820627 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5044 15:36:17.827448 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5045 15:36:17.833695 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5046 15:36:17.840298 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5047 15:36:17.847047 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5048 15:36:17.850035 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5049 15:36:17.853524 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5050 15:36:17.860418 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5051 15:36:17.863631 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5052 15:36:17.866716 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5053 15:36:17.869931 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5054 15:36:17.873454 ===================================
5055 15:36:17.876552 LPDDR4 DRAM CONFIGURATION
5056 15:36:17.884056 ===================================
5057 15:36:17.884153 EX_ROW_EN[0] = 0x0
5058 15:36:17.884218 EX_ROW_EN[1] = 0x0
5059 15:36:17.886444 LP4Y_EN = 0x0
5060 15:36:17.886550 WORK_FSP = 0x0
5061 15:36:17.889592 WL = 0x3
5062 15:36:17.889673 RL = 0x3
5063 15:36:17.893014 BL = 0x2
5064 15:36:17.893095 RPST = 0x0
5065 15:36:17.896524 RD_PRE = 0x0
5066 15:36:17.900009 WR_PRE = 0x1
5067 15:36:17.900090 WR_PST = 0x0
5068 15:36:17.903069 DBI_WR = 0x0
5069 15:36:17.903151 DBI_RD = 0x0
5070 15:36:17.906032 OTF = 0x1
5071 15:36:17.909467 ===================================
5072 15:36:17.912960 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5073 15:36:17.916290 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5074 15:36:17.919641 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5075 15:36:17.923229 ===================================
5076 15:36:17.925993 LPDDR4 DRAM CONFIGURATION
5077 15:36:17.930046 ===================================
5078 15:36:17.932658 EX_ROW_EN[0] = 0x10
5079 15:36:17.932739 EX_ROW_EN[1] = 0x0
5080 15:36:17.936109 LP4Y_EN = 0x0
5081 15:36:17.936193 WORK_FSP = 0x0
5082 15:36:17.939403 WL = 0x3
5083 15:36:17.939483 RL = 0x3
5084 15:36:17.942716 BL = 0x2
5085 15:36:17.942823 RPST = 0x0
5086 15:36:17.946158 RD_PRE = 0x0
5087 15:36:17.949158 WR_PRE = 0x1
5088 15:36:17.949238 WR_PST = 0x0
5089 15:36:17.952696 DBI_WR = 0x0
5090 15:36:17.952778 DBI_RD = 0x0
5091 15:36:17.955762 OTF = 0x1
5092 15:36:17.959427 ===================================
5093 15:36:17.962354 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5094 15:36:17.967946 nWR fixed to 30
5095 15:36:17.971443 [ModeRegInit_LP4] CH0 RK0
5096 15:36:17.971524 [ModeRegInit_LP4] CH0 RK1
5097 15:36:17.974669 [ModeRegInit_LP4] CH1 RK0
5098 15:36:17.977686 [ModeRegInit_LP4] CH1 RK1
5099 15:36:17.977766 match AC timing 9
5100 15:36:17.984690 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5101 15:36:17.988165 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5102 15:36:17.991152 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5103 15:36:17.998057 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5104 15:36:18.000935 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5105 15:36:18.001017 ==
5106 15:36:18.004294 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 15:36:18.007622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 15:36:18.007702 ==
5109 15:36:18.013886 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 15:36:18.021200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5111 15:36:18.023950 [CA 0] Center 37 (7~68) winsize 62
5112 15:36:18.027444 [CA 1] Center 37 (7~68) winsize 62
5113 15:36:18.030815 [CA 2] Center 34 (4~65) winsize 62
5114 15:36:18.033802 [CA 3] Center 35 (5~65) winsize 61
5115 15:36:18.037233 [CA 4] Center 33 (3~64) winsize 62
5116 15:36:18.040331 [CA 5] Center 33 (3~63) winsize 61
5117 15:36:18.040411
5118 15:36:18.043729 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5119 15:36:18.043810
5120 15:36:18.047009 [CATrainingPosCal] consider 1 rank data
5121 15:36:18.050165 u2DelayCellTimex100 = 270/100 ps
5122 15:36:18.053905 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5123 15:36:18.056910 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5124 15:36:18.060061 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5125 15:36:18.063631 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5126 15:36:18.070034 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5127 15:36:18.073666 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5128 15:36:18.073747
5129 15:36:18.076789 CA PerBit enable=1, Macro0, CA PI delay=33
5130 15:36:18.076870
5131 15:36:18.080121 [CBTSetCACLKResult] CA Dly = 33
5132 15:36:18.080201 CS Dly: 7 (0~38)
5133 15:36:18.080266 ==
5134 15:36:18.083336 Dram Type= 6, Freq= 0, CH_0, rank 1
5135 15:36:18.090231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 15:36:18.090313 ==
5137 15:36:18.093348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5138 15:36:18.099887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5139 15:36:18.103316 [CA 0] Center 37 (7~68) winsize 62
5140 15:36:18.106464 [CA 1] Center 37 (7~68) winsize 62
5141 15:36:18.109695 [CA 2] Center 34 (4~65) winsize 62
5142 15:36:18.112947 [CA 3] Center 34 (4~65) winsize 62
5143 15:36:18.116471 [CA 4] Center 33 (3~64) winsize 62
5144 15:36:18.119895 [CA 5] Center 33 (3~63) winsize 61
5145 15:36:18.119976
5146 15:36:18.122798 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5147 15:36:18.122878
5148 15:36:18.126839 [CATrainingPosCal] consider 2 rank data
5149 15:36:18.129562 u2DelayCellTimex100 = 270/100 ps
5150 15:36:18.133126 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5151 15:36:18.139724 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5152 15:36:18.142931 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5153 15:36:18.146524 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5154 15:36:18.149403 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5155 15:36:18.152890 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5156 15:36:18.152971
5157 15:36:18.156106 CA PerBit enable=1, Macro0, CA PI delay=33
5158 15:36:18.156187
5159 15:36:18.159119 [CBTSetCACLKResult] CA Dly = 33
5160 15:36:18.162957 CS Dly: 7 (0~39)
5161 15:36:18.163038
5162 15:36:18.166362 ----->DramcWriteLeveling(PI) begin...
5163 15:36:18.166444 ==
5164 15:36:18.169192 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 15:36:18.172598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 15:36:18.172683 ==
5167 15:36:18.175941 Write leveling (Byte 0): 34 => 34
5168 15:36:18.179431 Write leveling (Byte 1): 30 => 30
5169 15:36:18.182643 DramcWriteLeveling(PI) end<-----
5170 15:36:18.182724
5171 15:36:18.182788 ==
5172 15:36:18.185993 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 15:36:18.189195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 15:36:18.189300 ==
5175 15:36:18.192348 [Gating] SW mode calibration
5176 15:36:18.199010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5177 15:36:18.205644 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5178 15:36:18.208958 0 14 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5179 15:36:18.212460 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
5180 15:36:18.218734 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 15:36:18.222281 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 15:36:18.225318 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 15:36:18.232478 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 15:36:18.235312 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 15:36:18.238731 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5186 15:36:18.245296 0 15 0 | B1->B0 | 3030 2525 | 0 0 | (0 0) (0 0)
5187 15:36:18.248802 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5188 15:36:18.251703 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 15:36:18.258227 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 15:36:18.262083 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 15:36:18.265044 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 15:36:18.271534 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 15:36:18.275437 0 15 28 | B1->B0 | 2423 3838 | 1 1 | (0 0) (0 0)
5194 15:36:18.278203 1 0 0 | B1->B0 | 2e2e 4545 | 1 0 | (0 0) (0 0)
5195 15:36:18.285003 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 15:36:18.288238 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 15:36:18.291476 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 15:36:18.298160 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 15:36:18.301317 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 15:36:18.304748 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 15:36:18.311205 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 15:36:18.314790 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5203 15:36:18.317700 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 15:36:18.324670 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 15:36:18.327975 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 15:36:18.330901 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 15:36:18.337577 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 15:36:18.341126 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 15:36:18.344421 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 15:36:18.351256 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 15:36:18.354037 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 15:36:18.357606 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 15:36:18.363924 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 15:36:18.367364 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 15:36:18.370456 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 15:36:18.376956 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5217 15:36:18.380578 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5218 15:36:18.384246 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5219 15:36:18.387020 Total UI for P1: 0, mck2ui 16
5220 15:36:18.390507 best dqsien dly found for B0: ( 1, 2, 26)
5221 15:36:18.396650 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 15:36:18.396731 Total UI for P1: 0, mck2ui 16
5223 15:36:18.403351 best dqsien dly found for B1: ( 1, 3, 0)
5224 15:36:18.407114 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5225 15:36:18.410032 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5226 15:36:18.410112
5227 15:36:18.413202 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5228 15:36:18.416684 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5229 15:36:18.420035 [Gating] SW calibration Done
5230 15:36:18.420116 ==
5231 15:36:18.423090 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 15:36:18.427001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 15:36:18.427082 ==
5234 15:36:18.430003 RX Vref Scan: 0
5235 15:36:18.430083
5236 15:36:18.430146 RX Vref 0 -> 0, step: 1
5237 15:36:18.430206
5238 15:36:18.433124 RX Delay -80 -> 252, step: 8
5239 15:36:18.436537 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5240 15:36:18.443124 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5241 15:36:18.446285 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5242 15:36:18.449649 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5243 15:36:18.452802 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5244 15:36:18.456045 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5245 15:36:18.460001 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5246 15:36:18.466266 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5247 15:36:18.469491 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5248 15:36:18.472898 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5249 15:36:18.476146 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5250 15:36:18.479722 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5251 15:36:18.485955 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5252 15:36:18.489184 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5253 15:36:18.492668 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5254 15:36:18.496249 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5255 15:36:18.496329 ==
5256 15:36:18.499332 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 15:36:18.505598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 15:36:18.505679 ==
5259 15:36:18.505743 DQS Delay:
5260 15:36:18.505803 DQS0 = 0, DQS1 = 0
5261 15:36:18.509127 DQM Delay:
5262 15:36:18.509213 DQM0 = 98, DQM1 = 86
5263 15:36:18.512568 DQ Delay:
5264 15:36:18.515936 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5265 15:36:18.519629 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5266 15:36:18.523001 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5267 15:36:18.525829 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5268 15:36:18.525908
5269 15:36:18.525972
5270 15:36:18.526037 ==
5271 15:36:18.529155 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 15:36:18.532652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 15:36:18.532732 ==
5274 15:36:18.532816
5275 15:36:18.532878
5276 15:36:18.535455 TX Vref Scan disable
5277 15:36:18.535535 == TX Byte 0 ==
5278 15:36:18.542374 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5279 15:36:18.545243 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5280 15:36:18.548551 == TX Byte 1 ==
5281 15:36:18.552021 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5282 15:36:18.555321 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5283 15:36:18.555401 ==
5284 15:36:18.558313 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 15:36:18.561533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 15:36:18.565226 ==
5287 15:36:18.565307
5288 15:36:18.565371
5289 15:36:18.565430 TX Vref Scan disable
5290 15:36:18.568666 == TX Byte 0 ==
5291 15:36:18.572106 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5292 15:36:18.578782 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5293 15:36:18.578865 == TX Byte 1 ==
5294 15:36:18.581822 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5295 15:36:18.588208 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5296 15:36:18.588324
5297 15:36:18.588400 [DATLAT]
5298 15:36:18.588461 Freq=933, CH0 RK0
5299 15:36:18.588521
5300 15:36:18.591892 DATLAT Default: 0xd
5301 15:36:18.591972 0, 0xFFFF, sum = 0
5302 15:36:18.594956 1, 0xFFFF, sum = 0
5303 15:36:18.598335 2, 0xFFFF, sum = 0
5304 15:36:18.598416 3, 0xFFFF, sum = 0
5305 15:36:18.601779 4, 0xFFFF, sum = 0
5306 15:36:18.601863 5, 0xFFFF, sum = 0
5307 15:36:18.604938 6, 0xFFFF, sum = 0
5308 15:36:18.605019 7, 0xFFFF, sum = 0
5309 15:36:18.608417 8, 0xFFFF, sum = 0
5310 15:36:18.608499 9, 0xFFFF, sum = 0
5311 15:36:18.611362 10, 0x0, sum = 1
5312 15:36:18.611443 11, 0x0, sum = 2
5313 15:36:18.614630 12, 0x0, sum = 3
5314 15:36:18.614724 13, 0x0, sum = 4
5315 15:36:18.614789 best_step = 11
5316 15:36:18.618018
5317 15:36:18.618098 ==
5318 15:36:18.621481 Dram Type= 6, Freq= 0, CH_0, rank 0
5319 15:36:18.624710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 15:36:18.624790 ==
5321 15:36:18.624853 RX Vref Scan: 1
5322 15:36:18.624911
5323 15:36:18.628179 RX Vref 0 -> 0, step: 1
5324 15:36:18.628273
5325 15:36:18.631404 RX Delay -61 -> 252, step: 4
5326 15:36:18.631487
5327 15:36:18.634697 Set Vref, RX VrefLevel [Byte0]: 61
5328 15:36:18.638528 [Byte1]: 49
5329 15:36:18.641292
5330 15:36:18.641372 Final RX Vref Byte 0 = 61 to rank0
5331 15:36:18.644660 Final RX Vref Byte 1 = 49 to rank0
5332 15:36:18.647608 Final RX Vref Byte 0 = 61 to rank1
5333 15:36:18.651094 Final RX Vref Byte 1 = 49 to rank1==
5334 15:36:18.654237 Dram Type= 6, Freq= 0, CH_0, rank 0
5335 15:36:18.660857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 15:36:18.660939 ==
5337 15:36:18.661003 DQS Delay:
5338 15:36:18.664854 DQS0 = 0, DQS1 = 0
5339 15:36:18.664933 DQM Delay:
5340 15:36:18.664996 DQM0 = 97, DQM1 = 85
5341 15:36:18.667771 DQ Delay:
5342 15:36:18.670816 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5343 15:36:18.674030 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5344 15:36:18.677595 DQ8 =78, DQ9 =74, DQ10 =84, DQ11 =80
5345 15:36:18.681075 DQ12 =90, DQ13 =88, DQ14 =96, DQ15 =92
5346 15:36:18.681154
5347 15:36:18.681217
5348 15:36:18.687409 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5349 15:36:18.691175 CH0 RK0: MR19=505, MR18=2E15
5350 15:36:18.697745 CH0_RK0: MR19=0x505, MR18=0x2E15, DQSOSC=407, MR23=63, INC=65, DEC=43
5351 15:36:18.697824
5352 15:36:18.700762 ----->DramcWriteLeveling(PI) begin...
5353 15:36:18.700842 ==
5354 15:36:18.704460 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 15:36:18.707187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 15:36:18.707267 ==
5357 15:36:18.710547 Write leveling (Byte 0): 33 => 33
5358 15:36:18.713988 Write leveling (Byte 1): 32 => 32
5359 15:36:18.716932 DramcWriteLeveling(PI) end<-----
5360 15:36:18.717012
5361 15:36:18.717075 ==
5362 15:36:18.720299 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 15:36:18.723591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 15:36:18.726832 ==
5365 15:36:18.726912 [Gating] SW mode calibration
5366 15:36:18.733539 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5367 15:36:18.740382 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5368 15:36:18.743886 0 14 0 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)
5369 15:36:18.750537 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 15:36:18.753970 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 15:36:18.757277 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 15:36:18.763255 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 15:36:18.766854 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 15:36:18.769920 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 15:36:18.776884 0 14 28 | B1->B0 | 3232 2b2b | 1 0 | (1 0) (1 0)
5376 15:36:18.779926 0 15 0 | B1->B0 | 2f2f 2828 | 0 0 | (0 1) (1 1)
5377 15:36:18.783159 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 15:36:18.790280 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 15:36:18.793141 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 15:36:18.796476 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 15:36:18.803212 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 15:36:18.806202 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 15:36:18.809818 0 15 28 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
5384 15:36:18.816451 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5385 15:36:18.819653 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 15:36:18.823306 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 15:36:18.829532 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 15:36:18.833255 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 15:36:18.836131 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 15:36:18.842638 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 15:36:18.845951 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5392 15:36:18.849130 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5393 15:36:18.855713 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 15:36:18.859082 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 15:36:18.862413 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 15:36:18.869317 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 15:36:18.872292 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 15:36:18.875506 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 15:36:18.882531 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 15:36:18.885259 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 15:36:18.888627 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 15:36:18.895405 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 15:36:18.898799 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 15:36:18.901960 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 15:36:18.908234 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 15:36:18.912248 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 15:36:18.915381 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5408 15:36:18.921869 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5409 15:36:18.921949 Total UI for P1: 0, mck2ui 16
5410 15:36:18.928055 best dqsien dly found for B0: ( 1, 2, 28)
5411 15:36:18.931410 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 15:36:18.934877 Total UI for P1: 0, mck2ui 16
5413 15:36:18.937890 best dqsien dly found for B1: ( 1, 2, 30)
5414 15:36:18.942040 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5415 15:36:18.944513 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5416 15:36:18.944593
5417 15:36:18.947993 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5418 15:36:18.951465 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5419 15:36:18.954456 [Gating] SW calibration Done
5420 15:36:18.954565 ==
5421 15:36:18.957839 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 15:36:18.964581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 15:36:18.964687 ==
5424 15:36:18.964787 RX Vref Scan: 0
5425 15:36:18.964889
5426 15:36:18.967760 RX Vref 0 -> 0, step: 1
5427 15:36:18.967842
5428 15:36:18.971199 RX Delay -80 -> 252, step: 8
5429 15:36:18.974585 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5430 15:36:18.978133 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5431 15:36:18.981255 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5432 15:36:18.984142 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5433 15:36:18.987402 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5434 15:36:18.994371 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5435 15:36:18.997343 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5436 15:36:19.000631 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5437 15:36:19.004382 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5438 15:36:19.007442 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5439 15:36:19.014000 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5440 15:36:19.017784 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5441 15:36:19.020614 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5442 15:36:19.024034 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5443 15:36:19.026942 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5444 15:36:19.033740 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5445 15:36:19.033820 ==
5446 15:36:19.037431 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 15:36:19.040369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 15:36:19.040446 ==
5449 15:36:19.040532 DQS Delay:
5450 15:36:19.044126 DQS0 = 0, DQS1 = 0
5451 15:36:19.044201 DQM Delay:
5452 15:36:19.047096 DQM0 = 96, DQM1 = 87
5453 15:36:19.047172 DQ Delay:
5454 15:36:19.050599 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5455 15:36:19.054055 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5456 15:36:19.056912 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5457 15:36:19.060026 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5458 15:36:19.060132
5459 15:36:19.060233
5460 15:36:19.060333 ==
5461 15:36:19.063447 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 15:36:19.066801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 15:36:19.070123 ==
5464 15:36:19.070224
5465 15:36:19.070314
5466 15:36:19.070401 TX Vref Scan disable
5467 15:36:19.073759 == TX Byte 0 ==
5468 15:36:19.077112 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5469 15:36:19.079927 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5470 15:36:19.083234 == TX Byte 1 ==
5471 15:36:19.086810 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5472 15:36:19.089882 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5473 15:36:19.093295 ==
5474 15:36:19.096637 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 15:36:19.099760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 15:36:19.099862 ==
5477 15:36:19.099951
5478 15:36:19.100042
5479 15:36:19.103613 TX Vref Scan disable
5480 15:36:19.103685 == TX Byte 0 ==
5481 15:36:19.109927 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5482 15:36:19.113200 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5483 15:36:19.113272 == TX Byte 1 ==
5484 15:36:19.120103 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5485 15:36:19.123356 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5486 15:36:19.123432
5487 15:36:19.123494 [DATLAT]
5488 15:36:19.127175 Freq=933, CH0 RK1
5489 15:36:19.127252
5490 15:36:19.127315 DATLAT Default: 0xb
5491 15:36:19.129789 0, 0xFFFF, sum = 0
5492 15:36:19.129861 1, 0xFFFF, sum = 0
5493 15:36:19.133190 2, 0xFFFF, sum = 0
5494 15:36:19.133266 3, 0xFFFF, sum = 0
5495 15:36:19.136460 4, 0xFFFF, sum = 0
5496 15:36:19.136537 5, 0xFFFF, sum = 0
5497 15:36:19.139841 6, 0xFFFF, sum = 0
5498 15:36:19.139912 7, 0xFFFF, sum = 0
5499 15:36:19.143049 8, 0xFFFF, sum = 0
5500 15:36:19.146388 9, 0xFFFF, sum = 0
5501 15:36:19.146459 10, 0x0, sum = 1
5502 15:36:19.146529 11, 0x0, sum = 2
5503 15:36:19.149721 12, 0x0, sum = 3
5504 15:36:19.149821 13, 0x0, sum = 4
5505 15:36:19.153058 best_step = 11
5506 15:36:19.153160
5507 15:36:19.153251 ==
5508 15:36:19.156428 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 15:36:19.159595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 15:36:19.159677 ==
5511 15:36:19.163029 RX Vref Scan: 0
5512 15:36:19.163110
5513 15:36:19.163175 RX Vref 0 -> 0, step: 1
5514 15:36:19.163235
5515 15:36:19.166102 RX Delay -61 -> 252, step: 4
5516 15:36:19.173429 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5517 15:36:19.177154 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5518 15:36:19.180012 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5519 15:36:19.183769 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5520 15:36:19.187034 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5521 15:36:19.190255 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5522 15:36:19.196926 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5523 15:36:19.200341 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5524 15:36:19.203678 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5525 15:36:19.206813 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5526 15:36:19.210317 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5527 15:36:19.216625 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5528 15:36:19.220010 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5529 15:36:19.223007 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5530 15:36:19.226817 iDelay=203, Bit 14, Center 98 (11 ~ 186) 176
5531 15:36:19.233292 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5532 15:36:19.233373 ==
5533 15:36:19.236556 Dram Type= 6, Freq= 0, CH_0, rank 1
5534 15:36:19.239944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 15:36:19.240027 ==
5536 15:36:19.240092 DQS Delay:
5537 15:36:19.243327 DQS0 = 0, DQS1 = 0
5538 15:36:19.243409 DQM Delay:
5539 15:36:19.246466 DQM0 = 95, DQM1 = 86
5540 15:36:19.246547 DQ Delay:
5541 15:36:19.250016 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =92
5542 15:36:19.252695 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5543 15:36:19.256028 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5544 15:36:19.259430 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5545 15:36:19.259512
5546 15:36:19.259576
5547 15:36:19.265931 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5548 15:36:19.269383 CH0 RK1: MR19=504, MR18=26F6
5549 15:36:19.276343 CH0_RK1: MR19=0x504, MR18=0x26F6, DQSOSC=409, MR23=63, INC=64, DEC=43
5550 15:36:19.279495 [RxdqsGatingPostProcess] freq 933
5551 15:36:19.285687 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5552 15:36:19.289219 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 15:36:19.292343 best DQS1 dly(2T, 0.5T) = (0, 11)
5554 15:36:19.296133 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 15:36:19.299494 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5556 15:36:19.299576 best DQS0 dly(2T, 0.5T) = (0, 10)
5557 15:36:19.302203 best DQS1 dly(2T, 0.5T) = (0, 10)
5558 15:36:19.305816 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5559 15:36:19.309136 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5560 15:36:19.312330 Pre-setting of DQS Precalculation
5561 15:36:19.318979 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5562 15:36:19.319062 ==
5563 15:36:19.322389 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 15:36:19.325526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 15:36:19.325609 ==
5566 15:36:19.332186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 15:36:19.339081 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5568 15:36:19.342155 [CA 0] Center 36 (6~67) winsize 62
5569 15:36:19.345224 [CA 1] Center 36 (6~67) winsize 62
5570 15:36:19.348612 [CA 2] Center 34 (4~65) winsize 62
5571 15:36:19.351965 [CA 3] Center 33 (3~64) winsize 62
5572 15:36:19.355479 [CA 4] Center 34 (4~64) winsize 61
5573 15:36:19.358338 [CA 5] Center 33 (3~64) winsize 62
5574 15:36:19.358419
5575 15:36:19.362029 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5576 15:36:19.362110
5577 15:36:19.365513 [CATrainingPosCal] consider 1 rank data
5578 15:36:19.368627 u2DelayCellTimex100 = 270/100 ps
5579 15:36:19.371593 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5580 15:36:19.374953 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5581 15:36:19.378178 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5582 15:36:19.381685 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5583 15:36:19.385039 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5584 15:36:19.388262 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5585 15:36:19.388343
5586 15:36:19.394497 CA PerBit enable=1, Macro0, CA PI delay=33
5587 15:36:19.394579
5588 15:36:19.398034 [CBTSetCACLKResult] CA Dly = 33
5589 15:36:19.398116 CS Dly: 6 (0~37)
5590 15:36:19.398181 ==
5591 15:36:19.401499 Dram Type= 6, Freq= 0, CH_1, rank 1
5592 15:36:19.404840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 15:36:19.404923 ==
5594 15:36:19.411600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 15:36:19.418270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5596 15:36:19.421373 [CA 0] Center 36 (6~67) winsize 62
5597 15:36:19.424890 [CA 1] Center 36 (6~67) winsize 62
5598 15:36:19.427773 [CA 2] Center 34 (4~65) winsize 62
5599 15:36:19.431220 [CA 3] Center 33 (3~64) winsize 62
5600 15:36:19.434461 [CA 4] Center 34 (3~65) winsize 63
5601 15:36:19.438073 [CA 5] Center 33 (3~64) winsize 62
5602 15:36:19.438154
5603 15:36:19.441209 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5604 15:36:19.441291
5605 15:36:19.444192 [CATrainingPosCal] consider 2 rank data
5606 15:36:19.447725 u2DelayCellTimex100 = 270/100 ps
5607 15:36:19.451111 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5608 15:36:19.454379 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5609 15:36:19.457686 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5610 15:36:19.460669 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5611 15:36:19.467401 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5612 15:36:19.470629 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5613 15:36:19.470711
5614 15:36:19.474175 CA PerBit enable=1, Macro0, CA PI delay=33
5615 15:36:19.474257
5616 15:36:19.477540 [CBTSetCACLKResult] CA Dly = 33
5617 15:36:19.477621 CS Dly: 7 (0~39)
5618 15:36:19.477685
5619 15:36:19.481054 ----->DramcWriteLeveling(PI) begin...
5620 15:36:19.481138 ==
5621 15:36:19.483721 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 15:36:19.490373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 15:36:19.490455 ==
5624 15:36:19.493580 Write leveling (Byte 0): 25 => 25
5625 15:36:19.496988 Write leveling (Byte 1): 26 => 26
5626 15:36:19.497070 DramcWriteLeveling(PI) end<-----
5627 15:36:19.497135
5628 15:36:19.500146 ==
5629 15:36:19.503736 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 15:36:19.506814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 15:36:19.506896 ==
5632 15:36:19.510434 [Gating] SW mode calibration
5633 15:36:19.516655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5634 15:36:19.520022 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5635 15:36:19.526749 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 15:36:19.530117 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 15:36:19.533736 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 15:36:19.539961 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 15:36:19.543243 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 15:36:19.546528 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 15:36:19.553229 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
5642 15:36:19.556223 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5643 15:36:19.559666 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5644 15:36:19.566498 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 15:36:19.569755 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 15:36:19.572972 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 15:36:19.579363 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 15:36:19.583278 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 15:36:19.586218 0 15 24 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
5650 15:36:19.592608 0 15 28 | B1->B0 | 3939 4141 | 1 0 | (0 0) (0 0)
5651 15:36:19.596156 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 15:36:19.599534 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 15:36:19.605971 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 15:36:19.609191 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 15:36:19.612615 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 15:36:19.619178 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 15:36:19.622709 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5658 15:36:19.626165 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5659 15:36:19.632474 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 15:36:19.635964 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 15:36:19.639487 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 15:36:19.645378 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 15:36:19.649054 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 15:36:19.652219 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 15:36:19.658802 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 15:36:19.662448 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 15:36:19.665565 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 15:36:19.671906 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 15:36:19.675464 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 15:36:19.678542 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 15:36:19.685510 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 15:36:19.688790 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 15:36:19.692216 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5674 15:36:19.698287 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 15:36:19.698370 Total UI for P1: 0, mck2ui 16
5676 15:36:19.705112 best dqsien dly found for B0: ( 1, 2, 24)
5677 15:36:19.705194 Total UI for P1: 0, mck2ui 16
5678 15:36:19.711825 best dqsien dly found for B1: ( 1, 2, 26)
5679 15:36:19.715290 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5680 15:36:19.718122 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5681 15:36:19.718203
5682 15:36:19.721509 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5683 15:36:19.724702 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5684 15:36:19.728156 [Gating] SW calibration Done
5685 15:36:19.728247 ==
5686 15:36:19.731425 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 15:36:19.734769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 15:36:19.734851 ==
5689 15:36:19.738086 RX Vref Scan: 0
5690 15:36:19.738177
5691 15:36:19.738250 RX Vref 0 -> 0, step: 1
5692 15:36:19.738311
5693 15:36:19.741517 RX Delay -80 -> 252, step: 8
5694 15:36:19.748072 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5695 15:36:19.751434 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5696 15:36:19.754894 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5697 15:36:19.758123 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5698 15:36:19.761301 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5699 15:36:19.764585 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5700 15:36:19.771247 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5701 15:36:19.774616 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5702 15:36:19.777707 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5703 15:36:19.781228 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5704 15:36:19.785148 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5705 15:36:19.787946 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5706 15:36:19.794087 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5707 15:36:19.797570 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5708 15:36:19.800759 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5709 15:36:19.804243 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5710 15:36:19.804325 ==
5711 15:36:19.807359 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 15:36:19.811454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 15:36:19.814072 ==
5714 15:36:19.814153 DQS Delay:
5715 15:36:19.814218 DQS0 = 0, DQS1 = 0
5716 15:36:19.817799 DQM Delay:
5717 15:36:19.817880 DQM0 = 102, DQM1 = 91
5718 15:36:19.821020 DQ Delay:
5719 15:36:19.824325 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =103
5720 15:36:19.827595 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5721 15:36:19.830927 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5722 15:36:19.833877 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5723 15:36:19.833958
5724 15:36:19.834022
5725 15:36:19.834082 ==
5726 15:36:19.837644 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 15:36:19.840383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 15:36:19.840466 ==
5729 15:36:19.840530
5730 15:36:19.840591
5731 15:36:19.843668 TX Vref Scan disable
5732 15:36:19.843750 == TX Byte 0 ==
5733 15:36:19.850448 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5734 15:36:19.853720 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5735 15:36:19.857130 == TX Byte 1 ==
5736 15:36:19.860961 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5737 15:36:19.863547 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5738 15:36:19.863629 ==
5739 15:36:19.867579 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 15:36:19.870115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 15:36:19.870197 ==
5742 15:36:19.873420
5743 15:36:19.873501
5744 15:36:19.873565 TX Vref Scan disable
5745 15:36:19.877146 == TX Byte 0 ==
5746 15:36:19.880375 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5747 15:36:19.886825 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5748 15:36:19.886933 == TX Byte 1 ==
5749 15:36:19.890224 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5750 15:36:19.896630 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5751 15:36:19.896713
5752 15:36:19.896777 [DATLAT]
5753 15:36:19.896837 Freq=933, CH1 RK0
5754 15:36:19.896897
5755 15:36:19.900150 DATLAT Default: 0xd
5756 15:36:19.900232 0, 0xFFFF, sum = 0
5757 15:36:19.903393 1, 0xFFFF, sum = 0
5758 15:36:19.907183 2, 0xFFFF, sum = 0
5759 15:36:19.907266 3, 0xFFFF, sum = 0
5760 15:36:19.909855 4, 0xFFFF, sum = 0
5761 15:36:19.909938 5, 0xFFFF, sum = 0
5762 15:36:19.913351 6, 0xFFFF, sum = 0
5763 15:36:19.913434 7, 0xFFFF, sum = 0
5764 15:36:19.916719 8, 0xFFFF, sum = 0
5765 15:36:19.916802 9, 0xFFFF, sum = 0
5766 15:36:19.919755 10, 0x0, sum = 1
5767 15:36:19.919837 11, 0x0, sum = 2
5768 15:36:19.923208 12, 0x0, sum = 3
5769 15:36:19.923291 13, 0x0, sum = 4
5770 15:36:19.923357 best_step = 11
5771 15:36:19.926492
5772 15:36:19.926573 ==
5773 15:36:19.929814 Dram Type= 6, Freq= 0, CH_1, rank 0
5774 15:36:19.933411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 15:36:19.933493 ==
5776 15:36:19.933558 RX Vref Scan: 1
5777 15:36:19.933617
5778 15:36:19.936882 RX Vref 0 -> 0, step: 1
5779 15:36:19.936963
5780 15:36:19.939619 RX Delay -61 -> 252, step: 4
5781 15:36:19.939700
5782 15:36:19.943109 Set Vref, RX VrefLevel [Byte0]: 48
5783 15:36:19.945966 [Byte1]: 53
5784 15:36:19.949393
5785 15:36:19.949474 Final RX Vref Byte 0 = 48 to rank0
5786 15:36:19.952919 Final RX Vref Byte 1 = 53 to rank0
5787 15:36:19.956347 Final RX Vref Byte 0 = 48 to rank1
5788 15:36:19.959758 Final RX Vref Byte 1 = 53 to rank1==
5789 15:36:19.962962 Dram Type= 6, Freq= 0, CH_1, rank 0
5790 15:36:19.969798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 15:36:19.969880 ==
5792 15:36:19.969945 DQS Delay:
5793 15:36:19.970006 DQS0 = 0, DQS1 = 0
5794 15:36:19.972892 DQM Delay:
5795 15:36:19.972973 DQM0 = 101, DQM1 = 94
5796 15:36:19.975951 DQ Delay:
5797 15:36:19.979365 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5798 15:36:19.982728 DQ4 =98, DQ5 =110, DQ6 =112, DQ7 =98
5799 15:36:19.985937 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =84
5800 15:36:19.989339 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5801 15:36:19.989421
5802 15:36:19.989485
5803 15:36:19.996021 [DQSOSCAuto] RK0, (LSB)MR18= 0x2010, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 411 ps
5804 15:36:19.999353 CH1 RK0: MR19=505, MR18=2010
5805 15:36:20.005857 CH1_RK0: MR19=0x505, MR18=0x2010, DQSOSC=411, MR23=63, INC=64, DEC=42
5806 15:36:20.005940
5807 15:36:20.009152 ----->DramcWriteLeveling(PI) begin...
5808 15:36:20.009235 ==
5809 15:36:20.012815 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 15:36:20.015523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 15:36:20.015606 ==
5812 15:36:20.019033 Write leveling (Byte 0): 27 => 27
5813 15:36:20.022509 Write leveling (Byte 1): 29 => 29
5814 15:36:20.025477 DramcWriteLeveling(PI) end<-----
5815 15:36:20.025559
5816 15:36:20.025624 ==
5817 15:36:20.029392 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 15:36:20.035311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 15:36:20.035393 ==
5820 15:36:20.035459 [Gating] SW mode calibration
5821 15:36:20.045092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5822 15:36:20.048353 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5823 15:36:20.054941 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5824 15:36:20.058184 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 15:36:20.061846 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 15:36:20.068127 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 15:36:20.071738 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 15:36:20.075061 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5829 15:36:20.081588 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5830 15:36:20.084659 0 14 28 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (0 1)
5831 15:36:20.087833 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 15:36:20.094519 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 15:36:20.097806 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 15:36:20.100949 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 15:36:20.107739 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 15:36:20.111216 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 15:36:20.114284 0 15 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5838 15:36:20.121312 0 15 28 | B1->B0 | 3b3b 3232 | 1 0 | (0 0) (0 0)
5839 15:36:20.124436 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5840 15:36:20.128154 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 15:36:20.134904 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 15:36:20.137502 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 15:36:20.141045 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 15:36:20.144191 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 15:36:20.150775 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 15:36:20.154357 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5847 15:36:20.157723 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 15:36:20.164010 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 15:36:20.167778 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 15:36:20.170681 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 15:36:20.177520 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 15:36:20.180887 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 15:36:20.184016 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 15:36:20.190612 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 15:36:20.194163 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 15:36:20.197898 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 15:36:20.203895 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 15:36:20.207204 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 15:36:20.210522 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 15:36:20.217433 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5861 15:36:20.220922 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5862 15:36:20.223616 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 15:36:20.227459 Total UI for P1: 0, mck2ui 16
5864 15:36:20.230522 best dqsien dly found for B0: ( 1, 2, 26)
5865 15:36:20.233918 Total UI for P1: 0, mck2ui 16
5866 15:36:20.236750 best dqsien dly found for B1: ( 1, 2, 22)
5867 15:36:20.240152 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5868 15:36:20.243758 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5869 15:36:20.243832
5870 15:36:20.250076 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5871 15:36:20.253312 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5872 15:36:20.256599 [Gating] SW calibration Done
5873 15:36:20.256704 ==
5874 15:36:20.260199 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 15:36:20.263549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 15:36:20.263625 ==
5877 15:36:20.263706 RX Vref Scan: 0
5878 15:36:20.263806
5879 15:36:20.266861 RX Vref 0 -> 0, step: 1
5880 15:36:20.266940
5881 15:36:20.270015 RX Delay -80 -> 252, step: 8
5882 15:36:20.273603 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5883 15:36:20.276798 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5884 15:36:20.283221 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5885 15:36:20.286459 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5886 15:36:20.289887 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5887 15:36:20.293568 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5888 15:36:20.296406 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5889 15:36:20.299814 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5890 15:36:20.306516 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5891 15:36:20.309442 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5892 15:36:20.313114 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5893 15:36:20.316648 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5894 15:36:20.319283 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5895 15:36:20.326108 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5896 15:36:20.329399 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5897 15:36:20.332800 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5898 15:36:20.332881 ==
5899 15:36:20.335985 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 15:36:20.339803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 15:36:20.339885 ==
5902 15:36:20.342510 DQS Delay:
5903 15:36:20.342599 DQS0 = 0, DQS1 = 0
5904 15:36:20.345708 DQM Delay:
5905 15:36:20.345789 DQM0 = 100, DQM1 = 90
5906 15:36:20.345854 DQ Delay:
5907 15:36:20.348940 DQ0 =107, DQ1 =99, DQ2 =83, DQ3 =99
5908 15:36:20.352447 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5909 15:36:20.356014 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5910 15:36:20.359391 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =103
5911 15:36:20.362352
5912 15:36:20.362432
5913 15:36:20.362496 ==
5914 15:36:20.365720 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 15:36:20.369220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 15:36:20.369303 ==
5917 15:36:20.369368
5918 15:36:20.369428
5919 15:36:20.372392 TX Vref Scan disable
5920 15:36:20.372473 == TX Byte 0 ==
5921 15:36:20.379046 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5922 15:36:20.382034 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5923 15:36:20.382116 == TX Byte 1 ==
5924 15:36:20.388989 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5925 15:36:20.392412 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5926 15:36:20.392508 ==
5927 15:36:20.395687 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 15:36:20.398995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 15:36:20.399077 ==
5930 15:36:20.399143
5931 15:36:20.399203
5932 15:36:20.401832 TX Vref Scan disable
5933 15:36:20.405367 == TX Byte 0 ==
5934 15:36:20.408676 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5935 15:36:20.411933 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5936 15:36:20.415409 == TX Byte 1 ==
5937 15:36:20.418526 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5938 15:36:20.422277 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5939 15:36:20.422362
5940 15:36:20.425099 [DATLAT]
5941 15:36:20.425181 Freq=933, CH1 RK1
5942 15:36:20.425246
5943 15:36:20.428854 DATLAT Default: 0xb
5944 15:36:20.428935 0, 0xFFFF, sum = 0
5945 15:36:20.431871 1, 0xFFFF, sum = 0
5946 15:36:20.431983 2, 0xFFFF, sum = 0
5947 15:36:20.435044 3, 0xFFFF, sum = 0
5948 15:36:20.435126 4, 0xFFFF, sum = 0
5949 15:36:20.438257 5, 0xFFFF, sum = 0
5950 15:36:20.438341 6, 0xFFFF, sum = 0
5951 15:36:20.442015 7, 0xFFFF, sum = 0
5952 15:36:20.442097 8, 0xFFFF, sum = 0
5953 15:36:20.445004 9, 0xFFFF, sum = 0
5954 15:36:20.445087 10, 0x0, sum = 1
5955 15:36:20.448398 11, 0x0, sum = 2
5956 15:36:20.448481 12, 0x0, sum = 3
5957 15:36:20.451530 13, 0x0, sum = 4
5958 15:36:20.451613 best_step = 11
5959 15:36:20.451682
5960 15:36:20.451747 ==
5961 15:36:20.454828 Dram Type= 6, Freq= 0, CH_1, rank 1
5962 15:36:20.461347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5963 15:36:20.461429 ==
5964 15:36:20.461495 RX Vref Scan: 0
5965 15:36:20.461558
5966 15:36:20.465258 RX Vref 0 -> 0, step: 1
5967 15:36:20.465339
5968 15:36:20.468015 RX Delay -69 -> 252, step: 4
5969 15:36:20.471319 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5970 15:36:20.478356 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5971 15:36:20.481196 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5972 15:36:20.484676 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5973 15:36:20.488004 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5974 15:36:20.491240 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5975 15:36:20.494719 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5976 15:36:20.501353 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5977 15:36:20.504545 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5978 15:36:20.507938 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
5979 15:36:20.511434 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
5980 15:36:20.514397 iDelay=207, Bit 11, Center 82 (-9 ~ 174) 184
5981 15:36:20.521224 iDelay=207, Bit 12, Center 100 (7 ~ 194) 188
5982 15:36:20.524331 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
5983 15:36:20.527934 iDelay=207, Bit 14, Center 96 (3 ~ 190) 188
5984 15:36:20.531348 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5985 15:36:20.531431 ==
5986 15:36:20.534441 Dram Type= 6, Freq= 0, CH_1, rank 1
5987 15:36:20.537349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5988 15:36:20.541412 ==
5989 15:36:20.541497 DQS Delay:
5990 15:36:20.541582 DQS0 = 0, DQS1 = 0
5991 15:36:20.544221 DQM Delay:
5992 15:36:20.544303 DQM0 = 101, DQM1 = 92
5993 15:36:20.547524 DQ Delay:
5994 15:36:20.550891 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
5995 15:36:20.554094 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =98
5996 15:36:20.557192 DQ8 =82, DQ9 =82, DQ10 =92, DQ11 =82
5997 15:36:20.560865 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =102
5998 15:36:20.560946
5999 15:36:20.561011
6000 15:36:20.567249 [DQSOSCAuto] RK1, (LSB)MR18= 0x600, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
6001 15:36:20.570759 CH1 RK1: MR19=505, MR18=600
6002 15:36:20.577497 CH1_RK1: MR19=0x505, MR18=0x600, DQSOSC=420, MR23=63, INC=61, DEC=40
6003 15:36:20.580888 [RxdqsGatingPostProcess] freq 933
6004 15:36:20.584220 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6005 15:36:20.587038 best DQS0 dly(2T, 0.5T) = (0, 10)
6006 15:36:20.590672 best DQS1 dly(2T, 0.5T) = (0, 10)
6007 15:36:20.593574 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6008 15:36:20.596868 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6009 15:36:20.600119 best DQS0 dly(2T, 0.5T) = (0, 10)
6010 15:36:20.603498 best DQS1 dly(2T, 0.5T) = (0, 10)
6011 15:36:20.606689 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6012 15:36:20.610101 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6013 15:36:20.613805 Pre-setting of DQS Precalculation
6014 15:36:20.616402 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6015 15:36:20.626570 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6016 15:36:20.632967 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6017 15:36:20.633050
6018 15:36:20.633114
6019 15:36:20.636657 [Calibration Summary] 1866 Mbps
6020 15:36:20.636739 CH 0, Rank 0
6021 15:36:20.639977 SW Impedance : PASS
6022 15:36:20.640058 DUTY Scan : NO K
6023 15:36:20.643320 ZQ Calibration : PASS
6024 15:36:20.646298 Jitter Meter : NO K
6025 15:36:20.646380 CBT Training : PASS
6026 15:36:20.649503 Write leveling : PASS
6027 15:36:20.652979 RX DQS gating : PASS
6028 15:36:20.653128 RX DQ/DQS(RDDQC) : PASS
6029 15:36:20.656104 TX DQ/DQS : PASS
6030 15:36:20.659409 RX DATLAT : PASS
6031 15:36:20.659491 RX DQ/DQS(Engine): PASS
6032 15:36:20.662688 TX OE : NO K
6033 15:36:20.662769 All Pass.
6034 15:36:20.662834
6035 15:36:20.666197 CH 0, Rank 1
6036 15:36:20.666278 SW Impedance : PASS
6037 15:36:20.669224 DUTY Scan : NO K
6038 15:36:20.672821 ZQ Calibration : PASS
6039 15:36:20.672902 Jitter Meter : NO K
6040 15:36:20.676225 CBT Training : PASS
6041 15:36:20.679191 Write leveling : PASS
6042 15:36:20.679272 RX DQS gating : PASS
6043 15:36:20.682826 RX DQ/DQS(RDDQC) : PASS
6044 15:36:20.685844 TX DQ/DQS : PASS
6045 15:36:20.685926 RX DATLAT : PASS
6046 15:36:20.689097 RX DQ/DQS(Engine): PASS
6047 15:36:20.692973 TX OE : NO K
6048 15:36:20.693055 All Pass.
6049 15:36:20.693120
6050 15:36:20.693179 CH 1, Rank 0
6051 15:36:20.695835 SW Impedance : PASS
6052 15:36:20.699163 DUTY Scan : NO K
6053 15:36:20.699245 ZQ Calibration : PASS
6054 15:36:20.702524 Jitter Meter : NO K
6055 15:36:20.705389 CBT Training : PASS
6056 15:36:20.705470 Write leveling : PASS
6057 15:36:20.709390 RX DQS gating : PASS
6058 15:36:20.712164 RX DQ/DQS(RDDQC) : PASS
6059 15:36:20.712245 TX DQ/DQS : PASS
6060 15:36:20.715573 RX DATLAT : PASS
6061 15:36:20.715654 RX DQ/DQS(Engine): PASS
6062 15:36:20.719067 TX OE : NO K
6063 15:36:20.719148 All Pass.
6064 15:36:20.719213
6065 15:36:20.721966 CH 1, Rank 1
6066 15:36:20.722048 SW Impedance : PASS
6067 15:36:20.725818 DUTY Scan : NO K
6068 15:36:20.728485 ZQ Calibration : PASS
6069 15:36:20.728567 Jitter Meter : NO K
6070 15:36:20.732071 CBT Training : PASS
6071 15:36:20.735548 Write leveling : PASS
6072 15:36:20.735629 RX DQS gating : PASS
6073 15:36:20.738765 RX DQ/DQS(RDDQC) : PASS
6074 15:36:20.741755 TX DQ/DQS : PASS
6075 15:36:20.741837 RX DATLAT : PASS
6076 15:36:20.745040 RX DQ/DQS(Engine): PASS
6077 15:36:20.748466 TX OE : NO K
6078 15:36:20.748548 All Pass.
6079 15:36:20.748613
6080 15:36:20.752167 DramC Write-DBI off
6081 15:36:20.752248 PER_BANK_REFRESH: Hybrid Mode
6082 15:36:20.756058 TX_TRACKING: ON
6083 15:36:20.764834 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6084 15:36:20.767857 [FAST_K] Save calibration result to emmc
6085 15:36:20.771288 dramc_set_vcore_voltage set vcore to 650000
6086 15:36:20.771370 Read voltage for 400, 6
6087 15:36:20.774455 Vio18 = 0
6088 15:36:20.774563 Vcore = 650000
6089 15:36:20.774683 Vdram = 0
6090 15:36:20.777951 Vddq = 0
6091 15:36:20.778032 Vmddr = 0
6092 15:36:20.784674 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6093 15:36:20.787975 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6094 15:36:20.791221 MEM_TYPE=3, freq_sel=20
6095 15:36:20.794514 sv_algorithm_assistance_LP4_800
6096 15:36:20.798139 ============ PULL DRAM RESETB DOWN ============
6097 15:36:20.801025 ========== PULL DRAM RESETB DOWN end =========
6098 15:36:20.807401 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6099 15:36:20.811137 ===================================
6100 15:36:20.811229 LPDDR4 DRAM CONFIGURATION
6101 15:36:20.814141 ===================================
6102 15:36:20.817511 EX_ROW_EN[0] = 0x0
6103 15:36:20.820929 EX_ROW_EN[1] = 0x0
6104 15:36:20.821017 LP4Y_EN = 0x0
6105 15:36:20.824297 WORK_FSP = 0x0
6106 15:36:20.824394 WL = 0x2
6107 15:36:20.827375 RL = 0x2
6108 15:36:20.827454 BL = 0x2
6109 15:36:20.830860 RPST = 0x0
6110 15:36:20.830931 RD_PRE = 0x0
6111 15:36:20.834219 WR_PRE = 0x1
6112 15:36:20.834313 WR_PST = 0x0
6113 15:36:20.837820 DBI_WR = 0x0
6114 15:36:20.837923 DBI_RD = 0x0
6115 15:36:20.840971 OTF = 0x1
6116 15:36:20.844175 ===================================
6117 15:36:20.847126 ===================================
6118 15:36:20.847196 ANA top config
6119 15:36:20.850513 ===================================
6120 15:36:20.853834 DLL_ASYNC_EN = 0
6121 15:36:20.857056 ALL_SLAVE_EN = 1
6122 15:36:20.860603 NEW_RANK_MODE = 1
6123 15:36:20.860708 DLL_IDLE_MODE = 1
6124 15:36:20.863986 LP45_APHY_COMB_EN = 1
6125 15:36:20.867061 TX_ODT_DIS = 1
6126 15:36:20.870271 NEW_8X_MODE = 1
6127 15:36:20.873583 ===================================
6128 15:36:20.877455 ===================================
6129 15:36:20.880425 data_rate = 800
6130 15:36:20.880525 CKR = 1
6131 15:36:20.883557 DQ_P2S_RATIO = 4
6132 15:36:20.886609 ===================================
6133 15:36:20.889895 CA_P2S_RATIO = 4
6134 15:36:20.893568 DQ_CA_OPEN = 0
6135 15:36:20.896698 DQ_SEMI_OPEN = 1
6136 15:36:20.899909 CA_SEMI_OPEN = 1
6137 15:36:20.899994 CA_FULL_RATE = 0
6138 15:36:20.903615 DQ_CKDIV4_EN = 0
6139 15:36:20.906492 CA_CKDIV4_EN = 1
6140 15:36:20.910041 CA_PREDIV_EN = 0
6141 15:36:20.913126 PH8_DLY = 0
6142 15:36:20.916621 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6143 15:36:20.916719 DQ_AAMCK_DIV = 0
6144 15:36:20.920103 CA_AAMCK_DIV = 0
6145 15:36:20.922937 CA_ADMCK_DIV = 4
6146 15:36:20.926358 DQ_TRACK_CA_EN = 0
6147 15:36:20.929682 CA_PICK = 800
6148 15:36:20.933167 CA_MCKIO = 400
6149 15:36:20.936490 MCKIO_SEMI = 400
6150 15:36:20.939633 PLL_FREQ = 3016
6151 15:36:20.939727 DQ_UI_PI_RATIO = 32
6152 15:36:20.942668 CA_UI_PI_RATIO = 32
6153 15:36:20.946022 ===================================
6154 15:36:20.949624 ===================================
6155 15:36:20.952500 memory_type:LPDDR4
6156 15:36:20.955884 GP_NUM : 10
6157 15:36:20.955962 SRAM_EN : 1
6158 15:36:20.959303 MD32_EN : 0
6159 15:36:20.962948 ===================================
6160 15:36:20.966227 [ANA_INIT] >>>>>>>>>>>>>>
6161 15:36:20.966328 <<<<<< [CONFIGURE PHASE]: ANA_TX
6162 15:36:20.972432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6163 15:36:20.975700 ===================================
6164 15:36:20.975811 data_rate = 800,PCW = 0X7400
6165 15:36:20.979058 ===================================
6166 15:36:20.982194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6167 15:36:20.988692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6168 15:36:21.002460 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6169 15:36:21.005323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6170 15:36:21.008900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6171 15:36:21.011832 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6172 15:36:21.015287 [ANA_INIT] flow start
6173 15:36:21.015368 [ANA_INIT] PLL >>>>>>>>
6174 15:36:21.018781 [ANA_INIT] PLL <<<<<<<<
6175 15:36:21.022142 [ANA_INIT] MIDPI >>>>>>>>
6176 15:36:21.022225 [ANA_INIT] MIDPI <<<<<<<<
6177 15:36:21.024947 [ANA_INIT] DLL >>>>>>>>
6178 15:36:21.028415 [ANA_INIT] flow end
6179 15:36:21.031864 ============ LP4 DIFF to SE enter ============
6180 15:36:21.034998 ============ LP4 DIFF to SE exit ============
6181 15:36:21.038305 [ANA_INIT] <<<<<<<<<<<<<
6182 15:36:21.041761 [Flow] Enable top DCM control >>>>>
6183 15:36:21.045094 [Flow] Enable top DCM control <<<<<
6184 15:36:21.048647 Enable DLL master slave shuffle
6185 15:36:21.051386 ==============================================================
6186 15:36:21.054837 Gating Mode config
6187 15:36:21.061466 ==============================================================
6188 15:36:21.061549 Config description:
6189 15:36:21.071515 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6190 15:36:21.077729 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6191 15:36:21.085005 SELPH_MODE 0: By rank 1: By Phase
6192 15:36:21.088171 ==============================================================
6193 15:36:21.091450 GAT_TRACK_EN = 0
6194 15:36:21.094440 RX_GATING_MODE = 2
6195 15:36:21.098133 RX_GATING_TRACK_MODE = 2
6196 15:36:21.101424 SELPH_MODE = 1
6197 15:36:21.104230 PICG_EARLY_EN = 1
6198 15:36:21.107570 VALID_LAT_VALUE = 1
6199 15:36:21.111402 ==============================================================
6200 15:36:21.114156 Enter into Gating configuration >>>>
6201 15:36:21.117848 Exit from Gating configuration <<<<
6202 15:36:21.120860 Enter into DVFS_PRE_config >>>>>
6203 15:36:21.134087 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6204 15:36:21.137100 Exit from DVFS_PRE_config <<<<<
6205 15:36:21.140390 Enter into PICG configuration >>>>
6206 15:36:21.144072 Exit from PICG configuration <<<<
6207 15:36:21.144158 [RX_INPUT] configuration >>>>>
6208 15:36:21.146963 [RX_INPUT] configuration <<<<<
6209 15:36:21.153829 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6210 15:36:21.160156 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6211 15:36:21.163470 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6212 15:36:21.170210 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6213 15:36:21.176884 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6214 15:36:21.183464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6215 15:36:21.186955 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6216 15:36:21.190395 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6217 15:36:21.196879 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6218 15:36:21.199945 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6219 15:36:21.203230 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6220 15:36:21.210098 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6221 15:36:21.213642 ===================================
6222 15:36:21.213722 LPDDR4 DRAM CONFIGURATION
6223 15:36:21.216738 ===================================
6224 15:36:21.219906 EX_ROW_EN[0] = 0x0
6225 15:36:21.220014 EX_ROW_EN[1] = 0x0
6226 15:36:21.223391 LP4Y_EN = 0x0
6227 15:36:21.223467 WORK_FSP = 0x0
6228 15:36:21.226811 WL = 0x2
6229 15:36:21.230020 RL = 0x2
6230 15:36:21.230123 BL = 0x2
6231 15:36:21.233267 RPST = 0x0
6232 15:36:21.233343 RD_PRE = 0x0
6233 15:36:21.236208 WR_PRE = 0x1
6234 15:36:21.236281 WR_PST = 0x0
6235 15:36:21.239959 DBI_WR = 0x0
6236 15:36:21.240038 DBI_RD = 0x0
6237 15:36:21.242769 OTF = 0x1
6238 15:36:21.246277 ===================================
6239 15:36:21.249363 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6240 15:36:21.252794 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6241 15:36:21.259486 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6242 15:36:21.262452 ===================================
6243 15:36:21.262535 LPDDR4 DRAM CONFIGURATION
6244 15:36:21.265766 ===================================
6245 15:36:21.269261 EX_ROW_EN[0] = 0x10
6246 15:36:21.272492 EX_ROW_EN[1] = 0x0
6247 15:36:21.272572 LP4Y_EN = 0x0
6248 15:36:21.276052 WORK_FSP = 0x0
6249 15:36:21.276133 WL = 0x2
6250 15:36:21.279154 RL = 0x2
6251 15:36:21.279236 BL = 0x2
6252 15:36:21.282506 RPST = 0x0
6253 15:36:21.282587 RD_PRE = 0x0
6254 15:36:21.285569 WR_PRE = 0x1
6255 15:36:21.285650 WR_PST = 0x0
6256 15:36:21.288817 DBI_WR = 0x0
6257 15:36:21.288898 DBI_RD = 0x0
6258 15:36:21.291993 OTF = 0x1
6259 15:36:21.295480 ===================================
6260 15:36:21.302382 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6261 15:36:21.305716 nWR fixed to 30
6262 15:36:21.305797 [ModeRegInit_LP4] CH0 RK0
6263 15:36:21.308843 [ModeRegInit_LP4] CH0 RK1
6264 15:36:21.312290 [ModeRegInit_LP4] CH1 RK0
6265 15:36:21.315509 [ModeRegInit_LP4] CH1 RK1
6266 15:36:21.315594 match AC timing 19
6267 15:36:21.322113 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6268 15:36:21.325330 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6269 15:36:21.328314 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6270 15:36:21.335463 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6271 15:36:21.338575 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6272 15:36:21.338663 ==
6273 15:36:21.341766 Dram Type= 6, Freq= 0, CH_0, rank 0
6274 15:36:21.345778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 15:36:21.345849 ==
6276 15:36:21.352000 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6277 15:36:21.358189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6278 15:36:21.361713 [CA 0] Center 36 (8~64) winsize 57
6279 15:36:21.364998 [CA 1] Center 36 (8~64) winsize 57
6280 15:36:21.365100 [CA 2] Center 36 (8~64) winsize 57
6281 15:36:21.367951 [CA 3] Center 36 (8~64) winsize 57
6282 15:36:21.371749 [CA 4] Center 36 (8~64) winsize 57
6283 15:36:21.374899 [CA 5] Center 36 (8~64) winsize 57
6284 15:36:21.374973
6285 15:36:21.378293 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6286 15:36:21.381313
6287 15:36:21.384377 [CATrainingPosCal] consider 1 rank data
6288 15:36:21.387746 u2DelayCellTimex100 = 270/100 ps
6289 15:36:21.391311 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 15:36:21.394532 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 15:36:21.398041 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 15:36:21.401487 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 15:36:21.404381 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 15:36:21.407850 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 15:36:21.407922
6296 15:36:21.411052 CA PerBit enable=1, Macro0, CA PI delay=36
6297 15:36:21.411124
6298 15:36:21.414456 [CBTSetCACLKResult] CA Dly = 36
6299 15:36:21.417570 CS Dly: 1 (0~32)
6300 15:36:21.417656 ==
6301 15:36:21.420934 Dram Type= 6, Freq= 0, CH_0, rank 1
6302 15:36:21.424730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 15:36:21.424811 ==
6304 15:36:21.430703 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6305 15:36:21.437270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6306 15:36:21.437350 [CA 0] Center 36 (8~64) winsize 57
6307 15:36:21.440688 [CA 1] Center 36 (8~64) winsize 57
6308 15:36:21.443831 [CA 2] Center 36 (8~64) winsize 57
6309 15:36:21.447224 [CA 3] Center 36 (8~64) winsize 57
6310 15:36:21.450400 [CA 4] Center 36 (8~64) winsize 57
6311 15:36:21.453602 [CA 5] Center 36 (8~64) winsize 57
6312 15:36:21.453702
6313 15:36:21.457059 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6314 15:36:21.457162
6315 15:36:21.463702 [CATrainingPosCal] consider 2 rank data
6316 15:36:21.463810 u2DelayCellTimex100 = 270/100 ps
6317 15:36:21.467180 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 15:36:21.474116 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 15:36:21.476683 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 15:36:21.480135 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 15:36:21.483707 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 15:36:21.486910 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 15:36:21.486995
6324 15:36:21.490346 CA PerBit enable=1, Macro0, CA PI delay=36
6325 15:36:21.490428
6326 15:36:21.493703 [CBTSetCACLKResult] CA Dly = 36
6327 15:36:21.496556 CS Dly: 1 (0~32)
6328 15:36:21.496627
6329 15:36:21.500334 ----->DramcWriteLeveling(PI) begin...
6330 15:36:21.500423 ==
6331 15:36:21.503401 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 15:36:21.506898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 15:36:21.506970 ==
6334 15:36:21.510236 Write leveling (Byte 0): 40 => 8
6335 15:36:21.513012 Write leveling (Byte 1): 32 => 0
6336 15:36:21.516413 DramcWriteLeveling(PI) end<-----
6337 15:36:21.516486
6338 15:36:21.516547 ==
6339 15:36:21.519717 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 15:36:21.523389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 15:36:21.523463 ==
6342 15:36:21.526502 [Gating] SW mode calibration
6343 15:36:21.532774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6344 15:36:21.539450 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6345 15:36:21.543102 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6346 15:36:21.545916 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6347 15:36:21.552774 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6348 15:36:21.555726 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6349 15:36:21.559079 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 15:36:21.566106 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 15:36:21.569540 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 15:36:21.572605 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 15:36:21.578944 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6354 15:36:21.582678 Total UI for P1: 0, mck2ui 16
6355 15:36:21.585713 best dqsien dly found for B0: ( 0, 14, 24)
6356 15:36:21.585784 Total UI for P1: 0, mck2ui 16
6357 15:36:21.592260 best dqsien dly found for B1: ( 0, 14, 24)
6358 15:36:21.595685 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6359 15:36:21.599018 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6360 15:36:21.599093
6361 15:36:21.602730 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6362 15:36:21.605971 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6363 15:36:21.608872 [Gating] SW calibration Done
6364 15:36:21.608977 ==
6365 15:36:21.612029 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 15:36:21.615380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 15:36:21.615477 ==
6368 15:36:21.618832 RX Vref Scan: 0
6369 15:36:21.618928
6370 15:36:21.621892 RX Vref 0 -> 0, step: 1
6371 15:36:21.621977
6372 15:36:21.622044 RX Delay -410 -> 252, step: 16
6373 15:36:21.629149 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6374 15:36:21.631849 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6375 15:36:21.635783 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6376 15:36:21.638649 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6377 15:36:21.645506 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6378 15:36:21.648724 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6379 15:36:21.651723 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6380 15:36:21.658364 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6381 15:36:21.661814 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6382 15:36:21.665162 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6383 15:36:21.668476 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6384 15:36:21.675071 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6385 15:36:21.678329 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6386 15:36:21.681647 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6387 15:36:21.684918 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6388 15:36:21.691576 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6389 15:36:21.691657 ==
6390 15:36:21.694570 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 15:36:21.698113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 15:36:21.698194 ==
6393 15:36:21.698259 DQS Delay:
6394 15:36:21.701590 DQS0 = 43, DQS1 = 59
6395 15:36:21.701671 DQM Delay:
6396 15:36:21.704795 DQM0 = 10, DQM1 = 13
6397 15:36:21.704876 DQ Delay:
6398 15:36:21.707900 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6399 15:36:21.711199 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6400 15:36:21.714772 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6401 15:36:21.717755 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6402 15:36:21.717836
6403 15:36:21.717899
6404 15:36:21.717958 ==
6405 15:36:21.720938 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 15:36:21.724629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 15:36:21.724737 ==
6408 15:36:21.724839
6409 15:36:21.727949
6410 15:36:21.728038 TX Vref Scan disable
6411 15:36:21.731391 == TX Byte 0 ==
6412 15:36:21.734655 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6413 15:36:21.737700 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6414 15:36:21.741302 == TX Byte 1 ==
6415 15:36:21.744765 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6416 15:36:21.747383 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6417 15:36:21.747475 ==
6418 15:36:21.750948 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 15:36:21.754514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 15:36:21.757490 ==
6421 15:36:21.757601
6422 15:36:21.757686
6423 15:36:21.757765 TX Vref Scan disable
6424 15:36:21.761285 == TX Byte 0 ==
6425 15:36:21.763899 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6426 15:36:21.767247 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6427 15:36:21.771007 == TX Byte 1 ==
6428 15:36:21.773940 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6429 15:36:21.777402 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6430 15:36:21.777502
6431 15:36:21.781082 [DATLAT]
6432 15:36:21.781181 Freq=400, CH0 RK0
6433 15:36:21.781265
6434 15:36:21.783809 DATLAT Default: 0xf
6435 15:36:21.783884 0, 0xFFFF, sum = 0
6436 15:36:21.787510 1, 0xFFFF, sum = 0
6437 15:36:21.787588 2, 0xFFFF, sum = 0
6438 15:36:21.790496 3, 0xFFFF, sum = 0
6439 15:36:21.790616 4, 0xFFFF, sum = 0
6440 15:36:21.794260 5, 0xFFFF, sum = 0
6441 15:36:21.794338 6, 0xFFFF, sum = 0
6442 15:36:21.797204 7, 0xFFFF, sum = 0
6443 15:36:21.797308 8, 0xFFFF, sum = 0
6444 15:36:21.800358 9, 0xFFFF, sum = 0
6445 15:36:21.803807 10, 0xFFFF, sum = 0
6446 15:36:21.803913 11, 0xFFFF, sum = 0
6447 15:36:21.806948 12, 0xFFFF, sum = 0
6448 15:36:21.807029 13, 0x0, sum = 1
6449 15:36:21.810043 14, 0x0, sum = 2
6450 15:36:21.810122 15, 0x0, sum = 3
6451 15:36:21.810224 16, 0x0, sum = 4
6452 15:36:21.813634 best_step = 14
6453 15:36:21.813709
6454 15:36:21.813790 ==
6455 15:36:21.816920 Dram Type= 6, Freq= 0, CH_0, rank 0
6456 15:36:21.820150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 15:36:21.820252 ==
6458 15:36:21.823752 RX Vref Scan: 1
6459 15:36:21.823832
6460 15:36:21.827178 RX Vref 0 -> 0, step: 1
6461 15:36:21.827251
6462 15:36:21.827331 RX Delay -359 -> 252, step: 8
6463 15:36:21.827409
6464 15:36:21.829921 Set Vref, RX VrefLevel [Byte0]: 61
6465 15:36:21.833206 [Byte1]: 49
6466 15:36:21.839074
6467 15:36:21.839151 Final RX Vref Byte 0 = 61 to rank0
6468 15:36:21.842199 Final RX Vref Byte 1 = 49 to rank0
6469 15:36:21.845053 Final RX Vref Byte 0 = 61 to rank1
6470 15:36:21.848396 Final RX Vref Byte 1 = 49 to rank1==
6471 15:36:21.851840 Dram Type= 6, Freq= 0, CH_0, rank 0
6472 15:36:21.858743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 15:36:21.858834 ==
6474 15:36:21.858897 DQS Delay:
6475 15:36:21.861649 DQS0 = 48, DQS1 = 60
6476 15:36:21.861718 DQM Delay:
6477 15:36:21.861778 DQM0 = 11, DQM1 = 12
6478 15:36:21.865199 DQ Delay:
6479 15:36:21.868399 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6480 15:36:21.871989 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6481 15:36:21.872086 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6482 15:36:21.878108 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6483 15:36:21.878180
6484 15:36:21.878252
6485 15:36:21.884972 [DQSOSCAuto] RK0, (LSB)MR18= 0xbc7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6486 15:36:21.888478 CH0 RK0: MR19=C0C, MR18=BC7F
6487 15:36:21.894889 CH0_RK0: MR19=0xC0C, MR18=0xBC7F, DQSOSC=386, MR23=63, INC=396, DEC=264
6488 15:36:21.894972 ==
6489 15:36:21.898360 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 15:36:21.901545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 15:36:21.901642 ==
6492 15:36:21.904688 [Gating] SW mode calibration
6493 15:36:21.911245 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6494 15:36:21.918726 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6495 15:36:21.921928 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6496 15:36:21.924769 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6497 15:36:21.931048 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6498 15:36:21.934759 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6499 15:36:21.937498 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 15:36:21.944350 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 15:36:21.947737 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 15:36:21.951265 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 15:36:21.957512 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6504 15:36:21.957593 Total UI for P1: 0, mck2ui 16
6505 15:36:21.964247 best dqsien dly found for B0: ( 0, 14, 24)
6506 15:36:21.964328 Total UI for P1: 0, mck2ui 16
6507 15:36:21.970993 best dqsien dly found for B1: ( 0, 14, 24)
6508 15:36:21.974533 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6509 15:36:21.977710 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6510 15:36:21.977791
6511 15:36:21.980736 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6512 15:36:21.984549 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6513 15:36:21.987654 [Gating] SW calibration Done
6514 15:36:21.987735 ==
6515 15:36:21.990522 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 15:36:21.993927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 15:36:21.994018 ==
6518 15:36:21.997471 RX Vref Scan: 0
6519 15:36:21.997552
6520 15:36:21.997644 RX Vref 0 -> 0, step: 1
6521 15:36:22.000757
6522 15:36:22.000838 RX Delay -410 -> 252, step: 16
6523 15:36:22.006948 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6524 15:36:22.010352 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6525 15:36:22.013564 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6526 15:36:22.016865 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6527 15:36:22.023702 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6528 15:36:22.027047 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6529 15:36:22.029902 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6530 15:36:22.036687 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6531 15:36:22.040816 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6532 15:36:22.044128 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6533 15:36:22.046584 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6534 15:36:22.053538 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6535 15:36:22.056273 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6536 15:36:22.059485 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6537 15:36:22.062923 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6538 15:36:22.069808 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6539 15:36:22.069890 ==
6540 15:36:22.072714 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 15:36:22.076078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 15:36:22.076159 ==
6543 15:36:22.076224 DQS Delay:
6544 15:36:22.079465 DQS0 = 43, DQS1 = 59
6545 15:36:22.079545 DQM Delay:
6546 15:36:22.082792 DQM0 = 10, DQM1 = 16
6547 15:36:22.082872 DQ Delay:
6548 15:36:22.086234 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6549 15:36:22.089244 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6550 15:36:22.092699 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6551 15:36:22.095686 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6552 15:36:22.095767
6553 15:36:22.095831
6554 15:36:22.095890 ==
6555 15:36:22.099095 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 15:36:22.102308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 15:36:22.105725 ==
6558 15:36:22.105806
6559 15:36:22.105873
6560 15:36:22.105934 TX Vref Scan disable
6561 15:36:22.109386 == TX Byte 0 ==
6562 15:36:22.112890 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6563 15:36:22.115837 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6564 15:36:22.118939 == TX Byte 1 ==
6565 15:36:22.122120 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6566 15:36:22.125284 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6567 15:36:22.125365 ==
6568 15:36:22.128669 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 15:36:22.135176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 15:36:22.135257 ==
6571 15:36:22.135322
6572 15:36:22.135380
6573 15:36:22.135437 TX Vref Scan disable
6574 15:36:22.138655 == TX Byte 0 ==
6575 15:36:22.142165 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6576 15:36:22.145032 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6577 15:36:22.148972 == TX Byte 1 ==
6578 15:36:22.151652 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6579 15:36:22.155094 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6580 15:36:22.155176
6581 15:36:22.158082 [DATLAT]
6582 15:36:22.158162 Freq=400, CH0 RK1
6583 15:36:22.158227
6584 15:36:22.161851 DATLAT Default: 0xe
6585 15:36:22.161932 0, 0xFFFF, sum = 0
6586 15:36:22.164707 1, 0xFFFF, sum = 0
6587 15:36:22.164789 2, 0xFFFF, sum = 0
6588 15:36:22.167982 3, 0xFFFF, sum = 0
6589 15:36:22.168064 4, 0xFFFF, sum = 0
6590 15:36:22.171480 5, 0xFFFF, sum = 0
6591 15:36:22.171562 6, 0xFFFF, sum = 0
6592 15:36:22.174655 7, 0xFFFF, sum = 0
6593 15:36:22.178297 8, 0xFFFF, sum = 0
6594 15:36:22.178379 9, 0xFFFF, sum = 0
6595 15:36:22.181209 10, 0xFFFF, sum = 0
6596 15:36:22.181291 11, 0xFFFF, sum = 0
6597 15:36:22.184839 12, 0xFFFF, sum = 0
6598 15:36:22.184921 13, 0x0, sum = 1
6599 15:36:22.187886 14, 0x0, sum = 2
6600 15:36:22.187969 15, 0x0, sum = 3
6601 15:36:22.191046 16, 0x0, sum = 4
6602 15:36:22.191129 best_step = 14
6603 15:36:22.191196
6604 15:36:22.191256 ==
6605 15:36:22.194522 Dram Type= 6, Freq= 0, CH_0, rank 1
6606 15:36:22.197632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 15:36:22.197713 ==
6608 15:36:22.201435 RX Vref Scan: 0
6609 15:36:22.201515
6610 15:36:22.204194 RX Vref 0 -> 0, step: 1
6611 15:36:22.204275
6612 15:36:22.204339 RX Delay -359 -> 252, step: 8
6613 15:36:22.213487 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6614 15:36:22.216436 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6615 15:36:22.219746 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6616 15:36:22.226144 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6617 15:36:22.229959 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6618 15:36:22.233105 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6619 15:36:22.236508 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6620 15:36:22.242543 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6621 15:36:22.246399 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6622 15:36:22.249264 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6623 15:36:22.252544 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6624 15:36:22.259250 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6625 15:36:22.262750 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6626 15:36:22.266093 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6627 15:36:22.269057 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6628 15:36:22.276165 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6629 15:36:22.276274 ==
6630 15:36:22.279346 Dram Type= 6, Freq= 0, CH_0, rank 1
6631 15:36:22.282182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 15:36:22.282264 ==
6633 15:36:22.282328 DQS Delay:
6634 15:36:22.285919 DQS0 = 44, DQS1 = 60
6635 15:36:22.285999 DQM Delay:
6636 15:36:22.288946 DQM0 = 8, DQM1 = 16
6637 15:36:22.289027 DQ Delay:
6638 15:36:22.292310 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6639 15:36:22.295788 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6640 15:36:22.298978 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6641 15:36:22.302509 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6642 15:36:22.302609
6643 15:36:22.302689
6644 15:36:22.309140 [DQSOSCAuto] RK1, (LSB)MR18= 0xb943, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6645 15:36:22.312706 CH0 RK1: MR19=C0C, MR18=B943
6646 15:36:22.318556 CH0_RK1: MR19=0xC0C, MR18=0xB943, DQSOSC=386, MR23=63, INC=396, DEC=264
6647 15:36:22.322057 [RxdqsGatingPostProcess] freq 400
6648 15:36:22.328549 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6649 15:36:22.332126 best DQS0 dly(2T, 0.5T) = (0, 10)
6650 15:36:22.335119 best DQS1 dly(2T, 0.5T) = (0, 10)
6651 15:36:22.338691 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6652 15:36:22.341616 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6653 15:36:22.341713 best DQS0 dly(2T, 0.5T) = (0, 10)
6654 15:36:22.344929 best DQS1 dly(2T, 0.5T) = (0, 10)
6655 15:36:22.348507 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6656 15:36:22.352026 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6657 15:36:22.355000 Pre-setting of DQS Precalculation
6658 15:36:22.361514 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6659 15:36:22.361613 ==
6660 15:36:22.364957 Dram Type= 6, Freq= 0, CH_1, rank 0
6661 15:36:22.367954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 15:36:22.368052 ==
6663 15:36:22.374757 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6664 15:36:22.381880 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6665 15:36:22.384711 [CA 0] Center 36 (8~64) winsize 57
6666 15:36:22.387983 [CA 1] Center 36 (8~64) winsize 57
6667 15:36:22.388055 [CA 2] Center 36 (8~64) winsize 57
6668 15:36:22.391360 [CA 3] Center 36 (8~64) winsize 57
6669 15:36:22.394434 [CA 4] Center 36 (8~64) winsize 57
6670 15:36:22.398100 [CA 5] Center 36 (8~64) winsize 57
6671 15:36:22.398199
6672 15:36:22.400980 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6673 15:36:22.404474
6674 15:36:22.407784 [CATrainingPosCal] consider 1 rank data
6675 15:36:22.407856 u2DelayCellTimex100 = 270/100 ps
6676 15:36:22.414573 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 15:36:22.417470 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 15:36:22.420749 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 15:36:22.424081 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 15:36:22.427519 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 15:36:22.430945 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 15:36:22.431016
6683 15:36:22.434691 CA PerBit enable=1, Macro0, CA PI delay=36
6684 15:36:22.434760
6685 15:36:22.437843 [CBTSetCACLKResult] CA Dly = 36
6686 15:36:22.440751 CS Dly: 1 (0~32)
6687 15:36:22.440821 ==
6688 15:36:22.444238 Dram Type= 6, Freq= 0, CH_1, rank 1
6689 15:36:22.447575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 15:36:22.447646 ==
6691 15:36:22.453857 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6692 15:36:22.457545 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6693 15:36:22.460743 [CA 0] Center 36 (8~64) winsize 57
6694 15:36:22.464004 [CA 1] Center 36 (8~64) winsize 57
6695 15:36:22.467482 [CA 2] Center 36 (8~64) winsize 57
6696 15:36:22.470757 [CA 3] Center 36 (8~64) winsize 57
6697 15:36:22.474198 [CA 4] Center 36 (8~64) winsize 57
6698 15:36:22.476961 [CA 5] Center 36 (8~64) winsize 57
6699 15:36:22.477050
6700 15:36:22.480307 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6701 15:36:22.480376
6702 15:36:22.483780 [CATrainingPosCal] consider 2 rank data
6703 15:36:22.487253 u2DelayCellTimex100 = 270/100 ps
6704 15:36:22.490395 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 15:36:22.493873 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 15:36:22.500534 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 15:36:22.503594 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 15:36:22.507134 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 15:36:22.510327 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 15:36:22.510402
6711 15:36:22.513776 CA PerBit enable=1, Macro0, CA PI delay=36
6712 15:36:22.513872
6713 15:36:22.516534 [CBTSetCACLKResult] CA Dly = 36
6714 15:36:22.516615 CS Dly: 1 (0~32)
6715 15:36:22.519924
6716 15:36:22.523467 ----->DramcWriteLeveling(PI) begin...
6717 15:36:22.523540 ==
6718 15:36:22.526343 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 15:36:22.529951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 15:36:22.530033 ==
6721 15:36:22.533575 Write leveling (Byte 0): 40 => 8
6722 15:36:22.536525 Write leveling (Byte 1): 32 => 0
6723 15:36:22.539894 DramcWriteLeveling(PI) end<-----
6724 15:36:22.539966
6725 15:36:22.540027 ==
6726 15:36:22.542907 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 15:36:22.546539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 15:36:22.546647 ==
6729 15:36:22.549784 [Gating] SW mode calibration
6730 15:36:22.556392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6731 15:36:22.562730 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6732 15:36:22.565966 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6733 15:36:22.569410 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6734 15:36:22.576192 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6735 15:36:22.579547 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6736 15:36:22.582724 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 15:36:22.589050 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 15:36:22.592532 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 15:36:22.595863 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 15:36:22.602580 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6741 15:36:22.602690 Total UI for P1: 0, mck2ui 16
6742 15:36:22.609043 best dqsien dly found for B0: ( 0, 14, 24)
6743 15:36:22.609150 Total UI for P1: 0, mck2ui 16
6744 15:36:22.616105 best dqsien dly found for B1: ( 0, 14, 24)
6745 15:36:22.619060 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6746 15:36:22.622092 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6747 15:36:22.622168
6748 15:36:22.625349 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6749 15:36:22.628787 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6750 15:36:22.632273 [Gating] SW calibration Done
6751 15:36:22.632347 ==
6752 15:36:22.635330 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 15:36:22.638572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 15:36:22.638681 ==
6755 15:36:22.641965 RX Vref Scan: 0
6756 15:36:22.642046
6757 15:36:22.642109 RX Vref 0 -> 0, step: 1
6758 15:36:22.642170
6759 15:36:22.645433 RX Delay -410 -> 252, step: 16
6760 15:36:22.652465 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6761 15:36:22.655315 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6762 15:36:22.658396 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6763 15:36:22.661917 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6764 15:36:22.668503 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6765 15:36:22.672142 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6766 15:36:22.675192 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6767 15:36:22.678799 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6768 15:36:22.685085 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6769 15:36:22.688407 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6770 15:36:22.691972 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6771 15:36:22.695110 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6772 15:36:22.701680 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6773 15:36:22.705129 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6774 15:36:22.707925 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6775 15:36:22.714553 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6776 15:36:22.714661 ==
6777 15:36:22.718502 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 15:36:22.721139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 15:36:22.721225 ==
6780 15:36:22.721288 DQS Delay:
6781 15:36:22.724956 DQS0 = 43, DQS1 = 51
6782 15:36:22.725031 DQM Delay:
6783 15:36:22.728378 DQM0 = 12, DQM1 = 14
6784 15:36:22.728448 DQ Delay:
6785 15:36:22.731405 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6786 15:36:22.734942 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6787 15:36:22.737590 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6788 15:36:22.741335 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6789 15:36:22.741431
6790 15:36:22.741519
6791 15:36:22.741611 ==
6792 15:36:22.744350 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 15:36:22.747786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 15:36:22.747856 ==
6795 15:36:22.747931
6796 15:36:22.747990
6797 15:36:22.751413 TX Vref Scan disable
6798 15:36:22.751481 == TX Byte 0 ==
6799 15:36:22.757930 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6800 15:36:22.761389 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6801 15:36:22.761487 == TX Byte 1 ==
6802 15:36:22.767616 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6803 15:36:22.771041 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6804 15:36:22.771139 ==
6805 15:36:22.774422 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 15:36:22.777781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 15:36:22.777851 ==
6808 15:36:22.780731
6809 15:36:22.780826
6810 15:36:22.780923 TX Vref Scan disable
6811 15:36:22.784061 == TX Byte 0 ==
6812 15:36:22.787846 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6813 15:36:22.790859 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6814 15:36:22.794057 == TX Byte 1 ==
6815 15:36:22.797478 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6816 15:36:22.800472 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6817 15:36:22.800543
6818 15:36:22.803932 [DATLAT]
6819 15:36:22.804001 Freq=400, CH1 RK0
6820 15:36:22.804061
6821 15:36:22.807295 DATLAT Default: 0xf
6822 15:36:22.807364 0, 0xFFFF, sum = 0
6823 15:36:22.810733 1, 0xFFFF, sum = 0
6824 15:36:22.810804 2, 0xFFFF, sum = 0
6825 15:36:22.814195 3, 0xFFFF, sum = 0
6826 15:36:22.814292 4, 0xFFFF, sum = 0
6827 15:36:22.817344 5, 0xFFFF, sum = 0
6828 15:36:22.817440 6, 0xFFFF, sum = 0
6829 15:36:22.820501 7, 0xFFFF, sum = 0
6830 15:36:22.820572 8, 0xFFFF, sum = 0
6831 15:36:22.823865 9, 0xFFFF, sum = 0
6832 15:36:22.823940 10, 0xFFFF, sum = 0
6833 15:36:22.827128 11, 0xFFFF, sum = 0
6834 15:36:22.827199 12, 0xFFFF, sum = 0
6835 15:36:22.830519 13, 0x0, sum = 1
6836 15:36:22.830660 14, 0x0, sum = 2
6837 15:36:22.833785 15, 0x0, sum = 3
6838 15:36:22.833858 16, 0x0, sum = 4
6839 15:36:22.837393 best_step = 14
6840 15:36:22.837461
6841 15:36:22.837519 ==
6842 15:36:22.840652 Dram Type= 6, Freq= 0, CH_1, rank 0
6843 15:36:22.843933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 15:36:22.844014 ==
6845 15:36:22.846682 RX Vref Scan: 1
6846 15:36:22.846762
6847 15:36:22.846831 RX Vref 0 -> 0, step: 1
6848 15:36:22.846891
6849 15:36:22.850503 RX Delay -343 -> 252, step: 8
6850 15:36:22.850584
6851 15:36:22.853547 Set Vref, RX VrefLevel [Byte0]: 48
6852 15:36:22.856954 [Byte1]: 53
6853 15:36:22.861678
6854 15:36:22.861785 Final RX Vref Byte 0 = 48 to rank0
6855 15:36:22.864882 Final RX Vref Byte 1 = 53 to rank0
6856 15:36:22.868356 Final RX Vref Byte 0 = 48 to rank1
6857 15:36:22.871601 Final RX Vref Byte 1 = 53 to rank1==
6858 15:36:22.874488 Dram Type= 6, Freq= 0, CH_1, rank 0
6859 15:36:22.881664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 15:36:22.881739 ==
6861 15:36:22.881818 DQS Delay:
6862 15:36:22.884996 DQS0 = 44, DQS1 = 52
6863 15:36:22.885092 DQM Delay:
6864 15:36:22.885180 DQM0 = 8, DQM1 = 9
6865 15:36:22.888231 DQ Delay:
6866 15:36:22.891379 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6867 15:36:22.891449 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6868 15:36:22.894396 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6869 15:36:22.897879 DQ12 =20, DQ13 =12, DQ14 =16, DQ15 =16
6870 15:36:22.897951
6871 15:36:22.898012
6872 15:36:22.908163 [DQSOSCAuto] RK0, (LSB)MR18= 0xa077, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 389 ps
6873 15:36:22.911185 CH1 RK0: MR19=C0C, MR18=A077
6874 15:36:22.918128 CH1_RK0: MR19=0xC0C, MR18=0xA077, DQSOSC=389, MR23=63, INC=390, DEC=260
6875 15:36:22.918235 ==
6876 15:36:22.921284 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 15:36:22.924280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 15:36:22.924388 ==
6879 15:36:22.927852 [Gating] SW mode calibration
6880 15:36:22.934108 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6881 15:36:22.940743 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6882 15:36:22.944229 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6883 15:36:22.947232 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6884 15:36:22.953739 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6885 15:36:22.957021 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6886 15:36:22.960542 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 15:36:22.967049 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 15:36:22.970297 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 15:36:22.973719 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 15:36:22.980196 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6891 15:36:22.980283 Total UI for P1: 0, mck2ui 16
6892 15:36:22.986559 best dqsien dly found for B0: ( 0, 14, 24)
6893 15:36:22.986699 Total UI for P1: 0, mck2ui 16
6894 15:36:22.993656 best dqsien dly found for B1: ( 0, 14, 24)
6895 15:36:22.996902 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6896 15:36:22.999998 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6897 15:36:23.000070
6898 15:36:23.003322 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6899 15:36:23.006968 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6900 15:36:23.010019 [Gating] SW calibration Done
6901 15:36:23.010093 ==
6902 15:36:23.013172 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 15:36:23.016366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 15:36:23.016463 ==
6905 15:36:23.020116 RX Vref Scan: 0
6906 15:36:23.020216
6907 15:36:23.020278 RX Vref 0 -> 0, step: 1
6908 15:36:23.022978
6909 15:36:23.023056 RX Delay -410 -> 252, step: 16
6910 15:36:23.029371 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6911 15:36:23.033050 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6912 15:36:23.036013 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6913 15:36:23.039812 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6914 15:36:23.046489 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6915 15:36:23.049754 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6916 15:36:23.053285 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6917 15:36:23.056598 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6918 15:36:23.062880 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6919 15:36:23.065867 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6920 15:36:23.069189 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6921 15:36:23.075797 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6922 15:36:23.079049 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6923 15:36:23.082938 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6924 15:36:23.085773 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6925 15:36:23.092289 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6926 15:36:23.092389 ==
6927 15:36:23.095501 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 15:36:23.099467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 15:36:23.099541 ==
6930 15:36:23.099603 DQS Delay:
6931 15:36:23.102587 DQS0 = 51, DQS1 = 51
6932 15:36:23.102701 DQM Delay:
6933 15:36:23.105724 DQM0 = 19, DQM1 = 14
6934 15:36:23.105821 DQ Delay:
6935 15:36:23.109161 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6936 15:36:23.112534 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6937 15:36:23.115445 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6938 15:36:23.119138 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6939 15:36:23.119219
6940 15:36:23.119283
6941 15:36:23.119343 ==
6942 15:36:23.122118 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 15:36:23.125381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 15:36:23.125462 ==
6945 15:36:23.125527
6946 15:36:23.128980
6947 15:36:23.129060 TX Vref Scan disable
6948 15:36:23.132377 == TX Byte 0 ==
6949 15:36:23.135821 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6950 15:36:23.138757 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6951 15:36:23.142108 == TX Byte 1 ==
6952 15:36:23.145018 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6953 15:36:23.148577 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6954 15:36:23.148658 ==
6955 15:36:23.152062 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 15:36:23.154850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 15:36:23.158903 ==
6958 15:36:23.158984
6959 15:36:23.159047
6960 15:36:23.159109 TX Vref Scan disable
6961 15:36:23.161723 == TX Byte 0 ==
6962 15:36:23.165173 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6963 15:36:23.168084 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6964 15:36:23.171343 == TX Byte 1 ==
6965 15:36:23.175110 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6966 15:36:23.178301 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6967 15:36:23.178381
6968 15:36:23.181744 [DATLAT]
6969 15:36:23.181817 Freq=400, CH1 RK1
6970 15:36:23.181880
6971 15:36:23.185028 DATLAT Default: 0xe
6972 15:36:23.185131 0, 0xFFFF, sum = 0
6973 15:36:23.188206 1, 0xFFFF, sum = 0
6974 15:36:23.188278 2, 0xFFFF, sum = 0
6975 15:36:23.191445 3, 0xFFFF, sum = 0
6976 15:36:23.191516 4, 0xFFFF, sum = 0
6977 15:36:23.194705 5, 0xFFFF, sum = 0
6978 15:36:23.194791 6, 0xFFFF, sum = 0
6979 15:36:23.197740 7, 0xFFFF, sum = 0
6980 15:36:23.197836 8, 0xFFFF, sum = 0
6981 15:36:23.200953 9, 0xFFFF, sum = 0
6982 15:36:23.201041 10, 0xFFFF, sum = 0
6983 15:36:23.204590 11, 0xFFFF, sum = 0
6984 15:36:23.207689 12, 0xFFFF, sum = 0
6985 15:36:23.207762 13, 0x0, sum = 1
6986 15:36:23.207823 14, 0x0, sum = 2
6987 15:36:23.210924 15, 0x0, sum = 3
6988 15:36:23.210995 16, 0x0, sum = 4
6989 15:36:23.214765 best_step = 14
6990 15:36:23.214835
6991 15:36:23.214903 ==
6992 15:36:23.218032 Dram Type= 6, Freq= 0, CH_1, rank 1
6993 15:36:23.221214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6994 15:36:23.221285 ==
6995 15:36:23.224180 RX Vref Scan: 0
6996 15:36:23.224250
6997 15:36:23.224308 RX Vref 0 -> 0, step: 1
6998 15:36:23.224364
6999 15:36:23.227801 RX Delay -343 -> 252, step: 8
7000 15:36:23.235968 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7001 15:36:23.239190 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7002 15:36:23.242446 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7003 15:36:23.245827 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7004 15:36:23.252651 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7005 15:36:23.255609 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7006 15:36:23.259087 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
7007 15:36:23.265608 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7008 15:36:23.268852 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7009 15:36:23.272465 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7010 15:36:23.275416 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7011 15:36:23.281912 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7012 15:36:23.285530 iDelay=225, Bit 12, Center -32 (-279 ~ 216) 496
7013 15:36:23.288647 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7014 15:36:23.292208 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7015 15:36:23.298400 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7016 15:36:23.298497 ==
7017 15:36:23.301710 Dram Type= 6, Freq= 0, CH_1, rank 1
7018 15:36:23.305052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7019 15:36:23.305147 ==
7020 15:36:23.305243 DQS Delay:
7021 15:36:23.309063 DQS0 = 48, DQS1 = 56
7022 15:36:23.309132 DQM Delay:
7023 15:36:23.311647 DQM0 = 13, DQM1 = 12
7024 15:36:23.311715 DQ Delay:
7025 15:36:23.314880 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7026 15:36:23.318514 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =12
7027 15:36:23.321642 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7028 15:36:23.325120 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
7029 15:36:23.325214
7030 15:36:23.325311
7031 15:36:23.334716 [DQSOSCAuto] RK1, (LSB)MR18= 0x7060, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
7032 15:36:23.334791 CH1 RK1: MR19=C0C, MR18=7060
7033 15:36:23.341442 CH1_RK1: MR19=0xC0C, MR18=0x7060, DQSOSC=395, MR23=63, INC=378, DEC=252
7034 15:36:23.344453 [RxdqsGatingPostProcess] freq 400
7035 15:36:23.351279 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7036 15:36:23.354582 best DQS0 dly(2T, 0.5T) = (0, 10)
7037 15:36:23.357868 best DQS1 dly(2T, 0.5T) = (0, 10)
7038 15:36:23.361536 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7039 15:36:23.364408 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7040 15:36:23.367898 best DQS0 dly(2T, 0.5T) = (0, 10)
7041 15:36:23.367969 best DQS1 dly(2T, 0.5T) = (0, 10)
7042 15:36:23.371110 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7043 15:36:23.374169 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7044 15:36:23.378105 Pre-setting of DQS Precalculation
7045 15:36:23.384280 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7046 15:36:23.391146 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7047 15:36:23.397562 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7048 15:36:23.397669
7049 15:36:23.397761
7050 15:36:23.400809 [Calibration Summary] 800 Mbps
7051 15:36:23.404395 CH 0, Rank 0
7052 15:36:23.404509 SW Impedance : PASS
7053 15:36:23.408083 DUTY Scan : NO K
7054 15:36:23.408167 ZQ Calibration : PASS
7055 15:36:23.410925 Jitter Meter : NO K
7056 15:36:23.414335 CBT Training : PASS
7057 15:36:23.414416 Write leveling : PASS
7058 15:36:23.417489 RX DQS gating : PASS
7059 15:36:23.420735 RX DQ/DQS(RDDQC) : PASS
7060 15:36:23.420817 TX DQ/DQS : PASS
7061 15:36:23.424168 RX DATLAT : PASS
7062 15:36:23.427160 RX DQ/DQS(Engine): PASS
7063 15:36:23.427240 TX OE : NO K
7064 15:36:23.430831 All Pass.
7065 15:36:23.430916
7066 15:36:23.430981 CH 0, Rank 1
7067 15:36:23.434197 SW Impedance : PASS
7068 15:36:23.434277 DUTY Scan : NO K
7069 15:36:23.436933 ZQ Calibration : PASS
7070 15:36:23.440250 Jitter Meter : NO K
7071 15:36:23.440330 CBT Training : PASS
7072 15:36:23.443598 Write leveling : NO K
7073 15:36:23.447244 RX DQS gating : PASS
7074 15:36:23.447324 RX DQ/DQS(RDDQC) : PASS
7075 15:36:23.450607 TX DQ/DQS : PASS
7076 15:36:23.454009 RX DATLAT : PASS
7077 15:36:23.454090 RX DQ/DQS(Engine): PASS
7078 15:36:23.456925 TX OE : NO K
7079 15:36:23.457006 All Pass.
7080 15:36:23.457071
7081 15:36:23.460353 CH 1, Rank 0
7082 15:36:23.460434 SW Impedance : PASS
7083 15:36:23.463669 DUTY Scan : NO K
7084 15:36:23.466893 ZQ Calibration : PASS
7085 15:36:23.466974 Jitter Meter : NO K
7086 15:36:23.470621 CBT Training : PASS
7087 15:36:23.473676 Write leveling : PASS
7088 15:36:23.473757 RX DQS gating : PASS
7089 15:36:23.477184 RX DQ/DQS(RDDQC) : PASS
7090 15:36:23.477291 TX DQ/DQS : PASS
7091 15:36:23.480028 RX DATLAT : PASS
7092 15:36:23.483360 RX DQ/DQS(Engine): PASS
7093 15:36:23.483441 TX OE : NO K
7094 15:36:23.486745 All Pass.
7095 15:36:23.486826
7096 15:36:23.486890 CH 1, Rank 1
7097 15:36:23.490010 SW Impedance : PASS
7098 15:36:23.490121 DUTY Scan : NO K
7099 15:36:23.493535 ZQ Calibration : PASS
7100 15:36:23.496476 Jitter Meter : NO K
7101 15:36:23.496557 CBT Training : PASS
7102 15:36:23.499688 Write leveling : NO K
7103 15:36:23.503167 RX DQS gating : PASS
7104 15:36:23.503247 RX DQ/DQS(RDDQC) : PASS
7105 15:36:23.506245 TX DQ/DQS : PASS
7106 15:36:23.509769 RX DATLAT : PASS
7107 15:36:23.509850 RX DQ/DQS(Engine): PASS
7108 15:36:23.513380 TX OE : NO K
7109 15:36:23.513492 All Pass.
7110 15:36:23.513584
7111 15:36:23.516152 DramC Write-DBI off
7112 15:36:23.519546 PER_BANK_REFRESH: Hybrid Mode
7113 15:36:23.519626 TX_TRACKING: ON
7114 15:36:23.529394 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7115 15:36:23.533127 [FAST_K] Save calibration result to emmc
7116 15:36:23.536036 dramc_set_vcore_voltage set vcore to 725000
7117 15:36:23.539407 Read voltage for 1600, 0
7118 15:36:23.539487 Vio18 = 0
7119 15:36:23.542578 Vcore = 725000
7120 15:36:23.542694 Vdram = 0
7121 15:36:23.542759 Vddq = 0
7122 15:36:23.542818 Vmddr = 0
7123 15:36:23.548795 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7124 15:36:23.555339 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7125 15:36:23.555421 MEM_TYPE=3, freq_sel=13
7126 15:36:23.558958 sv_algorithm_assistance_LP4_3733
7127 15:36:23.562374 ============ PULL DRAM RESETB DOWN ============
7128 15:36:23.568670 ========== PULL DRAM RESETB DOWN end =========
7129 15:36:23.572241 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7130 15:36:23.575450 ===================================
7131 15:36:23.578953 LPDDR4 DRAM CONFIGURATION
7132 15:36:23.581818 ===================================
7133 15:36:23.581900 EX_ROW_EN[0] = 0x0
7134 15:36:23.585271 EX_ROW_EN[1] = 0x0
7135 15:36:23.588462 LP4Y_EN = 0x0
7136 15:36:23.588543 WORK_FSP = 0x1
7137 15:36:23.592000 WL = 0x5
7138 15:36:23.592087 RL = 0x5
7139 15:36:23.594791 BL = 0x2
7140 15:36:23.594872 RPST = 0x0
7141 15:36:23.598228 RD_PRE = 0x0
7142 15:36:23.598324 WR_PRE = 0x1
7143 15:36:23.601563 WR_PST = 0x1
7144 15:36:23.601644 DBI_WR = 0x0
7145 15:36:23.605057 DBI_RD = 0x0
7146 15:36:23.605138 OTF = 0x1
7147 15:36:23.608694 ===================================
7148 15:36:23.611777 ===================================
7149 15:36:23.614816 ANA top config
7150 15:36:23.617954 ===================================
7151 15:36:23.621250 DLL_ASYNC_EN = 0
7152 15:36:23.621330 ALL_SLAVE_EN = 0
7153 15:36:23.624867 NEW_RANK_MODE = 1
7154 15:36:23.627532 DLL_IDLE_MODE = 1
7155 15:36:23.630903 LP45_APHY_COMB_EN = 1
7156 15:36:23.630984 TX_ODT_DIS = 0
7157 15:36:23.634265 NEW_8X_MODE = 1
7158 15:36:23.637962 ===================================
7159 15:36:23.640698 ===================================
7160 15:36:23.644591 data_rate = 3200
7161 15:36:23.647640 CKR = 1
7162 15:36:23.651013 DQ_P2S_RATIO = 8
7163 15:36:23.653959 ===================================
7164 15:36:23.657741 CA_P2S_RATIO = 8
7165 15:36:23.657822 DQ_CA_OPEN = 0
7166 15:36:23.660649 DQ_SEMI_OPEN = 0
7167 15:36:23.664178 CA_SEMI_OPEN = 0
7168 15:36:23.667604 CA_FULL_RATE = 0
7169 15:36:23.670392 DQ_CKDIV4_EN = 0
7170 15:36:23.673795 CA_CKDIV4_EN = 0
7171 15:36:23.677164 CA_PREDIV_EN = 0
7172 15:36:23.677261 PH8_DLY = 12
7173 15:36:23.680535 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7174 15:36:23.683612 DQ_AAMCK_DIV = 4
7175 15:36:23.687167 CA_AAMCK_DIV = 4
7176 15:36:23.690453 CA_ADMCK_DIV = 4
7177 15:36:23.693679 DQ_TRACK_CA_EN = 0
7178 15:36:23.693750 CA_PICK = 1600
7179 15:36:23.697494 CA_MCKIO = 1600
7180 15:36:23.700356 MCKIO_SEMI = 0
7181 15:36:23.703855 PLL_FREQ = 3068
7182 15:36:23.707142 DQ_UI_PI_RATIO = 32
7183 15:36:23.709909 CA_UI_PI_RATIO = 0
7184 15:36:23.713344 ===================================
7185 15:36:23.716575 ===================================
7186 15:36:23.720031 memory_type:LPDDR4
7187 15:36:23.720121 GP_NUM : 10
7188 15:36:23.723422 SRAM_EN : 1
7189 15:36:23.723505 MD32_EN : 0
7190 15:36:23.726509 ===================================
7191 15:36:23.730041 [ANA_INIT] >>>>>>>>>>>>>>
7192 15:36:23.733105 <<<<<< [CONFIGURE PHASE]: ANA_TX
7193 15:36:23.736589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7194 15:36:23.739644 ===================================
7195 15:36:23.743499 data_rate = 3200,PCW = 0X7600
7196 15:36:23.746017 ===================================
7197 15:36:23.749404 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7198 15:36:23.756005 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7199 15:36:23.759547 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7200 15:36:23.766302 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7201 15:36:23.769415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7202 15:36:23.772818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7203 15:36:23.772900 [ANA_INIT] flow start
7204 15:36:23.776033 [ANA_INIT] PLL >>>>>>>>
7205 15:36:23.779497 [ANA_INIT] PLL <<<<<<<<
7206 15:36:23.779579 [ANA_INIT] MIDPI >>>>>>>>
7207 15:36:23.782905 [ANA_INIT] MIDPI <<<<<<<<
7208 15:36:23.786292 [ANA_INIT] DLL >>>>>>>>
7209 15:36:23.789834 [ANA_INIT] DLL <<<<<<<<
7210 15:36:23.789915 [ANA_INIT] flow end
7211 15:36:23.792989 ============ LP4 DIFF to SE enter ============
7212 15:36:23.799440 ============ LP4 DIFF to SE exit ============
7213 15:36:23.799520 [ANA_INIT] <<<<<<<<<<<<<
7214 15:36:23.802421 [Flow] Enable top DCM control >>>>>
7215 15:36:23.805617 [Flow] Enable top DCM control <<<<<
7216 15:36:23.809060 Enable DLL master slave shuffle
7217 15:36:23.815820 ==============================================================
7218 15:36:23.815897 Gating Mode config
7219 15:36:23.822780 ==============================================================
7220 15:36:23.825602 Config description:
7221 15:36:23.835286 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7222 15:36:23.842324 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7223 15:36:23.845008 SELPH_MODE 0: By rank 1: By Phase
7224 15:36:23.852025 ==============================================================
7225 15:36:23.855041 GAT_TRACK_EN = 1
7226 15:36:23.858725 RX_GATING_MODE = 2
7227 15:36:23.861687 RX_GATING_TRACK_MODE = 2
7228 15:36:23.861764 SELPH_MODE = 1
7229 15:36:23.864978 PICG_EARLY_EN = 1
7230 15:36:23.868435 VALID_LAT_VALUE = 1
7231 15:36:23.874652 ==============================================================
7232 15:36:23.878049 Enter into Gating configuration >>>>
7233 15:36:23.881365 Exit from Gating configuration <<<<
7234 15:36:23.884718 Enter into DVFS_PRE_config >>>>>
7235 15:36:23.894396 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7236 15:36:23.897910 Exit from DVFS_PRE_config <<<<<
7237 15:36:23.900887 Enter into PICG configuration >>>>
7238 15:36:23.904535 Exit from PICG configuration <<<<
7239 15:36:23.907644 [RX_INPUT] configuration >>>>>
7240 15:36:23.910975 [RX_INPUT] configuration <<<<<
7241 15:36:23.914508 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7242 15:36:23.920899 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7243 15:36:23.927528 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7244 15:36:23.934346 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7245 15:36:23.940896 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7246 15:36:23.944308 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7247 15:36:23.950784 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7248 15:36:23.954074 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7249 15:36:23.957428 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7250 15:36:23.963624 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7251 15:36:23.967408 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7252 15:36:23.970380 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7253 15:36:23.973598 ===================================
7254 15:36:23.976927 LPDDR4 DRAM CONFIGURATION
7255 15:36:23.980325 ===================================
7256 15:36:23.980397 EX_ROW_EN[0] = 0x0
7257 15:36:23.983801 EX_ROW_EN[1] = 0x0
7258 15:36:23.986853 LP4Y_EN = 0x0
7259 15:36:23.986949 WORK_FSP = 0x1
7260 15:36:23.990171 WL = 0x5
7261 15:36:23.990240 RL = 0x5
7262 15:36:23.993540 BL = 0x2
7263 15:36:23.993641 RPST = 0x0
7264 15:36:23.997022 RD_PRE = 0x0
7265 15:36:23.997102 WR_PRE = 0x1
7266 15:36:24.000057 WR_PST = 0x1
7267 15:36:24.000135 DBI_WR = 0x0
7268 15:36:24.003430 DBI_RD = 0x0
7269 15:36:24.003510 OTF = 0x1
7270 15:36:24.006783 ===================================
7271 15:36:24.010079 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7272 15:36:24.016700 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7273 15:36:24.019916 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7274 15:36:24.023383 ===================================
7275 15:36:24.026750 LPDDR4 DRAM CONFIGURATION
7276 15:36:24.030145 ===================================
7277 15:36:24.030243 EX_ROW_EN[0] = 0x10
7278 15:36:24.033230 EX_ROW_EN[1] = 0x0
7279 15:36:24.036573 LP4Y_EN = 0x0
7280 15:36:24.036646 WORK_FSP = 0x1
7281 15:36:24.039585 WL = 0x5
7282 15:36:24.039655 RL = 0x5
7283 15:36:24.043018 BL = 0x2
7284 15:36:24.043086 RPST = 0x0
7285 15:36:24.046055 RD_PRE = 0x0
7286 15:36:24.046123 WR_PRE = 0x1
7287 15:36:24.049777 WR_PST = 0x1
7288 15:36:24.049847 DBI_WR = 0x0
7289 15:36:24.052954 DBI_RD = 0x0
7290 15:36:24.053021 OTF = 0x1
7291 15:36:24.056272 ===================================
7292 15:36:24.062832 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7293 15:36:24.062910 ==
7294 15:36:24.066259 Dram Type= 6, Freq= 0, CH_0, rank 0
7295 15:36:24.069918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7296 15:36:24.072931 ==
7297 15:36:24.073005 [Duty_Offset_Calibration]
7298 15:36:24.076148 B0:1 B1:-1 CA:0
7299 15:36:24.076222
7300 15:36:24.079051 [DutyScan_Calibration_Flow] k_type=0
7301 15:36:24.088512
7302 15:36:24.088586 ==CLK 0==
7303 15:36:24.091633 Final CLK duty delay cell = 0
7304 15:36:24.094931 [0] MAX Duty = 5125%(X100), DQS PI = 20
7305 15:36:24.098252 [0] MIN Duty = 4907%(X100), DQS PI = 8
7306 15:36:24.098350 [0] AVG Duty = 5016%(X100)
7307 15:36:24.101549
7308 15:36:24.105177 CH0 CLK Duty spec in!! Max-Min= 218%
7309 15:36:24.108022 [DutyScan_Calibration_Flow] ====Done====
7310 15:36:24.108097
7311 15:36:24.111336 [DutyScan_Calibration_Flow] k_type=1
7312 15:36:24.127537
7313 15:36:24.127618 ==DQS 0 ==
7314 15:36:24.130701 Final DQS duty delay cell = -4
7315 15:36:24.134113 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7316 15:36:24.137425 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7317 15:36:24.140829 [-4] AVG Duty = 4922%(X100)
7318 15:36:24.140899
7319 15:36:24.140961 ==DQS 1 ==
7320 15:36:24.144118 Final DQS duty delay cell = 0
7321 15:36:24.146972 [0] MAX Duty = 5156%(X100), DQS PI = 2
7322 15:36:24.150365 [0] MIN Duty = 5031%(X100), DQS PI = 18
7323 15:36:24.153584 [0] AVG Duty = 5093%(X100)
7324 15:36:24.153653
7325 15:36:24.157052 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7326 15:36:24.157161
7327 15:36:24.160446 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7328 15:36:24.163891 [DutyScan_Calibration_Flow] ====Done====
7329 15:36:24.163963
7330 15:36:24.166951 [DutyScan_Calibration_Flow] k_type=3
7331 15:36:24.184659
7332 15:36:24.184735 ==DQM 0 ==
7333 15:36:24.187938 Final DQM duty delay cell = 0
7334 15:36:24.191339 [0] MAX Duty = 5124%(X100), DQS PI = 20
7335 15:36:24.194642 [0] MIN Duty = 4907%(X100), DQS PI = 8
7336 15:36:24.198053 [0] AVG Duty = 5015%(X100)
7337 15:36:24.198125
7338 15:36:24.198189 ==DQM 1 ==
7339 15:36:24.201402 Final DQM duty delay cell = 0
7340 15:36:24.205022 [0] MAX Duty = 5031%(X100), DQS PI = 52
7341 15:36:24.208222 [0] MIN Duty = 4813%(X100), DQS PI = 20
7342 15:36:24.211104 [0] AVG Duty = 4922%(X100)
7343 15:36:24.211175
7344 15:36:24.214706 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7345 15:36:24.214783
7346 15:36:24.217738 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7347 15:36:24.221012 [DutyScan_Calibration_Flow] ====Done====
7348 15:36:24.221087
7349 15:36:24.224270 [DutyScan_Calibration_Flow] k_type=2
7350 15:36:24.240386
7351 15:36:24.240459 ==DQ 0 ==
7352 15:36:24.244129 Final DQ duty delay cell = -4
7353 15:36:24.247092 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7354 15:36:24.250157 [-4] MIN Duty = 4907%(X100), DQS PI = 48
7355 15:36:24.254056 [-4] AVG Duty = 4969%(X100)
7356 15:36:24.254124
7357 15:36:24.254183 ==DQ 1 ==
7358 15:36:24.257194 Final DQ duty delay cell = -4
7359 15:36:24.260416 [-4] MAX Duty = 4969%(X100), DQS PI = 50
7360 15:36:24.263798 [-4] MIN Duty = 4875%(X100), DQS PI = 10
7361 15:36:24.267104 [-4] AVG Duty = 4922%(X100)
7362 15:36:24.267180
7363 15:36:24.269773 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7364 15:36:24.269843
7365 15:36:24.273645 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7366 15:36:24.276436 [DutyScan_Calibration_Flow] ====Done====
7367 15:36:24.276507 ==
7368 15:36:24.280097 Dram Type= 6, Freq= 0, CH_1, rank 0
7369 15:36:24.283528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7370 15:36:24.283598 ==
7371 15:36:24.286376 [Duty_Offset_Calibration]
7372 15:36:24.290539 B0:-1 B1:1 CA:2
7373 15:36:24.290650
7374 15:36:24.292877 [DutyScan_Calibration_Flow] k_type=0
7375 15:36:24.301387
7376 15:36:24.301468 ==CLK 0==
7377 15:36:24.304394 Final CLK duty delay cell = 0
7378 15:36:24.307684 [0] MAX Duty = 5187%(X100), DQS PI = 22
7379 15:36:24.311323 [0] MIN Duty = 5000%(X100), DQS PI = 0
7380 15:36:24.314980 [0] AVG Duty = 5093%(X100)
7381 15:36:24.315054
7382 15:36:24.318214 CH1 CLK Duty spec in!! Max-Min= 187%
7383 15:36:24.321007 [DutyScan_Calibration_Flow] ====Done====
7384 15:36:24.321083
7385 15:36:24.324281 [DutyScan_Calibration_Flow] k_type=1
7386 15:36:24.341116
7387 15:36:24.341199 ==DQS 0 ==
7388 15:36:24.344062 Final DQS duty delay cell = 0
7389 15:36:24.347284 [0] MAX Duty = 5156%(X100), DQS PI = 18
7390 15:36:24.350771 [0] MIN Duty = 4907%(X100), DQS PI = 10
7391 15:36:24.354249 [0] AVG Duty = 5031%(X100)
7392 15:36:24.354353
7393 15:36:24.354454 ==DQS 1 ==
7394 15:36:24.357301 Final DQS duty delay cell = 0
7395 15:36:24.360836 [0] MAX Duty = 5093%(X100), DQS PI = 24
7396 15:36:24.364251 [0] MIN Duty = 4969%(X100), DQS PI = 54
7397 15:36:24.367107 [0] AVG Duty = 5031%(X100)
7398 15:36:24.367187
7399 15:36:24.370414 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7400 15:36:24.370496
7401 15:36:24.373672 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7402 15:36:24.377287 [DutyScan_Calibration_Flow] ====Done====
7403 15:36:24.377368
7404 15:36:24.380247 [DutyScan_Calibration_Flow] k_type=3
7405 15:36:24.396948
7406 15:36:24.397031 ==DQM 0 ==
7407 15:36:24.400479 Final DQM duty delay cell = -4
7408 15:36:24.403663 [-4] MAX Duty = 5094%(X100), DQS PI = 36
7409 15:36:24.406618 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7410 15:36:24.410116 [-4] AVG Duty = 4953%(X100)
7411 15:36:24.410196
7412 15:36:24.410260 ==DQM 1 ==
7413 15:36:24.413623 Final DQM duty delay cell = 0
7414 15:36:24.416605 [0] MAX Duty = 5156%(X100), DQS PI = 0
7415 15:36:24.419884 [0] MIN Duty = 4969%(X100), DQS PI = 32
7416 15:36:24.423284 [0] AVG Duty = 5062%(X100)
7417 15:36:24.423387
7418 15:36:24.426446 CH1 DQM 0 Duty spec in!! Max-Min= 281%
7419 15:36:24.426545
7420 15:36:24.429962 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7421 15:36:24.433838 [DutyScan_Calibration_Flow] ====Done====
7422 15:36:24.433908
7423 15:36:24.436792 [DutyScan_Calibration_Flow] k_type=2
7424 15:36:24.454100
7425 15:36:24.454176 ==DQ 0 ==
7426 15:36:24.457436 Final DQ duty delay cell = 0
7427 15:36:24.460974 [0] MAX Duty = 5156%(X100), DQS PI = 28
7428 15:36:24.464290 [0] MIN Duty = 4906%(X100), DQS PI = 10
7429 15:36:24.464378 [0] AVG Duty = 5031%(X100)
7430 15:36:24.467511
7431 15:36:24.467591 ==DQ 1 ==
7432 15:36:24.470761 Final DQ duty delay cell = 0
7433 15:36:24.474216 [0] MAX Duty = 5156%(X100), DQS PI = 10
7434 15:36:24.477410 [0] MIN Duty = 4969%(X100), DQS PI = 56
7435 15:36:24.480685 [0] AVG Duty = 5062%(X100)
7436 15:36:24.480766
7437 15:36:24.483734 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7438 15:36:24.483816
7439 15:36:24.487071 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7440 15:36:24.490316 [DutyScan_Calibration_Flow] ====Done====
7441 15:36:24.493853 nWR fixed to 30
7442 15:36:24.496740 [ModeRegInit_LP4] CH0 RK0
7443 15:36:24.496817 [ModeRegInit_LP4] CH0 RK1
7444 15:36:24.500142 [ModeRegInit_LP4] CH1 RK0
7445 15:36:24.503459 [ModeRegInit_LP4] CH1 RK1
7446 15:36:24.503531 match AC timing 5
7447 15:36:24.510270 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7448 15:36:24.513715 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7449 15:36:24.516628 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7450 15:36:24.523222 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7451 15:36:24.526750 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7452 15:36:24.526825 [MiockJmeterHQA]
7453 15:36:24.526890
7454 15:36:24.529937 [DramcMiockJmeter] u1RxGatingPI = 0
7455 15:36:24.533376 0 : 4363, 4137
7456 15:36:24.533450 4 : 4253, 4026
7457 15:36:24.536545 8 : 4363, 4137
7458 15:36:24.536620 12 : 4252, 4027
7459 15:36:24.539984 16 : 4253, 4027
7460 15:36:24.540055 20 : 4363, 4137
7461 15:36:24.540115 24 : 4252, 4027
7462 15:36:24.542981 28 : 4252, 4027
7463 15:36:24.543051 32 : 4253, 4027
7464 15:36:24.546491 36 : 4255, 4029
7465 15:36:24.546586 40 : 4252, 4027
7466 15:36:24.549927 44 : 4252, 4027
7467 15:36:24.549997 48 : 4365, 4140
7468 15:36:24.553475 52 : 4252, 4027
7469 15:36:24.553546 56 : 4255, 4029
7470 15:36:24.553605 60 : 4250, 4026
7471 15:36:24.556617 64 : 4361, 4137
7472 15:36:24.556688 68 : 4250, 4027
7473 15:36:24.559465 72 : 4361, 4137
7474 15:36:24.559533 76 : 4250, 4027
7475 15:36:24.563109 80 : 4250, 4026
7476 15:36:24.563187 84 : 4250, 4027
7477 15:36:24.566388 88 : 4253, 4030
7478 15:36:24.566475 92 : 4361, 586
7479 15:36:24.566540 96 : 4252, 0
7480 15:36:24.569594 100 : 4363, 0
7481 15:36:24.569679 104 : 4361, 0
7482 15:36:24.572954 108 : 4250, 0
7483 15:36:24.573071 112 : 4252, 0
7484 15:36:24.573157 116 : 4361, 0
7485 15:36:24.576024 120 : 4361, 0
7486 15:36:24.576108 124 : 4252, 0
7487 15:36:24.576194 128 : 4253, 0
7488 15:36:24.579500 132 : 4250, 0
7489 15:36:24.579584 136 : 4252, 0
7490 15:36:24.582978 140 : 4252, 0
7491 15:36:24.583062 144 : 4250, 0
7492 15:36:24.583148 148 : 4252, 0
7493 15:36:24.586259 152 : 4363, 0
7494 15:36:24.586343 156 : 4361, 0
7495 15:36:24.589216 160 : 4363, 0
7496 15:36:24.589303 164 : 4252, 0
7497 15:36:24.589389 168 : 4361, 0
7498 15:36:24.592643 172 : 4360, 0
7499 15:36:24.592726 176 : 4252, 0
7500 15:36:24.596081 180 : 4252, 0
7501 15:36:24.596165 184 : 4250, 0
7502 15:36:24.596251 188 : 4253, 0
7503 15:36:24.598982 192 : 4252, 0
7504 15:36:24.599066 196 : 4250, 0
7505 15:36:24.602801 200 : 4252, 0
7506 15:36:24.602885 204 : 4360, 0
7507 15:36:24.602970 208 : 4361, 0
7508 15:36:24.605703 212 : 4363, 0
7509 15:36:24.605787 216 : 4250, 0
7510 15:36:24.609433 220 : 4361, 0
7511 15:36:24.609514 224 : 4361, 302
7512 15:36:24.609579 228 : 4250, 3371
7513 15:36:24.612092 232 : 4250, 4027
7514 15:36:24.612173 236 : 4250, 4027
7515 15:36:24.615467 240 : 4250, 4027
7516 15:36:24.615549 244 : 4250, 4026
7517 15:36:24.619225 248 : 4360, 4137
7518 15:36:24.619306 252 : 4250, 4026
7519 15:36:24.622201 256 : 4250, 4027
7520 15:36:24.622283 260 : 4360, 4138
7521 15:36:24.625295 264 : 4361, 4137
7522 15:36:24.625377 268 : 4250, 4026
7523 15:36:24.629152 272 : 4363, 4139
7524 15:36:24.629233 276 : 4250, 4027
7525 15:36:24.632025 280 : 4250, 4027
7526 15:36:24.632107 284 : 4250, 4027
7527 15:36:24.632172 288 : 4252, 4029
7528 15:36:24.635306 292 : 4250, 4027
7529 15:36:24.635387 296 : 4252, 4029
7530 15:36:24.638538 300 : 4250, 4027
7531 15:36:24.638627 304 : 4252, 4029
7532 15:36:24.641999 308 : 4250, 4027
7533 15:36:24.642080 312 : 4360, 4138
7534 15:36:24.645239 316 : 4363, 4137
7535 15:36:24.645320 320 : 4250, 4026
7536 15:36:24.648579 324 : 4363, 4140
7537 15:36:24.648660 328 : 4250, 4027
7538 15:36:24.652223 332 : 4250, 4027
7539 15:36:24.652321 336 : 4250, 3760
7540 15:36:24.655387 340 : 4252, 2033
7541 15:36:24.655468
7542 15:36:24.655531 MIOCK jitter meter ch=0
7543 15:36:24.655590
7544 15:36:24.658208 1T = (340-92) = 248 dly cells
7545 15:36:24.665007 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7546 15:36:24.665089 ==
7547 15:36:24.668283 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 15:36:24.672003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 15:36:24.672084 ==
7550 15:36:24.678595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7551 15:36:24.681798 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7552 15:36:24.687995 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7553 15:36:24.691271 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7554 15:36:24.701542 [CA 0] Center 43 (12~74) winsize 63
7555 15:36:24.705184 [CA 1] Center 43 (13~73) winsize 61
7556 15:36:24.707864 [CA 2] Center 38 (9~68) winsize 60
7557 15:36:24.711340 [CA 3] Center 38 (9~68) winsize 60
7558 15:36:24.715034 [CA 4] Center 37 (8~66) winsize 59
7559 15:36:24.717965 [CA 5] Center 36 (6~66) winsize 61
7560 15:36:24.718046
7561 15:36:24.721665 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7562 15:36:24.721745
7563 15:36:24.724541 [CATrainingPosCal] consider 1 rank data
7564 15:36:24.727806 u2DelayCellTimex100 = 262/100 ps
7565 15:36:24.734531 CA0 delay=43 (12~74),Diff = 7 PI (26 cell)
7566 15:36:24.737831 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7567 15:36:24.740760 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7568 15:36:24.744072 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7569 15:36:24.747438 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7570 15:36:24.751050 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7571 15:36:24.751131
7572 15:36:24.754033 CA PerBit enable=1, Macro0, CA PI delay=36
7573 15:36:24.754113
7574 15:36:24.757212 [CBTSetCACLKResult] CA Dly = 36
7575 15:36:24.760644 CS Dly: 11 (0~42)
7576 15:36:24.764217 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7577 15:36:24.767862 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7578 15:36:24.767943 ==
7579 15:36:24.770727 Dram Type= 6, Freq= 0, CH_0, rank 1
7580 15:36:24.777262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 15:36:24.777343 ==
7582 15:36:24.780670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7583 15:36:24.787136 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7584 15:36:24.790173 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7585 15:36:24.797174 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7586 15:36:24.804704 [CA 0] Center 43 (13~74) winsize 62
7587 15:36:24.808188 [CA 1] Center 44 (14~74) winsize 61
7588 15:36:24.811731 [CA 2] Center 38 (9~68) winsize 60
7589 15:36:24.814625 [CA 3] Center 38 (9~68) winsize 60
7590 15:36:24.818420 [CA 4] Center 36 (7~66) winsize 60
7591 15:36:24.821460 [CA 5] Center 36 (6~66) winsize 61
7592 15:36:24.821540
7593 15:36:24.824410 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7594 15:36:24.824490
7595 15:36:24.831180 [CATrainingPosCal] consider 2 rank data
7596 15:36:24.831261 u2DelayCellTimex100 = 262/100 ps
7597 15:36:24.837659 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7598 15:36:24.841093 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7599 15:36:24.844569 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7600 15:36:24.848177 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7601 15:36:24.850976 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7602 15:36:24.854411 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7603 15:36:24.854491
7604 15:36:24.857709 CA PerBit enable=1, Macro0, CA PI delay=36
7605 15:36:24.857789
7606 15:36:24.860922 [CBTSetCACLKResult] CA Dly = 36
7607 15:36:24.864335 CS Dly: 12 (0~44)
7608 15:36:24.867271 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7609 15:36:24.870733 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7610 15:36:24.870848
7611 15:36:24.874091 ----->DramcWriteLeveling(PI) begin...
7612 15:36:24.874168 ==
7613 15:36:24.877286 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 15:36:24.883841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 15:36:24.883918 ==
7616 15:36:24.887342 Write leveling (Byte 0): 36 => 36
7617 15:36:24.890330 Write leveling (Byte 1): 28 => 28
7618 15:36:24.890408 DramcWriteLeveling(PI) end<-----
7619 15:36:24.893746
7620 15:36:24.893822 ==
7621 15:36:24.897178 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 15:36:24.900521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 15:36:24.900593 ==
7624 15:36:24.903797 [Gating] SW mode calibration
7625 15:36:24.909877 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7626 15:36:24.913180 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7627 15:36:24.919904 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 15:36:24.923224 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 15:36:24.930186 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 15:36:24.933048 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7631 15:36:24.936833 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7632 15:36:24.939680 1 4 20 | B1->B0 | 2827 3434 | 1 1 | (0 0) (1 1)
7633 15:36:24.946401 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7634 15:36:24.949512 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7635 15:36:24.952985 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 15:36:24.959674 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 15:36:24.963161 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7638 15:36:24.966182 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7639 15:36:24.972933 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7640 15:36:24.976667 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7641 15:36:24.979321 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7642 15:36:24.986107 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 15:36:24.989756 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 15:36:24.992500 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 15:36:24.999414 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7646 15:36:25.002478 1 6 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
7647 15:36:25.005906 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7648 15:36:25.012716 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7649 15:36:25.016149 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 15:36:25.019014 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 15:36:25.025749 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 15:36:25.029295 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 15:36:25.032046 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 15:36:25.038725 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7655 15:36:25.042028 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7656 15:36:25.045634 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7657 15:36:25.052114 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 15:36:25.055722 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 15:36:25.058923 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 15:36:25.065125 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 15:36:25.068496 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 15:36:25.071878 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 15:36:25.078549 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 15:36:25.081874 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 15:36:25.084950 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 15:36:25.091786 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 15:36:25.094871 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 15:36:25.098188 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 15:36:25.104694 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7670 15:36:25.108424 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7671 15:36:25.111062 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7672 15:36:25.117856 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7673 15:36:25.121132 Total UI for P1: 0, mck2ui 16
7674 15:36:25.124805 best dqsien dly found for B0: ( 1, 9, 12)
7675 15:36:25.127598 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 15:36:25.130988 Total UI for P1: 0, mck2ui 16
7677 15:36:25.134412 best dqsien dly found for B1: ( 1, 9, 20)
7678 15:36:25.137819 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7679 15:36:25.141127 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7680 15:36:25.141208
7681 15:36:25.144143 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7682 15:36:25.150708 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7683 15:36:25.150788 [Gating] SW calibration Done
7684 15:36:25.150852 ==
7685 15:36:25.154564 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 15:36:25.160779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 15:36:25.160864 ==
7688 15:36:25.160949 RX Vref Scan: 0
7689 15:36:25.161011
7690 15:36:25.163933 RX Vref 0 -> 0, step: 1
7691 15:36:25.164013
7692 15:36:25.167469 RX Delay 0 -> 252, step: 8
7693 15:36:25.170833 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7694 15:36:25.174183 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7695 15:36:25.176997 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7696 15:36:25.183964 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7697 15:36:25.187364 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7698 15:36:25.190884 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7699 15:36:25.193730 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7700 15:36:25.197289 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7701 15:36:25.203736 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7702 15:36:25.206935 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7703 15:36:25.210492 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7704 15:36:25.213707 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7705 15:36:25.216795 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7706 15:36:25.223470 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7707 15:36:25.226960 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7708 15:36:25.230167 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7709 15:36:25.230273 ==
7710 15:36:25.233494 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 15:36:25.237028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 15:36:25.239802 ==
7713 15:36:25.239882 DQS Delay:
7714 15:36:25.239945 DQS0 = 0, DQS1 = 0
7715 15:36:25.243359 DQM Delay:
7716 15:36:25.243439 DQM0 = 136, DQM1 = 126
7717 15:36:25.246377 DQ Delay:
7718 15:36:25.249910 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7719 15:36:25.253320 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =147
7720 15:36:25.256686 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7721 15:36:25.259787 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7722 15:36:25.259867
7723 15:36:25.259931
7724 15:36:25.259989 ==
7725 15:36:25.262700 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 15:36:25.266145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 15:36:25.266225 ==
7728 15:36:25.270192
7729 15:36:25.270271
7730 15:36:25.270334 TX Vref Scan disable
7731 15:36:25.272871 == TX Byte 0 ==
7732 15:36:25.276310 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7733 15:36:25.279794 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7734 15:36:25.283052 == TX Byte 1 ==
7735 15:36:25.286259 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7736 15:36:25.289426 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7737 15:36:25.289506 ==
7738 15:36:25.292819 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 15:36:25.299724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 15:36:25.299806 ==
7741 15:36:25.312061
7742 15:36:25.315288 TX Vref early break, caculate TX vref
7743 15:36:25.318241 TX Vref=16, minBit 9, minWin=21, winSum=363
7744 15:36:25.321927 TX Vref=18, minBit 8, minWin=22, winSum=375
7745 15:36:25.325013 TX Vref=20, minBit 1, minWin=23, winSum=386
7746 15:36:25.328325 TX Vref=22, minBit 10, minWin=23, winSum=393
7747 15:36:25.331341 TX Vref=24, minBit 0, minWin=25, winSum=406
7748 15:36:25.338348 TX Vref=26, minBit 1, minWin=25, winSum=409
7749 15:36:25.341792 TX Vref=28, minBit 1, minWin=25, winSum=416
7750 15:36:25.344636 TX Vref=30, minBit 4, minWin=24, winSum=410
7751 15:36:25.348276 TX Vref=32, minBit 7, minWin=23, winSum=398
7752 15:36:25.351611 TX Vref=34, minBit 4, minWin=23, winSum=390
7753 15:36:25.357799 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 28
7754 15:36:25.357880
7755 15:36:25.361133 Final TX Range 0 Vref 28
7756 15:36:25.361214
7757 15:36:25.361277 ==
7758 15:36:25.364879 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 15:36:25.367903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 15:36:25.367984 ==
7761 15:36:25.368048
7762 15:36:25.368107
7763 15:36:25.371207 TX Vref Scan disable
7764 15:36:25.378076 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7765 15:36:25.378158 == TX Byte 0 ==
7766 15:36:25.380989 u2DelayCellOfst[0]=14 cells (4 PI)
7767 15:36:25.384241 u2DelayCellOfst[1]=18 cells (5 PI)
7768 15:36:25.387840 u2DelayCellOfst[2]=14 cells (4 PI)
7769 15:36:25.390860 u2DelayCellOfst[3]=14 cells (4 PI)
7770 15:36:25.394071 u2DelayCellOfst[4]=11 cells (3 PI)
7771 15:36:25.397474 u2DelayCellOfst[5]=0 cells (0 PI)
7772 15:36:25.401026 u2DelayCellOfst[6]=18 cells (5 PI)
7773 15:36:25.404273 u2DelayCellOfst[7]=22 cells (6 PI)
7774 15:36:25.407567 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7775 15:36:25.411043 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7776 15:36:25.414347 == TX Byte 1 ==
7777 15:36:25.417068 u2DelayCellOfst[8]=0 cells (0 PI)
7778 15:36:25.420435 u2DelayCellOfst[9]=3 cells (1 PI)
7779 15:36:25.423711 u2DelayCellOfst[10]=7 cells (2 PI)
7780 15:36:25.427517 u2DelayCellOfst[11]=3 cells (1 PI)
7781 15:36:25.427598 u2DelayCellOfst[12]=11 cells (3 PI)
7782 15:36:25.430228 u2DelayCellOfst[13]=11 cells (3 PI)
7783 15:36:25.433780 u2DelayCellOfst[14]=18 cells (5 PI)
7784 15:36:25.437052 u2DelayCellOfst[15]=11 cells (3 PI)
7785 15:36:25.443987 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7786 15:36:25.446909 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7787 15:36:25.447000 DramC Write-DBI on
7788 15:36:25.450136 ==
7789 15:36:25.453608 Dram Type= 6, Freq= 0, CH_0, rank 0
7790 15:36:25.457064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7791 15:36:25.457145 ==
7792 15:36:25.457209
7793 15:36:25.457268
7794 15:36:25.460307 TX Vref Scan disable
7795 15:36:25.460387 == TX Byte 0 ==
7796 15:36:25.467175 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7797 15:36:25.467256 == TX Byte 1 ==
7798 15:36:25.470532 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7799 15:36:25.473610 DramC Write-DBI off
7800 15:36:25.473690
7801 15:36:25.473753 [DATLAT]
7802 15:36:25.477170 Freq=1600, CH0 RK0
7803 15:36:25.477279
7804 15:36:25.477342 DATLAT Default: 0xf
7805 15:36:25.480462 0, 0xFFFF, sum = 0
7806 15:36:25.480555 1, 0xFFFF, sum = 0
7807 15:36:25.483607 2, 0xFFFF, sum = 0
7808 15:36:25.483687 3, 0xFFFF, sum = 0
7809 15:36:25.487052 4, 0xFFFF, sum = 0
7810 15:36:25.487134 5, 0xFFFF, sum = 0
7811 15:36:25.489969 6, 0xFFFF, sum = 0
7812 15:36:25.493398 7, 0xFFFF, sum = 0
7813 15:36:25.493480 8, 0xFFFF, sum = 0
7814 15:36:25.496523 9, 0xFFFF, sum = 0
7815 15:36:25.496604 10, 0xFFFF, sum = 0
7816 15:36:25.500057 11, 0xFFFF, sum = 0
7817 15:36:25.500139 12, 0xFFFF, sum = 0
7818 15:36:25.503604 13, 0xFFFF, sum = 0
7819 15:36:25.503685 14, 0x0, sum = 1
7820 15:36:25.506323 15, 0x0, sum = 2
7821 15:36:25.506404 16, 0x0, sum = 3
7822 15:36:25.509795 17, 0x0, sum = 4
7823 15:36:25.509877 best_step = 15
7824 15:36:25.509941
7825 15:36:25.510000 ==
7826 15:36:25.513391 Dram Type= 6, Freq= 0, CH_0, rank 0
7827 15:36:25.516397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7828 15:36:25.519780 ==
7829 15:36:25.519858 RX Vref Scan: 1
7830 15:36:25.519927
7831 15:36:25.523311 Set Vref Range= 24 -> 127
7832 15:36:25.523410
7833 15:36:25.526679 RX Vref 24 -> 127, step: 1
7834 15:36:25.526757
7835 15:36:25.526821 RX Delay 11 -> 252, step: 4
7836 15:36:25.526880
7837 15:36:25.529583 Set Vref, RX VrefLevel [Byte0]: 24
7838 15:36:25.533160 [Byte1]: 24
7839 15:36:25.536986
7840 15:36:25.537059 Set Vref, RX VrefLevel [Byte0]: 25
7841 15:36:25.539874 [Byte1]: 25
7842 15:36:25.544683
7843 15:36:25.544759 Set Vref, RX VrefLevel [Byte0]: 26
7844 15:36:25.547575 [Byte1]: 26
7845 15:36:25.552019
7846 15:36:25.552091 Set Vref, RX VrefLevel [Byte0]: 27
7847 15:36:25.555210 [Byte1]: 27
7848 15:36:25.559818
7849 15:36:25.559903 Set Vref, RX VrefLevel [Byte0]: 28
7850 15:36:25.562550 [Byte1]: 28
7851 15:36:25.567364
7852 15:36:25.567444 Set Vref, RX VrefLevel [Byte0]: 29
7853 15:36:25.570214 [Byte1]: 29
7854 15:36:25.574744
7855 15:36:25.574824 Set Vref, RX VrefLevel [Byte0]: 30
7856 15:36:25.578045 [Byte1]: 30
7857 15:36:25.582217
7858 15:36:25.582297 Set Vref, RX VrefLevel [Byte0]: 31
7859 15:36:25.585872 [Byte1]: 31
7860 15:36:25.589737
7861 15:36:25.589826 Set Vref, RX VrefLevel [Byte0]: 32
7862 15:36:25.593726 [Byte1]: 32
7863 15:36:25.597646
7864 15:36:25.597734 Set Vref, RX VrefLevel [Byte0]: 33
7865 15:36:25.601328 [Byte1]: 33
7866 15:36:25.605390
7867 15:36:25.605492 Set Vref, RX VrefLevel [Byte0]: 34
7868 15:36:25.608762 [Byte1]: 34
7869 15:36:25.612618
7870 15:36:25.612700 Set Vref, RX VrefLevel [Byte0]: 35
7871 15:36:25.616185 [Byte1]: 35
7872 15:36:25.620539
7873 15:36:25.620620 Set Vref, RX VrefLevel [Byte0]: 36
7874 15:36:25.623894 [Byte1]: 36
7875 15:36:25.628014
7876 15:36:25.631651 Set Vref, RX VrefLevel [Byte0]: 37
7877 15:36:25.634556 [Byte1]: 37
7878 15:36:25.634675
7879 15:36:25.638148 Set Vref, RX VrefLevel [Byte0]: 38
7880 15:36:25.641068 [Byte1]: 38
7881 15:36:25.641148
7882 15:36:25.644435 Set Vref, RX VrefLevel [Byte0]: 39
7883 15:36:25.647559 [Byte1]: 39
7884 15:36:25.650914
7885 15:36:25.650993 Set Vref, RX VrefLevel [Byte0]: 40
7886 15:36:25.654113 [Byte1]: 40
7887 15:36:25.658265
7888 15:36:25.658352 Set Vref, RX VrefLevel [Byte0]: 41
7889 15:36:25.661635 [Byte1]: 41
7890 15:36:25.666165
7891 15:36:25.666251 Set Vref, RX VrefLevel [Byte0]: 42
7892 15:36:25.669578 [Byte1]: 42
7893 15:36:25.673625
7894 15:36:25.673704 Set Vref, RX VrefLevel [Byte0]: 43
7895 15:36:25.677025 [Byte1]: 43
7896 15:36:25.681135
7897 15:36:25.681214 Set Vref, RX VrefLevel [Byte0]: 44
7898 15:36:25.684555 [Byte1]: 44
7899 15:36:25.688916
7900 15:36:25.688997 Set Vref, RX VrefLevel [Byte0]: 45
7901 15:36:25.691978 [Byte1]: 45
7902 15:36:25.696491
7903 15:36:25.696575 Set Vref, RX VrefLevel [Byte0]: 46
7904 15:36:25.699835 [Byte1]: 46
7905 15:36:25.703959
7906 15:36:25.704039 Set Vref, RX VrefLevel [Byte0]: 47
7907 15:36:25.707536 [Byte1]: 47
7908 15:36:25.711881
7909 15:36:25.711962 Set Vref, RX VrefLevel [Byte0]: 48
7910 15:36:25.715431 [Byte1]: 48
7911 15:36:25.719487
7912 15:36:25.719566 Set Vref, RX VrefLevel [Byte0]: 49
7913 15:36:25.722510 [Byte1]: 49
7914 15:36:25.727205
7915 15:36:25.727285 Set Vref, RX VrefLevel [Byte0]: 50
7916 15:36:25.730770 [Byte1]: 50
7917 15:36:25.734610
7918 15:36:25.734691 Set Vref, RX VrefLevel [Byte0]: 51
7919 15:36:25.738064 [Byte1]: 51
7920 15:36:25.742137
7921 15:36:25.742218 Set Vref, RX VrefLevel [Byte0]: 52
7922 15:36:25.745581 [Byte1]: 52
7923 15:36:25.749580
7924 15:36:25.749660 Set Vref, RX VrefLevel [Byte0]: 53
7925 15:36:25.753085 [Byte1]: 53
7926 15:36:25.757449
7927 15:36:25.757532 Set Vref, RX VrefLevel [Byte0]: 54
7928 15:36:25.760548 [Byte1]: 54
7929 15:36:25.765024
7930 15:36:25.765107 Set Vref, RX VrefLevel [Byte0]: 55
7931 15:36:25.768171 [Byte1]: 55
7932 15:36:25.772570
7933 15:36:25.772651 Set Vref, RX VrefLevel [Byte0]: 56
7934 15:36:25.776366 [Byte1]: 56
7935 15:36:25.780375
7936 15:36:25.780456 Set Vref, RX VrefLevel [Byte0]: 57
7937 15:36:25.783683 [Byte1]: 57
7938 15:36:25.787748
7939 15:36:25.787828 Set Vref, RX VrefLevel [Byte0]: 58
7940 15:36:25.791400 [Byte1]: 58
7941 15:36:25.795219
7942 15:36:25.795299 Set Vref, RX VrefLevel [Byte0]: 59
7943 15:36:25.798945 [Byte1]: 59
7944 15:36:25.803003
7945 15:36:25.803084 Set Vref, RX VrefLevel [Byte0]: 60
7946 15:36:25.806426 [Byte1]: 60
7947 15:36:25.810883
7948 15:36:25.810989 Set Vref, RX VrefLevel [Byte0]: 61
7949 15:36:25.813818 [Byte1]: 61
7950 15:36:25.818108
7951 15:36:25.818188 Set Vref, RX VrefLevel [Byte0]: 62
7952 15:36:25.821949 [Byte1]: 62
7953 15:36:25.825713
7954 15:36:25.825793 Set Vref, RX VrefLevel [Byte0]: 63
7955 15:36:25.829565 [Byte1]: 63
7956 15:36:25.833484
7957 15:36:25.833564 Set Vref, RX VrefLevel [Byte0]: 64
7958 15:36:25.837040 [Byte1]: 64
7959 15:36:25.841600
7960 15:36:25.841680 Set Vref, RX VrefLevel [Byte0]: 65
7961 15:36:25.844638 [Byte1]: 65
7962 15:36:25.849012
7963 15:36:25.849092 Set Vref, RX VrefLevel [Byte0]: 66
7964 15:36:25.852325 [Byte1]: 66
7965 15:36:25.856136
7966 15:36:25.856216 Set Vref, RX VrefLevel [Byte0]: 67
7967 15:36:25.859555 [Byte1]: 67
7968 15:36:25.864012
7969 15:36:25.864092 Set Vref, RX VrefLevel [Byte0]: 68
7970 15:36:25.867326 [Byte1]: 68
7971 15:36:25.871545
7972 15:36:25.871625 Set Vref, RX VrefLevel [Byte0]: 69
7973 15:36:25.874808 [Byte1]: 69
7974 15:36:25.879181
7975 15:36:25.879260 Set Vref, RX VrefLevel [Byte0]: 70
7976 15:36:25.882362 [Byte1]: 70
7977 15:36:25.886793
7978 15:36:25.886872 Set Vref, RX VrefLevel [Byte0]: 71
7979 15:36:25.890175 [Byte1]: 71
7980 15:36:25.894778
7981 15:36:25.894884 Set Vref, RX VrefLevel [Byte0]: 72
7982 15:36:25.897955 [Byte1]: 72
7983 15:36:25.902060
7984 15:36:25.902142 Set Vref, RX VrefLevel [Byte0]: 73
7985 15:36:25.905247 [Byte1]: 73
7986 15:36:25.909679
7987 15:36:25.909768 Set Vref, RX VrefLevel [Byte0]: 74
7988 15:36:25.912995 [Byte1]: 74
7989 15:36:25.917162
7990 15:36:25.917247 Set Vref, RX VrefLevel [Byte0]: 75
7991 15:36:25.920339 [Byte1]: 75
7992 15:36:25.924783
7993 15:36:25.927905 Set Vref, RX VrefLevel [Byte0]: 76
7994 15:36:25.927985 [Byte1]: 76
7995 15:36:25.932327
7996 15:36:25.932407 Set Vref, RX VrefLevel [Byte0]: 77
7997 15:36:25.935486 [Byte1]: 77
7998 15:36:25.939988
7999 15:36:25.940068 Set Vref, RX VrefLevel [Byte0]: 78
8000 15:36:25.943453 [Byte1]: 78
8001 15:36:25.947984
8002 15:36:25.948063 Set Vref, RX VrefLevel [Byte0]: 79
8003 15:36:25.951110 [Byte1]: 79
8004 15:36:25.955636
8005 15:36:25.955715 Final RX Vref Byte 0 = 64 to rank0
8006 15:36:25.958978 Final RX Vref Byte 1 = 57 to rank0
8007 15:36:25.961784 Final RX Vref Byte 0 = 64 to rank1
8008 15:36:25.965074 Final RX Vref Byte 1 = 57 to rank1==
8009 15:36:25.968498 Dram Type= 6, Freq= 0, CH_0, rank 0
8010 15:36:25.975282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 15:36:25.975363 ==
8012 15:36:25.975426 DQS Delay:
8013 15:36:25.978281 DQS0 = 0, DQS1 = 0
8014 15:36:25.978361 DQM Delay:
8015 15:36:25.978425 DQM0 = 133, DQM1 = 123
8016 15:36:25.981687 DQ Delay:
8017 15:36:25.984944 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8018 15:36:25.988159 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8019 15:36:25.991489 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =118
8020 15:36:25.994845 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
8021 15:36:25.994926
8022 15:36:25.994989
8023 15:36:25.995048
8024 15:36:25.998227 [DramC_TX_OE_Calibration] TA2
8025 15:36:26.001613 Original DQ_B0 (3 6) =30, OEN = 27
8026 15:36:26.004930 Original DQ_B1 (3 6) =30, OEN = 27
8027 15:36:26.008009 24, 0x0, End_B0=24 End_B1=24
8028 15:36:26.008091 25, 0x0, End_B0=25 End_B1=25
8029 15:36:26.011250 26, 0x0, End_B0=26 End_B1=26
8030 15:36:26.014573 27, 0x0, End_B0=27 End_B1=27
8031 15:36:26.018028 28, 0x0, End_B0=28 End_B1=28
8032 15:36:26.021635 29, 0x0, End_B0=29 End_B1=29
8033 15:36:26.021712 30, 0x0, End_B0=30 End_B1=30
8034 15:36:26.024467 31, 0x4141, End_B0=30 End_B1=30
8035 15:36:26.027619 Byte0 end_step=30 best_step=27
8036 15:36:26.030917 Byte1 end_step=30 best_step=27
8037 15:36:26.034281 Byte0 TX OE(2T, 0.5T) = (3, 3)
8038 15:36:26.037921 Byte1 TX OE(2T, 0.5T) = (3, 3)
8039 15:36:26.038031
8040 15:36:26.038126
8041 15:36:26.044419 [DQSOSCAuto] RK0, (LSB)MR18= 0x2213, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
8042 15:36:26.047575 CH0 RK0: MR19=303, MR18=2213
8043 15:36:26.053906 CH0_RK0: MR19=0x303, MR18=0x2213, DQSOSC=392, MR23=63, INC=24, DEC=16
8044 15:36:26.053987
8045 15:36:26.057328 ----->DramcWriteLeveling(PI) begin...
8046 15:36:26.057410 ==
8047 15:36:26.060918 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 15:36:26.064035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 15:36:26.064117 ==
8050 15:36:26.067223 Write leveling (Byte 0): 35 => 35
8051 15:36:26.070577 Write leveling (Byte 1): 28 => 28
8052 15:36:26.074045 DramcWriteLeveling(PI) end<-----
8053 15:36:26.074124
8054 15:36:26.074187 ==
8055 15:36:26.077433 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 15:36:26.084077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 15:36:26.084158 ==
8058 15:36:26.084222 [Gating] SW mode calibration
8059 15:36:26.094261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8060 15:36:26.096772 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8061 15:36:26.100642 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 15:36:26.107009 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 15:36:26.109923 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 15:36:26.113480 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8065 15:36:26.120101 1 4 16 | B1->B0 | 2322 3434 | 1 0 | (0 0) (0 0)
8066 15:36:26.123159 1 4 20 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8067 15:36:26.126780 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 15:36:26.133010 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 15:36:26.136559 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 15:36:26.139598 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 15:36:26.146375 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8072 15:36:26.149466 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8073 15:36:26.152655 1 5 16 | B1->B0 | 3333 2626 | 0 0 | (0 1) (0 0)
8074 15:36:26.159782 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
8075 15:36:26.162901 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 15:36:26.169812 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 15:36:26.172518 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 15:36:26.175962 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 15:36:26.182656 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 15:36:26.185621 1 6 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8081 15:36:26.189010 1 6 16 | B1->B0 | 2c2c 4545 | 0 0 | (0 0) (1 1)
8082 15:36:26.195880 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 15:36:26.198856 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 15:36:26.202257 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 15:36:26.205509 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 15:36:26.212243 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 15:36:26.215308 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 15:36:26.221972 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8089 15:36:26.225271 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8090 15:36:26.228625 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8091 15:36:26.235280 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 15:36:26.238577 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 15:36:26.241876 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 15:36:26.248177 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 15:36:26.251605 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 15:36:26.254951 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 15:36:26.261584 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 15:36:26.265035 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 15:36:26.268010 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 15:36:26.274624 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 15:36:26.278149 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 15:36:26.281350 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 15:36:26.287859 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 15:36:26.290952 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8105 15:36:26.294243 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8106 15:36:26.297672 Total UI for P1: 0, mck2ui 16
8107 15:36:26.301127 best dqsien dly found for B0: ( 1, 9, 12)
8108 15:36:26.307573 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8109 15:36:26.310705 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 15:36:26.314141 Total UI for P1: 0, mck2ui 16
8111 15:36:26.317223 best dqsien dly found for B1: ( 1, 9, 18)
8112 15:36:26.320466 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8113 15:36:26.324059 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8114 15:36:26.324139
8115 15:36:26.327625 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8116 15:36:26.330893 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8117 15:36:26.333625 [Gating] SW calibration Done
8118 15:36:26.333730 ==
8119 15:36:26.337058 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 15:36:26.340741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 15:36:26.343787 ==
8122 15:36:26.343859 RX Vref Scan: 0
8123 15:36:26.343923
8124 15:36:26.347308 RX Vref 0 -> 0, step: 1
8125 15:36:26.347382
8126 15:36:26.350881 RX Delay 0 -> 252, step: 8
8127 15:36:26.353529 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8128 15:36:26.357171 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8129 15:36:26.360522 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8130 15:36:26.363766 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8131 15:36:26.370151 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8132 15:36:26.373534 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8133 15:36:26.377098 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8134 15:36:26.380258 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8135 15:36:26.383405 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8136 15:36:26.390405 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8137 15:36:26.393474 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8138 15:36:26.396643 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8139 15:36:26.399899 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8140 15:36:26.403158 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8141 15:36:26.410247 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8142 15:36:26.413558 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8143 15:36:26.413632 ==
8144 15:36:26.417215 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 15:36:26.419783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 15:36:26.419860 ==
8147 15:36:26.422883 DQS Delay:
8148 15:36:26.422955 DQS0 = 0, DQS1 = 0
8149 15:36:26.423015 DQM Delay:
8150 15:36:26.426385 DQM0 = 132, DQM1 = 130
8151 15:36:26.426491 DQ Delay:
8152 15:36:26.429660 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8153 15:36:26.436326 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8154 15:36:26.439423 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =127
8155 15:36:26.442702 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8156 15:36:26.442775
8157 15:36:26.442836
8158 15:36:26.442904 ==
8159 15:36:26.446178 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 15:36:26.449345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 15:36:26.449423 ==
8162 15:36:26.449486
8163 15:36:26.449544
8164 15:36:26.452864 TX Vref Scan disable
8165 15:36:26.456472 == TX Byte 0 ==
8166 15:36:26.459289 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8167 15:36:26.462778 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8168 15:36:26.465996 == TX Byte 1 ==
8169 15:36:26.469418 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8170 15:36:26.472474 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8171 15:36:26.472547 ==
8172 15:36:26.475787 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 15:36:26.482296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 15:36:26.482401 ==
8175 15:36:26.494337
8176 15:36:26.497820 TX Vref early break, caculate TX vref
8177 15:36:26.501014 TX Vref=16, minBit 3, minWin=22, winSum=372
8178 15:36:26.504145 TX Vref=18, minBit 8, minWin=22, winSum=381
8179 15:36:26.507484 TX Vref=20, minBit 1, minWin=22, winSum=390
8180 15:36:26.511075 TX Vref=22, minBit 1, minWin=24, winSum=399
8181 15:36:26.514390 TX Vref=24, minBit 0, minWin=24, winSum=403
8182 15:36:26.520707 TX Vref=26, minBit 0, minWin=24, winSum=406
8183 15:36:26.524111 TX Vref=28, minBit 2, minWin=24, winSum=412
8184 15:36:26.527503 TX Vref=30, minBit 1, minWin=24, winSum=406
8185 15:36:26.530959 TX Vref=32, minBit 0, minWin=24, winSum=395
8186 15:36:26.533841 TX Vref=34, minBit 0, minWin=23, winSum=388
8187 15:36:26.540783 [TxChooseVref] Worse bit 2, Min win 24, Win sum 412, Final Vref 28
8188 15:36:26.540859
8189 15:36:26.543906 Final TX Range 0 Vref 28
8190 15:36:26.543985
8191 15:36:26.544049 ==
8192 15:36:26.547611 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 15:36:26.550565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 15:36:26.550692 ==
8195 15:36:26.550756
8196 15:36:26.550815
8197 15:36:26.553640 TX Vref Scan disable
8198 15:36:26.560172 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8199 15:36:26.560250 == TX Byte 0 ==
8200 15:36:26.563720 u2DelayCellOfst[0]=14 cells (4 PI)
8201 15:36:26.567158 u2DelayCellOfst[1]=18 cells (5 PI)
8202 15:36:26.570421 u2DelayCellOfst[2]=14 cells (4 PI)
8203 15:36:26.573369 u2DelayCellOfst[3]=14 cells (4 PI)
8204 15:36:26.576855 u2DelayCellOfst[4]=11 cells (3 PI)
8205 15:36:26.580262 u2DelayCellOfst[5]=0 cells (0 PI)
8206 15:36:26.583515 u2DelayCellOfst[6]=18 cells (5 PI)
8207 15:36:26.586938 u2DelayCellOfst[7]=22 cells (6 PI)
8208 15:36:26.590022 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8209 15:36:26.593213 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8210 15:36:26.596646 == TX Byte 1 ==
8211 15:36:26.599802 u2DelayCellOfst[8]=0 cells (0 PI)
8212 15:36:26.603042 u2DelayCellOfst[9]=0 cells (0 PI)
8213 15:36:26.606057 u2DelayCellOfst[10]=3 cells (1 PI)
8214 15:36:26.609365 u2DelayCellOfst[11]=0 cells (0 PI)
8215 15:36:26.609435 u2DelayCellOfst[12]=7 cells (2 PI)
8216 15:36:26.612570 u2DelayCellOfst[13]=7 cells (2 PI)
8217 15:36:26.616015 u2DelayCellOfst[14]=14 cells (4 PI)
8218 15:36:26.619351 u2DelayCellOfst[15]=7 cells (2 PI)
8219 15:36:26.625727 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8220 15:36:26.629448 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8221 15:36:26.629521 DramC Write-DBI on
8222 15:36:26.632303 ==
8223 15:36:26.636262 Dram Type= 6, Freq= 0, CH_0, rank 1
8224 15:36:26.638974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 15:36:26.639045 ==
8226 15:36:26.639105
8227 15:36:26.639163
8228 15:36:26.642511 TX Vref Scan disable
8229 15:36:26.642610 == TX Byte 0 ==
8230 15:36:26.649262 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8231 15:36:26.649336 == TX Byte 1 ==
8232 15:36:26.652491 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8233 15:36:26.655648 DramC Write-DBI off
8234 15:36:26.655726
8235 15:36:26.655789 [DATLAT]
8236 15:36:26.658947 Freq=1600, CH0 RK1
8237 15:36:26.659020
8238 15:36:26.659081 DATLAT Default: 0xf
8239 15:36:26.661985 0, 0xFFFF, sum = 0
8240 15:36:26.662056 1, 0xFFFF, sum = 0
8241 15:36:26.665319 2, 0xFFFF, sum = 0
8242 15:36:26.665420 3, 0xFFFF, sum = 0
8243 15:36:26.668750 4, 0xFFFF, sum = 0
8244 15:36:26.671918 5, 0xFFFF, sum = 0
8245 15:36:26.671994 6, 0xFFFF, sum = 0
8246 15:36:26.675378 7, 0xFFFF, sum = 0
8247 15:36:26.675460 8, 0xFFFF, sum = 0
8248 15:36:26.678554 9, 0xFFFF, sum = 0
8249 15:36:26.678686 10, 0xFFFF, sum = 0
8250 15:36:26.681611 11, 0xFFFF, sum = 0
8251 15:36:26.681682 12, 0xFFFF, sum = 0
8252 15:36:26.684951 13, 0xFFFF, sum = 0
8253 15:36:26.685023 14, 0x0, sum = 1
8254 15:36:26.688378 15, 0x0, sum = 2
8255 15:36:26.688455 16, 0x0, sum = 3
8256 15:36:26.691740 17, 0x0, sum = 4
8257 15:36:26.691818 best_step = 15
8258 15:36:26.691879
8259 15:36:26.691937 ==
8260 15:36:26.695130 Dram Type= 6, Freq= 0, CH_0, rank 1
8261 15:36:26.701890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 15:36:26.701976 ==
8263 15:36:26.702043 RX Vref Scan: 0
8264 15:36:26.702104
8265 15:36:26.704629 RX Vref 0 -> 0, step: 1
8266 15:36:26.704701
8267 15:36:26.707949 RX Delay 11 -> 252, step: 4
8268 15:36:26.711374 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8269 15:36:26.714735 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8270 15:36:26.718150 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8271 15:36:26.724723 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8272 15:36:26.727957 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8273 15:36:26.731057 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8274 15:36:26.734304 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8275 15:36:26.737919 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8276 15:36:26.744693 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8277 15:36:26.748153 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8278 15:36:26.750877 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8279 15:36:26.754361 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8280 15:36:26.761186 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8281 15:36:26.764289 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8282 15:36:26.767654 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8283 15:36:26.771128 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8284 15:36:26.771208 ==
8285 15:36:26.774402 Dram Type= 6, Freq= 0, CH_0, rank 1
8286 15:36:26.777528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 15:36:26.780687 ==
8288 15:36:26.780767 DQS Delay:
8289 15:36:26.780831 DQS0 = 0, DQS1 = 0
8290 15:36:26.784209 DQM Delay:
8291 15:36:26.784289 DQM0 = 130, DQM1 = 125
8292 15:36:26.787204 DQ Delay:
8293 15:36:26.790978 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =128
8294 15:36:26.794216 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8295 15:36:26.797306 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8296 15:36:26.800818 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8297 15:36:26.800898
8298 15:36:26.800981
8299 15:36:26.801042
8300 15:36:26.803992 [DramC_TX_OE_Calibration] TA2
8301 15:36:26.807483 Original DQ_B0 (3 6) =30, OEN = 27
8302 15:36:26.810632 Original DQ_B1 (3 6) =30, OEN = 27
8303 15:36:26.813693 24, 0x0, End_B0=24 End_B1=24
8304 15:36:26.813774 25, 0x0, End_B0=25 End_B1=25
8305 15:36:26.816929 26, 0x0, End_B0=26 End_B1=26
8306 15:36:26.820643 27, 0x0, End_B0=27 End_B1=27
8307 15:36:26.823639 28, 0x0, End_B0=28 End_B1=28
8308 15:36:26.827325 29, 0x0, End_B0=29 End_B1=29
8309 15:36:26.827407 30, 0x0, End_B0=30 End_B1=30
8310 15:36:26.830023 31, 0x4141, End_B0=30 End_B1=30
8311 15:36:26.833419 Byte0 end_step=30 best_step=27
8312 15:36:26.837136 Byte1 end_step=30 best_step=27
8313 15:36:26.840646 Byte0 TX OE(2T, 0.5T) = (3, 3)
8314 15:36:26.843280 Byte1 TX OE(2T, 0.5T) = (3, 3)
8315 15:36:26.843359
8316 15:36:26.843423
8317 15:36:26.850028 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8318 15:36:26.853305 CH0 RK1: MR19=303, MR18=1E02
8319 15:36:26.859707 CH0_RK1: MR19=0x303, MR18=0x1E02, DQSOSC=394, MR23=63, INC=23, DEC=15
8320 15:36:26.863458 [RxdqsGatingPostProcess] freq 1600
8321 15:36:26.866326 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8322 15:36:26.869975 best DQS0 dly(2T, 0.5T) = (1, 1)
8323 15:36:26.873441 best DQS1 dly(2T, 0.5T) = (1, 1)
8324 15:36:26.876613 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8325 15:36:26.879877 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8326 15:36:26.882782 best DQS0 dly(2T, 0.5T) = (1, 1)
8327 15:36:26.886159 best DQS1 dly(2T, 0.5T) = (1, 1)
8328 15:36:26.889451 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8329 15:36:26.893066 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8330 15:36:26.896087 Pre-setting of DQS Precalculation
8331 15:36:26.899647 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8332 15:36:26.899727 ==
8333 15:36:26.902857 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 15:36:26.909508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 15:36:26.909617 ==
8336 15:36:26.912577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8337 15:36:26.919193 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8338 15:36:26.922498 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8339 15:36:26.928942 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8340 15:36:26.936944 [CA 0] Center 42 (12~72) winsize 61
8341 15:36:26.940194 [CA 1] Center 42 (13~72) winsize 60
8342 15:36:26.943463 [CA 2] Center 38 (9~67) winsize 59
8343 15:36:26.946722 [CA 3] Center 37 (8~66) winsize 59
8344 15:36:26.949928 [CA 4] Center 37 (8~67) winsize 60
8345 15:36:26.953187 [CA 5] Center 37 (8~67) winsize 60
8346 15:36:26.953267
8347 15:36:26.956399 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8348 15:36:26.956478
8349 15:36:26.963214 [CATrainingPosCal] consider 1 rank data
8350 15:36:26.963294 u2DelayCellTimex100 = 262/100 ps
8351 15:36:26.969879 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8352 15:36:26.973163 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8353 15:36:26.976498 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8354 15:36:26.979390 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8355 15:36:26.982801 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8356 15:36:26.986111 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8357 15:36:26.986190
8358 15:36:26.989570 CA PerBit enable=1, Macro0, CA PI delay=37
8359 15:36:26.989650
8360 15:36:26.993207 [CBTSetCACLKResult] CA Dly = 37
8361 15:36:26.995795 CS Dly: 9 (0~40)
8362 15:36:26.999089 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8363 15:36:27.002713 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8364 15:36:27.002792 ==
8365 15:36:27.005927 Dram Type= 6, Freq= 0, CH_1, rank 1
8366 15:36:27.012440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 15:36:27.012521 ==
8368 15:36:27.015838 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8369 15:36:27.022478 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8370 15:36:27.025665 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8371 15:36:27.031983 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8372 15:36:27.040095 [CA 0] Center 41 (12~71) winsize 60
8373 15:36:27.043337 [CA 1] Center 42 (13~72) winsize 60
8374 15:36:27.046220 [CA 2] Center 37 (8~67) winsize 60
8375 15:36:27.050290 [CA 3] Center 36 (7~66) winsize 60
8376 15:36:27.053024 [CA 4] Center 37 (8~67) winsize 60
8377 15:36:27.056448 [CA 5] Center 36 (7~66) winsize 60
8378 15:36:27.056595
8379 15:36:27.059532 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8380 15:36:27.059751
8381 15:36:27.066989 [CATrainingPosCal] consider 2 rank data
8382 15:36:27.067138 u2DelayCellTimex100 = 262/100 ps
8383 15:36:27.072884 CA0 delay=41 (12~71),Diff = 4 PI (14 cell)
8384 15:36:27.076398 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8385 15:36:27.079312 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8386 15:36:27.082582 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8387 15:36:27.086069 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8388 15:36:27.089317 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8389 15:36:27.089399
8390 15:36:27.092607 CA PerBit enable=1, Macro0, CA PI delay=37
8391 15:36:27.092689
8392 15:36:27.096047 [CBTSetCACLKResult] CA Dly = 37
8393 15:36:27.099131 CS Dly: 11 (0~44)
8394 15:36:27.102408 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8395 15:36:27.105705 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8396 15:36:27.105780
8397 15:36:27.109024 ----->DramcWriteLeveling(PI) begin...
8398 15:36:27.112436 ==
8399 15:36:27.112510 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 15:36:27.118974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 15:36:27.119088 ==
8402 15:36:27.122343 Write leveling (Byte 0): 23 => 23
8403 15:36:27.125154 Write leveling (Byte 1): 26 => 26
8404 15:36:27.128695 DramcWriteLeveling(PI) end<-----
8405 15:36:27.128778
8406 15:36:27.128861 ==
8407 15:36:27.131682 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 15:36:27.135392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 15:36:27.135470 ==
8410 15:36:27.138788 [Gating] SW mode calibration
8411 15:36:27.144902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8412 15:36:27.151641 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8413 15:36:27.154769 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 15:36:27.158489 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 15:36:27.165097 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8416 15:36:27.168243 1 4 12 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8417 15:36:27.171237 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 15:36:27.178753 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 15:36:27.181389 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 15:36:27.184696 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 15:36:27.191423 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 15:36:27.194275 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 15:36:27.197935 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8424 15:36:27.204477 1 5 12 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (1 0)
8425 15:36:27.208041 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 15:36:27.211380 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 15:36:27.217829 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 15:36:27.220920 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 15:36:27.224341 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 15:36:27.231302 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 15:36:27.234293 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8432 15:36:27.238180 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8433 15:36:27.244566 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 15:36:27.247674 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 15:36:27.250826 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 15:36:27.257524 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 15:36:27.260447 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 15:36:27.263869 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 15:36:27.268004 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8440 15:36:27.274131 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8441 15:36:27.277348 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 15:36:27.283946 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 15:36:27.287487 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 15:36:27.290440 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 15:36:27.293634 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 15:36:27.300579 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 15:36:27.303466 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 15:36:27.307060 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 15:36:27.313597 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 15:36:27.317066 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 15:36:27.320554 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 15:36:27.326497 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 15:36:27.330133 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 15:36:27.333587 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 15:36:27.340270 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8456 15:36:27.343089 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8457 15:36:27.346398 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 15:36:27.350064 Total UI for P1: 0, mck2ui 16
8459 15:36:27.353144 best dqsien dly found for B0: ( 1, 9, 10)
8460 15:36:27.356527 Total UI for P1: 0, mck2ui 16
8461 15:36:27.359521 best dqsien dly found for B1: ( 1, 9, 10)
8462 15:36:27.362994 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8463 15:36:27.369351 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8464 15:36:27.369452
8465 15:36:27.373181 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8466 15:36:27.376159 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8467 15:36:27.379383 [Gating] SW calibration Done
8468 15:36:27.379457 ==
8469 15:36:27.382865 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 15:36:27.385902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 15:36:27.385972 ==
8472 15:36:27.389399 RX Vref Scan: 0
8473 15:36:27.389468
8474 15:36:27.389527 RX Vref 0 -> 0, step: 1
8475 15:36:27.389585
8476 15:36:27.393029 RX Delay 0 -> 252, step: 8
8477 15:36:27.396410 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8478 15:36:27.399331 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8479 15:36:27.406208 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8480 15:36:27.409263 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8481 15:36:27.412611 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8482 15:36:27.415739 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8483 15:36:27.422791 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8484 15:36:27.425620 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8485 15:36:27.428938 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8486 15:36:27.432310 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8487 15:36:27.435616 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8488 15:36:27.441817 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8489 15:36:27.445485 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8490 15:36:27.448556 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8491 15:36:27.451990 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8492 15:36:27.458434 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8493 15:36:27.458539 ==
8494 15:36:27.462397 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 15:36:27.465496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 15:36:27.465566 ==
8497 15:36:27.465641 DQS Delay:
8498 15:36:27.468610 DQS0 = 0, DQS1 = 0
8499 15:36:27.468684 DQM Delay:
8500 15:36:27.472469 DQM0 = 138, DQM1 = 128
8501 15:36:27.472546 DQ Delay:
8502 15:36:27.475343 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8503 15:36:27.478622 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8504 15:36:27.482019 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8505 15:36:27.485033 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8506 15:36:27.485117
8507 15:36:27.485214
8508 15:36:27.485309 ==
8509 15:36:27.488647 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 15:36:27.495212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 15:36:27.495319 ==
8512 15:36:27.495423
8513 15:36:27.495520
8514 15:36:27.498222 TX Vref Scan disable
8515 15:36:27.498326 == TX Byte 0 ==
8516 15:36:27.501591 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8517 15:36:27.508973 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8518 15:36:27.509051 == TX Byte 1 ==
8519 15:36:27.511382 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8520 15:36:27.517847 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8521 15:36:27.517925 ==
8522 15:36:27.521884 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 15:36:27.524788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 15:36:27.524867 ==
8525 15:36:27.537895
8526 15:36:27.541394 TX Vref early break, caculate TX vref
8527 15:36:27.544271 TX Vref=16, minBit 0, minWin=21, winSum=373
8528 15:36:27.547932 TX Vref=18, minBit 5, minWin=21, winSum=380
8529 15:36:27.551155 TX Vref=20, minBit 0, minWin=23, winSum=390
8530 15:36:27.553855 TX Vref=22, minBit 0, minWin=23, winSum=396
8531 15:36:27.557441 TX Vref=24, minBit 0, minWin=24, winSum=411
8532 15:36:27.564204 TX Vref=26, minBit 0, minWin=24, winSum=417
8533 15:36:27.567228 TX Vref=28, minBit 5, minWin=24, winSum=419
8534 15:36:27.570762 TX Vref=30, minBit 0, minWin=24, winSum=408
8535 15:36:27.573967 TX Vref=32, minBit 6, minWin=23, winSum=404
8536 15:36:27.576966 TX Vref=34, minBit 6, minWin=22, winSum=390
8537 15:36:27.584238 [TxChooseVref] Worse bit 5, Min win 24, Win sum 419, Final Vref 28
8538 15:36:27.584319
8539 15:36:27.587085 Final TX Range 0 Vref 28
8540 15:36:27.587166
8541 15:36:27.587230 ==
8542 15:36:27.590631 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 15:36:27.593570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 15:36:27.593650 ==
8545 15:36:27.593715
8546 15:36:27.593774
8547 15:36:27.596998 TX Vref Scan disable
8548 15:36:27.603640 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8549 15:36:27.603723 == TX Byte 0 ==
8550 15:36:27.607119 u2DelayCellOfst[0]=22 cells (6 PI)
8551 15:36:27.610559 u2DelayCellOfst[1]=14 cells (4 PI)
8552 15:36:27.613453 u2DelayCellOfst[2]=0 cells (0 PI)
8553 15:36:27.617012 u2DelayCellOfst[3]=7 cells (2 PI)
8554 15:36:27.620153 u2DelayCellOfst[4]=11 cells (3 PI)
8555 15:36:27.623421 u2DelayCellOfst[5]=22 cells (6 PI)
8556 15:36:27.626738 u2DelayCellOfst[6]=22 cells (6 PI)
8557 15:36:27.630253 u2DelayCellOfst[7]=7 cells (2 PI)
8558 15:36:27.633273 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8559 15:36:27.636478 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8560 15:36:27.640097 == TX Byte 1 ==
8561 15:36:27.643163 u2DelayCellOfst[8]=0 cells (0 PI)
8562 15:36:27.646939 u2DelayCellOfst[9]=3 cells (1 PI)
8563 15:36:27.647037 u2DelayCellOfst[10]=11 cells (3 PI)
8564 15:36:27.649998 u2DelayCellOfst[11]=7 cells (2 PI)
8565 15:36:27.653278 u2DelayCellOfst[12]=14 cells (4 PI)
8566 15:36:27.656498 u2DelayCellOfst[13]=18 cells (5 PI)
8567 15:36:27.660131 u2DelayCellOfst[14]=18 cells (5 PI)
8568 15:36:27.662921 u2DelayCellOfst[15]=18 cells (5 PI)
8569 15:36:27.669720 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8570 15:36:27.673043 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8571 15:36:27.673148 DramC Write-DBI on
8572 15:36:27.673236 ==
8573 15:36:27.676041 Dram Type= 6, Freq= 0, CH_1, rank 0
8574 15:36:27.682545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8575 15:36:27.682674 ==
8576 15:36:27.682762
8577 15:36:27.682838
8578 15:36:27.686352 TX Vref Scan disable
8579 15:36:27.686455 == TX Byte 0 ==
8580 15:36:27.692839 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8581 15:36:27.692917 == TX Byte 1 ==
8582 15:36:27.695992 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8583 15:36:27.699549 DramC Write-DBI off
8584 15:36:27.699657
8585 15:36:27.699757 [DATLAT]
8586 15:36:27.702352 Freq=1600, CH1 RK0
8587 15:36:27.702459
8588 15:36:27.702557 DATLAT Default: 0xf
8589 15:36:27.705827 0, 0xFFFF, sum = 0
8590 15:36:27.705907 1, 0xFFFF, sum = 0
8591 15:36:27.708870 2, 0xFFFF, sum = 0
8592 15:36:27.708949 3, 0xFFFF, sum = 0
8593 15:36:27.712231 4, 0xFFFF, sum = 0
8594 15:36:27.712308 5, 0xFFFF, sum = 0
8595 15:36:27.715888 6, 0xFFFF, sum = 0
8596 15:36:27.715965 7, 0xFFFF, sum = 0
8597 15:36:27.719292 8, 0xFFFF, sum = 0
8598 15:36:27.719368 9, 0xFFFF, sum = 0
8599 15:36:27.722257 10, 0xFFFF, sum = 0
8600 15:36:27.725314 11, 0xFFFF, sum = 0
8601 15:36:27.725394 12, 0xFFFF, sum = 0
8602 15:36:27.729072 13, 0xFFFF, sum = 0
8603 15:36:27.729153 14, 0x0, sum = 1
8604 15:36:27.732406 15, 0x0, sum = 2
8605 15:36:27.732488 16, 0x0, sum = 3
8606 15:36:27.735276 17, 0x0, sum = 4
8607 15:36:27.735352 best_step = 15
8608 15:36:27.735432
8609 15:36:27.735512 ==
8610 15:36:27.738563 Dram Type= 6, Freq= 0, CH_1, rank 0
8611 15:36:27.742055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8612 15:36:27.742155 ==
8613 15:36:27.745655 RX Vref Scan: 1
8614 15:36:27.745730
8615 15:36:27.749088 Set Vref Range= 24 -> 127
8616 15:36:27.749163
8617 15:36:27.749248 RX Vref 24 -> 127, step: 1
8618 15:36:27.749323
8619 15:36:27.752053 RX Delay 11 -> 252, step: 4
8620 15:36:27.752152
8621 15:36:27.755428 Set Vref, RX VrefLevel [Byte0]: 24
8622 15:36:27.758918 [Byte1]: 24
8623 15:36:27.762356
8624 15:36:27.762430 Set Vref, RX VrefLevel [Byte0]: 25
8625 15:36:27.765911 [Byte1]: 25
8626 15:36:27.769961
8627 15:36:27.770035 Set Vref, RX VrefLevel [Byte0]: 26
8628 15:36:27.776377 [Byte1]: 26
8629 15:36:27.776462
8630 15:36:27.779248 Set Vref, RX VrefLevel [Byte0]: 27
8631 15:36:27.782934 [Byte1]: 27
8632 15:36:27.783040
8633 15:36:27.785861 Set Vref, RX VrefLevel [Byte0]: 28
8634 15:36:27.789687 [Byte1]: 28
8635 15:36:27.792497
8636 15:36:27.792577 Set Vref, RX VrefLevel [Byte0]: 29
8637 15:36:27.796097 [Byte1]: 29
8638 15:36:27.800205
8639 15:36:27.800284 Set Vref, RX VrefLevel [Byte0]: 30
8640 15:36:27.804091 [Byte1]: 30
8641 15:36:27.808183
8642 15:36:27.808261 Set Vref, RX VrefLevel [Byte0]: 31
8643 15:36:27.811419 [Byte1]: 31
8644 15:36:27.815771
8645 15:36:27.815847 Set Vref, RX VrefLevel [Byte0]: 32
8646 15:36:27.818530 [Byte1]: 32
8647 15:36:27.823241
8648 15:36:27.823320 Set Vref, RX VrefLevel [Byte0]: 33
8649 15:36:27.826326 [Byte1]: 33
8650 15:36:27.831119
8651 15:36:27.831200 Set Vref, RX VrefLevel [Byte0]: 34
8652 15:36:27.834060 [Byte1]: 34
8653 15:36:27.838254
8654 15:36:27.838330 Set Vref, RX VrefLevel [Byte0]: 35
8655 15:36:27.841458 [Byte1]: 35
8656 15:36:27.845901
8657 15:36:27.845976 Set Vref, RX VrefLevel [Byte0]: 36
8658 15:36:27.849356 [Byte1]: 36
8659 15:36:27.853797
8660 15:36:27.853876 Set Vref, RX VrefLevel [Byte0]: 37
8661 15:36:27.856650 [Byte1]: 37
8662 15:36:27.861047
8663 15:36:27.861123 Set Vref, RX VrefLevel [Byte0]: 38
8664 15:36:27.864543 [Byte1]: 38
8665 15:36:27.868704
8666 15:36:27.868783 Set Vref, RX VrefLevel [Byte0]: 39
8667 15:36:27.871970 [Byte1]: 39
8668 15:36:27.876866
8669 15:36:27.876948 Set Vref, RX VrefLevel [Byte0]: 40
8670 15:36:27.879422 [Byte1]: 40
8671 15:36:27.883917
8672 15:36:27.883997 Set Vref, RX VrefLevel [Byte0]: 41
8673 15:36:27.887153 [Byte1]: 41
8674 15:36:27.891717
8675 15:36:27.891793 Set Vref, RX VrefLevel [Byte0]: 42
8676 15:36:27.895472 [Byte1]: 42
8677 15:36:27.899045
8678 15:36:27.899146 Set Vref, RX VrefLevel [Byte0]: 43
8679 15:36:27.902492 [Byte1]: 43
8680 15:36:27.906722
8681 15:36:27.906804 Set Vref, RX VrefLevel [Byte0]: 44
8682 15:36:27.910088 [Byte1]: 44
8683 15:36:27.914522
8684 15:36:27.914660 Set Vref, RX VrefLevel [Byte0]: 45
8685 15:36:27.918032 [Byte1]: 45
8686 15:36:27.922080
8687 15:36:27.922155 Set Vref, RX VrefLevel [Byte0]: 46
8688 15:36:27.925206 [Byte1]: 46
8689 15:36:27.929403
8690 15:36:27.929489 Set Vref, RX VrefLevel [Byte0]: 47
8691 15:36:27.932861 [Byte1]: 47
8692 15:36:27.937507
8693 15:36:27.937587 Set Vref, RX VrefLevel [Byte0]: 48
8694 15:36:27.940348 [Byte1]: 48
8695 15:36:27.944884
8696 15:36:27.944967 Set Vref, RX VrefLevel [Byte0]: 49
8697 15:36:27.948254 [Byte1]: 49
8698 15:36:27.952417
8699 15:36:27.952496 Set Vref, RX VrefLevel [Byte0]: 50
8700 15:36:27.955594 [Byte1]: 50
8701 15:36:27.959876
8702 15:36:27.959995 Set Vref, RX VrefLevel [Byte0]: 51
8703 15:36:27.963613 [Byte1]: 51
8704 15:36:27.967464
8705 15:36:27.967538 Set Vref, RX VrefLevel [Byte0]: 52
8706 15:36:27.974143 [Byte1]: 52
8707 15:36:27.974217
8708 15:36:27.977675 Set Vref, RX VrefLevel [Byte0]: 53
8709 15:36:27.980616 [Byte1]: 53
8710 15:36:27.980688
8711 15:36:27.984195 Set Vref, RX VrefLevel [Byte0]: 54
8712 15:36:27.987286 [Byte1]: 54
8713 15:36:27.990873
8714 15:36:27.990947 Set Vref, RX VrefLevel [Byte0]: 55
8715 15:36:27.993977 [Byte1]: 55
8716 15:36:27.998444
8717 15:36:27.998544 Set Vref, RX VrefLevel [Byte0]: 56
8718 15:36:28.001300 [Byte1]: 56
8719 15:36:28.005892
8720 15:36:28.005996 Set Vref, RX VrefLevel [Byte0]: 57
8721 15:36:28.009012 [Byte1]: 57
8722 15:36:28.013242
8723 15:36:28.013318 Set Vref, RX VrefLevel [Byte0]: 58
8724 15:36:28.016746 [Byte1]: 58
8725 15:36:28.021316
8726 15:36:28.021392 Set Vref, RX VrefLevel [Byte0]: 59
8727 15:36:28.024171 [Byte1]: 59
8728 15:36:28.028700
8729 15:36:28.028798 Set Vref, RX VrefLevel [Byte0]: 60
8730 15:36:28.031678 [Byte1]: 60
8731 15:36:28.036247
8732 15:36:28.036317 Set Vref, RX VrefLevel [Byte0]: 61
8733 15:36:28.039421 [Byte1]: 61
8734 15:36:28.043971
8735 15:36:28.044042 Set Vref, RX VrefLevel [Byte0]: 62
8736 15:36:28.047238 [Byte1]: 62
8737 15:36:28.051224
8738 15:36:28.051295 Set Vref, RX VrefLevel [Byte0]: 63
8739 15:36:28.054631 [Byte1]: 63
8740 15:36:28.059100
8741 15:36:28.059171 Set Vref, RX VrefLevel [Byte0]: 64
8742 15:36:28.062200 [Byte1]: 64
8743 15:36:28.066536
8744 15:36:28.066653 Set Vref, RX VrefLevel [Byte0]: 65
8745 15:36:28.072733 [Byte1]: 65
8746 15:36:28.072811
8747 15:36:28.075954 Set Vref, RX VrefLevel [Byte0]: 66
8748 15:36:28.080176 [Byte1]: 66
8749 15:36:28.080254
8750 15:36:28.082841 Set Vref, RX VrefLevel [Byte0]: 67
8751 15:36:28.086044 [Byte1]: 67
8752 15:36:28.089839
8753 15:36:28.089919 Set Vref, RX VrefLevel [Byte0]: 68
8754 15:36:28.092708 [Byte1]: 68
8755 15:36:28.097372
8756 15:36:28.097482 Set Vref, RX VrefLevel [Byte0]: 69
8757 15:36:28.100292 [Byte1]: 69
8758 15:36:28.104788
8759 15:36:28.104863 Set Vref, RX VrefLevel [Byte0]: 70
8760 15:36:28.107959 [Byte1]: 70
8761 15:36:28.112201
8762 15:36:28.112278 Set Vref, RX VrefLevel [Byte0]: 71
8763 15:36:28.115447 [Byte1]: 71
8764 15:36:28.119899
8765 15:36:28.119976 Set Vref, RX VrefLevel [Byte0]: 72
8766 15:36:28.123254 [Byte1]: 72
8767 15:36:28.127377
8768 15:36:28.127480 Final RX Vref Byte 0 = 52 to rank0
8769 15:36:28.130849 Final RX Vref Byte 1 = 61 to rank0
8770 15:36:28.134740 Final RX Vref Byte 0 = 52 to rank1
8771 15:36:28.137545 Final RX Vref Byte 1 = 61 to rank1==
8772 15:36:28.140524 Dram Type= 6, Freq= 0, CH_1, rank 0
8773 15:36:28.147721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8774 15:36:28.147796 ==
8775 15:36:28.147859 DQS Delay:
8776 15:36:28.150572 DQS0 = 0, DQS1 = 0
8777 15:36:28.150658 DQM Delay:
8778 15:36:28.150721 DQM0 = 133, DQM1 = 128
8779 15:36:28.153994 DQ Delay:
8780 15:36:28.157192 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8781 15:36:28.160807 DQ4 =132, DQ5 =146, DQ6 =144, DQ7 =128
8782 15:36:28.163719 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8783 15:36:28.167222 DQ12 =136, DQ13 =136, DQ14 =138, DQ15 =136
8784 15:36:28.167297
8785 15:36:28.167359
8786 15:36:28.167422
8787 15:36:28.170356 [DramC_TX_OE_Calibration] TA2
8788 15:36:28.173684 Original DQ_B0 (3 6) =30, OEN = 27
8789 15:36:28.177412 Original DQ_B1 (3 6) =30, OEN = 27
8790 15:36:28.179934 24, 0x0, End_B0=24 End_B1=24
8791 15:36:28.183302 25, 0x0, End_B0=25 End_B1=25
8792 15:36:28.183405 26, 0x0, End_B0=26 End_B1=26
8793 15:36:28.186550 27, 0x0, End_B0=27 End_B1=27
8794 15:36:28.189924 28, 0x0, End_B0=28 End_B1=28
8795 15:36:28.193248 29, 0x0, End_B0=29 End_B1=29
8796 15:36:28.193330 30, 0x0, End_B0=30 End_B1=30
8797 15:36:28.196402 31, 0x4141, End_B0=30 End_B1=30
8798 15:36:28.200189 Byte0 end_step=30 best_step=27
8799 15:36:28.202970 Byte1 end_step=30 best_step=27
8800 15:36:28.206739 Byte0 TX OE(2T, 0.5T) = (3, 3)
8801 15:36:28.209846 Byte1 TX OE(2T, 0.5T) = (3, 3)
8802 15:36:28.209927
8803 15:36:28.209991
8804 15:36:28.216465 [DQSOSCAuto] RK0, (LSB)MR18= 0x190e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8805 15:36:28.219656 CH1 RK0: MR19=303, MR18=190E
8806 15:36:28.225978 CH1_RK0: MR19=0x303, MR18=0x190E, DQSOSC=397, MR23=63, INC=23, DEC=15
8807 15:36:28.226060
8808 15:36:28.229436 ----->DramcWriteLeveling(PI) begin...
8809 15:36:28.229523 ==
8810 15:36:28.233325 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 15:36:28.236174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 15:36:28.236255 ==
8813 15:36:28.239314 Write leveling (Byte 0): 25 => 25
8814 15:36:28.242533 Write leveling (Byte 1): 27 => 27
8815 15:36:28.245869 DramcWriteLeveling(PI) end<-----
8816 15:36:28.245950
8817 15:36:28.246013 ==
8818 15:36:28.249142 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 15:36:28.256289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 15:36:28.256371 ==
8821 15:36:28.256435 [Gating] SW mode calibration
8822 15:36:28.265660 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8823 15:36:28.269204 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8824 15:36:28.272565 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 15:36:28.279043 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 15:36:28.282767 1 4 8 | B1->B0 | 2322 2323 | 1 0 | (1 0) (0 0)
8827 15:36:28.285755 1 4 12 | B1->B0 | 3434 2322 | 0 1 | (0 0) (0 0)
8828 15:36:28.292295 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 15:36:28.295582 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 15:36:28.298944 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 15:36:28.305494 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 15:36:28.308800 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 15:36:28.311901 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 15:36:28.318763 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8835 15:36:28.322175 1 5 12 | B1->B0 | 2525 3434 | 1 1 | (1 0) (1 0)
8836 15:36:28.325409 1 5 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8837 15:36:28.331796 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 15:36:28.334988 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 15:36:28.338322 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 15:36:28.344892 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 15:36:28.348304 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 15:36:28.351322 1 6 8 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8843 15:36:28.358146 1 6 12 | B1->B0 | 4646 2f2f | 0 0 | (0 0) (0 0)
8844 15:36:28.361901 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 15:36:28.364671 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 15:36:28.371456 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 15:36:28.374546 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 15:36:28.377795 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 15:36:28.384352 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 15:36:28.387672 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8851 15:36:28.394242 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8852 15:36:28.397554 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 15:36:28.400999 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 15:36:28.407619 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 15:36:28.411039 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 15:36:28.414112 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 15:36:28.420754 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 15:36:28.423966 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 15:36:28.427445 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 15:36:28.433881 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 15:36:28.437205 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 15:36:28.440629 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 15:36:28.447133 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 15:36:28.450340 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 15:36:28.453972 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 15:36:28.460073 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8867 15:36:28.463525 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8868 15:36:28.466772 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 15:36:28.470200 Total UI for P1: 0, mck2ui 16
8870 15:36:28.473913 best dqsien dly found for B0: ( 1, 9, 10)
8871 15:36:28.477361 Total UI for P1: 0, mck2ui 16
8872 15:36:28.480038 best dqsien dly found for B1: ( 1, 9, 10)
8873 15:36:28.483553 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8874 15:36:28.487059 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8875 15:36:28.487140
8876 15:36:28.490192 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8877 15:36:28.496852 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8878 15:36:28.496934 [Gating] SW calibration Done
8879 15:36:28.496999 ==
8880 15:36:28.499885 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 15:36:28.507066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 15:36:28.507148 ==
8883 15:36:28.507212 RX Vref Scan: 0
8884 15:36:28.507271
8885 15:36:28.509826 RX Vref 0 -> 0, step: 1
8886 15:36:28.509907
8887 15:36:28.512994 RX Delay 0 -> 252, step: 8
8888 15:36:28.516219 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8889 15:36:28.519495 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8890 15:36:28.522981 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8891 15:36:28.529893 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8892 15:36:28.532873 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8893 15:36:28.536134 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8894 15:36:28.539190 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8895 15:36:28.542721 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8896 15:36:28.549070 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8897 15:36:28.552429 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8898 15:36:28.555901 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8899 15:36:28.558945 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8900 15:36:28.565749 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8901 15:36:28.569290 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8902 15:36:28.572343 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8903 15:36:28.575495 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8904 15:36:28.575576 ==
8905 15:36:28.579159 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 15:36:28.585650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 15:36:28.585732 ==
8908 15:36:28.585796 DQS Delay:
8909 15:36:28.585857 DQS0 = 0, DQS1 = 0
8910 15:36:28.588931 DQM Delay:
8911 15:36:28.589012 DQM0 = 136, DQM1 = 129
8912 15:36:28.592297 DQ Delay:
8913 15:36:28.595528 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8914 15:36:28.598883 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8915 15:36:28.602316 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8916 15:36:28.605186 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8917 15:36:28.605267
8918 15:36:28.605331
8919 15:36:28.605390 ==
8920 15:36:28.608451 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 15:36:28.612480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 15:36:28.615974 ==
8923 15:36:28.616055
8924 15:36:28.616118
8925 15:36:28.616178 TX Vref Scan disable
8926 15:36:28.618435 == TX Byte 0 ==
8927 15:36:28.621895 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8928 15:36:28.625117 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8929 15:36:28.628522 == TX Byte 1 ==
8930 15:36:28.631691 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8931 15:36:28.635631 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8932 15:36:28.638452 ==
8933 15:36:28.641615 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 15:36:28.644768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 15:36:28.644850 ==
8936 15:36:28.657096
8937 15:36:28.660757 TX Vref early break, caculate TX vref
8938 15:36:28.663580 TX Vref=16, minBit 1, minWin=22, winSum=387
8939 15:36:28.667251 TX Vref=18, minBit 0, minWin=24, winSum=395
8940 15:36:28.670321 TX Vref=20, minBit 0, minWin=24, winSum=406
8941 15:36:28.673930 TX Vref=22, minBit 1, minWin=24, winSum=412
8942 15:36:28.676838 TX Vref=24, minBit 1, minWin=25, winSum=420
8943 15:36:28.683437 TX Vref=26, minBit 0, minWin=26, winSum=425
8944 15:36:28.686664 TX Vref=28, minBit 0, minWin=26, winSum=426
8945 15:36:28.689835 TX Vref=30, minBit 0, minWin=25, winSum=420
8946 15:36:28.693051 TX Vref=32, minBit 0, minWin=24, winSum=411
8947 15:36:28.697030 TX Vref=34, minBit 0, minWin=24, winSum=402
8948 15:36:28.703507 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8949 15:36:28.703590
8950 15:36:28.706471 Final TX Range 0 Vref 28
8951 15:36:28.706578
8952 15:36:28.706690 ==
8953 15:36:28.709702 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 15:36:28.713039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 15:36:28.713121 ==
8956 15:36:28.713186
8957 15:36:28.713246
8958 15:36:28.716508 TX Vref Scan disable
8959 15:36:28.722775 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8960 15:36:28.722855 == TX Byte 0 ==
8961 15:36:28.726087 u2DelayCellOfst[0]=22 cells (6 PI)
8962 15:36:28.729554 u2DelayCellOfst[1]=14 cells (4 PI)
8963 15:36:28.733035 u2DelayCellOfst[2]=0 cells (0 PI)
8964 15:36:28.736503 u2DelayCellOfst[3]=7 cells (2 PI)
8965 15:36:28.739336 u2DelayCellOfst[4]=7 cells (2 PI)
8966 15:36:28.742939 u2DelayCellOfst[5]=22 cells (6 PI)
8967 15:36:28.746406 u2DelayCellOfst[6]=22 cells (6 PI)
8968 15:36:28.749456 u2DelayCellOfst[7]=7 cells (2 PI)
8969 15:36:28.752760 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8970 15:36:28.756236 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8971 15:36:28.759456 == TX Byte 1 ==
8972 15:36:28.762860 u2DelayCellOfst[8]=0 cells (0 PI)
8973 15:36:28.765737 u2DelayCellOfst[9]=3 cells (1 PI)
8974 15:36:28.769053 u2DelayCellOfst[10]=11 cells (3 PI)
8975 15:36:28.769135 u2DelayCellOfst[11]=3 cells (1 PI)
8976 15:36:28.772776 u2DelayCellOfst[12]=18 cells (5 PI)
8977 15:36:28.775856 u2DelayCellOfst[13]=18 cells (5 PI)
8978 15:36:28.779045 u2DelayCellOfst[14]=18 cells (5 PI)
8979 15:36:28.782722 u2DelayCellOfst[15]=18 cells (5 PI)
8980 15:36:28.789115 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8981 15:36:28.792334 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8982 15:36:28.792437 DramC Write-DBI on
8983 15:36:28.795572 ==
8984 15:36:28.795653 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 15:36:28.802010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 15:36:28.802119 ==
8987 15:36:28.802211
8988 15:36:28.802303
8989 15:36:28.805516 TX Vref Scan disable
8990 15:36:28.805600 == TX Byte 0 ==
8991 15:36:28.812093 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8992 15:36:28.812174 == TX Byte 1 ==
8993 15:36:28.815281 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8994 15:36:28.818785 DramC Write-DBI off
8995 15:36:28.818866
8996 15:36:28.818929 [DATLAT]
8997 15:36:28.821984 Freq=1600, CH1 RK1
8998 15:36:28.822065
8999 15:36:28.822129 DATLAT Default: 0xf
9000 15:36:28.825080 0, 0xFFFF, sum = 0
9001 15:36:28.825163 1, 0xFFFF, sum = 0
9002 15:36:28.828828 2, 0xFFFF, sum = 0
9003 15:36:28.828910 3, 0xFFFF, sum = 0
9004 15:36:28.831680 4, 0xFFFF, sum = 0
9005 15:36:28.831768 5, 0xFFFF, sum = 0
9006 15:36:28.834977 6, 0xFFFF, sum = 0
9007 15:36:28.835060 7, 0xFFFF, sum = 0
9008 15:36:28.838209 8, 0xFFFF, sum = 0
9009 15:36:28.841618 9, 0xFFFF, sum = 0
9010 15:36:28.841701 10, 0xFFFF, sum = 0
9011 15:36:28.845418 11, 0xFFFF, sum = 0
9012 15:36:28.845499 12, 0xFFFF, sum = 0
9013 15:36:28.848399 13, 0xFFFF, sum = 0
9014 15:36:28.848481 14, 0x0, sum = 1
9015 15:36:28.851740 15, 0x0, sum = 2
9016 15:36:28.851823 16, 0x0, sum = 3
9017 15:36:28.854846 17, 0x0, sum = 4
9018 15:36:28.854928 best_step = 15
9019 15:36:28.854992
9020 15:36:28.855052 ==
9021 15:36:28.858321 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 15:36:28.861545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 15:36:28.861626 ==
9024 15:36:28.864721 RX Vref Scan: 0
9025 15:36:28.864802
9026 15:36:28.867884 RX Vref 0 -> 0, step: 1
9027 15:36:28.867990
9028 15:36:28.868083 RX Delay 11 -> 252, step: 4
9029 15:36:28.875711 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9030 15:36:28.878981 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9031 15:36:28.882242 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9032 15:36:28.885657 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9033 15:36:28.888608 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9034 15:36:28.895072 iDelay=203, Bit 5, Center 142 (91 ~ 194) 104
9035 15:36:28.898353 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9036 15:36:28.901921 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9037 15:36:28.905076 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9038 15:36:28.911634 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9039 15:36:28.914561 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9040 15:36:28.918231 iDelay=203, Bit 11, Center 120 (67 ~ 174) 108
9041 15:36:28.922147 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9042 15:36:28.924690 iDelay=203, Bit 13, Center 134 (83 ~ 186) 104
9043 15:36:28.931234 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9044 15:36:28.934729 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9045 15:36:28.934811 ==
9046 15:36:28.938534 Dram Type= 6, Freq= 0, CH_1, rank 1
9047 15:36:28.941093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9048 15:36:28.941174 ==
9049 15:36:28.944290 DQS Delay:
9050 15:36:28.944371 DQS0 = 0, DQS1 = 0
9051 15:36:28.944435 DQM Delay:
9052 15:36:28.947966 DQM0 = 133, DQM1 = 127
9053 15:36:28.948047 DQ Delay:
9054 15:36:28.950925 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9055 15:36:28.954485 DQ4 =132, DQ5 =142, DQ6 =146, DQ7 =130
9056 15:36:28.961111 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =120
9057 15:36:28.964081 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9058 15:36:28.964161
9059 15:36:28.964226
9060 15:36:28.964285
9061 15:36:28.968125 [DramC_TX_OE_Calibration] TA2
9062 15:36:28.970732 Original DQ_B0 (3 6) =30, OEN = 27
9063 15:36:28.974343 Original DQ_B1 (3 6) =30, OEN = 27
9064 15:36:28.974425 24, 0x0, End_B0=24 End_B1=24
9065 15:36:28.977406 25, 0x0, End_B0=25 End_B1=25
9066 15:36:28.980929 26, 0x0, End_B0=26 End_B1=26
9067 15:36:28.984227 27, 0x0, End_B0=27 End_B1=27
9068 15:36:28.987717 28, 0x0, End_B0=28 End_B1=28
9069 15:36:28.987799 29, 0x0, End_B0=29 End_B1=29
9070 15:36:28.991002 30, 0x0, End_B0=30 End_B1=30
9071 15:36:28.993850 31, 0x4545, End_B0=30 End_B1=30
9072 15:36:28.997328 Byte0 end_step=30 best_step=27
9073 15:36:29.000474 Byte1 end_step=30 best_step=27
9074 15:36:29.004043 Byte0 TX OE(2T, 0.5T) = (3, 3)
9075 15:36:29.004124 Byte1 TX OE(2T, 0.5T) = (3, 3)
9076 15:36:29.004189
9077 15:36:29.004249
9078 15:36:29.013919 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9079 15:36:29.017007 CH1 RK1: MR19=303, MR18=E0B
9080 15:36:29.020576 CH1_RK1: MR19=0x303, MR18=0xE0B, DQSOSC=402, MR23=63, INC=22, DEC=15
9081 15:36:29.023591 [RxdqsGatingPostProcess] freq 1600
9082 15:36:29.030068 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9083 15:36:29.033502 best DQS0 dly(2T, 0.5T) = (1, 1)
9084 15:36:29.036899 best DQS1 dly(2T, 0.5T) = (1, 1)
9085 15:36:29.040544 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9086 15:36:29.043260 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9087 15:36:29.046535 best DQS0 dly(2T, 0.5T) = (1, 1)
9088 15:36:29.050330 best DQS1 dly(2T, 0.5T) = (1, 1)
9089 15:36:29.053412 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9090 15:36:29.056446 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9091 15:36:29.056527 Pre-setting of DQS Precalculation
9092 15:36:29.063144 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9093 15:36:29.069349 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9094 15:36:29.075998 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9095 15:36:29.076081
9096 15:36:29.079597
9097 15:36:29.079678 [Calibration Summary] 3200 Mbps
9098 15:36:29.082728 CH 0, Rank 0
9099 15:36:29.082809 SW Impedance : PASS
9100 15:36:29.085881 DUTY Scan : NO K
9101 15:36:29.089627 ZQ Calibration : PASS
9102 15:36:29.089708 Jitter Meter : NO K
9103 15:36:29.093098 CBT Training : PASS
9104 15:36:29.095869 Write leveling : PASS
9105 15:36:29.095950 RX DQS gating : PASS
9106 15:36:29.099293 RX DQ/DQS(RDDQC) : PASS
9107 15:36:29.102716 TX DQ/DQS : PASS
9108 15:36:29.102798 RX DATLAT : PASS
9109 15:36:29.106316 RX DQ/DQS(Engine): PASS
9110 15:36:29.109253 TX OE : PASS
9111 15:36:29.109333 All Pass.
9112 15:36:29.109397
9113 15:36:29.109456 CH 0, Rank 1
9114 15:36:29.112514 SW Impedance : PASS
9115 15:36:29.115705 DUTY Scan : NO K
9116 15:36:29.115786 ZQ Calibration : PASS
9117 15:36:29.118939 Jitter Meter : NO K
9118 15:36:29.122452 CBT Training : PASS
9119 15:36:29.122577 Write leveling : PASS
9120 15:36:29.125591 RX DQS gating : PASS
9121 15:36:29.125681 RX DQ/DQS(RDDQC) : PASS
9122 15:36:29.129280 TX DQ/DQS : PASS
9123 15:36:29.132200 RX DATLAT : PASS
9124 15:36:29.132280 RX DQ/DQS(Engine): PASS
9125 15:36:29.135774 TX OE : PASS
9126 15:36:29.135855 All Pass.
9127 15:36:29.135919
9128 15:36:29.138658 CH 1, Rank 0
9129 15:36:29.138738 SW Impedance : PASS
9130 15:36:29.141877 DUTY Scan : NO K
9131 15:36:29.145745 ZQ Calibration : PASS
9132 15:36:29.145825 Jitter Meter : NO K
9133 15:36:29.148617 CBT Training : PASS
9134 15:36:29.152294 Write leveling : PASS
9135 15:36:29.152375 RX DQS gating : PASS
9136 15:36:29.155486 RX DQ/DQS(RDDQC) : PASS
9137 15:36:29.158506 TX DQ/DQS : PASS
9138 15:36:29.158649 RX DATLAT : PASS
9139 15:36:29.162062 RX DQ/DQS(Engine): PASS
9140 15:36:29.165318 TX OE : PASS
9141 15:36:29.165399 All Pass.
9142 15:36:29.165463
9143 15:36:29.165522 CH 1, Rank 1
9144 15:36:29.169054 SW Impedance : PASS
9145 15:36:29.172028 DUTY Scan : NO K
9146 15:36:29.172109 ZQ Calibration : PASS
9147 15:36:29.175352 Jitter Meter : NO K
9148 15:36:29.178569 CBT Training : PASS
9149 15:36:29.178712 Write leveling : PASS
9150 15:36:29.182050 RX DQS gating : PASS
9151 15:36:29.185305 RX DQ/DQS(RDDQC) : PASS
9152 15:36:29.185386 TX DQ/DQS : PASS
9153 15:36:29.188215 RX DATLAT : PASS
9154 15:36:29.191542 RX DQ/DQS(Engine): PASS
9155 15:36:29.191623 TX OE : PASS
9156 15:36:29.191689 All Pass.
9157 15:36:29.194770
9158 15:36:29.194850 DramC Write-DBI on
9159 15:36:29.198242 PER_BANK_REFRESH: Hybrid Mode
9160 15:36:29.198323 TX_TRACKING: ON
9161 15:36:29.208222 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9162 15:36:29.215041 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9163 15:36:29.224560 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9164 15:36:29.228011 [FAST_K] Save calibration result to emmc
9165 15:36:29.231156 sync common calibartion params.
9166 15:36:29.231237 sync cbt_mode0:1, 1:1
9167 15:36:29.234610 dram_init: ddr_geometry: 2
9168 15:36:29.238127 dram_init: ddr_geometry: 2
9169 15:36:29.238208 dram_init: ddr_geometry: 2
9170 15:36:29.241034 0:dram_rank_size:100000000
9171 15:36:29.244243 1:dram_rank_size:100000000
9172 15:36:29.250850 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9173 15:36:29.250932 DFS_SHUFFLE_HW_MODE: ON
9174 15:36:29.254071 dramc_set_vcore_voltage set vcore to 725000
9175 15:36:29.257930 Read voltage for 1600, 0
9176 15:36:29.258011 Vio18 = 0
9177 15:36:29.261091 Vcore = 725000
9178 15:36:29.261171 Vdram = 0
9179 15:36:29.261236 Vddq = 0
9180 15:36:29.264278 Vmddr = 0
9181 15:36:29.264358 switch to 3200 Mbps bootup
9182 15:36:29.267850 [DramcRunTimeConfig]
9183 15:36:29.267930 PHYPLL
9184 15:36:29.270950 DPM_CONTROL_AFTERK: ON
9185 15:36:29.271032 PER_BANK_REFRESH: ON
9186 15:36:29.274020 REFRESH_OVERHEAD_REDUCTION: ON
9187 15:36:29.277582 CMD_PICG_NEW_MODE: OFF
9188 15:36:29.277701 XRTWTW_NEW_MODE: ON
9189 15:36:29.281160 XRTRTR_NEW_MODE: ON
9190 15:36:29.281236 TX_TRACKING: ON
9191 15:36:29.284171 RDSEL_TRACKING: OFF
9192 15:36:29.287587 DQS Precalculation for DVFS: ON
9193 15:36:29.287662 RX_TRACKING: OFF
9194 15:36:29.290500 HW_GATING DBG: ON
9195 15:36:29.290633 ZQCS_ENABLE_LP4: ON
9196 15:36:29.294140 RX_PICG_NEW_MODE: ON
9197 15:36:29.294247 TX_PICG_NEW_MODE: ON
9198 15:36:29.297336 ENABLE_RX_DCM_DPHY: ON
9199 15:36:29.300880 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9200 15:36:29.303850 DUMMY_READ_FOR_TRACKING: OFF
9201 15:36:29.303931 !!! SPM_CONTROL_AFTERK: OFF
9202 15:36:29.307321 !!! SPM could not control APHY
9203 15:36:29.310462 IMPEDANCE_TRACKING: ON
9204 15:36:29.310545 TEMP_SENSOR: ON
9205 15:36:29.314397 HW_SAVE_FOR_SR: OFF
9206 15:36:29.317106 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9207 15:36:29.320611 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9208 15:36:29.323932 Read ODT Tracking: ON
9209 15:36:29.324013 Refresh Rate DeBounce: ON
9210 15:36:29.326900 DFS_NO_QUEUE_FLUSH: ON
9211 15:36:29.330536 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9212 15:36:29.334160 ENABLE_DFS_RUNTIME_MRW: OFF
9213 15:36:29.334240 DDR_RESERVE_NEW_MODE: ON
9214 15:36:29.337860 MR_CBT_SWITCH_FREQ: ON
9215 15:36:29.340356 =========================
9216 15:36:29.357956 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9217 15:36:29.361060 dram_init: ddr_geometry: 2
9218 15:36:29.379546 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9219 15:36:29.382557 dram_init: dram init end (result: 0)
9220 15:36:29.389076 DRAM-K: Full calibration passed in 24634 msecs
9221 15:36:29.392759 MRC: failed to locate region type 0.
9222 15:36:29.392840 DRAM rank0 size:0x100000000,
9223 15:36:29.396101 DRAM rank1 size=0x100000000
9224 15:36:29.405590 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9225 15:36:29.412039 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9226 15:36:29.418900 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9227 15:36:29.429257 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9228 15:36:29.429372 DRAM rank0 size:0x100000000,
9229 15:36:29.432181 DRAM rank1 size=0x100000000
9230 15:36:29.432306 CBMEM:
9231 15:36:29.435617 IMD: root @ 0xfffff000 254 entries.
9232 15:36:29.439264 IMD: root @ 0xffffec00 62 entries.
9233 15:36:29.442245 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9234 15:36:29.448785 WARNING: RO_VPD is uninitialized or empty.
9235 15:36:29.451642 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9236 15:36:29.462337 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9237 15:36:29.472174 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9238 15:36:29.483612 BS: romstage times (exec / console): total (unknown) / 24122 ms
9239 15:36:29.483699
9240 15:36:29.483766
9241 15:36:29.493947 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9242 15:36:29.496742 ARM64: Exception handlers installed.
9243 15:36:29.500247 ARM64: Testing exception
9244 15:36:29.503794 ARM64: Done test exception
9245 15:36:29.503877 Enumerating buses...
9246 15:36:29.506660 Show all devs... Before device enumeration.
9247 15:36:29.509805 Root Device: enabled 1
9248 15:36:29.513416 CPU_CLUSTER: 0: enabled 1
9249 15:36:29.513498 CPU: 00: enabled 1
9250 15:36:29.516751 Compare with tree...
9251 15:36:29.516832 Root Device: enabled 1
9252 15:36:29.519837 CPU_CLUSTER: 0: enabled 1
9253 15:36:29.523636 CPU: 00: enabled 1
9254 15:36:29.523717 Root Device scanning...
9255 15:36:29.526412 scan_static_bus for Root Device
9256 15:36:29.529521 CPU_CLUSTER: 0 enabled
9257 15:36:29.532933 scan_static_bus for Root Device done
9258 15:36:29.535960 scan_bus: bus Root Device finished in 8 msecs
9259 15:36:29.536042 done
9260 15:36:29.542865 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9261 15:36:29.546028 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9262 15:36:29.553222 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9263 15:36:29.556034 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9264 15:36:29.559630 Allocating resources...
9265 15:36:29.562811 Reading resources...
9266 15:36:29.566035 Root Device read_resources bus 0 link: 0
9267 15:36:29.569260 DRAM rank0 size:0x100000000,
9268 15:36:29.569341 DRAM rank1 size=0x100000000
9269 15:36:29.572600 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9270 15:36:29.575850 CPU: 00 missing read_resources
9271 15:36:29.582427 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9272 15:36:29.585940 Root Device read_resources bus 0 link: 0 done
9273 15:36:29.586022 Done reading resources.
9274 15:36:29.592852 Show resources in subtree (Root Device)...After reading.
9275 15:36:29.596293 Root Device child on link 0 CPU_CLUSTER: 0
9276 15:36:29.598859 CPU_CLUSTER: 0 child on link 0 CPU: 00
9277 15:36:29.609234 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9278 15:36:29.609319 CPU: 00
9279 15:36:29.612279 Root Device assign_resources, bus 0 link: 0
9280 15:36:29.615826 CPU_CLUSTER: 0 missing set_resources
9281 15:36:29.622165 Root Device assign_resources, bus 0 link: 0 done
9282 15:36:29.622247 Done setting resources.
9283 15:36:29.629199 Show resources in subtree (Root Device)...After assigning values.
9284 15:36:29.632362 Root Device child on link 0 CPU_CLUSTER: 0
9285 15:36:29.635246 CPU_CLUSTER: 0 child on link 0 CPU: 00
9286 15:36:29.645132 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9287 15:36:29.645218 CPU: 00
9288 15:36:29.648884 Done allocating resources.
9289 15:36:29.655547 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9290 15:36:29.655630 Enabling resources...
9291 15:36:29.658357 done.
9292 15:36:29.661924 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9293 15:36:29.665113 Initializing devices...
9294 15:36:29.665195 Root Device init
9295 15:36:29.668327 init hardware done!
9296 15:36:29.668409 0x00000018: ctrlr->caps
9297 15:36:29.671529 52.000 MHz: ctrlr->f_max
9298 15:36:29.674834 0.400 MHz: ctrlr->f_min
9299 15:36:29.674917 0x40ff8080: ctrlr->voltages
9300 15:36:29.677941 sclk: 390625
9301 15:36:29.678022 Bus Width = 1
9302 15:36:29.681462 sclk: 390625
9303 15:36:29.681543 Bus Width = 1
9304 15:36:29.684670 Early init status = 3
9305 15:36:29.687809 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9306 15:36:29.691271 in-header: 03 fc 00 00 01 00 00 00
9307 15:36:29.694967 in-data: 00
9308 15:36:29.698062 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9309 15:36:29.703167 in-header: 03 fd 00 00 00 00 00 00
9310 15:36:29.706419 in-data:
9311 15:36:29.709681 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9312 15:36:29.714192 in-header: 03 fc 00 00 01 00 00 00
9313 15:36:29.716670 in-data: 00
9314 15:36:29.720432 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9315 15:36:29.724890 in-header: 03 fd 00 00 00 00 00 00
9316 15:36:29.727968 in-data:
9317 15:36:29.731393 [SSUSB] Setting up USB HOST controller...
9318 15:36:29.734185 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9319 15:36:29.737808 [SSUSB] phy power-on done.
9320 15:36:29.740864 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9321 15:36:29.747581 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9322 15:36:29.751374 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9323 15:36:29.757679 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9324 15:36:29.763825 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9325 15:36:29.770845 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9326 15:36:29.777599 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9327 15:36:29.783751 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9328 15:36:29.787019 SPM: binary array size = 0x9dc
9329 15:36:29.790857 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9330 15:36:29.797334 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9331 15:36:29.803570 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9332 15:36:29.810273 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9333 15:36:29.813840 configure_display: Starting display init
9334 15:36:29.847982 anx7625_power_on_init: Init interface.
9335 15:36:29.851003 anx7625_disable_pd_protocol: Disabled PD feature.
9336 15:36:29.854436 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9337 15:36:29.882259 anx7625_start_dp_work: Secure OCM version=00
9338 15:36:29.885694 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9339 15:36:29.900398 sp_tx_get_edid_block: EDID Block = 1
9340 15:36:30.003159 Extracted contents:
9341 15:36:30.006503 header: 00 ff ff ff ff ff ff 00
9342 15:36:30.009581 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9343 15:36:30.012945 version: 01 04
9344 15:36:30.015998 basic params: 95 1f 11 78 0a
9345 15:36:30.019502 chroma info: 76 90 94 55 54 90 27 21 50 54
9346 15:36:30.022447 established: 00 00 00
9347 15:36:30.029286 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9348 15:36:30.036167 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9349 15:36:30.038925 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9350 15:36:30.045462 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9351 15:36:30.052420 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9352 15:36:30.055606 extensions: 00
9353 15:36:30.055688 checksum: fb
9354 15:36:30.055753
9355 15:36:30.062752 Manufacturer: IVO Model 57d Serial Number 0
9356 15:36:30.062836 Made week 0 of 2020
9357 15:36:30.065902 EDID version: 1.4
9358 15:36:30.065984 Digital display
9359 15:36:30.068824 6 bits per primary color channel
9360 15:36:30.068908 DisplayPort interface
9361 15:36:30.071870 Maximum image size: 31 cm x 17 cm
9362 15:36:30.075600 Gamma: 220%
9363 15:36:30.075682 Check DPMS levels
9364 15:36:30.082044 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9365 15:36:30.085606 First detailed timing is preferred timing
9366 15:36:30.085691 Established timings supported:
9367 15:36:30.088551 Standard timings supported:
9368 15:36:30.091662 Detailed timings
9369 15:36:30.095054 Hex of detail: 383680a07038204018303c0035ae10000019
9370 15:36:30.101571 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9371 15:36:30.104974 0780 0798 07c8 0820 hborder 0
9372 15:36:30.108521 0438 043b 0447 0458 vborder 0
9373 15:36:30.111832 -hsync -vsync
9374 15:36:30.111914 Did detailed timing
9375 15:36:30.118447 Hex of detail: 000000000000000000000000000000000000
9376 15:36:30.121585 Manufacturer-specified data, tag 0
9377 15:36:30.124709 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9378 15:36:30.128115 ASCII string: InfoVision
9379 15:36:30.131338 Hex of detail: 000000fe00523134304e574635205248200a
9380 15:36:30.134708 ASCII string: R140NWF5 RH
9381 15:36:30.134791 Checksum
9382 15:36:30.138102 Checksum: 0xfb (valid)
9383 15:36:30.141495 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9384 15:36:30.144655 DSI data_rate: 832800000 bps
9385 15:36:30.151333 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9386 15:36:30.154423 anx7625_parse_edid: pixelclock(138800).
9387 15:36:30.157842 hactive(1920), hsync(48), hfp(24), hbp(88)
9388 15:36:30.161116 vactive(1080), vsync(12), vfp(3), vbp(17)
9389 15:36:30.165011 anx7625_dsi_config: config dsi.
9390 15:36:30.170958 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9391 15:36:30.184782 anx7625_dsi_config: success to config DSI
9392 15:36:30.188035 anx7625_dp_start: MIPI phy setup OK.
9393 15:36:30.191440 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9394 15:36:30.194514 mtk_ddp_mode_set invalid vrefresh 60
9395 15:36:30.198168 main_disp_path_setup
9396 15:36:30.198250 ovl_layer_smi_id_en
9397 15:36:30.201361 ovl_layer_smi_id_en
9398 15:36:30.201442 ccorr_config
9399 15:36:30.201507 aal_config
9400 15:36:30.204668 gamma_config
9401 15:36:30.204749 postmask_config
9402 15:36:30.207686 dither_config
9403 15:36:30.211624 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9404 15:36:30.217834 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9405 15:36:30.220856 Root Device init finished in 552 msecs
9406 15:36:30.224634 CPU_CLUSTER: 0 init
9407 15:36:30.231217 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9408 15:36:30.237789 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9409 15:36:30.237871 APU_MBOX 0x190000b0 = 0x10001
9410 15:36:30.240690 APU_MBOX 0x190001b0 = 0x10001
9411 15:36:30.244094 APU_MBOX 0x190005b0 = 0x10001
9412 15:36:30.247540 APU_MBOX 0x190006b0 = 0x10001
9413 15:36:30.253875 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9414 15:36:30.264066 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9415 15:36:30.276109 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9416 15:36:30.282603 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9417 15:36:30.294563 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9418 15:36:30.303753 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9419 15:36:30.306724 CPU_CLUSTER: 0 init finished in 81 msecs
9420 15:36:30.310071 Devices initialized
9421 15:36:30.313496 Show all devs... After init.
9422 15:36:30.313577 Root Device: enabled 1
9423 15:36:30.316597 CPU_CLUSTER: 0: enabled 1
9424 15:36:30.320184 CPU: 00: enabled 1
9425 15:36:30.323264 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9426 15:36:30.326729 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9427 15:36:30.330137 ELOG: NV offset 0x57f000 size 0x1000
9428 15:36:30.336779 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9429 15:36:30.343249 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9430 15:36:30.346599 ELOG: Event(17) added with size 13 at 2023-08-22 15:36:30 UTC
9431 15:36:30.353399 out: cmd=0x121: 03 db 21 01 00 00 00 00
9432 15:36:30.356320 in-header: 03 ba 00 00 2c 00 00 00
9433 15:36:30.366151 in-data: a5 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9434 15:36:30.373194 ELOG: Event(A1) added with size 10 at 2023-08-22 15:36:30 UTC
9435 15:36:30.379607 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9436 15:36:30.386436 ELOG: Event(A0) added with size 9 at 2023-08-22 15:36:30 UTC
9437 15:36:30.389388 elog_add_boot_reason: Logged dev mode boot
9438 15:36:30.395951 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9439 15:36:30.396034 Finalize devices...
9440 15:36:30.399349 Devices finalized
9441 15:36:30.402741 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9442 15:36:30.406001 Writing coreboot table at 0xffe64000
9443 15:36:30.409365 0. 000000000010a000-0000000000113fff: RAMSTAGE
9444 15:36:30.415786 1. 0000000040000000-00000000400fffff: RAM
9445 15:36:30.419409 2. 0000000040100000-000000004032afff: RAMSTAGE
9446 15:36:30.422678 3. 000000004032b000-00000000545fffff: RAM
9447 15:36:30.426191 4. 0000000054600000-000000005465ffff: BL31
9448 15:36:30.429151 5. 0000000054660000-00000000ffe63fff: RAM
9449 15:36:30.435697 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9450 15:36:30.438966 7. 0000000100000000-000000023fffffff: RAM
9451 15:36:30.442577 Passing 5 GPIOs to payload:
9452 15:36:30.446061 NAME | PORT | POLARITY | VALUE
9453 15:36:30.452384 EC in RW | 0x000000aa | low | undefined
9454 15:36:30.455723 EC interrupt | 0x00000005 | low | undefined
9455 15:36:30.459097 TPM interrupt | 0x000000ab | high | undefined
9456 15:36:30.465444 SD card detect | 0x00000011 | high | undefined
9457 15:36:30.469323 speaker enable | 0x00000093 | high | undefined
9458 15:36:30.472032 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9459 15:36:30.475293 in-header: 03 f9 00 00 02 00 00 00
9460 15:36:30.478755 in-data: 02 00
9461 15:36:30.481822 ADC[4]: Raw value=903770 ID=7
9462 15:36:30.481904 ADC[3]: Raw value=213282 ID=1
9463 15:36:30.485308 RAM Code: 0x71
9464 15:36:30.488641 ADC[6]: Raw value=75036 ID=0
9465 15:36:30.492478 ADC[5]: Raw value=212912 ID=1
9466 15:36:30.492560 SKU Code: 0x1
9467 15:36:30.498617 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a16d
9468 15:36:30.498715 coreboot table: 964 bytes.
9469 15:36:30.501758 IMD ROOT 0. 0xfffff000 0x00001000
9470 15:36:30.505017 IMD SMALL 1. 0xffffe000 0x00001000
9471 15:36:30.508382 RO MCACHE 2. 0xffffc000 0x00001104
9472 15:36:30.511771 CONSOLE 3. 0xfff7c000 0x00080000
9473 15:36:30.514873 FMAP 4. 0xfff7b000 0x00000452
9474 15:36:30.518463 TIME STAMP 5. 0xfff7a000 0x00000910
9475 15:36:30.521375 VBOOT WORK 6. 0xfff66000 0x00014000
9476 15:36:30.525089 RAMOOPS 7. 0xffe66000 0x00100000
9477 15:36:30.528422 COREBOOT 8. 0xffe64000 0x00002000
9478 15:36:30.531314 IMD small region:
9479 15:36:30.534967 IMD ROOT 0. 0xffffec00 0x00000400
9480 15:36:30.538053 VPD 1. 0xffffeb80 0x0000006c
9481 15:36:30.541282 MMC STATUS 2. 0xffffeb60 0x00000004
9482 15:36:30.547962 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9483 15:36:30.548045 Probing TPM: done!
9484 15:36:30.554779 Connected to device vid:did:rid of 1ae0:0028:00
9485 15:36:30.561267 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9486 15:36:30.564771 Initialized TPM device CR50 revision 0
9487 15:36:30.567790 Checking cr50 for pending updates
9488 15:36:30.573378 Reading cr50 TPM mode
9489 15:36:30.581939 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9490 15:36:30.588401 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9491 15:36:30.628956 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9492 15:36:30.632461 Checking segment from ROM address 0x40100000
9493 15:36:30.635292 Checking segment from ROM address 0x4010001c
9494 15:36:30.642378 Loading segment from ROM address 0x40100000
9495 15:36:30.642460 code (compression=0)
9496 15:36:30.651790 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9497 15:36:30.658626 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9498 15:36:30.658723 it's not compressed!
9499 15:36:30.665256 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9500 15:36:30.671649 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9501 15:36:30.689194 Loading segment from ROM address 0x4010001c
9502 15:36:30.689279 Entry Point 0x80000000
9503 15:36:30.692734 Loaded segments
9504 15:36:30.695987 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9505 15:36:30.702329 Jumping to boot code at 0x80000000(0xffe64000)
9506 15:36:30.709188 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9507 15:36:30.715641 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9508 15:36:30.723360 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9509 15:36:30.726883 Checking segment from ROM address 0x40100000
9510 15:36:30.730241 Checking segment from ROM address 0x4010001c
9511 15:36:30.736917 Loading segment from ROM address 0x40100000
9512 15:36:30.737000 code (compression=1)
9513 15:36:30.743258 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9514 15:36:30.753189 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9515 15:36:30.753273 using LZMA
9516 15:36:30.762615 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9517 15:36:30.768566 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9518 15:36:30.772246 Loading segment from ROM address 0x4010001c
9519 15:36:30.772328 Entry Point 0x54601000
9520 15:36:30.775047 Loaded segments
9521 15:36:30.778387 NOTICE: MT8192 bl31_setup
9522 15:36:30.786132 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9523 15:36:30.788997 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9524 15:36:30.792341 WARNING: region 0:
9525 15:36:30.795467 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 15:36:30.795549 WARNING: region 1:
9527 15:36:30.801991 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9528 15:36:30.805430 WARNING: region 2:
9529 15:36:30.808507 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9530 15:36:30.811683 WARNING: region 3:
9531 15:36:30.815468 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9532 15:36:30.818386 WARNING: region 4:
9533 15:36:30.825162 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9534 15:36:30.825275 WARNING: region 5:
9535 15:36:30.828413 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 15:36:30.831613 WARNING: region 6:
9537 15:36:30.835224 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 15:36:30.838475 WARNING: region 7:
9539 15:36:30.841901 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9540 15:36:30.848834 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9541 15:36:30.851886 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9542 15:36:30.855182 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9543 15:36:30.861696 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9544 15:36:30.865079 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9545 15:36:30.871639 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9546 15:36:30.875173 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9547 15:36:30.878205 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9548 15:36:30.885179 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9549 15:36:30.888465 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9550 15:36:30.891495 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9551 15:36:30.898219 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9552 15:36:30.901940 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9553 15:36:30.908446 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9554 15:36:30.911336 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9555 15:36:30.914797 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9556 15:36:30.921862 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9557 15:36:30.924782 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9558 15:36:30.927921 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9559 15:36:30.935025 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9560 15:36:30.937968 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9561 15:36:30.944417 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9562 15:36:30.948133 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9563 15:36:30.951253 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9564 15:36:30.957892 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9565 15:36:30.961260 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9566 15:36:30.968049 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9567 15:36:30.971045 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9568 15:36:30.977658 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9569 15:36:30.980939 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9570 15:36:30.984311 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9571 15:36:30.991429 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9572 15:36:30.994507 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9573 15:36:30.998081 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9574 15:36:31.001098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9575 15:36:31.007416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9576 15:36:31.010895 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9577 15:36:31.014398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9578 15:36:31.017291 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9579 15:36:31.023866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9580 15:36:31.027519 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9581 15:36:31.030576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9582 15:36:31.033760 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9583 15:36:31.040789 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9584 15:36:31.044022 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9585 15:36:31.047397 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9586 15:36:31.053936 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9587 15:36:31.057323 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9588 15:36:31.060823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9589 15:36:31.067643 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9590 15:36:31.070332 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9591 15:36:31.077286 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9592 15:36:31.080500 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9593 15:36:31.083870 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9594 15:36:31.090258 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9595 15:36:31.093537 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9596 15:36:31.100375 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9597 15:36:31.103549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9598 15:36:31.110156 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9599 15:36:31.113469 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9600 15:36:31.116687 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9601 15:36:31.123381 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9602 15:36:31.126860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9603 15:36:31.133345 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9604 15:36:31.136438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9605 15:36:31.143153 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9606 15:36:31.146633 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9607 15:36:31.153438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9608 15:36:31.157017 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9609 15:36:31.159762 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9610 15:36:31.166534 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9611 15:36:31.169886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9612 15:36:31.176804 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9613 15:36:31.179594 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9614 15:36:31.186326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9615 15:36:31.189513 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9616 15:36:31.196405 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9617 15:36:31.200139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9618 15:36:31.202893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9619 15:36:31.209900 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9620 15:36:31.213074 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9621 15:36:31.219592 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9622 15:36:31.223171 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9623 15:36:31.230067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9624 15:36:31.232907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9625 15:36:31.236406 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9626 15:36:31.242906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9627 15:36:31.246533 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9628 15:36:31.252587 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9629 15:36:31.256154 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9630 15:36:31.263102 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9631 15:36:31.266259 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9632 15:36:31.269795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9633 15:36:31.276026 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9634 15:36:31.279471 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9635 15:36:31.285919 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9636 15:36:31.289200 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9637 15:36:31.292281 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9638 15:36:31.299114 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9639 15:36:31.302620 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9640 15:36:31.305560 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9641 15:36:31.312798 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9642 15:36:31.315675 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9643 15:36:31.318843 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9644 15:36:31.325299 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9645 15:36:31.328819 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9646 15:36:31.335419 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9647 15:36:31.338644 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9648 15:36:31.342060 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9649 15:36:31.348796 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9650 15:36:31.352145 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9651 15:36:31.358994 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9652 15:36:31.362290 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9653 15:36:31.368415 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9654 15:36:31.371996 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9655 15:36:31.375139 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9656 15:36:31.378492 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9657 15:36:31.385250 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9658 15:36:31.388151 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9659 15:36:31.391575 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9660 15:36:31.398237 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9661 15:36:31.402216 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9662 15:36:31.404696 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9663 15:36:31.408528 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9664 15:36:31.414955 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9665 15:36:31.418577 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9666 15:36:31.424935 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9667 15:36:31.427967 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9668 15:36:31.431461 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9669 15:36:31.438335 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9670 15:36:31.441357 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9671 15:36:31.448556 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9672 15:36:31.451145 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9673 15:36:31.454766 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9674 15:36:31.461302 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9675 15:36:31.464574 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9676 15:36:31.471484 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9677 15:36:31.474562 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9678 15:36:31.477839 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9679 15:36:31.485147 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9680 15:36:31.487694 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9681 15:36:31.494820 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9682 15:36:31.497846 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9683 15:36:31.501264 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9684 15:36:31.508160 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9685 15:36:31.511407 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9686 15:36:31.514352 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9687 15:36:31.521271 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9688 15:36:31.524355 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9689 15:36:31.530771 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9690 15:36:31.534007 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9691 15:36:31.537666 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9692 15:36:31.543951 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9693 15:36:31.547752 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9694 15:36:31.554129 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9695 15:36:31.557190 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9696 15:36:31.560680 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9697 15:36:31.567442 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9698 15:36:31.570551 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9699 15:36:31.577298 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9700 15:36:31.580240 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9701 15:36:31.583730 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9702 15:36:31.590167 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9703 15:36:31.593583 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9704 15:36:31.600263 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9705 15:36:31.603467 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9706 15:36:31.606835 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9707 15:36:31.613381 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9708 15:36:31.616600 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9709 15:36:31.623206 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9710 15:36:31.626564 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9711 15:36:31.629833 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9712 15:36:31.636740 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9713 15:36:31.640048 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9714 15:36:31.646321 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9715 15:36:31.649799 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9716 15:36:31.653237 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9717 15:36:31.660096 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9718 15:36:31.662852 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9719 15:36:31.669357 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9720 15:36:31.672647 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9721 15:36:31.676810 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9722 15:36:31.682518 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9723 15:36:31.685908 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9724 15:36:31.692686 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9725 15:36:31.696361 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9726 15:36:31.700111 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9727 15:36:31.705663 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9728 15:36:31.709300 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9729 15:36:31.715577 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9730 15:36:31.719012 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9731 15:36:31.725692 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9732 15:36:31.729434 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9733 15:36:31.732149 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9734 15:36:31.738938 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9735 15:36:31.742167 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9736 15:36:31.748945 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9737 15:36:31.752013 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9738 15:36:31.758717 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9739 15:36:31.761886 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9740 15:36:31.765590 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9741 15:36:31.771613 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9742 15:36:31.775003 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9743 15:36:31.781770 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9744 15:36:31.784938 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9745 15:36:31.788353 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9746 15:36:31.795106 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9747 15:36:31.798401 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9748 15:36:31.805107 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9749 15:36:31.808217 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9750 15:36:31.814964 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9751 15:36:31.818406 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9752 15:36:31.821499 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9753 15:36:31.827800 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9754 15:36:31.831482 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9755 15:36:31.837694 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9756 15:36:31.841055 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9757 15:36:31.847879 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9758 15:36:31.851078 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9759 15:36:31.854232 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9760 15:36:31.861241 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9761 15:36:31.864478 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9762 15:36:31.870816 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9763 15:36:31.874343 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9764 15:36:31.880563 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9765 15:36:31.883744 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9766 15:36:31.886996 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9767 15:36:31.894119 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9768 15:36:31.897350 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9769 15:36:31.903705 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9770 15:36:31.906825 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9771 15:36:31.910152 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9772 15:36:31.913331 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9773 15:36:31.917016 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9774 15:36:31.923655 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9775 15:36:31.926852 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9776 15:36:31.933770 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9777 15:36:31.936652 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9778 15:36:31.940274 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9779 15:36:31.946598 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9780 15:36:31.949689 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9781 15:36:31.956636 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9782 15:36:31.959747 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9783 15:36:31.963159 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9784 15:36:31.969517 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9785 15:36:31.972711 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9786 15:36:31.976840 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9787 15:36:31.983057 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9788 15:36:31.986328 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9789 15:36:31.989722 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9790 15:36:31.996083 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9791 15:36:31.999926 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9792 15:36:32.006652 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9793 15:36:32.009587 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9794 15:36:32.013064 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9795 15:36:32.019618 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9796 15:36:32.022404 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9797 15:36:32.028900 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9798 15:36:32.032435 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9799 15:36:32.035982 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9800 15:36:32.042293 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9801 15:36:32.045835 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9802 15:36:32.048775 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9803 15:36:32.055517 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9804 15:36:32.059137 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9805 15:36:32.062928 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9806 15:36:32.068892 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9807 15:36:32.071795 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9808 15:36:32.075350 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9809 15:36:32.082201 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9810 15:36:32.085541 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9811 15:36:32.088848 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9812 15:36:32.091691 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9813 15:36:32.098345 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9814 15:36:32.101753 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9815 15:36:32.104964 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9816 15:36:32.108304 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9817 15:36:32.115011 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9818 15:36:32.118109 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9819 15:36:32.121142 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9820 15:36:32.127874 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9821 15:36:32.131421 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9822 15:36:32.134397 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9823 15:36:32.141069 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9824 15:36:32.144148 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9825 15:36:32.150867 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9826 15:36:32.154207 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9827 15:36:32.160858 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9828 15:36:32.164235 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9829 15:36:32.167335 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9830 15:36:32.173831 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9831 15:36:32.176997 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9832 15:36:32.183926 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9833 15:36:32.187159 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9834 15:36:32.190849 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9835 15:36:32.197031 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9836 15:36:32.200655 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9837 15:36:32.207324 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9838 15:36:32.210268 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9839 15:36:32.213442 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9840 15:36:32.220360 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9841 15:36:32.223265 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9842 15:36:32.229852 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9843 15:36:32.233661 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9844 15:36:32.239938 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9845 15:36:32.243145 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9846 15:36:32.246224 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9847 15:36:32.253228 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9848 15:36:32.256314 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9849 15:36:32.263193 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9850 15:36:32.266191 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9851 15:36:32.272848 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9852 15:36:32.276067 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9853 15:36:32.279496 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9854 15:36:32.286158 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9855 15:36:32.289406 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9856 15:36:32.295908 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9857 15:36:32.299489 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9858 15:36:32.302498 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9859 15:36:32.309042 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9860 15:36:32.312668 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9861 15:36:32.319507 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9862 15:36:32.322786 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9863 15:36:32.325925 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9864 15:36:32.332362 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9865 15:36:32.335796 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9866 15:36:32.342111 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9867 15:36:32.345175 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9868 15:36:32.352191 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9869 15:36:32.355146 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9870 15:36:32.358352 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9871 15:36:32.365407 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9872 15:36:32.369310 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9873 15:36:32.375376 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9874 15:36:32.378440 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9875 15:36:32.381964 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9876 15:36:32.388868 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9877 15:36:32.391904 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9878 15:36:32.398235 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9879 15:36:32.401719 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9880 15:36:32.408336 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9881 15:36:32.411343 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9882 15:36:32.415124 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9883 15:36:32.421577 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9884 15:36:32.424837 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9885 15:36:32.431405 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9886 15:36:32.434868 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9887 15:36:32.438501 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9888 15:36:32.444637 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9889 15:36:32.448040 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9890 15:36:32.454444 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9891 15:36:32.457842 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9892 15:36:32.464134 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9893 15:36:32.467707 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9894 15:36:32.470791 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9895 15:36:32.477207 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9896 15:36:32.480695 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9897 15:36:32.487369 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9898 15:36:32.490670 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9899 15:36:32.497404 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9900 15:36:32.500308 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9901 15:36:32.503628 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9902 15:36:32.510727 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9903 15:36:32.513875 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9904 15:36:32.520164 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9905 15:36:32.523520 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9906 15:36:32.530220 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9907 15:36:32.533698 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9908 15:36:32.540144 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9909 15:36:32.543685 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9910 15:36:32.546842 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9911 15:36:32.553230 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9912 15:36:32.556676 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9913 15:36:32.563792 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9914 15:36:32.566567 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9915 15:36:32.573248 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9916 15:36:32.576580 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9917 15:36:32.579962 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9918 15:36:32.586381 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9919 15:36:32.589722 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9920 15:36:32.596294 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9921 15:36:32.599753 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9922 15:36:32.606571 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9923 15:36:32.609462 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9924 15:36:32.616316 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9925 15:36:32.619537 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9926 15:36:32.623175 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9927 15:36:32.629355 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9928 15:36:32.632750 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9929 15:36:32.639328 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9930 15:36:32.642829 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9931 15:36:32.649432 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9932 15:36:32.652764 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9933 15:36:32.656241 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9934 15:36:32.662412 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9935 15:36:32.666009 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9936 15:36:32.672915 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9937 15:36:32.675969 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9938 15:36:32.682278 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9939 15:36:32.685495 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9940 15:36:32.692024 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9941 15:36:32.695877 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9942 15:36:32.698909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9943 15:36:32.705263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9944 15:36:32.708581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9945 15:36:32.715418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9946 15:36:32.718366 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9947 15:36:32.725150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9948 15:36:32.728321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9949 15:36:32.734914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9950 15:36:32.738320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9951 15:36:32.745283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9952 15:36:32.748227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9953 15:36:32.754999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9954 15:36:32.758224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9955 15:36:32.765057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9956 15:36:32.767886 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9957 15:36:32.774619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9958 15:36:32.777730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9959 15:36:32.784574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9960 15:36:32.787870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9961 15:36:32.794841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9962 15:36:32.797620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9963 15:36:32.804796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9964 15:36:32.807700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9965 15:36:32.814371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9966 15:36:32.817387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9967 15:36:32.823908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9968 15:36:32.827339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9969 15:36:32.833793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9970 15:36:32.837512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9971 15:36:32.844014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9972 15:36:32.847126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9973 15:36:32.853715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9974 15:36:32.857049 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9975 15:36:32.860342 INFO: [APUAPC] vio 0
9976 15:36:32.864079 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9977 15:36:32.870361 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9978 15:36:32.873616 INFO: [APUAPC] D0_APC_0: 0x400510
9979 15:36:32.873724 INFO: [APUAPC] D0_APC_1: 0x0
9980 15:36:32.877319 INFO: [APUAPC] D0_APC_2: 0x1540
9981 15:36:32.880442 INFO: [APUAPC] D0_APC_3: 0x0
9982 15:36:32.883478 INFO: [APUAPC] D1_APC_0: 0xffffffff
9983 15:36:32.887069 INFO: [APUAPC] D1_APC_1: 0xffffffff
9984 15:36:32.890239 INFO: [APUAPC] D1_APC_2: 0x3fffff
9985 15:36:32.893747 INFO: [APUAPC] D1_APC_3: 0x0
9986 15:36:32.896723 INFO: [APUAPC] D2_APC_0: 0xffffffff
9987 15:36:32.899948 INFO: [APUAPC] D2_APC_1: 0xffffffff
9988 15:36:32.903270 INFO: [APUAPC] D2_APC_2: 0x3fffff
9989 15:36:32.906767 INFO: [APUAPC] D2_APC_3: 0x0
9990 15:36:32.909560 INFO: [APUAPC] D3_APC_0: 0xffffffff
9991 15:36:32.913250 INFO: [APUAPC] D3_APC_1: 0xffffffff
9992 15:36:32.917096 INFO: [APUAPC] D3_APC_2: 0x3fffff
9993 15:36:32.919684 INFO: [APUAPC] D3_APC_3: 0x0
9994 15:36:32.923135 INFO: [APUAPC] D4_APC_0: 0xffffffff
9995 15:36:32.926363 INFO: [APUAPC] D4_APC_1: 0xffffffff
9996 15:36:32.929853 INFO: [APUAPC] D4_APC_2: 0x3fffff
9997 15:36:32.933195 INFO: [APUAPC] D4_APC_3: 0x0
9998 15:36:32.936507 INFO: [APUAPC] D5_APC_0: 0xffffffff
9999 15:36:32.939783 INFO: [APUAPC] D5_APC_1: 0xffffffff
10000 15:36:32.943005 INFO: [APUAPC] D5_APC_2: 0x3fffff
10001 15:36:32.946018 INFO: [APUAPC] D5_APC_3: 0x0
10002 15:36:32.949590 INFO: [APUAPC] D6_APC_0: 0xffffffff
10003 15:36:32.952958 INFO: [APUAPC] D6_APC_1: 0xffffffff
10004 15:36:32.956061 INFO: [APUAPC] D6_APC_2: 0x3fffff
10005 15:36:32.959387 INFO: [APUAPC] D6_APC_3: 0x0
10006 15:36:32.962521 INFO: [APUAPC] D7_APC_0: 0xffffffff
10007 15:36:32.965747 INFO: [APUAPC] D7_APC_1: 0xffffffff
10008 15:36:32.969239 INFO: [APUAPC] D7_APC_2: 0x3fffff
10009 15:36:32.972385 INFO: [APUAPC] D7_APC_3: 0x0
10010 15:36:32.976273 INFO: [APUAPC] D8_APC_0: 0xffffffff
10011 15:36:32.979211 INFO: [APUAPC] D8_APC_1: 0xffffffff
10012 15:36:32.982509 INFO: [APUAPC] D8_APC_2: 0x3fffff
10013 15:36:32.985677 INFO: [APUAPC] D8_APC_3: 0x0
10014 15:36:32.989331 INFO: [APUAPC] D9_APC_0: 0xffffffff
10015 15:36:32.992231 INFO: [APUAPC] D9_APC_1: 0xffffffff
10016 15:36:32.995544 INFO: [APUAPC] D9_APC_2: 0x3fffff
10017 15:36:32.999006 INFO: [APUAPC] D9_APC_3: 0x0
10018 15:36:33.002145 INFO: [APUAPC] D10_APC_0: 0xffffffff
10019 15:36:33.005700 INFO: [APUAPC] D10_APC_1: 0xffffffff
10020 15:36:33.008711 INFO: [APUAPC] D10_APC_2: 0x3fffff
10021 15:36:33.011986 INFO: [APUAPC] D10_APC_3: 0x0
10022 15:36:33.015339 INFO: [APUAPC] D11_APC_0: 0xffffffff
10023 15:36:33.018984 INFO: [APUAPC] D11_APC_1: 0xffffffff
10024 15:36:33.022074 INFO: [APUAPC] D11_APC_2: 0x3fffff
10025 15:36:33.024988 INFO: [APUAPC] D11_APC_3: 0x0
10026 15:36:33.028815 INFO: [APUAPC] D12_APC_0: 0xffffffff
10027 15:36:33.032066 INFO: [APUAPC] D12_APC_1: 0xffffffff
10028 15:36:33.035022 INFO: [APUAPC] D12_APC_2: 0x3fffff
10029 15:36:33.038465 INFO: [APUAPC] D12_APC_3: 0x0
10030 15:36:33.041437 INFO: [APUAPC] D13_APC_0: 0xffffffff
10031 15:36:33.044851 INFO: [APUAPC] D13_APC_1: 0xffffffff
10032 15:36:33.048216 INFO: [APUAPC] D13_APC_2: 0x3fffff
10033 15:36:33.051511 INFO: [APUAPC] D13_APC_3: 0x0
10034 15:36:33.055027 INFO: [APUAPC] D14_APC_0: 0xffffffff
10035 15:36:33.058470 INFO: [APUAPC] D14_APC_1: 0xffffffff
10036 15:36:33.061388 INFO: [APUAPC] D14_APC_2: 0x3fffff
10037 15:36:33.064684 INFO: [APUAPC] D14_APC_3: 0x0
10038 15:36:33.067891 INFO: [APUAPC] D15_APC_0: 0xffffffff
10039 15:36:33.071221 INFO: [APUAPC] D15_APC_1: 0xffffffff
10040 15:36:33.074632 INFO: [APUAPC] D15_APC_2: 0x3fffff
10041 15:36:33.078001 INFO: [APUAPC] D15_APC_3: 0x0
10042 15:36:33.081879 INFO: [APUAPC] APC_CON: 0x4
10043 15:36:33.084727 INFO: [NOCDAPC] D0_APC_0: 0x0
10044 15:36:33.087641 INFO: [NOCDAPC] D0_APC_1: 0x0
10045 15:36:33.091440 INFO: [NOCDAPC] D1_APC_0: 0x0
10046 15:36:33.094315 INFO: [NOCDAPC] D1_APC_1: 0xfff
10047 15:36:33.094396 INFO: [NOCDAPC] D2_APC_0: 0x0
10048 15:36:33.097654 INFO: [NOCDAPC] D2_APC_1: 0xfff
10049 15:36:33.100964 INFO: [NOCDAPC] D3_APC_0: 0x0
10050 15:36:33.104733 INFO: [NOCDAPC] D3_APC_1: 0xfff
10051 15:36:33.107629 INFO: [NOCDAPC] D4_APC_0: 0x0
10052 15:36:33.110827 INFO: [NOCDAPC] D4_APC_1: 0xfff
10053 15:36:33.114335 INFO: [NOCDAPC] D5_APC_0: 0x0
10054 15:36:33.117466 INFO: [NOCDAPC] D5_APC_1: 0xfff
10055 15:36:33.120615 INFO: [NOCDAPC] D6_APC_0: 0x0
10056 15:36:33.124186 INFO: [NOCDAPC] D6_APC_1: 0xfff
10057 15:36:33.127134 INFO: [NOCDAPC] D7_APC_0: 0x0
10058 15:36:33.130771 INFO: [NOCDAPC] D7_APC_1: 0xfff
10059 15:36:33.130853 INFO: [NOCDAPC] D8_APC_0: 0x0
10060 15:36:33.134474 INFO: [NOCDAPC] D8_APC_1: 0xfff
10061 15:36:33.137218 INFO: [NOCDAPC] D9_APC_0: 0x0
10062 15:36:33.140831 INFO: [NOCDAPC] D9_APC_1: 0xfff
10063 15:36:33.143906 INFO: [NOCDAPC] D10_APC_0: 0x0
10064 15:36:33.147618 INFO: [NOCDAPC] D10_APC_1: 0xfff
10065 15:36:33.150422 INFO: [NOCDAPC] D11_APC_0: 0x0
10066 15:36:33.154547 INFO: [NOCDAPC] D11_APC_1: 0xfff
10067 15:36:33.157832 INFO: [NOCDAPC] D12_APC_0: 0x0
10068 15:36:33.160543 INFO: [NOCDAPC] D12_APC_1: 0xfff
10069 15:36:33.163666 INFO: [NOCDAPC] D13_APC_0: 0x0
10070 15:36:33.167445 INFO: [NOCDAPC] D13_APC_1: 0xfff
10071 15:36:33.171097 INFO: [NOCDAPC] D14_APC_0: 0x0
10072 15:36:33.173956 INFO: [NOCDAPC] D14_APC_1: 0xfff
10073 15:36:33.174038 INFO: [NOCDAPC] D15_APC_0: 0x0
10074 15:36:33.177460 INFO: [NOCDAPC] D15_APC_1: 0xfff
10075 15:36:33.180318 INFO: [NOCDAPC] APC_CON: 0x4
10076 15:36:33.183973 INFO: [APUAPC] set_apusys_apc done
10077 15:36:33.186843 INFO: [DEVAPC] devapc_init done
10078 15:36:33.193998 INFO: GICv3 without legacy support detected.
10079 15:36:33.197212 INFO: ARM GICv3 driver initialized in EL3
10080 15:36:33.200400 INFO: Maximum SPI INTID supported: 639
10081 15:36:33.203549 INFO: BL31: Initializing runtime services
10082 15:36:33.210117 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10083 15:36:33.213495 INFO: SPM: enable CPC mode
10084 15:36:33.216560 INFO: mcdi ready for mcusys-off-idle and system suspend
10085 15:36:33.223158 INFO: BL31: Preparing for EL3 exit to normal world
10086 15:36:33.226767 INFO: Entry point address = 0x80000000
10087 15:36:33.226849 INFO: SPSR = 0x8
10088 15:36:33.233395
10089 15:36:33.233476
10090 15:36:33.233541
10091 15:36:33.236666 Starting depthcharge on Spherion...
10092 15:36:33.236748
10093 15:36:33.236813 Wipe memory regions:
10094 15:36:33.236874
10095 15:36:33.237558 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10096 15:36:33.237673 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10097 15:36:33.237758 Setting prompt string to ['asurada:']
10098 15:36:33.237838 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10099 15:36:33.239763 [0x00000040000000, 0x00000054600000)
10100 15:36:33.362416
10101 15:36:33.362569 [0x00000054660000, 0x00000080000000)
10102 15:36:33.623080
10103 15:36:33.623220 [0x000000821a7280, 0x000000ffe64000)
10104 15:36:34.367535
10105 15:36:34.367674 [0x00000100000000, 0x00000240000000)
10106 15:36:36.257019
10107 15:36:36.260195 Initializing XHCI USB controller at 0x11200000.
10108 15:36:37.241473
10109 15:36:37.241614 R8152: Initializing
10110 15:36:37.241683
10111 15:36:37.245191 Version 9 (ocp_data = 6010)
10112 15:36:37.245273
10113 15:36:37.248088 R8152: Done initializing
10114 15:36:37.248170
10115 15:36:37.248235 Adding net device
10116 15:36:37.770428
10117 15:36:37.773089 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10118 15:36:37.773170
10119 15:36:37.773251
10120 15:36:37.773313
10121 15:36:37.773593 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10123 15:36:37.873952 asurada: tftpboot 192.168.201.1 11331363/tftp-deploy-nz64uxrg/kernel/image.itb 11331363/tftp-deploy-nz64uxrg/kernel/cmdline
10124 15:36:37.874088 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10125 15:36:37.874172 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10126 15:36:37.878915 tftpboot 192.168.201.1 11331363/tftp-deploy-nz64uxrg/kernel/image.itp-deploy-nz64uxrg/kernel/cmdline
10127 15:36:37.878996
10128 15:36:37.879061 Waiting for link
10129 15:36:38.080585
10130 15:36:38.080712 done.
10131 15:36:38.080781
10132 15:36:38.080859 MAC: f4:f5:e8:50:de:0a
10133 15:36:38.080922
10134 15:36:38.083744 Sending DHCP discover... done.
10135 15:36:38.083828
10136 15:36:38.088001 Waiting for reply... done.
10137 15:36:38.088076
10138 15:36:38.090758 Sending DHCP request... done.
10139 15:36:38.090836
10140 15:36:38.094513 Waiting for reply... done.
10141 15:36:38.094650
10142 15:36:38.094716 My ip is 192.168.201.14
10143 15:36:38.094777
10144 15:36:38.097997 The DHCP server ip is 192.168.201.1
10145 15:36:38.098065
10146 15:36:38.104987 TFTP server IP predefined by user: 192.168.201.1
10147 15:36:38.105072
10148 15:36:38.110993 Bootfile predefined by user: 11331363/tftp-deploy-nz64uxrg/kernel/image.itb
10149 15:36:38.111077
10150 15:36:38.114890 Sending tftp read request... done.
10151 15:36:38.114989
10152 15:36:38.118586 Waiting for the transfer...
10153 15:36:38.118734
10154 15:36:38.358232 00000000 ################################################################
10155 15:36:38.358395
10156 15:36:38.601773 00080000 ################################################################
10157 15:36:38.601938
10158 15:36:38.844336 00100000 ################################################################
10159 15:36:38.844471
10160 15:36:39.078949 00180000 ################################################################
10161 15:36:39.079090
10162 15:36:39.328806 00200000 ################################################################
10163 15:36:39.328951
10164 15:36:39.560831 00280000 ################################################################
10165 15:36:39.560981
10166 15:36:39.791192 00300000 ################################################################
10167 15:36:39.791335
10168 15:36:40.024551 00380000 ################################################################
10169 15:36:40.024697
10170 15:36:40.251250 00400000 ################################################################
10171 15:36:40.251424
10172 15:36:40.486222 00480000 ################################################################
10173 15:36:40.486399
10174 15:36:40.713907 00500000 ################################################################
10175 15:36:40.714049
10176 15:36:40.943664 00580000 ################################################################
10177 15:36:40.943798
10178 15:36:41.168891 00600000 ################################################################
10179 15:36:41.169035
10180 15:36:41.409683 00680000 ################################################################
10181 15:36:41.409831
10182 15:36:41.646698 00700000 ################################################################
10183 15:36:41.646865
10184 15:36:41.883314 00780000 ################################################################
10185 15:36:41.883463
10186 15:36:42.107371 00800000 ################################################################
10187 15:36:42.107514
10188 15:36:42.342515 00880000 ################################################################
10189 15:36:42.342681
10190 15:36:42.580510 00900000 ################################################################
10191 15:36:42.580680
10192 15:36:42.813529 00980000 ################################################################
10193 15:36:42.813670
10194 15:36:43.058170 00a00000 ################################################################
10195 15:36:43.058334
10196 15:36:43.292215 00a80000 ################################################################
10197 15:36:43.292380
10198 15:36:43.522922 00b00000 ################################################################
10199 15:36:43.523071
10200 15:36:43.749341 00b80000 ################################################################
10201 15:36:43.749484
10202 15:36:43.994338 00c00000 ################################################################
10203 15:36:43.994481
10204 15:36:44.265911 00c80000 ################################################################
10205 15:36:44.266057
10206 15:36:44.525099 00d00000 ################################################################
10207 15:36:44.525248
10208 15:36:44.774042 00d80000 ################################################################
10209 15:36:44.774240
10210 15:36:45.031528 00e00000 ################################################################
10211 15:36:45.031724
10212 15:36:45.278513 00e80000 ################################################################
10213 15:36:45.278733
10214 15:36:45.519842 00f00000 ################################################################
10215 15:36:45.520033
10216 15:36:45.763896 00f80000 ################################################################
10217 15:36:45.764072
10218 15:36:45.998512 01000000 ################################################################
10219 15:36:45.998699
10220 15:36:46.244612 01080000 ################################################################
10221 15:36:46.244749
10222 15:36:46.481637 01100000 ################################################################
10223 15:36:46.481770
10224 15:36:46.722448 01180000 ################################################################
10225 15:36:46.722617
10226 15:36:46.956146 01200000 ################################################################
10227 15:36:46.956279
10228 15:36:47.189519 01280000 ################################################################
10229 15:36:47.189650
10230 15:36:47.429089 01300000 ################################################################
10231 15:36:47.429239
10232 15:36:47.675339 01380000 ################################################################
10233 15:36:47.675483
10234 15:36:47.923240 01400000 ################################################################
10235 15:36:47.923389
10236 15:36:48.176724 01480000 ################################################################
10237 15:36:48.176874
10238 15:36:48.427495 01500000 ################################################################
10239 15:36:48.427643
10240 15:36:48.681491 01580000 ################################################################
10241 15:36:48.681652
10242 15:36:48.920618 01600000 ################################################################
10243 15:36:48.920750
10244 15:36:49.176450 01680000 ################################################################
10245 15:36:49.176593
10246 15:36:49.420445 01700000 ################################################################
10247 15:36:49.420584
10248 15:36:49.649951 01780000 ################################################################
10249 15:36:49.650114
10250 15:36:49.885674 01800000 ################################################################
10251 15:36:49.885836
10252 15:36:50.136466 01880000 ################################################################
10253 15:36:50.136602
10254 15:36:50.384835 01900000 ################################################################
10255 15:36:50.384971
10256 15:36:50.630964 01980000 ################################################################
10257 15:36:50.631117
10258 15:36:50.879394 01a00000 ################################################################
10259 15:36:50.879545
10260 15:36:51.136466 01a80000 ################################################################
10261 15:36:51.136625
10262 15:36:51.381799 01b00000 ################################################################
10263 15:36:51.381943
10264 15:36:51.629553 01b80000 ################################################################
10265 15:36:51.629687
10266 15:36:51.898510 01c00000 ################################################################
10267 15:36:51.898685
10268 15:36:52.173333 01c80000 ################################################################
10269 15:36:52.173551
10270 15:36:52.448868 01d00000 ################################################################
10271 15:36:52.449082
10272 15:36:52.724868 01d80000 ################################################################
10273 15:36:52.725085
10274 15:36:52.999570 01e00000 ################################################################
10275 15:36:52.999782
10276 15:36:53.239479 01e80000 ########################################################### done.
10277 15:36:53.239671
10278 15:36:53.242352 The bootfile was 32458910 bytes long.
10279 15:36:53.242470
10280 15:36:53.246213 Sending tftp read request... done.
10281 15:36:53.246333
10282 15:36:53.249050 Waiting for the transfer...
10283 15:36:53.249168
10284 15:36:53.249275 00000000 # done.
10285 15:36:53.249384
10286 15:36:53.259191 Command line loaded dynamically from TFTP file: 11331363/tftp-deploy-nz64uxrg/kernel/cmdline
10287 15:36:53.259317
10288 15:36:53.272180 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10289 15:36:53.272304
10290 15:36:53.272410 Loading FIT.
10291 15:36:53.272516
10292 15:36:53.275674 Image ramdisk-1 has 21374256 bytes.
10293 15:36:53.275791
10294 15:36:53.278757 Image fdt-1 has 47278 bytes.
10295 15:36:53.278875
10296 15:36:53.282170 Image kernel-1 has 11035343 bytes.
10297 15:36:53.282287
10298 15:36:53.292127 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10299 15:36:53.292246
10300 15:36:53.308582 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10301 15:36:53.308709
10302 15:36:53.312163 Choosing best match conf-1 for compat google,spherion-rev2.
10303 15:36:53.317789
10304 15:36:53.321779 Connected to device vid:did:rid of 1ae0:0028:00
10305 15:36:53.328907
10306 15:36:53.332413 tpm_get_response: command 0x17b, return code 0x0
10307 15:36:53.332530
10308 15:36:53.335759 ec_init: CrosEC protocol v3 supported (256, 248)
10309 15:36:53.339909
10310 15:36:53.343232 tpm_cleanup: add release locality here.
10311 15:36:53.343350
10312 15:36:53.343456 Shutting down all USB controllers.
10313 15:36:53.346630
10314 15:36:53.346761 Removing current net device
10315 15:36:53.346868
10316 15:36:53.353353 Exiting depthcharge with code 4 at timestamp: 49546788
10317 15:36:53.353472
10318 15:36:53.356433 LZMA decompressing kernel-1 to 0x821a6718
10319 15:36:53.356551
10320 15:36:53.360089 LZMA decompressing kernel-1 to 0x40000000
10321 15:36:54.748161
10322 15:36:54.748306 jumping to kernel
10323 15:36:54.748709 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10324 15:36:54.748810 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10325 15:36:54.748914 Setting prompt string to ['Linux version [0-9]']
10326 15:36:54.748981 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10327 15:36:54.749045 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10328 15:36:54.830240
10329 15:36:54.833175 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10330 15:36:54.836634 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10331 15:36:54.836732 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10332 15:36:54.836804 Setting prompt string to []
10333 15:36:54.836884 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10334 15:36:54.836959 Using line separator: #'\n'#
10335 15:36:54.837017 No login prompt set.
10336 15:36:54.837076 Parsing kernel messages
10337 15:36:54.837133 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10338 15:36:54.837258 [login-action] Waiting for messages, (timeout 00:04:03)
10339 15:36:54.856213 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j17681-arm64-gcc-10-defconfig-arm64-chromebook-c49jr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Aug 22 15:20:14 UTC 2023
10340 15:36:54.859609 [ 0.000000] random: crng init done
10341 15:36:54.865497 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10342 15:36:54.869250 [ 0.000000] efi: UEFI not found.
10343 15:36:54.875647 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10344 15:36:54.882034 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10345 15:36:54.892155 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10346 15:36:54.901776 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10347 15:36:54.908935 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10348 15:36:54.915140 [ 0.000000] printk: bootconsole [mtk8250] enabled
10349 15:36:54.921856 [ 0.000000] NUMA: No NUMA configuration found
10350 15:36:54.928715 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10351 15:36:54.931784 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10352 15:36:54.935161 [ 0.000000] Zone ranges:
10353 15:36:54.942015 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10354 15:36:54.944852 [ 0.000000] DMA32 empty
10355 15:36:54.951548 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10356 15:36:54.955286 [ 0.000000] Movable zone start for each node
10357 15:36:54.958114 [ 0.000000] Early memory node ranges
10358 15:36:54.965369 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10359 15:36:54.971757 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10360 15:36:54.978466 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10361 15:36:54.984653 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10362 15:36:54.991057 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10363 15:36:54.998089 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10364 15:36:55.053823 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10365 15:36:55.060373 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10366 15:36:55.067283 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10367 15:36:55.070330 [ 0.000000] psci: probing for conduit method from DT.
10368 15:36:55.076729 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10369 15:36:55.080016 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10370 15:36:55.086738 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10371 15:36:55.090053 [ 0.000000] psci: SMC Calling Convention v1.2
10372 15:36:55.096505 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10373 15:36:55.099802 [ 0.000000] Detected VIPT I-cache on CPU0
10374 15:36:55.106555 [ 0.000000] CPU features: detected: GIC system register CPU interface
10375 15:36:55.113159 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10376 15:36:55.119347 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10377 15:36:55.126176 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10378 15:36:55.136126 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10379 15:36:55.142690 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10380 15:36:55.145871 [ 0.000000] alternatives: applying boot alternatives
10381 15:36:55.153530 [ 0.000000] Fallback order for Node 0: 0
10382 15:36:55.159105 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10383 15:36:55.162442 [ 0.000000] Policy zone: Normal
10384 15:36:55.176115 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10385 15:36:55.185504 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10386 15:36:55.198824 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10387 15:36:55.208146 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10388 15:36:55.215143 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10389 15:36:55.218213 <6>[ 0.000000] software IO TLB: area num 8.
10390 15:36:55.274776 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10391 15:36:55.424082 <6>[ 0.000000] Memory: 7948680K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 404088K reserved, 32768K cma-reserved)
10392 15:36:55.430555 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10393 15:36:55.437197 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10394 15:36:55.440858 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10395 15:36:55.447006 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10396 15:36:55.454015 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10397 15:36:55.456755 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10398 15:36:55.466967 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10399 15:36:55.473271 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10400 15:36:55.480055 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10401 15:36:55.486416 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10402 15:36:55.490535 <6>[ 0.000000] GICv3: 608 SPIs implemented
10403 15:36:55.493539 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10404 15:36:55.499670 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10405 15:36:55.502870 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10406 15:36:55.509651 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10407 15:36:55.523083 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10408 15:36:55.536170 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10409 15:36:55.542929 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10410 15:36:55.550570 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10411 15:36:55.563742 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10412 15:36:55.570254 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10413 15:36:55.577374 <6>[ 0.009230] Console: colour dummy device 80x25
10414 15:36:55.587433 <6>[ 0.013957] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10415 15:36:55.593713 <6>[ 0.024399] pid_max: default: 32768 minimum: 301
10416 15:36:55.596956 <6>[ 0.029272] LSM: Security Framework initializing
10417 15:36:55.604002 <6>[ 0.034209] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10418 15:36:55.613508 <6>[ 0.042070] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10419 15:36:55.623061 <6>[ 0.051503] cblist_init_generic: Setting adjustable number of callback queues.
10420 15:36:55.629877 <6>[ 0.058996] cblist_init_generic: Setting shift to 3 and lim to 1.
10421 15:36:55.636972 <6>[ 0.065336] cblist_init_generic: Setting adjustable number of callback queues.
10422 15:36:55.643379 <6>[ 0.072807] cblist_init_generic: Setting shift to 3 and lim to 1.
10423 15:36:55.646684 <6>[ 0.079247] rcu: Hierarchical SRCU implementation.
10424 15:36:55.653186 <6>[ 0.084291] rcu: Max phase no-delay instances is 1000.
10425 15:36:55.660085 <6>[ 0.091325] EFI services will not be available.
10426 15:36:55.662698 <6>[ 0.096297] smp: Bringing up secondary CPUs ...
10427 15:36:55.672143 <6>[ 0.101351] Detected VIPT I-cache on CPU1
10428 15:36:55.678935 <6>[ 0.101419] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10429 15:36:55.685209 <6>[ 0.101451] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10430 15:36:55.688440 <6>[ 0.101791] Detected VIPT I-cache on CPU2
10431 15:36:55.698766 <6>[ 0.101845] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10432 15:36:55.705092 <6>[ 0.101862] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10433 15:36:55.709629 <6>[ 0.102120] Detected VIPT I-cache on CPU3
10434 15:36:55.715154 <6>[ 0.102166] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10435 15:36:55.721550 <6>[ 0.102180] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10436 15:36:55.728148 <6>[ 0.102486] CPU features: detected: Spectre-v4
10437 15:36:55.731261 <6>[ 0.102492] CPU features: detected: Spectre-BHB
10438 15:36:55.734571 <6>[ 0.102497] Detected PIPT I-cache on CPU4
10439 15:36:55.740789 <6>[ 0.102556] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10440 15:36:55.750841 <6>[ 0.102573] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10441 15:36:55.754898 <6>[ 0.102865] Detected PIPT I-cache on CPU5
10442 15:36:55.760870 <6>[ 0.102930] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10443 15:36:55.767797 <6>[ 0.102946] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10444 15:36:55.770999 <6>[ 0.103231] Detected PIPT I-cache on CPU6
10445 15:36:55.780930 <6>[ 0.103298] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10446 15:36:55.787308 <6>[ 0.103315] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10447 15:36:55.790516 <6>[ 0.103601] Detected PIPT I-cache on CPU7
10448 15:36:55.797493 <6>[ 0.103661] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10449 15:36:55.803798 <6>[ 0.103677] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10450 15:36:55.807446 <6>[ 0.103723] smp: Brought up 1 node, 8 CPUs
10451 15:36:55.814376 <6>[ 0.245054] SMP: Total of 8 processors activated.
10452 15:36:55.820242 <6>[ 0.249975] CPU features: detected: 32-bit EL0 Support
10453 15:36:55.827299 <6>[ 0.255338] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10454 15:36:55.833421 <6>[ 0.264139] CPU features: detected: Common not Private translations
10455 15:36:55.839898 <6>[ 0.270615] CPU features: detected: CRC32 instructions
10456 15:36:55.846945 <6>[ 0.275966] CPU features: detected: RCpc load-acquire (LDAPR)
10457 15:36:55.850672 <6>[ 0.281963] CPU features: detected: LSE atomic instructions
10458 15:36:55.856310 <6>[ 0.287744] CPU features: detected: Privileged Access Never
10459 15:36:55.862822 <6>[ 0.293523] CPU features: detected: RAS Extension Support
10460 15:36:55.869990 <6>[ 0.299167] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10461 15:36:55.873250 <6>[ 0.306431] CPU: All CPU(s) started at EL2
10462 15:36:55.880428 <6>[ 0.310748] alternatives: applying system-wide alternatives
10463 15:36:55.889391 <6>[ 0.321399] devtmpfs: initialized
10464 15:36:55.904846 <6>[ 0.330354] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10465 15:36:55.911491 <6>[ 0.340314] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10466 15:36:55.918091 <6>[ 0.348325] pinctrl core: initialized pinctrl subsystem
10467 15:36:55.921394 <6>[ 0.355089] DMI not present or invalid.
10468 15:36:55.928401 <6>[ 0.359499] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10469 15:36:55.937842 <6>[ 0.366349] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10470 15:36:55.944805 <6>[ 0.373931] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10471 15:36:55.955150 <6>[ 0.382152] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10472 15:36:55.958355 <6>[ 0.390395] audit: initializing netlink subsys (disabled)
10473 15:36:55.968106 <5>[ 0.396090] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10474 15:36:55.974443 <6>[ 0.396845] thermal_sys: Registered thermal governor 'step_wise'
10475 15:36:55.980742 <6>[ 0.404056] thermal_sys: Registered thermal governor 'power_allocator'
10476 15:36:55.984243 <6>[ 0.410312] cpuidle: using governor menu
10477 15:36:55.991074 <6>[ 0.421275] NET: Registered PF_QIPCRTR protocol family
10478 15:36:55.997589 <6>[ 0.426761] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10479 15:36:56.004066 <6>[ 0.433867] ASID allocator initialised with 32768 entries
10480 15:36:56.007496 <6>[ 0.440498] Serial: AMBA PL011 UART driver
10481 15:36:56.017850 <4>[ 0.449689] Trying to register duplicate clock ID: 134
10482 15:36:56.074676 <6>[ 0.509800] KASLR enabled
10483 15:36:56.089877 <6>[ 0.517559] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10484 15:36:56.095770 <6>[ 0.524572] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10485 15:36:56.102196 <6>[ 0.531062] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10486 15:36:56.108549 <6>[ 0.538068] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10487 15:36:56.115615 <6>[ 0.544557] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10488 15:36:56.122102 <6>[ 0.551563] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10489 15:36:56.128433 <6>[ 0.558052] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10490 15:36:56.135045 <6>[ 0.565057] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10491 15:36:56.138488 <6>[ 0.572571] ACPI: Interpreter disabled.
10492 15:36:56.147482 <6>[ 0.579050] iommu: Default domain type: Translated
10493 15:36:56.154128 <6>[ 0.584163] iommu: DMA domain TLB invalidation policy: strict mode
10494 15:36:56.156971 <5>[ 0.590817] SCSI subsystem initialized
10495 15:36:56.163204 <6>[ 0.594980] usbcore: registered new interface driver usbfs
10496 15:36:56.170190 <6>[ 0.600710] usbcore: registered new interface driver hub
10497 15:36:56.172799 <6>[ 0.606260] usbcore: registered new device driver usb
10498 15:36:56.180152 <6>[ 0.612407] pps_core: LinuxPPS API ver. 1 registered
10499 15:36:56.189809 <6>[ 0.617602] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10500 15:36:56.193237 <6>[ 0.626949] PTP clock support registered
10501 15:36:56.196583 <6>[ 0.631194] EDAC MC: Ver: 3.0.0
10502 15:36:56.203989 <6>[ 0.636398] FPGA manager framework
10503 15:36:56.210945 <6>[ 0.640074] Advanced Linux Sound Architecture Driver Initialized.
10504 15:36:56.214016 <6>[ 0.646851] vgaarb: loaded
10505 15:36:56.221110 <6>[ 0.650029] clocksource: Switched to clocksource arch_sys_counter
10506 15:36:56.224127 <5>[ 0.656450] VFS: Disk quotas dquot_6.6.0
10507 15:36:56.230699 <6>[ 0.660633] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10508 15:36:56.234352 <6>[ 0.667822] pnp: PnP ACPI: disabled
10509 15:36:56.242569 <6>[ 0.674483] NET: Registered PF_INET protocol family
10510 15:36:56.253025 <6>[ 0.680068] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10511 15:36:56.264154 <6>[ 0.692363] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10512 15:36:56.274353 <6>[ 0.701177] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10513 15:36:56.280054 <6>[ 0.709145] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10514 15:36:56.287118 <6>[ 0.717845] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10515 15:36:56.299972 <6>[ 0.727596] TCP: Hash tables configured (established 65536 bind 65536)
10516 15:36:56.305317 <6>[ 0.734454] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10517 15:36:56.311906 <6>[ 0.741652] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10518 15:36:56.318256 <6>[ 0.749356] NET: Registered PF_UNIX/PF_LOCAL protocol family
10519 15:36:56.325867 <6>[ 0.755530] RPC: Registered named UNIX socket transport module.
10520 15:36:56.328821 <6>[ 0.761684] RPC: Registered udp transport module.
10521 15:36:56.335550 <6>[ 0.766618] RPC: Registered tcp transport module.
10522 15:36:56.341636 <6>[ 0.771549] RPC: Registered tcp NFSv4.1 backchannel transport module.
10523 15:36:56.345112 <6>[ 0.778219] PCI: CLS 0 bytes, default 64
10524 15:36:56.348978 <6>[ 0.782613] Unpacking initramfs...
10525 15:36:56.373696 <6>[ 0.802138] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10526 15:36:56.382919 <6>[ 0.810798] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10527 15:36:56.387107 <6>[ 0.819671] kvm [1]: IPA Size Limit: 40 bits
10528 15:36:56.393322 <6>[ 0.824189] kvm [1]: GICv3: no GICV resource entry
10529 15:36:56.396160 <6>[ 0.829210] kvm [1]: disabling GICv2 emulation
10530 15:36:56.403200 <6>[ 0.833897] kvm [1]: GIC system register CPU interface enabled
10531 15:36:56.406106 <6>[ 0.840057] kvm [1]: vgic interrupt IRQ18
10532 15:36:56.412620 <6>[ 0.844411] kvm [1]: VHE mode initialized successfully
10533 15:36:56.419917 <5>[ 0.850873] Initialise system trusted keyrings
10534 15:36:56.425976 <6>[ 0.855697] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10535 15:36:56.433621 <6>[ 0.865713] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10536 15:36:56.440241 <5>[ 0.872087] NFS: Registering the id_resolver key type
10537 15:36:56.444194 <5>[ 0.877386] Key type id_resolver registered
10538 15:36:56.450437 <5>[ 0.881802] Key type id_legacy registered
10539 15:36:56.457296 <6>[ 0.886080] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10540 15:36:56.463470 <6>[ 0.893005] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10541 15:36:56.470683 <6>[ 0.900716] 9p: Installing v9fs 9p2000 file system support
10542 15:36:56.506776 <5>[ 0.939019] Key type asymmetric registered
10543 15:36:56.509973 <5>[ 0.943352] Asymmetric key parser 'x509' registered
10544 15:36:56.520317 <6>[ 0.948500] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10545 15:36:56.523264 <6>[ 0.956112] io scheduler mq-deadline registered
10546 15:36:56.526991 <6>[ 0.960896] io scheduler kyber registered
10547 15:36:56.546362 <6>[ 0.978515] EINJ: ACPI disabled.
10548 15:36:56.579587 <4>[ 1.004847] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10549 15:36:56.589289 <4>[ 1.015508] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10550 15:36:56.604545 <6>[ 1.036544] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10551 15:36:56.612832 <6>[ 1.044641] printk: console [ttyS0] disabled
10552 15:36:56.640806 <6>[ 1.069292] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10553 15:36:56.646916 <6>[ 1.078769] printk: console [ttyS0] enabled
10554 15:36:56.650233 <6>[ 1.078769] printk: console [ttyS0] enabled
10555 15:36:56.656970 <6>[ 1.087664] printk: bootconsole [mtk8250] disabled
10556 15:36:56.660535 <6>[ 1.087664] printk: bootconsole [mtk8250] disabled
10557 15:36:56.666546 <6>[ 1.099010] SuperH (H)SCI(F) driver initialized
10558 15:36:56.670352 <6>[ 1.104311] msm_serial: driver initialized
10559 15:36:56.684306 <6>[ 1.113425] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10560 15:36:56.694100 <6>[ 1.121974] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10561 15:36:56.701498 <6>[ 1.130515] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10562 15:36:56.711208 <6>[ 1.139144] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10563 15:36:56.721169 <6>[ 1.147851] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10564 15:36:56.727924 <6>[ 1.156573] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10565 15:36:56.737441 <6>[ 1.165114] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10566 15:36:56.744649 <6>[ 1.173920] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10567 15:36:56.754164 <6>[ 1.182463] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10568 15:36:56.766002 <6>[ 1.198377] loop: module loaded
10569 15:36:56.773054 <6>[ 1.204395] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10570 15:36:56.795209 <4>[ 1.227441] mtk-pmic-keys: Failed to locate of_node [id: -1]
10571 15:36:56.802474 <6>[ 1.234317] megasas: 07.719.03.00-rc1
10572 15:36:56.812187 <6>[ 1.243920] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10573 15:36:56.821469 <6>[ 1.253404] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10574 15:36:56.837925 <6>[ 1.270040] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10575 15:36:56.898533 <6>[ 1.324064] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10576 15:36:57.254528 <6>[ 1.686916] Freeing initrd memory: 20872K
10577 15:36:57.270387 <6>[ 1.702541] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10578 15:36:57.281572 <6>[ 1.713319] tun: Universal TUN/TAP device driver, 1.6
10579 15:36:57.285033 <6>[ 1.719411] thunder_xcv, ver 1.0
10580 15:36:57.288028 <6>[ 1.722918] thunder_bgx, ver 1.0
10581 15:36:57.291314 <6>[ 1.726416] nicpf, ver 1.0
10582 15:36:57.301593 <6>[ 1.730472] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10583 15:36:57.305189 <6>[ 1.737947] hns3: Copyright (c) 2017 Huawei Corporation.
10584 15:36:57.311527 <6>[ 1.743534] hclge is initializing
10585 15:36:57.314780 <6>[ 1.747116] e1000: Intel(R) PRO/1000 Network Driver
10586 15:36:57.321626 <6>[ 1.752245] e1000: Copyright (c) 1999-2006 Intel Corporation.
10587 15:36:57.325424 <6>[ 1.758260] e1000e: Intel(R) PRO/1000 Network Driver
10588 15:36:57.331520 <6>[ 1.763476] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10589 15:36:57.338257 <6>[ 1.769661] igb: Intel(R) Gigabit Ethernet Network Driver
10590 15:36:57.344845 <6>[ 1.775310] igb: Copyright (c) 2007-2014 Intel Corporation.
10591 15:36:57.351842 <6>[ 1.781145] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10592 15:36:57.358225 <6>[ 1.787663] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10593 15:36:57.361016 <6>[ 1.794143] sky2: driver version 1.30
10594 15:36:57.367570 <6>[ 1.799196] VFIO - User Level meta-driver version: 0.3
10595 15:36:57.375413 <6>[ 1.807543] usbcore: registered new interface driver usb-storage
10596 15:36:57.381738 <6>[ 1.813987] usbcore: registered new device driver onboard-usb-hub
10597 15:36:57.391163 <6>[ 1.823182] mt6397-rtc mt6359-rtc: registered as rtc0
10598 15:36:57.401033 <6>[ 1.828647] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-22T15:36:57 UTC (1692718617)
10599 15:36:57.403855 <6>[ 1.838245] i2c_dev: i2c /dev entries driver
10600 15:36:57.421136 <6>[ 1.850151] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10601 15:36:57.441107 <6>[ 1.873144] cpu cpu0: EM: created perf domain
10602 15:36:57.444763 <6>[ 1.878184] cpu cpu4: EM: created perf domain
10603 15:36:57.451672 <6>[ 1.883789] sdhci: Secure Digital Host Controller Interface driver
10604 15:36:57.458443 <6>[ 1.890223] sdhci: Copyright(c) Pierre Ossman
10605 15:36:57.464853 <6>[ 1.895223] Synopsys Designware Multimedia Card Interface Driver
10606 15:36:57.471862 <6>[ 1.901888] sdhci-pltfm: SDHCI platform and OF driver helper
10607 15:36:57.475169 <6>[ 1.901915] mmc0: CQHCI version 5.10
10608 15:36:57.481415 <6>[ 1.911856] ledtrig-cpu: registered to indicate activity on CPUs
10609 15:36:57.488142 <6>[ 1.918970] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10610 15:36:57.495173 <6>[ 1.926062] usbcore: registered new interface driver usbhid
10611 15:36:57.498005 <6>[ 1.931883] usbhid: USB HID core driver
10612 15:36:57.504334 <6>[ 1.936077] spi_master spi0: will run message pump with realtime priority
10613 15:36:57.552609 <6>[ 1.978091] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10614 15:36:57.572359 <6>[ 1.994423] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10615 15:36:57.576018 <6>[ 2.008640] mmc0: Command Queue Engine enabled
10616 15:36:57.582862 <6>[ 2.009175] cros-ec-spi spi0.0: Chrome EC device registered
10617 15:36:57.589648 <6>[ 2.013412] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10618 15:36:57.592923 <6>[ 2.026424] mmcblk0: mmc0:0001 DA4128 116 GiB
10619 15:36:57.605384 <6>[ 2.037146] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10620 15:36:57.615082 <6>[ 2.037499] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10621 15:36:57.621290 <6>[ 2.044118] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10622 15:36:57.625032 <6>[ 2.053345] NET: Registered PF_PACKET protocol family
10623 15:36:57.631679 <6>[ 2.058261] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10624 15:36:57.635057 <6>[ 2.063044] 9pnet: Installing 9P2000 support
10625 15:36:57.641277 <6>[ 2.068676] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10626 15:36:57.648067 <5>[ 2.072693] Key type dns_resolver registered
10627 15:36:57.651610 <6>[ 2.084162] registered taskstats version 1
10628 15:36:57.658445 <5>[ 2.088533] Loading compiled-in X.509 certificates
10629 15:36:57.685812 <4>[ 2.111600] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10630 15:36:57.696528 <4>[ 2.122391] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10631 15:36:57.702751 <3>[ 2.132929] debugfs: File 'uA_load' in directory '/' already present!
10632 15:36:57.709190 <3>[ 2.139686] debugfs: File 'min_uV' in directory '/' already present!
10633 15:36:57.716083 <3>[ 2.146305] debugfs: File 'max_uV' in directory '/' already present!
10634 15:36:57.722521 <3>[ 2.152913] debugfs: File 'constraint_flags' in directory '/' already present!
10635 15:36:57.734085 <3>[ 2.162792] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10636 15:36:57.746377 <6>[ 2.178291] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10637 15:36:57.752867 <6>[ 2.185048] xhci-mtk 11200000.usb: xHCI Host Controller
10638 15:36:57.759277 <6>[ 2.190549] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10639 15:36:57.769882 <6>[ 2.198398] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10640 15:36:57.776519 <6>[ 2.207847] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10641 15:36:57.782734 <6>[ 2.213946] xhci-mtk 11200000.usb: xHCI Host Controller
10642 15:36:57.789660 <6>[ 2.219577] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10643 15:36:57.795836 <6>[ 2.227248] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10644 15:36:57.802760 <6>[ 2.235133] hub 1-0:1.0: USB hub found
10645 15:36:57.806051 <6>[ 2.239166] hub 1-0:1.0: 1 port detected
10646 15:36:57.815922 <6>[ 2.243470] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10647 15:36:57.819247 <6>[ 2.252270] hub 2-0:1.0: USB hub found
10648 15:36:57.822535 <6>[ 2.256295] hub 2-0:1.0: 1 port detected
10649 15:36:57.832904 <6>[ 2.264633] mtk-msdc 11f70000.mmc: Got CD GPIO
10650 15:36:57.842361 <6>[ 2.271226] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10651 15:36:57.848973 <6>[ 2.279248] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10652 15:36:57.858607 <4>[ 2.287174] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10653 15:36:57.868777 <6>[ 2.296730] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10654 15:36:57.875766 <6>[ 2.304807] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10655 15:36:57.881792 <6>[ 2.312803] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10656 15:36:57.892105 <6>[ 2.320719] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10657 15:36:57.898159 <6>[ 2.328535] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10658 15:36:57.908269 <6>[ 2.336352] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10659 15:36:57.918356 <6>[ 2.346797] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10660 15:36:57.925065 <6>[ 2.355177] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10661 15:36:57.935235 <6>[ 2.363518] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10662 15:36:57.941810 <6>[ 2.371861] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10663 15:36:57.951039 <6>[ 2.380199] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10664 15:36:57.961472 <6>[ 2.388537] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10665 15:36:57.967925 <6>[ 2.396875] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10666 15:36:57.978254 <6>[ 2.405213] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10667 15:36:57.984398 <6>[ 2.413551] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10668 15:36:57.994672 <6>[ 2.421889] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10669 15:36:58.000506 <6>[ 2.430229] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10670 15:36:58.010584 <6>[ 2.438567] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10671 15:36:58.016933 <6>[ 2.446905] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10672 15:36:58.027473 <6>[ 2.455247] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10673 15:36:58.034315 <6>[ 2.463584] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10674 15:36:58.040784 <6>[ 2.472387] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10675 15:36:58.047287 <6>[ 2.479549] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10676 15:36:58.054045 <6>[ 2.486313] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10677 15:36:58.064546 <6>[ 2.493085] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10678 15:36:58.070259 <6>[ 2.500030] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10679 15:36:58.077295 <6>[ 2.506882] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10680 15:36:58.087356 <6>[ 2.516015] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10681 15:36:58.097050 <6>[ 2.525136] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10682 15:36:58.106609 <6>[ 2.534430] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10683 15:36:58.116630 <6>[ 2.543899] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10684 15:36:58.126723 <6>[ 2.553366] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10685 15:36:58.133210 <6>[ 2.562486] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10686 15:36:58.143272 <6>[ 2.571952] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10687 15:36:58.152852 <6>[ 2.581071] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10688 15:36:58.163279 <6>[ 2.590368] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10689 15:36:58.172896 <6>[ 2.600529] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10690 15:36:58.183688 <6>[ 2.612508] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10691 15:36:58.213555 <6>[ 2.642603] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10692 15:36:58.241706 <6>[ 2.674105] hub 2-1:1.0: USB hub found
10693 15:36:58.245415 <6>[ 2.678580] hub 2-1:1.0: 3 ports detected
10694 15:36:58.364804 <6>[ 2.794162] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10695 15:36:58.520530 <6>[ 2.952451] hub 1-1:1.0: USB hub found
10696 15:36:58.523250 <6>[ 2.956946] hub 1-1:1.0: 4 ports detected
10697 15:36:58.844976 <6>[ 3.274351] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10698 15:36:58.976248 <6>[ 3.408595] hub 1-1.1:1.0: USB hub found
10699 15:36:58.979591 <6>[ 3.412954] hub 1-1.1:1.0: 4 ports detected
10700 15:36:59.093355 <6>[ 3.522345] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10701 15:36:59.225451 <6>[ 3.657867] hub 1-1.4:1.0: USB hub found
10702 15:36:59.228449 <6>[ 3.662516] hub 1-1.4:1.0: 2 ports detected
10703 15:36:59.309251 <6>[ 3.738331] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10704 15:36:59.496953 <6>[ 3.926354] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10705 15:36:59.581727 <3>[ 4.014421] usb 1-1.1.4: device descriptor read/64, error -32
10706 15:36:59.774276 <3>[ 4.206501] usb 1-1.1.4: device descriptor read/64, error -32
10707 15:36:59.968897 <6>[ 4.398314] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10708 15:37:00.157089 <6>[ 4.586330] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10709 15:37:00.241920 <3>[ 4.674521] usb 1-1.1.4: device descriptor read/64, error -32
10710 15:37:00.433623 <3>[ 4.866515] usb 1-1.1.4: device descriptor read/64, error -32
10711 15:37:00.546021 <6>[ 4.978847] usb 1-1.1-port4: attempt power cycle
10712 15:37:00.633128 <6>[ 5.062335] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10713 15:37:01.156947 <6>[ 5.586335] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10714 15:37:01.163382 <4>[ 5.593814] usb 1-1.1.4: Device not responding to setup address.
10715 15:37:01.373493 <4>[ 5.806593] usb 1-1.1.4: Device not responding to setup address.
10716 15:37:01.585613 <3>[ 6.018388] usb 1-1.1.4: device not accepting address 10, error -71
10717 15:37:01.673317 <6>[ 6.102357] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10718 15:37:01.679391 <4>[ 6.109775] usb 1-1.1.4: Device not responding to setup address.
10719 15:37:01.890012 <4>[ 6.322632] usb 1-1.1.4: Device not responding to setup address.
10720 15:37:02.101832 <3>[ 6.534341] usb 1-1.1.4: device not accepting address 11, error -71
10721 15:37:02.109149 <3>[ 6.541399] usb 1-1.1-port4: unable to enumerate USB device
10722 15:37:10.458985 <6>[ 14.895408] ALSA device list:
10723 15:37:10.465520 <6>[ 14.898707] No soundcards found.
10724 15:37:10.473489 <6>[ 14.906779] Freeing unused kernel memory: 8384K
10725 15:37:10.476926 <6>[ 14.911783] Run /init as init process
10726 15:37:10.512799 Starting syslogd: OK
10727 15:37:10.516793 Starting klogd: OK
10728 15:37:10.526174 Running sysctl: OK
10729 15:37:10.533139 Populating /dev using udev: <30>[ 14.968236] udevd[185]: starting version 3.2.9
10730 15:37:10.542546 <27>[ 14.976282] udevd[185]: specified user 'tss' unknown
10731 15:37:10.549429 <27>[ 14.981655] udevd[185]: specified group 'tss' unknown
10732 15:37:10.555902 <30>[ 14.988085] udevd[186]: starting eudev-3.2.9
10733 15:37:10.574812 <27>[ 15.007942] udevd[186]: specified user 'tss' unknown
10734 15:37:10.580770 <27>[ 15.013311] udevd[186]: specified group 'tss' unknown
10735 15:37:10.675839 <6>[ 15.105741] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10736 15:37:10.689988 <6>[ 15.123345] remoteproc remoteproc0: scp is available
10737 15:37:10.696955 <6>[ 15.129032] remoteproc remoteproc0: powering up scp
10738 15:37:10.703476 <6>[ 15.134196] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10739 15:37:10.713215 <6>[ 15.141768] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10740 15:37:10.716644 <6>[ 15.142649] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10741 15:37:10.726697 <3>[ 15.145988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 15:37:10.733201 <3>[ 15.146004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 15:37:10.742863 <3>[ 15.146048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 15:37:10.749527 <3>[ 15.146155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 15:37:10.760103 <3>[ 15.146163] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 15:37:10.765788 <3>[ 15.146171] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 15:37:10.772665 <3>[ 15.146182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 15:37:10.782421 <3>[ 15.146190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 15:37:10.788986 <3>[ 15.146243] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 15:37:10.799328 <3>[ 15.146292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 15:37:10.806006 <3>[ 15.146300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 15:37:10.815561 <3>[ 15.146307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 15:37:10.821954 <3>[ 15.146371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 15:37:10.831954 <3>[ 15.146379] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 15:37:10.838643 <3>[ 15.146386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 15:37:10.845431 <3>[ 15.146394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 15:37:10.855437 <3>[ 15.146401] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 15:37:10.862226 <3>[ 15.147384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 15:37:10.872667 <6>[ 15.150440] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10760 15:37:10.878758 <6>[ 15.204608] usbcore: registered new interface driver r8152
10761 15:37:10.885257 <6>[ 15.212499] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10762 15:37:10.895497 <6>[ 15.213006] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10763 15:37:10.898954 <6>[ 15.213206] mc: Linux media interface: v0.10
10764 15:37:10.908745 <4>[ 15.235415] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10765 15:37:10.912050 <4>[ 15.235415] Fallback method does not support PEC.
10766 15:37:10.918728 <6>[ 15.261563] videodev: Linux video capture interface: v2.00
10767 15:37:10.925045 <4>[ 15.261916] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10768 15:37:10.931944 <4>[ 15.262156] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10769 15:37:10.938305 <6>[ 15.281436] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10770 15:37:10.948094 <6>[ 15.285240] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10771 15:37:10.955651 <6>[ 15.285248] remoteproc remoteproc0: remote processor scp is now up
10772 15:37:10.961970 <6>[ 15.294359] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10773 15:37:10.972114 <3>[ 15.303491] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10774 15:37:10.982041 <6>[ 15.330500] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10775 15:37:10.988720 <6>[ 15.367605] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10776 15:37:10.998405 <6>[ 15.372297] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10777 15:37:11.005327 <6>[ 15.372746] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10778 15:37:11.014927 <6>[ 15.374810] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10779 15:37:11.018237 <6>[ 15.378316] pci_bus 0000:00: root bus resource [bus 00-ff]
10780 15:37:11.024631 <6>[ 15.378325] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10781 15:37:11.034862 <6>[ 15.378329] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10782 15:37:11.041188 <6>[ 15.378377] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10783 15:37:11.051130 <6>[ 15.382692] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10784 15:37:11.061317 <3>[ 15.407491] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10785 15:37:11.067851 <6>[ 15.409580] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10786 15:37:11.074660 <6>[ 15.419821] usbcore: registered new interface driver cdc_ether
10787 15:37:11.077989 <6>[ 15.426398] pci 0000:00:00.0: supports D1 D2
10788 15:37:11.080591 <6>[ 15.452562] Bluetooth: Core ver 2.22
10789 15:37:11.087523 <6>[ 15.452689] usbcore: registered new interface driver r8153_ecm
10790 15:37:11.097594 <4>[ 15.455520] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10791 15:37:11.106977 <4>[ 15.455529] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10792 15:37:11.113572 <6>[ 15.457643] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10793 15:37:11.117133 <6>[ 15.464827] NET: Registered PF_BLUETOOTH protocol family
10794 15:37:11.123454 <6>[ 15.465531] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10795 15:37:11.137505 <6>[ 15.466815] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10796 15:37:11.143396 <6>[ 15.466949] usbcore: registered new interface driver uvcvideo
10797 15:37:11.146943 <6>[ 15.470217] r8152 1-1.1.1:1.0 eth0: v1.12.13
10798 15:37:11.156398 <6>[ 15.475628] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10799 15:37:11.163304 <6>[ 15.480926] Bluetooth: HCI device and connection manager initialized
10800 15:37:11.166851 <6>[ 15.480958] Bluetooth: HCI socket layer initialized
10801 15:37:11.173146 <6>[ 15.490390] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10802 15:37:11.180009 <6>[ 15.499007] Bluetooth: L2CAP socket layer initialized
10803 15:37:11.186090 <6>[ 15.499510] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10804 15:37:11.192724 <6>[ 15.506500] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10805 15:37:11.199274 <6>[ 15.512587] Bluetooth: SCO socket layer initialized
10806 15:37:11.205960 <6>[ 15.517090] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10807 15:37:11.212868 <6>[ 15.564374] usbcore: registered new interface driver btusb
10808 15:37:11.222828 <4>[ 15.565265] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10809 15:37:11.229231 <3>[ 15.565275] Bluetooth: hci0: Failed to load firmware file (-2)
10810 15:37:11.232365 <3>[ 15.565279] Bluetooth: hci0: Failed to set up firmware (-2)
10811 15:37:11.245744 <4>[ 15.565283] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10812 15:37:11.252154 <6>[ 15.576330] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10813 15:37:11.255608 <6>[ 15.691048] pci 0000:01:00.0: supports D1 D2
10814 15:37:11.262321 <6>[ 15.695568] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10815 15:37:11.287737 <6>[ 15.718224] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10816 15:37:11.294673 <6>[ 15.725149] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10817 15:37:11.300959 <6>[ 15.733230] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10818 15:37:11.310941 <6>[ 15.741225] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10819 15:37:11.317341 <6>[ 15.749228] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10820 15:37:11.327468 <6>[ 15.757230] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10821 15:37:11.330822 <6>[ 15.765231] pci 0000:00:00.0: PCI bridge to [bus 01]
10822 15:37:11.340123 <6>[ 15.770449] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10823 15:37:11.346543 <6>[ 15.778654] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10824 15:37:11.353500 <6>[ 15.785458] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10825 15:37:11.359968 <6>[ 15.792299] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10826 15:37:11.375453 <5>[ 15.805984] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10827 15:37:11.408173 <5>[ 15.838386] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10828 15:37:11.414338 <4>[ 15.845283] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10829 15:37:11.420962 <6>[ 15.854212] cfg80211: failed to load regulatory.db
10830 15:37:11.472604 <6>[ 15.902710] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10831 15:37:11.479051 <6>[ 15.910251] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10832 15:37:11.503747 <6>[ 15.937124] mt7921e 0000:01:00.0: ASIC revision: 79610010
10833 15:37:11.612426 <4>[ 16.038676] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10834 15:37:11.628016 done
10835 15:37:11.635188 Saving random seed: OK
10836 15:37:11.648614 Starting network: OK
10837 15:37:11.678290 Starting dropbear sshd: <6>[ 16.111695] NET: Registered PF_INET6 protocol family
10838 15:37:11.681644 <6>[ 16.117707] Segment Routing with IPv6
10839 15:37:11.688032 <6>[ 16.121649] In-situ OAM (IOAM) with IPv6
10840 15:37:11.691397 OK
10841 15:37:11.701591 /bin/sh: can't access tty; job control turned off
10842 15:37:11.702722 Matched prompt #10: / #
10844 15:37:11.703893 Setting prompt string to ['/ #']
10845 15:37:11.704428 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10847 15:37:11.705589 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10848 15:37:11.706136 start: 2.2.6 expect-shell-connection (timeout 00:03:47) [common]
10849 15:37:11.706542 Setting prompt string to ['/ #']
10850 15:37:11.706966 Forcing a shell prompt, looking for ['/ #']
10852 15:37:11.757982 / #
10853 15:37:11.758758 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10854 15:37:11.759427 Waiting using forced prompt support (timeout 00:02:30)
10855 15:37:11.760111 <4>[ 16.156854] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10856 15:37:11.764675
10857 15:37:11.765663 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10858 15:37:11.766278 start: 2.2.7 export-device-env (timeout 00:03:47) [common]
10859 15:37:11.767066 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10860 15:37:11.767656 end: 2.2 depthcharge-retry (duration 00:01:13) [common]
10861 15:37:11.768268 end: 2 depthcharge-action (duration 00:01:13) [common]
10862 15:37:11.768874 start: 3 lava-test-retry (timeout 00:01:00) [common]
10863 15:37:11.769457 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10864 15:37:11.770073 Using namespace: common
10866 15:37:11.871441 / # #
10867 15:37:11.872102 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10868 15:37:11.872708 #<4>[ 16.278224] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10869 15:37:11.878191
10870 15:37:11.879106 Using /lava-11331363
10872 15:37:11.980436 / # export SHELL=/bin/sh
10873 15:37:11.981227 export SHELL=/bin/sh<4>[ 16.399297] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10874 15:37:11.987529
10876 15:37:12.089352 / # . /lava-11331363/environment
10877 15:37:12.092051 . /lava-11331363/environment<4>[ 16.518813] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10878 15:37:12.135176
10880 15:37:12.237076 / # /lava-11331363/bin/lava-test-runner /lava-11331363/0
10881 15:37:12.237702 Test shell timeout: 10s (minimum of the action and connection timeout)
10882 15:37:12.239405 /lava-11331363/bin/lava-test-runner /lava-11331363/0<4>[ 16.639809] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10883 15:37:12.243955
10884 15:37:12.287087 + export 'TESTRUN_ID=0_dmesg'
10885 15:37:12.287665 +<8>[ 16.702975] <LAVA_SIGNAL_STARTRUN 0_dmesg 11331363_1.5.2.3.1>
10886 15:37:12.288203 cd /lava-11331363/0/tests/0_dmesg
10887 15:37:12.288749 + cat uuid
10888 15:37:12.289109 + UUID=11331363_1.5.2.3.1
10889 15:37:12.289447 + set +x
10890 15:37:12.290064 Received signal: <STARTRUN> 0_dmesg 11331363_1.5.2.3.1
10891 15:37:12.290434 Starting test lava.0_dmesg (11331363_1.5.2.3.1)
10892 15:37:12.290921 Skipping test definition patterns.
10893 15:37:12.291461 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10894 15:37:12.291829 <8>[ 16.721364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10895 15:37:12.292442 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10897 15:37:12.311169 <8>[ 16.741451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10898 15:37:12.312019 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10900 15:37:12.338470 <4>[ 16.764994] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10901 15:37:12.345605 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10903 15:37:12.347950 <8>[ 16.766513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10904 15:37:12.348435 + set +x
10905 15:37:12.354564 <8>[ 16.786725] <LAVA_SIGNAL_ENDRUN 0_dmesg 11331363_1.5.2.3.1>
10906 15:37:12.355494 Received signal: <ENDRUN> 0_dmesg 11331363_1.5.2.3.1
10907 15:37:12.355991 Ending use of test pattern.
10908 15:37:12.356421 Ending test lava.0_dmesg (11331363_1.5.2.3.1), duration 0.07
10910 15:37:12.358527 <LAVA_TEST_RUNNER EXIT>
10911 15:37:12.359305 ok: lava_test_shell seems to have completed
10912 15:37:12.360178 alert: pass
crit: pass
emerg: pass
10913 15:37:12.360651 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10914 15:37:12.361121 end: 3 lava-test-retry (duration 00:00:01) [common]
10915 15:37:12.361586 start: 4 lava-test-retry (timeout 00:01:00) [common]
10916 15:37:12.362043 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10917 15:37:12.362409 Using namespace: common
10919 15:37:12.463783 / # #
10920 15:37:12.464471 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10921 15:37:12.465161 Using /lava-11331363
10923 15:37:12.566453 export SHELL=/bin/sh
10924 15:37:12.567393 #<4>[ 16.885707] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10925 15:37:12.567949
10927 15:37:12.669503 / # export SHELL=/bin/sh. /lava-11331363/environment
10928 15:37:12.669748 <4>[ 17.007106] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10929 15:37:12.669856
10931 15:37:12.770461 / # . /lava-11331363/environment/lava-11331363/bin/lava-test-runner /lava-11331363/1
10932 15:37:12.770687 Test shell timeout: 10s (minimum of the action and connection timeout)
10933 15:37:12.770839
10934 15:37:12.770915 / # <4>[ 17.127669] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10935 15:37:12.775795 /lava-11331363/bin/lava-test-runner /lava-11331363/1
10936 15:37:12.822832 + export 'TESTRUN_ID=1_bootrr'
10937 15:37:12.823003 + cd /lava-11331<8>[ 17.235338] <LAVA_SIGNAL_STARTRUN 1_bootrr 11331363_1.5.2.3.5>
10938 15:37:12.823118 363/1/tests/1_bootrr
10939 15:37:12.823216 + cat uuid
10940 15:37:12.823315 + UUID=11331363_1.5.2.3.5
10941 15:37:12.823413 + s<3>[ 17.248327] mt7921e 0000:01:00.0: hardware init failed
10942 15:37:12.823506 et +x
10943 15:37:12.823803 Received signal: <STARTRUN> 1_bootrr 11331363_1.5.2.3.5
10944 15:37:12.823907 Starting test lava.1_bootrr (11331363_1.5.2.3.5)
10945 15:37:12.824043 Skipping test definition patterns.
10946 15:37:12.828608 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11331363/1/../bin<8>[ 17.259807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10947 15:37:12.828884 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10949 15:37:12.831562 :/sbin:/usr/sbin:/bin:/usr/bin'
10950 15:37:12.834940 + cd /opt/bootrr/libexec/bootrr
10951 15:37:12.838700 + sh helpers/bootrr-auto
10952 15:37:12.848648 /lava-11331363/1/../bin/lava-test-ca<8>[ 17.278183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10953 15:37:12.848869 se
10954 15:37:12.849235 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10956 15:37:12.851507 /lava-11331363/1/../bin/lava-test-case
10957 15:37:12.855206 /usr/bin/tpm2_getcap
10958 15:37:12.890411 /lava-11331363/1/../bin/lava-test-case
10959 15:37:12.897272 <8>[ 17.328705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10960 15:37:12.898151 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10962 15:37:12.916565 /lava-11331363/1/../bin/lava-test-case
10963 15:37:12.922872 <8>[ 17.352958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10964 15:37:12.923749 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10966 15:37:12.934662 /lava-11331363/1/../bin/lava-test-case
10967 15:37:12.940517 <8>[ 17.370544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10968 15:37:12.941372 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10970 15:37:12.953597 /lava-11331363/1/../bin/lava-test-case
10971 15:37:12.959778 <8>[ 17.391197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10972 15:37:12.960656 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10974 15:37:12.970375 /lava-11331363/1/../bin/lava-test-case
10975 15:37:12.976951 <8>[ 17.408049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10976 15:37:12.977292 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10978 15:37:12.989897 /lava-11331363/1/../bin/lava-test-case
10979 15:37:12.996223 <8>[ 17.427852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10980 15:37:12.996541 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10982 15:37:13.007161 /lava-11331363/1/../bin/lava-test-case
10983 15:37:13.013332 <8>[ 17.444088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10984 15:37:13.013687 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10986 15:37:13.035212 /lava-11331363/1/../bin/lava-tes<8>[ 17.465165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10987 15:37:13.035414 t-case
10988 15:37:13.035753 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10990 15:37:13.043086 /lava-11331363/1/../bin/lava-test-case
10991 15:37:13.052970 <8>[ 17.481352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10992 15:37:13.053434 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10994 15:37:13.069974 /lava-11331363/1/../bin/lava-tes<8>[ 17.499924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10995 15:37:13.070361 t-case
10996 15:37:13.070974 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10998 15:37:13.080365 /lava-11331363/1/../bin/lava-test-case
10999 15:37:13.087494 <8>[ 17.517963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11000 15:37:13.088380 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11002 15:37:13.103581 /lava-11331363/1/../bin/lava-test-case
11003 15:37:13.110254 <8>[ 17.539872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11004 15:37:13.111157 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11006 15:37:13.122427 /lava-11331363/1/../bin/lava-test-case
11007 15:37:13.128854 <8>[ 17.558327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11008 15:37:13.129701 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11010 15:37:13.145919 /lava-11331363/1/../bin/lava-tes<8>[ 17.575633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11011 15:37:13.146487 t-case
11012 15:37:13.147247 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11014 15:37:13.156508 /lava-11331363/1/../bin/lava-test-case
11015 15:37:13.162466 <8>[ 17.593512] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11016 15:37:13.163466 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11018 15:37:13.171306 /lava-11331363/1/../bin/lava-test-case
11019 15:37:13.178186 <8>[ 17.608251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11020 15:37:13.179088 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11022 15:37:13.189358 /lava-11331363/1/../bin/lava-test-case
11023 15:37:13.195978 <8>[ 17.626505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11024 15:37:13.196824 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11026 15:37:13.204814 /lava-11331363/1/../bin/lava-test-case
11027 15:37:13.211785 <8>[ 17.641899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11028 15:37:13.212630 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11030 15:37:13.222906 /lava-11331363/1/../bin/lava-test-case
11031 15:37:13.229488 <8>[ 17.660139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11032 15:37:13.230332 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11034 15:37:13.237595 /lava-11331363/1/../bin/lava-test-case
11035 15:37:13.244315 <8>[ 17.674426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11036 15:37:13.245157 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11038 15:37:13.255756 /lava-11331363/1/../bin/lava-test-case
11039 15:37:13.261637 <8>[ 17.693124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11040 15:37:13.262460 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11042 15:37:13.271095 /lava-11331363/1/../bin/lava-test-case
11043 15:37:13.277954 <8>[ 17.708168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11044 15:37:13.278813 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11046 15:37:13.290269 /lava-11331363/1/../bin/lava-test-case
11047 15:37:13.296735 <8>[ 17.727924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11048 15:37:13.297464 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11050 15:37:13.309299 /lava-11331363/1/../bin/lava-test-case
11051 15:37:13.315391 <8>[ 17.746686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11052 15:37:13.316214 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11054 15:37:13.327836 /lava-11331363/1/../bin/lava-test-case
11055 15:37:13.334036 <8>[ 17.764304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11056 15:37:13.334926 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11058 15:37:13.345492 /lava-11331363/1/../bin/lava-test-case
11059 15:37:13.355326 <8>[ 17.784166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11060 15:37:13.356174 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11062 15:37:13.364006 /lava-11331363/1/../bin/lava-test-case
11063 15:37:13.370768 <8>[ 17.800983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11064 15:37:13.371532 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11066 15:37:13.382896 /lava-11331363/1/../bin/lava-test-case
11067 15:37:13.388892 <8>[ 17.819571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11068 15:37:13.389768 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11070 15:37:13.399968 /lava-11331363/1/../bin/lava-test-case
11071 15:37:13.407090 <8>[ 17.836910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11072 15:37:13.407935 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11074 15:37:13.416646 /lava-11331363/1/../bin/lava-test-case
11075 15:37:13.423226 <8>[ 17.854838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11076 15:37:13.424243 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11078 15:37:13.435911 /lava-11331363/1/../bin/lava-test-case
11079 15:37:13.441962 <8>[ 17.872611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11080 15:37:13.442856 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11082 15:37:13.451907 /lava-11331363/1/../bin/lava-test-case
11083 15:37:13.458508 <8>[ 17.888258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11084 15:37:13.459402 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11086 15:37:13.479140 /lava-11331363/1/../bin/lava-tes<8>[ 17.908717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11087 15:37:13.479702 t-case
11088 15:37:13.480388 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11090 15:37:13.490330 /lava-11331363/1/../bin/lava-test-case
11091 15:37:13.496926 <8>[ 17.926604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11092 15:37:13.497746 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11094 15:37:13.513131 /lava-11331363/1/../bin/lava-tes<8>[ 17.942278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11095 15:37:13.513714 t-case
11096 15:37:13.514367 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11098 15:37:13.523782 /lava-11331363/1/../bin/lava-test-case
11099 15:37:13.530641 <8>[ 17.960310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11100 15:37:13.531618 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11102 15:37:13.542655 /lava-11331363/1/../bin/lava-test-case
11103 15:37:13.549499 <8>[ 17.980905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11104 15:37:13.550289 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11106 15:37:13.561151 /lava-11331363/1/../bin/lava-test-case
11107 15:37:13.567339 <8>[ 17.999354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11108 15:37:13.568023 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11110 15:37:13.585151 /lava-11331363/1/../bin/lava-tes<8>[ 18.014947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11111 15:37:13.585665 t-case
11112 15:37:13.586273 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11114 15:37:13.599466 /lava-11331363/1/../bin/lava-test-case
11115 15:37:13.609255 <8>[ 18.039192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11116 15:37:13.609940 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11118 15:37:13.618302 /lava-11331363/1/../bin/lava-test-case
11119 15:37:13.625367 <8>[ 18.055436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11120 15:37:13.626166 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11122 15:37:13.637380 /lava-11331363/1/../bin/lava-test-case
11123 15:37:13.644054 <8>[ 18.074886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11124 15:37:13.644736 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11126 15:37:13.653352 /lava-11331363/1/../bin/lava-test-case
11127 15:37:13.659757 <8>[ 18.090317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11128 15:37:13.660576 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11130 15:37:13.672270 /lava-11331363/1/../bin/lava-test-case
11131 15:37:13.678497 <8>[ 18.108782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11132 15:37:13.679430 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11134 15:37:13.686575 /lava-11331363/1/../bin/lava-test-case
11135 15:37:13.693058 <8>[ 18.123934] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11136 15:37:13.693835 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11138 15:37:13.705392 /lava-11331363/1/../bin/lava-test-case
11139 15:37:13.712213 <8>[ 18.141960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11140 15:37:13.713058 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11142 15:37:13.725900 /lava-11331363/1/../bin/lava-tes<8>[ 18.155822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11143 15:37:13.726471 t-case
11144 15:37:13.727161 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11146 15:37:13.739868 /lava-11331363/1/../bin/lava-test-case
11147 15:37:13.747059 <8>[ 18.177231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11148 15:37:13.747907 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11150 15:37:13.756510 /lava-11331363/1/../bin/lava-test-case
11151 15:37:13.768120 <8>[ 18.198304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11152 15:37:13.768942 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11154 15:37:13.777373 /lava-11331363/1/../bin/lava-test-case
11155 15:37:13.784044 <8>[ 18.214620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11156 15:37:13.784863 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11158 15:37:13.795316 /lava-11331363/1/../bin/lava-test-case
11159 15:37:13.802205 <8>[ 18.232536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11160 15:37:13.803045 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11162 15:37:13.810725 /lava-11331363/1/../bin/lava-test-case
11163 15:37:13.817110 <8>[ 18.248461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11164 15:37:13.817953 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11166 15:37:13.828146 /lava-11331363/1/../bin/lava-test-case
11167 15:37:13.835367 <8>[ 18.265924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11168 15:37:13.836216 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11170 15:37:13.847243 /lava-11331363/1/../bin/lava-test-case
11171 15:37:13.853927 <8>[ 18.284297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11172 15:37:13.854747 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11174 15:37:13.863732 /lava-11331363/1/../bin/lava-test-case
11175 15:37:13.870297 <8>[ 18.300810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11176 15:37:13.871225 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11178 15:37:13.883497 /lava-11331363/1/../bin/lava-test-case
11179 15:37:13.889841 <8>[ 18.321304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11180 15:37:13.890734 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11182 15:37:13.900408 /lava-11331363/1/../bin/lava-test-case
11183 15:37:13.906749 <8>[ 18.337429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11184 15:37:13.907688 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11186 15:37:13.916419 /lava-11331363/1/../bin/lava-test-case
11187 15:37:13.922887 <8>[ 18.352997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11188 15:37:13.923737 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11190 15:37:13.932591 /lava-11331363/1/../bin/lava-test-case
11191 15:37:13.939466 <8>[ 18.371223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11192 15:37:13.940323 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11194 15:37:13.951316 /lava-11331363/1/../bin/lava-test-case
11195 15:37:13.958159 <8>[ 18.388444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11196 15:37:13.959052 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11198 15:37:13.965594 /lava-11331363/1/../bin/lava-test-case
11199 15:37:13.972838 <8>[ 18.402933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11200 15:37:13.973582 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11202 15:37:13.985848 /lava-11331363/1/../bin/lava-test-case
11203 15:37:13.991832 <8>[ 18.422316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11204 15:37:13.992675 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11206 15:37:13.999960 /lava-11331363/1/../bin/lava-test-case
11207 15:37:14.006517 <8>[ 18.437239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11208 15:37:14.007370 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11210 15:37:14.018586 /lava-11331363/1/../bin/lava-test-case
11211 15:37:14.025077 <8>[ 18.456131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11212 15:37:14.025929 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11214 15:37:14.041467 /lava-11331363/1/../bin/lava-tes<8>[ 18.471269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11215 15:37:14.042036 t-case
11216 15:37:14.042750 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11218 15:37:14.051512 /lava-11331363/1/../bin/lava-test-case
11219 15:37:14.057598 <8>[ 18.489067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11220 15:37:14.058452 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11222 15:37:14.076612 /lava-11331363/1/../bin/lava-tes<8>[ 18.506123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11223 15:37:14.077184 t-case
11224 15:37:14.077836 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11226 15:37:14.085583 /lava-11331363/1/../bin/lava-test-case
11227 15:37:14.092218 <8>[ 18.523850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11228 15:37:14.093051 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11230 15:37:14.105006 /lava-11331363/1/../bin/lava-test-case
11231 15:37:14.111608 <8>[ 18.542304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11232 15:37:14.112533 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11234 15:37:14.123287 /lava-11331363/1/../bin/lava-test-case
11235 15:37:14.128596 <8>[ 18.559312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11236 15:37:14.129420 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11238 15:37:14.139726 /lava-11331363/1/../bin/lava-test-case
11239 15:37:14.146243 <8>[ 18.577151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11240 15:37:14.146557 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11242 15:37:14.156759 /lava-11331363/1/../bin/lava-test-case
11243 15:37:14.163660 <8>[ 18.595327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11244 15:37:14.164491 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11246 15:37:14.176064 /lava-11331363/1/../bin/lava-test-case
11247 15:37:14.182837 <8>[ 18.613464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11248 15:37:14.183680 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11250 15:37:14.193155 /lava-11331363/1/../bin/lava-test-case
11251 15:37:14.199700 <8>[ 18.630652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11252 15:37:14.200528 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11254 15:37:14.214246 /lava-11331363/1/../bin/lava-test-case
11255 15:37:14.221016 <8>[ 18.652229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11256 15:37:14.221771 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11258 15:37:14.231181 /lava-11331363/1/../bin/lava-test-case
11259 15:37:14.237741 <8>[ 18.669412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11260 15:37:14.238541 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11262 15:37:14.249336 /lava-11331363/1/../bin/lava-test-case
11263 15:37:14.256015 <8>[ 18.687210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11264 15:37:14.256786 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11266 15:37:14.267074 /lava-11331363/1/../bin/lava-test-case
11267 15:37:14.274018 <8>[ 18.704532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11268 15:37:14.274934 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11270 15:37:14.284607 /lava-11331363/1/../bin/lava-test-case
11271 15:37:14.294679 <8>[ 18.724358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11272 15:37:14.295467 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11274 15:37:14.305368 /lava-11331363/1/../bin/lava-test-case
11275 15:37:14.311922 <8>[ 18.742707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11276 15:37:14.312766 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11278 15:37:14.320537 /lava-11331363/1/../bin/lava-test-case
11279 15:37:14.326682 <8>[ 18.757596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11280 15:37:14.327504 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11282 15:37:14.339144 /lava-11331363/1/../bin/lava-test-case
11283 15:37:14.345304 <8>[ 18.777108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11284 15:37:14.346047 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11286 15:37:14.354260 /lava-11331363/1/../bin/lava-test-case
11287 15:37:14.360716 <8>[ 18.790935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11288 15:37:14.361387 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11290 15:37:14.375002 /lava-11331363/1/../bin/lava-test-case
11291 15:37:14.382196 <8>[ 18.814135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11292 15:37:14.383040 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11294 15:37:14.399518 /lava-11331363/1/../bin/lava-tes<8>[ 18.829372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11295 15:37:14.400024 t-case
11296 15:37:14.400642 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11298 15:37:14.413961 /lava-11331363/1/../bin/lava-test-case
11299 15:37:14.420365 <8>[ 18.851687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11300 15:37:14.421236 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11302 15:37:14.433013 /lava-11331363/1/../bin/lava-test-case
11303 15:37:14.443210 <8>[ 18.872715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11304 15:37:14.443891 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11306 15:37:14.454388 /lava-11331363/1/../bin/lava-test-case
11307 15:37:14.461626 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11309 15:37:14.463736 <8>[ 18.893826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11310 15:37:14.471975 /lava-11331363/1/../bin/lava-test-case
11311 15:37:14.478699 <8>[ 18.909889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11312 15:37:14.479487 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11314 15:37:14.489873 /lava-11331363/1/../bin/lava-test-case
11315 15:37:14.495834 <8>[ 18.928284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11316 15:37:14.496517 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11318 15:37:14.507102 /lava-11331363/1/../bin/lava-test-case
11319 15:37:14.513327 <8>[ 18.943980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11320 15:37:14.514012 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11322 15:37:14.524665 /lava-11331363/1/../bin/lava-test-case
11323 15:37:14.531271 <8>[ 18.963126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11324 15:37:14.531956 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11326 15:37:14.544327 /lava-11331363/1/../bin/lava-test-case
11327 15:37:14.550663 <8>[ 18.981171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11328 15:37:14.551399 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11330 15:37:14.559805 /lava-11331363/1/../bin/lava-test-case
11331 15:37:14.565898 <8>[ 18.996816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11332 15:37:14.566691 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11334 15:37:14.578768 /lava-11331363/1/../bin/lava-test-case
11335 15:37:14.585113 <8>[ 19.015223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11336 15:37:14.585976 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11338 15:37:14.595118 /lava-11331363/1/../bin/lava-test-case
11339 15:37:14.601176 <8>[ 19.032843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11340 15:37:14.602254 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11342 15:37:14.613271 /lava-11331363/1/../bin/lava-test-case
11343 15:37:14.619674 <8>[ 19.051203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11344 15:37:14.620525 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11346 15:37:14.628452 /lava-11331363/1/../bin/lava-test-case
11347 15:37:14.635240 <8>[ 19.065450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11348 15:37:14.636096 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11350 15:37:15.648276 /lava-11331363/1/../bin/lava-test-case
11351 15:37:15.655303 <8>[ 20.085713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11352 15:37:15.656156 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11354 15:37:15.675449 /lava-11331363/1/../bin/lava-tes<8>[ 20.105483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11355 15:37:15.676043 t-case
11356 15:37:15.676695 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11358 15:37:16.688202 /lava-11331363/1/../bin/lava-test-case
11359 15:37:16.695447 <8>[ 21.126635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11360 15:37:16.695744 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11362 15:37:16.706929 /lava-11331363/1/../bin/lava-test-case
11363 15:37:16.716989 <8>[ 21.146440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11364 15:37:16.717246 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11366 15:37:17.730568 /lava-11331363/1/../bin/lava-test-case
11367 15:37:17.736863 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11369 15:37:17.740137 <8>[ 22.169679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11370 15:37:17.749111 /lava-11331363/1/../bin/lava-test-case
11371 15:37:17.755433 <8>[ 22.187329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11372 15:37:17.755795 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11374 15:37:18.770253 /lava-11331363/1/../bin/lava-test-case
11375 15:37:18.776381 <8>[ 23.208099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11376 15:37:18.777207 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11378 15:37:18.797227 /lava-11331363/1/../bin/lava-tes<8>[ 23.227757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11379 15:37:18.797782 t-case
11380 15:37:18.798421 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11382 15:37:19.810312 /lava-11331363/1/../bin/lava-test-case
11383 15:37:19.816838 <8>[ 24.250444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11384 15:37:19.817740 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11386 15:37:19.828628 /lava-11331363/1/../bin/lava-test-case
11387 15:37:19.834707 <8>[ 24.265947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11388 15:37:19.835651 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11390 15:37:20.849611 /lava-11331363/1/../bin/lava-test-case
11391 15:37:20.855585 <8>[ 25.287154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11392 15:37:20.856273 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11394 15:37:20.867915 /lava-11331363/1/../bin/lava-test-case
11395 15:37:20.874557 <8>[ 25.307152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11396 15:37:20.875295 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11398 15:37:21.893940 /lava-11331363/1/../bin/lava-test-case
11399 15:37:21.900706 <8>[ 26.332318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11400 15:37:21.901464 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11402 15:37:21.912462 /lava-11331363/1/../bin/lava-test-case
11403 15:37:21.919186 <8>[ 26.350435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11404 15:37:21.919869 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11406 15:37:21.935588 /lava-11331363/1/../bin/lava-tes<8>[ 26.366341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11407 15:37:21.936115 t-case
11408 15:37:21.936716 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11410 15:37:22.950296 /lava-11331363/1/../bin/lava-test-case
11411 15:37:22.956337 <8>[ 27.388236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11412 15:37:22.957159 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11414 15:37:22.974127 /lava-11331363/1/../bin/lava-tes<8>[ 27.404979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11415 15:37:22.974555 t-case
11416 15:37:22.975267 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11418 15:37:22.988677 /lava-11331363/1/../bin/lava-test-case
11419 15:37:22.995206 <8>[ 27.427825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11420 15:37:22.995883 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11422 15:37:23.006659 /lava-11331363/1/../bin/lava-test-case
11423 15:37:23.013035 <8>[ 27.443960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11424 15:37:23.013712 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11426 15:37:23.031758 /lava-11331363/1/../bin/lava-tes<8>[ 27.462613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11427 15:37:23.032182 t-case
11428 15:37:23.032769 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11430 15:37:23.043703 /lava-11331363/1/../bin/lava-test-case
11431 15:37:23.053552 <8>[ 27.485013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11432 15:37:23.054227 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11434 15:37:23.065015 /lava-11331363/1/../bin/lava-test-case
11435 15:37:23.071359 <8>[ 27.503133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11436 15:37:23.072064 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11438 15:37:23.089033 /lava-11331363/1/../bin/lava-tes<8>[ 27.519810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11439 15:37:23.089471 t-case
11440 15:37:23.090083 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11442 15:37:23.103010 /lava-11331363/1/../bin/lava-test-case
11443 15:37:23.109982 <8>[ 27.543019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11444 15:37:23.110707 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11446 15:37:23.123868 /lava-11331363/1/../bin/lava-test-case
11447 15:37:23.130239 <8>[ 27.563010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11448 15:37:23.130959 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11450 15:37:23.140125 /lava-11331363/1/../bin/lava-test-case
11451 15:37:23.146164 <8>[ 27.578183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11452 15:37:23.146843 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11454 15:37:23.159640 /lava-11331363/1/../bin/lava-test-case
11455 15:37:23.166264 <8>[ 27.598152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11456 15:37:23.167016 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11458 15:37:23.174658 /lava-11331363/1/../bin/lava-test-case
11459 15:37:23.186028 <8>[ 27.617475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11460 15:37:23.186724 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11462 15:37:23.197881 /lava-11331363/1/../bin/lava-test-case
11463 15:37:23.204476 <8>[ 27.636320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11464 15:37:23.205180 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11466 15:37:23.220890 /lava-11331363/1/../bin/lava-tes<8>[ 27.652130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11467 15:37:23.221371 t-case
11468 15:37:23.222236 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11470 15:37:23.242193 /lava-11331363/1/../bin/lava-tes<8>[ 27.673361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11471 15:37:23.242762 t-case
11472 15:37:23.243401 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11474 15:37:23.251608 /lava-11331363/1/../bin/lava-test-case
11475 15:37:23.258348 <8>[ 27.689806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11476 15:37:23.259158 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11478 15:37:23.270254 /lava-11331363/1/../bin/lava-test-case
11479 15:37:23.276889 <8>[ 27.709025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11480 15:37:23.277755 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11482 15:37:23.286117 /lava-11331363/1/../bin/lava-test-case
11483 15:37:23.293610 <8>[ 27.724527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11484 15:37:23.294455 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11486 15:37:23.307449 /lava-11331363/1/../bin/lava-test-case
11487 15:37:23.313871 <8>[ 27.746772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11488 15:37:23.314673 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11490 15:37:23.323070 /lava-11331363/1/../bin/lava-test-case
11491 15:37:23.329881 <8>[ 27.761909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11492 15:37:23.330714 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11494 15:37:24.344022 /lava-11331363/1/../bin/lava-test-case
11495 15:37:24.350504 <8>[ 28.782200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11496 15:37:24.351261 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11498 15:37:25.364142 /lava-11331363/1/../bin/lava-test-case
11499 15:37:25.370761 <8>[ 29.804023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11500 15:37:25.371450 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11502 15:37:25.381881 /lava-11331363/1/../bin/lava-test-case
11503 15:37:25.388227 <8>[ 29.819892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11504 15:37:25.389068 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11506 15:37:25.402834 /lava-11331363/1/../bin/lava-test-case
11507 15:37:25.409159 <8>[ 29.840744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11508 15:37:25.410028 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11510 15:37:25.418914 /lava-11331363/1/../bin/lava-test-case
11511 15:37:25.424992 <8>[ 29.857178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11512 15:37:25.425813 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11514 15:37:25.436929 /lava-11331363/1/../bin/lava-test-case
11515 15:37:25.443388 <8>[ 29.875336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11516 15:37:25.444230 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11518 15:37:25.451209 /lava-11331363/1/../bin/lava-test-case
11519 15:37:25.457997 <8>[ 29.890497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11520 15:37:25.458830 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11522 15:37:25.470554 /lava-11331363/1/../bin/lava-test-case
11523 15:37:25.476044 <8>[ 29.908106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11524 15:37:25.476831 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11526 15:37:25.483873 /lava-11331363/1/../bin/lava-test-case
11527 15:37:25.495193 <8>[ 29.926958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11528 15:37:25.496023 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11530 15:37:25.505997 /lava-11331363/1/../bin/lava-test-case
11531 15:37:25.512741 <8>[ 29.944679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11532 15:37:25.513497 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11534 15:37:25.529625 /lava-11331363/1/../bin/lava-tes<8>[ 29.960471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11535 15:37:25.530109 t-case
11536 15:37:25.530725 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11538 15:37:25.541074 /lava-11331363/1/../bin/lava-test-case
11539 15:37:25.547221 <8>[ 29.978446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11540 15:37:25.547939 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11542 15:37:25.562819 /lava-11331363/1/../bin/lava-tes<8>[ 29.994102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11543 15:37:25.563384 t-case
11544 15:37:25.564032 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11546 15:37:25.573831 /lava-11331363/1/../bin/lava-test-case
11547 15:37:25.579699 <8>[ 30.011405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11548 15:37:25.580665 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11550 15:37:25.593426 /lava-11331363/1/../bin/lava-test-case
11551 15:37:25.599892 <8>[ 30.032472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11552 15:37:25.600661 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11554 15:37:25.610640 /lava-11331363/1/../bin/lava-test-case
11555 15:37:25.617260 <8>[ 30.049289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11556 15:37:25.618063 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11558 15:37:25.626370 /lava-11331363/1/../bin/lava-test-case
11559 15:37:25.633216 <8>[ 30.064487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11560 15:37:25.634034 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11562 15:37:25.647541 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11564 15:37:25.650316 /lava-11331363/1/../bin/lava-tes<8>[ 30.081719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11565 15:37:25.650790 t-case
11566 15:37:25.661128 /lava-11331363/1/../bin/lava-test-case
11567 15:37:25.667349 <8>[ 30.100087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11568 15:37:25.668124 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11570 15:37:25.678321 /lava-11331363/1/../bin/lava-test-case
11571 15:37:25.684926 <8>[ 30.117370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11572 15:37:25.685718 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11574 15:37:25.694463 /lava-11331363/1/../bin/lava-test-case
11575 15:37:25.701113 <8>[ 30.132598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11576 15:37:25.701953 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11578 15:37:25.713167 /lava-11331363/1/../bin/lava-test-case
11579 15:37:25.719743 <8>[ 30.151066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11580 15:37:25.720635 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11582 15:37:26.730999 /lava-11331363/1/../bin/lava-test-case
11583 15:37:26.737222 <8>[ 31.169290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11584 15:37:26.738042 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11586 15:37:27.750909 /lava-11331363/1/../bin/lava-test-case
11587 15:37:27.757292 <8>[ 32.191153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11588 15:37:27.757554 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11589 15:37:27.757641 Bad test result: blocked
11590 15:37:27.767026 /lava-11331363/1/../bin/lava-test-case
11591 15:37:27.773661 <8>[ 32.206553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11592 15:37:27.773933 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11594 15:37:28.790824 /lava-11331363/1/../bin/lava-test-case
11595 15:37:28.797756 <8>[ 33.230791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11596 15:37:28.798015 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11598 15:37:28.805655 /lava-11331363/1/../bin/lava-test-case
11599 15:37:28.812502 <8>[ 33.245067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11600 15:37:28.812750 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11602 15:37:28.827128 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11604 15:37:28.830166 /lava-11331363/1/../bin/lava-tes<8>[ 33.262630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11605 15:37:28.830238 t-case
11606 15:37:28.840016 /lava-11331363/1/../bin/lava-test-case
11607 15:37:28.847057 <8>[ 33.281818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11608 15:37:28.847306 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11610 15:37:28.857328 /lava-11331363/1/../bin/lava-test-case
11611 15:37:28.863790 <8>[ 33.296868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11612 15:37:28.864037 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11614 15:37:28.876473 /lava-11331363/1/../bin/lava-test-case
11615 15:37:28.882816 <8>[ 33.315548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11616 15:37:28.883065 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11618 15:37:28.890519 /lava-11331363/1/../bin/lava-test-case
11619 15:37:28.902048 <8>[ 33.334413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11620 15:37:28.902291 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11622 15:37:29.914884 /lava-11331363/1/../bin/lava-test-case
11623 15:37:29.921530 <8>[ 34.354533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11624 15:37:29.921799 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11626 15:37:29.933036 /lava-11331363/1/../bin/lava-test-case
11627 15:37:29.939727 <8>[ 34.374452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11628 15:37:29.939976 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11630 15:37:30.954254 /lava-11331363/1/../bin/lava-test-case
11631 15:37:30.961087 <8>[ 35.393774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11632 15:37:30.961350 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11634 15:37:30.968847 /lava-11331363/1/../bin/lava-test-case
11635 15:37:30.975436 <8>[ 35.409471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11636 15:37:30.975690 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11638 15:37:31.990068 /lava-11331363/1/../bin/lava-test-case
11639 15:37:31.997180 <8>[ 36.430576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11640 15:37:31.997868 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11642 15:37:32.006270 /lava-11331363/1/../bin/lava-test-case
11643 15:37:32.012498 <8>[ 36.444993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11644 15:37:32.013176 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11646 15:37:33.031095 /lava-11331363/1/../bin/lava-test-case
11647 15:37:33.037623 <8>[ 37.471866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11648 15:37:33.038314 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11650 15:37:33.047474 /lava-11331363/1/../bin/lava-test-case
11651 15:37:33.053948 <8>[ 37.486858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11652 15:37:33.054833 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11654 15:37:33.067274 /lava-11331363/1/../bin/lava-test-case
11655 15:37:33.074264 <8>[ 37.506814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11656 15:37:33.074975 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11658 15:37:33.088833 /lava-11331363/1/../bin/lava-tes<8>[ 37.524200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11659 15:37:33.089502 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11661 15:37:33.092034 t-case
11662 15:37:33.100245 /lava-11331363/1/../bin/lava-test-case
11663 15:37:33.106753 <8>[ 37.539446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11664 15:37:33.107423 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11666 15:37:33.120866 /lava-11331363/1/../bin/lava-tes<8>[ 37.556390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11667 15:37:33.121533 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11669 15:37:33.124314 t-case
11670 15:37:33.135145 /lava-11331363/1/../bin/lava-test-case
11671 15:37:33.144585 <8>[ 37.576357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11672 15:37:33.145264 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11674 15:37:33.155282 /lava-11331363/1/../bin/lava-test-case
11675 15:37:33.161859 <8>[ 37.595238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11676 15:37:33.162538 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11678 15:37:33.173077 /lava-11331363/1/../bin/lava-test-case
11679 15:37:33.179446 <8>[ 37.612409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11680 15:37:33.180114 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11682 15:37:33.190380 /lava-11331363/1/../bin/lava-test-case
11683 15:37:33.196964 <8>[ 37.630158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11684 15:37:33.197632 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11686 15:37:33.201096 + set +x
11687 15:37:33.204532 Received signal: <ENDRUN> 1_bootrr 11331363_1.5.2.3.5
11688 15:37:33.204970 Ending use of test pattern.
11689 15:37:33.205304 Ending test lava.1_bootrr (11331363_1.5.2.3.5), duration 20.38
11691 15:37:33.207794 <8>[ 37.640379] <LAVA_SIGNAL_ENDRUN 1_bootrr 11331363_1.5.2.3.5>
11692 15:37:33.211028 <LAVA_TEST_RUNNER EXIT>
11693 15:37:33.211688 ok: lava_test_shell seems to have completed
11694 15:37:33.216735 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11695 15:37:33.217441 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11696 15:37:33.217875 end: 4 lava-test-retry (duration 00:00:21) [common]
11697 15:37:33.218309 start: 5 finalize (timeout 00:08:04) [common]
11698 15:37:33.218779 start: 5.1 power-off (timeout 00:00:30) [common]
11699 15:37:33.219539 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11700 15:37:33.340637 >> Command sent successfully.
11701 15:37:33.344478 Returned 0 in 0 seconds
11702 15:37:33.445310 end: 5.1 power-off (duration 00:00:00) [common]
11704 15:37:33.447129 start: 5.2 read-feedback (timeout 00:08:03) [common]
11705 15:37:33.448353 Listened to connection for namespace 'common' for up to 1s
11706 15:37:34.448989 Finalising connection for namespace 'common'
11707 15:37:34.449614 Disconnecting from shell: Finalise
11708 15:37:34.450002 / #
11709 15:37:34.550915 end: 5.2 read-feedback (duration 00:00:01) [common]
11710 15:37:34.551534 end: 5 finalize (duration 00:00:01) [common]
11711 15:37:34.552069 Cleaning after the job
11712 15:37:34.552559 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/ramdisk
11713 15:37:34.566823 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/kernel
11714 15:37:34.579473 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/dtb
11715 15:37:34.579646 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331363/tftp-deploy-nz64uxrg/modules
11716 15:37:34.586904 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11331363
11717 15:37:34.632589 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11331363
11718 15:37:34.632753 Job finished correctly