Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 19
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 33
- Errors: 1
1 15:36:08.415892 lava-dispatcher, installed at version: 2023.06
2 15:36:08.416114 start: 0 validate
3 15:36:08.416251 Start time: 2023-08-22 15:36:08.416243+00:00 (UTC)
4 15:36:08.416386 Using caching service: 'http://localhost/cache/?uri=%s'
5 15:36:08.416535 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 15:36:08.683951 Using caching service: 'http://localhost/cache/?uri=%s'
7 15:36:08.684137 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 15:36:23.184094 Using caching service: 'http://localhost/cache/?uri=%s'
9 15:36:23.184258 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 15:36:23.442916 Using caching service: 'http://localhost/cache/?uri=%s'
11 15:36:23.443075 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 15:36:25.700217 validate duration: 17.28
14 15:36:25.700468 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 15:36:25.700564 start: 1.1 download-retry (timeout 00:10:00) [common]
16 15:36:25.700652 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 15:36:25.700781 Not decompressing ramdisk as can be used compressed.
18 15:36:25.700885 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 15:36:25.700968 saving as /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/ramdisk/rootfs.cpio.gz
20 15:36:25.701032 total size: 34390042 (32 MB)
21 15:36:25.966180 progress 0 % (0 MB)
22 15:36:25.975439 progress 5 % (1 MB)
23 15:36:25.984814 progress 10 % (3 MB)
24 15:36:25.994124 progress 15 % (4 MB)
25 15:36:26.003444 progress 20 % (6 MB)
26 15:36:26.012624 progress 25 % (8 MB)
27 15:36:26.021578 progress 30 % (9 MB)
28 15:36:26.030804 progress 35 % (11 MB)
29 15:36:26.039768 progress 40 % (13 MB)
30 15:36:26.048827 progress 45 % (14 MB)
31 15:36:26.057953 progress 50 % (16 MB)
32 15:36:26.067222 progress 55 % (18 MB)
33 15:36:26.076762 progress 60 % (19 MB)
34 15:36:26.086341 progress 65 % (21 MB)
35 15:36:26.095583 progress 70 % (22 MB)
36 15:36:26.105467 progress 75 % (24 MB)
37 15:36:26.115212 progress 80 % (26 MB)
38 15:36:26.125191 progress 85 % (27 MB)
39 15:36:26.134350 progress 90 % (29 MB)
40 15:36:26.143516 progress 95 % (31 MB)
41 15:36:26.152568 progress 100 % (32 MB)
42 15:36:26.152767 32 MB downloaded in 0.45 s (72.60 MB/s)
43 15:36:26.152939 end: 1.1.1 http-download (duration 00:00:00) [common]
45 15:36:26.153182 end: 1.1 download-retry (duration 00:00:00) [common]
46 15:36:26.153272 start: 1.2 download-retry (timeout 00:10:00) [common]
47 15:36:26.153355 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 15:36:26.153508 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 15:36:26.153584 saving as /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/kernel/Image
50 15:36:26.153656 total size: 49220096 (46 MB)
51 15:36:26.153719 No compression specified
52 15:36:26.154860 progress 0 % (0 MB)
53 15:36:26.168224 progress 5 % (2 MB)
54 15:36:26.181358 progress 10 % (4 MB)
55 15:36:26.194447 progress 15 % (7 MB)
56 15:36:26.207741 progress 20 % (9 MB)
57 15:36:26.221005 progress 25 % (11 MB)
58 15:36:26.234235 progress 30 % (14 MB)
59 15:36:26.247595 progress 35 % (16 MB)
60 15:36:26.260998 progress 40 % (18 MB)
61 15:36:26.274381 progress 45 % (21 MB)
62 15:36:26.287989 progress 50 % (23 MB)
63 15:36:26.301455 progress 55 % (25 MB)
64 15:36:26.314944 progress 60 % (28 MB)
65 15:36:26.328332 progress 65 % (30 MB)
66 15:36:26.341659 progress 70 % (32 MB)
67 15:36:26.354795 progress 75 % (35 MB)
68 15:36:26.368164 progress 80 % (37 MB)
69 15:36:26.381367 progress 85 % (39 MB)
70 15:36:26.394567 progress 90 % (42 MB)
71 15:36:26.407443 progress 95 % (44 MB)
72 15:36:26.421003 progress 100 % (46 MB)
73 15:36:26.421215 46 MB downloaded in 0.27 s (175.44 MB/s)
74 15:36:26.421432 end: 1.2.1 http-download (duration 00:00:00) [common]
76 15:36:26.421812 end: 1.2 download-retry (duration 00:00:00) [common]
77 15:36:26.421941 start: 1.3 download-retry (timeout 00:09:59) [common]
78 15:36:26.422069 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 15:36:26.422259 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 15:36:26.422362 saving as /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/dtb/mt8192-asurada-spherion-r0.dtb
81 15:36:26.422454 total size: 47278 (0 MB)
82 15:36:26.422548 No compression specified
83 15:36:26.424156 progress 69 % (0 MB)
84 15:36:26.424481 progress 100 % (0 MB)
85 15:36:26.424680 0 MB downloaded in 0.00 s (20.28 MB/s)
86 15:36:26.424857 end: 1.3.1 http-download (duration 00:00:00) [common]
88 15:36:26.425233 end: 1.3 download-retry (duration 00:00:00) [common]
89 15:36:26.425352 start: 1.4 download-retry (timeout 00:09:59) [common]
90 15:36:26.425467 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 15:36:26.425640 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 15:36:26.425738 saving as /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/modules/modules.tar
93 15:36:26.425839 total size: 8608784 (8 MB)
94 15:36:26.425933 Using unxz to decompress xz
95 15:36:26.430902 progress 0 % (0 MB)
96 15:36:26.453924 progress 5 % (0 MB)
97 15:36:26.479105 progress 10 % (0 MB)
98 15:36:26.507848 progress 15 % (1 MB)
99 15:36:26.536622 progress 20 % (1 MB)
100 15:36:26.565618 progress 25 % (2 MB)
101 15:36:26.595319 progress 30 % (2 MB)
102 15:36:26.622777 progress 35 % (2 MB)
103 15:36:26.652909 progress 40 % (3 MB)
104 15:36:26.679940 progress 45 % (3 MB)
105 15:36:26.709531 progress 50 % (4 MB)
106 15:36:26.737280 progress 55 % (4 MB)
107 15:36:26.764167 progress 60 % (4 MB)
108 15:36:26.789365 progress 65 % (5 MB)
109 15:36:26.817416 progress 70 % (5 MB)
110 15:36:26.846985 progress 75 % (6 MB)
111 15:36:26.875888 progress 80 % (6 MB)
112 15:36:26.909207 progress 85 % (7 MB)
113 15:36:26.937787 progress 90 % (7 MB)
114 15:36:26.964415 progress 95 % (7 MB)
115 15:36:26.990322 progress 100 % (8 MB)
116 15:36:26.996916 8 MB downloaded in 0.57 s (14.38 MB/s)
117 15:36:26.997191 end: 1.4.1 http-download (duration 00:00:01) [common]
119 15:36:26.997614 end: 1.4 download-retry (duration 00:00:01) [common]
120 15:36:26.997751 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 15:36:26.997889 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 15:36:26.998004 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 15:36:26.998133 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 15:36:26.998407 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql
125 15:36:26.998602 makedir: /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin
126 15:36:26.998747 makedir: /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/tests
127 15:36:26.998853 makedir: /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/results
128 15:36:26.998994 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-add-keys
129 15:36:26.999187 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-add-sources
130 15:36:26.999366 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-background-process-start
131 15:36:26.999543 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-background-process-stop
132 15:36:26.999711 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-common-functions
133 15:36:26.999844 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-echo-ipv4
134 15:36:26.999991 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-install-packages
135 15:36:27.000129 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-installed-packages
136 15:36:27.000270 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-os-build
137 15:36:27.000432 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-probe-channel
138 15:36:27.000599 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-probe-ip
139 15:36:27.000770 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-target-ip
140 15:36:27.000933 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-target-mac
141 15:36:27.001104 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-target-storage
142 15:36:27.001279 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-test-case
143 15:36:27.001450 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-test-event
144 15:36:27.001623 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-test-feedback
145 15:36:27.001790 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-test-raise
146 15:36:27.001959 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-test-reference
147 15:36:27.002125 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-test-runner
148 15:36:27.002294 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-test-set
149 15:36:27.002461 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-test-shell
150 15:36:27.002637 Updating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-install-packages (oe)
151 15:36:27.002823 Updating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/bin/lava-installed-packages (oe)
152 15:36:27.002953 Creating /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/environment
153 15:36:27.003069 LAVA metadata
154 15:36:27.003147 - LAVA_JOB_ID=11331361
155 15:36:27.003244 - LAVA_DISPATCHER_IP=192.168.201.1
156 15:36:27.003393 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 15:36:27.003487 skipped lava-vland-overlay
158 15:36:27.003608 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 15:36:27.003695 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 15:36:27.003790 skipped lava-multinode-overlay
161 15:36:27.003868 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 15:36:27.003972 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 15:36:27.004066 Loading test definitions
164 15:36:27.004196 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 15:36:27.004303 Using /lava-11331361 at stage 0
166 15:36:27.004754 uuid=11331361_1.5.2.3.1 testdef=None
167 15:36:27.004885 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 15:36:27.005005 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 15:36:27.005768 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 15:36:27.006142 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 15:36:27.006977 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 15:36:27.007365 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 15:36:27.008115 runner path: /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/0/tests/0_cros-ec test_uuid 11331361_1.5.2.3.1
176 15:36:27.008313 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 15:36:27.008668 Creating lava-test-runner.conf files
179 15:36:27.008762 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11331361/lava-overlay-2r4y5gql/lava-11331361/0 for stage 0
180 15:36:27.008889 - 0_cros-ec
181 15:36:27.009021 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 15:36:27.009146 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 15:36:27.017627 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 15:36:27.017786 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 15:36:27.017908 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 15:36:27.018036 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 15:36:27.018157 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 15:36:28.171024 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 15:36:28.171615 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 15:36:28.171834 extracting modules file /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11331361/extract-overlay-ramdisk-1mdd_c82/ramdisk
191 15:36:28.493038 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 15:36:28.493212 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 15:36:28.493318 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11331361/compress-overlay-wbjnt1em/overlay-1.5.2.4.tar.gz to ramdisk
194 15:36:28.493392 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11331361/compress-overlay-wbjnt1em/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11331361/extract-overlay-ramdisk-1mdd_c82/ramdisk
195 15:36:28.500665 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 15:36:28.500802 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 15:36:28.500895 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 15:36:28.500984 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 15:36:28.501068 Building ramdisk /var/lib/lava/dispatcher/tmp/11331361/extract-overlay-ramdisk-1mdd_c82/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11331361/extract-overlay-ramdisk-1mdd_c82/ramdisk
200 15:36:29.337838 >> 270881 blocks
201 15:36:34.409779 rename /var/lib/lava/dispatcher/tmp/11331361/extract-overlay-ramdisk-1mdd_c82/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/ramdisk/ramdisk.cpio.gz
202 15:36:34.410242 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 15:36:34.410372 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 15:36:34.410475 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 15:36:34.410583 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/kernel/Image'
206 15:36:48.840521 Returned 0 in 14 seconds
207 15:36:48.941132 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/kernel/image.itb
208 15:36:49.653629 output: FIT description: Kernel Image image with one or more FDT blobs
209 15:36:49.653994 output: Created: Tue Aug 22 16:36:49 2023
210 15:36:49.654072 output: Image 0 (kernel-1)
211 15:36:49.654140 output: Description:
212 15:36:49.654202 output: Created: Tue Aug 22 16:36:49 2023
213 15:36:49.654266 output: Type: Kernel Image
214 15:36:49.654327 output: Compression: lzma compressed
215 15:36:49.654385 output: Data Size: 11035343 Bytes = 10776.70 KiB = 10.52 MiB
216 15:36:49.654444 output: Architecture: AArch64
217 15:36:49.654503 output: OS: Linux
218 15:36:49.654558 output: Load Address: 0x00000000
219 15:36:49.654611 output: Entry Point: 0x00000000
220 15:36:49.654664 output: Hash algo: crc32
221 15:36:49.654717 output: Hash value: fe81bcf6
222 15:36:49.654770 output: Image 1 (fdt-1)
223 15:36:49.654822 output: Description: mt8192-asurada-spherion-r0
224 15:36:49.654875 output: Created: Tue Aug 22 16:36:49 2023
225 15:36:49.654928 output: Type: Flat Device Tree
226 15:36:49.654981 output: Compression: uncompressed
227 15:36:49.655033 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 15:36:49.655086 output: Architecture: AArch64
229 15:36:49.655139 output: Hash algo: crc32
230 15:36:49.655191 output: Hash value: cc4352de
231 15:36:49.655242 output: Image 2 (ramdisk-1)
232 15:36:49.655295 output: Description: unavailable
233 15:36:49.655346 output: Created: Tue Aug 22 16:36:49 2023
234 15:36:49.655399 output: Type: RAMDisk Image
235 15:36:49.655452 output: Compression: Unknown Compression
236 15:36:49.655504 output: Data Size: 47512613 Bytes = 46399.04 KiB = 45.31 MiB
237 15:36:49.655558 output: Architecture: AArch64
238 15:36:49.655628 output: OS: Linux
239 15:36:49.655695 output: Load Address: unavailable
240 15:36:49.655750 output: Entry Point: unavailable
241 15:36:49.655802 output: Hash algo: crc32
242 15:36:49.655855 output: Hash value: 7b87bcd0
243 15:36:49.655908 output: Default Configuration: 'conf-1'
244 15:36:49.655960 output: Configuration 0 (conf-1)
245 15:36:49.656012 output: Description: mt8192-asurada-spherion-r0
246 15:36:49.656064 output: Kernel: kernel-1
247 15:36:49.656116 output: Init Ramdisk: ramdisk-1
248 15:36:49.656168 output: FDT: fdt-1
249 15:36:49.656220 output: Loadables: kernel-1
250 15:36:49.656272 output:
251 15:36:49.656476 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 15:36:49.656579 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 15:36:49.656686 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 15:36:49.656779 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 15:36:49.656858 No LXC device requested
256 15:36:49.656938 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 15:36:49.657027 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 15:36:49.657103 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 15:36:49.657175 Checking files for TFTP limit of 4294967296 bytes.
260 15:36:49.657677 end: 1 tftp-deploy (duration 00:00:24) [common]
261 15:36:49.657781 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 15:36:49.657871 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 15:36:49.657992 substitutions:
264 15:36:49.658060 - {DTB}: 11331361/tftp-deploy-7nu3mvel/dtb/mt8192-asurada-spherion-r0.dtb
265 15:36:49.658124 - {INITRD}: 11331361/tftp-deploy-7nu3mvel/ramdisk/ramdisk.cpio.gz
266 15:36:49.658182 - {KERNEL}: 11331361/tftp-deploy-7nu3mvel/kernel/Image
267 15:36:49.658239 - {LAVA_MAC}: None
268 15:36:49.658295 - {PRESEED_CONFIG}: None
269 15:36:49.658349 - {PRESEED_LOCAL}: None
270 15:36:49.658403 - {RAMDISK}: 11331361/tftp-deploy-7nu3mvel/ramdisk/ramdisk.cpio.gz
271 15:36:49.658458 - {ROOT_PART}: None
272 15:36:49.658511 - {ROOT}: None
273 15:36:49.658564 - {SERVER_IP}: 192.168.201.1
274 15:36:49.658617 - {TEE}: None
275 15:36:49.658672 Parsed boot commands:
276 15:36:49.658725 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 15:36:49.658919 Parsed boot commands: tftpboot 192.168.201.1 11331361/tftp-deploy-7nu3mvel/kernel/image.itb 11331361/tftp-deploy-7nu3mvel/kernel/cmdline
278 15:36:49.659011 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 15:36:49.659099 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 15:36:49.659197 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 15:36:49.659285 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 15:36:49.659356 Not connected, no need to disconnect.
283 15:36:49.659430 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 15:36:49.659509 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 15:36:49.659579 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 15:36:49.663929 Setting prompt string to ['lava-test: # ']
287 15:36:49.664319 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 15:36:49.664437 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 15:36:49.664547 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 15:36:49.664636 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 15:36:49.664841 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 15:36:54.790277 >> Command sent successfully.
293 15:36:54.792868 Returned 0 in 5 seconds
294 15:36:54.893256 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 15:36:54.893686 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 15:36:54.893818 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 15:36:54.893939 Setting prompt string to 'Starting depthcharge on Spherion...'
299 15:36:54.894041 Changing prompt to 'Starting depthcharge on Spherion...'
300 15:36:54.894145 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 15:36:54.894525 [Enter `^Ec?' for help]
302 15:36:55.066604
303 15:36:55.066767
304 15:36:55.066875 F0: 102B 0000
305 15:36:55.066973
306 15:36:55.067071 F3: 1001 0000 [0200]
307 15:36:55.069994
308 15:36:55.070102 F3: 1001 0000
309 15:36:55.070196
310 15:36:55.070286 F7: 102D 0000
311 15:36:55.070378
312 15:36:55.073169 F1: 0000 0000
313 15:36:55.073263
314 15:36:55.073358 V0: 0000 0000 [0001]
315 15:36:55.073452
316 15:36:55.076868 00: 0007 8000
317 15:36:55.076957
318 15:36:55.077027 01: 0000 0000
319 15:36:55.077092
320 15:36:55.080205 BP: 0C00 0209 [0000]
321 15:36:55.080318
322 15:36:55.080415 G0: 1182 0000
323 15:36:55.080506
324 15:36:55.083433 EC: 0000 0021 [4000]
325 15:36:55.083545
326 15:36:55.083653 S7: 0000 0000 [0000]
327 15:36:55.083749
328 15:36:55.087115 CC: 0000 0000 [0001]
329 15:36:55.087228
330 15:36:55.087325 T0: 0000 0040 [010F]
331 15:36:55.087425
332 15:36:55.087526 Jump to BL
333 15:36:55.087631
334 15:36:55.114339
335 15:36:55.114484
336 15:36:55.114582
337 15:36:55.121187 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 15:36:55.124963 ARM64: Exception handlers installed.
339 15:36:55.128613 ARM64: Testing exception
340 15:36:55.131586 ARM64: Done test exception
341 15:36:55.138220 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 15:36:55.148494 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 15:36:55.155320 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 15:36:55.165384 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 15:36:55.172410 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 15:36:55.178705 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 15:36:55.190894 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 15:36:55.197375 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 15:36:55.216675 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 15:36:55.219978 WDT: Last reset was cold boot
351 15:36:55.223056 SPI1(PAD0) initialized at 2873684 Hz
352 15:36:55.226247 SPI5(PAD0) initialized at 992727 Hz
353 15:36:55.230190 VBOOT: Loading verstage.
354 15:36:55.236587 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 15:36:55.239976 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 15:36:55.243782 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 15:36:55.246951 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 15:36:55.254161 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 15:36:55.260607 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 15:36:55.271644 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 15:36:55.271731
362 15:36:55.271805
363 15:36:55.282084 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 15:36:55.285778 ARM64: Exception handlers installed.
365 15:36:55.288974 ARM64: Testing exception
366 15:36:55.289063 ARM64: Done test exception
367 15:36:55.292324 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 15:36:55.298871 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 15:36:55.312194 Probing TPM: . done!
370 15:36:55.312285 TPM ready after 0 ms
371 15:36:55.320670 Connected to device vid:did:rid of 1ae0:0028:00
372 15:36:55.327375 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 15:36:55.386133 Initialized TPM device CR50 revision 0
374 15:36:55.398448 tlcl_send_startup: Startup return code is 0
375 15:36:55.398563 TPM: setup succeeded
376 15:36:55.410072 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 15:36:55.418435 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 15:36:55.430816 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 15:36:55.440607 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 15:36:55.444355 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 15:36:55.448103 in-header: 03 07 00 00 08 00 00 00
382 15:36:55.452042 in-data: aa e4 47 04 13 02 00 00
383 15:36:55.452134 Chrome EC: UHEPI supported
384 15:36:55.459514 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 15:36:55.464163 in-header: 03 95 00 00 08 00 00 00
386 15:36:55.467677 in-data: 18 20 20 08 00 00 00 00
387 15:36:55.467772 Phase 1
388 15:36:55.471467 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 15:36:55.479101 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 15:36:55.486341 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 15:36:55.486430 Recovery requested (1009000e)
392 15:36:55.498973 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 15:36:55.502643 tlcl_extend: response is 0
394 15:36:55.511520 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 15:36:55.516737 tlcl_extend: response is 0
396 15:36:55.523596 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 15:36:55.543847 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 15:36:55.550740 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 15:36:55.550835
400 15:36:55.550902
401 15:36:55.560657 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 15:36:55.563964 ARM64: Exception handlers installed.
403 15:36:55.567164 ARM64: Testing exception
404 15:36:55.567272 ARM64: Done test exception
405 15:36:55.589293 pmic_efuse_setting: Set efuses in 11 msecs
406 15:36:55.592438 pmwrap_interface_init: Select PMIF_VLD_RDY
407 15:36:55.599353 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 15:36:55.602544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 15:36:55.609713 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 15:36:55.613666 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 15:36:55.617597 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 15:36:55.624711 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 15:36:55.628486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 15:36:55.632528 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 15:36:55.636195 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 15:36:55.644055 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 15:36:55.647834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 15:36:55.651903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 15:36:55.655303 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 15:36:55.662769 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 15:36:55.666490 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 15:36:55.673826 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 15:36:55.677752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 15:36:55.684817 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 15:36:55.689063 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 15:36:55.696315 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 15:36:55.699980 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 15:36:55.707721 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 15:36:55.711739 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 15:36:55.718694 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 15:36:55.722512 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 15:36:55.730221 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 15:36:55.733946 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 15:36:55.737253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 15:36:55.744547 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 15:36:55.748515 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 15:36:55.752276 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 15:36:55.759317 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 15:36:55.763312 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 15:36:55.766789 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 15:36:55.774207 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 15:36:55.778164 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 15:36:55.785628 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 15:36:55.789249 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 15:36:55.793021 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 15:36:55.796755 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 15:36:55.800526 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 15:36:55.807784 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 15:36:55.811696 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 15:36:55.815541 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 15:36:55.819304 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 15:36:55.823175 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 15:36:55.826498 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 15:36:55.830437 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 15:36:55.838110 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 15:36:55.841379 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 15:36:55.845078 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 15:36:55.852626 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 15:36:55.859768 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 15:36:55.867345 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 15:36:55.874948 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 15:36:55.882200 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 15:36:55.886100 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 15:36:55.889638 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 15:36:55.897068 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 15:36:55.901030 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18
467 15:36:55.908127 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 15:36:55.911792 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 15:36:55.915585 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 15:36:55.927102 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 15:36:55.936276 [RTC]rtc_get_frequency_meter,154: input=23, output=941
472 15:36:55.946325 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 15:36:55.955308 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 15:36:55.964999 [RTC]rtc_get_frequency_meter,154: input=16, output=781
475 15:36:55.975171 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 15:36:55.984910 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 15:36:55.987995 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 15:36:55.992179 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 15:36:55.995858 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 15:36:56.003371 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 15:36:56.007233 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 15:36:56.010569 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 15:36:56.014505 ADC[4]: Raw value=906942 ID=7
484 15:36:56.014615 ADC[3]: Raw value=213441 ID=1
485 15:36:56.019349 RAM Code: 0x71
486 15:36:56.022994 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 15:36:56.026585 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 15:36:56.034209 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 15:36:56.041097 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 15:36:56.044968 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 15:36:56.048687 in-header: 03 07 00 00 08 00 00 00
492 15:36:56.052436 in-data: aa e4 47 04 13 02 00 00
493 15:36:56.055636 Chrome EC: UHEPI supported
494 15:36:56.063458 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 15:36:56.063569 in-header: 03 95 00 00 08 00 00 00
496 15:36:56.067409 in-data: 18 20 20 08 00 00 00 00
497 15:36:56.071089 MRC: failed to locate region type 0.
498 15:36:56.078622 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 15:36:56.082492 DRAM-K: Running full calibration
500 15:36:56.086284 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 15:36:56.090190 header.status = 0x0
502 15:36:56.093979 header.version = 0x6 (expected: 0x6)
503 15:36:56.097762 header.size = 0xd00 (expected: 0xd00)
504 15:36:56.097870 header.flags = 0x0
505 15:36:56.104670 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 15:36:56.121841 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 15:36:56.129428 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 15:36:56.133200 dram_init: ddr_geometry: 2
509 15:36:56.133286 [EMI] MDL number = 2
510 15:36:56.136912 [EMI] Get MDL freq = 0
511 15:36:56.136989 dram_init: ddr_type: 0
512 15:36:56.140518 is_discrete_lpddr4: 1
513 15:36:56.144704 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 15:36:56.144787
515 15:36:56.144851
516 15:36:56.144917 [Bian_co] ETT version 0.0.0.1
517 15:36:56.151779 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 15:36:56.151866
519 15:36:56.155288 dramc_set_vcore_voltage set vcore to 650000
520 15:36:56.155402 Read voltage for 800, 4
521 15:36:56.159164 Vio18 = 0
522 15:36:56.159269 Vcore = 650000
523 15:36:56.159364 Vdram = 0
524 15:36:56.159464 Vddq = 0
525 15:36:56.162426 Vmddr = 0
526 15:36:56.162529 dram_init: config_dvfs: 1
527 15:36:56.170322 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 15:36:56.174520 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 15:36:56.178299 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 15:36:56.181656 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 15:36:56.185726 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 15:36:56.189595 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 15:36:56.192937 MEM_TYPE=3, freq_sel=18
534 15:36:56.196039 sv_algorithm_assistance_LP4_1600
535 15:36:56.199911 ============ PULL DRAM RESETB DOWN ============
536 15:36:56.203013 ========== PULL DRAM RESETB DOWN end =========
537 15:36:56.206249 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 15:36:56.209796 ===================================
539 15:36:56.213399 LPDDR4 DRAM CONFIGURATION
540 15:36:56.217333 ===================================
541 15:36:56.217446 EX_ROW_EN[0] = 0x0
542 15:36:56.220519 EX_ROW_EN[1] = 0x0
543 15:36:56.220624 LP4Y_EN = 0x0
544 15:36:56.224886 WORK_FSP = 0x0
545 15:36:56.224989 WL = 0x2
546 15:36:56.229050 RL = 0x2
547 15:36:56.229154 BL = 0x2
548 15:36:56.231982 RPST = 0x0
549 15:36:56.232055 RD_PRE = 0x0
550 15:36:56.235619 WR_PRE = 0x1
551 15:36:56.235707 WR_PST = 0x0
552 15:36:56.238925 DBI_WR = 0x0
553 15:36:56.238999 DBI_RD = 0x0
554 15:36:56.242117 OTF = 0x1
555 15:36:56.245567 ===================================
556 15:36:56.249251 ===================================
557 15:36:56.249342 ANA top config
558 15:36:56.252241 ===================================
559 15:36:56.255782 DLL_ASYNC_EN = 0
560 15:36:56.258678 ALL_SLAVE_EN = 1
561 15:36:56.258780 NEW_RANK_MODE = 1
562 15:36:56.262913 DLL_IDLE_MODE = 1
563 15:36:56.265383 LP45_APHY_COMB_EN = 1
564 15:36:56.268931 TX_ODT_DIS = 1
565 15:36:56.269035 NEW_8X_MODE = 1
566 15:36:56.272690 ===================================
567 15:36:56.276621 ===================================
568 15:36:56.279570 data_rate = 1600
569 15:36:56.282766 CKR = 1
570 15:36:56.286049 DQ_P2S_RATIO = 8
571 15:36:56.289263 ===================================
572 15:36:56.292621 CA_P2S_RATIO = 8
573 15:36:56.292722 DQ_CA_OPEN = 0
574 15:36:56.296393 DQ_SEMI_OPEN = 0
575 15:36:56.299705 CA_SEMI_OPEN = 0
576 15:36:56.302974 CA_FULL_RATE = 0
577 15:36:56.306247 DQ_CKDIV4_EN = 1
578 15:36:56.309519 CA_CKDIV4_EN = 1
579 15:36:56.309617 CA_PREDIV_EN = 0
580 15:36:56.312712 PH8_DLY = 0
581 15:36:56.316344 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 15:36:56.319755 DQ_AAMCK_DIV = 4
583 15:36:56.322972 CA_AAMCK_DIV = 4
584 15:36:56.323065 CA_ADMCK_DIV = 4
585 15:36:56.326179 DQ_TRACK_CA_EN = 0
586 15:36:56.330017 CA_PICK = 800
587 15:36:56.333048 CA_MCKIO = 800
588 15:36:56.336849 MCKIO_SEMI = 0
589 15:36:56.340426 PLL_FREQ = 3068
590 15:36:56.340504 DQ_UI_PI_RATIO = 32
591 15:36:56.343968 CA_UI_PI_RATIO = 0
592 15:36:56.348284 ===================================
593 15:36:56.351469 ===================================
594 15:36:56.355337 memory_type:LPDDR4
595 15:36:56.355445 GP_NUM : 10
596 15:36:56.359194 SRAM_EN : 1
597 15:36:56.359298 MD32_EN : 0
598 15:36:56.362923 ===================================
599 15:36:56.366538 [ANA_INIT] >>>>>>>>>>>>>>
600 15:36:56.370238 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 15:36:56.370360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 15:36:56.373305 ===================================
603 15:36:56.376468 data_rate = 1600,PCW = 0X7600
604 15:36:56.379944 ===================================
605 15:36:56.383511 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 15:36:56.390241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 15:36:56.396931 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 15:36:56.400176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 15:36:56.403402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 15:36:56.406591 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 15:36:56.409934 [ANA_INIT] flow start
612 15:36:56.410009 [ANA_INIT] PLL >>>>>>>>
613 15:36:56.413840 [ANA_INIT] PLL <<<<<<<<
614 15:36:56.417072 [ANA_INIT] MIDPI >>>>>>>>
615 15:36:56.417155 [ANA_INIT] MIDPI <<<<<<<<
616 15:36:56.420269 [ANA_INIT] DLL >>>>>>>>
617 15:36:56.423380 [ANA_INIT] flow end
618 15:36:56.426852 ============ LP4 DIFF to SE enter ============
619 15:36:56.430453 ============ LP4 DIFF to SE exit ============
620 15:36:56.433598 [ANA_INIT] <<<<<<<<<<<<<
621 15:36:56.437390 [Flow] Enable top DCM control >>>>>
622 15:36:56.440354 [Flow] Enable top DCM control <<<<<
623 15:36:56.443453 Enable DLL master slave shuffle
624 15:36:56.446760 ==============================================================
625 15:36:56.450189 Gating Mode config
626 15:36:56.456967 ==============================================================
627 15:36:56.457083 Config description:
628 15:36:56.467397 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 15:36:56.473453 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 15:36:56.476695 SELPH_MODE 0: By rank 1: By Phase
631 15:36:56.483784 ==============================================================
632 15:36:56.487331 GAT_TRACK_EN = 1
633 15:36:56.490213 RX_GATING_MODE = 2
634 15:36:56.493574 RX_GATING_TRACK_MODE = 2
635 15:36:56.496788 SELPH_MODE = 1
636 15:36:56.500442 PICG_EARLY_EN = 1
637 15:36:56.500573 VALID_LAT_VALUE = 1
638 15:36:56.507188 ==============================================================
639 15:36:56.510489 Enter into Gating configuration >>>>
640 15:36:56.513699 Exit from Gating configuration <<<<
641 15:36:56.517100 Enter into DVFS_PRE_config >>>>>
642 15:36:56.527192 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 15:36:56.530433 Exit from DVFS_PRE_config <<<<<
644 15:36:56.534063 Enter into PICG configuration >>>>
645 15:36:56.537374 Exit from PICG configuration <<<<
646 15:36:56.540892 [RX_INPUT] configuration >>>>>
647 15:36:56.544034 [RX_INPUT] configuration <<<<<
648 15:36:56.547127 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 15:36:56.554294 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 15:36:56.560859 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 15:36:56.567572 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 15:36:56.574073 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 15:36:56.577194 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 15:36:56.584011 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 15:36:56.587239 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 15:36:56.590537 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 15:36:56.594362 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 15:36:56.597525 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 15:36:56.604423 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 15:36:56.607426 ===================================
661 15:36:56.607516 LPDDR4 DRAM CONFIGURATION
662 15:36:56.610996 ===================================
663 15:36:56.613891 EX_ROW_EN[0] = 0x0
664 15:36:56.617312 EX_ROW_EN[1] = 0x0
665 15:36:56.617397 LP4Y_EN = 0x0
666 15:36:56.620507 WORK_FSP = 0x0
667 15:36:56.620591 WL = 0x2
668 15:36:56.624075 RL = 0x2
669 15:36:56.624171 BL = 0x2
670 15:36:56.627294 RPST = 0x0
671 15:36:56.627401 RD_PRE = 0x0
672 15:36:56.631255 WR_PRE = 0x1
673 15:36:56.631337 WR_PST = 0x0
674 15:36:56.634542 DBI_WR = 0x0
675 15:36:56.634625 DBI_RD = 0x0
676 15:36:56.637691 OTF = 0x1
677 15:36:56.640777 ===================================
678 15:36:56.644293 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 15:36:56.647781 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 15:36:56.654445 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 15:36:56.657437 ===================================
682 15:36:56.657551 LPDDR4 DRAM CONFIGURATION
683 15:36:56.661287 ===================================
684 15:36:56.664224 EX_ROW_EN[0] = 0x10
685 15:36:56.664325 EX_ROW_EN[1] = 0x0
686 15:36:56.667834 LP4Y_EN = 0x0
687 15:36:56.667932 WORK_FSP = 0x0
688 15:36:56.673397 WL = 0x2
689 15:36:56.673523 RL = 0x2
690 15:36:56.674811 BL = 0x2
691 15:36:56.674886 RPST = 0x0
692 15:36:56.678019 RD_PRE = 0x0
693 15:36:56.681238 WR_PRE = 0x1
694 15:36:56.681338 WR_PST = 0x0
695 15:36:56.684344 DBI_WR = 0x0
696 15:36:56.684416 DBI_RD = 0x0
697 15:36:56.688044 OTF = 0x1
698 15:36:56.691244 ===================================
699 15:36:56.694468 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 15:36:56.699754 nWR fixed to 40
701 15:36:56.703010 [ModeRegInit_LP4] CH0 RK0
702 15:36:56.703096 [ModeRegInit_LP4] CH0 RK1
703 15:36:56.706222 [ModeRegInit_LP4] CH1 RK0
704 15:36:56.710147 [ModeRegInit_LP4] CH1 RK1
705 15:36:56.710244 match AC timing 13
706 15:36:56.716387 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 15:36:56.719520 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 15:36:56.723251 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 15:36:56.729797 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 15:36:56.732843 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 15:36:56.732948 [EMI DOE] emi_dcm 0
712 15:36:56.739815 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 15:36:56.739896 ==
714 15:36:56.743041 Dram Type= 6, Freq= 0, CH_0, rank 0
715 15:36:56.747101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 15:36:56.747222 ==
717 15:36:56.753247 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 15:36:56.756412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 15:36:56.766898 [CA 0] Center 36 (6~67) winsize 62
720 15:36:56.770446 [CA 1] Center 36 (6~67) winsize 62
721 15:36:56.774050 [CA 2] Center 34 (4~65) winsize 62
722 15:36:56.777487 [CA 3] Center 33 (3~64) winsize 62
723 15:36:56.780832 [CA 4] Center 33 (2~64) winsize 63
724 15:36:56.783996 [CA 5] Center 32 (3~62) winsize 60
725 15:36:56.784078
726 15:36:56.787240 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 15:36:56.787322
728 15:36:56.790373 [CATrainingPosCal] consider 1 rank data
729 15:36:56.793608 u2DelayCellTimex100 = 270/100 ps
730 15:36:56.797472 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 15:36:56.800532 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 15:36:56.807010 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 15:36:56.810876 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 15:36:56.814124 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
735 15:36:56.817412 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 15:36:56.817494
737 15:36:56.820538 CA PerBit enable=1, Macro0, CA PI delay=32
738 15:36:56.820623
739 15:36:56.823786 [CBTSetCACLKResult] CA Dly = 32
740 15:36:56.823870 CS Dly: 4 (0~35)
741 15:36:56.826923 ==
742 15:36:56.827005 Dram Type= 6, Freq= 0, CH_0, rank 1
743 15:36:56.833457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 15:36:56.833573 ==
745 15:36:56.837091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 15:36:56.844200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 15:36:56.853323 [CA 0] Center 36 (6~67) winsize 62
748 15:36:56.856781 [CA 1] Center 36 (6~67) winsize 62
749 15:36:56.860015 [CA 2] Center 34 (3~65) winsize 63
750 15:36:56.863200 [CA 3] Center 33 (3~64) winsize 62
751 15:36:56.867094 [CA 4] Center 33 (3~63) winsize 61
752 15:36:56.870204 [CA 5] Center 32 (2~63) winsize 62
753 15:36:56.870288
754 15:36:56.873572 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 15:36:56.873688
756 15:36:56.877038 [CATrainingPosCal] consider 2 rank data
757 15:36:56.879992 u2DelayCellTimex100 = 270/100 ps
758 15:36:56.883440 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 15:36:56.886453 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 15:36:56.893511 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 15:36:56.896611 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 15:36:56.900559 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 15:36:56.903238 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 15:36:56.903326
765 15:36:56.907287 CA PerBit enable=1, Macro0, CA PI delay=32
766 15:36:56.907370
767 15:36:56.910021 [CBTSetCACLKResult] CA Dly = 32
768 15:36:56.910103 CS Dly: 4 (0~36)
769 15:36:56.910170
770 15:36:56.914025 ----->DramcWriteLeveling(PI) begin...
771 15:36:56.914108 ==
772 15:36:56.917451 Dram Type= 6, Freq= 0, CH_0, rank 0
773 15:36:56.924567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 15:36:56.924678 ==
775 15:36:56.924747 Write leveling (Byte 0): 32 => 32
776 15:36:56.928400 Write leveling (Byte 1): 28 => 28
777 15:36:56.931681 DramcWriteLeveling(PI) end<-----
778 15:36:56.931806
779 15:36:56.931942 ==
780 15:36:56.934994 Dram Type= 6, Freq= 0, CH_0, rank 0
781 15:36:56.938128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 15:36:56.941236 ==
783 15:36:56.941357 [Gating] SW mode calibration
784 15:36:56.948851 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 15:36:56.955295 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 15:36:56.959121 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 15:36:56.962105 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 15:36:56.968769 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 15:36:56.972378 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 15:36:56.975390 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 15:36:56.982141 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 15:36:56.985952 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 15:36:56.988970 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 15:36:56.995346 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 15:36:56.999155 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 15:36:57.002241 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 15:36:57.008760 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 15:36:57.012052 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 15:36:57.015891 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 15:36:57.022468 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 15:36:57.025762 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 15:36:57.028937 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 15:36:57.032205 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 15:36:57.038652 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
805 15:36:57.042568 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 15:36:57.045751 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 15:36:57.052381 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 15:36:57.055632 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 15:36:57.058868 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 15:36:57.065972 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 15:36:57.069099 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 15:36:57.072256 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
813 15:36:57.079202 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
814 15:36:57.082600 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 15:36:57.086184 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 15:36:57.092271 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 15:36:57.096017 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 15:36:57.099090 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 15:36:57.106014 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
820 15:36:57.109558 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
821 15:36:57.112591 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
822 15:36:57.115794 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 15:36:57.122774 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 15:36:57.125948 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 15:36:57.129261 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 15:36:57.136323 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 15:36:57.139480 0 11 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
828 15:36:57.142733 0 11 8 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)
829 15:36:57.149838 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
830 15:36:57.153074 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 15:36:57.156134 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 15:36:57.162978 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 15:36:57.166253 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 15:36:57.169974 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 15:36:57.173095 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 15:36:57.179508 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 15:36:57.182655 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 15:36:57.186406 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 15:36:57.192565 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 15:36:57.196209 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 15:36:57.199435 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 15:36:57.206273 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 15:36:57.209458 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 15:36:57.213414 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 15:36:57.219716 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 15:36:57.223025 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 15:36:57.226280 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 15:36:57.232729 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 15:36:57.236596 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 15:36:57.239847 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 15:36:57.246268 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 15:36:57.249978 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 15:36:57.253041 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 15:36:57.256356 Total UI for P1: 0, mck2ui 16
855 15:36:57.260184 best dqsien dly found for B0: ( 0, 14, 6)
856 15:36:57.263260 Total UI for P1: 0, mck2ui 16
857 15:36:57.266885 best dqsien dly found for B1: ( 0, 14, 8)
858 15:36:57.270630 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 15:36:57.273747 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 15:36:57.273829
861 15:36:57.276917 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 15:36:57.280144 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 15:36:57.283891 [Gating] SW calibration Done
864 15:36:57.283972 ==
865 15:36:57.287125 Dram Type= 6, Freq= 0, CH_0, rank 0
866 15:36:57.290360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 15:36:57.290441 ==
868 15:36:57.293513 RX Vref Scan: 0
869 15:36:57.293590
870 15:36:57.297388 RX Vref 0 -> 0, step: 1
871 15:36:57.297472
872 15:36:57.297542 RX Delay -130 -> 252, step: 16
873 15:36:57.303557 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 15:36:57.307229 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 15:36:57.310500 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 15:36:57.314258 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 15:36:57.317074 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 15:36:57.324128 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 15:36:57.327008 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 15:36:57.330518 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 15:36:57.334116 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 15:36:57.337063 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
883 15:36:57.344104 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 15:36:57.347300 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 15:36:57.350626 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 15:36:57.353912 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 15:36:57.357188 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 15:36:57.364249 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 15:36:57.364339 ==
890 15:36:57.367478 Dram Type= 6, Freq= 0, CH_0, rank 0
891 15:36:57.370646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 15:36:57.370752 ==
893 15:36:57.370823 DQS Delay:
894 15:36:57.374292 DQS0 = 0, DQS1 = 0
895 15:36:57.374399 DQM Delay:
896 15:36:57.377527 DQM0 = 89, DQM1 = 82
897 15:36:57.377603 DQ Delay:
898 15:36:57.380695 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 15:36:57.384417 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 15:36:57.387416 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
901 15:36:57.390742 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
902 15:36:57.390850
903 15:36:57.390942
904 15:36:57.391044 ==
905 15:36:57.393985 Dram Type= 6, Freq= 0, CH_0, rank 0
906 15:36:57.397805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 15:36:57.397884 ==
908 15:36:57.397949
909 15:36:57.398024
910 15:36:57.401092 TX Vref Scan disable
911 15:36:57.404415 == TX Byte 0 ==
912 15:36:57.407462 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 15:36:57.410813 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 15:36:57.414490 == TX Byte 1 ==
915 15:36:57.417461 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
916 15:36:57.420814 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
917 15:36:57.420905 ==
918 15:36:57.424180 Dram Type= 6, Freq= 0, CH_0, rank 0
919 15:36:57.427344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 15:36:57.431027 ==
921 15:36:57.442495 TX Vref=22, minBit 3, minWin=27, winSum=449
922 15:36:57.445772 TX Vref=24, minBit 0, minWin=28, winSum=454
923 15:36:57.449424 TX Vref=26, minBit 0, minWin=28, winSum=457
924 15:36:57.452678 TX Vref=28, minBit 10, minWin=28, winSum=459
925 15:36:57.455919 TX Vref=30, minBit 8, minWin=27, winSum=457
926 15:36:57.459889 TX Vref=32, minBit 8, minWin=27, winSum=452
927 15:36:57.466113 [TxChooseVref] Worse bit 10, Min win 28, Win sum 459, Final Vref 28
928 15:36:57.466219
929 15:36:57.469342 Final TX Range 1 Vref 28
930 15:36:57.469442
931 15:36:57.469543 ==
932 15:36:57.472641 Dram Type= 6, Freq= 0, CH_0, rank 0
933 15:36:57.476263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 15:36:57.476343 ==
935 15:36:57.476406
936 15:36:57.479407
937 15:36:57.479533 TX Vref Scan disable
938 15:36:57.483024 == TX Byte 0 ==
939 15:36:57.486193 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 15:36:57.489315 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 15:36:57.493246 == TX Byte 1 ==
942 15:36:57.496361 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
943 15:36:57.499561 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
944 15:36:57.502753
945 15:36:57.502862 [DATLAT]
946 15:36:57.502991 Freq=800, CH0 RK0
947 15:36:57.503078
948 15:36:57.505999 DATLAT Default: 0xa
949 15:36:57.506125 0, 0xFFFF, sum = 0
950 15:36:57.509863 1, 0xFFFF, sum = 0
951 15:36:57.509968 2, 0xFFFF, sum = 0
952 15:36:57.513066 3, 0xFFFF, sum = 0
953 15:36:57.513144 4, 0xFFFF, sum = 0
954 15:36:57.516327 5, 0xFFFF, sum = 0
955 15:36:57.516415 6, 0xFFFF, sum = 0
956 15:36:57.519467 7, 0xFFFF, sum = 0
957 15:36:57.519587 8, 0xFFFF, sum = 0
958 15:36:57.522675 9, 0x0, sum = 1
959 15:36:57.522771 10, 0x0, sum = 2
960 15:36:57.526660 11, 0x0, sum = 3
961 15:36:57.526760 12, 0x0, sum = 4
962 15:36:57.529665 best_step = 10
963 15:36:57.529769
964 15:36:57.529858 ==
965 15:36:57.532787 Dram Type= 6, Freq= 0, CH_0, rank 0
966 15:36:57.536384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 15:36:57.536459 ==
968 15:36:57.539818 RX Vref Scan: 1
969 15:36:57.539909
970 15:36:57.539976 Set Vref Range= 32 -> 127
971 15:36:57.540064
972 15:36:57.542716 RX Vref 32 -> 127, step: 1
973 15:36:57.542797
974 15:36:57.546131 RX Delay -79 -> 252, step: 8
975 15:36:57.546222
976 15:36:57.549699 Set Vref, RX VrefLevel [Byte0]: 32
977 15:36:57.553220 [Byte1]: 32
978 15:36:57.553297
979 15:36:57.556641 Set Vref, RX VrefLevel [Byte0]: 33
980 15:36:57.559486 [Byte1]: 33
981 15:36:57.562944
982 15:36:57.563050 Set Vref, RX VrefLevel [Byte0]: 34
983 15:36:57.566331 [Byte1]: 34
984 15:36:57.570560
985 15:36:57.570644 Set Vref, RX VrefLevel [Byte0]: 35
986 15:36:57.573907 [Byte1]: 35
987 15:36:57.578332
988 15:36:57.578407 Set Vref, RX VrefLevel [Byte0]: 36
989 15:36:57.581527 [Byte1]: 36
990 15:36:57.585948
991 15:36:57.586028 Set Vref, RX VrefLevel [Byte0]: 37
992 15:36:57.589204 [Byte1]: 37
993 15:36:57.593484
994 15:36:57.593564 Set Vref, RX VrefLevel [Byte0]: 38
995 15:36:57.596939 [Byte1]: 38
996 15:36:57.601284
997 15:36:57.601368 Set Vref, RX VrefLevel [Byte0]: 39
998 15:36:57.604479 [Byte1]: 39
999 15:36:57.608399
1000 15:36:57.608478 Set Vref, RX VrefLevel [Byte0]: 40
1001 15:36:57.611663 [Byte1]: 40
1002 15:36:57.615576
1003 15:36:57.618807 Set Vref, RX VrefLevel [Byte0]: 41
1004 15:36:57.618887 [Byte1]: 41
1005 15:36:57.623355
1006 15:36:57.623433 Set Vref, RX VrefLevel [Byte0]: 42
1007 15:36:57.626586 [Byte1]: 42
1008 15:36:57.631329
1009 15:36:57.631404 Set Vref, RX VrefLevel [Byte0]: 43
1010 15:36:57.634527 [Byte1]: 43
1011 15:36:57.638956
1012 15:36:57.639037 Set Vref, RX VrefLevel [Byte0]: 44
1013 15:36:57.642007 [Byte1]: 44
1014 15:36:57.646470
1015 15:36:57.646548 Set Vref, RX VrefLevel [Byte0]: 45
1016 15:36:57.649413 [Byte1]: 45
1017 15:36:57.653607
1018 15:36:57.653688 Set Vref, RX VrefLevel [Byte0]: 46
1019 15:36:57.656750 [Byte1]: 46
1020 15:36:57.661241
1021 15:36:57.661318 Set Vref, RX VrefLevel [Byte0]: 47
1022 15:36:57.664327 [Byte1]: 47
1023 15:36:57.669146
1024 15:36:57.669244 Set Vref, RX VrefLevel [Byte0]: 48
1025 15:36:57.672050 [Byte1]: 48
1026 15:36:57.676098
1027 15:36:57.676178 Set Vref, RX VrefLevel [Byte0]: 49
1028 15:36:57.679777 [Byte1]: 49
1029 15:36:57.684171
1030 15:36:57.684260 Set Vref, RX VrefLevel [Byte0]: 50
1031 15:36:57.687351 [Byte1]: 50
1032 15:36:57.691574
1033 15:36:57.691690 Set Vref, RX VrefLevel [Byte0]: 51
1034 15:36:57.694653 [Byte1]: 51
1035 15:36:57.699052
1036 15:36:57.699129 Set Vref, RX VrefLevel [Byte0]: 52
1037 15:36:57.702250 [Byte1]: 52
1038 15:36:57.706943
1039 15:36:57.707019 Set Vref, RX VrefLevel [Byte0]: 53
1040 15:36:57.710190 [Byte1]: 53
1041 15:36:57.713896
1042 15:36:57.713982 Set Vref, RX VrefLevel [Byte0]: 54
1043 15:36:57.717133 [Byte1]: 54
1044 15:36:57.721629
1045 15:36:57.721740 Set Vref, RX VrefLevel [Byte0]: 55
1046 15:36:57.724778 [Byte1]: 55
1047 15:36:57.729312
1048 15:36:57.729421 Set Vref, RX VrefLevel [Byte0]: 56
1049 15:36:57.732627 [Byte1]: 56
1050 15:36:57.737244
1051 15:36:57.737327 Set Vref, RX VrefLevel [Byte0]: 57
1052 15:36:57.740614 [Byte1]: 57
1053 15:36:57.744231
1054 15:36:57.744314 Set Vref, RX VrefLevel [Byte0]: 58
1055 15:36:57.747480 [Byte1]: 58
1056 15:36:57.751952
1057 15:36:57.752061 Set Vref, RX VrefLevel [Byte0]: 59
1058 15:36:57.755035 [Byte1]: 59
1059 15:36:57.759254
1060 15:36:57.759371 Set Vref, RX VrefLevel [Byte0]: 60
1061 15:36:57.762501 [Byte1]: 60
1062 15:36:57.766754
1063 15:36:57.766837 Set Vref, RX VrefLevel [Byte0]: 61
1064 15:36:57.770514 [Byte1]: 61
1065 15:36:57.774321
1066 15:36:57.774402 Set Vref, RX VrefLevel [Byte0]: 62
1067 15:36:57.778018 [Byte1]: 62
1068 15:36:57.781827
1069 15:36:57.781907 Set Vref, RX VrefLevel [Byte0]: 63
1070 15:36:57.785550 [Byte1]: 63
1071 15:36:57.789615
1072 15:36:57.789694 Set Vref, RX VrefLevel [Byte0]: 64
1073 15:36:57.793097 [Byte1]: 64
1074 15:36:57.797215
1075 15:36:57.797294 Set Vref, RX VrefLevel [Byte0]: 65
1076 15:36:57.800475 [Byte1]: 65
1077 15:36:57.804350
1078 15:36:57.804430 Set Vref, RX VrefLevel [Byte0]: 66
1079 15:36:57.808170 [Byte1]: 66
1080 15:36:57.811964
1081 15:36:57.812040 Set Vref, RX VrefLevel [Byte0]: 67
1082 15:36:57.815240 [Byte1]: 67
1083 15:36:57.819906
1084 15:36:57.819986 Set Vref, RX VrefLevel [Byte0]: 68
1085 15:36:57.823034 [Byte1]: 68
1086 15:36:57.826983
1087 15:36:57.827058 Set Vref, RX VrefLevel [Byte0]: 69
1088 15:36:57.830851 [Byte1]: 69
1089 15:36:57.834614
1090 15:36:57.834691 Set Vref, RX VrefLevel [Byte0]: 70
1091 15:36:57.837790 [Byte1]: 70
1092 15:36:57.842423
1093 15:36:57.842497 Set Vref, RX VrefLevel [Byte0]: 71
1094 15:36:57.845659 [Byte1]: 71
1095 15:36:57.850225
1096 15:36:57.850300 Set Vref, RX VrefLevel [Byte0]: 72
1097 15:36:57.853346 [Byte1]: 72
1098 15:36:57.857273
1099 15:36:57.857348 Set Vref, RX VrefLevel [Byte0]: 73
1100 15:36:57.860470 [Byte1]: 73
1101 15:36:57.864994
1102 15:36:57.865068 Set Vref, RX VrefLevel [Byte0]: 74
1103 15:36:57.868025 [Byte1]: 74
1104 15:36:57.872313
1105 15:36:57.872385 Set Vref, RX VrefLevel [Byte0]: 75
1106 15:36:57.875896 [Byte1]: 75
1107 15:36:57.879868
1108 15:36:57.879941 Set Vref, RX VrefLevel [Byte0]: 76
1109 15:36:57.883126 [Byte1]: 76
1110 15:36:57.887415
1111 15:36:57.887494 Set Vref, RX VrefLevel [Byte0]: 77
1112 15:36:57.891006 [Byte1]: 77
1113 15:36:57.895427
1114 15:36:57.895506 Set Vref, RX VrefLevel [Byte0]: 78
1115 15:36:57.898381 [Byte1]: 78
1116 15:36:57.902591
1117 15:36:57.902670 Set Vref, RX VrefLevel [Byte0]: 79
1118 15:36:57.906073 [Byte1]: 79
1119 15:36:57.910423
1120 15:36:57.910533 Final RX Vref Byte 0 = 57 to rank0
1121 15:36:57.913478 Final RX Vref Byte 1 = 59 to rank0
1122 15:36:57.917065 Final RX Vref Byte 0 = 57 to rank1
1123 15:36:57.920121 Final RX Vref Byte 1 = 59 to rank1==
1124 15:36:57.923975 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 15:36:57.930673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 15:36:57.930755 ==
1127 15:36:57.930820 DQS Delay:
1128 15:36:57.930880 DQS0 = 0, DQS1 = 0
1129 15:36:57.933430 DQM Delay:
1130 15:36:57.933502 DQM0 = 92, DQM1 = 85
1131 15:36:57.936888 DQ Delay:
1132 15:36:57.940726 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1133 15:36:57.944082 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1134 15:36:57.944156 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1135 15:36:57.950648 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1136 15:36:57.950757
1137 15:36:57.950850
1138 15:36:57.957240 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1139 15:36:57.960667 CH0 RK0: MR19=606, MR18=4C43
1140 15:36:57.967256 CH0_RK0: MR19=0x606, MR18=0x4C43, DQSOSC=390, MR23=63, INC=97, DEC=64
1141 15:36:57.967336
1142 15:36:57.970532 ----->DramcWriteLeveling(PI) begin...
1143 15:36:57.970614 ==
1144 15:36:57.973602 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 15:36:57.976848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 15:36:57.976922 ==
1147 15:36:57.980648 Write leveling (Byte 0): 33 => 33
1148 15:36:57.983863 Write leveling (Byte 1): 31 => 31
1149 15:36:57.987123 DramcWriteLeveling(PI) end<-----
1150 15:36:57.987204
1151 15:36:57.987269 ==
1152 15:36:58.030966 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 15:36:58.031101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 15:36:58.031390 ==
1155 15:36:58.031489 [Gating] SW mode calibration
1156 15:36:58.031608 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 15:36:58.031703 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 15:36:58.031792 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 15:36:58.031879 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1160 15:36:58.031979 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1161 15:36:58.032066 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 15:36:58.032163 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 15:36:58.068275 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 15:36:58.068562 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 15:36:58.068665 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 15:36:58.068760 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 15:36:58.068874 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 15:36:58.068967 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 15:36:58.069056 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 15:36:58.072111 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 15:36:58.072188 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 15:36:58.075281 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 15:36:58.079160 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 15:36:58.085410 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 15:36:58.089233 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1176 15:36:58.092577 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1177 15:36:58.095747 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 15:36:58.102155 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 15:36:58.105825 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 15:36:58.108881 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 15:36:58.115512 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 15:36:58.118987 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 15:36:58.122484 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 15:36:58.129027 0 9 8 | B1->B0 | 2e2e 2b2b | 1 1 | (1 1) (0 0)
1185 15:36:58.132254 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 15:36:58.135962 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 15:36:58.142577 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 15:36:58.145783 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 15:36:58.149105 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 15:36:58.155868 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 15:36:58.159807 0 10 4 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
1192 15:36:58.163289 0 10 8 | B1->B0 | 2525 2929 | 0 0 | (0 0) (0 0)
1193 15:36:58.167166 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 15:36:58.170389 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 15:36:58.177977 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 15:36:58.181292 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 15:36:58.184630 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 15:36:58.187935 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 15:36:58.194914 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1200 15:36:58.198194 0 11 8 | B1->B0 | 3c3c 3737 | 0 0 | (0 0) (1 1)
1201 15:36:58.202063 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 15:36:58.208400 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 15:36:58.211700 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 15:36:58.214855 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 15:36:58.221977 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 15:36:58.225070 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 15:36:58.228404 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1208 15:36:58.232181 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1209 15:36:58.238760 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 15:36:58.242143 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 15:36:58.245387 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 15:36:58.252225 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 15:36:58.255255 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 15:36:58.258529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 15:36:58.265647 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 15:36:58.269056 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 15:36:58.272389 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 15:36:58.279117 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 15:36:58.282456 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 15:36:58.285732 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 15:36:58.292306 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 15:36:58.295368 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 15:36:58.299024 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 15:36:58.302403 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1225 15:36:58.308757 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 15:36:58.312431 Total UI for P1: 0, mck2ui 16
1227 15:36:58.315584 best dqsien dly found for B0: ( 0, 14, 8)
1228 15:36:58.318743 Total UI for P1: 0, mck2ui 16
1229 15:36:58.321955 best dqsien dly found for B1: ( 0, 14, 8)
1230 15:36:58.325853 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1231 15:36:58.329134 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1232 15:36:58.329214
1233 15:36:58.332462 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1234 15:36:58.335731 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1235 15:36:58.339438 [Gating] SW calibration Done
1236 15:36:58.339514 ==
1237 15:36:58.342495 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 15:36:58.346108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 15:36:58.346189 ==
1240 15:36:58.348997 RX Vref Scan: 0
1241 15:36:58.349079
1242 15:36:58.349142 RX Vref 0 -> 0, step: 1
1243 15:36:58.349202
1244 15:36:58.352400 RX Delay -130 -> 252, step: 16
1245 15:36:58.355520 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1246 15:36:58.362759 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1247 15:36:58.365737 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1248 15:36:58.369359 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1249 15:36:58.372537 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1250 15:36:58.375735 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1251 15:36:58.382757 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1252 15:36:58.385960 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1253 15:36:58.389224 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1254 15:36:58.392378 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1255 15:36:58.396269 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1256 15:36:58.402432 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1257 15:36:58.406139 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1258 15:36:58.409458 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1259 15:36:58.412712 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1260 15:36:58.416291 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1261 15:36:58.416372 ==
1262 15:36:58.419415 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 15:36:58.426344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 15:36:58.426426 ==
1265 15:36:58.426490 DQS Delay:
1266 15:36:58.429437 DQS0 = 0, DQS1 = 0
1267 15:36:58.429519 DQM Delay:
1268 15:36:58.429584 DQM0 = 92, DQM1 = 82
1269 15:36:58.432756 DQ Delay:
1270 15:36:58.435924 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1271 15:36:58.439373 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1272 15:36:58.442536 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
1273 15:36:58.445861 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1274 15:36:58.445944
1275 15:36:58.446016
1276 15:36:58.446078 ==
1277 15:36:58.449080 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 15:36:58.452392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 15:36:58.452493 ==
1280 15:36:58.452585
1281 15:36:58.452673
1282 15:36:58.456158 TX Vref Scan disable
1283 15:36:58.456259 == TX Byte 0 ==
1284 15:36:58.462795 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1285 15:36:58.466219 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1286 15:36:58.466295 == TX Byte 1 ==
1287 15:36:58.472511 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1288 15:36:58.476159 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1289 15:36:58.476264 ==
1290 15:36:58.479165 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 15:36:58.482775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 15:36:58.482880 ==
1293 15:36:58.497314 TX Vref=22, minBit 10, minWin=27, winSum=449
1294 15:36:58.500516 TX Vref=24, minBit 10, minWin=27, winSum=452
1295 15:36:58.503631 TX Vref=26, minBit 3, minWin=28, winSum=455
1296 15:36:58.506952 TX Vref=28, minBit 8, minWin=28, winSum=460
1297 15:36:58.510082 TX Vref=30, minBit 7, minWin=28, winSum=460
1298 15:36:58.516704 TX Vref=32, minBit 2, minWin=28, winSum=453
1299 15:36:58.520530 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 28
1300 15:36:58.520614
1301 15:36:58.523793 Final TX Range 1 Vref 28
1302 15:36:58.523865
1303 15:36:58.523930 ==
1304 15:36:58.526994 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 15:36:58.530117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 15:36:58.530223 ==
1307 15:36:58.533998
1308 15:36:58.534099
1309 15:36:58.534192 TX Vref Scan disable
1310 15:36:58.537233 == TX Byte 0 ==
1311 15:36:58.540569 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1312 15:36:58.543865 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1313 15:36:58.546993 == TX Byte 1 ==
1314 15:36:58.550333 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1315 15:36:58.554165 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1316 15:36:58.557445
1317 15:36:58.557521 [DATLAT]
1318 15:36:58.557584 Freq=800, CH0 RK1
1319 15:36:58.557655
1320 15:36:58.560741 DATLAT Default: 0xa
1321 15:36:58.560815 0, 0xFFFF, sum = 0
1322 15:36:58.564143 1, 0xFFFF, sum = 0
1323 15:36:58.564238 2, 0xFFFF, sum = 0
1324 15:36:58.567372 3, 0xFFFF, sum = 0
1325 15:36:58.567471 4, 0xFFFF, sum = 0
1326 15:36:58.570598 5, 0xFFFF, sum = 0
1327 15:36:58.570695 6, 0xFFFF, sum = 0
1328 15:36:58.573955 7, 0xFFFF, sum = 0
1329 15:36:58.577462 8, 0xFFFF, sum = 0
1330 15:36:58.577571 9, 0x0, sum = 1
1331 15:36:58.577666 10, 0x0, sum = 2
1332 15:36:58.580453 11, 0x0, sum = 3
1333 15:36:58.580565 12, 0x0, sum = 4
1334 15:36:58.584091 best_step = 10
1335 15:36:58.584198
1336 15:36:58.584317 ==
1337 15:36:58.587608 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 15:36:58.590584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 15:36:58.590686 ==
1340 15:36:58.594258 RX Vref Scan: 0
1341 15:36:58.594363
1342 15:36:58.594453 RX Vref 0 -> 0, step: 1
1343 15:36:58.594541
1344 15:36:58.597306 RX Delay -95 -> 252, step: 8
1345 15:36:58.604175 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1346 15:36:58.607281 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1347 15:36:58.611041 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1348 15:36:58.614134 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1349 15:36:58.617306 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1350 15:36:58.623828 iDelay=209, Bit 5, Center 84 (-31 ~ 200) 232
1351 15:36:58.627148 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1352 15:36:58.630943 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1353 15:36:58.633917 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1354 15:36:58.637589 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1355 15:36:58.640675 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1356 15:36:58.647290 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1357 15:36:58.650557 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1358 15:36:58.653895 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1359 15:36:58.657780 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1360 15:36:58.664478 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1361 15:36:58.664597 ==
1362 15:36:58.667137 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 15:36:58.670513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 15:36:58.670618 ==
1365 15:36:58.670710 DQS Delay:
1366 15:36:58.673783 DQS0 = 0, DQS1 = 0
1367 15:36:58.673865 DQM Delay:
1368 15:36:58.677601 DQM0 = 93, DQM1 = 83
1369 15:36:58.677707 DQ Delay:
1370 15:36:58.680866 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1371 15:36:58.684067 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1372 15:36:58.687338 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1373 15:36:58.691197 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =92
1374 15:36:58.691301
1375 15:36:58.691393
1376 15:36:58.697394 [DQSOSCAuto] RK1, (LSB)MR18= 0x4212, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1377 15:36:58.700745 CH0 RK1: MR19=606, MR18=4212
1378 15:36:58.707339 CH0_RK1: MR19=0x606, MR18=0x4212, DQSOSC=393, MR23=63, INC=95, DEC=63
1379 15:36:58.710721 [RxdqsGatingPostProcess] freq 800
1380 15:36:58.717375 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 15:36:58.717457 Pre-setting of DQS Precalculation
1382 15:36:58.724488 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 15:36:58.724572 ==
1384 15:36:58.727700 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 15:36:58.730807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 15:36:58.730885 ==
1387 15:36:58.737957 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 15:36:58.744540 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 15:36:58.752286 [CA 0] Center 36 (6~67) winsize 62
1390 15:36:58.755342 [CA 1] Center 36 (6~67) winsize 62
1391 15:36:58.759205 [CA 2] Center 35 (5~66) winsize 62
1392 15:36:58.761937 [CA 3] Center 34 (4~65) winsize 62
1393 15:36:58.765713 [CA 4] Center 34 (4~65) winsize 62
1394 15:36:58.769193 [CA 5] Center 34 (4~64) winsize 61
1395 15:36:58.769292
1396 15:36:58.772489 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1397 15:36:58.772588
1398 15:36:58.775717 [CATrainingPosCal] consider 1 rank data
1399 15:36:58.779026 u2DelayCellTimex100 = 270/100 ps
1400 15:36:58.782353 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1401 15:36:58.785653 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1402 15:36:58.788889 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1403 15:36:58.795727 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1404 15:36:58.799004 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1405 15:36:58.802152 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1406 15:36:58.802254
1407 15:36:58.805472 CA PerBit enable=1, Macro0, CA PI delay=34
1408 15:36:58.805570
1409 15:36:58.808819 [CBTSetCACLKResult] CA Dly = 34
1410 15:36:58.808918 CS Dly: 6 (0~37)
1411 15:36:58.809015 ==
1412 15:36:58.812242 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 15:36:58.819258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 15:36:58.819365 ==
1415 15:36:58.822432 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 15:36:58.830357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 15:36:58.838340 [CA 0] Center 36 (6~67) winsize 62
1418 15:36:58.842174 [CA 1] Center 36 (6~67) winsize 62
1419 15:36:58.845935 [CA 2] Center 35 (4~66) winsize 63
1420 15:36:58.849654 [CA 3] Center 34 (4~65) winsize 62
1421 15:36:58.853374 [CA 4] Center 34 (4~65) winsize 62
1422 15:36:58.857386 [CA 5] Center 34 (4~65) winsize 62
1423 15:36:58.857468
1424 15:36:58.860620 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1425 15:36:58.860699
1426 15:36:58.863944 [CATrainingPosCal] consider 2 rank data
1427 15:36:58.867274 u2DelayCellTimex100 = 270/100 ps
1428 15:36:58.870548 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1429 15:36:58.873826 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 15:36:58.877139 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1431 15:36:58.880377 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1432 15:36:58.883726 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1433 15:36:58.887116 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1434 15:36:58.887225
1435 15:36:58.890261 CA PerBit enable=1, Macro0, CA PI delay=34
1436 15:36:58.890363
1437 15:36:58.893676 [CBTSetCACLKResult] CA Dly = 34
1438 15:36:58.897458 CS Dly: 6 (0~38)
1439 15:36:58.897562
1440 15:36:58.900717 ----->DramcWriteLeveling(PI) begin...
1441 15:36:58.900815 ==
1442 15:36:58.903912 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 15:36:58.907228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 15:36:58.907328 ==
1445 15:36:58.910454 Write leveling (Byte 0): 28 => 28
1446 15:36:58.914359 Write leveling (Byte 1): 28 => 28
1447 15:36:58.917578 DramcWriteLeveling(PI) end<-----
1448 15:36:58.917684
1449 15:36:58.917776 ==
1450 15:36:58.920942 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 15:36:58.924355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 15:36:58.924474 ==
1453 15:36:58.927434 [Gating] SW mode calibration
1454 15:36:58.934372 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 15:36:58.940957 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 15:36:58.944418 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1457 15:36:58.947391 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1458 15:36:58.954223 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 15:36:58.957732 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 15:36:58.961107 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 15:36:58.967572 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 15:36:58.971214 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 15:36:58.974309 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 15:36:58.977716 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 15:36:58.984458 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 15:36:58.987787 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 15:36:58.991186 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 15:36:58.997774 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 15:36:59.001106 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 15:36:59.004947 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 15:36:59.011629 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 15:36:59.014678 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1473 15:36:59.018199 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1474 15:36:59.024459 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1475 15:36:59.028187 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 15:36:59.031418 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 15:36:59.034736 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 15:36:59.041289 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 15:36:59.045113 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 15:36:59.048132 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 15:36:59.054938 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1482 15:36:59.058481 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1483 15:36:59.061391 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 15:36:59.068484 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 15:36:59.071251 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 15:36:59.075000 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 15:36:59.081478 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 15:36:59.084842 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 15:36:59.088316 0 10 4 | B1->B0 | 3333 2c2c | 0 0 | (0 0) (0 0)
1490 15:36:59.094639 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1491 15:36:59.098547 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 15:36:59.101640 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 15:36:59.108016 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 15:36:59.111797 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 15:36:59.115054 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 15:36:59.121691 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 15:36:59.124805 0 11 4 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
1498 15:36:59.128005 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1499 15:36:59.131710 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 15:36:59.138048 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 15:36:59.141776 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 15:36:59.144987 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 15:36:59.151442 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 15:36:59.154584 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1505 15:36:59.158459 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 15:36:59.164780 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 15:36:59.168417 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 15:36:59.171363 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 15:36:59.178288 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 15:36:59.181955 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 15:36:59.184728 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 15:36:59.191313 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 15:36:59.194861 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 15:36:59.198275 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 15:36:59.201884 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 15:36:59.208424 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 15:36:59.211642 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 15:36:59.215456 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 15:36:59.221899 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 15:36:59.224941 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1521 15:36:59.228167 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 15:36:59.231882 Total UI for P1: 0, mck2ui 16
1523 15:36:59.234981 best dqsien dly found for B0: ( 0, 14, 0)
1524 15:36:59.238574 Total UI for P1: 0, mck2ui 16
1525 15:36:59.241765 best dqsien dly found for B1: ( 0, 14, 0)
1526 15:36:59.245075 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1527 15:36:59.248300 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1528 15:36:59.248420
1529 15:36:59.255265 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1530 15:36:59.259109 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1531 15:36:59.259206 [Gating] SW calibration Done
1532 15:36:59.259302 ==
1533 15:36:59.262231 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 15:36:59.268621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1535 15:36:59.268704 ==
1536 15:36:59.268787 RX Vref Scan: 0
1537 15:36:59.268869
1538 15:36:59.271817 RX Vref 0 -> 0, step: 1
1539 15:36:59.271897
1540 15:36:59.275697 RX Delay -130 -> 252, step: 16
1541 15:36:59.278916 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1542 15:36:59.282109 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1543 15:36:59.285117 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1544 15:36:59.291948 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1545 15:36:59.295297 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1546 15:36:59.299042 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1547 15:36:59.302204 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1548 15:36:59.305178 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1549 15:36:59.308765 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1550 15:36:59.315381 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1551 15:36:59.318516 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1552 15:36:59.321695 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1553 15:36:59.324956 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1554 15:36:59.332080 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1555 15:36:59.335252 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1556 15:36:59.338401 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1557 15:36:59.338480 ==
1558 15:36:59.342025 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 15:36:59.345022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 15:36:59.345100 ==
1561 15:36:59.348856 DQS Delay:
1562 15:36:59.348936 DQS0 = 0, DQS1 = 0
1563 15:36:59.352066 DQM Delay:
1564 15:36:59.352144 DQM0 = 94, DQM1 = 89
1565 15:36:59.352225 DQ Delay:
1566 15:36:59.355194 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1567 15:36:59.359078 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1568 15:36:59.362034 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1569 15:36:59.365143 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1570 15:36:59.365232
1571 15:36:59.365297
1572 15:36:59.368436 ==
1573 15:36:59.371740 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 15:36:59.375589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 15:36:59.375680 ==
1576 15:36:59.375746
1577 15:36:59.375806
1578 15:36:59.378967 TX Vref Scan disable
1579 15:36:59.379050 == TX Byte 0 ==
1580 15:36:59.382188 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1581 15:36:59.388858 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1582 15:36:59.388941 == TX Byte 1 ==
1583 15:36:59.392055 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1584 15:36:59.398641 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1585 15:36:59.398725 ==
1586 15:36:59.401756 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 15:36:59.405252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 15:36:59.405345 ==
1589 15:36:59.418343 TX Vref=22, minBit 3, minWin=26, winSum=437
1590 15:36:59.422145 TX Vref=24, minBit 3, minWin=26, winSum=440
1591 15:36:59.425029 TX Vref=26, minBit 0, minWin=27, winSum=442
1592 15:36:59.428589 TX Vref=28, minBit 0, minWin=27, winSum=446
1593 15:36:59.431959 TX Vref=30, minBit 3, minWin=27, winSum=448
1594 15:36:59.435117 TX Vref=32, minBit 2, minWin=27, winSum=448
1595 15:36:59.442208 [TxChooseVref] Worse bit 3, Min win 27, Win sum 448, Final Vref 30
1596 15:36:59.442292
1597 15:36:59.445386 Final TX Range 1 Vref 30
1598 15:36:59.445469
1599 15:36:59.445537 ==
1600 15:36:59.448447 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 15:36:59.452016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 15:36:59.452129 ==
1603 15:36:59.452226
1604 15:36:59.454736
1605 15:36:59.454850 TX Vref Scan disable
1606 15:36:59.458635 == TX Byte 0 ==
1607 15:36:59.461906 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1608 15:36:59.465148 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1609 15:36:59.468160 == TX Byte 1 ==
1610 15:36:59.472022 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1611 15:36:59.475318 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1612 15:36:59.478475
1613 15:36:59.478556 [DATLAT]
1614 15:36:59.478631 Freq=800, CH1 RK0
1615 15:36:59.478691
1616 15:36:59.481642 DATLAT Default: 0xa
1617 15:36:59.481750 0, 0xFFFF, sum = 0
1618 15:36:59.484796 1, 0xFFFF, sum = 0
1619 15:36:59.484901 2, 0xFFFF, sum = 0
1620 15:36:59.488335 3, 0xFFFF, sum = 0
1621 15:36:59.488443 4, 0xFFFF, sum = 0
1622 15:36:59.491604 5, 0xFFFF, sum = 0
1623 15:36:59.491684 6, 0xFFFF, sum = 0
1624 15:36:59.494967 7, 0xFFFF, sum = 0
1625 15:36:59.498202 8, 0xFFFF, sum = 0
1626 15:36:59.498285 9, 0x0, sum = 1
1627 15:36:59.498360 10, 0x0, sum = 2
1628 15:36:59.501538 11, 0x0, sum = 3
1629 15:36:59.501661 12, 0x0, sum = 4
1630 15:36:59.505504 best_step = 10
1631 15:36:59.505590
1632 15:36:59.505656 ==
1633 15:36:59.508581 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 15:36:59.511812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 15:36:59.511950 ==
1636 15:36:59.514881 RX Vref Scan: 1
1637 15:36:59.514965
1638 15:36:59.515036 Set Vref Range= 32 -> 127
1639 15:36:59.515096
1640 15:36:59.518398 RX Vref 32 -> 127, step: 1
1641 15:36:59.518470
1642 15:36:59.521600 RX Delay -79 -> 252, step: 8
1643 15:36:59.521714
1644 15:36:59.525568 Set Vref, RX VrefLevel [Byte0]: 32
1645 15:36:59.528763 [Byte1]: 32
1646 15:36:59.528838
1647 15:36:59.531751 Set Vref, RX VrefLevel [Byte0]: 33
1648 15:36:59.535293 [Byte1]: 33
1649 15:36:59.538357
1650 15:36:59.538470 Set Vref, RX VrefLevel [Byte0]: 34
1651 15:36:59.542104 [Byte1]: 34
1652 15:36:59.545999
1653 15:36:59.546074 Set Vref, RX VrefLevel [Byte0]: 35
1654 15:36:59.549337 [Byte1]: 35
1655 15:36:59.553803
1656 15:36:59.553888 Set Vref, RX VrefLevel [Byte0]: 36
1657 15:36:59.556960 [Byte1]: 36
1658 15:36:59.560879
1659 15:36:59.561002 Set Vref, RX VrefLevel [Byte0]: 37
1660 15:36:59.564252 [Byte1]: 37
1661 15:36:59.568766
1662 15:36:59.568875 Set Vref, RX VrefLevel [Byte0]: 38
1663 15:36:59.572082 [Byte1]: 38
1664 15:36:59.576493
1665 15:36:59.576580 Set Vref, RX VrefLevel [Byte0]: 39
1666 15:36:59.579838 [Byte1]: 39
1667 15:36:59.583819
1668 15:36:59.583927 Set Vref, RX VrefLevel [Byte0]: 40
1669 15:36:59.587089 [Byte1]: 40
1670 15:36:59.591675
1671 15:36:59.591779 Set Vref, RX VrefLevel [Byte0]: 41
1672 15:36:59.595041 [Byte1]: 41
1673 15:36:59.599164
1674 15:36:59.599276 Set Vref, RX VrefLevel [Byte0]: 42
1675 15:36:59.602413 [Byte1]: 42
1676 15:36:59.606254
1677 15:36:59.606331 Set Vref, RX VrefLevel [Byte0]: 43
1678 15:36:59.609528 [Byte1]: 43
1679 15:36:59.614223
1680 15:36:59.614326 Set Vref, RX VrefLevel [Byte0]: 44
1681 15:36:59.617352 [Byte1]: 44
1682 15:36:59.621796
1683 15:36:59.621901 Set Vref, RX VrefLevel [Byte0]: 45
1684 15:36:59.624939 [Byte1]: 45
1685 15:36:59.629215
1686 15:36:59.629296 Set Vref, RX VrefLevel [Byte0]: 46
1687 15:36:59.632407 [Byte1]: 46
1688 15:36:59.636345
1689 15:36:59.636458 Set Vref, RX VrefLevel [Byte0]: 47
1690 15:36:59.640031 [Byte1]: 47
1691 15:36:59.644505
1692 15:36:59.644613 Set Vref, RX VrefLevel [Byte0]: 48
1693 15:36:59.647579 [Byte1]: 48
1694 15:36:59.651671
1695 15:36:59.651756 Set Vref, RX VrefLevel [Byte0]: 49
1696 15:36:59.655311 [Byte1]: 49
1697 15:36:59.659325
1698 15:36:59.659433 Set Vref, RX VrefLevel [Byte0]: 50
1699 15:36:59.662633 [Byte1]: 50
1700 15:36:59.667009
1701 15:36:59.667120 Set Vref, RX VrefLevel [Byte0]: 51
1702 15:36:59.670204 [Byte1]: 51
1703 15:36:59.674174
1704 15:36:59.674261 Set Vref, RX VrefLevel [Byte0]: 52
1705 15:36:59.677977 [Byte1]: 52
1706 15:36:59.681899
1707 15:36:59.681983 Set Vref, RX VrefLevel [Byte0]: 53
1708 15:36:59.685073 [Byte1]: 53
1709 15:36:59.689231
1710 15:36:59.689314 Set Vref, RX VrefLevel [Byte0]: 54
1711 15:36:59.693130 [Byte1]: 54
1712 15:36:59.697008
1713 15:36:59.697087 Set Vref, RX VrefLevel [Byte0]: 55
1714 15:36:59.700405 [Byte1]: 55
1715 15:36:59.704445
1716 15:36:59.704525 Set Vref, RX VrefLevel [Byte0]: 56
1717 15:36:59.707749 [Byte1]: 56
1718 15:36:59.712289
1719 15:36:59.712377 Set Vref, RX VrefLevel [Byte0]: 57
1720 15:36:59.715574 [Byte1]: 57
1721 15:36:59.719586
1722 15:36:59.719674 Set Vref, RX VrefLevel [Byte0]: 58
1723 15:36:59.722728 [Byte1]: 58
1724 15:36:59.726899
1725 15:36:59.727015 Set Vref, RX VrefLevel [Byte0]: 59
1726 15:36:59.730752 [Byte1]: 59
1727 15:36:59.734571
1728 15:36:59.734679 Set Vref, RX VrefLevel [Byte0]: 60
1729 15:36:59.737736 [Byte1]: 60
1730 15:36:59.742340
1731 15:36:59.742455 Set Vref, RX VrefLevel [Byte0]: 61
1732 15:36:59.745450 [Byte1]: 61
1733 15:36:59.749875
1734 15:36:59.749983 Set Vref, RX VrefLevel [Byte0]: 62
1735 15:36:59.753129 [Byte1]: 62
1736 15:36:59.757599
1737 15:36:59.757683 Set Vref, RX VrefLevel [Byte0]: 63
1738 15:36:59.760459 [Byte1]: 63
1739 15:36:59.764589
1740 15:36:59.764706 Set Vref, RX VrefLevel [Byte0]: 64
1741 15:36:59.768181 [Byte1]: 64
1742 15:36:59.772188
1743 15:36:59.772299 Set Vref, RX VrefLevel [Byte0]: 65
1744 15:36:59.775973 [Byte1]: 65
1745 15:36:59.779954
1746 15:36:59.780062 Set Vref, RX VrefLevel [Byte0]: 66
1747 15:36:59.783176 [Byte1]: 66
1748 15:36:59.787661
1749 15:36:59.787765 Set Vref, RX VrefLevel [Byte0]: 67
1750 15:36:59.790957 [Byte1]: 67
1751 15:36:59.794936
1752 15:36:59.795047 Set Vref, RX VrefLevel [Byte0]: 68
1753 15:36:59.798239 [Byte1]: 68
1754 15:36:59.802983
1755 15:36:59.803093 Set Vref, RX VrefLevel [Byte0]: 69
1756 15:36:59.806145 [Byte1]: 69
1757 15:36:59.810144
1758 15:36:59.810253 Set Vref, RX VrefLevel [Byte0]: 70
1759 15:36:59.813398 [Byte1]: 70
1760 15:36:59.818054
1761 15:36:59.818164 Set Vref, RX VrefLevel [Byte0]: 71
1762 15:36:59.821273 [Byte1]: 71
1763 15:36:59.825310
1764 15:36:59.825434 Final RX Vref Byte 0 = 58 to rank0
1765 15:36:59.828505 Final RX Vref Byte 1 = 61 to rank0
1766 15:36:59.831893 Final RX Vref Byte 0 = 58 to rank1
1767 15:36:59.835019 Final RX Vref Byte 1 = 61 to rank1==
1768 15:36:59.838813 Dram Type= 6, Freq= 0, CH_1, rank 0
1769 15:36:59.845555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1770 15:36:59.845660 ==
1771 15:36:59.845756 DQS Delay:
1772 15:36:59.845848 DQS0 = 0, DQS1 = 0
1773 15:36:59.848838 DQM Delay:
1774 15:36:59.848913 DQM0 = 97, DQM1 = 91
1775 15:36:59.852157 DQ Delay:
1776 15:36:59.855502 DQ0 =100, DQ1 =88, DQ2 =88, DQ3 =92
1777 15:36:59.858933 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
1778 15:36:59.862036 DQ8 =76, DQ9 =84, DQ10 =92, DQ11 =84
1779 15:36:59.865120 DQ12 =96, DQ13 =100, DQ14 =100, DQ15 =96
1780 15:36:59.865228
1781 15:36:59.865328
1782 15:36:59.872005 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1783 15:36:59.875237 CH1 RK0: MR19=606, MR18=2C48
1784 15:36:59.882582 CH1_RK0: MR19=0x606, MR18=0x2C48, DQSOSC=391, MR23=63, INC=96, DEC=64
1785 15:36:59.882699
1786 15:36:59.885716 ----->DramcWriteLeveling(PI) begin...
1787 15:36:59.885793 ==
1788 15:36:59.888998 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 15:36:59.892447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 15:36:59.892533 ==
1791 15:36:59.895905 Write leveling (Byte 0): 25 => 25
1792 15:36:59.898996 Write leveling (Byte 1): 29 => 29
1793 15:36:59.902365 DramcWriteLeveling(PI) end<-----
1794 15:36:59.902479
1795 15:36:59.902583 ==
1796 15:36:59.905589 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 15:36:59.908900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 15:36:59.908982 ==
1799 15:36:59.912285 [Gating] SW mode calibration
1800 15:36:59.918910 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1801 15:36:59.925617 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1802 15:36:59.928890 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1803 15:36:59.932182 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1804 15:36:59.938762 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 15:36:59.942462 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 15:36:59.945675 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 15:36:59.952858 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 15:36:59.956195 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 15:36:59.958985 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 15:36:59.965589 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 15:36:59.969391 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 15:36:59.972640 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 15:36:59.975903 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 15:36:59.982462 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 15:36:59.986150 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 15:36:59.989204 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 15:36:59.995846 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 15:36:59.999404 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1819 15:37:00.002359 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1820 15:37:00.009316 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 15:37:00.012687 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 15:37:00.015864 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 15:37:00.022961 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 15:37:00.026232 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 15:37:00.029589 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 15:37:00.036096 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 15:37:00.039446 0 9 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1828 15:37:00.042508 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1829 15:37:00.046357 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 15:37:00.053037 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 15:37:00.056237 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 15:37:00.059257 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 15:37:00.066034 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 15:37:00.069441 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1835 15:37:00.072738 0 10 4 | B1->B0 | 2727 3232 | 0 0 | (1 0) (0 1)
1836 15:37:00.079684 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1837 15:37:00.083014 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 15:37:00.086068 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 15:37:00.093096 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 15:37:00.096301 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 15:37:00.099409 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 15:37:00.106465 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1843 15:37:00.109525 0 11 4 | B1->B0 | 3333 2929 | 0 1 | (0 0) (0 0)
1844 15:37:00.113134 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1845 15:37:00.119429 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 15:37:00.123220 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 15:37:00.126341 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 15:37:00.129590 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 15:37:00.136205 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 15:37:00.139567 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1851 15:37:00.142968 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1852 15:37:00.149874 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 15:37:00.153029 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 15:37:00.156316 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 15:37:00.163356 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 15:37:00.166585 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 15:37:00.169878 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 15:37:00.176580 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 15:37:00.179696 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 15:37:00.182995 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 15:37:00.189650 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 15:37:00.192989 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 15:37:00.196729 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 15:37:00.199885 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 15:37:00.206710 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 15:37:00.209952 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 15:37:00.213051 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1868 15:37:00.220309 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 15:37:00.223328 Total UI for P1: 0, mck2ui 16
1870 15:37:00.226391 best dqsien dly found for B0: ( 0, 14, 6)
1871 15:37:00.229506 Total UI for P1: 0, mck2ui 16
1872 15:37:00.233137 best dqsien dly found for B1: ( 0, 14, 4)
1873 15:37:00.236187 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1874 15:37:00.240059 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1875 15:37:00.240136
1876 15:37:00.243325 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1877 15:37:00.246604 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1878 15:37:00.249901 [Gating] SW calibration Done
1879 15:37:00.249978 ==
1880 15:37:00.253206 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 15:37:00.256461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 15:37:00.256550 ==
1883 15:37:00.259763 RX Vref Scan: 0
1884 15:37:00.259847
1885 15:37:00.259909 RX Vref 0 -> 0, step: 1
1886 15:37:00.259972
1887 15:37:00.263065 RX Delay -130 -> 252, step: 16
1888 15:37:00.266274 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1889 15:37:00.273298 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1890 15:37:00.276625 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1891 15:37:00.279906 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1892 15:37:00.283209 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1893 15:37:00.286437 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1894 15:37:00.292952 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1895 15:37:00.296292 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1896 15:37:00.299599 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1897 15:37:00.303082 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1898 15:37:00.306946 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1899 15:37:00.313056 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1900 15:37:00.316841 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1901 15:37:00.319773 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1902 15:37:00.323133 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1903 15:37:00.326542 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1904 15:37:00.329925 ==
1905 15:37:00.330048 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 15:37:00.336560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 15:37:00.336664 ==
1908 15:37:00.336756 DQS Delay:
1909 15:37:00.340357 DQS0 = 0, DQS1 = 0
1910 15:37:00.340434 DQM Delay:
1911 15:37:00.343597 DQM0 = 93, DQM1 = 90
1912 15:37:00.343687 DQ Delay:
1913 15:37:00.346939 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1914 15:37:00.349921 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1915 15:37:00.353148 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1916 15:37:00.356781 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1917 15:37:00.356864
1918 15:37:00.356933
1919 15:37:00.356995 ==
1920 15:37:00.360179 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 15:37:00.363480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 15:37:00.363606 ==
1923 15:37:00.363696
1924 15:37:00.363758
1925 15:37:00.366788 TX Vref Scan disable
1926 15:37:00.370117 == TX Byte 0 ==
1927 15:37:00.373359 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1928 15:37:00.376564 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1929 15:37:00.379752 == TX Byte 1 ==
1930 15:37:00.383581 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1931 15:37:00.386898 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1932 15:37:00.386996 ==
1933 15:37:00.390182 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 15:37:00.393511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 15:37:00.396654 ==
1936 15:37:00.407966 TX Vref=22, minBit 3, minWin=25, winSum=434
1937 15:37:00.411352 TX Vref=24, minBit 1, minWin=26, winSum=435
1938 15:37:00.414618 TX Vref=26, minBit 2, minWin=26, winSum=444
1939 15:37:00.418172 TX Vref=28, minBit 1, minWin=26, winSum=444
1940 15:37:00.421394 TX Vref=30, minBit 0, minWin=26, winSum=444
1941 15:37:00.424570 TX Vref=32, minBit 0, minWin=26, winSum=441
1942 15:37:00.431721 [TxChooseVref] Worse bit 2, Min win 26, Win sum 444, Final Vref 26
1943 15:37:00.431813
1944 15:37:00.435187 Final TX Range 1 Vref 26
1945 15:37:00.435295
1946 15:37:00.435393 ==
1947 15:37:00.438558 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 15:37:00.442004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 15:37:00.442104 ==
1950 15:37:00.442204
1951 15:37:00.442295
1952 15:37:00.445247 TX Vref Scan disable
1953 15:37:00.448525 == TX Byte 0 ==
1954 15:37:00.451987 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1955 15:37:00.455110 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1956 15:37:00.458242 == TX Byte 1 ==
1957 15:37:00.461986 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1958 15:37:00.465423 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1959 15:37:00.465539
1960 15:37:00.468363 [DATLAT]
1961 15:37:00.468476 Freq=800, CH1 RK1
1962 15:37:00.468574
1963 15:37:00.471841 DATLAT Default: 0xa
1964 15:37:00.471948 0, 0xFFFF, sum = 0
1965 15:37:00.475384 1, 0xFFFF, sum = 0
1966 15:37:00.475476 2, 0xFFFF, sum = 0
1967 15:37:00.478312 3, 0xFFFF, sum = 0
1968 15:37:00.478403 4, 0xFFFF, sum = 0
1969 15:37:00.482120 5, 0xFFFF, sum = 0
1970 15:37:00.482196 6, 0xFFFF, sum = 0
1971 15:37:00.485134 7, 0xFFFF, sum = 0
1972 15:37:00.485242 8, 0xFFFF, sum = 0
1973 15:37:00.488520 9, 0x0, sum = 1
1974 15:37:00.488622 10, 0x0, sum = 2
1975 15:37:00.491731 11, 0x0, sum = 3
1976 15:37:00.491851 12, 0x0, sum = 4
1977 15:37:00.495651 best_step = 10
1978 15:37:00.495751
1979 15:37:00.495845 ==
1980 15:37:00.498878 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 15:37:00.502116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 15:37:00.502191 ==
1983 15:37:00.502256 RX Vref Scan: 0
1984 15:37:00.505423
1985 15:37:00.505521 RX Vref 0 -> 0, step: 1
1986 15:37:00.505615
1987 15:37:00.508589 RX Delay -63 -> 252, step: 8
1988 15:37:00.511936 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1989 15:37:00.518649 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1990 15:37:00.522320 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1991 15:37:00.525304 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1992 15:37:00.528327 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1993 15:37:00.532078 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1994 15:37:00.535381 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1995 15:37:00.542040 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1996 15:37:00.545246 iDelay=209, Bit 8, Center 76 (-23 ~ 176) 200
1997 15:37:00.548397 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1998 15:37:00.552352 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
1999 15:37:00.555570 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2000 15:37:00.562181 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2001 15:37:00.565468 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2002 15:37:00.568799 iDelay=209, Bit 14, Center 92 (-7 ~ 192) 200
2003 15:37:00.571922 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2004 15:37:00.572009 ==
2005 15:37:00.575093 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 15:37:00.579042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 15:37:00.581958 ==
2008 15:37:00.582030 DQS Delay:
2009 15:37:00.582109 DQS0 = 0, DQS1 = 0
2010 15:37:00.585416 DQM Delay:
2011 15:37:00.585488 DQM0 = 97, DQM1 = 90
2012 15:37:00.589001 DQ Delay:
2013 15:37:00.592000 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2014 15:37:00.595504 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2015 15:37:00.595596 DQ8 =76, DQ9 =80, DQ10 =92, DQ11 =88
2016 15:37:00.602060 DQ12 =100, DQ13 =96, DQ14 =92, DQ15 =96
2017 15:37:00.602179
2018 15:37:00.602318
2019 15:37:00.608978 [DQSOSCAuto] RK1, (LSB)MR18= 0x4913, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2020 15:37:00.612222 CH1 RK1: MR19=606, MR18=4913
2021 15:37:00.618948 CH1_RK1: MR19=0x606, MR18=0x4913, DQSOSC=391, MR23=63, INC=96, DEC=64
2022 15:37:00.622231 [RxdqsGatingPostProcess] freq 800
2023 15:37:00.625475 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2024 15:37:00.628679 Pre-setting of DQS Precalculation
2025 15:37:00.635475 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2026 15:37:00.642046 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2027 15:37:00.648582 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2028 15:37:00.648667
2029 15:37:00.648731
2030 15:37:00.652497 [Calibration Summary] 1600 Mbps
2031 15:37:00.652572 CH 0, Rank 0
2032 15:37:00.655760 SW Impedance : PASS
2033 15:37:00.659105 DUTY Scan : NO K
2034 15:37:00.659182 ZQ Calibration : PASS
2035 15:37:00.662356 Jitter Meter : NO K
2036 15:37:00.662431 CBT Training : PASS
2037 15:37:00.665593 Write leveling : PASS
2038 15:37:00.668961 RX DQS gating : PASS
2039 15:37:00.669057 RX DQ/DQS(RDDQC) : PASS
2040 15:37:00.672143 TX DQ/DQS : PASS
2041 15:37:00.675434 RX DATLAT : PASS
2042 15:37:00.675539 RX DQ/DQS(Engine): PASS
2043 15:37:00.678778 TX OE : NO K
2044 15:37:00.678877 All Pass.
2045 15:37:00.678969
2046 15:37:00.682023 CH 0, Rank 1
2047 15:37:00.682096 SW Impedance : PASS
2048 15:37:00.685375 DUTY Scan : NO K
2049 15:37:00.689141 ZQ Calibration : PASS
2050 15:37:00.689216 Jitter Meter : NO K
2051 15:37:00.692298 CBT Training : PASS
2052 15:37:00.695942 Write leveling : PASS
2053 15:37:00.696017 RX DQS gating : PASS
2054 15:37:00.699204 RX DQ/DQS(RDDQC) : PASS
2055 15:37:00.699281 TX DQ/DQS : PASS
2056 15:37:00.702485 RX DATLAT : PASS
2057 15:37:00.705709 RX DQ/DQS(Engine): PASS
2058 15:37:00.705829 TX OE : NO K
2059 15:37:00.709172 All Pass.
2060 15:37:00.709289
2061 15:37:00.709396 CH 1, Rank 0
2062 15:37:00.712049 SW Impedance : PASS
2063 15:37:00.712162 DUTY Scan : NO K
2064 15:37:00.715512 ZQ Calibration : PASS
2065 15:37:00.719114 Jitter Meter : NO K
2066 15:37:00.719223 CBT Training : PASS
2067 15:37:00.722137 Write leveling : PASS
2068 15:37:00.725930 RX DQS gating : PASS
2069 15:37:00.726034 RX DQ/DQS(RDDQC) : PASS
2070 15:37:00.728826 TX DQ/DQS : PASS
2071 15:37:00.732099 RX DATLAT : PASS
2072 15:37:00.732183 RX DQ/DQS(Engine): PASS
2073 15:37:00.735631 TX OE : NO K
2074 15:37:00.735736 All Pass.
2075 15:37:00.735834
2076 15:37:00.739303 CH 1, Rank 1
2077 15:37:00.739380 SW Impedance : PASS
2078 15:37:00.742270 DUTY Scan : NO K
2079 15:37:00.742344 ZQ Calibration : PASS
2080 15:37:00.745897 Jitter Meter : NO K
2081 15:37:00.749154 CBT Training : PASS
2082 15:37:00.749228 Write leveling : PASS
2083 15:37:00.752373 RX DQS gating : PASS
2084 15:37:00.755715 RX DQ/DQS(RDDQC) : PASS
2085 15:37:00.755825 TX DQ/DQS : PASS
2086 15:37:00.758915 RX DATLAT : PASS
2087 15:37:00.762877 RX DQ/DQS(Engine): PASS
2088 15:37:00.762990 TX OE : NO K
2089 15:37:00.766215 All Pass.
2090 15:37:00.766311
2091 15:37:00.766411 DramC Write-DBI off
2092 15:37:00.769393 PER_BANK_REFRESH: Hybrid Mode
2093 15:37:00.769462 TX_TRACKING: ON
2094 15:37:00.772763 [GetDramInforAfterCalByMRR] Vendor 6.
2095 15:37:00.779208 [GetDramInforAfterCalByMRR] Revision 606.
2096 15:37:00.782498 [GetDramInforAfterCalByMRR] Revision 2 0.
2097 15:37:00.782604 MR0 0x3b3b
2098 15:37:00.782699 MR8 0x5151
2099 15:37:00.785622 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 15:37:00.785721
2101 15:37:00.789077 MR0 0x3b3b
2102 15:37:00.789148 MR8 0x5151
2103 15:37:00.792911 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 15:37:00.793000
2105 15:37:00.802574 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2106 15:37:00.806346 [FAST_K] Save calibration result to emmc
2107 15:37:00.809081 [FAST_K] Save calibration result to emmc
2108 15:37:00.813045 dram_init: config_dvfs: 1
2109 15:37:00.816145 dramc_set_vcore_voltage set vcore to 662500
2110 15:37:00.816247 Read voltage for 1200, 2
2111 15:37:00.819201 Vio18 = 0
2112 15:37:00.819304 Vcore = 662500
2113 15:37:00.819399 Vdram = 0
2114 15:37:00.822920 Vddq = 0
2115 15:37:00.823021 Vmddr = 0
2116 15:37:00.829528 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2117 15:37:00.832584 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2118 15:37:00.836245 MEM_TYPE=3, freq_sel=15
2119 15:37:00.839202 sv_algorithm_assistance_LP4_1600
2120 15:37:00.842973 ============ PULL DRAM RESETB DOWN ============
2121 15:37:00.845864 ========== PULL DRAM RESETB DOWN end =========
2122 15:37:00.852698 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 15:37:00.855924 ===================================
2124 15:37:00.856031 LPDDR4 DRAM CONFIGURATION
2125 15:37:00.859276 ===================================
2126 15:37:00.862494 EX_ROW_EN[0] = 0x0
2127 15:37:00.862609 EX_ROW_EN[1] = 0x0
2128 15:37:00.865687 LP4Y_EN = 0x0
2129 15:37:00.865791 WORK_FSP = 0x0
2130 15:37:00.869085 WL = 0x4
2131 15:37:00.872451 RL = 0x4
2132 15:37:00.872555 BL = 0x2
2133 15:37:00.875712 RPST = 0x0
2134 15:37:00.875786 RD_PRE = 0x0
2135 15:37:00.879443 WR_PRE = 0x1
2136 15:37:00.879547 WR_PST = 0x0
2137 15:37:00.882647 DBI_WR = 0x0
2138 15:37:00.882766 DBI_RD = 0x0
2139 15:37:00.886063 OTF = 0x1
2140 15:37:00.889315 ===================================
2141 15:37:00.892696 ===================================
2142 15:37:00.892802 ANA top config
2143 15:37:00.895854 ===================================
2144 15:37:00.899172 DLL_ASYNC_EN = 0
2145 15:37:00.902448 ALL_SLAVE_EN = 0
2146 15:37:00.902548 NEW_RANK_MODE = 1
2147 15:37:00.906260 DLL_IDLE_MODE = 1
2148 15:37:00.909347 LP45_APHY_COMB_EN = 1
2149 15:37:00.912476 TX_ODT_DIS = 1
2150 15:37:00.912558 NEW_8X_MODE = 1
2151 15:37:00.915698 ===================================
2152 15:37:00.918923 ===================================
2153 15:37:00.922859 data_rate = 2400
2154 15:37:00.926244 CKR = 1
2155 15:37:00.929457 DQ_P2S_RATIO = 8
2156 15:37:00.932764 ===================================
2157 15:37:00.935866 CA_P2S_RATIO = 8
2158 15:37:00.939571 DQ_CA_OPEN = 0
2159 15:37:00.939661 DQ_SEMI_OPEN = 0
2160 15:37:00.942708 CA_SEMI_OPEN = 0
2161 15:37:00.946079 CA_FULL_RATE = 0
2162 15:37:00.949102 DQ_CKDIV4_EN = 0
2163 15:37:00.952711 CA_CKDIV4_EN = 0
2164 15:37:00.956041 CA_PREDIV_EN = 0
2165 15:37:00.956123 PH8_DLY = 17
2166 15:37:00.959550 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2167 15:37:00.962395 DQ_AAMCK_DIV = 4
2168 15:37:00.965960 CA_AAMCK_DIV = 4
2169 15:37:00.969379 CA_ADMCK_DIV = 4
2170 15:37:00.972607 DQ_TRACK_CA_EN = 0
2171 15:37:00.972718 CA_PICK = 1200
2172 15:37:00.975846 CA_MCKIO = 1200
2173 15:37:00.979151 MCKIO_SEMI = 0
2174 15:37:00.982419 PLL_FREQ = 2366
2175 15:37:00.985718 DQ_UI_PI_RATIO = 32
2176 15:37:00.988993 CA_UI_PI_RATIO = 0
2177 15:37:00.992903 ===================================
2178 15:37:00.996191 ===================================
2179 15:37:00.999370 memory_type:LPDDR4
2180 15:37:00.999473 GP_NUM : 10
2181 15:37:01.002546 SRAM_EN : 1
2182 15:37:01.002646 MD32_EN : 0
2183 15:37:01.005777 ===================================
2184 15:37:01.009190 [ANA_INIT] >>>>>>>>>>>>>>
2185 15:37:01.012524 <<<<<< [CONFIGURE PHASE]: ANA_TX
2186 15:37:01.016150 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2187 15:37:01.019312 ===================================
2188 15:37:01.023148 data_rate = 2400,PCW = 0X5b00
2189 15:37:01.025888 ===================================
2190 15:37:01.029215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2191 15:37:01.032911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 15:37:01.039386 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 15:37:01.043182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2194 15:37:01.046269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2195 15:37:01.049550 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2196 15:37:01.052697 [ANA_INIT] flow start
2197 15:37:01.056555 [ANA_INIT] PLL >>>>>>>>
2198 15:37:01.056669 [ANA_INIT] PLL <<<<<<<<
2199 15:37:01.059588 [ANA_INIT] MIDPI >>>>>>>>
2200 15:37:01.062834 [ANA_INIT] MIDPI <<<<<<<<
2201 15:37:01.062938 [ANA_INIT] DLL >>>>>>>>
2202 15:37:01.066653 [ANA_INIT] DLL <<<<<<<<
2203 15:37:01.069629 [ANA_INIT] flow end
2204 15:37:01.073137 ============ LP4 DIFF to SE enter ============
2205 15:37:01.076632 ============ LP4 DIFF to SE exit ============
2206 15:37:01.079745 [ANA_INIT] <<<<<<<<<<<<<
2207 15:37:01.083358 [Flow] Enable top DCM control >>>>>
2208 15:37:01.086459 [Flow] Enable top DCM control <<<<<
2209 15:37:01.090280 Enable DLL master slave shuffle
2210 15:37:01.093580 ==============================================================
2211 15:37:01.096844 Gating Mode config
2212 15:37:01.100198 ==============================================================
2213 15:37:01.103399 Config description:
2214 15:37:01.113299 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2215 15:37:01.119898 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2216 15:37:01.123707 SELPH_MODE 0: By rank 1: By Phase
2217 15:37:01.130262 ==============================================================
2218 15:37:01.133537 GAT_TRACK_EN = 1
2219 15:37:01.136899 RX_GATING_MODE = 2
2220 15:37:01.140114 RX_GATING_TRACK_MODE = 2
2221 15:37:01.143216 SELPH_MODE = 1
2222 15:37:01.143323 PICG_EARLY_EN = 1
2223 15:37:01.147174 VALID_LAT_VALUE = 1
2224 15:37:01.153328 ==============================================================
2225 15:37:01.157134 Enter into Gating configuration >>>>
2226 15:37:01.160054 Exit from Gating configuration <<<<
2227 15:37:01.163175 Enter into DVFS_PRE_config >>>>>
2228 15:37:01.173660 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2229 15:37:01.176921 Exit from DVFS_PRE_config <<<<<
2230 15:37:01.180037 Enter into PICG configuration >>>>
2231 15:37:01.183625 Exit from PICG configuration <<<<
2232 15:37:01.186616 [RX_INPUT] configuration >>>>>
2233 15:37:01.190183 [RX_INPUT] configuration <<<<<
2234 15:37:01.193251 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2235 15:37:01.199852 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2236 15:37:01.207014 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 15:37:01.213923 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 15:37:01.220440 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 15:37:01.223729 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 15:37:01.230171 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2241 15:37:01.234001 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2242 15:37:01.237257 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2243 15:37:01.240363 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2244 15:37:01.243640 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2245 15:37:01.250190 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2246 15:37:01.254088 ===================================
2247 15:37:01.254191 LPDDR4 DRAM CONFIGURATION
2248 15:37:01.257241 ===================================
2249 15:37:01.260264 EX_ROW_EN[0] = 0x0
2250 15:37:01.263637 EX_ROW_EN[1] = 0x0
2251 15:37:01.263740 LP4Y_EN = 0x0
2252 15:37:01.266976 WORK_FSP = 0x0
2253 15:37:01.267078 WL = 0x4
2254 15:37:01.270147 RL = 0x4
2255 15:37:01.270247 BL = 0x2
2256 15:37:01.274050 RPST = 0x0
2257 15:37:01.274152 RD_PRE = 0x0
2258 15:37:01.277323 WR_PRE = 0x1
2259 15:37:01.277423 WR_PST = 0x0
2260 15:37:01.280711 DBI_WR = 0x0
2261 15:37:01.280785 DBI_RD = 0x0
2262 15:37:01.283954 OTF = 0x1
2263 15:37:01.287216 ===================================
2264 15:37:01.290365 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2265 15:37:01.294066 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2266 15:37:01.300761 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 15:37:01.303847 ===================================
2268 15:37:01.303955 LPDDR4 DRAM CONFIGURATION
2269 15:37:01.307031 ===================================
2270 15:37:01.310984 EX_ROW_EN[0] = 0x10
2271 15:37:01.311084 EX_ROW_EN[1] = 0x0
2272 15:37:01.314150 LP4Y_EN = 0x0
2273 15:37:01.314249 WORK_FSP = 0x0
2274 15:37:01.317314 WL = 0x4
2275 15:37:01.317415 RL = 0x4
2276 15:37:01.320586 BL = 0x2
2277 15:37:01.323919 RPST = 0x0
2278 15:37:01.323997 RD_PRE = 0x0
2279 15:37:01.327108 WR_PRE = 0x1
2280 15:37:01.327205 WR_PST = 0x0
2281 15:37:01.331015 DBI_WR = 0x0
2282 15:37:01.331087 DBI_RD = 0x0
2283 15:37:01.334240 OTF = 0x1
2284 15:37:01.337264 ===================================
2285 15:37:01.340479 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2286 15:37:01.344228 ==
2287 15:37:01.346962 Dram Type= 6, Freq= 0, CH_0, rank 0
2288 15:37:01.350894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2289 15:37:01.350995 ==
2290 15:37:01.354163 [Duty_Offset_Calibration]
2291 15:37:01.354259 B0:2 B1:1 CA:1
2292 15:37:01.354347
2293 15:37:01.357463 [DutyScan_Calibration_Flow] k_type=0
2294 15:37:01.367154
2295 15:37:01.367241 ==CLK 0==
2296 15:37:01.370197 Final CLK duty delay cell = 0
2297 15:37:01.373597 [0] MAX Duty = 5218%(X100), DQS PI = 24
2298 15:37:01.376560 [0] MIN Duty = 4875%(X100), DQS PI = 0
2299 15:37:01.376664 [0] AVG Duty = 5046%(X100)
2300 15:37:01.380512
2301 15:37:01.380617 CH0 CLK Duty spec in!! Max-Min= 343%
2302 15:37:01.387051 [DutyScan_Calibration_Flow] ====Done====
2303 15:37:01.387155
2304 15:37:01.389821 [DutyScan_Calibration_Flow] k_type=1
2305 15:37:01.404236
2306 15:37:01.404325 ==DQS 0 ==
2307 15:37:01.407493 Final DQS duty delay cell = -4
2308 15:37:01.411249 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2309 15:37:01.414221 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2310 15:37:01.417926 [-4] AVG Duty = 4937%(X100)
2311 15:37:01.418035
2312 15:37:01.418140 ==DQS 1 ==
2313 15:37:01.421085 Final DQS duty delay cell = -4
2314 15:37:01.424265 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2315 15:37:01.427658 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2316 15:37:01.430927 [-4] AVG Duty = 4922%(X100)
2317 15:37:01.431028
2318 15:37:01.434273 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2319 15:37:01.434380
2320 15:37:01.437462 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2321 15:37:01.441226 [DutyScan_Calibration_Flow] ====Done====
2322 15:37:01.441334
2323 15:37:01.444372 [DutyScan_Calibration_Flow] k_type=3
2324 15:37:01.461384
2325 15:37:01.461502 ==DQM 0 ==
2326 15:37:01.464783 Final DQM duty delay cell = 0
2327 15:37:01.468067 [0] MAX Duty = 5156%(X100), DQS PI = 30
2328 15:37:01.471704 [0] MIN Duty = 4906%(X100), DQS PI = 52
2329 15:37:01.474896 [0] AVG Duty = 5031%(X100)
2330 15:37:01.474999
2331 15:37:01.475102 ==DQM 1 ==
2332 15:37:01.478294 Final DQM duty delay cell = 0
2333 15:37:01.481385 [0] MAX Duty = 5125%(X100), DQS PI = 58
2334 15:37:01.484565 [0] MIN Duty = 5031%(X100), DQS PI = 52
2335 15:37:01.487888 [0] AVG Duty = 5078%(X100)
2336 15:37:01.487970
2337 15:37:01.491223 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2338 15:37:01.491298
2339 15:37:01.494557 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2340 15:37:01.498297 [DutyScan_Calibration_Flow] ====Done====
2341 15:37:01.498398
2342 15:37:01.501524 [DutyScan_Calibration_Flow] k_type=2
2343 15:37:01.518181
2344 15:37:01.518291 ==DQ 0 ==
2345 15:37:01.521946 Final DQ duty delay cell = 0
2346 15:37:01.524923 [0] MAX Duty = 5062%(X100), DQS PI = 32
2347 15:37:01.527901 [0] MIN Duty = 4906%(X100), DQS PI = 0
2348 15:37:01.528006 [0] AVG Duty = 4984%(X100)
2349 15:37:01.528099
2350 15:37:01.531807 ==DQ 1 ==
2351 15:37:01.535146 Final DQ duty delay cell = 0
2352 15:37:01.538506 [0] MAX Duty = 5093%(X100), DQS PI = 8
2353 15:37:01.541690 [0] MIN Duty = 4938%(X100), DQS PI = 36
2354 15:37:01.541796 [0] AVG Duty = 5015%(X100)
2355 15:37:01.541889
2356 15:37:01.544864 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2357 15:37:01.544971
2358 15:37:01.548069 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2359 15:37:01.554694 [DutyScan_Calibration_Flow] ====Done====
2360 15:37:01.554801 ==
2361 15:37:01.557865 Dram Type= 6, Freq= 0, CH_1, rank 0
2362 15:37:01.561503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 15:37:01.561609 ==
2364 15:37:01.564836 [Duty_Offset_Calibration]
2365 15:37:01.564940 B0:1 B1:0 CA:0
2366 15:37:01.565033
2367 15:37:01.568231 [DutyScan_Calibration_Flow] k_type=0
2368 15:37:01.577310
2369 15:37:01.577416 ==CLK 0==
2370 15:37:01.580422 Final CLK duty delay cell = -4
2371 15:37:01.583950 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2372 15:37:01.587035 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2373 15:37:01.590677 [-4] AVG Duty = 4969%(X100)
2374 15:37:01.590793
2375 15:37:01.594080 CH1 CLK Duty spec in!! Max-Min= 124%
2376 15:37:01.597279 [DutyScan_Calibration_Flow] ====Done====
2377 15:37:01.597411
2378 15:37:01.600499 [DutyScan_Calibration_Flow] k_type=1
2379 15:37:01.616952
2380 15:37:01.617061 ==DQS 0 ==
2381 15:37:01.620193 Final DQS duty delay cell = 0
2382 15:37:01.623976 [0] MAX Duty = 5062%(X100), DQS PI = 12
2383 15:37:01.626733 [0] MIN Duty = 4875%(X100), DQS PI = 0
2384 15:37:01.626848 [0] AVG Duty = 4968%(X100)
2385 15:37:01.630625
2386 15:37:01.630729 ==DQS 1 ==
2387 15:37:01.633493 Final DQS duty delay cell = 0
2388 15:37:01.637134 [0] MAX Duty = 5187%(X100), DQS PI = 18
2389 15:37:01.640268 [0] MIN Duty = 4969%(X100), DQS PI = 10
2390 15:37:01.640384 [0] AVG Duty = 5078%(X100)
2391 15:37:01.643551
2392 15:37:01.646940 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2393 15:37:01.647047
2394 15:37:01.650242 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2395 15:37:01.653532 [DutyScan_Calibration_Flow] ====Done====
2396 15:37:01.653635
2397 15:37:01.657128 [DutyScan_Calibration_Flow] k_type=3
2398 15:37:01.673550
2399 15:37:01.673672 ==DQM 0 ==
2400 15:37:01.676868 Final DQM duty delay cell = 0
2401 15:37:01.680290 [0] MAX Duty = 5156%(X100), DQS PI = 8
2402 15:37:01.683377 [0] MIN Duty = 5031%(X100), DQS PI = 0
2403 15:37:01.683479 [0] AVG Duty = 5093%(X100)
2404 15:37:01.687171
2405 15:37:01.687291 ==DQM 1 ==
2406 15:37:01.690218 Final DQM duty delay cell = 0
2407 15:37:01.693330 [0] MAX Duty = 5031%(X100), DQS PI = 14
2408 15:37:01.697187 [0] MIN Duty = 4907%(X100), DQS PI = 36
2409 15:37:01.697269 [0] AVG Duty = 4969%(X100)
2410 15:37:01.697348
2411 15:37:01.703608 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2412 15:37:01.703708
2413 15:37:01.706767 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2414 15:37:01.710202 [DutyScan_Calibration_Flow] ====Done====
2415 15:37:01.710325
2416 15:37:01.713562 [DutyScan_Calibration_Flow] k_type=2
2417 15:37:01.729036
2418 15:37:01.729163 ==DQ 0 ==
2419 15:37:01.732443 Final DQ duty delay cell = -4
2420 15:37:01.735797 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2421 15:37:01.739669 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2422 15:37:01.742872 [-4] AVG Duty = 4984%(X100)
2423 15:37:01.742974
2424 15:37:01.743056 ==DQ 1 ==
2425 15:37:01.746002 Final DQ duty delay cell = 0
2426 15:37:01.749753 [0] MAX Duty = 5125%(X100), DQS PI = 20
2427 15:37:01.752999 [0] MIN Duty = 4969%(X100), DQS PI = 12
2428 15:37:01.753115 [0] AVG Duty = 5047%(X100)
2429 15:37:01.756371
2430 15:37:01.759583 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2431 15:37:01.759677
2432 15:37:01.762891 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2433 15:37:01.766269 [DutyScan_Calibration_Flow] ====Done====
2434 15:37:01.769533 nWR fixed to 30
2435 15:37:01.769641 [ModeRegInit_LP4] CH0 RK0
2436 15:37:01.772690 [ModeRegInit_LP4] CH0 RK1
2437 15:37:01.775797 [ModeRegInit_LP4] CH1 RK0
2438 15:37:01.779635 [ModeRegInit_LP4] CH1 RK1
2439 15:37:01.779713 match AC timing 7
2440 15:37:01.782672 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2441 15:37:01.785910 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2442 15:37:01.793219 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2443 15:37:01.796322 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2444 15:37:01.802795 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2445 15:37:01.802882 ==
2446 15:37:01.806531 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 15:37:01.809485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 15:37:01.809598 ==
2449 15:37:01.815922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2450 15:37:01.819788 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2451 15:37:01.829610 [CA 0] Center 39 (8~70) winsize 63
2452 15:37:01.832728 [CA 1] Center 39 (8~70) winsize 63
2453 15:37:01.835942 [CA 2] Center 35 (5~66) winsize 62
2454 15:37:01.840051 [CA 3] Center 34 (4~65) winsize 62
2455 15:37:01.843314 [CA 4] Center 33 (3~64) winsize 62
2456 15:37:01.845945 [CA 5] Center 32 (3~62) winsize 60
2457 15:37:01.846026
2458 15:37:01.849789 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2459 15:37:01.849876
2460 15:37:01.852976 [CATrainingPosCal] consider 1 rank data
2461 15:37:01.856117 u2DelayCellTimex100 = 270/100 ps
2462 15:37:01.859466 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2463 15:37:01.862842 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2464 15:37:01.869900 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2465 15:37:01.873275 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2466 15:37:01.876639 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2467 15:37:01.879903 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2468 15:37:01.880002
2469 15:37:01.883147 CA PerBit enable=1, Macro0, CA PI delay=32
2470 15:37:01.883247
2471 15:37:01.886268 [CBTSetCACLKResult] CA Dly = 32
2472 15:37:01.886377 CS Dly: 6 (0~37)
2473 15:37:01.886470 ==
2474 15:37:01.890105 Dram Type= 6, Freq= 0, CH_0, rank 1
2475 15:37:01.896297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 15:37:01.896413 ==
2477 15:37:01.899659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 15:37:01.906503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2479 15:37:01.915373 [CA 0] Center 38 (8~69) winsize 62
2480 15:37:01.918578 [CA 1] Center 38 (8~69) winsize 62
2481 15:37:01.922160 [CA 2] Center 35 (5~66) winsize 62
2482 15:37:01.925214 [CA 3] Center 34 (4~65) winsize 62
2483 15:37:01.928433 [CA 4] Center 33 (3~64) winsize 62
2484 15:37:01.931723 [CA 5] Center 32 (3~62) winsize 60
2485 15:37:01.931805
2486 15:37:01.935573 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2487 15:37:01.935688
2488 15:37:01.938935 [CATrainingPosCal] consider 2 rank data
2489 15:37:01.942100 u2DelayCellTimex100 = 270/100 ps
2490 15:37:01.945408 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2491 15:37:01.948744 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2492 15:37:01.955140 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2493 15:37:01.958317 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2494 15:37:01.962125 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2495 15:37:01.965318 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2496 15:37:01.965423
2497 15:37:01.968484 CA PerBit enable=1, Macro0, CA PI delay=32
2498 15:37:01.968559
2499 15:37:01.971846 [CBTSetCACLKResult] CA Dly = 32
2500 15:37:01.971924 CS Dly: 7 (0~39)
2501 15:37:01.972004
2502 15:37:01.975192 ----->DramcWriteLeveling(PI) begin...
2503 15:37:01.978408 ==
2504 15:37:01.978482 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 15:37:01.985204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 15:37:01.985331 ==
2507 15:37:01.989090 Write leveling (Byte 0): 35 => 35
2508 15:37:01.992308 Write leveling (Byte 1): 29 => 29
2509 15:37:01.995483 DramcWriteLeveling(PI) end<-----
2510 15:37:01.995571
2511 15:37:01.995643 ==
2512 15:37:01.998579 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 15:37:02.002283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 15:37:02.002404 ==
2515 15:37:02.005268 [Gating] SW mode calibration
2516 15:37:02.012048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2517 15:37:02.015268 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2518 15:37:02.021996 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (0 0)
2519 15:37:02.025129 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2520 15:37:02.028472 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 15:37:02.035410 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 15:37:02.038656 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 15:37:02.041822 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 15:37:02.048845 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2525 15:37:02.052007 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2526 15:37:02.055341 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2527 15:37:02.061737 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 15:37:02.065091 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 15:37:02.068675 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 15:37:02.075435 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 15:37:02.078880 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 15:37:02.081967 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2533 15:37:02.088605 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2534 15:37:02.091956 1 1 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2535 15:37:02.095318 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 15:37:02.101941 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 15:37:02.105158 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 15:37:02.108899 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 15:37:02.112164 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 15:37:02.118543 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 15:37:02.122001 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2542 15:37:02.125353 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2543 15:37:02.132488 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 15:37:02.135391 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 15:37:02.138607 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 15:37:02.145679 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 15:37:02.148990 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 15:37:02.152429 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 15:37:02.159034 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 15:37:02.162250 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 15:37:02.165490 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 15:37:02.172254 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 15:37:02.175409 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 15:37:02.179338 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 15:37:02.182215 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 15:37:02.189004 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2557 15:37:02.192319 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 15:37:02.195438 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 15:37:02.199445 Total UI for P1: 0, mck2ui 16
2560 15:37:02.202231 best dqsien dly found for B0: ( 1, 3, 26)
2561 15:37:02.209369 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 15:37:02.209516 Total UI for P1: 0, mck2ui 16
2563 15:37:02.215981 best dqsien dly found for B1: ( 1, 4, 0)
2564 15:37:02.219429 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2565 15:37:02.222701 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2566 15:37:02.222812
2567 15:37:02.225719 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2568 15:37:02.229349 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2569 15:37:02.232200 [Gating] SW calibration Done
2570 15:37:02.232295 ==
2571 15:37:02.235630 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 15:37:02.239344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 15:37:02.239472 ==
2574 15:37:02.242489 RX Vref Scan: 0
2575 15:37:02.242614
2576 15:37:02.242723 RX Vref 0 -> 0, step: 1
2577 15:37:02.242822
2578 15:37:02.245592 RX Delay -40 -> 252, step: 8
2579 15:37:02.249080 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2580 15:37:02.252715 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2581 15:37:02.259328 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2582 15:37:02.262770 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2583 15:37:02.266296 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2584 15:37:02.269403 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2585 15:37:02.272610 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2586 15:37:02.279443 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2587 15:37:02.282752 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2588 15:37:02.286492 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2589 15:37:02.289385 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2590 15:37:02.292528 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2591 15:37:02.299571 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2592 15:37:02.302796 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2593 15:37:02.306038 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2594 15:37:02.309424 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2595 15:37:02.309526 ==
2596 15:37:02.312616 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 15:37:02.316423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 15:37:02.319562 ==
2599 15:37:02.319687 DQS Delay:
2600 15:37:02.319785 DQS0 = 0, DQS1 = 0
2601 15:37:02.322843 DQM Delay:
2602 15:37:02.322964 DQM0 = 121, DQM1 = 113
2603 15:37:02.325924 DQ Delay:
2604 15:37:02.329303 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2605 15:37:02.333247 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2606 15:37:02.336599 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2607 15:37:02.339738 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2608 15:37:02.339858
2609 15:37:02.339954
2610 15:37:02.340046 ==
2611 15:37:02.342723 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 15:37:02.346581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 15:37:02.346700 ==
2614 15:37:02.346810
2615 15:37:02.346911
2616 15:37:02.349480 TX Vref Scan disable
2617 15:37:02.352891 == TX Byte 0 ==
2618 15:37:02.356491 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2619 15:37:02.360006 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2620 15:37:02.363219 == TX Byte 1 ==
2621 15:37:02.366368 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2622 15:37:02.369531 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2623 15:37:02.369641 ==
2624 15:37:02.373327 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 15:37:02.376679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 15:37:02.379450 ==
2627 15:37:02.390651 TX Vref=22, minBit 4, minWin=24, winSum=406
2628 15:37:02.394025 TX Vref=24, minBit 0, minWin=24, winSum=411
2629 15:37:02.397007 TX Vref=26, minBit 2, minWin=25, winSum=415
2630 15:37:02.400636 TX Vref=28, minBit 0, minWin=26, winSum=421
2631 15:37:02.403671 TX Vref=30, minBit 0, minWin=26, winSum=422
2632 15:37:02.406854 TX Vref=32, minBit 5, minWin=25, winSum=420
2633 15:37:02.413956 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 30
2634 15:37:02.414085
2635 15:37:02.417258 Final TX Range 1 Vref 30
2636 15:37:02.417377
2637 15:37:02.417473 ==
2638 15:37:02.420542 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 15:37:02.423774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 15:37:02.423884 ==
2641 15:37:02.423979
2642 15:37:02.424079
2643 15:37:02.426942 TX Vref Scan disable
2644 15:37:02.431008 == TX Byte 0 ==
2645 15:37:02.433536 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2646 15:37:02.437488 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2647 15:37:02.440674 == TX Byte 1 ==
2648 15:37:02.444070 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2649 15:37:02.447285 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2650 15:37:02.447389
2651 15:37:02.450514 [DATLAT]
2652 15:37:02.450628 Freq=1200, CH0 RK0
2653 15:37:02.450727
2654 15:37:02.453572 DATLAT Default: 0xd
2655 15:37:02.453688 0, 0xFFFF, sum = 0
2656 15:37:02.457357 1, 0xFFFF, sum = 0
2657 15:37:02.457468 2, 0xFFFF, sum = 0
2658 15:37:02.460489 3, 0xFFFF, sum = 0
2659 15:37:02.460592 4, 0xFFFF, sum = 0
2660 15:37:02.463826 5, 0xFFFF, sum = 0
2661 15:37:02.463912 6, 0xFFFF, sum = 0
2662 15:37:02.467214 7, 0xFFFF, sum = 0
2663 15:37:02.467318 8, 0xFFFF, sum = 0
2664 15:37:02.470692 9, 0xFFFF, sum = 0
2665 15:37:02.470801 10, 0xFFFF, sum = 0
2666 15:37:02.474077 11, 0xFFFF, sum = 0
2667 15:37:02.474160 12, 0x0, sum = 1
2668 15:37:02.477088 13, 0x0, sum = 2
2669 15:37:02.477199 14, 0x0, sum = 3
2670 15:37:02.480756 15, 0x0, sum = 4
2671 15:37:02.480850 best_step = 13
2672 15:37:02.480951
2673 15:37:02.481051 ==
2674 15:37:02.484020 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 15:37:02.490462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 15:37:02.490570 ==
2677 15:37:02.490670 RX Vref Scan: 1
2678 15:37:02.490769
2679 15:37:02.493540 Set Vref Range= 32 -> 127
2680 15:37:02.493650
2681 15:37:02.497352 RX Vref 32 -> 127, step: 1
2682 15:37:02.497454
2683 15:37:02.500492 RX Delay -13 -> 252, step: 4
2684 15:37:02.500593
2685 15:37:02.503533 Set Vref, RX VrefLevel [Byte0]: 32
2686 15:37:02.506903 [Byte1]: 32
2687 15:37:02.507008
2688 15:37:02.510136 Set Vref, RX VrefLevel [Byte0]: 33
2689 15:37:02.513920 [Byte1]: 33
2690 15:37:02.514024
2691 15:37:02.517121 Set Vref, RX VrefLevel [Byte0]: 34
2692 15:37:02.520481 [Byte1]: 34
2693 15:37:02.524428
2694 15:37:02.524544 Set Vref, RX VrefLevel [Byte0]: 35
2695 15:37:02.527826 [Byte1]: 35
2696 15:37:02.532555
2697 15:37:02.532634 Set Vref, RX VrefLevel [Byte0]: 36
2698 15:37:02.535733 [Byte1]: 36
2699 15:37:02.540444
2700 15:37:02.540553 Set Vref, RX VrefLevel [Byte0]: 37
2701 15:37:02.543669 [Byte1]: 37
2702 15:37:02.548329
2703 15:37:02.548403 Set Vref, RX VrefLevel [Byte0]: 38
2704 15:37:02.551046 [Byte1]: 38
2705 15:37:02.555574
2706 15:37:02.555665 Set Vref, RX VrefLevel [Byte0]: 39
2707 15:37:02.559484 [Byte1]: 39
2708 15:37:02.564123
2709 15:37:02.564202 Set Vref, RX VrefLevel [Byte0]: 40
2710 15:37:02.567287 [Byte1]: 40
2711 15:37:02.571383
2712 15:37:02.571456 Set Vref, RX VrefLevel [Byte0]: 41
2713 15:37:02.575211 [Byte1]: 41
2714 15:37:02.579739
2715 15:37:02.579841 Set Vref, RX VrefLevel [Byte0]: 42
2716 15:37:02.582676 [Byte1]: 42
2717 15:37:02.587667
2718 15:37:02.587780 Set Vref, RX VrefLevel [Byte0]: 43
2719 15:37:02.590772 [Byte1]: 43
2720 15:37:02.595181
2721 15:37:02.595257 Set Vref, RX VrefLevel [Byte0]: 44
2722 15:37:02.598391 [Byte1]: 44
2723 15:37:02.603204
2724 15:37:02.603310 Set Vref, RX VrefLevel [Byte0]: 45
2725 15:37:02.606421 [Byte1]: 45
2726 15:37:02.611041
2727 15:37:02.611120 Set Vref, RX VrefLevel [Byte0]: 46
2728 15:37:02.614396 [Byte1]: 46
2729 15:37:02.618832
2730 15:37:02.618939 Set Vref, RX VrefLevel [Byte0]: 47
2731 15:37:02.622447 [Byte1]: 47
2732 15:37:02.626644
2733 15:37:02.626726 Set Vref, RX VrefLevel [Byte0]: 48
2734 15:37:02.630261 [Byte1]: 48
2735 15:37:02.634907
2736 15:37:02.635013 Set Vref, RX VrefLevel [Byte0]: 49
2737 15:37:02.638073 [Byte1]: 49
2738 15:37:02.642916
2739 15:37:02.643018 Set Vref, RX VrefLevel [Byte0]: 50
2740 15:37:02.646202 [Byte1]: 50
2741 15:37:02.650844
2742 15:37:02.650919 Set Vref, RX VrefLevel [Byte0]: 51
2743 15:37:02.654190 [Byte1]: 51
2744 15:37:02.658652
2745 15:37:02.658758 Set Vref, RX VrefLevel [Byte0]: 52
2746 15:37:02.662067 [Byte1]: 52
2747 15:37:02.666588
2748 15:37:02.666671 Set Vref, RX VrefLevel [Byte0]: 53
2749 15:37:02.669330 [Byte1]: 53
2750 15:37:02.674011
2751 15:37:02.674115 Set Vref, RX VrefLevel [Byte0]: 54
2752 15:37:02.677309 [Byte1]: 54
2753 15:37:02.682039
2754 15:37:02.682129 Set Vref, RX VrefLevel [Byte0]: 55
2755 15:37:02.685395 [Byte1]: 55
2756 15:37:02.690134
2757 15:37:02.690239 Set Vref, RX VrefLevel [Byte0]: 56
2758 15:37:02.692944 [Byte1]: 56
2759 15:37:02.698058
2760 15:37:02.698138 Set Vref, RX VrefLevel [Byte0]: 57
2761 15:37:02.701418 [Byte1]: 57
2762 15:37:02.705664
2763 15:37:02.705745 Set Vref, RX VrefLevel [Byte0]: 58
2764 15:37:02.709232 [Byte1]: 58
2765 15:37:02.713413
2766 15:37:02.713518 Set Vref, RX VrefLevel [Byte0]: 59
2767 15:37:02.717092 [Byte1]: 59
2768 15:37:02.721365
2769 15:37:02.721469 Set Vref, RX VrefLevel [Byte0]: 60
2770 15:37:02.724895 [Byte1]: 60
2771 15:37:02.729110
2772 15:37:02.729214 Set Vref, RX VrefLevel [Byte0]: 61
2773 15:37:02.733019 [Byte1]: 61
2774 15:37:02.737063
2775 15:37:02.737167 Set Vref, RX VrefLevel [Byte0]: 62
2776 15:37:02.740489 [Byte1]: 62
2777 15:37:02.745009
2778 15:37:02.745121 Set Vref, RX VrefLevel [Byte0]: 63
2779 15:37:02.748113 [Byte1]: 63
2780 15:37:02.752806
2781 15:37:02.752915 Set Vref, RX VrefLevel [Byte0]: 64
2782 15:37:02.756087 [Byte1]: 64
2783 15:37:02.760800
2784 15:37:02.760904 Set Vref, RX VrefLevel [Byte0]: 65
2785 15:37:02.764047 [Byte1]: 65
2786 15:37:02.768619
2787 15:37:02.768721 Set Vref, RX VrefLevel [Byte0]: 66
2788 15:37:02.771955 [Byte1]: 66
2789 15:37:02.776611
2790 15:37:02.776714 Set Vref, RX VrefLevel [Byte0]: 67
2791 15:37:02.779840 [Byte1]: 67
2792 15:37:02.784640
2793 15:37:02.784741 Set Vref, RX VrefLevel [Byte0]: 68
2794 15:37:02.787980 [Byte1]: 68
2795 15:37:02.792458
2796 15:37:02.792558 Final RX Vref Byte 0 = 55 to rank0
2797 15:37:02.795718 Final RX Vref Byte 1 = 46 to rank0
2798 15:37:02.798982 Final RX Vref Byte 0 = 55 to rank1
2799 15:37:02.802267 Final RX Vref Byte 1 = 46 to rank1==
2800 15:37:02.805632 Dram Type= 6, Freq= 0, CH_0, rank 0
2801 15:37:02.812922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2802 15:37:02.813009 ==
2803 15:37:02.813077 DQS Delay:
2804 15:37:02.813155 DQS0 = 0, DQS1 = 0
2805 15:37:02.815955 DQM Delay:
2806 15:37:02.816033 DQM0 = 120, DQM1 = 111
2807 15:37:02.819082 DQ Delay:
2808 15:37:02.822916 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =120
2809 15:37:02.826155 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =124
2810 15:37:02.829369 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =104
2811 15:37:02.832710 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2812 15:37:02.832826
2813 15:37:02.832919
2814 15:37:02.839515 [DQSOSCAuto] RK0, (LSB)MR18= 0x1811, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
2815 15:37:02.842542 CH0 RK0: MR19=404, MR18=1811
2816 15:37:02.849388 CH0_RK0: MR19=0x404, MR18=0x1811, DQSOSC=400, MR23=63, INC=40, DEC=27
2817 15:37:02.849469
2818 15:37:02.852914 ----->DramcWriteLeveling(PI) begin...
2819 15:37:02.852997 ==
2820 15:37:02.856363 Dram Type= 6, Freq= 0, CH_0, rank 1
2821 15:37:02.859869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 15:37:02.859953 ==
2823 15:37:02.862935 Write leveling (Byte 0): 33 => 33
2824 15:37:02.866195 Write leveling (Byte 1): 28 => 28
2825 15:37:02.869428 DramcWriteLeveling(PI) end<-----
2826 15:37:02.869535
2827 15:37:02.869632 ==
2828 15:37:02.872665 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 15:37:02.875843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 15:37:02.879798 ==
2831 15:37:02.879875 [Gating] SW mode calibration
2832 15:37:02.889518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2833 15:37:02.892752 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2834 15:37:02.896069 0 15 0 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
2835 15:37:02.902618 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 15:37:02.905986 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 15:37:02.909350 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 15:37:02.915953 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 15:37:02.919167 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 15:37:02.922386 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 15:37:02.929468 0 15 28 | B1->B0 | 2f2f 2b2b | 1 0 | (1 0) (0 0)
2842 15:37:02.932627 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 15:37:02.935907 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 15:37:02.942837 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 15:37:02.945936 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 15:37:02.949082 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 15:37:02.956252 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 15:37:02.959548 1 0 24 | B1->B0 | 2828 2525 | 0 1 | (0 0) (0 0)
2849 15:37:02.962603 1 0 28 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 1)
2850 15:37:02.969118 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 15:37:02.972500 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 15:37:02.976301 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 15:37:02.979404 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 15:37:02.985873 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 15:37:02.989717 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 15:37:02.992980 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 15:37:02.999565 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2858 15:37:03.002903 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 15:37:03.006209 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 15:37:03.012748 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 15:37:03.016102 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 15:37:03.019470 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 15:37:03.026119 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 15:37:03.029250 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 15:37:03.033086 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 15:37:03.039329 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 15:37:03.042498 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 15:37:03.045841 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 15:37:03.052599 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 15:37:03.055935 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 15:37:03.059333 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 15:37:03.063233 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 15:37:03.069727 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2874 15:37:03.072984 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 15:37:03.076127 Total UI for P1: 0, mck2ui 16
2876 15:37:03.079317 best dqsien dly found for B0: ( 1, 3, 28)
2877 15:37:03.083079 Total UI for P1: 0, mck2ui 16
2878 15:37:03.086479 best dqsien dly found for B1: ( 1, 3, 28)
2879 15:37:03.089306 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2880 15:37:03.092845 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2881 15:37:03.092932
2882 15:37:03.096045 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2883 15:37:03.099416 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2884 15:37:03.102793 [Gating] SW calibration Done
2885 15:37:03.102869 ==
2886 15:37:03.105984 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 15:37:03.109335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 15:37:03.112653 ==
2889 15:37:03.112738 RX Vref Scan: 0
2890 15:37:03.112808
2891 15:37:03.116035 RX Vref 0 -> 0, step: 1
2892 15:37:03.116186
2893 15:37:03.119368 RX Delay -40 -> 252, step: 8
2894 15:37:03.122704 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2895 15:37:03.126006 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2896 15:37:03.129370 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2897 15:37:03.133121 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2898 15:37:03.139713 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2899 15:37:03.142755 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2900 15:37:03.146502 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2901 15:37:03.149984 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2902 15:37:03.153208 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2903 15:37:03.156348 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2904 15:37:03.163274 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2905 15:37:03.166596 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2906 15:37:03.169328 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2907 15:37:03.173239 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2908 15:37:03.176588 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2909 15:37:03.183290 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2910 15:37:03.183381 ==
2911 15:37:03.186462 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 15:37:03.189794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 15:37:03.189882 ==
2914 15:37:03.189946 DQS Delay:
2915 15:37:03.193376 DQS0 = 0, DQS1 = 0
2916 15:37:03.193455 DQM Delay:
2917 15:37:03.196374 DQM0 = 122, DQM1 = 112
2918 15:37:03.196457 DQ Delay:
2919 15:37:03.200028 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2920 15:37:03.202931 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2921 15:37:03.206491 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2922 15:37:03.210083 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2923 15:37:03.210172
2924 15:37:03.210237
2925 15:37:03.213296 ==
2926 15:37:03.216537 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 15:37:03.220281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 15:37:03.220377 ==
2929 15:37:03.220447
2930 15:37:03.220514
2931 15:37:03.223369 TX Vref Scan disable
2932 15:37:03.223458 == TX Byte 0 ==
2933 15:37:03.226799 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2934 15:37:03.233145 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2935 15:37:03.233273 == TX Byte 1 ==
2936 15:37:03.236262 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2937 15:37:03.243419 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2938 15:37:03.243540 ==
2939 15:37:03.246634 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 15:37:03.249638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 15:37:03.249731 ==
2942 15:37:03.261974 TX Vref=22, minBit 1, minWin=25, winSum=415
2943 15:37:03.265796 TX Vref=24, minBit 2, minWin=25, winSum=419
2944 15:37:03.268770 TX Vref=26, minBit 0, minWin=26, winSum=423
2945 15:37:03.272011 TX Vref=28, minBit 0, minWin=26, winSum=425
2946 15:37:03.275844 TX Vref=30, minBit 0, minWin=26, winSum=426
2947 15:37:03.282516 TX Vref=32, minBit 0, minWin=25, winSum=419
2948 15:37:03.285206 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
2949 15:37:03.285342
2950 15:37:03.289095 Final TX Range 1 Vref 30
2951 15:37:03.289176
2952 15:37:03.289256 ==
2953 15:37:03.292404 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 15:37:03.295576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 15:37:03.295702 ==
2956 15:37:03.298651
2957 15:37:03.298767
2958 15:37:03.298874 TX Vref Scan disable
2959 15:37:03.302412 == TX Byte 0 ==
2960 15:37:03.305766 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2961 15:37:03.309098 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2962 15:37:03.312225 == TX Byte 1 ==
2963 15:37:03.315418 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2964 15:37:03.318496 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2965 15:37:03.322273
2966 15:37:03.322371 [DATLAT]
2967 15:37:03.322436 Freq=1200, CH0 RK1
2968 15:37:03.322497
2969 15:37:03.325494 DATLAT Default: 0xd
2970 15:37:03.325572 0, 0xFFFF, sum = 0
2971 15:37:03.328914 1, 0xFFFF, sum = 0
2972 15:37:03.329013 2, 0xFFFF, sum = 0
2973 15:37:03.332225 3, 0xFFFF, sum = 0
2974 15:37:03.332305 4, 0xFFFF, sum = 0
2975 15:37:03.335414 5, 0xFFFF, sum = 0
2976 15:37:03.338768 6, 0xFFFF, sum = 0
2977 15:37:03.338849 7, 0xFFFF, sum = 0
2978 15:37:03.342039 8, 0xFFFF, sum = 0
2979 15:37:03.342119 9, 0xFFFF, sum = 0
2980 15:37:03.345450 10, 0xFFFF, sum = 0
2981 15:37:03.345569 11, 0xFFFF, sum = 0
2982 15:37:03.348481 12, 0x0, sum = 1
2983 15:37:03.348589 13, 0x0, sum = 2
2984 15:37:03.352515 14, 0x0, sum = 3
2985 15:37:03.352638 15, 0x0, sum = 4
2986 15:37:03.352743 best_step = 13
2987 15:37:03.352837
2988 15:37:03.355795 ==
2989 15:37:03.358892 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 15:37:03.361931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 15:37:03.362055 ==
2992 15:37:03.362160 RX Vref Scan: 0
2993 15:37:03.362260
2994 15:37:03.365166 RX Vref 0 -> 0, step: 1
2995 15:37:03.365254
2996 15:37:03.369079 RX Delay -13 -> 252, step: 4
2997 15:37:03.372321 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
2998 15:37:03.378426 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
2999 15:37:03.381999 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3000 15:37:03.385084 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3001 15:37:03.388787 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3002 15:37:03.392037 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3003 15:37:03.395393 iDelay=195, Bit 6, Center 126 (63 ~ 190) 128
3004 15:37:03.401948 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3005 15:37:03.405622 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3006 15:37:03.408893 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3007 15:37:03.412050 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3008 15:37:03.415111 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3009 15:37:03.422417 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3010 15:37:03.425697 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3011 15:37:03.428738 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3012 15:37:03.431877 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3013 15:37:03.432026 ==
3014 15:37:03.435863 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 15:37:03.442371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 15:37:03.442507 ==
3017 15:37:03.442618 DQS Delay:
3018 15:37:03.445790 DQS0 = 0, DQS1 = 0
3019 15:37:03.445898 DQM Delay:
3020 15:37:03.445999 DQM0 = 121, DQM1 = 109
3021 15:37:03.449093 DQ Delay:
3022 15:37:03.451976 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3023 15:37:03.455882 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3024 15:37:03.459192 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3025 15:37:03.462520 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3026 15:37:03.462631
3027 15:37:03.462730
3028 15:37:03.469414 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3029 15:37:03.472566 CH0 RK1: MR19=403, MR18=10F0
3030 15:37:03.478944 CH0_RK1: MR19=0x403, MR18=0x10F0, DQSOSC=403, MR23=63, INC=40, DEC=26
3031 15:37:03.482225 [RxdqsGatingPostProcess] freq 1200
3032 15:37:03.489268 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3033 15:37:03.492509 best DQS0 dly(2T, 0.5T) = (0, 11)
3034 15:37:03.492621 best DQS1 dly(2T, 0.5T) = (0, 12)
3035 15:37:03.495587 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3036 15:37:03.499194 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3037 15:37:03.502262 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 15:37:03.505538 best DQS1 dly(2T, 0.5T) = (0, 11)
3039 15:37:03.509443 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 15:37:03.512777 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3041 15:37:03.515915 Pre-setting of DQS Precalculation
3042 15:37:03.522256 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3043 15:37:03.522383 ==
3044 15:37:03.526157 Dram Type= 6, Freq= 0, CH_1, rank 0
3045 15:37:03.529373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 15:37:03.529489 ==
3047 15:37:03.535786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3048 15:37:03.538891 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3049 15:37:03.548717 [CA 0] Center 37 (7~68) winsize 62
3050 15:37:03.552032 [CA 1] Center 37 (7~68) winsize 62
3051 15:37:03.555165 [CA 2] Center 35 (5~65) winsize 61
3052 15:37:03.558327 [CA 3] Center 34 (4~64) winsize 61
3053 15:37:03.561981 [CA 4] Center 34 (4~64) winsize 61
3054 15:37:03.565314 [CA 5] Center 33 (3~63) winsize 61
3055 15:37:03.565420
3056 15:37:03.568437 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3057 15:37:03.568550
3058 15:37:03.572318 [CATrainingPosCal] consider 1 rank data
3059 15:37:03.575572 u2DelayCellTimex100 = 270/100 ps
3060 15:37:03.578554 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3061 15:37:03.582313 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3062 15:37:03.585484 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3063 15:37:03.592074 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3064 15:37:03.595310 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3065 15:37:03.598599 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3066 15:37:03.598681
3067 15:37:03.601895 CA PerBit enable=1, Macro0, CA PI delay=33
3068 15:37:03.602002
3069 15:37:03.605635 [CBTSetCACLKResult] CA Dly = 33
3070 15:37:03.605739 CS Dly: 7 (0~38)
3071 15:37:03.605832 ==
3072 15:37:03.608681 Dram Type= 6, Freq= 0, CH_1, rank 1
3073 15:37:03.615561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 15:37:03.615683 ==
3075 15:37:03.618920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3076 15:37:03.625269 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3077 15:37:03.634302 [CA 0] Center 37 (7~68) winsize 62
3078 15:37:03.637469 [CA 1] Center 38 (8~68) winsize 61
3079 15:37:03.640648 [CA 2] Center 35 (5~65) winsize 61
3080 15:37:03.644137 [CA 3] Center 34 (4~65) winsize 62
3081 15:37:03.647967 [CA 4] Center 34 (4~65) winsize 62
3082 15:37:03.651274 [CA 5] Center 34 (4~64) winsize 61
3083 15:37:03.651391
3084 15:37:03.654672 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3085 15:37:03.654758
3086 15:37:03.657927 [CATrainingPosCal] consider 2 rank data
3087 15:37:03.661166 u2DelayCellTimex100 = 270/100 ps
3088 15:37:03.664539 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3089 15:37:03.667580 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3090 15:37:03.671488 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3091 15:37:03.677914 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 15:37:03.681159 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3093 15:37:03.684286 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3094 15:37:03.684365
3095 15:37:03.687866 CA PerBit enable=1, Macro0, CA PI delay=33
3096 15:37:03.687948
3097 15:37:03.691074 [CBTSetCACLKResult] CA Dly = 33
3098 15:37:03.691184 CS Dly: 8 (0~41)
3099 15:37:03.691275
3100 15:37:03.694399 ----->DramcWriteLeveling(PI) begin...
3101 15:37:03.694509 ==
3102 15:37:03.697958 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 15:37:03.704398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 15:37:03.704485 ==
3105 15:37:03.707859 Write leveling (Byte 0): 27 => 27
3106 15:37:03.707968 Write leveling (Byte 1): 27 => 27
3107 15:37:03.711164 DramcWriteLeveling(PI) end<-----
3108 15:37:03.711273
3109 15:37:03.714844 ==
3110 15:37:03.714959 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 15:37:03.721210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 15:37:03.721327 ==
3113 15:37:03.724789 [Gating] SW mode calibration
3114 15:37:03.731391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3115 15:37:03.734483 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3116 15:37:03.741204 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3117 15:37:03.744861 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 15:37:03.748250 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 15:37:03.754549 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 15:37:03.757892 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 15:37:03.761178 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 15:37:03.768311 0 15 24 | B1->B0 | 3232 2828 | 0 0 | (0 0) (0 1)
3123 15:37:03.771340 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3124 15:37:03.774665 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 15:37:03.778045 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 15:37:03.784507 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 15:37:03.788257 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 15:37:03.791498 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 15:37:03.798118 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 15:37:03.801459 1 0 24 | B1->B0 | 3030 3d3c | 1 1 | (0 0) (0 0)
3131 15:37:03.804833 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 15:37:03.811439 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 15:37:03.814761 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 15:37:03.818042 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 15:37:03.825299 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 15:37:03.828028 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 15:37:03.831664 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 15:37:03.838520 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3139 15:37:03.841376 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3140 15:37:03.844947 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 15:37:03.848409 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 15:37:03.854847 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 15:37:03.858540 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 15:37:03.861608 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 15:37:03.868091 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 15:37:03.872130 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 15:37:03.875260 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 15:37:03.881797 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 15:37:03.885183 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 15:37:03.888562 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 15:37:03.895295 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 15:37:03.898663 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 15:37:03.901795 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 15:37:03.908333 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3155 15:37:03.912054 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3156 15:37:03.915281 Total UI for P1: 0, mck2ui 16
3157 15:37:03.918725 best dqsien dly found for B0: ( 1, 3, 24)
3158 15:37:03.922093 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 15:37:03.925287 Total UI for P1: 0, mck2ui 16
3160 15:37:03.928488 best dqsien dly found for B1: ( 1, 3, 26)
3161 15:37:03.931766 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3162 15:37:03.934875 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3163 15:37:03.934992
3164 15:37:03.938220 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3165 15:37:03.945198 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3166 15:37:03.945281 [Gating] SW calibration Done
3167 15:37:03.945346 ==
3168 15:37:03.948499 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 15:37:03.955246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 15:37:03.955370 ==
3171 15:37:03.955471 RX Vref Scan: 0
3172 15:37:03.955577
3173 15:37:03.958346 RX Vref 0 -> 0, step: 1
3174 15:37:03.958422
3175 15:37:03.961551 RX Delay -40 -> 252, step: 8
3176 15:37:03.964967 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3177 15:37:03.968168 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3178 15:37:03.971925 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3179 15:37:03.978113 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3180 15:37:03.981833 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3181 15:37:03.985080 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3182 15:37:03.988283 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3183 15:37:03.991606 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3184 15:37:03.994835 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3185 15:37:04.001992 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3186 15:37:04.005268 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3187 15:37:04.007945 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3188 15:37:04.011632 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3189 15:37:04.018438 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3190 15:37:04.021381 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3191 15:37:04.025243 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3192 15:37:04.025356 ==
3193 15:37:04.028482 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 15:37:04.031735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 15:37:04.031822 ==
3196 15:37:04.035034 DQS Delay:
3197 15:37:04.035148 DQS0 = 0, DQS1 = 0
3198 15:37:04.035244 DQM Delay:
3199 15:37:04.038417 DQM0 = 119, DQM1 = 116
3200 15:37:04.038514 DQ Delay:
3201 15:37:04.041602 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3202 15:37:04.045000 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3203 15:37:04.051919 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3204 15:37:04.054924 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3205 15:37:04.055035
3206 15:37:04.055133
3207 15:37:04.055228 ==
3208 15:37:04.058293 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 15:37:04.061405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 15:37:04.061492 ==
3211 15:37:04.061557
3212 15:37:04.061626
3213 15:37:04.065305 TX Vref Scan disable
3214 15:37:04.065387 == TX Byte 0 ==
3215 15:37:04.072022 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3216 15:37:04.075238 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3217 15:37:04.075357 == TX Byte 1 ==
3218 15:37:04.081577 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3219 15:37:04.084911 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3220 15:37:04.085020 ==
3221 15:37:04.088323 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 15:37:04.091240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 15:37:04.091357 ==
3224 15:37:04.104574 TX Vref=22, minBit 9, minWin=24, winSum=407
3225 15:37:04.107866 TX Vref=24, minBit 9, minWin=24, winSum=417
3226 15:37:04.111183 TX Vref=26, minBit 9, minWin=25, winSum=423
3227 15:37:04.114592 TX Vref=28, minBit 1, minWin=26, winSum=427
3228 15:37:04.117975 TX Vref=30, minBit 10, minWin=25, winSum=428
3229 15:37:04.124425 TX Vref=32, minBit 10, minWin=24, winSum=430
3230 15:37:04.127414 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
3231 15:37:04.127530
3232 15:37:04.130910 Final TX Range 1 Vref 28
3233 15:37:04.130991
3234 15:37:04.131060 ==
3235 15:37:04.134523 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 15:37:04.137869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 15:37:04.137948 ==
3238 15:37:04.138011
3239 15:37:04.141093
3240 15:37:04.141182 TX Vref Scan disable
3241 15:37:04.144386 == TX Byte 0 ==
3242 15:37:04.147709 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3243 15:37:04.151091 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3244 15:37:04.154290 == TX Byte 1 ==
3245 15:37:04.158078 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3246 15:37:04.161256 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3247 15:37:04.161366
3248 15:37:04.164622 [DATLAT]
3249 15:37:04.164729 Freq=1200, CH1 RK0
3250 15:37:04.164831
3251 15:37:04.167825 DATLAT Default: 0xd
3252 15:37:04.167944 0, 0xFFFF, sum = 0
3253 15:37:04.171131 1, 0xFFFF, sum = 0
3254 15:37:04.171242 2, 0xFFFF, sum = 0
3255 15:37:04.174271 3, 0xFFFF, sum = 0
3256 15:37:04.174384 4, 0xFFFF, sum = 0
3257 15:37:04.178141 5, 0xFFFF, sum = 0
3258 15:37:04.178247 6, 0xFFFF, sum = 0
3259 15:37:04.181670 7, 0xFFFF, sum = 0
3260 15:37:04.181790 8, 0xFFFF, sum = 0
3261 15:37:04.184663 9, 0xFFFF, sum = 0
3262 15:37:04.187901 10, 0xFFFF, sum = 0
3263 15:37:04.188024 11, 0xFFFF, sum = 0
3264 15:37:04.191132 12, 0x0, sum = 1
3265 15:37:04.191211 13, 0x0, sum = 2
3266 15:37:04.191282 14, 0x0, sum = 3
3267 15:37:04.194322 15, 0x0, sum = 4
3268 15:37:04.194431 best_step = 13
3269 15:37:04.194525
3270 15:37:04.194619 ==
3271 15:37:04.198212 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 15:37:04.204342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 15:37:04.204448 ==
3274 15:37:04.204544 RX Vref Scan: 1
3275 15:37:04.204633
3276 15:37:04.208197 Set Vref Range= 32 -> 127
3277 15:37:04.208302
3278 15:37:04.211456 RX Vref 32 -> 127, step: 1
3279 15:37:04.211558
3280 15:37:04.214735 RX Delay -5 -> 252, step: 4
3281 15:37:04.214808
3282 15:37:04.218130 Set Vref, RX VrefLevel [Byte0]: 32
3283 15:37:04.218205 [Byte1]: 32
3284 15:37:04.222755
3285 15:37:04.222840 Set Vref, RX VrefLevel [Byte0]: 33
3286 15:37:04.225976 [Byte1]: 33
3287 15:37:04.230605
3288 15:37:04.230691 Set Vref, RX VrefLevel [Byte0]: 34
3289 15:37:04.233863 [Byte1]: 34
3290 15:37:04.238461
3291 15:37:04.238544 Set Vref, RX VrefLevel [Byte0]: 35
3292 15:37:04.241467 [Byte1]: 35
3293 15:37:04.246382
3294 15:37:04.246506 Set Vref, RX VrefLevel [Byte0]: 36
3295 15:37:04.249619 [Byte1]: 36
3296 15:37:04.254345
3297 15:37:04.254448 Set Vref, RX VrefLevel [Byte0]: 37
3298 15:37:04.257432 [Byte1]: 37
3299 15:37:04.261853
3300 15:37:04.261953 Set Vref, RX VrefLevel [Byte0]: 38
3301 15:37:04.265029 [Byte1]: 38
3302 15:37:04.269596
3303 15:37:04.269673 Set Vref, RX VrefLevel [Byte0]: 39
3304 15:37:04.272857 [Byte1]: 39
3305 15:37:04.277415
3306 15:37:04.277519 Set Vref, RX VrefLevel [Byte0]: 40
3307 15:37:04.281056 [Byte1]: 40
3308 15:37:04.285530
3309 15:37:04.285611 Set Vref, RX VrefLevel [Byte0]: 41
3310 15:37:04.288844 [Byte1]: 41
3311 15:37:04.293386
3312 15:37:04.293491 Set Vref, RX VrefLevel [Byte0]: 42
3313 15:37:04.296723 [Byte1]: 42
3314 15:37:04.300815
3315 15:37:04.304144 Set Vref, RX VrefLevel [Byte0]: 43
3316 15:37:04.304221 [Byte1]: 43
3317 15:37:04.308683
3318 15:37:04.308760 Set Vref, RX VrefLevel [Byte0]: 44
3319 15:37:04.311870 [Byte1]: 44
3320 15:37:04.316936
3321 15:37:04.317013 Set Vref, RX VrefLevel [Byte0]: 45
3322 15:37:04.319992 [Byte1]: 45
3323 15:37:04.324832
3324 15:37:04.324943 Set Vref, RX VrefLevel [Byte0]: 46
3325 15:37:04.328170 [Byte1]: 46
3326 15:37:04.332661
3327 15:37:04.332743 Set Vref, RX VrefLevel [Byte0]: 47
3328 15:37:04.335885 [Byte1]: 47
3329 15:37:04.340417
3330 15:37:04.340505 Set Vref, RX VrefLevel [Byte0]: 48
3331 15:37:04.343506 [Byte1]: 48
3332 15:37:04.347863
3333 15:37:04.347955 Set Vref, RX VrefLevel [Byte0]: 49
3334 15:37:04.351326 [Byte1]: 49
3335 15:37:04.355955
3336 15:37:04.356061 Set Vref, RX VrefLevel [Byte0]: 50
3337 15:37:04.359099 [Byte1]: 50
3338 15:37:04.363608
3339 15:37:04.363718 Set Vref, RX VrefLevel [Byte0]: 51
3340 15:37:04.367287 [Byte1]: 51
3341 15:37:04.371921
3342 15:37:04.372001 Set Vref, RX VrefLevel [Byte0]: 52
3343 15:37:04.375168 [Byte1]: 52
3344 15:37:04.379640
3345 15:37:04.379717 Set Vref, RX VrefLevel [Byte0]: 53
3346 15:37:04.382710 [Byte1]: 53
3347 15:37:04.387757
3348 15:37:04.387879 Set Vref, RX VrefLevel [Byte0]: 54
3349 15:37:04.390887 [Byte1]: 54
3350 15:37:04.395418
3351 15:37:04.395529 Set Vref, RX VrefLevel [Byte0]: 55
3352 15:37:04.398728 [Byte1]: 55
3353 15:37:04.402880
3354 15:37:04.402988 Set Vref, RX VrefLevel [Byte0]: 56
3355 15:37:04.406107 [Byte1]: 56
3356 15:37:04.410682
3357 15:37:04.410791 Set Vref, RX VrefLevel [Byte0]: 57
3358 15:37:04.413980 [Byte1]: 57
3359 15:37:04.418496
3360 15:37:04.418604 Set Vref, RX VrefLevel [Byte0]: 58
3361 15:37:04.422362 [Byte1]: 58
3362 15:37:04.426700
3363 15:37:04.426837 Set Vref, RX VrefLevel [Byte0]: 59
3364 15:37:04.429928 [Byte1]: 59
3365 15:37:04.434639
3366 15:37:04.434739 Set Vref, RX VrefLevel [Byte0]: 60
3367 15:37:04.437891 [Byte1]: 60
3368 15:37:04.442069
3369 15:37:04.442144 Set Vref, RX VrefLevel [Byte0]: 61
3370 15:37:04.445295 [Byte1]: 61
3371 15:37:04.449915
3372 15:37:04.450027 Set Vref, RX VrefLevel [Byte0]: 62
3373 15:37:04.453657 [Byte1]: 62
3374 15:37:04.458263
3375 15:37:04.458372 Set Vref, RX VrefLevel [Byte0]: 63
3376 15:37:04.461344 [Byte1]: 63
3377 15:37:04.465638
3378 15:37:04.465743 Set Vref, RX VrefLevel [Byte0]: 64
3379 15:37:04.468894 [Byte1]: 64
3380 15:37:04.473886
3381 15:37:04.473996 Set Vref, RX VrefLevel [Byte0]: 65
3382 15:37:04.477171 [Byte1]: 65
3383 15:37:04.481843
3384 15:37:04.481953 Set Vref, RX VrefLevel [Byte0]: 66
3385 15:37:04.485220 [Byte1]: 66
3386 15:37:04.489738
3387 15:37:04.489816 Set Vref, RX VrefLevel [Byte0]: 67
3388 15:37:04.492872 [Byte1]: 67
3389 15:37:04.497342
3390 15:37:04.497451 Set Vref, RX VrefLevel [Byte0]: 68
3391 15:37:04.500538 [Byte1]: 68
3392 15:37:04.505031
3393 15:37:04.505146 Set Vref, RX VrefLevel [Byte0]: 69
3394 15:37:04.508306 [Byte1]: 69
3395 15:37:04.512971
3396 15:37:04.513082 Final RX Vref Byte 0 = 53 to rank0
3397 15:37:04.516169 Final RX Vref Byte 1 = 53 to rank0
3398 15:37:04.519442 Final RX Vref Byte 0 = 53 to rank1
3399 15:37:04.522845 Final RX Vref Byte 1 = 53 to rank1==
3400 15:37:04.526135 Dram Type= 6, Freq= 0, CH_1, rank 0
3401 15:37:04.533371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 15:37:04.533477 ==
3403 15:37:04.533612 DQS Delay:
3404 15:37:04.533701 DQS0 = 0, DQS1 = 0
3405 15:37:04.536619 DQM Delay:
3406 15:37:04.536730 DQM0 = 120, DQM1 = 117
3407 15:37:04.539787 DQ Delay:
3408 15:37:04.543411 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3409 15:37:04.546452 DQ4 =118, DQ5 =130, DQ6 =128, DQ7 =120
3410 15:37:04.549547 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3411 15:37:04.553190 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3412 15:37:04.553298
3413 15:37:04.553404
3414 15:37:04.559743 [DQSOSCAuto] RK0, (LSB)MR18= 0x113, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3415 15:37:04.562955 CH1 RK0: MR19=404, MR18=113
3416 15:37:04.569706 CH1_RK0: MR19=0x404, MR18=0x113, DQSOSC=402, MR23=63, INC=40, DEC=27
3417 15:37:04.569845
3418 15:37:04.573382 ----->DramcWriteLeveling(PI) begin...
3419 15:37:04.573497 ==
3420 15:37:04.576503 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 15:37:04.579604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 15:37:04.579707 ==
3423 15:37:04.582858 Write leveling (Byte 0): 25 => 25
3424 15:37:04.586872 Write leveling (Byte 1): 29 => 29
3425 15:37:04.590139 DramcWriteLeveling(PI) end<-----
3426 15:37:04.590238
3427 15:37:04.590344 ==
3428 15:37:04.593365 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 15:37:04.596534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 15:37:04.599769 ==
3431 15:37:04.599848 [Gating] SW mode calibration
3432 15:37:04.610086 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3433 15:37:04.612981 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3434 15:37:04.616764 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 15:37:04.623447 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 15:37:04.626684 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 15:37:04.629901 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 15:37:04.637054 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 15:37:04.640167 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 15:37:04.643442 0 15 24 | B1->B0 | 2929 3434 | 0 0 | (1 0) (0 1)
3441 15:37:04.649932 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3442 15:37:04.653681 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 15:37:04.657001 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 15:37:04.660494 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 15:37:04.666762 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 15:37:04.670361 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 15:37:04.673377 1 0 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3448 15:37:04.680589 1 0 24 | B1->B0 | 3f3f 2323 | 0 0 | (0 0) (0 0)
3449 15:37:04.683505 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 15:37:04.687120 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 15:37:04.693521 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 15:37:04.696666 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 15:37:04.700373 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 15:37:04.706860 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 15:37:04.710072 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3456 15:37:04.713766 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3457 15:37:04.720107 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3458 15:37:04.723863 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 15:37:04.727116 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 15:37:04.733560 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 15:37:04.736845 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 15:37:04.740084 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 15:37:04.743744 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 15:37:04.750400 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 15:37:04.753578 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 15:37:04.756546 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 15:37:04.763725 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 15:37:04.766941 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 15:37:04.770110 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 15:37:04.776771 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 15:37:04.780231 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3472 15:37:04.783637 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3473 15:37:04.787064 Total UI for P1: 0, mck2ui 16
3474 15:37:04.790425 best dqsien dly found for B1: ( 1, 3, 20)
3475 15:37:04.797078 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3476 15:37:04.799941 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 15:37:04.803416 Total UI for P1: 0, mck2ui 16
3478 15:37:04.806547 best dqsien dly found for B0: ( 1, 3, 26)
3479 15:37:04.809872 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3480 15:37:04.813242 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3481 15:37:04.813343
3482 15:37:04.817038 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3483 15:37:04.820218 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3484 15:37:04.823473 [Gating] SW calibration Done
3485 15:37:04.823577 ==
3486 15:37:04.826674 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 15:37:04.830081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 15:37:04.830190 ==
3489 15:37:04.833297 RX Vref Scan: 0
3490 15:37:04.833401
3491 15:37:04.836510 RX Vref 0 -> 0, step: 1
3492 15:37:04.836623
3493 15:37:04.836719 RX Delay -40 -> 252, step: 8
3494 15:37:04.843736 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3495 15:37:04.846954 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3496 15:37:04.850081 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3497 15:37:04.853368 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3498 15:37:04.856656 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3499 15:37:04.863212 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3500 15:37:04.866755 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3501 15:37:04.869831 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3502 15:37:04.873097 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3503 15:37:04.876403 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3504 15:37:04.883605 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3505 15:37:04.886751 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3506 15:37:04.889843 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3507 15:37:04.893537 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3508 15:37:04.896495 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3509 15:37:04.903273 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3510 15:37:04.903382 ==
3511 15:37:04.906583 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 15:37:04.910168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 15:37:04.910272 ==
3514 15:37:04.910373 DQS Delay:
3515 15:37:04.913356 DQS0 = 0, DQS1 = 0
3516 15:37:04.913435 DQM Delay:
3517 15:37:04.916504 DQM0 = 120, DQM1 = 117
3518 15:37:04.916602 DQ Delay:
3519 15:37:04.919921 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3520 15:37:04.923611 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3521 15:37:04.926654 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3522 15:37:04.929914 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3523 15:37:04.930025
3524 15:37:04.933738
3525 15:37:04.933847 ==
3526 15:37:04.936961 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 15:37:04.940012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 15:37:04.940130 ==
3529 15:37:04.940224
3530 15:37:04.940324
3531 15:37:04.943338 TX Vref Scan disable
3532 15:37:04.943439 == TX Byte 0 ==
3533 15:37:04.947092 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3534 15:37:04.953364 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3535 15:37:04.953470 == TX Byte 1 ==
3536 15:37:04.960326 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3537 15:37:04.963470 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3538 15:37:04.963578 ==
3539 15:37:04.966879 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 15:37:04.969936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 15:37:04.970039 ==
3542 15:37:04.982409 TX Vref=22, minBit 0, minWin=26, winSum=422
3543 15:37:04.985591 TX Vref=24, minBit 0, minWin=26, winSum=424
3544 15:37:04.988780 TX Vref=26, minBit 1, minWin=26, winSum=424
3545 15:37:04.992542 TX Vref=28, minBit 2, minWin=26, winSum=431
3546 15:37:04.995725 TX Vref=30, minBit 9, minWin=26, winSum=435
3547 15:37:04.998905 TX Vref=32, minBit 9, minWin=26, winSum=437
3548 15:37:05.005354 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 32
3549 15:37:05.005437
3550 15:37:05.009261 Final TX Range 1 Vref 32
3551 15:37:05.009364
3552 15:37:05.009442 ==
3553 15:37:05.012420 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 15:37:05.015498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 15:37:05.015609 ==
3556 15:37:05.015702
3557 15:37:05.018916
3558 15:37:05.019027 TX Vref Scan disable
3559 15:37:05.022416 == TX Byte 0 ==
3560 15:37:05.025352 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3561 15:37:05.028707 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3562 15:37:05.031974 == TX Byte 1 ==
3563 15:37:05.035596 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3564 15:37:05.038862 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3565 15:37:05.041994
3566 15:37:05.042103 [DATLAT]
3567 15:37:05.042209 Freq=1200, CH1 RK1
3568 15:37:05.042305
3569 15:37:05.045255 DATLAT Default: 0xd
3570 15:37:05.045368 0, 0xFFFF, sum = 0
3571 15:37:05.049072 1, 0xFFFF, sum = 0
3572 15:37:05.049174 2, 0xFFFF, sum = 0
3573 15:37:05.052298 3, 0xFFFF, sum = 0
3574 15:37:05.052400 4, 0xFFFF, sum = 0
3575 15:37:05.055217 5, 0xFFFF, sum = 0
3576 15:37:05.059007 6, 0xFFFF, sum = 0
3577 15:37:05.059086 7, 0xFFFF, sum = 0
3578 15:37:05.062180 8, 0xFFFF, sum = 0
3579 15:37:05.062290 9, 0xFFFF, sum = 0
3580 15:37:05.065501 10, 0xFFFF, sum = 0
3581 15:37:05.065615 11, 0xFFFF, sum = 0
3582 15:37:05.068612 12, 0x0, sum = 1
3583 15:37:05.068720 13, 0x0, sum = 2
3584 15:37:05.071715 14, 0x0, sum = 3
3585 15:37:05.071818 15, 0x0, sum = 4
3586 15:37:05.071914 best_step = 13
3587 15:37:05.072002
3588 15:37:05.075492 ==
3589 15:37:05.078623 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 15:37:05.082254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 15:37:05.082338 ==
3592 15:37:05.082403 RX Vref Scan: 0
3593 15:37:05.082464
3594 15:37:05.085494 RX Vref 0 -> 0, step: 1
3595 15:37:05.085563
3596 15:37:05.088402 RX Delay -5 -> 252, step: 4
3597 15:37:05.092135 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3598 15:37:05.098946 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3599 15:37:05.101863 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3600 15:37:05.105142 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3601 15:37:05.108355 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3602 15:37:05.112102 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3603 15:37:05.118312 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3604 15:37:05.121552 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3605 15:37:05.125285 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3606 15:37:05.128530 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3607 15:37:05.131806 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3608 15:37:05.138531 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3609 15:37:05.141488 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3610 15:37:05.144889 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3611 15:37:05.148203 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3612 15:37:05.151527 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3613 15:37:05.154906 ==
3614 15:37:05.157945 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 15:37:05.161410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 15:37:05.161508 ==
3617 15:37:05.161577 DQS Delay:
3618 15:37:05.165086 DQS0 = 0, DQS1 = 0
3619 15:37:05.165169 DQM Delay:
3620 15:37:05.168310 DQM0 = 120, DQM1 = 118
3621 15:37:05.168395 DQ Delay:
3622 15:37:05.171474 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3623 15:37:05.174598 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3624 15:37:05.178496 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3625 15:37:05.181611 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3626 15:37:05.181696
3627 15:37:05.181765
3628 15:37:05.191676 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3629 15:37:05.194824 CH1 RK1: MR19=403, MR18=12EE
3630 15:37:05.197680 CH1_RK1: MR19=0x403, MR18=0x12EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3631 15:37:05.201322 [RxdqsGatingPostProcess] freq 1200
3632 15:37:05.208089 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3633 15:37:05.211277 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 15:37:05.214426 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 15:37:05.218172 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 15:37:05.221263 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 15:37:05.224422 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 15:37:05.227638 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 15:37:05.231568 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 15:37:05.234723 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 15:37:05.234802 Pre-setting of DQS Precalculation
3642 15:37:05.241257 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3643 15:37:05.247911 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3644 15:37:05.254424 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3645 15:37:05.254514
3646 15:37:05.254584
3647 15:37:05.257961 [Calibration Summary] 2400 Mbps
3648 15:37:05.261147 CH 0, Rank 0
3649 15:37:05.261227 SW Impedance : PASS
3650 15:37:05.264324 DUTY Scan : NO K
3651 15:37:05.268043 ZQ Calibration : PASS
3652 15:37:05.268125 Jitter Meter : NO K
3653 15:37:05.271048 CBT Training : PASS
3654 15:37:05.274564 Write leveling : PASS
3655 15:37:05.274643 RX DQS gating : PASS
3656 15:37:05.277829 RX DQ/DQS(RDDQC) : PASS
3657 15:37:05.277918 TX DQ/DQS : PASS
3658 15:37:05.281108 RX DATLAT : PASS
3659 15:37:05.284270 RX DQ/DQS(Engine): PASS
3660 15:37:05.284355 TX OE : NO K
3661 15:37:05.288295 All Pass.
3662 15:37:05.288382
3663 15:37:05.288464 CH 0, Rank 1
3664 15:37:05.291517 SW Impedance : PASS
3665 15:37:05.291605 DUTY Scan : NO K
3666 15:37:05.294525 ZQ Calibration : PASS
3667 15:37:05.297624 Jitter Meter : NO K
3668 15:37:05.297703 CBT Training : PASS
3669 15:37:05.300830 Write leveling : PASS
3670 15:37:05.304611 RX DQS gating : PASS
3671 15:37:05.304695 RX DQ/DQS(RDDQC) : PASS
3672 15:37:05.307627 TX DQ/DQS : PASS
3673 15:37:05.311191 RX DATLAT : PASS
3674 15:37:05.311266 RX DQ/DQS(Engine): PASS
3675 15:37:05.314173 TX OE : NO K
3676 15:37:05.314257 All Pass.
3677 15:37:05.314329
3678 15:37:05.317838 CH 1, Rank 0
3679 15:37:05.317949 SW Impedance : PASS
3680 15:37:05.321009 DUTY Scan : NO K
3681 15:37:05.324664 ZQ Calibration : PASS
3682 15:37:05.324744 Jitter Meter : NO K
3683 15:37:05.327785 CBT Training : PASS
3684 15:37:05.327867 Write leveling : PASS
3685 15:37:05.330983 RX DQS gating : PASS
3686 15:37:05.334264 RX DQ/DQS(RDDQC) : PASS
3687 15:37:05.334349 TX DQ/DQS : PASS
3688 15:37:05.337373 RX DATLAT : PASS
3689 15:37:05.341050 RX DQ/DQS(Engine): PASS
3690 15:37:05.341129 TX OE : NO K
3691 15:37:05.344332 All Pass.
3692 15:37:05.344409
3693 15:37:05.344478 CH 1, Rank 1
3694 15:37:05.347484 SW Impedance : PASS
3695 15:37:05.347601 DUTY Scan : NO K
3696 15:37:05.350917 ZQ Calibration : PASS
3697 15:37:05.353870 Jitter Meter : NO K
3698 15:37:05.353956 CBT Training : PASS
3699 15:37:05.357529 Write leveling : PASS
3700 15:37:05.360520 RX DQS gating : PASS
3701 15:37:05.360604 RX DQ/DQS(RDDQC) : PASS
3702 15:37:05.364203 TX DQ/DQS : PASS
3703 15:37:05.367167 RX DATLAT : PASS
3704 15:37:05.367253 RX DQ/DQS(Engine): PASS
3705 15:37:05.370343 TX OE : NO K
3706 15:37:05.370425 All Pass.
3707 15:37:05.370493
3708 15:37:05.374188 DramC Write-DBI off
3709 15:37:05.377332 PER_BANK_REFRESH: Hybrid Mode
3710 15:37:05.377414 TX_TRACKING: ON
3711 15:37:05.387458 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3712 15:37:05.390534 [FAST_K] Save calibration result to emmc
3713 15:37:05.393978 dramc_set_vcore_voltage set vcore to 650000
3714 15:37:05.397359 Read voltage for 600, 5
3715 15:37:05.397442 Vio18 = 0
3716 15:37:05.397514 Vcore = 650000
3717 15:37:05.400501 Vdram = 0
3718 15:37:05.400589 Vddq = 0
3719 15:37:05.400657 Vmddr = 0
3720 15:37:05.407470 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3721 15:37:05.410664 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3722 15:37:05.413882 MEM_TYPE=3, freq_sel=19
3723 15:37:05.416906 sv_algorithm_assistance_LP4_1600
3724 15:37:05.420450 ============ PULL DRAM RESETB DOWN ============
3725 15:37:05.423494 ========== PULL DRAM RESETB DOWN end =========
3726 15:37:05.430663 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 15:37:05.433964 ===================================
3728 15:37:05.434083 LPDDR4 DRAM CONFIGURATION
3729 15:37:05.436911 ===================================
3730 15:37:05.440592 EX_ROW_EN[0] = 0x0
3731 15:37:05.443862 EX_ROW_EN[1] = 0x0
3732 15:37:05.443944 LP4Y_EN = 0x0
3733 15:37:05.447137 WORK_FSP = 0x0
3734 15:37:05.447218 WL = 0x2
3735 15:37:05.450396 RL = 0x2
3736 15:37:05.450477 BL = 0x2
3737 15:37:05.453573 RPST = 0x0
3738 15:37:05.453654 RD_PRE = 0x0
3739 15:37:05.456950 WR_PRE = 0x1
3740 15:37:05.457045 WR_PST = 0x0
3741 15:37:05.460136 DBI_WR = 0x0
3742 15:37:05.460217 DBI_RD = 0x0
3743 15:37:05.463246 OTF = 0x1
3744 15:37:05.466886 ===================================
3745 15:37:05.469930 ===================================
3746 15:37:05.470013 ANA top config
3747 15:37:05.473589 ===================================
3748 15:37:05.477019 DLL_ASYNC_EN = 0
3749 15:37:05.480307 ALL_SLAVE_EN = 1
3750 15:37:05.483408 NEW_RANK_MODE = 1
3751 15:37:05.483490 DLL_IDLE_MODE = 1
3752 15:37:05.486715 LP45_APHY_COMB_EN = 1
3753 15:37:05.489864 TX_ODT_DIS = 1
3754 15:37:05.493479 NEW_8X_MODE = 1
3755 15:37:05.496596 ===================================
3756 15:37:05.500202 ===================================
3757 15:37:05.503303 data_rate = 1200
3758 15:37:05.503383 CKR = 1
3759 15:37:05.506883 DQ_P2S_RATIO = 8
3760 15:37:05.509704 ===================================
3761 15:37:05.513132 CA_P2S_RATIO = 8
3762 15:37:05.516346 DQ_CA_OPEN = 0
3763 15:37:05.519970 DQ_SEMI_OPEN = 0
3764 15:37:05.523102 CA_SEMI_OPEN = 0
3765 15:37:05.523197 CA_FULL_RATE = 0
3766 15:37:05.526748 DQ_CKDIV4_EN = 1
3767 15:37:05.529711 CA_CKDIV4_EN = 1
3768 15:37:05.533291 CA_PREDIV_EN = 0
3769 15:37:05.536342 PH8_DLY = 0
3770 15:37:05.539639 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3771 15:37:05.539729 DQ_AAMCK_DIV = 4
3772 15:37:05.543057 CA_AAMCK_DIV = 4
3773 15:37:05.546244 CA_ADMCK_DIV = 4
3774 15:37:05.549511 DQ_TRACK_CA_EN = 0
3775 15:37:05.553239 CA_PICK = 600
3776 15:37:05.556590 CA_MCKIO = 600
3777 15:37:05.559865 MCKIO_SEMI = 0
3778 15:37:05.559951 PLL_FREQ = 2288
3779 15:37:05.563051 DQ_UI_PI_RATIO = 32
3780 15:37:05.566281 CA_UI_PI_RATIO = 0
3781 15:37:05.570026 ===================================
3782 15:37:05.573100 ===================================
3783 15:37:05.576570 memory_type:LPDDR4
3784 15:37:05.576648 GP_NUM : 10
3785 15:37:05.579623 SRAM_EN : 1
3786 15:37:05.583468 MD32_EN : 0
3787 15:37:05.586630 ===================================
3788 15:37:05.586733 [ANA_INIT] >>>>>>>>>>>>>>
3789 15:37:05.589962 <<<<<< [CONFIGURE PHASE]: ANA_TX
3790 15:37:05.593171 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3791 15:37:05.596328 ===================================
3792 15:37:05.599400 data_rate = 1200,PCW = 0X5800
3793 15:37:05.603208 ===================================
3794 15:37:05.606478 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3795 15:37:05.612778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 15:37:05.616085 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 15:37:05.622751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3798 15:37:05.626452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3799 15:37:05.629347 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3800 15:37:05.629439 [ANA_INIT] flow start
3801 15:37:05.632716 [ANA_INIT] PLL >>>>>>>>
3802 15:37:05.636137 [ANA_INIT] PLL <<<<<<<<
3803 15:37:05.639480 [ANA_INIT] MIDPI >>>>>>>>
3804 15:37:05.639560 [ANA_INIT] MIDPI <<<<<<<<
3805 15:37:05.642860 [ANA_INIT] DLL >>>>>>>>
3806 15:37:05.642945 [ANA_INIT] flow end
3807 15:37:05.649661 ============ LP4 DIFF to SE enter ============
3808 15:37:05.653155 ============ LP4 DIFF to SE exit ============
3809 15:37:05.656515 [ANA_INIT] <<<<<<<<<<<<<
3810 15:37:05.659720 [Flow] Enable top DCM control >>>>>
3811 15:37:05.663110 [Flow] Enable top DCM control <<<<<
3812 15:37:05.663196 Enable DLL master slave shuffle
3813 15:37:05.669567 ==============================================================
3814 15:37:05.672669 Gating Mode config
3815 15:37:05.676458 ==============================================================
3816 15:37:05.679538 Config description:
3817 15:37:05.689396 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3818 15:37:05.696005 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3819 15:37:05.699263 SELPH_MODE 0: By rank 1: By Phase
3820 15:37:05.706138 ==============================================================
3821 15:37:05.709244 GAT_TRACK_EN = 1
3822 15:37:05.713190 RX_GATING_MODE = 2
3823 15:37:05.716301 RX_GATING_TRACK_MODE = 2
3824 15:37:05.719438 SELPH_MODE = 1
3825 15:37:05.719550 PICG_EARLY_EN = 1
3826 15:37:05.722691 VALID_LAT_VALUE = 1
3827 15:37:05.729540 ==============================================================
3828 15:37:05.732743 Enter into Gating configuration >>>>
3829 15:37:05.736072 Exit from Gating configuration <<<<
3830 15:37:05.739088 Enter into DVFS_PRE_config >>>>>
3831 15:37:05.749354 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3832 15:37:05.752595 Exit from DVFS_PRE_config <<<<<
3833 15:37:05.756254 Enter into PICG configuration >>>>
3834 15:37:05.759299 Exit from PICG configuration <<<<
3835 15:37:05.762754 [RX_INPUT] configuration >>>>>
3836 15:37:05.765614 [RX_INPUT] configuration <<<<<
3837 15:37:05.769462 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3838 15:37:05.775884 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3839 15:37:05.782476 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3840 15:37:05.789709 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3841 15:37:05.796138 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 15:37:05.799171 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 15:37:05.806245 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3844 15:37:05.809238 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3845 15:37:05.812632 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3846 15:37:05.816083 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3847 15:37:05.819176 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3848 15:37:05.826332 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3849 15:37:05.829534 ===================================
3850 15:37:05.829623 LPDDR4 DRAM CONFIGURATION
3851 15:37:05.832819 ===================================
3852 15:37:05.835994 EX_ROW_EN[0] = 0x0
3853 15:37:05.839996 EX_ROW_EN[1] = 0x0
3854 15:37:05.840080 LP4Y_EN = 0x0
3855 15:37:05.843184 WORK_FSP = 0x0
3856 15:37:05.843265 WL = 0x2
3857 15:37:05.846250 RL = 0x2
3858 15:37:05.846330 BL = 0x2
3859 15:37:05.849432 RPST = 0x0
3860 15:37:05.849514 RD_PRE = 0x0
3861 15:37:05.853210 WR_PRE = 0x1
3862 15:37:05.853299 WR_PST = 0x0
3863 15:37:05.856324 DBI_WR = 0x0
3864 15:37:05.856407 DBI_RD = 0x0
3865 15:37:05.859537 OTF = 0x1
3866 15:37:05.862664 ===================================
3867 15:37:05.865877 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3868 15:37:05.869717 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3869 15:37:05.875854 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 15:37:05.879415 ===================================
3871 15:37:05.879493 LPDDR4 DRAM CONFIGURATION
3872 15:37:05.882931 ===================================
3873 15:37:05.885932 EX_ROW_EN[0] = 0x10
3874 15:37:05.889230 EX_ROW_EN[1] = 0x0
3875 15:37:05.889307 LP4Y_EN = 0x0
3876 15:37:05.892481 WORK_FSP = 0x0
3877 15:37:05.892558 WL = 0x2
3878 15:37:05.895728 RL = 0x2
3879 15:37:05.895806 BL = 0x2
3880 15:37:05.899037 RPST = 0x0
3881 15:37:05.899118 RD_PRE = 0x0
3882 15:37:05.902847 WR_PRE = 0x1
3883 15:37:05.902922 WR_PST = 0x0
3884 15:37:05.905969 DBI_WR = 0x0
3885 15:37:05.906046 DBI_RD = 0x0
3886 15:37:05.909191 OTF = 0x1
3887 15:37:05.912650 ===================================
3888 15:37:05.919510 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3889 15:37:05.922895 nWR fixed to 30
3890 15:37:05.922983 [ModeRegInit_LP4] CH0 RK0
3891 15:37:05.925964 [ModeRegInit_LP4] CH0 RK1
3892 15:37:05.929232 [ModeRegInit_LP4] CH1 RK0
3893 15:37:05.929307 [ModeRegInit_LP4] CH1 RK1
3894 15:37:05.933026 match AC timing 17
3895 15:37:05.936104 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3896 15:37:05.942455 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3897 15:37:05.945690 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3898 15:37:05.949310 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3899 15:37:05.955667 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3900 15:37:05.955779 ==
3901 15:37:05.959458 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 15:37:05.962757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3903 15:37:05.962857 ==
3904 15:37:05.968976 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3905 15:37:05.975898 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3906 15:37:05.978993 [CA 0] Center 35 (5~66) winsize 62
3907 15:37:05.982295 [CA 1] Center 35 (5~66) winsize 62
3908 15:37:05.985459 [CA 2] Center 34 (3~65) winsize 63
3909 15:37:05.988634 [CA 3] Center 33 (3~64) winsize 62
3910 15:37:05.992569 [CA 4] Center 33 (2~64) winsize 63
3911 15:37:05.995606 [CA 5] Center 32 (2~63) winsize 62
3912 15:37:05.995679
3913 15:37:05.998983 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3914 15:37:05.999058
3915 15:37:06.002539 [CATrainingPosCal] consider 1 rank data
3916 15:37:06.005771 u2DelayCellTimex100 = 270/100 ps
3917 15:37:06.009212 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3918 15:37:06.012246 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3919 15:37:06.015677 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3920 15:37:06.018906 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3921 15:37:06.022480 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3922 15:37:06.025685 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3923 15:37:06.025777
3924 15:37:06.029092 CA PerBit enable=1, Macro0, CA PI delay=32
3925 15:37:06.032288
3926 15:37:06.032383 [CBTSetCACLKResult] CA Dly = 32
3927 15:37:06.035957 CS Dly: 4 (0~35)
3928 15:37:06.036037 ==
3929 15:37:06.039140 Dram Type= 6, Freq= 0, CH_0, rank 1
3930 15:37:06.042236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 15:37:06.042312 ==
3932 15:37:06.048661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 15:37:06.055525 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3934 15:37:06.058800 [CA 0] Center 35 (5~66) winsize 62
3935 15:37:06.061974 [CA 1] Center 35 (5~66) winsize 62
3936 15:37:06.065254 [CA 2] Center 34 (3~65) winsize 63
3937 15:37:06.068529 [CA 3] Center 33 (2~64) winsize 63
3938 15:37:06.071947 [CA 4] Center 33 (2~64) winsize 63
3939 15:37:06.075184 [CA 5] Center 32 (2~63) winsize 62
3940 15:37:06.075291
3941 15:37:06.078945 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3942 15:37:06.079055
3943 15:37:06.082193 [CATrainingPosCal] consider 2 rank data
3944 15:37:06.085577 u2DelayCellTimex100 = 270/100 ps
3945 15:37:06.088746 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3946 15:37:06.091969 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3947 15:37:06.095295 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3948 15:37:06.098529 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3949 15:37:06.101654 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3950 15:37:06.105603 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3951 15:37:06.108811
3952 15:37:06.111956 CA PerBit enable=1, Macro0, CA PI delay=32
3953 15:37:06.112032
3954 15:37:06.115244 [CBTSetCACLKResult] CA Dly = 32
3955 15:37:06.115319 CS Dly: 4 (0~36)
3956 15:37:06.115382
3957 15:37:06.118334 ----->DramcWriteLeveling(PI) begin...
3958 15:37:06.118451 ==
3959 15:37:06.122090 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 15:37:06.125310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 15:37:06.128378 ==
3962 15:37:06.128459 Write leveling (Byte 0): 34 => 34
3963 15:37:06.131865 Write leveling (Byte 1): 30 => 30
3964 15:37:06.135352 DramcWriteLeveling(PI) end<-----
3965 15:37:06.135433
3966 15:37:06.135499 ==
3967 15:37:06.138240 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 15:37:06.145138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 15:37:06.145221 ==
3970 15:37:06.145285 [Gating] SW mode calibration
3971 15:37:06.155145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3972 15:37:06.158330 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3973 15:37:06.161430 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 15:37:06.168043 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 15:37:06.171874 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3976 15:37:06.174992 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
3977 15:37:06.181631 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
3978 15:37:06.185128 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 15:37:06.188383 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 15:37:06.194767 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 15:37:06.197938 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 15:37:06.201655 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 15:37:06.207978 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 15:37:06.211716 0 10 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
3985 15:37:06.214905 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
3986 15:37:06.221917 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 15:37:06.225018 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 15:37:06.228290 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 15:37:06.234707 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 15:37:06.237966 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 15:37:06.241692 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 15:37:06.247819 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3993 15:37:06.251496 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3994 15:37:06.254515 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 15:37:06.261131 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 15:37:06.264611 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 15:37:06.267994 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 15:37:06.275003 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 15:37:06.278309 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 15:37:06.281480 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 15:37:06.287737 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 15:37:06.291315 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 15:37:06.294370 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 15:37:06.298103 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 15:37:06.304586 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 15:37:06.307467 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 15:37:06.311188 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 15:37:06.317534 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 15:37:06.321389 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 15:37:06.324555 Total UI for P1: 0, mck2ui 16
4011 15:37:06.327660 best dqsien dly found for B0: ( 0, 13, 14)
4012 15:37:06.331339 Total UI for P1: 0, mck2ui 16
4013 15:37:06.334652 best dqsien dly found for B1: ( 0, 13, 14)
4014 15:37:06.337972 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4015 15:37:06.341173 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4016 15:37:06.341252
4017 15:37:06.344886 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4018 15:37:06.347887 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4019 15:37:06.350993 [Gating] SW calibration Done
4020 15:37:06.351072 ==
4021 15:37:06.354813 Dram Type= 6, Freq= 0, CH_0, rank 0
4022 15:37:06.361188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 15:37:06.361277 ==
4024 15:37:06.361341 RX Vref Scan: 0
4025 15:37:06.361400
4026 15:37:06.364250 RX Vref 0 -> 0, step: 1
4027 15:37:06.364336
4028 15:37:06.367617 RX Delay -230 -> 252, step: 16
4029 15:37:06.371310 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4030 15:37:06.374369 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4031 15:37:06.377379 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4032 15:37:06.384134 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4033 15:37:06.387606 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4034 15:37:06.391327 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4035 15:37:06.394576 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4036 15:37:06.397709 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4037 15:37:06.404370 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4038 15:37:06.407995 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4039 15:37:06.411076 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4040 15:37:06.414135 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4041 15:37:06.421167 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4042 15:37:06.424409 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4043 15:37:06.427744 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4044 15:37:06.431228 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4045 15:37:06.431306 ==
4046 15:37:06.434368 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 15:37:06.440733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 15:37:06.440816 ==
4049 15:37:06.440880 DQS Delay:
4050 15:37:06.444667 DQS0 = 0, DQS1 = 0
4051 15:37:06.444748 DQM Delay:
4052 15:37:06.444827 DQM0 = 53, DQM1 = 47
4053 15:37:06.448026 DQ Delay:
4054 15:37:06.451072 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4055 15:37:06.454134 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4056 15:37:06.457703 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4057 15:37:06.460858 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =57
4058 15:37:06.460940
4059 15:37:06.461003
4060 15:37:06.461061 ==
4061 15:37:06.463937 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 15:37:06.467820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 15:37:06.467902 ==
4064 15:37:06.467983
4065 15:37:06.468046
4066 15:37:06.471059 TX Vref Scan disable
4067 15:37:06.471135 == TX Byte 0 ==
4068 15:37:06.477493 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4069 15:37:06.480724 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4070 15:37:06.480835 == TX Byte 1 ==
4071 15:37:06.487741 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4072 15:37:06.490603 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4073 15:37:06.490685 ==
4074 15:37:06.494129 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 15:37:06.497609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 15:37:06.497710 ==
4077 15:37:06.497776
4078 15:37:06.500733
4079 15:37:06.500814 TX Vref Scan disable
4080 15:37:06.504403 == TX Byte 0 ==
4081 15:37:06.507957 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4082 15:37:06.510822 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4083 15:37:06.514344 == TX Byte 1 ==
4084 15:37:06.517393 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4085 15:37:06.520975 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4086 15:37:06.524412
4087 15:37:06.524525 [DATLAT]
4088 15:37:06.524628 Freq=600, CH0 RK0
4089 15:37:06.524719
4090 15:37:06.527536 DATLAT Default: 0x9
4091 15:37:06.527662 0, 0xFFFF, sum = 0
4092 15:37:06.530833 1, 0xFFFF, sum = 0
4093 15:37:06.530945 2, 0xFFFF, sum = 0
4094 15:37:06.533967 3, 0xFFFF, sum = 0
4095 15:37:06.534082 4, 0xFFFF, sum = 0
4096 15:37:06.537188 5, 0xFFFF, sum = 0
4097 15:37:06.540992 6, 0xFFFF, sum = 0
4098 15:37:06.541099 7, 0xFFFF, sum = 0
4099 15:37:06.541202 8, 0x0, sum = 1
4100 15:37:06.544169 9, 0x0, sum = 2
4101 15:37:06.544292 10, 0x0, sum = 3
4102 15:37:06.547398 11, 0x0, sum = 4
4103 15:37:06.547515 best_step = 9
4104 15:37:06.547618
4105 15:37:06.547693 ==
4106 15:37:06.550739 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 15:37:06.557130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 15:37:06.557241 ==
4109 15:37:06.557356 RX Vref Scan: 1
4110 15:37:06.557447
4111 15:37:06.560881 RX Vref 0 -> 0, step: 1
4112 15:37:06.560960
4113 15:37:06.563856 RX Delay -163 -> 252, step: 8
4114 15:37:06.563952
4115 15:37:06.567495 Set Vref, RX VrefLevel [Byte0]: 55
4116 15:37:06.570557 [Byte1]: 46
4117 15:37:06.570646
4118 15:37:06.573807 Final RX Vref Byte 0 = 55 to rank0
4119 15:37:06.577026 Final RX Vref Byte 1 = 46 to rank0
4120 15:37:06.580668 Final RX Vref Byte 0 = 55 to rank1
4121 15:37:06.583841 Final RX Vref Byte 1 = 46 to rank1==
4122 15:37:06.587109 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 15:37:06.590946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 15:37:06.591030 ==
4125 15:37:06.594185 DQS Delay:
4126 15:37:06.594270 DQS0 = 0, DQS1 = 0
4127 15:37:06.594336 DQM Delay:
4128 15:37:06.597385 DQM0 = 53, DQM1 = 45
4129 15:37:06.597471 DQ Delay:
4130 15:37:06.600340 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4131 15:37:06.603936 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4132 15:37:06.607336 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4133 15:37:06.610826 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4134 15:37:06.610948
4135 15:37:06.611029
4136 15:37:06.620204 [DQSOSCAuto] RK0, (LSB)MR18= 0x7468, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4137 15:37:06.624066 CH0 RK0: MR19=808, MR18=7468
4138 15:37:06.627165 CH0_RK0: MR19=0x808, MR18=0x7468, DQSOSC=388, MR23=63, INC=174, DEC=116
4139 15:37:06.627246
4140 15:37:06.630673 ----->DramcWriteLeveling(PI) begin...
4141 15:37:06.634048 ==
4142 15:37:06.637100 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 15:37:06.640658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 15:37:06.640741 ==
4145 15:37:06.643738 Write leveling (Byte 0): 35 => 35
4146 15:37:06.647026 Write leveling (Byte 1): 32 => 32
4147 15:37:06.650185 DramcWriteLeveling(PI) end<-----
4148 15:37:06.650283
4149 15:37:06.650387 ==
4150 15:37:06.653440 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 15:37:06.656882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 15:37:06.656969 ==
4153 15:37:06.660063 [Gating] SW mode calibration
4154 15:37:06.666819 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4155 15:37:06.673711 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4156 15:37:06.677022 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 15:37:06.680035 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 15:37:06.683956 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 15:37:06.690407 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
4160 15:37:06.693575 0 9 16 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
4161 15:37:06.696828 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 15:37:06.703303 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 15:37:06.707094 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 15:37:06.710240 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 15:37:06.716646 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 15:37:06.719930 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 15:37:06.723176 0 10 12 | B1->B0 | 2727 2e2e | 0 0 | (1 1) (0 0)
4168 15:37:06.729834 0 10 16 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
4169 15:37:06.733586 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 15:37:06.736688 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 15:37:06.743326 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 15:37:06.746938 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 15:37:06.749937 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 15:37:06.756426 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 15:37:06.760190 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4176 15:37:06.763389 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 15:37:06.769856 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 15:37:06.772982 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 15:37:06.776223 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 15:37:06.783006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 15:37:06.786566 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 15:37:06.789598 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 15:37:06.796507 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 15:37:06.799672 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 15:37:06.802870 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 15:37:06.809956 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 15:37:06.813267 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 15:37:06.816404 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 15:37:06.820173 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 15:37:06.826482 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 15:37:06.830142 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 15:37:06.833017 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 15:37:06.836519 Total UI for P1: 0, mck2ui 16
4194 15:37:06.839932 best dqsien dly found for B0: ( 0, 13, 14)
4195 15:37:06.843406 Total UI for P1: 0, mck2ui 16
4196 15:37:06.846696 best dqsien dly found for B1: ( 0, 13, 14)
4197 15:37:06.849722 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4198 15:37:06.853151 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4199 15:37:06.853263
4200 15:37:06.860095 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4201 15:37:06.863123 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4202 15:37:06.866742 [Gating] SW calibration Done
4203 15:37:06.866825 ==
4204 15:37:06.870180 Dram Type= 6, Freq= 0, CH_0, rank 1
4205 15:37:06.873323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 15:37:06.873432 ==
4207 15:37:06.873529 RX Vref Scan: 0
4208 15:37:06.873628
4209 15:37:06.876469 RX Vref 0 -> 0, step: 1
4210 15:37:06.876555
4211 15:37:06.879657 RX Delay -230 -> 252, step: 16
4212 15:37:06.883400 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4213 15:37:06.886664 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4214 15:37:06.893342 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4215 15:37:06.896343 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4216 15:37:06.900086 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4217 15:37:06.903288 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4218 15:37:06.909733 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4219 15:37:06.913047 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4220 15:37:06.916180 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4221 15:37:06.919452 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4222 15:37:06.923197 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4223 15:37:06.929671 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4224 15:37:06.932989 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4225 15:37:06.936074 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4226 15:37:06.939746 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4227 15:37:06.946414 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4228 15:37:06.946523 ==
4229 15:37:06.949460 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 15:37:06.952878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 15:37:06.952961 ==
4232 15:37:06.953028 DQS Delay:
4233 15:37:06.955829 DQS0 = 0, DQS1 = 0
4234 15:37:06.955910 DQM Delay:
4235 15:37:06.959373 DQM0 = 50, DQM1 = 43
4236 15:37:06.959483 DQ Delay:
4237 15:37:06.963030 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4238 15:37:06.966313 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4239 15:37:06.969290 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4240 15:37:06.973229 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4241 15:37:06.973337
4242 15:37:06.973430
4243 15:37:06.973522 ==
4244 15:37:06.976277 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 15:37:06.979233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 15:37:06.982905 ==
4247 15:37:06.982981
4248 15:37:06.983048
4249 15:37:06.983115 TX Vref Scan disable
4250 15:37:06.986229 == TX Byte 0 ==
4251 15:37:06.989522 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4252 15:37:06.992830 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4253 15:37:06.995904 == TX Byte 1 ==
4254 15:37:06.999565 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4255 15:37:07.002708 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4256 15:37:07.005864 ==
4257 15:37:07.009548 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 15:37:07.012782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 15:37:07.012864 ==
4260 15:37:07.012927
4261 15:37:07.012986
4262 15:37:07.016109 TX Vref Scan disable
4263 15:37:07.016215 == TX Byte 0 ==
4264 15:37:07.022432 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4265 15:37:07.025671 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4266 15:37:07.025776 == TX Byte 1 ==
4267 15:37:07.032917 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4268 15:37:07.035981 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4269 15:37:07.036087
4270 15:37:07.036185 [DATLAT]
4271 15:37:07.039189 Freq=600, CH0 RK1
4272 15:37:07.039293
4273 15:37:07.039387 DATLAT Default: 0x9
4274 15:37:07.042308 0, 0xFFFF, sum = 0
4275 15:37:07.042416 1, 0xFFFF, sum = 0
4276 15:37:07.046193 2, 0xFFFF, sum = 0
4277 15:37:07.046301 3, 0xFFFF, sum = 0
4278 15:37:07.049400 4, 0xFFFF, sum = 0
4279 15:37:07.052393 5, 0xFFFF, sum = 0
4280 15:37:07.052499 6, 0xFFFF, sum = 0
4281 15:37:07.055514 7, 0xFFFF, sum = 0
4282 15:37:07.055624 8, 0x0, sum = 1
4283 15:37:07.055723 9, 0x0, sum = 2
4284 15:37:07.059193 10, 0x0, sum = 3
4285 15:37:07.059298 11, 0x0, sum = 4
4286 15:37:07.062438 best_step = 9
4287 15:37:07.062539
4288 15:37:07.062642 ==
4289 15:37:07.065615 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 15:37:07.069353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 15:37:07.069462 ==
4292 15:37:07.072337 RX Vref Scan: 0
4293 15:37:07.072447
4294 15:37:07.072542 RX Vref 0 -> 0, step: 1
4295 15:37:07.072632
4296 15:37:07.075433 RX Delay -163 -> 252, step: 8
4297 15:37:07.082876 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4298 15:37:07.086027 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4299 15:37:07.089225 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4300 15:37:07.092923 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4301 15:37:07.095980 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4302 15:37:07.102559 iDelay=197, Bit 5, Center 48 (-91 ~ 188) 280
4303 15:37:07.105983 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4304 15:37:07.109479 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4305 15:37:07.112654 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4306 15:37:07.115828 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4307 15:37:07.122973 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4308 15:37:07.126186 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4309 15:37:07.129462 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4310 15:37:07.132787 iDelay=197, Bit 13, Center 48 (-91 ~ 188) 280
4311 15:37:07.139145 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4312 15:37:07.142360 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4313 15:37:07.142467 ==
4314 15:37:07.145873 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 15:37:07.149153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 15:37:07.149260 ==
4317 15:37:07.152316 DQS Delay:
4318 15:37:07.152389 DQS0 = 0, DQS1 = 0
4319 15:37:07.152455 DQM Delay:
4320 15:37:07.155407 DQM0 = 53, DQM1 = 46
4321 15:37:07.155500 DQ Delay:
4322 15:37:07.159233 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4323 15:37:07.162242 DQ4 =56, DQ5 =48, DQ6 =56, DQ7 =56
4324 15:37:07.165409 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4325 15:37:07.169193 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4326 15:37:07.169294
4327 15:37:07.169386
4328 15:37:07.178704 [DQSOSCAuto] RK1, (LSB)MR18= 0x6828, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4329 15:37:07.178792 CH0 RK1: MR19=808, MR18=6828
4330 15:37:07.185535 CH0_RK1: MR19=0x808, MR18=0x6828, DQSOSC=390, MR23=63, INC=172, DEC=114
4331 15:37:07.188622 [RxdqsGatingPostProcess] freq 600
4332 15:37:07.195836 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4333 15:37:07.198941 Pre-setting of DQS Precalculation
4334 15:37:07.202511 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4335 15:37:07.202622 ==
4336 15:37:07.205938 Dram Type= 6, Freq= 0, CH_1, rank 0
4337 15:37:07.212479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 15:37:07.212584 ==
4339 15:37:07.215474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4340 15:37:07.222315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4341 15:37:07.225654 [CA 0] Center 35 (5~66) winsize 62
4342 15:37:07.228928 [CA 1] Center 35 (5~66) winsize 62
4343 15:37:07.232219 [CA 2] Center 34 (4~65) winsize 62
4344 15:37:07.235386 [CA 3] Center 34 (4~65) winsize 62
4345 15:37:07.238651 [CA 4] Center 34 (4~65) winsize 62
4346 15:37:07.242385 [CA 5] Center 33 (3~64) winsize 62
4347 15:37:07.242459
4348 15:37:07.245612 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4349 15:37:07.245686
4350 15:37:07.248570 [CATrainingPosCal] consider 1 rank data
4351 15:37:07.252374 u2DelayCellTimex100 = 270/100 ps
4352 15:37:07.255604 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4353 15:37:07.258648 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4354 15:37:07.265061 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4355 15:37:07.268690 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4356 15:37:07.271879 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4357 15:37:07.275607 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4358 15:37:07.275694
4359 15:37:07.278733 CA PerBit enable=1, Macro0, CA PI delay=33
4360 15:37:07.278809
4361 15:37:07.282203 [CBTSetCACLKResult] CA Dly = 33
4362 15:37:07.282319 CS Dly: 5 (0~36)
4363 15:37:07.282411 ==
4364 15:37:07.285338 Dram Type= 6, Freq= 0, CH_1, rank 1
4365 15:37:07.291686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 15:37:07.291790 ==
4367 15:37:07.295427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4368 15:37:07.301930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4369 15:37:07.305081 [CA 0] Center 36 (5~67) winsize 63
4370 15:37:07.308908 [CA 1] Center 36 (6~67) winsize 62
4371 15:37:07.311811 [CA 2] Center 35 (4~66) winsize 63
4372 15:37:07.315428 [CA 3] Center 35 (4~66) winsize 63
4373 15:37:07.318674 [CA 4] Center 35 (4~66) winsize 63
4374 15:37:07.321714 [CA 5] Center 34 (4~65) winsize 62
4375 15:37:07.321791
4376 15:37:07.325329 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4377 15:37:07.325430
4378 15:37:07.328290 [CATrainingPosCal] consider 2 rank data
4379 15:37:07.331959 u2DelayCellTimex100 = 270/100 ps
4380 15:37:07.335142 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4381 15:37:07.338415 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4382 15:37:07.345387 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4383 15:37:07.348563 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4384 15:37:07.351699 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4385 15:37:07.355410 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4386 15:37:07.355521
4387 15:37:07.358710 CA PerBit enable=1, Macro0, CA PI delay=34
4388 15:37:07.358816
4389 15:37:07.361520 [CBTSetCACLKResult] CA Dly = 34
4390 15:37:07.361618 CS Dly: 6 (0~38)
4391 15:37:07.361715
4392 15:37:07.364730 ----->DramcWriteLeveling(PI) begin...
4393 15:37:07.368510 ==
4394 15:37:07.371539 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 15:37:07.375291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 15:37:07.375394 ==
4397 15:37:07.378439 Write leveling (Byte 0): 30 => 30
4398 15:37:07.381616 Write leveling (Byte 1): 30 => 30
4399 15:37:07.384778 DramcWriteLeveling(PI) end<-----
4400 15:37:07.384952
4401 15:37:07.385068 ==
4402 15:37:07.387983 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 15:37:07.391817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 15:37:07.391891 ==
4405 15:37:07.394927 [Gating] SW mode calibration
4406 15:37:07.401215 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4407 15:37:07.408435 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4408 15:37:07.411516 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4409 15:37:07.414568 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 15:37:07.418070 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4411 15:37:07.424681 0 9 12 | B1->B0 | 2f2f 2d2d | 0 1 | (0 0) (0 0)
4412 15:37:07.428393 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4413 15:37:07.431543 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 15:37:07.438281 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 15:37:07.441504 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 15:37:07.444751 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 15:37:07.451695 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 15:37:07.455020 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4419 15:37:07.458053 0 10 12 | B1->B0 | 3636 3838 | 0 0 | (1 1) (0 0)
4420 15:37:07.464949 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 15:37:07.468214 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 15:37:07.471310 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 15:37:07.478334 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 15:37:07.481491 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 15:37:07.485201 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 15:37:07.491590 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 15:37:07.494732 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 15:37:07.497981 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4429 15:37:07.505076 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 15:37:07.508107 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 15:37:07.511490 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 15:37:07.514591 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 15:37:07.521523 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 15:37:07.524515 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 15:37:07.528151 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 15:37:07.534689 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 15:37:07.537823 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 15:37:07.541548 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 15:37:07.548178 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 15:37:07.551206 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 15:37:07.554914 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 15:37:07.561246 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 15:37:07.564299 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4444 15:37:07.568148 Total UI for P1: 0, mck2ui 16
4445 15:37:07.571241 best dqsien dly found for B0: ( 0, 13, 10)
4446 15:37:07.574477 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 15:37:07.578054 Total UI for P1: 0, mck2ui 16
4448 15:37:07.581403 best dqsien dly found for B1: ( 0, 13, 12)
4449 15:37:07.584673 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4450 15:37:07.587781 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4451 15:37:07.590811
4452 15:37:07.594629 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4453 15:37:07.597803 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4454 15:37:07.600890 [Gating] SW calibration Done
4455 15:37:07.600964 ==
4456 15:37:07.604117 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 15:37:07.607837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 15:37:07.607916 ==
4459 15:37:07.607980 RX Vref Scan: 0
4460 15:37:07.610948
4461 15:37:07.611020 RX Vref 0 -> 0, step: 1
4462 15:37:07.611080
4463 15:37:07.614197 RX Delay -230 -> 252, step: 16
4464 15:37:07.617391 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4465 15:37:07.624499 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4466 15:37:07.627817 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4467 15:37:07.631085 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4468 15:37:07.633949 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4469 15:37:07.637490 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4470 15:37:07.643938 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4471 15:37:07.647807 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4472 15:37:07.651002 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4473 15:37:07.654196 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4474 15:37:07.661053 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4475 15:37:07.664064 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4476 15:37:07.667677 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4477 15:37:07.670878 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4478 15:37:07.673839 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4479 15:37:07.680754 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4480 15:37:07.680859 ==
4481 15:37:07.683995 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 15:37:07.687138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 15:37:07.687246 ==
4484 15:37:07.687336 DQS Delay:
4485 15:37:07.690974 DQS0 = 0, DQS1 = 0
4486 15:37:07.691049 DQM Delay:
4487 15:37:07.694074 DQM0 = 50, DQM1 = 47
4488 15:37:07.694181 DQ Delay:
4489 15:37:07.697311 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4490 15:37:07.700568 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =41
4491 15:37:07.703678 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4492 15:37:07.707604 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4493 15:37:07.707711
4494 15:37:07.707810
4495 15:37:07.707899 ==
4496 15:37:07.710654 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 15:37:07.713949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 15:37:07.714068 ==
4499 15:37:07.717082
4500 15:37:07.717195
4501 15:37:07.717298 TX Vref Scan disable
4502 15:37:07.720865 == TX Byte 0 ==
4503 15:37:07.724132 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4504 15:37:07.727299 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4505 15:37:07.730481 == TX Byte 1 ==
4506 15:37:07.733946 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4507 15:37:07.737386 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4508 15:37:07.737490 ==
4509 15:37:07.740640 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 15:37:07.747267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 15:37:07.747357 ==
4512 15:37:07.747450
4513 15:37:07.747545
4514 15:37:07.747639 TX Vref Scan disable
4515 15:37:07.751953 == TX Byte 0 ==
4516 15:37:07.754959 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4517 15:37:07.758853 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4518 15:37:07.761848 == TX Byte 1 ==
4519 15:37:07.764972 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4520 15:37:07.771812 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4521 15:37:07.771919
4522 15:37:07.772011 [DATLAT]
4523 15:37:07.772103 Freq=600, CH1 RK0
4524 15:37:07.772190
4525 15:37:07.775220 DATLAT Default: 0x9
4526 15:37:07.775323 0, 0xFFFF, sum = 0
4527 15:37:07.778053 1, 0xFFFF, sum = 0
4528 15:37:07.778154 2, 0xFFFF, sum = 0
4529 15:37:07.781526 3, 0xFFFF, sum = 0
4530 15:37:07.785140 4, 0xFFFF, sum = 0
4531 15:37:07.785247 5, 0xFFFF, sum = 0
4532 15:37:07.788309 6, 0xFFFF, sum = 0
4533 15:37:07.788413 7, 0xFFFF, sum = 0
4534 15:37:07.788510 8, 0x0, sum = 1
4535 15:37:07.791427 9, 0x0, sum = 2
4536 15:37:07.791532 10, 0x0, sum = 3
4537 15:37:07.795266 11, 0x0, sum = 4
4538 15:37:07.795370 best_step = 9
4539 15:37:07.795459
4540 15:37:07.795545 ==
4541 15:37:07.798531 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 15:37:07.805290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 15:37:07.805394 ==
4544 15:37:07.805489 RX Vref Scan: 1
4545 15:37:07.805578
4546 15:37:07.808519 RX Vref 0 -> 0, step: 1
4547 15:37:07.808619
4548 15:37:07.811948 RX Delay -163 -> 252, step: 8
4549 15:37:07.812025
4550 15:37:07.814959 Set Vref, RX VrefLevel [Byte0]: 53
4551 15:37:07.818168 [Byte1]: 53
4552 15:37:07.818272
4553 15:37:07.821981 Final RX Vref Byte 0 = 53 to rank0
4554 15:37:07.825187 Final RX Vref Byte 1 = 53 to rank0
4555 15:37:07.828398 Final RX Vref Byte 0 = 53 to rank1
4556 15:37:07.831522 Final RX Vref Byte 1 = 53 to rank1==
4557 15:37:07.834823 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 15:37:07.838147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 15:37:07.838269 ==
4560 15:37:07.841260 DQS Delay:
4561 15:37:07.841363 DQS0 = 0, DQS1 = 0
4562 15:37:07.841463 DQM Delay:
4563 15:37:07.844953 DQM0 = 48, DQM1 = 45
4564 15:37:07.845056 DQ Delay:
4565 15:37:07.848129 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4566 15:37:07.851164 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4567 15:37:07.855081 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4568 15:37:07.857974 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4569 15:37:07.858074
4570 15:37:07.858165
4571 15:37:07.867684 [DQSOSCAuto] RK0, (LSB)MR18= 0x496e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4572 15:37:07.870927 CH1 RK0: MR19=808, MR18=496E
4573 15:37:07.874816 CH1_RK0: MR19=0x808, MR18=0x496E, DQSOSC=389, MR23=63, INC=173, DEC=115
4574 15:37:07.877976
4575 15:37:07.881043 ----->DramcWriteLeveling(PI) begin...
4576 15:37:07.881145 ==
4577 15:37:07.884484 Dram Type= 6, Freq= 0, CH_1, rank 1
4578 15:37:07.887643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 15:37:07.887717 ==
4580 15:37:07.891037 Write leveling (Byte 0): 29 => 29
4581 15:37:07.894304 Write leveling (Byte 1): 32 => 32
4582 15:37:07.897841 DramcWriteLeveling(PI) end<-----
4583 15:37:07.897956
4584 15:37:07.898056 ==
4585 15:37:07.901326 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 15:37:07.904564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 15:37:07.904643 ==
4588 15:37:07.907474 [Gating] SW mode calibration
4589 15:37:07.914395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4590 15:37:07.921304 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4591 15:37:07.924501 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 15:37:07.927803 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 15:37:07.930955 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4594 15:37:07.938023 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
4595 15:37:07.941199 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 15:37:07.944312 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 15:37:07.951234 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 15:37:07.954425 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 15:37:07.957597 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 15:37:07.964492 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 15:37:07.967609 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 15:37:07.971046 0 10 12 | B1->B0 | 3f3f 3737 | 0 0 | (0 0) (0 0)
4603 15:37:07.978025 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 15:37:07.981171 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 15:37:07.984400 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 15:37:07.990745 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 15:37:07.994590 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 15:37:07.997644 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 15:37:08.004540 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4610 15:37:08.007328 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 15:37:08.010863 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 15:37:08.017543 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 15:37:08.020936 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 15:37:08.024053 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 15:37:08.030685 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 15:37:08.033993 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 15:37:08.037160 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 15:37:08.044382 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 15:37:08.047719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 15:37:08.050533 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 15:37:08.054375 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 15:37:08.060879 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 15:37:08.063998 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 15:37:08.067235 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 15:37:08.074353 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4626 15:37:08.077200 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 15:37:08.080751 Total UI for P1: 0, mck2ui 16
4628 15:37:08.083896 best dqsien dly found for B0: ( 0, 13, 8)
4629 15:37:08.087131 Total UI for P1: 0, mck2ui 16
4630 15:37:08.090983 best dqsien dly found for B1: ( 0, 13, 10)
4631 15:37:08.093999 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4632 15:37:08.097175 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4633 15:37:08.097298
4634 15:37:08.100815 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4635 15:37:08.104017 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4636 15:37:08.107325 [Gating] SW calibration Done
4637 15:37:08.107428 ==
4638 15:37:08.110432 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 15:37:08.117039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 15:37:08.117187 ==
4641 15:37:08.117290 RX Vref Scan: 0
4642 15:37:08.117387
4643 15:37:08.120826 RX Vref 0 -> 0, step: 1
4644 15:37:08.120932
4645 15:37:08.123952 RX Delay -230 -> 252, step: 16
4646 15:37:08.127469 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4647 15:37:08.130345 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4648 15:37:08.133884 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4649 15:37:08.140353 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4650 15:37:08.144066 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4651 15:37:08.147271 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4652 15:37:08.150503 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4653 15:37:08.154041 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4654 15:37:08.160350 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4655 15:37:08.164178 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4656 15:37:08.167229 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4657 15:37:08.170463 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4658 15:37:08.177012 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4659 15:37:08.180770 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4660 15:37:08.183816 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4661 15:37:08.186879 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4662 15:37:08.186984 ==
4663 15:37:08.190590 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 15:37:08.197166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 15:37:08.197272 ==
4666 15:37:08.197366 DQS Delay:
4667 15:37:08.200210 DQS0 = 0, DQS1 = 0
4668 15:37:08.200311 DQM Delay:
4669 15:37:08.200405 DQM0 = 49, DQM1 = 47
4670 15:37:08.203870 DQ Delay:
4671 15:37:08.206897 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4672 15:37:08.210610 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4673 15:37:08.213770 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4674 15:37:08.217401 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4675 15:37:08.217504
4676 15:37:08.217599
4677 15:37:08.217688 ==
4678 15:37:08.220591 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 15:37:08.223498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 15:37:08.223621 ==
4681 15:37:08.223719
4682 15:37:08.223807
4683 15:37:08.227302 TX Vref Scan disable
4684 15:37:08.230423 == TX Byte 0 ==
4685 15:37:08.233675 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4686 15:37:08.236815 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4687 15:37:08.240479 == TX Byte 1 ==
4688 15:37:08.243556 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4689 15:37:08.247234 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4690 15:37:08.247344 ==
4691 15:37:08.250160 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 15:37:08.253624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 15:37:08.256914 ==
4694 15:37:08.257027
4695 15:37:08.257114
4696 15:37:08.257211 TX Vref Scan disable
4697 15:37:08.260608 == TX Byte 0 ==
4698 15:37:08.263711 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4699 15:37:08.267538 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4700 15:37:08.270651 == TX Byte 1 ==
4701 15:37:08.273805 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4702 15:37:08.280815 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4703 15:37:08.280945
4704 15:37:08.281159 [DATLAT]
4705 15:37:08.281265 Freq=600, CH1 RK1
4706 15:37:08.281371
4707 15:37:08.283971 DATLAT Default: 0x9
4708 15:37:08.284047 0, 0xFFFF, sum = 0
4709 15:37:08.287226 1, 0xFFFF, sum = 0
4710 15:37:08.287347 2, 0xFFFF, sum = 0
4711 15:37:08.290750 3, 0xFFFF, sum = 0
4712 15:37:08.290857 4, 0xFFFF, sum = 0
4713 15:37:08.293937 5, 0xFFFF, sum = 0
4714 15:37:08.297150 6, 0xFFFF, sum = 0
4715 15:37:08.297300 7, 0xFFFF, sum = 0
4716 15:37:08.297395 8, 0x0, sum = 1
4717 15:37:08.300311 9, 0x0, sum = 2
4718 15:37:08.300432 10, 0x0, sum = 3
4719 15:37:08.303610 11, 0x0, sum = 4
4720 15:37:08.303686 best_step = 9
4721 15:37:08.303748
4722 15:37:08.303842 ==
4723 15:37:08.306997 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 15:37:08.313664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 15:37:08.313769 ==
4726 15:37:08.313863 RX Vref Scan: 0
4727 15:37:08.313965
4728 15:37:08.317265 RX Vref 0 -> 0, step: 1
4729 15:37:08.317365
4730 15:37:08.320549 RX Delay -163 -> 252, step: 8
4731 15:37:08.323793 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4732 15:37:08.327329 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4733 15:37:08.333840 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4734 15:37:08.337127 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4735 15:37:08.340760 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4736 15:37:08.343833 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4737 15:37:08.347097 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4738 15:37:08.354243 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4739 15:37:08.357538 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4740 15:37:08.360479 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4741 15:37:08.364132 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4742 15:37:08.370341 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4743 15:37:08.373928 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4744 15:37:08.377329 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4745 15:37:08.380932 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4746 15:37:08.384112 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4747 15:37:08.384195 ==
4748 15:37:08.387336 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 15:37:08.393784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 15:37:08.393869 ==
4751 15:37:08.393933 DQS Delay:
4752 15:37:08.397364 DQS0 = 0, DQS1 = 0
4753 15:37:08.397446 DQM Delay:
4754 15:37:08.397510 DQM0 = 49, DQM1 = 46
4755 15:37:08.400415 DQ Delay:
4756 15:37:08.404208 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4757 15:37:08.407316 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4758 15:37:08.410509 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4759 15:37:08.413720 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4760 15:37:08.413802
4761 15:37:08.413866
4762 15:37:08.420193 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4763 15:37:08.423918 CH1 RK1: MR19=808, MR18=6A22
4764 15:37:08.430628 CH1_RK1: MR19=0x808, MR18=0x6A22, DQSOSC=389, MR23=63, INC=173, DEC=115
4765 15:37:08.433524 [RxdqsGatingPostProcess] freq 600
4766 15:37:08.437103 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4767 15:37:08.440223 Pre-setting of DQS Precalculation
4768 15:37:08.447160 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4769 15:37:08.453344 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4770 15:37:08.460277 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4771 15:37:08.460363
4772 15:37:08.460434
4773 15:37:08.463477 [Calibration Summary] 1200 Mbps
4774 15:37:08.463587 CH 0, Rank 0
4775 15:37:08.466667 SW Impedance : PASS
4776 15:37:08.470421 DUTY Scan : NO K
4777 15:37:08.470501 ZQ Calibration : PASS
4778 15:37:08.473419 Jitter Meter : NO K
4779 15:37:08.477015 CBT Training : PASS
4780 15:37:08.477111 Write leveling : PASS
4781 15:37:08.480439 RX DQS gating : PASS
4782 15:37:08.483695 RX DQ/DQS(RDDQC) : PASS
4783 15:37:08.483777 TX DQ/DQS : PASS
4784 15:37:08.486685 RX DATLAT : PASS
4785 15:37:08.490185 RX DQ/DQS(Engine): PASS
4786 15:37:08.490281 TX OE : NO K
4787 15:37:08.494017 All Pass.
4788 15:37:08.494099
4789 15:37:08.494164 CH 0, Rank 1
4790 15:37:08.497211 SW Impedance : PASS
4791 15:37:08.497321 DUTY Scan : NO K
4792 15:37:08.499846 ZQ Calibration : PASS
4793 15:37:08.503701 Jitter Meter : NO K
4794 15:37:08.503775 CBT Training : PASS
4795 15:37:08.507059 Write leveling : PASS
4796 15:37:08.507131 RX DQS gating : PASS
4797 15:37:08.510048 RX DQ/DQS(RDDQC) : PASS
4798 15:37:08.513320 TX DQ/DQS : PASS
4799 15:37:08.513402 RX DATLAT : PASS
4800 15:37:08.516534 RX DQ/DQS(Engine): PASS
4801 15:37:08.520308 TX OE : NO K
4802 15:37:08.520429 All Pass.
4803 15:37:08.520531
4804 15:37:08.520621 CH 1, Rank 0
4805 15:37:08.523565 SW Impedance : PASS
4806 15:37:08.526793 DUTY Scan : NO K
4807 15:37:08.526913 ZQ Calibration : PASS
4808 15:37:08.530348 Jitter Meter : NO K
4809 15:37:08.533401 CBT Training : PASS
4810 15:37:08.533479 Write leveling : PASS
4811 15:37:08.537092 RX DQS gating : PASS
4812 15:37:08.540014 RX DQ/DQS(RDDQC) : PASS
4813 15:37:08.540095 TX DQ/DQS : PASS
4814 15:37:08.543061 RX DATLAT : PASS
4815 15:37:08.546673 RX DQ/DQS(Engine): PASS
4816 15:37:08.546750 TX OE : NO K
4817 15:37:08.546818 All Pass.
4818 15:37:08.549707
4819 15:37:08.549811 CH 1, Rank 1
4820 15:37:08.553460 SW Impedance : PASS
4821 15:37:08.553541 DUTY Scan : NO K
4822 15:37:08.556700 ZQ Calibration : PASS
4823 15:37:08.556805 Jitter Meter : NO K
4824 15:37:08.559988 CBT Training : PASS
4825 15:37:08.563268 Write leveling : PASS
4826 15:37:08.563373 RX DQS gating : PASS
4827 15:37:08.567001 RX DQ/DQS(RDDQC) : PASS
4828 15:37:08.570258 TX DQ/DQS : PASS
4829 15:37:08.570339 RX DATLAT : PASS
4830 15:37:08.573571 RX DQ/DQS(Engine): PASS
4831 15:37:08.576770 TX OE : NO K
4832 15:37:08.576875 All Pass.
4833 15:37:08.576966
4834 15:37:08.579987 DramC Write-DBI off
4835 15:37:08.580090 PER_BANK_REFRESH: Hybrid Mode
4836 15:37:08.583166 TX_TRACKING: ON
4837 15:37:08.589918 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4838 15:37:08.596253 [FAST_K] Save calibration result to emmc
4839 15:37:08.599814 dramc_set_vcore_voltage set vcore to 662500
4840 15:37:08.599891 Read voltage for 933, 3
4841 15:37:08.603277 Vio18 = 0
4842 15:37:08.603368 Vcore = 662500
4843 15:37:08.603432 Vdram = 0
4844 15:37:08.606558 Vddq = 0
4845 15:37:08.606661 Vmddr = 0
4846 15:37:08.609719 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4847 15:37:08.616345 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4848 15:37:08.619529 MEM_TYPE=3, freq_sel=17
4849 15:37:08.622749 sv_algorithm_assistance_LP4_1600
4850 15:37:08.626658 ============ PULL DRAM RESETB DOWN ============
4851 15:37:08.629828 ========== PULL DRAM RESETB DOWN end =========
4852 15:37:08.632989 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4853 15:37:08.636162 ===================================
4854 15:37:08.639407 LPDDR4 DRAM CONFIGURATION
4855 15:37:08.643082 ===================================
4856 15:37:08.646642 EX_ROW_EN[0] = 0x0
4857 15:37:08.646731 EX_ROW_EN[1] = 0x0
4858 15:37:08.649815 LP4Y_EN = 0x0
4859 15:37:08.649903 WORK_FSP = 0x0
4860 15:37:08.653274 WL = 0x3
4861 15:37:08.653354 RL = 0x3
4862 15:37:08.656132 BL = 0x2
4863 15:37:08.656215 RPST = 0x0
4864 15:37:08.659919 RD_PRE = 0x0
4865 15:37:08.660006 WR_PRE = 0x1
4866 15:37:08.662876 WR_PST = 0x0
4867 15:37:08.666106 DBI_WR = 0x0
4868 15:37:08.666197 DBI_RD = 0x0
4869 15:37:08.669835 OTF = 0x1
4870 15:37:08.673138 ===================================
4871 15:37:08.676339 ===================================
4872 15:37:08.676422 ANA top config
4873 15:37:08.679648 ===================================
4874 15:37:08.682771 DLL_ASYNC_EN = 0
4875 15:37:08.682877 ALL_SLAVE_EN = 1
4876 15:37:08.686525 NEW_RANK_MODE = 1
4877 15:37:08.689559 DLL_IDLE_MODE = 1
4878 15:37:08.692614 LP45_APHY_COMB_EN = 1
4879 15:37:08.696332 TX_ODT_DIS = 1
4880 15:37:08.696417 NEW_8X_MODE = 1
4881 15:37:08.699521 ===================================
4882 15:37:08.702692 ===================================
4883 15:37:08.706251 data_rate = 1866
4884 15:37:08.709908 CKR = 1
4885 15:37:08.712970 DQ_P2S_RATIO = 8
4886 15:37:08.716154 ===================================
4887 15:37:08.719740 CA_P2S_RATIO = 8
4888 15:37:08.719827 DQ_CA_OPEN = 0
4889 15:37:08.723397 DQ_SEMI_OPEN = 0
4890 15:37:08.726267 CA_SEMI_OPEN = 0
4891 15:37:08.729423 CA_FULL_RATE = 0
4892 15:37:08.733197 DQ_CKDIV4_EN = 1
4893 15:37:08.736527 CA_CKDIV4_EN = 1
4894 15:37:08.736609 CA_PREDIV_EN = 0
4895 15:37:08.739666 PH8_DLY = 0
4896 15:37:08.742738 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4897 15:37:08.746668 DQ_AAMCK_DIV = 4
4898 15:37:08.749867 CA_AAMCK_DIV = 4
4899 15:37:08.752933 CA_ADMCK_DIV = 4
4900 15:37:08.753040 DQ_TRACK_CA_EN = 0
4901 15:37:08.756074 CA_PICK = 933
4902 15:37:08.759980 CA_MCKIO = 933
4903 15:37:08.763050 MCKIO_SEMI = 0
4904 15:37:08.765965 PLL_FREQ = 3732
4905 15:37:08.769460 DQ_UI_PI_RATIO = 32
4906 15:37:08.773050 CA_UI_PI_RATIO = 0
4907 15:37:08.776400 ===================================
4908 15:37:08.779473 ===================================
4909 15:37:08.779575 memory_type:LPDDR4
4910 15:37:08.782713 GP_NUM : 10
4911 15:37:08.786011 SRAM_EN : 1
4912 15:37:08.786091 MD32_EN : 0
4913 15:37:08.789923 ===================================
4914 15:37:08.793124 [ANA_INIT] >>>>>>>>>>>>>>
4915 15:37:08.796343 <<<<<< [CONFIGURE PHASE]: ANA_TX
4916 15:37:08.799360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4917 15:37:08.803022 ===================================
4918 15:37:08.806176 data_rate = 1866,PCW = 0X8f00
4919 15:37:08.809287 ===================================
4920 15:37:08.812780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4921 15:37:08.816184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4922 15:37:08.822988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 15:37:08.826207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4924 15:37:08.829209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4925 15:37:08.832889 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4926 15:37:08.836296 [ANA_INIT] flow start
4927 15:37:08.839461 [ANA_INIT] PLL >>>>>>>>
4928 15:37:08.839567 [ANA_INIT] PLL <<<<<<<<
4929 15:37:08.842793 [ANA_INIT] MIDPI >>>>>>>>
4930 15:37:08.846257 [ANA_INIT] MIDPI <<<<<<<<
4931 15:37:08.846333 [ANA_INIT] DLL >>>>>>>>
4932 15:37:08.849418 [ANA_INIT] flow end
4933 15:37:08.852568 ============ LP4 DIFF to SE enter ============
4934 15:37:08.859431 ============ LP4 DIFF to SE exit ============
4935 15:37:08.859541 [ANA_INIT] <<<<<<<<<<<<<
4936 15:37:08.862615 [Flow] Enable top DCM control >>>>>
4937 15:37:08.865895 [Flow] Enable top DCM control <<<<<
4938 15:37:08.869098 Enable DLL master slave shuffle
4939 15:37:08.876016 ==============================================================
4940 15:37:08.876131 Gating Mode config
4941 15:37:08.882270 ==============================================================
4942 15:37:08.885559 Config description:
4943 15:37:08.892521 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4944 15:37:08.899046 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4945 15:37:08.905803 SELPH_MODE 0: By rank 1: By Phase
4946 15:37:08.912147 ==============================================================
4947 15:37:08.912231 GAT_TRACK_EN = 1
4948 15:37:08.915853 RX_GATING_MODE = 2
4949 15:37:08.918819 RX_GATING_TRACK_MODE = 2
4950 15:37:08.922580 SELPH_MODE = 1
4951 15:37:08.925944 PICG_EARLY_EN = 1
4952 15:37:08.928864 VALID_LAT_VALUE = 1
4953 15:37:08.936103 ==============================================================
4954 15:37:08.939214 Enter into Gating configuration >>>>
4955 15:37:08.942173 Exit from Gating configuration <<<<
4956 15:37:08.945841 Enter into DVFS_PRE_config >>>>>
4957 15:37:08.955988 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4958 15:37:08.959239 Exit from DVFS_PRE_config <<<<<
4959 15:37:08.962466 Enter into PICG configuration >>>>
4960 15:37:08.965504 Exit from PICG configuration <<<<
4961 15:37:08.969172 [RX_INPUT] configuration >>>>>
4962 15:37:08.969286 [RX_INPUT] configuration <<<<<
4963 15:37:08.975452 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4964 15:37:08.981816 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4965 15:37:08.985593 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4966 15:37:08.991866 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4967 15:37:08.998989 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 15:37:09.005271 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 15:37:09.008998 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4970 15:37:09.012255 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4971 15:37:09.019126 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4972 15:37:09.022176 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4973 15:37:09.025362 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4974 15:37:09.032199 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4975 15:37:09.035361 ===================================
4976 15:37:09.035468 LPDDR4 DRAM CONFIGURATION
4977 15:37:09.038657 ===================================
4978 15:37:09.041842 EX_ROW_EN[0] = 0x0
4979 15:37:09.041951 EX_ROW_EN[1] = 0x0
4980 15:37:09.045553 LP4Y_EN = 0x0
4981 15:37:09.045655 WORK_FSP = 0x0
4982 15:37:09.049092 WL = 0x3
4983 15:37:09.049169 RL = 0x3
4984 15:37:09.051901 BL = 0x2
4985 15:37:09.051975 RPST = 0x0
4986 15:37:09.055336 RD_PRE = 0x0
4987 15:37:09.059055 WR_PRE = 0x1
4988 15:37:09.059160 WR_PST = 0x0
4989 15:37:09.062278 DBI_WR = 0x0
4990 15:37:09.062390 DBI_RD = 0x0
4991 15:37:09.065564 OTF = 0x1
4992 15:37:09.068706 ===================================
4993 15:37:09.072554 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4994 15:37:09.075608 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4995 15:37:09.078884 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4996 15:37:09.082117 ===================================
4997 15:37:09.085336 LPDDR4 DRAM CONFIGURATION
4998 15:37:09.089131 ===================================
4999 15:37:09.092066 EX_ROW_EN[0] = 0x10
5000 15:37:09.092144 EX_ROW_EN[1] = 0x0
5001 15:37:09.095316 LP4Y_EN = 0x0
5002 15:37:09.095417 WORK_FSP = 0x0
5003 15:37:09.098785 WL = 0x3
5004 15:37:09.098860 RL = 0x3
5005 15:37:09.102170 BL = 0x2
5006 15:37:09.102277 RPST = 0x0
5007 15:37:09.105132 RD_PRE = 0x0
5008 15:37:09.105231 WR_PRE = 0x1
5009 15:37:09.109051 WR_PST = 0x0
5010 15:37:09.109132 DBI_WR = 0x0
5011 15:37:09.112219 DBI_RD = 0x0
5012 15:37:09.112293 OTF = 0x1
5013 15:37:09.115259 ===================================
5014 15:37:09.122184 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5015 15:37:09.127231 nWR fixed to 30
5016 15:37:09.130371 [ModeRegInit_LP4] CH0 RK0
5017 15:37:09.130470 [ModeRegInit_LP4] CH0 RK1
5018 15:37:09.133532 [ModeRegInit_LP4] CH1 RK0
5019 15:37:09.136734 [ModeRegInit_LP4] CH1 RK1
5020 15:37:09.136838 match AC timing 9
5021 15:37:09.143367 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5022 15:37:09.146469 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5023 15:37:09.150434 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5024 15:37:09.156690 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5025 15:37:09.160102 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5026 15:37:09.160178 ==
5027 15:37:09.163120 Dram Type= 6, Freq= 0, CH_0, rank 0
5028 15:37:09.166847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5029 15:37:09.166926 ==
5030 15:37:09.173346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5031 15:37:09.179683 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5032 15:37:09.183459 [CA 0] Center 37 (6~68) winsize 63
5033 15:37:09.186639 [CA 1] Center 37 (7~68) winsize 62
5034 15:37:09.189868 [CA 2] Center 34 (4~65) winsize 62
5035 15:37:09.193071 [CA 3] Center 34 (3~65) winsize 63
5036 15:37:09.196326 [CA 4] Center 33 (3~64) winsize 62
5037 15:37:09.200257 [CA 5] Center 32 (2~62) winsize 61
5038 15:37:09.200333
5039 15:37:09.203348 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5040 15:37:09.203447
5041 15:37:09.206397 [CATrainingPosCal] consider 1 rank data
5042 15:37:09.209869 u2DelayCellTimex100 = 270/100 ps
5043 15:37:09.213049 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5044 15:37:09.216190 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5045 15:37:09.220016 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5046 15:37:09.223068 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5047 15:37:09.226593 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5048 15:37:09.232835 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5049 15:37:09.232921
5050 15:37:09.236534 CA PerBit enable=1, Macro0, CA PI delay=32
5051 15:37:09.236611
5052 15:37:09.239821 [CBTSetCACLKResult] CA Dly = 32
5053 15:37:09.239922 CS Dly: 5 (0~36)
5054 15:37:09.240013 ==
5055 15:37:09.242981 Dram Type= 6, Freq= 0, CH_0, rank 1
5056 15:37:09.246187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 15:37:09.249225 ==
5058 15:37:09.252373 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 15:37:09.259462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5060 15:37:09.262553 [CA 0] Center 37 (6~68) winsize 63
5061 15:37:09.265644 [CA 1] Center 37 (7~68) winsize 62
5062 15:37:09.269149 [CA 2] Center 34 (4~65) winsize 62
5063 15:37:09.272596 [CA 3] Center 34 (3~65) winsize 63
5064 15:37:09.275720 [CA 4] Center 32 (2~63) winsize 62
5065 15:37:09.279001 [CA 5] Center 32 (2~62) winsize 61
5066 15:37:09.279106
5067 15:37:09.282176 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5068 15:37:09.282276
5069 15:37:09.285997 [CATrainingPosCal] consider 2 rank data
5070 15:37:09.289098 u2DelayCellTimex100 = 270/100 ps
5071 15:37:09.292265 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5072 15:37:09.295425 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5073 15:37:09.299351 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5074 15:37:09.305628 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5075 15:37:09.308970 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5076 15:37:09.312238 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5077 15:37:09.312346
5078 15:37:09.315481 CA PerBit enable=1, Macro0, CA PI delay=32
5079 15:37:09.315581
5080 15:37:09.319269 [CBTSetCACLKResult] CA Dly = 32
5081 15:37:09.319369 CS Dly: 5 (0~37)
5082 15:37:09.319462
5083 15:37:09.322702 ----->DramcWriteLeveling(PI) begin...
5084 15:37:09.322802 ==
5085 15:37:09.326067 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 15:37:09.332113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 15:37:09.332202 ==
5088 15:37:09.335748 Write leveling (Byte 0): 34 => 34
5089 15:37:09.339134 Write leveling (Byte 1): 30 => 30
5090 15:37:09.339244 DramcWriteLeveling(PI) end<-----
5091 15:37:09.342244
5092 15:37:09.342344 ==
5093 15:37:09.346078 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 15:37:09.349256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 15:37:09.349364 ==
5096 15:37:09.352334 [Gating] SW mode calibration
5097 15:37:09.359275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5098 15:37:09.362484 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5099 15:37:09.368958 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5100 15:37:09.372176 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 15:37:09.375722 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 15:37:09.382598 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 15:37:09.385927 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 15:37:09.388902 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 15:37:09.395847 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5106 15:37:09.399139 0 14 28 | B1->B0 | 3232 2525 | 1 0 | (1 0) (1 0)
5107 15:37:09.402328 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5108 15:37:09.408542 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 15:37:09.411825 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 15:37:09.415482 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 15:37:09.421962 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 15:37:09.425082 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 15:37:09.428396 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5114 15:37:09.435397 0 15 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
5115 15:37:09.438420 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5116 15:37:09.442130 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 15:37:09.448595 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 15:37:09.452169 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 15:37:09.455079 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 15:37:09.462019 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 15:37:09.465247 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5122 15:37:09.468411 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5123 15:37:09.475326 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5124 15:37:09.478554 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 15:37:09.481705 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 15:37:09.488646 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 15:37:09.491747 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 15:37:09.495019 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 15:37:09.498206 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 15:37:09.505209 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 15:37:09.508360 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 15:37:09.511707 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 15:37:09.518141 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 15:37:09.521370 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 15:37:09.525237 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 15:37:09.531786 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 15:37:09.535082 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5138 15:37:09.538324 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5139 15:37:09.545265 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 15:37:09.545378 Total UI for P1: 0, mck2ui 16
5141 15:37:09.551452 best dqsien dly found for B0: ( 1, 2, 26)
5142 15:37:09.551555 Total UI for P1: 0, mck2ui 16
5143 15:37:09.558404 best dqsien dly found for B1: ( 1, 2, 30)
5144 15:37:09.562053 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5145 15:37:09.564894 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5146 15:37:09.565004
5147 15:37:09.568505 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5148 15:37:09.571883 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5149 15:37:09.575081 [Gating] SW calibration Done
5150 15:37:09.575188 ==
5151 15:37:09.578281 Dram Type= 6, Freq= 0, CH_0, rank 0
5152 15:37:09.581579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 15:37:09.581680 ==
5154 15:37:09.584794 RX Vref Scan: 0
5155 15:37:09.584900
5156 15:37:09.585000 RX Vref 0 -> 0, step: 1
5157 15:37:09.585088
5158 15:37:09.588086 RX Delay -80 -> 252, step: 8
5159 15:37:09.591279 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5160 15:37:09.598121 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5161 15:37:09.601344 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5162 15:37:09.604979 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5163 15:37:09.608171 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5164 15:37:09.611302 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5165 15:37:09.615197 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5166 15:37:09.621643 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5167 15:37:09.624910 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5168 15:37:09.628165 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5169 15:37:09.631413 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5170 15:37:09.635357 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5171 15:37:09.638406 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5172 15:37:09.641575 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5173 15:37:09.647848 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5174 15:37:09.651465 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5175 15:37:09.651578 ==
5176 15:37:09.655047 Dram Type= 6, Freq= 0, CH_0, rank 0
5177 15:37:09.657996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 15:37:09.658078 ==
5179 15:37:09.661577 DQS Delay:
5180 15:37:09.661659 DQS0 = 0, DQS1 = 0
5181 15:37:09.661723 DQM Delay:
5182 15:37:09.664605 DQM0 = 104, DQM1 = 95
5183 15:37:09.664687 DQ Delay:
5184 15:37:09.668286 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5185 15:37:09.671794 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5186 15:37:09.674725 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5187 15:37:09.677742 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5188 15:37:09.677829
5189 15:37:09.677893
5190 15:37:09.681574 ==
5191 15:37:09.684673 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 15:37:09.687867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 15:37:09.687950 ==
5194 15:37:09.688015
5195 15:37:09.688074
5196 15:37:09.691166 TX Vref Scan disable
5197 15:37:09.691265 == TX Byte 0 ==
5198 15:37:09.694978 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5199 15:37:09.701057 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5200 15:37:09.701139 == TX Byte 1 ==
5201 15:37:09.704676 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5202 15:37:09.711320 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5203 15:37:09.711437 ==
5204 15:37:09.714460 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 15:37:09.717632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 15:37:09.717719 ==
5207 15:37:09.717785
5208 15:37:09.717845
5209 15:37:09.720884 TX Vref Scan disable
5210 15:37:09.724124 == TX Byte 0 ==
5211 15:37:09.727861 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5212 15:37:09.731174 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5213 15:37:09.734501 == TX Byte 1 ==
5214 15:37:09.737539 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5215 15:37:09.740788 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5216 15:37:09.740868
5217 15:37:09.744658 [DATLAT]
5218 15:37:09.744773 Freq=933, CH0 RK0
5219 15:37:09.744837
5220 15:37:09.747873 DATLAT Default: 0xd
5221 15:37:09.747958 0, 0xFFFF, sum = 0
5222 15:37:09.751191 1, 0xFFFF, sum = 0
5223 15:37:09.751330 2, 0xFFFF, sum = 0
5224 15:37:09.754370 3, 0xFFFF, sum = 0
5225 15:37:09.754447 4, 0xFFFF, sum = 0
5226 15:37:09.757559 5, 0xFFFF, sum = 0
5227 15:37:09.757655 6, 0xFFFF, sum = 0
5228 15:37:09.761166 7, 0xFFFF, sum = 0
5229 15:37:09.761286 8, 0xFFFF, sum = 0
5230 15:37:09.763989 9, 0xFFFF, sum = 0
5231 15:37:09.764063 10, 0x0, sum = 1
5232 15:37:09.767380 11, 0x0, sum = 2
5233 15:37:09.767456 12, 0x0, sum = 3
5234 15:37:09.771209 13, 0x0, sum = 4
5235 15:37:09.771297 best_step = 11
5236 15:37:09.771387
5237 15:37:09.771444 ==
5238 15:37:09.774301 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 15:37:09.780985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 15:37:09.781100 ==
5241 15:37:09.781197 RX Vref Scan: 1
5242 15:37:09.781286
5243 15:37:09.784098 RX Vref 0 -> 0, step: 1
5244 15:37:09.784175
5245 15:37:09.787356 RX Delay -45 -> 252, step: 4
5246 15:37:09.787471
5247 15:37:09.790496 Set Vref, RX VrefLevel [Byte0]: 55
5248 15:37:09.794154 [Byte1]: 46
5249 15:37:09.794258
5250 15:37:09.797236 Final RX Vref Byte 0 = 55 to rank0
5251 15:37:09.800436 Final RX Vref Byte 1 = 46 to rank0
5252 15:37:09.804215 Final RX Vref Byte 0 = 55 to rank1
5253 15:37:09.807135 Final RX Vref Byte 1 = 46 to rank1==
5254 15:37:09.810851 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 15:37:09.813881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 15:37:09.814005 ==
5257 15:37:09.817424 DQS Delay:
5258 15:37:09.817502 DQS0 = 0, DQS1 = 0
5259 15:37:09.817564 DQM Delay:
5260 15:37:09.820592 DQM0 = 105, DQM1 = 94
5261 15:37:09.820684 DQ Delay:
5262 15:37:09.823729 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =102
5263 15:37:09.827615 DQ4 =106, DQ5 =94, DQ6 =114, DQ7 =110
5264 15:37:09.830845 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =90
5265 15:37:09.834126 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5266 15:37:09.834238
5267 15:37:09.837471
5268 15:37:09.844264 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5269 15:37:09.847351 CH0 RK0: MR19=505, MR18=3129
5270 15:37:09.854051 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5271 15:37:09.854167
5272 15:37:09.857488 ----->DramcWriteLeveling(PI) begin...
5273 15:37:09.857592 ==
5274 15:37:09.860650 Dram Type= 6, Freq= 0, CH_0, rank 1
5275 15:37:09.863960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 15:37:09.864037 ==
5277 15:37:09.867367 Write leveling (Byte 0): 31 => 31
5278 15:37:09.870465 Write leveling (Byte 1): 29 => 29
5279 15:37:09.873562 DramcWriteLeveling(PI) end<-----
5280 15:37:09.873663
5281 15:37:09.873762 ==
5282 15:37:09.876908 Dram Type= 6, Freq= 0, CH_0, rank 1
5283 15:37:09.880703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 15:37:09.880803 ==
5285 15:37:09.883984 [Gating] SW mode calibration
5286 15:37:09.890167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5287 15:37:09.897270 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5288 15:37:09.900293 0 14 0 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 0)
5289 15:37:09.903990 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 15:37:09.910603 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 15:37:09.913623 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 15:37:09.916831 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 15:37:09.923542 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 15:37:09.927349 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5295 15:37:09.930369 0 14 28 | B1->B0 | 2d2d 2b2b | 0 0 | (0 0) (0 0)
5296 15:37:09.936734 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5297 15:37:09.940016 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 15:37:09.943205 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 15:37:09.950361 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 15:37:09.953517 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 15:37:09.956747 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 15:37:09.960019 0 15 24 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
5303 15:37:09.967013 0 15 28 | B1->B0 | 3c3c 3d3d | 0 1 | (0 0) (0 0)
5304 15:37:09.970110 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 15:37:09.973262 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 15:37:09.980321 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 15:37:09.983478 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 15:37:09.987064 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 15:37:09.993709 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 15:37:09.996862 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 15:37:09.999966 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5312 15:37:10.007328 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5313 15:37:10.010215 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 15:37:10.013636 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 15:37:10.020208 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 15:37:10.023623 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 15:37:10.026774 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 15:37:10.033874 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 15:37:10.036752 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 15:37:10.040347 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 15:37:10.046674 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 15:37:10.049946 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 15:37:10.053728 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 15:37:10.060185 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 15:37:10.063290 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 15:37:10.066428 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 15:37:10.073479 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5328 15:37:10.076747 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5329 15:37:10.079977 Total UI for P1: 0, mck2ui 16
5330 15:37:10.083196 best dqsien dly found for B1: ( 1, 2, 28)
5331 15:37:10.086473 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 15:37:10.090291 Total UI for P1: 0, mck2ui 16
5333 15:37:10.093438 best dqsien dly found for B0: ( 1, 2, 30)
5334 15:37:10.096577 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5335 15:37:10.099992 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5336 15:37:10.100092
5337 15:37:10.102883 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5338 15:37:10.109761 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5339 15:37:10.109866 [Gating] SW calibration Done
5340 15:37:10.109961 ==
5341 15:37:10.112895 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 15:37:10.119999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 15:37:10.120073 ==
5344 15:37:10.120140 RX Vref Scan: 0
5345 15:37:10.120205
5346 15:37:10.123323 RX Vref 0 -> 0, step: 1
5347 15:37:10.123423
5348 15:37:10.126746 RX Delay -80 -> 252, step: 8
5349 15:37:10.129545 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5350 15:37:10.133122 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5351 15:37:10.136710 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5352 15:37:10.140048 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5353 15:37:10.146287 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5354 15:37:10.149906 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5355 15:37:10.153173 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5356 15:37:10.156409 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5357 15:37:10.160092 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5358 15:37:10.163399 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5359 15:37:10.169839 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5360 15:37:10.173111 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5361 15:37:10.176357 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5362 15:37:10.179655 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5363 15:37:10.182850 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5364 15:37:10.186085 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5365 15:37:10.189319 ==
5366 15:37:10.193142 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 15:37:10.196364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 15:37:10.196462 ==
5369 15:37:10.196554 DQS Delay:
5370 15:37:10.199659 DQS0 = 0, DQS1 = 0
5371 15:37:10.199757 DQM Delay:
5372 15:37:10.202761 DQM0 = 104, DQM1 = 92
5373 15:37:10.202860 DQ Delay:
5374 15:37:10.206538 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5375 15:37:10.209774 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5376 15:37:10.212842 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5377 15:37:10.216244 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5378 15:37:10.216322
5379 15:37:10.216384
5380 15:37:10.216443 ==
5381 15:37:10.219608 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 15:37:10.222635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 15:37:10.222737 ==
5384 15:37:10.226506
5385 15:37:10.226578
5386 15:37:10.226638 TX Vref Scan disable
5387 15:37:10.229525 == TX Byte 0 ==
5388 15:37:10.233228 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5389 15:37:10.236072 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5390 15:37:10.239378 == TX Byte 1 ==
5391 15:37:10.242748 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5392 15:37:10.246163 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5393 15:37:10.246261 ==
5394 15:37:10.249282 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 15:37:10.256072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 15:37:10.256145 ==
5397 15:37:10.256211
5398 15:37:10.256269
5399 15:37:10.256325 TX Vref Scan disable
5400 15:37:10.260583 == TX Byte 0 ==
5401 15:37:10.263493 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5402 15:37:10.270586 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5403 15:37:10.270686 == TX Byte 1 ==
5404 15:37:10.273816 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5405 15:37:10.280372 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5406 15:37:10.280458
5407 15:37:10.280555 [DATLAT]
5408 15:37:10.280646 Freq=933, CH0 RK1
5409 15:37:10.280734
5410 15:37:10.283410 DATLAT Default: 0xb
5411 15:37:10.283506 0, 0xFFFF, sum = 0
5412 15:37:10.286759 1, 0xFFFF, sum = 0
5413 15:37:10.286860 2, 0xFFFF, sum = 0
5414 15:37:10.290029 3, 0xFFFF, sum = 0
5415 15:37:10.293926 4, 0xFFFF, sum = 0
5416 15:37:10.294029 5, 0xFFFF, sum = 0
5417 15:37:10.297145 6, 0xFFFF, sum = 0
5418 15:37:10.297246 7, 0xFFFF, sum = 0
5419 15:37:10.300227 8, 0xFFFF, sum = 0
5420 15:37:10.300326 9, 0xFFFF, sum = 0
5421 15:37:10.303546 10, 0x0, sum = 1
5422 15:37:10.303642 11, 0x0, sum = 2
5423 15:37:10.303715 12, 0x0, sum = 3
5424 15:37:10.306727 13, 0x0, sum = 4
5425 15:37:10.306826 best_step = 11
5426 15:37:10.306916
5427 15:37:10.307005 ==
5428 15:37:10.310696 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 15:37:10.316868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 15:37:10.316978 ==
5431 15:37:10.317071 RX Vref Scan: 0
5432 15:37:10.317165
5433 15:37:10.320546 RX Vref 0 -> 0, step: 1
5434 15:37:10.320642
5435 15:37:10.323649 RX Delay -53 -> 252, step: 4
5436 15:37:10.326644 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5437 15:37:10.333166 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5438 15:37:10.337027 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5439 15:37:10.340162 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5440 15:37:10.343225 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5441 15:37:10.346826 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5442 15:37:10.353668 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5443 15:37:10.356516 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5444 15:37:10.360153 iDelay=199, Bit 8, Center 82 (-1 ~ 166) 168
5445 15:37:10.363263 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5446 15:37:10.366879 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5447 15:37:10.370347 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5448 15:37:10.376930 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5449 15:37:10.379963 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5450 15:37:10.383249 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5451 15:37:10.386920 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5452 15:37:10.386997 ==
5453 15:37:10.390091 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 15:37:10.396611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 15:37:10.396714 ==
5456 15:37:10.396817 DQS Delay:
5457 15:37:10.396909 DQS0 = 0, DQS1 = 0
5458 15:37:10.399817 DQM Delay:
5459 15:37:10.399886 DQM0 = 104, DQM1 = 93
5460 15:37:10.403047 DQ Delay:
5461 15:37:10.406983 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5462 15:37:10.410147 DQ4 =106, DQ5 =96, DQ6 =108, DQ7 =112
5463 15:37:10.413359 DQ8 =82, DQ9 =82, DQ10 =96, DQ11 =88
5464 15:37:10.416558 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5465 15:37:10.416656
5466 15:37:10.416746
5467 15:37:10.423524 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5468 15:37:10.426649 CH0 RK1: MR19=505, MR18=2C03
5469 15:37:10.432896 CH0_RK1: MR19=0x505, MR18=0x2C03, DQSOSC=408, MR23=63, INC=65, DEC=43
5470 15:37:10.436524 [RxdqsGatingPostProcess] freq 933
5471 15:37:10.443173 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5472 15:37:10.443278 best DQS0 dly(2T, 0.5T) = (0, 10)
5473 15:37:10.446395 best DQS1 dly(2T, 0.5T) = (0, 10)
5474 15:37:10.450240 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5475 15:37:10.453260 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5476 15:37:10.456399 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 15:37:10.459579 best DQS1 dly(2T, 0.5T) = (0, 10)
5478 15:37:10.463058 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 15:37:10.466707 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5480 15:37:10.469907 Pre-setting of DQS Precalculation
5481 15:37:10.476389 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5482 15:37:10.476500 ==
5483 15:37:10.479325 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 15:37:10.482776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 15:37:10.482856 ==
5486 15:37:10.489512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5487 15:37:10.492724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5488 15:37:10.496628 [CA 0] Center 36 (6~67) winsize 62
5489 15:37:10.499910 [CA 1] Center 36 (6~67) winsize 62
5490 15:37:10.503132 [CA 2] Center 34 (4~65) winsize 62
5491 15:37:10.507139 [CA 3] Center 34 (4~65) winsize 62
5492 15:37:10.510324 [CA 4] Center 34 (4~64) winsize 61
5493 15:37:10.513637 [CA 5] Center 33 (3~64) winsize 62
5494 15:37:10.513734
5495 15:37:10.516675 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5496 15:37:10.516783
5497 15:37:10.520057 [CATrainingPosCal] consider 1 rank data
5498 15:37:10.523265 u2DelayCellTimex100 = 270/100 ps
5499 15:37:10.526427 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5500 15:37:10.530250 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5501 15:37:10.536679 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5502 15:37:10.539820 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5503 15:37:10.543035 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5504 15:37:10.546646 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5505 15:37:10.546722
5506 15:37:10.549696 CA PerBit enable=1, Macro0, CA PI delay=33
5507 15:37:10.549794
5508 15:37:10.553354 [CBTSetCACLKResult] CA Dly = 33
5509 15:37:10.553457 CS Dly: 7 (0~38)
5510 15:37:10.556621 ==
5511 15:37:10.556694 Dram Type= 6, Freq= 0, CH_1, rank 1
5512 15:37:10.563398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 15:37:10.563500 ==
5514 15:37:10.566407 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5515 15:37:10.572715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5516 15:37:10.576968 [CA 0] Center 36 (6~67) winsize 62
5517 15:37:10.579822 [CA 1] Center 37 (6~68) winsize 63
5518 15:37:10.583326 [CA 2] Center 35 (5~66) winsize 62
5519 15:37:10.586620 [CA 3] Center 34 (4~65) winsize 62
5520 15:37:10.590191 [CA 4] Center 34 (4~65) winsize 62
5521 15:37:10.593217 [CA 5] Center 34 (4~64) winsize 61
5522 15:37:10.593321
5523 15:37:10.596700 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5524 15:37:10.596802
5525 15:37:10.599729 [CATrainingPosCal] consider 2 rank data
5526 15:37:10.603444 u2DelayCellTimex100 = 270/100 ps
5527 15:37:10.606845 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5528 15:37:10.609986 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5529 15:37:10.616581 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5530 15:37:10.619815 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5531 15:37:10.623548 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5532 15:37:10.626798 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5533 15:37:10.626897
5534 15:37:10.630105 CA PerBit enable=1, Macro0, CA PI delay=34
5535 15:37:10.630174
5536 15:37:10.633604 [CBTSetCACLKResult] CA Dly = 34
5537 15:37:10.633698 CS Dly: 8 (0~40)
5538 15:37:10.633757
5539 15:37:10.636919 ----->DramcWriteLeveling(PI) begin...
5540 15:37:10.640204 ==
5541 15:37:10.640302 Dram Type= 6, Freq= 0, CH_1, rank 0
5542 15:37:10.647045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 15:37:10.647173 ==
5544 15:37:10.650150 Write leveling (Byte 0): 26 => 26
5545 15:37:10.653354 Write leveling (Byte 1): 27 => 27
5546 15:37:10.656410 DramcWriteLeveling(PI) end<-----
5547 15:37:10.656522
5548 15:37:10.656591 ==
5549 15:37:10.660053 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 15:37:10.663310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 15:37:10.663425 ==
5552 15:37:10.666544 [Gating] SW mode calibration
5553 15:37:10.673363 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5554 15:37:10.679487 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5555 15:37:10.683333 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 15:37:10.686542 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 15:37:10.689545 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 15:37:10.696331 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 15:37:10.699560 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 15:37:10.702623 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 15:37:10.709749 0 14 24 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (1 0)
5562 15:37:10.712713 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5563 15:37:10.716294 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 15:37:10.722758 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 15:37:10.725993 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 15:37:10.729216 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 15:37:10.736028 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 15:37:10.739204 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 15:37:10.743055 0 15 24 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
5570 15:37:10.749401 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5571 15:37:10.752617 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 15:37:10.755877 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 15:37:10.762412 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 15:37:10.766087 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 15:37:10.769109 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 15:37:10.776132 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 15:37:10.779419 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5578 15:37:10.782464 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5579 15:37:10.789231 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 15:37:10.792492 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 15:37:10.796354 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 15:37:10.802503 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 15:37:10.806395 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 15:37:10.809156 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 15:37:10.816128 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 15:37:10.819091 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 15:37:10.822653 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 15:37:10.829227 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 15:37:10.832316 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 15:37:10.835573 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 15:37:10.838895 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 15:37:10.845777 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 15:37:10.848963 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5594 15:37:10.852180 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 15:37:10.855402 Total UI for P1: 0, mck2ui 16
5596 15:37:10.859263 best dqsien dly found for B0: ( 1, 2, 24)
5597 15:37:10.862398 Total UI for P1: 0, mck2ui 16
5598 15:37:10.865737 best dqsien dly found for B1: ( 1, 2, 24)
5599 15:37:10.868813 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5600 15:37:10.872401 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5601 15:37:10.875349
5602 15:37:10.879205 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5603 15:37:10.882431 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5604 15:37:10.885696 [Gating] SW calibration Done
5605 15:37:10.885770 ==
5606 15:37:10.888845 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 15:37:10.891961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 15:37:10.892062 ==
5609 15:37:10.892152 RX Vref Scan: 0
5610 15:37:10.892239
5611 15:37:10.895867 RX Vref 0 -> 0, step: 1
5612 15:37:10.895946
5613 15:37:10.899032 RX Delay -80 -> 252, step: 8
5614 15:37:10.902209 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5615 15:37:10.905418 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5616 15:37:10.912263 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5617 15:37:10.915287 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5618 15:37:10.919098 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5619 15:37:10.921964 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5620 15:37:10.925583 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5621 15:37:10.929081 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5622 15:37:10.932234 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5623 15:37:10.938656 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5624 15:37:10.941941 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5625 15:37:10.945355 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5626 15:37:10.948575 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5627 15:37:10.951962 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5628 15:37:10.959122 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5629 15:37:10.962286 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5630 15:37:10.962368 ==
5631 15:37:10.965554 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 15:37:10.968794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 15:37:10.968876 ==
5634 15:37:10.972119 DQS Delay:
5635 15:37:10.972200 DQS0 = 0, DQS1 = 0
5636 15:37:10.972263 DQM Delay:
5637 15:37:10.975465 DQM0 = 102, DQM1 = 98
5638 15:37:10.975572 DQ Delay:
5639 15:37:10.978606 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5640 15:37:10.982174 DQ4 =99, DQ5 =115, DQ6 =107, DQ7 =103
5641 15:37:10.985127 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5642 15:37:10.988894 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5643 15:37:10.988999
5644 15:37:10.989091
5645 15:37:10.992064 ==
5646 15:37:10.995200 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 15:37:10.998353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 15:37:10.998455 ==
5649 15:37:10.998572
5650 15:37:10.998660
5651 15:37:11.001518 TX Vref Scan disable
5652 15:37:11.001628 == TX Byte 0 ==
5653 15:37:11.008686 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5654 15:37:11.011814 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5655 15:37:11.011922 == TX Byte 1 ==
5656 15:37:11.018834 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5657 15:37:11.022178 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5658 15:37:11.022260 ==
5659 15:37:11.025244 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 15:37:11.028340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 15:37:11.028422 ==
5662 15:37:11.028514
5663 15:37:11.028576
5664 15:37:11.031985 TX Vref Scan disable
5665 15:37:11.035456 == TX Byte 0 ==
5666 15:37:11.038415 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5667 15:37:11.041662 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5668 15:37:11.045522 == TX Byte 1 ==
5669 15:37:11.048594 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5670 15:37:11.051627 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5671 15:37:11.051727
5672 15:37:11.051817 [DATLAT]
5673 15:37:11.055023 Freq=933, CH1 RK0
5674 15:37:11.055133
5675 15:37:11.058331 DATLAT Default: 0xd
5676 15:37:11.058431 0, 0xFFFF, sum = 0
5677 15:37:11.061838 1, 0xFFFF, sum = 0
5678 15:37:11.061920 2, 0xFFFF, sum = 0
5679 15:37:11.065227 3, 0xFFFF, sum = 0
5680 15:37:11.065307 4, 0xFFFF, sum = 0
5681 15:37:11.068471 5, 0xFFFF, sum = 0
5682 15:37:11.068549 6, 0xFFFF, sum = 0
5683 15:37:11.071685 7, 0xFFFF, sum = 0
5684 15:37:11.071777 8, 0xFFFF, sum = 0
5685 15:37:11.075777 9, 0xFFFF, sum = 0
5686 15:37:11.075856 10, 0x0, sum = 1
5687 15:37:11.078977 11, 0x0, sum = 2
5688 15:37:11.079082 12, 0x0, sum = 3
5689 15:37:11.081595 13, 0x0, sum = 4
5690 15:37:11.081675 best_step = 11
5691 15:37:11.081738
5692 15:37:11.081806 ==
5693 15:37:11.085369 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 15:37:11.088437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 15:37:11.088514 ==
5696 15:37:11.091560 RX Vref Scan: 1
5697 15:37:11.091661
5698 15:37:11.095277 RX Vref 0 -> 0, step: 1
5699 15:37:11.095369
5700 15:37:11.095434 RX Delay -45 -> 252, step: 4
5701 15:37:11.095493
5702 15:37:11.098449 Set Vref, RX VrefLevel [Byte0]: 53
5703 15:37:11.101736 [Byte1]: 53
5704 15:37:11.106890
5705 15:37:11.106971 Final RX Vref Byte 0 = 53 to rank0
5706 15:37:11.110023 Final RX Vref Byte 1 = 53 to rank0
5707 15:37:11.113261 Final RX Vref Byte 0 = 53 to rank1
5708 15:37:11.116387 Final RX Vref Byte 1 = 53 to rank1==
5709 15:37:11.120163 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 15:37:11.126636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 15:37:11.126716 ==
5712 15:37:11.126783 DQS Delay:
5713 15:37:11.126842 DQS0 = 0, DQS1 = 0
5714 15:37:11.129868 DQM Delay:
5715 15:37:11.129946 DQM0 = 103, DQM1 = 100
5716 15:37:11.133474 DQ Delay:
5717 15:37:11.136716 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5718 15:37:11.139909 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5719 15:37:11.142870 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5720 15:37:11.146426 DQ12 =108, DQ13 =108, DQ14 =108, DQ15 =108
5721 15:37:11.146507
5722 15:37:11.146570
5723 15:37:11.152929 [DQSOSCAuto] RK0, (LSB)MR18= 0x172e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5724 15:37:11.156244 CH1 RK0: MR19=505, MR18=172E
5725 15:37:11.163404 CH1_RK0: MR19=0x505, MR18=0x172E, DQSOSC=407, MR23=63, INC=65, DEC=43
5726 15:37:11.163486
5727 15:37:11.166421 ----->DramcWriteLeveling(PI) begin...
5728 15:37:11.166504 ==
5729 15:37:11.170096 Dram Type= 6, Freq= 0, CH_1, rank 1
5730 15:37:11.173036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 15:37:11.173112 ==
5732 15:37:11.176185 Write leveling (Byte 0): 27 => 27
5733 15:37:11.179542 Write leveling (Byte 1): 28 => 28
5734 15:37:11.182724 DramcWriteLeveling(PI) end<-----
5735 15:37:11.182801
5736 15:37:11.182864 ==
5737 15:37:11.186624 Dram Type= 6, Freq= 0, CH_1, rank 1
5738 15:37:11.192956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 15:37:11.193038 ==
5740 15:37:11.193103 [Gating] SW mode calibration
5741 15:37:11.202919 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5742 15:37:11.206384 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5743 15:37:11.209452 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 15:37:11.216369 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 15:37:11.219443 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 15:37:11.222943 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 15:37:11.229449 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 15:37:11.232565 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 15:37:11.236246 0 14 24 | B1->B0 | 2a2a 3131 | 0 0 | (1 0) (0 0)
5750 15:37:11.242765 0 14 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5751 15:37:11.245967 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 15:37:11.249581 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 15:37:11.256399 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 15:37:11.259741 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 15:37:11.262857 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 15:37:11.269900 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5757 15:37:11.272974 0 15 24 | B1->B0 | 3434 2b2a | 0 1 | (0 0) (0 0)
5758 15:37:11.276317 0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5759 15:37:11.282725 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 15:37:11.285913 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 15:37:11.289454 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 15:37:11.296076 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 15:37:11.299303 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 15:37:11.302521 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 15:37:11.306479 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5766 15:37:11.312545 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5767 15:37:11.315995 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 15:37:11.319458 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 15:37:11.326132 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 15:37:11.329191 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 15:37:11.333124 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 15:37:11.339481 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 15:37:11.342727 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 15:37:11.346023 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 15:37:11.352358 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 15:37:11.356416 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 15:37:11.359351 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 15:37:11.366330 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 15:37:11.369622 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 15:37:11.372766 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 15:37:11.379058 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5782 15:37:11.382974 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5783 15:37:11.386097 Total UI for P1: 0, mck2ui 16
5784 15:37:11.389455 best dqsien dly found for B1: ( 1, 2, 24)
5785 15:37:11.392793 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 15:37:11.395916 Total UI for P1: 0, mck2ui 16
5787 15:37:11.399064 best dqsien dly found for B0: ( 1, 2, 26)
5788 15:37:11.402690 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5789 15:37:11.405605 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5790 15:37:11.405681
5791 15:37:11.409331 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5792 15:37:11.415806 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5793 15:37:11.415896 [Gating] SW calibration Done
5794 15:37:11.415968 ==
5795 15:37:11.418896 Dram Type= 6, Freq= 0, CH_1, rank 1
5796 15:37:11.425692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 15:37:11.425798 ==
5798 15:37:11.425898 RX Vref Scan: 0
5799 15:37:11.425990
5800 15:37:11.429215 RX Vref 0 -> 0, step: 1
5801 15:37:11.429290
5802 15:37:11.432150 RX Delay -80 -> 252, step: 8
5803 15:37:11.435630 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5804 15:37:11.438828 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5805 15:37:11.442300 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5806 15:37:11.446211 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5807 15:37:11.452530 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5808 15:37:11.455773 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5809 15:37:11.459039 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5810 15:37:11.462131 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5811 15:37:11.465954 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5812 15:37:11.469371 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5813 15:37:11.475895 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5814 15:37:11.479129 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5815 15:37:11.482326 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5816 15:37:11.486197 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5817 15:37:11.489444 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5818 15:37:11.495937 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5819 15:37:11.496017 ==
5820 15:37:11.499238 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 15:37:11.502285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 15:37:11.502402 ==
5823 15:37:11.502495 DQS Delay:
5824 15:37:11.506238 DQS0 = 0, DQS1 = 0
5825 15:37:11.506345 DQM Delay:
5826 15:37:11.509366 DQM0 = 102, DQM1 = 99
5827 15:37:11.509477 DQ Delay:
5828 15:37:11.512425 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5829 15:37:11.516159 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5830 15:37:11.519192 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5831 15:37:11.522449 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5832 15:37:11.522529
5833 15:37:11.522601
5834 15:37:11.522667 ==
5835 15:37:11.525609 Dram Type= 6, Freq= 0, CH_1, rank 1
5836 15:37:11.528818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5837 15:37:11.532545 ==
5838 15:37:11.532626
5839 15:37:11.532688
5840 15:37:11.532777 TX Vref Scan disable
5841 15:37:11.535745 == TX Byte 0 ==
5842 15:37:11.538944 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5843 15:37:11.542212 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5844 15:37:11.545843 == TX Byte 1 ==
5845 15:37:11.549402 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5846 15:37:11.552336 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5847 15:37:11.555837 ==
5848 15:37:11.555954 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 15:37:11.562665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 15:37:11.562783 ==
5851 15:37:11.562881
5852 15:37:11.562978
5853 15:37:11.565802 TX Vref Scan disable
5854 15:37:11.565906 == TX Byte 0 ==
5855 15:37:11.572314 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5856 15:37:11.575928 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5857 15:37:11.576015 == TX Byte 1 ==
5858 15:37:11.582537 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5859 15:37:11.585704 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5860 15:37:11.585795
5861 15:37:11.585864 [DATLAT]
5862 15:37:11.588948 Freq=933, CH1 RK1
5863 15:37:11.589031
5864 15:37:11.589097 DATLAT Default: 0xb
5865 15:37:11.592246 0, 0xFFFF, sum = 0
5866 15:37:11.592324 1, 0xFFFF, sum = 0
5867 15:37:11.595496 2, 0xFFFF, sum = 0
5868 15:37:11.595617 3, 0xFFFF, sum = 0
5869 15:37:11.598796 4, 0xFFFF, sum = 0
5870 15:37:11.598897 5, 0xFFFF, sum = 0
5871 15:37:11.602702 6, 0xFFFF, sum = 0
5872 15:37:11.602809 7, 0xFFFF, sum = 0
5873 15:37:11.605895 8, 0xFFFF, sum = 0
5874 15:37:11.605971 9, 0xFFFF, sum = 0
5875 15:37:11.609179 10, 0x0, sum = 1
5876 15:37:11.609291 11, 0x0, sum = 2
5877 15:37:11.612417 12, 0x0, sum = 3
5878 15:37:11.612516 13, 0x0, sum = 4
5879 15:37:11.615571 best_step = 11
5880 15:37:11.615661
5881 15:37:11.615723 ==
5882 15:37:11.618780 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 15:37:11.622512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 15:37:11.622635 ==
5885 15:37:11.625519 RX Vref Scan: 0
5886 15:37:11.625631
5887 15:37:11.625724 RX Vref 0 -> 0, step: 1
5888 15:37:11.625824
5889 15:37:11.629170 RX Delay -45 -> 252, step: 4
5890 15:37:11.635479 iDelay=199, Bit 0, Center 108 (27 ~ 190) 164
5891 15:37:11.639257 iDelay=199, Bit 1, Center 98 (15 ~ 182) 168
5892 15:37:11.642339 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5893 15:37:11.645644 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5894 15:37:11.648940 iDelay=199, Bit 4, Center 100 (19 ~ 182) 164
5895 15:37:11.655383 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5896 15:37:11.658762 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5897 15:37:11.662347 iDelay=199, Bit 7, Center 102 (19 ~ 186) 168
5898 15:37:11.665322 iDelay=199, Bit 8, Center 92 (11 ~ 174) 164
5899 15:37:11.668662 iDelay=199, Bit 9, Center 90 (3 ~ 178) 176
5900 15:37:11.675888 iDelay=199, Bit 10, Center 100 (15 ~ 186) 172
5901 15:37:11.679131 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5902 15:37:11.682237 iDelay=199, Bit 12, Center 110 (23 ~ 198) 176
5903 15:37:11.685065 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5904 15:37:11.688928 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5905 15:37:11.695017 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5906 15:37:11.695102 ==
5907 15:37:11.698859 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 15:37:11.702081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 15:37:11.702184 ==
5910 15:37:11.702279 DQS Delay:
5911 15:37:11.705382 DQS0 = 0, DQS1 = 0
5912 15:37:11.705486 DQM Delay:
5913 15:37:11.708512 DQM0 = 103, DQM1 = 100
5914 15:37:11.708587 DQ Delay:
5915 15:37:11.711753 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5916 15:37:11.714929 DQ4 =100, DQ5 =116, DQ6 =112, DQ7 =102
5917 15:37:11.718308 DQ8 =92, DQ9 =90, DQ10 =100, DQ11 =94
5918 15:37:11.722171 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5919 15:37:11.722279
5920 15:37:11.722371
5921 15:37:11.731729 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5922 15:37:11.735417 CH1 RK1: MR19=505, MR18=2F02
5923 15:37:11.738291 CH1_RK1: MR19=0x505, MR18=0x2F02, DQSOSC=407, MR23=63, INC=65, DEC=43
5924 15:37:11.741930 [RxdqsGatingPostProcess] freq 933
5925 15:37:11.748426 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5926 15:37:11.751675 best DQS0 dly(2T, 0.5T) = (0, 10)
5927 15:37:11.754932 best DQS1 dly(2T, 0.5T) = (0, 10)
5928 15:37:11.758169 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5929 15:37:11.761895 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5930 15:37:11.765130 best DQS0 dly(2T, 0.5T) = (0, 10)
5931 15:37:11.768313 best DQS1 dly(2T, 0.5T) = (0, 10)
5932 15:37:11.771510 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5933 15:37:11.775168 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5934 15:37:11.778542 Pre-setting of DQS Precalculation
5935 15:37:11.781320 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5936 15:37:11.788162 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5937 15:37:11.795359 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5938 15:37:11.795478
5939 15:37:11.795588
5940 15:37:11.798489 [Calibration Summary] 1866 Mbps
5941 15:37:11.802124 CH 0, Rank 0
5942 15:37:11.802248 SW Impedance : PASS
5943 15:37:11.805245 DUTY Scan : NO K
5944 15:37:11.808460 ZQ Calibration : PASS
5945 15:37:11.808572 Jitter Meter : NO K
5946 15:37:11.811759 CBT Training : PASS
5947 15:37:11.814919 Write leveling : PASS
5948 15:37:11.815035 RX DQS gating : PASS
5949 15:37:11.818196 RX DQ/DQS(RDDQC) : PASS
5950 15:37:11.821396 TX DQ/DQS : PASS
5951 15:37:11.821496 RX DATLAT : PASS
5952 15:37:11.824619 RX DQ/DQS(Engine): PASS
5953 15:37:11.824692 TX OE : NO K
5954 15:37:11.828516 All Pass.
5955 15:37:11.828628
5956 15:37:11.828729 CH 0, Rank 1
5957 15:37:11.831782 SW Impedance : PASS
5958 15:37:11.831893 DUTY Scan : NO K
5959 15:37:11.834925 ZQ Calibration : PASS
5960 15:37:11.838114 Jitter Meter : NO K
5961 15:37:11.838201 CBT Training : PASS
5962 15:37:11.841374 Write leveling : PASS
5963 15:37:11.844580 RX DQS gating : PASS
5964 15:37:11.844691 RX DQ/DQS(RDDQC) : PASS
5965 15:37:11.848287 TX DQ/DQS : PASS
5966 15:37:11.851398 RX DATLAT : PASS
5967 15:37:11.851503 RX DQ/DQS(Engine): PASS
5968 15:37:11.854920 TX OE : NO K
5969 15:37:11.855031 All Pass.
5970 15:37:11.855122
5971 15:37:11.857959 CH 1, Rank 0
5972 15:37:11.858061 SW Impedance : PASS
5973 15:37:11.861520 DUTY Scan : NO K
5974 15:37:11.864677 ZQ Calibration : PASS
5975 15:37:11.864768 Jitter Meter : NO K
5976 15:37:11.867990 CBT Training : PASS
5977 15:37:11.871130 Write leveling : PASS
5978 15:37:11.871244 RX DQS gating : PASS
5979 15:37:11.875001 RX DQ/DQS(RDDQC) : PASS
5980 15:37:11.875110 TX DQ/DQS : PASS
5981 15:37:11.878123 RX DATLAT : PASS
5982 15:37:11.881284 RX DQ/DQS(Engine): PASS
5983 15:37:11.881384 TX OE : NO K
5984 15:37:11.884893 All Pass.
5985 15:37:11.884997
5986 15:37:11.885093 CH 1, Rank 1
5987 15:37:11.888284 SW Impedance : PASS
5988 15:37:11.888399 DUTY Scan : NO K
5989 15:37:11.891736 ZQ Calibration : PASS
5990 15:37:11.894941 Jitter Meter : NO K
5991 15:37:11.895043 CBT Training : PASS
5992 15:37:11.897951 Write leveling : PASS
5993 15:37:11.901631 RX DQS gating : PASS
5994 15:37:11.901743 RX DQ/DQS(RDDQC) : PASS
5995 15:37:11.904967 TX DQ/DQS : PASS
5996 15:37:11.907896 RX DATLAT : PASS
5997 15:37:11.907983 RX DQ/DQS(Engine): PASS
5998 15:37:11.911315 TX OE : NO K
5999 15:37:11.911391 All Pass.
6000 15:37:11.911460
6001 15:37:11.914419 DramC Write-DBI off
6002 15:37:11.918346 PER_BANK_REFRESH: Hybrid Mode
6003 15:37:11.918421 TX_TRACKING: ON
6004 15:37:11.928020 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6005 15:37:11.931233 [FAST_K] Save calibration result to emmc
6006 15:37:11.934509 dramc_set_vcore_voltage set vcore to 650000
6007 15:37:11.937755 Read voltage for 400, 6
6008 15:37:11.937830 Vio18 = 0
6009 15:37:11.937893 Vcore = 650000
6010 15:37:11.941064 Vdram = 0
6011 15:37:11.941142 Vddq = 0
6012 15:37:11.941210 Vmddr = 0
6013 15:37:11.947984 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6014 15:37:11.951274 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6015 15:37:11.954534 MEM_TYPE=3, freq_sel=20
6016 15:37:11.957846 sv_algorithm_assistance_LP4_800
6017 15:37:11.961526 ============ PULL DRAM RESETB DOWN ============
6018 15:37:11.964545 ========== PULL DRAM RESETB DOWN end =========
6019 15:37:11.971082 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6020 15:37:11.974719 ===================================
6021 15:37:11.974797 LPDDR4 DRAM CONFIGURATION
6022 15:37:11.977841 ===================================
6023 15:37:11.981670 EX_ROW_EN[0] = 0x0
6024 15:37:11.981748 EX_ROW_EN[1] = 0x0
6025 15:37:11.984921 LP4Y_EN = 0x0
6026 15:37:11.985026 WORK_FSP = 0x0
6027 15:37:11.988123 WL = 0x2
6028 15:37:11.991514 RL = 0x2
6029 15:37:11.991626 BL = 0x2
6030 15:37:11.994496 RPST = 0x0
6031 15:37:11.994572 RD_PRE = 0x0
6032 15:37:11.997843 WR_PRE = 0x1
6033 15:37:11.997919 WR_PST = 0x0
6034 15:37:12.001205 DBI_WR = 0x0
6035 15:37:12.001310 DBI_RD = 0x0
6036 15:37:12.004924 OTF = 0x1
6037 15:37:12.008073 ===================================
6038 15:37:12.011300 ===================================
6039 15:37:12.011403 ANA top config
6040 15:37:12.014368 ===================================
6041 15:37:12.018006 DLL_ASYNC_EN = 0
6042 15:37:12.021296 ALL_SLAVE_EN = 1
6043 15:37:12.021375 NEW_RANK_MODE = 1
6044 15:37:12.024718 DLL_IDLE_MODE = 1
6045 15:37:12.027721 LP45_APHY_COMB_EN = 1
6046 15:37:12.031019 TX_ODT_DIS = 1
6047 15:37:12.034309 NEW_8X_MODE = 1
6048 15:37:12.037626 ===================================
6049 15:37:12.040910 ===================================
6050 15:37:12.041014 data_rate = 800
6051 15:37:12.044135 CKR = 1
6052 15:37:12.047227 DQ_P2S_RATIO = 4
6053 15:37:12.051015 ===================================
6054 15:37:12.054419 CA_P2S_RATIO = 4
6055 15:37:12.057549 DQ_CA_OPEN = 0
6056 15:37:12.060734 DQ_SEMI_OPEN = 1
6057 15:37:12.060812 CA_SEMI_OPEN = 1
6058 15:37:12.063944 CA_FULL_RATE = 0
6059 15:37:12.067174 DQ_CKDIV4_EN = 0
6060 15:37:12.070960 CA_CKDIV4_EN = 1
6061 15:37:12.074063 CA_PREDIV_EN = 0
6062 15:37:12.077763 PH8_DLY = 0
6063 15:37:12.077838 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6064 15:37:12.080753 DQ_AAMCK_DIV = 0
6065 15:37:12.084441 CA_AAMCK_DIV = 0
6066 15:37:12.087453 CA_ADMCK_DIV = 4
6067 15:37:12.090885 DQ_TRACK_CA_EN = 0
6068 15:37:12.094106 CA_PICK = 800
6069 15:37:12.094211 CA_MCKIO = 400
6070 15:37:12.097343 MCKIO_SEMI = 400
6071 15:37:12.100545 PLL_FREQ = 3016
6072 15:37:12.104249 DQ_UI_PI_RATIO = 32
6073 15:37:12.107112 CA_UI_PI_RATIO = 32
6074 15:37:12.110805 ===================================
6075 15:37:12.113972 ===================================
6076 15:37:12.117243 memory_type:LPDDR4
6077 15:37:12.117348 GP_NUM : 10
6078 15:37:12.120438 SRAM_EN : 1
6079 15:37:12.123660 MD32_EN : 0
6080 15:37:12.127311 ===================================
6081 15:37:12.127409 [ANA_INIT] >>>>>>>>>>>>>>
6082 15:37:12.130228 <<<<<< [CONFIGURE PHASE]: ANA_TX
6083 15:37:12.133652 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6084 15:37:12.137049 ===================================
6085 15:37:12.140521 data_rate = 800,PCW = 0X7400
6086 15:37:12.143846 ===================================
6087 15:37:12.147100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6088 15:37:12.153381 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6089 15:37:12.163717 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 15:37:12.170184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6091 15:37:12.173372 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6092 15:37:12.177211 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6093 15:37:12.177317 [ANA_INIT] flow start
6094 15:37:12.179980 [ANA_INIT] PLL >>>>>>>>
6095 15:37:12.183602 [ANA_INIT] PLL <<<<<<<<
6096 15:37:12.183684 [ANA_INIT] MIDPI >>>>>>>>
6097 15:37:12.186774 [ANA_INIT] MIDPI <<<<<<<<
6098 15:37:12.190632 [ANA_INIT] DLL >>>>>>>>
6099 15:37:12.190737 [ANA_INIT] flow end
6100 15:37:12.193750 ============ LP4 DIFF to SE enter ============
6101 15:37:12.200435 ============ LP4 DIFF to SE exit ============
6102 15:37:12.200516 [ANA_INIT] <<<<<<<<<<<<<
6103 15:37:12.203670 [Flow] Enable top DCM control >>>>>
6104 15:37:12.207041 [Flow] Enable top DCM control <<<<<
6105 15:37:12.210129 Enable DLL master slave shuffle
6106 15:37:12.217257 ==============================================================
6107 15:37:12.217361 Gating Mode config
6108 15:37:12.223609 ==============================================================
6109 15:37:12.226907 Config description:
6110 15:37:12.236735 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6111 15:37:12.243632 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6112 15:37:12.247247 SELPH_MODE 0: By rank 1: By Phase
6113 15:37:12.253323 ==============================================================
6114 15:37:12.257025 GAT_TRACK_EN = 0
6115 15:37:12.260238 RX_GATING_MODE = 2
6116 15:37:12.260334 RX_GATING_TRACK_MODE = 2
6117 15:37:12.263479 SELPH_MODE = 1
6118 15:37:12.266769 PICG_EARLY_EN = 1
6119 15:37:12.270055 VALID_LAT_VALUE = 1
6120 15:37:12.276583 ==============================================================
6121 15:37:12.279693 Enter into Gating configuration >>>>
6122 15:37:12.283632 Exit from Gating configuration <<<<
6123 15:37:12.287054 Enter into DVFS_PRE_config >>>>>
6124 15:37:12.296540 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6125 15:37:12.299749 Exit from DVFS_PRE_config <<<<<
6126 15:37:12.303462 Enter into PICG configuration >>>>
6127 15:37:12.306662 Exit from PICG configuration <<<<
6128 15:37:12.309934 [RX_INPUT] configuration >>>>>
6129 15:37:12.313218 [RX_INPUT] configuration <<<<<
6130 15:37:12.316512 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6131 15:37:12.323205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6132 15:37:12.329837 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6133 15:37:12.336416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6134 15:37:12.339738 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6135 15:37:12.346220 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6136 15:37:12.349593 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6137 15:37:12.356627 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6138 15:37:12.359713 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6139 15:37:12.362900 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6140 15:37:12.366469 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6141 15:37:12.373277 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6142 15:37:12.376310 ===================================
6143 15:37:12.376411 LPDDR4 DRAM CONFIGURATION
6144 15:37:12.379611 ===================================
6145 15:37:12.383244 EX_ROW_EN[0] = 0x0
6146 15:37:12.386452 EX_ROW_EN[1] = 0x0
6147 15:37:12.386561 LP4Y_EN = 0x0
6148 15:37:12.389925 WORK_FSP = 0x0
6149 15:37:12.390027 WL = 0x2
6150 15:37:12.392977 RL = 0x2
6151 15:37:12.393089 BL = 0x2
6152 15:37:12.396215 RPST = 0x0
6153 15:37:12.396290 RD_PRE = 0x0
6154 15:37:12.399500 WR_PRE = 0x1
6155 15:37:12.399614 WR_PST = 0x0
6156 15:37:12.402815 DBI_WR = 0x0
6157 15:37:12.402897 DBI_RD = 0x0
6158 15:37:12.405946 OTF = 0x1
6159 15:37:12.409699 ===================================
6160 15:37:12.412751 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6161 15:37:12.416059 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6162 15:37:12.422568 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6163 15:37:12.425907 ===================================
6164 15:37:12.425989 LPDDR4 DRAM CONFIGURATION
6165 15:37:12.429548 ===================================
6166 15:37:12.432620 EX_ROW_EN[0] = 0x10
6167 15:37:12.432696 EX_ROW_EN[1] = 0x0
6168 15:37:12.436411 LP4Y_EN = 0x0
6169 15:37:12.439466 WORK_FSP = 0x0
6170 15:37:12.439550 WL = 0x2
6171 15:37:12.442724 RL = 0x2
6172 15:37:12.442798 BL = 0x2
6173 15:37:12.446115 RPST = 0x0
6174 15:37:12.446190 RD_PRE = 0x0
6175 15:37:12.449299 WR_PRE = 0x1
6176 15:37:12.449378 WR_PST = 0x0
6177 15:37:12.452618 DBI_WR = 0x0
6178 15:37:12.452727 DBI_RD = 0x0
6179 15:37:12.456408 OTF = 0x1
6180 15:37:12.459538 ===================================
6181 15:37:12.466072 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6182 15:37:12.469371 nWR fixed to 30
6183 15:37:12.469469 [ModeRegInit_LP4] CH0 RK0
6184 15:37:12.472786 [ModeRegInit_LP4] CH0 RK1
6185 15:37:12.476126 [ModeRegInit_LP4] CH1 RK0
6186 15:37:12.476232 [ModeRegInit_LP4] CH1 RK1
6187 15:37:12.479202 match AC timing 19
6188 15:37:12.482592 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6189 15:37:12.485949 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6190 15:37:12.492414 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6191 15:37:12.495684 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6192 15:37:12.502341 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6193 15:37:12.502425 ==
6194 15:37:12.506185 Dram Type= 6, Freq= 0, CH_0, rank 0
6195 15:37:12.509510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6196 15:37:12.509589 ==
6197 15:37:12.515875 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6198 15:37:12.519487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6199 15:37:12.522781 [CA 0] Center 36 (8~64) winsize 57
6200 15:37:12.526038 [CA 1] Center 36 (8~64) winsize 57
6201 15:37:12.529185 [CA 2] Center 36 (8~64) winsize 57
6202 15:37:12.532452 [CA 3] Center 36 (8~64) winsize 57
6203 15:37:12.535862 [CA 4] Center 36 (8~64) winsize 57
6204 15:37:12.538798 [CA 5] Center 36 (8~64) winsize 57
6205 15:37:12.538902
6206 15:37:12.542467 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6207 15:37:12.542572
6208 15:37:12.545740 [CATrainingPosCal] consider 1 rank data
6209 15:37:12.548845 u2DelayCellTimex100 = 270/100 ps
6210 15:37:12.552225 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 15:37:12.555407 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 15:37:12.562421 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 15:37:12.565789 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 15:37:12.568947 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 15:37:12.572201 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 15:37:12.572291
6217 15:37:12.575600 CA PerBit enable=1, Macro0, CA PI delay=36
6218 15:37:12.575676
6219 15:37:12.579118 [CBTSetCACLKResult] CA Dly = 36
6220 15:37:12.579203 CS Dly: 1 (0~32)
6221 15:37:12.579267 ==
6222 15:37:12.582413 Dram Type= 6, Freq= 0, CH_0, rank 1
6223 15:37:12.588970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6224 15:37:12.589090 ==
6225 15:37:12.592233 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6226 15:37:12.598906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6227 15:37:12.602076 [CA 0] Center 36 (8~64) winsize 57
6228 15:37:12.605539 [CA 1] Center 36 (8~64) winsize 57
6229 15:37:12.608450 [CA 2] Center 36 (8~64) winsize 57
6230 15:37:12.611913 [CA 3] Center 36 (8~64) winsize 57
6231 15:37:12.615127 [CA 4] Center 36 (8~64) winsize 57
6232 15:37:12.618422 [CA 5] Center 36 (8~64) winsize 57
6233 15:37:12.618505
6234 15:37:12.621835 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6235 15:37:12.621921
6236 15:37:12.625624 [CATrainingPosCal] consider 2 rank data
6237 15:37:12.628829 u2DelayCellTimex100 = 270/100 ps
6238 15:37:12.632137 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 15:37:12.635383 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 15:37:12.638706 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 15:37:12.641840 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 15:37:12.645070 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 15:37:12.651587 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 15:37:12.651711
6245 15:37:12.655457 CA PerBit enable=1, Macro0, CA PI delay=36
6246 15:37:12.655567
6247 15:37:12.658701 [CBTSetCACLKResult] CA Dly = 36
6248 15:37:12.658776 CS Dly: 1 (0~32)
6249 15:37:12.658838
6250 15:37:12.662091 ----->DramcWriteLeveling(PI) begin...
6251 15:37:12.662203 ==
6252 15:37:12.665325 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 15:37:12.668896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 15:37:12.672068 ==
6255 15:37:12.672147 Write leveling (Byte 0): 40 => 8
6256 15:37:12.675377 Write leveling (Byte 1): 40 => 8
6257 15:37:12.678468 DramcWriteLeveling(PI) end<-----
6258 15:37:12.678544
6259 15:37:12.678613 ==
6260 15:37:12.681901 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 15:37:12.685160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 15:37:12.688427 ==
6263 15:37:12.688514 [Gating] SW mode calibration
6264 15:37:12.698658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6265 15:37:12.701796 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6266 15:37:12.705806 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 15:37:12.712346 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 15:37:12.715560 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 15:37:12.718763 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 15:37:12.724984 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 15:37:12.728579 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 15:37:12.731799 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 15:37:12.738467 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 15:37:12.742032 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 15:37:12.745475 Total UI for P1: 0, mck2ui 16
6276 15:37:12.748389 best dqsien dly found for B0: ( 0, 14, 24)
6277 15:37:12.751784 Total UI for P1: 0, mck2ui 16
6278 15:37:12.755463 best dqsien dly found for B1: ( 0, 14, 24)
6279 15:37:12.758651 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6280 15:37:12.761831 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6281 15:37:12.761930
6282 15:37:12.765167 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6283 15:37:12.768380 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 15:37:12.771581 [Gating] SW calibration Done
6285 15:37:12.771664 ==
6286 15:37:12.775084 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 15:37:12.778208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 15:37:12.781964 ==
6289 15:37:12.782066 RX Vref Scan: 0
6290 15:37:12.782179
6291 15:37:12.785262 RX Vref 0 -> 0, step: 1
6292 15:37:12.785380
6293 15:37:12.788455 RX Delay -410 -> 252, step: 16
6294 15:37:12.791852 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6295 15:37:12.794933 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6296 15:37:12.798694 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6297 15:37:12.805095 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6298 15:37:12.808336 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6299 15:37:12.811520 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6300 15:37:12.814839 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6301 15:37:12.821932 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6302 15:37:12.825236 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6303 15:37:12.828622 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6304 15:37:12.831438 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6305 15:37:12.838300 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6306 15:37:12.841370 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6307 15:37:12.845103 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6308 15:37:12.848146 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6309 15:37:12.854879 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6310 15:37:12.854962 ==
6311 15:37:12.858315 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 15:37:12.861618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 15:37:12.861721 ==
6314 15:37:12.861840 DQS Delay:
6315 15:37:12.864645 DQS0 = 27, DQS1 = 35
6316 15:37:12.864737 DQM Delay:
6317 15:37:12.868019 DQM0 = 10, DQM1 = 12
6318 15:37:12.868116 DQ Delay:
6319 15:37:12.871376 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6320 15:37:12.874888 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6321 15:37:12.877960 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6322 15:37:12.881269 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6323 15:37:12.881361
6324 15:37:12.881422
6325 15:37:12.881479 ==
6326 15:37:12.884523 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 15:37:12.887815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 15:37:12.887891 ==
6329 15:37:12.887965
6330 15:37:12.888030
6331 15:37:12.891720 TX Vref Scan disable
6332 15:37:12.895062 == TX Byte 0 ==
6333 15:37:12.898385 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6334 15:37:12.901634 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6335 15:37:12.901734 == TX Byte 1 ==
6336 15:37:12.908223 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6337 15:37:12.911437 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6338 15:37:12.911544 ==
6339 15:37:12.914571 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 15:37:12.917972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 15:37:12.918047 ==
6342 15:37:12.918138
6343 15:37:12.921180
6344 15:37:12.921270 TX Vref Scan disable
6345 15:37:12.924551 == TX Byte 0 ==
6346 15:37:12.927901 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 15:37:12.931227 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 15:37:12.934688 == TX Byte 1 ==
6349 15:37:12.937780 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6350 15:37:12.941587 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6351 15:37:12.941666
6352 15:37:12.941729 [DATLAT]
6353 15:37:12.944895 Freq=400, CH0 RK0
6354 15:37:12.944974
6355 15:37:12.945036 DATLAT Default: 0xf
6356 15:37:12.948049 0, 0xFFFF, sum = 0
6357 15:37:12.948129 1, 0xFFFF, sum = 0
6358 15:37:12.951196 2, 0xFFFF, sum = 0
6359 15:37:12.954351 3, 0xFFFF, sum = 0
6360 15:37:12.954431 4, 0xFFFF, sum = 0
6361 15:37:12.958440 5, 0xFFFF, sum = 0
6362 15:37:12.958535 6, 0xFFFF, sum = 0
6363 15:37:12.961501 7, 0xFFFF, sum = 0
6364 15:37:12.961583 8, 0xFFFF, sum = 0
6365 15:37:12.964551 9, 0xFFFF, sum = 0
6366 15:37:12.964649 10, 0xFFFF, sum = 0
6367 15:37:12.967807 11, 0xFFFF, sum = 0
6368 15:37:12.967917 12, 0xFFFF, sum = 0
6369 15:37:12.971087 13, 0x0, sum = 1
6370 15:37:12.971204 14, 0x0, sum = 2
6371 15:37:12.974428 15, 0x0, sum = 3
6372 15:37:12.974510 16, 0x0, sum = 4
6373 15:37:12.974599 best_step = 14
6374 15:37:12.978325
6375 15:37:12.978406 ==
6376 15:37:12.981205 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 15:37:12.984950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 15:37:12.985059 ==
6379 15:37:12.985158 RX Vref Scan: 1
6380 15:37:12.985247
6381 15:37:12.987823 RX Vref 0 -> 0, step: 1
6382 15:37:12.987905
6383 15:37:12.991148 RX Delay -311 -> 252, step: 8
6384 15:37:12.991231
6385 15:37:12.994727 Set Vref, RX VrefLevel [Byte0]: 55
6386 15:37:12.997769 [Byte1]: 46
6387 15:37:13.001847
6388 15:37:13.001931 Final RX Vref Byte 0 = 55 to rank0
6389 15:37:13.005082 Final RX Vref Byte 1 = 46 to rank0
6390 15:37:13.008460 Final RX Vref Byte 0 = 55 to rank1
6391 15:37:13.011939 Final RX Vref Byte 1 = 46 to rank1==
6392 15:37:13.015229 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 15:37:13.021732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 15:37:13.021813 ==
6395 15:37:13.021895 DQS Delay:
6396 15:37:13.024986 DQS0 = 28, DQS1 = 36
6397 15:37:13.025061 DQM Delay:
6398 15:37:13.025122 DQM0 = 10, DQM1 = 13
6399 15:37:13.028343 DQ Delay:
6400 15:37:13.031576 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6401 15:37:13.034810 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6402 15:37:13.034886 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6403 15:37:13.038160 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6404 15:37:13.041187
6405 15:37:13.041267
6406 15:37:13.048468 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6407 15:37:13.051060 CH0 RK0: MR19=C0C, MR18=CDBA
6408 15:37:13.057971 CH0_RK0: MR19=0xC0C, MR18=0xCDBA, DQSOSC=384, MR23=63, INC=400, DEC=267
6409 15:37:13.058059 ==
6410 15:37:13.061233 Dram Type= 6, Freq= 0, CH_0, rank 1
6411 15:37:13.064582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 15:37:13.064665 ==
6413 15:37:13.067747 [Gating] SW mode calibration
6414 15:37:13.074531 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6415 15:37:13.080947 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6416 15:37:13.084147 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6417 15:37:13.087893 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 15:37:13.094502 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 15:37:13.097750 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 15:37:13.100872 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 15:37:13.107587 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 15:37:13.110687 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 15:37:13.114282 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 15:37:13.120586 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 15:37:13.120672 Total UI for P1: 0, mck2ui 16
6426 15:37:13.124517 best dqsien dly found for B0: ( 0, 14, 24)
6427 15:37:13.127945 Total UI for P1: 0, mck2ui 16
6428 15:37:13.130649 best dqsien dly found for B1: ( 0, 14, 24)
6429 15:37:13.134598 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6430 15:37:13.141153 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6431 15:37:13.141237
6432 15:37:13.144091 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6433 15:37:13.147748 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 15:37:13.150988 [Gating] SW calibration Done
6435 15:37:13.151072 ==
6436 15:37:13.154224 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 15:37:13.157508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 15:37:13.157620 ==
6439 15:37:13.161220 RX Vref Scan: 0
6440 15:37:13.161322
6441 15:37:13.161413 RX Vref 0 -> 0, step: 1
6442 15:37:13.161501
6443 15:37:13.164277 RX Delay -410 -> 252, step: 16
6444 15:37:13.167636 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6445 15:37:13.174145 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6446 15:37:13.177299 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6447 15:37:13.180568 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6448 15:37:13.184321 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6449 15:37:13.190623 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6450 15:37:13.194511 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6451 15:37:13.197116 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6452 15:37:13.200696 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6453 15:37:13.207255 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6454 15:37:13.210526 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6455 15:37:13.213922 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6456 15:37:13.217200 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6457 15:37:13.223857 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6458 15:37:13.227228 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6459 15:37:13.230821 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6460 15:37:13.230901 ==
6461 15:37:13.233701 Dram Type= 6, Freq= 0, CH_0, rank 1
6462 15:37:13.240825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 15:37:13.240908 ==
6464 15:37:13.240972 DQS Delay:
6465 15:37:13.244034 DQS0 = 27, DQS1 = 35
6466 15:37:13.244106 DQM Delay:
6467 15:37:13.244166 DQM0 = 12, DQM1 = 12
6468 15:37:13.247613 DQ Delay:
6469 15:37:13.250685 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6470 15:37:13.250792 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6471 15:37:13.253984 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6472 15:37:13.257205 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6473 15:37:13.257291
6474 15:37:13.257389
6475 15:37:13.260387 ==
6476 15:37:13.263651 Dram Type= 6, Freq= 0, CH_0, rank 1
6477 15:37:13.267456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 15:37:13.267569 ==
6479 15:37:13.267672
6480 15:37:13.267760
6481 15:37:13.270668 TX Vref Scan disable
6482 15:37:13.270757 == TX Byte 0 ==
6483 15:37:13.273812 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6484 15:37:13.280916 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6485 15:37:13.281019 == TX Byte 1 ==
6486 15:37:13.284185 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6487 15:37:13.287273 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6488 15:37:13.290550 ==
6489 15:37:13.294207 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 15:37:13.297147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 15:37:13.297230 ==
6492 15:37:13.297295
6493 15:37:13.297354
6494 15:37:13.300580 TX Vref Scan disable
6495 15:37:13.300671 == TX Byte 0 ==
6496 15:37:13.303955 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6497 15:37:13.310396 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6498 15:37:13.310500 == TX Byte 1 ==
6499 15:37:13.313762 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6500 15:37:13.320400 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6501 15:37:13.320510
6502 15:37:13.320587 [DATLAT]
6503 15:37:13.320683 Freq=400, CH0 RK1
6504 15:37:13.320772
6505 15:37:13.323721 DATLAT Default: 0xe
6506 15:37:13.323828 0, 0xFFFF, sum = 0
6507 15:37:13.326991 1, 0xFFFF, sum = 0
6508 15:37:13.327077 2, 0xFFFF, sum = 0
6509 15:37:13.330207 3, 0xFFFF, sum = 0
6510 15:37:13.333328 4, 0xFFFF, sum = 0
6511 15:37:13.333441 5, 0xFFFF, sum = 0
6512 15:37:13.336906 6, 0xFFFF, sum = 0
6513 15:37:13.336989 7, 0xFFFF, sum = 0
6514 15:37:13.340093 8, 0xFFFF, sum = 0
6515 15:37:13.340184 9, 0xFFFF, sum = 0
6516 15:37:13.343130 10, 0xFFFF, sum = 0
6517 15:37:13.343213 11, 0xFFFF, sum = 0
6518 15:37:13.346640 12, 0xFFFF, sum = 0
6519 15:37:13.346746 13, 0x0, sum = 1
6520 15:37:13.349820 14, 0x0, sum = 2
6521 15:37:13.349903 15, 0x0, sum = 3
6522 15:37:13.353685 16, 0x0, sum = 4
6523 15:37:13.353804 best_step = 14
6524 15:37:13.353902
6525 15:37:13.354004 ==
6526 15:37:13.356732 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 15:37:13.359996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 15:37:13.363176 ==
6529 15:37:13.363284 RX Vref Scan: 0
6530 15:37:13.363381
6531 15:37:13.366501 RX Vref 0 -> 0, step: 1
6532 15:37:13.366609
6533 15:37:13.369906 RX Delay -311 -> 252, step: 8
6534 15:37:13.376189 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6535 15:37:13.380116 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6536 15:37:13.383326 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6537 15:37:13.386467 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6538 15:37:13.392682 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6539 15:37:13.396635 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6540 15:37:13.399537 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6541 15:37:13.402573 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6542 15:37:13.409186 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6543 15:37:13.413103 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6544 15:37:13.416298 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6545 15:37:13.419535 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6546 15:37:13.426089 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6547 15:37:13.429336 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6548 15:37:13.432687 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6549 15:37:13.436049 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6550 15:37:13.439164 ==
6551 15:37:13.439276 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 15:37:13.445782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 15:37:13.445887 ==
6554 15:37:13.445979 DQS Delay:
6555 15:37:13.448941 DQS0 = 24, DQS1 = 36
6556 15:37:13.449044 DQM Delay:
6557 15:37:13.452777 DQM0 = 8, DQM1 = 13
6558 15:37:13.452884 DQ Delay:
6559 15:37:13.455908 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6560 15:37:13.458808 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6561 15:37:13.462300 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6562 15:37:13.465878 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6563 15:37:13.465953
6564 15:37:13.466016
6565 15:37:13.472443 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6566 15:37:13.475886 CH0 RK1: MR19=C0C, MR18=BD5D
6567 15:37:13.482461 CH0_RK1: MR19=0xC0C, MR18=0xBD5D, DQSOSC=386, MR23=63, INC=396, DEC=264
6568 15:37:13.485800 [RxdqsGatingPostProcess] freq 400
6569 15:37:13.488498 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6570 15:37:13.492211 best DQS0 dly(2T, 0.5T) = (0, 10)
6571 15:37:13.495856 best DQS1 dly(2T, 0.5T) = (0, 10)
6572 15:37:13.498856 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6573 15:37:13.502126 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6574 15:37:13.505318 best DQS0 dly(2T, 0.5T) = (0, 10)
6575 15:37:13.508347 best DQS1 dly(2T, 0.5T) = (0, 10)
6576 15:37:13.512203 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6577 15:37:13.515439 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6578 15:37:13.518686 Pre-setting of DQS Precalculation
6579 15:37:13.521990 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6580 15:37:13.525376 ==
6581 15:37:13.525453 Dram Type= 6, Freq= 0, CH_1, rank 0
6582 15:37:13.531822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 15:37:13.531899 ==
6584 15:37:13.535072 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6585 15:37:13.542084 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6586 15:37:13.545204 [CA 0] Center 36 (8~64) winsize 57
6587 15:37:13.548554 [CA 1] Center 36 (8~64) winsize 57
6588 15:37:13.551868 [CA 2] Center 36 (8~64) winsize 57
6589 15:37:13.555217 [CA 3] Center 36 (8~64) winsize 57
6590 15:37:13.558462 [CA 4] Center 36 (8~64) winsize 57
6591 15:37:13.561758 [CA 5] Center 36 (8~64) winsize 57
6592 15:37:13.561836
6593 15:37:13.564974 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6594 15:37:13.565087
6595 15:37:13.568890 [CATrainingPosCal] consider 1 rank data
6596 15:37:13.572269 u2DelayCellTimex100 = 270/100 ps
6597 15:37:13.575214 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 15:37:13.578583 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 15:37:13.581644 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 15:37:13.585246 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 15:37:13.588275 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 15:37:13.595213 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 15:37:13.595326
6604 15:37:13.598606 CA PerBit enable=1, Macro0, CA PI delay=36
6605 15:37:13.598689
6606 15:37:13.601703 [CBTSetCACLKResult] CA Dly = 36
6607 15:37:13.601785 CS Dly: 1 (0~32)
6608 15:37:13.601865 ==
6609 15:37:13.604723 Dram Type= 6, Freq= 0, CH_1, rank 1
6610 15:37:13.608364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 15:37:13.611937 ==
6612 15:37:13.615162 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6613 15:37:13.621979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6614 15:37:13.625369 [CA 0] Center 36 (8~64) winsize 57
6615 15:37:13.628026 [CA 1] Center 36 (8~64) winsize 57
6616 15:37:13.632062 [CA 2] Center 36 (8~64) winsize 57
6617 15:37:13.635406 [CA 3] Center 36 (8~64) winsize 57
6618 15:37:13.638461 [CA 4] Center 36 (8~64) winsize 57
6619 15:37:13.641774 [CA 5] Center 36 (8~64) winsize 57
6620 15:37:13.641859
6621 15:37:13.645037 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6622 15:37:13.645127
6623 15:37:13.648042 [CATrainingPosCal] consider 2 rank data
6624 15:37:13.651349 u2DelayCellTimex100 = 270/100 ps
6625 15:37:13.654692 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 15:37:13.658015 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 15:37:13.661319 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 15:37:13.664752 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 15:37:13.667953 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 15:37:13.671288 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 15:37:13.671404
6632 15:37:13.675152 CA PerBit enable=1, Macro0, CA PI delay=36
6633 15:37:13.675267
6634 15:37:13.677888 [CBTSetCACLKResult] CA Dly = 36
6635 15:37:13.681720 CS Dly: 1 (0~32)
6636 15:37:13.681834
6637 15:37:13.684901 ----->DramcWriteLeveling(PI) begin...
6638 15:37:13.685003 ==
6639 15:37:13.688022 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 15:37:13.691154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 15:37:13.691256 ==
6642 15:37:13.694960 Write leveling (Byte 0): 40 => 8
6643 15:37:13.697985 Write leveling (Byte 1): 40 => 8
6644 15:37:13.701549 DramcWriteLeveling(PI) end<-----
6645 15:37:13.701625
6646 15:37:13.701687 ==
6647 15:37:13.704439 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 15:37:13.708113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 15:37:13.708190 ==
6650 15:37:13.711466 [Gating] SW mode calibration
6651 15:37:13.718166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6652 15:37:13.724964 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6653 15:37:13.727833 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6654 15:37:13.735023 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 15:37:13.738215 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 15:37:13.741481 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 15:37:13.744728 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 15:37:13.751248 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 15:37:13.754548 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 15:37:13.757987 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 15:37:13.764400 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 15:37:13.768251 Total UI for P1: 0, mck2ui 16
6663 15:37:13.771359 best dqsien dly found for B0: ( 0, 14, 24)
6664 15:37:13.771463 Total UI for P1: 0, mck2ui 16
6665 15:37:13.777900 best dqsien dly found for B1: ( 0, 14, 24)
6666 15:37:13.781126 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6667 15:37:13.784391 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6668 15:37:13.784492
6669 15:37:13.787728 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6670 15:37:13.791536 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 15:37:13.794622 [Gating] SW calibration Done
6672 15:37:13.794723 ==
6673 15:37:13.798091 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 15:37:13.801259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 15:37:13.801343 ==
6676 15:37:13.804584 RX Vref Scan: 0
6677 15:37:13.804661
6678 15:37:13.804725 RX Vref 0 -> 0, step: 1
6679 15:37:13.804784
6680 15:37:13.807832 RX Delay -410 -> 252, step: 16
6681 15:37:13.814867 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6682 15:37:13.817842 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6683 15:37:13.821351 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6684 15:37:13.824307 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6685 15:37:13.831224 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6686 15:37:13.834437 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6687 15:37:13.838118 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6688 15:37:13.841094 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6689 15:37:13.847613 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6690 15:37:13.850987 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6691 15:37:13.855039 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6692 15:37:13.858075 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6693 15:37:13.864134 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6694 15:37:13.867427 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6695 15:37:13.871341 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6696 15:37:13.874008 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6697 15:37:13.877852 ==
6698 15:37:13.881151 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 15:37:13.884399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 15:37:13.884511 ==
6701 15:37:13.884608 DQS Delay:
6702 15:37:13.887685 DQS0 = 35, DQS1 = 35
6703 15:37:13.887765 DQM Delay:
6704 15:37:13.890925 DQM0 = 17, DQM1 = 12
6705 15:37:13.891029 DQ Delay:
6706 15:37:13.894154 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6707 15:37:13.897484 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6708 15:37:13.900569 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6709 15:37:13.903836 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6710 15:37:13.903916
6711 15:37:13.903980
6712 15:37:13.904045 ==
6713 15:37:13.907849 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 15:37:13.910801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 15:37:13.910908 ==
6716 15:37:13.911007
6717 15:37:13.911098
6718 15:37:13.913894 TX Vref Scan disable
6719 15:37:13.913985 == TX Byte 0 ==
6720 15:37:13.920421 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6721 15:37:13.924150 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6722 15:37:13.924246 == TX Byte 1 ==
6723 15:37:13.930599 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6724 15:37:13.933757 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6725 15:37:13.933863 ==
6726 15:37:13.937623 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 15:37:13.940284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 15:37:13.940393 ==
6729 15:37:13.940493
6730 15:37:13.940587
6731 15:37:13.944034 TX Vref Scan disable
6732 15:37:13.944138 == TX Byte 0 ==
6733 15:37:13.950451 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 15:37:13.954077 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 15:37:13.954181 == TX Byte 1 ==
6736 15:37:13.960654 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6737 15:37:13.963778 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6738 15:37:13.963882
6739 15:37:13.963962 [DATLAT]
6740 15:37:13.967211 Freq=400, CH1 RK0
6741 15:37:13.967313
6742 15:37:13.967408 DATLAT Default: 0xf
6743 15:37:13.970974 0, 0xFFFF, sum = 0
6744 15:37:13.971078 1, 0xFFFF, sum = 0
6745 15:37:13.974281 2, 0xFFFF, sum = 0
6746 15:37:13.974356 3, 0xFFFF, sum = 0
6747 15:37:13.977320 4, 0xFFFF, sum = 0
6748 15:37:13.977424 5, 0xFFFF, sum = 0
6749 15:37:13.980514 6, 0xFFFF, sum = 0
6750 15:37:13.980617 7, 0xFFFF, sum = 0
6751 15:37:13.984337 8, 0xFFFF, sum = 0
6752 15:37:13.984439 9, 0xFFFF, sum = 0
6753 15:37:13.987608 10, 0xFFFF, sum = 0
6754 15:37:13.987681 11, 0xFFFF, sum = 0
6755 15:37:13.990852 12, 0xFFFF, sum = 0
6756 15:37:13.990951 13, 0x0, sum = 1
6757 15:37:13.994051 14, 0x0, sum = 2
6758 15:37:13.994152 15, 0x0, sum = 3
6759 15:37:13.997332 16, 0x0, sum = 4
6760 15:37:13.997434 best_step = 14
6761 15:37:13.997525
6762 15:37:13.997611 ==
6763 15:37:14.001155 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 15:37:14.007613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 15:37:14.007693 ==
6766 15:37:14.007755 RX Vref Scan: 1
6767 15:37:14.007818
6768 15:37:14.010882 RX Vref 0 -> 0, step: 1
6769 15:37:14.010965
6770 15:37:14.014142 RX Delay -311 -> 252, step: 8
6771 15:37:14.014249
6772 15:37:14.017328 Set Vref, RX VrefLevel [Byte0]: 53
6773 15:37:14.020649 [Byte1]: 53
6774 15:37:14.020757
6775 15:37:14.024630 Final RX Vref Byte 0 = 53 to rank0
6776 15:37:14.027634 Final RX Vref Byte 1 = 53 to rank0
6777 15:37:14.030710 Final RX Vref Byte 0 = 53 to rank1
6778 15:37:14.034461 Final RX Vref Byte 1 = 53 to rank1==
6779 15:37:14.037515 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 15:37:14.040693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 15:37:14.043864 ==
6782 15:37:14.043935 DQS Delay:
6783 15:37:14.044027 DQS0 = 32, DQS1 = 32
6784 15:37:14.047090 DQM Delay:
6785 15:37:14.047188 DQM0 = 13, DQM1 = 11
6786 15:37:14.051060 DQ Delay:
6787 15:37:14.051165 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6788 15:37:14.054219 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6789 15:37:14.057427 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6790 15:37:14.060631 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6791 15:37:14.060734
6792 15:37:14.060825
6793 15:37:14.070380 [DQSOSCAuto] RK0, (LSB)MR18= 0x92c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6794 15:37:14.073905 CH1 RK0: MR19=C0C, MR18=92C9
6795 15:37:14.080222 CH1_RK0: MR19=0xC0C, MR18=0x92C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6796 15:37:14.080305 ==
6797 15:37:14.083611 Dram Type= 6, Freq= 0, CH_1, rank 1
6798 15:37:14.086915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 15:37:14.087023 ==
6800 15:37:14.090276 [Gating] SW mode calibration
6801 15:37:14.097036 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6802 15:37:14.100446 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6803 15:37:14.107086 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6804 15:37:14.110190 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 15:37:14.114093 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 15:37:14.120046 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 15:37:14.123928 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 15:37:14.127154 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 15:37:14.133600 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 15:37:14.136848 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 15:37:14.140552 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 15:37:14.143758 Total UI for P1: 0, mck2ui 16
6813 15:37:14.146975 best dqsien dly found for B0: ( 0, 14, 24)
6814 15:37:14.150120 Total UI for P1: 0, mck2ui 16
6815 15:37:14.153515 best dqsien dly found for B1: ( 0, 14, 24)
6816 15:37:14.156895 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6817 15:37:14.160198 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6818 15:37:14.160305
6819 15:37:14.166811 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6820 15:37:14.170025 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 15:37:14.173901 [Gating] SW calibration Done
6822 15:37:14.174004 ==
6823 15:37:14.177068 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 15:37:14.180187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 15:37:14.180289 ==
6826 15:37:14.180382 RX Vref Scan: 0
6827 15:37:14.180484
6828 15:37:14.183275 RX Vref 0 -> 0, step: 1
6829 15:37:14.183355
6830 15:37:14.187088 RX Delay -410 -> 252, step: 16
6831 15:37:14.189996 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6832 15:37:14.197009 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6833 15:37:14.200286 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6834 15:37:14.203778 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6835 15:37:14.207155 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6836 15:37:14.213832 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6837 15:37:14.216904 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6838 15:37:14.220037 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6839 15:37:14.223356 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6840 15:37:14.227091 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6841 15:37:14.233467 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6842 15:37:14.236650 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6843 15:37:14.240432 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6844 15:37:14.243646 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6845 15:37:14.250079 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6846 15:37:14.253152 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6847 15:37:14.253257 ==
6848 15:37:14.256377 Dram Type= 6, Freq= 0, CH_1, rank 1
6849 15:37:14.260315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 15:37:14.262978 ==
6851 15:37:14.263051 DQS Delay:
6852 15:37:14.263112 DQS0 = 35, DQS1 = 35
6853 15:37:14.266818 DQM Delay:
6854 15:37:14.266919 DQM0 = 19, DQM1 = 15
6855 15:37:14.269987 DQ Delay:
6856 15:37:14.270090 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6857 15:37:14.273245 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6858 15:37:14.276373 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6859 15:37:14.280174 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6860 15:37:14.280279
6861 15:37:14.280370
6862 15:37:14.283397 ==
6863 15:37:14.286694 Dram Type= 6, Freq= 0, CH_1, rank 1
6864 15:37:14.289975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 15:37:14.290076 ==
6866 15:37:14.290166
6867 15:37:14.290259
6868 15:37:14.293144 TX Vref Scan disable
6869 15:37:14.293218 == TX Byte 0 ==
6870 15:37:14.296352 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6871 15:37:14.302786 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6872 15:37:14.302890 == TX Byte 1 ==
6873 15:37:14.306439 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6874 15:37:14.309641 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6875 15:37:14.312865 ==
6876 15:37:14.316463 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 15:37:14.320114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 15:37:14.320218 ==
6879 15:37:14.320306
6880 15:37:14.320397
6881 15:37:14.323166 TX Vref Scan disable
6882 15:37:14.323261 == TX Byte 0 ==
6883 15:37:14.326090 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6884 15:37:14.332952 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6885 15:37:14.333055 == TX Byte 1 ==
6886 15:37:14.336704 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6887 15:37:14.339658 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6888 15:37:14.343405
6889 15:37:14.343506 [DATLAT]
6890 15:37:14.343602 Freq=400, CH1 RK1
6891 15:37:14.343690
6892 15:37:14.346629 DATLAT Default: 0xe
6893 15:37:14.346727 0, 0xFFFF, sum = 0
6894 15:37:14.349908 1, 0xFFFF, sum = 0
6895 15:37:14.350008 2, 0xFFFF, sum = 0
6896 15:37:14.353093 3, 0xFFFF, sum = 0
6897 15:37:14.353161 4, 0xFFFF, sum = 0
6898 15:37:14.356300 5, 0xFFFF, sum = 0
6899 15:37:14.359478 6, 0xFFFF, sum = 0
6900 15:37:14.359577 7, 0xFFFF, sum = 0
6901 15:37:14.363428 8, 0xFFFF, sum = 0
6902 15:37:14.363527 9, 0xFFFF, sum = 0
6903 15:37:14.366754 10, 0xFFFF, sum = 0
6904 15:37:14.366851 11, 0xFFFF, sum = 0
6905 15:37:14.369949 12, 0xFFFF, sum = 0
6906 15:37:14.370046 13, 0x0, sum = 1
6907 15:37:14.373029 14, 0x0, sum = 2
6908 15:37:14.373102 15, 0x0, sum = 3
6909 15:37:14.376160 16, 0x0, sum = 4
6910 15:37:14.376233 best_step = 14
6911 15:37:14.376293
6912 15:37:14.376350 ==
6913 15:37:14.379985 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 15:37:14.383286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 15:37:14.383393 ==
6916 15:37:14.386505 RX Vref Scan: 0
6917 15:37:14.386608
6918 15:37:14.389723 RX Vref 0 -> 0, step: 1
6919 15:37:14.389828
6920 15:37:14.389933 RX Delay -311 -> 252, step: 8
6921 15:37:14.398176 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6922 15:37:14.401356 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6923 15:37:14.405154 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6924 15:37:14.408180 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6925 15:37:14.414670 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6926 15:37:14.418149 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6927 15:37:14.421166 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6928 15:37:14.424884 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6929 15:37:14.431191 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6930 15:37:14.434569 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6931 15:37:14.438233 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6932 15:37:14.441361 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6933 15:37:14.448005 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6934 15:37:14.451313 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6935 15:37:14.454428 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6936 15:37:14.461247 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6937 15:37:14.461356 ==
6938 15:37:14.464661 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 15:37:14.468325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 15:37:14.468432 ==
6941 15:37:14.468524 DQS Delay:
6942 15:37:14.471499 DQS0 = 28, DQS1 = 36
6943 15:37:14.471610 DQM Delay:
6944 15:37:14.474835 DQM0 = 10, DQM1 = 15
6945 15:37:14.474936 DQ Delay:
6946 15:37:14.477974 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6947 15:37:14.481112 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6948 15:37:14.485002 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6949 15:37:14.488192 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6950 15:37:14.488292
6951 15:37:14.488387
6952 15:37:14.494748 [DQSOSCAuto] RK1, (LSB)MR18= 0xc859, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6953 15:37:14.497931 CH1 RK1: MR19=C0C, MR18=C859
6954 15:37:14.504431 CH1_RK1: MR19=0xC0C, MR18=0xC859, DQSOSC=385, MR23=63, INC=398, DEC=265
6955 15:37:14.507666 [RxdqsGatingPostProcess] freq 400
6956 15:37:14.511084 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6957 15:37:14.514213 best DQS0 dly(2T, 0.5T) = (0, 10)
6958 15:37:14.517973 best DQS1 dly(2T, 0.5T) = (0, 10)
6959 15:37:14.520996 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6960 15:37:14.524579 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6961 15:37:14.527394 best DQS0 dly(2T, 0.5T) = (0, 10)
6962 15:37:14.530886 best DQS1 dly(2T, 0.5T) = (0, 10)
6963 15:37:14.534612 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6964 15:37:14.537734 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6965 15:37:14.540887 Pre-setting of DQS Precalculation
6966 15:37:14.544704 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6967 15:37:14.554338 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6968 15:37:14.561404 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6969 15:37:14.561511
6970 15:37:14.561605
6971 15:37:14.564394 [Calibration Summary] 800 Mbps
6972 15:37:14.564495 CH 0, Rank 0
6973 15:37:14.568148 SW Impedance : PASS
6974 15:37:14.568252 DUTY Scan : NO K
6975 15:37:14.570946 ZQ Calibration : PASS
6976 15:37:14.574404 Jitter Meter : NO K
6977 15:37:14.574505 CBT Training : PASS
6978 15:37:14.577548 Write leveling : PASS
6979 15:37:14.581098 RX DQS gating : PASS
6980 15:37:14.581206 RX DQ/DQS(RDDQC) : PASS
6981 15:37:14.584144 TX DQ/DQS : PASS
6982 15:37:14.587833 RX DATLAT : PASS
6983 15:37:14.587912 RX DQ/DQS(Engine): PASS
6984 15:37:14.591154 TX OE : NO K
6985 15:37:14.591259 All Pass.
6986 15:37:14.591366
6987 15:37:14.594585 CH 0, Rank 1
6988 15:37:14.594694 SW Impedance : PASS
6989 15:37:14.597806 DUTY Scan : NO K
6990 15:37:14.597882 ZQ Calibration : PASS
6991 15:37:14.600978 Jitter Meter : NO K
6992 15:37:14.604190 CBT Training : PASS
6993 15:37:14.604263 Write leveling : NO K
6994 15:37:14.607369 RX DQS gating : PASS
6995 15:37:14.611216 RX DQ/DQS(RDDQC) : PASS
6996 15:37:14.611289 TX DQ/DQS : PASS
6997 15:37:14.614525 RX DATLAT : PASS
6998 15:37:14.617749 RX DQ/DQS(Engine): PASS
6999 15:37:14.617830 TX OE : NO K
7000 15:37:14.620986 All Pass.
7001 15:37:14.621068
7002 15:37:14.621132 CH 1, Rank 0
7003 15:37:14.624172 SW Impedance : PASS
7004 15:37:14.624254 DUTY Scan : NO K
7005 15:37:14.627304 ZQ Calibration : PASS
7006 15:37:14.631110 Jitter Meter : NO K
7007 15:37:14.631218 CBT Training : PASS
7008 15:37:14.634104 Write leveling : PASS
7009 15:37:14.637877 RX DQS gating : PASS
7010 15:37:14.637980 RX DQ/DQS(RDDQC) : PASS
7011 15:37:14.640667 TX DQ/DQS : PASS
7012 15:37:14.640770 RX DATLAT : PASS
7013 15:37:14.644161 RX DQ/DQS(Engine): PASS
7014 15:37:14.647315 TX OE : NO K
7015 15:37:14.647419 All Pass.
7016 15:37:14.647511
7017 15:37:14.647613 CH 1, Rank 1
7018 15:37:14.650578 SW Impedance : PASS
7019 15:37:14.654578 DUTY Scan : NO K
7020 15:37:14.654683 ZQ Calibration : PASS
7021 15:37:14.657709 Jitter Meter : NO K
7022 15:37:14.660861 CBT Training : PASS
7023 15:37:14.660963 Write leveling : NO K
7024 15:37:14.664212 RX DQS gating : PASS
7025 15:37:14.667550 RX DQ/DQS(RDDQC) : PASS
7026 15:37:14.667666 TX DQ/DQS : PASS
7027 15:37:14.670870 RX DATLAT : PASS
7028 15:37:14.674121 RX DQ/DQS(Engine): PASS
7029 15:37:14.674236 TX OE : NO K
7030 15:37:14.677492 All Pass.
7031 15:37:14.677606
7032 15:37:14.677702 DramC Write-DBI off
7033 15:37:14.680842 PER_BANK_REFRESH: Hybrid Mode
7034 15:37:14.680944 TX_TRACKING: ON
7035 15:37:14.690668 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7036 15:37:14.693846 [FAST_K] Save calibration result to emmc
7037 15:37:14.697420 dramc_set_vcore_voltage set vcore to 725000
7038 15:37:14.700505 Read voltage for 1600, 0
7039 15:37:14.700594 Vio18 = 0
7040 15:37:14.703894 Vcore = 725000
7041 15:37:14.703985 Vdram = 0
7042 15:37:14.704063 Vddq = 0
7043 15:37:14.707184 Vmddr = 0
7044 15:37:14.710008 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7045 15:37:14.716777 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7046 15:37:14.716857 MEM_TYPE=3, freq_sel=13
7047 15:37:14.720369 sv_algorithm_assistance_LP4_3733
7048 15:37:14.726796 ============ PULL DRAM RESETB DOWN ============
7049 15:37:14.730560 ========== PULL DRAM RESETB DOWN end =========
7050 15:37:14.733729 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7051 15:37:14.737073 ===================================
7052 15:37:14.740357 LPDDR4 DRAM CONFIGURATION
7053 15:37:14.743651 ===================================
7054 15:37:14.743734 EX_ROW_EN[0] = 0x0
7055 15:37:14.746973 EX_ROW_EN[1] = 0x0
7056 15:37:14.750007 LP4Y_EN = 0x0
7057 15:37:14.750115 WORK_FSP = 0x1
7058 15:37:14.753527 WL = 0x5
7059 15:37:14.753608 RL = 0x5
7060 15:37:14.757158 BL = 0x2
7061 15:37:14.757240 RPST = 0x0
7062 15:37:14.760399 RD_PRE = 0x0
7063 15:37:14.760481 WR_PRE = 0x1
7064 15:37:14.763630 WR_PST = 0x1
7065 15:37:14.763712 DBI_WR = 0x0
7066 15:37:14.766857 DBI_RD = 0x0
7067 15:37:14.766938 OTF = 0x1
7068 15:37:14.770177 ===================================
7069 15:37:14.773961 ===================================
7070 15:37:14.777221 ANA top config
7071 15:37:14.780602 ===================================
7072 15:37:14.780706 DLL_ASYNC_EN = 0
7073 15:37:14.783899 ALL_SLAVE_EN = 0
7074 15:37:14.787103 NEW_RANK_MODE = 1
7075 15:37:14.790462 DLL_IDLE_MODE = 1
7076 15:37:14.793818 LP45_APHY_COMB_EN = 1
7077 15:37:14.793900 TX_ODT_DIS = 0
7078 15:37:14.796908 NEW_8X_MODE = 1
7079 15:37:14.800146 ===================================
7080 15:37:14.803371 ===================================
7081 15:37:14.807240 data_rate = 3200
7082 15:37:14.810277 CKR = 1
7083 15:37:14.813559 DQ_P2S_RATIO = 8
7084 15:37:14.817374 ===================================
7085 15:37:14.817492 CA_P2S_RATIO = 8
7086 15:37:14.820473 DQ_CA_OPEN = 0
7087 15:37:14.824239 DQ_SEMI_OPEN = 0
7088 15:37:14.827393 CA_SEMI_OPEN = 0
7089 15:37:14.830579 CA_FULL_RATE = 0
7090 15:37:14.830682 DQ_CKDIV4_EN = 0
7091 15:37:14.834146 CA_CKDIV4_EN = 0
7092 15:37:14.836948 CA_PREDIV_EN = 0
7093 15:37:14.840797 PH8_DLY = 12
7094 15:37:14.843845 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7095 15:37:14.847210 DQ_AAMCK_DIV = 4
7096 15:37:14.847314 CA_AAMCK_DIV = 4
7097 15:37:14.850468 CA_ADMCK_DIV = 4
7098 15:37:14.853785 DQ_TRACK_CA_EN = 0
7099 15:37:14.856933 CA_PICK = 1600
7100 15:37:14.860153 CA_MCKIO = 1600
7101 15:37:14.863822 MCKIO_SEMI = 0
7102 15:37:14.867362 PLL_FREQ = 3068
7103 15:37:14.870324 DQ_UI_PI_RATIO = 32
7104 15:37:14.870406 CA_UI_PI_RATIO = 0
7105 15:37:14.873536 ===================================
7106 15:37:14.876781 ===================================
7107 15:37:14.880197 memory_type:LPDDR4
7108 15:37:14.883434 GP_NUM : 10
7109 15:37:14.883542 SRAM_EN : 1
7110 15:37:14.887485 MD32_EN : 0
7111 15:37:14.890502 ===================================
7112 15:37:14.893871 [ANA_INIT] >>>>>>>>>>>>>>
7113 15:37:14.897029 <<<<<< [CONFIGURE PHASE]: ANA_TX
7114 15:37:14.900166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7115 15:37:14.903685 ===================================
7116 15:37:14.903768 data_rate = 3200,PCW = 0X7600
7117 15:37:14.906941 ===================================
7118 15:37:14.910127 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7119 15:37:14.917431 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7120 15:37:14.924007 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 15:37:14.927142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7122 15:37:14.930403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7123 15:37:14.933862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7124 15:37:14.937254 [ANA_INIT] flow start
7125 15:37:14.937331 [ANA_INIT] PLL >>>>>>>>
7126 15:37:14.940532 [ANA_INIT] PLL <<<<<<<<
7127 15:37:14.943934 [ANA_INIT] MIDPI >>>>>>>>
7128 15:37:14.944019 [ANA_INIT] MIDPI <<<<<<<<
7129 15:37:14.947204 [ANA_INIT] DLL >>>>>>>>
7130 15:37:14.950475 [ANA_INIT] DLL <<<<<<<<
7131 15:37:14.950577 [ANA_INIT] flow end
7132 15:37:14.957059 ============ LP4 DIFF to SE enter ============
7133 15:37:14.960401 ============ LP4 DIFF to SE exit ============
7134 15:37:14.963703 [ANA_INIT] <<<<<<<<<<<<<
7135 15:37:14.967154 [Flow] Enable top DCM control >>>>>
7136 15:37:14.970043 [Flow] Enable top DCM control <<<<<
7137 15:37:14.970147 Enable DLL master slave shuffle
7138 15:37:14.976899 ==============================================================
7139 15:37:14.980287 Gating Mode config
7140 15:37:14.983482 ==============================================================
7141 15:37:14.986574 Config description:
7142 15:37:14.996864 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7143 15:37:15.003539 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7144 15:37:15.006620 SELPH_MODE 0: By rank 1: By Phase
7145 15:37:15.013685 ==============================================================
7146 15:37:15.016930 GAT_TRACK_EN = 1
7147 15:37:15.020244 RX_GATING_MODE = 2
7148 15:37:15.023251 RX_GATING_TRACK_MODE = 2
7149 15:37:15.023328 SELPH_MODE = 1
7150 15:37:15.027189 PICG_EARLY_EN = 1
7151 15:37:15.029890 VALID_LAT_VALUE = 1
7152 15:37:15.036966 ==============================================================
7153 15:37:15.040170 Enter into Gating configuration >>>>
7154 15:37:15.043436 Exit from Gating configuration <<<<
7155 15:37:15.046785 Enter into DVFS_PRE_config >>>>>
7156 15:37:15.056607 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7157 15:37:15.059812 Exit from DVFS_PRE_config <<<<<
7158 15:37:15.063174 Enter into PICG configuration >>>>
7159 15:37:15.066491 Exit from PICG configuration <<<<
7160 15:37:15.070357 [RX_INPUT] configuration >>>>>
7161 15:37:15.073336 [RX_INPUT] configuration <<<<<
7162 15:37:15.077034 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7163 15:37:15.083256 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7164 15:37:15.089609 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7165 15:37:15.096516 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7166 15:37:15.103067 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7167 15:37:15.106805 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7168 15:37:15.113132 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7169 15:37:15.116361 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7170 15:37:15.120202 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7171 15:37:15.123490 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7172 15:37:15.126518 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7173 15:37:15.133209 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7174 15:37:15.136234 ===================================
7175 15:37:15.140224 LPDDR4 DRAM CONFIGURATION
7176 15:37:15.143360 ===================================
7177 15:37:15.143469 EX_ROW_EN[0] = 0x0
7178 15:37:15.146570 EX_ROW_EN[1] = 0x0
7179 15:37:15.146653 LP4Y_EN = 0x0
7180 15:37:15.149859 WORK_FSP = 0x1
7181 15:37:15.149941 WL = 0x5
7182 15:37:15.152982 RL = 0x5
7183 15:37:15.153064 BL = 0x2
7184 15:37:15.156240 RPST = 0x0
7185 15:37:15.156333 RD_PRE = 0x0
7186 15:37:15.160062 WR_PRE = 0x1
7187 15:37:15.160168 WR_PST = 0x1
7188 15:37:15.163204 DBI_WR = 0x0
7189 15:37:15.163312 DBI_RD = 0x0
7190 15:37:15.166368 OTF = 0x1
7191 15:37:15.169701 ===================================
7192 15:37:15.172998 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7193 15:37:15.176196 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7194 15:37:15.182860 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7195 15:37:15.186188 ===================================
7196 15:37:15.186304 LPDDR4 DRAM CONFIGURATION
7197 15:37:15.189440 ===================================
7198 15:37:15.192666 EX_ROW_EN[0] = 0x10
7199 15:37:15.196380 EX_ROW_EN[1] = 0x0
7200 15:37:15.196491 LP4Y_EN = 0x0
7201 15:37:15.199616 WORK_FSP = 0x1
7202 15:37:15.199725 WL = 0x5
7203 15:37:15.202816 RL = 0x5
7204 15:37:15.202915 BL = 0x2
7205 15:37:15.206585 RPST = 0x0
7206 15:37:15.206695 RD_PRE = 0x0
7207 15:37:15.209709 WR_PRE = 0x1
7208 15:37:15.209785 WR_PST = 0x1
7209 15:37:15.212754 DBI_WR = 0x0
7210 15:37:15.212864 DBI_RD = 0x0
7211 15:37:15.216089 OTF = 0x1
7212 15:37:15.219319 ===================================
7213 15:37:15.226214 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7214 15:37:15.226329 ==
7215 15:37:15.229303 Dram Type= 6, Freq= 0, CH_0, rank 0
7216 15:37:15.232657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7217 15:37:15.232766 ==
7218 15:37:15.236210 [Duty_Offset_Calibration]
7219 15:37:15.236310 B0:2 B1:1 CA:1
7220 15:37:15.236407
7221 15:37:15.239800 [DutyScan_Calibration_Flow] k_type=0
7222 15:37:15.250273
7223 15:37:15.250402 ==CLK 0==
7224 15:37:15.253618 Final CLK duty delay cell = 0
7225 15:37:15.256931 [0] MAX Duty = 5156%(X100), DQS PI = 22
7226 15:37:15.260096 [0] MIN Duty = 4875%(X100), DQS PI = 62
7227 15:37:15.263324 [0] AVG Duty = 5015%(X100)
7228 15:37:15.263402
7229 15:37:15.266581 CH0 CLK Duty spec in!! Max-Min= 281%
7230 15:37:15.269920 [DutyScan_Calibration_Flow] ====Done====
7231 15:37:15.270003
7232 15:37:15.273168 [DutyScan_Calibration_Flow] k_type=1
7233 15:37:15.289450
7234 15:37:15.289563 ==DQS 0 ==
7235 15:37:15.292603 Final DQS duty delay cell = -4
7236 15:37:15.295952 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7237 15:37:15.299101 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7238 15:37:15.302828 [-4] AVG Duty = 4891%(X100)
7239 15:37:15.302936
7240 15:37:15.303036 ==DQS 1 ==
7241 15:37:15.305847 Final DQS duty delay cell = 0
7242 15:37:15.309046 [0] MAX Duty = 5187%(X100), DQS PI = 4
7243 15:37:15.312380 [0] MIN Duty = 5062%(X100), DQS PI = 30
7244 15:37:15.316261 [0] AVG Duty = 5124%(X100)
7245 15:37:15.316351
7246 15:37:15.319538 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7247 15:37:15.319641
7248 15:37:15.322712 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7249 15:37:15.325839 [DutyScan_Calibration_Flow] ====Done====
7250 15:37:15.325916
7251 15:37:15.328780 [DutyScan_Calibration_Flow] k_type=3
7252 15:37:15.345802
7253 15:37:15.345918 ==DQM 0 ==
7254 15:37:15.349359 Final DQM duty delay cell = 0
7255 15:37:15.352890 [0] MAX Duty = 5218%(X100), DQS PI = 32
7256 15:37:15.355931 [0] MIN Duty = 4907%(X100), DQS PI = 56
7257 15:37:15.359201 [0] AVG Duty = 5062%(X100)
7258 15:37:15.359307
7259 15:37:15.359407 ==DQM 1 ==
7260 15:37:15.362399 Final DQM duty delay cell = -4
7261 15:37:15.366319 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7262 15:37:15.369577 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7263 15:37:15.372868 [-4] AVG Duty = 4906%(X100)
7264 15:37:15.372955
7265 15:37:15.376158 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7266 15:37:15.376251
7267 15:37:15.379475 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7268 15:37:15.382800 [DutyScan_Calibration_Flow] ====Done====
7269 15:37:15.382921
7270 15:37:15.386159 [DutyScan_Calibration_Flow] k_type=2
7271 15:37:15.403365
7272 15:37:15.403464 ==DQ 0 ==
7273 15:37:15.406640 Final DQ duty delay cell = 0
7274 15:37:15.410455 [0] MAX Duty = 5062%(X100), DQS PI = 24
7275 15:37:15.413741 [0] MIN Duty = 4907%(X100), DQS PI = 0
7276 15:37:15.413827 [0] AVG Duty = 4984%(X100)
7277 15:37:15.413911
7278 15:37:15.416901 ==DQ 1 ==
7279 15:37:15.420181 Final DQ duty delay cell = 0
7280 15:37:15.424023 [0] MAX Duty = 5125%(X100), DQS PI = 6
7281 15:37:15.427330 [0] MIN Duty = 4907%(X100), DQS PI = 34
7282 15:37:15.427438 [0] AVG Duty = 5016%(X100)
7283 15:37:15.427537
7284 15:37:15.430326 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7285 15:37:15.430435
7286 15:37:15.433611 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7287 15:37:15.440684 [DutyScan_Calibration_Flow] ====Done====
7288 15:37:15.440766 ==
7289 15:37:15.443735 Dram Type= 6, Freq= 0, CH_1, rank 0
7290 15:37:15.446798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7291 15:37:15.446877 ==
7292 15:37:15.450533 [Duty_Offset_Calibration]
7293 15:37:15.450642 B0:1 B1:0 CA:1
7294 15:37:15.450734
7295 15:37:15.453843 [DutyScan_Calibration_Flow] k_type=0
7296 15:37:15.462666
7297 15:37:15.462772 ==CLK 0==
7298 15:37:15.466096 Final CLK duty delay cell = -4
7299 15:37:15.469674 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7300 15:37:15.472501 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7301 15:37:15.476103 [-4] AVG Duty = 4938%(X100)
7302 15:37:15.476209
7303 15:37:15.479680 CH1 CLK Duty spec in!! Max-Min= 124%
7304 15:37:15.482956 [DutyScan_Calibration_Flow] ====Done====
7305 15:37:15.483075
7306 15:37:15.486258 [DutyScan_Calibration_Flow] k_type=1
7307 15:37:15.502541
7308 15:37:15.502648 ==DQS 0 ==
7309 15:37:15.506052 Final DQS duty delay cell = 0
7310 15:37:15.509176 [0] MAX Duty = 5094%(X100), DQS PI = 18
7311 15:37:15.512480 [0] MIN Duty = 4844%(X100), DQS PI = 48
7312 15:37:15.515708 [0] AVG Duty = 4969%(X100)
7313 15:37:15.515788
7314 15:37:15.515850 ==DQS 1 ==
7315 15:37:15.519547 Final DQS duty delay cell = 0
7316 15:37:15.522593 [0] MAX Duty = 5249%(X100), DQS PI = 16
7317 15:37:15.526294 [0] MIN Duty = 4969%(X100), DQS PI = 6
7318 15:37:15.529557 [0] AVG Duty = 5109%(X100)
7319 15:37:15.529655
7320 15:37:15.532582 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7321 15:37:15.532656
7322 15:37:15.536204 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7323 15:37:15.539160 [DutyScan_Calibration_Flow] ====Done====
7324 15:37:15.539235
7325 15:37:15.542853 [DutyScan_Calibration_Flow] k_type=3
7326 15:37:15.559574
7327 15:37:15.559668 ==DQM 0 ==
7328 15:37:15.562969 Final DQM duty delay cell = 0
7329 15:37:15.566154 [0] MAX Duty = 5187%(X100), DQS PI = 10
7330 15:37:15.569817 [0] MIN Duty = 4969%(X100), DQS PI = 48
7331 15:37:15.572896 [0] AVG Duty = 5078%(X100)
7332 15:37:15.572972
7333 15:37:15.573033 ==DQM 1 ==
7334 15:37:15.576511 Final DQM duty delay cell = 0
7335 15:37:15.579558 [0] MAX Duty = 5093%(X100), DQS PI = 16
7336 15:37:15.582744 [0] MIN Duty = 4907%(X100), DQS PI = 52
7337 15:37:15.586290 [0] AVG Duty = 5000%(X100)
7338 15:37:15.586397
7339 15:37:15.589659 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7340 15:37:15.589732
7341 15:37:15.592740 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7342 15:37:15.595956 [DutyScan_Calibration_Flow] ====Done====
7343 15:37:15.596029
7344 15:37:15.599778 [DutyScan_Calibration_Flow] k_type=2
7345 15:37:15.616098
7346 15:37:15.616201 ==DQ 0 ==
7347 15:37:15.619341 Final DQ duty delay cell = -4
7348 15:37:15.622469 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7349 15:37:15.625654 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7350 15:37:15.629340 [-4] AVG Duty = 4968%(X100)
7351 15:37:15.629437
7352 15:37:15.629526 ==DQ 1 ==
7353 15:37:15.632496 Final DQ duty delay cell = 0
7354 15:37:15.635691 [0] MAX Duty = 5125%(X100), DQS PI = 20
7355 15:37:15.638806 [0] MIN Duty = 4938%(X100), DQS PI = 10
7356 15:37:15.642418 [0] AVG Duty = 5031%(X100)
7357 15:37:15.642498
7358 15:37:15.645709 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7359 15:37:15.645790
7360 15:37:15.648877 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7361 15:37:15.651981 [DutyScan_Calibration_Flow] ====Done====
7362 15:37:15.655730 nWR fixed to 30
7363 15:37:15.658880 [ModeRegInit_LP4] CH0 RK0
7364 15:37:15.658960 [ModeRegInit_LP4] CH0 RK1
7365 15:37:15.662639 [ModeRegInit_LP4] CH1 RK0
7366 15:37:15.665885 [ModeRegInit_LP4] CH1 RK1
7367 15:37:15.665965 match AC timing 5
7368 15:37:15.672295 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7369 15:37:15.675476 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7370 15:37:15.679379 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7371 15:37:15.686061 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7372 15:37:15.689267 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7373 15:37:15.689350 [MiockJmeterHQA]
7374 15:37:15.689414
7375 15:37:15.692435 [DramcMiockJmeter] u1RxGatingPI = 0
7376 15:37:15.695565 0 : 4252, 4027
7377 15:37:15.695661 4 : 4363, 4137
7378 15:37:15.699094 8 : 4252, 4027
7379 15:37:15.699209 12 : 4252, 4027
7380 15:37:15.699305 16 : 4253, 4027
7381 15:37:15.701998 20 : 4252, 4027
7382 15:37:15.702108 24 : 4252, 4027
7383 15:37:15.705378 28 : 4363, 4137
7384 15:37:15.705455 32 : 4253, 4027
7385 15:37:15.708666 36 : 4363, 4137
7386 15:37:15.708740 40 : 4252, 4027
7387 15:37:15.712476 44 : 4252, 4027
7388 15:37:15.712549 48 : 4252, 4026
7389 15:37:15.712610 52 : 4363, 4138
7390 15:37:15.715597 56 : 4252, 4027
7391 15:37:15.715674 60 : 4361, 4137
7392 15:37:15.718845 64 : 4250, 4027
7393 15:37:15.718918 68 : 4250, 4026
7394 15:37:15.722290 72 : 4252, 4027
7395 15:37:15.722398 76 : 4249, 4027
7396 15:37:15.722489 80 : 4361, 4137
7397 15:37:15.725457 84 : 4252, 4024
7398 15:37:15.725556 88 : 4363, 104
7399 15:37:15.728659 92 : 4363, 0
7400 15:37:15.728731 96 : 4360, 0
7401 15:37:15.728827 100 : 4250, 0
7402 15:37:15.731840 104 : 4250, 0
7403 15:37:15.731911 108 : 4364, 0
7404 15:37:15.735687 112 : 4361, 0
7405 15:37:15.735789 116 : 4360, 0
7406 15:37:15.735884 120 : 4253, 0
7407 15:37:15.738869 124 : 4252, 0
7408 15:37:15.738939 128 : 4250, 0
7409 15:37:15.741927 132 : 4250, 0
7410 15:37:15.742003 136 : 4250, 0
7411 15:37:15.742067 140 : 4250, 0
7412 15:37:15.745589 144 : 4249, 0
7413 15:37:15.745678 148 : 4363, 0
7414 15:37:15.748576 152 : 4361, 0
7415 15:37:15.748683 156 : 4247, 0
7416 15:37:15.748776 160 : 4361, 0
7417 15:37:15.752326 164 : 4360, 0
7418 15:37:15.752403 168 : 4363, 0
7419 15:37:15.752467 172 : 4250, 0
7420 15:37:15.755482 176 : 4250, 0
7421 15:37:15.755579 180 : 4250, 0
7422 15:37:15.758604 184 : 4250, 0
7423 15:37:15.758702 188 : 4250, 0
7424 15:37:15.758770 192 : 4250, 0
7425 15:37:15.761749 196 : 4253, 0
7426 15:37:15.761833 200 : 4361, 0
7427 15:37:15.765585 204 : 4250, 1361
7428 15:37:15.765681 208 : 4250, 3993
7429 15:37:15.768761 212 : 4250, 4027
7430 15:37:15.768863 216 : 4252, 4030
7431 15:37:15.772119 220 : 4249, 4027
7432 15:37:15.772192 224 : 4250, 4027
7433 15:37:15.772253 228 : 4250, 4027
7434 15:37:15.775373 232 : 4249, 4027
7435 15:37:15.775479 236 : 4250, 4026
7436 15:37:15.778508 240 : 4361, 4137
7437 15:37:15.778613 244 : 4360, 4138
7438 15:37:15.781564 248 : 4247, 4024
7439 15:37:15.781663 252 : 4361, 4137
7440 15:37:15.784820 256 : 4361, 4137
7441 15:37:15.784897 260 : 4250, 4027
7442 15:37:15.788724 264 : 4250, 4027
7443 15:37:15.788798 268 : 4249, 4027
7444 15:37:15.791730 272 : 4250, 4026
7445 15:37:15.791805 276 : 4250, 4027
7446 15:37:15.794849 280 : 4250, 4027
7447 15:37:15.794934 284 : 4250, 4027
7448 15:37:15.798643 288 : 4250, 4026
7449 15:37:15.798743 292 : 4361, 4137
7450 15:37:15.798833 296 : 4360, 4138
7451 15:37:15.801863 300 : 4247, 4024
7452 15:37:15.801965 304 : 4365, 4143
7453 15:37:15.805052 308 : 4361, 4052
7454 15:37:15.805136 312 : 4250, 1774
7455 15:37:15.805203
7456 15:37:15.808322 MIOCK jitter meter ch=0
7457 15:37:15.808395
7458 15:37:15.811948 1T = (312-88) = 224 dly cells
7459 15:37:15.818668 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7460 15:37:15.818747 ==
7461 15:37:15.821724 Dram Type= 6, Freq= 0, CH_0, rank 0
7462 15:37:15.825040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7463 15:37:15.825113 ==
7464 15:37:15.831889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7465 15:37:15.835085 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7466 15:37:15.838357 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7467 15:37:15.844659 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7468 15:37:15.853448 [CA 0] Center 42 (12~73) winsize 62
7469 15:37:15.856895 [CA 1] Center 43 (12~74) winsize 63
7470 15:37:15.859849 [CA 2] Center 37 (8~67) winsize 60
7471 15:37:15.863534 [CA 3] Center 37 (7~67) winsize 61
7472 15:37:15.866753 [CA 4] Center 36 (6~66) winsize 61
7473 15:37:15.870424 [CA 5] Center 34 (5~64) winsize 60
7474 15:37:15.870505
7475 15:37:15.873590 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7476 15:37:15.873672
7477 15:37:15.876919 [CATrainingPosCal] consider 1 rank data
7478 15:37:15.880042 u2DelayCellTimex100 = 290/100 ps
7479 15:37:15.883751 CA0 delay=42 (12~73),Diff = 8 PI (26 cell)
7480 15:37:15.890169 CA1 delay=43 (12~74),Diff = 9 PI (30 cell)
7481 15:37:15.893314 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
7482 15:37:15.897042 CA3 delay=37 (7~67),Diff = 3 PI (10 cell)
7483 15:37:15.900244 CA4 delay=36 (6~66),Diff = 2 PI (6 cell)
7484 15:37:15.903891 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
7485 15:37:15.903972
7486 15:37:15.906997 CA PerBit enable=1, Macro0, CA PI delay=34
7487 15:37:15.907078
7488 15:37:15.910303 [CBTSetCACLKResult] CA Dly = 34
7489 15:37:15.913560 CS Dly: 9 (0~40)
7490 15:37:15.916703 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7491 15:37:15.919977 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7492 15:37:15.920058 ==
7493 15:37:15.923482 Dram Type= 6, Freq= 0, CH_0, rank 1
7494 15:37:15.926885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 15:37:15.926967 ==
7496 15:37:15.933319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 15:37:15.936924 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 15:37:15.943665 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 15:37:15.946838 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 15:37:15.957017 [CA 0] Center 43 (13~73) winsize 61
7501 15:37:15.960190 [CA 1] Center 43 (13~73) winsize 61
7502 15:37:15.963777 [CA 2] Center 38 (8~68) winsize 61
7503 15:37:15.966808 [CA 3] Center 38 (8~68) winsize 61
7504 15:37:15.970165 [CA 4] Center 36 (6~66) winsize 61
7505 15:37:15.973368 [CA 5] Center 35 (6~65) winsize 60
7506 15:37:15.973449
7507 15:37:15.976913 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7508 15:37:15.977023
7509 15:37:15.980383 [CATrainingPosCal] consider 2 rank data
7510 15:37:15.983492 u2DelayCellTimex100 = 290/100 ps
7511 15:37:15.986802 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7512 15:37:15.993900 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7513 15:37:15.997206 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7514 15:37:16.000296 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7515 15:37:16.003502 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7516 15:37:16.007140 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7517 15:37:16.007213
7518 15:37:16.010210 CA PerBit enable=1, Macro0, CA PI delay=35
7519 15:37:16.010292
7520 15:37:16.013736 [CBTSetCACLKResult] CA Dly = 35
7521 15:37:16.013817 CS Dly: 10 (0~42)
7522 15:37:16.020561 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 15:37:16.023943 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 15:37:16.024031
7525 15:37:16.026978 ----->DramcWriteLeveling(PI) begin...
7526 15:37:16.027050 ==
7527 15:37:16.030078 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 15:37:16.033888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 15:37:16.033963 ==
7530 15:37:16.036764 Write leveling (Byte 0): 34 => 34
7531 15:37:16.040106 Write leveling (Byte 1): 26 => 26
7532 15:37:16.043718 DramcWriteLeveling(PI) end<-----
7533 15:37:16.043796
7534 15:37:16.043860 ==
7535 15:37:16.046740 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 15:37:16.053203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 15:37:16.053306 ==
7538 15:37:16.053407 [Gating] SW mode calibration
7539 15:37:16.063316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7540 15:37:16.066533 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7541 15:37:16.073020 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 15:37:16.076754 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7543 15:37:16.079925 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7544 15:37:16.086180 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7545 15:37:16.089649 1 4 16 | B1->B0 | 2323 3737 | 1 0 | (1 1) (1 1)
7546 15:37:16.093029 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
7547 15:37:16.096583 1 4 24 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7548 15:37:16.102970 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7549 15:37:16.106258 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7550 15:37:16.109952 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7551 15:37:16.116110 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7552 15:37:16.119723 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7553 15:37:16.122860 1 5 16 | B1->B0 | 3333 2525 | 1 0 | (1 0) (0 0)
7554 15:37:16.129859 1 5 20 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
7555 15:37:16.133002 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7556 15:37:16.136255 1 5 28 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7557 15:37:16.142614 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7558 15:37:16.146210 1 6 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7559 15:37:16.149256 1 6 8 | B1->B0 | 2323 3433 | 0 1 | (0 0) (1 1)
7560 15:37:16.156000 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7561 15:37:16.159414 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7562 15:37:16.162953 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7563 15:37:16.169529 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7564 15:37:16.172846 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 15:37:16.175915 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 15:37:16.182744 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 15:37:16.186010 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 15:37:16.189238 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7569 15:37:16.196175 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7570 15:37:16.199109 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7571 15:37:16.202548 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 15:37:16.209539 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 15:37:16.212739 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 15:37:16.215914 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 15:37:16.222337 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 15:37:16.226083 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 15:37:16.229054 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 15:37:16.236181 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 15:37:16.239293 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 15:37:16.242502 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 15:37:16.245874 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 15:37:16.252232 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 15:37:16.255957 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7584 15:37:16.258925 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7585 15:37:16.265549 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7586 15:37:16.268946 Total UI for P1: 0, mck2ui 16
7587 15:37:16.272494 best dqsien dly found for B0: ( 1, 9, 10)
7588 15:37:16.275965 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7589 15:37:16.279278 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 15:37:16.282443 Total UI for P1: 0, mck2ui 16
7591 15:37:16.285552 best dqsien dly found for B1: ( 1, 9, 18)
7592 15:37:16.288843 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7593 15:37:16.292119 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7594 15:37:16.292218
7595 15:37:16.298991 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7596 15:37:16.302197 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7597 15:37:16.305351 [Gating] SW calibration Done
7598 15:37:16.305456 ==
7599 15:37:16.309121 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 15:37:16.312710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 15:37:16.312816 ==
7602 15:37:16.312908 RX Vref Scan: 0
7603 15:37:16.313006
7604 15:37:16.315523 RX Vref 0 -> 0, step: 1
7605 15:37:16.315635
7606 15:37:16.319268 RX Delay 0 -> 252, step: 8
7607 15:37:16.322161 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7608 15:37:16.325576 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7609 15:37:16.332302 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7610 15:37:16.335982 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7611 15:37:16.339209 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7612 15:37:16.342518 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7613 15:37:16.345578 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7614 15:37:16.348879 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7615 15:37:16.355206 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7616 15:37:16.358526 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7617 15:37:16.362342 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7618 15:37:16.365330 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7619 15:37:16.368506 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7620 15:37:16.375177 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7621 15:37:16.378878 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7622 15:37:16.382003 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7623 15:37:16.382075 ==
7624 15:37:16.384994 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 15:37:16.388545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 15:37:16.391873 ==
7627 15:37:16.391949 DQS Delay:
7628 15:37:16.392011 DQS0 = 0, DQS1 = 0
7629 15:37:16.395365 DQM Delay:
7630 15:37:16.395448 DQM0 = 137, DQM1 = 131
7631 15:37:16.398386 DQ Delay:
7632 15:37:16.402254 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7633 15:37:16.405381 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7634 15:37:16.408679 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7635 15:37:16.412417 DQ12 =139, DQ13 =139, DQ14 =143, DQ15 =135
7636 15:37:16.412523
7637 15:37:16.412624
7638 15:37:16.412723 ==
7639 15:37:16.415731 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 15:37:16.418733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 15:37:16.418847 ==
7642 15:37:16.418943
7643 15:37:16.419040
7644 15:37:16.422354 TX Vref Scan disable
7645 15:37:16.425278 == TX Byte 0 ==
7646 15:37:16.428948 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7647 15:37:16.431666 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7648 15:37:16.435373 == TX Byte 1 ==
7649 15:37:16.438495 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7650 15:37:16.442361 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7651 15:37:16.442478 ==
7652 15:37:16.445685 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 15:37:16.452108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 15:37:16.452190 ==
7655 15:37:16.463022
7656 15:37:16.466309 TX Vref early break, caculate TX vref
7657 15:37:16.469333 TX Vref=16, minBit 0, minWin=23, winSum=383
7658 15:37:16.472601 TX Vref=18, minBit 7, minWin=23, winSum=393
7659 15:37:16.476508 TX Vref=20, minBit 3, minWin=24, winSum=404
7660 15:37:16.479565 TX Vref=22, minBit 7, minWin=24, winSum=415
7661 15:37:16.483261 TX Vref=24, minBit 1, minWin=25, winSum=416
7662 15:37:16.489943 TX Vref=26, minBit 0, minWin=26, winSum=432
7663 15:37:16.493021 TX Vref=28, minBit 6, minWin=24, winSum=423
7664 15:37:16.496134 TX Vref=30, minBit 6, minWin=24, winSum=412
7665 15:37:16.499843 TX Vref=32, minBit 6, minWin=24, winSum=407
7666 15:37:16.506049 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 26
7667 15:37:16.506172
7668 15:37:16.509211 Final TX Range 0 Vref 26
7669 15:37:16.509303
7670 15:37:16.509373 ==
7671 15:37:16.512686 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 15:37:16.516173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 15:37:16.516282 ==
7674 15:37:16.516347
7675 15:37:16.516406
7676 15:37:16.519289 TX Vref Scan disable
7677 15:37:16.522608 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7678 15:37:16.525850 == TX Byte 0 ==
7679 15:37:16.529364 u2DelayCellOfst[0]=10 cells (3 PI)
7680 15:37:16.532363 u2DelayCellOfst[1]=13 cells (4 PI)
7681 15:37:16.536001 u2DelayCellOfst[2]=10 cells (3 PI)
7682 15:37:16.539532 u2DelayCellOfst[3]=10 cells (3 PI)
7683 15:37:16.542253 u2DelayCellOfst[4]=10 cells (3 PI)
7684 15:37:16.545826 u2DelayCellOfst[5]=0 cells (0 PI)
7685 15:37:16.545923 u2DelayCellOfst[6]=16 cells (5 PI)
7686 15:37:16.549015 u2DelayCellOfst[7]=13 cells (4 PI)
7687 15:37:16.556076 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7688 15:37:16.559369 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7689 15:37:16.559478 == TX Byte 1 ==
7690 15:37:16.562538 u2DelayCellOfst[8]=0 cells (0 PI)
7691 15:37:16.565715 u2DelayCellOfst[9]=0 cells (0 PI)
7692 15:37:16.568926 u2DelayCellOfst[10]=6 cells (2 PI)
7693 15:37:16.572628 u2DelayCellOfst[11]=6 cells (2 PI)
7694 15:37:16.575651 u2DelayCellOfst[12]=10 cells (3 PI)
7695 15:37:16.579483 u2DelayCellOfst[13]=10 cells (3 PI)
7696 15:37:16.582691 u2DelayCellOfst[14]=13 cells (4 PI)
7697 15:37:16.585919 u2DelayCellOfst[15]=10 cells (3 PI)
7698 15:37:16.588905 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7699 15:37:16.592640 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7700 15:37:16.596019 DramC Write-DBI on
7701 15:37:16.596101 ==
7702 15:37:16.599236 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 15:37:16.602452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 15:37:16.602534 ==
7705 15:37:16.602598
7706 15:37:16.602656
7707 15:37:16.605699 TX Vref Scan disable
7708 15:37:16.609522 == TX Byte 0 ==
7709 15:37:16.612693 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7710 15:37:16.615786 == TX Byte 1 ==
7711 15:37:16.619542 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7712 15:37:16.619651 DramC Write-DBI off
7713 15:37:16.619717
7714 15:37:16.622491 [DATLAT]
7715 15:37:16.622571 Freq=1600, CH0 RK0
7716 15:37:16.622655
7717 15:37:16.625967 DATLAT Default: 0xf
7718 15:37:16.626046 0, 0xFFFF, sum = 0
7719 15:37:16.629298 1, 0xFFFF, sum = 0
7720 15:37:16.629379 2, 0xFFFF, sum = 0
7721 15:37:16.632601 3, 0xFFFF, sum = 0
7722 15:37:16.632682 4, 0xFFFF, sum = 0
7723 15:37:16.635751 5, 0xFFFF, sum = 0
7724 15:37:16.635832 6, 0xFFFF, sum = 0
7725 15:37:16.639486 7, 0xFFFF, sum = 0
7726 15:37:16.639615 8, 0xFFFF, sum = 0
7727 15:37:16.642573 9, 0xFFFF, sum = 0
7728 15:37:16.642679 10, 0xFFFF, sum = 0
7729 15:37:16.646166 11, 0xFFFF, sum = 0
7730 15:37:16.649193 12, 0xFFFF, sum = 0
7731 15:37:16.649275 13, 0xFFFF, sum = 0
7732 15:37:16.652734 14, 0x0, sum = 1
7733 15:37:16.652817 15, 0x0, sum = 2
7734 15:37:16.655770 16, 0x0, sum = 3
7735 15:37:16.655851 17, 0x0, sum = 4
7736 15:37:16.655914 best_step = 15
7737 15:37:16.655972
7738 15:37:16.659409 ==
7739 15:37:16.659514 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 15:37:16.665782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 15:37:16.665862 ==
7742 15:37:16.665925 RX Vref Scan: 1
7743 15:37:16.665983
7744 15:37:16.668929 Set Vref Range= 24 -> 127
7745 15:37:16.669008
7746 15:37:16.672859 RX Vref 24 -> 127, step: 1
7747 15:37:16.672952
7748 15:37:16.675944 RX Delay 27 -> 252, step: 4
7749 15:37:16.676024
7750 15:37:16.679036 Set Vref, RX VrefLevel [Byte0]: 24
7751 15:37:16.682301 [Byte1]: 24
7752 15:37:16.682381
7753 15:37:16.686049 Set Vref, RX VrefLevel [Byte0]: 25
7754 15:37:16.689281 [Byte1]: 25
7755 15:37:16.689361
7756 15:37:16.692320 Set Vref, RX VrefLevel [Byte0]: 26
7757 15:37:16.695866 [Byte1]: 26
7758 15:37:16.698982
7759 15:37:16.699061 Set Vref, RX VrefLevel [Byte0]: 27
7760 15:37:16.702359 [Byte1]: 27
7761 15:37:16.706218
7762 15:37:16.706308 Set Vref, RX VrefLevel [Byte0]: 28
7763 15:37:16.709536 [Byte1]: 28
7764 15:37:16.713948
7765 15:37:16.714053 Set Vref, RX VrefLevel [Byte0]: 29
7766 15:37:16.717120 [Byte1]: 29
7767 15:37:16.721615
7768 15:37:16.721699 Set Vref, RX VrefLevel [Byte0]: 30
7769 15:37:16.724825 [Byte1]: 30
7770 15:37:16.728747
7771 15:37:16.728826 Set Vref, RX VrefLevel [Byte0]: 31
7772 15:37:16.732507 [Byte1]: 31
7773 15:37:16.736234
7774 15:37:16.736313 Set Vref, RX VrefLevel [Byte0]: 32
7775 15:37:16.739753 [Byte1]: 32
7776 15:37:16.744060
7777 15:37:16.744140 Set Vref, RX VrefLevel [Byte0]: 33
7778 15:37:16.747521 [Byte1]: 33
7779 15:37:16.751599
7780 15:37:16.751694 Set Vref, RX VrefLevel [Byte0]: 34
7781 15:37:16.754586 [Byte1]: 34
7782 15:37:16.758987
7783 15:37:16.759067 Set Vref, RX VrefLevel [Byte0]: 35
7784 15:37:16.762458 [Byte1]: 35
7785 15:37:16.766588
7786 15:37:16.766667 Set Vref, RX VrefLevel [Byte0]: 36
7787 15:37:16.770230 [Byte1]: 36
7788 15:37:16.774447
7789 15:37:16.774526 Set Vref, RX VrefLevel [Byte0]: 37
7790 15:37:16.777687 [Byte1]: 37
7791 15:37:16.782004
7792 15:37:16.782084 Set Vref, RX VrefLevel [Byte0]: 38
7793 15:37:16.785370 [Byte1]: 38
7794 15:37:16.789092
7795 15:37:16.789171 Set Vref, RX VrefLevel [Byte0]: 39
7796 15:37:16.792217 [Byte1]: 39
7797 15:37:16.796913
7798 15:37:16.796992 Set Vref, RX VrefLevel [Byte0]: 40
7799 15:37:16.800069 [Byte1]: 40
7800 15:37:16.804152
7801 15:37:16.804236 Set Vref, RX VrefLevel [Byte0]: 41
7802 15:37:16.807805 [Byte1]: 41
7803 15:37:16.812166
7804 15:37:16.812245 Set Vref, RX VrefLevel [Byte0]: 42
7805 15:37:16.815374 [Byte1]: 42
7806 15:37:16.819200
7807 15:37:16.819312 Set Vref, RX VrefLevel [Byte0]: 43
7808 15:37:16.822875 [Byte1]: 43
7809 15:37:16.826701
7810 15:37:16.826780 Set Vref, RX VrefLevel [Byte0]: 44
7811 15:37:16.830358 [Byte1]: 44
7812 15:37:16.834074
7813 15:37:16.834159 Set Vref, RX VrefLevel [Byte0]: 45
7814 15:37:16.837959 [Byte1]: 45
7815 15:37:16.841872
7816 15:37:16.841959 Set Vref, RX VrefLevel [Byte0]: 46
7817 15:37:16.845513 [Byte1]: 46
7818 15:37:16.849293
7819 15:37:16.849374 Set Vref, RX VrefLevel [Byte0]: 47
7820 15:37:16.853205 [Byte1]: 47
7821 15:37:16.857104
7822 15:37:16.857184 Set Vref, RX VrefLevel [Byte0]: 48
7823 15:37:16.860081 [Byte1]: 48
7824 15:37:16.864255
7825 15:37:16.864337 Set Vref, RX VrefLevel [Byte0]: 49
7826 15:37:16.867582 [Byte1]: 49
7827 15:37:16.871908
7828 15:37:16.872051 Set Vref, RX VrefLevel [Byte0]: 50
7829 15:37:16.875457 [Byte1]: 50
7830 15:37:16.879815
7831 15:37:16.879925 Set Vref, RX VrefLevel [Byte0]: 51
7832 15:37:16.882796 [Byte1]: 51
7833 15:37:16.886961
7834 15:37:16.887055 Set Vref, RX VrefLevel [Byte0]: 52
7835 15:37:16.890662 [Byte1]: 52
7836 15:37:16.894735
7837 15:37:16.894815 Set Vref, RX VrefLevel [Byte0]: 53
7838 15:37:16.897933 [Byte1]: 53
7839 15:37:16.902217
7840 15:37:16.902296 Set Vref, RX VrefLevel [Byte0]: 54
7841 15:37:16.905395 [Byte1]: 54
7842 15:37:16.909899
7843 15:37:16.910002 Set Vref, RX VrefLevel [Byte0]: 55
7844 15:37:16.913038 [Byte1]: 55
7845 15:37:16.917284
7846 15:37:16.917364 Set Vref, RX VrefLevel [Byte0]: 56
7847 15:37:16.920470 [Byte1]: 56
7848 15:37:16.924906
7849 15:37:16.924987 Set Vref, RX VrefLevel [Byte0]: 57
7850 15:37:16.928077 [Byte1]: 57
7851 15:37:16.932439
7852 15:37:16.932520 Set Vref, RX VrefLevel [Byte0]: 58
7853 15:37:16.935677 [Byte1]: 58
7854 15:37:16.940202
7855 15:37:16.940283 Set Vref, RX VrefLevel [Byte0]: 59
7856 15:37:16.942873 [Byte1]: 59
7857 15:37:16.947171
7858 15:37:16.947252 Set Vref, RX VrefLevel [Byte0]: 60
7859 15:37:16.950934 [Byte1]: 60
7860 15:37:16.954899
7861 15:37:16.954980 Set Vref, RX VrefLevel [Byte0]: 61
7862 15:37:16.958736 [Byte1]: 61
7863 15:37:16.962377
7864 15:37:16.962458 Set Vref, RX VrefLevel [Byte0]: 62
7865 15:37:16.966043 [Byte1]: 62
7866 15:37:16.970156
7867 15:37:16.970237 Set Vref, RX VrefLevel [Byte0]: 63
7868 15:37:16.973468 [Byte1]: 63
7869 15:37:16.977590
7870 15:37:16.977670 Set Vref, RX VrefLevel [Byte0]: 64
7871 15:37:16.981011 [Byte1]: 64
7872 15:37:16.984825
7873 15:37:16.984906 Set Vref, RX VrefLevel [Byte0]: 65
7874 15:37:16.988506 [Byte1]: 65
7875 15:37:16.992642
7876 15:37:16.992726 Set Vref, RX VrefLevel [Byte0]: 66
7877 15:37:16.996113 [Byte1]: 66
7878 15:37:17.000173
7879 15:37:17.000265 Set Vref, RX VrefLevel [Byte0]: 67
7880 15:37:17.003393 [Byte1]: 67
7881 15:37:17.007861
7882 15:37:17.007947 Set Vref, RX VrefLevel [Byte0]: 68
7883 15:37:17.010916 [Byte1]: 68
7884 15:37:17.015303
7885 15:37:17.015403 Set Vref, RX VrefLevel [Byte0]: 69
7886 15:37:17.018446 [Byte1]: 69
7887 15:37:17.022673
7888 15:37:17.022747 Set Vref, RX VrefLevel [Byte0]: 70
7889 15:37:17.029568 [Byte1]: 70
7890 15:37:17.029650
7891 15:37:17.032939 Set Vref, RX VrefLevel [Byte0]: 71
7892 15:37:17.036000 [Byte1]: 71
7893 15:37:17.036080
7894 15:37:17.039287 Set Vref, RX VrefLevel [Byte0]: 72
7895 15:37:17.042533 [Byte1]: 72
7896 15:37:17.042614
7897 15:37:17.045800 Set Vref, RX VrefLevel [Byte0]: 73
7898 15:37:17.049019 [Byte1]: 73
7899 15:37:17.052792
7900 15:37:17.052873 Set Vref, RX VrefLevel [Byte0]: 74
7901 15:37:17.055963 [Byte1]: 74
7902 15:37:17.060516
7903 15:37:17.060597 Set Vref, RX VrefLevel [Byte0]: 75
7904 15:37:17.063732 [Byte1]: 75
7905 15:37:17.068219
7906 15:37:17.068300 Set Vref, RX VrefLevel [Byte0]: 76
7907 15:37:17.071400 [Byte1]: 76
7908 15:37:17.075922
7909 15:37:17.076004 Final RX Vref Byte 0 = 56 to rank0
7910 15:37:17.078915 Final RX Vref Byte 1 = 66 to rank0
7911 15:37:17.082098 Final RX Vref Byte 0 = 56 to rank1
7912 15:37:17.085321 Final RX Vref Byte 1 = 66 to rank1==
7913 15:37:17.089101 Dram Type= 6, Freq= 0, CH_0, rank 0
7914 15:37:17.095486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7915 15:37:17.095600 ==
7916 15:37:17.095669 DQS Delay:
7917 15:37:17.095729 DQS0 = 0, DQS1 = 0
7918 15:37:17.098626 DQM Delay:
7919 15:37:17.098732 DQM0 = 134, DQM1 = 128
7920 15:37:17.101873 DQ Delay:
7921 15:37:17.105415 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7922 15:37:17.108936 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7923 15:37:17.111947 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
7924 15:37:17.115308 DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136
7925 15:37:17.115389
7926 15:37:17.115452
7927 15:37:17.115511
7928 15:37:17.118589 [DramC_TX_OE_Calibration] TA2
7929 15:37:17.121942 Original DQ_B0 (3 6) =30, OEN = 27
7930 15:37:17.125724 Original DQ_B1 (3 6) =30, OEN = 27
7931 15:37:17.128762 24, 0x0, End_B0=24 End_B1=24
7932 15:37:17.128843 25, 0x0, End_B0=25 End_B1=25
7933 15:37:17.132301 26, 0x0, End_B0=26 End_B1=26
7934 15:37:17.135231 27, 0x0, End_B0=27 End_B1=27
7935 15:37:17.138915 28, 0x0, End_B0=28 End_B1=28
7936 15:37:17.138996 29, 0x0, End_B0=29 End_B1=29
7937 15:37:17.141984 30, 0x0, End_B0=30 End_B1=30
7938 15:37:17.145306 31, 0x4141, End_B0=30 End_B1=30
7939 15:37:17.149020 Byte0 end_step=30 best_step=27
7940 15:37:17.152266 Byte1 end_step=30 best_step=27
7941 15:37:17.155295 Byte0 TX OE(2T, 0.5T) = (3, 3)
7942 15:37:17.155374 Byte1 TX OE(2T, 0.5T) = (3, 3)
7943 15:37:17.155437
7944 15:37:17.158385
7945 15:37:17.165558 [DQSOSCAuto] RK0, (LSB)MR18= 0x2621, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
7946 15:37:17.168722 CH0 RK0: MR19=303, MR18=2621
7947 15:37:17.175085 CH0_RK0: MR19=0x303, MR18=0x2621, DQSOSC=390, MR23=63, INC=24, DEC=16
7948 15:37:17.175165
7949 15:37:17.178925 ----->DramcWriteLeveling(PI) begin...
7950 15:37:17.179006 ==
7951 15:37:17.182339 Dram Type= 6, Freq= 0, CH_0, rank 1
7952 15:37:17.185175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7953 15:37:17.185255 ==
7954 15:37:17.188862 Write leveling (Byte 0): 33 => 33
7955 15:37:17.192076 Write leveling (Byte 1): 27 => 27
7956 15:37:17.195227 DramcWriteLeveling(PI) end<-----
7957 15:37:17.195306
7958 15:37:17.195369 ==
7959 15:37:17.198334 Dram Type= 6, Freq= 0, CH_0, rank 1
7960 15:37:17.202105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 15:37:17.202185 ==
7962 15:37:17.205037 [Gating] SW mode calibration
7963 15:37:17.211888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7964 15:37:17.218592 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7965 15:37:17.221587 1 4 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7966 15:37:17.225338 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7967 15:37:17.232059 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7968 15:37:17.235179 1 4 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7969 15:37:17.238779 1 4 16 | B1->B0 | 2d2d 3736 | 1 1 | (1 1) (1 1)
7970 15:37:17.245253 1 4 20 | B1->B0 | 3434 3938 | 1 1 | (1 1) (1 1)
7971 15:37:17.248578 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7972 15:37:17.251905 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7973 15:37:17.258374 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7974 15:37:17.261442 1 5 4 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7975 15:37:17.265256 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 1)
7976 15:37:17.271801 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (0 1)
7977 15:37:17.274818 1 5 16 | B1->B0 | 2e2e 2d2d | 0 1 | (0 0) (0 0)
7978 15:37:17.278046 1 5 20 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
7979 15:37:17.285152 1 5 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7980 15:37:17.288453 1 5 28 | B1->B0 | 2323 1c1c | 0 1 | (0 0) (0 0)
7981 15:37:17.291452 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7982 15:37:17.298189 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7983 15:37:17.301294 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7984 15:37:17.305315 1 6 12 | B1->B0 | 2929 3635 | 0 1 | (1 1) (0 0)
7985 15:37:17.311559 1 6 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7986 15:37:17.314728 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 15:37:17.318127 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 15:37:17.321560 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 15:37:17.328089 1 7 0 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7990 15:37:17.331295 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 15:37:17.334901 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 15:37:17.341116 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 15:37:17.344953 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7994 15:37:17.348007 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7995 15:37:17.354606 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 15:37:17.357792 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 15:37:17.361579 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 15:37:17.367814 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 15:37:17.371705 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 15:37:17.375027 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 15:37:17.381110 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 15:37:17.384834 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 15:37:17.388218 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 15:37:17.394595 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 15:37:17.397777 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 15:37:17.401558 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 15:37:17.407844 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 15:37:17.411730 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8009 15:37:17.414973 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8010 15:37:17.421478 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 15:37:17.421586 Total UI for P1: 0, mck2ui 16
8012 15:37:17.427600 best dqsien dly found for B0: ( 1, 9, 14)
8013 15:37:17.427679 Total UI for P1: 0, mck2ui 16
8014 15:37:17.431364 best dqsien dly found for B1: ( 1, 9, 16)
8015 15:37:17.434264 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8016 15:37:17.441206 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8017 15:37:17.441314
8018 15:37:17.444249 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8019 15:37:17.448016 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8020 15:37:17.451099 [Gating] SW calibration Done
8021 15:37:17.451198 ==
8022 15:37:17.454361 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 15:37:17.458010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 15:37:17.458111 ==
8025 15:37:17.460925 RX Vref Scan: 0
8026 15:37:17.461030
8027 15:37:17.461110 RX Vref 0 -> 0, step: 1
8028 15:37:17.461172
8029 15:37:17.464413 RX Delay 0 -> 252, step: 8
8030 15:37:17.467947 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8031 15:37:17.471108 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8032 15:37:17.477495 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8033 15:37:17.481366 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8034 15:37:17.484484 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8035 15:37:17.487644 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8036 15:37:17.490877 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8037 15:37:17.497989 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8038 15:37:17.501023 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8039 15:37:17.504211 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8040 15:37:17.508058 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8041 15:37:17.511243 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8042 15:37:17.517929 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8043 15:37:17.521328 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8044 15:37:17.524546 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8045 15:37:17.527694 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8046 15:37:17.527762 ==
8047 15:37:17.530929 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 15:37:17.538003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 15:37:17.538103 ==
8050 15:37:17.538191 DQS Delay:
8051 15:37:17.541125 DQS0 = 0, DQS1 = 0
8052 15:37:17.541199 DQM Delay:
8053 15:37:17.541260 DQM0 = 137, DQM1 = 131
8054 15:37:17.544233 DQ Delay:
8055 15:37:17.547649 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8056 15:37:17.551114 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8057 15:37:17.554177 DQ8 =123, DQ9 =123, DQ10 =131, DQ11 =123
8058 15:37:17.557894 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8059 15:37:17.557995
8060 15:37:17.558083
8061 15:37:17.558149 ==
8062 15:37:17.560966 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 15:37:17.564042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 15:37:17.567726 ==
8065 15:37:17.567828
8066 15:37:17.567916
8067 15:37:17.567988 TX Vref Scan disable
8068 15:37:17.571247 == TX Byte 0 ==
8069 15:37:17.573987 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8070 15:37:17.577627 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8071 15:37:17.580803 == TX Byte 1 ==
8072 15:37:17.584133 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8073 15:37:17.587723 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8074 15:37:17.587838 ==
8075 15:37:17.590959 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 15:37:17.597436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 15:37:17.597521 ==
8078 15:37:17.610404
8079 15:37:17.613878 TX Vref early break, caculate TX vref
8080 15:37:17.617135 TX Vref=16, minBit 1, minWin=23, winSum=392
8081 15:37:17.620248 TX Vref=18, minBit 1, minWin=23, winSum=401
8082 15:37:17.623335 TX Vref=20, minBit 0, minWin=24, winSum=409
8083 15:37:17.626586 TX Vref=22, minBit 1, minWin=25, winSum=418
8084 15:37:17.630281 TX Vref=24, minBit 1, minWin=25, winSum=426
8085 15:37:17.636887 TX Vref=26, minBit 1, minWin=25, winSum=431
8086 15:37:17.640111 TX Vref=28, minBit 0, minWin=26, winSum=426
8087 15:37:17.643183 TX Vref=30, minBit 1, minWin=25, winSum=415
8088 15:37:17.646951 TX Vref=32, minBit 0, minWin=25, winSum=412
8089 15:37:17.650294 TX Vref=34, minBit 0, minWin=24, winSum=401
8090 15:37:17.656487 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8091 15:37:17.656570
8092 15:37:17.660053 Final TX Range 0 Vref 28
8093 15:37:17.660135
8094 15:37:17.660199 ==
8095 15:37:17.663377 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 15:37:17.666863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 15:37:17.666965 ==
8098 15:37:17.667059
8099 15:37:17.667151
8100 15:37:17.669919 TX Vref Scan disable
8101 15:37:17.676371 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8102 15:37:17.676454 == TX Byte 0 ==
8103 15:37:17.680247 u2DelayCellOfst[0]=13 cells (4 PI)
8104 15:37:17.683388 u2DelayCellOfst[1]=13 cells (4 PI)
8105 15:37:17.686242 u2DelayCellOfst[2]=10 cells (3 PI)
8106 15:37:17.690321 u2DelayCellOfst[3]=10 cells (3 PI)
8107 15:37:17.693450 u2DelayCellOfst[4]=6 cells (2 PI)
8108 15:37:17.696527 u2DelayCellOfst[5]=0 cells (0 PI)
8109 15:37:17.700075 u2DelayCellOfst[6]=16 cells (5 PI)
8110 15:37:17.703291 u2DelayCellOfst[7]=16 cells (5 PI)
8111 15:37:17.706258 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8112 15:37:17.709434 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8113 15:37:17.713306 == TX Byte 1 ==
8114 15:37:17.713409 u2DelayCellOfst[8]=0 cells (0 PI)
8115 15:37:17.716392 u2DelayCellOfst[9]=0 cells (0 PI)
8116 15:37:17.719512 u2DelayCellOfst[10]=6 cells (2 PI)
8117 15:37:17.722723 u2DelayCellOfst[11]=3 cells (1 PI)
8118 15:37:17.726479 u2DelayCellOfst[12]=10 cells (3 PI)
8119 15:37:17.729641 u2DelayCellOfst[13]=10 cells (3 PI)
8120 15:37:17.732917 u2DelayCellOfst[14]=13 cells (4 PI)
8121 15:37:17.736119 u2DelayCellOfst[15]=13 cells (4 PI)
8122 15:37:17.739768 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8123 15:37:17.746173 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8124 15:37:17.746255 DramC Write-DBI on
8125 15:37:17.746320 ==
8126 15:37:17.749360 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 15:37:17.752626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 15:37:17.755913 ==
8129 15:37:17.755998
8130 15:37:17.756065
8131 15:37:17.756124 TX Vref Scan disable
8132 15:37:17.759912 == TX Byte 0 ==
8133 15:37:17.762877 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8134 15:37:17.766694 == TX Byte 1 ==
8135 15:37:17.769735 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8136 15:37:17.773437 DramC Write-DBI off
8137 15:37:17.773537
8138 15:37:17.773626 [DATLAT]
8139 15:37:17.773723 Freq=1600, CH0 RK1
8140 15:37:17.773810
8141 15:37:17.776113 DATLAT Default: 0xf
8142 15:37:17.776184 0, 0xFFFF, sum = 0
8143 15:37:17.779613 1, 0xFFFF, sum = 0
8144 15:37:17.782803 2, 0xFFFF, sum = 0
8145 15:37:17.782907 3, 0xFFFF, sum = 0
8146 15:37:17.785949 4, 0xFFFF, sum = 0
8147 15:37:17.786061 5, 0xFFFF, sum = 0
8148 15:37:17.789881 6, 0xFFFF, sum = 0
8149 15:37:17.789985 7, 0xFFFF, sum = 0
8150 15:37:17.793079 8, 0xFFFF, sum = 0
8151 15:37:17.793161 9, 0xFFFF, sum = 0
8152 15:37:17.796385 10, 0xFFFF, sum = 0
8153 15:37:17.796465 11, 0xFFFF, sum = 0
8154 15:37:17.799529 12, 0xFFFF, sum = 0
8155 15:37:17.799641 13, 0xFFFF, sum = 0
8156 15:37:17.803080 14, 0x0, sum = 1
8157 15:37:17.803187 15, 0x0, sum = 2
8158 15:37:17.806074 16, 0x0, sum = 3
8159 15:37:17.806181 17, 0x0, sum = 4
8160 15:37:17.809944 best_step = 15
8161 15:37:17.810048
8162 15:37:17.810140 ==
8163 15:37:17.813313 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 15:37:17.815996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 15:37:17.816073 ==
8166 15:37:17.816139 RX Vref Scan: 0
8167 15:37:17.819355
8168 15:37:17.819461 RX Vref 0 -> 0, step: 1
8169 15:37:17.819553
8170 15:37:17.822873 RX Delay 27 -> 252, step: 4
8171 15:37:17.826001 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8172 15:37:17.833004 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8173 15:37:17.836317 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8174 15:37:17.839419 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8175 15:37:17.842596 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8176 15:37:17.846401 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8177 15:37:17.852688 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8178 15:37:17.855959 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8179 15:37:17.859788 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8180 15:37:17.863073 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8181 15:37:17.866257 iDelay=191, Bit 10, Center 128 (79 ~ 178) 100
8182 15:37:17.872664 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8183 15:37:17.876503 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8184 15:37:17.879597 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8185 15:37:17.882603 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8186 15:37:17.886108 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8187 15:37:17.886190 ==
8188 15:37:17.889381 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 15:37:17.896178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 15:37:17.896261 ==
8191 15:37:17.896326 DQS Delay:
8192 15:37:17.899347 DQS0 = 0, DQS1 = 0
8193 15:37:17.899455 DQM Delay:
8194 15:37:17.902559 DQM0 = 134, DQM1 = 127
8195 15:37:17.902640 DQ Delay:
8196 15:37:17.906383 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8197 15:37:17.909529 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8198 15:37:17.912677 DQ8 =120, DQ9 =116, DQ10 =128, DQ11 =118
8199 15:37:17.915934 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8200 15:37:17.916015
8201 15:37:17.916080
8202 15:37:17.916140
8203 15:37:17.919528 [DramC_TX_OE_Calibration] TA2
8204 15:37:17.922818 Original DQ_B0 (3 6) =30, OEN = 27
8205 15:37:17.925910 Original DQ_B1 (3 6) =30, OEN = 27
8206 15:37:17.929164 24, 0x0, End_B0=24 End_B1=24
8207 15:37:17.929247 25, 0x0, End_B0=25 End_B1=25
8208 15:37:17.932684 26, 0x0, End_B0=26 End_B1=26
8209 15:37:17.936060 27, 0x0, End_B0=27 End_B1=27
8210 15:37:17.939697 28, 0x0, End_B0=28 End_B1=28
8211 15:37:17.942803 29, 0x0, End_B0=29 End_B1=29
8212 15:37:17.942884 30, 0x0, End_B0=30 End_B1=30
8213 15:37:17.945762 31, 0x4141, End_B0=30 End_B1=30
8214 15:37:17.949279 Byte0 end_step=30 best_step=27
8215 15:37:17.953054 Byte1 end_step=30 best_step=27
8216 15:37:17.956074 Byte0 TX OE(2T, 0.5T) = (3, 3)
8217 15:37:17.959141 Byte1 TX OE(2T, 0.5T) = (3, 3)
8218 15:37:17.959223
8219 15:37:17.959288
8220 15:37:17.966244 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8221 15:37:17.969414 CH0 RK1: MR19=303, MR18=2008
8222 15:37:17.975660 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8223 15:37:17.978915 [RxdqsGatingPostProcess] freq 1600
8224 15:37:17.982795 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8225 15:37:17.986009 best DQS0 dly(2T, 0.5T) = (1, 1)
8226 15:37:17.989222 best DQS1 dly(2T, 0.5T) = (1, 1)
8227 15:37:17.992252 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8228 15:37:17.995918 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8229 15:37:17.999226 best DQS0 dly(2T, 0.5T) = (1, 1)
8230 15:37:18.002683 best DQS1 dly(2T, 0.5T) = (1, 1)
8231 15:37:18.005730 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8232 15:37:18.008896 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8233 15:37:18.012502 Pre-setting of DQS Precalculation
8234 15:37:18.015777 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8235 15:37:18.015852 ==
8236 15:37:18.019148 Dram Type= 6, Freq= 0, CH_1, rank 0
8237 15:37:18.022202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 15:37:18.025376 ==
8239 15:37:18.029282 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8240 15:37:18.032044 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8241 15:37:18.038868 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8242 15:37:18.042468 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8243 15:37:18.052788 [CA 0] Center 41 (12~71) winsize 60
8244 15:37:18.056419 [CA 1] Center 41 (12~71) winsize 60
8245 15:37:18.059161 [CA 2] Center 38 (9~68) winsize 60
8246 15:37:18.062632 [CA 3] Center 37 (9~66) winsize 58
8247 15:37:18.066175 [CA 4] Center 37 (8~67) winsize 60
8248 15:37:18.069173 [CA 5] Center 36 (7~66) winsize 60
8249 15:37:18.069252
8250 15:37:18.072653 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8251 15:37:18.072756
8252 15:37:18.075878 [CATrainingPosCal] consider 1 rank data
8253 15:37:18.079448 u2DelayCellTimex100 = 290/100 ps
8254 15:37:18.082707 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8255 15:37:18.089200 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8256 15:37:18.092379 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8257 15:37:18.095806 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8258 15:37:18.099120 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8259 15:37:18.102363 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8260 15:37:18.102446
8261 15:37:18.106051 CA PerBit enable=1, Macro0, CA PI delay=36
8262 15:37:18.106133
8263 15:37:18.108970 [CBTSetCACLKResult] CA Dly = 36
8264 15:37:18.112465 CS Dly: 10 (0~41)
8265 15:37:18.115945 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8266 15:37:18.118953 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8267 15:37:18.119035 ==
8268 15:37:18.122388 Dram Type= 6, Freq= 0, CH_1, rank 1
8269 15:37:18.126180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 15:37:18.126260 ==
8271 15:37:18.132592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8272 15:37:18.135980 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8273 15:37:18.142294 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8274 15:37:18.146057 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8275 15:37:18.156167 [CA 0] Center 42 (12~72) winsize 61
8276 15:37:18.159068 [CA 1] Center 41 (12~71) winsize 60
8277 15:37:18.162895 [CA 2] Center 38 (9~68) winsize 60
8278 15:37:18.166111 [CA 3] Center 37 (8~67) winsize 60
8279 15:37:18.169320 [CA 4] Center 38 (8~68) winsize 61
8280 15:37:18.172400 [CA 5] Center 37 (8~67) winsize 60
8281 15:37:18.172481
8282 15:37:18.176108 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8283 15:37:18.176190
8284 15:37:18.179057 [CATrainingPosCal] consider 2 rank data
8285 15:37:18.182557 u2DelayCellTimex100 = 290/100 ps
8286 15:37:18.186043 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8287 15:37:18.192822 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8288 15:37:18.196149 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8289 15:37:18.199297 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8290 15:37:18.202479 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8291 15:37:18.205619 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8292 15:37:18.205715
8293 15:37:18.209554 CA PerBit enable=1, Macro0, CA PI delay=37
8294 15:37:18.209634
8295 15:37:18.212744 [CBTSetCACLKResult] CA Dly = 37
8296 15:37:18.212826 CS Dly: 11 (0~44)
8297 15:37:18.219206 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8298 15:37:18.222316 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8299 15:37:18.222397
8300 15:37:18.225859 ----->DramcWriteLeveling(PI) begin...
8301 15:37:18.225959 ==
8302 15:37:18.228946 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 15:37:18.232282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 15:37:18.235985 ==
8305 15:37:18.236066 Write leveling (Byte 0): 24 => 24
8306 15:37:18.238988 Write leveling (Byte 1): 28 => 28
8307 15:37:18.242578 DramcWriteLeveling(PI) end<-----
8308 15:37:18.242658
8309 15:37:18.242722 ==
8310 15:37:18.245671 Dram Type= 6, Freq= 0, CH_1, rank 0
8311 15:37:18.252506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 15:37:18.252588 ==
8313 15:37:18.252652 [Gating] SW mode calibration
8314 15:37:18.262527 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8315 15:37:18.265728 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8316 15:37:18.269419 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 15:37:18.275855 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 15:37:18.279123 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8319 15:37:18.282238 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8320 15:37:18.289282 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 15:37:18.292208 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 15:37:18.295817 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 15:37:18.302464 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 15:37:18.305549 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 15:37:18.308840 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 15:37:18.315407 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
8327 15:37:18.319167 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
8328 15:37:18.322284 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 15:37:18.329010 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 15:37:18.332256 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 15:37:18.335602 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 15:37:18.342016 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 15:37:18.345453 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 15:37:18.349069 1 6 8 | B1->B0 | 2323 4040 | 0 0 | (0 0) (1 1)
8335 15:37:18.355106 1 6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8336 15:37:18.358751 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 15:37:18.362196 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 15:37:18.368283 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 15:37:18.371582 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 15:37:18.375248 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 15:37:18.381674 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 15:37:18.384841 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8343 15:37:18.388591 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8344 15:37:18.394823 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8345 15:37:18.398585 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 15:37:18.401708 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 15:37:18.405485 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 15:37:18.411806 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 15:37:18.414850 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 15:37:18.418668 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 15:37:18.424890 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 15:37:18.428779 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 15:37:18.431910 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 15:37:18.438790 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 15:37:18.442048 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 15:37:18.445351 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 15:37:18.451783 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 15:37:18.454991 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8359 15:37:18.458486 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8360 15:37:18.465038 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 15:37:18.465150 Total UI for P1: 0, mck2ui 16
8362 15:37:18.471630 best dqsien dly found for B0: ( 1, 9, 10)
8363 15:37:18.471724 Total UI for P1: 0, mck2ui 16
8364 15:37:18.478469 best dqsien dly found for B1: ( 1, 9, 10)
8365 15:37:18.481705 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8366 15:37:18.485185 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8367 15:37:18.485271
8368 15:37:18.488585 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8369 15:37:18.491474 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8370 15:37:18.495352 [Gating] SW calibration Done
8371 15:37:18.495445 ==
8372 15:37:18.498480 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 15:37:18.501593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 15:37:18.501677 ==
8375 15:37:18.504735 RX Vref Scan: 0
8376 15:37:18.504818
8377 15:37:18.504883 RX Vref 0 -> 0, step: 1
8378 15:37:18.504943
8379 15:37:18.508656 RX Delay 0 -> 252, step: 8
8380 15:37:18.511684 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8381 15:37:18.515321 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8382 15:37:18.522050 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8383 15:37:18.525167 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8384 15:37:18.528181 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8385 15:37:18.531684 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8386 15:37:18.534918 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8387 15:37:18.541339 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8388 15:37:18.545242 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8389 15:37:18.548447 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8390 15:37:18.551721 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8391 15:37:18.554911 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8392 15:37:18.561304 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8393 15:37:18.565111 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8394 15:37:18.568201 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8395 15:37:18.571467 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8396 15:37:18.571579 ==
8397 15:37:18.574589 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 15:37:18.581337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 15:37:18.581450 ==
8400 15:37:18.581519 DQS Delay:
8401 15:37:18.585063 DQS0 = 0, DQS1 = 0
8402 15:37:18.585149 DQM Delay:
8403 15:37:18.588092 DQM0 = 136, DQM1 = 132
8404 15:37:18.588176 DQ Delay:
8405 15:37:18.591124 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8406 15:37:18.594630 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8407 15:37:18.598054 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8408 15:37:18.601344 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8409 15:37:18.601426
8410 15:37:18.601491
8411 15:37:18.601551 ==
8412 15:37:18.604657 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 15:37:18.611050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 15:37:18.611133 ==
8415 15:37:18.611198
8416 15:37:18.611257
8417 15:37:18.611315 TX Vref Scan disable
8418 15:37:18.614335 == TX Byte 0 ==
8419 15:37:18.617980 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8420 15:37:18.621114 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8421 15:37:18.624812 == TX Byte 1 ==
8422 15:37:18.627985 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8423 15:37:18.631195 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8424 15:37:18.634943 ==
8425 15:37:18.637905 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 15:37:18.641001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 15:37:18.641084 ==
8428 15:37:18.653671
8429 15:37:18.656966 TX Vref early break, caculate TX vref
8430 15:37:18.660120 TX Vref=16, minBit 11, minWin=22, winSum=378
8431 15:37:18.663357 TX Vref=18, minBit 1, minWin=23, winSum=384
8432 15:37:18.666511 TX Vref=20, minBit 0, minWin=23, winSum=397
8433 15:37:18.670387 TX Vref=22, minBit 6, minWin=24, winSum=409
8434 15:37:18.673533 TX Vref=24, minBit 0, minWin=25, winSum=418
8435 15:37:18.679865 TX Vref=26, minBit 0, minWin=26, winSum=426
8436 15:37:18.683037 TX Vref=28, minBit 0, minWin=25, winSum=428
8437 15:37:18.686600 TX Vref=30, minBit 10, minWin=25, winSum=423
8438 15:37:18.690226 TX Vref=32, minBit 0, minWin=24, winSum=411
8439 15:37:18.693271 TX Vref=34, minBit 10, minWin=23, winSum=402
8440 15:37:18.699762 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
8441 15:37:18.699860
8442 15:37:18.703456 Final TX Range 0 Vref 26
8443 15:37:18.703566
8444 15:37:18.703650 ==
8445 15:37:18.706562 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 15:37:18.710048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 15:37:18.710136 ==
8448 15:37:18.710202
8449 15:37:18.710294
8450 15:37:18.713018 TX Vref Scan disable
8451 15:37:18.719532 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8452 15:37:18.719621 == TX Byte 0 ==
8453 15:37:18.723261 u2DelayCellOfst[0]=16 cells (5 PI)
8454 15:37:18.726255 u2DelayCellOfst[1]=10 cells (3 PI)
8455 15:37:18.729910 u2DelayCellOfst[2]=0 cells (0 PI)
8456 15:37:18.733020 u2DelayCellOfst[3]=3 cells (1 PI)
8457 15:37:18.736270 u2DelayCellOfst[4]=10 cells (3 PI)
8458 15:37:18.739466 u2DelayCellOfst[5]=16 cells (5 PI)
8459 15:37:18.743109 u2DelayCellOfst[6]=16 cells (5 PI)
8460 15:37:18.746124 u2DelayCellOfst[7]=6 cells (2 PI)
8461 15:37:18.749900 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8462 15:37:18.753038 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8463 15:37:18.756311 == TX Byte 1 ==
8464 15:37:18.759455 u2DelayCellOfst[8]=0 cells (0 PI)
8465 15:37:18.759557 u2DelayCellOfst[9]=3 cells (1 PI)
8466 15:37:18.762721 u2DelayCellOfst[10]=13 cells (4 PI)
8467 15:37:18.765936 u2DelayCellOfst[11]=6 cells (2 PI)
8468 15:37:18.769189 u2DelayCellOfst[12]=16 cells (5 PI)
8469 15:37:18.773010 u2DelayCellOfst[13]=16 cells (5 PI)
8470 15:37:18.776038 u2DelayCellOfst[14]=16 cells (5 PI)
8471 15:37:18.779735 u2DelayCellOfst[15]=16 cells (5 PI)
8472 15:37:18.782865 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8473 15:37:18.789656 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8474 15:37:18.789759 DramC Write-DBI on
8475 15:37:18.789854 ==
8476 15:37:18.792777 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 15:37:18.796369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 15:37:18.799416 ==
8479 15:37:18.799514
8480 15:37:18.799612
8481 15:37:18.799674 TX Vref Scan disable
8482 15:37:18.803291 == TX Byte 0 ==
8483 15:37:18.806523 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8484 15:37:18.809585 == TX Byte 1 ==
8485 15:37:18.812885 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8486 15:37:18.816710 DramC Write-DBI off
8487 15:37:18.816815
8488 15:37:18.816906 [DATLAT]
8489 15:37:18.816998 Freq=1600, CH1 RK0
8490 15:37:18.817086
8491 15:37:18.819964 DATLAT Default: 0xf
8492 15:37:18.820033 0, 0xFFFF, sum = 0
8493 15:37:18.822905 1, 0xFFFF, sum = 0
8494 15:37:18.822975 2, 0xFFFF, sum = 0
8495 15:37:18.826278 3, 0xFFFF, sum = 0
8496 15:37:18.829527 4, 0xFFFF, sum = 0
8497 15:37:18.829602 5, 0xFFFF, sum = 0
8498 15:37:18.832942 6, 0xFFFF, sum = 0
8499 15:37:18.833045 7, 0xFFFF, sum = 0
8500 15:37:18.836221 8, 0xFFFF, sum = 0
8501 15:37:18.836298 9, 0xFFFF, sum = 0
8502 15:37:18.839355 10, 0xFFFF, sum = 0
8503 15:37:18.839458 11, 0xFFFF, sum = 0
8504 15:37:18.842831 12, 0xFFFF, sum = 0
8505 15:37:18.842923 13, 0xFFFF, sum = 0
8506 15:37:18.845827 14, 0x0, sum = 1
8507 15:37:18.845909 15, 0x0, sum = 2
8508 15:37:18.849242 16, 0x0, sum = 3
8509 15:37:18.849349 17, 0x0, sum = 4
8510 15:37:18.853087 best_step = 15
8511 15:37:18.853162
8512 15:37:18.853227 ==
8513 15:37:18.856021 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 15:37:18.859797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 15:37:18.859879 ==
8516 15:37:18.862990 RX Vref Scan: 1
8517 15:37:18.863066
8518 15:37:18.863128 Set Vref Range= 24 -> 127
8519 15:37:18.863186
8520 15:37:18.866202 RX Vref 24 -> 127, step: 1
8521 15:37:18.866300
8522 15:37:18.869462 RX Delay 27 -> 252, step: 4
8523 15:37:18.869560
8524 15:37:18.872662 Set Vref, RX VrefLevel [Byte0]: 24
8525 15:37:18.875829 [Byte1]: 24
8526 15:37:18.875906
8527 15:37:18.879697 Set Vref, RX VrefLevel [Byte0]: 25
8528 15:37:18.882871 [Byte1]: 25
8529 15:37:18.882946
8530 15:37:18.886052 Set Vref, RX VrefLevel [Byte0]: 26
8531 15:37:18.889311 [Byte1]: 26
8532 15:37:18.893133
8533 15:37:18.893212 Set Vref, RX VrefLevel [Byte0]: 27
8534 15:37:18.896911 [Byte1]: 27
8535 15:37:18.900620
8536 15:37:18.900731 Set Vref, RX VrefLevel [Byte0]: 28
8537 15:37:18.904202 [Byte1]: 28
8538 15:37:18.908642
8539 15:37:18.908724 Set Vref, RX VrefLevel [Byte0]: 29
8540 15:37:18.911905 [Byte1]: 29
8541 15:37:18.915706
8542 15:37:18.915787 Set Vref, RX VrefLevel [Byte0]: 30
8543 15:37:18.918955 [Byte1]: 30
8544 15:37:18.923286
8545 15:37:18.923367 Set Vref, RX VrefLevel [Byte0]: 31
8546 15:37:18.926509 [Byte1]: 31
8547 15:37:18.930926
8548 15:37:18.931005 Set Vref, RX VrefLevel [Byte0]: 32
8549 15:37:18.934486 [Byte1]: 32
8550 15:37:18.938190
8551 15:37:18.938270 Set Vref, RX VrefLevel [Byte0]: 33
8552 15:37:18.941762 [Byte1]: 33
8553 15:37:18.946101
8554 15:37:18.946180 Set Vref, RX VrefLevel [Byte0]: 34
8555 15:37:18.949196 [Byte1]: 34
8556 15:37:18.953549
8557 15:37:18.953630 Set Vref, RX VrefLevel [Byte0]: 35
8558 15:37:18.957003 [Byte1]: 35
8559 15:37:18.961009
8560 15:37:18.961089 Set Vref, RX VrefLevel [Byte0]: 36
8561 15:37:18.964319 [Byte1]: 36
8562 15:37:18.968629
8563 15:37:18.968709 Set Vref, RX VrefLevel [Byte0]: 37
8564 15:37:18.971879 [Byte1]: 37
8565 15:37:18.976208
8566 15:37:18.976289 Set Vref, RX VrefLevel [Byte0]: 38
8567 15:37:18.979463 [Byte1]: 38
8568 15:37:18.984049
8569 15:37:18.984128 Set Vref, RX VrefLevel [Byte0]: 39
8570 15:37:18.986934 [Byte1]: 39
8571 15:37:18.990970
8572 15:37:18.991050 Set Vref, RX VrefLevel [Byte0]: 40
8573 15:37:18.994788 [Byte1]: 40
8574 15:37:18.998572
8575 15:37:18.998651 Set Vref, RX VrefLevel [Byte0]: 41
8576 15:37:19.002393 [Byte1]: 41
8577 15:37:19.006254
8578 15:37:19.006334 Set Vref, RX VrefLevel [Byte0]: 42
8579 15:37:19.009821 [Byte1]: 42
8580 15:37:19.014126
8581 15:37:19.014207 Set Vref, RX VrefLevel [Byte0]: 43
8582 15:37:19.017309 [Byte1]: 43
8583 15:37:19.021610
8584 15:37:19.021716 Set Vref, RX VrefLevel [Byte0]: 44
8585 15:37:19.024794 [Byte1]: 44
8586 15:37:19.028617
8587 15:37:19.028696 Set Vref, RX VrefLevel [Byte0]: 45
8588 15:37:19.031921 [Byte1]: 45
8589 15:37:19.036391
8590 15:37:19.036476 Set Vref, RX VrefLevel [Byte0]: 46
8591 15:37:19.039599 [Byte1]: 46
8592 15:37:19.043875
8593 15:37:19.043958 Set Vref, RX VrefLevel [Byte0]: 47
8594 15:37:19.047417 [Byte1]: 47
8595 15:37:19.051432
8596 15:37:19.051512 Set Vref, RX VrefLevel [Byte0]: 48
8597 15:37:19.054599 [Byte1]: 48
8598 15:37:19.058814
8599 15:37:19.058894 Set Vref, RX VrefLevel [Byte0]: 49
8600 15:37:19.061989 [Byte1]: 49
8601 15:37:19.066269
8602 15:37:19.066349 Set Vref, RX VrefLevel [Byte0]: 50
8603 15:37:19.069963 [Byte1]: 50
8604 15:37:19.074094
8605 15:37:19.074173 Set Vref, RX VrefLevel [Byte0]: 51
8606 15:37:19.077001 [Byte1]: 51
8607 15:37:19.081739
8608 15:37:19.081818 Set Vref, RX VrefLevel [Byte0]: 52
8609 15:37:19.084982 [Byte1]: 52
8610 15:37:19.089308
8611 15:37:19.089388 Set Vref, RX VrefLevel [Byte0]: 53
8612 15:37:19.092214 [Byte1]: 53
8613 15:37:19.096546
8614 15:37:19.096654 Set Vref, RX VrefLevel [Byte0]: 54
8615 15:37:19.099787 [Byte1]: 54
8616 15:37:19.104039
8617 15:37:19.104119 Set Vref, RX VrefLevel [Byte0]: 55
8618 15:37:19.107232 [Byte1]: 55
8619 15:37:19.111790
8620 15:37:19.111869 Set Vref, RX VrefLevel [Byte0]: 56
8621 15:37:19.115313 [Byte1]: 56
8622 15:37:19.119453
8623 15:37:19.119559 Set Vref, RX VrefLevel [Byte0]: 57
8624 15:37:19.122593 [Byte1]: 57
8625 15:37:19.126925
8626 15:37:19.127005 Set Vref, RX VrefLevel [Byte0]: 58
8627 15:37:19.130240 [Byte1]: 58
8628 15:37:19.133966
8629 15:37:19.134069 Set Vref, RX VrefLevel [Byte0]: 59
8630 15:37:19.137708 [Byte1]: 59
8631 15:37:19.142154
8632 15:37:19.142261 Set Vref, RX VrefLevel [Byte0]: 60
8633 15:37:19.145335 [Byte1]: 60
8634 15:37:19.149477
8635 15:37:19.149578 Set Vref, RX VrefLevel [Byte0]: 61
8636 15:37:19.152565 [Byte1]: 61
8637 15:37:19.156541
8638 15:37:19.156647 Set Vref, RX VrefLevel [Byte0]: 62
8639 15:37:19.160448 [Byte1]: 62
8640 15:37:19.164179
8641 15:37:19.164254 Set Vref, RX VrefLevel [Byte0]: 63
8642 15:37:19.167971 [Byte1]: 63
8643 15:37:19.171932
8644 15:37:19.172002 Set Vref, RX VrefLevel [Byte0]: 64
8645 15:37:19.175075 [Byte1]: 64
8646 15:37:19.179343
8647 15:37:19.179440 Set Vref, RX VrefLevel [Byte0]: 65
8648 15:37:19.182887 [Byte1]: 65
8649 15:37:19.186942
8650 15:37:19.187026 Set Vref, RX VrefLevel [Byte0]: 66
8651 15:37:19.190417 [Byte1]: 66
8652 15:37:19.194614
8653 15:37:19.194696 Set Vref, RX VrefLevel [Byte0]: 67
8654 15:37:19.197867 [Byte1]: 67
8655 15:37:19.202360
8656 15:37:19.202444 Set Vref, RX VrefLevel [Byte0]: 68
8657 15:37:19.205516 [Byte1]: 68
8658 15:37:19.209863
8659 15:37:19.209945 Set Vref, RX VrefLevel [Byte0]: 69
8660 15:37:19.213188 [Byte1]: 69
8661 15:37:19.216947
8662 15:37:19.217053 Set Vref, RX VrefLevel [Byte0]: 70
8663 15:37:19.220261 [Byte1]: 70
8664 15:37:19.224511
8665 15:37:19.224617 Set Vref, RX VrefLevel [Byte0]: 71
8666 15:37:19.228176 [Byte1]: 71
8667 15:37:19.231924
8668 15:37:19.232005 Set Vref, RX VrefLevel [Byte0]: 72
8669 15:37:19.235727 [Byte1]: 72
8670 15:37:19.239701
8671 15:37:19.239783 Set Vref, RX VrefLevel [Byte0]: 73
8672 15:37:19.242785 [Byte1]: 73
8673 15:37:19.247625
8674 15:37:19.247706 Set Vref, RX VrefLevel [Byte0]: 74
8675 15:37:19.250600 [Byte1]: 74
8676 15:37:19.255112
8677 15:37:19.255193 Set Vref, RX VrefLevel [Byte0]: 75
8678 15:37:19.258191 [Byte1]: 75
8679 15:37:19.262584
8680 15:37:19.262692 Set Vref, RX VrefLevel [Byte0]: 76
8681 15:37:19.265747 [Byte1]: 76
8682 15:37:19.270137
8683 15:37:19.270219 Set Vref, RX VrefLevel [Byte0]: 77
8684 15:37:19.273283 [Byte1]: 77
8685 15:37:19.277230
8686 15:37:19.277311 Set Vref, RX VrefLevel [Byte0]: 78
8687 15:37:19.280375 [Byte1]: 78
8688 15:37:19.285208
8689 15:37:19.285283 Final RX Vref Byte 0 = 62 to rank0
8690 15:37:19.288224 Final RX Vref Byte 1 = 55 to rank0
8691 15:37:19.291403 Final RX Vref Byte 0 = 62 to rank1
8692 15:37:19.294612 Final RX Vref Byte 1 = 55 to rank1==
8693 15:37:19.298295 Dram Type= 6, Freq= 0, CH_1, rank 0
8694 15:37:19.304866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8695 15:37:19.304950 ==
8696 15:37:19.305017 DQS Delay:
8697 15:37:19.305078 DQS0 = 0, DQS1 = 0
8698 15:37:19.307987 DQM Delay:
8699 15:37:19.308056 DQM0 = 134, DQM1 = 131
8700 15:37:19.311100 DQ Delay:
8701 15:37:19.314864 DQ0 =140, DQ1 =130, DQ2 =122, DQ3 =130
8702 15:37:19.318149 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8703 15:37:19.321295 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8704 15:37:19.324516 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8705 15:37:19.324611
8706 15:37:19.324678
8707 15:37:19.324738
8708 15:37:19.327695 [DramC_TX_OE_Calibration] TA2
8709 15:37:19.331455 Original DQ_B0 (3 6) =30, OEN = 27
8710 15:37:19.334473 Original DQ_B1 (3 6) =30, OEN = 27
8711 15:37:19.337979 24, 0x0, End_B0=24 End_B1=24
8712 15:37:19.338060 25, 0x0, End_B0=25 End_B1=25
8713 15:37:19.340995 26, 0x0, End_B0=26 End_B1=26
8714 15:37:19.344315 27, 0x0, End_B0=27 End_B1=27
8715 15:37:19.347831 28, 0x0, End_B0=28 End_B1=28
8716 15:37:19.351002 29, 0x0, End_B0=29 End_B1=29
8717 15:37:19.351083 30, 0x0, End_B0=30 End_B1=30
8718 15:37:19.354414 31, 0x4141, End_B0=30 End_B1=30
8719 15:37:19.358086 Byte0 end_step=30 best_step=27
8720 15:37:19.361035 Byte1 end_step=30 best_step=27
8721 15:37:19.364135 Byte0 TX OE(2T, 0.5T) = (3, 3)
8722 15:37:19.367498 Byte1 TX OE(2T, 0.5T) = (3, 3)
8723 15:37:19.367615
8724 15:37:19.367693
8725 15:37:19.374405 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8726 15:37:19.377599 CH1 RK0: MR19=303, MR18=1624
8727 15:37:19.384608 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8728 15:37:19.384690
8729 15:37:19.387857 ----->DramcWriteLeveling(PI) begin...
8730 15:37:19.387938 ==
8731 15:37:19.390705 Dram Type= 6, Freq= 0, CH_1, rank 1
8732 15:37:19.394509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 15:37:19.394590 ==
8734 15:37:19.397736 Write leveling (Byte 0): 27 => 27
8735 15:37:19.400768 Write leveling (Byte 1): 29 => 29
8736 15:37:19.404502 DramcWriteLeveling(PI) end<-----
8737 15:37:19.404582
8738 15:37:19.404644 ==
8739 15:37:19.407755 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 15:37:19.410678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 15:37:19.410759 ==
8742 15:37:19.414352 [Gating] SW mode calibration
8743 15:37:19.420661 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8744 15:37:19.427615 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8745 15:37:19.430741 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 15:37:19.434581 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 15:37:19.440842 1 4 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8748 15:37:19.444556 1 4 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8749 15:37:19.447379 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 15:37:19.453872 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 15:37:19.457608 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 15:37:19.460628 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 15:37:19.467245 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 15:37:19.470698 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8755 15:37:19.474187 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8756 15:37:19.481001 1 5 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8757 15:37:19.484262 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 15:37:19.487416 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 15:37:19.493766 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 15:37:19.497491 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 15:37:19.500469 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 15:37:19.507491 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8763 15:37:19.510654 1 6 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8764 15:37:19.513948 1 6 12 | B1->B0 | 4545 4242 | 0 0 | (0 0) (0 0)
8765 15:37:19.520380 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 15:37:19.523975 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 15:37:19.527055 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 15:37:19.534030 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 15:37:19.537353 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 15:37:19.540635 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8771 15:37:19.547003 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8772 15:37:19.550157 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8773 15:37:19.553762 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8774 15:37:19.560544 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 15:37:19.563937 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 15:37:19.567072 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 15:37:19.570222 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 15:37:19.577245 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 15:37:19.580269 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 15:37:19.584044 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 15:37:19.590358 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 15:37:19.594280 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 15:37:19.597328 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 15:37:19.603457 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 15:37:19.607186 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 15:37:19.610295 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8787 15:37:19.617146 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8788 15:37:19.620326 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8789 15:37:19.623390 Total UI for P1: 0, mck2ui 16
8790 15:37:19.627303 best dqsien dly found for B1: ( 1, 9, 6)
8791 15:37:19.630497 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 15:37:19.633648 Total UI for P1: 0, mck2ui 16
8793 15:37:19.636652 best dqsien dly found for B0: ( 1, 9, 12)
8794 15:37:19.640085 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8795 15:37:19.643780 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8796 15:37:19.643882
8797 15:37:19.649964 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8798 15:37:19.653778 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8799 15:37:19.653883 [Gating] SW calibration Done
8800 15:37:19.656989 ==
8801 15:37:19.660118 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 15:37:19.663581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 15:37:19.663670 ==
8804 15:37:19.663734 RX Vref Scan: 0
8805 15:37:19.663793
8806 15:37:19.667288 RX Vref 0 -> 0, step: 1
8807 15:37:19.667382
8808 15:37:19.670267 RX Delay 0 -> 252, step: 8
8809 15:37:19.673436 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8810 15:37:19.676723 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8811 15:37:19.680415 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8812 15:37:19.686667 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8813 15:37:19.690428 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8814 15:37:19.693607 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8815 15:37:19.696879 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8816 15:37:19.700165 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8817 15:37:19.706775 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8818 15:37:19.710325 iDelay=208, Bit 9, Center 123 (64 ~ 183) 120
8819 15:37:19.713512 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8820 15:37:19.716539 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8821 15:37:19.720231 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8822 15:37:19.726881 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8823 15:37:19.730237 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8824 15:37:19.733587 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8825 15:37:19.733688 ==
8826 15:37:19.736890 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 15:37:19.740165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 15:37:19.740268 ==
8829 15:37:19.743416 DQS Delay:
8830 15:37:19.743516 DQS0 = 0, DQS1 = 0
8831 15:37:19.746572 DQM Delay:
8832 15:37:19.746674 DQM0 = 136, DQM1 = 134
8833 15:37:19.750269 DQ Delay:
8834 15:37:19.753372 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8835 15:37:19.756442 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8836 15:37:19.759647 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8837 15:37:19.763121 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8838 15:37:19.763208
8839 15:37:19.763300
8840 15:37:19.763387 ==
8841 15:37:19.766381 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 15:37:19.770285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 15:37:19.770398 ==
8844 15:37:19.770498
8845 15:37:19.770587
8846 15:37:19.773321 TX Vref Scan disable
8847 15:37:19.776248 == TX Byte 0 ==
8848 15:37:19.779987 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8849 15:37:19.783143 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8850 15:37:19.786711 == TX Byte 1 ==
8851 15:37:19.789983 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8852 15:37:19.793399 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8853 15:37:19.793478 ==
8854 15:37:19.796444 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 15:37:19.799570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 15:37:19.802717 ==
8857 15:37:19.814861
8858 15:37:19.818862 TX Vref early break, caculate TX vref
8859 15:37:19.821914 TX Vref=16, minBit 0, minWin=23, winSum=378
8860 15:37:19.825221 TX Vref=18, minBit 0, minWin=23, winSum=392
8861 15:37:19.828427 TX Vref=20, minBit 0, minWin=24, winSum=399
8862 15:37:19.831545 TX Vref=22, minBit 4, minWin=24, winSum=407
8863 15:37:19.834906 TX Vref=24, minBit 0, minWin=25, winSum=418
8864 15:37:19.841703 TX Vref=26, minBit 0, minWin=25, winSum=426
8865 15:37:19.845210 TX Vref=28, minBit 0, minWin=26, winSum=424
8866 15:37:19.848541 TX Vref=30, minBit 0, minWin=25, winSum=419
8867 15:37:19.851952 TX Vref=32, minBit 1, minWin=25, winSum=413
8868 15:37:19.855114 TX Vref=34, minBit 6, minWin=24, winSum=404
8869 15:37:19.858294 TX Vref=36, minBit 0, minWin=24, winSum=395
8870 15:37:19.865314 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8871 15:37:19.865419
8872 15:37:19.868615 Final TX Range 0 Vref 28
8873 15:37:19.868717
8874 15:37:19.868807 ==
8875 15:37:19.871809 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 15:37:19.875125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 15:37:19.875225 ==
8878 15:37:19.875316
8879 15:37:19.875407
8880 15:37:19.878477 TX Vref Scan disable
8881 15:37:19.885081 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8882 15:37:19.885164 == TX Byte 0 ==
8883 15:37:19.888062 u2DelayCellOfst[0]=16 cells (5 PI)
8884 15:37:19.891581 u2DelayCellOfst[1]=13 cells (4 PI)
8885 15:37:19.895174 u2DelayCellOfst[2]=0 cells (0 PI)
8886 15:37:19.898361 u2DelayCellOfst[3]=6 cells (2 PI)
8887 15:37:19.901694 u2DelayCellOfst[4]=10 cells (3 PI)
8888 15:37:19.904975 u2DelayCellOfst[5]=16 cells (5 PI)
8889 15:37:19.908080 u2DelayCellOfst[6]=20 cells (6 PI)
8890 15:37:19.911905 u2DelayCellOfst[7]=6 cells (2 PI)
8891 15:37:19.915238 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8892 15:37:19.918380 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8893 15:37:19.921561 == TX Byte 1 ==
8894 15:37:19.925000 u2DelayCellOfst[8]=0 cells (0 PI)
8895 15:37:19.925076 u2DelayCellOfst[9]=3 cells (1 PI)
8896 15:37:19.928277 u2DelayCellOfst[10]=10 cells (3 PI)
8897 15:37:19.931653 u2DelayCellOfst[11]=3 cells (1 PI)
8898 15:37:19.934821 u2DelayCellOfst[12]=13 cells (4 PI)
8899 15:37:19.938318 u2DelayCellOfst[13]=16 cells (5 PI)
8900 15:37:19.941540 u2DelayCellOfst[14]=16 cells (5 PI)
8901 15:37:19.944937 u2DelayCellOfst[15]=16 cells (5 PI)
8902 15:37:19.948255 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8903 15:37:19.954868 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8904 15:37:19.954976 DramC Write-DBI on
8905 15:37:19.955069 ==
8906 15:37:19.958108 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 15:37:19.962070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 15:37:19.965272 ==
8909 15:37:19.965382
8910 15:37:19.965474
8911 15:37:19.965566 TX Vref Scan disable
8912 15:37:19.968598 == TX Byte 0 ==
8913 15:37:19.971781 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8914 15:37:19.975137 == TX Byte 1 ==
8915 15:37:19.978475 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8916 15:37:19.981766 DramC Write-DBI off
8917 15:37:19.981874
8918 15:37:19.981972 [DATLAT]
8919 15:37:19.982068 Freq=1600, CH1 RK1
8920 15:37:19.982163
8921 15:37:19.985145 DATLAT Default: 0xf
8922 15:37:19.985246 0, 0xFFFF, sum = 0
8923 15:37:19.988378 1, 0xFFFF, sum = 0
8924 15:37:19.991604 2, 0xFFFF, sum = 0
8925 15:37:19.991690 3, 0xFFFF, sum = 0
8926 15:37:19.995076 4, 0xFFFF, sum = 0
8927 15:37:19.995183 5, 0xFFFF, sum = 0
8928 15:37:19.998287 6, 0xFFFF, sum = 0
8929 15:37:19.998391 7, 0xFFFF, sum = 0
8930 15:37:20.001538 8, 0xFFFF, sum = 0
8931 15:37:20.001643 9, 0xFFFF, sum = 0
8932 15:37:20.004574 10, 0xFFFF, sum = 0
8933 15:37:20.004679 11, 0xFFFF, sum = 0
8934 15:37:20.008072 12, 0xFFFF, sum = 0
8935 15:37:20.008177 13, 0xFFFF, sum = 0
8936 15:37:20.011187 14, 0x0, sum = 1
8937 15:37:20.011292 15, 0x0, sum = 2
8938 15:37:20.015047 16, 0x0, sum = 3
8939 15:37:20.015152 17, 0x0, sum = 4
8940 15:37:20.018124 best_step = 15
8941 15:37:20.018231
8942 15:37:20.018331 ==
8943 15:37:20.021360 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 15:37:20.024569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 15:37:20.024680 ==
8946 15:37:20.027788 RX Vref Scan: 0
8947 15:37:20.027891
8948 15:37:20.027972 RX Vref 0 -> 0, step: 1
8949 15:37:20.028033
8950 15:37:20.031127 RX Delay 19 -> 252, step: 4
8951 15:37:20.034444 iDelay=199, Bit 0, Center 138 (91 ~ 186) 96
8952 15:37:20.041382 iDelay=199, Bit 1, Center 132 (83 ~ 182) 100
8953 15:37:20.044631 iDelay=199, Bit 2, Center 122 (71 ~ 174) 104
8954 15:37:20.047775 iDelay=199, Bit 3, Center 128 (83 ~ 174) 92
8955 15:37:20.051095 iDelay=199, Bit 4, Center 130 (83 ~ 178) 96
8956 15:37:20.054286 iDelay=199, Bit 5, Center 148 (99 ~ 198) 100
8957 15:37:20.060960 iDelay=199, Bit 6, Center 146 (99 ~ 194) 96
8958 15:37:20.064180 iDelay=199, Bit 7, Center 134 (83 ~ 186) 104
8959 15:37:20.067557 iDelay=199, Bit 8, Center 118 (67 ~ 170) 104
8960 15:37:20.070952 iDelay=199, Bit 9, Center 120 (67 ~ 174) 108
8961 15:37:20.074136 iDelay=199, Bit 10, Center 132 (83 ~ 182) 100
8962 15:37:20.081178 iDelay=199, Bit 11, Center 124 (71 ~ 178) 108
8963 15:37:20.084567 iDelay=199, Bit 12, Center 140 (87 ~ 194) 108
8964 15:37:20.087937 iDelay=199, Bit 13, Center 138 (87 ~ 190) 104
8965 15:37:20.091171 iDelay=199, Bit 14, Center 136 (87 ~ 186) 100
8966 15:37:20.094486 iDelay=199, Bit 15, Center 140 (91 ~ 190) 100
8967 15:37:20.097688 ==
8968 15:37:20.100931 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 15:37:20.104350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 15:37:20.104451 ==
8971 15:37:20.104548 DQS Delay:
8972 15:37:20.107452 DQS0 = 0, DQS1 = 0
8973 15:37:20.107545 DQM Delay:
8974 15:37:20.110770 DQM0 = 134, DQM1 = 131
8975 15:37:20.110868 DQ Delay:
8976 15:37:20.113966 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =128
8977 15:37:20.117571 DQ4 =130, DQ5 =148, DQ6 =146, DQ7 =134
8978 15:37:20.120923 DQ8 =118, DQ9 =120, DQ10 =132, DQ11 =124
8979 15:37:20.124531 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8980 15:37:20.124633
8981 15:37:20.124726
8982 15:37:20.124814
8983 15:37:20.127677 [DramC_TX_OE_Calibration] TA2
8984 15:37:20.130742 Original DQ_B0 (3 6) =30, OEN = 27
8985 15:37:20.133846 Original DQ_B1 (3 6) =30, OEN = 27
8986 15:37:20.137053 24, 0x0, End_B0=24 End_B1=24
8987 15:37:20.141037 25, 0x0, End_B0=25 End_B1=25
8988 15:37:20.141120 26, 0x0, End_B0=26 End_B1=26
8989 15:37:20.144336 27, 0x0, End_B0=27 End_B1=27
8990 15:37:20.147511 28, 0x0, End_B0=28 End_B1=28
8991 15:37:20.150758 29, 0x0, End_B0=29 End_B1=29
8992 15:37:20.153738 30, 0x0, End_B0=30 End_B1=30
8993 15:37:20.153843 31, 0x4141, End_B0=30 End_B1=30
8994 15:37:20.157549 Byte0 end_step=30 best_step=27
8995 15:37:20.160431 Byte1 end_step=30 best_step=27
8996 15:37:20.163667 Byte0 TX OE(2T, 0.5T) = (3, 3)
8997 15:37:20.167503 Byte1 TX OE(2T, 0.5T) = (3, 3)
8998 15:37:20.167619
8999 15:37:20.167685
9000 15:37:20.173968 [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
9001 15:37:20.177288 CH1 RK1: MR19=303, MR18=2207
9002 15:37:20.183813 CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16
9003 15:37:20.186912 [RxdqsGatingPostProcess] freq 1600
9004 15:37:20.193593 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9005 15:37:20.193703 best DQS0 dly(2T, 0.5T) = (1, 1)
9006 15:37:20.196931 best DQS1 dly(2T, 0.5T) = (1, 1)
9007 15:37:20.200253 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9008 15:37:20.204081 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9009 15:37:20.206853 best DQS0 dly(2T, 0.5T) = (1, 1)
9010 15:37:20.210203 best DQS1 dly(2T, 0.5T) = (1, 1)
9011 15:37:20.213575 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9012 15:37:20.216890 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9013 15:37:20.220222 Pre-setting of DQS Precalculation
9014 15:37:20.223465 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9015 15:37:20.233841 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9016 15:37:20.239989 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9017 15:37:20.240069
9018 15:37:20.240135
9019 15:37:20.243612 [Calibration Summary] 3200 Mbps
9020 15:37:20.243714 CH 0, Rank 0
9021 15:37:20.246518 SW Impedance : PASS
9022 15:37:20.246621 DUTY Scan : NO K
9023 15:37:20.250363 ZQ Calibration : PASS
9024 15:37:20.253610 Jitter Meter : NO K
9025 15:37:20.253711 CBT Training : PASS
9026 15:37:20.256935 Write leveling : PASS
9027 15:37:20.259906 RX DQS gating : PASS
9028 15:37:20.259985 RX DQ/DQS(RDDQC) : PASS
9029 15:37:20.263620 TX DQ/DQS : PASS
9030 15:37:20.266742 RX DATLAT : PASS
9031 15:37:20.266830 RX DQ/DQS(Engine): PASS
9032 15:37:20.270072 TX OE : PASS
9033 15:37:20.270172 All Pass.
9034 15:37:20.270264
9035 15:37:20.273350 CH 0, Rank 1
9036 15:37:20.273451 SW Impedance : PASS
9037 15:37:20.276646 DUTY Scan : NO K
9038 15:37:20.276747 ZQ Calibration : PASS
9039 15:37:20.279987 Jitter Meter : NO K
9040 15:37:20.283324 CBT Training : PASS
9041 15:37:20.283425 Write leveling : PASS
9042 15:37:20.286729 RX DQS gating : PASS
9043 15:37:20.289887 RX DQ/DQS(RDDQC) : PASS
9044 15:37:20.289988 TX DQ/DQS : PASS
9045 15:37:20.293010 RX DATLAT : PASS
9046 15:37:20.296855 RX DQ/DQS(Engine): PASS
9047 15:37:20.296954 TX OE : PASS
9048 15:37:20.300235 All Pass.
9049 15:37:20.300312
9050 15:37:20.300373 CH 1, Rank 0
9051 15:37:20.303345 SW Impedance : PASS
9052 15:37:20.303439 DUTY Scan : NO K
9053 15:37:20.306371 ZQ Calibration : PASS
9054 15:37:20.309747 Jitter Meter : NO K
9055 15:37:20.309824 CBT Training : PASS
9056 15:37:20.312924 Write leveling : PASS
9057 15:37:20.316424 RX DQS gating : PASS
9058 15:37:20.316510 RX DQ/DQS(RDDQC) : PASS
9059 15:37:20.319890 TX DQ/DQS : PASS
9060 15:37:20.323179 RX DATLAT : PASS
9061 15:37:20.323259 RX DQ/DQS(Engine): PASS
9062 15:37:20.326427 TX OE : PASS
9063 15:37:20.326501 All Pass.
9064 15:37:20.326563
9065 15:37:20.329680 CH 1, Rank 1
9066 15:37:20.329754 SW Impedance : PASS
9067 15:37:20.332955 DUTY Scan : NO K
9068 15:37:20.333047 ZQ Calibration : PASS
9069 15:37:20.336201 Jitter Meter : NO K
9070 15:37:20.339991 CBT Training : PASS
9071 15:37:20.340111 Write leveling : PASS
9072 15:37:20.343245 RX DQS gating : PASS
9073 15:37:20.346599 RX DQ/DQS(RDDQC) : PASS
9074 15:37:20.346700 TX DQ/DQS : PASS
9075 15:37:20.349625 RX DATLAT : PASS
9076 15:37:20.352988 RX DQ/DQS(Engine): PASS
9077 15:37:20.353095 TX OE : PASS
9078 15:37:20.356071 All Pass.
9079 15:37:20.356143
9080 15:37:20.356205 DramC Write-DBI on
9081 15:37:20.359466 PER_BANK_REFRESH: Hybrid Mode
9082 15:37:20.359571 TX_TRACKING: ON
9083 15:37:20.369454 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9084 15:37:20.379212 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9085 15:37:20.386080 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9086 15:37:20.389253 [FAST_K] Save calibration result to emmc
9087 15:37:20.392539 sync common calibartion params.
9088 15:37:20.392652 sync cbt_mode0:1, 1:1
9089 15:37:20.395849 dram_init: ddr_geometry: 2
9090 15:37:20.399569 dram_init: ddr_geometry: 2
9091 15:37:20.399656 dram_init: ddr_geometry: 2
9092 15:37:20.402735 0:dram_rank_size:100000000
9093 15:37:20.405932 1:dram_rank_size:100000000
9094 15:37:20.412534 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9095 15:37:20.412623 DFS_SHUFFLE_HW_MODE: ON
9096 15:37:20.415878 dramc_set_vcore_voltage set vcore to 725000
9097 15:37:20.419279 Read voltage for 1600, 0
9098 15:37:20.419354 Vio18 = 0
9099 15:37:20.422645 Vcore = 725000
9100 15:37:20.422722 Vdram = 0
9101 15:37:20.422785 Vddq = 0
9102 15:37:20.426122 Vmddr = 0
9103 15:37:20.426216 switch to 3200 Mbps bootup
9104 15:37:20.428896 [DramcRunTimeConfig]
9105 15:37:20.428970 PHYPLL
9106 15:37:20.432079 DPM_CONTROL_AFTERK: ON
9107 15:37:20.432162 PER_BANK_REFRESH: ON
9108 15:37:20.435925 REFRESH_OVERHEAD_REDUCTION: ON
9109 15:37:20.439163 CMD_PICG_NEW_MODE: OFF
9110 15:37:20.439272 XRTWTW_NEW_MODE: ON
9111 15:37:20.442453 XRTRTR_NEW_MODE: ON
9112 15:37:20.442549 TX_TRACKING: ON
9113 15:37:20.445603 RDSEL_TRACKING: OFF
9114 15:37:20.449307 DQS Precalculation for DVFS: ON
9115 15:37:20.449408 RX_TRACKING: OFF
9116 15:37:20.452432 HW_GATING DBG: ON
9117 15:37:20.452504 ZQCS_ENABLE_LP4: ON
9118 15:37:20.455885 RX_PICG_NEW_MODE: ON
9119 15:37:20.455994 TX_PICG_NEW_MODE: ON
9120 15:37:20.459120 ENABLE_RX_DCM_DPHY: ON
9121 15:37:20.462305 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9122 15:37:20.465634 DUMMY_READ_FOR_TRACKING: OFF
9123 15:37:20.465734 !!! SPM_CONTROL_AFTERK: OFF
9124 15:37:20.468818 !!! SPM could not control APHY
9125 15:37:20.472650 IMPEDANCE_TRACKING: ON
9126 15:37:20.472752 TEMP_SENSOR: ON
9127 15:37:20.475691 HW_SAVE_FOR_SR: OFF
9128 15:37:20.478894 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9129 15:37:20.482008 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9130 15:37:20.485672 Read ODT Tracking: ON
9131 15:37:20.485746 Refresh Rate DeBounce: ON
9132 15:37:20.489240 DFS_NO_QUEUE_FLUSH: ON
9133 15:37:20.492342 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9134 15:37:20.492422 ENABLE_DFS_RUNTIME_MRW: OFF
9135 15:37:20.496087 DDR_RESERVE_NEW_MODE: ON
9136 15:37:20.499364 MR_CBT_SWITCH_FREQ: ON
9137 15:37:20.499462 =========================
9138 15:37:20.519922 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9139 15:37:20.523227 dram_init: ddr_geometry: 2
9140 15:37:20.541236 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9141 15:37:20.544401 dram_init: dram init end (result: 0)
9142 15:37:20.551124 DRAM-K: Full calibration passed in 24458 msecs
9143 15:37:20.554188 MRC: failed to locate region type 0.
9144 15:37:20.554304 DRAM rank0 size:0x100000000,
9145 15:37:20.558125 DRAM rank1 size=0x100000000
9146 15:37:20.567751 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9147 15:37:20.574738 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9148 15:37:20.581025 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9149 15:37:20.587975 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9150 15:37:20.591049 DRAM rank0 size:0x100000000,
9151 15:37:20.594633 DRAM rank1 size=0x100000000
9152 15:37:20.594746 CBMEM:
9153 15:37:20.597628 IMD: root @ 0xfffff000 254 entries.
9154 15:37:20.600709 IMD: root @ 0xffffec00 62 entries.
9155 15:37:20.604451 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9156 15:37:20.607737 WARNING: RO_VPD is uninitialized or empty.
9157 15:37:20.614087 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9158 15:37:20.620916 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9159 15:37:20.633862 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9160 15:37:20.645580 BS: romstage times (exec / console): total (unknown) / 23990 ms
9161 15:37:20.645662
9162 15:37:20.645726
9163 15:37:20.655485 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9164 15:37:20.658647 ARM64: Exception handlers installed.
9165 15:37:20.661800 ARM64: Testing exception
9166 15:37:20.665541 ARM64: Done test exception
9167 15:37:20.665620 Enumerating buses...
9168 15:37:20.668842 Show all devs... Before device enumeration.
9169 15:37:20.672040 Root Device: enabled 1
9170 15:37:20.675507 CPU_CLUSTER: 0: enabled 1
9171 15:37:20.675615 CPU: 00: enabled 1
9172 15:37:20.678798 Compare with tree...
9173 15:37:20.678905 Root Device: enabled 1
9174 15:37:20.681823 CPU_CLUSTER: 0: enabled 1
9175 15:37:20.684957 CPU: 00: enabled 1
9176 15:37:20.685068 Root Device scanning...
9177 15:37:20.688912 scan_static_bus for Root Device
9178 15:37:20.692031 CPU_CLUSTER: 0 enabled
9179 15:37:20.695265 scan_static_bus for Root Device done
9180 15:37:20.698260 scan_bus: bus Root Device finished in 8 msecs
9181 15:37:20.698367 done
9182 15:37:20.705430 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9183 15:37:20.708337 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9184 15:37:20.714899 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9185 15:37:20.718680 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9186 15:37:20.721956 Allocating resources...
9187 15:37:20.722064 Reading resources...
9188 15:37:20.728831 Root Device read_resources bus 0 link: 0
9189 15:37:20.728949 DRAM rank0 size:0x100000000,
9190 15:37:20.731794 DRAM rank1 size=0x100000000
9191 15:37:20.735067 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9192 15:37:20.738460 CPU: 00 missing read_resources
9193 15:37:20.741700 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9194 15:37:20.748081 Root Device read_resources bus 0 link: 0 done
9195 15:37:20.748177 Done reading resources.
9196 15:37:20.755235 Show resources in subtree (Root Device)...After reading.
9197 15:37:20.758494 Root Device child on link 0 CPU_CLUSTER: 0
9198 15:37:20.761866 CPU_CLUSTER: 0 child on link 0 CPU: 00
9199 15:37:20.772085 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9200 15:37:20.772198 CPU: 00
9201 15:37:20.775312 Root Device assign_resources, bus 0 link: 0
9202 15:37:20.778580 CPU_CLUSTER: 0 missing set_resources
9203 15:37:20.782014 Root Device assign_resources, bus 0 link: 0 done
9204 15:37:20.785161 Done setting resources.
9205 15:37:20.792045 Show resources in subtree (Root Device)...After assigning values.
9206 15:37:20.795205 Root Device child on link 0 CPU_CLUSTER: 0
9207 15:37:20.798206 CPU_CLUSTER: 0 child on link 0 CPU: 00
9208 15:37:20.808387 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9209 15:37:20.808498 CPU: 00
9210 15:37:20.811544 Done allocating resources.
9211 15:37:20.814917 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9212 15:37:20.818416 Enabling resources...
9213 15:37:20.818524 done.
9214 15:37:20.821453 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9215 15:37:20.825051 Initializing devices...
9216 15:37:20.828249 Root Device init
9217 15:37:20.828355 init hardware done!
9218 15:37:20.832047 0x00000018: ctrlr->caps
9219 15:37:20.832132 52.000 MHz: ctrlr->f_max
9220 15:37:20.835160 0.400 MHz: ctrlr->f_min
9221 15:37:20.838104 0x40ff8080: ctrlr->voltages
9222 15:37:20.838219 sclk: 390625
9223 15:37:20.841627 Bus Width = 1
9224 15:37:20.841730 sclk: 390625
9225 15:37:20.841827 Bus Width = 1
9226 15:37:20.844864 Early init status = 3
9227 15:37:20.848178 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9228 15:37:20.853177 in-header: 03 fc 00 00 01 00 00 00
9229 15:37:20.856288 in-data: 00
9230 15:37:20.859503 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9231 15:37:20.863973 in-header: 03 fd 00 00 00 00 00 00
9232 15:37:20.867320 in-data:
9233 15:37:20.870573 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9234 15:37:20.873909 in-header: 03 fc 00 00 01 00 00 00
9235 15:37:20.877673 in-data: 00
9236 15:37:20.880616 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9237 15:37:20.885397 in-header: 03 fd 00 00 00 00 00 00
9238 15:37:20.888584 in-data:
9239 15:37:20.892512 [SSUSB] Setting up USB HOST controller...
9240 15:37:20.895859 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9241 15:37:20.899025 [SSUSB] phy power-on done.
9242 15:37:20.901861 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9243 15:37:20.908537 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9244 15:37:20.912377 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9245 15:37:20.919116 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9246 15:37:20.925594 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9247 15:37:20.932272 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9248 15:37:20.938796 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9249 15:37:20.945629 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9250 15:37:20.945713 SPM: binary array size = 0x9dc
9251 15:37:20.951801 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9252 15:37:20.958563 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9253 15:37:20.965256 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9254 15:37:20.968524 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9255 15:37:20.971860 configure_display: Starting display init
9256 15:37:21.008607 anx7625_power_on_init: Init interface.
9257 15:37:21.011927 anx7625_disable_pd_protocol: Disabled PD feature.
9258 15:37:21.015428 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9259 15:37:21.043000 anx7625_start_dp_work: Secure OCM version=00
9260 15:37:21.046181 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9261 15:37:21.061057 sp_tx_get_edid_block: EDID Block = 1
9262 15:37:21.164027 Extracted contents:
9263 15:37:21.167321 header: 00 ff ff ff ff ff ff 00
9264 15:37:21.170242 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9265 15:37:21.173514 version: 01 04
9266 15:37:21.177140 basic params: 95 1f 11 78 0a
9267 15:37:21.180247 chroma info: 76 90 94 55 54 90 27 21 50 54
9268 15:37:21.183541 established: 00 00 00
9269 15:37:21.190268 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9270 15:37:21.193588 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9271 15:37:21.200128 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9272 15:37:21.206678 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9273 15:37:21.213206 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9274 15:37:21.216550 extensions: 00
9275 15:37:21.216635 checksum: fb
9276 15:37:21.216699
9277 15:37:21.219990 Manufacturer: IVO Model 57d Serial Number 0
9278 15:37:21.223038 Made week 0 of 2020
9279 15:37:21.223123 EDID version: 1.4
9280 15:37:21.226289 Digital display
9281 15:37:21.229684 6 bits per primary color channel
9282 15:37:21.229768 DisplayPort interface
9283 15:37:21.232915 Maximum image size: 31 cm x 17 cm
9284 15:37:21.236253 Gamma: 220%
9285 15:37:21.236359 Check DPMS levels
9286 15:37:21.240112 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9287 15:37:21.243141 First detailed timing is preferred timing
9288 15:37:21.246847 Established timings supported:
9289 15:37:21.249805 Standard timings supported:
9290 15:37:21.249920 Detailed timings
9291 15:37:21.256777 Hex of detail: 383680a07038204018303c0035ae10000019
9292 15:37:21.260050 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9293 15:37:21.266640 0780 0798 07c8 0820 hborder 0
9294 15:37:21.269901 0438 043b 0447 0458 vborder 0
9295 15:37:21.273338 -hsync -vsync
9296 15:37:21.273449 Did detailed timing
9297 15:37:21.276543 Hex of detail: 000000000000000000000000000000000000
9298 15:37:21.279675 Manufacturer-specified data, tag 0
9299 15:37:21.286599 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9300 15:37:21.286709 ASCII string: InfoVision
9301 15:37:21.293107 Hex of detail: 000000fe00523134304e574635205248200a
9302 15:37:21.296569 ASCII string: R140NWF5 RH
9303 15:37:21.296681 Checksum
9304 15:37:21.296780 Checksum: 0xfb (valid)
9305 15:37:21.303168 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9306 15:37:21.306400 DSI data_rate: 832800000 bps
9307 15:37:21.312879 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9308 15:37:21.316693 anx7625_parse_edid: pixelclock(138800).
9309 15:37:21.319972 hactive(1920), hsync(48), hfp(24), hbp(88)
9310 15:37:21.323208 vactive(1080), vsync(12), vfp(3), vbp(17)
9311 15:37:21.326491 anx7625_dsi_config: config dsi.
9312 15:37:21.333117 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9313 15:37:21.345503 anx7625_dsi_config: success to config DSI
9314 15:37:21.349358 anx7625_dp_start: MIPI phy setup OK.
9315 15:37:21.352107 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9316 15:37:21.355983 mtk_ddp_mode_set invalid vrefresh 60
9317 15:37:21.359021 main_disp_path_setup
9318 15:37:21.359132 ovl_layer_smi_id_en
9319 15:37:21.362201 ovl_layer_smi_id_en
9320 15:37:21.362307 ccorr_config
9321 15:37:21.362407 aal_config
9322 15:37:21.366019 gamma_config
9323 15:37:21.366120 postmask_config
9324 15:37:21.369102 dither_config
9325 15:37:21.372181 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9326 15:37:21.378678 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9327 15:37:21.382082 Root Device init finished in 551 msecs
9328 15:37:21.385443 CPU_CLUSTER: 0 init
9329 15:37:21.391978 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9330 15:37:21.398368 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9331 15:37:21.398454 APU_MBOX 0x190000b0 = 0x10001
9332 15:37:21.401573 APU_MBOX 0x190001b0 = 0x10001
9333 15:37:21.405285 APU_MBOX 0x190005b0 = 0x10001
9334 15:37:21.408566 APU_MBOX 0x190006b0 = 0x10001
9335 15:37:21.415114 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9336 15:37:21.424943 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9337 15:37:21.437093 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9338 15:37:21.443921 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9339 15:37:21.455222 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9340 15:37:21.464357 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9341 15:37:21.468053 CPU_CLUSTER: 0 init finished in 81 msecs
9342 15:37:21.471473 Devices initialized
9343 15:37:21.474645 Show all devs... After init.
9344 15:37:21.474761 Root Device: enabled 1
9345 15:37:21.477953 CPU_CLUSTER: 0: enabled 1
9346 15:37:21.481211 CPU: 00: enabled 1
9347 15:37:21.484450 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9348 15:37:21.487943 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9349 15:37:21.491358 ELOG: NV offset 0x57f000 size 0x1000
9350 15:37:21.498138 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9351 15:37:21.504428 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9352 15:37:21.507629 ELOG: Event(17) added with size 13 at 2023-08-22 15:36:16 UTC
9353 15:37:21.510770 out: cmd=0x121: 03 db 21 01 00 00 00 00
9354 15:37:21.515117 in-header: 03 de 00 00 2c 00 00 00
9355 15:37:21.528001 in-data: 81 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9356 15:37:21.535018 ELOG: Event(A1) added with size 10 at 2023-08-22 15:36:16 UTC
9357 15:37:21.541325 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9358 15:37:21.547803 ELOG: Event(A0) added with size 9 at 2023-08-22 15:36:16 UTC
9359 15:37:21.551123 elog_add_boot_reason: Logged dev mode boot
9360 15:37:21.554460 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9361 15:37:21.558385 Finalize devices...
9362 15:37:21.558462 Devices finalized
9363 15:37:21.564849 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9364 15:37:21.568154 Writing coreboot table at 0xffe64000
9365 15:37:21.571452 0. 000000000010a000-0000000000113fff: RAMSTAGE
9366 15:37:21.574842 1. 0000000040000000-00000000400fffff: RAM
9367 15:37:21.577907 2. 0000000040100000-000000004032afff: RAMSTAGE
9368 15:37:21.584414 3. 000000004032b000-00000000545fffff: RAM
9369 15:37:21.587768 4. 0000000054600000-000000005465ffff: BL31
9370 15:37:21.591133 5. 0000000054660000-00000000ffe63fff: RAM
9371 15:37:21.595069 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9372 15:37:21.601348 7. 0000000100000000-000000023fffffff: RAM
9373 15:37:21.601431 Passing 5 GPIOs to payload:
9374 15:37:21.608229 NAME | PORT | POLARITY | VALUE
9375 15:37:21.611506 EC in RW | 0x000000aa | low | undefined
9376 15:37:21.618190 EC interrupt | 0x00000005 | low | undefined
9377 15:37:21.621150 TPM interrupt | 0x000000ab | high | undefined
9378 15:37:21.624848 SD card detect | 0x00000011 | high | undefined
9379 15:37:21.631258 speaker enable | 0x00000093 | high | undefined
9380 15:37:21.634352 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9381 15:37:21.638173 in-header: 03 f9 00 00 02 00 00 00
9382 15:37:21.638297 in-data: 02 00
9383 15:37:21.641256 ADC[4]: Raw value=904726 ID=7
9384 15:37:21.644387 ADC[3]: Raw value=213441 ID=1
9385 15:37:21.644481 RAM Code: 0x71
9386 15:37:21.647606 ADC[6]: Raw value=75701 ID=0
9387 15:37:21.651086 ADC[5]: Raw value=213072 ID=1
9388 15:37:21.651173 SKU Code: 0x1
9389 15:37:21.657658 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b7d7
9390 15:37:21.661039 coreboot table: 964 bytes.
9391 15:37:21.664255 IMD ROOT 0. 0xfffff000 0x00001000
9392 15:37:21.667504 IMD SMALL 1. 0xffffe000 0x00001000
9393 15:37:21.670823 RO MCACHE 2. 0xffffc000 0x00001104
9394 15:37:21.674653 CONSOLE 3. 0xfff7c000 0x00080000
9395 15:37:21.677911 FMAP 4. 0xfff7b000 0x00000452
9396 15:37:21.681124 TIME STAMP 5. 0xfff7a000 0x00000910
9397 15:37:21.684260 VBOOT WORK 6. 0xfff66000 0x00014000
9398 15:37:21.687529 RAMOOPS 7. 0xffe66000 0x00100000
9399 15:37:21.691007 COREBOOT 8. 0xffe64000 0x00002000
9400 15:37:21.691125 IMD small region:
9401 15:37:21.694299 IMD ROOT 0. 0xffffec00 0x00000400
9402 15:37:21.697657 VPD 1. 0xffffeb80 0x0000006c
9403 15:37:21.700998 MMC STATUS 2. 0xffffeb60 0x00000004
9404 15:37:21.707443 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9405 15:37:21.710930 Probing TPM: done!
9406 15:37:21.713973 Connected to device vid:did:rid of 1ae0:0028:00
9407 15:37:21.724233 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9408 15:37:21.727659 Initialized TPM device CR50 revision 0
9409 15:37:21.731431 Checking cr50 for pending updates
9410 15:37:21.734722 Reading cr50 TPM mode
9411 15:37:21.743200 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9412 15:37:21.749533 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9413 15:37:21.789673 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9414 15:37:21.793163 Checking segment from ROM address 0x40100000
9415 15:37:21.796417 Checking segment from ROM address 0x4010001c
9416 15:37:21.803111 Loading segment from ROM address 0x40100000
9417 15:37:21.803217 code (compression=0)
9418 15:37:21.813127 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9419 15:37:21.820328 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9420 15:37:21.820443 it's not compressed!
9421 15:37:21.826973 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9422 15:37:21.830182 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9423 15:37:21.850164 Loading segment from ROM address 0x4010001c
9424 15:37:21.850250 Entry Point 0x80000000
9425 15:37:21.853478 Loaded segments
9426 15:37:21.857095 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9427 15:37:21.863876 Jumping to boot code at 0x80000000(0xffe64000)
9428 15:37:21.870043 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9429 15:37:21.876538 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9430 15:37:21.884666 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9431 15:37:21.888064 Checking segment from ROM address 0x40100000
9432 15:37:21.891282 Checking segment from ROM address 0x4010001c
9433 15:37:21.897903 Loading segment from ROM address 0x40100000
9434 15:37:21.897989 code (compression=1)
9435 15:37:21.905069 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9436 15:37:21.914966 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9437 15:37:21.915049 using LZMA
9438 15:37:21.922933 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9439 15:37:21.929544 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9440 15:37:21.932953 Loading segment from ROM address 0x4010001c
9441 15:37:21.933035 Entry Point 0x54601000
9442 15:37:21.936642 Loaded segments
9443 15:37:21.939924 NOTICE: MT8192 bl31_setup
9444 15:37:21.946590 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9445 15:37:21.949871 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9446 15:37:21.953221 WARNING: region 0:
9447 15:37:21.956615 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9448 15:37:21.956697 WARNING: region 1:
9449 15:37:21.963148 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9450 15:37:21.966471 WARNING: region 2:
9451 15:37:21.969848 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9452 15:37:21.973020 WARNING: region 3:
9453 15:37:21.976909 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9454 15:37:21.980075 WARNING: region 4:
9455 15:37:21.983392 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9456 15:37:21.986518 WARNING: region 5:
9457 15:37:21.990279 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 15:37:21.993694 WARNING: region 6:
9459 15:37:21.996973 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 15:37:21.997085 WARNING: region 7:
9461 15:37:22.003259 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 15:37:22.010177 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9463 15:37:22.013538 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9464 15:37:22.016881 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9465 15:37:22.023940 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9466 15:37:22.027216 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9467 15:37:22.030406 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9468 15:37:22.036982 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9469 15:37:22.040279 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9470 15:37:22.043526 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9471 15:37:22.050148 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9472 15:37:22.054026 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9473 15:37:22.057225 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9474 15:37:22.063669 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9475 15:37:22.066943 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9476 15:37:22.073818 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9477 15:37:22.077162 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9478 15:37:22.080485 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9479 15:37:22.086998 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9480 15:37:22.090257 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9481 15:37:22.093698 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9482 15:37:22.100305 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9483 15:37:22.103915 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9484 15:37:22.110759 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9485 15:37:22.113877 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9486 15:37:22.117521 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9487 15:37:22.123715 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9488 15:37:22.127475 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9489 15:37:22.130737 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9490 15:37:22.137382 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9491 15:37:22.140777 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9492 15:37:22.147332 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9493 15:37:22.150550 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9494 15:37:22.153655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9495 15:37:22.160359 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9496 15:37:22.163797 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9497 15:37:22.167106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9498 15:37:22.170487 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9499 15:37:22.177194 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9500 15:37:22.180565 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9501 15:37:22.184378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9502 15:37:22.187368 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9503 15:37:22.190452 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9504 15:37:22.197430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9505 15:37:22.200624 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9506 15:37:22.203889 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9507 15:37:22.210379 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9508 15:37:22.214274 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9509 15:37:22.217648 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9510 15:37:22.220799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9511 15:37:22.227359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9512 15:37:22.230402 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9513 15:37:22.237567 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9514 15:37:22.240651 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9515 15:37:22.247056 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9516 15:37:22.251038 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9517 15:37:22.253832 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9518 15:37:22.260961 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9519 15:37:22.264213 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9520 15:37:22.270965 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9521 15:37:22.274204 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9522 15:37:22.281077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9523 15:37:22.284210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9524 15:37:22.290638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9525 15:37:22.294110 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9526 15:37:22.297106 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9527 15:37:22.304375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9528 15:37:22.307532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9529 15:37:22.314435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9530 15:37:22.317535 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9531 15:37:22.320767 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9532 15:37:22.327826 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9533 15:37:22.331284 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9534 15:37:22.337562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9535 15:37:22.340974 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9536 15:37:22.347222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9537 15:37:22.351178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9538 15:37:22.353775 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9539 15:37:22.360944 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9540 15:37:22.364370 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9541 15:37:22.370922 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9542 15:37:22.374333 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9543 15:37:22.380893 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9544 15:37:22.384307 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9545 15:37:22.391065 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9546 15:37:22.394225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9547 15:37:22.397502 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9548 15:37:22.404301 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9549 15:37:22.407408 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9550 15:37:22.414413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9551 15:37:22.417797 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9552 15:37:22.420997 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9553 15:37:22.427769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9554 15:37:22.430779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9555 15:37:22.437407 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9556 15:37:22.440728 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9557 15:37:22.447298 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9558 15:37:22.450625 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9559 15:37:22.454387 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9560 15:37:22.457510 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9561 15:37:22.464226 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9562 15:37:22.467672 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9563 15:37:22.471082 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9564 15:37:22.477692 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9565 15:37:22.481020 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9566 15:37:22.487538 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9567 15:37:22.490823 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9568 15:37:22.494090 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9569 15:37:22.501096 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9570 15:37:22.504430 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9571 15:37:22.510924 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9572 15:37:22.514072 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9573 15:37:22.517450 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9574 15:37:22.524717 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9575 15:37:22.527605 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9576 15:37:22.530931 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9577 15:37:22.537942 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9578 15:37:22.541125 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9579 15:37:22.544256 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9580 15:37:22.551297 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9581 15:37:22.554487 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9582 15:37:22.557765 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9583 15:37:22.561037 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9584 15:37:22.567503 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9585 15:37:22.571148 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9586 15:37:22.574164 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9587 15:37:22.581442 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9588 15:37:22.584781 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9589 15:37:22.588170 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9590 15:37:22.594794 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9591 15:37:22.598287 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9592 15:37:22.604677 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9593 15:37:22.608039 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9594 15:37:22.611366 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9595 15:37:22.617598 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9596 15:37:22.621017 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9597 15:37:22.628059 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9598 15:37:22.631207 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9599 15:37:22.634640 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9600 15:37:22.641003 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9601 15:37:22.644357 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9602 15:37:22.648311 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9603 15:37:22.654690 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9604 15:37:22.657857 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9605 15:37:22.664924 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9606 15:37:22.667937 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9607 15:37:22.671270 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9608 15:37:22.678142 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9609 15:37:22.681867 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9610 15:37:22.685053 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9611 15:37:22.691837 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9612 15:37:22.695091 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9613 15:37:22.698504 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9614 15:37:22.704935 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9615 15:37:22.708309 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9616 15:37:22.714802 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9617 15:37:22.718177 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9618 15:37:22.721927 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9619 15:37:22.728741 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9620 15:37:22.731947 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9621 15:37:22.738378 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9622 15:37:22.742114 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9623 15:37:22.745082 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9624 15:37:22.751600 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9625 15:37:22.754722 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9626 15:37:22.761415 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9627 15:37:22.764902 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9628 15:37:22.768439 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9629 15:37:22.775322 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9630 15:37:22.778354 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9631 15:37:22.781888 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9632 15:37:22.787997 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9633 15:37:22.791462 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9634 15:37:22.798205 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9635 15:37:22.801314 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9636 15:37:22.804591 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9637 15:37:22.811447 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9638 15:37:22.814616 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9639 15:37:22.821248 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9640 15:37:22.824323 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9641 15:37:22.828170 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9642 15:37:22.834528 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9643 15:37:22.837657 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9644 15:37:22.844509 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9645 15:37:22.847972 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9646 15:37:22.851579 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9647 15:37:22.857997 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9648 15:37:22.861107 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9649 15:37:22.867961 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9650 15:37:22.871221 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9651 15:37:22.874236 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9652 15:37:22.881151 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9653 15:37:22.884265 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9654 15:37:22.891066 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9655 15:37:22.894474 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9656 15:37:22.897521 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9657 15:37:22.904545 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9658 15:37:22.907389 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9659 15:37:22.914489 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9660 15:37:22.917405 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9661 15:37:22.924012 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9662 15:37:22.927627 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9663 15:37:22.930598 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9664 15:37:22.937540 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9665 15:37:22.941173 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9666 15:37:22.947427 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9667 15:37:22.951163 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9668 15:37:22.957273 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9669 15:37:22.960782 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9670 15:37:22.964062 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9671 15:37:22.970697 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9672 15:37:22.973832 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9673 15:37:22.980753 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9674 15:37:22.983888 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9675 15:37:22.986988 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9676 15:37:22.993729 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9677 15:37:22.997432 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9678 15:37:23.003639 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9679 15:37:23.007444 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9680 15:37:23.014054 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9681 15:37:23.017335 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9682 15:37:23.020369 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9683 15:37:23.026982 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9684 15:37:23.030436 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9685 15:37:23.037031 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9686 15:37:23.040204 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9687 15:37:23.043982 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9688 15:37:23.050389 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9689 15:37:23.053620 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9690 15:37:23.060515 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9691 15:37:23.063657 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9692 15:37:23.066743 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9693 15:37:23.070397 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9694 15:37:23.077144 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9695 15:37:23.079907 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9696 15:37:23.083379 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9697 15:37:23.090384 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9698 15:37:23.093054 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9699 15:37:23.096770 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9700 15:37:23.103165 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9701 15:37:23.106846 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9702 15:37:23.110063 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9703 15:37:23.116418 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9704 15:37:23.120153 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9705 15:37:23.123304 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9706 15:37:23.129729 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9707 15:37:23.133336 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9708 15:37:23.140072 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9709 15:37:23.143260 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9710 15:37:23.146442 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9711 15:37:23.152895 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9712 15:37:23.156193 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9713 15:37:23.159358 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9714 15:37:23.166012 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9715 15:37:23.170002 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9716 15:37:23.173305 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9717 15:37:23.179600 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9718 15:37:23.182819 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9719 15:37:23.189703 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9720 15:37:23.193076 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9721 15:37:23.195924 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9722 15:37:23.202684 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9723 15:37:23.205844 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9724 15:37:23.212739 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9725 15:37:23.215926 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9726 15:37:23.219284 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9727 15:37:23.226178 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9728 15:37:23.229312 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9729 15:37:23.232497 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9730 15:37:23.239541 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9731 15:37:23.242523 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9732 15:37:23.246164 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9733 15:37:23.249440 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9734 15:37:23.252516 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9735 15:37:23.259478 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9736 15:37:23.262505 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9737 15:37:23.265815 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9738 15:37:23.269158 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9739 15:37:23.275660 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9740 15:37:23.279582 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9741 15:37:23.282617 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9742 15:37:23.286121 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9743 15:37:23.292353 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9744 15:37:23.295611 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9745 15:37:23.302409 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9746 15:37:23.305836 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9747 15:37:23.309126 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9748 15:37:23.315835 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9749 15:37:23.319130 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9750 15:37:23.325924 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9751 15:37:23.329034 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9752 15:37:23.332534 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9753 15:37:23.339050 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9754 15:37:23.342190 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9755 15:37:23.348821 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9756 15:37:23.352209 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9757 15:37:23.358500 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9758 15:37:23.362324 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9759 15:37:23.365344 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9760 15:37:23.372193 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9761 15:37:23.375279 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9762 15:37:23.381809 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9763 15:37:23.385699 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9764 15:37:23.388797 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9765 15:37:23.395337 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9766 15:37:23.398636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9767 15:37:23.405156 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9768 15:37:23.409064 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9769 15:37:23.412120 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9770 15:37:23.418684 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9771 15:37:23.422022 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9772 15:37:23.428678 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9773 15:37:23.431662 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9774 15:37:23.438720 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9775 15:37:23.442010 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9776 15:37:23.445244 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9777 15:37:23.451818 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9778 15:37:23.455163 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9779 15:37:23.461457 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9780 15:37:23.465142 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9781 15:37:23.468434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9782 15:37:23.474767 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9783 15:37:23.478565 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9784 15:37:23.481878 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9785 15:37:23.488485 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9786 15:37:23.491683 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9787 15:37:23.498295 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9788 15:37:23.501538 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9789 15:37:23.508220 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9790 15:37:23.512076 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9791 15:37:23.515325 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9792 15:37:23.522195 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9793 15:37:23.525503 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9794 15:37:23.528750 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9795 15:37:23.535036 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9796 15:37:23.538685 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9797 15:37:23.544962 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9798 15:37:23.548604 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9799 15:37:23.555086 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9800 15:37:23.558071 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9801 15:37:23.561500 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9802 15:37:23.568472 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9803 15:37:23.571693 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9804 15:37:23.578802 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9805 15:37:23.581826 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9806 15:37:23.585409 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9807 15:37:23.591538 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9808 15:37:23.595508 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9809 15:37:23.601902 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9810 15:37:23.605140 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9811 15:37:23.608299 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9812 15:37:23.614786 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9813 15:37:23.618481 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9814 15:37:23.624860 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9815 15:37:23.628515 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9816 15:37:23.631874 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9817 15:37:23.638382 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9818 15:37:23.641477 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9819 15:37:23.647867 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9820 15:37:23.651484 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9821 15:37:23.658198 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9822 15:37:23.661325 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9823 15:37:23.664761 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9824 15:37:23.671376 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9825 15:37:23.674693 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9826 15:37:23.681619 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9827 15:37:23.685010 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9828 15:37:23.691015 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9829 15:37:23.694761 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9830 15:37:23.701493 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9831 15:37:23.704586 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9832 15:37:23.707700 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9833 15:37:23.714251 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9834 15:37:23.718004 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9835 15:37:23.724502 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9836 15:37:23.727662 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9837 15:37:23.734527 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9838 15:37:23.737649 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9839 15:37:23.740695 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9840 15:37:23.747472 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9841 15:37:23.751192 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9842 15:37:23.757422 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9843 15:37:23.761168 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9844 15:37:23.767325 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9845 15:37:23.770759 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9846 15:37:23.777429 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9847 15:37:23.780761 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9848 15:37:23.783840 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9849 15:37:23.790895 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9850 15:37:23.794123 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9851 15:37:23.800504 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9852 15:37:23.804386 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9853 15:37:23.810855 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9854 15:37:23.814309 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9855 15:37:23.817216 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9856 15:37:23.824377 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9857 15:37:23.827406 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9858 15:37:23.834271 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9859 15:37:23.837592 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9860 15:37:23.843925 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9861 15:37:23.847186 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9862 15:37:23.854205 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9863 15:37:23.857243 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9864 15:37:23.860657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9865 15:37:23.867270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9866 15:37:23.870442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9867 15:37:23.877411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9868 15:37:23.880616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9869 15:37:23.883878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9870 15:37:23.890895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9871 15:37:23.893918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9872 15:37:23.900297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9873 15:37:23.904034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9874 15:37:23.910481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9875 15:37:23.913894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9876 15:37:23.920563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9877 15:37:23.923534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9878 15:37:23.930562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9879 15:37:23.933895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9880 15:37:23.940025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9881 15:37:23.943975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9882 15:37:23.950277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9883 15:37:23.953403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9884 15:37:23.960468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9885 15:37:23.963456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9886 15:37:23.970339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9887 15:37:23.973245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9888 15:37:23.980402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9889 15:37:23.983800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9890 15:37:23.990245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9891 15:37:23.994080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9892 15:37:24.000568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9893 15:37:24.003855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9894 15:37:24.010428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9895 15:37:24.013523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9896 15:37:24.016704 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9897 15:37:24.020084 INFO: [APUAPC] vio 0
9898 15:37:24.026424 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9899 15:37:24.030038 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9900 15:37:24.033136 INFO: [APUAPC] D0_APC_0: 0x400510
9901 15:37:24.036377 INFO: [APUAPC] D0_APC_1: 0x0
9902 15:37:24.039638 INFO: [APUAPC] D0_APC_2: 0x1540
9903 15:37:24.043326 INFO: [APUAPC] D0_APC_3: 0x0
9904 15:37:24.046512 INFO: [APUAPC] D1_APC_0: 0xffffffff
9905 15:37:24.049627 INFO: [APUAPC] D1_APC_1: 0xffffffff
9906 15:37:24.053426 INFO: [APUAPC] D1_APC_2: 0x3fffff
9907 15:37:24.056238 INFO: [APUAPC] D1_APC_3: 0x0
9908 15:37:24.059541 INFO: [APUAPC] D2_APC_0: 0xffffffff
9909 15:37:24.063115 INFO: [APUAPC] D2_APC_1: 0xffffffff
9910 15:37:24.066310 INFO: [APUAPC] D2_APC_2: 0x3fffff
9911 15:37:24.070050 INFO: [APUAPC] D2_APC_3: 0x0
9912 15:37:24.073166 INFO: [APUAPC] D3_APC_0: 0xffffffff
9913 15:37:24.076211 INFO: [APUAPC] D3_APC_1: 0xffffffff
9914 15:37:24.079267 INFO: [APUAPC] D3_APC_2: 0x3fffff
9915 15:37:24.079350 INFO: [APUAPC] D3_APC_3: 0x0
9916 15:37:24.086374 INFO: [APUAPC] D4_APC_0: 0xffffffff
9917 15:37:24.089567 INFO: [APUAPC] D4_APC_1: 0xffffffff
9918 15:37:24.092721 INFO: [APUAPC] D4_APC_2: 0x3fffff
9919 15:37:24.092803 INFO: [APUAPC] D4_APC_3: 0x0
9920 15:37:24.095975 INFO: [APUAPC] D5_APC_0: 0xffffffff
9921 15:37:24.099780 INFO: [APUAPC] D5_APC_1: 0xffffffff
9922 15:37:24.102948 INFO: [APUAPC] D5_APC_2: 0x3fffff
9923 15:37:24.106154 INFO: [APUAPC] D5_APC_3: 0x0
9924 15:37:24.109398 INFO: [APUAPC] D6_APC_0: 0xffffffff
9925 15:37:24.112620 INFO: [APUAPC] D6_APC_1: 0xffffffff
9926 15:37:24.115903 INFO: [APUAPC] D6_APC_2: 0x3fffff
9927 15:37:24.119711 INFO: [APUAPC] D6_APC_3: 0x0
9928 15:37:24.123034 INFO: [APUAPC] D7_APC_0: 0xffffffff
9929 15:37:24.126183 INFO: [APUAPC] D7_APC_1: 0xffffffff
9930 15:37:24.129394 INFO: [APUAPC] D7_APC_2: 0x3fffff
9931 15:37:24.132530 INFO: [APUAPC] D7_APC_3: 0x0
9932 15:37:24.136244 INFO: [APUAPC] D8_APC_0: 0xffffffff
9933 15:37:24.139322 INFO: [APUAPC] D8_APC_1: 0xffffffff
9934 15:37:24.142872 INFO: [APUAPC] D8_APC_2: 0x3fffff
9935 15:37:24.145768 INFO: [APUAPC] D8_APC_3: 0x0
9936 15:37:24.149263 INFO: [APUAPC] D9_APC_0: 0xffffffff
9937 15:37:24.152766 INFO: [APUAPC] D9_APC_1: 0xffffffff
9938 15:37:24.156004 INFO: [APUAPC] D9_APC_2: 0x3fffff
9939 15:37:24.159294 INFO: [APUAPC] D9_APC_3: 0x0
9940 15:37:24.162561 INFO: [APUAPC] D10_APC_0: 0xffffffff
9941 15:37:24.166080 INFO: [APUAPC] D10_APC_1: 0xffffffff
9942 15:37:24.169265 INFO: [APUAPC] D10_APC_2: 0x3fffff
9943 15:37:24.172770 INFO: [APUAPC] D10_APC_3: 0x0
9944 15:37:24.176496 INFO: [APUAPC] D11_APC_0: 0xffffffff
9945 15:37:24.179354 INFO: [APUAPC] D11_APC_1: 0xffffffff
9946 15:37:24.182792 INFO: [APUAPC] D11_APC_2: 0x3fffff
9947 15:37:24.186010 INFO: [APUAPC] D11_APC_3: 0x0
9948 15:37:24.189224 INFO: [APUAPC] D12_APC_0: 0xffffffff
9949 15:37:24.192806 INFO: [APUAPC] D12_APC_1: 0xffffffff
9950 15:37:24.196063 INFO: [APUAPC] D12_APC_2: 0x3fffff
9951 15:37:24.199172 INFO: [APUAPC] D12_APC_3: 0x0
9952 15:37:24.202439 INFO: [APUAPC] D13_APC_0: 0xffffffff
9953 15:37:24.205756 INFO: [APUAPC] D13_APC_1: 0xffffffff
9954 15:37:24.208961 INFO: [APUAPC] D13_APC_2: 0x3fffff
9955 15:37:24.212419 INFO: [APUAPC] D13_APC_3: 0x0
9956 15:37:24.215761 INFO: [APUAPC] D14_APC_0: 0xffffffff
9957 15:37:24.219019 INFO: [APUAPC] D14_APC_1: 0xffffffff
9958 15:37:24.222172 INFO: [APUAPC] D14_APC_2: 0x3fffff
9959 15:37:24.225429 INFO: [APUAPC] D14_APC_3: 0x0
9960 15:37:24.229262 INFO: [APUAPC] D15_APC_0: 0xffffffff
9961 15:37:24.232462 INFO: [APUAPC] D15_APC_1: 0xffffffff
9962 15:37:24.235507 INFO: [APUAPC] D15_APC_2: 0x3fffff
9963 15:37:24.238821 INFO: [APUAPC] D15_APC_3: 0x0
9964 15:37:24.242496 INFO: [APUAPC] APC_CON: 0x4
9965 15:37:24.245828 INFO: [NOCDAPC] D0_APC_0: 0x0
9966 15:37:24.248907 INFO: [NOCDAPC] D0_APC_1: 0x0
9967 15:37:24.252472 INFO: [NOCDAPC] D1_APC_0: 0x0
9968 15:37:24.255588 INFO: [NOCDAPC] D1_APC_1: 0xfff
9969 15:37:24.255677 INFO: [NOCDAPC] D2_APC_0: 0x0
9970 15:37:24.259046 INFO: [NOCDAPC] D2_APC_1: 0xfff
9971 15:37:24.262065 INFO: [NOCDAPC] D3_APC_0: 0x0
9972 15:37:24.265669 INFO: [NOCDAPC] D3_APC_1: 0xfff
9973 15:37:24.269074 INFO: [NOCDAPC] D4_APC_0: 0x0
9974 15:37:24.272812 INFO: [NOCDAPC] D4_APC_1: 0xfff
9975 15:37:24.275625 INFO: [NOCDAPC] D5_APC_0: 0x0
9976 15:37:24.278826 INFO: [NOCDAPC] D5_APC_1: 0xfff
9977 15:37:24.282587 INFO: [NOCDAPC] D6_APC_0: 0x0
9978 15:37:24.285575 INFO: [NOCDAPC] D6_APC_1: 0xfff
9979 15:37:24.285654 INFO: [NOCDAPC] D7_APC_0: 0x0
9980 15:37:24.288923 INFO: [NOCDAPC] D7_APC_1: 0xfff
9981 15:37:24.292537 INFO: [NOCDAPC] D8_APC_0: 0x0
9982 15:37:24.295562 INFO: [NOCDAPC] D8_APC_1: 0xfff
9983 15:37:24.299367 INFO: [NOCDAPC] D9_APC_0: 0x0
9984 15:37:24.302516 INFO: [NOCDAPC] D9_APC_1: 0xfff
9985 15:37:24.305651 INFO: [NOCDAPC] D10_APC_0: 0x0
9986 15:37:24.309161 INFO: [NOCDAPC] D10_APC_1: 0xfff
9987 15:37:24.312004 INFO: [NOCDAPC] D11_APC_0: 0x0
9988 15:37:24.315277 INFO: [NOCDAPC] D11_APC_1: 0xfff
9989 15:37:24.319249 INFO: [NOCDAPC] D12_APC_0: 0x0
9990 15:37:24.322387 INFO: [NOCDAPC] D12_APC_1: 0xfff
9991 15:37:24.325470 INFO: [NOCDAPC] D13_APC_0: 0x0
9992 15:37:24.325543 INFO: [NOCDAPC] D13_APC_1: 0xfff
9993 15:37:24.328888 INFO: [NOCDAPC] D14_APC_0: 0x0
9994 15:37:24.331916 INFO: [NOCDAPC] D14_APC_1: 0xfff
9995 15:37:24.335090 INFO: [NOCDAPC] D15_APC_0: 0x0
9996 15:37:24.338726 INFO: [NOCDAPC] D15_APC_1: 0xfff
9997 15:37:24.341916 INFO: [NOCDAPC] APC_CON: 0x4
9998 15:37:24.345097 INFO: [APUAPC] set_apusys_apc done
9999 15:37:24.348396 INFO: [DEVAPC] devapc_init done
10000 15:37:24.352353 INFO: GICv3 without legacy support detected.
10001 15:37:24.355488 INFO: ARM GICv3 driver initialized in EL3
10002 15:37:24.362174 INFO: Maximum SPI INTID supported: 639
10003 15:37:24.365392 INFO: BL31: Initializing runtime services
10004 15:37:24.372087 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10005 15:37:24.372167 INFO: SPM: enable CPC mode
10006 15:37:24.378600 INFO: mcdi ready for mcusys-off-idle and system suspend
10007 15:37:24.381597 INFO: BL31: Preparing for EL3 exit to normal world
10008 15:37:24.388384 INFO: Entry point address = 0x80000000
10009 15:37:24.388467 INFO: SPSR = 0x8
10010 15:37:24.394267
10011 15:37:24.394351
10012 15:37:24.394415
10013 15:37:24.398014 Starting depthcharge on Spherion...
10014 15:37:24.398126
10015 15:37:24.398191 Wipe memory regions:
10016 15:37:24.398252
10017 15:37:24.398961 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10018 15:37:24.399075 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10019 15:37:24.399161 Setting prompt string to ['asurada:']
10020 15:37:24.399249 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10021 15:37:24.401100 [0x00000040000000, 0x00000054600000)
10022 15:37:24.523165
10023 15:37:24.523307 [0x00000054660000, 0x00000080000000)
10024 15:37:24.783984
10025 15:37:24.784124 [0x000000821a7280, 0x000000ffe64000)
10026 15:37:25.528579
10027 15:37:25.528736 [0x00000100000000, 0x00000240000000)
10028 15:37:27.418570
10029 15:37:27.421424 Initializing XHCI USB controller at 0x11200000.
10030 15:37:28.459574
10031 15:37:28.462766 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10032 15:37:28.463220
10033 15:37:28.463650
10034 15:37:28.463998
10035 15:37:28.464759 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10037 15:37:28.565821 asurada: tftpboot 192.168.201.1 11331361/tftp-deploy-7nu3mvel/kernel/image.itb 11331361/tftp-deploy-7nu3mvel/kernel/cmdline
10038 15:37:28.566378 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10039 15:37:28.566907 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10040 15:37:28.571147 tftpboot 192.168.201.1 11331361/tftp-deploy-7nu3mvel/kernel/image.ittp-deploy-7nu3mvel/kernel/cmdline
10041 15:37:28.571568
10042 15:37:28.571966 Waiting for link
10043 15:37:28.731476
10044 15:37:28.732018 R8152: Initializing
10045 15:37:28.732350
10046 15:37:28.734945 Version 9 (ocp_data = 6010)
10047 15:37:28.735384
10048 15:37:28.738287 R8152: Done initializing
10049 15:37:28.738699
10050 15:37:28.739022 Adding net device
10051 15:37:30.607911
10052 15:37:30.608457 done.
10053 15:37:30.608798
10054 15:37:30.609112 MAC: 00:e0:4c:78:7a:aa
10055 15:37:30.609411
10056 15:37:30.610917 Sending DHCP discover... done.
10057 15:37:30.611332
10058 15:37:30.614485 Waiting for reply... done.
10059 15:37:30.614913
10060 15:37:30.617885 Sending DHCP request... done.
10061 15:37:30.618343
10062 15:37:30.621361 Waiting for reply... done.
10063 15:37:30.621825
10064 15:37:30.622216 My ip is 192.168.201.12
10065 15:37:30.622550
10066 15:37:30.624886 The DHCP server ip is 192.168.201.1
10067 15:37:30.625314
10068 15:37:30.631746 TFTP server IP predefined by user: 192.168.201.1
10069 15:37:30.632166
10070 15:37:30.638273 Bootfile predefined by user: 11331361/tftp-deploy-7nu3mvel/kernel/image.itb
10071 15:37:30.638690
10072 15:37:30.639013 Sending tftp read request... done.
10073 15:37:30.639317
10074 15:37:30.647668 Waiting for the transfer...
10075 15:37:30.648084
10076 15:37:30.933460 00000000 ################################################################
10077 15:37:30.933635
10078 15:37:31.202212 00080000 ################################################################
10079 15:37:31.202345
10080 15:37:31.495425 00100000 ################################################################
10081 15:37:31.495571
10082 15:37:31.780648 00180000 ################################################################
10083 15:37:31.780797
10084 15:37:32.072655 00200000 ################################################################
10085 15:37:32.072795
10086 15:37:32.355803 00280000 ################################################################
10087 15:37:32.355931
10088 15:37:32.623523 00300000 ################################################################
10089 15:37:32.623737
10090 15:37:32.879464 00380000 ################################################################
10091 15:37:32.879607
10092 15:37:33.129347 00400000 ################################################################
10093 15:37:33.129478
10094 15:37:33.397942 00480000 ################################################################
10095 15:37:33.398069
10096 15:37:33.663499 00500000 ################################################################
10097 15:37:33.663642
10098 15:37:33.919896 00580000 ################################################################
10099 15:37:33.920030
10100 15:37:34.178127 00600000 ################################################################
10101 15:37:34.178265
10102 15:37:34.443780 00680000 ################################################################
10103 15:37:34.443921
10104 15:37:34.722010 00700000 ################################################################
10105 15:37:34.722140
10106 15:37:35.008441 00780000 ################################################################
10107 15:37:35.008588
10108 15:37:35.270816 00800000 ################################################################
10109 15:37:35.270950
10110 15:37:35.555606 00880000 ################################################################
10111 15:37:35.555744
10112 15:37:35.843656 00900000 ################################################################
10113 15:37:35.843796
10114 15:37:36.124559 00980000 ################################################################
10115 15:37:36.124719
10116 15:37:36.374258 00a00000 ################################################################
10117 15:37:36.374387
10118 15:37:36.650517 00a80000 ################################################################
10119 15:37:36.650660
10120 15:37:36.913351 00b00000 ################################################################
10121 15:37:36.913506
10122 15:37:37.184697 00b80000 ################################################################
10123 15:37:37.184836
10124 15:37:37.477501 00c00000 ################################################################
10125 15:37:37.477645
10126 15:37:37.758071 00c80000 ################################################################
10127 15:37:37.758210
10128 15:37:38.008629 00d00000 ################################################################
10129 15:37:38.008781
10130 15:37:38.258332 00d80000 ################################################################
10131 15:37:38.258470
10132 15:37:38.518866 00e00000 ################################################################
10133 15:37:38.519006
10134 15:37:38.784083 00e80000 ################################################################
10135 15:37:38.784217
10136 15:37:39.044836 00f00000 ################################################################
10137 15:37:39.044966
10138 15:37:39.297700 00f80000 ################################################################
10139 15:37:39.297837
10140 15:37:39.549922 01000000 ################################################################
10141 15:37:39.550061
10142 15:37:39.808478 01080000 ################################################################
10143 15:37:39.808617
10144 15:37:40.070956 01100000 ################################################################
10145 15:37:40.071088
10146 15:37:40.343144 01180000 ################################################################
10147 15:37:40.343289
10148 15:37:40.602563 01200000 ################################################################
10149 15:37:40.602699
10150 15:37:40.872081 01280000 ################################################################
10151 15:37:40.872215
10152 15:37:41.121267 01300000 ################################################################
10153 15:37:41.121403
10154 15:37:41.370987 01380000 ################################################################
10155 15:37:41.371121
10156 15:37:41.621239 01400000 ################################################################
10157 15:37:41.621364
10158 15:37:41.870232 01480000 ################################################################
10159 15:37:41.870385
10160 15:37:42.119766 01500000 ################################################################
10161 15:37:42.119899
10162 15:37:42.380254 01580000 ################################################################
10163 15:37:42.380385
10164 15:37:42.672553 01600000 ################################################################
10165 15:37:42.672714
10166 15:37:42.970096 01680000 ################################################################
10167 15:37:42.970260
10168 15:37:43.226782 01700000 ################################################################
10169 15:37:43.226943
10170 15:37:43.485841 01780000 ################################################################
10171 15:37:43.486008
10172 15:37:43.735414 01800000 ################################################################
10173 15:37:43.735544
10174 15:37:43.990023 01880000 ################################################################
10175 15:37:43.990174
10176 15:37:44.240085 01900000 ################################################################
10177 15:37:44.240220
10178 15:37:44.504956 01980000 ################################################################
10179 15:37:44.505081
10180 15:37:44.761504 01a00000 ################################################################
10181 15:37:44.761660
10182 15:37:45.032810 01a80000 ################################################################
10183 15:37:45.032964
10184 15:37:45.327144 01b00000 ################################################################
10185 15:37:45.327282
10186 15:37:45.619882 01b80000 ################################################################
10187 15:37:45.620016
10188 15:37:45.913666 01c00000 ################################################################
10189 15:37:45.913805
10190 15:37:46.209238 01c80000 ################################################################
10191 15:37:46.209400
10192 15:37:46.471772 01d00000 ################################################################
10193 15:37:46.471926
10194 15:37:46.734756 01d80000 ################################################################
10195 15:37:46.734886
10196 15:37:46.995910 01e00000 ################################################################
10197 15:37:46.996057
10198 15:37:47.250877 01e80000 ################################################################
10199 15:37:47.251006
10200 15:37:47.509286 01f00000 ################################################################
10201 15:37:47.509422
10202 15:37:47.772709 01f80000 ################################################################
10203 15:37:47.772845
10204 15:37:48.031990 02000000 ################################################################
10205 15:37:48.032163
10206 15:37:48.291581 02080000 ################################################################
10207 15:37:48.291751
10208 15:37:48.553492 02100000 ################################################################
10209 15:37:48.553623
10210 15:37:48.811272 02180000 ################################################################
10211 15:37:48.811435
10212 15:37:49.079044 02200000 ################################################################
10213 15:37:49.079178
10214 15:37:49.354188 02280000 ################################################################
10215 15:37:49.354321
10216 15:37:49.634623 02300000 ################################################################
10217 15:37:49.634770
10218 15:37:49.905334 02380000 ################################################################
10219 15:37:49.905471
10220 15:37:50.173038 02400000 ################################################################
10221 15:37:50.173172
10222 15:37:50.451537 02480000 ################################################################
10223 15:37:50.451710
10224 15:37:50.746926 02500000 ################################################################
10225 15:37:50.747072
10226 15:37:50.999464 02580000 ################################################################
10227 15:37:50.999671
10228 15:37:51.249633 02600000 ################################################################
10229 15:37:51.249786
10230 15:37:51.532850 02680000 ################################################################
10231 15:37:51.532996
10232 15:37:51.789831 02700000 ################################################################
10233 15:37:51.789966
10234 15:37:52.056053 02780000 ################################################################
10235 15:37:52.056182
10236 15:37:52.347040 02800000 ################################################################
10237 15:37:52.347187
10238 15:37:52.622015 02880000 ################################################################
10239 15:37:52.622166
10240 15:37:52.892639 02900000 ################################################################
10241 15:37:52.892832
10242 15:37:53.142465 02980000 ################################################################
10243 15:37:53.142611
10244 15:37:53.429712 02a00000 ################################################################
10245 15:37:53.429844
10246 15:37:53.690291 02a80000 ################################################################
10247 15:37:53.690465
10248 15:37:53.948222 02b00000 ################################################################
10249 15:37:53.948359
10250 15:37:54.206934 02b80000 ################################################################
10251 15:37:54.207066
10252 15:37:54.457836 02c00000 ################################################################
10253 15:37:54.457970
10254 15:37:54.709415 02c80000 ################################################################
10255 15:37:54.709559
10256 15:37:54.963058 02d00000 ################################################################
10257 15:37:54.963192
10258 15:37:55.212711 02d80000 ################################################################
10259 15:37:55.212842
10260 15:37:55.465927 02e00000 ################################################################
10261 15:37:55.466065
10262 15:37:55.718765 02e80000 ################################################################
10263 15:37:55.718894
10264 15:37:55.993440 02f00000 ################################################################
10265 15:37:55.993577
10266 15:37:56.288271 02f80000 ################################################################
10267 15:37:56.288405
10268 15:37:56.564829 03000000 ################################################################
10269 15:37:56.564987
10270 15:37:56.825677 03080000 ################################################################
10271 15:37:56.825806
10272 15:37:57.081166 03100000 ################################################################
10273 15:37:57.081331
10274 15:37:57.345799 03180000 ################################################################
10275 15:37:57.345963
10276 15:37:57.604471 03200000 ################################################################
10277 15:37:57.604632
10278 15:37:57.871577 03280000 ################################################################
10279 15:37:57.871778
10280 15:37:58.127761 03300000 ################################################################
10281 15:37:58.127917
10282 15:37:58.381942 03380000 ################################################################
10283 15:37:58.382102
10284 15:37:58.636986 03400000 ################################################################
10285 15:37:58.637115
10286 15:37:58.895774 03480000 ################################################################
10287 15:37:58.895936
10288 15:37:59.152948 03500000 ################################################################
10289 15:37:59.153105
10290 15:37:59.426322 03580000 ################################################################
10291 15:37:59.426475
10292 15:37:59.675707 03600000 ################################################################
10293 15:37:59.675842
10294 15:37:59.931933 03680000 ################################################################
10295 15:37:59.932095
10296 15:38:00.181833 03700000 ################################################################
10297 15:38:00.181997
10298 15:38:00.395395 03780000 ################################################# done.
10299 15:38:00.395553
10300 15:38:00.399082 The bootfile was 58597270 bytes long.
10301 15:38:00.399175
10302 15:38:00.402242 Sending tftp read request... done.
10303 15:38:00.402348
10304 15:38:00.402416 Waiting for the transfer...
10305 15:38:00.402480
10306 15:38:00.405908 00000000 # done.
10307 15:38:00.406002
10308 15:38:00.412342 Command line loaded dynamically from TFTP file: 11331361/tftp-deploy-7nu3mvel/kernel/cmdline
10309 15:38:00.412519
10310 15:38:00.425969 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10311 15:38:00.426169
10312 15:38:00.429151 Loading FIT.
10313 15:38:00.429364
10314 15:38:00.432464 Image ramdisk-1 has 47512613 bytes.
10315 15:38:00.432667
10316 15:38:00.432834 Image fdt-1 has 47278 bytes.
10317 15:38:00.435629
10318 15:38:00.435775 Image kernel-1 has 11035343 bytes.
10319 15:38:00.435891
10320 15:38:00.445385 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10321 15:38:00.445670
10322 15:38:00.462402 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10323 15:38:00.462900
10324 15:38:00.468873 Choosing best match conf-1 for compat google,spherion-rev2.
10325 15:38:00.473396
10326 15:38:00.478276 Connected to device vid:did:rid of 1ae0:0028:00
10327 15:38:00.486178
10328 15:38:00.489541 tpm_get_response: command 0x17b, return code 0x0
10329 15:38:00.490092
10330 15:38:00.492770 ec_init: CrosEC protocol v3 supported (256, 248)
10331 15:38:00.497014
10332 15:38:00.499759 tpm_cleanup: add release locality here.
10333 15:38:00.500217
10334 15:38:00.500575 Shutting down all USB controllers.
10335 15:38:00.503531
10336 15:38:00.504085 Removing current net device
10337 15:38:00.504413
10338 15:38:00.509960 Exiting depthcharge with code 4 at timestamp: 65391863
10339 15:38:00.510468
10340 15:38:00.513198 LZMA decompressing kernel-1 to 0x821a6718
10341 15:38:00.513695
10342 15:38:00.516678 LZMA decompressing kernel-1 to 0x40000000
10343 15:38:01.903814
10344 15:38:01.904354 jumping to kernel
10345 15:38:01.905920 end: 2.2.4 bootloader-commands (duration 00:00:38) [common]
10346 15:38:01.906475 start: 2.2.5 auto-login-action (timeout 00:03:48) [common]
10347 15:38:01.906869 Setting prompt string to ['Linux version [0-9]']
10348 15:38:01.907237 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10349 15:38:01.907653 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10350 15:38:01.985059
10351 15:38:01.988722 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10352 15:38:01.992285 start: 2.2.5.1 login-action (timeout 00:03:48) [common]
10353 15:38:01.992852 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10354 15:38:01.993261 Setting prompt string to []
10355 15:38:01.993721 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10356 15:38:01.994187 Using line separator: #'\n'#
10357 15:38:01.994518 No login prompt set.
10358 15:38:01.994854 Parsing kernel messages
10359 15:38:01.995246 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10360 15:38:01.995878 [login-action] Waiting for messages, (timeout 00:03:48)
10361 15:38:02.012130 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j17681-arm64-gcc-10-defconfig-arm64-chromebook-c49jr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Aug 22 15:20:14 UTC 2023
10362 15:38:02.015228 [ 0.000000] random: crng init done
10363 15:38:02.018736 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10364 15:38:02.021801 [ 0.000000] efi: UEFI not found.
10365 15:38:02.032002 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10366 15:38:02.038703 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10367 15:38:02.048535 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10368 15:38:02.058023 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10369 15:38:02.064991 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10370 15:38:02.067975 [ 0.000000] printk: bootconsole [mtk8250] enabled
10371 15:38:02.077124 [ 0.000000] NUMA: No NUMA configuration found
10372 15:38:02.083745 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10373 15:38:02.089957 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10374 15:38:02.090414 [ 0.000000] Zone ranges:
10375 15:38:02.096650 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10376 15:38:02.099997 [ 0.000000] DMA32 empty
10377 15:38:02.106516 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10378 15:38:02.109872 [ 0.000000] Movable zone start for each node
10379 15:38:02.113188 [ 0.000000] Early memory node ranges
10380 15:38:02.119720 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10381 15:38:02.126870 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10382 15:38:02.133481 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10383 15:38:02.140306 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10384 15:38:02.146621 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10385 15:38:02.153104 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10386 15:38:02.209928 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10387 15:38:02.216592 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10388 15:38:02.222954 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10389 15:38:02.226357 [ 0.000000] psci: probing for conduit method from DT.
10390 15:38:02.232752 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10391 15:38:02.236126 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10392 15:38:02.242659 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10393 15:38:02.246183 [ 0.000000] psci: SMC Calling Convention v1.2
10394 15:38:02.252714 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10395 15:38:02.255803 [ 0.000000] Detected VIPT I-cache on CPU0
10396 15:38:02.262758 [ 0.000000] CPU features: detected: GIC system register CPU interface
10397 15:38:02.269248 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10398 15:38:02.275661 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10399 15:38:02.282837 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10400 15:38:02.289339 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10401 15:38:02.299431 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10402 15:38:02.302457 [ 0.000000] alternatives: applying boot alternatives
10403 15:38:02.309232 [ 0.000000] Fallback order for Node 0: 0
10404 15:38:02.315563 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10405 15:38:02.319113 [ 0.000000] Policy zone: Normal
10406 15:38:02.332298 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10407 15:38:02.342397 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10408 15:38:02.353033 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10409 15:38:02.363140 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10410 15:38:02.369472 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10411 15:38:02.372794 <6>[ 0.000000] software IO TLB: area num 8.
10412 15:38:02.429705 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10413 15:38:02.578787 <6>[ 0.000000] Memory: 7923156K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 429612K reserved, 32768K cma-reserved)
10414 15:38:02.585146 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10415 15:38:02.591618 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10416 15:38:02.595303 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10417 15:38:02.602061 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10418 15:38:02.608850 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10419 15:38:02.612206 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10420 15:38:02.621905 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10421 15:38:02.628338 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10422 15:38:02.631944 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10423 15:38:02.639682 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10424 15:38:02.643096 <6>[ 0.000000] GICv3: 608 SPIs implemented
10425 15:38:02.649792 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10426 15:38:02.652938 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10427 15:38:02.656468 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10428 15:38:02.666212 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10429 15:38:02.676200 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10430 15:38:02.689328 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10431 15:38:02.695691 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10432 15:38:02.704897 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10433 15:38:02.717962 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10434 15:38:02.724746 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10435 15:38:02.731244 <6>[ 0.009182] Console: colour dummy device 80x25
10436 15:38:02.741648 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10437 15:38:02.747703 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10438 15:38:02.751241 <6>[ 0.029251] LSM: Security Framework initializing
10439 15:38:02.758310 <6>[ 0.034191] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10440 15:38:02.768305 <6>[ 0.042051] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10441 15:38:02.775031 <6>[ 0.051533] cblist_init_generic: Setting adjustable number of callback queues.
10442 15:38:02.781859 <6>[ 0.059023] cblist_init_generic: Setting shift to 3 and lim to 1.
10443 15:38:02.791641 <6>[ 0.065400] cblist_init_generic: Setting adjustable number of callback queues.
10444 15:38:02.795104 <6>[ 0.072872] cblist_init_generic: Setting shift to 3 and lim to 1.
10445 15:38:02.801894 <6>[ 0.079271] rcu: Hierarchical SRCU implementation.
10446 15:38:02.808325 <6>[ 0.084284] rcu: Max phase no-delay instances is 1000.
10447 15:38:02.815038 <6>[ 0.091313] EFI services will not be available.
10448 15:38:02.817893 <6>[ 0.096311] smp: Bringing up secondary CPUs ...
10449 15:38:02.826394 <6>[ 0.101367] Detected VIPT I-cache on CPU1
10450 15:38:02.832994 <6>[ 0.101438] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10451 15:38:02.839298 <6>[ 0.101469] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10452 15:38:02.842622 <6>[ 0.101806] Detected VIPT I-cache on CPU2
10453 15:38:02.849161 <6>[ 0.101859] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10454 15:38:02.855695 <6>[ 0.101875] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10455 15:38:02.862435 <6>[ 0.102137] Detected VIPT I-cache on CPU3
10456 15:38:02.869351 <6>[ 0.102184] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10457 15:38:02.876151 <6>[ 0.102198] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10458 15:38:02.878817 <6>[ 0.102502] CPU features: detected: Spectre-v4
10459 15:38:02.885760 <6>[ 0.102508] CPU features: detected: Spectre-BHB
10460 15:38:02.889203 <6>[ 0.102513] Detected PIPT I-cache on CPU4
10461 15:38:02.895489 <6>[ 0.102569] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10462 15:38:02.902314 <6>[ 0.102587] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10463 15:38:02.909088 <6>[ 0.102880] Detected PIPT I-cache on CPU5
10464 15:38:02.915865 <6>[ 0.102944] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10465 15:38:02.922150 <6>[ 0.102961] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10466 15:38:02.925100 <6>[ 0.103245] Detected PIPT I-cache on CPU6
10467 15:38:02.931917 <6>[ 0.103311] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10468 15:38:02.938682 <6>[ 0.103328] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10469 15:38:02.945517 <6>[ 0.103630] Detected PIPT I-cache on CPU7
10470 15:38:02.951882 <6>[ 0.103696] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10471 15:38:02.958502 <6>[ 0.103713] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10472 15:38:02.962160 <6>[ 0.103761] smp: Brought up 1 node, 8 CPUs
10473 15:38:02.968763 <6>[ 0.245142] SMP: Total of 8 processors activated.
10474 15:38:02.971484 <6>[ 0.250064] CPU features: detected: 32-bit EL0 Support
10475 15:38:02.982154 <6>[ 0.255460] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10476 15:38:02.988668 <6>[ 0.264259] CPU features: detected: Common not Private translations
10477 15:38:02.991737 <6>[ 0.270736] CPU features: detected: CRC32 instructions
10478 15:38:02.998926 <6>[ 0.276087] CPU features: detected: RCpc load-acquire (LDAPR)
10479 15:38:03.005630 <6>[ 0.282085] CPU features: detected: LSE atomic instructions
10480 15:38:03.012001 <6>[ 0.287902] CPU features: detected: Privileged Access Never
10481 15:38:03.015132 <6>[ 0.293717] CPU features: detected: RAS Extension Support
10482 15:38:03.025249 <6>[ 0.299326] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10483 15:38:03.028300 <6>[ 0.306547] CPU: All CPU(s) started at EL2
10484 15:38:03.034851 <6>[ 0.310891] alternatives: applying system-wide alternatives
10485 15:38:03.043996 <6>[ 0.321602] devtmpfs: initialized
10486 15:38:03.056176 <6>[ 0.330596] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10487 15:38:03.066113 <6>[ 0.340553] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10488 15:38:03.069506 <6>[ 0.348133] pinctrl core: initialized pinctrl subsystem
10489 15:38:03.077197 <6>[ 0.354812] DMI not present or invalid.
10490 15:38:03.083967 <6>[ 0.359222] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10491 15:38:03.090208 <6>[ 0.366091] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10492 15:38:03.100262 <6>[ 0.373675] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10493 15:38:03.107038 <6>[ 0.381906] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10494 15:38:03.113337 <6>[ 0.390151] audit: initializing netlink subsys (disabled)
10495 15:38:03.119717 <5>[ 0.395840] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10496 15:38:03.126670 <6>[ 0.396547] thermal_sys: Registered thermal governor 'step_wise'
10497 15:38:03.133449 <6>[ 0.403809] thermal_sys: Registered thermal governor 'power_allocator'
10498 15:38:03.136449 <6>[ 0.410067] cpuidle: using governor menu
10499 15:38:03.143642 <6>[ 0.421025] NET: Registered PF_QIPCRTR protocol family
10500 15:38:03.150261 <6>[ 0.426503] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10501 15:38:03.156508 <6>[ 0.433606] ASID allocator initialised with 32768 entries
10502 15:38:03.163474 <6>[ 0.440185] Serial: AMBA PL011 UART driver
10503 15:38:03.171301 <4>[ 0.449027] Trying to register duplicate clock ID: 134
10504 15:38:03.227304 <6>[ 0.508408] KASLR enabled
10505 15:38:03.241534 <6>[ 0.516077] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10506 15:38:03.248319 <6>[ 0.523092] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10507 15:38:03.254931 <6>[ 0.529581] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10508 15:38:03.261829 <6>[ 0.536587] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10509 15:38:03.268196 <6>[ 0.543076] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10510 15:38:03.274916 <6>[ 0.550080] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10511 15:38:03.281132 <6>[ 0.556564] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10512 15:38:03.288118 <6>[ 0.563567] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10513 15:38:03.291363 <6>[ 0.571021] ACPI: Interpreter disabled.
10514 15:38:03.299722 <6>[ 0.577426] iommu: Default domain type: Translated
10515 15:38:03.306437 <6>[ 0.582563] iommu: DMA domain TLB invalidation policy: strict mode
10516 15:38:03.310148 <5>[ 0.589219] SCSI subsystem initialized
10517 15:38:03.316533 <6>[ 0.593464] usbcore: registered new interface driver usbfs
10518 15:38:03.323285 <6>[ 0.599197] usbcore: registered new interface driver hub
10519 15:38:03.326258 <6>[ 0.604749] usbcore: registered new device driver usb
10520 15:38:03.333538 <6>[ 0.610874] pps_core: LinuxPPS API ver. 1 registered
10521 15:38:03.342899 <6>[ 0.616069] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10522 15:38:03.346555 <6>[ 0.625412] PTP clock support registered
10523 15:38:03.350322 <6>[ 0.629653] EDAC MC: Ver: 3.0.0
10524 15:38:03.357119 <6>[ 0.634840] FPGA manager framework
10525 15:38:03.360150 <6>[ 0.638518] Advanced Linux Sound Architecture Driver Initialized.
10526 15:38:03.364587 <6>[ 0.645286] vgaarb: loaded
10527 15:38:03.370875 <6>[ 0.648457] clocksource: Switched to clocksource arch_sys_counter
10528 15:38:03.377601 <5>[ 0.654904] VFS: Disk quotas dquot_6.6.0
10529 15:38:03.384062 <6>[ 0.659090] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10530 15:38:03.387673 <6>[ 0.666264] pnp: PnP ACPI: disabled
10531 15:38:03.395214 <6>[ 0.672961] NET: Registered PF_INET protocol family
10532 15:38:03.401879 <6>[ 0.678552] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10533 15:38:03.416159 <6>[ 0.690874] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10534 15:38:03.426412 <6>[ 0.699684] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10535 15:38:03.432759 <6>[ 0.707655] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10536 15:38:03.442449 <6>[ 0.716353] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10537 15:38:03.449379 <6>[ 0.726109] TCP: Hash tables configured (established 65536 bind 65536)
10538 15:38:03.456154 <6>[ 0.732980] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10539 15:38:03.466099 <6>[ 0.740179] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10540 15:38:03.469339 <6>[ 0.747884] NET: Registered PF_UNIX/PF_LOCAL protocol family
10541 15:38:03.476401 <6>[ 0.754034] RPC: Registered named UNIX socket transport module.
10542 15:38:03.483075 <6>[ 0.760190] RPC: Registered udp transport module.
10543 15:38:03.486681 <6>[ 0.765125] RPC: Registered tcp transport module.
10544 15:38:03.492951 <6>[ 0.770057] RPC: Registered tcp NFSv4.1 backchannel transport module.
10545 15:38:03.499418 <6>[ 0.776725] PCI: CLS 0 bytes, default 64
10546 15:38:03.503233 <6>[ 0.781128] Unpacking initramfs...
10547 15:38:03.509655 <6>[ 0.784833] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10548 15:38:03.519238 <6>[ 0.793472] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10549 15:38:03.523040 <6>[ 0.802311] kvm [1]: IPA Size Limit: 40 bits
10550 15:38:03.529623 <6>[ 0.806838] kvm [1]: GICv3: no GICV resource entry
10551 15:38:03.532324 <6>[ 0.811860] kvm [1]: disabling GICv2 emulation
10552 15:38:03.539304 <6>[ 0.816548] kvm [1]: GIC system register CPU interface enabled
10553 15:38:03.542733 <6>[ 0.822719] kvm [1]: vgic interrupt IRQ18
10554 15:38:03.550991 <6>[ 0.828499] kvm [1]: VHE mode initialized successfully
10555 15:38:03.557650 <5>[ 0.834829] Initialise system trusted keyrings
10556 15:38:03.564322 <6>[ 0.839627] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10557 15:38:03.572343 <6>[ 0.849634] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10558 15:38:03.578680 <5>[ 0.856009] NFS: Registering the id_resolver key type
10559 15:38:03.581656 <5>[ 0.861310] Key type id_resolver registered
10560 15:38:03.588318 <5>[ 0.865727] Key type id_legacy registered
10561 15:38:03.595467 <6>[ 0.870004] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10562 15:38:03.602094 <6>[ 0.876926] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10563 15:38:03.608473 <6>[ 0.884652] 9p: Installing v9fs 9p2000 file system support
10564 15:38:03.645116 <5>[ 0.922737] Key type asymmetric registered
10565 15:38:03.648228 <5>[ 0.927066] Asymmetric key parser 'x509' registered
10566 15:38:03.658338 <6>[ 0.932201] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10567 15:38:03.661138 <6>[ 0.939815] io scheduler mq-deadline registered
10568 15:38:03.664697 <6>[ 0.944576] io scheduler kyber registered
10569 15:38:03.683699 <6>[ 0.961566] EINJ: ACPI disabled.
10570 15:38:03.716337 <4>[ 0.987511] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 15:38:03.726037 <4>[ 0.998155] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10572 15:38:03.741597 <6>[ 1.019001] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10573 15:38:03.749232 <6>[ 1.026978] printk: console [ttyS0] disabled
10574 15:38:03.777041 <6>[ 1.051625] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10575 15:38:03.783829 <6>[ 1.061102] printk: console [ttyS0] enabled
10576 15:38:03.787235 <6>[ 1.061102] printk: console [ttyS0] enabled
10577 15:38:03.794162 <6>[ 1.069996] printk: bootconsole [mtk8250] disabled
10578 15:38:03.797091 <6>[ 1.069996] printk: bootconsole [mtk8250] disabled
10579 15:38:03.803685 <6>[ 1.081247] SuperH (H)SCI(F) driver initialized
10580 15:38:03.807497 <6>[ 1.086513] msm_serial: driver initialized
10581 15:38:03.821249 <6>[ 1.095500] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10582 15:38:03.831701 <6>[ 1.104046] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10583 15:38:03.837384 <6>[ 1.112588] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10584 15:38:03.847737 <6>[ 1.121218] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10585 15:38:03.854168 <6>[ 1.129925] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10586 15:38:03.864571 <6>[ 1.138646] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10587 15:38:03.873929 <6>[ 1.147187] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10588 15:38:03.880835 <6>[ 1.155992] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10589 15:38:03.890757 <6>[ 1.164537] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10590 15:38:03.902796 <6>[ 1.180369] loop: module loaded
10591 15:38:03.909187 <6>[ 1.186354] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10592 15:38:03.931690 <4>[ 1.209780] mtk-pmic-keys: Failed to locate of_node [id: -1]
10593 15:38:03.939019 <6>[ 1.216712] megasas: 07.719.03.00-rc1
10594 15:38:03.948371 <6>[ 1.226322] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10595 15:38:03.957905 <6>[ 1.235826] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10596 15:38:03.974421 <6>[ 1.251813] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10597 15:38:04.028365 <6>[ 1.299819] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10598 15:38:05.488575 <6>[ 2.766325] Freeing initrd memory: 46396K
10599 15:38:05.498401 <6>[ 2.776645] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10600 15:38:05.509665 <6>[ 2.787809] tun: Universal TUN/TAP device driver, 1.6
10601 15:38:05.512758 <6>[ 2.793890] thunder_xcv, ver 1.0
10602 15:38:05.516432 <6>[ 2.797398] thunder_bgx, ver 1.0
10603 15:38:05.519822 <6>[ 2.800896] nicpf, ver 1.0
10604 15:38:05.530275 <6>[ 2.804939] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10605 15:38:05.533680 <6>[ 2.812414] hns3: Copyright (c) 2017 Huawei Corporation.
10606 15:38:05.536932 <6>[ 2.818003] hclge is initializing
10607 15:38:05.544154 <6>[ 2.821585] e1000: Intel(R) PRO/1000 Network Driver
10608 15:38:05.550771 <6>[ 2.826714] e1000: Copyright (c) 1999-2006 Intel Corporation.
10609 15:38:05.553463 <6>[ 2.832729] e1000e: Intel(R) PRO/1000 Network Driver
10610 15:38:05.560095 <6>[ 2.837944] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10611 15:38:05.566935 <6>[ 2.844129] igb: Intel(R) Gigabit Ethernet Network Driver
10612 15:38:05.573554 <6>[ 2.849780] igb: Copyright (c) 2007-2014 Intel Corporation.
10613 15:38:05.580186 <6>[ 2.855617] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10614 15:38:05.586627 <6>[ 2.862134] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10615 15:38:05.590386 <6>[ 2.868620] sky2: driver version 1.30
10616 15:38:05.596600 <6>[ 2.873624] VFIO - User Level meta-driver version: 0.3
10617 15:38:05.603629 <6>[ 2.881923] usbcore: registered new interface driver usb-storage
10618 15:38:05.611116 <6>[ 2.888369] usbcore: registered new device driver onboard-usb-hub
10619 15:38:05.619493 <6>[ 2.897549] mt6397-rtc mt6359-rtc: registered as rtc0
10620 15:38:05.629516 <6>[ 2.903036] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-22T15:37:00 UTC (1692718620)
10621 15:38:05.633158 <6>[ 2.912642] i2c_dev: i2c /dev entries driver
10622 15:38:05.649977 <6>[ 2.924496] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10623 15:38:05.669111 <6>[ 2.947500] cpu cpu0: EM: created perf domain
10624 15:38:05.672784 <6>[ 2.952497] cpu cpu4: EM: created perf domain
10625 15:38:05.680509 <6>[ 2.958117] sdhci: Secure Digital Host Controller Interface driver
10626 15:38:05.686599 <6>[ 2.964551] sdhci: Copyright(c) Pierre Ossman
10627 15:38:05.693773 <6>[ 2.969503] Synopsys Designware Multimedia Card Interface Driver
10628 15:38:05.700145 <6>[ 2.976141] sdhci-pltfm: SDHCI platform and OF driver helper
10629 15:38:05.703681 <6>[ 2.976251] mmc0: CQHCI version 5.10
10630 15:38:05.710314 <6>[ 2.986085] ledtrig-cpu: registered to indicate activity on CPUs
10631 15:38:05.716845 <6>[ 2.993106] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10632 15:38:05.723723 <6>[ 3.000168] usbcore: registered new interface driver usbhid
10633 15:38:05.727028 <6>[ 3.005993] usbhid: USB HID core driver
10634 15:38:05.733710 <6>[ 3.010196] spi_master spi0: will run message pump with realtime priority
10635 15:38:05.780567 <6>[ 3.052037] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10636 15:38:05.799723 <6>[ 3.067663] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10637 15:38:05.802587 <6>[ 3.082813] mmc0: Command Queue Engine enabled
10638 15:38:05.810193 <6>[ 3.082910] cros-ec-spi spi0.0: Chrome EC device registered
10639 15:38:05.816655 <6>[ 3.087538] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10640 15:38:05.823455 <6>[ 3.100728] mmcblk0: mmc0:0001 DA4128 116 GiB
10641 15:38:05.833437 <6>[ 3.108264] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10642 15:38:05.840199 <6>[ 3.112011] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10643 15:38:05.847069 <6>[ 3.118676] NET: Registered PF_PACKET protocol family
10644 15:38:05.849740 <6>[ 3.124584] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10645 15:38:05.856290 <6>[ 3.128858] 9pnet: Installing 9P2000 support
10646 15:38:05.860114 <6>[ 3.134663] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10647 15:38:05.866546 <5>[ 3.138552] Key type dns_resolver registered
10648 15:38:05.873328 <6>[ 3.144336] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10649 15:38:05.876495 <6>[ 3.148713] registered taskstats version 1
10650 15:38:05.880211 <5>[ 3.159149] Loading compiled-in X.509 certificates
10651 15:38:05.916120 <4>[ 3.187375] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 15:38:05.925658 <4>[ 3.198077] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 15:38:05.932611 <3>[ 3.208602] debugfs: File 'uA_load' in directory '/' already present!
10654 15:38:05.938613 <3>[ 3.215301] debugfs: File 'min_uV' in directory '/' already present!
10655 15:38:05.945547 <3>[ 3.221971] debugfs: File 'max_uV' in directory '/' already present!
10656 15:38:05.952146 <3>[ 3.228588] debugfs: File 'constraint_flags' in directory '/' already present!
10657 15:38:05.969397 <3>[ 3.243894] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10658 15:38:05.977831 <6>[ 3.255887] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10659 15:38:05.984368 <6>[ 3.262752] xhci-mtk 11200000.usb: xHCI Host Controller
10660 15:38:05.991406 <6>[ 3.268269] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10661 15:38:06.001593 <6>[ 3.276228] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10662 15:38:06.008358 <6>[ 3.285658] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10663 15:38:06.014849 <6>[ 3.291744] xhci-mtk 11200000.usb: xHCI Host Controller
10664 15:38:06.021368 <6>[ 3.297226] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10665 15:38:06.027735 <6>[ 3.304883] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10666 15:38:06.035025 <6>[ 3.312729] hub 1-0:1.0: USB hub found
10667 15:38:06.037864 <6>[ 3.316770] hub 1-0:1.0: 1 port detected
10668 15:38:06.047838 <6>[ 3.321046] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10669 15:38:06.051379 <6>[ 3.329769] hub 2-0:1.0: USB hub found
10670 15:38:06.054298 <6>[ 3.333790] hub 2-0:1.0: 1 port detected
10671 15:38:06.063928 <6>[ 3.341869] mtk-msdc 11f70000.mmc: Got CD GPIO
10672 15:38:06.074300 <6>[ 3.348703] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10673 15:38:06.080334 <6>[ 3.356731] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10674 15:38:06.090715 <4>[ 3.364627] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10675 15:38:06.100678 <6>[ 3.374150] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10676 15:38:06.106988 <6>[ 3.382231] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10677 15:38:06.113814 <6>[ 3.390317] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10678 15:38:06.124220 <6>[ 3.398296] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10679 15:38:06.130654 <6>[ 3.406117] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10680 15:38:06.140250 <6>[ 3.413948] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10681 15:38:06.150523 <6>[ 3.424587] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10682 15:38:06.156876 <6>[ 3.432983] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10683 15:38:06.166522 <6>[ 3.441325] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10684 15:38:06.176374 <6>[ 3.449676] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10685 15:38:06.182941 <6>[ 3.458015] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10686 15:38:06.193179 <6>[ 3.466365] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10687 15:38:06.199417 <6>[ 3.474703] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10688 15:38:06.209690 <6>[ 3.483053] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10689 15:38:06.216603 <6>[ 3.491393] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10690 15:38:06.226824 <6>[ 3.499742] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10691 15:38:06.232887 <6>[ 3.508080] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10692 15:38:06.243122 <6>[ 3.516419] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10693 15:38:06.249811 <6>[ 3.524759] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10694 15:38:06.259235 <6>[ 3.533098] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10695 15:38:06.266612 <6>[ 3.541436] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10696 15:38:06.272845 <6>[ 3.550229] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10697 15:38:06.279364 <6>[ 3.557443] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10698 15:38:06.285707 <6>[ 3.564220] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10699 15:38:06.296266 <6>[ 3.570984] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10700 15:38:06.302801 <6>[ 3.577926] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10701 15:38:06.309237 <6>[ 3.584793] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10702 15:38:06.319570 <6>[ 3.593924] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10703 15:38:06.329405 <6>[ 3.603043] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10704 15:38:06.339780 <6>[ 3.612359] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10705 15:38:06.349589 <6>[ 3.621834] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10706 15:38:06.356295 <6>[ 3.631303] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10707 15:38:06.365877 <6>[ 3.640423] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10708 15:38:06.376005 <6>[ 3.649891] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10709 15:38:06.386274 <6>[ 3.659009] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10710 15:38:06.395875 <6>[ 3.668306] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10711 15:38:06.405604 <6>[ 3.678465] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10712 15:38:06.415749 <6>[ 3.690034] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10713 15:38:06.446257 <6>[ 3.720982] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10714 15:38:06.473963 <6>[ 3.752130] hub 2-1:1.0: USB hub found
10715 15:38:06.477607 <6>[ 3.756613] hub 2-1:1.0: 3 ports detected
10716 15:38:06.597775 <6>[ 3.872750] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10717 15:38:06.753075 <6>[ 4.030914] hub 1-1:1.0: USB hub found
10718 15:38:06.756525 <6>[ 4.035382] hub 1-1:1.0: 4 ports detected
10719 15:38:06.830205 <6>[ 4.105032] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10720 15:38:07.077733 <6>[ 4.352772] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10721 15:38:07.210968 <6>[ 4.488791] hub 1-1.4:1.0: USB hub found
10722 15:38:07.213813 <6>[ 4.493467] hub 1-1.4:1.0: 2 ports detected
10723 15:38:07.509911 <6>[ 4.784750] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10724 15:38:07.701746 <6>[ 4.976745] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10725 15:38:18.706634 <6>[ 15.989743] ALSA device list:
10726 15:38:18.713082 <6>[ 15.993042] No soundcards found.
10727 15:38:18.720724 <6>[ 16.001018] Freeing unused kernel memory: 8384K
10728 15:38:18.724332 <6>[ 16.006125] Run /init as init process
10729 15:38:18.773475 <6>[ 16.053548] NET: Registered PF_INET6 protocol family
10730 15:38:18.780081 <6>[ 16.059732] Segment Routing with IPv6
10731 15:38:18.783484 <6>[ 16.063683] In-situ OAM (IOAM) with IPv6
10732 15:38:18.817419 <30>[ 16.077881] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10733 15:38:18.821040 <30>[ 16.101655] systemd[1]: Detected architecture arm64.
10734 15:38:18.821151
10735 15:38:18.827389 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10736 15:38:18.827524
10737 15:38:18.840542 <30>[ 16.120759] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10738 15:38:18.975391 <30>[ 16.252048] systemd[1]: Queued start job for default target Graphical Interface.
10739 15:38:19.029690 <30>[ 16.309614] systemd[1]: Created slice system-getty.slice.
10740 15:38:19.036303 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10741 15:38:19.053778 <30>[ 16.333829] systemd[1]: Created slice system-modprobe.slice.
10742 15:38:19.060454 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10743 15:38:19.077073 <30>[ 16.357250] systemd[1]: Created slice system-serial\x2dgetty.slice.
10744 15:38:19.086908 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10745 15:38:19.101802 <30>[ 16.382118] systemd[1]: Created slice User and Session Slice.
10746 15:38:19.108433 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10747 15:38:19.129114 <30>[ 16.405558] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10748 15:38:19.138497 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10749 15:38:19.156337 <30>[ 16.432933] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10750 15:38:19.162997 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10751 15:38:19.183537 <30>[ 16.456817] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10752 15:38:19.190216 <30>[ 16.468969] systemd[1]: Reached target Local Encrypted Volumes.
10753 15:38:19.196703 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10754 15:38:19.213031 <30>[ 16.493301] systemd[1]: Reached target Paths.
10755 15:38:19.219793 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10756 15:38:19.232411 <30>[ 16.512750] systemd[1]: Reached target Remote File Systems.
10757 15:38:19.239081 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10758 15:38:19.257006 <30>[ 16.537107] systemd[1]: Reached target Slices.
10759 15:38:19.263360 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10760 15:38:19.276696 <30>[ 16.556763] systemd[1]: Reached target Swap.
10761 15:38:19.279692 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10762 15:38:19.300395 <30>[ 16.577256] systemd[1]: Listening on initctl Compatibility Named Pipe.
10763 15:38:19.306965 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10764 15:38:19.313557 <30>[ 16.592512] systemd[1]: Listening on Journal Audit Socket.
10765 15:38:19.320143 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10766 15:38:19.332796 <30>[ 16.613211] systemd[1]: Listening on Journal Socket (/dev/log).
10767 15:38:19.339913 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10768 15:38:19.357719 <30>[ 16.637978] systemd[1]: Listening on Journal Socket.
10769 15:38:19.364713 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10770 15:38:19.380462 <30>[ 16.657436] systemd[1]: Listening on Network Service Netlink Socket.
10771 15:38:19.387136 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10772 15:38:19.401043 <30>[ 16.681278] systemd[1]: Listening on udev Control Socket.
10773 15:38:19.407445 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10774 15:38:19.425627 <30>[ 16.705822] systemd[1]: Listening on udev Kernel Socket.
10775 15:38:19.432223 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10776 15:38:19.480936 <30>[ 16.761046] systemd[1]: Mounting Huge Pages File System...
10777 15:38:19.487510 Mounting [0;1;39mHuge Pages File System[0m...
10778 15:38:19.503564 <30>[ 16.783665] systemd[1]: Mounting POSIX Message Queue File System...
10779 15:38:19.510497 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10780 15:38:19.526465 <30>[ 16.806628] systemd[1]: Mounting Kernel Debug File System...
10781 15:38:19.533091 Mounting [0;1;39mKernel Debug File System[0m...
10782 15:38:19.551889 <30>[ 16.829027] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10783 15:38:19.563368 <30>[ 16.840073] systemd[1]: Starting Create list of static device nodes for the current kernel...
10784 15:38:19.569581 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10785 15:38:19.616878 <30>[ 16.897140] systemd[1]: Starting Load Kernel Module configfs...
10786 15:38:19.623717 Starting [0;1;39mLoad Kernel Module configfs[0m...
10787 15:38:19.640902 <30>[ 16.921251] systemd[1]: Starting Load Kernel Module drm...
10788 15:38:19.647471 Starting [0;1;39mLoad Kernel Module drm[0m...
10789 15:38:19.664411 <30>[ 16.941150] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10790 15:38:19.701266 <30>[ 16.981146] systemd[1]: Starting Journal Service...
10791 15:38:19.704231 Starting [0;1;39mJournal Service[0m...
10792 15:38:19.724078 <30>[ 17.003820] systemd[1]: Starting Load Kernel Modules...
10793 15:38:19.730732 Starting [0;1;39mLoad Kernel Modules[0m...
10794 15:38:19.750911 <30>[ 17.027328] systemd[1]: Starting Remount Root and Kernel File Systems...
10795 15:38:19.757441 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10796 15:38:19.773768 <30>[ 17.053691] systemd[1]: Starting Coldplug All udev Devices...
10797 15:38:19.780449 Starting [0;1;39mColdplug All udev Devices[0m...
10798 15:38:19.795421 <30>[ 17.075360] systemd[1]: Started Journal Service.
10799 15:38:19.802220 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10800 15:38:19.820191 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10801 15:38:19.837953 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10802 15:38:19.854829 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10803 15:38:19.873570 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10804 15:38:19.891374 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10805 15:38:19.911389 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10806 15:38:19.925589 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10807 15:38:19.945553 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10808 15:38:19.964665 See 'systemctl status systemd-remount-fs.service' for details.
10809 15:38:20.025279 Mounting [0;1;39mKernel Configuration File System[0m...
10810 15:38:20.050016 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10811 15:38:20.062727 <46>[ 17.339728] systemd-journald[177]: Received client request to flush runtime journal.
10812 15:38:20.073963 Starting [0;1;39mLoad/Save Random Seed[0m...
10813 15:38:20.096330 Starting [0;1;39mApply Kernel Variables[0m...
10814 15:38:20.122637 Starting [0;1;39mCreate System Users[0m...
10815 15:38:20.145773 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10816 15:38:20.161769 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10817 15:38:20.181728 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10818 15:38:20.194580 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10819 15:38:20.210568 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10820 15:38:20.225279 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10821 15:38:20.277387 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10822 15:38:20.299984 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10823 15:38:20.312691 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10824 15:38:20.332422 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10825 15:38:20.356149 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10826 15:38:20.384882 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10827 15:38:20.407116 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10828 15:38:20.426245 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10829 15:38:20.471820 Starting [0;1;39mNetwork Service[0m...
10830 15:38:20.498000 Starting [0;1;39mNetwork Time Synchronization[0m...
10831 15:38:20.520203 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10832 15:38:20.541279 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10833 15:38:20.578796 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10834 15:38:20.594374 <6>[ 17.871154] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10835 15:38:20.607356 <6>[ 17.884067] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10836 15:38:20.617013 <6>[ 17.892905] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10837 15:38:20.624037 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10838 15:38:20.633772 <3>[ 17.909466] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10839 15:38:20.640557 <3>[ 17.917782] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10840 15:38:20.650461 <3>[ 17.925913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10841 15:38:20.656986 <6>[ 17.927717] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10842 15:38:20.663733 <6>[ 17.933453] usbcore: registered new interface driver r8152
10843 15:38:20.678377 <4>[ 17.954935] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10844 15:38:20.681694 <6>[ 17.956807] remoteproc remoteproc0: scp is available
10845 15:38:20.692083 <3>[ 17.963547] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10846 15:38:20.698595 <4>[ 17.963694] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10847 15:38:20.701824 <6>[ 17.967807] remoteproc remoteproc0: powering up scp
10848 15:38:20.711751 <3>[ 17.975756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10849 15:38:20.714871 <6>[ 17.977114] mc: Linux media interface: v0.10
10850 15:38:20.725105 <6>[ 17.983192] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10851 15:38:20.731738 <3>[ 17.988363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10852 15:38:20.738267 <6>[ 17.996416] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10853 15:38:20.744670 <3>[ 18.000878] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 15:38:20.754968 <6>[ 18.013045] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10855 15:38:20.761560 <3>[ 18.017374] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 15:38:20.768275 <6>[ 18.031810] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10857 15:38:20.774565 <3>[ 18.040066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 15:38:20.781467 <6>[ 18.046423] pci_bus 0000:00: root bus resource [bus 00-ff]
10859 15:38:20.788077 <6>[ 18.047355] videodev: Linux video capture interface: v2.00
10860 15:38:20.794914 <6>[ 18.049672] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10861 15:38:20.805608 <3>[ 18.053441] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 15:38:20.811760 <6>[ 18.061293] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10863 15:38:20.821571 <6>[ 18.061297] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10864 15:38:20.828111 <6>[ 18.061362] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10865 15:38:20.835218 <3>[ 18.067156] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10866 15:38:20.846499 <6>[ 18.071711] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10867 15:38:20.852690 <6>[ 18.072936] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10868 15:38:20.859567 <4>[ 18.074556] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10869 15:38:20.865815 <4>[ 18.074556] Fallback method does not support PEC.
10870 15:38:20.873396 <3>[ 18.080554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 15:38:20.876555 <6>[ 18.088937] pci 0000:00:00.0: supports D1 D2
10872 15:38:20.886555 <3>[ 18.091763] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10873 15:38:20.896108 <3>[ 18.095864] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10874 15:38:20.902778 <6>[ 18.105670] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10875 15:38:20.909296 <3>[ 18.111931] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 15:38:20.919271 <6>[ 18.121018] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10877 15:38:20.925956 <3>[ 18.129407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 15:38:20.935800 <3>[ 18.129625] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 15:38:20.942275 <3>[ 18.130385] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10880 15:38:20.952475 <6>[ 18.133309] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10881 15:38:20.962648 <6>[ 18.133726] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10882 15:38:20.968952 <6>[ 18.136881] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10883 15:38:20.975581 <6>[ 18.137087] usbcore: registered new interface driver cdc_ether
10884 15:38:20.982262 <6>[ 18.145443] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10885 15:38:20.989544 <6>[ 18.145451] remoteproc remoteproc0: remote processor scp is now up
10886 15:38:20.999500 <6>[ 18.145454] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10887 15:38:21.006312 <6>[ 18.148454] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10888 15:38:21.013105 <3>[ 18.150717] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 15:38:21.019739 <6>[ 18.158581] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10890 15:38:21.026586 <6>[ 18.158620] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10891 15:38:21.033333 <6>[ 18.160476] usbcore: registered new interface driver r8153_ecm
10892 15:38:21.039891 <6>[ 18.163257] r8152 2-1.3:1.0 eth0: v1.12.13
10893 15:38:21.046270 <3>[ 18.164490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10894 15:38:21.052982 <3>[ 18.164551] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10895 15:38:21.062670 <6>[ 18.171915] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10896 15:38:21.066606 <6>[ 18.172907] Bluetooth: Core ver 2.22
10897 15:38:21.073313 <6>[ 18.173072] NET: Registered PF_BLUETOOTH protocol family
10898 15:38:21.076710 <6>[ 18.173077] Bluetooth: HCI device and connection manager initialized
10899 15:38:21.083532 <6>[ 18.173122] Bluetooth: HCI socket layer initialized
10900 15:38:21.090059 <6>[ 18.173141] Bluetooth: L2CAP socket layer initialized
10901 15:38:21.093013 <6>[ 18.173169] Bluetooth: SCO socket layer initialized
10902 15:38:21.103250 <6>[ 18.175178] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10903 15:38:21.109778 <6>[ 18.177612] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10904 15:38:21.116389 <6>[ 18.199473] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10905 15:38:21.119795 <6>[ 18.203289] pci 0000:01:00.0: supports D1 D2
10906 15:38:21.126514 <6>[ 18.205039] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10907 15:38:21.139927 <6>[ 18.206826] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10908 15:38:21.146337 <6>[ 18.207006] usbcore: registered new interface driver uvcvideo
10909 15:38:21.156331 <3>[ 18.213949] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 15:38:21.162910 <6>[ 18.220071] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10911 15:38:21.166521 <6>[ 18.221089] usbcore: registered new interface driver btusb
10912 15:38:21.179798 <4>[ 18.229461] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10913 15:38:21.183282 <6>[ 18.232518] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10914 15:38:21.193300 <6>[ 18.232557] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10915 15:38:21.199902 <6>[ 18.232561] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10916 15:38:21.210127 <6>[ 18.232568] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10917 15:38:21.216475 <6>[ 18.232581] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10918 15:38:21.226699 <6>[ 18.232594] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10919 15:38:21.230179 <6>[ 18.232606] pci 0000:00:00.0: PCI bridge to [bus 01]
10920 15:38:21.239942 <6>[ 18.232611] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10921 15:38:21.242960 <6>[ 18.232754] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10922 15:38:21.250209 <6>[ 18.233206] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10923 15:38:21.256778 <6>[ 18.233491] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10924 15:38:21.263463 <6>[ 18.250164] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10925 15:38:21.270134 <3>[ 18.254662] Bluetooth: hci0: Failed to load firmware file (-2)
10926 15:38:21.276680 <5>[ 18.263235] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10927 15:38:21.283605 <3>[ 18.269309] Bluetooth: hci0: Failed to set up firmware (-2)
10928 15:38:21.293522 <4>[ 18.269320] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10929 15:38:21.303449 <3>[ 18.523880] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10930 15:38:21.309935 <3>[ 18.542376] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 15:38:21.320024 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10932 15:38:21.330408 <5>[ 18.607621] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10933 15:38:21.336877 <4>[ 18.614497] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10934 15:38:21.343572 <6>[ 18.623374] cfg80211: failed to load regulatory.db
10935 15:38:21.389883 <6>[ 18.666684] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10936 15:38:21.396800 <3>[ 18.667206] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 15:38:21.402736 <6>[ 18.674186] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10938 15:38:21.420092 <3>[ 18.697158] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10939 15:38:21.428340 <6>[ 18.708649] mt7921e 0000:01:00.0: ASIC revision: 79610010
10940 15:38:21.455605 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10941 15:38:21.475349 [[0;32m OK [<3>[ 18.749512] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 15:38:21.478368 0m] Reached target [0;1;39mBluetooth[0m.
10943 15:38:21.499737 [[0;32m OK [0m] Reached target [0;1;39mSyst<3>[ 18.776654] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 15:38:21.503024 em Time Set[0m.
10945 15:38:21.518789 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10946 15:38:21.535669 <4>[ 18.808925] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10947 15:38:21.546143 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10948 15:38:21.604609 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10949 15:38:21.628869 Starting [0;1;39mNetwork Name Resolution[0m...
10950 15:38:21.654049 <4>[ 18.927759] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10951 15:38:21.664166 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10952 15:38:21.678410 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10953 15:38:21.698177 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10954 15:38:21.712456 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10955 15:38:21.724953 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10956 15:38:21.745258 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10957 15:38:21.773583 [[0;32m OK [0m] Reached target [0;1;39mSock<4>[ 19.047670] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10958 15:38:21.774025 ets[0m.
10959 15:38:21.790999 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10960 15:38:21.853673 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10961 15:38:21.894146 <4>[ 19.167620] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10962 15:38:21.907520 Starting [0;1;39mUser Login Management[0m...
10963 15:38:21.925697 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10964 15:38:21.945581 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10965 15:38:21.965670 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10966 15:38:21.985041 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10967 15:38:22.013194 [[0;32m OK [0m] Reached target [0;1;39mHost<4>[ 19.287317] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10968 15:38:22.016103 and Network Name Lookups[0m.
10969 15:38:22.081770 Starting [0;1;39mPermit User Sessions[0m...
10970 15:38:22.098703 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10971 15:38:22.121709 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10972 15:38:22.135045 <4>[ 19.407852] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10973 15:38:22.135130
10974 15:38:22.186068 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10975 15:38:22.206615 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10976 15:38:22.225928 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10977 15:38:22.254049 [[0;32m OK [0m] Reached target [0;1;39mMult<4>[ 19.527561] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10978 15:38:22.257066 i-User System[0m.
10979 15:38:22.274241 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10980 15:38:22.325236 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10981 15:38:22.375744 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System R<4>[ 19.647870] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10982 15:38:22.375847 unlevel Changes[0m.
10983 15:38:22.424316
10984 15:38:22.424398
10985 15:38:22.427893 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10986 15:38:22.427975
10987 15:38:22.430871 debian-bullseye-arm64 login: root (automatic login)
10988 15:38:22.430953
10989 15:38:22.431016
10990 15:38:22.447271 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Tue Aug 22 15:20:14 UTC 2023 aarch64
10991 15:38:22.447354
10992 15:38:22.454128 The programs included with the Debian GNU/Linux system are free software;
10993 15:38:22.460618 the exact distribution terms for each program are described in the
10994 15:38:22.464291 individual files in /usr/share/doc/*/copyright.
10995 15:38:22.464372
10996 15:38:22.470722 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10997 15:38:22.474130 permitted by applicable law.
10998 15:38:22.474502 Matched prompt #10: / #
11000 15:38:22.474706 Setting prompt string to ['/ #']
11001 15:38:22.474797 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11003 15:38:22.474986 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11004 15:38:22.475071 start: 2.2.6 expect-shell-connection (timeout 00:03:27) [common]
11005 15:38:22.475140 Setting prompt string to ['/ #']
11006 15:38:22.475199 Forcing a shell prompt, looking for ['/ #']
11008 15:38:22.525406 / #
11009 15:38:22.525500 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11010 15:38:22.525575 Waiting using forced prompt support (timeout 00:02:30)
11011 15:38:22.525691 <4>[ 19.767521] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11012 15:38:22.531107
11013 15:38:22.531373 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11014 15:38:22.531465 start: 2.2.7 export-device-env (timeout 00:03:27) [common]
11015 15:38:22.531555 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11016 15:38:22.531691 end: 2.2 depthcharge-retry (duration 00:01:33) [common]
11017 15:38:22.531776 end: 2 depthcharge-action (duration 00:01:33) [common]
11018 15:38:22.531861 start: 3 lava-test-retry (timeout 00:05:00) [common]
11019 15:38:22.531946 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11020 15:38:22.532017 Using namespace: common
11022 15:38:22.632342 / # #
11023 15:38:22.632467 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11024 15:38:22.632622 <6>[ 19.845101] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11025 15:38:22.632691 <6>[ 19.853173] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11026 15:38:22.632754 #<4>[ 19.887289] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11027 15:38:22.637134
11028 15:38:22.637399 Using /lava-11331361
11030 15:38:22.737737 / # export SHELL=/bin/sh
11031 15:38:22.737893 export SHELL=/bin/sh<3>[ 20.004758] mt7921e 0000:01:00.0: hardware init failed
11032 15:38:22.742701
11034 15:38:22.843215 / # . /lava-11331361/environment
11035 15:38:22.848540 . /lava-11331361/environment
11037 15:38:22.949067 / # /lava-11331361/bin/lava-test-runner /lava-11331361/0
11038 15:38:22.949183 Test shell timeout: 10s (minimum of the action and connection timeout)
11039 15:38:22.954476 /lava-11331361/bin/lava-test-runner /lava-11331361/0
11040 15:38:22.975756 + export TESTRUN_ID=0_cros-ec
11041 15:38:22.982892 + c<8>[ 20.261901] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11331361_1.5.2.3.1>
11042 15:38:22.983149 Received signal: <STARTRUN> 0_cros-ec 11331361_1.5.2.3.1
11043 15:38:22.983228 Starting test lava.0_cros-ec (11331361_1.5.2.3.1)
11044 15:38:22.983310 Skipping test definition patterns.
11045 15:38:22.985862 d /lava-11331361/0/tests/0_cros-ec
11046 15:38:22.985942 + cat uuid
11047 15:38:22.989490 + UUID=11331361_1.5.2.3.1
11048 15:38:22.989571 + set +x
11049 15:38:22.995867 + python3 -m cros.runners.lava_runner -v
11050 15:38:23.394742 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11051 15:38:23.401503 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11052 15:38:23.404562
11053 15:38:23.408441 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11055 15:38:23.411243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11056 15:38:23.417783 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11057 15:38:23.424951 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11058 15:38:23.425033
11059 15:38:23.432048 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8
11060 15:38:23.432143 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_accel_iio_data_is_<8', 'result': 'unknown'}
11061 15:38:23.438332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8>[ 20.716846] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11331361_1.5.2.3.1>
11062 15:38:23.438415 valid RESULT=skip>
11063 15:38:23.438649 Received signal: <ENDRUN> 0_cros-ec 11331361_1.5.2.3.1
11064 15:38:23.438725 Ending use of test pattern.
11065 15:38:23.438785 Ending test lava.0_cros-ec (11331361_1.5.2.3.1), duration 0.46
11067 15:38:23.444755 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11068 15:38:23.451235 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11069 15:38:23.451317
11070 15:38:23.457611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11071 15:38:23.457862 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11073 15:38:23.464370 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11074 15:38:23.470793 Checks the standard ABI for the main Embedded Controller. ... ok
11075 15:38:23.470879
11076 15:38:23.474307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11077 15:38:23.474551 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11079 15:38:23.480964 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11080 15:38:23.487768 Checks the main Embedded controller character device. ... ok
11081 15:38:23.487849
11082 15:38:23.490633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11083 15:38:23.490873 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11085 15:38:23.497198 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11086 15:38:23.504093 Checks basic comunication with the main Embedded controller. ... ok
11087 15:38:23.504175
11088 15:38:23.510937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11089 15:38:23.511184 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11091 15:38:23.513961 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11092 15:38:23.520588 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11093 15:38:23.523956
11094 15:38:23.526988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11095 15:38:23.527224 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11097 15:38:23.533410 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11098 15:38:23.540415 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11099 15:38:23.540494
11100 15:38:23.547015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11101 15:38:23.547261 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11103 15:38:23.553658 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11104 15:38:23.560503 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11105 15:38:23.560579
11106 15:38:23.566447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11107 15:38:23.566692 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11109 15:38:23.569941 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11110 15:38:23.579703 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11111 15:38:23.579786
11112 15:38:23.583196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11113 15:38:23.583437 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11115 15:38:23.589591 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11116 15:38:23.600025 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11117 15:38:23.600103
11118 15:38:23.602853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11119 15:38:23.603122 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11121 15:38:23.609816 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11122 15:38:23.616035 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11123 15:38:23.616111
11124 15:38:23.622581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11125 15:38:23.622825 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11127 15:38:23.626090 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11128 15:38:23.636151 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11129 15:38:23.636229
11130 15:38:23.642423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11131 15:38:23.642663 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11133 15:38:23.646098 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11134 15:38:23.655868 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11135 15:38:23.655943
11136 15:38:23.662413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11137 15:38:23.662652 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11139 15:38:23.669135 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11140 15:38:23.675867 Check the cros battery ABI. ... skipped 'No BAT found'
11141 15:38:23.675942
11142 15:38:23.682381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11143 15:38:23.682621 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11145 15:38:23.689047 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11146 15:38:23.695352 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11147 15:38:23.695422
11148 15:38:23.702530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11149 15:38:23.702773 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11151 15:38:23.705976 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11152 15:38:23.712428 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11153 15:38:23.712502
11154 15:38:23.718709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11155 15:38:23.718950 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11157 15:38:23.725332 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11158 15:38:23.732349 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11159 15:38:23.732423
11160 15:38:23.739052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11161 15:38:23.739128
11162 15:38:23.739367 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11164 15:38:23.745665 ----------------------------------------------------------------------
11165 15:38:23.749020 Ran 18 tests in 0.006s
11166 15:38:23.749108
11167 15:38:23.749170 OK (skipped=15)
11168 15:38:23.749229 + set +x
11169 15:38:23.751987 <LAVA_TEST_RUNNER EXIT>
11170 15:38:23.752240 ok: lava_test_shell seems to have completed
11171 15:38:23.752403 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11172 15:38:23.752501 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11173 15:38:23.752582 end: 3 lava-test-retry (duration 00:00:01) [common]
11174 15:38:23.752669 start: 4 finalize (timeout 00:08:02) [common]
11175 15:38:23.752755 start: 4.1 power-off (timeout 00:00:30) [common]
11176 15:38:23.752902 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11177 15:38:23.829522 >> Command sent successfully.
11178 15:38:23.831961 Returned 0 in 0 seconds
11179 15:38:23.932333 end: 4.1 power-off (duration 00:00:00) [common]
11181 15:38:23.932655 start: 4.2 read-feedback (timeout 00:08:02) [common]
11182 15:38:23.932920 Listened to connection for namespace 'common' for up to 1s
11183 15:38:24.933873 Finalising connection for namespace 'common'
11184 15:38:24.934049 Disconnecting from shell: Finalise
11185 15:38:24.934129 / #
11186 15:38:25.034463 end: 4.2 read-feedback (duration 00:00:01) [common]
11187 15:38:25.034641 end: 4 finalize (duration 00:00:01) [common]
11188 15:38:25.034759 Cleaning after the job
11189 15:38:25.034859 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/ramdisk
11190 15:38:25.041613 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/kernel
11191 15:38:25.050163 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/dtb
11192 15:38:25.050342 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331361/tftp-deploy-7nu3mvel/modules
11193 15:38:25.057709 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11331361
11194 15:38:25.177751 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11331361
11195 15:38:25.177926 Job finished correctly