Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 25
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 132
- Errors: 0
1 15:34:56.488698 lava-dispatcher, installed at version: 2023.06
2 15:34:56.488924 start: 0 validate
3 15:34:56.489068 Start time: 2023-08-22 15:34:56.489056+00:00 (UTC)
4 15:34:56.489208 Using caching service: 'http://localhost/cache/?uri=%s'
5 15:34:56.489359 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 15:34:56.752562 Using caching service: 'http://localhost/cache/?uri=%s'
7 15:34:56.752772 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 15:34:57.019403 Using caching service: 'http://localhost/cache/?uri=%s'
9 15:34:57.020135 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 15:35:32.818860 Using caching service: 'http://localhost/cache/?uri=%s'
11 15:35:32.819031 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 15:35:33.348907 validate duration: 36.86
14 15:35:33.349165 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 15:35:33.349265 start: 1.1 download-retry (timeout 00:10:00) [common]
16 15:35:33.349355 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 15:35:33.349488 Not decompressing ramdisk as can be used compressed.
18 15:35:33.349579 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 15:35:33.349644 saving as /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/ramdisk/rootfs.cpio.gz
20 15:35:33.349710 total size: 84918747 (80 MB)
21 15:35:37.822516 progress 0 % (0 MB)
22 15:35:37.884257 progress 5 % (4 MB)
23 15:35:37.907214 progress 10 % (8 MB)
24 15:35:37.929160 progress 15 % (12 MB)
25 15:35:37.951428 progress 20 % (16 MB)
26 15:35:37.973679 progress 25 % (20 MB)
27 15:35:37.995679 progress 30 % (24 MB)
28 15:35:38.017461 progress 35 % (28 MB)
29 15:35:38.039395 progress 40 % (32 MB)
30 15:35:38.061466 progress 45 % (36 MB)
31 15:35:38.083158 progress 50 % (40 MB)
32 15:35:38.105879 progress 55 % (44 MB)
33 15:35:38.128216 progress 60 % (48 MB)
34 15:35:38.150855 progress 65 % (52 MB)
35 15:35:38.172718 progress 70 % (56 MB)
36 15:35:38.194341 progress 75 % (60 MB)
37 15:35:38.216214 progress 80 % (64 MB)
38 15:35:38.238231 progress 85 % (68 MB)
39 15:35:38.261127 progress 90 % (72 MB)
40 15:35:38.283040 progress 95 % (76 MB)
41 15:35:38.304610 progress 100 % (80 MB)
42 15:35:38.304890 80 MB downloaded in 4.96 s (16.34 MB/s)
43 15:35:38.305062 end: 1.1.1 http-download (duration 00:00:05) [common]
45 15:35:38.305306 end: 1.1 download-retry (duration 00:00:05) [common]
46 15:35:38.305397 start: 1.2 download-retry (timeout 00:09:55) [common]
47 15:35:38.305481 start: 1.2.1 http-download (timeout 00:09:55) [common]
48 15:35:38.305628 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 15:35:38.305699 saving as /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/kernel/Image
50 15:35:38.305761 total size: 49220096 (46 MB)
51 15:35:38.305823 No compression specified
52 15:35:38.306958 progress 0 % (0 MB)
53 15:35:38.319809 progress 5 % (2 MB)
54 15:35:38.332623 progress 10 % (4 MB)
55 15:35:38.346025 progress 15 % (7 MB)
56 15:35:38.359036 progress 20 % (9 MB)
57 15:35:38.371792 progress 25 % (11 MB)
58 15:35:38.384802 progress 30 % (14 MB)
59 15:35:38.397594 progress 35 % (16 MB)
60 15:35:38.410438 progress 40 % (18 MB)
61 15:35:38.423201 progress 45 % (21 MB)
62 15:35:38.436425 progress 50 % (23 MB)
63 15:35:38.449603 progress 55 % (25 MB)
64 15:35:38.462477 progress 60 % (28 MB)
65 15:35:38.475514 progress 65 % (30 MB)
66 15:35:38.488482 progress 70 % (32 MB)
67 15:35:38.501303 progress 75 % (35 MB)
68 15:35:38.514137 progress 80 % (37 MB)
69 15:35:38.526915 progress 85 % (39 MB)
70 15:35:38.539825 progress 90 % (42 MB)
71 15:35:38.552763 progress 95 % (44 MB)
72 15:35:38.565838 progress 100 % (46 MB)
73 15:35:38.566020 46 MB downloaded in 0.26 s (180.36 MB/s)
74 15:35:38.566203 end: 1.2.1 http-download (duration 00:00:00) [common]
76 15:35:38.566469 end: 1.2 download-retry (duration 00:00:00) [common]
77 15:35:38.566574 start: 1.3 download-retry (timeout 00:09:55) [common]
78 15:35:38.566681 start: 1.3.1 http-download (timeout 00:09:55) [common]
79 15:35:38.566944 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 15:35:38.567043 saving as /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/dtb/mt8192-asurada-spherion-r0.dtb
81 15:35:38.567135 total size: 47278 (0 MB)
82 15:35:38.567227 No compression specified
83 15:35:38.568920 progress 69 % (0 MB)
84 15:35:38.569227 progress 100 % (0 MB)
85 15:35:38.569412 0 MB downloaded in 0.00 s (19.83 MB/s)
86 15:35:38.569581 end: 1.3.1 http-download (duration 00:00:00) [common]
88 15:35:38.569937 end: 1.3 download-retry (duration 00:00:00) [common]
89 15:35:38.570052 start: 1.4 download-retry (timeout 00:09:55) [common]
90 15:35:38.570164 start: 1.4.1 http-download (timeout 00:09:55) [common]
91 15:35:38.570311 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 15:35:38.570405 saving as /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/modules/modules.tar
93 15:35:38.570494 total size: 8608784 (8 MB)
94 15:35:38.570584 Using unxz to decompress xz
95 15:35:38.575050 progress 0 % (0 MB)
96 15:35:38.596946 progress 5 % (0 MB)
97 15:35:38.619733 progress 10 % (0 MB)
98 15:35:38.646413 progress 15 % (1 MB)
99 15:35:38.672345 progress 20 % (1 MB)
100 15:35:38.699137 progress 25 % (2 MB)
101 15:35:38.727917 progress 30 % (2 MB)
102 15:35:38.753507 progress 35 % (2 MB)
103 15:35:38.780878 progress 40 % (3 MB)
104 15:35:38.805711 progress 45 % (3 MB)
105 15:35:38.832556 progress 50 % (4 MB)
106 15:35:38.858491 progress 55 % (4 MB)
107 15:35:38.883645 progress 60 % (4 MB)
108 15:35:38.906280 progress 65 % (5 MB)
109 15:35:38.931668 progress 70 % (5 MB)
110 15:35:38.958570 progress 75 % (6 MB)
111 15:35:38.985102 progress 80 % (6 MB)
112 15:35:39.015226 progress 85 % (7 MB)
113 15:35:39.041885 progress 90 % (7 MB)
114 15:35:39.066807 progress 95 % (7 MB)
115 15:35:39.090208 progress 100 % (8 MB)
116 15:35:39.096173 8 MB downloaded in 0.53 s (15.62 MB/s)
117 15:35:39.096436 end: 1.4.1 http-download (duration 00:00:01) [common]
119 15:35:39.096734 end: 1.4 download-retry (duration 00:00:01) [common]
120 15:35:39.096830 start: 1.5 prepare-tftp-overlay (timeout 00:09:54) [common]
121 15:35:39.096925 start: 1.5.1 extract-nfsrootfs (timeout 00:09:54) [common]
122 15:35:39.097008 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 15:35:39.097102 start: 1.5.2 lava-overlay (timeout 00:09:54) [common]
124 15:35:39.097402 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_
125 15:35:39.097573 makedir: /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin
126 15:35:39.097683 makedir: /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/tests
127 15:35:39.097786 makedir: /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/results
128 15:35:39.097904 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-add-keys
129 15:35:39.098058 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-add-sources
130 15:35:39.098200 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-background-process-start
131 15:35:39.098333 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-background-process-stop
132 15:35:39.098462 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-common-functions
133 15:35:39.098590 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-echo-ipv4
134 15:35:39.098719 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-install-packages
135 15:35:39.098847 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-installed-packages
136 15:35:39.098973 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-os-build
137 15:35:39.099100 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-probe-channel
138 15:35:39.099226 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-probe-ip
139 15:35:39.099353 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-target-ip
140 15:35:39.099479 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-target-mac
141 15:35:39.099605 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-target-storage
142 15:35:39.099738 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-test-case
143 15:35:39.099866 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-test-event
144 15:35:39.099992 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-test-feedback
145 15:35:39.100118 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-test-raise
146 15:35:39.100251 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-test-reference
147 15:35:39.100379 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-test-runner
148 15:35:39.100505 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-test-set
149 15:35:39.100635 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-test-shell
150 15:35:39.100807 Updating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-install-packages (oe)
151 15:35:39.100965 Updating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/bin/lava-installed-packages (oe)
152 15:35:39.101098 Creating /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/environment
153 15:35:39.101243 LAVA metadata
154 15:35:39.101351 - LAVA_JOB_ID=11331384
155 15:35:39.101417 - LAVA_DISPATCHER_IP=192.168.201.1
156 15:35:39.101522 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:54) [common]
157 15:35:39.101591 skipped lava-vland-overlay
158 15:35:39.101665 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 15:35:39.101748 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
160 15:35:39.101811 skipped lava-multinode-overlay
161 15:35:39.101887 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 15:35:39.101971 start: 1.5.2.3 test-definition (timeout 00:09:54) [common]
163 15:35:39.102044 Loading test definitions
164 15:35:39.102131 start: 1.5.2.3.1 git-repo-action (timeout 00:09:54) [common]
165 15:35:39.102206 Using /lava-11331384 at stage 0
166 15:35:39.102300 Fetching tests from https://github.com/kernelci/kernelci-core
167 15:35:39.102381 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/0/tests/0_sleep'
168 15:35:39.785102 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/0/tests/0_sleep
169 15:35:39.786454 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 15:35:39.786887 uuid=11331384_1.5.2.3.1 testdef=None
171 15:35:39.787052 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 15:35:39.787341 start: 1.5.2.3.2 test-overlay (timeout 00:09:54) [common]
174 15:35:39.787933 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 15:35:39.788193 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:54) [common]
177 15:35:39.789114 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 15:35:39.789384 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
180 15:35:39.790117 runner path: /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/0/tests/0_sleep test_uuid 11331384_1.5.2.3.1
181 15:35:39.790207 sleep_params='mem freeze'
182 15:35:39.790382 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 15:35:39.790620 Creating lava-test-runner.conf files
185 15:35:39.790706 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11331384/lava-overlay-o97v403_/lava-11331384/0 for stage 0
186 15:35:39.790831 - 0_sleep
187 15:35:39.790985 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 15:35:39.791116 start: 1.5.2.4 compress-overlay (timeout 00:09:54) [common]
189 15:35:39.917724 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 15:35:39.917889 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
191 15:35:39.918011 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 15:35:39.918133 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 15:35:39.918238 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
194 15:35:42.392501 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 15:35:42.392922 start: 1.5.4 extract-modules (timeout 00:09:51) [common]
196 15:35:42.393043 extracting modules file /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11331384/extract-overlay-ramdisk-krz0vm3w/ramdisk
197 15:35:42.624534 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 15:35:42.624720 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
199 15:35:42.624836 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11331384/compress-overlay-h7qr1czi/overlay-1.5.2.4.tar.gz to ramdisk
200 15:35:42.624910 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11331384/compress-overlay-h7qr1czi/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11331384/extract-overlay-ramdisk-krz0vm3w/ramdisk
201 15:35:42.720600 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 15:35:42.720801 start: 1.5.6 configure-preseed-file (timeout 00:09:51) [common]
203 15:35:42.720896 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 15:35:42.720986 start: 1.5.7 compress-ramdisk (timeout 00:09:51) [common]
205 15:35:42.721068 Building ramdisk /var/lib/lava/dispatcher/tmp/11331384/extract-overlay-ramdisk-krz0vm3w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11331384/extract-overlay-ramdisk-krz0vm3w/ramdisk
206 15:35:44.126774 >> 563301 blocks
207 15:35:53.866665 rename /var/lib/lava/dispatcher/tmp/11331384/extract-overlay-ramdisk-krz0vm3w/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/ramdisk/ramdisk.cpio.gz
208 15:35:53.867175 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 15:35:53.867365 start: 1.5.8 prepare-kernel (timeout 00:09:39) [common]
210 15:35:53.867506 start: 1.5.8.1 prepare-fit (timeout 00:09:39) [common]
211 15:35:53.867658 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/kernel/Image'
212 15:36:07.020231 Returned 0 in 13 seconds
213 15:36:07.121124 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/kernel/image.itb
214 15:36:08.432311 output: FIT description: Kernel Image image with one or more FDT blobs
215 15:36:08.432673 output: Created: Tue Aug 22 16:36:08 2023
216 15:36:08.432755 output: Image 0 (kernel-1)
217 15:36:08.432822 output: Description:
218 15:36:08.432887 output: Created: Tue Aug 22 16:36:08 2023
219 15:36:08.432947 output: Type: Kernel Image
220 15:36:08.433011 output: Compression: lzma compressed
221 15:36:08.433071 output: Data Size: 11035343 Bytes = 10776.70 KiB = 10.52 MiB
222 15:36:08.433131 output: Architecture: AArch64
223 15:36:08.433190 output: OS: Linux
224 15:36:08.433248 output: Load Address: 0x00000000
225 15:36:08.433303 output: Entry Point: 0x00000000
226 15:36:08.433357 output: Hash algo: crc32
227 15:36:08.433411 output: Hash value: fe81bcf6
228 15:36:08.433464 output: Image 1 (fdt-1)
229 15:36:08.433517 output: Description: mt8192-asurada-spherion-r0
230 15:36:08.433571 output: Created: Tue Aug 22 16:36:08 2023
231 15:36:08.433624 output: Type: Flat Device Tree
232 15:36:08.433677 output: Compression: uncompressed
233 15:36:08.433730 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 15:36:08.433783 output: Architecture: AArch64
235 15:36:08.433836 output: Hash algo: crc32
236 15:36:08.433889 output: Hash value: cc4352de
237 15:36:08.433941 output: Image 2 (ramdisk-1)
238 15:36:08.433994 output: Description: unavailable
239 15:36:08.434047 output: Created: Tue Aug 22 16:36:08 2023
240 15:36:08.434100 output: Type: RAMDisk Image
241 15:36:08.434157 output: Compression: Unknown Compression
242 15:36:08.434236 output: Data Size: 98314785 Bytes = 96010.53 KiB = 93.76 MiB
243 15:36:08.434313 output: Architecture: AArch64
244 15:36:08.434388 output: OS: Linux
245 15:36:08.434464 output: Load Address: unavailable
246 15:36:08.434539 output: Entry Point: unavailable
247 15:36:08.434614 output: Hash algo: crc32
248 15:36:08.434706 output: Hash value: 19b1dc92
249 15:36:08.434799 output: Default Configuration: 'conf-1'
250 15:36:08.434891 output: Configuration 0 (conf-1)
251 15:36:08.434984 output: Description: mt8192-asurada-spherion-r0
252 15:36:08.435076 output: Kernel: kernel-1
253 15:36:08.435169 output: Init Ramdisk: ramdisk-1
254 15:36:08.435261 output: FDT: fdt-1
255 15:36:08.435353 output: Loadables: kernel-1
256 15:36:08.435445 output:
257 15:36:08.435694 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 15:36:08.435832 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 15:36:08.435982 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
260 15:36:08.436124 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:25) [common]
261 15:36:08.436242 No LXC device requested
262 15:36:08.436366 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 15:36:08.436499 start: 1.7 deploy-device-env (timeout 00:09:25) [common]
264 15:36:08.436616 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 15:36:08.436731 Checking files for TFTP limit of 4294967296 bytes.
266 15:36:08.437264 end: 1 tftp-deploy (duration 00:00:35) [common]
267 15:36:08.437383 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 15:36:08.437490 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 15:36:08.437630 substitutions:
270 15:36:08.437707 - {DTB}: 11331384/tftp-deploy-8yx1oycu/dtb/mt8192-asurada-spherion-r0.dtb
271 15:36:08.437793 - {INITRD}: 11331384/tftp-deploy-8yx1oycu/ramdisk/ramdisk.cpio.gz
272 15:36:08.437892 - {KERNEL}: 11331384/tftp-deploy-8yx1oycu/kernel/Image
273 15:36:08.437990 - {LAVA_MAC}: None
274 15:36:08.438087 - {PRESEED_CONFIG}: None
275 15:36:08.438185 - {PRESEED_LOCAL}: None
276 15:36:08.438281 - {RAMDISK}: 11331384/tftp-deploy-8yx1oycu/ramdisk/ramdisk.cpio.gz
277 15:36:08.438377 - {ROOT_PART}: None
278 15:36:08.438471 - {ROOT}: None
279 15:36:08.438567 - {SERVER_IP}: 192.168.201.1
280 15:36:08.438661 - {TEE}: None
281 15:36:08.438756 Parsed boot commands:
282 15:36:08.438849 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 15:36:08.439087 Parsed boot commands: tftpboot 192.168.201.1 11331384/tftp-deploy-8yx1oycu/kernel/image.itb 11331384/tftp-deploy-8yx1oycu/kernel/cmdline
284 15:36:08.439221 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 15:36:08.439348 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 15:36:08.439487 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 15:36:08.439618 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 15:36:08.439728 Not connected, no need to disconnect.
289 15:36:08.439845 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 15:36:08.439970 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 15:36:08.440074 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
292 15:36:08.444151 Setting prompt string to ['lava-test: # ']
293 15:36:08.444548 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 15:36:08.444706 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 15:36:08.444824 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 15:36:08.444935 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 15:36:08.445149 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
298 15:36:13.577957 >> Command sent successfully.
299 15:36:13.581074 Returned 0 in 5 seconds
300 15:36:13.681498 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 15:36:13.681941 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 15:36:13.682072 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 15:36:13.682199 Setting prompt string to 'Starting depthcharge on Spherion...'
305 15:36:13.682300 Changing prompt to 'Starting depthcharge on Spherion...'
306 15:36:13.682403 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 15:36:13.682772 [Enter `^Ec?' for help]
308 15:36:13.856536
309 15:36:13.856732
310 15:36:13.856821 F0: 102B 0000
311 15:36:13.856894
312 15:36:13.856957 F3: 1001 0000 [0200]
313 15:36:13.857019
314 15:36:13.860331 F3: 1001 0000
315 15:36:13.860443
316 15:36:13.860543 F7: 102D 0000
317 15:36:13.860636
318 15:36:13.860740 F1: 0000 0000
319 15:36:13.860830
320 15:36:13.864198 V0: 0000 0000 [0001]
321 15:36:13.864290
322 15:36:13.864357 00: 0007 8000
323 15:36:13.864439
324 15:36:13.867649 01: 0000 0000
325 15:36:13.867737
326 15:36:13.867804 BP: 0C00 0209 [0000]
327 15:36:13.867867
328 15:36:13.867927 G0: 1182 0000
329 15:36:13.871168
330 15:36:13.871253 EC: 0000 0021 [4000]
331 15:36:13.871321
332 15:36:13.874810 S7: 0000 0000 [0000]
333 15:36:13.874896
334 15:36:13.874963 CC: 0000 0000 [0001]
335 15:36:13.875026
336 15:36:13.878159 T0: 0000 0040 [010F]
337 15:36:13.878246
338 15:36:13.878313 Jump to BL
339 15:36:13.878377
340 15:36:13.903057
341 15:36:13.903192
342 15:36:13.903262
343 15:36:13.910193 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 15:36:13.913358 ARM64: Exception handlers installed.
345 15:36:13.916876 ARM64: Testing exception
346 15:36:13.920565 ARM64: Done test exception
347 15:36:13.928068 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 15:36:13.939041 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 15:36:13.945461 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 15:36:13.955932 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 15:36:13.962698 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 15:36:13.969432 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 15:36:13.979739 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 15:36:13.986535 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 15:36:14.006252 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 15:36:14.008964 WDT: Last reset was cold boot
357 15:36:14.012503 SPI1(PAD0) initialized at 2873684 Hz
358 15:36:14.015772 SPI5(PAD0) initialized at 992727 Hz
359 15:36:14.019248 VBOOT: Loading verstage.
360 15:36:14.025766 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 15:36:14.029378 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 15:36:14.032489 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 15:36:14.035926 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 15:36:14.043541 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 15:36:14.049898 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 15:36:14.061001 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
367 15:36:14.061100
368 15:36:14.061174
369 15:36:14.070817 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 15:36:14.074544 ARM64: Exception handlers installed.
371 15:36:14.077656 ARM64: Testing exception
372 15:36:14.077738 ARM64: Done test exception
373 15:36:14.083905 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 15:36:14.087848 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 15:36:14.103075 Probing TPM: . done!
376 15:36:14.103205 TPM ready after 0 ms
377 15:36:14.107481 Connected to device vid:did:rid of 1ae0:0028:00
378 15:36:14.118438 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 15:36:14.174077 Initialized TPM device CR50 revision 0
380 15:36:14.185557 tlcl_send_startup: Startup return code is 0
381 15:36:14.185678 TPM: setup succeeded
382 15:36:14.196983 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 15:36:14.205573 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 15:36:14.215671 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 15:36:14.225277 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 15:36:14.228554 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 15:36:14.240283 in-header: 03 07 00 00 08 00 00 00
388 15:36:14.244238 in-data: aa e4 47 04 13 02 00 00
389 15:36:14.247622 Chrome EC: UHEPI supported
390 15:36:14.255380 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 15:36:14.258633 in-header: 03 ad 00 00 08 00 00 00
392 15:36:14.258723 in-data: 00 20 20 08 00 00 00 00
393 15:36:14.262261 Phase 1
394 15:36:14.265861 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 15:36:14.269861 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 15:36:14.277395 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 15:36:14.281570 Recovery requested (1009000e)
398 15:36:14.290651 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 15:36:14.294559 tlcl_extend: response is 0
400 15:36:14.303106 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 15:36:14.308542 tlcl_extend: response is 0
402 15:36:14.315435 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 15:36:14.335855 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
404 15:36:14.342528 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 15:36:14.342653
406 15:36:14.342738
407 15:36:14.353577 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 15:36:14.356781 ARM64: Exception handlers installed.
409 15:36:14.356875 ARM64: Testing exception
410 15:36:14.360091 ARM64: Done test exception
411 15:36:14.380997 pmic_efuse_setting: Set efuses in 11 msecs
412 15:36:14.384889 pmwrap_interface_init: Select PMIF_VLD_RDY
413 15:36:14.391384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 15:36:14.394927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 15:36:14.398626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 15:36:14.405617 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 15:36:14.409807 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 15:36:14.413468 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 15:36:14.420337 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 15:36:14.424111 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 15:36:14.428861 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 15:36:14.432036 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 15:36:14.439591 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 15:36:14.443344 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 15:36:14.446991 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 15:36:14.454626 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 15:36:14.458672 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 15:36:14.465730 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 15:36:14.469713 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 15:36:14.476593 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 15:36:14.480554 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 15:36:14.487936 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 15:36:14.491997 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 15:36:14.499218 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 15:36:14.503262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 15:36:14.510116 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 15:36:14.514414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 15:36:14.521446 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 15:36:14.525178 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 15:36:14.529185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 15:36:14.535968 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 15:36:14.539606 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 15:36:14.546866 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 15:36:14.550747 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 15:36:14.554269 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 15:36:14.561689 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 15:36:14.565049 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 15:36:14.568955 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 15:36:14.576707 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 15:36:14.580302 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 15:36:14.584240 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 15:36:14.588025 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 15:36:14.595171 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 15:36:14.599499 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 15:36:14.602560 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 15:36:14.606650 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 15:36:14.610059 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 15:36:14.614065 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 15:36:14.621723 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 15:36:14.625222 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 15:36:14.628378 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 15:36:14.632764 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 15:36:14.636481 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 15:36:14.643365 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 15:36:14.650939 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 15:36:14.658136 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 15:36:14.665617 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 15:36:14.672677 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 15:36:14.680123 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 15:36:14.683724 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 15:36:14.687604 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 15:36:14.694437 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2a
473 15:36:14.698136 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 15:36:14.706343 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
475 15:36:14.709446 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 15:36:14.718850 [RTC]rtc_get_frequency_meter,154: input=15, output=790
477 15:36:14.728512 [RTC]rtc_get_frequency_meter,154: input=23, output=978
478 15:36:14.737742 [RTC]rtc_get_frequency_meter,154: input=19, output=885
479 15:36:14.747786 [RTC]rtc_get_frequency_meter,154: input=17, output=837
480 15:36:14.756895 [RTC]rtc_get_frequency_meter,154: input=16, output=814
481 15:36:14.766588 [RTC]rtc_get_frequency_meter,154: input=15, output=790
482 15:36:14.775439 [RTC]rtc_get_frequency_meter,154: input=16, output=813
483 15:36:14.778902 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
484 15:36:14.786799 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
485 15:36:14.790726 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 15:36:14.794401 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 15:36:14.797982 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 15:36:14.802080 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 15:36:14.805397 ADC[4]: Raw value=900959 ID=7
490 15:36:14.809240 ADC[3]: Raw value=213336 ID=1
491 15:36:14.809332 RAM Code: 0x71
492 15:36:14.813105 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 15:36:14.820460 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 15:36:14.827780 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 15:36:14.835390 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 15:36:14.835502 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 15:36:14.840515 in-header: 03 07 00 00 08 00 00 00
498 15:36:14.845049 in-data: aa e4 47 04 13 02 00 00
499 15:36:14.848333 Chrome EC: UHEPI supported
500 15:36:14.856338 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 15:36:14.856437 in-header: 03 ed 00 00 08 00 00 00
502 15:36:14.859457 in-data: 80 20 60 08 00 00 00 00
503 15:36:14.863494 MRC: failed to locate region type 0.
504 15:36:14.871424 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 15:36:14.875027 DRAM-K: Running full calibration
506 15:36:14.878366 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 15:36:14.882669 header.status = 0x0
508 15:36:14.886171 header.version = 0x6 (expected: 0x6)
509 15:36:14.889596 header.size = 0xd00 (expected: 0xd00)
510 15:36:14.889698 header.flags = 0x0
511 15:36:14.897122 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 15:36:14.914240 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
513 15:36:14.922778 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 15:36:14.922904 dram_init: ddr_geometry: 2
515 15:36:14.925348 [EMI] MDL number = 2
516 15:36:14.929172 [EMI] Get MDL freq = 0
517 15:36:14.929260 dram_init: ddr_type: 0
518 15:36:14.933069 is_discrete_lpddr4: 1
519 15:36:14.936507 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 15:36:14.936593
521 15:36:14.936711
522 15:36:14.936797 [Bian_co] ETT version 0.0.0.1
523 15:36:14.943964 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 15:36:14.944080
525 15:36:14.947525 dramc_set_vcore_voltage set vcore to 650000
526 15:36:14.947617 Read voltage for 800, 4
527 15:36:14.950845 Vio18 = 0
528 15:36:14.950931 Vcore = 650000
529 15:36:14.951024 Vdram = 0
530 15:36:14.954116 Vddq = 0
531 15:36:14.954205 Vmddr = 0
532 15:36:14.957784 dram_init: config_dvfs: 1
533 15:36:14.961369 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 15:36:14.967736 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 15:36:14.971104 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
536 15:36:14.974317 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
537 15:36:14.977885 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
538 15:36:14.981373 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
539 15:36:14.984538 MEM_TYPE=3, freq_sel=18
540 15:36:14.988443 sv_algorithm_assistance_LP4_1600
541 15:36:14.992208 ============ PULL DRAM RESETB DOWN ============
542 15:36:14.994984 ========== PULL DRAM RESETB DOWN end =========
543 15:36:15.001648 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 15:36:15.005123 ===================================
545 15:36:15.005204 LPDDR4 DRAM CONFIGURATION
546 15:36:15.008200 ===================================
547 15:36:15.011437 EX_ROW_EN[0] = 0x0
548 15:36:15.011516 EX_ROW_EN[1] = 0x0
549 15:36:15.015248 LP4Y_EN = 0x0
550 15:36:15.015330 WORK_FSP = 0x0
551 15:36:15.018812 WL = 0x2
552 15:36:15.018893 RL = 0x2
553 15:36:15.021855 BL = 0x2
554 15:36:15.021947 RPST = 0x0
555 15:36:15.025312 RD_PRE = 0x0
556 15:36:15.025392 WR_PRE = 0x1
557 15:36:15.028209 WR_PST = 0x0
558 15:36:15.031665 DBI_WR = 0x0
559 15:36:15.031746 DBI_RD = 0x0
560 15:36:15.035269 OTF = 0x1
561 15:36:15.035352 ===================================
562 15:36:15.038692 ===================================
563 15:36:15.041747 ANA top config
564 15:36:15.045284 ===================================
565 15:36:15.048325 DLL_ASYNC_EN = 0
566 15:36:15.048404 ALL_SLAVE_EN = 1
567 15:36:15.051663 NEW_RANK_MODE = 1
568 15:36:15.054915 DLL_IDLE_MODE = 1
569 15:36:15.058651 LP45_APHY_COMB_EN = 1
570 15:36:15.058729 TX_ODT_DIS = 1
571 15:36:15.061623 NEW_8X_MODE = 1
572 15:36:15.065087 ===================================
573 15:36:15.068352 ===================================
574 15:36:15.072385 data_rate = 1600
575 15:36:15.075758 CKR = 1
576 15:36:15.078831 DQ_P2S_RATIO = 8
577 15:36:15.082295 ===================================
578 15:36:15.085259 CA_P2S_RATIO = 8
579 15:36:15.085340 DQ_CA_OPEN = 0
580 15:36:15.088484 DQ_SEMI_OPEN = 0
581 15:36:15.092357 CA_SEMI_OPEN = 0
582 15:36:15.095344 CA_FULL_RATE = 0
583 15:36:15.099168 DQ_CKDIV4_EN = 1
584 15:36:15.099309 CA_CKDIV4_EN = 1
585 15:36:15.102121 CA_PREDIV_EN = 0
586 15:36:15.105794 PH8_DLY = 0
587 15:36:15.108984 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 15:36:15.111968 DQ_AAMCK_DIV = 4
589 15:36:15.115883 CA_AAMCK_DIV = 4
590 15:36:15.115990 CA_ADMCK_DIV = 4
591 15:36:15.118775 DQ_TRACK_CA_EN = 0
592 15:36:15.122080 CA_PICK = 800
593 15:36:15.125825 CA_MCKIO = 800
594 15:36:15.129204 MCKIO_SEMI = 0
595 15:36:15.133001 PLL_FREQ = 3068
596 15:36:15.133085 DQ_UI_PI_RATIO = 32
597 15:36:15.136447 CA_UI_PI_RATIO = 0
598 15:36:15.140129 ===================================
599 15:36:15.144041 ===================================
600 15:36:15.147996 memory_type:LPDDR4
601 15:36:15.148081 GP_NUM : 10
602 15:36:15.151155 SRAM_EN : 1
603 15:36:15.151246 MD32_EN : 0
604 15:36:15.154989 ===================================
605 15:36:15.158964 [ANA_INIT] >>>>>>>>>>>>>>
606 15:36:15.162318 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 15:36:15.162463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 15:36:15.166618 ===================================
609 15:36:15.169512 data_rate = 1600,PCW = 0X7600
610 15:36:15.173378 ===================================
611 15:36:15.176464 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 15:36:15.182834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 15:36:15.186485 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 15:36:15.193104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 15:36:15.196408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 15:36:15.199732 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 15:36:15.199816 [ANA_INIT] flow start
618 15:36:15.203176 [ANA_INIT] PLL >>>>>>>>
619 15:36:15.206713 [ANA_INIT] PLL <<<<<<<<
620 15:36:15.206796 [ANA_INIT] MIDPI >>>>>>>>
621 15:36:15.209950 [ANA_INIT] MIDPI <<<<<<<<
622 15:36:15.213581 [ANA_INIT] DLL >>>>>>>>
623 15:36:15.213658 [ANA_INIT] flow end
624 15:36:15.220149 ============ LP4 DIFF to SE enter ============
625 15:36:15.223447 ============ LP4 DIFF to SE exit ============
626 15:36:15.226913 [ANA_INIT] <<<<<<<<<<<<<
627 15:36:15.230211 [Flow] Enable top DCM control >>>>>
628 15:36:15.230292 [Flow] Enable top DCM control <<<<<
629 15:36:15.233814 Enable DLL master slave shuffle
630 15:36:15.241128 ==============================================================
631 15:36:15.243631 Gating Mode config
632 15:36:15.247342 ==============================================================
633 15:36:15.250215 Config description:
634 15:36:15.260991 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 15:36:15.267706 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 15:36:15.270776 SELPH_MODE 0: By rank 1: By Phase
637 15:36:15.277721 ==============================================================
638 15:36:15.281176 GAT_TRACK_EN = 1
639 15:36:15.281299 RX_GATING_MODE = 2
640 15:36:15.284045 RX_GATING_TRACK_MODE = 2
641 15:36:15.287357 SELPH_MODE = 1
642 15:36:15.290981 PICG_EARLY_EN = 1
643 15:36:15.294139 VALID_LAT_VALUE = 1
644 15:36:15.301087 ==============================================================
645 15:36:15.304277 Enter into Gating configuration >>>>
646 15:36:15.307674 Exit from Gating configuration <<<<
647 15:36:15.311033 Enter into DVFS_PRE_config >>>>>
648 15:36:15.321213 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 15:36:15.324148 Exit from DVFS_PRE_config <<<<<
650 15:36:15.327922 Enter into PICG configuration >>>>
651 15:36:15.331515 Exit from PICG configuration <<<<
652 15:36:15.334596 [RX_INPUT] configuration >>>>>
653 15:36:15.334715 [RX_INPUT] configuration <<<<<
654 15:36:15.341156 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 15:36:15.347887 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 15:36:15.351563 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 15:36:15.358064 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 15:36:15.365148 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 15:36:15.372002 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 15:36:15.375174 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 15:36:15.378350 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 15:36:15.381594 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 15:36:15.388601 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 15:36:15.391926 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 15:36:15.395024 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 15:36:15.398483 ===================================
667 15:36:15.401737 LPDDR4 DRAM CONFIGURATION
668 15:36:15.405070 ===================================
669 15:36:15.405148 EX_ROW_EN[0] = 0x0
670 15:36:15.408612 EX_ROW_EN[1] = 0x0
671 15:36:15.408733 LP4Y_EN = 0x0
672 15:36:15.412354 WORK_FSP = 0x0
673 15:36:15.415800 WL = 0x2
674 15:36:15.415909 RL = 0x2
675 15:36:15.418715 BL = 0x2
676 15:36:15.418793 RPST = 0x0
677 15:36:15.422063 RD_PRE = 0x0
678 15:36:15.422171 WR_PRE = 0x1
679 15:36:15.425605 WR_PST = 0x0
680 15:36:15.425683 DBI_WR = 0x0
681 15:36:15.429023 DBI_RD = 0x0
682 15:36:15.429102 OTF = 0x1
683 15:36:15.432201 ===================================
684 15:36:15.435699 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 15:36:15.439546 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 15:36:15.445586 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 15:36:15.449204 ===================================
688 15:36:15.452571 LPDDR4 DRAM CONFIGURATION
689 15:36:15.452683 ===================================
690 15:36:15.455972 EX_ROW_EN[0] = 0x10
691 15:36:15.459486 EX_ROW_EN[1] = 0x0
692 15:36:15.459587 LP4Y_EN = 0x0
693 15:36:15.462810 WORK_FSP = 0x0
694 15:36:15.462888 WL = 0x2
695 15:36:15.466083 RL = 0x2
696 15:36:15.466161 BL = 0x2
697 15:36:15.469628 RPST = 0x0
698 15:36:15.469704 RD_PRE = 0x0
699 15:36:15.473163 WR_PRE = 0x1
700 15:36:15.473269 WR_PST = 0x0
701 15:36:15.476453 DBI_WR = 0x0
702 15:36:15.476552 DBI_RD = 0x0
703 15:36:15.479967 OTF = 0x1
704 15:36:15.483341 ===================================
705 15:36:15.489862 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 15:36:15.493250 nWR fixed to 40
707 15:36:15.493329 [ModeRegInit_LP4] CH0 RK0
708 15:36:15.496886 [ModeRegInit_LP4] CH0 RK1
709 15:36:15.499735 [ModeRegInit_LP4] CH1 RK0
710 15:36:15.499814 [ModeRegInit_LP4] CH1 RK1
711 15:36:15.503456 match AC timing 13
712 15:36:15.506279 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 15:36:15.510073 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 15:36:15.516682 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 15:36:15.520032 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 15:36:15.526376 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 15:36:15.526460 [EMI DOE] emi_dcm 0
718 15:36:15.529956 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 15:36:15.533353 ==
720 15:36:15.533437 Dram Type= 6, Freq= 0, CH_0, rank 0
721 15:36:15.540544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 15:36:15.540629 ==
723 15:36:15.543727 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 15:36:15.550257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 15:36:15.559798 [CA 0] Center 37 (7~68) winsize 62
726 15:36:15.563166 [CA 1] Center 37 (6~68) winsize 63
727 15:36:15.566318 [CA 2] Center 35 (5~65) winsize 61
728 15:36:15.569900 [CA 3] Center 34 (4~65) winsize 62
729 15:36:15.573126 [CA 4] Center 34 (3~65) winsize 63
730 15:36:15.576452 [CA 5] Center 33 (3~64) winsize 62
731 15:36:15.576565
732 15:36:15.580065 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 15:36:15.580174
734 15:36:15.583205 [CATrainingPosCal] consider 1 rank data
735 15:36:15.587022 u2DelayCellTimex100 = 270/100 ps
736 15:36:15.590166 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 15:36:15.593187 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
738 15:36:15.596794 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
739 15:36:15.603527 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
740 15:36:15.606843 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
741 15:36:15.609995 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 15:36:15.610078
743 15:36:15.613459 CA PerBit enable=1, Macro0, CA PI delay=33
744 15:36:15.613542
745 15:36:15.617052 [CBTSetCACLKResult] CA Dly = 33
746 15:36:15.617135 CS Dly: 4 (0~35)
747 15:36:15.617201 ==
748 15:36:15.620456 Dram Type= 6, Freq= 0, CH_0, rank 1
749 15:36:15.627131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 15:36:15.627215 ==
751 15:36:15.630029 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 15:36:15.637054 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 15:36:15.645997 [CA 0] Center 37 (6~68) winsize 63
754 15:36:15.649549 [CA 1] Center 37 (7~68) winsize 62
755 15:36:15.652722 [CA 2] Center 35 (4~66) winsize 63
756 15:36:15.656352 [CA 3] Center 35 (4~66) winsize 63
757 15:36:15.659308 [CA 4] Center 34 (3~65) winsize 63
758 15:36:15.662941 [CA 5] Center 33 (3~64) winsize 62
759 15:36:15.663025
760 15:36:15.666085 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 15:36:15.666169
762 15:36:15.669658 [CATrainingPosCal] consider 2 rank data
763 15:36:15.672864 u2DelayCellTimex100 = 270/100 ps
764 15:36:15.676233 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 15:36:15.679791 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 15:36:15.682996 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
767 15:36:15.690038 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
768 15:36:15.693020 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
769 15:36:15.696517 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 15:36:15.696644
771 15:36:15.699859 CA PerBit enable=1, Macro0, CA PI delay=33
772 15:36:15.699988
773 15:36:15.703241 [CBTSetCACLKResult] CA Dly = 33
774 15:36:15.703317 CS Dly: 5 (0~37)
775 15:36:15.703395
776 15:36:15.706248 ----->DramcWriteLeveling(PI) begin...
777 15:36:15.706382 ==
778 15:36:15.710147 Dram Type= 6, Freq= 0, CH_0, rank 0
779 15:36:15.713945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 15:36:15.717377 ==
781 15:36:15.717460 Write leveling (Byte 0): 29 => 29
782 15:36:15.721230 Write leveling (Byte 1): 29 => 29
783 15:36:15.725148 DramcWriteLeveling(PI) end<-----
784 15:36:15.725236
785 15:36:15.725301 ==
786 15:36:15.729071 Dram Type= 6, Freq= 0, CH_0, rank 0
787 15:36:15.732202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 15:36:15.732286 ==
789 15:36:15.735902 [Gating] SW mode calibration
790 15:36:15.742256 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 15:36:15.745789 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 15:36:15.752859 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 15:36:15.756400 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 15:36:15.759319 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
795 15:36:15.765830 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
796 15:36:15.769540 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 15:36:15.773222 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 15:36:15.780037 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 15:36:15.782962 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 15:36:15.786102 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 15:36:15.792864 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 15:36:15.796231 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 15:36:15.799672 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 15:36:15.803005 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 15:36:15.809843 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 15:36:15.813690 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 15:36:15.816555 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 15:36:15.823292 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 15:36:15.826695 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
810 15:36:15.830160 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
811 15:36:15.837264 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 15:36:15.839999 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 15:36:15.843353 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 15:36:15.847147 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 15:36:15.853561 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 15:36:15.857214 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 15:36:15.860143 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 15:36:15.867274 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
819 15:36:15.870308 0 9 12 | B1->B0 | 2727 2e2e | 0 1 | (0 0) (0 0)
820 15:36:15.873712 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 15:36:15.880941 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 15:36:15.884439 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 15:36:15.887625 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 15:36:15.893983 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 15:36:15.897214 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
826 15:36:15.900948 0 10 8 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 1)
827 15:36:15.903866 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
828 15:36:15.910585 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
829 15:36:15.914350 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 15:36:15.917379 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 15:36:15.924784 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 15:36:15.928162 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 15:36:15.930891 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 15:36:15.937820 0 11 8 | B1->B0 | 2828 3131 | 0 0 | (1 1) (0 0)
835 15:36:15.941046 0 11 12 | B1->B0 | 3939 4040 | 0 0 | (0 0) (0 0)
836 15:36:15.944171 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 15:36:15.951318 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 15:36:15.954544 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 15:36:15.957906 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 15:36:15.961620 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 15:36:15.967755 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 15:36:15.971263 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
843 15:36:15.974606 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
844 15:36:15.981597 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 15:36:15.985474 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 15:36:15.988423 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 15:36:15.994933 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 15:36:15.998474 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 15:36:16.001207 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 15:36:16.008237 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 15:36:16.011365 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 15:36:16.015109 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 15:36:16.018266 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 15:36:16.025453 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 15:36:16.028193 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 15:36:16.031909 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 15:36:16.038762 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 15:36:16.041902 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 15:36:16.045322 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
860 15:36:16.048720 Total UI for P1: 0, mck2ui 16
861 15:36:16.052153 best dqsien dly found for B0: ( 0, 14, 8)
862 15:36:16.055416 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 15:36:16.058847 Total UI for P1: 0, mck2ui 16
864 15:36:16.062259 best dqsien dly found for B1: ( 0, 14, 10)
865 15:36:16.065636 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
866 15:36:16.072107 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
867 15:36:16.072191
868 15:36:16.075745 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 15:36:16.078867 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
870 15:36:16.082643 [Gating] SW calibration Done
871 15:36:16.082726 ==
872 15:36:16.085987 Dram Type= 6, Freq= 0, CH_0, rank 0
873 15:36:16.089107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
874 15:36:16.089191 ==
875 15:36:16.089257 RX Vref Scan: 0
876 15:36:16.089318
877 15:36:16.092455 RX Vref 0 -> 0, step: 1
878 15:36:16.092538
879 15:36:16.095753 RX Delay -130 -> 252, step: 16
880 15:36:16.099119 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
881 15:36:16.102589 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
882 15:36:16.106332 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
883 15:36:16.112832 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
884 15:36:16.116053 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
885 15:36:16.119188 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
886 15:36:16.122790 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
887 15:36:16.126051 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
888 15:36:16.132660 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
889 15:36:16.136139 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
890 15:36:16.139322 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
891 15:36:16.142674 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
892 15:36:16.146115 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
893 15:36:16.152674 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
894 15:36:16.156490 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
895 15:36:16.159648 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
896 15:36:16.159730 ==
897 15:36:16.162763 Dram Type= 6, Freq= 0, CH_0, rank 0
898 15:36:16.166177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
899 15:36:16.166261 ==
900 15:36:16.170005 DQS Delay:
901 15:36:16.170088 DQS0 = 0, DQS1 = 0
902 15:36:16.172880 DQM Delay:
903 15:36:16.172966 DQM0 = 88, DQM1 = 81
904 15:36:16.173033 DQ Delay:
905 15:36:16.176250 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
906 15:36:16.179797 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
907 15:36:16.183105 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
908 15:36:16.186673 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
909 15:36:16.186756
910 15:36:16.186822
911 15:36:16.186886 ==
912 15:36:16.189928 Dram Type= 6, Freq= 0, CH_0, rank 0
913 15:36:16.196592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 15:36:16.196693 ==
915 15:36:16.196796
916 15:36:16.196879
917 15:36:16.196961 TX Vref Scan disable
918 15:36:16.199868 == TX Byte 0 ==
919 15:36:16.203834 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
920 15:36:16.206967 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
921 15:36:16.210329 == TX Byte 1 ==
922 15:36:16.213472 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
923 15:36:16.217165 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
924 15:36:16.220229 ==
925 15:36:16.223965 Dram Type= 6, Freq= 0, CH_0, rank 0
926 15:36:16.227132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 15:36:16.227222 ==
928 15:36:16.239162 TX Vref=22, minBit 0, minWin=27, winSum=437
929 15:36:16.242391 TX Vref=24, minBit 3, minWin=27, winSum=442
930 15:36:16.245857 TX Vref=26, minBit 5, minWin=27, winSum=445
931 15:36:16.249157 TX Vref=28, minBit 12, minWin=27, winSum=450
932 15:36:16.252478 TX Vref=30, minBit 13, minWin=27, winSum=450
933 15:36:16.259224 TX Vref=32, minBit 2, minWin=28, winSum=453
934 15:36:16.262868 [TxChooseVref] Worse bit 2, Min win 28, Win sum 453, Final Vref 32
935 15:36:16.262955
936 15:36:16.265895 Final TX Range 1 Vref 32
937 15:36:16.265979
938 15:36:16.266045 ==
939 15:36:16.269804 Dram Type= 6, Freq= 0, CH_0, rank 0
940 15:36:16.272691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 15:36:16.272780 ==
942 15:36:16.272862
943 15:36:16.275980
944 15:36:16.276063 TX Vref Scan disable
945 15:36:16.279636 == TX Byte 0 ==
946 15:36:16.282843 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
947 15:36:16.286313 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
948 15:36:16.289383 == TX Byte 1 ==
949 15:36:16.292731 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
950 15:36:16.296455 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
951 15:36:16.296539
952 15:36:16.299417 [DATLAT]
953 15:36:16.299500 Freq=800, CH0 RK0
954 15:36:16.299567
955 15:36:16.302943 DATLAT Default: 0xa
956 15:36:16.303026 0, 0xFFFF, sum = 0
957 15:36:16.306227 1, 0xFFFF, sum = 0
958 15:36:16.306311 2, 0xFFFF, sum = 0
959 15:36:16.309758 3, 0xFFFF, sum = 0
960 15:36:16.309842 4, 0xFFFF, sum = 0
961 15:36:16.312888 5, 0xFFFF, sum = 0
962 15:36:16.312973 6, 0xFFFF, sum = 0
963 15:36:16.316369 7, 0xFFFF, sum = 0
964 15:36:16.316453 8, 0xFFFF, sum = 0
965 15:36:16.320111 9, 0x0, sum = 1
966 15:36:16.320197 10, 0x0, sum = 2
967 15:36:16.323207 11, 0x0, sum = 3
968 15:36:16.323345 12, 0x0, sum = 4
969 15:36:16.326854 best_step = 10
970 15:36:16.326937
971 15:36:16.327002 ==
972 15:36:16.330046 Dram Type= 6, Freq= 0, CH_0, rank 0
973 15:36:16.333376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 15:36:16.333460 ==
975 15:36:16.333525 RX Vref Scan: 1
976 15:36:16.336569
977 15:36:16.336653 Set Vref Range= 32 -> 127
978 15:36:16.336745
979 15:36:16.340023 RX Vref 32 -> 127, step: 1
980 15:36:16.340106
981 15:36:16.343759 RX Delay -95 -> 252, step: 8
982 15:36:16.343864
983 15:36:16.346655 Set Vref, RX VrefLevel [Byte0]: 32
984 15:36:16.350554 [Byte1]: 32
985 15:36:16.350637
986 15:36:16.353782 Set Vref, RX VrefLevel [Byte0]: 33
987 15:36:16.357372 [Byte1]: 33
988 15:36:16.357456
989 15:36:16.360438 Set Vref, RX VrefLevel [Byte0]: 34
990 15:36:16.363860 [Byte1]: 34
991 15:36:16.367070
992 15:36:16.367170 Set Vref, RX VrefLevel [Byte0]: 35
993 15:36:16.370720 [Byte1]: 35
994 15:36:16.374977
995 15:36:16.375059 Set Vref, RX VrefLevel [Byte0]: 36
996 15:36:16.378381 [Byte1]: 36
997 15:36:16.383098
998 15:36:16.383180 Set Vref, RX VrefLevel [Byte0]: 37
999 15:36:16.386382 [Byte1]: 37
1000 15:36:16.390478
1001 15:36:16.390561 Set Vref, RX VrefLevel [Byte0]: 38
1002 15:36:16.394409 [Byte1]: 38
1003 15:36:16.397775
1004 15:36:16.397872 Set Vref, RX VrefLevel [Byte0]: 39
1005 15:36:16.401089 [Byte1]: 39
1006 15:36:16.405162
1007 15:36:16.405245 Set Vref, RX VrefLevel [Byte0]: 40
1008 15:36:16.408500 [Byte1]: 40
1009 15:36:16.413398
1010 15:36:16.413481 Set Vref, RX VrefLevel [Byte0]: 41
1011 15:36:16.416410 [Byte1]: 41
1012 15:36:16.420308
1013 15:36:16.420390 Set Vref, RX VrefLevel [Byte0]: 42
1014 15:36:16.423374 [Byte1]: 42
1015 15:36:16.427809
1016 15:36:16.427914 Set Vref, RX VrefLevel [Byte0]: 43
1017 15:36:16.431328 [Byte1]: 43
1018 15:36:16.435526
1019 15:36:16.435621 Set Vref, RX VrefLevel [Byte0]: 44
1020 15:36:16.438861 [Byte1]: 44
1021 15:36:16.443174
1022 15:36:16.443250 Set Vref, RX VrefLevel [Byte0]: 45
1023 15:36:16.446462 [Byte1]: 45
1024 15:36:16.450703
1025 15:36:16.450784 Set Vref, RX VrefLevel [Byte0]: 46
1026 15:36:16.453889 [Byte1]: 46
1027 15:36:16.458643
1028 15:36:16.458716 Set Vref, RX VrefLevel [Byte0]: 47
1029 15:36:16.461494 [Byte1]: 47
1030 15:36:16.465831
1031 15:36:16.465906 Set Vref, RX VrefLevel [Byte0]: 48
1032 15:36:16.469267 [Byte1]: 48
1033 15:36:16.473472
1034 15:36:16.473548 Set Vref, RX VrefLevel [Byte0]: 49
1035 15:36:16.477024 [Byte1]: 49
1036 15:36:16.481249
1037 15:36:16.481325 Set Vref, RX VrefLevel [Byte0]: 50
1038 15:36:16.484231 [Byte1]: 50
1039 15:36:16.488375
1040 15:36:16.488451 Set Vref, RX VrefLevel [Byte0]: 51
1041 15:36:16.492277 [Byte1]: 51
1042 15:36:16.496466
1043 15:36:16.496543 Set Vref, RX VrefLevel [Byte0]: 52
1044 15:36:16.499599 [Byte1]: 52
1045 15:36:16.504000
1046 15:36:16.504116 Set Vref, RX VrefLevel [Byte0]: 53
1047 15:36:16.506930 [Byte1]: 53
1048 15:36:16.511466
1049 15:36:16.511568 Set Vref, RX VrefLevel [Byte0]: 54
1050 15:36:16.514827 [Byte1]: 54
1051 15:36:16.519047
1052 15:36:16.519126 Set Vref, RX VrefLevel [Byte0]: 55
1053 15:36:16.522106 [Byte1]: 55
1054 15:36:16.526585
1055 15:36:16.526690 Set Vref, RX VrefLevel [Byte0]: 56
1056 15:36:16.529878 [Byte1]: 56
1057 15:36:16.534169
1058 15:36:16.534246 Set Vref, RX VrefLevel [Byte0]: 57
1059 15:36:16.537358 [Byte1]: 57
1060 15:36:16.541532
1061 15:36:16.541609 Set Vref, RX VrefLevel [Byte0]: 58
1062 15:36:16.545192 [Byte1]: 58
1063 15:36:16.549960
1064 15:36:16.550065 Set Vref, RX VrefLevel [Byte0]: 59
1065 15:36:16.552998 [Byte1]: 59
1066 15:36:16.556921
1067 15:36:16.557012 Set Vref, RX VrefLevel [Byte0]: 60
1068 15:36:16.560362 [Byte1]: 60
1069 15:36:16.564948
1070 15:36:16.565024 Set Vref, RX VrefLevel [Byte0]: 61
1071 15:36:16.567786 [Byte1]: 61
1072 15:36:16.572300
1073 15:36:16.572372 Set Vref, RX VrefLevel [Byte0]: 62
1074 15:36:16.575617 [Byte1]: 62
1075 15:36:16.579760
1076 15:36:16.579858 Set Vref, RX VrefLevel [Byte0]: 63
1077 15:36:16.583336 [Byte1]: 63
1078 15:36:16.587557
1079 15:36:16.587636 Set Vref, RX VrefLevel [Byte0]: 64
1080 15:36:16.590585 [Byte1]: 64
1081 15:36:16.595108
1082 15:36:16.595185 Set Vref, RX VrefLevel [Byte0]: 65
1083 15:36:16.598625 [Byte1]: 65
1084 15:36:16.602375
1085 15:36:16.602453 Set Vref, RX VrefLevel [Byte0]: 66
1086 15:36:16.605819 [Byte1]: 66
1087 15:36:16.610025
1088 15:36:16.610135 Set Vref, RX VrefLevel [Byte0]: 67
1089 15:36:16.613392 [Byte1]: 67
1090 15:36:16.617949
1091 15:36:16.618049 Set Vref, RX VrefLevel [Byte0]: 68
1092 15:36:16.620870 [Byte1]: 68
1093 15:36:16.625281
1094 15:36:16.625394 Set Vref, RX VrefLevel [Byte0]: 69
1095 15:36:16.628701 [Byte1]: 69
1096 15:36:16.633189
1097 15:36:16.633263 Set Vref, RX VrefLevel [Byte0]: 70
1098 15:36:16.636351 [Byte1]: 70
1099 15:36:16.640501
1100 15:36:16.640602 Set Vref, RX VrefLevel [Byte0]: 71
1101 15:36:16.643938 [Byte1]: 71
1102 15:36:16.648368
1103 15:36:16.648477 Set Vref, RX VrefLevel [Byte0]: 72
1104 15:36:16.651224 [Byte1]: 72
1105 15:36:16.655466
1106 15:36:16.655558 Set Vref, RX VrefLevel [Byte0]: 73
1107 15:36:16.659394 [Byte1]: 73
1108 15:36:16.663448
1109 15:36:16.663556 Set Vref, RX VrefLevel [Byte0]: 74
1110 15:36:16.666685 [Byte1]: 74
1111 15:36:16.671190
1112 15:36:16.671288 Set Vref, RX VrefLevel [Byte0]: 75
1113 15:36:16.674336 [Byte1]: 75
1114 15:36:16.678700
1115 15:36:16.678800 Set Vref, RX VrefLevel [Byte0]: 76
1116 15:36:16.682132 [Byte1]: 76
1117 15:36:16.686433
1118 15:36:16.686530 Final RX Vref Byte 0 = 62 to rank0
1119 15:36:16.689615 Final RX Vref Byte 1 = 58 to rank0
1120 15:36:16.692618 Final RX Vref Byte 0 = 62 to rank1
1121 15:36:16.696347 Final RX Vref Byte 1 = 58 to rank1==
1122 15:36:16.699449 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 15:36:16.706319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1124 15:36:16.706394 ==
1125 15:36:16.706457 DQS Delay:
1126 15:36:16.706527 DQS0 = 0, DQS1 = 0
1127 15:36:16.709435 DQM Delay:
1128 15:36:16.709540 DQM0 = 86, DQM1 = 79
1129 15:36:16.712745 DQ Delay:
1130 15:36:16.716477 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1131 15:36:16.716582 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1132 15:36:16.719469 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1133 15:36:16.722990 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1134 15:36:16.723102
1135 15:36:16.726346
1136 15:36:16.733194 [DQSOSCAuto] RK0, (LSB)MR18= 0x270f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1137 15:36:16.736256 CH0 RK0: MR19=606, MR18=270F
1138 15:36:16.743290 CH0_RK0: MR19=0x606, MR18=0x270F, DQSOSC=400, MR23=63, INC=92, DEC=61
1139 15:36:16.743372
1140 15:36:16.747084 ----->DramcWriteLeveling(PI) begin...
1141 15:36:16.747188 ==
1142 15:36:16.750111 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 15:36:16.753072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 15:36:16.753147 ==
1145 15:36:16.756623 Write leveling (Byte 0): 29 => 29
1146 15:36:16.760019 Write leveling (Byte 1): 29 => 29
1147 15:36:16.763252 DramcWriteLeveling(PI) end<-----
1148 15:36:16.763352
1149 15:36:16.763442 ==
1150 15:36:16.766974 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 15:36:16.770331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 15:36:16.770466 ==
1153 15:36:16.773462 [Gating] SW mode calibration
1154 15:36:16.780119 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 15:36:16.783648 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 15:36:16.790386 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 15:36:16.834163 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1158 15:36:16.834490 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1159 15:36:16.834594 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 15:36:16.834717 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 15:36:16.834861 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 15:36:16.834951 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 15:36:16.835606 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 15:36:16.835707 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 15:36:16.835986 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 15:36:16.836400 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 15:36:16.878363 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 15:36:16.878748 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 15:36:16.878848 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 15:36:16.879288 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 15:36:16.879861 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 15:36:16.880421 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 15:36:16.880700 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1174 15:36:16.880812 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1175 15:36:16.880926 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 15:36:16.881224 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 15:36:16.884260 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 15:36:16.887560 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 15:36:16.890564 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 15:36:16.894095 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 15:36:16.900946 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1182 15:36:16.904077 0 9 8 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
1183 15:36:16.907398 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1184 15:36:16.910661 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 15:36:16.917326 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 15:36:16.921469 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 15:36:16.924504 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 15:36:16.931336 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 15:36:16.934163 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
1190 15:36:16.938299 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
1191 15:36:16.944225 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1192 15:36:16.947893 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 15:36:16.951219 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 15:36:16.957781 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 15:36:16.961839 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 15:36:16.965189 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 15:36:16.969359 0 11 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1198 15:36:16.972847 0 11 8 | B1->B0 | 2c2c 4040 | 1 0 | (0 0) (0 0)
1199 15:36:16.979990 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
1200 15:36:16.983161 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 15:36:16.986534 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 15:36:16.990429 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 15:36:16.997375 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 15:36:17.000620 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 15:36:17.004230 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1206 15:36:17.007708 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1207 15:36:17.014132 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 15:36:17.017692 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 15:36:17.020910 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 15:36:17.027898 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 15:36:17.031246 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 15:36:17.034141 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 15:36:17.040943 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 15:36:17.044460 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 15:36:17.047792 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 15:36:17.054469 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 15:36:17.057944 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 15:36:17.061350 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 15:36:17.064613 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 15:36:17.071285 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 15:36:17.074676 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1222 15:36:17.078149 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1223 15:36:17.084577 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 15:36:17.084705 Total UI for P1: 0, mck2ui 16
1225 15:36:17.091531 best dqsien dly found for B0: ( 0, 14, 6)
1226 15:36:17.091638 Total UI for P1: 0, mck2ui 16
1227 15:36:17.098057 best dqsien dly found for B1: ( 0, 14, 10)
1228 15:36:17.101860 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1229 15:36:17.105210 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1230 15:36:17.105302
1231 15:36:17.108610 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1232 15:36:17.111962 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1233 15:36:17.115245 [Gating] SW calibration Done
1234 15:36:17.115374 ==
1235 15:36:17.118983 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 15:36:17.122064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1237 15:36:17.122210 ==
1238 15:36:17.125298 RX Vref Scan: 0
1239 15:36:17.125378
1240 15:36:17.125443 RX Vref 0 -> 0, step: 1
1241 15:36:17.125503
1242 15:36:17.128458 RX Delay -130 -> 252, step: 16
1243 15:36:17.132080 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1244 15:36:17.135594 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1245 15:36:17.142466 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1246 15:36:17.145480 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1247 15:36:17.148619 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1248 15:36:17.151960 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1249 15:36:17.155455 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1250 15:36:17.162271 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1251 15:36:17.165615 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1252 15:36:17.168958 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1253 15:36:17.172446 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1254 15:36:17.176219 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1255 15:36:17.182334 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1256 15:36:17.185670 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1257 15:36:17.189023 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1258 15:36:17.192952 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1259 15:36:17.193061 ==
1260 15:36:17.196524 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 15:36:17.199046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 15:36:17.202599 ==
1263 15:36:17.202676 DQS Delay:
1264 15:36:17.202742 DQS0 = 0, DQS1 = 0
1265 15:36:17.205691 DQM Delay:
1266 15:36:17.205793 DQM0 = 86, DQM1 = 77
1267 15:36:17.209660 DQ Delay:
1268 15:36:17.209745 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1269 15:36:17.212541 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1270 15:36:17.215764 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1271 15:36:17.219331 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1272 15:36:17.219443
1273 15:36:17.222634
1274 15:36:17.222718 ==
1275 15:36:17.226009 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 15:36:17.229407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 15:36:17.229511 ==
1278 15:36:17.229579
1279 15:36:17.229654
1280 15:36:17.232794 TX Vref Scan disable
1281 15:36:17.232866 == TX Byte 0 ==
1282 15:36:17.239343 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1283 15:36:17.243301 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1284 15:36:17.243377 == TX Byte 1 ==
1285 15:36:17.246498 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1286 15:36:17.252995 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1287 15:36:17.253080 ==
1288 15:36:17.256278 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 15:36:17.259510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 15:36:17.259614 ==
1291 15:36:17.272703 TX Vref=22, minBit 2, minWin=27, winSum=441
1292 15:36:17.276150 TX Vref=24, minBit 7, minWin=27, winSum=448
1293 15:36:17.279733 TX Vref=26, minBit 3, minWin=27, winSum=449
1294 15:36:17.282725 TX Vref=28, minBit 9, minWin=27, winSum=453
1295 15:36:17.286067 TX Vref=30, minBit 0, minWin=28, winSum=454
1296 15:36:17.289854 TX Vref=32, minBit 0, minWin=28, winSum=454
1297 15:36:17.296518 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1298 15:36:17.296641
1299 15:36:17.299783 Final TX Range 1 Vref 30
1300 15:36:17.299903
1301 15:36:17.299994 ==
1302 15:36:17.302768 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 15:36:17.306139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 15:36:17.306223 ==
1305 15:36:17.306286
1306 15:36:17.306344
1307 15:36:17.309848 TX Vref Scan disable
1308 15:36:17.312787 == TX Byte 0 ==
1309 15:36:17.316510 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1310 15:36:17.319642 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1311 15:36:17.323334 == TX Byte 1 ==
1312 15:36:17.326618 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1313 15:36:17.329773 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1314 15:36:17.329872
1315 15:36:17.333059 [DATLAT]
1316 15:36:17.333136 Freq=800, CH0 RK1
1317 15:36:17.333200
1318 15:36:17.336237 DATLAT Default: 0xa
1319 15:36:17.336337 0, 0xFFFF, sum = 0
1320 15:36:17.339477 1, 0xFFFF, sum = 0
1321 15:36:17.339577 2, 0xFFFF, sum = 0
1322 15:36:17.342860 3, 0xFFFF, sum = 0
1323 15:36:17.342959 4, 0xFFFF, sum = 0
1324 15:36:17.346171 5, 0xFFFF, sum = 0
1325 15:36:17.346271 6, 0xFFFF, sum = 0
1326 15:36:17.349822 7, 0xFFFF, sum = 0
1327 15:36:17.349938 8, 0xFFFF, sum = 0
1328 15:36:17.353257 9, 0x0, sum = 1
1329 15:36:17.353357 10, 0x0, sum = 2
1330 15:36:17.356760 11, 0x0, sum = 3
1331 15:36:17.356873 12, 0x0, sum = 4
1332 15:36:17.359803 best_step = 10
1333 15:36:17.359905
1334 15:36:17.360005 ==
1335 15:36:17.363136 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 15:36:17.366389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 15:36:17.366487 ==
1338 15:36:17.366587 RX Vref Scan: 0
1339 15:36:17.369727
1340 15:36:17.369803 RX Vref 0 -> 0, step: 1
1341 15:36:17.369865
1342 15:36:17.373039 RX Delay -95 -> 252, step: 8
1343 15:36:17.376484 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1344 15:36:17.383280 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1345 15:36:17.386707 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1346 15:36:17.390255 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1347 15:36:17.393154 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1348 15:36:17.396781 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1349 15:36:17.403524 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1350 15:36:17.406913 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1351 15:36:17.410416 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1352 15:36:17.413820 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1353 15:36:17.417341 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1354 15:36:17.420228 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1355 15:36:17.427319 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1356 15:36:17.430483 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1357 15:36:17.433749 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1358 15:36:17.437077 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1359 15:36:17.437162 ==
1360 15:36:17.440414 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 15:36:17.447167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 15:36:17.447312 ==
1363 15:36:17.447398 DQS Delay:
1364 15:36:17.450543 DQS0 = 0, DQS1 = 0
1365 15:36:17.450628 DQM Delay:
1366 15:36:17.450712 DQM0 = 87, DQM1 = 77
1367 15:36:17.454193 DQ Delay:
1368 15:36:17.457082 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1369 15:36:17.460652 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1370 15:36:17.460760 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1371 15:36:17.467129 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1372 15:36:17.467213
1373 15:36:17.467298
1374 15:36:17.473971 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
1375 15:36:17.477211 CH0 RK1: MR19=606, MR18=2F17
1376 15:36:17.483870 CH0_RK1: MR19=0x606, MR18=0x2F17, DQSOSC=397, MR23=63, INC=93, DEC=62
1377 15:36:17.487445 [RxdqsGatingPostProcess] freq 800
1378 15:36:17.490978 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1379 15:36:17.494093 Pre-setting of DQS Precalculation
1380 15:36:17.501115 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1381 15:36:17.501199 ==
1382 15:36:17.504422 Dram Type= 6, Freq= 0, CH_1, rank 0
1383 15:36:17.507693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1384 15:36:17.507778 ==
1385 15:36:17.510825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1386 15:36:17.517876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1387 15:36:17.527721 [CA 0] Center 36 (6~66) winsize 61
1388 15:36:17.530666 [CA 1] Center 36 (6~66) winsize 61
1389 15:36:17.534313 [CA 2] Center 35 (5~65) winsize 61
1390 15:36:17.537577 [CA 3] Center 34 (4~65) winsize 62
1391 15:36:17.540635 [CA 4] Center 34 (4~65) winsize 62
1392 15:36:17.543915 [CA 5] Center 34 (4~64) winsize 61
1393 15:36:17.543990
1394 15:36:17.547827 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1395 15:36:17.547922
1396 15:36:17.550968 [CATrainingPosCal] consider 1 rank data
1397 15:36:17.554236 u2DelayCellTimex100 = 270/100 ps
1398 15:36:17.557890 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1399 15:36:17.561137 CA1 delay=36 (6~66),Diff = 2 PI (14 cell)
1400 15:36:17.564086 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1401 15:36:17.571123 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 15:36:17.574085 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1403 15:36:17.577440 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1404 15:36:17.577524
1405 15:36:17.580876 CA PerBit enable=1, Macro0, CA PI delay=34
1406 15:36:17.580964
1407 15:36:17.584642 [CBTSetCACLKResult] CA Dly = 34
1408 15:36:17.584780 CS Dly: 4 (0~35)
1409 15:36:17.584884 ==
1410 15:36:17.587913 Dram Type= 6, Freq= 0, CH_1, rank 1
1411 15:36:17.594572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 15:36:17.594646 ==
1413 15:36:17.597902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 15:36:17.604914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 15:36:17.613467 [CA 0] Center 36 (6~67) winsize 62
1416 15:36:17.617252 [CA 1] Center 36 (6~66) winsize 61
1417 15:36:17.620233 [CA 2] Center 34 (4~64) winsize 61
1418 15:36:17.623607 [CA 3] Center 33 (3~64) winsize 62
1419 15:36:17.627015 [CA 4] Center 34 (4~65) winsize 62
1420 15:36:17.630908 [CA 5] Center 33 (3~64) winsize 62
1421 15:36:17.630992
1422 15:36:17.634636 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1423 15:36:17.634728
1424 15:36:17.638489 [CATrainingPosCal] consider 2 rank data
1425 15:36:17.642141 u2DelayCellTimex100 = 270/100 ps
1426 15:36:17.645698 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1427 15:36:17.649761 CA1 delay=36 (6~66),Diff = 2 PI (14 cell)
1428 15:36:17.653648 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1429 15:36:17.657212 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1430 15:36:17.660833 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1431 15:36:17.664298 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1432 15:36:17.664397
1433 15:36:17.668490 CA PerBit enable=1, Macro0, CA PI delay=34
1434 15:36:17.668587
1435 15:36:17.671386 [CBTSetCACLKResult] CA Dly = 34
1436 15:36:17.671493 CS Dly: 5 (0~37)
1437 15:36:17.671582
1438 15:36:17.674560 ----->DramcWriteLeveling(PI) begin...
1439 15:36:17.674657 ==
1440 15:36:17.677924 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 15:36:17.681460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 15:36:17.681564 ==
1443 15:36:17.685385 Write leveling (Byte 0): 28 => 28
1444 15:36:17.687889 Write leveling (Byte 1): 28 => 28
1445 15:36:17.691560 DramcWriteLeveling(PI) end<-----
1446 15:36:17.691670
1447 15:36:17.691762 ==
1448 15:36:17.694644 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 15:36:17.697864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 15:36:17.701485 ==
1451 15:36:17.701557 [Gating] SW mode calibration
1452 15:36:17.711106 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1453 15:36:17.714712 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1454 15:36:17.718161 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1455 15:36:17.724773 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1456 15:36:17.728121 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 15:36:17.732198 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 15:36:17.738107 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 15:36:17.741758 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 15:36:17.744945 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 15:36:17.748660 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 15:36:17.755079 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 15:36:17.758531 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 15:36:17.761532 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 15:36:17.768580 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1466 15:36:17.772099 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1467 15:36:17.775392 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1468 15:36:17.782153 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1469 15:36:17.785305 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1470 15:36:17.788534 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1471 15:36:17.795536 0 8 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1472 15:36:17.798826 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1473 15:36:17.801918 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 15:36:17.808833 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1475 15:36:17.812250 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 15:36:17.815412 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 15:36:17.818512 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 15:36:17.825341 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1479 15:36:17.829475 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 15:36:17.832323 0 9 8 | B1->B0 | 2626 2626 | 0 1 | (0 0) (0 0)
1481 15:36:17.838819 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1482 15:36:17.842399 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 15:36:17.845894 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1484 15:36:17.852379 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 15:36:17.856582 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1486 15:36:17.859669 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 15:36:17.865956 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 15:36:17.868941 0 10 8 | B1->B0 | 3030 2e2e | 0 0 | (1 1) (1 1)
1489 15:36:17.872431 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1490 15:36:17.876000 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 15:36:17.882707 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 15:36:17.885916 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1493 15:36:17.889567 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1494 15:36:17.895995 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 15:36:17.899464 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1496 15:36:17.902984 0 11 8 | B1->B0 | 3838 2e2e | 0 0 | (0 0) (0 0)
1497 15:36:17.909457 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 15:36:17.913037 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 15:36:17.915928 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 15:36:17.922995 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 15:36:17.926111 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 15:36:17.929991 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 15:36:17.932996 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 15:36:17.939756 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1505 15:36:17.943061 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 15:36:17.946536 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 15:36:17.953216 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 15:36:17.956675 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 15:36:17.960426 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 15:36:17.966378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 15:36:17.969756 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 15:36:17.973528 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 15:36:17.979836 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 15:36:17.983158 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 15:36:17.986978 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 15:36:17.990275 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 15:36:17.996525 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 15:36:18.000054 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 15:36:18.003357 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 15:36:18.010128 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1521 15:36:18.013828 Total UI for P1: 0, mck2ui 16
1522 15:36:18.016850 best dqsien dly found for B1: ( 0, 14, 6)
1523 15:36:18.019909 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1524 15:36:18.023748 Total UI for P1: 0, mck2ui 16
1525 15:36:18.026840 best dqsien dly found for B0: ( 0, 14, 8)
1526 15:36:18.030406 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1527 15:36:18.033761 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1528 15:36:18.033836
1529 15:36:18.036773 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1530 15:36:18.040567 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1531 15:36:18.043739 [Gating] SW calibration Done
1532 15:36:18.043813 ==
1533 15:36:18.047168 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 15:36:18.050721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1535 15:36:18.050799 ==
1536 15:36:18.054084 RX Vref Scan: 0
1537 15:36:18.054159
1538 15:36:18.056968 RX Vref 0 -> 0, step: 1
1539 15:36:18.057046
1540 15:36:18.057109 RX Delay -130 -> 252, step: 16
1541 15:36:18.063735 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1542 15:36:18.067183 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1543 15:36:18.070511 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1544 15:36:18.074175 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1545 15:36:18.077028 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1546 15:36:18.084151 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1547 15:36:18.087256 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1548 15:36:18.090749 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1549 15:36:18.094120 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1550 15:36:18.097475 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1551 15:36:18.100897 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1552 15:36:18.107168 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1553 15:36:18.110764 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1554 15:36:18.114541 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1555 15:36:18.118078 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1556 15:36:18.120824 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1557 15:36:18.124132 ==
1558 15:36:18.127750 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 15:36:18.130870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 15:36:18.130945 ==
1561 15:36:18.131008 DQS Delay:
1562 15:36:18.134431 DQS0 = 0, DQS1 = 0
1563 15:36:18.134501 DQM Delay:
1564 15:36:18.137678 DQM0 = 85, DQM1 = 77
1565 15:36:18.137757 DQ Delay:
1566 15:36:18.140814 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1567 15:36:18.144435 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1568 15:36:18.148084 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1569 15:36:18.151064 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1570 15:36:18.151133
1571 15:36:18.151194
1572 15:36:18.151252 ==
1573 15:36:18.154489 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 15:36:18.158033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 15:36:18.158103 ==
1576 15:36:18.158163
1577 15:36:18.158229
1578 15:36:18.161387 TX Vref Scan disable
1579 15:36:18.161460 == TX Byte 0 ==
1580 15:36:18.168179 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1581 15:36:18.171527 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1582 15:36:18.171603 == TX Byte 1 ==
1583 15:36:18.178098 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1584 15:36:18.181381 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1585 15:36:18.181458 ==
1586 15:36:18.184856 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 15:36:18.187914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 15:36:18.187984 ==
1589 15:36:18.202001 TX Vref=22, minBit 10, minWin=26, winSum=437
1590 15:36:18.205794 TX Vref=24, minBit 8, minWin=27, winSum=445
1591 15:36:18.208509 TX Vref=26, minBit 1, minWin=27, winSum=445
1592 15:36:18.212222 TX Vref=28, minBit 4, minWin=27, winSum=449
1593 15:36:18.215869 TX Vref=30, minBit 0, minWin=28, winSum=452
1594 15:36:18.219677 TX Vref=32, minBit 0, minWin=27, winSum=450
1595 15:36:18.226208 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
1596 15:36:18.226304
1597 15:36:18.229666 Final TX Range 1 Vref 30
1598 15:36:18.229744
1599 15:36:18.229807 ==
1600 15:36:18.232854 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 15:36:18.236366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 15:36:18.236451 ==
1603 15:36:18.236513
1604 15:36:18.236571
1605 15:36:18.239657 TX Vref Scan disable
1606 15:36:18.242932 == TX Byte 0 ==
1607 15:36:18.246763 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1608 15:36:18.249836 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1609 15:36:18.253059 == TX Byte 1 ==
1610 15:36:18.256252 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1611 15:36:18.259769 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1612 15:36:18.259852
1613 15:36:18.259912 [DATLAT]
1614 15:36:18.262977 Freq=800, CH1 RK0
1615 15:36:18.263049
1616 15:36:18.266773 DATLAT Default: 0xa
1617 15:36:18.266858 0, 0xFFFF, sum = 0
1618 15:36:18.270011 1, 0xFFFF, sum = 0
1619 15:36:18.270079 2, 0xFFFF, sum = 0
1620 15:36:18.273005 3, 0xFFFF, sum = 0
1621 15:36:18.273109 4, 0xFFFF, sum = 0
1622 15:36:18.276597 5, 0xFFFF, sum = 0
1623 15:36:18.276687 6, 0xFFFF, sum = 0
1624 15:36:18.280188 7, 0xFFFF, sum = 0
1625 15:36:18.280255 8, 0xFFFF, sum = 0
1626 15:36:18.282895 9, 0x0, sum = 1
1627 15:36:18.282963 10, 0x0, sum = 2
1628 15:36:18.286481 11, 0x0, sum = 3
1629 15:36:18.286553 12, 0x0, sum = 4
1630 15:36:18.286614 best_step = 10
1631 15:36:18.286679
1632 15:36:18.289796 ==
1633 15:36:18.293318 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 15:36:18.296767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 15:36:18.296853 ==
1636 15:36:18.296918 RX Vref Scan: 1
1637 15:36:18.296978
1638 15:36:18.299843 Set Vref Range= 32 -> 127
1639 15:36:18.299915
1640 15:36:18.303383 RX Vref 32 -> 127, step: 1
1641 15:36:18.303462
1642 15:36:18.306399 RX Delay -95 -> 252, step: 8
1643 15:36:18.306472
1644 15:36:18.309831 Set Vref, RX VrefLevel [Byte0]: 32
1645 15:36:18.313174 [Byte1]: 32
1646 15:36:18.313251
1647 15:36:18.316603 Set Vref, RX VrefLevel [Byte0]: 33
1648 15:36:18.320767 [Byte1]: 33
1649 15:36:18.320844
1650 15:36:18.323137 Set Vref, RX VrefLevel [Byte0]: 34
1651 15:36:18.326628 [Byte1]: 34
1652 15:36:18.326707
1653 15:36:18.330242 Set Vref, RX VrefLevel [Byte0]: 35
1654 15:36:18.333297 [Byte1]: 35
1655 15:36:18.337333
1656 15:36:18.337407 Set Vref, RX VrefLevel [Byte0]: 36
1657 15:36:18.340754 [Byte1]: 36
1658 15:36:18.344932
1659 15:36:18.345007 Set Vref, RX VrefLevel [Byte0]: 37
1660 15:36:18.348407 [Byte1]: 37
1661 15:36:18.352931
1662 15:36:18.353007 Set Vref, RX VrefLevel [Byte0]: 38
1663 15:36:18.355785 [Byte1]: 38
1664 15:36:18.360334
1665 15:36:18.360403 Set Vref, RX VrefLevel [Byte0]: 39
1666 15:36:18.363392 [Byte1]: 39
1667 15:36:18.368163
1668 15:36:18.368238 Set Vref, RX VrefLevel [Byte0]: 40
1669 15:36:18.371166 [Byte1]: 40
1670 15:36:18.375745
1671 15:36:18.375815 Set Vref, RX VrefLevel [Byte0]: 41
1672 15:36:18.378796 [Byte1]: 41
1673 15:36:18.383069
1674 15:36:18.383138 Set Vref, RX VrefLevel [Byte0]: 42
1675 15:36:18.386361 [Byte1]: 42
1676 15:36:18.390443
1677 15:36:18.390520 Set Vref, RX VrefLevel [Byte0]: 43
1678 15:36:18.393779 [Byte1]: 43
1679 15:36:18.398346
1680 15:36:18.398422 Set Vref, RX VrefLevel [Byte0]: 44
1681 15:36:18.401429 [Byte1]: 44
1682 15:36:18.405901
1683 15:36:18.405971 Set Vref, RX VrefLevel [Byte0]: 45
1684 15:36:18.408807 [Byte1]: 45
1685 15:36:18.413240
1686 15:36:18.413315 Set Vref, RX VrefLevel [Byte0]: 46
1687 15:36:18.416505 [Byte1]: 46
1688 15:36:18.421080
1689 15:36:18.421164 Set Vref, RX VrefLevel [Byte0]: 47
1690 15:36:18.424439 [Byte1]: 47
1691 15:36:18.428567
1692 15:36:18.428690 Set Vref, RX VrefLevel [Byte0]: 48
1693 15:36:18.431771 [Byte1]: 48
1694 15:36:18.435851
1695 15:36:18.435927 Set Vref, RX VrefLevel [Byte0]: 49
1696 15:36:18.440087 [Byte1]: 49
1697 15:36:18.443861
1698 15:36:18.443938 Set Vref, RX VrefLevel [Byte0]: 50
1699 15:36:18.447289 [Byte1]: 50
1700 15:36:18.451719
1701 15:36:18.451800 Set Vref, RX VrefLevel [Byte0]: 51
1702 15:36:18.455022 [Byte1]: 51
1703 15:36:18.458865
1704 15:36:18.458941 Set Vref, RX VrefLevel [Byte0]: 52
1705 15:36:18.462166 [Byte1]: 52
1706 15:36:18.466633
1707 15:36:18.466705 Set Vref, RX VrefLevel [Byte0]: 53
1708 15:36:18.469911 [Byte1]: 53
1709 15:36:18.473879
1710 15:36:18.473956 Set Vref, RX VrefLevel [Byte0]: 54
1711 15:36:18.477625 [Byte1]: 54
1712 15:36:18.481460
1713 15:36:18.481537 Set Vref, RX VrefLevel [Byte0]: 55
1714 15:36:18.484768 [Byte1]: 55
1715 15:36:18.489167
1716 15:36:18.489236 Set Vref, RX VrefLevel [Byte0]: 56
1717 15:36:18.492403 [Byte1]: 56
1718 15:36:18.496673
1719 15:36:18.496768 Set Vref, RX VrefLevel [Byte0]: 57
1720 15:36:18.500093 [Byte1]: 57
1721 15:36:18.504358
1722 15:36:18.504427 Set Vref, RX VrefLevel [Byte0]: 58
1723 15:36:18.507940 [Byte1]: 58
1724 15:36:18.511856
1725 15:36:18.511926 Set Vref, RX VrefLevel [Byte0]: 59
1726 15:36:18.515348 [Byte1]: 59
1727 15:36:18.520184
1728 15:36:18.520258 Set Vref, RX VrefLevel [Byte0]: 60
1729 15:36:18.523002 [Byte1]: 60
1730 15:36:18.527706
1731 15:36:18.527823 Set Vref, RX VrefLevel [Byte0]: 61
1732 15:36:18.530567 [Byte1]: 61
1733 15:36:18.534908
1734 15:36:18.535005 Set Vref, RX VrefLevel [Byte0]: 62
1735 15:36:18.537956 [Byte1]: 62
1736 15:36:18.542588
1737 15:36:18.542659 Set Vref, RX VrefLevel [Byte0]: 63
1738 15:36:18.545885 [Byte1]: 63
1739 15:36:18.549919
1740 15:36:18.549996 Set Vref, RX VrefLevel [Byte0]: 64
1741 15:36:18.553311 [Byte1]: 64
1742 15:36:18.557607
1743 15:36:18.557677 Set Vref, RX VrefLevel [Byte0]: 65
1744 15:36:18.560790 [Byte1]: 65
1745 15:36:18.565288
1746 15:36:18.565359 Set Vref, RX VrefLevel [Byte0]: 66
1747 15:36:18.568323 [Byte1]: 66
1748 15:36:18.572803
1749 15:36:18.572876 Set Vref, RX VrefLevel [Byte0]: 67
1750 15:36:18.576626 [Byte1]: 67
1751 15:36:18.580384
1752 15:36:18.580460 Set Vref, RX VrefLevel [Byte0]: 68
1753 15:36:18.583643 [Byte1]: 68
1754 15:36:18.587864
1755 15:36:18.587938 Set Vref, RX VrefLevel [Byte0]: 69
1756 15:36:18.591274 [Byte1]: 69
1757 15:36:18.595994
1758 15:36:18.596067 Set Vref, RX VrefLevel [Byte0]: 70
1759 15:36:18.599038 [Byte1]: 70
1760 15:36:18.603384
1761 15:36:18.603458 Set Vref, RX VrefLevel [Byte0]: 71
1762 15:36:18.606654 [Byte1]: 71
1763 15:36:18.610651
1764 15:36:18.610721 Set Vref, RX VrefLevel [Byte0]: 72
1765 15:36:18.614266 [Byte1]: 72
1766 15:36:18.618699
1767 15:36:18.618770 Set Vref, RX VrefLevel [Byte0]: 73
1768 15:36:18.621664 [Byte1]: 73
1769 15:36:18.626046
1770 15:36:18.626120 Set Vref, RX VrefLevel [Byte0]: 74
1771 15:36:18.629712 [Byte1]: 74
1772 15:36:18.633795
1773 15:36:18.633868 Set Vref, RX VrefLevel [Byte0]: 75
1774 15:36:18.637314 [Byte1]: 75
1775 15:36:18.641607
1776 15:36:18.641690 Set Vref, RX VrefLevel [Byte0]: 76
1777 15:36:18.644487 [Byte1]: 76
1778 15:36:18.648821
1779 15:36:18.648913 Set Vref, RX VrefLevel [Byte0]: 77
1780 15:36:18.652368 [Byte1]: 77
1781 15:36:18.656925
1782 15:36:18.657001 Set Vref, RX VrefLevel [Byte0]: 78
1783 15:36:18.659858 [Byte1]: 78
1784 15:36:18.664058
1785 15:36:18.664145 Final RX Vref Byte 0 = 62 to rank0
1786 15:36:18.667560 Final RX Vref Byte 1 = 57 to rank0
1787 15:36:18.671177 Final RX Vref Byte 0 = 62 to rank1
1788 15:36:18.674569 Final RX Vref Byte 1 = 57 to rank1==
1789 15:36:18.677237 Dram Type= 6, Freq= 0, CH_1, rank 0
1790 15:36:18.680476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 15:36:18.683926 ==
1792 15:36:18.684025 DQS Delay:
1793 15:36:18.684130 DQS0 = 0, DQS1 = 0
1794 15:36:18.687350 DQM Delay:
1795 15:36:18.687459 DQM0 = 83, DQM1 = 73
1796 15:36:18.690740 DQ Delay:
1797 15:36:18.690833 DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =84
1798 15:36:18.694251 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1799 15:36:18.697295 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1800 15:36:18.701110 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1801 15:36:18.701196
1802 15:36:18.701259
1803 15:36:18.711371 [DQSOSCAuto] RK0, (LSB)MR18= 0x3005, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
1804 15:36:18.714415 CH1 RK0: MR19=606, MR18=3005
1805 15:36:18.717908 CH1_RK0: MR19=0x606, MR18=0x3005, DQSOSC=397, MR23=63, INC=93, DEC=62
1806 15:36:18.721826
1807 15:36:18.725106 ----->DramcWriteLeveling(PI) begin...
1808 15:36:18.725179 ==
1809 15:36:18.728436 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 15:36:18.731470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 15:36:18.731544 ==
1812 15:36:18.734787 Write leveling (Byte 0): 27 => 27
1813 15:36:18.738056 Write leveling (Byte 1): 27 => 27
1814 15:36:18.741485 DramcWriteLeveling(PI) end<-----
1815 15:36:18.741560
1816 15:36:18.741623 ==
1817 15:36:18.745071 Dram Type= 6, Freq= 0, CH_1, rank 1
1818 15:36:18.747949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1819 15:36:18.748023 ==
1820 15:36:18.751346 [Gating] SW mode calibration
1821 15:36:18.758006 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1822 15:36:18.761684 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1823 15:36:18.768352 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1824 15:36:18.771635 0 6 4 | B1->B0 | 2423 2323 | 1 0 | (1 0) (0 0)
1825 15:36:18.774846 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 15:36:18.781889 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1827 15:36:18.784929 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 15:36:18.788498 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1829 15:36:18.795181 0 6 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1830 15:36:18.798412 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 15:36:18.801824 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 15:36:18.805351 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 15:36:18.812238 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1834 15:36:18.815406 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1835 15:36:18.818805 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1836 15:36:18.825491 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1837 15:36:18.828844 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 15:36:18.832159 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1839 15:36:18.838933 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 1)
1840 15:36:18.842858 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (1 1)
1841 15:36:18.845866 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1842 15:36:18.852293 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1843 15:36:18.856048 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1844 15:36:18.859288 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 15:36:18.862493 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 15:36:18.869214 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 15:36:18.872713 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1848 15:36:18.875776 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
1849 15:36:18.882804 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1850 15:36:18.885901 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1851 15:36:18.889223 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 15:36:18.896121 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1853 15:36:18.899568 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1854 15:36:18.903000 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1855 15:36:18.909325 0 10 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1856 15:36:18.912748 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (1 0) (0 1)
1857 15:36:18.916162 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
1858 15:36:18.919573 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 15:36:18.926763 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 15:36:18.929869 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1861 15:36:18.933047 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 15:36:18.939646 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1863 15:36:18.943138 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1864 15:36:18.946320 0 11 4 | B1->B0 | 2626 3232 | 0 1 | (0 0) (0 0)
1865 15:36:18.953869 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1866 15:36:18.956433 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 15:36:18.960230 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 15:36:18.966441 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 15:36:18.969875 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 15:36:18.973151 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 15:36:18.979960 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 15:36:18.983019 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1873 15:36:18.986965 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1874 15:36:18.990112 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 15:36:18.996774 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 15:36:18.999838 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 15:36:19.003255 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 15:36:19.010149 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 15:36:19.013391 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 15:36:19.016527 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 15:36:19.023609 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 15:36:19.027008 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 15:36:19.030353 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 15:36:19.036903 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 15:36:19.040404 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 15:36:19.043709 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 15:36:19.046839 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 15:36:19.053609 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1889 15:36:19.057282 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1890 15:36:19.060396 Total UI for P1: 0, mck2ui 16
1891 15:36:19.064240 best dqsien dly found for B0: ( 0, 14, 4)
1892 15:36:19.067155 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 15:36:19.070153 Total UI for P1: 0, mck2ui 16
1894 15:36:19.074016 best dqsien dly found for B1: ( 0, 14, 8)
1895 15:36:19.076997 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1896 15:36:19.080716 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1897 15:36:19.080799
1898 15:36:19.087710 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1899 15:36:19.090433 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1900 15:36:19.090518 [Gating] SW calibration Done
1901 15:36:19.090583 ==
1902 15:36:19.094413 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 15:36:19.100556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 15:36:19.100640 ==
1905 15:36:19.100744 RX Vref Scan: 0
1906 15:36:19.100806
1907 15:36:19.104213 RX Vref 0 -> 0, step: 1
1908 15:36:19.104295
1909 15:36:19.107267 RX Delay -130 -> 252, step: 16
1910 15:36:19.111038 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1911 15:36:19.114074 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1912 15:36:19.117452 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1913 15:36:19.124089 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1914 15:36:19.127835 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1915 15:36:19.131140 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1916 15:36:19.134116 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1917 15:36:19.137410 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1918 15:36:19.141119 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1919 15:36:19.147590 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1920 15:36:19.151004 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1921 15:36:19.154829 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1922 15:36:19.157806 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1923 15:36:19.161118 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1924 15:36:19.168390 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1925 15:36:19.171167 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1926 15:36:19.171252 ==
1927 15:36:19.174710 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 15:36:19.178107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 15:36:19.178190 ==
1930 15:36:19.181097 DQS Delay:
1931 15:36:19.181179 DQS0 = 0, DQS1 = 0
1932 15:36:19.181261 DQM Delay:
1933 15:36:19.184370 DQM0 = 82, DQM1 = 77
1934 15:36:19.184454 DQ Delay:
1935 15:36:19.188014 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1936 15:36:19.191474 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1937 15:36:19.194780 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1938 15:36:19.197787 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1939 15:36:19.197875
1940 15:36:19.197941
1941 15:36:19.198002 ==
1942 15:36:19.201273 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 15:36:19.204529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 15:36:19.208065 ==
1945 15:36:19.208148
1946 15:36:19.208214
1947 15:36:19.208275 TX Vref Scan disable
1948 15:36:19.211201 == TX Byte 0 ==
1949 15:36:19.214771 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1950 15:36:19.218128 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1951 15:36:19.221449 == TX Byte 1 ==
1952 15:36:19.224510 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1953 15:36:19.228281 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1954 15:36:19.231257 ==
1955 15:36:19.231341 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 15:36:19.238240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 15:36:19.238325 ==
1958 15:36:19.250618 TX Vref=22, minBit 1, minWin=27, winSum=441
1959 15:36:19.253770 TX Vref=24, minBit 1, minWin=27, winSum=443
1960 15:36:19.256835 TX Vref=26, minBit 11, minWin=27, winSum=446
1961 15:36:19.260180 TX Vref=28, minBit 13, minWin=27, winSum=446
1962 15:36:19.263506 TX Vref=30, minBit 15, minWin=27, winSum=449
1963 15:36:19.269888 TX Vref=32, minBit 0, minWin=28, winSum=454
1964 15:36:19.273529 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1965 15:36:19.273618
1966 15:36:19.277138 Final TX Range 1 Vref 32
1967 15:36:19.277222
1968 15:36:19.277288 ==
1969 15:36:19.280401 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 15:36:19.283330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 15:36:19.283414 ==
1972 15:36:19.283481
1973 15:36:19.286772
1974 15:36:19.286854 TX Vref Scan disable
1975 15:36:19.290568 == TX Byte 0 ==
1976 15:36:19.293777 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1977 15:36:19.297055 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1978 15:36:19.300412 == TX Byte 1 ==
1979 15:36:19.303683 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1980 15:36:19.307336 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1981 15:36:19.307420
1982 15:36:19.310171 [DATLAT]
1983 15:36:19.310247 Freq=800, CH1 RK1
1984 15:36:19.310331
1985 15:36:19.313768 DATLAT Default: 0xa
1986 15:36:19.313843 0, 0xFFFF, sum = 0
1987 15:36:19.317308 1, 0xFFFF, sum = 0
1988 15:36:19.317423 2, 0xFFFF, sum = 0
1989 15:36:19.320270 3, 0xFFFF, sum = 0
1990 15:36:19.320359 4, 0xFFFF, sum = 0
1991 15:36:19.323940 5, 0xFFFF, sum = 0
1992 15:36:19.324015 6, 0xFFFF, sum = 0
1993 15:36:19.327209 7, 0xFFFF, sum = 0
1994 15:36:19.327295 8, 0xFFFF, sum = 0
1995 15:36:19.330501 9, 0x0, sum = 1
1996 15:36:19.330585 10, 0x0, sum = 2
1997 15:36:19.333773 11, 0x0, sum = 3
1998 15:36:19.333850 12, 0x0, sum = 4
1999 15:36:19.337153 best_step = 10
2000 15:36:19.337227
2001 15:36:19.337306 ==
2002 15:36:19.340505 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 15:36:19.343907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 15:36:19.343986 ==
2005 15:36:19.347121 RX Vref Scan: 0
2006 15:36:19.347196
2007 15:36:19.347275 RX Vref 0 -> 0, step: 1
2008 15:36:19.347354
2009 15:36:19.350575 RX Delay -95 -> 252, step: 8
2010 15:36:19.357871 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2011 15:36:19.360764 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2012 15:36:19.364045 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2013 15:36:19.367536 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2014 15:36:19.371019 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2015 15:36:19.373907 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
2016 15:36:19.380794 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2017 15:36:19.384837 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2018 15:36:19.387861 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2019 15:36:19.390851 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2020 15:36:19.394539 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2021 15:36:19.400985 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2022 15:36:19.404026 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2023 15:36:19.407427 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2024 15:36:19.410617 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2025 15:36:19.414121 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2026 15:36:19.417431 ==
2027 15:36:19.417524 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 15:36:19.424250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 15:36:19.424354 ==
2030 15:36:19.424445 DQS Delay:
2031 15:36:19.427566 DQS0 = 0, DQS1 = 0
2032 15:36:19.427650 DQM Delay:
2033 15:36:19.430859 DQM0 = 79, DQM1 = 75
2034 15:36:19.430943 DQ Delay:
2035 15:36:19.434016 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2036 15:36:19.437537 DQ4 =80, DQ5 =88, DQ6 =92, DQ7 =76
2037 15:36:19.440867 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2038 15:36:19.444162 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2039 15:36:19.444245
2040 15:36:19.444309
2041 15:36:19.450887 [DQSOSCAuto] RK1, (LSB)MR18= 0x2632, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2042 15:36:19.454233 CH1 RK1: MR19=606, MR18=2632
2043 15:36:19.460954 CH1_RK1: MR19=0x606, MR18=0x2632, DQSOSC=397, MR23=63, INC=93, DEC=62
2044 15:36:19.464412 [RxdqsGatingPostProcess] freq 800
2045 15:36:19.467755 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2046 15:36:19.471278 Pre-setting of DQS Precalculation
2047 15:36:19.477849 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2048 15:36:19.484864 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2049 15:36:19.491489 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2050 15:36:19.491574
2051 15:36:19.491638
2052 15:36:19.495010 [Calibration Summary] 1600 Mbps
2053 15:36:19.495092 CH 0, Rank 0
2054 15:36:19.498345 SW Impedance : PASS
2055 15:36:19.501827 DUTY Scan : NO K
2056 15:36:19.501910 ZQ Calibration : PASS
2057 15:36:19.504993 Jitter Meter : NO K
2058 15:36:19.505075 CBT Training : PASS
2059 15:36:19.508543 Write leveling : PASS
2060 15:36:19.511685 RX DQS gating : PASS
2061 15:36:19.511768 RX DQ/DQS(RDDQC) : PASS
2062 15:36:19.514794 TX DQ/DQS : PASS
2063 15:36:19.518500 RX DATLAT : PASS
2064 15:36:19.518583 RX DQ/DQS(Engine): PASS
2065 15:36:19.521691 TX OE : NO K
2066 15:36:19.521774 All Pass.
2067 15:36:19.521839
2068 15:36:19.525234 CH 0, Rank 1
2069 15:36:19.525317 SW Impedance : PASS
2070 15:36:19.528557 DUTY Scan : NO K
2071 15:36:19.532027 ZQ Calibration : PASS
2072 15:36:19.532111 Jitter Meter : NO K
2073 15:36:19.535274 CBT Training : PASS
2074 15:36:19.535356 Write leveling : PASS
2075 15:36:19.538592 RX DQS gating : PASS
2076 15:36:19.541956 RX DQ/DQS(RDDQC) : PASS
2077 15:36:19.542063 TX DQ/DQS : PASS
2078 15:36:19.545245 RX DATLAT : PASS
2079 15:36:19.548706 RX DQ/DQS(Engine): PASS
2080 15:36:19.548798 TX OE : NO K
2081 15:36:19.551849 All Pass.
2082 15:36:19.551923
2083 15:36:19.551991 CH 1, Rank 0
2084 15:36:19.555633 SW Impedance : PASS
2085 15:36:19.555704 DUTY Scan : NO K
2086 15:36:19.558662 ZQ Calibration : PASS
2087 15:36:19.562077 Jitter Meter : NO K
2088 15:36:19.562152 CBT Training : PASS
2089 15:36:19.565512 Write leveling : PASS
2090 15:36:19.565587 RX DQS gating : PASS
2091 15:36:19.568822 RX DQ/DQS(RDDQC) : PASS
2092 15:36:19.572189 TX DQ/DQS : PASS
2093 15:36:19.572260 RX DATLAT : PASS
2094 15:36:19.576014 RX DQ/DQS(Engine): PASS
2095 15:36:19.579028 TX OE : NO K
2096 15:36:19.579104 All Pass.
2097 15:36:19.579166
2098 15:36:19.579224 CH 1, Rank 1
2099 15:36:19.582537 SW Impedance : PASS
2100 15:36:19.585701 DUTY Scan : NO K
2101 15:36:19.585774 ZQ Calibration : PASS
2102 15:36:19.589286 Jitter Meter : NO K
2103 15:36:19.592367 CBT Training : PASS
2104 15:36:19.592466 Write leveling : PASS
2105 15:36:19.596303 RX DQS gating : PASS
2106 15:36:19.596378 RX DQ/DQS(RDDQC) : PASS
2107 15:36:19.599392 TX DQ/DQS : PASS
2108 15:36:19.603042 RX DATLAT : PASS
2109 15:36:19.603118 RX DQ/DQS(Engine): PASS
2110 15:36:19.606431 TX OE : NO K
2111 15:36:19.606510 All Pass.
2112 15:36:19.606571
2113 15:36:19.609272 DramC Write-DBI off
2114 15:36:19.612612 PER_BANK_REFRESH: Hybrid Mode
2115 15:36:19.612717 TX_TRACKING: ON
2116 15:36:19.615976 [GetDramInforAfterCalByMRR] Vendor 6.
2117 15:36:19.619419 [GetDramInforAfterCalByMRR] Revision 606.
2118 15:36:19.622614 [GetDramInforAfterCalByMRR] Revision 2 0.
2119 15:36:19.625880 MR0 0x3b3b
2120 15:36:19.625966 MR8 0x5151
2121 15:36:19.629349 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 15:36:19.629464
2123 15:36:19.629554 MR0 0x3b3b
2124 15:36:19.632510 MR8 0x5151
2125 15:36:19.636017 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2126 15:36:19.636115
2127 15:36:19.645966 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2128 15:36:19.649398 [FAST_K] Save calibration result to emmc
2129 15:36:19.652851 [FAST_K] Save calibration result to emmc
2130 15:36:19.652927 dram_init: config_dvfs: 1
2131 15:36:19.659925 dramc_set_vcore_voltage set vcore to 662500
2132 15:36:19.660031 Read voltage for 1200, 2
2133 15:36:19.662900 Vio18 = 0
2134 15:36:19.662977 Vcore = 662500
2135 15:36:19.663040 Vdram = 0
2136 15:36:19.663098 Vddq = 0
2137 15:36:19.666626 Vmddr = 0
2138 15:36:19.669719 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2139 15:36:19.676317 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2140 15:36:19.676422 MEM_TYPE=3, freq_sel=15
2141 15:36:19.679628 sv_algorithm_assistance_LP4_1600
2142 15:36:19.686308 ============ PULL DRAM RESETB DOWN ============
2143 15:36:19.689956 ========== PULL DRAM RESETB DOWN end =========
2144 15:36:19.693192 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2145 15:36:19.696779 ===================================
2146 15:36:19.699920 LPDDR4 DRAM CONFIGURATION
2147 15:36:19.703614 ===================================
2148 15:36:19.706632 EX_ROW_EN[0] = 0x0
2149 15:36:19.706740 EX_ROW_EN[1] = 0x0
2150 15:36:19.710150 LP4Y_EN = 0x0
2151 15:36:19.710223 WORK_FSP = 0x0
2152 15:36:19.713665 WL = 0x4
2153 15:36:19.713740 RL = 0x4
2154 15:36:19.716513 BL = 0x2
2155 15:36:19.716613 RPST = 0x0
2156 15:36:19.719981 RD_PRE = 0x0
2157 15:36:19.720054 WR_PRE = 0x1
2158 15:36:19.723998 WR_PST = 0x0
2159 15:36:19.724072 DBI_WR = 0x0
2160 15:36:19.726846 DBI_RD = 0x0
2161 15:36:19.726912 OTF = 0x1
2162 15:36:19.730334 ===================================
2163 15:36:19.733357 ===================================
2164 15:36:19.736785 ANA top config
2165 15:36:19.740499 ===================================
2166 15:36:19.740599 DLL_ASYNC_EN = 0
2167 15:36:19.743876 ALL_SLAVE_EN = 0
2168 15:36:19.747367 NEW_RANK_MODE = 1
2169 15:36:19.750370 DLL_IDLE_MODE = 1
2170 15:36:19.750448 LP45_APHY_COMB_EN = 1
2171 15:36:19.753487 TX_ODT_DIS = 1
2172 15:36:19.757303 NEW_8X_MODE = 1
2173 15:36:19.760096 ===================================
2174 15:36:19.763719 ===================================
2175 15:36:19.766861 data_rate = 2400
2176 15:36:19.770604 CKR = 1
2177 15:36:19.770705 DQ_P2S_RATIO = 8
2178 15:36:19.773563 ===================================
2179 15:36:19.776879 CA_P2S_RATIO = 8
2180 15:36:19.780332 DQ_CA_OPEN = 0
2181 15:36:19.784260 DQ_SEMI_OPEN = 0
2182 15:36:19.787002 CA_SEMI_OPEN = 0
2183 15:36:19.790517 CA_FULL_RATE = 0
2184 15:36:19.790619 DQ_CKDIV4_EN = 0
2185 15:36:19.793799 CA_CKDIV4_EN = 0
2186 15:36:19.797686 CA_PREDIV_EN = 0
2187 15:36:19.801052 PH8_DLY = 17
2188 15:36:19.804341 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2189 15:36:19.807450 DQ_AAMCK_DIV = 4
2190 15:36:19.807547 CA_AAMCK_DIV = 4
2191 15:36:19.810490 CA_ADMCK_DIV = 4
2192 15:36:19.814401 DQ_TRACK_CA_EN = 0
2193 15:36:19.817420 CA_PICK = 1200
2194 15:36:19.820981 CA_MCKIO = 1200
2195 15:36:19.824353 MCKIO_SEMI = 0
2196 15:36:19.824463 PLL_FREQ = 2366
2197 15:36:19.827333 DQ_UI_PI_RATIO = 32
2198 15:36:19.831086 CA_UI_PI_RATIO = 0
2199 15:36:19.834519 ===================================
2200 15:36:19.837513 ===================================
2201 15:36:19.840902 memory_type:LPDDR4
2202 15:36:19.840986 GP_NUM : 10
2203 15:36:19.844621 SRAM_EN : 1
2204 15:36:19.847510 MD32_EN : 0
2205 15:36:19.851017 ===================================
2206 15:36:19.851121 [ANA_INIT] >>>>>>>>>>>>>>
2207 15:36:19.854241 <<<<<< [CONFIGURE PHASE]: ANA_TX
2208 15:36:19.857477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2209 15:36:19.861371 ===================================
2210 15:36:19.864354 data_rate = 2400,PCW = 0X5b00
2211 15:36:19.867642 ===================================
2212 15:36:19.871539 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2213 15:36:19.878003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 15:36:19.881287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 15:36:19.888100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2216 15:36:19.891214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2217 15:36:19.894763 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2218 15:36:19.894875 [ANA_INIT] flow start
2219 15:36:19.897975 [ANA_INIT] PLL >>>>>>>>
2220 15:36:19.901467 [ANA_INIT] PLL <<<<<<<<
2221 15:36:19.901572 [ANA_INIT] MIDPI >>>>>>>>
2222 15:36:19.904772 [ANA_INIT] MIDPI <<<<<<<<
2223 15:36:19.908344 [ANA_INIT] DLL >>>>>>>>
2224 15:36:19.908447 [ANA_INIT] DLL <<<<<<<<
2225 15:36:19.911385 [ANA_INIT] flow end
2226 15:36:19.914863 ============ LP4 DIFF to SE enter ============
2227 15:36:19.918288 ============ LP4 DIFF to SE exit ============
2228 15:36:19.921371 [ANA_INIT] <<<<<<<<<<<<<
2229 15:36:19.924828 [Flow] Enable top DCM control >>>>>
2230 15:36:19.928371 [Flow] Enable top DCM control <<<<<
2231 15:36:19.931405 Enable DLL master slave shuffle
2232 15:36:19.938034 ==============================================================
2233 15:36:19.938142 Gating Mode config
2234 15:36:19.944561 ==============================================================
2235 15:36:19.944672 Config description:
2236 15:36:19.954764 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2237 15:36:19.961420 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2238 15:36:19.968018 SELPH_MODE 0: By rank 1: By Phase
2239 15:36:19.971670 ==============================================================
2240 15:36:19.974803 GAT_TRACK_EN = 1
2241 15:36:19.978006 RX_GATING_MODE = 2
2242 15:36:19.981697 RX_GATING_TRACK_MODE = 2
2243 15:36:19.984892 SELPH_MODE = 1
2244 15:36:19.988345 PICG_EARLY_EN = 1
2245 15:36:19.991745 VALID_LAT_VALUE = 1
2246 15:36:19.995192 ==============================================================
2247 15:36:19.998449 Enter into Gating configuration >>>>
2248 15:36:20.001658 Exit from Gating configuration <<<<
2249 15:36:20.005286 Enter into DVFS_PRE_config >>>>>
2250 15:36:20.018981 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2251 15:36:20.022064 Exit from DVFS_PRE_config <<<<<
2252 15:36:20.022141 Enter into PICG configuration >>>>
2253 15:36:20.025320 Exit from PICG configuration <<<<
2254 15:36:20.028577 [RX_INPUT] configuration >>>>>
2255 15:36:20.032062 [RX_INPUT] configuration <<<<<
2256 15:36:20.039183 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2257 15:36:20.042325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2258 15:36:20.048631 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 15:36:20.055581 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 15:36:20.062312 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2261 15:36:20.069156 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2262 15:36:20.072563 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2263 15:36:20.075965 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2264 15:36:20.079103 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2265 15:36:20.082427 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2266 15:36:20.089202 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2267 15:36:20.092408 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 15:36:20.095766 ===================================
2269 15:36:20.099014 LPDDR4 DRAM CONFIGURATION
2270 15:36:20.102548 ===================================
2271 15:36:20.102654 EX_ROW_EN[0] = 0x0
2272 15:36:20.106059 EX_ROW_EN[1] = 0x0
2273 15:36:20.106145 LP4Y_EN = 0x0
2274 15:36:20.109066 WORK_FSP = 0x0
2275 15:36:20.109152 WL = 0x4
2276 15:36:20.112590 RL = 0x4
2277 15:36:20.112697 BL = 0x2
2278 15:36:20.116074 RPST = 0x0
2279 15:36:20.116171 RD_PRE = 0x0
2280 15:36:20.118953 WR_PRE = 0x1
2281 15:36:20.119024 WR_PST = 0x0
2282 15:36:20.122729 DBI_WR = 0x0
2283 15:36:20.126005 DBI_RD = 0x0
2284 15:36:20.126093 OTF = 0x1
2285 15:36:20.129038 ===================================
2286 15:36:20.132702 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2287 15:36:20.135961 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2288 15:36:20.142636 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2289 15:36:20.146176 ===================================
2290 15:36:20.146258 LPDDR4 DRAM CONFIGURATION
2291 15:36:20.149400 ===================================
2292 15:36:20.152999 EX_ROW_EN[0] = 0x10
2293 15:36:20.156622 EX_ROW_EN[1] = 0x0
2294 15:36:20.156711 LP4Y_EN = 0x0
2295 15:36:20.160299 WORK_FSP = 0x0
2296 15:36:20.160379 WL = 0x4
2297 15:36:20.162936 RL = 0x4
2298 15:36:20.163017 BL = 0x2
2299 15:36:20.166726 RPST = 0x0
2300 15:36:20.166807 RD_PRE = 0x0
2301 15:36:20.169987 WR_PRE = 0x1
2302 15:36:20.170067 WR_PST = 0x0
2303 15:36:20.173062 DBI_WR = 0x0
2304 15:36:20.173143 DBI_RD = 0x0
2305 15:36:20.176426 OTF = 0x1
2306 15:36:20.179653 ===================================
2307 15:36:20.186741 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2308 15:36:20.186823 ==
2309 15:36:20.189707 Dram Type= 6, Freq= 0, CH_0, rank 0
2310 15:36:20.193216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2311 15:36:20.193298 ==
2312 15:36:20.196547 [Duty_Offset_Calibration]
2313 15:36:20.196627 B0:2 B1:-1 CA:1
2314 15:36:20.196728
2315 15:36:20.199659 [DutyScan_Calibration_Flow] k_type=0
2316 15:36:20.208794
2317 15:36:20.208874 ==CLK 0==
2318 15:36:20.212121 Final CLK duty delay cell = -4
2319 15:36:20.215746 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2320 15:36:20.219122 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2321 15:36:20.222166 [-4] AVG Duty = 4953%(X100)
2322 15:36:20.222247
2323 15:36:20.226018 CH0 CLK Duty spec in!! Max-Min= 156%
2324 15:36:20.228929 [DutyScan_Calibration_Flow] ====Done====
2325 15:36:20.229010
2326 15:36:20.232383 [DutyScan_Calibration_Flow] k_type=1
2327 15:36:20.247762
2328 15:36:20.247842 ==DQS 0 ==
2329 15:36:20.250930 Final DQS duty delay cell = 0
2330 15:36:20.254624 [0] MAX Duty = 5156%(X100), DQS PI = 46
2331 15:36:20.257801 [0] MIN Duty = 5000%(X100), DQS PI = 12
2332 15:36:20.257882 [0] AVG Duty = 5078%(X100)
2333 15:36:20.261065
2334 15:36:20.261144 ==DQS 1 ==
2335 15:36:20.264486 Final DQS duty delay cell = -4
2336 15:36:20.267698 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2337 15:36:20.271448 [-4] MIN Duty = 5000%(X100), DQS PI = 58
2338 15:36:20.274723 [-4] AVG Duty = 5062%(X100)
2339 15:36:20.274803
2340 15:36:20.277791 CH0 DQS 0 Duty spec in!! Max-Min= 156%
2341 15:36:20.277871
2342 15:36:20.281378 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2343 15:36:20.284576 [DutyScan_Calibration_Flow] ====Done====
2344 15:36:20.284687
2345 15:36:20.288206 [DutyScan_Calibration_Flow] k_type=3
2346 15:36:20.304414
2347 15:36:20.304492 ==DQM 0 ==
2348 15:36:20.307838 Final DQM duty delay cell = 0
2349 15:36:20.311112 [0] MAX Duty = 5031%(X100), DQS PI = 56
2350 15:36:20.314656 [0] MIN Duty = 4875%(X100), DQS PI = 2
2351 15:36:20.314725 [0] AVG Duty = 4953%(X100)
2352 15:36:20.314801
2353 15:36:20.318303 ==DQM 1 ==
2354 15:36:20.321224 Final DQM duty delay cell = 0
2355 15:36:20.324596 [0] MAX Duty = 5156%(X100), DQS PI = 62
2356 15:36:20.328337 [0] MIN Duty = 4969%(X100), DQS PI = 10
2357 15:36:20.328433 [0] AVG Duty = 5062%(X100)
2358 15:36:20.328524
2359 15:36:20.331220 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2360 15:36:20.334962
2361 15:36:20.338211 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2362 15:36:20.341453 [DutyScan_Calibration_Flow] ====Done====
2363 15:36:20.341574
2364 15:36:20.344995 [DutyScan_Calibration_Flow] k_type=2
2365 15:36:20.360091
2366 15:36:20.360192 ==DQ 0 ==
2367 15:36:20.363472 Final DQ duty delay cell = -4
2368 15:36:20.366908 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2369 15:36:20.370131 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2370 15:36:20.373574 [-4] AVG Duty = 4969%(X100)
2371 15:36:20.373650
2372 15:36:20.373712 ==DQ 1 ==
2373 15:36:20.376887 Final DQ duty delay cell = 0
2374 15:36:20.380072 [0] MAX Duty = 5031%(X100), DQS PI = 18
2375 15:36:20.383595 [0] MIN Duty = 4907%(X100), DQS PI = 46
2376 15:36:20.383701 [0] AVG Duty = 4969%(X100)
2377 15:36:20.386745
2378 15:36:20.390258 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2379 15:36:20.390354
2380 15:36:20.393728 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2381 15:36:20.397370 [DutyScan_Calibration_Flow] ====Done====
2382 15:36:20.397447 ==
2383 15:36:20.400751 Dram Type= 6, Freq= 0, CH_1, rank 0
2384 15:36:20.403804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2385 15:36:20.403905 ==
2386 15:36:20.407357 [Duty_Offset_Calibration]
2387 15:36:20.407454 B0:1 B1:1 CA:2
2388 15:36:20.407543
2389 15:36:20.410321 [DutyScan_Calibration_Flow] k_type=0
2390 15:36:20.420948
2391 15:36:20.421026 ==CLK 0==
2392 15:36:20.424063 Final CLK duty delay cell = 0
2393 15:36:20.427186 [0] MAX Duty = 5156%(X100), DQS PI = 24
2394 15:36:20.431018 [0] MIN Duty = 4969%(X100), DQS PI = 38
2395 15:36:20.431138 [0] AVG Duty = 5062%(X100)
2396 15:36:20.431232
2397 15:36:20.433890 CH1 CLK Duty spec in!! Max-Min= 187%
2398 15:36:20.440569 [DutyScan_Calibration_Flow] ====Done====
2399 15:36:20.440677
2400 15:36:20.443813 [DutyScan_Calibration_Flow] k_type=1
2401 15:36:20.459960
2402 15:36:20.460064 ==DQS 0 ==
2403 15:36:20.463445 Final DQS duty delay cell = 0
2404 15:36:20.466679 [0] MAX Duty = 5031%(X100), DQS PI = 18
2405 15:36:20.470009 [0] MIN Duty = 4813%(X100), DQS PI = 50
2406 15:36:20.470117 [0] AVG Duty = 4922%(X100)
2407 15:36:20.473130
2408 15:36:20.473201 ==DQS 1 ==
2409 15:36:20.476429 Final DQS duty delay cell = 0
2410 15:36:20.479768 [0] MAX Duty = 5062%(X100), DQS PI = 36
2411 15:36:20.483124 [0] MIN Duty = 4907%(X100), DQS PI = 16
2412 15:36:20.483205 [0] AVG Duty = 4984%(X100)
2413 15:36:20.486391
2414 15:36:20.490138 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2415 15:36:20.490219
2416 15:36:20.493436 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2417 15:36:20.497038 [DutyScan_Calibration_Flow] ====Done====
2418 15:36:20.497119
2419 15:36:20.500189 [DutyScan_Calibration_Flow] k_type=3
2420 15:36:20.516658
2421 15:36:20.516764 ==DQM 0 ==
2422 15:36:20.519729 Final DQM duty delay cell = 0
2423 15:36:20.522995 [0] MAX Duty = 5093%(X100), DQS PI = 18
2424 15:36:20.526536 [0] MIN Duty = 4907%(X100), DQS PI = 48
2425 15:36:20.526620 [0] AVG Duty = 5000%(X100)
2426 15:36:20.529625
2427 15:36:20.529706 ==DQM 1 ==
2428 15:36:20.533587 Final DQM duty delay cell = 0
2429 15:36:20.536563 [0] MAX Duty = 5125%(X100), DQS PI = 0
2430 15:36:20.539998 [0] MIN Duty = 4938%(X100), DQS PI = 24
2431 15:36:20.540080 [0] AVG Duty = 5031%(X100)
2432 15:36:20.540144
2433 15:36:20.546629 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2434 15:36:20.546711
2435 15:36:20.550078 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2436 15:36:20.553283 [DutyScan_Calibration_Flow] ====Done====
2437 15:36:20.553365
2438 15:36:20.556488 [DutyScan_Calibration_Flow] k_type=2
2439 15:36:20.572227
2440 15:36:20.572309 ==DQ 0 ==
2441 15:36:20.575359 Final DQ duty delay cell = 0
2442 15:36:20.578656 [0] MAX Duty = 5156%(X100), DQS PI = 18
2443 15:36:20.581920 [0] MIN Duty = 4938%(X100), DQS PI = 50
2444 15:36:20.582005 [0] AVG Duty = 5047%(X100)
2445 15:36:20.582070
2446 15:36:20.585655 ==DQ 1 ==
2447 15:36:20.588803 Final DQ duty delay cell = -4
2448 15:36:20.592318 [-4] MAX Duty = 4969%(X100), DQS PI = 10
2449 15:36:20.595523 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2450 15:36:20.595606 [-4] AVG Duty = 4938%(X100)
2451 15:36:20.595671
2452 15:36:20.598722 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2453 15:36:20.602526
2454 15:36:20.606257 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2455 15:36:20.608881 [DutyScan_Calibration_Flow] ====Done====
2456 15:36:20.612503 nWR fixed to 30
2457 15:36:20.612617 [ModeRegInit_LP4] CH0 RK0
2458 15:36:20.615684 [ModeRegInit_LP4] CH0 RK1
2459 15:36:20.618972 [ModeRegInit_LP4] CH1 RK0
2460 15:36:20.619055 [ModeRegInit_LP4] CH1 RK1
2461 15:36:20.622824 match AC timing 7
2462 15:36:20.625670 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2463 15:36:20.628803 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2464 15:36:20.636060 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2465 15:36:20.639202 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2466 15:36:20.645751 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2467 15:36:20.645836 ==
2468 15:36:20.649113 Dram Type= 6, Freq= 0, CH_0, rank 0
2469 15:36:20.653072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 15:36:20.653160 ==
2471 15:36:20.659667 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 15:36:20.662334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 15:36:20.672182 [CA 0] Center 40 (10~71) winsize 62
2474 15:36:20.675826 [CA 1] Center 39 (9~70) winsize 62
2475 15:36:20.679043 [CA 2] Center 36 (6~67) winsize 62
2476 15:36:20.682465 [CA 3] Center 36 (6~66) winsize 61
2477 15:36:20.685890 [CA 4] Center 34 (4~65) winsize 62
2478 15:36:20.689359 [CA 5] Center 34 (4~64) winsize 61
2479 15:36:20.689440
2480 15:36:20.692785 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2481 15:36:20.692881
2482 15:36:20.695653 [CATrainingPosCal] consider 1 rank data
2483 15:36:20.699387 u2DelayCellTimex100 = 270/100 ps
2484 15:36:20.702552 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2485 15:36:20.705573 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2486 15:36:20.713005 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2487 15:36:20.716018 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2488 15:36:20.719278 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2489 15:36:20.722584 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2490 15:36:20.722682
2491 15:36:20.726218 CA PerBit enable=1, Macro0, CA PI delay=34
2492 15:36:20.726299
2493 15:36:20.729527 [CBTSetCACLKResult] CA Dly = 34
2494 15:36:20.729609 CS Dly: 7 (0~38)
2495 15:36:20.729673 ==
2496 15:36:20.732765 Dram Type= 6, Freq= 0, CH_0, rank 1
2497 15:36:20.739885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 15:36:20.739971 ==
2499 15:36:20.743048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2500 15:36:20.749469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2501 15:36:20.758319 [CA 0] Center 39 (9~70) winsize 62
2502 15:36:20.761561 [CA 1] Center 39 (9~70) winsize 62
2503 15:36:20.764894 [CA 2] Center 36 (6~67) winsize 62
2504 15:36:20.768403 [CA 3] Center 35 (5~66) winsize 62
2505 15:36:20.771487 [CA 4] Center 34 (4~65) winsize 62
2506 15:36:20.775335 [CA 5] Center 34 (4~64) winsize 61
2507 15:36:20.775416
2508 15:36:20.779063 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2509 15:36:20.779147
2510 15:36:20.782134 [CATrainingPosCal] consider 2 rank data
2511 15:36:20.785296 u2DelayCellTimex100 = 270/100 ps
2512 15:36:20.788488 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2513 15:36:20.791749 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2514 15:36:20.795274 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2515 15:36:20.802245 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2516 15:36:20.805373 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2517 15:36:20.809086 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2518 15:36:20.809168
2519 15:36:20.812191 CA PerBit enable=1, Macro0, CA PI delay=34
2520 15:36:20.812272
2521 15:36:20.815552 [CBTSetCACLKResult] CA Dly = 34
2522 15:36:20.815635 CS Dly: 8 (0~41)
2523 15:36:20.815700
2524 15:36:20.819191 ----->DramcWriteLeveling(PI) begin...
2525 15:36:20.819307 ==
2526 15:36:20.822703 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 15:36:20.829245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 15:36:20.829330 ==
2529 15:36:20.832657 Write leveling (Byte 0): 32 => 32
2530 15:36:20.832764 Write leveling (Byte 1): 29 => 29
2531 15:36:20.835668 DramcWriteLeveling(PI) end<-----
2532 15:36:20.835763
2533 15:36:20.835827 ==
2534 15:36:20.838988 Dram Type= 6, Freq= 0, CH_0, rank 0
2535 15:36:20.845831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 15:36:20.845914 ==
2537 15:36:20.848836 [Gating] SW mode calibration
2538 15:36:20.855520 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2539 15:36:20.858766 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2540 15:36:20.865994 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 15:36:20.869529 0 15 4 | B1->B0 | 2322 2f2f | 1 0 | (0 0) (0 0)
2542 15:36:20.872336 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 15:36:20.876054 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 15:36:20.882301 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 15:36:20.886117 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 15:36:20.889198 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 15:36:20.895976 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2548 15:36:20.899362 1 0 0 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
2549 15:36:20.902889 1 0 4 | B1->B0 | 2525 2323 | 1 0 | (1 0) (1 0)
2550 15:36:20.909327 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 15:36:20.912570 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 15:36:20.916044 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 15:36:20.923000 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 15:36:20.925996 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 15:36:20.929889 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 15:36:20.936166 1 1 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2557 15:36:20.939356 1 1 4 | B1->B0 | 3e3e 4545 | 1 0 | (0 0) (0 0)
2558 15:36:20.942861 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 15:36:20.946002 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 15:36:20.953045 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 15:36:20.956076 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 15:36:20.959830 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 15:36:20.966465 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 15:36:20.970105 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2565 15:36:20.972991 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2566 15:36:20.979916 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 15:36:20.983086 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 15:36:20.986410 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 15:36:20.993394 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 15:36:20.996818 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 15:36:20.999778 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 15:36:21.003145 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 15:36:21.010410 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 15:36:21.013367 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 15:36:21.016505 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 15:36:21.023263 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 15:36:21.026773 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 15:36:21.030483 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 15:36:21.036996 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 15:36:21.040488 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2581 15:36:21.043349 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2582 15:36:21.047310 Total UI for P1: 0, mck2ui 16
2583 15:36:21.050399 best dqsien dly found for B0: ( 1, 4, 0)
2584 15:36:21.053460 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 15:36:21.056959 Total UI for P1: 0, mck2ui 16
2586 15:36:21.060422 best dqsien dly found for B1: ( 1, 4, 2)
2587 15:36:21.064024 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2588 15:36:21.067154 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2589 15:36:21.067252
2590 15:36:21.073754 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2591 15:36:21.077176 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2592 15:36:21.077259 [Gating] SW calibration Done
2593 15:36:21.080304 ==
2594 15:36:21.084354 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 15:36:21.087375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 15:36:21.087459 ==
2597 15:36:21.087525 RX Vref Scan: 0
2598 15:36:21.087586
2599 15:36:21.090495 RX Vref 0 -> 0, step: 1
2600 15:36:21.090579
2601 15:36:21.094095 RX Delay -40 -> 252, step: 8
2602 15:36:21.097114 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2603 15:36:21.101029 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2604 15:36:21.103923 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2605 15:36:21.110889 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2606 15:36:21.114387 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2607 15:36:21.117295 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2608 15:36:21.121092 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2609 15:36:21.124616 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2610 15:36:21.127524 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2611 15:36:21.134364 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2612 15:36:21.138003 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2613 15:36:21.140953 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2614 15:36:21.144332 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2615 15:36:21.147370 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2616 15:36:21.153946 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2617 15:36:21.157502 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2618 15:36:21.157586 ==
2619 15:36:21.160821 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 15:36:21.164267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 15:36:21.164351 ==
2622 15:36:21.167651 DQS Delay:
2623 15:36:21.167735 DQS0 = 0, DQS1 = 0
2624 15:36:21.167800 DQM Delay:
2625 15:36:21.170855 DQM0 = 115, DQM1 = 107
2626 15:36:21.170938 DQ Delay:
2627 15:36:21.174724 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2628 15:36:21.177984 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2629 15:36:21.181024 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2630 15:36:21.187799 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2631 15:36:21.187906
2632 15:36:21.188007
2633 15:36:21.188095 ==
2634 15:36:21.191276 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 15:36:21.194736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 15:36:21.194817 ==
2637 15:36:21.194913
2638 15:36:21.195001
2639 15:36:21.197902 TX Vref Scan disable
2640 15:36:21.198004 == TX Byte 0 ==
2641 15:36:21.205051 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2642 15:36:21.207744 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2643 15:36:21.207840 == TX Byte 1 ==
2644 15:36:21.214677 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2645 15:36:21.218022 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2646 15:36:21.218113 ==
2647 15:36:21.221329 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 15:36:21.224988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 15:36:21.225070 ==
2650 15:36:21.237142 TX Vref=22, minBit 1, minWin=25, winSum=420
2651 15:36:21.240447 TX Vref=24, minBit 0, minWin=26, winSum=425
2652 15:36:21.243801 TX Vref=26, minBit 0, minWin=26, winSum=426
2653 15:36:21.247036 TX Vref=28, minBit 1, minWin=26, winSum=434
2654 15:36:21.250504 TX Vref=30, minBit 1, minWin=26, winSum=435
2655 15:36:21.253764 TX Vref=32, minBit 0, minWin=26, winSum=434
2656 15:36:21.260943 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 30
2657 15:36:21.261030
2658 15:36:21.263844 Final TX Range 1 Vref 30
2659 15:36:21.263926
2660 15:36:21.263990 ==
2661 15:36:21.267478 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 15:36:21.271129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 15:36:21.271211 ==
2664 15:36:21.271275
2665 15:36:21.271334
2666 15:36:21.273875 TX Vref Scan disable
2667 15:36:21.277801 == TX Byte 0 ==
2668 15:36:21.280822 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2669 15:36:21.283841 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2670 15:36:21.287187 == TX Byte 1 ==
2671 15:36:21.290740 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2672 15:36:21.293896 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2673 15:36:21.293980
2674 15:36:21.297490 [DATLAT]
2675 15:36:21.297571 Freq=1200, CH0 RK0
2676 15:36:21.297635
2677 15:36:21.300605 DATLAT Default: 0xd
2678 15:36:21.300728 0, 0xFFFF, sum = 0
2679 15:36:21.304308 1, 0xFFFF, sum = 0
2680 15:36:21.304391 2, 0xFFFF, sum = 0
2681 15:36:21.307389 3, 0xFFFF, sum = 0
2682 15:36:21.307472 4, 0xFFFF, sum = 0
2683 15:36:21.310849 5, 0xFFFF, sum = 0
2684 15:36:21.310931 6, 0xFFFF, sum = 0
2685 15:36:21.314396 7, 0xFFFF, sum = 0
2686 15:36:21.314478 8, 0xFFFF, sum = 0
2687 15:36:21.317607 9, 0xFFFF, sum = 0
2688 15:36:21.317690 10, 0xFFFF, sum = 0
2689 15:36:21.321156 11, 0xFFFF, sum = 0
2690 15:36:21.321254 12, 0x0, sum = 1
2691 15:36:21.324393 13, 0x0, sum = 2
2692 15:36:21.324476 14, 0x0, sum = 3
2693 15:36:21.327806 15, 0x0, sum = 4
2694 15:36:21.327889 best_step = 13
2695 15:36:21.327953
2696 15:36:21.328013 ==
2697 15:36:21.331402 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 15:36:21.334583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 15:36:21.337626 ==
2700 15:36:21.337708 RX Vref Scan: 1
2701 15:36:21.337772
2702 15:36:21.340995 Set Vref Range= 32 -> 127
2703 15:36:21.341096
2704 15:36:21.344751 RX Vref 32 -> 127, step: 1
2705 15:36:21.344848
2706 15:36:21.344911 RX Delay -21 -> 252, step: 4
2707 15:36:21.344971
2708 15:36:21.347887 Set Vref, RX VrefLevel [Byte0]: 32
2709 15:36:21.351211 [Byte1]: 32
2710 15:36:21.355084
2711 15:36:21.355165 Set Vref, RX VrefLevel [Byte0]: 33
2712 15:36:21.358466 [Byte1]: 33
2713 15:36:21.363033
2714 15:36:21.363114 Set Vref, RX VrefLevel [Byte0]: 34
2715 15:36:21.366290 [Byte1]: 34
2716 15:36:21.370892
2717 15:36:21.370973 Set Vref, RX VrefLevel [Byte0]: 35
2718 15:36:21.374239 [Byte1]: 35
2719 15:36:21.378871
2720 15:36:21.378952 Set Vref, RX VrefLevel [Byte0]: 36
2721 15:36:21.382739 [Byte1]: 36
2722 15:36:21.387261
2723 15:36:21.387342 Set Vref, RX VrefLevel [Byte0]: 37
2724 15:36:21.390126 [Byte1]: 37
2725 15:36:21.395137
2726 15:36:21.395232 Set Vref, RX VrefLevel [Byte0]: 38
2727 15:36:21.398353 [Byte1]: 38
2728 15:36:21.402732
2729 15:36:21.402813 Set Vref, RX VrefLevel [Byte0]: 39
2730 15:36:21.406367 [Byte1]: 39
2731 15:36:21.411171
2732 15:36:21.411272 Set Vref, RX VrefLevel [Byte0]: 40
2733 15:36:21.414109 [Byte1]: 40
2734 15:36:21.419006
2735 15:36:21.419088 Set Vref, RX VrefLevel [Byte0]: 41
2736 15:36:21.422199 [Byte1]: 41
2737 15:36:21.426480
2738 15:36:21.426561 Set Vref, RX VrefLevel [Byte0]: 42
2739 15:36:21.430192 [Byte1]: 42
2740 15:36:21.434632
2741 15:36:21.434714 Set Vref, RX VrefLevel [Byte0]: 43
2742 15:36:21.438114 [Byte1]: 43
2743 15:36:21.442234
2744 15:36:21.442315 Set Vref, RX VrefLevel [Byte0]: 44
2745 15:36:21.445841 [Byte1]: 44
2746 15:36:21.450167
2747 15:36:21.450248 Set Vref, RX VrefLevel [Byte0]: 45
2748 15:36:21.453713 [Byte1]: 45
2749 15:36:21.458623
2750 15:36:21.458704 Set Vref, RX VrefLevel [Byte0]: 46
2751 15:36:21.461596 [Byte1]: 46
2752 15:36:21.466171
2753 15:36:21.466252 Set Vref, RX VrefLevel [Byte0]: 47
2754 15:36:21.469359 [Byte1]: 47
2755 15:36:21.473980
2756 15:36:21.474061 Set Vref, RX VrefLevel [Byte0]: 48
2757 15:36:21.477386 [Byte1]: 48
2758 15:36:21.482205
2759 15:36:21.482286 Set Vref, RX VrefLevel [Byte0]: 49
2760 15:36:21.485281 [Byte1]: 49
2761 15:36:21.490322
2762 15:36:21.490419 Set Vref, RX VrefLevel [Byte0]: 50
2763 15:36:21.493963 [Byte1]: 50
2764 15:36:21.497997
2765 15:36:21.498069 Set Vref, RX VrefLevel [Byte0]: 51
2766 15:36:21.501380 [Byte1]: 51
2767 15:36:21.505913
2768 15:36:21.505988 Set Vref, RX VrefLevel [Byte0]: 52
2769 15:36:21.508988 [Byte1]: 52
2770 15:36:21.513645
2771 15:36:21.513728 Set Vref, RX VrefLevel [Byte0]: 53
2772 15:36:21.516906 [Byte1]: 53
2773 15:36:21.521797
2774 15:36:21.521878 Set Vref, RX VrefLevel [Byte0]: 54
2775 15:36:21.524918 [Byte1]: 54
2776 15:36:21.529491
2777 15:36:21.529573 Set Vref, RX VrefLevel [Byte0]: 55
2778 15:36:21.533379 [Byte1]: 55
2779 15:36:21.537697
2780 15:36:21.537780 Set Vref, RX VrefLevel [Byte0]: 56
2781 15:36:21.541483 [Byte1]: 56
2782 15:36:21.545445
2783 15:36:21.545526 Set Vref, RX VrefLevel [Byte0]: 57
2784 15:36:21.549006 [Byte1]: 57
2785 15:36:21.553647
2786 15:36:21.553725 Set Vref, RX VrefLevel [Byte0]: 58
2787 15:36:21.556977 [Byte1]: 58
2788 15:36:21.561499
2789 15:36:21.561598 Set Vref, RX VrefLevel [Byte0]: 59
2790 15:36:21.564428 [Byte1]: 59
2791 15:36:21.569285
2792 15:36:21.569361 Set Vref, RX VrefLevel [Byte0]: 60
2793 15:36:21.572799 [Byte1]: 60
2794 15:36:21.577264
2795 15:36:21.577349 Set Vref, RX VrefLevel [Byte0]: 61
2796 15:36:21.580268 [Byte1]: 61
2797 15:36:21.585315
2798 15:36:21.585411 Set Vref, RX VrefLevel [Byte0]: 62
2799 15:36:21.588270 [Byte1]: 62
2800 15:36:21.593048
2801 15:36:21.593152 Set Vref, RX VrefLevel [Byte0]: 63
2802 15:36:21.596724 [Byte1]: 63
2803 15:36:21.601084
2804 15:36:21.601160 Set Vref, RX VrefLevel [Byte0]: 64
2805 15:36:21.604154 [Byte1]: 64
2806 15:36:21.608697
2807 15:36:21.608798 Set Vref, RX VrefLevel [Byte0]: 65
2808 15:36:21.612092 [Byte1]: 65
2809 15:36:21.616662
2810 15:36:21.616752 Set Vref, RX VrefLevel [Byte0]: 66
2811 15:36:21.619947 [Byte1]: 66
2812 15:36:21.624777
2813 15:36:21.624859 Set Vref, RX VrefLevel [Byte0]: 67
2814 15:36:21.628138 [Byte1]: 67
2815 15:36:21.633365
2816 15:36:21.633445 Final RX Vref Byte 0 = 53 to rank0
2817 15:36:21.636134 Final RX Vref Byte 1 = 50 to rank0
2818 15:36:21.640134 Final RX Vref Byte 0 = 53 to rank1
2819 15:36:21.642747 Final RX Vref Byte 1 = 50 to rank1==
2820 15:36:21.646415 Dram Type= 6, Freq= 0, CH_0, rank 0
2821 15:36:21.649560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 15:36:21.653290 ==
2823 15:36:21.653365 DQS Delay:
2824 15:36:21.653435 DQS0 = 0, DQS1 = 0
2825 15:36:21.656178 DQM Delay:
2826 15:36:21.656244 DQM0 = 115, DQM1 = 105
2827 15:36:21.659928 DQ Delay:
2828 15:36:21.662926 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =112
2829 15:36:21.666154 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2830 15:36:21.669601 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
2831 15:36:21.673210 DQ12 =114, DQ13 =110, DQ14 =120, DQ15 =114
2832 15:36:21.673285
2833 15:36:21.673356
2834 15:36:21.679625 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2835 15:36:21.683091 CH0 RK0: MR19=303, MR18=FEED
2836 15:36:21.689954 CH0_RK0: MR19=0x303, MR18=0xFEED, DQSOSC=410, MR23=63, INC=39, DEC=26
2837 15:36:21.690031
2838 15:36:21.693196 ----->DramcWriteLeveling(PI) begin...
2839 15:36:21.693273 ==
2840 15:36:21.696604 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 15:36:21.699755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 15:36:21.699829 ==
2843 15:36:21.703137 Write leveling (Byte 0): 33 => 33
2844 15:36:21.706407 Write leveling (Byte 1): 29 => 29
2845 15:36:21.709946 DramcWriteLeveling(PI) end<-----
2846 15:36:21.710047
2847 15:36:21.710113 ==
2848 15:36:21.713593 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 15:36:21.716594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 15:36:21.716700 ==
2851 15:36:21.720520 [Gating] SW mode calibration
2852 15:36:21.726499 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2853 15:36:21.733353 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2854 15:36:21.736513 0 15 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
2855 15:36:21.743614 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2856 15:36:21.746688 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 15:36:21.749989 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 15:36:21.753754 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 15:36:21.760159 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 15:36:21.763918 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2861 15:36:21.767030 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2862 15:36:21.773797 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2863 15:36:21.777228 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 15:36:21.780153 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 15:36:21.787049 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 15:36:21.790462 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 15:36:21.793849 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 15:36:21.800358 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2869 15:36:21.803952 1 0 28 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
2870 15:36:21.807128 1 1 0 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
2871 15:36:21.810386 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 15:36:21.817274 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 15:36:21.820911 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 15:36:21.824451 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 15:36:21.830885 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 15:36:21.834045 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2877 15:36:21.837317 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2878 15:36:21.844345 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2879 15:36:21.847576 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 15:36:21.850862 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 15:36:21.857659 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 15:36:21.861618 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 15:36:21.864690 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 15:36:21.867973 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 15:36:21.874220 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 15:36:21.877650 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 15:36:21.881196 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 15:36:21.888165 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 15:36:21.891359 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 15:36:21.894404 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 15:36:21.901611 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 15:36:21.904912 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2893 15:36:21.907893 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2894 15:36:21.914808 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2895 15:36:21.914924 Total UI for P1: 0, mck2ui 16
2896 15:36:21.917995 best dqsien dly found for B0: ( 1, 3, 26)
2897 15:36:21.925112 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 15:36:21.928634 Total UI for P1: 0, mck2ui 16
2899 15:36:21.931567 best dqsien dly found for B1: ( 1, 4, 0)
2900 15:36:21.934929 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2901 15:36:21.937976 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2902 15:36:21.938055
2903 15:36:21.941474 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2904 15:36:21.944911 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2905 15:36:21.948126 [Gating] SW calibration Done
2906 15:36:21.948201 ==
2907 15:36:21.951513 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 15:36:21.955073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 15:36:21.955173 ==
2910 15:36:21.958432 RX Vref Scan: 0
2911 15:36:21.958512
2912 15:36:21.958576 RX Vref 0 -> 0, step: 1
2913 15:36:21.958636
2914 15:36:21.961720 RX Delay -40 -> 252, step: 8
2915 15:36:21.965036 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2916 15:36:21.972043 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2917 15:36:21.975281 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2918 15:36:21.978431 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2919 15:36:21.981821 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2920 15:36:21.985046 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2921 15:36:21.988596 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2922 15:36:21.995302 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2923 15:36:21.998510 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2924 15:36:22.002631 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2925 15:36:22.005285 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2926 15:36:22.008583 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2927 15:36:22.015513 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2928 15:36:22.018834 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2929 15:36:22.022136 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2930 15:36:22.025669 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2931 15:36:22.025757 ==
2932 15:36:22.028865 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 15:36:22.032464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 15:36:22.035497 ==
2935 15:36:22.035572 DQS Delay:
2936 15:36:22.035636 DQS0 = 0, DQS1 = 0
2937 15:36:22.039031 DQM Delay:
2938 15:36:22.039103 DQM0 = 115, DQM1 = 105
2939 15:36:22.042521 DQ Delay:
2940 15:36:22.045753 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2941 15:36:22.049224 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2942 15:36:22.052243 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =95
2943 15:36:22.055526 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2944 15:36:22.055601
2945 15:36:22.055664
2946 15:36:22.055723 ==
2947 15:36:22.059047 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 15:36:22.062483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 15:36:22.062557 ==
2950 15:36:22.062627
2951 15:36:22.062687
2952 15:36:22.065808 TX Vref Scan disable
2953 15:36:22.069070 == TX Byte 0 ==
2954 15:36:22.072524 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2955 15:36:22.075736 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2956 15:36:22.079661 == TX Byte 1 ==
2957 15:36:22.082647 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2958 15:36:22.085844 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2959 15:36:22.085925 ==
2960 15:36:22.089312 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 15:36:22.092597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 15:36:22.092741 ==
2963 15:36:22.106359 TX Vref=22, minBit 3, minWin=25, winSum=425
2964 15:36:22.109613 TX Vref=24, minBit 1, minWin=25, winSum=425
2965 15:36:22.112532 TX Vref=26, minBit 0, minWin=26, winSum=430
2966 15:36:22.116204 TX Vref=28, minBit 0, minWin=26, winSum=434
2967 15:36:22.119418 TX Vref=30, minBit 3, minWin=26, winSum=434
2968 15:36:22.122963 TX Vref=32, minBit 3, minWin=26, winSum=433
2969 15:36:22.129505 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 28
2970 15:36:22.129591
2971 15:36:22.132928 Final TX Range 1 Vref 28
2972 15:36:22.133009
2973 15:36:22.133081 ==
2974 15:36:22.136217 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 15:36:22.139964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 15:36:22.140039 ==
2977 15:36:22.140110
2978 15:36:22.140171
2979 15:36:22.143180 TX Vref Scan disable
2980 15:36:22.146610 == TX Byte 0 ==
2981 15:36:22.149848 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2982 15:36:22.153412 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2983 15:36:22.156554 == TX Byte 1 ==
2984 15:36:22.160032 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2985 15:36:22.162995 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2986 15:36:22.163072
2987 15:36:22.167000 [DATLAT]
2988 15:36:22.167075 Freq=1200, CH0 RK1
2989 15:36:22.167137
2990 15:36:22.169754 DATLAT Default: 0xd
2991 15:36:22.169826 0, 0xFFFF, sum = 0
2992 15:36:22.173134 1, 0xFFFF, sum = 0
2993 15:36:22.173208 2, 0xFFFF, sum = 0
2994 15:36:22.176751 3, 0xFFFF, sum = 0
2995 15:36:22.176834 4, 0xFFFF, sum = 0
2996 15:36:22.180587 5, 0xFFFF, sum = 0
2997 15:36:22.180711 6, 0xFFFF, sum = 0
2998 15:36:22.183548 7, 0xFFFF, sum = 0
2999 15:36:22.183621 8, 0xFFFF, sum = 0
3000 15:36:22.187025 9, 0xFFFF, sum = 0
3001 15:36:22.187096 10, 0xFFFF, sum = 0
3002 15:36:22.190416 11, 0xFFFF, sum = 0
3003 15:36:22.190493 12, 0x0, sum = 1
3004 15:36:22.194067 13, 0x0, sum = 2
3005 15:36:22.194143 14, 0x0, sum = 3
3006 15:36:22.197095 15, 0x0, sum = 4
3007 15:36:22.197207 best_step = 13
3008 15:36:22.197313
3009 15:36:22.197402 ==
3010 15:36:22.200019 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 15:36:22.203740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 15:36:22.207006 ==
3013 15:36:22.207079 RX Vref Scan: 0
3014 15:36:22.207141
3015 15:36:22.210272 RX Vref 0 -> 0, step: 1
3016 15:36:22.210344
3017 15:36:22.210411 RX Delay -21 -> 252, step: 4
3018 15:36:22.217973 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3019 15:36:22.221381 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3020 15:36:22.224649 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3021 15:36:22.228361 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3022 15:36:22.231482 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3023 15:36:22.238334 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3024 15:36:22.241763 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3025 15:36:22.245293 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3026 15:36:22.248185 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3027 15:36:22.252150 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3028 15:36:22.258622 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3029 15:36:22.261392 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3030 15:36:22.264821 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3031 15:36:22.268385 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3032 15:36:22.271833 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3033 15:36:22.274956 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3034 15:36:22.278604 ==
3035 15:36:22.281606 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 15:36:22.285298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 15:36:22.285376 ==
3038 15:36:22.285440 DQS Delay:
3039 15:36:22.288442 DQS0 = 0, DQS1 = 0
3040 15:36:22.288519 DQM Delay:
3041 15:36:22.291734 DQM0 = 114, DQM1 = 104
3042 15:36:22.291806 DQ Delay:
3043 15:36:22.294998 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3044 15:36:22.298873 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3045 15:36:22.302168 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3046 15:36:22.305104 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3047 15:36:22.305195
3048 15:36:22.305267
3049 15:36:22.315618 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3050 15:36:22.315724 CH0 RK1: MR19=403, MR18=4F5
3051 15:36:22.321812 CH0_RK1: MR19=0x403, MR18=0x4F5, DQSOSC=408, MR23=63, INC=39, DEC=26
3052 15:36:22.325436 [RxdqsGatingPostProcess] freq 1200
3053 15:36:22.332332 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3054 15:36:22.335182 best DQS0 dly(2T, 0.5T) = (0, 12)
3055 15:36:22.338560 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 15:36:22.341888 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3057 15:36:22.341965 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 15:36:22.345551 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 15:36:22.348917 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 15:36:22.352334 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 15:36:22.355773 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 15:36:22.358816 Pre-setting of DQS Precalculation
3063 15:36:22.365554 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3064 15:36:22.365659 ==
3065 15:36:22.368837 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 15:36:22.372120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 15:36:22.372194 ==
3068 15:36:22.376018 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3069 15:36:22.382503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3070 15:36:22.391466 [CA 0] Center 38 (8~68) winsize 61
3071 15:36:22.395219 [CA 1] Center 38 (8~68) winsize 61
3072 15:36:22.398369 [CA 2] Center 35 (5~65) winsize 61
3073 15:36:22.402024 [CA 3] Center 34 (4~65) winsize 62
3074 15:36:22.405149 [CA 4] Center 34 (4~65) winsize 62
3075 15:36:22.409098 [CA 5] Center 34 (4~64) winsize 61
3076 15:36:22.409171
3077 15:36:22.411911 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3078 15:36:22.411985
3079 15:36:22.415125 [CATrainingPosCal] consider 1 rank data
3080 15:36:22.418605 u2DelayCellTimex100 = 270/100 ps
3081 15:36:22.421861 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3082 15:36:22.424929 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3083 15:36:22.428284 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3084 15:36:22.435057 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3085 15:36:22.438501 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3086 15:36:22.441746 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3087 15:36:22.441820
3088 15:36:22.445121 CA PerBit enable=1, Macro0, CA PI delay=34
3089 15:36:22.445191
3090 15:36:22.448589 [CBTSetCACLKResult] CA Dly = 34
3091 15:36:22.448712 CS Dly: 6 (0~37)
3092 15:36:22.448779 ==
3093 15:36:22.451905 Dram Type= 6, Freq= 0, CH_1, rank 1
3094 15:36:22.455377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 15:36:22.458770 ==
3096 15:36:22.462398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3097 15:36:22.468867 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3098 15:36:22.477224 [CA 0] Center 38 (8~68) winsize 61
3099 15:36:22.480314 [CA 1] Center 38 (9~68) winsize 60
3100 15:36:22.483751 [CA 2] Center 34 (4~65) winsize 62
3101 15:36:22.487021 [CA 3] Center 34 (4~65) winsize 62
3102 15:36:22.490775 [CA 4] Center 34 (4~65) winsize 62
3103 15:36:22.494081 [CA 5] Center 33 (3~63) winsize 61
3104 15:36:22.494152
3105 15:36:22.497544 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3106 15:36:22.497615
3107 15:36:22.500964 [CATrainingPosCal] consider 2 rank data
3108 15:36:22.503740 u2DelayCellTimex100 = 270/100 ps
3109 15:36:22.507148 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3110 15:36:22.511038 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3111 15:36:22.514461 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3112 15:36:22.520872 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3113 15:36:22.524267 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3114 15:36:22.527488 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3115 15:36:22.527572
3116 15:36:22.530957 CA PerBit enable=1, Macro0, CA PI delay=33
3117 15:36:22.531056
3118 15:36:22.534145 [CBTSetCACLKResult] CA Dly = 33
3119 15:36:22.534220 CS Dly: 7 (0~40)
3120 15:36:22.534281
3121 15:36:22.537461 ----->DramcWriteLeveling(PI) begin...
3122 15:36:22.537535 ==
3123 15:36:22.541005 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 15:36:22.547837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 15:36:22.547912 ==
3126 15:36:22.551116 Write leveling (Byte 0): 27 => 27
3127 15:36:22.551188 Write leveling (Byte 1): 29 => 29
3128 15:36:22.554377 DramcWriteLeveling(PI) end<-----
3129 15:36:22.554448
3130 15:36:22.554507 ==
3131 15:36:22.557580 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 15:36:22.564250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 15:36:22.564329 ==
3134 15:36:22.567455 [Gating] SW mode calibration
3135 15:36:22.574349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3136 15:36:22.577803 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3137 15:36:22.584577 0 15 0 | B1->B0 | 2828 2424 | 1 1 | (0 0) (0 0)
3138 15:36:22.587656 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 15:36:22.591290 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 15:36:22.594617 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 15:36:22.601193 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 15:36:22.604505 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 15:36:22.607956 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 15:36:22.614895 0 15 28 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
3145 15:36:22.618200 1 0 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3146 15:36:22.621931 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 15:36:22.629030 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3148 15:36:22.631510 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 15:36:22.634893 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 15:36:22.641302 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 15:36:22.645026 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 15:36:22.648374 1 0 28 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (0 0)
3153 15:36:22.651865 1 1 0 | B1->B0 | 4242 3131 | 0 0 | (0 0) (0 0)
3154 15:36:22.658717 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 15:36:22.662183 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 15:36:22.665740 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 15:36:22.672061 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 15:36:22.675278 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 15:36:22.678683 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 15:36:22.685453 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 15:36:22.688580 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 15:36:22.691841 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 15:36:22.698996 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 15:36:22.702136 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 15:36:22.705642 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 15:36:22.708824 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 15:36:22.715806 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 15:36:22.719293 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 15:36:22.722204 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 15:36:22.728906 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 15:36:22.732295 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 15:36:22.735950 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 15:36:22.742715 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 15:36:22.745950 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 15:36:22.749040 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 15:36:22.756022 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3177 15:36:22.759463 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3178 15:36:22.762533 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 15:36:22.766037 Total UI for P1: 0, mck2ui 16
3180 15:36:22.769785 best dqsien dly found for B0: ( 1, 3, 30)
3181 15:36:22.772780 Total UI for P1: 0, mck2ui 16
3182 15:36:22.776092 best dqsien dly found for B1: ( 1, 3, 30)
3183 15:36:22.779937 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3184 15:36:22.782771 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3185 15:36:22.782855
3186 15:36:22.785990 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3187 15:36:22.789280 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3188 15:36:22.792841 [Gating] SW calibration Done
3189 15:36:22.792925 ==
3190 15:36:22.796444 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 15:36:22.799841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 15:36:22.802915 ==
3193 15:36:22.802988 RX Vref Scan: 0
3194 15:36:22.803050
3195 15:36:22.806238 RX Vref 0 -> 0, step: 1
3196 15:36:22.806323
3197 15:36:22.809449 RX Delay -40 -> 252, step: 8
3198 15:36:22.813095 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3199 15:36:22.816271 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3200 15:36:22.820233 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3201 15:36:22.823360 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3202 15:36:22.826176 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3203 15:36:22.833238 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3204 15:36:22.836490 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3205 15:36:22.840002 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3206 15:36:22.843778 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3207 15:36:22.846601 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3208 15:36:22.853662 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3209 15:36:22.856856 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3210 15:36:22.859876 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3211 15:36:22.863526 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3212 15:36:22.866618 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3213 15:36:22.873784 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3214 15:36:22.873868 ==
3215 15:36:22.876785 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 15:36:22.880508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 15:36:22.880618 ==
3218 15:36:22.880749 DQS Delay:
3219 15:36:22.883441 DQS0 = 0, DQS1 = 0
3220 15:36:22.883525 DQM Delay:
3221 15:36:22.886733 DQM0 = 115, DQM1 = 108
3222 15:36:22.886817 DQ Delay:
3223 15:36:22.890433 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3224 15:36:22.893861 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3225 15:36:22.897255 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3226 15:36:22.900287 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3227 15:36:22.900380
3228 15:36:22.900465
3229 15:36:22.900563 ==
3230 15:36:22.903549 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 15:36:22.910380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 15:36:22.910469 ==
3233 15:36:22.910554
3234 15:36:22.910634
3235 15:36:22.910712 TX Vref Scan disable
3236 15:36:22.913577 == TX Byte 0 ==
3237 15:36:22.916748 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3238 15:36:22.920388 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3239 15:36:22.923989 == TX Byte 1 ==
3240 15:36:22.927392 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3241 15:36:22.930489 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3242 15:36:22.933866 ==
3243 15:36:22.937243 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 15:36:22.940503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 15:36:22.940616 ==
3246 15:36:22.951722 TX Vref=22, minBit 1, minWin=25, winSum=410
3247 15:36:22.955150 TX Vref=24, minBit 1, minWin=25, winSum=417
3248 15:36:22.958383 TX Vref=26, minBit 8, minWin=25, winSum=423
3249 15:36:22.961628 TX Vref=28, minBit 8, minWin=25, winSum=430
3250 15:36:22.964800 TX Vref=30, minBit 0, minWin=26, winSum=424
3251 15:36:22.968371 TX Vref=32, minBit 1, minWin=26, winSum=430
3252 15:36:22.974776 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 32
3253 15:36:22.974877
3254 15:36:22.978456 Final TX Range 1 Vref 32
3255 15:36:22.978555
3256 15:36:22.978652 ==
3257 15:36:22.981728 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 15:36:22.985113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 15:36:22.985200 ==
3260 15:36:22.985287
3261 15:36:22.985370
3262 15:36:22.988776 TX Vref Scan disable
3263 15:36:22.991803 == TX Byte 0 ==
3264 15:36:22.995724 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3265 15:36:22.998577 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3266 15:36:23.001659 == TX Byte 1 ==
3267 15:36:23.005191 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3268 15:36:23.008619 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3269 15:36:23.008719
3270 15:36:23.012241 [DATLAT]
3271 15:36:23.012326 Freq=1200, CH1 RK0
3272 15:36:23.012430
3273 15:36:23.015574 DATLAT Default: 0xd
3274 15:36:23.015660 0, 0xFFFF, sum = 0
3275 15:36:23.018477 1, 0xFFFF, sum = 0
3276 15:36:23.018565 2, 0xFFFF, sum = 0
3277 15:36:23.021837 3, 0xFFFF, sum = 0
3278 15:36:23.021922 4, 0xFFFF, sum = 0
3279 15:36:23.025231 5, 0xFFFF, sum = 0
3280 15:36:23.025323 6, 0xFFFF, sum = 0
3281 15:36:23.028490 7, 0xFFFF, sum = 0
3282 15:36:23.028577 8, 0xFFFF, sum = 0
3283 15:36:23.032064 9, 0xFFFF, sum = 0
3284 15:36:23.032151 10, 0xFFFF, sum = 0
3285 15:36:23.035351 11, 0xFFFF, sum = 0
3286 15:36:23.035439 12, 0x0, sum = 1
3287 15:36:23.039216 13, 0x0, sum = 2
3288 15:36:23.039304 14, 0x0, sum = 3
3289 15:36:23.042281 15, 0x0, sum = 4
3290 15:36:23.042367 best_step = 13
3291 15:36:23.042454
3292 15:36:23.042535 ==
3293 15:36:23.045492 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 15:36:23.049040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 15:36:23.052266 ==
3296 15:36:23.052351 RX Vref Scan: 1
3297 15:36:23.052438
3298 15:36:23.055837 Set Vref Range= 32 -> 127
3299 15:36:23.055943
3300 15:36:23.056032 RX Vref 32 -> 127, step: 1
3301 15:36:23.059036
3302 15:36:23.059119 RX Delay -21 -> 252, step: 4
3303 15:36:23.059184
3304 15:36:23.062489 Set Vref, RX VrefLevel [Byte0]: 32
3305 15:36:23.065878 [Byte1]: 32
3306 15:36:23.070128
3307 15:36:23.070210 Set Vref, RX VrefLevel [Byte0]: 33
3308 15:36:23.072954 [Byte1]: 33
3309 15:36:23.077817
3310 15:36:23.077900 Set Vref, RX VrefLevel [Byte0]: 34
3311 15:36:23.081363 [Byte1]: 34
3312 15:36:23.085619
3313 15:36:23.085698 Set Vref, RX VrefLevel [Byte0]: 35
3314 15:36:23.088887 [Byte1]: 35
3315 15:36:23.093565
3316 15:36:23.093660 Set Vref, RX VrefLevel [Byte0]: 36
3317 15:36:23.097083 [Byte1]: 36
3318 15:36:23.101263
3319 15:36:23.101342 Set Vref, RX VrefLevel [Byte0]: 37
3320 15:36:23.105075 [Byte1]: 37
3321 15:36:23.109692
3322 15:36:23.109772 Set Vref, RX VrefLevel [Byte0]: 38
3323 15:36:23.112754 [Byte1]: 38
3324 15:36:23.117199
3325 15:36:23.117279 Set Vref, RX VrefLevel [Byte0]: 39
3326 15:36:23.120278 [Byte1]: 39
3327 15:36:23.125383
3328 15:36:23.125460 Set Vref, RX VrefLevel [Byte0]: 40
3329 15:36:23.128280 [Byte1]: 40
3330 15:36:23.133162
3331 15:36:23.133240 Set Vref, RX VrefLevel [Byte0]: 41
3332 15:36:23.136336 [Byte1]: 41
3333 15:36:23.140789
3334 15:36:23.140869 Set Vref, RX VrefLevel [Byte0]: 42
3335 15:36:23.144334 [Byte1]: 42
3336 15:36:23.148613
3337 15:36:23.148747 Set Vref, RX VrefLevel [Byte0]: 43
3338 15:36:23.152081 [Byte1]: 43
3339 15:36:23.156695
3340 15:36:23.156771 Set Vref, RX VrefLevel [Byte0]: 44
3341 15:36:23.160549 [Byte1]: 44
3342 15:36:23.164684
3343 15:36:23.164776 Set Vref, RX VrefLevel [Byte0]: 45
3344 15:36:23.167942 [Byte1]: 45
3345 15:36:23.172624
3346 15:36:23.172746 Set Vref, RX VrefLevel [Byte0]: 46
3347 15:36:23.176353 [Byte1]: 46
3348 15:36:23.180496
3349 15:36:23.180582 Set Vref, RX VrefLevel [Byte0]: 47
3350 15:36:23.184147 [Byte1]: 47
3351 15:36:23.188861
3352 15:36:23.188945 Set Vref, RX VrefLevel [Byte0]: 48
3353 15:36:23.191948 [Byte1]: 48
3354 15:36:23.196210
3355 15:36:23.196293 Set Vref, RX VrefLevel [Byte0]: 49
3356 15:36:23.199739 [Byte1]: 49
3357 15:36:23.204234
3358 15:36:23.204318 Set Vref, RX VrefLevel [Byte0]: 50
3359 15:36:23.207594 [Byte1]: 50
3360 15:36:23.212194
3361 15:36:23.212278 Set Vref, RX VrefLevel [Byte0]: 51
3362 15:36:23.215863 [Byte1]: 51
3363 15:36:23.220208
3364 15:36:23.220291 Set Vref, RX VrefLevel [Byte0]: 52
3365 15:36:23.223712 [Byte1]: 52
3366 15:36:23.228210
3367 15:36:23.228293 Set Vref, RX VrefLevel [Byte0]: 53
3368 15:36:23.231457 [Byte1]: 53
3369 15:36:23.235985
3370 15:36:23.236069 Set Vref, RX VrefLevel [Byte0]: 54
3371 15:36:23.239390 [Byte1]: 54
3372 15:36:23.243737
3373 15:36:23.243820 Set Vref, RX VrefLevel [Byte0]: 55
3374 15:36:23.247061 [Byte1]: 55
3375 15:36:23.252036
3376 15:36:23.252119 Set Vref, RX VrefLevel [Byte0]: 56
3377 15:36:23.255240 [Byte1]: 56
3378 15:36:23.259777
3379 15:36:23.259860 Set Vref, RX VrefLevel [Byte0]: 57
3380 15:36:23.262936 [Byte1]: 57
3381 15:36:23.268125
3382 15:36:23.268209 Set Vref, RX VrefLevel [Byte0]: 58
3383 15:36:23.270881 [Byte1]: 58
3384 15:36:23.275615
3385 15:36:23.275698 Set Vref, RX VrefLevel [Byte0]: 59
3386 15:36:23.278802 [Byte1]: 59
3387 15:36:23.283415
3388 15:36:23.283499 Set Vref, RX VrefLevel [Byte0]: 60
3389 15:36:23.286856 [Byte1]: 60
3390 15:36:23.291459
3391 15:36:23.291543 Set Vref, RX VrefLevel [Byte0]: 61
3392 15:36:23.294786 [Byte1]: 61
3393 15:36:23.299318
3394 15:36:23.299401 Set Vref, RX VrefLevel [Byte0]: 62
3395 15:36:23.302732 [Byte1]: 62
3396 15:36:23.307644
3397 15:36:23.307727 Set Vref, RX VrefLevel [Byte0]: 63
3398 15:36:23.310613 [Byte1]: 63
3399 15:36:23.315021
3400 15:36:23.315104 Set Vref, RX VrefLevel [Byte0]: 64
3401 15:36:23.318795 [Byte1]: 64
3402 15:36:23.323140
3403 15:36:23.323223 Set Vref, RX VrefLevel [Byte0]: 65
3404 15:36:23.326611 [Byte1]: 65
3405 15:36:23.330881
3406 15:36:23.330965 Set Vref, RX VrefLevel [Byte0]: 66
3407 15:36:23.334823 [Byte1]: 66
3408 15:36:23.338818
3409 15:36:23.338929 Set Vref, RX VrefLevel [Byte0]: 67
3410 15:36:23.342434 [Byte1]: 67
3411 15:36:23.346863
3412 15:36:23.346962 Set Vref, RX VrefLevel [Byte0]: 68
3413 15:36:23.350214 [Byte1]: 68
3414 15:36:23.354603
3415 15:36:23.354691 Set Vref, RX VrefLevel [Byte0]: 69
3416 15:36:23.358375 [Byte1]: 69
3417 15:36:23.362699
3418 15:36:23.362803 Set Vref, RX VrefLevel [Byte0]: 70
3419 15:36:23.366155 [Byte1]: 70
3420 15:36:23.370781
3421 15:36:23.370887 Set Vref, RX VrefLevel [Byte0]: 71
3422 15:36:23.373935 [Byte1]: 71
3423 15:36:23.378352
3424 15:36:23.378434 Set Vref, RX VrefLevel [Byte0]: 72
3425 15:36:23.381612 [Byte1]: 72
3426 15:36:23.386369
3427 15:36:23.386444 Set Vref, RX VrefLevel [Byte0]: 73
3428 15:36:23.389686 [Byte1]: 73
3429 15:36:23.394383
3430 15:36:23.394481 Final RX Vref Byte 0 = 58 to rank0
3431 15:36:23.397806 Final RX Vref Byte 1 = 52 to rank0
3432 15:36:23.400844 Final RX Vref Byte 0 = 58 to rank1
3433 15:36:23.404222 Final RX Vref Byte 1 = 52 to rank1==
3434 15:36:23.407757 Dram Type= 6, Freq= 0, CH_1, rank 0
3435 15:36:23.411818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3436 15:36:23.414838 ==
3437 15:36:23.414959 DQS Delay:
3438 15:36:23.415024 DQS0 = 0, DQS1 = 0
3439 15:36:23.417708 DQM Delay:
3440 15:36:23.417805 DQM0 = 116, DQM1 = 109
3441 15:36:23.421364 DQ Delay:
3442 15:36:23.424661 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3443 15:36:23.427858 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3444 15:36:23.431420 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3445 15:36:23.434778 DQ12 =116, DQ13 =118, DQ14 =116, DQ15 =114
3446 15:36:23.434881
3447 15:36:23.434976
3448 15:36:23.441248 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
3449 15:36:23.444727 CH1 RK0: MR19=403, MR18=2E6
3450 15:36:23.451111 CH1_RK0: MR19=0x403, MR18=0x2E6, DQSOSC=409, MR23=63, INC=39, DEC=26
3451 15:36:23.451211
3452 15:36:23.454556 ----->DramcWriteLeveling(PI) begin...
3453 15:36:23.454628 ==
3454 15:36:23.457990 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 15:36:23.461519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 15:36:23.461595 ==
3457 15:36:23.465244 Write leveling (Byte 0): 28 => 28
3458 15:36:23.468222 Write leveling (Byte 1): 29 => 29
3459 15:36:23.471726 DramcWriteLeveling(PI) end<-----
3460 15:36:23.471799
3461 15:36:23.471860 ==
3462 15:36:23.474840 Dram Type= 6, Freq= 0, CH_1, rank 1
3463 15:36:23.478296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3464 15:36:23.478369 ==
3465 15:36:23.481776 [Gating] SW mode calibration
3466 15:36:23.488599 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3467 15:36:23.495448 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3468 15:36:23.498619 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3469 15:36:23.502027 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3470 15:36:23.508304 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 15:36:23.512202 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3472 15:36:23.515094 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 15:36:23.521905 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3474 15:36:23.525000 0 15 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 0)
3475 15:36:23.528488 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
3476 15:36:23.535077 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 15:36:23.538649 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 15:36:23.541830 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 15:36:23.548914 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 15:36:23.551734 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 15:36:23.555038 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 15:36:23.562308 1 0 24 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
3483 15:36:23.565487 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3484 15:36:23.568600 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 15:36:23.575573 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 15:36:23.578736 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 15:36:23.581849 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 15:36:23.585123 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 15:36:23.591860 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3490 15:36:23.595287 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3491 15:36:23.598451 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3492 15:36:23.605444 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 15:36:23.608522 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 15:36:23.611955 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 15:36:23.618701 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 15:36:23.621975 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 15:36:23.625059 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 15:36:23.631814 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 15:36:23.635124 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 15:36:23.639017 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 15:36:23.645746 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 15:36:23.648614 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 15:36:23.652162 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 15:36:23.655373 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 15:36:23.662048 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3506 15:36:23.665694 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3507 15:36:23.668758 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3508 15:36:23.672238 Total UI for P1: 0, mck2ui 16
3509 15:36:23.675290 best dqsien dly found for B0: ( 1, 3, 22)
3510 15:36:23.682199 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 15:36:23.685147 Total UI for P1: 0, mck2ui 16
3512 15:36:23.688769 best dqsien dly found for B1: ( 1, 3, 28)
3513 15:36:23.691847 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3514 15:36:23.695290 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3515 15:36:23.695422
3516 15:36:23.698942 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3517 15:36:23.702309 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3518 15:36:23.705557 [Gating] SW calibration Done
3519 15:36:23.705634 ==
3520 15:36:23.708797 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 15:36:23.712369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 15:36:23.712441 ==
3523 15:36:23.715423 RX Vref Scan: 0
3524 15:36:23.715502
3525 15:36:23.715582 RX Vref 0 -> 0, step: 1
3526 15:36:23.715656
3527 15:36:23.718604 RX Delay -40 -> 252, step: 8
3528 15:36:23.722290 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3529 15:36:23.729095 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3530 15:36:23.732233 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3531 15:36:23.735586 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3532 15:36:23.739234 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3533 15:36:23.742239 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3534 15:36:23.748989 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3535 15:36:23.752451 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3536 15:36:23.755514 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3537 15:36:23.758763 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3538 15:36:23.762718 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3539 15:36:23.768919 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3540 15:36:23.771995 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3541 15:36:23.775393 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3542 15:36:23.778782 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3543 15:36:23.782602 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3544 15:36:23.782741 ==
3545 15:36:23.786096 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 15:36:23.792069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 15:36:23.792173 ==
3548 15:36:23.792268 DQS Delay:
3549 15:36:23.795608 DQS0 = 0, DQS1 = 0
3550 15:36:23.795708 DQM Delay:
3551 15:36:23.798878 DQM0 = 113, DQM1 = 109
3552 15:36:23.798951 DQ Delay:
3553 15:36:23.802177 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3554 15:36:23.805552 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3555 15:36:23.808759 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3556 15:36:23.812081 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3557 15:36:23.812156
3558 15:36:23.812261
3559 15:36:23.812350 ==
3560 15:36:23.815328 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 15:36:23.818885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 15:36:23.822430 ==
3563 15:36:23.822505
3564 15:36:23.822568
3565 15:36:23.822628 TX Vref Scan disable
3566 15:36:23.825855 == TX Byte 0 ==
3567 15:36:23.829668 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3568 15:36:23.832381 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3569 15:36:23.835969 == TX Byte 1 ==
3570 15:36:23.838715 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3571 15:36:23.842486 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3572 15:36:23.842590 ==
3573 15:36:23.846078 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 15:36:23.852454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 15:36:23.852544 ==
3576 15:36:23.862876 TX Vref=22, minBit 2, minWin=25, winSum=418
3577 15:36:23.865988 TX Vref=24, minBit 2, minWin=25, winSum=423
3578 15:36:23.869601 TX Vref=26, minBit 3, minWin=25, winSum=430
3579 15:36:23.873071 TX Vref=28, minBit 2, minWin=26, winSum=432
3580 15:36:23.876350 TX Vref=30, minBit 3, minWin=26, winSum=433
3581 15:36:23.879413 TX Vref=32, minBit 3, minWin=26, winSum=432
3582 15:36:23.886265 [TxChooseVref] Worse bit 3, Min win 26, Win sum 433, Final Vref 30
3583 15:36:23.886342
3584 15:36:23.890041 Final TX Range 1 Vref 30
3585 15:36:23.890122
3586 15:36:23.890186 ==
3587 15:36:23.892882 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 15:36:23.896317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 15:36:23.896422 ==
3590 15:36:23.896514
3591 15:36:23.896602
3592 15:36:23.899916 TX Vref Scan disable
3593 15:36:23.902852 == TX Byte 0 ==
3594 15:36:23.906055 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3595 15:36:23.909643 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3596 15:36:23.912872 == TX Byte 1 ==
3597 15:36:23.916321 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3598 15:36:23.919918 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3599 15:36:23.919994
3600 15:36:23.923038 [DATLAT]
3601 15:36:23.923116 Freq=1200, CH1 RK1
3602 15:36:23.923180
3603 15:36:23.926306 DATLAT Default: 0xd
3604 15:36:23.926380 0, 0xFFFF, sum = 0
3605 15:36:23.929826 1, 0xFFFF, sum = 0
3606 15:36:23.929907 2, 0xFFFF, sum = 0
3607 15:36:23.932823 3, 0xFFFF, sum = 0
3608 15:36:23.932900 4, 0xFFFF, sum = 0
3609 15:36:23.936453 5, 0xFFFF, sum = 0
3610 15:36:23.936562 6, 0xFFFF, sum = 0
3611 15:36:23.939595 7, 0xFFFF, sum = 0
3612 15:36:23.939673 8, 0xFFFF, sum = 0
3613 15:36:23.942766 9, 0xFFFF, sum = 0
3614 15:36:23.942870 10, 0xFFFF, sum = 0
3615 15:36:23.946208 11, 0xFFFF, sum = 0
3616 15:36:23.946310 12, 0x0, sum = 1
3617 15:36:23.949893 13, 0x0, sum = 2
3618 15:36:23.950050 14, 0x0, sum = 3
3619 15:36:23.952792 15, 0x0, sum = 4
3620 15:36:23.952868 best_step = 13
3621 15:36:23.952938
3622 15:36:23.952997 ==
3623 15:36:23.956309 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 15:36:23.963339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 15:36:23.963448 ==
3626 15:36:23.963546 RX Vref Scan: 0
3627 15:36:23.963635
3628 15:36:23.966665 RX Vref 0 -> 0, step: 1
3629 15:36:23.966767
3630 15:36:23.969796 RX Delay -21 -> 252, step: 4
3631 15:36:23.972917 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3632 15:36:23.976591 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3633 15:36:23.983342 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3634 15:36:23.986698 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3635 15:36:23.989862 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3636 15:36:23.993216 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3637 15:36:23.996518 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3638 15:36:24.003013 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3639 15:36:24.006393 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3640 15:36:24.010280 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3641 15:36:24.013196 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3642 15:36:24.016710 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3643 15:36:24.019982 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3644 15:36:24.026947 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3645 15:36:24.029923 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3646 15:36:24.033324 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3647 15:36:24.033447 ==
3648 15:36:24.036749 Dram Type= 6, Freq= 0, CH_1, rank 1
3649 15:36:24.040578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3650 15:36:24.040705 ==
3651 15:36:24.043196 DQS Delay:
3652 15:36:24.043267 DQS0 = 0, DQS1 = 0
3653 15:36:24.046777 DQM Delay:
3654 15:36:24.046854 DQM0 = 113, DQM1 = 109
3655 15:36:24.046918 DQ Delay:
3656 15:36:24.053682 DQ0 =114, DQ1 =110, DQ2 =104, DQ3 =112
3657 15:36:24.057130 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3658 15:36:24.060458 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3659 15:36:24.063709 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =118
3660 15:36:24.063786
3661 15:36:24.063850
3662 15:36:24.069842 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3663 15:36:24.073331 CH1 RK1: MR19=304, MR18=FB02
3664 15:36:24.080056 CH1_RK1: MR19=0x304, MR18=0xFB02, DQSOSC=409, MR23=63, INC=39, DEC=26
3665 15:36:24.083695 [RxdqsGatingPostProcess] freq 1200
3666 15:36:24.086760 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3667 15:36:24.090081 best DQS0 dly(2T, 0.5T) = (0, 11)
3668 15:36:24.093434 best DQS1 dly(2T, 0.5T) = (0, 11)
3669 15:36:24.096851 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3670 15:36:24.099975 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3671 15:36:24.103743 best DQS0 dly(2T, 0.5T) = (0, 11)
3672 15:36:24.106969 best DQS1 dly(2T, 0.5T) = (0, 11)
3673 15:36:24.109886 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3674 15:36:24.113437 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3675 15:36:24.116865 Pre-setting of DQS Precalculation
3676 15:36:24.119998 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3677 15:36:24.130319 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3678 15:36:24.137307 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3679 15:36:24.137392
3680 15:36:24.137477
3681 15:36:24.140047 [Calibration Summary] 2400 Mbps
3682 15:36:24.140132 CH 0, Rank 0
3683 15:36:24.143708 SW Impedance : PASS
3684 15:36:24.143792 DUTY Scan : NO K
3685 15:36:24.146866 ZQ Calibration : PASS
3686 15:36:24.150284 Jitter Meter : NO K
3687 15:36:24.150370 CBT Training : PASS
3688 15:36:24.153806 Write leveling : PASS
3689 15:36:24.156909 RX DQS gating : PASS
3690 15:36:24.156992 RX DQ/DQS(RDDQC) : PASS
3691 15:36:24.161029 TX DQ/DQS : PASS
3692 15:36:24.161114 RX DATLAT : PASS
3693 15:36:24.163646 RX DQ/DQS(Engine): PASS
3694 15:36:24.167323 TX OE : NO K
3695 15:36:24.167407 All Pass.
3696 15:36:24.167492
3697 15:36:24.167572 CH 0, Rank 1
3698 15:36:24.170769 SW Impedance : PASS
3699 15:36:24.173605 DUTY Scan : NO K
3700 15:36:24.173689 ZQ Calibration : PASS
3701 15:36:24.176975 Jitter Meter : NO K
3702 15:36:24.180820 CBT Training : PASS
3703 15:36:24.180903 Write leveling : PASS
3704 15:36:24.183707 RX DQS gating : PASS
3705 15:36:24.186948 RX DQ/DQS(RDDQC) : PASS
3706 15:36:24.187032 TX DQ/DQS : PASS
3707 15:36:24.190223 RX DATLAT : PASS
3708 15:36:24.193615 RX DQ/DQS(Engine): PASS
3709 15:36:24.193698 TX OE : NO K
3710 15:36:24.193783 All Pass.
3711 15:36:24.197103
3712 15:36:24.197187 CH 1, Rank 0
3713 15:36:24.200955 SW Impedance : PASS
3714 15:36:24.201042 DUTY Scan : NO K
3715 15:36:24.203927 ZQ Calibration : PASS
3716 15:36:24.204011 Jitter Meter : NO K
3717 15:36:24.207203 CBT Training : PASS
3718 15:36:24.210587 Write leveling : PASS
3719 15:36:24.210716 RX DQS gating : PASS
3720 15:36:24.214366 RX DQ/DQS(RDDQC) : PASS
3721 15:36:24.217366 TX DQ/DQS : PASS
3722 15:36:24.217466 RX DATLAT : PASS
3723 15:36:24.220413 RX DQ/DQS(Engine): PASS
3724 15:36:24.224072 TX OE : NO K
3725 15:36:24.224157 All Pass.
3726 15:36:24.224241
3727 15:36:24.224340 CH 1, Rank 1
3728 15:36:24.227084 SW Impedance : PASS
3729 15:36:24.230865 DUTY Scan : NO K
3730 15:36:24.230948 ZQ Calibration : PASS
3731 15:36:24.234596 Jitter Meter : NO K
3732 15:36:24.237209 CBT Training : PASS
3733 15:36:24.237293 Write leveling : PASS
3734 15:36:24.240561 RX DQS gating : PASS
3735 15:36:24.240678 RX DQ/DQS(RDDQC) : PASS
3736 15:36:24.244135 TX DQ/DQS : PASS
3737 15:36:24.247343 RX DATLAT : PASS
3738 15:36:24.247427 RX DQ/DQS(Engine): PASS
3739 15:36:24.250559 TX OE : NO K
3740 15:36:24.250643 All Pass.
3741 15:36:24.250728
3742 15:36:24.253962 DramC Write-DBI off
3743 15:36:24.257098 PER_BANK_REFRESH: Hybrid Mode
3744 15:36:24.257182 TX_TRACKING: ON
3745 15:36:24.267397 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3746 15:36:24.270812 [FAST_K] Save calibration result to emmc
3747 15:36:24.274120 dramc_set_vcore_voltage set vcore to 650000
3748 15:36:24.277420 Read voltage for 600, 5
3749 15:36:24.277504 Vio18 = 0
3750 15:36:24.277589 Vcore = 650000
3751 15:36:24.281104 Vdram = 0
3752 15:36:24.281188 Vddq = 0
3753 15:36:24.281290 Vmddr = 0
3754 15:36:24.287425 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3755 15:36:24.291018 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3756 15:36:24.293912 MEM_TYPE=3, freq_sel=19
3757 15:36:24.297512 sv_algorithm_assistance_LP4_1600
3758 15:36:24.300624 ============ PULL DRAM RESETB DOWN ============
3759 15:36:24.304413 ========== PULL DRAM RESETB DOWN end =========
3760 15:36:24.310964 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3761 15:36:24.314112 ===================================
3762 15:36:24.314197 LPDDR4 DRAM CONFIGURATION
3763 15:36:24.317402 ===================================
3764 15:36:24.320886 EX_ROW_EN[0] = 0x0
3765 15:36:24.324297 EX_ROW_EN[1] = 0x0
3766 15:36:24.324381 LP4Y_EN = 0x0
3767 15:36:24.327528 WORK_FSP = 0x0
3768 15:36:24.327631 WL = 0x2
3769 15:36:24.330707 RL = 0x2
3770 15:36:24.330790 BL = 0x2
3771 15:36:24.334137 RPST = 0x0
3772 15:36:24.334221 RD_PRE = 0x0
3773 15:36:24.337545 WR_PRE = 0x1
3774 15:36:24.337629 WR_PST = 0x0
3775 15:36:24.340909 DBI_WR = 0x0
3776 15:36:24.340993 DBI_RD = 0x0
3777 15:36:24.344400 OTF = 0x1
3778 15:36:24.347912 ===================================
3779 15:36:24.350822 ===================================
3780 15:36:24.350906 ANA top config
3781 15:36:24.354592 ===================================
3782 15:36:24.357531 DLL_ASYNC_EN = 0
3783 15:36:24.361280 ALL_SLAVE_EN = 1
3784 15:36:24.361364 NEW_RANK_MODE = 1
3785 15:36:24.364252 DLL_IDLE_MODE = 1
3786 15:36:24.367663 LP45_APHY_COMB_EN = 1
3787 15:36:24.371228 TX_ODT_DIS = 1
3788 15:36:24.374794 NEW_8X_MODE = 1
3789 15:36:24.377739 ===================================
3790 15:36:24.377823 ===================================
3791 15:36:24.381149 data_rate = 1200
3792 15:36:24.384599 CKR = 1
3793 15:36:24.387769 DQ_P2S_RATIO = 8
3794 15:36:24.391600 ===================================
3795 15:36:24.394705 CA_P2S_RATIO = 8
3796 15:36:24.397870 DQ_CA_OPEN = 0
3797 15:36:24.397969 DQ_SEMI_OPEN = 0
3798 15:36:24.400841 CA_SEMI_OPEN = 0
3799 15:36:24.404791 CA_FULL_RATE = 0
3800 15:36:24.407754 DQ_CKDIV4_EN = 1
3801 15:36:24.410764 CA_CKDIV4_EN = 1
3802 15:36:24.414382 CA_PREDIV_EN = 0
3803 15:36:24.414480 PH8_DLY = 0
3804 15:36:24.417596 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3805 15:36:24.420818 DQ_AAMCK_DIV = 4
3806 15:36:24.424323 CA_AAMCK_DIV = 4
3807 15:36:24.427863 CA_ADMCK_DIV = 4
3808 15:36:24.430797 DQ_TRACK_CA_EN = 0
3809 15:36:24.434429 CA_PICK = 600
3810 15:36:24.434514 CA_MCKIO = 600
3811 15:36:24.437909 MCKIO_SEMI = 0
3812 15:36:24.441487 PLL_FREQ = 2288
3813 15:36:24.444588 DQ_UI_PI_RATIO = 32
3814 15:36:24.447706 CA_UI_PI_RATIO = 0
3815 15:36:24.451097 ===================================
3816 15:36:24.454447 ===================================
3817 15:36:24.454531 memory_type:LPDDR4
3818 15:36:24.457877 GP_NUM : 10
3819 15:36:24.460928 SRAM_EN : 1
3820 15:36:24.461012 MD32_EN : 0
3821 15:36:24.464206 ===================================
3822 15:36:24.467704 [ANA_INIT] >>>>>>>>>>>>>>
3823 15:36:24.471179 <<<<<< [CONFIGURE PHASE]: ANA_TX
3824 15:36:24.474639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3825 15:36:24.477853 ===================================
3826 15:36:24.481197 data_rate = 1200,PCW = 0X5800
3827 15:36:24.484796 ===================================
3828 15:36:24.487720 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3829 15:36:24.491356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3830 15:36:24.497587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3831 15:36:24.501387 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3832 15:36:24.504748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3833 15:36:24.508193 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3834 15:36:24.512044 [ANA_INIT] flow start
3835 15:36:24.514358 [ANA_INIT] PLL >>>>>>>>
3836 15:36:24.514435 [ANA_INIT] PLL <<<<<<<<
3837 15:36:24.517778 [ANA_INIT] MIDPI >>>>>>>>
3838 15:36:24.521385 [ANA_INIT] MIDPI <<<<<<<<
3839 15:36:24.524782 [ANA_INIT] DLL >>>>>>>>
3840 15:36:24.524858 [ANA_INIT] flow end
3841 15:36:24.527960 ============ LP4 DIFF to SE enter ============
3842 15:36:24.534411 ============ LP4 DIFF to SE exit ============
3843 15:36:24.534497 [ANA_INIT] <<<<<<<<<<<<<
3844 15:36:24.537680 [Flow] Enable top DCM control >>>>>
3845 15:36:24.541255 [Flow] Enable top DCM control <<<<<
3846 15:36:24.544360 Enable DLL master slave shuffle
3847 15:36:24.550971 ==============================================================
3848 15:36:24.551057 Gating Mode config
3849 15:36:24.558398 ==============================================================
3850 15:36:24.561304 Config description:
3851 15:36:24.567670 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3852 15:36:24.574658 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3853 15:36:24.581154 SELPH_MODE 0: By rank 1: By Phase
3854 15:36:24.588281 ==============================================================
3855 15:36:24.588363 GAT_TRACK_EN = 1
3856 15:36:24.591236 RX_GATING_MODE = 2
3857 15:36:24.594493 RX_GATING_TRACK_MODE = 2
3858 15:36:24.597624 SELPH_MODE = 1
3859 15:36:24.601454 PICG_EARLY_EN = 1
3860 15:36:24.604596 VALID_LAT_VALUE = 1
3861 15:36:24.611347 ==============================================================
3862 15:36:24.615122 Enter into Gating configuration >>>>
3863 15:36:24.618043 Exit from Gating configuration <<<<
3864 15:36:24.621297 Enter into DVFS_PRE_config >>>>>
3865 15:36:24.631144 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3866 15:36:24.634479 Exit from DVFS_PRE_config <<<<<
3867 15:36:24.638199 Enter into PICG configuration >>>>
3868 15:36:24.641491 Exit from PICG configuration <<<<
3869 15:36:24.641578 [RX_INPUT] configuration >>>>>
3870 15:36:24.644921 [RX_INPUT] configuration <<<<<
3871 15:36:24.651077 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3872 15:36:24.654694 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3873 15:36:24.661469 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3874 15:36:24.668405 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3875 15:36:24.674599 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3876 15:36:24.681472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3877 15:36:24.684844 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3878 15:36:24.687837 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3879 15:36:24.694611 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3880 15:36:24.697999 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3881 15:36:24.701128 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3882 15:36:24.704918 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3883 15:36:24.708432 ===================================
3884 15:36:24.711256 LPDDR4 DRAM CONFIGURATION
3885 15:36:24.714606 ===================================
3886 15:36:24.717934 EX_ROW_EN[0] = 0x0
3887 15:36:24.718018 EX_ROW_EN[1] = 0x0
3888 15:36:24.721438 LP4Y_EN = 0x0
3889 15:36:24.721522 WORK_FSP = 0x0
3890 15:36:24.725113 WL = 0x2
3891 15:36:24.725194 RL = 0x2
3892 15:36:24.728084 BL = 0x2
3893 15:36:24.728164 RPST = 0x0
3894 15:36:24.731487 RD_PRE = 0x0
3895 15:36:24.731568 WR_PRE = 0x1
3896 15:36:24.734919 WR_PST = 0x0
3897 15:36:24.734992 DBI_WR = 0x0
3898 15:36:24.737875 DBI_RD = 0x0
3899 15:36:24.737986 OTF = 0x1
3900 15:36:24.741334 ===================================
3901 15:36:24.747882 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3902 15:36:24.751319 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3903 15:36:24.755098 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3904 15:36:24.757987 ===================================
3905 15:36:24.761233 LPDDR4 DRAM CONFIGURATION
3906 15:36:24.764626 ===================================
3907 15:36:24.764748 EX_ROW_EN[0] = 0x10
3908 15:36:24.768004 EX_ROW_EN[1] = 0x0
3909 15:36:24.771424 LP4Y_EN = 0x0
3910 15:36:24.771526 WORK_FSP = 0x0
3911 15:36:24.774604 WL = 0x2
3912 15:36:24.774680 RL = 0x2
3913 15:36:24.778503 BL = 0x2
3914 15:36:24.778575 RPST = 0x0
3915 15:36:24.781413 RD_PRE = 0x0
3916 15:36:24.781514 WR_PRE = 0x1
3917 15:36:24.784743 WR_PST = 0x0
3918 15:36:24.784816 DBI_WR = 0x0
3919 15:36:24.788069 DBI_RD = 0x0
3920 15:36:24.788182 OTF = 0x1
3921 15:36:24.791475 ===================================
3922 15:36:24.797968 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3923 15:36:24.802189 nWR fixed to 30
3924 15:36:24.805774 [ModeRegInit_LP4] CH0 RK0
3925 15:36:24.805876 [ModeRegInit_LP4] CH0 RK1
3926 15:36:24.809312 [ModeRegInit_LP4] CH1 RK0
3927 15:36:24.812330 [ModeRegInit_LP4] CH1 RK1
3928 15:36:24.812406 match AC timing 17
3929 15:36:24.818922 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3930 15:36:24.822099 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3931 15:36:24.825994 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3932 15:36:24.832597 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3933 15:36:24.835902 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3934 15:36:24.835989 ==
3935 15:36:24.838875 Dram Type= 6, Freq= 0, CH_0, rank 0
3936 15:36:24.842611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3937 15:36:24.842697 ==
3938 15:36:24.849451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3939 15:36:24.855587 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3940 15:36:24.859151 [CA 0] Center 36 (6~66) winsize 61
3941 15:36:24.862136 [CA 1] Center 35 (5~66) winsize 62
3942 15:36:24.865681 [CA 2] Center 34 (4~65) winsize 62
3943 15:36:24.868875 [CA 3] Center 34 (4~64) winsize 61
3944 15:36:24.872498 [CA 4] Center 33 (3~64) winsize 62
3945 15:36:24.875443 [CA 5] Center 33 (3~64) winsize 62
3946 15:36:24.875520
3947 15:36:24.879017 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3948 15:36:24.879116
3949 15:36:24.882552 [CATrainingPosCal] consider 1 rank data
3950 15:36:24.885664 u2DelayCellTimex100 = 270/100 ps
3951 15:36:24.888870 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3952 15:36:24.892709 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3953 15:36:24.895682 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3954 15:36:24.898896 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3955 15:36:24.902793 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3956 15:36:24.905489 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3957 15:36:24.905575
3958 15:36:24.912316 CA PerBit enable=1, Macro0, CA PI delay=33
3959 15:36:24.912400
3960 15:36:24.912486 [CBTSetCACLKResult] CA Dly = 33
3961 15:36:24.915764 CS Dly: 4 (0~35)
3962 15:36:24.915848 ==
3963 15:36:24.919178 Dram Type= 6, Freq= 0, CH_0, rank 1
3964 15:36:24.922282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 15:36:24.922366 ==
3966 15:36:24.929023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3967 15:36:24.936176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3968 15:36:24.939312 [CA 0] Center 36 (6~66) winsize 61
3969 15:36:24.942282 [CA 1] Center 36 (6~66) winsize 61
3970 15:36:24.946160 [CA 2] Center 34 (4~65) winsize 62
3971 15:36:24.949139 [CA 3] Center 34 (4~65) winsize 62
3972 15:36:24.952388 [CA 4] Center 33 (3~64) winsize 62
3973 15:36:24.955661 [CA 5] Center 33 (3~64) winsize 62
3974 15:36:24.955745
3975 15:36:24.959348 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3976 15:36:24.959432
3977 15:36:24.962551 [CATrainingPosCal] consider 2 rank data
3978 15:36:24.966112 u2DelayCellTimex100 = 270/100 ps
3979 15:36:24.969262 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3980 15:36:24.972942 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3981 15:36:24.975908 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3982 15:36:24.979207 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3983 15:36:24.982655 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3984 15:36:24.986322 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3985 15:36:24.986406
3986 15:36:24.989084 CA PerBit enable=1, Macro0, CA PI delay=33
3987 15:36:24.989196
3988 15:36:24.993018 [CBTSetCACLKResult] CA Dly = 33
3989 15:36:24.996009 CS Dly: 5 (0~37)
3990 15:36:24.996110
3991 15:36:24.999868 ----->DramcWriteLeveling(PI) begin...
3992 15:36:24.999972 ==
3993 15:36:25.002678 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 15:36:25.006067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 15:36:25.006170 ==
3996 15:36:25.009324 Write leveling (Byte 0): 31 => 31
3997 15:36:25.012953 Write leveling (Byte 1): 29 => 29
3998 15:36:25.015954 DramcWriteLeveling(PI) end<-----
3999 15:36:25.016048
4000 15:36:25.016135 ==
4001 15:36:25.019313 Dram Type= 6, Freq= 0, CH_0, rank 0
4002 15:36:25.023134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 15:36:25.023219 ==
4004 15:36:25.026053 [Gating] SW mode calibration
4005 15:36:25.032806 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4006 15:36:25.039445 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4007 15:36:25.042866 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 15:36:25.049489 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 15:36:25.052986 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4010 15:36:25.056045 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4011 15:36:25.059330 0 9 16 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (1 1)
4012 15:36:25.066024 0 9 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4013 15:36:25.069588 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 15:36:25.072697 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 15:36:25.079583 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 15:36:25.082771 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 15:36:25.086135 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 15:36:25.092820 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4019 15:36:25.096289 0 10 16 | B1->B0 | 3434 3c3c | 0 0 | (1 1) (1 1)
4020 15:36:25.099697 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 15:36:25.106152 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 15:36:25.109509 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 15:36:25.113131 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 15:36:25.119430 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 15:36:25.123097 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 15:36:25.126292 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 15:36:25.129639 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4028 15:36:25.136389 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 15:36:25.139743 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 15:36:25.143693 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 15:36:25.149970 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 15:36:25.153086 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 15:36:25.156994 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 15:36:25.163297 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 15:36:25.166868 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 15:36:25.169832 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 15:36:25.176413 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 15:36:25.180083 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 15:36:25.183081 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 15:36:25.189901 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 15:36:25.192958 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 15:36:25.196266 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 15:36:25.203214 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4044 15:36:25.206588 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 15:36:25.209840 Total UI for P1: 0, mck2ui 16
4046 15:36:25.213083 best dqsien dly found for B0: ( 0, 13, 16)
4047 15:36:25.216335 Total UI for P1: 0, mck2ui 16
4048 15:36:25.220084 best dqsien dly found for B1: ( 0, 13, 16)
4049 15:36:25.223344 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4050 15:36:25.226365 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4051 15:36:25.226474
4052 15:36:25.230073 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4053 15:36:25.233156 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4054 15:36:25.236374 [Gating] SW calibration Done
4055 15:36:25.236457 ==
4056 15:36:25.239992 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 15:36:25.243387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 15:36:25.243475 ==
4059 15:36:25.246759 RX Vref Scan: 0
4060 15:36:25.246842
4061 15:36:25.249940 RX Vref 0 -> 0, step: 1
4062 15:36:25.250023
4063 15:36:25.250088 RX Delay -230 -> 252, step: 16
4064 15:36:25.256673 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4065 15:36:25.259773 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4066 15:36:25.263362 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4067 15:36:25.266726 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4068 15:36:25.273272 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4069 15:36:25.276395 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4070 15:36:25.279854 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4071 15:36:25.283388 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4072 15:36:25.286375 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4073 15:36:25.293422 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4074 15:36:25.296396 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4075 15:36:25.299758 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4076 15:36:25.303499 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4077 15:36:25.310176 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4078 15:36:25.313027 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4079 15:36:25.316408 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4080 15:36:25.316506 ==
4081 15:36:25.319852 Dram Type= 6, Freq= 0, CH_0, rank 0
4082 15:36:25.323393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4083 15:36:25.323467 ==
4084 15:36:25.326422 DQS Delay:
4085 15:36:25.326504 DQS0 = 0, DQS1 = 0
4086 15:36:25.329626 DQM Delay:
4087 15:36:25.329701 DQM0 = 40, DQM1 = 32
4088 15:36:25.329764 DQ Delay:
4089 15:36:25.333452 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4090 15:36:25.336929 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4091 15:36:25.339719 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4092 15:36:25.343134 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4093 15:36:25.343233
4094 15:36:25.343334
4095 15:36:25.346612 ==
4096 15:36:25.346709 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 15:36:25.353533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 15:36:25.353611 ==
4099 15:36:25.353676
4100 15:36:25.353755
4101 15:36:25.356766 TX Vref Scan disable
4102 15:36:25.356865 == TX Byte 0 ==
4103 15:36:25.359964 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4104 15:36:25.367768 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4105 15:36:25.367946 == TX Byte 1 ==
4106 15:36:25.369633 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4107 15:36:25.376484 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4108 15:36:25.376582 ==
4109 15:36:25.379698 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 15:36:25.383265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 15:36:25.383372 ==
4112 15:36:25.383462
4113 15:36:25.383559
4114 15:36:25.386643 TX Vref Scan disable
4115 15:36:25.389845 == TX Byte 0 ==
4116 15:36:25.392982 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4117 15:36:25.396468 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4118 15:36:25.399662 == TX Byte 1 ==
4119 15:36:25.402970 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4120 15:36:25.406340 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4121 15:36:25.406445
4122 15:36:25.410422 [DATLAT]
4123 15:36:25.410511 Freq=600, CH0 RK0
4124 15:36:25.410576
4125 15:36:25.413041 DATLAT Default: 0x9
4126 15:36:25.413179 0, 0xFFFF, sum = 0
4127 15:36:25.416612 1, 0xFFFF, sum = 0
4128 15:36:25.416756 2, 0xFFFF, sum = 0
4129 15:36:25.419786 3, 0xFFFF, sum = 0
4130 15:36:25.419885 4, 0xFFFF, sum = 0
4131 15:36:25.423216 5, 0xFFFF, sum = 0
4132 15:36:25.423314 6, 0xFFFF, sum = 0
4133 15:36:25.426309 7, 0xFFFF, sum = 0
4134 15:36:25.426406 8, 0x0, sum = 1
4135 15:36:25.429771 9, 0x0, sum = 2
4136 15:36:25.429843 10, 0x0, sum = 3
4137 15:36:25.433270 11, 0x0, sum = 4
4138 15:36:25.433378 best_step = 9
4139 15:36:25.433468
4140 15:36:25.433555 ==
4141 15:36:25.436817 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 15:36:25.439914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 15:36:25.440003 ==
4144 15:36:25.443187 RX Vref Scan: 1
4145 15:36:25.443284
4146 15:36:25.446199 RX Vref 0 -> 0, step: 1
4147 15:36:25.446280
4148 15:36:25.446347 RX Delay -195 -> 252, step: 8
4149 15:36:25.446407
4150 15:36:25.449685 Set Vref, RX VrefLevel [Byte0]: 53
4151 15:36:25.453004 [Byte1]: 50
4152 15:36:25.457648
4153 15:36:25.457727 Final RX Vref Byte 0 = 53 to rank0
4154 15:36:25.461823 Final RX Vref Byte 1 = 50 to rank0
4155 15:36:25.464246 Final RX Vref Byte 0 = 53 to rank1
4156 15:36:25.467868 Final RX Vref Byte 1 = 50 to rank1==
4157 15:36:25.471413 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 15:36:25.477600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 15:36:25.477678 ==
4160 15:36:25.477741 DQS Delay:
4161 15:36:25.477800 DQS0 = 0, DQS1 = 0
4162 15:36:25.481067 DQM Delay:
4163 15:36:25.481138 DQM0 = 43, DQM1 = 33
4164 15:36:25.484831 DQ Delay:
4165 15:36:25.487750 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4166 15:36:25.487821 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4167 15:36:25.491007 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4168 15:36:25.494351 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4169 15:36:25.497763
4170 15:36:25.497850
4171 15:36:25.504267 [DQSOSCAuto] RK0, (LSB)MR18= 0x4928, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4172 15:36:25.507622 CH0 RK0: MR19=808, MR18=4928
4173 15:36:25.514557 CH0_RK0: MR19=0x808, MR18=0x4928, DQSOSC=396, MR23=63, INC=167, DEC=111
4174 15:36:25.514639
4175 15:36:25.517702 ----->DramcWriteLeveling(PI) begin...
4176 15:36:25.517802 ==
4177 15:36:25.520832 Dram Type= 6, Freq= 0, CH_0, rank 1
4178 15:36:25.524639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 15:36:25.524759 ==
4180 15:36:25.527478 Write leveling (Byte 0): 32 => 32
4181 15:36:25.530740 Write leveling (Byte 1): 31 => 31
4182 15:36:25.534500 DramcWriteLeveling(PI) end<-----
4183 15:36:25.534605
4184 15:36:25.534695 ==
4185 15:36:25.537960 Dram Type= 6, Freq= 0, CH_0, rank 1
4186 15:36:25.540600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 15:36:25.540747 ==
4188 15:36:25.544229 [Gating] SW mode calibration
4189 15:36:25.551079 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4190 15:36:25.557717 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4191 15:36:25.561058 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 15:36:25.564354 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 15:36:25.571087 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4194 15:36:25.574419 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
4195 15:36:25.577481 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4196 15:36:25.584337 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 15:36:25.587588 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 15:36:25.590801 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 15:36:25.597580 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 15:36:25.601463 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 15:36:25.604385 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 15:36:25.611068 0 10 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
4203 15:36:25.614302 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
4204 15:36:25.617705 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 15:36:25.624363 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 15:36:25.627559 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 15:36:25.631204 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 15:36:25.634545 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 15:36:25.641144 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 15:36:25.644273 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4211 15:36:25.647676 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 15:36:25.654355 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 15:36:25.657690 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 15:36:25.661368 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 15:36:25.667852 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 15:36:25.670977 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 15:36:25.674519 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 15:36:25.681110 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 15:36:25.684872 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 15:36:25.688078 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 15:36:25.694671 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 15:36:25.697931 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 15:36:25.700964 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 15:36:25.707500 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 15:36:25.711034 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 15:36:25.714884 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4227 15:36:25.721232 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4228 15:36:25.721309 Total UI for P1: 0, mck2ui 16
4229 15:36:25.724271 best dqsien dly found for B1: ( 0, 13, 14)
4230 15:36:25.731591 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 15:36:25.734308 Total UI for P1: 0, mck2ui 16
4232 15:36:25.738109 best dqsien dly found for B0: ( 0, 13, 14)
4233 15:36:25.741131 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4234 15:36:25.744468 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4235 15:36:25.744543
4236 15:36:25.747845 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4237 15:36:25.751662 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4238 15:36:25.754315 [Gating] SW calibration Done
4239 15:36:25.754389 ==
4240 15:36:25.757571 Dram Type= 6, Freq= 0, CH_0, rank 1
4241 15:36:25.761496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 15:36:25.761587 ==
4243 15:36:25.764343 RX Vref Scan: 0
4244 15:36:25.764428
4245 15:36:25.767839 RX Vref 0 -> 0, step: 1
4246 15:36:25.767923
4247 15:36:25.767984 RX Delay -230 -> 252, step: 16
4248 15:36:25.774537 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4249 15:36:25.777762 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4250 15:36:25.781259 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4251 15:36:25.784533 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4252 15:36:25.791382 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4253 15:36:25.794434 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4254 15:36:25.798023 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4255 15:36:25.801037 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4256 15:36:25.804680 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4257 15:36:25.811868 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4258 15:36:25.814765 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4259 15:36:25.818064 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4260 15:36:25.821149 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4261 15:36:25.827766 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4262 15:36:25.831149 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4263 15:36:25.834730 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4264 15:36:25.834815 ==
4265 15:36:25.837954 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 15:36:25.841414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 15:36:25.841500 ==
4268 15:36:25.844709 DQS Delay:
4269 15:36:25.844793 DQS0 = 0, DQS1 = 0
4270 15:36:25.848212 DQM Delay:
4271 15:36:25.848295 DQM0 = 39, DQM1 = 31
4272 15:36:25.848381 DQ Delay:
4273 15:36:25.851307 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4274 15:36:25.854511 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4275 15:36:25.858298 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4276 15:36:25.861715 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4277 15:36:25.861799
4278 15:36:25.861883
4279 15:36:25.861963 ==
4280 15:36:25.864783 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 15:36:25.871426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 15:36:25.871510 ==
4283 15:36:25.871596
4284 15:36:25.871676
4285 15:36:25.871754 TX Vref Scan disable
4286 15:36:25.875107 == TX Byte 0 ==
4287 15:36:25.878757 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4288 15:36:25.885354 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4289 15:36:25.885439 == TX Byte 1 ==
4290 15:36:25.888574 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4291 15:36:25.895094 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4292 15:36:25.895178 ==
4293 15:36:25.898563 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 15:36:25.902067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 15:36:25.902152 ==
4296 15:36:25.902237
4297 15:36:25.902318
4298 15:36:25.905113 TX Vref Scan disable
4299 15:36:25.908350 == TX Byte 0 ==
4300 15:36:25.911575 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4301 15:36:25.915097 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4302 15:36:25.918377 == TX Byte 1 ==
4303 15:36:25.921674 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4304 15:36:25.925509 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4305 15:36:25.925600
4306 15:36:25.925664 [DATLAT]
4307 15:36:25.928295 Freq=600, CH0 RK1
4308 15:36:25.928376
4309 15:36:25.928439 DATLAT Default: 0x9
4310 15:36:25.931605 0, 0xFFFF, sum = 0
4311 15:36:25.931691 1, 0xFFFF, sum = 0
4312 15:36:25.935038 2, 0xFFFF, sum = 0
4313 15:36:25.938281 3, 0xFFFF, sum = 0
4314 15:36:25.938363 4, 0xFFFF, sum = 0
4315 15:36:25.941907 5, 0xFFFF, sum = 0
4316 15:36:25.941989 6, 0xFFFF, sum = 0
4317 15:36:25.945114 7, 0xFFFF, sum = 0
4318 15:36:25.945197 8, 0x0, sum = 1
4319 15:36:25.945261 9, 0x0, sum = 2
4320 15:36:25.948374 10, 0x0, sum = 3
4321 15:36:25.948489 11, 0x0, sum = 4
4322 15:36:25.951877 best_step = 9
4323 15:36:25.951957
4324 15:36:25.952021 ==
4325 15:36:25.955142 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 15:36:25.958484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 15:36:25.958565 ==
4328 15:36:25.961757 RX Vref Scan: 0
4329 15:36:25.961837
4330 15:36:25.961900 RX Vref 0 -> 0, step: 1
4331 15:36:25.961959
4332 15:36:25.964909 RX Delay -195 -> 252, step: 8
4333 15:36:25.972286 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4334 15:36:25.975976 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4335 15:36:25.978810 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4336 15:36:25.982327 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4337 15:36:25.989262 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4338 15:36:25.992556 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4339 15:36:25.995628 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4340 15:36:25.998807 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4341 15:36:26.002722 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4342 15:36:26.009209 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4343 15:36:26.012202 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4344 15:36:26.015698 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4345 15:36:26.019021 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4346 15:36:26.025698 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4347 15:36:26.029029 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4348 15:36:26.032369 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4349 15:36:26.032449 ==
4350 15:36:26.035890 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 15:36:26.038940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 15:36:26.039027 ==
4353 15:36:26.042543 DQS Delay:
4354 15:36:26.042628 DQS0 = 0, DQS1 = 0
4355 15:36:26.045462 DQM Delay:
4356 15:36:26.045546 DQM0 = 40, DQM1 = 32
4357 15:36:26.045649 DQ Delay:
4358 15:36:26.049252 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4359 15:36:26.052330 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4360 15:36:26.055723 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =20
4361 15:36:26.058874 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4362 15:36:26.058958
4363 15:36:26.059043
4364 15:36:26.068937 [DQSOSCAuto] RK1, (LSB)MR18= 0x5132, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4365 15:36:26.072463 CH0 RK1: MR19=808, MR18=5132
4366 15:36:26.078889 CH0_RK1: MR19=0x808, MR18=0x5132, DQSOSC=394, MR23=63, INC=168, DEC=112
4367 15:36:26.078974 [RxdqsGatingPostProcess] freq 600
4368 15:36:26.085622 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4369 15:36:26.088817 Pre-setting of DQS Precalculation
4370 15:36:26.092511 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4371 15:36:26.092639 ==
4372 15:36:26.095610 Dram Type= 6, Freq= 0, CH_1, rank 0
4373 15:36:26.102672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 15:36:26.102751 ==
4375 15:36:26.106006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 15:36:26.112344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4377 15:36:26.116176 [CA 0] Center 35 (5~66) winsize 62
4378 15:36:26.119110 [CA 1] Center 35 (5~66) winsize 62
4379 15:36:26.122308 [CA 2] Center 33 (3~64) winsize 62
4380 15:36:26.126090 [CA 3] Center 33 (3~64) winsize 62
4381 15:36:26.129443 [CA 4] Center 33 (3~64) winsize 62
4382 15:36:26.132524 [CA 5] Center 33 (3~64) winsize 62
4383 15:36:26.132637
4384 15:36:26.135953 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4385 15:36:26.136024
4386 15:36:26.139071 [CATrainingPosCal] consider 1 rank data
4387 15:36:26.142835 u2DelayCellTimex100 = 270/100 ps
4388 15:36:26.146200 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4389 15:36:26.149063 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4390 15:36:26.152625 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4391 15:36:26.159368 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4392 15:36:26.162416 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4393 15:36:26.166348 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4394 15:36:26.166432
4395 15:36:26.168984 CA PerBit enable=1, Macro0, CA PI delay=33
4396 15:36:26.169071
4397 15:36:26.172689 [CBTSetCACLKResult] CA Dly = 33
4398 15:36:26.172770 CS Dly: 5 (0~36)
4399 15:36:26.172833 ==
4400 15:36:26.175883 Dram Type= 6, Freq= 0, CH_1, rank 1
4401 15:36:26.182662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 15:36:26.182764 ==
4403 15:36:26.185929 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4404 15:36:26.192322 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4405 15:36:26.195820 [CA 0] Center 35 (5~66) winsize 62
4406 15:36:26.199566 [CA 1] Center 35 (5~66) winsize 62
4407 15:36:26.202492 [CA 2] Center 34 (4~65) winsize 62
4408 15:36:26.206022 [CA 3] Center 34 (3~65) winsize 63
4409 15:36:26.209512 [CA 4] Center 34 (4~65) winsize 62
4410 15:36:26.212505 [CA 5] Center 33 (3~64) winsize 62
4411 15:36:26.212589
4412 15:36:26.215816 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4413 15:36:26.215900
4414 15:36:26.219383 [CATrainingPosCal] consider 2 rank data
4415 15:36:26.222535 u2DelayCellTimex100 = 270/100 ps
4416 15:36:26.226160 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4417 15:36:26.229218 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4418 15:36:26.236264 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4419 15:36:26.239550 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 15:36:26.242392 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4421 15:36:26.246093 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4422 15:36:26.246175
4423 15:36:26.249126 CA PerBit enable=1, Macro0, CA PI delay=33
4424 15:36:26.249199
4425 15:36:26.252613 [CBTSetCACLKResult] CA Dly = 33
4426 15:36:26.252751 CS Dly: 5 (0~37)
4427 15:36:26.252817
4428 15:36:26.256208 ----->DramcWriteLeveling(PI) begin...
4429 15:36:26.259093 ==
4430 15:36:26.259168 Dram Type= 6, Freq= 0, CH_1, rank 0
4431 15:36:26.266291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 15:36:26.266379 ==
4433 15:36:26.269471 Write leveling (Byte 0): 30 => 30
4434 15:36:26.273166 Write leveling (Byte 1): 30 => 30
4435 15:36:26.275949 DramcWriteLeveling(PI) end<-----
4436 15:36:26.276022
4437 15:36:26.276118 ==
4438 15:36:26.279353 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 15:36:26.282443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 15:36:26.282520 ==
4441 15:36:26.285745 [Gating] SW mode calibration
4442 15:36:26.292571 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4443 15:36:26.295963 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4444 15:36:26.302995 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 15:36:26.305988 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4446 15:36:26.309383 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4447 15:36:26.316176 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 0)
4448 15:36:26.319258 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4449 15:36:26.323281 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 15:36:26.329279 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 15:36:26.333026 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 15:36:26.336051 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 15:36:26.342725 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 15:36:26.346350 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 15:36:26.349687 0 10 12 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
4456 15:36:26.353034 0 10 16 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
4457 15:36:26.359905 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 15:36:26.362935 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 15:36:26.366239 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 15:36:26.373404 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 15:36:26.376358 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 15:36:26.380565 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 15:36:26.386722 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4464 15:36:26.389804 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4465 15:36:26.393260 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 15:36:26.399975 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 15:36:26.403145 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 15:36:26.406594 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 15:36:26.413067 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 15:36:26.416454 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 15:36:26.420535 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 15:36:26.423159 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 15:36:26.429956 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 15:36:26.433670 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 15:36:26.436697 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 15:36:26.443604 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 15:36:26.447115 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 15:36:26.449891 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 15:36:26.456922 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 15:36:26.459835 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 15:36:26.463757 Total UI for P1: 0, mck2ui 16
4482 15:36:26.467020 best dqsien dly found for B0: ( 0, 13, 14)
4483 15:36:26.469961 Total UI for P1: 0, mck2ui 16
4484 15:36:26.473519 best dqsien dly found for B1: ( 0, 13, 14)
4485 15:36:26.476814 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4486 15:36:26.480100 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4487 15:36:26.480199
4488 15:36:26.484196 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4489 15:36:26.487329 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4490 15:36:26.490498 [Gating] SW calibration Done
4491 15:36:26.490570 ==
4492 15:36:26.493366 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 15:36:26.496683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 15:36:26.500569 ==
4495 15:36:26.500676 RX Vref Scan: 0
4496 15:36:26.500757
4497 15:36:26.503381 RX Vref 0 -> 0, step: 1
4498 15:36:26.503529
4499 15:36:26.506690 RX Delay -230 -> 252, step: 16
4500 15:36:26.510040 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4501 15:36:26.513327 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4502 15:36:26.516600 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4503 15:36:26.519874 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4504 15:36:26.526565 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4505 15:36:26.529782 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4506 15:36:26.533466 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4507 15:36:26.536519 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4508 15:36:26.543386 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4509 15:36:26.546587 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4510 15:36:26.550259 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4511 15:36:26.553593 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4512 15:36:26.557347 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4513 15:36:26.563331 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4514 15:36:26.567031 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4515 15:36:26.570455 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4516 15:36:26.570572 ==
4517 15:36:26.573425 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 15:36:26.577203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 15:36:26.580075 ==
4520 15:36:26.580150 DQS Delay:
4521 15:36:26.580213 DQS0 = 0, DQS1 = 0
4522 15:36:26.583442 DQM Delay:
4523 15:36:26.583527 DQM0 = 45, DQM1 = 34
4524 15:36:26.586672 DQ Delay:
4525 15:36:26.586749 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4526 15:36:26.590483 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4527 15:36:26.593717 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4528 15:36:26.596846 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4529 15:36:26.596982
4530 15:36:26.597074
4531 15:36:26.600393 ==
4532 15:36:26.603415 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 15:36:26.606708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 15:36:26.606809 ==
4535 15:36:26.606904
4536 15:36:26.606993
4537 15:36:26.610169 TX Vref Scan disable
4538 15:36:26.610271 == TX Byte 0 ==
4539 15:36:26.617034 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4540 15:36:26.620584 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4541 15:36:26.620709 == TX Byte 1 ==
4542 15:36:26.623843 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4543 15:36:26.630520 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4544 15:36:26.630613 ==
4545 15:36:26.633567 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 15:36:26.637164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 15:36:26.637236 ==
4548 15:36:26.637298
4549 15:36:26.637359
4550 15:36:26.640584 TX Vref Scan disable
4551 15:36:26.644034 == TX Byte 0 ==
4552 15:36:26.647153 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4553 15:36:26.650570 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4554 15:36:26.653599 == TX Byte 1 ==
4555 15:36:26.657230 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4556 15:36:26.660379 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4557 15:36:26.660450
4558 15:36:26.663711 [DATLAT]
4559 15:36:26.663784 Freq=600, CH1 RK0
4560 15:36:26.663846
4561 15:36:26.667088 DATLAT Default: 0x9
4562 15:36:26.667185 0, 0xFFFF, sum = 0
4563 15:36:26.670923 1, 0xFFFF, sum = 0
4564 15:36:26.671020 2, 0xFFFF, sum = 0
4565 15:36:26.673724 3, 0xFFFF, sum = 0
4566 15:36:26.673800 4, 0xFFFF, sum = 0
4567 15:36:26.677359 5, 0xFFFF, sum = 0
4568 15:36:26.677433 6, 0xFFFF, sum = 0
4569 15:36:26.680263 7, 0xFFFF, sum = 0
4570 15:36:26.680337 8, 0x0, sum = 1
4571 15:36:26.683680 9, 0x0, sum = 2
4572 15:36:26.683757 10, 0x0, sum = 3
4573 15:36:26.687070 11, 0x0, sum = 4
4574 15:36:26.687168 best_step = 9
4575 15:36:26.687255
4576 15:36:26.687343 ==
4577 15:36:26.690360 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 15:36:26.694084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 15:36:26.694155 ==
4580 15:36:26.697448 RX Vref Scan: 1
4581 15:36:26.697543
4582 15:36:26.700777 RX Vref 0 -> 0, step: 1
4583 15:36:26.700849
4584 15:36:26.700909 RX Delay -195 -> 252, step: 8
4585 15:36:26.700967
4586 15:36:26.703969 Set Vref, RX VrefLevel [Byte0]: 58
4587 15:36:26.707190 [Byte1]: 52
4588 15:36:26.711730
4589 15:36:26.711809 Final RX Vref Byte 0 = 58 to rank0
4590 15:36:26.715099 Final RX Vref Byte 1 = 52 to rank0
4591 15:36:26.718503 Final RX Vref Byte 0 = 58 to rank1
4592 15:36:26.721571 Final RX Vref Byte 1 = 52 to rank1==
4593 15:36:26.725219 Dram Type= 6, Freq= 0, CH_1, rank 0
4594 15:36:26.731734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 15:36:26.731808 ==
4596 15:36:26.731891 DQS Delay:
4597 15:36:26.731984 DQS0 = 0, DQS1 = 0
4598 15:36:26.735149 DQM Delay:
4599 15:36:26.735217 DQM0 = 40, DQM1 = 32
4600 15:36:26.738337 DQ Delay:
4601 15:36:26.741633 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4602 15:36:26.741712 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4603 15:36:26.745258 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4604 15:36:26.748680 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4605 15:36:26.751878
4606 15:36:26.751951
4607 15:36:26.758291 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c11, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
4608 15:36:26.761709 CH1 RK0: MR19=808, MR18=4C11
4609 15:36:26.768341 CH1_RK0: MR19=0x808, MR18=0x4C11, DQSOSC=395, MR23=63, INC=168, DEC=112
4610 15:36:26.768415
4611 15:36:26.772474 ----->DramcWriteLeveling(PI) begin...
4612 15:36:26.772546 ==
4613 15:36:26.775027 Dram Type= 6, Freq= 0, CH_1, rank 1
4614 15:36:26.778633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 15:36:26.778741 ==
4616 15:36:26.781891 Write leveling (Byte 0): 29 => 29
4617 15:36:26.785497 Write leveling (Byte 1): 31 => 31
4618 15:36:26.788469 DramcWriteLeveling(PI) end<-----
4619 15:36:26.788567
4620 15:36:26.788657 ==
4621 15:36:26.791811 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 15:36:26.795083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 15:36:26.795193 ==
4624 15:36:26.798472 [Gating] SW mode calibration
4625 15:36:26.805624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4626 15:36:26.812072 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4627 15:36:26.815155 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 15:36:26.818860 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4629 15:36:26.825559 0 9 8 | B1->B0 | 3535 3333 | 1 1 | (0 0) (1 0)
4630 15:36:26.828300 0 9 12 | B1->B0 | 3131 2929 | 1 0 | (1 0) (1 1)
4631 15:36:26.831862 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4632 15:36:26.838692 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4633 15:36:26.842036 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 15:36:26.845276 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4635 15:36:26.851873 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4636 15:36:26.855290 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4637 15:36:26.858849 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 15:36:26.861961 0 10 12 | B1->B0 | 2f2f 3939 | 1 0 | (0 0) (0 0)
4639 15:36:26.869029 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 15:36:26.872080 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 15:36:26.875621 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 15:36:26.882069 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 15:36:26.885265 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 15:36:26.888815 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 15:36:26.895780 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 15:36:26.898480 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4647 15:36:26.902363 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 15:36:26.909016 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 15:36:26.911940 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 15:36:26.915620 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 15:36:26.922132 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 15:36:26.925297 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 15:36:26.928782 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 15:36:26.932222 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 15:36:26.939358 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 15:36:26.942026 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 15:36:26.945496 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 15:36:26.952456 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 15:36:26.955316 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 15:36:26.959025 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 15:36:26.965888 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4662 15:36:26.968630 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4663 15:36:26.972261 Total UI for P1: 0, mck2ui 16
4664 15:36:26.975253 best dqsien dly found for B0: ( 0, 13, 8)
4665 15:36:26.978826 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 15:36:26.982154 Total UI for P1: 0, mck2ui 16
4667 15:36:26.985676 best dqsien dly found for B1: ( 0, 13, 12)
4668 15:36:26.988849 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4669 15:36:26.992586 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4670 15:36:26.992697
4671 15:36:26.999088 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4672 15:36:27.002064 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4673 15:36:27.002167 [Gating] SW calibration Done
4674 15:36:27.005505 ==
4675 15:36:27.005601 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 15:36:27.012416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 15:36:27.012494 ==
4678 15:36:27.012596 RX Vref Scan: 0
4679 15:36:27.012690
4680 15:36:27.015922 RX Vref 0 -> 0, step: 1
4681 15:36:27.016018
4682 15:36:27.019391 RX Delay -230 -> 252, step: 16
4683 15:36:27.022176 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4684 15:36:27.025670 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4685 15:36:27.032236 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4686 15:36:27.035852 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4687 15:36:27.038966 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4688 15:36:27.042572 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4689 15:36:27.045721 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4690 15:36:27.052381 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4691 15:36:27.055839 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4692 15:36:27.058825 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4693 15:36:27.062667 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4694 15:36:27.065950 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4695 15:36:27.072708 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4696 15:36:27.075674 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4697 15:36:27.079196 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4698 15:36:27.082288 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4699 15:36:27.085477 ==
4700 15:36:27.089262 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 15:36:27.092605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 15:36:27.092706 ==
4703 15:36:27.092771 DQS Delay:
4704 15:36:27.095645 DQS0 = 0, DQS1 = 0
4705 15:36:27.095743 DQM Delay:
4706 15:36:27.098927 DQM0 = 40, DQM1 = 34
4707 15:36:27.099025 DQ Delay:
4708 15:36:27.102531 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4709 15:36:27.106214 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4710 15:36:27.108954 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4711 15:36:27.112615 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4712 15:36:27.112712
4713 15:36:27.112777
4714 15:36:27.112841 ==
4715 15:36:27.115709 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 15:36:27.119269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 15:36:27.119370 ==
4718 15:36:27.119464
4719 15:36:27.119565
4720 15:36:27.122410 TX Vref Scan disable
4721 15:36:27.125822 == TX Byte 0 ==
4722 15:36:27.128975 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4723 15:36:27.132211 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4724 15:36:27.135731 == TX Byte 1 ==
4725 15:36:27.138985 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4726 15:36:27.142530 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4727 15:36:27.142610 ==
4728 15:36:27.146273 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 15:36:27.149500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 15:36:27.149575 ==
4731 15:36:27.149645
4732 15:36:27.152409
4733 15:36:27.152484 TX Vref Scan disable
4734 15:36:27.156212 == TX Byte 0 ==
4735 15:36:27.159605 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4736 15:36:27.162613 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4737 15:36:27.165928 == TX Byte 1 ==
4738 15:36:27.169854 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4739 15:36:27.172760 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4740 15:36:27.176109
4741 15:36:27.176208 [DATLAT]
4742 15:36:27.176301 Freq=600, CH1 RK1
4743 15:36:27.176392
4744 15:36:27.179423 DATLAT Default: 0x9
4745 15:36:27.179523 0, 0xFFFF, sum = 0
4746 15:36:27.182832 1, 0xFFFF, sum = 0
4747 15:36:27.182931 2, 0xFFFF, sum = 0
4748 15:36:27.186278 3, 0xFFFF, sum = 0
4749 15:36:27.186350 4, 0xFFFF, sum = 0
4750 15:36:27.189640 5, 0xFFFF, sum = 0
4751 15:36:27.189712 6, 0xFFFF, sum = 0
4752 15:36:27.193617 7, 0xFFFF, sum = 0
4753 15:36:27.193688 8, 0x0, sum = 1
4754 15:36:27.196313 9, 0x0, sum = 2
4755 15:36:27.196384 10, 0x0, sum = 3
4756 15:36:27.199715 11, 0x0, sum = 4
4757 15:36:27.199787 best_step = 9
4758 15:36:27.199866
4759 15:36:27.199965 ==
4760 15:36:27.202987 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 15:36:27.209510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 15:36:27.209647 ==
4763 15:36:27.209740 RX Vref Scan: 0
4764 15:36:27.209827
4765 15:36:27.212961 RX Vref 0 -> 0, step: 1
4766 15:36:27.213034
4767 15:36:27.216585 RX Delay -195 -> 252, step: 8
4768 15:36:27.219505 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4769 15:36:27.222868 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4770 15:36:27.229584 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4771 15:36:27.233107 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4772 15:36:27.236308 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4773 15:36:27.239830 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4774 15:36:27.246483 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4775 15:36:27.249611 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4776 15:36:27.252903 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4777 15:36:27.256212 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4778 15:36:27.259310 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4779 15:36:27.266217 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4780 15:36:27.269709 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4781 15:36:27.273302 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4782 15:36:27.276397 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4783 15:36:27.282798 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4784 15:36:27.282873 ==
4785 15:36:27.285935 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 15:36:27.289738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 15:36:27.289823 ==
4788 15:36:27.289887 DQS Delay:
4789 15:36:27.293342 DQS0 = 0, DQS1 = 0
4790 15:36:27.293415 DQM Delay:
4791 15:36:27.296286 DQM0 = 38, DQM1 = 33
4792 15:36:27.296374 DQ Delay:
4793 15:36:27.299411 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4794 15:36:27.302642 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4795 15:36:27.306178 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4796 15:36:27.309578 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4797 15:36:27.309678
4798 15:36:27.309818
4799 15:36:27.319589 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e4c, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4800 15:36:27.319668 CH1 RK1: MR19=808, MR18=3E4C
4801 15:36:27.326353 CH1_RK1: MR19=0x808, MR18=0x3E4C, DQSOSC=395, MR23=63, INC=168, DEC=112
4802 15:36:27.329352 [RxdqsGatingPostProcess] freq 600
4803 15:36:27.336240 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4804 15:36:27.339749 Pre-setting of DQS Precalculation
4805 15:36:27.343689 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4806 15:36:27.349582 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4807 15:36:27.356104 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4808 15:36:27.356187
4809 15:36:27.356252
4810 15:36:27.359738 [Calibration Summary] 1200 Mbps
4811 15:36:27.362726 CH 0, Rank 0
4812 15:36:27.362828 SW Impedance : PASS
4813 15:36:27.366580 DUTY Scan : NO K
4814 15:36:27.369576 ZQ Calibration : PASS
4815 15:36:27.369653 Jitter Meter : NO K
4816 15:36:27.372958 CBT Training : PASS
4817 15:36:27.376575 Write leveling : PASS
4818 15:36:27.376661 RX DQS gating : PASS
4819 15:36:27.379574 RX DQ/DQS(RDDQC) : PASS
4820 15:36:27.379658 TX DQ/DQS : PASS
4821 15:36:27.383349 RX DATLAT : PASS
4822 15:36:27.386279 RX DQ/DQS(Engine): PASS
4823 15:36:27.386363 TX OE : NO K
4824 15:36:27.390028 All Pass.
4825 15:36:27.390110
4826 15:36:27.390176 CH 0, Rank 1
4827 15:36:27.393061 SW Impedance : PASS
4828 15:36:27.393137 DUTY Scan : NO K
4829 15:36:27.396593 ZQ Calibration : PASS
4830 15:36:27.400139 Jitter Meter : NO K
4831 15:36:27.400257 CBT Training : PASS
4832 15:36:27.403053 Write leveling : PASS
4833 15:36:27.406659 RX DQS gating : PASS
4834 15:36:27.406754 RX DQ/DQS(RDDQC) : PASS
4835 15:36:27.409776 TX DQ/DQS : PASS
4836 15:36:27.413331 RX DATLAT : PASS
4837 15:36:27.413402 RX DQ/DQS(Engine): PASS
4838 15:36:27.416188 TX OE : NO K
4839 15:36:27.416281 All Pass.
4840 15:36:27.416371
4841 15:36:27.419610 CH 1, Rank 0
4842 15:36:27.419705 SW Impedance : PASS
4843 15:36:27.423284 DUTY Scan : NO K
4844 15:36:27.423378 ZQ Calibration : PASS
4845 15:36:27.426309 Jitter Meter : NO K
4846 15:36:27.429753 CBT Training : PASS
4847 15:36:27.429825 Write leveling : PASS
4848 15:36:27.432966 RX DQS gating : PASS
4849 15:36:27.436452 RX DQ/DQS(RDDQC) : PASS
4850 15:36:27.436557 TX DQ/DQS : PASS
4851 15:36:27.439971 RX DATLAT : PASS
4852 15:36:27.443393 RX DQ/DQS(Engine): PASS
4853 15:36:27.443496 TX OE : NO K
4854 15:36:27.446327 All Pass.
4855 15:36:27.446424
4856 15:36:27.446524 CH 1, Rank 1
4857 15:36:27.449710 SW Impedance : PASS
4858 15:36:27.449783 DUTY Scan : NO K
4859 15:36:27.452984 ZQ Calibration : PASS
4860 15:36:27.456345 Jitter Meter : NO K
4861 15:36:27.456444 CBT Training : PASS
4862 15:36:27.459811 Write leveling : PASS
4863 15:36:27.463006 RX DQS gating : PASS
4864 15:36:27.463101 RX DQ/DQS(RDDQC) : PASS
4865 15:36:27.466533 TX DQ/DQS : PASS
4866 15:36:27.466628 RX DATLAT : PASS
4867 15:36:27.469755 RX DQ/DQS(Engine): PASS
4868 15:36:27.472996 TX OE : NO K
4869 15:36:27.473070 All Pass.
4870 15:36:27.473131
4871 15:36:27.476476 DramC Write-DBI off
4872 15:36:27.476574 PER_BANK_REFRESH: Hybrid Mode
4873 15:36:27.479970 TX_TRACKING: ON
4874 15:36:27.489881 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4875 15:36:27.492778 [FAST_K] Save calibration result to emmc
4876 15:36:27.496265 dramc_set_vcore_voltage set vcore to 662500
4877 15:36:27.496426 Read voltage for 933, 3
4878 15:36:27.499467 Vio18 = 0
4879 15:36:27.499577 Vcore = 662500
4880 15:36:27.499669 Vdram = 0
4881 15:36:27.502843 Vddq = 0
4882 15:36:27.502930 Vmddr = 0
4883 15:36:27.506303 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4884 15:36:27.513070 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4885 15:36:27.516750 MEM_TYPE=3, freq_sel=17
4886 15:36:27.519484 sv_algorithm_assistance_LP4_1600
4887 15:36:27.523043 ============ PULL DRAM RESETB DOWN ============
4888 15:36:27.526276 ========== PULL DRAM RESETB DOWN end =========
4889 15:36:27.532922 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4890 15:36:27.536164 ===================================
4891 15:36:27.536265 LPDDR4 DRAM CONFIGURATION
4892 15:36:27.539748 ===================================
4893 15:36:27.543133 EX_ROW_EN[0] = 0x0
4894 15:36:27.543246 EX_ROW_EN[1] = 0x0
4895 15:36:27.546582 LP4Y_EN = 0x0
4896 15:36:27.546659 WORK_FSP = 0x0
4897 15:36:27.549709 WL = 0x3
4898 15:36:27.549814 RL = 0x3
4899 15:36:27.553228 BL = 0x2
4900 15:36:27.553314 RPST = 0x0
4901 15:36:27.556793 RD_PRE = 0x0
4902 15:36:27.556877 WR_PRE = 0x1
4903 15:36:27.559959 WR_PST = 0x0
4904 15:36:27.560097 DBI_WR = 0x0
4905 15:36:27.563064 DBI_RD = 0x0
4906 15:36:27.566657 OTF = 0x1
4907 15:36:27.569631 ===================================
4908 15:36:27.569754 ===================================
4909 15:36:27.573107 ANA top config
4910 15:36:27.576477 ===================================
4911 15:36:27.579669 DLL_ASYNC_EN = 0
4912 15:36:27.579775 ALL_SLAVE_EN = 1
4913 15:36:27.583336 NEW_RANK_MODE = 1
4914 15:36:27.587022 DLL_IDLE_MODE = 1
4915 15:36:27.590183 LP45_APHY_COMB_EN = 1
4916 15:36:27.593397 TX_ODT_DIS = 1
4917 15:36:27.593495 NEW_8X_MODE = 1
4918 15:36:27.597574 ===================================
4919 15:36:27.599841 ===================================
4920 15:36:27.603236 data_rate = 1866
4921 15:36:27.606369 CKR = 1
4922 15:36:27.610071 DQ_P2S_RATIO = 8
4923 15:36:27.613389 ===================================
4924 15:36:27.616829 CA_P2S_RATIO = 8
4925 15:36:27.616932 DQ_CA_OPEN = 0
4926 15:36:27.619809 DQ_SEMI_OPEN = 0
4927 15:36:27.623250 CA_SEMI_OPEN = 0
4928 15:36:27.626839 CA_FULL_RATE = 0
4929 15:36:27.629987 DQ_CKDIV4_EN = 1
4930 15:36:27.633372 CA_CKDIV4_EN = 1
4931 15:36:27.633473 CA_PREDIV_EN = 0
4932 15:36:27.636599 PH8_DLY = 0
4933 15:36:27.640526 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4934 15:36:27.643809 DQ_AAMCK_DIV = 4
4935 15:36:27.646781 CA_AAMCK_DIV = 4
4936 15:36:27.646856 CA_ADMCK_DIV = 4
4937 15:36:27.650396 DQ_TRACK_CA_EN = 0
4938 15:36:27.653993 CA_PICK = 933
4939 15:36:27.657175 CA_MCKIO = 933
4940 15:36:27.661008 MCKIO_SEMI = 0
4941 15:36:27.663641 PLL_FREQ = 3732
4942 15:36:27.667398 DQ_UI_PI_RATIO = 32
4943 15:36:27.667484 CA_UI_PI_RATIO = 0
4944 15:36:27.670224 ===================================
4945 15:36:27.673758 ===================================
4946 15:36:27.677053 memory_type:LPDDR4
4947 15:36:27.680444 GP_NUM : 10
4948 15:36:27.680528 SRAM_EN : 1
4949 15:36:27.683977 MD32_EN : 0
4950 15:36:27.687334 ===================================
4951 15:36:27.690271 [ANA_INIT] >>>>>>>>>>>>>>
4952 15:36:27.690355 <<<<<< [CONFIGURE PHASE]: ANA_TX
4953 15:36:27.696916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4954 15:36:27.697000 ===================================
4955 15:36:27.700347 data_rate = 1866,PCW = 0X8f00
4956 15:36:27.703705 ===================================
4957 15:36:27.707611 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4958 15:36:27.714257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4959 15:36:27.720879 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4960 15:36:27.723890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4961 15:36:27.727178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4962 15:36:27.731021 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4963 15:36:27.733875 [ANA_INIT] flow start
4964 15:36:27.733964 [ANA_INIT] PLL >>>>>>>>
4965 15:36:27.737216 [ANA_INIT] PLL <<<<<<<<
4966 15:36:27.741096 [ANA_INIT] MIDPI >>>>>>>>
4967 15:36:27.741175 [ANA_INIT] MIDPI <<<<<<<<
4968 15:36:27.744345 [ANA_INIT] DLL >>>>>>>>
4969 15:36:27.747329 [ANA_INIT] flow end
4970 15:36:27.750828 ============ LP4 DIFF to SE enter ============
4971 15:36:27.754028 ============ LP4 DIFF to SE exit ============
4972 15:36:27.757352 [ANA_INIT] <<<<<<<<<<<<<
4973 15:36:27.760953 [Flow] Enable top DCM control >>>>>
4974 15:36:27.764001 [Flow] Enable top DCM control <<<<<
4975 15:36:27.767524 Enable DLL master slave shuffle
4976 15:36:27.770671 ==============================================================
4977 15:36:27.774385 Gating Mode config
4978 15:36:27.781047 ==============================================================
4979 15:36:27.781116 Config description:
4980 15:36:27.790811 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4981 15:36:27.797396 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4982 15:36:27.800717 SELPH_MODE 0: By rank 1: By Phase
4983 15:36:27.807266 ==============================================================
4984 15:36:27.810725 GAT_TRACK_EN = 1
4985 15:36:27.814339 RX_GATING_MODE = 2
4986 15:36:27.817307 RX_GATING_TRACK_MODE = 2
4987 15:36:27.820779 SELPH_MODE = 1
4988 15:36:27.824162 PICG_EARLY_EN = 1
4989 15:36:27.824282 VALID_LAT_VALUE = 1
4990 15:36:27.830695 ==============================================================
4991 15:36:27.834438 Enter into Gating configuration >>>>
4992 15:36:27.837583 Exit from Gating configuration <<<<
4993 15:36:27.840824 Enter into DVFS_PRE_config >>>>>
4994 15:36:27.851567 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4995 15:36:27.854516 Exit from DVFS_PRE_config <<<<<
4996 15:36:27.858042 Enter into PICG configuration >>>>
4997 15:36:27.861337 Exit from PICG configuration <<<<
4998 15:36:27.864290 [RX_INPUT] configuration >>>>>
4999 15:36:27.867602 [RX_INPUT] configuration <<<<<
5000 15:36:27.871244 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5001 15:36:27.878004 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5002 15:36:27.884443 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 15:36:27.891021 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 15:36:27.894657 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5005 15:36:27.901245 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5006 15:36:27.904782 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5007 15:36:27.911276 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5008 15:36:27.914557 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5009 15:36:27.917989 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5010 15:36:27.921039 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5011 15:36:27.928092 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5012 15:36:27.932133 ===================================
5013 15:36:27.932257 LPDDR4 DRAM CONFIGURATION
5014 15:36:27.934890 ===================================
5015 15:36:27.937917 EX_ROW_EN[0] = 0x0
5016 15:36:27.941835 EX_ROW_EN[1] = 0x0
5017 15:36:27.941940 LP4Y_EN = 0x0
5018 15:36:27.944779 WORK_FSP = 0x0
5019 15:36:27.944857 WL = 0x3
5020 15:36:27.948046 RL = 0x3
5021 15:36:27.948148 BL = 0x2
5022 15:36:27.951512 RPST = 0x0
5023 15:36:27.951618 RD_PRE = 0x0
5024 15:36:27.954722 WR_PRE = 0x1
5025 15:36:27.954819 WR_PST = 0x0
5026 15:36:27.958019 DBI_WR = 0x0
5027 15:36:27.958095 DBI_RD = 0x0
5028 15:36:27.961314 OTF = 0x1
5029 15:36:27.964453 ===================================
5030 15:36:27.968001 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5031 15:36:27.971303 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5032 15:36:27.978105 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5033 15:36:27.981278 ===================================
5034 15:36:27.981351 LPDDR4 DRAM CONFIGURATION
5035 15:36:27.984661 ===================================
5036 15:36:27.988013 EX_ROW_EN[0] = 0x10
5037 15:36:27.988114 EX_ROW_EN[1] = 0x0
5038 15:36:27.991369 LP4Y_EN = 0x0
5039 15:36:27.991473 WORK_FSP = 0x0
5040 15:36:27.994657 WL = 0x3
5041 15:36:27.998269 RL = 0x3
5042 15:36:27.998366 BL = 0x2
5043 15:36:28.001499 RPST = 0x0
5044 15:36:28.001598 RD_PRE = 0x0
5045 15:36:28.004853 WR_PRE = 0x1
5046 15:36:28.004954 WR_PST = 0x0
5047 15:36:28.007987 DBI_WR = 0x0
5048 15:36:28.008060 DBI_RD = 0x0
5049 15:36:28.011509 OTF = 0x1
5050 15:36:28.014728 ===================================
5051 15:36:28.021491 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5052 15:36:28.024769 nWR fixed to 30
5053 15:36:28.024868 [ModeRegInit_LP4] CH0 RK0
5054 15:36:28.027833 [ModeRegInit_LP4] CH0 RK1
5055 15:36:28.031262 [ModeRegInit_LP4] CH1 RK0
5056 15:36:28.031358 [ModeRegInit_LP4] CH1 RK1
5057 15:36:28.034703 match AC timing 9
5058 15:36:28.037905 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5059 15:36:28.041258 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5060 15:36:28.048012 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5061 15:36:28.051093 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5062 15:36:28.057685 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5063 15:36:28.057786 ==
5064 15:36:28.061579 Dram Type= 6, Freq= 0, CH_0, rank 0
5065 15:36:28.065122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 15:36:28.065229 ==
5067 15:36:28.071167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 15:36:28.074648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5069 15:36:28.078745 [CA 0] Center 38 (8~69) winsize 62
5070 15:36:28.081976 [CA 1] Center 38 (7~69) winsize 63
5071 15:36:28.085459 [CA 2] Center 35 (5~66) winsize 62
5072 15:36:28.088766 [CA 3] Center 35 (4~66) winsize 63
5073 15:36:28.092239 [CA 4] Center 34 (4~65) winsize 62
5074 15:36:28.095613 [CA 5] Center 33 (3~64) winsize 62
5075 15:36:28.095717
5076 15:36:28.099053 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5077 15:36:28.099152
5078 15:36:28.102125 [CATrainingPosCal] consider 1 rank data
5079 15:36:28.105582 u2DelayCellTimex100 = 270/100 ps
5080 15:36:28.109248 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5081 15:36:28.112632 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5082 15:36:28.115663 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5083 15:36:28.122860 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5084 15:36:28.126061 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5085 15:36:28.129085 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5086 15:36:28.129169
5087 15:36:28.132413 CA PerBit enable=1, Macro0, CA PI delay=33
5088 15:36:28.132497
5089 15:36:28.135980 [CBTSetCACLKResult] CA Dly = 33
5090 15:36:28.136064 CS Dly: 6 (0~37)
5091 15:36:28.136149 ==
5092 15:36:28.139085 Dram Type= 6, Freq= 0, CH_0, rank 1
5093 15:36:28.145852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 15:36:28.145938 ==
5095 15:36:28.149271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5096 15:36:28.156290 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5097 15:36:28.158995 [CA 0] Center 38 (8~69) winsize 62
5098 15:36:28.162396 [CA 1] Center 38 (8~68) winsize 61
5099 15:36:28.165905 [CA 2] Center 35 (5~66) winsize 62
5100 15:36:28.169690 [CA 3] Center 35 (5~66) winsize 62
5101 15:36:28.172761 [CA 4] Center 34 (4~65) winsize 62
5102 15:36:28.176267 [CA 5] Center 33 (3~64) winsize 62
5103 15:36:28.176351
5104 15:36:28.179092 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5105 15:36:28.179175
5106 15:36:28.182527 [CATrainingPosCal] consider 2 rank data
5107 15:36:28.186118 u2DelayCellTimex100 = 270/100 ps
5108 15:36:28.189423 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5109 15:36:28.192617 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5110 15:36:28.195841 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5111 15:36:28.202639 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5112 15:36:28.206137 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5113 15:36:28.209235 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5114 15:36:28.209357
5115 15:36:28.212822 CA PerBit enable=1, Macro0, CA PI delay=33
5116 15:36:28.212910
5117 15:36:28.216048 [CBTSetCACLKResult] CA Dly = 33
5118 15:36:28.216184 CS Dly: 7 (0~39)
5119 15:36:28.216274
5120 15:36:28.219204 ----->DramcWriteLeveling(PI) begin...
5121 15:36:28.219315 ==
5122 15:36:28.222643 Dram Type= 6, Freq= 0, CH_0, rank 0
5123 15:36:28.229397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5124 15:36:28.229477 ==
5125 15:36:28.232905 Write leveling (Byte 0): 29 => 29
5126 15:36:28.236131 Write leveling (Byte 1): 27 => 27
5127 15:36:28.236228 DramcWriteLeveling(PI) end<-----
5128 15:36:28.236328
5129 15:36:28.239501 ==
5130 15:36:28.242844 Dram Type= 6, Freq= 0, CH_0, rank 0
5131 15:36:28.246310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 15:36:28.246390 ==
5133 15:36:28.249282 [Gating] SW mode calibration
5134 15:36:28.256228 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5135 15:36:28.259553 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5136 15:36:28.266072 0 14 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
5137 15:36:28.269576 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5138 15:36:28.272820 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 15:36:28.279136 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 15:36:28.283189 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 15:36:28.285884 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 15:36:28.292588 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 15:36:28.295913 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5144 15:36:28.299620 0 15 0 | B1->B0 | 3030 2525 | 1 1 | (1 0) (0 0)
5145 15:36:28.306376 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5146 15:36:28.309124 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 15:36:28.312592 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 15:36:28.316213 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 15:36:28.322504 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 15:36:28.326124 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 15:36:28.329062 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5152 15:36:28.336138 1 0 0 | B1->B0 | 3131 4242 | 0 0 | (1 1) (0 0)
5153 15:36:28.339320 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 15:36:28.342804 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 15:36:28.349255 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 15:36:28.352590 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 15:36:28.356396 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 15:36:28.362980 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 15:36:28.365971 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5160 15:36:28.369608 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 15:36:28.376190 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5162 15:36:28.379388 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 15:36:28.382862 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 15:36:28.389364 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 15:36:28.392826 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 15:36:28.396327 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 15:36:28.399966 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 15:36:28.406206 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 15:36:28.409819 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 15:36:28.413099 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 15:36:28.419677 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 15:36:28.422909 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 15:36:28.426270 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 15:36:28.433184 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 15:36:28.436041 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5176 15:36:28.439927 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5177 15:36:28.446280 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 15:36:28.446369 Total UI for P1: 0, mck2ui 16
5179 15:36:28.453070 best dqsien dly found for B0: ( 1, 2, 30)
5180 15:36:28.453157 Total UI for P1: 0, mck2ui 16
5181 15:36:28.456306 best dqsien dly found for B1: ( 1, 2, 30)
5182 15:36:28.462874 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5183 15:36:28.466402 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5184 15:36:28.466488
5185 15:36:28.470302 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5186 15:36:28.473206 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5187 15:36:28.476688 [Gating] SW calibration Done
5188 15:36:28.476774 ==
5189 15:36:28.479743 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 15:36:28.483109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 15:36:28.483200 ==
5192 15:36:28.486356 RX Vref Scan: 0
5193 15:36:28.486442
5194 15:36:28.486528 RX Vref 0 -> 0, step: 1
5195 15:36:28.486611
5196 15:36:28.490084 RX Delay -80 -> 252, step: 8
5197 15:36:28.492924 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5198 15:36:28.496620 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5199 15:36:28.503156 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5200 15:36:28.506673 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5201 15:36:28.509828 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5202 15:36:28.513347 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5203 15:36:28.516386 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5204 15:36:28.519888 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5205 15:36:28.526823 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5206 15:36:28.529690 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5207 15:36:28.533482 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5208 15:36:28.536354 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5209 15:36:28.540363 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5210 15:36:28.546422 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5211 15:36:28.549830 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5212 15:36:28.553447 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5213 15:36:28.553530 ==
5214 15:36:28.556615 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 15:36:28.560110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 15:36:28.560194 ==
5217 15:36:28.563372 DQS Delay:
5218 15:36:28.563455 DQS0 = 0, DQS1 = 0
5219 15:36:28.563520 DQM Delay:
5220 15:36:28.566267 DQM0 = 97, DQM1 = 86
5221 15:36:28.566352 DQ Delay:
5222 15:36:28.569678 DQ0 =99, DQ1 =103, DQ2 =91, DQ3 =91
5223 15:36:28.573163 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5224 15:36:28.576414 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5225 15:36:28.580282 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5226 15:36:28.580392
5227 15:36:28.580485
5228 15:36:28.580584 ==
5229 15:36:28.583248 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 15:36:28.590353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 15:36:28.590429 ==
5232 15:36:28.590508
5233 15:36:28.590570
5234 15:36:28.590627 TX Vref Scan disable
5235 15:36:28.593235 == TX Byte 0 ==
5236 15:36:28.597036 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5237 15:36:28.600172 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5238 15:36:28.603746 == TX Byte 1 ==
5239 15:36:28.606622 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5240 15:36:28.610016 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5241 15:36:28.613894 ==
5242 15:36:28.616798 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 15:36:28.620512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 15:36:28.620614 ==
5245 15:36:28.620743
5246 15:36:28.620830
5247 15:36:28.623414 TX Vref Scan disable
5248 15:36:28.623510 == TX Byte 0 ==
5249 15:36:28.630199 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5250 15:36:28.633313 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5251 15:36:28.633389 == TX Byte 1 ==
5252 15:36:28.640212 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5253 15:36:28.643245 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5254 15:36:28.643325
5255 15:36:28.643405 [DATLAT]
5256 15:36:28.646828 Freq=933, CH0 RK0
5257 15:36:28.646931
5258 15:36:28.647033 DATLAT Default: 0xd
5259 15:36:28.649984 0, 0xFFFF, sum = 0
5260 15:36:28.650085 1, 0xFFFF, sum = 0
5261 15:36:28.653467 2, 0xFFFF, sum = 0
5262 15:36:28.653559 3, 0xFFFF, sum = 0
5263 15:36:28.656783 4, 0xFFFF, sum = 0
5264 15:36:28.656892 5, 0xFFFF, sum = 0
5265 15:36:28.660306 6, 0xFFFF, sum = 0
5266 15:36:28.660380 7, 0xFFFF, sum = 0
5267 15:36:28.663418 8, 0xFFFF, sum = 0
5268 15:36:28.663525 9, 0xFFFF, sum = 0
5269 15:36:28.667009 10, 0x0, sum = 1
5270 15:36:28.667099 11, 0x0, sum = 2
5271 15:36:28.670081 12, 0x0, sum = 3
5272 15:36:28.670154 13, 0x0, sum = 4
5273 15:36:28.673639 best_step = 11
5274 15:36:28.673740
5275 15:36:28.673829 ==
5276 15:36:28.676925 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 15:36:28.680354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 15:36:28.680459 ==
5279 15:36:28.683456 RX Vref Scan: 1
5280 15:36:28.683560
5281 15:36:28.683649 RX Vref 0 -> 0, step: 1
5282 15:36:28.683735
5283 15:36:28.686888 RX Delay -61 -> 252, step: 4
5284 15:36:28.686991
5285 15:36:28.690394 Set Vref, RX VrefLevel [Byte0]: 53
5286 15:36:28.693724 [Byte1]: 50
5287 15:36:28.697472
5288 15:36:28.697569 Final RX Vref Byte 0 = 53 to rank0
5289 15:36:28.700592 Final RX Vref Byte 1 = 50 to rank0
5290 15:36:28.703991 Final RX Vref Byte 0 = 53 to rank1
5291 15:36:28.707305 Final RX Vref Byte 1 = 50 to rank1==
5292 15:36:28.710708 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 15:36:28.717415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 15:36:28.717491 ==
5295 15:36:28.717558 DQS Delay:
5296 15:36:28.717631 DQS0 = 0, DQS1 = 0
5297 15:36:28.720998 DQM Delay:
5298 15:36:28.721075 DQM0 = 97, DQM1 = 87
5299 15:36:28.724127 DQ Delay:
5300 15:36:28.727679 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5301 15:36:28.730500 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =104
5302 15:36:28.734228 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =80
5303 15:36:28.737189 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =96
5304 15:36:28.737264
5305 15:36:28.737326
5306 15:36:28.744456 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5307 15:36:28.747918 CH0 RK0: MR19=505, MR18=1601
5308 15:36:28.754300 CH0_RK0: MR19=0x505, MR18=0x1601, DQSOSC=414, MR23=63, INC=63, DEC=42
5309 15:36:28.754378
5310 15:36:28.757149 ----->DramcWriteLeveling(PI) begin...
5311 15:36:28.757256 ==
5312 15:36:28.760680 Dram Type= 6, Freq= 0, CH_0, rank 1
5313 15:36:28.763968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 15:36:28.764074 ==
5315 15:36:28.767471 Write leveling (Byte 0): 31 => 31
5316 15:36:28.770641 Write leveling (Byte 1): 30 => 30
5317 15:36:28.774155 DramcWriteLeveling(PI) end<-----
5318 15:36:28.774236
5319 15:36:28.774332 ==
5320 15:36:28.777947 Dram Type= 6, Freq= 0, CH_0, rank 1
5321 15:36:28.780762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 15:36:28.780851 ==
5323 15:36:28.784107 [Gating] SW mode calibration
5324 15:36:28.791034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5325 15:36:28.797581 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5326 15:36:28.800960 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5327 15:36:28.804238 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 15:36:28.810872 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 15:36:28.814659 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 15:36:28.817799 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 15:36:28.824348 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 15:36:28.827936 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5333 15:36:28.831111 0 14 28 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0)
5334 15:36:28.838036 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5335 15:36:28.841057 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 15:36:28.844723 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 15:36:28.848044 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 15:36:28.854642 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 15:36:28.857734 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 15:36:28.861370 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 15:36:28.867780 0 15 28 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5342 15:36:28.871260 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5343 15:36:28.874473 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 15:36:28.881500 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 15:36:28.885543 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 15:36:28.888246 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 15:36:28.894491 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 15:36:28.898271 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 15:36:28.901354 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5350 15:36:28.907969 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5351 15:36:28.911474 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5352 15:36:28.914636 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 15:36:28.917891 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 15:36:28.925076 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 15:36:28.928253 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 15:36:28.931770 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 15:36:28.938422 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 15:36:28.941376 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 15:36:28.944845 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 15:36:28.951418 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 15:36:28.954654 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 15:36:28.957847 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 15:36:28.965052 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 15:36:28.968217 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 15:36:28.971393 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5366 15:36:28.978364 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5367 15:36:28.978447 Total UI for P1: 0, mck2ui 16
5368 15:36:28.981494 best dqsien dly found for B0: ( 1, 2, 28)
5369 15:36:28.988036 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 15:36:28.991891 Total UI for P1: 0, mck2ui 16
5371 15:36:28.994851 best dqsien dly found for B1: ( 1, 3, 0)
5372 15:36:28.998311 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5373 15:36:29.001762 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5374 15:36:29.001846
5375 15:36:29.004808 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5376 15:36:29.008041 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5377 15:36:29.011225 [Gating] SW calibration Done
5378 15:36:29.011330 ==
5379 15:36:29.014806 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 15:36:29.017817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 15:36:29.017901 ==
5382 15:36:29.021470 RX Vref Scan: 0
5383 15:36:29.021553
5384 15:36:29.024595 RX Vref 0 -> 0, step: 1
5385 15:36:29.024740
5386 15:36:29.024825 RX Delay -80 -> 252, step: 8
5387 15:36:29.031377 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5388 15:36:29.034984 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5389 15:36:29.038034 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5390 15:36:29.041720 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5391 15:36:29.044680 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5392 15:36:29.048210 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5393 15:36:29.051290 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5394 15:36:29.058013 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5395 15:36:29.061361 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5396 15:36:29.064998 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5397 15:36:29.068462 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5398 15:36:29.072011 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5399 15:36:29.078540 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5400 15:36:29.081922 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5401 15:36:29.084898 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5402 15:36:29.088118 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5403 15:36:29.088225 ==
5404 15:36:29.091632 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 15:36:29.095080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 15:36:29.095183 ==
5407 15:36:29.098478 DQS Delay:
5408 15:36:29.098584 DQS0 = 0, DQS1 = 0
5409 15:36:29.101669 DQM Delay:
5410 15:36:29.101771 DQM0 = 96, DQM1 = 86
5411 15:36:29.101866 DQ Delay:
5412 15:36:29.105088 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5413 15:36:29.108618 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5414 15:36:29.111673 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =75
5415 15:36:29.115479 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =95
5416 15:36:29.115586
5417 15:36:29.115684
5418 15:36:29.118421 ==
5419 15:36:29.121649 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 15:36:29.125198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 15:36:29.125351 ==
5422 15:36:29.125517
5423 15:36:29.125622
5424 15:36:29.128448 TX Vref Scan disable
5425 15:36:29.128553 == TX Byte 0 ==
5426 15:36:29.131735 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5427 15:36:29.138611 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5428 15:36:29.138716 == TX Byte 1 ==
5429 15:36:29.141999 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5430 15:36:29.148237 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5431 15:36:29.148344 ==
5432 15:36:29.151890 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 15:36:29.155190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 15:36:29.155294 ==
5435 15:36:29.155386
5436 15:36:29.155475
5437 15:36:29.158437 TX Vref Scan disable
5438 15:36:29.162145 == TX Byte 0 ==
5439 15:36:29.165388 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5440 15:36:29.168937 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5441 15:36:29.172002 == TX Byte 1 ==
5442 15:36:29.175531 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5443 15:36:29.178847 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5444 15:36:29.178925
5445 15:36:29.178990 [DATLAT]
5446 15:36:29.181950 Freq=933, CH0 RK1
5447 15:36:29.182025
5448 15:36:29.182091 DATLAT Default: 0xb
5449 15:36:29.185236 0, 0xFFFF, sum = 0
5450 15:36:29.185310 1, 0xFFFF, sum = 0
5451 15:36:29.188301 2, 0xFFFF, sum = 0
5452 15:36:29.191690 3, 0xFFFF, sum = 0
5453 15:36:29.191765 4, 0xFFFF, sum = 0
5454 15:36:29.195014 5, 0xFFFF, sum = 0
5455 15:36:29.195112 6, 0xFFFF, sum = 0
5456 15:36:29.198648 7, 0xFFFF, sum = 0
5457 15:36:29.198746 8, 0xFFFF, sum = 0
5458 15:36:29.201693 9, 0xFFFF, sum = 0
5459 15:36:29.201771 10, 0x0, sum = 1
5460 15:36:29.204931 11, 0x0, sum = 2
5461 15:36:29.205034 12, 0x0, sum = 3
5462 15:36:29.205127 13, 0x0, sum = 4
5463 15:36:29.208731 best_step = 11
5464 15:36:29.208813
5465 15:36:29.208905 ==
5466 15:36:29.211840 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 15:36:29.215497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 15:36:29.215574 ==
5469 15:36:29.218713 RX Vref Scan: 0
5470 15:36:29.218813
5471 15:36:29.218902 RX Vref 0 -> 0, step: 1
5472 15:36:29.221586
5473 15:36:29.221664 RX Delay -69 -> 252, step: 4
5474 15:36:29.229632 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5475 15:36:29.232602 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5476 15:36:29.236569 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5477 15:36:29.239853 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5478 15:36:29.243345 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5479 15:36:29.246845 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5480 15:36:29.249748 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5481 15:36:29.256341 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5482 15:36:29.259755 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5483 15:36:29.263029 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5484 15:36:29.266364 iDelay=199, Bit 10, Center 90 (3 ~ 178) 176
5485 15:36:29.269562 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5486 15:36:29.276439 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5487 15:36:29.279908 iDelay=199, Bit 13, Center 90 (3 ~ 178) 176
5488 15:36:29.283040 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5489 15:36:29.286483 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5490 15:36:29.286567 ==
5491 15:36:29.289636 Dram Type= 6, Freq= 0, CH_0, rank 1
5492 15:36:29.292871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 15:36:29.292956 ==
5494 15:36:29.296749 DQS Delay:
5495 15:36:29.296832 DQS0 = 0, DQS1 = 0
5496 15:36:29.299896 DQM Delay:
5497 15:36:29.299980 DQM0 = 96, DQM1 = 87
5498 15:36:29.300065 DQ Delay:
5499 15:36:29.302856 DQ0 =96, DQ1 =96, DQ2 =94, DQ3 =96
5500 15:36:29.306254 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5501 15:36:29.309708 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =78
5502 15:36:29.313034 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =94
5503 15:36:29.313117
5504 15:36:29.313202
5505 15:36:29.323626 [DQSOSCAuto] RK1, (LSB)MR18= 0x1905, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5506 15:36:29.326514 CH0 RK1: MR19=505, MR18=1905
5507 15:36:29.329819 CH0_RK1: MR19=0x505, MR18=0x1905, DQSOSC=413, MR23=63, INC=63, DEC=42
5508 15:36:29.333199 [RxdqsGatingPostProcess] freq 933
5509 15:36:29.340071 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5510 15:36:29.343282 best DQS0 dly(2T, 0.5T) = (0, 10)
5511 15:36:29.346684 best DQS1 dly(2T, 0.5T) = (0, 10)
5512 15:36:29.350235 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5513 15:36:29.353506 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5514 15:36:29.356484 best DQS0 dly(2T, 0.5T) = (0, 10)
5515 15:36:29.359792 best DQS1 dly(2T, 0.5T) = (0, 11)
5516 15:36:29.363137 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5517 15:36:29.366528 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5518 15:36:29.366612 Pre-setting of DQS Precalculation
5519 15:36:29.373264 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5520 15:36:29.373353 ==
5521 15:36:29.376434 Dram Type= 6, Freq= 0, CH_1, rank 0
5522 15:36:29.380036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 15:36:29.380120 ==
5524 15:36:29.386817 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 15:36:29.393354 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5526 15:36:29.396587 [CA 0] Center 36 (6~67) winsize 62
5527 15:36:29.400246 [CA 1] Center 36 (6~67) winsize 62
5528 15:36:29.403332 [CA 2] Center 34 (4~64) winsize 61
5529 15:36:29.406877 [CA 3] Center 33 (3~64) winsize 62
5530 15:36:29.409835 [CA 4] Center 34 (4~64) winsize 61
5531 15:36:29.413425 [CA 5] Center 33 (3~63) winsize 61
5532 15:36:29.413536
5533 15:36:29.416461 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5534 15:36:29.416571
5535 15:36:29.419898 [CATrainingPosCal] consider 1 rank data
5536 15:36:29.423695 u2DelayCellTimex100 = 270/100 ps
5537 15:36:29.426608 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5538 15:36:29.430334 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5539 15:36:29.433578 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5540 15:36:29.436484 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5541 15:36:29.440165 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5542 15:36:29.443247 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5543 15:36:29.443333
5544 15:36:29.446690 CA PerBit enable=1, Macro0, CA PI delay=33
5545 15:36:29.450157
5546 15:36:29.450239 [CBTSetCACLKResult] CA Dly = 33
5547 15:36:29.453416 CS Dly: 4 (0~35)
5548 15:36:29.453499 ==
5549 15:36:29.456649 Dram Type= 6, Freq= 0, CH_1, rank 1
5550 15:36:29.460290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 15:36:29.460373 ==
5552 15:36:29.467269 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 15:36:29.473111 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5554 15:36:29.476650 [CA 0] Center 36 (6~67) winsize 62
5555 15:36:29.480227 [CA 1] Center 36 (6~67) winsize 62
5556 15:36:29.483825 [CA 2] Center 33 (3~64) winsize 62
5557 15:36:29.486934 [CA 3] Center 33 (3~64) winsize 62
5558 15:36:29.490239 [CA 4] Center 33 (3~64) winsize 62
5559 15:36:29.493633 [CA 5] Center 33 (3~63) winsize 61
5560 15:36:29.493716
5561 15:36:29.496706 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5562 15:36:29.496816
5563 15:36:29.499749 [CATrainingPosCal] consider 2 rank data
5564 15:36:29.503339 u2DelayCellTimex100 = 270/100 ps
5565 15:36:29.506639 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 15:36:29.509990 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 15:36:29.513388 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 15:36:29.516526 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5569 15:36:29.520333 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5570 15:36:29.523702 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5571 15:36:29.523785
5572 15:36:29.526673 CA PerBit enable=1, Macro0, CA PI delay=33
5573 15:36:29.529930
5574 15:36:29.530012 [CBTSetCACLKResult] CA Dly = 33
5575 15:36:29.533189 CS Dly: 5 (0~37)
5576 15:36:29.533271
5577 15:36:29.536790 ----->DramcWriteLeveling(PI) begin...
5578 15:36:29.536875 ==
5579 15:36:29.539860 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 15:36:29.543461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 15:36:29.543581 ==
5582 15:36:29.547017 Write leveling (Byte 0): 29 => 29
5583 15:36:29.550152 Write leveling (Byte 1): 29 => 29
5584 15:36:29.553644 DramcWriteLeveling(PI) end<-----
5585 15:36:29.553728
5586 15:36:29.553802 ==
5587 15:36:29.556917 Dram Type= 6, Freq= 0, CH_1, rank 0
5588 15:36:29.560020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 15:36:29.560124 ==
5590 15:36:29.563403 [Gating] SW mode calibration
5591 15:36:29.570574 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5592 15:36:29.576728 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5593 15:36:29.580140 0 14 0 | B1->B0 | 3232 3030 | 1 1 | (1 1) (1 1)
5594 15:36:29.586781 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5595 15:36:29.590243 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 15:36:29.593428 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 15:36:29.596902 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5598 15:36:29.603359 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 15:36:29.606845 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 15:36:29.610166 0 14 28 | B1->B0 | 2f2f 3232 | 0 1 | (1 0) (1 0)
5601 15:36:29.617108 0 15 0 | B1->B0 | 2a2a 2626 | 0 0 | (1 0) (1 0)
5602 15:36:29.620282 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 15:36:29.623496 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5604 15:36:29.630069 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 15:36:29.633493 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5606 15:36:29.636892 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5607 15:36:29.643877 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 15:36:29.647056 0 15 28 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (0 0)
5609 15:36:29.650812 1 0 0 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
5610 15:36:29.657366 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 15:36:29.660594 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 15:36:29.663551 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 15:36:29.670353 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 15:36:29.673791 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 15:36:29.677079 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 15:36:29.680453 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5617 15:36:29.686947 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 15:36:29.690400 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 15:36:29.694100 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 15:36:29.700568 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 15:36:29.703439 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 15:36:29.707170 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 15:36:29.713575 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 15:36:29.716897 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 15:36:29.720211 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 15:36:29.726725 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 15:36:29.729896 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 15:36:29.733232 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 15:36:29.740127 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 15:36:29.743104 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 15:36:29.746775 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 15:36:29.753205 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5633 15:36:29.756530 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 15:36:29.760019 Total UI for P1: 0, mck2ui 16
5635 15:36:29.763102 best dqsien dly found for B0: ( 1, 2, 28)
5636 15:36:29.766424 Total UI for P1: 0, mck2ui 16
5637 15:36:29.769647 best dqsien dly found for B1: ( 1, 2, 28)
5638 15:36:29.772939 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5639 15:36:29.776418 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5640 15:36:29.776527
5641 15:36:29.779816 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5642 15:36:29.783082 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5643 15:36:29.786322 [Gating] SW calibration Done
5644 15:36:29.786405 ==
5645 15:36:29.789791 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 15:36:29.793687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 15:36:29.796871 ==
5648 15:36:29.796980 RX Vref Scan: 0
5649 15:36:29.797074
5650 15:36:29.799925 RX Vref 0 -> 0, step: 1
5651 15:36:29.800008
5652 15:36:29.803382 RX Delay -80 -> 252, step: 8
5653 15:36:29.806157 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5654 15:36:29.809756 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5655 15:36:29.813411 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5656 15:36:29.816398 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5657 15:36:29.819795 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5658 15:36:29.826539 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5659 15:36:29.830105 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5660 15:36:29.833460 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5661 15:36:29.836922 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5662 15:36:29.839982 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5663 15:36:29.843039 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5664 15:36:29.849993 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5665 15:36:29.853325 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5666 15:36:29.856476 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5667 15:36:29.859816 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5668 15:36:29.863045 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5669 15:36:29.863130 ==
5670 15:36:29.866660 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 15:36:29.873867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 15:36:29.873952 ==
5673 15:36:29.874017 DQS Delay:
5674 15:36:29.874078 DQS0 = 0, DQS1 = 0
5675 15:36:29.876827 DQM Delay:
5676 15:36:29.876913 DQM0 = 97, DQM1 = 89
5677 15:36:29.880011 DQ Delay:
5678 15:36:29.883239 DQ0 =99, DQ1 =95, DQ2 =79, DQ3 =95
5679 15:36:29.883310 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =95
5680 15:36:29.886749 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =87
5681 15:36:29.893195 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5682 15:36:29.893273
5683 15:36:29.893337
5684 15:36:29.893403 ==
5685 15:36:29.896657 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 15:36:29.900019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 15:36:29.900122 ==
5688 15:36:29.900214
5689 15:36:29.900305
5690 15:36:29.903085 TX Vref Scan disable
5691 15:36:29.903162 == TX Byte 0 ==
5692 15:36:29.910614 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5693 15:36:29.913497 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5694 15:36:29.913576 == TX Byte 1 ==
5695 15:36:29.919739 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5696 15:36:29.923281 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5697 15:36:29.923357 ==
5698 15:36:29.926861 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 15:36:29.929949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 15:36:29.930021 ==
5701 15:36:29.930082
5702 15:36:29.930151
5703 15:36:29.933610 TX Vref Scan disable
5704 15:36:29.937063 == TX Byte 0 ==
5705 15:36:29.940139 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5706 15:36:29.943793 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5707 15:36:29.946926 == TX Byte 1 ==
5708 15:36:29.950129 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5709 15:36:29.953363 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5710 15:36:29.953436
5711 15:36:29.956705 [DATLAT]
5712 15:36:29.956791 Freq=933, CH1 RK0
5713 15:36:29.956859
5714 15:36:29.960015 DATLAT Default: 0xd
5715 15:36:29.960085 0, 0xFFFF, sum = 0
5716 15:36:29.963441 1, 0xFFFF, sum = 0
5717 15:36:29.963517 2, 0xFFFF, sum = 0
5718 15:36:29.966611 3, 0xFFFF, sum = 0
5719 15:36:29.966688 4, 0xFFFF, sum = 0
5720 15:36:29.970066 5, 0xFFFF, sum = 0
5721 15:36:29.970134 6, 0xFFFF, sum = 0
5722 15:36:29.973392 7, 0xFFFF, sum = 0
5723 15:36:29.973463 8, 0xFFFF, sum = 0
5724 15:36:29.976861 9, 0xFFFF, sum = 0
5725 15:36:29.976966 10, 0x0, sum = 1
5726 15:36:29.980040 11, 0x0, sum = 2
5727 15:36:29.980137 12, 0x0, sum = 3
5728 15:36:29.983454 13, 0x0, sum = 4
5729 15:36:29.983555 best_step = 11
5730 15:36:29.983642
5731 15:36:29.983731 ==
5732 15:36:29.986706 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 15:36:29.990160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 15:36:29.990259 ==
5735 15:36:29.993525 RX Vref Scan: 1
5736 15:36:29.993598
5737 15:36:29.996958 RX Vref 0 -> 0, step: 1
5738 15:36:29.997030
5739 15:36:29.997090 RX Delay -61 -> 252, step: 4
5740 15:36:29.999987
5741 15:36:30.000087 Set Vref, RX VrefLevel [Byte0]: 58
5742 15:36:30.003766 [Byte1]: 52
5743 15:36:30.008223
5744 15:36:30.008321 Final RX Vref Byte 0 = 58 to rank0
5745 15:36:30.011712 Final RX Vref Byte 1 = 52 to rank0
5746 15:36:30.015194 Final RX Vref Byte 0 = 58 to rank1
5747 15:36:30.018663 Final RX Vref Byte 1 = 52 to rank1==
5748 15:36:30.021762 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 15:36:30.028549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 15:36:30.028633 ==
5751 15:36:30.028734 DQS Delay:
5752 15:36:30.028825 DQS0 = 0, DQS1 = 0
5753 15:36:30.032245 DQM Delay:
5754 15:36:30.032326 DQM0 = 98, DQM1 = 90
5755 15:36:30.035243 DQ Delay:
5756 15:36:30.038686 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =98
5757 15:36:30.042222 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5758 15:36:30.045134 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =86
5759 15:36:30.049285 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5760 15:36:30.049366
5761 15:36:30.049430
5762 15:36:30.055464 [DQSOSCAuto] RK0, (LSB)MR18= 0x17f4, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5763 15:36:30.058988 CH1 RK0: MR19=504, MR18=17F4
5764 15:36:30.065249 CH1_RK0: MR19=0x504, MR18=0x17F4, DQSOSC=414, MR23=63, INC=63, DEC=42
5765 15:36:30.065329
5766 15:36:30.068431 ----->DramcWriteLeveling(PI) begin...
5767 15:36:30.068531 ==
5768 15:36:30.072189 Dram Type= 6, Freq= 0, CH_1, rank 1
5769 15:36:30.075400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 15:36:30.075471 ==
5771 15:36:30.078969 Write leveling (Byte 0): 28 => 28
5772 15:36:30.082002 Write leveling (Byte 1): 27 => 27
5773 15:36:30.085387 DramcWriteLeveling(PI) end<-----
5774 15:36:30.085463
5775 15:36:30.085525 ==
5776 15:36:30.088525 Dram Type= 6, Freq= 0, CH_1, rank 1
5777 15:36:30.092073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 15:36:30.092176 ==
5779 15:36:30.095253 [Gating] SW mode calibration
5780 15:36:30.101905 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5781 15:36:30.108799 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5782 15:36:30.112478 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 15:36:30.115468 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 15:36:30.121958 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 15:36:30.125564 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 15:36:30.128699 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 15:36:30.135776 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
5788 15:36:30.139033 0 14 24 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 0)
5789 15:36:30.142527 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5790 15:36:30.148914 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5791 15:36:30.152418 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 15:36:30.155457 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 15:36:30.158701 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 15:36:30.165567 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 15:36:30.168979 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 15:36:30.172280 0 15 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
5797 15:36:30.178620 0 15 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5798 15:36:30.182213 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 15:36:30.185398 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 15:36:30.192146 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 15:36:30.195351 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 15:36:30.198782 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 15:36:30.205607 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 15:36:30.208845 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5805 15:36:30.212007 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 15:36:30.219104 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 15:36:30.222267 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 15:36:30.226004 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 15:36:30.232614 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 15:36:30.235552 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 15:36:30.238863 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 15:36:30.242693 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 15:36:30.248878 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 15:36:30.252564 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 15:36:30.255642 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 15:36:30.262581 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 15:36:30.266077 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 15:36:30.269126 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 15:36:30.275837 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 15:36:30.279220 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5821 15:36:30.282475 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 15:36:30.285977 Total UI for P1: 0, mck2ui 16
5823 15:36:30.289508 best dqsien dly found for B0: ( 1, 2, 24)
5824 15:36:30.292269 Total UI for P1: 0, mck2ui 16
5825 15:36:30.296288 best dqsien dly found for B1: ( 1, 2, 26)
5826 15:36:30.299364 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5827 15:36:30.302355 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5828 15:36:30.302466
5829 15:36:30.305990 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5830 15:36:30.312420 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5831 15:36:30.312546 [Gating] SW calibration Done
5832 15:36:30.312641 ==
5833 15:36:30.316143 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 15:36:30.322884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 15:36:30.322987 ==
5836 15:36:30.323079 RX Vref Scan: 0
5837 15:36:30.323179
5838 15:36:30.326301 RX Vref 0 -> 0, step: 1
5839 15:36:30.326375
5840 15:36:30.329674 RX Delay -80 -> 252, step: 8
5841 15:36:30.332840 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5842 15:36:30.336648 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5843 15:36:30.339800 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5844 15:36:30.342876 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5845 15:36:30.346248 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5846 15:36:30.353043 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5847 15:36:30.356327 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5848 15:36:30.359707 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5849 15:36:30.363042 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5850 15:36:30.366358 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5851 15:36:30.372886 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5852 15:36:30.376386 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5853 15:36:30.379681 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5854 15:36:30.382968 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5855 15:36:30.386352 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5856 15:36:30.389639 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5857 15:36:30.389744 ==
5858 15:36:30.393310 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 15:36:30.399580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 15:36:30.399702 ==
5861 15:36:30.399793 DQS Delay:
5862 15:36:30.402712 DQS0 = 0, DQS1 = 0
5863 15:36:30.402807 DQM Delay:
5864 15:36:30.402871 DQM0 = 94, DQM1 = 88
5865 15:36:30.406127 DQ Delay:
5866 15:36:30.409768 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5867 15:36:30.413267 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5868 15:36:30.416490 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5869 15:36:30.419609 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5870 15:36:30.419710
5871 15:36:30.419810
5872 15:36:30.419900 ==
5873 15:36:30.423262 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 15:36:30.426263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 15:36:30.426361 ==
5876 15:36:30.426461
5877 15:36:30.426548
5878 15:36:30.429856 TX Vref Scan disable
5879 15:36:30.429927 == TX Byte 0 ==
5880 15:36:30.436029 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5881 15:36:30.439739 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5882 15:36:30.439846 == TX Byte 1 ==
5883 15:36:30.446382 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5884 15:36:30.449590 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5885 15:36:30.449667 ==
5886 15:36:30.453220 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 15:36:30.456343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 15:36:30.456420 ==
5889 15:36:30.456503
5890 15:36:30.456571
5891 15:36:30.460084 TX Vref Scan disable
5892 15:36:30.463186 == TX Byte 0 ==
5893 15:36:30.466590 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5894 15:36:30.470297 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5895 15:36:30.473292 == TX Byte 1 ==
5896 15:36:30.476517 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5897 15:36:30.479894 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5898 15:36:30.480002
5899 15:36:30.483562 [DATLAT]
5900 15:36:30.483636 Freq=933, CH1 RK1
5901 15:36:30.483719
5902 15:36:30.486474 DATLAT Default: 0xb
5903 15:36:30.486570 0, 0xFFFF, sum = 0
5904 15:36:30.489825 1, 0xFFFF, sum = 0
5905 15:36:30.489929 2, 0xFFFF, sum = 0
5906 15:36:30.493342 3, 0xFFFF, sum = 0
5907 15:36:30.493417 4, 0xFFFF, sum = 0
5908 15:36:30.496547 5, 0xFFFF, sum = 0
5909 15:36:30.496658 6, 0xFFFF, sum = 0
5910 15:36:30.500337 7, 0xFFFF, sum = 0
5911 15:36:30.500443 8, 0xFFFF, sum = 0
5912 15:36:30.503693 9, 0xFFFF, sum = 0
5913 15:36:30.503772 10, 0x0, sum = 1
5914 15:36:30.506569 11, 0x0, sum = 2
5915 15:36:30.506678 12, 0x0, sum = 3
5916 15:36:30.509696 13, 0x0, sum = 4
5917 15:36:30.509805 best_step = 11
5918 15:36:30.509897
5919 15:36:30.509984 ==
5920 15:36:30.513365 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 15:36:30.519712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 15:36:30.519827 ==
5923 15:36:30.519920 RX Vref Scan: 0
5924 15:36:30.520007
5925 15:36:30.523305 RX Vref 0 -> 0, step: 1
5926 15:36:30.523402
5927 15:36:30.526438 RX Delay -61 -> 252, step: 4
5928 15:36:30.529818 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5929 15:36:30.533536 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5930 15:36:30.536817 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5931 15:36:30.543558 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5932 15:36:30.546496 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5933 15:36:30.550020 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5934 15:36:30.553291 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5935 15:36:30.556446 iDelay=199, Bit 7, Center 90 (3 ~ 178) 176
5936 15:36:30.560244 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5937 15:36:30.566893 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5938 15:36:30.570010 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5939 15:36:30.573715 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5940 15:36:30.576922 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5941 15:36:30.579894 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5942 15:36:30.586659 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5943 15:36:30.590363 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5944 15:36:30.590471 ==
5945 15:36:30.593890 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 15:36:30.596839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 15:36:30.596915 ==
5948 15:36:30.596992 DQS Delay:
5949 15:36:30.600627 DQS0 = 0, DQS1 = 0
5950 15:36:30.600761 DQM Delay:
5951 15:36:30.604108 DQM0 = 95, DQM1 = 91
5952 15:36:30.604184 DQ Delay:
5953 15:36:30.607450 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5954 15:36:30.610631 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =90
5955 15:36:30.613519 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =82
5956 15:36:30.616921 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
5957 15:36:30.616994
5958 15:36:30.617056
5959 15:36:30.627204 [DQSOSCAuto] RK1, (LSB)MR18= 0x111b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5960 15:36:30.627278 CH1 RK1: MR19=505, MR18=111B
5961 15:36:30.633629 CH1_RK1: MR19=0x505, MR18=0x111B, DQSOSC=413, MR23=63, INC=63, DEC=42
5962 15:36:30.637161 [RxdqsGatingPostProcess] freq 933
5963 15:36:30.644136 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5964 15:36:30.646756 best DQS0 dly(2T, 0.5T) = (0, 10)
5965 15:36:30.650398 best DQS1 dly(2T, 0.5T) = (0, 10)
5966 15:36:30.654085 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5967 15:36:30.657391 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5968 15:36:30.660454 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 15:36:30.660552 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 15:36:30.663979 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 15:36:30.667058 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 15:36:30.670092 Pre-setting of DQS Precalculation
5973 15:36:30.677042 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5974 15:36:30.683805 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5975 15:36:30.690823 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5976 15:36:30.690923
5977 15:36:30.691012
5978 15:36:30.693812 [Calibration Summary] 1866 Mbps
5979 15:36:30.693881 CH 0, Rank 0
5980 15:36:30.697511 SW Impedance : PASS
5981 15:36:30.700802 DUTY Scan : NO K
5982 15:36:30.700897 ZQ Calibration : PASS
5983 15:36:30.704109 Jitter Meter : NO K
5984 15:36:30.707446 CBT Training : PASS
5985 15:36:30.707551 Write leveling : PASS
5986 15:36:30.710563 RX DQS gating : PASS
5987 15:36:30.714375 RX DQ/DQS(RDDQC) : PASS
5988 15:36:30.714450 TX DQ/DQS : PASS
5989 15:36:30.717450 RX DATLAT : PASS
5990 15:36:30.717555 RX DQ/DQS(Engine): PASS
5991 15:36:30.720803 TX OE : NO K
5992 15:36:30.720899 All Pass.
5993 15:36:30.720990
5994 15:36:30.724113 CH 0, Rank 1
5995 15:36:30.724211 SW Impedance : PASS
5996 15:36:30.727262 DUTY Scan : NO K
5997 15:36:30.730734 ZQ Calibration : PASS
5998 15:36:30.730806 Jitter Meter : NO K
5999 15:36:30.734041 CBT Training : PASS
6000 15:36:30.737776 Write leveling : PASS
6001 15:36:30.737848 RX DQS gating : PASS
6002 15:36:30.740943 RX DQ/DQS(RDDQC) : PASS
6003 15:36:30.744756 TX DQ/DQS : PASS
6004 15:36:30.744854 RX DATLAT : PASS
6005 15:36:30.747720 RX DQ/DQS(Engine): PASS
6006 15:36:30.750631 TX OE : NO K
6007 15:36:30.750729 All Pass.
6008 15:36:30.750830
6009 15:36:30.750894 CH 1, Rank 0
6010 15:36:30.754001 SW Impedance : PASS
6011 15:36:30.754103 DUTY Scan : NO K
6012 15:36:30.757654 ZQ Calibration : PASS
6013 15:36:30.760939 Jitter Meter : NO K
6014 15:36:30.761046 CBT Training : PASS
6015 15:36:30.764114 Write leveling : PASS
6016 15:36:30.767648 RX DQS gating : PASS
6017 15:36:30.767745 RX DQ/DQS(RDDQC) : PASS
6018 15:36:30.770874 TX DQ/DQS : PASS
6019 15:36:30.774186 RX DATLAT : PASS
6020 15:36:30.774290 RX DQ/DQS(Engine): PASS
6021 15:36:30.777754 TX OE : NO K
6022 15:36:30.777827 All Pass.
6023 15:36:30.777910
6024 15:36:30.780906 CH 1, Rank 1
6025 15:36:30.780981 SW Impedance : PASS
6026 15:36:30.784307 DUTY Scan : NO K
6027 15:36:30.788110 ZQ Calibration : PASS
6028 15:36:30.788209 Jitter Meter : NO K
6029 15:36:30.791391 CBT Training : PASS
6030 15:36:30.794442 Write leveling : PASS
6031 15:36:30.794515 RX DQS gating : PASS
6032 15:36:30.797638 RX DQ/DQS(RDDQC) : PASS
6033 15:36:30.797739 TX DQ/DQS : PASS
6034 15:36:30.800979 RX DATLAT : PASS
6035 15:36:30.804470 RX DQ/DQS(Engine): PASS
6036 15:36:30.804568 TX OE : NO K
6037 15:36:30.807394 All Pass.
6038 15:36:30.807502
6039 15:36:30.807594 DramC Write-DBI off
6040 15:36:30.811118 PER_BANK_REFRESH: Hybrid Mode
6041 15:36:30.814035 TX_TRACKING: ON
6042 15:36:30.821011 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6043 15:36:30.824139 [FAST_K] Save calibration result to emmc
6044 15:36:30.827570 dramc_set_vcore_voltage set vcore to 650000
6045 15:36:30.831131 Read voltage for 400, 6
6046 15:36:30.831209 Vio18 = 0
6047 15:36:30.834201 Vcore = 650000
6048 15:36:30.834271 Vdram = 0
6049 15:36:30.834333 Vddq = 0
6050 15:36:30.837829 Vmddr = 0
6051 15:36:30.840757 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6052 15:36:30.847510 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6053 15:36:30.847601 MEM_TYPE=3, freq_sel=20
6054 15:36:30.851054 sv_algorithm_assistance_LP4_800
6055 15:36:30.857444 ============ PULL DRAM RESETB DOWN ============
6056 15:36:30.860884 ========== PULL DRAM RESETB DOWN end =========
6057 15:36:30.864445 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6058 15:36:30.867418 ===================================
6059 15:36:30.871398 LPDDR4 DRAM CONFIGURATION
6060 15:36:30.874533 ===================================
6061 15:36:30.874605 EX_ROW_EN[0] = 0x0
6062 15:36:30.877738 EX_ROW_EN[1] = 0x0
6063 15:36:30.881007 LP4Y_EN = 0x0
6064 15:36:30.881094 WORK_FSP = 0x0
6065 15:36:30.884015 WL = 0x2
6066 15:36:30.884086 RL = 0x2
6067 15:36:30.887528 BL = 0x2
6068 15:36:30.887605 RPST = 0x0
6069 15:36:30.890847 RD_PRE = 0x0
6070 15:36:30.890952 WR_PRE = 0x1
6071 15:36:30.894140 WR_PST = 0x0
6072 15:36:30.894213 DBI_WR = 0x0
6073 15:36:30.898034 DBI_RD = 0x0
6074 15:36:30.898106 OTF = 0x1
6075 15:36:30.901104 ===================================
6076 15:36:30.904129 ===================================
6077 15:36:30.907927 ANA top config
6078 15:36:30.911036 ===================================
6079 15:36:30.911145 DLL_ASYNC_EN = 0
6080 15:36:30.914160 ALL_SLAVE_EN = 1
6081 15:36:30.917574 NEW_RANK_MODE = 1
6082 15:36:30.921046 DLL_IDLE_MODE = 1
6083 15:36:30.921122 LP45_APHY_COMB_EN = 1
6084 15:36:30.924187 TX_ODT_DIS = 1
6085 15:36:30.927608 NEW_8X_MODE = 1
6086 15:36:30.931127 ===================================
6087 15:36:30.934314 ===================================
6088 15:36:30.937888 data_rate = 800
6089 15:36:30.941421 CKR = 1
6090 15:36:30.941501 DQ_P2S_RATIO = 4
6091 15:36:30.944301 ===================================
6092 15:36:30.947965 CA_P2S_RATIO = 4
6093 15:36:30.951275 DQ_CA_OPEN = 0
6094 15:36:30.954706 DQ_SEMI_OPEN = 1
6095 15:36:30.957636 CA_SEMI_OPEN = 1
6096 15:36:30.961189 CA_FULL_RATE = 0
6097 15:36:30.961277 DQ_CKDIV4_EN = 0
6098 15:36:30.964649 CA_CKDIV4_EN = 1
6099 15:36:30.967781 CA_PREDIV_EN = 0
6100 15:36:30.971008 PH8_DLY = 0
6101 15:36:30.974459 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6102 15:36:30.974535 DQ_AAMCK_DIV = 0
6103 15:36:30.978048 CA_AAMCK_DIV = 0
6104 15:36:30.981545 CA_ADMCK_DIV = 4
6105 15:36:30.984694 DQ_TRACK_CA_EN = 0
6106 15:36:30.987881 CA_PICK = 800
6107 15:36:30.991184 CA_MCKIO = 400
6108 15:36:30.994915 MCKIO_SEMI = 400
6109 15:36:30.995013 PLL_FREQ = 3016
6110 15:36:30.997802 DQ_UI_PI_RATIO = 32
6111 15:36:31.001480 CA_UI_PI_RATIO = 32
6112 15:36:31.004620 ===================================
6113 15:36:31.007905 ===================================
6114 15:36:31.011575 memory_type:LPDDR4
6115 15:36:31.011680 GP_NUM : 10
6116 15:36:31.014690 SRAM_EN : 1
6117 15:36:31.018015 MD32_EN : 0
6118 15:36:31.021441 ===================================
6119 15:36:31.021516 [ANA_INIT] >>>>>>>>>>>>>>
6120 15:36:31.024646 <<<<<< [CONFIGURE PHASE]: ANA_TX
6121 15:36:31.028071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6122 15:36:31.031489 ===================================
6123 15:36:31.035035 data_rate = 800,PCW = 0X7400
6124 15:36:31.038108 ===================================
6125 15:36:31.041789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6126 15:36:31.048069 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 15:36:31.057973 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6128 15:36:31.064540 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6129 15:36:31.068393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6130 15:36:31.071326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6131 15:36:31.071427 [ANA_INIT] flow start
6132 15:36:31.074565 [ANA_INIT] PLL >>>>>>>>
6133 15:36:31.078059 [ANA_INIT] PLL <<<<<<<<
6134 15:36:31.078156 [ANA_INIT] MIDPI >>>>>>>>
6135 15:36:31.081656 [ANA_INIT] MIDPI <<<<<<<<
6136 15:36:31.085170 [ANA_INIT] DLL >>>>>>>>
6137 15:36:31.085292 [ANA_INIT] flow end
6138 15:36:31.091377 ============ LP4 DIFF to SE enter ============
6139 15:36:31.094718 ============ LP4 DIFF to SE exit ============
6140 15:36:31.094815 [ANA_INIT] <<<<<<<<<<<<<
6141 15:36:31.098125 [Flow] Enable top DCM control >>>>>
6142 15:36:31.101608 [Flow] Enable top DCM control <<<<<
6143 15:36:31.104918 Enable DLL master slave shuffle
6144 15:36:31.112076 ==============================================================
6145 15:36:31.112176 Gating Mode config
6146 15:36:31.118144 ==============================================================
6147 15:36:31.121414 Config description:
6148 15:36:31.131366 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6149 15:36:31.137884 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6150 15:36:31.141190 SELPH_MODE 0: By rank 1: By Phase
6151 15:36:31.148758 ==============================================================
6152 15:36:31.151633 GAT_TRACK_EN = 0
6153 15:36:31.151736 RX_GATING_MODE = 2
6154 15:36:31.154881 RX_GATING_TRACK_MODE = 2
6155 15:36:31.157954 SELPH_MODE = 1
6156 15:36:31.161576 PICG_EARLY_EN = 1
6157 15:36:31.164954 VALID_LAT_VALUE = 1
6158 15:36:31.171176 ==============================================================
6159 15:36:31.174745 Enter into Gating configuration >>>>
6160 15:36:31.177967 Exit from Gating configuration <<<<
6161 15:36:31.181425 Enter into DVFS_PRE_config >>>>>
6162 15:36:31.191488 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6163 15:36:31.194637 Exit from DVFS_PRE_config <<<<<
6164 15:36:31.197838 Enter into PICG configuration >>>>
6165 15:36:31.201730 Exit from PICG configuration <<<<
6166 15:36:31.204923 [RX_INPUT] configuration >>>>>
6167 15:36:31.208029 [RX_INPUT] configuration <<<<<
6168 15:36:31.211211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6169 15:36:31.218095 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6170 15:36:31.224591 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6171 15:36:31.227989 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6172 15:36:31.234760 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6173 15:36:31.241276 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6174 15:36:31.244819 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6175 15:36:31.248067 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6176 15:36:31.255238 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6177 15:36:31.258106 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6178 15:36:31.261668 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6179 15:36:31.268085 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 15:36:31.271183 ===================================
6181 15:36:31.271280 LPDDR4 DRAM CONFIGURATION
6182 15:36:31.274721 ===================================
6183 15:36:31.278087 EX_ROW_EN[0] = 0x0
6184 15:36:31.278161 EX_ROW_EN[1] = 0x0
6185 15:36:31.281850 LP4Y_EN = 0x0
6186 15:36:31.281947 WORK_FSP = 0x0
6187 15:36:31.284792 WL = 0x2
6188 15:36:31.284862 RL = 0x2
6189 15:36:31.288201 BL = 0x2
6190 15:36:31.292242 RPST = 0x0
6191 15:36:31.292340 RD_PRE = 0x0
6192 15:36:31.295142 WR_PRE = 0x1
6193 15:36:31.295243 WR_PST = 0x0
6194 15:36:31.298230 DBI_WR = 0x0
6195 15:36:31.298300 DBI_RD = 0x0
6196 15:36:31.301554 OTF = 0x1
6197 15:36:31.305308 ===================================
6198 15:36:31.308122 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6199 15:36:31.311902 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6200 15:36:31.315344 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6201 15:36:31.318284 ===================================
6202 15:36:31.321706 LPDDR4 DRAM CONFIGURATION
6203 15:36:31.324752 ===================================
6204 15:36:31.328252 EX_ROW_EN[0] = 0x10
6205 15:36:31.328324 EX_ROW_EN[1] = 0x0
6206 15:36:31.331416 LP4Y_EN = 0x0
6207 15:36:31.331512 WORK_FSP = 0x0
6208 15:36:31.335102 WL = 0x2
6209 15:36:31.335197 RL = 0x2
6210 15:36:31.338528 BL = 0x2
6211 15:36:31.338625 RPST = 0x0
6212 15:36:31.341520 RD_PRE = 0x0
6213 15:36:31.341624 WR_PRE = 0x1
6214 15:36:31.345072 WR_PST = 0x0
6215 15:36:31.345142 DBI_WR = 0x0
6216 15:36:31.348348 DBI_RD = 0x0
6217 15:36:31.348452 OTF = 0x1
6218 15:36:31.351777 ===================================
6219 15:36:31.358421 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6220 15:36:31.363150 nWR fixed to 30
6221 15:36:31.366440 [ModeRegInit_LP4] CH0 RK0
6222 15:36:31.366548 [ModeRegInit_LP4] CH0 RK1
6223 15:36:31.369751 [ModeRegInit_LP4] CH1 RK0
6224 15:36:31.373232 [ModeRegInit_LP4] CH1 RK1
6225 15:36:31.373303 match AC timing 19
6226 15:36:31.379714 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6227 15:36:31.383433 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6228 15:36:31.386725 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6229 15:36:31.393068 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6230 15:36:31.396288 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6231 15:36:31.396392 ==
6232 15:36:31.399681 Dram Type= 6, Freq= 0, CH_0, rank 0
6233 15:36:31.403359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6234 15:36:31.403466 ==
6235 15:36:31.409798 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6236 15:36:31.416281 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6237 15:36:31.420057 [CA 0] Center 36 (8~64) winsize 57
6238 15:36:31.423096 [CA 1] Center 36 (8~64) winsize 57
6239 15:36:31.423193 [CA 2] Center 36 (8~64) winsize 57
6240 15:36:31.426328 [CA 3] Center 36 (8~64) winsize 57
6241 15:36:31.429716 [CA 4] Center 36 (8~64) winsize 57
6242 15:36:31.433025 [CA 5] Center 36 (8~64) winsize 57
6243 15:36:31.433096
6244 15:36:31.436602 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6245 15:36:31.439668
6246 15:36:31.442957 [CATrainingPosCal] consider 1 rank data
6247 15:36:31.443054 u2DelayCellTimex100 = 270/100 ps
6248 15:36:31.449910 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 15:36:31.452961 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 15:36:31.456419 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 15:36:31.459496 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 15:36:31.462916 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 15:36:31.466543 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 15:36:31.466647
6255 15:36:31.469701 CA PerBit enable=1, Macro0, CA PI delay=36
6256 15:36:31.469776
6257 15:36:31.473243 [CBTSetCACLKResult] CA Dly = 36
6258 15:36:31.476603 CS Dly: 1 (0~32)
6259 15:36:31.476745 ==
6260 15:36:31.479756 Dram Type= 6, Freq= 0, CH_0, rank 1
6261 15:36:31.483297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 15:36:31.483379 ==
6263 15:36:31.486509 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6264 15:36:31.493316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6265 15:36:31.496602 [CA 0] Center 36 (8~64) winsize 57
6266 15:36:31.500027 [CA 1] Center 36 (8~64) winsize 57
6267 15:36:31.503386 [CA 2] Center 36 (8~64) winsize 57
6268 15:36:31.506560 [CA 3] Center 36 (8~64) winsize 57
6269 15:36:31.509839 [CA 4] Center 36 (8~64) winsize 57
6270 15:36:31.512915 [CA 5] Center 36 (8~64) winsize 57
6271 15:36:31.513014
6272 15:36:31.516483 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6273 15:36:31.516586
6274 15:36:31.519800 [CATrainingPosCal] consider 2 rank data
6275 15:36:31.523379 u2DelayCellTimex100 = 270/100 ps
6276 15:36:31.526700 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 15:36:31.529736 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 15:36:31.533148 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 15:36:31.536934 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 15:36:31.539944 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 15:36:31.546761 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 15:36:31.546869
6283 15:36:31.549708 CA PerBit enable=1, Macro0, CA PI delay=36
6284 15:36:31.549792
6285 15:36:31.553062 [CBTSetCACLKResult] CA Dly = 36
6286 15:36:31.553171 CS Dly: 1 (0~32)
6287 15:36:31.553262
6288 15:36:31.556378 ----->DramcWriteLeveling(PI) begin...
6289 15:36:31.556485 ==
6290 15:36:31.559756 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 15:36:31.563069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 15:36:31.566452 ==
6293 15:36:31.566528 Write leveling (Byte 0): 40 => 8
6294 15:36:31.569921 Write leveling (Byte 1): 32 => 0
6295 15:36:31.573867 DramcWriteLeveling(PI) end<-----
6296 15:36:31.573943
6297 15:36:31.574006 ==
6298 15:36:31.576458 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 15:36:31.583190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 15:36:31.583291 ==
6301 15:36:31.583392 [Gating] SW mode calibration
6302 15:36:31.593263 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6303 15:36:31.596946 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6304 15:36:31.599862 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 15:36:31.607030 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6306 15:36:31.610428 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 15:36:31.613521 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 15:36:31.619951 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 15:36:31.623330 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 15:36:31.626614 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 15:36:31.633502 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 15:36:31.637082 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 15:36:31.640254 Total UI for P1: 0, mck2ui 16
6314 15:36:31.643738 best dqsien dly found for B0: ( 0, 14, 24)
6315 15:36:31.646938 Total UI for P1: 0, mck2ui 16
6316 15:36:31.650249 best dqsien dly found for B1: ( 0, 14, 24)
6317 15:36:31.653935 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6318 15:36:31.657402 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6319 15:36:31.657485
6320 15:36:31.660467 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 15:36:31.663534 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6322 15:36:31.666978 [Gating] SW calibration Done
6323 15:36:31.667085 ==
6324 15:36:31.670651 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 15:36:31.674124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 15:36:31.674208 ==
6327 15:36:31.676887 RX Vref Scan: 0
6328 15:36:31.676966
6329 15:36:31.680488 RX Vref 0 -> 0, step: 1
6330 15:36:31.680584
6331 15:36:31.680704 RX Delay -410 -> 252, step: 16
6332 15:36:31.686805 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6333 15:36:31.690332 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6334 15:36:31.694271 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6335 15:36:31.696777 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6336 15:36:31.704272 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6337 15:36:31.707096 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6338 15:36:31.710289 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6339 15:36:31.713507 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6340 15:36:31.720330 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6341 15:36:31.724114 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6342 15:36:31.727217 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6343 15:36:31.730412 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6344 15:36:31.737510 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6345 15:36:31.740315 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6346 15:36:31.743819 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6347 15:36:31.746911 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6348 15:36:31.750401 ==
6349 15:36:31.753907 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 15:36:31.757085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 15:36:31.757171 ==
6352 15:36:31.757272 DQS Delay:
6353 15:36:31.760533 DQS0 = 35, DQS1 = 51
6354 15:36:31.760642 DQM Delay:
6355 15:36:31.763922 DQM0 = 6, DQM1 = 10
6356 15:36:31.764032 DQ Delay:
6357 15:36:31.767193 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6358 15:36:31.770720 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6359 15:36:31.773748 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6360 15:36:31.776887 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6361 15:36:31.776989
6362 15:36:31.777082
6363 15:36:31.777183 ==
6364 15:36:31.781098 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 15:36:31.783482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 15:36:31.783579 ==
6367 15:36:31.783677
6368 15:36:31.783767
6369 15:36:31.787706 TX Vref Scan disable
6370 15:36:31.787809 == TX Byte 0 ==
6371 15:36:31.790565 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 15:36:31.797449 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 15:36:31.797523 == TX Byte 1 ==
6374 15:36:31.800437 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6375 15:36:31.807477 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6376 15:36:31.807590 ==
6377 15:36:31.811001 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 15:36:31.813845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 15:36:31.813922 ==
6380 15:36:31.814024
6381 15:36:31.814113
6382 15:36:31.817328 TX Vref Scan disable
6383 15:36:31.817418 == TX Byte 0 ==
6384 15:36:31.820614 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 15:36:31.827116 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 15:36:31.827216 == TX Byte 1 ==
6387 15:36:31.830821 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6388 15:36:31.837394 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6389 15:36:31.837469
6390 15:36:31.837531 [DATLAT]
6391 15:36:31.840390 Freq=400, CH0 RK0
6392 15:36:31.840487
6393 15:36:31.840586 DATLAT Default: 0xf
6394 15:36:31.843847 0, 0xFFFF, sum = 0
6395 15:36:31.843957 1, 0xFFFF, sum = 0
6396 15:36:31.847619 2, 0xFFFF, sum = 0
6397 15:36:31.847721 3, 0xFFFF, sum = 0
6398 15:36:31.850756 4, 0xFFFF, sum = 0
6399 15:36:31.850840 5, 0xFFFF, sum = 0
6400 15:36:31.854284 6, 0xFFFF, sum = 0
6401 15:36:31.854367 7, 0xFFFF, sum = 0
6402 15:36:31.857458 8, 0xFFFF, sum = 0
6403 15:36:31.857542 9, 0xFFFF, sum = 0
6404 15:36:31.860705 10, 0xFFFF, sum = 0
6405 15:36:31.860789 11, 0xFFFF, sum = 0
6406 15:36:31.864174 12, 0xFFFF, sum = 0
6407 15:36:31.864257 13, 0x0, sum = 1
6408 15:36:31.867483 14, 0x0, sum = 2
6409 15:36:31.867612 15, 0x0, sum = 3
6410 15:36:31.870745 16, 0x0, sum = 4
6411 15:36:31.870891 best_step = 14
6412 15:36:31.870956
6413 15:36:31.871016 ==
6414 15:36:31.874179 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 15:36:31.877553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 15:36:31.880993 ==
6417 15:36:31.881075 RX Vref Scan: 1
6418 15:36:31.881141
6419 15:36:31.884202 RX Vref 0 -> 0, step: 1
6420 15:36:31.884284
6421 15:36:31.887472 RX Delay -343 -> 252, step: 8
6422 15:36:31.887554
6423 15:36:31.891469 Set Vref, RX VrefLevel [Byte0]: 53
6424 15:36:31.894213 [Byte1]: 50
6425 15:36:31.894310
6426 15:36:31.898580 Final RX Vref Byte 0 = 53 to rank0
6427 15:36:31.901028 Final RX Vref Byte 1 = 50 to rank0
6428 15:36:31.904140 Final RX Vref Byte 0 = 53 to rank1
6429 15:36:31.907575 Final RX Vref Byte 1 = 50 to rank1==
6430 15:36:31.911026 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 15:36:31.914381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 15:36:31.914467 ==
6433 15:36:31.917570 DQS Delay:
6434 15:36:31.917652 DQS0 = 44, DQS1 = 60
6435 15:36:31.921109 DQM Delay:
6436 15:36:31.921191 DQM0 = 11, DQM1 = 14
6437 15:36:31.921256 DQ Delay:
6438 15:36:31.924425 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6439 15:36:31.927602 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6440 15:36:31.931126 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6441 15:36:31.934767 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6442 15:36:31.934849
6443 15:36:31.934914
6444 15:36:31.944439 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a58, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6445 15:36:31.944523 CH0 RK0: MR19=C0C, MR18=8A58
6446 15:36:31.951116 CH0_RK0: MR19=0xC0C, MR18=0x8A58, DQSOSC=392, MR23=63, INC=384, DEC=256
6447 15:36:31.951200 ==
6448 15:36:31.954195 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 15:36:31.961223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 15:36:31.961306 ==
6451 15:36:31.961371 [Gating] SW mode calibration
6452 15:36:31.971588 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6453 15:36:31.974463 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6454 15:36:31.978245 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 15:36:31.984334 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6456 15:36:31.988099 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 15:36:31.991316 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 15:36:31.997852 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 15:36:32.001290 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 15:36:32.004452 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 15:36:32.011166 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 15:36:32.014474 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 15:36:32.017808 Total UI for P1: 0, mck2ui 16
6464 15:36:32.021188 best dqsien dly found for B0: ( 0, 14, 24)
6465 15:36:32.024275 Total UI for P1: 0, mck2ui 16
6466 15:36:32.028163 best dqsien dly found for B1: ( 0, 14, 24)
6467 15:36:32.031023 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6468 15:36:32.034668 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6469 15:36:32.034753
6470 15:36:32.037965 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 15:36:32.041470 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6472 15:36:32.044637 [Gating] SW calibration Done
6473 15:36:32.044729 ==
6474 15:36:32.048237 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 15:36:32.051010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 15:36:32.054553 ==
6477 15:36:32.054637 RX Vref Scan: 0
6478 15:36:32.054704
6479 15:36:32.058028 RX Vref 0 -> 0, step: 1
6480 15:36:32.058112
6481 15:36:32.061273 RX Delay -410 -> 252, step: 16
6482 15:36:32.064530 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6483 15:36:32.067937 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6484 15:36:32.071379 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6485 15:36:32.077820 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6486 15:36:32.081255 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6487 15:36:32.085097 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6488 15:36:32.088481 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6489 15:36:32.094940 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6490 15:36:32.097916 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6491 15:36:32.101473 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6492 15:36:32.104745 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6493 15:36:32.111580 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6494 15:36:32.115088 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6495 15:36:32.118640 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6496 15:36:32.121714 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6497 15:36:32.128270 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6498 15:36:32.128376 ==
6499 15:36:32.131511 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 15:36:32.134796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 15:36:32.134896 ==
6502 15:36:32.134998 DQS Delay:
6503 15:36:32.138008 DQS0 = 43, DQS1 = 51
6504 15:36:32.138114 DQM Delay:
6505 15:36:32.141298 DQM0 = 11, DQM1 = 10
6506 15:36:32.141371 DQ Delay:
6507 15:36:32.144639 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6508 15:36:32.148114 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6509 15:36:32.151865 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6510 15:36:32.155425 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6511 15:36:32.155509
6512 15:36:32.155576
6513 15:36:32.155638 ==
6514 15:36:32.158198 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 15:36:32.161934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 15:36:32.162018 ==
6517 15:36:32.162085
6518 15:36:32.162146
6519 15:36:32.165378 TX Vref Scan disable
6520 15:36:32.165462 == TX Byte 0 ==
6521 15:36:32.171680 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6522 15:36:32.175299 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6523 15:36:32.175384 == TX Byte 1 ==
6524 15:36:32.178454 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6525 15:36:32.185539 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6526 15:36:32.185626 ==
6527 15:36:32.188596 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 15:36:32.191752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 15:36:32.191834 ==
6530 15:36:32.191898
6531 15:36:32.191959
6532 15:36:32.195307 TX Vref Scan disable
6533 15:36:32.195392 == TX Byte 0 ==
6534 15:36:32.198548 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6535 15:36:32.205207 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6536 15:36:32.205302 == TX Byte 1 ==
6537 15:36:32.208440 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6538 15:36:32.215677 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6539 15:36:32.215761
6540 15:36:32.215826 [DATLAT]
6541 15:36:32.215887 Freq=400, CH0 RK1
6542 15:36:32.215945
6543 15:36:32.218561 DATLAT Default: 0xe
6544 15:36:32.221817 0, 0xFFFF, sum = 0
6545 15:36:32.221901 1, 0xFFFF, sum = 0
6546 15:36:32.225302 2, 0xFFFF, sum = 0
6547 15:36:32.225386 3, 0xFFFF, sum = 0
6548 15:36:32.228663 4, 0xFFFF, sum = 0
6549 15:36:32.228772 5, 0xFFFF, sum = 0
6550 15:36:32.231757 6, 0xFFFF, sum = 0
6551 15:36:32.231840 7, 0xFFFF, sum = 0
6552 15:36:32.235302 8, 0xFFFF, sum = 0
6553 15:36:32.235386 9, 0xFFFF, sum = 0
6554 15:36:32.238371 10, 0xFFFF, sum = 0
6555 15:36:32.238454 11, 0xFFFF, sum = 0
6556 15:36:32.241985 12, 0xFFFF, sum = 0
6557 15:36:32.242070 13, 0x0, sum = 1
6558 15:36:32.245648 14, 0x0, sum = 2
6559 15:36:32.245731 15, 0x0, sum = 3
6560 15:36:32.248395 16, 0x0, sum = 4
6561 15:36:32.248495 best_step = 14
6562 15:36:32.248560
6563 15:36:32.248621 ==
6564 15:36:32.251606 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 15:36:32.255635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 15:36:32.258975 ==
6567 15:36:32.259074 RX Vref Scan: 0
6568 15:36:32.259173
6569 15:36:32.261861 RX Vref 0 -> 0, step: 1
6570 15:36:32.261943
6571 15:36:32.264948 RX Delay -343 -> 252, step: 8
6572 15:36:32.271553 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6573 15:36:32.275391 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6574 15:36:32.278332 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6575 15:36:32.281574 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6576 15:36:32.288404 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6577 15:36:32.291690 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6578 15:36:32.294868 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6579 15:36:32.298311 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6580 15:36:32.301869 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6581 15:36:32.308466 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6582 15:36:32.311995 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6583 15:36:32.315393 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6584 15:36:32.318492 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6585 15:36:32.325115 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6586 15:36:32.328530 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6587 15:36:32.331679 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6588 15:36:32.331767 ==
6589 15:36:32.335058 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 15:36:32.342152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 15:36:32.342243 ==
6592 15:36:32.342305 DQS Delay:
6593 15:36:32.345223 DQS0 = 48, DQS1 = 56
6594 15:36:32.345328 DQM Delay:
6595 15:36:32.345416 DQM0 = 13, DQM1 = 10
6596 15:36:32.348515 DQ Delay:
6597 15:36:32.352143 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6598 15:36:32.355337 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6599 15:36:32.355455 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6600 15:36:32.358277 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6601 15:36:32.361693
6602 15:36:32.361767
6603 15:36:32.368449 [DQSOSCAuto] RK1, (LSB)MR18= 0x9567, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6604 15:36:32.372451 CH0 RK1: MR19=C0C, MR18=9567
6605 15:36:32.378316 CH0_RK1: MR19=0xC0C, MR18=0x9567, DQSOSC=391, MR23=63, INC=386, DEC=257
6606 15:36:32.382289 [RxdqsGatingPostProcess] freq 400
6607 15:36:32.385521 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6608 15:36:32.388611 best DQS0 dly(2T, 0.5T) = (0, 10)
6609 15:36:32.392237 best DQS1 dly(2T, 0.5T) = (0, 10)
6610 15:36:32.395269 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6611 15:36:32.398867 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6612 15:36:32.402455 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 15:36:32.405222 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 15:36:32.408452 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 15:36:32.412008 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 15:36:32.415515 Pre-setting of DQS Precalculation
6617 15:36:32.418916 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6618 15:36:32.419002 ==
6619 15:36:32.422393 Dram Type= 6, Freq= 0, CH_1, rank 0
6620 15:36:32.425285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 15:36:32.429031 ==
6622 15:36:32.432159 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6623 15:36:32.439253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6624 15:36:32.442017 [CA 0] Center 36 (8~64) winsize 57
6625 15:36:32.445904 [CA 1] Center 36 (8~64) winsize 57
6626 15:36:32.449196 [CA 2] Center 36 (8~64) winsize 57
6627 15:36:32.452600 [CA 3] Center 36 (8~64) winsize 57
6628 15:36:32.455796 [CA 4] Center 36 (8~64) winsize 57
6629 15:36:32.455875 [CA 5] Center 36 (8~64) winsize 57
6630 15:36:32.455937
6631 15:36:32.462360 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6632 15:36:32.462448
6633 15:36:32.465549 [CATrainingPosCal] consider 1 rank data
6634 15:36:32.468983 u2DelayCellTimex100 = 270/100 ps
6635 15:36:32.472225 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 15:36:32.475555 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 15:36:32.478973 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 15:36:32.482597 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 15:36:32.485560 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 15:36:32.489883 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 15:36:32.489979
6642 15:36:32.492454 CA PerBit enable=1, Macro0, CA PI delay=36
6643 15:36:32.492531
6644 15:36:32.495992 [CBTSetCACLKResult] CA Dly = 36
6645 15:36:32.499049 CS Dly: 1 (0~32)
6646 15:36:32.499125 ==
6647 15:36:32.502464 Dram Type= 6, Freq= 0, CH_1, rank 1
6648 15:36:32.505729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 15:36:32.505810 ==
6650 15:36:32.512431 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6651 15:36:32.515795 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6652 15:36:32.519121 [CA 0] Center 36 (8~64) winsize 57
6653 15:36:32.522694 [CA 1] Center 36 (8~64) winsize 57
6654 15:36:32.525807 [CA 2] Center 36 (8~64) winsize 57
6655 15:36:32.529322 [CA 3] Center 36 (8~64) winsize 57
6656 15:36:32.532431 [CA 4] Center 36 (8~64) winsize 57
6657 15:36:32.536275 [CA 5] Center 36 (8~64) winsize 57
6658 15:36:32.536351
6659 15:36:32.539183 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6660 15:36:32.539261
6661 15:36:32.542810 [CATrainingPosCal] consider 2 rank data
6662 15:36:32.546536 u2DelayCellTimex100 = 270/100 ps
6663 15:36:32.549316 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 15:36:32.552717 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 15:36:32.556272 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 15:36:32.559617 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 15:36:32.565903 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 15:36:32.569419 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 15:36:32.569495
6670 15:36:32.572699 CA PerBit enable=1, Macro0, CA PI delay=36
6671 15:36:32.572784
6672 15:36:32.576103 [CBTSetCACLKResult] CA Dly = 36
6673 15:36:32.576182 CS Dly: 1 (0~32)
6674 15:36:32.576247
6675 15:36:32.579264 ----->DramcWriteLeveling(PI) begin...
6676 15:36:32.579344 ==
6677 15:36:32.583294 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 15:36:32.586124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 15:36:32.589714 ==
6680 15:36:32.589793 Write leveling (Byte 0): 40 => 8
6681 15:36:32.593070 Write leveling (Byte 1): 40 => 8
6682 15:36:32.596221 DramcWriteLeveling(PI) end<-----
6683 15:36:32.596295
6684 15:36:32.596358 ==
6685 15:36:32.599852 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 15:36:32.606445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 15:36:32.606534 ==
6688 15:36:32.606600 [Gating] SW mode calibration
6689 15:36:32.616600 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6690 15:36:32.619696 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6691 15:36:32.623369 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6692 15:36:32.630214 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6693 15:36:32.633543 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 15:36:32.636648 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 15:36:32.643148 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 15:36:32.646624 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 15:36:32.650478 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 15:36:32.656611 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 15:36:32.659933 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 15:36:32.663308 Total UI for P1: 0, mck2ui 16
6701 15:36:32.666633 best dqsien dly found for B0: ( 0, 14, 24)
6702 15:36:32.669998 Total UI for P1: 0, mck2ui 16
6703 15:36:32.673713 best dqsien dly found for B1: ( 0, 14, 24)
6704 15:36:32.676635 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6705 15:36:32.680219 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6706 15:36:32.680302
6707 15:36:32.683121 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 15:36:32.686784 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6709 15:36:32.690378 [Gating] SW calibration Done
6710 15:36:32.690463 ==
6711 15:36:32.693263 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 15:36:32.696598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 15:36:32.696713 ==
6714 15:36:32.700021 RX Vref Scan: 0
6715 15:36:32.700105
6716 15:36:32.703713 RX Vref 0 -> 0, step: 1
6717 15:36:32.703797
6718 15:36:32.703863 RX Delay -410 -> 252, step: 16
6719 15:36:32.710482 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6720 15:36:32.713338 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6721 15:36:32.716652 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6722 15:36:32.720301 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6723 15:36:32.727027 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6724 15:36:32.730286 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6725 15:36:32.733751 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6726 15:36:32.736620 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6727 15:36:32.743778 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6728 15:36:32.747012 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6729 15:36:32.750609 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6730 15:36:32.753770 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6731 15:36:32.760212 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6732 15:36:32.763860 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6733 15:36:32.767045 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6734 15:36:32.770337 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6735 15:36:32.774047 ==
6736 15:36:32.774131 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 15:36:32.780531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 15:36:32.780643 ==
6739 15:36:32.780729 DQS Delay:
6740 15:36:32.783696 DQS0 = 51, DQS1 = 59
6741 15:36:32.783779 DQM Delay:
6742 15:36:32.787457 DQM0 = 19, DQM1 = 17
6743 15:36:32.787541 DQ Delay:
6744 15:36:32.790510 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6745 15:36:32.793738 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6746 15:36:32.797079 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6747 15:36:32.800311 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6748 15:36:32.800395
6749 15:36:32.800461
6750 15:36:32.800523 ==
6751 15:36:32.803847 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 15:36:32.807159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 15:36:32.807242 ==
6754 15:36:32.807309
6755 15:36:32.807372
6756 15:36:32.810525 TX Vref Scan disable
6757 15:36:32.810611 == TX Byte 0 ==
6758 15:36:32.817434 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 15:36:32.821003 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 15:36:32.821079 == TX Byte 1 ==
6761 15:36:32.824089 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 15:36:32.830567 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 15:36:32.830652 ==
6764 15:36:32.834233 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 15:36:32.837265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 15:36:32.837341 ==
6767 15:36:32.837405
6768 15:36:32.837466
6769 15:36:32.840553 TX Vref Scan disable
6770 15:36:32.840651 == TX Byte 0 ==
6771 15:36:32.847983 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 15:36:32.850733 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 15:36:32.850819 == TX Byte 1 ==
6774 15:36:32.853951 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 15:36:32.860763 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 15:36:32.860846
6777 15:36:32.860912 [DATLAT]
6778 15:36:32.864073 Freq=400, CH1 RK0
6779 15:36:32.864145
6780 15:36:32.864226 DATLAT Default: 0xf
6781 15:36:32.867202 0, 0xFFFF, sum = 0
6782 15:36:32.867275 1, 0xFFFF, sum = 0
6783 15:36:32.870734 2, 0xFFFF, sum = 0
6784 15:36:32.870806 3, 0xFFFF, sum = 0
6785 15:36:32.873791 4, 0xFFFF, sum = 0
6786 15:36:32.873863 5, 0xFFFF, sum = 0
6787 15:36:32.877520 6, 0xFFFF, sum = 0
6788 15:36:32.877598 7, 0xFFFF, sum = 0
6789 15:36:32.880896 8, 0xFFFF, sum = 0
6790 15:36:32.880968 9, 0xFFFF, sum = 0
6791 15:36:32.883891 10, 0xFFFF, sum = 0
6792 15:36:32.883970 11, 0xFFFF, sum = 0
6793 15:36:32.887398 12, 0xFFFF, sum = 0
6794 15:36:32.887471 13, 0x0, sum = 1
6795 15:36:32.891049 14, 0x0, sum = 2
6796 15:36:32.891123 15, 0x0, sum = 3
6797 15:36:32.894063 16, 0x0, sum = 4
6798 15:36:32.894137 best_step = 14
6799 15:36:32.894224
6800 15:36:32.894284 ==
6801 15:36:32.897552 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 15:36:32.900886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 15:36:32.904148 ==
6804 15:36:32.904222 RX Vref Scan: 1
6805 15:36:32.904283
6806 15:36:32.907562 RX Vref 0 -> 0, step: 1
6807 15:36:32.907640
6808 15:36:32.911032 RX Delay -359 -> 252, step: 8
6809 15:36:32.911111
6810 15:36:32.914117 Set Vref, RX VrefLevel [Byte0]: 58
6811 15:36:32.917343 [Byte1]: 52
6812 15:36:32.917425
6813 15:36:32.921346 Final RX Vref Byte 0 = 58 to rank0
6814 15:36:32.924338 Final RX Vref Byte 1 = 52 to rank0
6815 15:36:32.927638 Final RX Vref Byte 0 = 58 to rank1
6816 15:36:32.930957 Final RX Vref Byte 1 = 52 to rank1==
6817 15:36:32.934214 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 15:36:32.937396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 15:36:32.937473 ==
6820 15:36:32.940856 DQS Delay:
6821 15:36:32.940926 DQS0 = 52, DQS1 = 60
6822 15:36:32.944008 DQM Delay:
6823 15:36:32.944078 DQM0 = 15, DQM1 = 12
6824 15:36:32.944139 DQ Delay:
6825 15:36:32.947376 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =16
6826 15:36:32.950716 DQ4 =12, DQ5 =28, DQ6 =28, DQ7 =8
6827 15:36:32.954204 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6828 15:36:32.957366 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6829 15:36:32.957438
6830 15:36:32.957506
6831 15:36:32.967496 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a30, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6832 15:36:32.970912 CH1 RK0: MR19=C0C, MR18=8A30
6833 15:36:32.974169 CH1_RK0: MR19=0xC0C, MR18=0x8A30, DQSOSC=392, MR23=63, INC=384, DEC=256
6834 15:36:32.977320 ==
6835 15:36:32.977391 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 15:36:32.984100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 15:36:32.984187 ==
6838 15:36:32.987468 [Gating] SW mode calibration
6839 15:36:32.994091 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6840 15:36:32.997406 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6841 15:36:33.004447 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6842 15:36:33.007770 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6843 15:36:33.010616 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 15:36:33.017423 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 15:36:33.020505 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 15:36:33.024042 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 15:36:33.030555 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 15:36:33.034423 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 15:36:33.037416 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 15:36:33.041003 Total UI for P1: 0, mck2ui 16
6851 15:36:33.044205 best dqsien dly found for B0: ( 0, 14, 24)
6852 15:36:33.047626 Total UI for P1: 0, mck2ui 16
6853 15:36:33.050941 best dqsien dly found for B1: ( 0, 14, 24)
6854 15:36:33.054475 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6855 15:36:33.057784 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6856 15:36:33.057857
6857 15:36:33.061582 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 15:36:33.064372 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6859 15:36:33.068207 [Gating] SW calibration Done
6860 15:36:33.068296 ==
6861 15:36:33.071384 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 15:36:33.074591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 15:36:33.078224 ==
6864 15:36:33.078299 RX Vref Scan: 0
6865 15:36:33.078371
6866 15:36:33.081376 RX Vref 0 -> 0, step: 1
6867 15:36:33.081450
6868 15:36:33.084431 RX Delay -410 -> 252, step: 16
6869 15:36:33.087948 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6870 15:36:33.091521 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6871 15:36:33.094782 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6872 15:36:33.101612 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6873 15:36:33.104533 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6874 15:36:33.108109 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6875 15:36:33.111652 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6876 15:36:33.118157 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6877 15:36:33.120997 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6878 15:36:33.124748 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6879 15:36:33.127741 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6880 15:36:33.134409 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6881 15:36:33.137966 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6882 15:36:33.141580 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6883 15:36:33.144396 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6884 15:36:33.150974 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6885 15:36:33.151063 ==
6886 15:36:33.154304 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 15:36:33.157879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 15:36:33.157959 ==
6889 15:36:33.158024 DQS Delay:
6890 15:36:33.161442 DQS0 = 43, DQS1 = 59
6891 15:36:33.161522 DQM Delay:
6892 15:36:33.164335 DQM0 = 9, DQM1 = 19
6893 15:36:33.164408 DQ Delay:
6894 15:36:33.167767 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6895 15:36:33.171612 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6896 15:36:33.174572 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6897 15:36:33.177835 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =32
6898 15:36:33.177913
6899 15:36:33.177976
6900 15:36:33.178036 ==
6901 15:36:33.180828 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 15:36:33.184558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 15:36:33.184639 ==
6904 15:36:33.184726
6905 15:36:33.184784
6906 15:36:33.187640 TX Vref Scan disable
6907 15:36:33.187713 == TX Byte 0 ==
6908 15:36:33.194550 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6909 15:36:33.197613 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6910 15:36:33.197687 == TX Byte 1 ==
6911 15:36:33.204545 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6912 15:36:33.208182 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6913 15:36:33.208262 ==
6914 15:36:33.211642 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 15:36:33.214634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 15:36:33.214705 ==
6917 15:36:33.214766
6918 15:36:33.214824
6919 15:36:33.218298 TX Vref Scan disable
6920 15:36:33.218369 == TX Byte 0 ==
6921 15:36:33.224497 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6922 15:36:33.227789 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6923 15:36:33.227960 == TX Byte 1 ==
6924 15:36:33.234695 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6925 15:36:33.238258 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6926 15:36:33.238357
6927 15:36:33.238424 [DATLAT]
6928 15:36:33.241466 Freq=400, CH1 RK1
6929 15:36:33.241548
6930 15:36:33.241637 DATLAT Default: 0xe
6931 15:36:33.244835 0, 0xFFFF, sum = 0
6932 15:36:33.244909 1, 0xFFFF, sum = 0
6933 15:36:33.248070 2, 0xFFFF, sum = 0
6934 15:36:33.248141 3, 0xFFFF, sum = 0
6935 15:36:33.251393 4, 0xFFFF, sum = 0
6936 15:36:33.251476 5, 0xFFFF, sum = 0
6937 15:36:33.254887 6, 0xFFFF, sum = 0
6938 15:36:33.254978 7, 0xFFFF, sum = 0
6939 15:36:33.257735 8, 0xFFFF, sum = 0
6940 15:36:33.257807 9, 0xFFFF, sum = 0
6941 15:36:33.261298 10, 0xFFFF, sum = 0
6942 15:36:33.264505 11, 0xFFFF, sum = 0
6943 15:36:33.264580 12, 0xFFFF, sum = 0
6944 15:36:33.268001 13, 0x0, sum = 1
6945 15:36:33.268084 14, 0x0, sum = 2
6946 15:36:33.268148 15, 0x0, sum = 3
6947 15:36:33.271402 16, 0x0, sum = 4
6948 15:36:33.271475 best_step = 14
6949 15:36:33.271542
6950 15:36:33.271600 ==
6951 15:36:33.274584 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 15:36:33.281298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 15:36:33.281374 ==
6954 15:36:33.281444 RX Vref Scan: 0
6955 15:36:33.281505
6956 15:36:33.284752 RX Vref 0 -> 0, step: 1
6957 15:36:33.284823
6958 15:36:33.287799 RX Delay -359 -> 252, step: 8
6959 15:36:33.294777 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6960 15:36:33.298106 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6961 15:36:33.301334 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6962 15:36:33.304985 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6963 15:36:33.311111 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6964 15:36:33.314418 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6965 15:36:33.317909 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6966 15:36:33.321444 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6967 15:36:33.328332 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6968 15:36:33.331054 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6969 15:36:33.334802 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6970 15:36:33.337954 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6971 15:36:33.344503 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6972 15:36:33.348043 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6973 15:36:33.351613 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6974 15:36:33.354835 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6975 15:36:33.357985 ==
6976 15:36:33.358063 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 15:36:33.364471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 15:36:33.364589 ==
6979 15:36:33.364698 DQS Delay:
6980 15:36:33.368003 DQS0 = 52, DQS1 = 56
6981 15:36:33.368087 DQM Delay:
6982 15:36:33.371297 DQM0 = 13, DQM1 = 8
6983 15:36:33.371370 DQ Delay:
6984 15:36:33.375018 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6985 15:36:33.378339 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6986 15:36:33.381185 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6987 15:36:33.384260 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6988 15:36:33.384332
6989 15:36:33.384393
6990 15:36:33.391463 [DQSOSCAuto] RK1, (LSB)MR18= 0x758b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6991 15:36:33.394560 CH1 RK1: MR19=C0C, MR18=758B
6992 15:36:33.401143 CH1_RK1: MR19=0xC0C, MR18=0x758B, DQSOSC=392, MR23=63, INC=384, DEC=256
6993 15:36:33.404787 [RxdqsGatingPostProcess] freq 400
6994 15:36:33.408046 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6995 15:36:33.411045 best DQS0 dly(2T, 0.5T) = (0, 10)
6996 15:36:33.414523 best DQS1 dly(2T, 0.5T) = (0, 10)
6997 15:36:33.417699 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6998 15:36:33.420982 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6999 15:36:33.424143 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 15:36:33.427883 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 15:36:33.431129 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 15:36:33.434097 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 15:36:33.437511 Pre-setting of DQS Precalculation
7004 15:36:33.441269 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7005 15:36:33.451187 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7006 15:36:33.457750 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7007 15:36:33.457837
7008 15:36:33.457903
7009 15:36:33.461019 [Calibration Summary] 800 Mbps
7010 15:36:33.461089 CH 0, Rank 0
7011 15:36:33.464234 SW Impedance : PASS
7012 15:36:33.464302 DUTY Scan : NO K
7013 15:36:33.467790 ZQ Calibration : PASS
7014 15:36:33.470978 Jitter Meter : NO K
7015 15:36:33.471065 CBT Training : PASS
7016 15:36:33.474620 Write leveling : PASS
7017 15:36:33.474732 RX DQS gating : PASS
7018 15:36:33.477917 RX DQ/DQS(RDDQC) : PASS
7019 15:36:33.481105 TX DQ/DQS : PASS
7020 15:36:33.481187 RX DATLAT : PASS
7021 15:36:33.484300 RX DQ/DQS(Engine): PASS
7022 15:36:33.487986 TX OE : NO K
7023 15:36:33.488075 All Pass.
7024 15:36:33.488140
7025 15:36:33.488200 CH 0, Rank 1
7026 15:36:33.491365 SW Impedance : PASS
7027 15:36:33.494508 DUTY Scan : NO K
7028 15:36:33.494619 ZQ Calibration : PASS
7029 15:36:33.498016 Jitter Meter : NO K
7030 15:36:33.501536 CBT Training : PASS
7031 15:36:33.501624 Write leveling : NO K
7032 15:36:33.504706 RX DQS gating : PASS
7033 15:36:33.507772 RX DQ/DQS(RDDQC) : PASS
7034 15:36:33.507854 TX DQ/DQS : PASS
7035 15:36:33.511206 RX DATLAT : PASS
7036 15:36:33.511278 RX DQ/DQS(Engine): PASS
7037 15:36:33.514677 TX OE : NO K
7038 15:36:33.514749 All Pass.
7039 15:36:33.514810
7040 15:36:33.517893 CH 1, Rank 0
7041 15:36:33.517961 SW Impedance : PASS
7042 15:36:33.521157 DUTY Scan : NO K
7043 15:36:33.524617 ZQ Calibration : PASS
7044 15:36:33.524723 Jitter Meter : NO K
7045 15:36:33.527891 CBT Training : PASS
7046 15:36:33.531422 Write leveling : PASS
7047 15:36:33.531503 RX DQS gating : PASS
7048 15:36:33.534743 RX DQ/DQS(RDDQC) : PASS
7049 15:36:33.538017 TX DQ/DQS : PASS
7050 15:36:33.538098 RX DATLAT : PASS
7051 15:36:33.541117 RX DQ/DQS(Engine): PASS
7052 15:36:33.544402 TX OE : NO K
7053 15:36:33.544485 All Pass.
7054 15:36:33.544550
7055 15:36:33.544610 CH 1, Rank 1
7056 15:36:33.548135 SW Impedance : PASS
7057 15:36:33.551218 DUTY Scan : NO K
7058 15:36:33.551300 ZQ Calibration : PASS
7059 15:36:33.555005 Jitter Meter : NO K
7060 15:36:33.555087 CBT Training : PASS
7061 15:36:33.558023 Write leveling : NO K
7062 15:36:33.561555 RX DQS gating : PASS
7063 15:36:33.561636 RX DQ/DQS(RDDQC) : PASS
7064 15:36:33.564564 TX DQ/DQS : PASS
7065 15:36:33.568204 RX DATLAT : PASS
7066 15:36:33.568276 RX DQ/DQS(Engine): PASS
7067 15:36:33.571400 TX OE : NO K
7068 15:36:33.571489 All Pass.
7069 15:36:33.571569
7070 15:36:33.574575 DramC Write-DBI off
7071 15:36:33.578270 PER_BANK_REFRESH: Hybrid Mode
7072 15:36:33.578353 TX_TRACKING: ON
7073 15:36:33.588486 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7074 15:36:33.591586 [FAST_K] Save calibration result to emmc
7075 15:36:33.594531 dramc_set_vcore_voltage set vcore to 725000
7076 15:36:33.597845 Read voltage for 1600, 0
7077 15:36:33.597926 Vio18 = 0
7078 15:36:33.597990 Vcore = 725000
7079 15:36:33.601550 Vdram = 0
7080 15:36:33.601631 Vddq = 0
7081 15:36:33.601694 Vmddr = 0
7082 15:36:33.608322 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7083 15:36:33.611395 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7084 15:36:33.614534 MEM_TYPE=3, freq_sel=13
7085 15:36:33.618162 sv_algorithm_assistance_LP4_3733
7086 15:36:33.621299 ============ PULL DRAM RESETB DOWN ============
7087 15:36:33.624967 ========== PULL DRAM RESETB DOWN end =========
7088 15:36:33.631807 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7089 15:36:33.635047 ===================================
7090 15:36:33.635130 LPDDR4 DRAM CONFIGURATION
7091 15:36:33.638153 ===================================
7092 15:36:33.641645 EX_ROW_EN[0] = 0x0
7093 15:36:33.644675 EX_ROW_EN[1] = 0x0
7094 15:36:33.644759 LP4Y_EN = 0x0
7095 15:36:33.648195 WORK_FSP = 0x1
7096 15:36:33.648291 WL = 0x5
7097 15:36:33.651354 RL = 0x5
7098 15:36:33.651435 BL = 0x2
7099 15:36:33.654855 RPST = 0x0
7100 15:36:33.654927 RD_PRE = 0x0
7101 15:36:33.658260 WR_PRE = 0x1
7102 15:36:33.658326 WR_PST = 0x1
7103 15:36:33.661691 DBI_WR = 0x0
7104 15:36:33.661767 DBI_RD = 0x0
7105 15:36:33.664993 OTF = 0x1
7106 15:36:33.668283 ===================================
7107 15:36:33.671513 ===================================
7108 15:36:33.671582 ANA top config
7109 15:36:33.675412 ===================================
7110 15:36:33.678224 DLL_ASYNC_EN = 0
7111 15:36:33.682254 ALL_SLAVE_EN = 0
7112 15:36:33.682333 NEW_RANK_MODE = 1
7113 15:36:33.684904 DLL_IDLE_MODE = 1
7114 15:36:33.688352 LP45_APHY_COMB_EN = 1
7115 15:36:33.691531 TX_ODT_DIS = 0
7116 15:36:33.694815 NEW_8X_MODE = 1
7117 15:36:33.698190 ===================================
7118 15:36:33.698264 ===================================
7119 15:36:33.701764 data_rate = 3200
7120 15:36:33.705326 CKR = 1
7121 15:36:33.708728 DQ_P2S_RATIO = 8
7122 15:36:33.712102 ===================================
7123 15:36:33.715095 CA_P2S_RATIO = 8
7124 15:36:33.719043 DQ_CA_OPEN = 0
7125 15:36:33.719119 DQ_SEMI_OPEN = 0
7126 15:36:33.722191 CA_SEMI_OPEN = 0
7127 15:36:33.725611 CA_FULL_RATE = 0
7128 15:36:33.728531 DQ_CKDIV4_EN = 0
7129 15:36:33.731840 CA_CKDIV4_EN = 0
7130 15:36:33.735218 CA_PREDIV_EN = 0
7131 15:36:33.735286 PH8_DLY = 12
7132 15:36:33.738585 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7133 15:36:33.741735 DQ_AAMCK_DIV = 4
7134 15:36:33.745486 CA_AAMCK_DIV = 4
7135 15:36:33.748653 CA_ADMCK_DIV = 4
7136 15:36:33.751958 DQ_TRACK_CA_EN = 0
7137 15:36:33.755293 CA_PICK = 1600
7138 15:36:33.755369 CA_MCKIO = 1600
7139 15:36:33.758655 MCKIO_SEMI = 0
7140 15:36:33.761940 PLL_FREQ = 3068
7141 15:36:33.765411 DQ_UI_PI_RATIO = 32
7142 15:36:33.768863 CA_UI_PI_RATIO = 0
7143 15:36:33.771788 ===================================
7144 15:36:33.775156 ===================================
7145 15:36:33.778540 memory_type:LPDDR4
7146 15:36:33.778614 GP_NUM : 10
7147 15:36:33.781554 SRAM_EN : 1
7148 15:36:33.781626 MD32_EN : 0
7149 15:36:33.785421 ===================================
7150 15:36:33.788424 [ANA_INIT] >>>>>>>>>>>>>>
7151 15:36:33.791675 <<<<<< [CONFIGURE PHASE]: ANA_TX
7152 15:36:33.794933 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7153 15:36:33.798936 ===================================
7154 15:36:33.802191 data_rate = 3200,PCW = 0X7600
7155 15:36:33.805725 ===================================
7156 15:36:33.808564 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7157 15:36:33.811581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 15:36:33.818481 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7159 15:36:33.821975 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7160 15:36:33.825154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7161 15:36:33.831994 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7162 15:36:33.832071 [ANA_INIT] flow start
7163 15:36:33.835300 [ANA_INIT] PLL >>>>>>>>
7164 15:36:33.835374 [ANA_INIT] PLL <<<<<<<<
7165 15:36:33.838512 [ANA_INIT] MIDPI >>>>>>>>
7166 15:36:33.841815 [ANA_INIT] MIDPI <<<<<<<<
7167 15:36:33.845267 [ANA_INIT] DLL >>>>>>>>
7168 15:36:33.845344 [ANA_INIT] DLL <<<<<<<<
7169 15:36:33.848624 [ANA_INIT] flow end
7170 15:36:33.851899 ============ LP4 DIFF to SE enter ============
7171 15:36:33.855444 ============ LP4 DIFF to SE exit ============
7172 15:36:33.859042 [ANA_INIT] <<<<<<<<<<<<<
7173 15:36:33.861749 [Flow] Enable top DCM control >>>>>
7174 15:36:33.865174 [Flow] Enable top DCM control <<<<<
7175 15:36:33.868542 Enable DLL master slave shuffle
7176 15:36:33.872095 ==============================================================
7177 15:36:33.875495 Gating Mode config
7178 15:36:33.882859 ==============================================================
7179 15:36:33.882981 Config description:
7180 15:36:33.891853 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7181 15:36:33.898554 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7182 15:36:33.905359 SELPH_MODE 0: By rank 1: By Phase
7183 15:36:33.908596 ==============================================================
7184 15:36:33.911879 GAT_TRACK_EN = 1
7185 15:36:33.915287 RX_GATING_MODE = 2
7186 15:36:33.918570 RX_GATING_TRACK_MODE = 2
7187 15:36:33.922050 SELPH_MODE = 1
7188 15:36:33.925468 PICG_EARLY_EN = 1
7189 15:36:33.928738 VALID_LAT_VALUE = 1
7190 15:36:33.931990 ==============================================================
7191 15:36:33.935710 Enter into Gating configuration >>>>
7192 15:36:33.938675 Exit from Gating configuration <<<<
7193 15:36:33.942072 Enter into DVFS_PRE_config >>>>>
7194 15:36:33.951983 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7195 15:36:33.956014 Exit from DVFS_PRE_config <<<<<
7196 15:36:33.958779 Enter into PICG configuration >>>>
7197 15:36:33.962174 Exit from PICG configuration <<<<
7198 15:36:33.965536 [RX_INPUT] configuration >>>>>
7199 15:36:33.968839 [RX_INPUT] configuration <<<<<
7200 15:36:33.975683 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7201 15:36:33.979626 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7202 15:36:33.985354 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7203 15:36:33.992305 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7204 15:36:33.999210 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7205 15:36:34.005449 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7206 15:36:34.009262 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7207 15:36:34.012354 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7208 15:36:34.015885 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7209 15:36:34.022435 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7210 15:36:34.025965 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7211 15:36:34.028842 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 15:36:34.032055 ===================================
7213 15:36:34.035346 LPDDR4 DRAM CONFIGURATION
7214 15:36:34.039194 ===================================
7215 15:36:34.039265 EX_ROW_EN[0] = 0x0
7216 15:36:34.042142 EX_ROW_EN[1] = 0x0
7217 15:36:34.042211 LP4Y_EN = 0x0
7218 15:36:34.045452 WORK_FSP = 0x1
7219 15:36:34.045522 WL = 0x5
7220 15:36:34.048960 RL = 0x5
7221 15:36:34.049056 BL = 0x2
7222 15:36:34.052315 RPST = 0x0
7223 15:36:34.052399 RD_PRE = 0x0
7224 15:36:34.055450 WR_PRE = 0x1
7225 15:36:34.058894 WR_PST = 0x1
7226 15:36:34.058968 DBI_WR = 0x0
7227 15:36:34.062221 DBI_RD = 0x0
7228 15:36:34.062294 OTF = 0x1
7229 15:36:34.065545 ===================================
7230 15:36:34.068944 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7231 15:36:34.072334 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7232 15:36:34.079257 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7233 15:36:34.082645 ===================================
7234 15:36:34.085446 LPDDR4 DRAM CONFIGURATION
7235 15:36:34.089338 ===================================
7236 15:36:34.089416 EX_ROW_EN[0] = 0x10
7237 15:36:34.092859 EX_ROW_EN[1] = 0x0
7238 15:36:34.092932 LP4Y_EN = 0x0
7239 15:36:34.095915 WORK_FSP = 0x1
7240 15:36:34.095987 WL = 0x5
7241 15:36:34.099230 RL = 0x5
7242 15:36:34.099304 BL = 0x2
7243 15:36:34.102357 RPST = 0x0
7244 15:36:34.102425 RD_PRE = 0x0
7245 15:36:34.105609 WR_PRE = 0x1
7246 15:36:34.105685 WR_PST = 0x1
7247 15:36:34.109009 DBI_WR = 0x0
7248 15:36:34.109087 DBI_RD = 0x0
7249 15:36:34.112176 OTF = 0x1
7250 15:36:34.115729 ===================================
7251 15:36:34.122793 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7252 15:36:34.122871 ==
7253 15:36:34.126144 Dram Type= 6, Freq= 0, CH_0, rank 0
7254 15:36:34.128957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7255 15:36:34.129035 ==
7256 15:36:34.132592 [Duty_Offset_Calibration]
7257 15:36:34.132695 B0:2 B1:-1 CA:1
7258 15:36:34.132759
7259 15:36:34.135719 [DutyScan_Calibration_Flow] k_type=0
7260 15:36:34.145465
7261 15:36:34.145543 ==CLK 0==
7262 15:36:34.149057 Final CLK duty delay cell = -4
7263 15:36:34.152280 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7264 15:36:34.155576 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7265 15:36:34.159294 [-4] AVG Duty = 4937%(X100)
7266 15:36:34.159365
7267 15:36:34.162485 CH0 CLK Duty spec in!! Max-Min= 187%
7268 15:36:34.165977 [DutyScan_Calibration_Flow] ====Done====
7269 15:36:34.166052
7270 15:36:34.169255 [DutyScan_Calibration_Flow] k_type=1
7271 15:36:34.185079
7272 15:36:34.185156 ==DQS 0 ==
7273 15:36:34.188739 Final DQS duty delay cell = 0
7274 15:36:34.192162 [0] MAX Duty = 5125%(X100), DQS PI = 56
7275 15:36:34.195402 [0] MIN Duty = 5031%(X100), DQS PI = 4
7276 15:36:34.195476 [0] AVG Duty = 5078%(X100)
7277 15:36:34.198357
7278 15:36:34.198432 ==DQS 1 ==
7279 15:36:34.201841 Final DQS duty delay cell = -4
7280 15:36:34.205585 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7281 15:36:34.208714 [-4] MIN Duty = 5031%(X100), DQS PI = 20
7282 15:36:34.212153 [-4] AVG Duty = 5062%(X100)
7283 15:36:34.212226
7284 15:36:34.215291 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7285 15:36:34.215385
7286 15:36:34.218862 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7287 15:36:34.222534 [DutyScan_Calibration_Flow] ====Done====
7288 15:36:34.222606
7289 15:36:34.225458 [DutyScan_Calibration_Flow] k_type=3
7290 15:36:34.242379
7291 15:36:34.242470 ==DQM 0 ==
7292 15:36:34.245609 Final DQM duty delay cell = 0
7293 15:36:34.249043 [0] MAX Duty = 5000%(X100), DQS PI = 18
7294 15:36:34.252370 [0] MIN Duty = 4875%(X100), DQS PI = 4
7295 15:36:34.252455 [0] AVG Duty = 4937%(X100)
7296 15:36:34.255925
7297 15:36:34.256011 ==DQM 1 ==
7298 15:36:34.259208 Final DQM duty delay cell = 0
7299 15:36:34.262631 [0] MAX Duty = 5218%(X100), DQS PI = 58
7300 15:36:34.265727 [0] MIN Duty = 4969%(X100), DQS PI = 20
7301 15:36:34.265809 [0] AVG Duty = 5093%(X100)
7302 15:36:34.269351
7303 15:36:34.272449 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7304 15:36:34.272545
7305 15:36:34.276482 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7306 15:36:34.279254 [DutyScan_Calibration_Flow] ====Done====
7307 15:36:34.279335
7308 15:36:34.282483 [DutyScan_Calibration_Flow] k_type=2
7309 15:36:34.299037
7310 15:36:34.299120 ==DQ 0 ==
7311 15:36:34.302275 Final DQ duty delay cell = -4
7312 15:36:34.305347 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7313 15:36:34.308613 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7314 15:36:34.308717 [-4] AVG Duty = 4922%(X100)
7315 15:36:34.311914
7316 15:36:34.311983 ==DQ 1 ==
7317 15:36:34.315235 Final DQ duty delay cell = 0
7318 15:36:34.318990 [0] MAX Duty = 5000%(X100), DQS PI = 0
7319 15:36:34.322097 [0] MIN Duty = 4938%(X100), DQS PI = 4
7320 15:36:34.322168 [0] AVG Duty = 4969%(X100)
7321 15:36:34.322231
7322 15:36:34.325259 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7323 15:36:34.325328
7324 15:36:34.328684 CH0 DQ 1 Duty spec in!! Max-Min= 62%
7325 15:36:34.335299 [DutyScan_Calibration_Flow] ====Done====
7326 15:36:34.335373 ==
7327 15:36:34.338940 Dram Type= 6, Freq= 0, CH_1, rank 0
7328 15:36:34.342697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7329 15:36:34.342785 ==
7330 15:36:34.345595 [Duty_Offset_Calibration]
7331 15:36:34.345678 B0:1 B1:1 CA:2
7332 15:36:34.345742
7333 15:36:34.348942 [DutyScan_Calibration_Flow] k_type=0
7334 15:36:34.358679
7335 15:36:34.358763 ==CLK 0==
7336 15:36:34.361932 Final CLK duty delay cell = 0
7337 15:36:34.365404 [0] MAX Duty = 5218%(X100), DQS PI = 24
7338 15:36:34.368841 [0] MIN Duty = 4938%(X100), DQS PI = 48
7339 15:36:34.368924 [0] AVG Duty = 5078%(X100)
7340 15:36:34.372166
7341 15:36:34.375276 CH1 CLK Duty spec in!! Max-Min= 280%
7342 15:36:34.378919 [DutyScan_Calibration_Flow] ====Done====
7343 15:36:34.379001
7344 15:36:34.382441 [DutyScan_Calibration_Flow] k_type=1
7345 15:36:34.398436
7346 15:36:34.398516 ==DQS 0 ==
7347 15:36:34.402075 Final DQS duty delay cell = 0
7348 15:36:34.405188 [0] MAX Duty = 5062%(X100), DQS PI = 20
7349 15:36:34.408465 [0] MIN Duty = 4813%(X100), DQS PI = 50
7350 15:36:34.411776 [0] AVG Duty = 4937%(X100)
7351 15:36:34.411857
7352 15:36:34.411921 ==DQS 1 ==
7353 15:36:34.415339 Final DQS duty delay cell = 0
7354 15:36:34.418336 [0] MAX Duty = 5031%(X100), DQS PI = 34
7355 15:36:34.421855 [0] MIN Duty = 4938%(X100), DQS PI = 22
7356 15:36:34.425366 [0] AVG Duty = 4984%(X100)
7357 15:36:34.425447
7358 15:36:34.428769 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7359 15:36:34.428851
7360 15:36:34.432094 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7361 15:36:34.435746 [DutyScan_Calibration_Flow] ====Done====
7362 15:36:34.435827
7363 15:36:34.438329 [DutyScan_Calibration_Flow] k_type=3
7364 15:36:34.455511
7365 15:36:34.455594 ==DQM 0 ==
7366 15:36:34.458470 Final DQM duty delay cell = 0
7367 15:36:34.462041 [0] MAX Duty = 5156%(X100), DQS PI = 20
7368 15:36:34.465390 [0] MIN Duty = 4813%(X100), DQS PI = 50
7369 15:36:34.465486 [0] AVG Duty = 4984%(X100)
7370 15:36:34.468629
7371 15:36:34.468736 ==DQM 1 ==
7372 15:36:34.471926 Final DQM duty delay cell = 0
7373 15:36:34.475370 [0] MAX Duty = 5125%(X100), DQS PI = 10
7374 15:36:34.479039 [0] MIN Duty = 4907%(X100), DQS PI = 20
7375 15:36:34.479135 [0] AVG Duty = 5016%(X100)
7376 15:36:34.479214
7377 15:36:34.482321 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7378 15:36:34.485820
7379 15:36:34.488984 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7380 15:36:34.492396 [DutyScan_Calibration_Flow] ====Done====
7381 15:36:34.492479
7382 15:36:34.495931 [DutyScan_Calibration_Flow] k_type=2
7383 15:36:34.512059
7384 15:36:34.512141 ==DQ 0 ==
7385 15:36:34.515566 Final DQ duty delay cell = 0
7386 15:36:34.518707 [0] MAX Duty = 5156%(X100), DQS PI = 20
7387 15:36:34.522064 [0] MIN Duty = 4907%(X100), DQS PI = 52
7388 15:36:34.522138 [0] AVG Duty = 5031%(X100)
7389 15:36:34.525357
7390 15:36:34.525436 ==DQ 1 ==
7391 15:36:34.529062 Final DQ duty delay cell = 0
7392 15:36:34.532308 [0] MAX Duty = 5124%(X100), DQS PI = 42
7393 15:36:34.535665 [0] MIN Duty = 5031%(X100), DQS PI = 0
7394 15:36:34.535747 [0] AVG Duty = 5077%(X100)
7395 15:36:34.535812
7396 15:36:34.538826 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7397 15:36:34.538907
7398 15:36:34.542001 CH1 DQ 1 Duty spec in!! Max-Min= 93%
7399 15:36:34.549081 [DutyScan_Calibration_Flow] ====Done====
7400 15:36:34.551884 nWR fixed to 30
7401 15:36:34.551967 [ModeRegInit_LP4] CH0 RK0
7402 15:36:34.555358 [ModeRegInit_LP4] CH0 RK1
7403 15:36:34.558613 [ModeRegInit_LP4] CH1 RK0
7404 15:36:34.558694 [ModeRegInit_LP4] CH1 RK1
7405 15:36:34.562371 match AC timing 5
7406 15:36:34.565244 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7407 15:36:34.568655 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7408 15:36:34.575391 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7409 15:36:34.578644 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7410 15:36:34.585278 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7411 15:36:34.585356 [MiockJmeterHQA]
7412 15:36:34.585420
7413 15:36:34.588672 [DramcMiockJmeter] u1RxGatingPI = 0
7414 15:36:34.592254 0 : 4255, 4029
7415 15:36:34.592333 4 : 4252, 4027
7416 15:36:34.592396 8 : 4252, 4027
7417 15:36:34.595224 12 : 4252, 4026
7418 15:36:34.595299 16 : 4253, 4026
7419 15:36:34.599162 20 : 4257, 4029
7420 15:36:34.599240 24 : 4368, 4143
7421 15:36:34.601969 28 : 4363, 4138
7422 15:36:34.602046 32 : 4363, 4138
7423 15:36:34.602108 36 : 4366, 4139
7424 15:36:34.605325 40 : 4253, 4026
7425 15:36:34.605398 44 : 4257, 4032
7426 15:36:34.608790 48 : 4252, 4027
7427 15:36:34.608864 52 : 4253, 4026
7428 15:36:34.612074 56 : 4258, 4030
7429 15:36:34.612149 60 : 4250, 4026
7430 15:36:34.612211 64 : 4255, 4029
7431 15:36:34.615624 68 : 4253, 4029
7432 15:36:34.615697 72 : 4250, 4027
7433 15:36:34.618746 76 : 4252, 4029
7434 15:36:34.618822 80 : 4250, 4026
7435 15:36:34.621959 84 : 4254, 4030
7436 15:36:34.622041 88 : 4252, 4027
7437 15:36:34.625233 92 : 4250, 4027
7438 15:36:34.625307 96 : 4255, 3225
7439 15:36:34.625371 100 : 4250, 0
7440 15:36:34.628517 104 : 4250, 0
7441 15:36:34.628621 108 : 4363, 0
7442 15:36:34.631966 112 : 4253, 0
7443 15:36:34.632039 116 : 4250, 0
7444 15:36:34.632099 120 : 4255, 0
7445 15:36:34.635626 124 : 4255, 0
7446 15:36:34.635710 128 : 4250, 0
7447 15:36:34.638723 132 : 4254, 0
7448 15:36:34.638795 136 : 4252, 0
7449 15:36:34.638856 140 : 4250, 0
7450 15:36:34.642183 144 : 4255, 0
7451 15:36:34.642255 148 : 4255, 0
7452 15:36:34.642320 152 : 4250, 0
7453 15:36:34.645344 156 : 4252, 0
7454 15:36:34.645417 160 : 4250, 0
7455 15:36:34.648955 164 : 4360, 0
7456 15:36:34.649028 168 : 4252, 0
7457 15:36:34.649090 172 : 4253, 0
7458 15:36:34.651841 176 : 4252, 0
7459 15:36:34.651925 180 : 4250, 0
7460 15:36:34.655355 184 : 4250, 0
7461 15:36:34.655430 188 : 4250, 0
7462 15:36:34.655493 192 : 4250, 0
7463 15:36:34.658810 196 : 4257, 0
7464 15:36:34.658883 200 : 4361, 0
7465 15:36:34.661883 204 : 4361, 0
7466 15:36:34.661958 208 : 4250, 0
7467 15:36:34.662022 212 : 4250, 234
7468 15:36:34.665297 216 : 4250, 3124
7469 15:36:34.665373 220 : 4253, 4029
7470 15:36:34.668991 224 : 4360, 4137
7471 15:36:34.669070 228 : 4250, 4027
7472 15:36:34.672028 232 : 4252, 4029
7473 15:36:34.672100 236 : 4250, 4027
7474 15:36:34.675603 240 : 4250, 4026
7475 15:36:34.675704 244 : 4252, 4027
7476 15:36:34.675769 248 : 4250, 4027
7477 15:36:34.678713 252 : 4363, 4139
7478 15:36:34.678794 256 : 4250, 4027
7479 15:36:34.682087 260 : 4361, 4137
7480 15:36:34.682165 264 : 4250, 4027
7481 15:36:34.685794 268 : 4249, 4027
7482 15:36:34.685884 272 : 4363, 4140
7483 15:36:34.688743 276 : 4250, 4027
7484 15:36:34.688817 280 : 4252, 4027
7485 15:36:34.692057 284 : 4255, 4029
7486 15:36:34.692134 288 : 4250, 4027
7487 15:36:34.695506 292 : 4255, 4029
7488 15:36:34.695587 296 : 4252, 4030
7489 15:36:34.698845 300 : 4257, 4031
7490 15:36:34.698919 304 : 4250, 4027
7491 15:36:34.698985 308 : 4363, 4137
7492 15:36:34.702159 312 : 4363, 4140
7493 15:36:34.702245 316 : 4248, 4024
7494 15:36:34.705453 320 : 4252, 4029
7495 15:36:34.705539 324 : 4363, 4140
7496 15:36:34.708700 328 : 4250, 4027
7497 15:36:34.708798 332 : 4252, 2837
7498 15:36:34.712140 336 : 4254, 27
7499 15:36:34.712222
7500 15:36:34.712286 MIOCK jitter meter ch=0
7501 15:36:34.712345
7502 15:36:34.715214 1T = (336-100) = 236 dly cells
7503 15:36:34.721883 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7504 15:36:34.721968 ==
7505 15:36:34.725334 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 15:36:34.728445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 15:36:34.728527 ==
7508 15:36:34.735096 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 15:36:34.738635 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 15:36:34.745060 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 15:36:34.748545 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 15:36:34.758871 [CA 0] Center 44 (14~75) winsize 62
7513 15:36:34.761920 [CA 1] Center 44 (14~74) winsize 61
7514 15:36:34.765222 [CA 2] Center 39 (10~68) winsize 59
7515 15:36:34.768823 [CA 3] Center 39 (10~68) winsize 59
7516 15:36:34.771795 [CA 4] Center 37 (7~67) winsize 61
7517 15:36:34.775429 [CA 5] Center 37 (7~67) winsize 61
7518 15:36:34.775511
7519 15:36:34.778781 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 15:36:34.778862
7521 15:36:34.782010 [CATrainingPosCal] consider 1 rank data
7522 15:36:34.785249 u2DelayCellTimex100 = 275/100 ps
7523 15:36:34.788721 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7524 15:36:34.795280 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7525 15:36:34.798378 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7526 15:36:34.802303 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7527 15:36:34.805459 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7528 15:36:34.808969 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7529 15:36:34.809050
7530 15:36:34.812353 CA PerBit enable=1, Macro0, CA PI delay=37
7531 15:36:34.812434
7532 15:36:34.815608 [CBTSetCACLKResult] CA Dly = 37
7533 15:36:34.818712 CS Dly: 10 (0~41)
7534 15:36:34.822073 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 15:36:34.825515 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 15:36:34.825592 ==
7537 15:36:34.829278 Dram Type= 6, Freq= 0, CH_0, rank 1
7538 15:36:34.832132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 15:36:34.832205 ==
7540 15:36:34.838975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7541 15:36:34.842357 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7542 15:36:34.849114 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7543 15:36:34.852047 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7544 15:36:34.862596 [CA 0] Center 43 (13~74) winsize 62
7545 15:36:34.865650 [CA 1] Center 43 (13~74) winsize 62
7546 15:36:34.869164 [CA 2] Center 39 (10~69) winsize 60
7547 15:36:34.872760 [CA 3] Center 38 (9~68) winsize 60
7548 15:36:34.875893 [CA 4] Center 37 (7~67) winsize 61
7549 15:36:34.879284 [CA 5] Center 37 (7~67) winsize 61
7550 15:36:34.879357
7551 15:36:34.882335 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7552 15:36:34.882407
7553 15:36:34.885740 [CATrainingPosCal] consider 2 rank data
7554 15:36:34.889082 u2DelayCellTimex100 = 275/100 ps
7555 15:36:34.892322 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7556 15:36:34.899427 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7557 15:36:34.902323 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7558 15:36:34.905831 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7559 15:36:34.909193 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7560 15:36:34.912329 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7561 15:36:34.912402
7562 15:36:34.916078 CA PerBit enable=1, Macro0, CA PI delay=37
7563 15:36:34.916166
7564 15:36:34.919716 [CBTSetCACLKResult] CA Dly = 37
7565 15:36:34.922374 CS Dly: 11 (0~44)
7566 15:36:34.925676 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7567 15:36:34.929230 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7568 15:36:34.929322
7569 15:36:34.932579 ----->DramcWriteLeveling(PI) begin...
7570 15:36:34.932652 ==
7571 15:36:34.935647 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 15:36:34.939322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 15:36:34.942445 ==
7574 15:36:34.942528 Write leveling (Byte 0): 31 => 31
7575 15:36:34.945676 Write leveling (Byte 1): 28 => 28
7576 15:36:34.949234 DramcWriteLeveling(PI) end<-----
7577 15:36:34.949317
7578 15:36:34.949381 ==
7579 15:36:34.952263 Dram Type= 6, Freq= 0, CH_0, rank 0
7580 15:36:34.959290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 15:36:34.959374 ==
7582 15:36:34.959440 [Gating] SW mode calibration
7583 15:36:34.969184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7584 15:36:34.972258 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7585 15:36:34.975827 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 15:36:34.982477 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 15:36:34.985759 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 15:36:34.989466 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 15:36:34.995887 1 4 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7590 15:36:34.999078 1 4 20 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7591 15:36:35.002636 1 4 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7592 15:36:35.009737 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 15:36:35.012564 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 15:36:35.015933 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 15:36:35.022787 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 15:36:35.026322 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7597 15:36:35.029123 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7598 15:36:35.035780 1 5 20 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
7599 15:36:35.039366 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
7600 15:36:35.042880 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 15:36:35.049317 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 15:36:35.052461 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 15:36:35.056265 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 15:36:35.059405 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 15:36:35.066184 1 6 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7606 15:36:35.069085 1 6 20 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7607 15:36:35.072459 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7608 15:36:35.079482 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 15:36:35.082582 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 15:36:35.085857 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 15:36:35.092805 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 15:36:35.095843 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 15:36:35.099487 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7614 15:36:35.106222 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7615 15:36:35.109551 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7616 15:36:35.113063 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 15:36:35.119653 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 15:36:35.122755 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 15:36:35.125845 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 15:36:35.133322 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 15:36:35.136344 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 15:36:35.139910 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 15:36:35.143068 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 15:36:35.149280 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 15:36:35.152590 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 15:36:35.156138 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 15:36:35.163184 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 15:36:35.165848 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 15:36:35.170002 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7630 15:36:35.176056 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7631 15:36:35.179289 Total UI for P1: 0, mck2ui 16
7632 15:36:35.182420 best dqsien dly found for B0: ( 1, 9, 16)
7633 15:36:35.186009 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7634 15:36:35.189294 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 15:36:35.192620 Total UI for P1: 0, mck2ui 16
7636 15:36:35.196001 best dqsien dly found for B1: ( 1, 9, 22)
7637 15:36:35.199431 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7638 15:36:35.202454 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7639 15:36:35.202550
7640 15:36:35.209297 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7641 15:36:35.212305 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7642 15:36:35.215729 [Gating] SW calibration Done
7643 15:36:35.215798 ==
7644 15:36:35.219138 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 15:36:35.222270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 15:36:35.222344 ==
7647 15:36:35.222407 RX Vref Scan: 0
7648 15:36:35.225810
7649 15:36:35.225876 RX Vref 0 -> 0, step: 1
7650 15:36:35.225934
7651 15:36:35.229049 RX Delay 0 -> 252, step: 8
7652 15:36:35.232633 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7653 15:36:35.236070 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7654 15:36:35.242678 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7655 15:36:35.245824 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7656 15:36:35.249070 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7657 15:36:35.252201 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7658 15:36:35.255719 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7659 15:36:35.259160 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7660 15:36:35.266481 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7661 15:36:35.269142 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7662 15:36:35.272945 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7663 15:36:35.276142 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7664 15:36:35.279590 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7665 15:36:35.286477 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7666 15:36:35.289334 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7667 15:36:35.292558 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7668 15:36:35.292640 ==
7669 15:36:35.296385 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 15:36:35.299727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 15:36:35.299797 ==
7672 15:36:35.302854 DQS Delay:
7673 15:36:35.302933 DQS0 = 0, DQS1 = 0
7674 15:36:35.305988 DQM Delay:
7675 15:36:35.306074 DQM0 = 132, DQM1 = 123
7676 15:36:35.306151 DQ Delay:
7677 15:36:35.309643 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7678 15:36:35.316635 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7679 15:36:35.319570 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7680 15:36:35.323161 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7681 15:36:35.323235
7682 15:36:35.323296
7683 15:36:35.323354 ==
7684 15:36:35.326244 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 15:36:35.329628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 15:36:35.329701 ==
7687 15:36:35.329761
7688 15:36:35.329818
7689 15:36:35.332777 TX Vref Scan disable
7690 15:36:35.336755 == TX Byte 0 ==
7691 15:36:35.339793 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7692 15:36:35.343075 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7693 15:36:35.346530 == TX Byte 1 ==
7694 15:36:35.349580 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7695 15:36:35.352918 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7696 15:36:35.353003 ==
7697 15:36:35.356319 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 15:36:35.359857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 15:36:35.359939 ==
7700 15:36:35.373834
7701 15:36:35.377669 TX Vref early break, caculate TX vref
7702 15:36:35.380633 TX Vref=16, minBit 0, minWin=21, winSum=357
7703 15:36:35.384458 TX Vref=18, minBit 1, minWin=21, winSum=363
7704 15:36:35.387298 TX Vref=20, minBit 7, minWin=21, winSum=378
7705 15:36:35.391059 TX Vref=22, minBit 7, minWin=22, winSum=394
7706 15:36:35.394220 TX Vref=24, minBit 1, minWin=23, winSum=399
7707 15:36:35.397500 TX Vref=26, minBit 4, minWin=23, winSum=406
7708 15:36:35.404308 TX Vref=28, minBit 7, minWin=24, winSum=417
7709 15:36:35.407389 TX Vref=30, minBit 0, minWin=24, winSum=418
7710 15:36:35.410800 TX Vref=32, minBit 0, minWin=24, winSum=412
7711 15:36:35.414099 TX Vref=34, minBit 4, minWin=23, winSum=395
7712 15:36:35.421019 [TxChooseVref] Worse bit 0, Min win 24, Win sum 418, Final Vref 30
7713 15:36:35.421104
7714 15:36:35.424418 Final TX Range 0 Vref 30
7715 15:36:35.424499
7716 15:36:35.424563 ==
7717 15:36:35.427664 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 15:36:35.431135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 15:36:35.431216 ==
7720 15:36:35.431281
7721 15:36:35.431340
7722 15:36:35.434399 TX Vref Scan disable
7723 15:36:35.437425 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7724 15:36:35.441274 == TX Byte 0 ==
7725 15:36:35.444266 u2DelayCellOfst[0]=14 cells (4 PI)
7726 15:36:35.447950 u2DelayCellOfst[1]=21 cells (6 PI)
7727 15:36:35.451335 u2DelayCellOfst[2]=10 cells (3 PI)
7728 15:36:35.454222 u2DelayCellOfst[3]=10 cells (3 PI)
7729 15:36:35.457952 u2DelayCellOfst[4]=10 cells (3 PI)
7730 15:36:35.458034 u2DelayCellOfst[5]=0 cells (0 PI)
7731 15:36:35.460990 u2DelayCellOfst[6]=21 cells (6 PI)
7732 15:36:35.464518 u2DelayCellOfst[7]=21 cells (6 PI)
7733 15:36:35.470805 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7734 15:36:35.473993 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7735 15:36:35.474075 == TX Byte 1 ==
7736 15:36:35.477486 u2DelayCellOfst[8]=0 cells (0 PI)
7737 15:36:35.481225 u2DelayCellOfst[9]=0 cells (0 PI)
7738 15:36:35.484124 u2DelayCellOfst[10]=7 cells (2 PI)
7739 15:36:35.487400 u2DelayCellOfst[11]=0 cells (0 PI)
7740 15:36:35.490823 u2DelayCellOfst[12]=14 cells (4 PI)
7741 15:36:35.494593 u2DelayCellOfst[13]=14 cells (4 PI)
7742 15:36:35.497605 u2DelayCellOfst[14]=17 cells (5 PI)
7743 15:36:35.500597 u2DelayCellOfst[15]=10 cells (3 PI)
7744 15:36:35.504232 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7745 15:36:35.507378 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7746 15:36:35.510609 DramC Write-DBI on
7747 15:36:35.510690 ==
7748 15:36:35.514524 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 15:36:35.517802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 15:36:35.517884 ==
7751 15:36:35.517948
7752 15:36:35.518007
7753 15:36:35.520596 TX Vref Scan disable
7754 15:36:35.524224 == TX Byte 0 ==
7755 15:36:35.527441 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7756 15:36:35.527523 == TX Byte 1 ==
7757 15:36:35.534145 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7758 15:36:35.534228 DramC Write-DBI off
7759 15:36:35.534292
7760 15:36:35.537850 [DATLAT]
7761 15:36:35.537931 Freq=1600, CH0 RK0
7762 15:36:35.537996
7763 15:36:35.540978 DATLAT Default: 0xf
7764 15:36:35.541060 0, 0xFFFF, sum = 0
7765 15:36:35.544634 1, 0xFFFF, sum = 0
7766 15:36:35.544732 2, 0xFFFF, sum = 0
7767 15:36:35.547707 3, 0xFFFF, sum = 0
7768 15:36:35.547791 4, 0xFFFF, sum = 0
7769 15:36:35.551206 5, 0xFFFF, sum = 0
7770 15:36:35.551289 6, 0xFFFF, sum = 0
7771 15:36:35.554192 7, 0xFFFF, sum = 0
7772 15:36:35.554307 8, 0xFFFF, sum = 0
7773 15:36:35.557476 9, 0xFFFF, sum = 0
7774 15:36:35.557559 10, 0xFFFF, sum = 0
7775 15:36:35.560837 11, 0xFFFF, sum = 0
7776 15:36:35.560920 12, 0xFFFF, sum = 0
7777 15:36:35.564202 13, 0xFFFF, sum = 0
7778 15:36:35.564285 14, 0x0, sum = 1
7779 15:36:35.567778 15, 0x0, sum = 2
7780 15:36:35.567861 16, 0x0, sum = 3
7781 15:36:35.571097 17, 0x0, sum = 4
7782 15:36:35.571179 best_step = 15
7783 15:36:35.571244
7784 15:36:35.571303 ==
7785 15:36:35.574549 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 15:36:35.580932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 15:36:35.581018 ==
7788 15:36:35.581083 RX Vref Scan: 1
7789 15:36:35.581144
7790 15:36:35.584248 Set Vref Range= 24 -> 127
7791 15:36:35.584328
7792 15:36:35.587638 RX Vref 24 -> 127, step: 1
7793 15:36:35.587720
7794 15:36:35.587784 RX Delay 11 -> 252, step: 4
7795 15:36:35.591137
7796 15:36:35.591218 Set Vref, RX VrefLevel [Byte0]: 24
7797 15:36:35.594271 [Byte1]: 24
7798 15:36:35.598988
7799 15:36:35.599068 Set Vref, RX VrefLevel [Byte0]: 25
7800 15:36:35.602079 [Byte1]: 25
7801 15:36:35.606298
7802 15:36:35.606379 Set Vref, RX VrefLevel [Byte0]: 26
7803 15:36:35.609589 [Byte1]: 26
7804 15:36:35.614171
7805 15:36:35.614252 Set Vref, RX VrefLevel [Byte0]: 27
7806 15:36:35.617682 [Byte1]: 27
7807 15:36:35.621844
7808 15:36:35.621951 Set Vref, RX VrefLevel [Byte0]: 28
7809 15:36:35.624783 [Byte1]: 28
7810 15:36:35.629000
7811 15:36:35.629111 Set Vref, RX VrefLevel [Byte0]: 29
7812 15:36:35.632404 [Byte1]: 29
7813 15:36:35.636941
7814 15:36:35.637050 Set Vref, RX VrefLevel [Byte0]: 30
7815 15:36:35.640505 [Byte1]: 30
7816 15:36:35.644328
7817 15:36:35.644409 Set Vref, RX VrefLevel [Byte0]: 31
7818 15:36:35.647528 [Byte1]: 31
7819 15:36:35.652314
7820 15:36:35.652438 Set Vref, RX VrefLevel [Byte0]: 32
7821 15:36:35.655260 [Byte1]: 32
7822 15:36:35.660142
7823 15:36:35.660254 Set Vref, RX VrefLevel [Byte0]: 33
7824 15:36:35.666324 [Byte1]: 33
7825 15:36:35.666405
7826 15:36:35.669347 Set Vref, RX VrefLevel [Byte0]: 34
7827 15:36:35.672709 [Byte1]: 34
7828 15:36:35.672805
7829 15:36:35.675946 Set Vref, RX VrefLevel [Byte0]: 35
7830 15:36:35.679246 [Byte1]: 35
7831 15:36:35.679327
7832 15:36:35.682954 Set Vref, RX VrefLevel [Byte0]: 36
7833 15:36:35.685721 [Byte1]: 36
7834 15:36:35.690253
7835 15:36:35.690334 Set Vref, RX VrefLevel [Byte0]: 37
7836 15:36:35.693238 [Byte1]: 37
7837 15:36:35.697901
7838 15:36:35.697982 Set Vref, RX VrefLevel [Byte0]: 38
7839 15:36:35.701076 [Byte1]: 38
7840 15:36:35.705544
7841 15:36:35.705625 Set Vref, RX VrefLevel [Byte0]: 39
7842 15:36:35.708739 [Byte1]: 39
7843 15:36:35.712929
7844 15:36:35.713010 Set Vref, RX VrefLevel [Byte0]: 40
7845 15:36:35.716471 [Byte1]: 40
7846 15:36:35.720910
7847 15:36:35.721006 Set Vref, RX VrefLevel [Byte0]: 41
7848 15:36:35.723846 [Byte1]: 41
7849 15:36:35.727901
7850 15:36:35.727981 Set Vref, RX VrefLevel [Byte0]: 42
7851 15:36:35.731172 [Byte1]: 42
7852 15:36:35.735826
7853 15:36:35.735907 Set Vref, RX VrefLevel [Byte0]: 43
7854 15:36:35.738879 [Byte1]: 43
7855 15:36:35.743109
7856 15:36:35.743190 Set Vref, RX VrefLevel [Byte0]: 44
7857 15:36:35.746800 [Byte1]: 44
7858 15:36:35.750954
7859 15:36:35.751035 Set Vref, RX VrefLevel [Byte0]: 45
7860 15:36:35.754434 [Byte1]: 45
7861 15:36:35.758468
7862 15:36:35.758573 Set Vref, RX VrefLevel [Byte0]: 46
7863 15:36:35.761846 [Byte1]: 46
7864 15:36:35.765937
7865 15:36:35.766050 Set Vref, RX VrefLevel [Byte0]: 47
7866 15:36:35.769428 [Byte1]: 47
7867 15:36:35.773602
7868 15:36:35.773743 Set Vref, RX VrefLevel [Byte0]: 48
7869 15:36:35.777077 [Byte1]: 48
7870 15:36:35.781615
7871 15:36:35.781731 Set Vref, RX VrefLevel [Byte0]: 49
7872 15:36:35.784610 [Byte1]: 49
7873 15:36:35.789370
7874 15:36:35.789511 Set Vref, RX VrefLevel [Byte0]: 50
7875 15:36:35.792406 [Byte1]: 50
7876 15:36:35.796480
7877 15:36:35.796578 Set Vref, RX VrefLevel [Byte0]: 51
7878 15:36:35.799851 [Byte1]: 51
7879 15:36:35.804476
7880 15:36:35.804574 Set Vref, RX VrefLevel [Byte0]: 52
7881 15:36:35.807362 [Byte1]: 52
7882 15:36:35.811778
7883 15:36:35.811875 Set Vref, RX VrefLevel [Byte0]: 53
7884 15:36:35.814885 [Byte1]: 53
7885 15:36:35.819466
7886 15:36:35.819549 Set Vref, RX VrefLevel [Byte0]: 54
7887 15:36:35.822497 [Byte1]: 54
7888 15:36:35.826995
7889 15:36:35.827064 Set Vref, RX VrefLevel [Byte0]: 55
7890 15:36:35.830117 [Byte1]: 55
7891 15:36:35.834725
7892 15:36:35.834794 Set Vref, RX VrefLevel [Byte0]: 56
7893 15:36:35.838212 [Byte1]: 56
7894 15:36:35.842112
7895 15:36:35.842199 Set Vref, RX VrefLevel [Byte0]: 57
7896 15:36:35.845405 [Byte1]: 57
7897 15:36:35.849581
7898 15:36:35.849650 Set Vref, RX VrefLevel [Byte0]: 58
7899 15:36:35.853581 [Byte1]: 58
7900 15:36:35.857566
7901 15:36:35.857637 Set Vref, RX VrefLevel [Byte0]: 59
7902 15:36:35.861071 [Byte1]: 59
7903 15:36:35.865140
7904 15:36:35.865223 Set Vref, RX VrefLevel [Byte0]: 60
7905 15:36:35.868188 [Byte1]: 60
7906 15:36:35.872501
7907 15:36:35.872619 Set Vref, RX VrefLevel [Byte0]: 61
7908 15:36:35.875917 [Byte1]: 61
7909 15:36:35.880407
7910 15:36:35.880518 Set Vref, RX VrefLevel [Byte0]: 62
7911 15:36:35.883878 [Byte1]: 62
7912 15:36:35.887643
7913 15:36:35.887736 Set Vref, RX VrefLevel [Byte0]: 63
7914 15:36:35.891005 [Byte1]: 63
7915 15:36:35.895652
7916 15:36:35.895751 Set Vref, RX VrefLevel [Byte0]: 64
7917 15:36:35.898852 [Byte1]: 64
7918 15:36:35.903467
7919 15:36:35.903575 Set Vref, RX VrefLevel [Byte0]: 65
7920 15:36:35.906209 [Byte1]: 65
7921 15:36:35.910871
7922 15:36:35.910946 Set Vref, RX VrefLevel [Byte0]: 66
7923 15:36:35.914013 [Byte1]: 66
7924 15:36:35.918414
7925 15:36:35.918518 Set Vref, RX VrefLevel [Byte0]: 67
7926 15:36:35.921635 [Byte1]: 67
7927 15:36:35.926026
7928 15:36:35.926130 Set Vref, RX VrefLevel [Byte0]: 68
7929 15:36:35.929096 [Byte1]: 68
7930 15:36:35.933694
7931 15:36:35.933847 Set Vref, RX VrefLevel [Byte0]: 69
7932 15:36:35.936773 [Byte1]: 69
7933 15:36:35.941300
7934 15:36:35.941394 Set Vref, RX VrefLevel [Byte0]: 70
7935 15:36:35.944514 [Byte1]: 70
7936 15:36:35.948729
7937 15:36:35.948838 Set Vref, RX VrefLevel [Byte0]: 71
7938 15:36:35.952229 [Byte1]: 71
7939 15:36:35.956640
7940 15:36:35.956761 Set Vref, RX VrefLevel [Byte0]: 72
7941 15:36:35.959565 [Byte1]: 72
7942 15:36:35.964120
7943 15:36:35.964218 Set Vref, RX VrefLevel [Byte0]: 73
7944 15:36:35.967468 [Byte1]: 73
7945 15:36:35.971768
7946 15:36:35.971866 Set Vref, RX VrefLevel [Byte0]: 74
7947 15:36:35.975019 [Byte1]: 74
7948 15:36:35.979687
7949 15:36:35.979784 Set Vref, RX VrefLevel [Byte0]: 75
7950 15:36:35.982414 [Byte1]: 75
7951 15:36:35.986918
7952 15:36:35.987026 Set Vref, RX VrefLevel [Byte0]: 76
7953 15:36:35.990069 [Byte1]: 76
7954 15:36:35.994442
7955 15:36:35.994548 Final RX Vref Byte 0 = 62 to rank0
7956 15:36:35.997652 Final RX Vref Byte 1 = 61 to rank0
7957 15:36:36.001176 Final RX Vref Byte 0 = 62 to rank1
7958 15:36:36.004383 Final RX Vref Byte 1 = 61 to rank1==
7959 15:36:36.007727 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 15:36:36.014404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 15:36:36.014519 ==
7962 15:36:36.014615 DQS Delay:
7963 15:36:36.014704 DQS0 = 0, DQS1 = 0
7964 15:36:36.017915 DQM Delay:
7965 15:36:36.018020 DQM0 = 129, DQM1 = 121
7966 15:36:36.021244 DQ Delay:
7967 15:36:36.024592 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7968 15:36:36.028038 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7969 15:36:36.031512 DQ8 =110, DQ9 =112, DQ10 =122, DQ11 =116
7970 15:36:36.034798 DQ12 =126, DQ13 =126, DQ14 =130, DQ15 =132
7971 15:36:36.034894
7972 15:36:36.034992
7973 15:36:36.035079
7974 15:36:36.038087 [DramC_TX_OE_Calibration] TA2
7975 15:36:36.041339 Original DQ_B0 (3 6) =30, OEN = 27
7976 15:36:36.044363 Original DQ_B1 (3 6) =30, OEN = 27
7977 15:36:36.047842 24, 0x0, End_B0=24 End_B1=24
7978 15:36:36.047919 25, 0x0, End_B0=25 End_B1=25
7979 15:36:36.051253 26, 0x0, End_B0=26 End_B1=26
7980 15:36:36.054465 27, 0x0, End_B0=27 End_B1=27
7981 15:36:36.058261 28, 0x0, End_B0=28 End_B1=28
7982 15:36:36.058337 29, 0x0, End_B0=29 End_B1=29
7983 15:36:36.061692 30, 0x0, End_B0=30 End_B1=30
7984 15:36:36.064631 31, 0x4141, End_B0=30 End_B1=30
7985 15:36:36.068538 Byte0 end_step=30 best_step=27
7986 15:36:36.071289 Byte1 end_step=30 best_step=27
7987 15:36:36.074703 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 15:36:36.074772 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 15:36:36.074843
7990 15:36:36.074990
7991 15:36:36.084777 [DQSOSCAuto] RK0, (LSB)MR18= 0x170b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
7992 15:36:36.088225 CH0 RK0: MR19=303, MR18=170B
7993 15:36:36.094730 CH0_RK0: MR19=0x303, MR18=0x170B, DQSOSC=398, MR23=63, INC=23, DEC=15
7994 15:36:36.094803
7995 15:36:36.097751 ----->DramcWriteLeveling(PI) begin...
7996 15:36:36.097825 ==
7997 15:36:36.101477 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 15:36:36.104556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 15:36:36.104675 ==
8000 15:36:36.107996 Write leveling (Byte 0): 35 => 35
8001 15:36:36.111391 Write leveling (Byte 1): 27 => 27
8002 15:36:36.114894 DramcWriteLeveling(PI) end<-----
8003 15:36:36.114966
8004 15:36:36.115043 ==
8005 15:36:36.118079 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 15:36:36.121383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 15:36:36.121473 ==
8008 15:36:36.124549 [Gating] SW mode calibration
8009 15:36:36.131415 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 15:36:36.138094 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 15:36:36.141320 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 15:36:36.144768 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 15:36:36.148113 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8014 15:36:36.154781 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8015 15:36:36.158318 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8016 15:36:36.161477 1 4 20 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
8017 15:36:36.168137 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 15:36:36.171409 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 15:36:36.175073 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 15:36:36.181512 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 15:36:36.184984 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
8022 15:36:36.188018 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8023 15:36:36.194758 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8024 15:36:36.198222 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
8025 15:36:36.201499 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8026 15:36:36.208484 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 15:36:36.211568 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 15:36:36.215036 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8029 15:36:36.221700 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8030 15:36:36.224932 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8031 15:36:36.228048 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8032 15:36:36.234741 1 6 20 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
8033 15:36:36.238398 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 15:36:36.241564 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 15:36:36.244804 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 15:36:36.251410 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 15:36:36.254654 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8038 15:36:36.258259 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 15:36:36.265124 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8040 15:36:36.268282 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 15:36:36.271779 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8042 15:36:36.278032 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 15:36:36.282417 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 15:36:36.284622 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 15:36:36.291671 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 15:36:36.294835 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 15:36:36.298374 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 15:36:36.305075 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 15:36:36.308239 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 15:36:36.311450 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 15:36:36.318237 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 15:36:36.321365 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 15:36:36.325122 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8054 15:36:36.331548 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8055 15:36:36.331638 Total UI for P1: 0, mck2ui 16
8056 15:36:36.335176 best dqsien dly found for B0: ( 1, 9, 8)
8057 15:36:36.341734 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8058 15:36:36.344953 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8059 15:36:36.348090 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8060 15:36:36.355228 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 15:36:36.357970 Total UI for P1: 0, mck2ui 16
8062 15:36:36.361539 best dqsien dly found for B1: ( 1, 9, 20)
8063 15:36:36.364730 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8064 15:36:36.368058 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8065 15:36:36.368128
8066 15:36:36.371550 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8067 15:36:36.374866 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8068 15:36:36.378236 [Gating] SW calibration Done
8069 15:36:36.378307 ==
8070 15:36:36.381377 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 15:36:36.384631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 15:36:36.384730 ==
8073 15:36:36.388037 RX Vref Scan: 0
8074 15:36:36.388113
8075 15:36:36.388175 RX Vref 0 -> 0, step: 1
8076 15:36:36.391273
8077 15:36:36.391353 RX Delay 0 -> 252, step: 8
8078 15:36:36.394536 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8079 15:36:36.401651 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8080 15:36:36.405158 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8081 15:36:36.408044 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8082 15:36:36.411633 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8083 15:36:36.415258 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8084 15:36:36.422132 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8085 15:36:36.425013 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8086 15:36:36.428206 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8087 15:36:36.431950 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8088 15:36:36.435037 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8089 15:36:36.441387 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8090 15:36:36.444837 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8091 15:36:36.448295 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8092 15:36:36.451576 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8093 15:36:36.455265 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8094 15:36:36.458618 ==
8095 15:36:36.458720 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 15:36:36.465076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 15:36:36.465170 ==
8098 15:36:36.465240 DQS Delay:
8099 15:36:36.468540 DQS0 = 0, DQS1 = 0
8100 15:36:36.468642 DQM Delay:
8101 15:36:36.471438 DQM0 = 131, DQM1 = 124
8102 15:36:36.471512 DQ Delay:
8103 15:36:36.475158 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8104 15:36:36.478499 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8105 15:36:36.481791 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8106 15:36:36.484801 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8107 15:36:36.484922
8108 15:36:36.485021
8109 15:36:36.485125 ==
8110 15:36:36.488237 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 15:36:36.494814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 15:36:36.494930 ==
8113 15:36:36.494998
8114 15:36:36.495058
8115 15:36:36.495116 TX Vref Scan disable
8116 15:36:36.498258 == TX Byte 0 ==
8117 15:36:36.501592 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8118 15:36:36.505016 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8119 15:36:36.508258 == TX Byte 1 ==
8120 15:36:36.511630 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8121 15:36:36.514727 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8122 15:36:36.518673 ==
8123 15:36:36.521658 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 15:36:36.524976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 15:36:36.525075 ==
8126 15:36:36.539308
8127 15:36:36.542740 TX Vref early break, caculate TX vref
8128 15:36:36.545884 TX Vref=16, minBit 9, minWin=21, winSum=373
8129 15:36:36.549276 TX Vref=18, minBit 9, minWin=22, winSum=382
8130 15:36:36.552459 TX Vref=20, minBit 9, minWin=23, winSum=391
8131 15:36:36.556267 TX Vref=22, minBit 9, minWin=23, winSum=396
8132 15:36:36.559665 TX Vref=24, minBit 4, minWin=24, winSum=407
8133 15:36:36.565889 TX Vref=26, minBit 0, minWin=25, winSum=413
8134 15:36:36.569465 TX Vref=28, minBit 0, minWin=25, winSum=418
8135 15:36:36.572779 TX Vref=30, minBit 4, minWin=25, winSum=418
8136 15:36:36.575983 TX Vref=32, minBit 0, minWin=25, winSum=411
8137 15:36:36.579651 TX Vref=34, minBit 1, minWin=24, winSum=401
8138 15:36:36.583192 TX Vref=36, minBit 4, minWin=23, winSum=391
8139 15:36:36.589440 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8140 15:36:36.589519
8141 15:36:36.592754 Final TX Range 0 Vref 28
8142 15:36:36.592849
8143 15:36:36.592916 ==
8144 15:36:36.596168 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 15:36:36.599473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 15:36:36.599574 ==
8147 15:36:36.599668
8148 15:36:36.599755
8149 15:36:36.603188 TX Vref Scan disable
8150 15:36:36.609671 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8151 15:36:36.609776 == TX Byte 0 ==
8152 15:36:36.613156 u2DelayCellOfst[0]=14 cells (4 PI)
8153 15:36:36.616444 u2DelayCellOfst[1]=17 cells (5 PI)
8154 15:36:36.619584 u2DelayCellOfst[2]=10 cells (3 PI)
8155 15:36:36.622887 u2DelayCellOfst[3]=14 cells (4 PI)
8156 15:36:36.626542 u2DelayCellOfst[4]=10 cells (3 PI)
8157 15:36:36.629530 u2DelayCellOfst[5]=0 cells (0 PI)
8158 15:36:36.633428 u2DelayCellOfst[6]=17 cells (5 PI)
8159 15:36:36.636159 u2DelayCellOfst[7]=17 cells (5 PI)
8160 15:36:36.639960 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8161 15:36:36.642997 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8162 15:36:36.646457 == TX Byte 1 ==
8163 15:36:36.646533 u2DelayCellOfst[8]=0 cells (0 PI)
8164 15:36:36.649584 u2DelayCellOfst[9]=0 cells (0 PI)
8165 15:36:36.652956 u2DelayCellOfst[10]=3 cells (1 PI)
8166 15:36:36.656308 u2DelayCellOfst[11]=0 cells (0 PI)
8167 15:36:36.659801 u2DelayCellOfst[12]=14 cells (4 PI)
8168 15:36:36.662965 u2DelayCellOfst[13]=10 cells (3 PI)
8169 15:36:36.666617 u2DelayCellOfst[14]=14 cells (4 PI)
8170 15:36:36.669936 u2DelayCellOfst[15]=10 cells (3 PI)
8171 15:36:36.673158 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8172 15:36:36.679880 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8173 15:36:36.680019 DramC Write-DBI on
8174 15:36:36.680141 ==
8175 15:36:36.683730 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 15:36:36.686587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 15:36:36.686662 ==
8178 15:36:36.686725
8179 15:36:36.689666
8180 15:36:36.689773 TX Vref Scan disable
8181 15:36:36.692939 == TX Byte 0 ==
8182 15:36:36.696709 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8183 15:36:36.699540 == TX Byte 1 ==
8184 15:36:36.703043 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8185 15:36:36.703154 DramC Write-DBI off
8186 15:36:36.706529
8187 15:36:36.706627 [DATLAT]
8188 15:36:36.706729 Freq=1600, CH0 RK1
8189 15:36:36.706819
8190 15:36:36.710012 DATLAT Default: 0xf
8191 15:36:36.710098 0, 0xFFFF, sum = 0
8192 15:36:36.712760 1, 0xFFFF, sum = 0
8193 15:36:36.712862 2, 0xFFFF, sum = 0
8194 15:36:36.716552 3, 0xFFFF, sum = 0
8195 15:36:36.716660 4, 0xFFFF, sum = 0
8196 15:36:36.719431 5, 0xFFFF, sum = 0
8197 15:36:36.722942 6, 0xFFFF, sum = 0
8198 15:36:36.723051 7, 0xFFFF, sum = 0
8199 15:36:36.726085 8, 0xFFFF, sum = 0
8200 15:36:36.726170 9, 0xFFFF, sum = 0
8201 15:36:36.729470 10, 0xFFFF, sum = 0
8202 15:36:36.729544 11, 0xFFFF, sum = 0
8203 15:36:36.733153 12, 0xFFFF, sum = 0
8204 15:36:36.733261 13, 0xFFFF, sum = 0
8205 15:36:36.736398 14, 0x0, sum = 1
8206 15:36:36.736472 15, 0x0, sum = 2
8207 15:36:36.739390 16, 0x0, sum = 3
8208 15:36:36.739490 17, 0x0, sum = 4
8209 15:36:36.743354 best_step = 15
8210 15:36:36.743461
8211 15:36:36.743551 ==
8212 15:36:36.746482 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 15:36:36.749777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 15:36:36.749853 ==
8215 15:36:36.749916 RX Vref Scan: 0
8216 15:36:36.749975
8217 15:36:36.753184 RX Vref 0 -> 0, step: 1
8218 15:36:36.753282
8219 15:36:36.756604 RX Delay 11 -> 252, step: 4
8220 15:36:36.759874 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8221 15:36:36.763154 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8222 15:36:36.770283 iDelay=191, Bit 2, Center 126 (71 ~ 182) 112
8223 15:36:36.773387 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8224 15:36:36.776606 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8225 15:36:36.779935 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8226 15:36:36.783087 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8227 15:36:36.790079 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8228 15:36:36.793485 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8229 15:36:36.796862 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8230 15:36:36.800049 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8231 15:36:36.803457 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8232 15:36:36.810041 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8233 15:36:36.813677 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8234 15:36:36.816585 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8235 15:36:36.820429 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8236 15:36:36.820536 ==
8237 15:36:36.823834 Dram Type= 6, Freq= 0, CH_0, rank 1
8238 15:36:36.826806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 15:36:36.830182 ==
8240 15:36:36.830284 DQS Delay:
8241 15:36:36.830373 DQS0 = 0, DQS1 = 0
8242 15:36:36.833757 DQM Delay:
8243 15:36:36.833827 DQM0 = 128, DQM1 = 122
8244 15:36:36.836478 DQ Delay:
8245 15:36:36.840133 DQ0 =126, DQ1 =130, DQ2 =126, DQ3 =126
8246 15:36:36.843281 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8247 15:36:36.847176 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8248 15:36:36.850306 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8249 15:36:36.850377
8250 15:36:36.850438
8251 15:36:36.850502
8252 15:36:36.853684 [DramC_TX_OE_Calibration] TA2
8253 15:36:36.856905 Original DQ_B0 (3 6) =30, OEN = 27
8254 15:36:36.860174 Original DQ_B1 (3 6) =30, OEN = 27
8255 15:36:36.863247 24, 0x0, End_B0=24 End_B1=24
8256 15:36:36.863370 25, 0x0, End_B0=25 End_B1=25
8257 15:36:36.866637 26, 0x0, End_B0=26 End_B1=26
8258 15:36:36.870001 27, 0x0, End_B0=27 End_B1=27
8259 15:36:36.874038 28, 0x0, End_B0=28 End_B1=28
8260 15:36:36.874123 29, 0x0, End_B0=29 End_B1=29
8261 15:36:36.876866 30, 0x0, End_B0=30 End_B1=30
8262 15:36:36.880680 31, 0x4141, End_B0=30 End_B1=30
8263 15:36:36.883441 Byte0 end_step=30 best_step=27
8264 15:36:36.887211 Byte1 end_step=30 best_step=27
8265 15:36:36.887323 Byte0 TX OE(2T, 0.5T) = (3, 3)
8266 15:36:36.890775 Byte1 TX OE(2T, 0.5T) = (3, 3)
8267 15:36:36.890875
8268 15:36:36.890975
8269 15:36:36.900233 [DQSOSCAuto] RK1, (LSB)MR18= 0x170b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8270 15:36:36.903667 CH0 RK1: MR19=303, MR18=170B
8271 15:36:36.907786 CH0_RK1: MR19=0x303, MR18=0x170B, DQSOSC=398, MR23=63, INC=23, DEC=15
8272 15:36:36.910598 [RxdqsGatingPostProcess] freq 1600
8273 15:36:36.917099 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8274 15:36:36.920775 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 15:36:36.923687 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 15:36:36.927243 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 15:36:36.930045 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 15:36:36.933589 best DQS0 dly(2T, 0.5T) = (1, 1)
8279 15:36:36.933694 best DQS1 dly(2T, 0.5T) = (1, 1)
8280 15:36:36.937142 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8281 15:36:36.940191 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8282 15:36:36.943441 Pre-setting of DQS Precalculation
8283 15:36:36.950268 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8284 15:36:36.950388 ==
8285 15:36:36.953441 Dram Type= 6, Freq= 0, CH_1, rank 0
8286 15:36:36.957050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 15:36:36.957130 ==
8288 15:36:36.963627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8289 15:36:36.967078 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8290 15:36:36.970428 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8291 15:36:36.976943 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8292 15:36:36.985797 [CA 0] Center 42 (14~71) winsize 58
8293 15:36:36.989444 [CA 1] Center 42 (14~71) winsize 58
8294 15:36:36.992562 [CA 2] Center 37 (9~66) winsize 58
8295 15:36:36.996140 [CA 3] Center 36 (7~66) winsize 60
8296 15:36:36.999248 [CA 4] Center 37 (8~66) winsize 59
8297 15:36:37.002585 [CA 5] Center 36 (7~66) winsize 60
8298 15:36:37.002688
8299 15:36:37.005849 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8300 15:36:37.005938
8301 15:36:37.009130 [CATrainingPosCal] consider 1 rank data
8302 15:36:37.012578 u2DelayCellTimex100 = 275/100 ps
8303 15:36:37.016030 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8304 15:36:37.022483 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8305 15:36:37.025721 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8306 15:36:37.029141 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8307 15:36:37.032848 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8308 15:36:37.035818 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8309 15:36:37.035913
8310 15:36:37.039045 CA PerBit enable=1, Macro0, CA PI delay=36
8311 15:36:37.039141
8312 15:36:37.042359 [CBTSetCACLKResult] CA Dly = 36
8313 15:36:37.042429 CS Dly: 9 (0~40)
8314 15:36:37.049465 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8315 15:36:37.052480 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8316 15:36:37.052576 ==
8317 15:36:37.055836 Dram Type= 6, Freq= 0, CH_1, rank 1
8318 15:36:37.059136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 15:36:37.059252 ==
8320 15:36:37.065893 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8321 15:36:37.069984 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8322 15:36:37.072601 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8323 15:36:37.079158 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8324 15:36:37.088930 [CA 0] Center 42 (13~72) winsize 60
8325 15:36:37.092503 [CA 1] Center 43 (14~72) winsize 59
8326 15:36:37.095632 [CA 2] Center 38 (9~67) winsize 59
8327 15:36:37.098966 [CA 3] Center 36 (7~66) winsize 60
8328 15:36:37.102232 [CA 4] Center 37 (8~67) winsize 60
8329 15:36:37.105569 [CA 5] Center 36 (7~66) winsize 60
8330 15:36:37.105654
8331 15:36:37.109294 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8332 15:36:37.109367
8333 15:36:37.112368 [CATrainingPosCal] consider 2 rank data
8334 15:36:37.115680 u2DelayCellTimex100 = 275/100 ps
8335 15:36:37.119008 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8336 15:36:37.125582 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8337 15:36:37.129031 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8338 15:36:37.132392 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8339 15:36:37.135391 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8340 15:36:37.139031 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8341 15:36:37.139129
8342 15:36:37.142617 CA PerBit enable=1, Macro0, CA PI delay=36
8343 15:36:37.142715
8344 15:36:37.145643 [CBTSetCACLKResult] CA Dly = 36
8345 15:36:37.149791 CS Dly: 11 (0~44)
8346 15:36:37.152513 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8347 15:36:37.155492 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8348 15:36:37.155596
8349 15:36:37.158882 ----->DramcWriteLeveling(PI) begin...
8350 15:36:37.158982 ==
8351 15:36:37.162290 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 15:36:37.165483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 15:36:37.169132 ==
8354 15:36:37.169242 Write leveling (Byte 0): 26 => 26
8355 15:36:37.172507 Write leveling (Byte 1): 28 => 28
8356 15:36:37.176104 DramcWriteLeveling(PI) end<-----
8357 15:36:37.176204
8358 15:36:37.176302 ==
8359 15:36:37.178879 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 15:36:37.185756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 15:36:37.185861 ==
8362 15:36:37.185955 [Gating] SW mode calibration
8363 15:36:37.195790 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8364 15:36:37.199116 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8365 15:36:37.202771 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 15:36:37.209578 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 15:36:37.213243 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 15:36:37.215948 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 15:36:37.222538 1 4 16 | B1->B0 | 2d2d 2626 | 0 1 | (0 0) (1 1)
8370 15:36:37.225619 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8371 15:36:37.229179 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 15:36:37.235801 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 15:36:37.239225 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 15:36:37.242231 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 15:36:37.249358 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 15:36:37.253048 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8377 15:36:37.255870 1 5 16 | B1->B0 | 2b2b 3232 | 0 1 | (0 1) (1 0)
8378 15:36:37.262752 1 5 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
8379 15:36:37.265846 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 15:36:37.269104 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 15:36:37.272765 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 15:36:37.279364 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 15:36:37.282434 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 15:36:37.286061 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 15:36:37.292789 1 6 16 | B1->B0 | 3a3a 3535 | 0 1 | (0 0) (0 0)
8386 15:36:37.296038 1 6 20 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8387 15:36:37.299544 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 15:36:37.306201 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 15:36:37.310098 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 15:36:37.312887 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 15:36:37.319442 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 15:36:37.322985 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8393 15:36:37.326002 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8394 15:36:37.333028 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8395 15:36:37.336155 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 15:36:37.339569 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 15:36:37.342726 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 15:36:37.349541 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 15:36:37.352818 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 15:36:37.356212 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 15:36:37.362828 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 15:36:37.366288 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 15:36:37.369523 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 15:36:37.376593 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 15:36:37.379562 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 15:36:37.383678 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 15:36:37.389834 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 15:36:37.393046 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 15:36:37.396479 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8410 15:36:37.403126 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 15:36:37.403208 Total UI for P1: 0, mck2ui 16
8412 15:36:37.406574 best dqsien dly found for B0: ( 1, 9, 16)
8413 15:36:37.409933 Total UI for P1: 0, mck2ui 16
8414 15:36:37.413453 best dqsien dly found for B1: ( 1, 9, 16)
8415 15:36:37.416268 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8416 15:36:37.419916 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8417 15:36:37.423239
8418 15:36:37.426271 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8419 15:36:37.429510 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8420 15:36:37.433638 [Gating] SW calibration Done
8421 15:36:37.433747 ==
8422 15:36:37.436964 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 15:36:37.439900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 15:36:37.439973 ==
8425 15:36:37.440036 RX Vref Scan: 0
8426 15:36:37.443147
8427 15:36:37.443253 RX Vref 0 -> 0, step: 1
8428 15:36:37.443344
8429 15:36:37.446580 RX Delay 0 -> 252, step: 8
8430 15:36:37.449602 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8431 15:36:37.453218 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8432 15:36:37.459846 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8433 15:36:37.462937 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8434 15:36:37.466242 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8435 15:36:37.469585 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8436 15:36:37.473088 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8437 15:36:37.476420 iDelay=208, Bit 7, Center 127 (72 ~ 183) 112
8438 15:36:37.483402 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8439 15:36:37.486854 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8440 15:36:37.490250 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8441 15:36:37.493611 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8442 15:36:37.496943 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8443 15:36:37.503564 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8444 15:36:37.506713 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8445 15:36:37.510297 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8446 15:36:37.510412 ==
8447 15:36:37.513337 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 15:36:37.516778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 15:36:37.516866 ==
8450 15:36:37.520156 DQS Delay:
8451 15:36:37.520267 DQS0 = 0, DQS1 = 0
8452 15:36:37.523702 DQM Delay:
8453 15:36:37.523787 DQM0 = 134, DQM1 = 127
8454 15:36:37.526853 DQ Delay:
8455 15:36:37.530415 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8456 15:36:37.533242 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8457 15:36:37.537239 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8458 15:36:37.540095 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8459 15:36:37.540179
8460 15:36:37.540245
8461 15:36:37.540306 ==
8462 15:36:37.543534 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 15:36:37.546853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 15:36:37.546938 ==
8465 15:36:37.547005
8466 15:36:37.547066
8467 15:36:37.550003 TX Vref Scan disable
8468 15:36:37.553683 == TX Byte 0 ==
8469 15:36:37.556805 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8470 15:36:37.560290 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8471 15:36:37.563926 == TX Byte 1 ==
8472 15:36:37.567186 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8473 15:36:37.570517 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8474 15:36:37.570622 ==
8475 15:36:37.573651 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 15:36:37.576769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 15:36:37.579913 ==
8478 15:36:37.592212
8479 15:36:37.595643 TX Vref early break, caculate TX vref
8480 15:36:37.598834 TX Vref=16, minBit 11, minWin=20, winSum=358
8481 15:36:37.602221 TX Vref=18, minBit 8, minWin=21, winSum=368
8482 15:36:37.605828 TX Vref=20, minBit 8, minWin=22, winSum=382
8483 15:36:37.608495 TX Vref=22, minBit 0, minWin=23, winSum=388
8484 15:36:37.611886 TX Vref=24, minBit 5, minWin=23, winSum=400
8485 15:36:37.619055 TX Vref=26, minBit 5, minWin=24, winSum=407
8486 15:36:37.622257 TX Vref=28, minBit 8, minWin=25, winSum=416
8487 15:36:37.625654 TX Vref=30, minBit 5, minWin=25, winSum=416
8488 15:36:37.628937 TX Vref=32, minBit 0, minWin=25, winSum=410
8489 15:36:37.632313 TX Vref=34, minBit 8, minWin=23, winSum=397
8490 15:36:37.635792 TX Vref=36, minBit 8, minWin=23, winSum=387
8491 15:36:37.642483 [TxChooseVref] Worse bit 8, Min win 25, Win sum 416, Final Vref 28
8492 15:36:37.642567
8493 15:36:37.645854 Final TX Range 0 Vref 28
8494 15:36:37.645930
8495 15:36:37.646000 ==
8496 15:36:37.649221 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 15:36:37.652394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 15:36:37.652472 ==
8499 15:36:37.652544
8500 15:36:37.652605
8501 15:36:37.655870 TX Vref Scan disable
8502 15:36:37.662100 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8503 15:36:37.662189 == TX Byte 0 ==
8504 15:36:37.665492 u2DelayCellOfst[0]=14 cells (4 PI)
8505 15:36:37.668852 u2DelayCellOfst[1]=10 cells (3 PI)
8506 15:36:37.672226 u2DelayCellOfst[2]=0 cells (0 PI)
8507 15:36:37.675671 u2DelayCellOfst[3]=7 cells (2 PI)
8508 15:36:37.678810 u2DelayCellOfst[4]=10 cells (3 PI)
8509 15:36:37.681946 u2DelayCellOfst[5]=21 cells (6 PI)
8510 15:36:37.685682 u2DelayCellOfst[6]=17 cells (5 PI)
8511 15:36:37.688926 u2DelayCellOfst[7]=7 cells (2 PI)
8512 15:36:37.691966 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8513 15:36:37.695427 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8514 15:36:37.698800 == TX Byte 1 ==
8515 15:36:37.698875 u2DelayCellOfst[8]=0 cells (0 PI)
8516 15:36:37.702108 u2DelayCellOfst[9]=7 cells (2 PI)
8517 15:36:37.705412 u2DelayCellOfst[10]=10 cells (3 PI)
8518 15:36:37.708786 u2DelayCellOfst[11]=7 cells (2 PI)
8519 15:36:37.712251 u2DelayCellOfst[12]=14 cells (4 PI)
8520 15:36:37.715199 u2DelayCellOfst[13]=17 cells (5 PI)
8521 15:36:37.718680 u2DelayCellOfst[14]=17 cells (5 PI)
8522 15:36:37.722100 u2DelayCellOfst[15]=17 cells (5 PI)
8523 15:36:37.725579 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8524 15:36:37.731987 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8525 15:36:37.732066 DramC Write-DBI on
8526 15:36:37.732137 ==
8527 15:36:37.735408 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 15:36:37.739877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 15:36:37.741962 ==
8530 15:36:37.742039
8531 15:36:37.742109
8532 15:36:37.742170 TX Vref Scan disable
8533 15:36:37.745453 == TX Byte 0 ==
8534 15:36:37.748268 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8535 15:36:37.751790 == TX Byte 1 ==
8536 15:36:37.755666 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8537 15:36:37.758660 DramC Write-DBI off
8538 15:36:37.758749
8539 15:36:37.758815 [DATLAT]
8540 15:36:37.758875 Freq=1600, CH1 RK0
8541 15:36:37.758957
8542 15:36:37.762349 DATLAT Default: 0xf
8543 15:36:37.762421 0, 0xFFFF, sum = 0
8544 15:36:37.765380 1, 0xFFFF, sum = 0
8545 15:36:37.765453 2, 0xFFFF, sum = 0
8546 15:36:37.769295 3, 0xFFFF, sum = 0
8547 15:36:37.769373 4, 0xFFFF, sum = 0
8548 15:36:37.772314 5, 0xFFFF, sum = 0
8549 15:36:37.775500 6, 0xFFFF, sum = 0
8550 15:36:37.775648 7, 0xFFFF, sum = 0
8551 15:36:37.778599 8, 0xFFFF, sum = 0
8552 15:36:37.778674 9, 0xFFFF, sum = 0
8553 15:36:37.782008 10, 0xFFFF, sum = 0
8554 15:36:37.782086 11, 0xFFFF, sum = 0
8555 15:36:37.785273 12, 0xFFFF, sum = 0
8556 15:36:37.785358 13, 0xFFFF, sum = 0
8557 15:36:37.788680 14, 0x0, sum = 1
8558 15:36:37.788762 15, 0x0, sum = 2
8559 15:36:37.791945 16, 0x0, sum = 3
8560 15:36:37.792017 17, 0x0, sum = 4
8561 15:36:37.795246 best_step = 15
8562 15:36:37.795348
8563 15:36:37.795434 ==
8564 15:36:37.798655 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 15:36:37.802643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 15:36:37.802722 ==
8567 15:36:37.802794 RX Vref Scan: 1
8568 15:36:37.802855
8569 15:36:37.805409 Set Vref Range= 24 -> 127
8570 15:36:37.805482
8571 15:36:37.808651 RX Vref 24 -> 127, step: 1
8572 15:36:37.808749
8573 15:36:37.811830 RX Delay 11 -> 252, step: 4
8574 15:36:37.811913
8575 15:36:37.815294 Set Vref, RX VrefLevel [Byte0]: 24
8576 15:36:37.818911 [Byte1]: 24
8577 15:36:37.818988
8578 15:36:37.822644 Set Vref, RX VrefLevel [Byte0]: 25
8579 15:36:37.825251 [Byte1]: 25
8580 15:36:37.825338
8581 15:36:37.829378 Set Vref, RX VrefLevel [Byte0]: 26
8582 15:36:37.832021 [Byte1]: 26
8583 15:36:37.836056
8584 15:36:37.836138 Set Vref, RX VrefLevel [Byte0]: 27
8585 15:36:37.838920 [Byte1]: 27
8586 15:36:37.843365
8587 15:36:37.843471 Set Vref, RX VrefLevel [Byte0]: 28
8588 15:36:37.846911 [Byte1]: 28
8589 15:36:37.850798
8590 15:36:37.850904 Set Vref, RX VrefLevel [Byte0]: 29
8591 15:36:37.854375 [Byte1]: 29
8592 15:36:37.858705
8593 15:36:37.858795 Set Vref, RX VrefLevel [Byte0]: 30
8594 15:36:37.861813 [Byte1]: 30
8595 15:36:37.866220
8596 15:36:37.866304 Set Vref, RX VrefLevel [Byte0]: 31
8597 15:36:37.869780 [Byte1]: 31
8598 15:36:37.873856
8599 15:36:37.873934 Set Vref, RX VrefLevel [Byte0]: 32
8600 15:36:37.877563 [Byte1]: 32
8601 15:36:37.881150
8602 15:36:37.881220 Set Vref, RX VrefLevel [Byte0]: 33
8603 15:36:37.884834 [Byte1]: 33
8604 15:36:37.888949
8605 15:36:37.889028 Set Vref, RX VrefLevel [Byte0]: 34
8606 15:36:37.892167 [Byte1]: 34
8607 15:36:37.897001
8608 15:36:37.897073 Set Vref, RX VrefLevel [Byte0]: 35
8609 15:36:37.899984 [Byte1]: 35
8610 15:36:37.904040
8611 15:36:37.904117 Set Vref, RX VrefLevel [Byte0]: 36
8612 15:36:37.907532 [Byte1]: 36
8613 15:36:37.911676
8614 15:36:37.911750 Set Vref, RX VrefLevel [Byte0]: 37
8615 15:36:37.915130 [Byte1]: 37
8616 15:36:37.919489
8617 15:36:37.919573 Set Vref, RX VrefLevel [Byte0]: 38
8618 15:36:37.922831 [Byte1]: 38
8619 15:36:37.927071
8620 15:36:37.927158 Set Vref, RX VrefLevel [Byte0]: 39
8621 15:36:37.930595 [Byte1]: 39
8622 15:36:37.934939
8623 15:36:37.935025 Set Vref, RX VrefLevel [Byte0]: 40
8624 15:36:37.938203 [Byte1]: 40
8625 15:36:37.942536
8626 15:36:37.942616 Set Vref, RX VrefLevel [Byte0]: 41
8627 15:36:37.945562 [Byte1]: 41
8628 15:36:37.949793
8629 15:36:37.949906 Set Vref, RX VrefLevel [Byte0]: 42
8630 15:36:37.953322 [Byte1]: 42
8631 15:36:37.957452
8632 15:36:37.957566 Set Vref, RX VrefLevel [Byte0]: 43
8633 15:36:37.961162 [Byte1]: 43
8634 15:36:37.965332
8635 15:36:37.965443 Set Vref, RX VrefLevel [Byte0]: 44
8636 15:36:37.968738 [Byte1]: 44
8637 15:36:37.972764
8638 15:36:37.972842 Set Vref, RX VrefLevel [Byte0]: 45
8639 15:36:37.976142 [Byte1]: 45
8640 15:36:37.980328
8641 15:36:37.980411 Set Vref, RX VrefLevel [Byte0]: 46
8642 15:36:37.983571 [Byte1]: 46
8643 15:36:37.987838
8644 15:36:37.987915 Set Vref, RX VrefLevel [Byte0]: 47
8645 15:36:37.991092 [Byte1]: 47
8646 15:36:37.995654
8647 15:36:37.995737 Set Vref, RX VrefLevel [Byte0]: 48
8648 15:36:37.998918 [Byte1]: 48
8649 15:36:38.003125
8650 15:36:38.003216 Set Vref, RX VrefLevel [Byte0]: 49
8651 15:36:38.006561 [Byte1]: 49
8652 15:36:38.010895
8653 15:36:38.011011 Set Vref, RX VrefLevel [Byte0]: 50
8654 15:36:38.013982 [Byte1]: 50
8655 15:36:38.018505
8656 15:36:38.018586 Set Vref, RX VrefLevel [Byte0]: 51
8657 15:36:38.021838 [Byte1]: 51
8658 15:36:38.026675
8659 15:36:38.026775 Set Vref, RX VrefLevel [Byte0]: 52
8660 15:36:38.029376 [Byte1]: 52
8661 15:36:38.033760
8662 15:36:38.033848 Set Vref, RX VrefLevel [Byte0]: 53
8663 15:36:38.037090 [Byte1]: 53
8664 15:36:38.041396
8665 15:36:38.041473 Set Vref, RX VrefLevel [Byte0]: 54
8666 15:36:38.044563 [Byte1]: 54
8667 15:36:38.048976
8668 15:36:38.049059 Set Vref, RX VrefLevel [Byte0]: 55
8669 15:36:38.052456 [Byte1]: 55
8670 15:36:38.056552
8671 15:36:38.056643 Set Vref, RX VrefLevel [Byte0]: 56
8672 15:36:38.059560 [Byte1]: 56
8673 15:36:38.064224
8674 15:36:38.064331 Set Vref, RX VrefLevel [Byte0]: 57
8675 15:36:38.067593 [Byte1]: 57
8676 15:36:38.071845
8677 15:36:38.071928 Set Vref, RX VrefLevel [Byte0]: 58
8678 15:36:38.075204 [Byte1]: 58
8679 15:36:38.079445
8680 15:36:38.079544 Set Vref, RX VrefLevel [Byte0]: 59
8681 15:36:38.082880 [Byte1]: 59
8682 15:36:38.087264
8683 15:36:38.087350 Set Vref, RX VrefLevel [Byte0]: 60
8684 15:36:38.090204 [Byte1]: 60
8685 15:36:38.094587
8686 15:36:38.094671 Set Vref, RX VrefLevel [Byte0]: 61
8687 15:36:38.097725 [Byte1]: 61
8688 15:36:38.102272
8689 15:36:38.102357 Set Vref, RX VrefLevel [Byte0]: 62
8690 15:36:38.105258 [Byte1]: 62
8691 15:36:38.109675
8692 15:36:38.109761 Set Vref, RX VrefLevel [Byte0]: 63
8693 15:36:38.112961 [Byte1]: 63
8694 15:36:38.117491
8695 15:36:38.117592 Set Vref, RX VrefLevel [Byte0]: 64
8696 15:36:38.120766 [Byte1]: 64
8697 15:36:38.124883
8698 15:36:38.124967 Set Vref, RX VrefLevel [Byte0]: 65
8699 15:36:38.128306 [Byte1]: 65
8700 15:36:38.132659
8701 15:36:38.132751 Set Vref, RX VrefLevel [Byte0]: 66
8702 15:36:38.135720 [Byte1]: 66
8703 15:36:38.140509
8704 15:36:38.140593 Set Vref, RX VrefLevel [Byte0]: 67
8705 15:36:38.144209 [Byte1]: 67
8706 15:36:38.147876
8707 15:36:38.147959 Set Vref, RX VrefLevel [Byte0]: 68
8708 15:36:38.151071 [Byte1]: 68
8709 15:36:38.155407
8710 15:36:38.155490 Set Vref, RX VrefLevel [Byte0]: 69
8711 15:36:38.158561 [Byte1]: 69
8712 15:36:38.163235
8713 15:36:38.163346 Set Vref, RX VrefLevel [Byte0]: 70
8714 15:36:38.166398 [Byte1]: 70
8715 15:36:38.171140
8716 15:36:38.171223 Set Vref, RX VrefLevel [Byte0]: 71
8717 15:36:38.174227 [Byte1]: 71
8718 15:36:38.178540
8719 15:36:38.178624 Set Vref, RX VrefLevel [Byte0]: 72
8720 15:36:38.181999 [Byte1]: 72
8721 15:36:38.186088
8722 15:36:38.186197 Set Vref, RX VrefLevel [Byte0]: 73
8723 15:36:38.189119 [Byte1]: 73
8724 15:36:38.193463
8725 15:36:38.193561 Set Vref, RX VrefLevel [Byte0]: 74
8726 15:36:38.196589 [Byte1]: 74
8727 15:36:38.201239
8728 15:36:38.201372 Set Vref, RX VrefLevel [Byte0]: 75
8729 15:36:38.204569 [Byte1]: 75
8730 15:36:38.208878
8731 15:36:38.208977 Final RX Vref Byte 0 = 57 to rank0
8732 15:36:38.212542 Final RX Vref Byte 1 = 56 to rank0
8733 15:36:38.215304 Final RX Vref Byte 0 = 57 to rank1
8734 15:36:38.218794 Final RX Vref Byte 1 = 56 to rank1==
8735 15:36:38.222302 Dram Type= 6, Freq= 0, CH_1, rank 0
8736 15:36:38.228511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 15:36:38.228615 ==
8738 15:36:38.228739 DQS Delay:
8739 15:36:38.228802 DQS0 = 0, DQS1 = 0
8740 15:36:38.231990 DQM Delay:
8741 15:36:38.232056 DQM0 = 131, DQM1 = 124
8742 15:36:38.235385 DQ Delay:
8743 15:36:38.238890 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8744 15:36:38.242113 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8745 15:36:38.245575 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8746 15:36:38.248535 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8747 15:36:38.248608
8748 15:36:38.248739
8749 15:36:38.248819
8750 15:36:38.252213 [DramC_TX_OE_Calibration] TA2
8751 15:36:38.255089 Original DQ_B0 (3 6) =30, OEN = 27
8752 15:36:38.258745 Original DQ_B1 (3 6) =30, OEN = 27
8753 15:36:38.261768 24, 0x0, End_B0=24 End_B1=24
8754 15:36:38.261848 25, 0x0, End_B0=25 End_B1=25
8755 15:36:38.265488 26, 0x0, End_B0=26 End_B1=26
8756 15:36:38.268966 27, 0x0, End_B0=27 End_B1=27
8757 15:36:38.271848 28, 0x0, End_B0=28 End_B1=28
8758 15:36:38.271927 29, 0x0, End_B0=29 End_B1=29
8759 15:36:38.275360 30, 0x0, End_B0=30 End_B1=30
8760 15:36:38.278844 31, 0x4141, End_B0=30 End_B1=30
8761 15:36:38.281917 Byte0 end_step=30 best_step=27
8762 15:36:38.284979 Byte1 end_step=30 best_step=27
8763 15:36:38.288715 Byte0 TX OE(2T, 0.5T) = (3, 3)
8764 15:36:38.288792 Byte1 TX OE(2T, 0.5T) = (3, 3)
8765 15:36:38.291972
8766 15:36:38.292047
8767 15:36:38.299161 [DQSOSCAuto] RK0, (LSB)MR18= 0x1802, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 397 ps
8768 15:36:38.302090 CH1 RK0: MR19=303, MR18=1802
8769 15:36:38.308342 CH1_RK0: MR19=0x303, MR18=0x1802, DQSOSC=397, MR23=63, INC=23, DEC=15
8770 15:36:38.308419
8771 15:36:38.311508 ----->DramcWriteLeveling(PI) begin...
8772 15:36:38.311587 ==
8773 15:36:38.314957 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 15:36:38.318692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 15:36:38.318791 ==
8776 15:36:38.321667 Write leveling (Byte 0): 27 => 27
8777 15:36:38.325136 Write leveling (Byte 1): 27 => 27
8778 15:36:38.328852 DramcWriteLeveling(PI) end<-----
8779 15:36:38.328924
8780 15:36:38.329003 ==
8781 15:36:38.331632 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 15:36:38.335049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 15:36:38.335124 ==
8784 15:36:38.338368 [Gating] SW mode calibration
8785 15:36:38.345412 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8786 15:36:38.351943 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8787 15:36:38.355263 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 15:36:38.358789 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 15:36:38.365510 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8790 15:36:38.368589 1 4 12 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8791 15:36:38.371980 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 15:36:38.379100 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 15:36:38.382206 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 15:36:38.385678 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 15:36:38.391965 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 15:36:38.395273 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8797 15:36:38.398742 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
8798 15:36:38.402207 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
8799 15:36:38.408919 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 15:36:38.412071 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 15:36:38.415127 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 15:36:38.421862 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 15:36:38.425342 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 15:36:38.428842 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8805 15:36:38.435273 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8806 15:36:38.438783 1 6 12 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
8807 15:36:38.441999 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 15:36:38.449042 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 15:36:38.452248 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 15:36:38.455405 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 15:36:38.461963 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 15:36:38.465790 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8813 15:36:38.469111 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8814 15:36:38.475819 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8815 15:36:38.479084 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8816 15:36:38.482261 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8817 15:36:38.488928 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 15:36:38.492074 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 15:36:38.495299 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 15:36:38.498657 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 15:36:38.505313 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 15:36:38.508819 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 15:36:38.511937 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 15:36:38.519231 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 15:36:38.522212 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 15:36:38.525403 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 15:36:38.532574 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 15:36:38.535397 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8829 15:36:38.538802 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8830 15:36:38.545436 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8831 15:36:38.545513 Total UI for P1: 0, mck2ui 16
8832 15:36:38.552221 best dqsien dly found for B0: ( 1, 9, 6)
8833 15:36:38.555643 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8834 15:36:38.559092 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 15:36:38.562253 Total UI for P1: 0, mck2ui 16
8836 15:36:38.565568 best dqsien dly found for B1: ( 1, 9, 14)
8837 15:36:38.568794 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8838 15:36:38.572335 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8839 15:36:38.572406
8840 15:36:38.575784 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8841 15:36:38.582506 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8842 15:36:38.582579 [Gating] SW calibration Done
8843 15:36:38.582641 ==
8844 15:36:38.585876 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 15:36:38.592284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 15:36:38.592359 ==
8847 15:36:38.592429 RX Vref Scan: 0
8848 15:36:38.592489
8849 15:36:38.595709 RX Vref 0 -> 0, step: 1
8850 15:36:38.595777
8851 15:36:38.599077 RX Delay 0 -> 252, step: 8
8852 15:36:38.602253 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8853 15:36:38.605552 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8854 15:36:38.608917 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8855 15:36:38.612514 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8856 15:36:38.619355 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8857 15:36:38.622776 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8858 15:36:38.625709 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8859 15:36:38.628934 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8860 15:36:38.632570 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8861 15:36:38.639025 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8862 15:36:38.642618 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8863 15:36:38.645898 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8864 15:36:38.649440 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8865 15:36:38.652415 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8866 15:36:38.659243 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8867 15:36:38.662478 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8868 15:36:38.662582 ==
8869 15:36:38.665934 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 15:36:38.669188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 15:36:38.669270 ==
8872 15:36:38.669342 DQS Delay:
8873 15:36:38.673148 DQS0 = 0, DQS1 = 0
8874 15:36:38.673238 DQM Delay:
8875 15:36:38.675899 DQM0 = 132, DQM1 = 127
8876 15:36:38.675970 DQ Delay:
8877 15:36:38.679233 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8878 15:36:38.682417 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8879 15:36:38.685583 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8880 15:36:38.692813 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8881 15:36:38.692902
8882 15:36:38.692967
8883 15:36:38.693026 ==
8884 15:36:38.695733 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 15:36:38.699213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 15:36:38.699330 ==
8887 15:36:38.699396
8888 15:36:38.699455
8889 15:36:38.702629 TX Vref Scan disable
8890 15:36:38.702766 == TX Byte 0 ==
8891 15:36:38.709038 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8892 15:36:38.712270 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8893 15:36:38.712401 == TX Byte 1 ==
8894 15:36:38.719116 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8895 15:36:38.722588 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8896 15:36:38.722710 ==
8897 15:36:38.725630 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 15:36:38.729470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 15:36:38.729557 ==
8900 15:36:38.743387
8901 15:36:38.747066 TX Vref early break, caculate TX vref
8902 15:36:38.750042 TX Vref=16, minBit 8, minWin=22, winSum=376
8903 15:36:38.753215 TX Vref=18, minBit 9, minWin=23, winSum=386
8904 15:36:38.756589 TX Vref=20, minBit 9, minWin=23, winSum=396
8905 15:36:38.759950 TX Vref=22, minBit 6, minWin=24, winSum=396
8906 15:36:38.763696 TX Vref=24, minBit 5, minWin=24, winSum=408
8907 15:36:38.770212 TX Vref=26, minBit 10, minWin=25, winSum=417
8908 15:36:38.773785 TX Vref=28, minBit 5, minWin=25, winSum=420
8909 15:36:38.776556 TX Vref=30, minBit 0, minWin=24, winSum=419
8910 15:36:38.779995 TX Vref=32, minBit 0, minWin=25, winSum=416
8911 15:36:38.783429 TX Vref=34, minBit 0, minWin=24, winSum=400
8912 15:36:38.786812 TX Vref=36, minBit 0, minWin=24, winSum=394
8913 15:36:38.793858 [TxChooseVref] Worse bit 5, Min win 25, Win sum 420, Final Vref 28
8914 15:36:38.793958
8915 15:36:38.796645 Final TX Range 0 Vref 28
8916 15:36:38.796753
8917 15:36:38.796848 ==
8918 15:36:38.799989 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 15:36:38.803571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 15:36:38.803655 ==
8921 15:36:38.803720
8922 15:36:38.803781
8923 15:36:38.806861 TX Vref Scan disable
8924 15:36:38.813531 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8925 15:36:38.813646 == TX Byte 0 ==
8926 15:36:38.816899 u2DelayCellOfst[0]=17 cells (5 PI)
8927 15:36:38.820024 u2DelayCellOfst[1]=14 cells (4 PI)
8928 15:36:38.823415 u2DelayCellOfst[2]=0 cells (0 PI)
8929 15:36:38.826842 u2DelayCellOfst[3]=7 cells (2 PI)
8930 15:36:38.830231 u2DelayCellOfst[4]=10 cells (3 PI)
8931 15:36:38.833399 u2DelayCellOfst[5]=17 cells (5 PI)
8932 15:36:38.836952 u2DelayCellOfst[6]=17 cells (5 PI)
8933 15:36:38.840545 u2DelayCellOfst[7]=7 cells (2 PI)
8934 15:36:38.843480 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8935 15:36:38.846838 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8936 15:36:38.850945 == TX Byte 1 ==
8937 15:36:38.851029 u2DelayCellOfst[8]=0 cells (0 PI)
8938 15:36:38.853777 u2DelayCellOfst[9]=3 cells (1 PI)
8939 15:36:38.857122 u2DelayCellOfst[10]=10 cells (3 PI)
8940 15:36:38.860390 u2DelayCellOfst[11]=7 cells (2 PI)
8941 15:36:38.863536 u2DelayCellOfst[12]=14 cells (4 PI)
8942 15:36:38.866864 u2DelayCellOfst[13]=14 cells (4 PI)
8943 15:36:38.870554 u2DelayCellOfst[14]=17 cells (5 PI)
8944 15:36:38.873519 u2DelayCellOfst[15]=14 cells (4 PI)
8945 15:36:38.876955 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8946 15:36:38.883871 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8947 15:36:38.883958 DramC Write-DBI on
8948 15:36:38.884026 ==
8949 15:36:38.887136 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 15:36:38.890755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 15:36:38.890889 ==
8952 15:36:38.894033
8953 15:36:38.894117
8954 15:36:38.894183 TX Vref Scan disable
8955 15:36:38.897505 == TX Byte 0 ==
8956 15:36:38.900611 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8957 15:36:38.903536 == TX Byte 1 ==
8958 15:36:38.907166 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8959 15:36:38.907294 DramC Write-DBI off
8960 15:36:38.907359
8961 15:36:38.910643 [DATLAT]
8962 15:36:38.910736 Freq=1600, CH1 RK1
8963 15:36:38.910803
8964 15:36:38.914260 DATLAT Default: 0xf
8965 15:36:38.914358 0, 0xFFFF, sum = 0
8966 15:36:38.917325 1, 0xFFFF, sum = 0
8967 15:36:38.917439 2, 0xFFFF, sum = 0
8968 15:36:38.920858 3, 0xFFFF, sum = 0
8969 15:36:38.920942 4, 0xFFFF, sum = 0
8970 15:36:38.924287 5, 0xFFFF, sum = 0
8971 15:36:38.924370 6, 0xFFFF, sum = 0
8972 15:36:38.927229 7, 0xFFFF, sum = 0
8973 15:36:38.927338 8, 0xFFFF, sum = 0
8974 15:36:38.930906 9, 0xFFFF, sum = 0
8975 15:36:38.930989 10, 0xFFFF, sum = 0
8976 15:36:38.934162 11, 0xFFFF, sum = 0
8977 15:36:38.937333 12, 0xFFFF, sum = 0
8978 15:36:38.937416 13, 0xFFFF, sum = 0
8979 15:36:38.940918 14, 0x0, sum = 1
8980 15:36:38.941001 15, 0x0, sum = 2
8981 15:36:38.941096 16, 0x0, sum = 3
8982 15:36:38.943981 17, 0x0, sum = 4
8983 15:36:38.944080 best_step = 15
8984 15:36:38.944178
8985 15:36:38.947401 ==
8986 15:36:38.947483 Dram Type= 6, Freq= 0, CH_1, rank 1
8987 15:36:38.953992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8988 15:36:38.954093 ==
8989 15:36:38.954172 RX Vref Scan: 0
8990 15:36:38.954231
8991 15:36:38.957469 RX Vref 0 -> 0, step: 1
8992 15:36:38.957551
8993 15:36:38.960760 RX Delay 11 -> 252, step: 4
8994 15:36:38.963812 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8995 15:36:38.967508 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8996 15:36:38.973826 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8997 15:36:38.977384 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8998 15:36:38.981003 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8999 15:36:38.984127 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9000 15:36:38.987089 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9001 15:36:38.994192 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9002 15:36:38.997064 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9003 15:36:39.000551 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9004 15:36:39.004134 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
9005 15:36:39.007062 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9006 15:36:39.013616 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9007 15:36:39.017028 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9008 15:36:39.020482 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9009 15:36:39.024042 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9010 15:36:39.024161 ==
9011 15:36:39.027007 Dram Type= 6, Freq= 0, CH_1, rank 1
9012 15:36:39.033775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9013 15:36:39.033893 ==
9014 15:36:39.033987 DQS Delay:
9015 15:36:39.034095 DQS0 = 0, DQS1 = 0
9016 15:36:39.037122 DQM Delay:
9017 15:36:39.037230 DQM0 = 129, DQM1 = 126
9018 15:36:39.041050 DQ Delay:
9019 15:36:39.043711 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9020 15:36:39.047229 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9021 15:36:39.050531 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =118
9022 15:36:39.054191 DQ12 =134, DQ13 =136, DQ14 =136, DQ15 =136
9023 15:36:39.054306
9024 15:36:39.054409
9025 15:36:39.054500
9026 15:36:39.057292 [DramC_TX_OE_Calibration] TA2
9027 15:36:39.060861 Original DQ_B0 (3 6) =30, OEN = 27
9028 15:36:39.064089 Original DQ_B1 (3 6) =30, OEN = 27
9029 15:36:39.067547 24, 0x0, End_B0=24 End_B1=24
9030 15:36:39.067665 25, 0x0, End_B0=25 End_B1=25
9031 15:36:39.070244 26, 0x0, End_B0=26 End_B1=26
9032 15:36:39.073709 27, 0x0, End_B0=27 End_B1=27
9033 15:36:39.077154 28, 0x0, End_B0=28 End_B1=28
9034 15:36:39.077279 29, 0x0, End_B0=29 End_B1=29
9035 15:36:39.080687 30, 0x0, End_B0=30 End_B1=30
9036 15:36:39.083854 31, 0x4141, End_B0=30 End_B1=30
9037 15:36:39.087536 Byte0 end_step=30 best_step=27
9038 15:36:39.090665 Byte1 end_step=30 best_step=27
9039 15:36:39.094252 Byte0 TX OE(2T, 0.5T) = (3, 3)
9040 15:36:39.094371 Byte1 TX OE(2T, 0.5T) = (3, 3)
9041 15:36:39.094475
9042 15:36:39.094567
9043 15:36:39.104116 [DQSOSCAuto] RK1, (LSB)MR18= 0xf15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9044 15:36:39.107655 CH1 RK1: MR19=303, MR18=F15
9045 15:36:39.110762 CH1_RK1: MR19=0x303, MR18=0xF15, DQSOSC=399, MR23=63, INC=23, DEC=15
9046 15:36:39.114087 [RxdqsGatingPostProcess] freq 1600
9047 15:36:39.121025 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9048 15:36:39.124089 best DQS0 dly(2T, 0.5T) = (1, 1)
9049 15:36:39.127637 best DQS1 dly(2T, 0.5T) = (1, 1)
9050 15:36:39.130775 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9051 15:36:39.134069 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9052 15:36:39.137864 best DQS0 dly(2T, 0.5T) = (1, 1)
9053 15:36:39.137976 best DQS1 dly(2T, 0.5T) = (1, 1)
9054 15:36:39.140755 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9055 15:36:39.144180 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9056 15:36:39.147524 Pre-setting of DQS Precalculation
9057 15:36:39.154177 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9058 15:36:39.160837 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9059 15:36:39.167410 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9060 15:36:39.167521
9061 15:36:39.167625
9062 15:36:39.170693 [Calibration Summary] 3200 Mbps
9063 15:36:39.170809 CH 0, Rank 0
9064 15:36:39.174299 SW Impedance : PASS
9065 15:36:39.177287 DUTY Scan : NO K
9066 15:36:39.177365 ZQ Calibration : PASS
9067 15:36:39.180769 Jitter Meter : NO K
9068 15:36:39.185104 CBT Training : PASS
9069 15:36:39.185188 Write leveling : PASS
9070 15:36:39.187501 RX DQS gating : PASS
9071 15:36:39.191369 RX DQ/DQS(RDDQC) : PASS
9072 15:36:39.191453 TX DQ/DQS : PASS
9073 15:36:39.194187 RX DATLAT : PASS
9074 15:36:39.194297 RX DQ/DQS(Engine): PASS
9075 15:36:39.197861 TX OE : PASS
9076 15:36:39.197945 All Pass.
9077 15:36:39.198011
9078 15:36:39.201357 CH 0, Rank 1
9079 15:36:39.201441 SW Impedance : PASS
9080 15:36:39.204797 DUTY Scan : NO K
9081 15:36:39.207992 ZQ Calibration : PASS
9082 15:36:39.208076 Jitter Meter : NO K
9083 15:36:39.210703 CBT Training : PASS
9084 15:36:39.214561 Write leveling : PASS
9085 15:36:39.214645 RX DQS gating : PASS
9086 15:36:39.217634 RX DQ/DQS(RDDQC) : PASS
9087 15:36:39.220860 TX DQ/DQS : PASS
9088 15:36:39.220955 RX DATLAT : PASS
9089 15:36:39.224198 RX DQ/DQS(Engine): PASS
9090 15:36:39.227429 TX OE : PASS
9091 15:36:39.227513 All Pass.
9092 15:36:39.227579
9093 15:36:39.227640 CH 1, Rank 0
9094 15:36:39.231028 SW Impedance : PASS
9095 15:36:39.234054 DUTY Scan : NO K
9096 15:36:39.234138 ZQ Calibration : PASS
9097 15:36:39.237374 Jitter Meter : NO K
9098 15:36:39.241349 CBT Training : PASS
9099 15:36:39.241433 Write leveling : PASS
9100 15:36:39.244393 RX DQS gating : PASS
9101 15:36:39.244477 RX DQ/DQS(RDDQC) : PASS
9102 15:36:39.247836 TX DQ/DQS : PASS
9103 15:36:39.250981 RX DATLAT : PASS
9104 15:36:39.251065 RX DQ/DQS(Engine): PASS
9105 15:36:39.253973 TX OE : PASS
9106 15:36:39.254057 All Pass.
9107 15:36:39.254124
9108 15:36:39.257333 CH 1, Rank 1
9109 15:36:39.257416 SW Impedance : PASS
9110 15:36:39.261277 DUTY Scan : NO K
9111 15:36:39.264315 ZQ Calibration : PASS
9112 15:36:39.264399 Jitter Meter : NO K
9113 15:36:39.267454 CBT Training : PASS
9114 15:36:39.270742 Write leveling : PASS
9115 15:36:39.270825 RX DQS gating : PASS
9116 15:36:39.274170 RX DQ/DQS(RDDQC) : PASS
9117 15:36:39.277843 TX DQ/DQS : PASS
9118 15:36:39.277927 RX DATLAT : PASS
9119 15:36:39.281481 RX DQ/DQS(Engine): PASS
9120 15:36:39.281581 TX OE : PASS
9121 15:36:39.284404 All Pass.
9122 15:36:39.284516
9123 15:36:39.284582 DramC Write-DBI on
9124 15:36:39.287438 PER_BANK_REFRESH: Hybrid Mode
9125 15:36:39.291158 TX_TRACKING: ON
9126 15:36:39.297898 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9127 15:36:39.307756 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9128 15:36:39.314435 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9129 15:36:39.318084 [FAST_K] Save calibration result to emmc
9130 15:36:39.321604 sync common calibartion params.
9131 15:36:39.321704 sync cbt_mode0:1, 1:1
9132 15:36:39.324424 dram_init: ddr_geometry: 2
9133 15:36:39.327846 dram_init: ddr_geometry: 2
9134 15:36:39.327929 dram_init: ddr_geometry: 2
9135 15:36:39.331461 0:dram_rank_size:100000000
9136 15:36:39.334214 1:dram_rank_size:100000000
9137 15:36:39.341211 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9138 15:36:39.341328 DFS_SHUFFLE_HW_MODE: ON
9139 15:36:39.344604 dramc_set_vcore_voltage set vcore to 725000
9140 15:36:39.347710 Read voltage for 1600, 0
9141 15:36:39.347803 Vio18 = 0
9142 15:36:39.351234 Vcore = 725000
9143 15:36:39.351318 Vdram = 0
9144 15:36:39.351382 Vddq = 0
9145 15:36:39.354601 Vmddr = 0
9146 15:36:39.354684 switch to 3200 Mbps bootup
9147 15:36:39.357601 [DramcRunTimeConfig]
9148 15:36:39.357704 PHYPLL
9149 15:36:39.361528 DPM_CONTROL_AFTERK: ON
9150 15:36:39.361623 PER_BANK_REFRESH: ON
9151 15:36:39.364634 REFRESH_OVERHEAD_REDUCTION: ON
9152 15:36:39.367878 CMD_PICG_NEW_MODE: OFF
9153 15:36:39.367954 XRTWTW_NEW_MODE: ON
9154 15:36:39.370881 XRTRTR_NEW_MODE: ON
9155 15:36:39.370957 TX_TRACKING: ON
9156 15:36:39.374352 RDSEL_TRACKING: OFF
9157 15:36:39.377849 DQS Precalculation for DVFS: ON
9158 15:36:39.377955 RX_TRACKING: OFF
9159 15:36:39.381136 HW_GATING DBG: ON
9160 15:36:39.381216 ZQCS_ENABLE_LP4: ON
9161 15:36:39.384279 RX_PICG_NEW_MODE: ON
9162 15:36:39.384364 TX_PICG_NEW_MODE: ON
9163 15:36:39.387691 ENABLE_RX_DCM_DPHY: ON
9164 15:36:39.391223 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9165 15:36:39.394780 DUMMY_READ_FOR_TRACKING: OFF
9166 15:36:39.394858 !!! SPM_CONTROL_AFTERK: OFF
9167 15:36:39.397816 !!! SPM could not control APHY
9168 15:36:39.401456 IMPEDANCE_TRACKING: ON
9169 15:36:39.401543 TEMP_SENSOR: ON
9170 15:36:39.404198 HW_SAVE_FOR_SR: OFF
9171 15:36:39.407870 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9172 15:36:39.410870 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9173 15:36:39.410945 Read ODT Tracking: ON
9174 15:36:39.414243 Refresh Rate DeBounce: ON
9175 15:36:39.417917 DFS_NO_QUEUE_FLUSH: ON
9176 15:36:39.421483 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9177 15:36:39.421564 ENABLE_DFS_RUNTIME_MRW: OFF
9178 15:36:39.424270 DDR_RESERVE_NEW_MODE: ON
9179 15:36:39.427480 MR_CBT_SWITCH_FREQ: ON
9180 15:36:39.427568 =========================
9181 15:36:39.447908 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9182 15:36:39.451481 dram_init: ddr_geometry: 2
9183 15:36:39.469707 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9184 15:36:39.472812 dram_init: dram init end (result: 0)
9185 15:36:39.479727 DRAM-K: Full calibration passed in 24594 msecs
9186 15:36:39.482978 MRC: failed to locate region type 0.
9187 15:36:39.483056 DRAM rank0 size:0x100000000,
9188 15:36:39.486749 DRAM rank1 size=0x100000000
9189 15:36:39.496512 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9190 15:36:39.502972 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9191 15:36:39.510140 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9192 15:36:39.516698 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9193 15:36:39.520205 DRAM rank0 size:0x100000000,
9194 15:36:39.523530 DRAM rank1 size=0x100000000
9195 15:36:39.523616 CBMEM:
9196 15:36:39.526893 IMD: root @ 0xfffff000 254 entries.
9197 15:36:39.529926 IMD: root @ 0xffffec00 62 entries.
9198 15:36:39.533058 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9199 15:36:39.536616 WARNING: RO_VPD is uninitialized or empty.
9200 15:36:39.542743 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9201 15:36:39.549888 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9202 15:36:39.562211 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9203 15:36:39.573800 BS: romstage times (exec / console): total (unknown) / 24100 ms
9204 15:36:39.573924
9205 15:36:39.574020
9206 15:36:39.583729 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9207 15:36:39.587245 ARM64: Exception handlers installed.
9208 15:36:39.590336 ARM64: Testing exception
9209 15:36:39.594037 ARM64: Done test exception
9210 15:36:39.594117 Enumerating buses...
9211 15:36:39.597610 Show all devs... Before device enumeration.
9212 15:36:39.600756 Root Device: enabled 1
9213 15:36:39.603592 CPU_CLUSTER: 0: enabled 1
9214 15:36:39.603668 CPU: 00: enabled 1
9215 15:36:39.607183 Compare with tree...
9216 15:36:39.607258 Root Device: enabled 1
9217 15:36:39.610808 CPU_CLUSTER: 0: enabled 1
9218 15:36:39.613810 CPU: 00: enabled 1
9219 15:36:39.613888 Root Device scanning...
9220 15:36:39.617311 scan_static_bus for Root Device
9221 15:36:39.620554 CPU_CLUSTER: 0 enabled
9222 15:36:39.624169 scan_static_bus for Root Device done
9223 15:36:39.626925 scan_bus: bus Root Device finished in 8 msecs
9224 15:36:39.627008 done
9225 15:36:39.634249 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9226 15:36:39.637601 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9227 15:36:39.644158 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9228 15:36:39.647259 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9229 15:36:39.650656 Allocating resources...
9230 15:36:39.650736 Reading resources...
9231 15:36:39.657176 Root Device read_resources bus 0 link: 0
9232 15:36:39.657251 DRAM rank0 size:0x100000000,
9233 15:36:39.660460 DRAM rank1 size=0x100000000
9234 15:36:39.663960 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9235 15:36:39.667242 CPU: 00 missing read_resources
9236 15:36:39.670591 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9237 15:36:39.677662 Root Device read_resources bus 0 link: 0 done
9238 15:36:39.677739 Done reading resources.
9239 15:36:39.684200 Show resources in subtree (Root Device)...After reading.
9240 15:36:39.687917 Root Device child on link 0 CPU_CLUSTER: 0
9241 15:36:39.690932 CPU_CLUSTER: 0 child on link 0 CPU: 00
9242 15:36:39.700872 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9243 15:36:39.700955 CPU: 00
9244 15:36:39.704065 Root Device assign_resources, bus 0 link: 0
9245 15:36:39.707617 CPU_CLUSTER: 0 missing set_resources
9246 15:36:39.711110 Root Device assign_resources, bus 0 link: 0 done
9247 15:36:39.714194 Done setting resources.
9248 15:36:39.721295 Show resources in subtree (Root Device)...After assigning values.
9249 15:36:39.724251 Root Device child on link 0 CPU_CLUSTER: 0
9250 15:36:39.727853 CPU_CLUSTER: 0 child on link 0 CPU: 00
9251 15:36:39.734698 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9252 15:36:39.737735 CPU: 00
9253 15:36:39.740961 Done allocating resources.
9254 15:36:39.744384 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9255 15:36:39.747803 Enabling resources...
9256 15:36:39.747892 done.
9257 15:36:39.751148 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9258 15:36:39.754699 Initializing devices...
9259 15:36:39.754778 Root Device init
9260 15:36:39.757439 init hardware done!
9261 15:36:39.760975 0x00000018: ctrlr->caps
9262 15:36:39.761061 52.000 MHz: ctrlr->f_max
9263 15:36:39.764536 0.400 MHz: ctrlr->f_min
9264 15:36:39.767438 0x40ff8080: ctrlr->voltages
9265 15:36:39.767554 sclk: 390625
9266 15:36:39.767647 Bus Width = 1
9267 15:36:39.770543 sclk: 390625
9268 15:36:39.770654 Bus Width = 1
9269 15:36:39.773924 Early init status = 3
9270 15:36:39.777379 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9271 15:36:39.781467 in-header: 03 fc 00 00 01 00 00 00
9272 15:36:39.784548 in-data: 00
9273 15:36:39.788030 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9274 15:36:39.793022 in-header: 03 fd 00 00 00 00 00 00
9275 15:36:39.796634 in-data:
9276 15:36:39.799857 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9277 15:36:39.803899 in-header: 03 fc 00 00 01 00 00 00
9278 15:36:39.807250 in-data: 00
9279 15:36:39.810137 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9280 15:36:39.816008 in-header: 03 fd 00 00 00 00 00 00
9281 15:36:39.819861 in-data:
9282 15:36:39.822784 [SSUSB] Setting up USB HOST controller...
9283 15:36:39.826082 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9284 15:36:39.829517 [SSUSB] phy power-on done.
9285 15:36:39.832858 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9286 15:36:39.839591 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9287 15:36:39.842756 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9288 15:36:39.849686 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9289 15:36:39.856218 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9290 15:36:39.862882 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9291 15:36:39.869656 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9292 15:36:39.872993 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9293 15:36:39.876556 SPM: binary array size = 0x9dc
9294 15:36:39.883469 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9295 15:36:39.889960 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9296 15:36:39.896426 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9297 15:36:39.899841 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9298 15:36:39.903215 configure_display: Starting display init
9299 15:36:39.939238 anx7625_power_on_init: Init interface.
9300 15:36:39.943049 anx7625_disable_pd_protocol: Disabled PD feature.
9301 15:36:39.946014 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9302 15:36:39.974249 anx7625_start_dp_work: Secure OCM version=00
9303 15:36:39.977175 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9304 15:36:39.991672 sp_tx_get_edid_block: EDID Block = 1
9305 15:36:40.094441 Extracted contents:
9306 15:36:40.098132 header: 00 ff ff ff ff ff ff 00
9307 15:36:40.101202 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9308 15:36:40.104836 version: 01 04
9309 15:36:40.108137 basic params: 95 1f 11 78 0a
9310 15:36:40.111054 chroma info: 76 90 94 55 54 90 27 21 50 54
9311 15:36:40.114639 established: 00 00 00
9312 15:36:40.121339 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9313 15:36:40.124537 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9314 15:36:40.131129 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9315 15:36:40.137908 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9316 15:36:40.144445 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9317 15:36:40.147944 extensions: 00
9318 15:36:40.148067 checksum: fb
9319 15:36:40.148162
9320 15:36:40.151438 Manufacturer: IVO Model 57d Serial Number 0
9321 15:36:40.154255 Made week 0 of 2020
9322 15:36:40.154379 EDID version: 1.4
9323 15:36:40.157681 Digital display
9324 15:36:40.161339 6 bits per primary color channel
9325 15:36:40.161453 DisplayPort interface
9326 15:36:40.164631 Maximum image size: 31 cm x 17 cm
9327 15:36:40.164770 Gamma: 220%
9328 15:36:40.168224 Check DPMS levels
9329 15:36:40.171056 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9330 15:36:40.174192 First detailed timing is preferred timing
9331 15:36:40.177884 Established timings supported:
9332 15:36:40.181342 Standard timings supported:
9333 15:36:40.181457 Detailed timings
9334 15:36:40.187668 Hex of detail: 383680a07038204018303c0035ae10000019
9335 15:36:40.191059 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9336 15:36:40.194476 0780 0798 07c8 0820 hborder 0
9337 15:36:40.201033 0438 043b 0447 0458 vborder 0
9338 15:36:40.201113 -hsync -vsync
9339 15:36:40.204337 Did detailed timing
9340 15:36:40.207923 Hex of detail: 000000000000000000000000000000000000
9341 15:36:40.211302 Manufacturer-specified data, tag 0
9342 15:36:40.218152 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9343 15:36:40.218250 ASCII string: InfoVision
9344 15:36:40.224695 Hex of detail: 000000fe00523134304e574635205248200a
9345 15:36:40.224805 ASCII string: R140NWF5 RH
9346 15:36:40.228183 Checksum
9347 15:36:40.228292 Checksum: 0xfb (valid)
9348 15:36:40.234277 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9349 15:36:40.234387 DSI data_rate: 832800000 bps
9350 15:36:40.242257 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9351 15:36:40.245137 anx7625_parse_edid: pixelclock(138800).
9352 15:36:40.248697 hactive(1920), hsync(48), hfp(24), hbp(88)
9353 15:36:40.252032 vactive(1080), vsync(12), vfp(3), vbp(17)
9354 15:36:40.255241 anx7625_dsi_config: config dsi.
9355 15:36:40.262475 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9356 15:36:40.276368 anx7625_dsi_config: success to config DSI
9357 15:36:40.279769 anx7625_dp_start: MIPI phy setup OK.
9358 15:36:40.283252 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9359 15:36:40.286856 mtk_ddp_mode_set invalid vrefresh 60
9360 15:36:40.290249 main_disp_path_setup
9361 15:36:40.290407 ovl_layer_smi_id_en
9362 15:36:40.293208 ovl_layer_smi_id_en
9363 15:36:40.293318 ccorr_config
9364 15:36:40.293418 aal_config
9365 15:36:40.296631 gamma_config
9366 15:36:40.296775 postmask_config
9367 15:36:40.299928 dither_config
9368 15:36:40.303361 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9369 15:36:40.309982 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9370 15:36:40.313555 Root Device init finished in 553 msecs
9371 15:36:40.313722 CPU_CLUSTER: 0 init
9372 15:36:40.323361 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9373 15:36:40.326803 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9374 15:36:40.330104 APU_MBOX 0x190000b0 = 0x10001
9375 15:36:40.333835 APU_MBOX 0x190001b0 = 0x10001
9376 15:36:40.337376 APU_MBOX 0x190005b0 = 0x10001
9377 15:36:40.337490 APU_MBOX 0x190006b0 = 0x10001
9378 15:36:40.343522 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9379 15:36:40.355537 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9380 15:36:40.367887 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9381 15:36:40.374680 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9382 15:36:40.386238 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9383 15:36:40.395072 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9384 15:36:40.398732 CPU_CLUSTER: 0 init finished in 81 msecs
9385 15:36:40.401995 Devices initialized
9386 15:36:40.405703 Show all devs... After init.
9387 15:36:40.405787 Root Device: enabled 1
9388 15:36:40.409296 CPU_CLUSTER: 0: enabled 1
9389 15:36:40.411741 CPU: 00: enabled 1
9390 15:36:40.415343 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9391 15:36:40.418532 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9392 15:36:40.422472 ELOG: NV offset 0x57f000 size 0x1000
9393 15:36:40.428747 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9394 15:36:40.435379 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9395 15:36:40.438808 ELOG: Event(17) added with size 13 at 2023-08-22 15:36:45 UTC
9396 15:36:40.441802 out: cmd=0x121: 03 db 21 01 00 00 00 00
9397 15:36:40.446168 in-header: 03 c2 00 00 2c 00 00 00
9398 15:36:40.459222 in-data: 9d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9399 15:36:40.466050 ELOG: Event(A1) added with size 10 at 2023-08-22 15:36:45 UTC
9400 15:36:40.472757 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9401 15:36:40.476507 ELOG: Event(A0) added with size 9 at 2023-08-22 15:36:45 UTC
9402 15:36:40.482895 elog_add_boot_reason: Logged dev mode boot
9403 15:36:40.486298 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9404 15:36:40.489601 Finalize devices...
9405 15:36:40.489694 Devices finalized
9406 15:36:40.496347 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9407 15:36:40.499712 Writing coreboot table at 0xffe64000
9408 15:36:40.502876 0. 000000000010a000-0000000000113fff: RAMSTAGE
9409 15:36:40.506414 1. 0000000040000000-00000000400fffff: RAM
9410 15:36:40.509859 2. 0000000040100000-000000004032afff: RAMSTAGE
9411 15:36:40.513509 3. 000000004032b000-00000000545fffff: RAM
9412 15:36:40.519376 4. 0000000054600000-000000005465ffff: BL31
9413 15:36:40.523029 5. 0000000054660000-00000000ffe63fff: RAM
9414 15:36:40.526682 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9415 15:36:40.533155 7. 0000000100000000-000000023fffffff: RAM
9416 15:36:40.533238 Passing 5 GPIOs to payload:
9417 15:36:40.539877 NAME | PORT | POLARITY | VALUE
9418 15:36:40.543065 EC in RW | 0x000000aa | low | undefined
9419 15:36:40.546503 EC interrupt | 0x00000005 | low | undefined
9420 15:36:40.553151 TPM interrupt | 0x000000ab | high | undefined
9421 15:36:40.556569 SD card detect | 0x00000011 | high | undefined
9422 15:36:40.563019 speaker enable | 0x00000093 | high | undefined
9423 15:36:40.566327 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9424 15:36:40.569756 in-header: 03 f9 00 00 02 00 00 00
9425 15:36:40.569840 in-data: 02 00
9426 15:36:40.573002 ADC[4]: Raw value=899114 ID=7
9427 15:36:40.576849 ADC[3]: Raw value=213336 ID=1
9428 15:36:40.576932 RAM Code: 0x71
9429 15:36:40.579435 ADC[6]: Raw value=74926 ID=0
9430 15:36:40.582925 ADC[5]: Raw value=212229 ID=1
9431 15:36:40.583007 SKU Code: 0x1
9432 15:36:40.589722 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ae81
9433 15:36:40.593149 coreboot table: 964 bytes.
9434 15:36:40.596981 IMD ROOT 0. 0xfffff000 0x00001000
9435 15:36:40.597062 IMD SMALL 1. 0xffffe000 0x00001000
9436 15:36:40.599994 RO MCACHE 2. 0xffffc000 0x00001104
9437 15:36:40.603314 CONSOLE 3. 0xfff7c000 0x00080000
9438 15:36:40.606817 FMAP 4. 0xfff7b000 0x00000452
9439 15:36:40.609849 TIME STAMP 5. 0xfff7a000 0x00000910
9440 15:36:40.613519 VBOOT WORK 6. 0xfff66000 0x00014000
9441 15:36:40.616805 RAMOOPS 7. 0xffe66000 0x00100000
9442 15:36:40.620504 COREBOOT 8. 0xffe64000 0x00002000
9443 15:36:40.623226 IMD small region:
9444 15:36:40.626753 IMD ROOT 0. 0xffffec00 0x00000400
9445 15:36:40.629805 VPD 1. 0xffffeb80 0x0000006c
9446 15:36:40.633547 MMC STATUS 2. 0xffffeb60 0x00000004
9447 15:36:40.636862 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9448 15:36:40.640058 Probing TPM: done!
9449 15:36:40.643845 Connected to device vid:did:rid of 1ae0:0028:00
9450 15:36:40.654977 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9451 15:36:40.658145 Initialized TPM device CR50 revision 0
9452 15:36:40.661893 Checking cr50 for pending updates
9453 15:36:40.665718 Reading cr50 TPM mode
9454 15:36:40.674235 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9455 15:36:40.680900 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9456 15:36:40.721695 read SPI 0x3990ec 0x4f1b0: 34856 us, 9295 KB/s, 74.360 Mbps
9457 15:36:40.724502 Checking segment from ROM address 0x40100000
9458 15:36:40.727469 Checking segment from ROM address 0x4010001c
9459 15:36:40.734187 Loading segment from ROM address 0x40100000
9460 15:36:40.734265 code (compression=0)
9461 15:36:40.741642 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9462 15:36:40.751421 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9463 15:36:40.751505 it's not compressed!
9464 15:36:40.758400 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9465 15:36:40.761181 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9466 15:36:40.781746 Loading segment from ROM address 0x4010001c
9467 15:36:40.781856 Entry Point 0x80000000
9468 15:36:40.784736 Loaded segments
9469 15:36:40.787962 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9470 15:36:40.794928 Jumping to boot code at 0x80000000(0xffe64000)
9471 15:36:40.801793 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9472 15:36:40.808312 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9473 15:36:40.815667 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9474 15:36:40.819330 Checking segment from ROM address 0x40100000
9475 15:36:40.822575 Checking segment from ROM address 0x4010001c
9476 15:36:40.829421 Loading segment from ROM address 0x40100000
9477 15:36:40.829571 code (compression=1)
9478 15:36:40.835789 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9479 15:36:40.846032 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9480 15:36:40.846145 using LZMA
9481 15:36:40.854287 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9482 15:36:40.860854 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9483 15:36:40.864190 Loading segment from ROM address 0x4010001c
9484 15:36:40.864295 Entry Point 0x54601000
9485 15:36:40.867732 Loaded segments
9486 15:36:40.871089 NOTICE: MT8192 bl31_setup
9487 15:36:40.877883 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9488 15:36:40.881319 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9489 15:36:40.884541 WARNING: region 0:
9490 15:36:40.888170 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 15:36:40.888258 WARNING: region 1:
9492 15:36:40.894344 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9493 15:36:40.897779 WARNING: region 2:
9494 15:36:40.901308 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9495 15:36:40.904566 WARNING: region 3:
9496 15:36:40.908027 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9497 15:36:40.911307 WARNING: region 4:
9498 15:36:40.914641 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9499 15:36:40.917749 WARNING: region 5:
9500 15:36:40.921103 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 15:36:40.924602 WARNING: region 6:
9502 15:36:40.928270 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 15:36:40.928355 WARNING: region 7:
9504 15:36:40.934702 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 15:36:40.941444 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9506 15:36:40.944900 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9507 15:36:40.948226 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9508 15:36:40.951847 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9509 15:36:40.958409 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9510 15:36:40.962013 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9511 15:36:40.968506 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9512 15:36:40.971783 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9513 15:36:40.975069 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9514 15:36:40.981718 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9515 15:36:40.985240 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9516 15:36:40.988344 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9517 15:36:40.995197 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9518 15:36:40.999190 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9519 15:36:41.001832 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9520 15:36:41.008526 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9521 15:36:41.011781 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9522 15:36:41.018870 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9523 15:36:41.022150 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9524 15:36:41.025383 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9525 15:36:41.031883 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9526 15:36:41.035264 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9527 15:36:41.039492 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9528 15:36:41.045371 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9529 15:36:41.048697 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9530 15:36:41.055592 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9531 15:36:41.058920 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9532 15:36:41.062179 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9533 15:36:41.068719 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9534 15:36:41.072331 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9535 15:36:41.079091 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9536 15:36:41.082336 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9537 15:36:41.085936 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9538 15:36:41.089119 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9539 15:36:41.096165 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9540 15:36:41.099475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9541 15:36:41.102726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9542 15:36:41.106010 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9543 15:36:41.109334 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9544 15:36:41.116284 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9545 15:36:41.119413 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9546 15:36:41.123429 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9547 15:36:41.126852 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9548 15:36:41.133145 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9549 15:36:41.136281 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9550 15:36:41.139520 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9551 15:36:41.142870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9552 15:36:41.149944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9553 15:36:41.153020 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9554 15:36:41.159574 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9555 15:36:41.163223 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9556 15:36:41.166619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9557 15:36:41.173142 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9558 15:36:41.176860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9559 15:36:41.183441 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9560 15:36:41.186703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9561 15:36:41.189907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9562 15:36:41.196858 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9563 15:36:41.200061 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9564 15:36:41.206597 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9565 15:36:41.209887 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9566 15:36:41.216908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9567 15:36:41.220060 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9568 15:36:41.223405 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9569 15:36:41.230011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9570 15:36:41.233559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9571 15:36:41.240395 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9572 15:36:41.243540 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9573 15:36:41.247086 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9574 15:36:41.254025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9575 15:36:41.256894 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9576 15:36:41.264000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9577 15:36:41.267332 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9578 15:36:41.273985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9579 15:36:41.277132 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9580 15:36:41.280647 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9581 15:36:41.287276 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9582 15:36:41.291219 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9583 15:36:41.297996 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9584 15:36:41.300871 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9585 15:36:41.307954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9586 15:36:41.311240 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9587 15:36:41.314483 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9588 15:36:41.321345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9589 15:36:41.324544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9590 15:36:41.331295 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9591 15:36:41.334588 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9592 15:36:41.337986 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9593 15:36:41.344603 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9594 15:36:41.348239 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9595 15:36:41.354751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9596 15:36:41.358025 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9597 15:36:41.365425 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9598 15:36:41.367879 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9599 15:36:41.374766 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9600 15:36:41.377837 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9601 15:36:41.381423 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9602 15:36:41.384899 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9603 15:36:41.391786 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9604 15:36:41.394577 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9605 15:36:41.398212 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9606 15:36:41.404872 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9607 15:36:41.407996 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9608 15:36:41.411565 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9609 15:36:41.417921 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9610 15:36:41.421128 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9611 15:36:41.428532 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9612 15:36:41.431519 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9613 15:36:41.434690 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9614 15:36:41.441393 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9615 15:36:41.444696 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9616 15:36:41.447932 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9617 15:36:41.454865 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9618 15:36:41.458061 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9619 15:36:41.464735 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9620 15:36:41.468187 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9621 15:36:41.471794 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9622 15:36:41.478148 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9623 15:36:41.481679 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9624 15:36:41.485518 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9625 15:36:41.488973 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9626 15:36:41.495067 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9627 15:36:41.498675 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9628 15:36:41.501710 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9629 15:36:41.505184 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9630 15:36:41.511690 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9631 15:36:41.515750 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9632 15:36:41.521868 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9633 15:36:41.525392 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9634 15:36:41.528610 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9635 15:36:41.535260 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9636 15:36:41.539009 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9637 15:36:41.542356 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9638 15:36:41.549400 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9639 15:36:41.552176 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9640 15:36:41.558649 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9641 15:36:41.562425 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9642 15:36:41.565823 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9643 15:36:41.572774 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9644 15:36:41.575949 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9645 15:36:41.578828 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9646 15:36:41.585496 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9647 15:36:41.589035 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9648 15:36:41.595957 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9649 15:36:41.599244 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9650 15:36:41.602691 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9651 15:36:41.609591 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9652 15:36:41.613060 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9653 15:36:41.616209 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9654 15:36:41.622613 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9655 15:36:41.626159 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9656 15:36:41.632897 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9657 15:36:41.636071 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9658 15:36:41.639800 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9659 15:36:41.646295 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9660 15:36:41.649250 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9661 15:36:41.652769 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9662 15:36:41.659342 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9663 15:36:41.662867 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9664 15:36:41.669673 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9665 15:36:41.672678 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9666 15:36:41.676068 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9667 15:36:41.683029 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9668 15:36:41.685919 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9669 15:36:41.692633 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9670 15:36:41.696314 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9671 15:36:41.699513 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9672 15:36:41.706118 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9673 15:36:41.709570 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9674 15:36:41.712696 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9675 15:36:41.719982 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9676 15:36:41.722830 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9677 15:36:41.729696 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9678 15:36:41.732917 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9679 15:36:41.736639 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9680 15:36:41.743390 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9681 15:36:41.746424 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9682 15:36:41.753240 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9683 15:36:41.756533 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9684 15:36:41.759563 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9685 15:36:41.766311 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9686 15:36:41.769733 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9687 15:36:41.773017 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9688 15:36:41.779709 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9689 15:36:41.782999 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9690 15:36:41.789534 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9691 15:36:41.793115 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9692 15:36:41.796529 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9693 15:36:41.803037 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9694 15:36:41.806212 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9695 15:36:41.813524 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9696 15:36:41.816741 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9697 15:36:41.819731 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9698 15:36:41.826457 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9699 15:36:41.829697 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9700 15:36:41.836618 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9701 15:36:41.839577 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9702 15:36:41.843402 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9703 15:36:41.849941 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9704 15:36:41.853018 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9705 15:36:41.859877 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9706 15:36:41.863166 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9707 15:36:41.866760 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9708 15:36:41.873646 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9709 15:36:41.876314 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9710 15:36:41.883714 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9711 15:36:41.886782 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9712 15:36:41.889853 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9713 15:36:41.896351 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9714 15:36:41.900121 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9715 15:36:41.906378 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9716 15:36:41.909675 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9717 15:36:41.917090 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9718 15:36:41.919991 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9719 15:36:41.923331 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9720 15:36:41.929821 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9721 15:36:41.933446 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9722 15:36:41.939782 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9723 15:36:41.943468 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9724 15:36:41.946751 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9725 15:36:41.953331 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9726 15:36:41.956654 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9727 15:36:41.963696 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9728 15:36:41.966754 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9729 15:36:41.970248 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9730 15:36:41.976717 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9731 15:36:41.980120 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9732 15:36:41.986987 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9733 15:36:41.990333 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9734 15:36:41.993325 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9735 15:36:41.997154 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9736 15:36:42.003634 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9737 15:36:42.007240 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9738 15:36:42.010345 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9739 15:36:42.013844 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9740 15:36:42.020553 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9741 15:36:42.023931 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9742 15:36:42.030200 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9743 15:36:42.033987 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9744 15:36:42.037090 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9745 15:36:42.043735 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9746 15:36:42.046963 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9747 15:36:42.050514 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9748 15:36:42.056859 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9749 15:36:42.060717 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9750 15:36:42.063908 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9751 15:36:42.070253 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9752 15:36:42.073617 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9753 15:36:42.077538 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9754 15:36:42.083868 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9755 15:36:42.086952 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9756 15:36:42.094306 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9757 15:36:42.096720 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9758 15:36:42.100062 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9759 15:36:42.107185 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9760 15:36:42.110236 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9761 15:36:42.113530 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9762 15:36:42.120376 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9763 15:36:42.123452 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9764 15:36:42.127122 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9765 15:36:42.133459 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9766 15:36:42.137301 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9767 15:36:42.143351 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9768 15:36:42.146783 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9769 15:36:42.149996 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9770 15:36:42.157289 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9771 15:36:42.160635 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9772 15:36:42.163618 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9773 15:36:42.170631 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9774 15:36:42.173809 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9775 15:36:42.176899 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9776 15:36:42.180328 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9777 15:36:42.183670 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9778 15:36:42.190235 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9779 15:36:42.193942 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9780 15:36:42.197419 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9781 15:36:42.200343 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9782 15:36:42.206903 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9783 15:36:42.210358 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9784 15:36:42.213512 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9785 15:36:42.220438 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9786 15:36:42.223925 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9787 15:36:42.227376 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9788 15:36:42.233630 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9789 15:36:42.237007 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9790 15:36:42.240387 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9791 15:36:42.247444 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9792 15:36:42.250329 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9793 15:36:42.257143 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9794 15:36:42.260477 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9795 15:36:42.263721 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9796 15:36:42.270394 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9797 15:36:42.274121 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9798 15:36:42.280459 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9799 15:36:42.284022 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9800 15:36:42.287202 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9801 15:36:42.294212 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9802 15:36:42.297733 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9803 15:36:42.304257 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9804 15:36:42.307066 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9805 15:36:42.311102 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9806 15:36:42.317139 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9807 15:36:42.320882 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9808 15:36:42.327399 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9809 15:36:42.330579 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9810 15:36:42.334087 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9811 15:36:42.340676 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9812 15:36:42.344157 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9813 15:36:42.350852 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9814 15:36:42.353872 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9815 15:36:42.357294 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9816 15:36:42.364100 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9817 15:36:42.367500 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9818 15:36:42.374169 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9819 15:36:42.377304 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9820 15:36:42.380976 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9821 15:36:42.387814 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9822 15:36:42.391410 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9823 15:36:42.397711 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9824 15:36:42.400568 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9825 15:36:42.404514 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9826 15:36:42.410646 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9827 15:36:42.414554 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9828 15:36:42.420689 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9829 15:36:42.423965 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9830 15:36:42.427368 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9831 15:36:42.434194 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9832 15:36:42.437175 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9833 15:36:42.444253 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9834 15:36:42.447301 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9835 15:36:42.450475 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9836 15:36:42.457349 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9837 15:36:42.460289 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9838 15:36:42.466986 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9839 15:36:42.470666 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9840 15:36:42.477197 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9841 15:36:42.480656 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9842 15:36:42.483428 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9843 15:36:42.490364 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9844 15:36:42.493517 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9845 15:36:42.500629 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9846 15:36:42.503774 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9847 15:36:42.507134 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9848 15:36:42.513586 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9849 15:36:42.517287 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9850 15:36:42.523624 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9851 15:36:42.527075 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9852 15:36:42.530227 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9853 15:36:42.537263 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9854 15:36:42.540849 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9855 15:36:42.546852 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9856 15:36:42.550411 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9857 15:36:42.553950 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9858 15:36:42.560415 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9859 15:36:42.563999 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9860 15:36:42.570352 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9861 15:36:42.573849 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9862 15:36:42.580372 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9863 15:36:42.583650 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9864 15:36:42.587115 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9865 15:36:42.593996 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9866 15:36:42.597070 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9867 15:36:42.603444 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9868 15:36:42.606823 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9869 15:36:42.613544 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9870 15:36:42.616656 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9871 15:36:42.620259 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9872 15:36:42.627291 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9873 15:36:42.630512 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9874 15:36:42.637089 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9875 15:36:42.640494 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9876 15:36:42.644061 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9877 15:36:42.650522 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9878 15:36:42.653571 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9879 15:36:42.660707 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9880 15:36:42.663782 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9881 15:36:42.670602 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9882 15:36:42.673594 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9883 15:36:42.677212 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9884 15:36:42.683983 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9885 15:36:42.687278 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9886 15:36:42.694022 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9887 15:36:42.697639 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9888 15:36:42.704081 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9889 15:36:42.707383 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9890 15:36:42.710862 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9891 15:36:42.717303 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9892 15:36:42.720888 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9893 15:36:42.727759 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9894 15:36:42.730814 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9895 15:36:42.737665 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9896 15:36:42.741127 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9897 15:36:42.744480 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9898 15:36:42.750909 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9899 15:36:42.754419 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9900 15:36:42.761153 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9901 15:36:42.764386 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9902 15:36:42.768322 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9903 15:36:42.774437 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9904 15:36:42.777490 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9905 15:36:42.784441 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9906 15:36:42.787742 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9907 15:36:42.791025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9908 15:36:42.797802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9909 15:36:42.801032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9910 15:36:42.807854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9911 15:36:42.810890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9912 15:36:42.818318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9913 15:36:42.820975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9914 15:36:42.827422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9915 15:36:42.831120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9916 15:36:42.837969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9917 15:36:42.841462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9918 15:36:42.847485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9919 15:36:42.851160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9920 15:36:42.857484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9921 15:36:42.861226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9922 15:36:42.864058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9923 15:36:42.870888 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9924 15:36:42.874194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9925 15:36:42.881300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9926 15:36:42.884343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9927 15:36:42.890905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9928 15:36:42.894550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9929 15:36:42.901109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9930 15:36:42.904175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9931 15:36:42.911273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9932 15:36:42.914365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9933 15:36:42.921027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9934 15:36:42.924425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9935 15:36:42.931242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9936 15:36:42.934364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9937 15:36:42.941664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9938 15:36:42.944288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9939 15:36:42.951083 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9940 15:36:42.951171 INFO: [APUAPC] vio 0
9941 15:36:42.957800 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9942 15:36:42.960883 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9943 15:36:42.964394 INFO: [APUAPC] D0_APC_0: 0x400510
9944 15:36:42.967900 INFO: [APUAPC] D0_APC_1: 0x0
9945 15:36:42.971281 INFO: [APUAPC] D0_APC_2: 0x1540
9946 15:36:42.974264 INFO: [APUAPC] D0_APC_3: 0x0
9947 15:36:42.977582 INFO: [APUAPC] D1_APC_0: 0xffffffff
9948 15:36:42.981063 INFO: [APUAPC] D1_APC_1: 0xffffffff
9949 15:36:42.984205 INFO: [APUAPC] D1_APC_2: 0x3fffff
9950 15:36:42.987527 INFO: [APUAPC] D1_APC_3: 0x0
9951 15:36:42.991011 INFO: [APUAPC] D2_APC_0: 0xffffffff
9952 15:36:42.994507 INFO: [APUAPC] D2_APC_1: 0xffffffff
9953 15:36:42.997794 INFO: [APUAPC] D2_APC_2: 0x3fffff
9954 15:36:43.000850 INFO: [APUAPC] D2_APC_3: 0x0
9955 15:36:43.004201 INFO: [APUAPC] D3_APC_0: 0xffffffff
9956 15:36:43.008036 INFO: [APUAPC] D3_APC_1: 0xffffffff
9957 15:36:43.010984 INFO: [APUAPC] D3_APC_2: 0x3fffff
9958 15:36:43.011062 INFO: [APUAPC] D3_APC_3: 0x0
9959 15:36:43.014189 INFO: [APUAPC] D4_APC_0: 0xffffffff
9960 15:36:43.021059 INFO: [APUAPC] D4_APC_1: 0xffffffff
9961 15:36:43.021149 INFO: [APUAPC] D4_APC_2: 0x3fffff
9962 15:36:43.024270 INFO: [APUAPC] D4_APC_3: 0x0
9963 15:36:43.027576 INFO: [APUAPC] D5_APC_0: 0xffffffff
9964 15:36:43.031184 INFO: [APUAPC] D5_APC_1: 0xffffffff
9965 15:36:43.034199 INFO: [APUAPC] D5_APC_2: 0x3fffff
9966 15:36:43.037866 INFO: [APUAPC] D5_APC_3: 0x0
9967 15:36:43.041302 INFO: [APUAPC] D6_APC_0: 0xffffffff
9968 15:36:43.044659 INFO: [APUAPC] D6_APC_1: 0xffffffff
9969 15:36:43.047862 INFO: [APUAPC] D6_APC_2: 0x3fffff
9970 15:36:43.051477 INFO: [APUAPC] D6_APC_3: 0x0
9971 15:36:43.054606 INFO: [APUAPC] D7_APC_0: 0xffffffff
9972 15:36:43.058126 INFO: [APUAPC] D7_APC_1: 0xffffffff
9973 15:36:43.061826 INFO: [APUAPC] D7_APC_2: 0x3fffff
9974 15:36:43.064456 INFO: [APUAPC] D7_APC_3: 0x0
9975 15:36:43.067745 INFO: [APUAPC] D8_APC_0: 0xffffffff
9976 15:36:43.071202 INFO: [APUAPC] D8_APC_1: 0xffffffff
9977 15:36:43.075051 INFO: [APUAPC] D8_APC_2: 0x3fffff
9978 15:36:43.077779 INFO: [APUAPC] D8_APC_3: 0x0
9979 15:36:43.081369 INFO: [APUAPC] D9_APC_0: 0xffffffff
9980 15:36:43.084457 INFO: [APUAPC] D9_APC_1: 0xffffffff
9981 15:36:43.087780 INFO: [APUAPC] D9_APC_2: 0x3fffff
9982 15:36:43.091244 INFO: [APUAPC] D9_APC_3: 0x0
9983 15:36:43.094832 INFO: [APUAPC] D10_APC_0: 0xffffffff
9984 15:36:43.098308 INFO: [APUAPC] D10_APC_1: 0xffffffff
9985 15:36:43.101677 INFO: [APUAPC] D10_APC_2: 0x3fffff
9986 15:36:43.104629 INFO: [APUAPC] D10_APC_3: 0x0
9987 15:36:43.108496 INFO: [APUAPC] D11_APC_0: 0xffffffff
9988 15:36:43.111452 INFO: [APUAPC] D11_APC_1: 0xffffffff
9989 15:36:43.115142 INFO: [APUAPC] D11_APC_2: 0x3fffff
9990 15:36:43.117893 INFO: [APUAPC] D11_APC_3: 0x0
9991 15:36:43.121445 INFO: [APUAPC] D12_APC_0: 0xffffffff
9992 15:36:43.124943 INFO: [APUAPC] D12_APC_1: 0xffffffff
9993 15:36:43.128094 INFO: [APUAPC] D12_APC_2: 0x3fffff
9994 15:36:43.131285 INFO: [APUAPC] D12_APC_3: 0x0
9995 15:36:43.134739 INFO: [APUAPC] D13_APC_0: 0xffffffff
9996 15:36:43.138101 INFO: [APUAPC] D13_APC_1: 0xffffffff
9997 15:36:43.141669 INFO: [APUAPC] D13_APC_2: 0x3fffff
9998 15:36:43.145010 INFO: [APUAPC] D13_APC_3: 0x0
9999 15:36:43.148010 INFO: [APUAPC] D14_APC_0: 0xffffffff
10000 15:36:43.151623 INFO: [APUAPC] D14_APC_1: 0xffffffff
10001 15:36:43.155119 INFO: [APUAPC] D14_APC_2: 0x3fffff
10002 15:36:43.158187 INFO: [APUAPC] D14_APC_3: 0x0
10003 15:36:43.161319 INFO: [APUAPC] D15_APC_0: 0xffffffff
10004 15:36:43.164736 INFO: [APUAPC] D15_APC_1: 0xffffffff
10005 15:36:43.167967 INFO: [APUAPC] D15_APC_2: 0x3fffff
10006 15:36:43.171452 INFO: [APUAPC] D15_APC_3: 0x0
10007 15:36:43.175348 INFO: [APUAPC] APC_CON: 0x4
10008 15:36:43.175459 INFO: [NOCDAPC] D0_APC_0: 0x0
10009 15:36:43.178374 INFO: [NOCDAPC] D0_APC_1: 0x0
10010 15:36:43.181799 INFO: [NOCDAPC] D1_APC_0: 0x0
10011 15:36:43.184854 INFO: [NOCDAPC] D1_APC_1: 0xfff
10012 15:36:43.188241 INFO: [NOCDAPC] D2_APC_0: 0x0
10013 15:36:43.191716 INFO: [NOCDAPC] D2_APC_1: 0xfff
10014 15:36:43.194841 INFO: [NOCDAPC] D3_APC_0: 0x0
10015 15:36:43.198208 INFO: [NOCDAPC] D3_APC_1: 0xfff
10016 15:36:43.201887 INFO: [NOCDAPC] D4_APC_0: 0x0
10017 15:36:43.205097 INFO: [NOCDAPC] D4_APC_1: 0xfff
10018 15:36:43.205172 INFO: [NOCDAPC] D5_APC_0: 0x0
10019 15:36:43.208223 INFO: [NOCDAPC] D5_APC_1: 0xfff
10020 15:36:43.211988 INFO: [NOCDAPC] D6_APC_0: 0x0
10021 15:36:43.215310 INFO: [NOCDAPC] D6_APC_1: 0xfff
10022 15:36:43.218363 INFO: [NOCDAPC] D7_APC_0: 0x0
10023 15:36:43.221834 INFO: [NOCDAPC] D7_APC_1: 0xfff
10024 15:36:43.225396 INFO: [NOCDAPC] D8_APC_0: 0x0
10025 15:36:43.228405 INFO: [NOCDAPC] D8_APC_1: 0xfff
10026 15:36:43.231884 INFO: [NOCDAPC] D9_APC_0: 0x0
10027 15:36:43.234998 INFO: [NOCDAPC] D9_APC_1: 0xfff
10028 15:36:43.235101 INFO: [NOCDAPC] D10_APC_0: 0x0
10029 15:36:43.238598 INFO: [NOCDAPC] D10_APC_1: 0xfff
10030 15:36:43.241870 INFO: [NOCDAPC] D11_APC_0: 0x0
10031 15:36:43.245304 INFO: [NOCDAPC] D11_APC_1: 0xfff
10032 15:36:43.248356 INFO: [NOCDAPC] D12_APC_0: 0x0
10033 15:36:43.251677 INFO: [NOCDAPC] D12_APC_1: 0xfff
10034 15:36:43.255574 INFO: [NOCDAPC] D13_APC_0: 0x0
10035 15:36:43.258614 INFO: [NOCDAPC] D13_APC_1: 0xfff
10036 15:36:43.261877 INFO: [NOCDAPC] D14_APC_0: 0x0
10037 15:36:43.264985 INFO: [NOCDAPC] D14_APC_1: 0xfff
10038 15:36:43.268385 INFO: [NOCDAPC] D15_APC_0: 0x0
10039 15:36:43.272136 INFO: [NOCDAPC] D15_APC_1: 0xfff
10040 15:36:43.275878 INFO: [NOCDAPC] APC_CON: 0x4
10041 15:36:43.278677 INFO: [APUAPC] set_apusys_apc done
10042 15:36:43.278793 INFO: [DEVAPC] devapc_init done
10043 15:36:43.285169 INFO: GICv3 without legacy support detected.
10044 15:36:43.288312 INFO: ARM GICv3 driver initialized in EL3
10045 15:36:43.291765 INFO: Maximum SPI INTID supported: 639
10046 15:36:43.295294 INFO: BL31: Initializing runtime services
10047 15:36:43.301702 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10048 15:36:43.305331 INFO: SPM: enable CPC mode
10049 15:36:43.308330 INFO: mcdi ready for mcusys-off-idle and system suspend
10050 15:36:43.315335 INFO: BL31: Preparing for EL3 exit to normal world
10051 15:36:43.318527 INFO: Entry point address = 0x80000000
10052 15:36:43.318605 INFO: SPSR = 0x8
10053 15:36:43.325881
10054 15:36:43.325962
10055 15:36:43.326036
10056 15:36:43.329192 Starting depthcharge on Spherion...
10057 15:36:43.329272
10058 15:36:43.329337 Wipe memory regions:
10059 15:36:43.329399
10060 15:36:43.330046 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10061 15:36:43.330155 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10062 15:36:43.330243 Setting prompt string to ['asurada:']
10063 15:36:43.330323 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10064 15:36:43.332482 [0x00000040000000, 0x00000054600000)
10065 15:36:43.454316
10066 15:36:43.454447 [0x00000054660000, 0x00000080000000)
10067 15:36:43.715002
10068 15:36:43.715164 [0x000000821a7280, 0x000000ffe64000)
10069 15:36:44.459391
10070 15:36:44.459540 [0x00000100000000, 0x00000240000000)
10071 15:36:46.348608
10072 15:36:46.351742 Initializing XHCI USB controller at 0x11200000.
10073 15:36:47.390225
10074 15:36:47.393216 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10075 15:36:47.393314
10076 15:36:47.393397
10077 15:36:47.393464
10078 15:36:47.393747 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10080 15:36:47.494089 asurada: tftpboot 192.168.201.1 11331384/tftp-deploy-8yx1oycu/kernel/image.itb 11331384/tftp-deploy-8yx1oycu/kernel/cmdline
10081 15:36:47.494234 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10082 15:36:47.494326 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10083 15:36:47.498204 tftpboot 192.168.201.1 11331384/tftp-deploy-8yx1oycu/kernel/image.itp-deploy-8yx1oycu/kernel/cmdline
10084 15:36:47.498287
10085 15:36:47.498353 Waiting for link
10086 15:36:47.658756
10087 15:36:47.658891 R8152: Initializing
10088 15:36:47.658959
10089 15:36:47.662451 Version 6 (ocp_data = 5c30)
10090 15:36:47.662564
10091 15:36:47.665184 R8152: Done initializing
10092 15:36:47.665297
10093 15:36:47.665394 Adding net device
10094 15:36:49.552855
10095 15:36:49.552993 done.
10096 15:36:49.553060
10097 15:36:49.553121 MAC: 00:24:32:30:78:52
10098 15:36:49.553180
10099 15:36:49.555897 Sending DHCP discover... done.
10100 15:36:49.556017
10101 15:36:49.559096 Waiting for reply... done.
10102 15:36:49.559179
10103 15:36:49.562269 Sending DHCP request... done.
10104 15:36:49.562351
10105 15:36:49.566072 Waiting for reply... done.
10106 15:36:49.566154
10107 15:36:49.566219 My ip is 192.168.201.14
10108 15:36:49.566279
10109 15:36:49.569504 The DHCP server ip is 192.168.201.1
10110 15:36:49.569587
10111 15:36:49.576411 TFTP server IP predefined by user: 192.168.201.1
10112 15:36:49.576495
10113 15:36:49.582766 Bootfile predefined by user: 11331384/tftp-deploy-8yx1oycu/kernel/image.itb
10114 15:36:49.582849
10115 15:36:49.582914 Sending tftp read request... done.
10116 15:36:49.585795
10117 15:36:49.589801 Waiting for the transfer...
10118 15:36:49.589883
10119 15:36:50.158121 00000000 ################################################################
10120 15:36:50.158253
10121 15:36:50.715749 00080000 ################################################################
10122 15:36:50.715883
10123 15:36:51.293207 00100000 ################################################################
10124 15:36:51.293361
10125 15:36:51.855186 00180000 ################################################################
10126 15:36:51.855347
10127 15:36:52.436638 00200000 ################################################################
10128 15:36:52.436816
10129 15:36:53.079392 00280000 ################################################################
10130 15:36:53.079829
10131 15:36:53.769802 00300000 ################################################################
10132 15:36:53.770299
10133 15:36:54.472076 00380000 ################################################################
10134 15:36:54.472598
10135 15:36:55.160802 00400000 ################################################################
10136 15:36:55.161362
10137 15:36:55.884008 00480000 ################################################################
10138 15:36:55.884583
10139 15:36:56.606136 00500000 ################################################################
10140 15:36:56.606719
10141 15:36:57.335827 00580000 ################################################################
10142 15:36:57.336373
10143 15:36:58.067263 00600000 ################################################################
10144 15:36:58.067789
10145 15:36:58.781105 00680000 ################################################################
10146 15:36:58.781625
10147 15:36:59.493343 00700000 ################################################################
10148 15:36:59.493916
10149 15:37:00.217329 00780000 ################################################################
10150 15:37:00.217852
10151 15:37:00.909379 00800000 ################################################################
10152 15:37:00.909958
10153 15:37:01.608223 00880000 ################################################################
10154 15:37:01.608793
10155 15:37:02.305149 00900000 ################################################################
10156 15:37:02.305672
10157 15:37:03.030548 00980000 ################################################################
10158 15:37:03.031107
10159 15:37:03.763487 00a00000 ################################################################
10160 15:37:03.763990
10161 15:37:04.478668 00a80000 ################################################################
10162 15:37:04.479191
10163 15:37:05.164934 00b00000 ################################################################
10164 15:37:05.165462
10165 15:37:05.842758 00b80000 ################################################################
10166 15:37:05.843268
10167 15:37:06.532169 00c00000 ################################################################
10168 15:37:06.532734
10169 15:37:07.213591 00c80000 ################################################################
10170 15:37:07.214257
10171 15:37:07.905665 00d00000 ################################################################
10172 15:37:07.906237
10173 15:37:08.521238 00d80000 ################################################################
10174 15:37:08.521374
10175 15:37:09.100182 00e00000 ################################################################
10176 15:37:09.100319
10177 15:37:09.664171 00e80000 ################################################################
10178 15:37:09.664308
10179 15:37:10.308608 00f00000 ################################################################
10180 15:37:10.308931
10181 15:37:10.897495 00f80000 ################################################################
10182 15:37:10.898150
10183 15:37:11.578970 01000000 ################################################################
10184 15:37:11.579461
10185 15:37:12.235712 01080000 ################################################################
10186 15:37:12.235852
10187 15:37:12.892956 01100000 ################################################################
10188 15:37:12.893565
10189 15:37:13.442097 01180000 ################################################################
10190 15:37:13.442263
10191 15:37:13.995009 01200000 ################################################################
10192 15:37:13.995160
10193 15:37:14.545276 01280000 ################################################################
10194 15:37:14.545412
10195 15:37:15.068356 01300000 ################################################################
10196 15:37:15.068540
10197 15:37:15.606147 01380000 ################################################################
10198 15:37:15.606296
10199 15:37:16.134795 01400000 ################################################################
10200 15:37:16.134934
10201 15:37:16.658120 01480000 ################################################################
10202 15:37:16.658287
10203 15:37:17.209533 01500000 ################################################################
10204 15:37:17.209672
10205 15:37:17.740305 01580000 ################################################################
10206 15:37:17.740442
10207 15:37:18.265792 01600000 ################################################################
10208 15:37:18.265930
10209 15:37:18.802493 01680000 ################################################################
10210 15:37:18.802638
10211 15:37:19.330844 01700000 ################################################################
10212 15:37:19.331014
10213 15:37:19.855549 01780000 ################################################################
10214 15:37:19.855716
10215 15:37:20.403050 01800000 ################################################################
10216 15:37:20.403196
10217 15:37:20.955039 01880000 ################################################################
10218 15:37:20.955185
10219 15:37:21.515435 01900000 ################################################################
10220 15:37:21.515579
10221 15:37:22.080370 01980000 ################################################################
10222 15:37:22.080509
10223 15:37:22.637125 01a00000 ################################################################
10224 15:37:22.637265
10225 15:37:23.192763 01a80000 ################################################################
10226 15:37:23.192907
10227 15:37:23.745240 01b00000 ################################################################
10228 15:37:23.745384
10229 15:37:24.297626 01b80000 ################################################################
10230 15:37:24.297766
10231 15:37:24.851485 01c00000 ################################################################
10232 15:37:24.851629
10233 15:37:25.417070 01c80000 ################################################################
10234 15:37:25.417220
10235 15:37:25.967079 01d00000 ################################################################
10236 15:37:25.967229
10237 15:37:26.523600 01d80000 ################################################################
10238 15:37:26.523751
10239 15:37:27.086448 01e00000 ################################################################
10240 15:37:27.086579
10241 15:37:27.650365 01e80000 ################################################################
10242 15:37:27.650507
10243 15:37:28.205839 01f00000 ################################################################
10244 15:37:28.206015
10245 15:37:28.773374 01f80000 ################################################################
10246 15:37:28.773520
10247 15:37:29.335383 02000000 ################################################################
10248 15:37:29.335528
10249 15:37:29.903181 02080000 ################################################################
10250 15:37:29.903327
10251 15:37:30.466554 02100000 ################################################################
10252 15:37:30.466727
10253 15:37:31.027274 02180000 ################################################################
10254 15:37:31.027426
10255 15:37:31.591209 02200000 ################################################################
10256 15:37:31.591362
10257 15:37:32.162628 02280000 ################################################################
10258 15:37:32.162768
10259 15:37:32.728245 02300000 ################################################################
10260 15:37:32.728381
10261 15:37:33.298372 02380000 ################################################################
10262 15:37:33.298519
10263 15:37:33.864486 02400000 ################################################################
10264 15:37:33.864634
10265 15:37:34.425304 02480000 ################################################################
10266 15:37:34.425448
10267 15:37:34.972008 02500000 ################################################################
10268 15:37:34.972157
10269 15:37:35.526902 02580000 ################################################################
10270 15:37:35.527061
10271 15:37:36.076515 02600000 ################################################################
10272 15:37:36.076674
10273 15:37:36.636034 02680000 ################################################################
10274 15:37:36.636181
10275 15:37:37.186251 02700000 ################################################################
10276 15:37:37.186391
10277 15:37:37.730255 02780000 ################################################################
10278 15:37:37.730401
10279 15:37:38.298163 02800000 ################################################################
10280 15:37:38.298306
10281 15:37:38.853630 02880000 ################################################################
10282 15:37:38.853787
10283 15:37:39.420229 02900000 ################################################################
10284 15:37:39.420371
10285 15:37:39.980260 02980000 ################################################################
10286 15:37:39.980410
10287 15:37:40.547557 02a00000 ################################################################
10288 15:37:40.547700
10289 15:37:41.095461 02a80000 ################################################################
10290 15:37:41.095611
10291 15:37:41.643999 02b00000 ################################################################
10292 15:37:41.644159
10293 15:37:42.207332 02b80000 ################################################################
10294 15:37:42.207474
10295 15:37:42.771839 02c00000 ################################################################
10296 15:37:42.771983
10297 15:37:43.337896 02c80000 ################################################################
10298 15:37:43.338041
10299 15:37:43.902292 02d00000 ################################################################
10300 15:37:43.902434
10301 15:37:44.466145 02d80000 ################################################################
10302 15:37:44.466286
10303 15:37:45.018519 02e00000 ################################################################
10304 15:37:45.018691
10305 15:37:45.560898 02e80000 ################################################################
10306 15:37:45.561035
10307 15:37:46.117846 02f00000 ################################################################
10308 15:37:46.118023
10309 15:37:46.681340 02f80000 ################################################################
10310 15:37:46.681478
10311 15:37:47.252646 03000000 ################################################################
10312 15:37:47.252814
10313 15:37:47.815701 03080000 ################################################################
10314 15:37:47.815893
10315 15:37:48.362711 03100000 ################################################################
10316 15:37:48.362875
10317 15:37:48.904800 03180000 ################################################################
10318 15:37:48.904932
10319 15:37:49.445581 03200000 ################################################################
10320 15:37:49.445713
10321 15:37:49.992327 03280000 ################################################################
10322 15:37:49.992522
10323 15:37:50.537860 03300000 ################################################################
10324 15:37:50.538006
10325 15:37:51.084321 03380000 ################################################################
10326 15:37:51.084486
10327 15:37:51.627145 03400000 ################################################################
10328 15:37:51.627282
10329 15:37:52.171426 03480000 ################################################################
10330 15:37:52.171565
10331 15:37:52.728937 03500000 ################################################################
10332 15:37:52.729105
10333 15:37:53.269931 03580000 ################################################################
10334 15:37:53.270099
10335 15:37:53.812756 03600000 ################################################################
10336 15:37:53.812894
10337 15:37:54.346878 03680000 ################################################################
10338 15:37:54.347040
10339 15:37:54.897306 03700000 ################################################################
10340 15:37:54.897450
10341 15:37:55.447167 03780000 ################################################################
10342 15:37:55.447303
10343 15:37:55.994995 03800000 ################################################################
10344 15:37:55.995130
10345 15:37:56.540581 03880000 ################################################################
10346 15:37:56.540754
10347 15:37:57.089066 03900000 ################################################################
10348 15:37:57.089202
10349 15:37:57.650260 03980000 ################################################################
10350 15:37:57.650404
10351 15:37:58.199700 03a00000 ################################################################
10352 15:37:58.199838
10353 15:37:58.754577 03a80000 ################################################################
10354 15:37:58.754715
10355 15:37:59.303050 03b00000 ################################################################
10356 15:37:59.303183
10357 15:37:59.848301 03b80000 ################################################################
10358 15:37:59.848443
10359 15:38:00.395802 03c00000 ################################################################
10360 15:38:00.395941
10361 15:38:00.958053 03c80000 ################################################################
10362 15:38:00.958188
10363 15:38:01.525621 03d00000 ################################################################
10364 15:38:01.525756
10365 15:38:02.081211 03d80000 ################################################################
10366 15:38:02.081349
10367 15:38:02.633797 03e00000 ################################################################
10368 15:38:02.633937
10369 15:38:03.188081 03e80000 ################################################################
10370 15:38:03.188218
10371 15:38:03.737778 03f00000 ################################################################
10372 15:38:03.737919
10373 15:38:04.276502 03f80000 ################################################################
10374 15:38:04.276694
10375 15:38:04.816551 04000000 ################################################################
10376 15:38:04.816740
10377 15:38:05.383363 04080000 ################################################################
10378 15:38:05.383509
10379 15:38:05.938322 04100000 ################################################################
10380 15:38:05.938487
10381 15:38:06.523692 04180000 ################################################################
10382 15:38:06.524189
10383 15:38:07.232195 04200000 ################################################################
10384 15:38:07.232822
10385 15:38:07.951456 04280000 ################################################################
10386 15:38:07.951945
10387 15:38:08.647015 04300000 ################################################################
10388 15:38:08.647313
10389 15:38:09.252414 04380000 ################################################################
10390 15:38:09.252552
10391 15:38:09.879536 04400000 ################################################################
10392 15:38:09.880009
10393 15:38:10.537028 04480000 ################################################################
10394 15:38:10.537392
10395 15:38:11.178908 04500000 ################################################################
10396 15:38:11.179290
10397 15:38:11.854127 04580000 ################################################################
10398 15:38:11.854631
10399 15:38:12.574736 04600000 ################################################################
10400 15:38:12.575259
10401 15:38:13.280514 04680000 ################################################################
10402 15:38:13.281097
10403 15:38:13.993838 04700000 ################################################################
10404 15:38:13.994378
10405 15:38:14.692081 04780000 ################################################################
10406 15:38:14.692609
10407 15:38:15.410574 04800000 ################################################################
10408 15:38:15.411120
10409 15:38:16.102334 04880000 ################################################################
10410 15:38:16.102843
10411 15:38:16.810657 04900000 ################################################################
10412 15:38:16.811344
10413 15:38:17.435714 04980000 ################################################################
10414 15:38:17.436221
10415 15:38:18.140707 04a00000 ################################################################
10416 15:38:18.141246
10417 15:38:18.844935 04a80000 ################################################################
10418 15:38:18.845448
10419 15:38:19.538794 04b00000 ################################################################
10420 15:38:19.538924
10421 15:38:20.251848 04b80000 ################################################################
10422 15:38:20.252363
10423 15:38:20.984141 04c00000 ################################################################
10424 15:38:20.984656
10425 15:38:21.681848 04c80000 ################################################################
10426 15:38:21.682408
10427 15:38:22.363089 04d00000 ################################################################
10428 15:38:22.363589
10429 15:38:23.073798 04d80000 ################################################################
10430 15:38:23.074408
10431 15:38:23.813325 04e00000 ################################################################
10432 15:38:23.813861
10433 15:38:24.524319 04e80000 ################################################################
10434 15:38:24.524587
10435 15:38:25.143805 04f00000 ################################################################
10436 15:38:25.144427
10437 15:38:25.849125 04f80000 ################################################################
10438 15:38:25.849642
10439 15:38:26.570951 05000000 ################################################################
10440 15:38:26.571484
10441 15:38:27.264699 05080000 ################################################################
10442 15:38:27.265068
10443 15:38:27.939493 05100000 ################################################################
10444 15:38:27.940152
10445 15:38:28.639364 05180000 ################################################################
10446 15:38:28.639959
10447 15:38:29.367842 05200000 ################################################################
10448 15:38:29.368404
10449 15:38:30.082666 05280000 ################################################################
10450 15:38:30.083196
10451 15:38:30.784188 05300000 ################################################################
10452 15:38:30.784744
10453 15:38:31.471352 05380000 ################################################################
10454 15:38:31.471887
10455 15:38:32.155675 05400000 ################################################################
10456 15:38:32.156339
10457 15:38:32.859160 05480000 ################################################################
10458 15:38:32.859677
10459 15:38:33.547393 05500000 ################################################################
10460 15:38:33.547901
10461 15:38:34.224646 05580000 ################################################################
10462 15:38:34.225278
10463 15:38:34.894923 05600000 ################################################################
10464 15:38:34.895359
10465 15:38:35.558637 05680000 ################################################################
10466 15:38:35.559140
10467 15:38:36.224204 05700000 ################################################################
10468 15:38:36.224370
10469 15:38:36.880751 05780000 ################################################################
10470 15:38:36.881419
10471 15:38:37.565239 05800000 ################################################################
10472 15:38:37.565541
10473 15:38:38.208766 05880000 ################################################################
10474 15:38:38.209320
10475 15:38:38.918713 05900000 ################################################################
10476 15:38:38.919244
10477 15:38:39.639846 05980000 ################################################################
10478 15:38:39.640395
10479 15:38:40.372827 05a00000 ################################################################
10480 15:38:40.373410
10481 15:38:41.092223 05a80000 ################################################################
10482 15:38:41.092849
10483 15:38:41.817177 05b00000 ################################################################
10484 15:38:41.817685
10485 15:38:42.538957 05b80000 ################################################################
10486 15:38:42.539499
10487 15:38:43.259106 05c00000 ################################################################
10488 15:38:43.259689
10489 15:38:43.992509 05c80000 ################################################################
10490 15:38:43.993189
10491 15:38:44.699988 05d00000 ################################################################
10492 15:38:44.700558
10493 15:38:45.401472 05d80000 ################################################################
10494 15:38:45.402020
10495 15:38:46.104804 05e00000 ################################################################
10496 15:38:46.105324
10497 15:38:46.845517 05e80000 ################################################################
10498 15:38:46.846093
10499 15:38:47.577792 05f00000 ################################################################
10500 15:38:47.578368
10501 15:38:48.298953 05f80000 ################################################################
10502 15:38:48.299477
10503 15:38:49.005819 06000000 ################################################################
10504 15:38:49.005984
10505 15:38:49.719528 06080000 ################################################################
10506 15:38:49.720109
10507 15:38:50.441852 06100000 ################################################################
10508 15:38:50.442431
10509 15:38:51.156748 06180000 ################################################################
10510 15:38:51.157332
10511 15:38:51.883711 06200000 ################################################################
10512 15:38:51.884320
10513 15:38:52.605588 06280000 ################################################################
10514 15:38:52.606174
10515 15:38:53.332746 06300000 ################################################################
10516 15:38:53.333303
10517 15:38:54.049558 06380000 ################################################################
10518 15:38:54.050117
10519 15:38:54.767665 06400000 ################################################################
10520 15:38:54.768202
10521 15:38:55.486871 06480000 ################################################################
10522 15:38:55.487416
10523 15:38:56.217422 06500000 ################################################################
10524 15:38:56.217953
10525 15:38:56.944365 06580000 ################################################################
10526 15:38:56.945079
10527 15:38:57.661231 06600000 ################################################################
10528 15:38:57.661885
10529 15:38:58.375059 06680000 ################################################################
10530 15:38:58.375623
10531 15:38:59.079659 06700000 ################################################################
10532 15:38:59.080196
10533 15:38:59.803851 06780000 ################################################################
10534 15:38:59.804508
10535 15:39:00.296534 06800000 ########################################### done.
10536 15:39:00.297123
10537 15:39:00.300109 The bootfile was 109399442 bytes long.
10538 15:39:00.300635
10539 15:39:00.302764 Sending tftp read request... done.
10540 15:39:00.303227
10541 15:39:00.306952 Waiting for the transfer...
10542 15:39:00.307375
10543 15:39:00.307706 00000000 # done.
10544 15:39:00.308027
10545 15:39:00.313751 Command line loaded dynamically from TFTP file: 11331384/tftp-deploy-8yx1oycu/kernel/cmdline
10546 15:39:00.314176
10547 15:39:00.327135 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10548 15:39:00.327571
10549 15:39:00.330515 Loading FIT.
10550 15:39:00.331005
10551 15:39:00.334550 Image ramdisk-1 has 98314785 bytes.
10552 15:39:00.335075
10553 15:39:00.337309 Image fdt-1 has 47278 bytes.
10554 15:39:00.337729
10555 15:39:00.338060 Image kernel-1 has 11035343 bytes.
10556 15:39:00.340748
10557 15:39:00.347270 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10558 15:39:00.347801
10559 15:39:00.364053 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10560 15:39:00.364610
10561 15:39:00.370926 Choosing best match conf-1 for compat google,spherion-rev2.
10562 15:39:00.375355
10563 15:39:00.379746 Connected to device vid:did:rid of 1ae0:0028:00
10564 15:39:00.387755
10565 15:39:00.391606 tpm_get_response: command 0x17b, return code 0x0
10566 15:39:00.392135
10567 15:39:00.394057 ec_init: CrosEC protocol v3 supported (256, 248)
10568 15:39:00.398918
10569 15:39:00.401686 tpm_cleanup: add release locality here.
10570 15:39:00.402217
10571 15:39:00.402556 Shutting down all USB controllers.
10572 15:39:00.405022
10573 15:39:00.405442 Removing current net device
10574 15:39:00.405778
10575 15:39:00.411706 Exiting depthcharge with code 4 at timestamp: 166504774
10576 15:39:00.412248
10577 15:39:00.414759 LZMA decompressing kernel-1 to 0x821a6718
10578 15:39:00.415186
10579 15:39:00.418478 LZMA decompressing kernel-1 to 0x40000000
10580 15:39:01.805604
10581 15:39:01.806169 jumping to kernel
10582 15:39:01.807975 end: 2.2.4 bootloader-commands (duration 00:02:18) [common]
10583 15:39:01.808510 start: 2.2.5 auto-login-action (timeout 00:02:07) [common]
10584 15:39:01.808979 Setting prompt string to ['Linux version [0-9]']
10585 15:39:01.809360 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10586 15:39:01.809745 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10587 15:39:01.887644
10588 15:39:01.891019 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10589 15:39:01.894713 start: 2.2.5.1 login-action (timeout 00:02:07) [common]
10590 15:39:01.895176 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10591 15:39:01.895536 Setting prompt string to []
10592 15:39:01.895919 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10593 15:39:01.896274 Using line separator: #'\n'#
10594 15:39:01.896575 No login prompt set.
10595 15:39:01.897014 Parsing kernel messages
10596 15:39:01.897379 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10597 15:39:01.897916 [login-action] Waiting for messages, (timeout 00:02:07)
10598 15:39:01.914466 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j17681-arm64-gcc-10-defconfig-arm64-chromebook-c49jr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Aug 22 15:20:14 UTC 2023
10599 15:39:01.917494 [ 0.000000] random: crng init done
10600 15:39:01.920647 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10601 15:39:01.924163 [ 0.000000] efi: UEFI not found.
10602 15:39:01.934031 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10603 15:39:01.940586 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10604 15:39:01.950841 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10605 15:39:01.960719 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10606 15:39:01.967548 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10607 15:39:01.971467 [ 0.000000] printk: bootconsole [mtk8250] enabled
10608 15:39:01.979677 [ 0.000000] NUMA: No NUMA configuration found
10609 15:39:01.986054 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10610 15:39:01.992443 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10611 15:39:01.992921 [ 0.000000] Zone ranges:
10612 15:39:01.999736 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10613 15:39:02.003319 [ 0.000000] DMA32 empty
10614 15:39:02.009648 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10615 15:39:02.012763 [ 0.000000] Movable zone start for each node
10616 15:39:02.016499 [ 0.000000] Early memory node ranges
10617 15:39:02.022515 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10618 15:39:02.029415 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10619 15:39:02.036311 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10620 15:39:02.043195 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10621 15:39:02.049342 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10622 15:39:02.056111 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10623 15:39:02.112556 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10624 15:39:02.119014 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10625 15:39:02.125989 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10626 15:39:02.129227 [ 0.000000] psci: probing for conduit method from DT.
10627 15:39:02.135822 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10628 15:39:02.138996 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10629 15:39:02.145965 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10630 15:39:02.148787 [ 0.000000] psci: SMC Calling Convention v1.2
10631 15:39:02.155229 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10632 15:39:02.158528 [ 0.000000] Detected VIPT I-cache on CPU0
10633 15:39:02.165535 [ 0.000000] CPU features: detected: GIC system register CPU interface
10634 15:39:02.172277 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10635 15:39:02.178953 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10636 15:39:02.185328 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10637 15:39:02.191991 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10638 15:39:02.199572 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10639 15:39:02.205698 [ 0.000000] alternatives: applying boot alternatives
10640 15:39:02.208824 [ 0.000000] Fallback order for Node 0: 0
10641 15:39:02.215687 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10642 15:39:02.218472 [ 0.000000] Policy zone: Normal
10643 15:39:02.235372 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10644 15:39:02.244937 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10645 15:39:02.256389 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10646 15:39:02.266716 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10647 15:39:02.272950 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10648 15:39:02.276196 <6>[ 0.000000] software IO TLB: area num 8.
10649 15:39:02.333463 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10650 15:39:02.482115 <6>[ 0.000000] Memory: 7873544K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 479224K reserved, 32768K cma-reserved)
10651 15:39:02.488949 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10652 15:39:02.495419 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10653 15:39:02.498884 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10654 15:39:02.505716 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10655 15:39:02.511951 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10656 15:39:02.516077 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10657 15:39:02.525469 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10658 15:39:02.532282 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10659 15:39:02.535289 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10660 15:39:02.543177 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10661 15:39:02.546212 <6>[ 0.000000] GICv3: 608 SPIs implemented
10662 15:39:02.553058 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10663 15:39:02.556487 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10664 15:39:02.559921 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10665 15:39:02.566807 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10666 15:39:02.580054 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10667 15:39:02.593315 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10668 15:39:02.599935 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10669 15:39:02.608854 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10670 15:39:02.621881 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10671 15:39:02.628563 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10672 15:39:02.635319 <6>[ 0.009183] Console: colour dummy device 80x25
10673 15:39:02.645218 <6>[ 0.013912] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10674 15:39:02.648408 <6>[ 0.024355] pid_max: default: 32768 minimum: 301
10675 15:39:02.655502 <6>[ 0.029225] LSM: Security Framework initializing
10676 15:39:02.662249 <6>[ 0.034162] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10677 15:39:02.671510 <6>[ 0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10678 15:39:02.678229 <6>[ 0.051455] cblist_init_generic: Setting adjustable number of callback queues.
10679 15:39:02.684792 <6>[ 0.058945] cblist_init_generic: Setting shift to 3 and lim to 1.
10680 15:39:02.694660 <6>[ 0.065283] cblist_init_generic: Setting adjustable number of callback queues.
10681 15:39:02.701567 <6>[ 0.072708] cblist_init_generic: Setting shift to 3 and lim to 1.
10682 15:39:02.704479 <6>[ 0.079149] rcu: Hierarchical SRCU implementation.
10683 15:39:02.711341 <6>[ 0.084193] rcu: Max phase no-delay instances is 1000.
10684 15:39:02.718146 <6>[ 0.091226] EFI services will not be available.
10685 15:39:02.721332 <6>[ 0.096201] smp: Bringing up secondary CPUs ...
10686 15:39:02.729763 <6>[ 0.101283] Detected VIPT I-cache on CPU1
10687 15:39:02.736222 <6>[ 0.101351] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10688 15:39:02.742787 <6>[ 0.101383] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10689 15:39:02.745922 <6>[ 0.101724] Detected VIPT I-cache on CPU2
10690 15:39:02.752960 <6>[ 0.101775] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10691 15:39:02.759543 <6>[ 0.101791] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10692 15:39:02.766112 <6>[ 0.102050] Detected VIPT I-cache on CPU3
10693 15:39:02.773114 <6>[ 0.102097] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10694 15:39:02.779463 <6>[ 0.102110] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10695 15:39:02.782910 <6>[ 0.102414] CPU features: detected: Spectre-v4
10696 15:39:02.789712 <6>[ 0.102420] CPU features: detected: Spectre-BHB
10697 15:39:02.792932 <6>[ 0.102425] Detected PIPT I-cache on CPU4
10698 15:39:02.799390 <6>[ 0.102481] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10699 15:39:02.806327 <6>[ 0.102498] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10700 15:39:02.810009 <6>[ 0.102788] Detected PIPT I-cache on CPU5
10701 15:39:02.819574 <6>[ 0.102850] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10702 15:39:02.826314 <6>[ 0.102867] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10703 15:39:02.829163 <6>[ 0.103148] Detected PIPT I-cache on CPU6
10704 15:39:02.836325 <6>[ 0.103213] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10705 15:39:02.842960 <6>[ 0.103230] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10706 15:39:02.846220 <6>[ 0.103530] Detected PIPT I-cache on CPU7
10707 15:39:02.856107 <6>[ 0.103594] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10708 15:39:02.862849 <6>[ 0.103611] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10709 15:39:02.866079 <6>[ 0.103658] smp: Brought up 1 node, 8 CPUs
10710 15:39:02.869747 <6>[ 0.244904] SMP: Total of 8 processors activated.
10711 15:39:02.875993 <6>[ 0.249825] CPU features: detected: 32-bit EL0 Support
10712 15:39:02.886121 <6>[ 0.255221] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10713 15:39:02.892962 <6>[ 0.264072] CPU features: detected: Common not Private translations
10714 15:39:02.896437 <6>[ 0.270588] CPU features: detected: CRC32 instructions
10715 15:39:02.902592 <6>[ 0.275972] CPU features: detected: RCpc load-acquire (LDAPR)
10716 15:39:02.909382 <6>[ 0.281969] CPU features: detected: LSE atomic instructions
10717 15:39:02.912860 <6>[ 0.287751] CPU features: detected: Privileged Access Never
10718 15:39:02.919730 <6>[ 0.293530] CPU features: detected: RAS Extension Support
10719 15:39:02.925983 <6>[ 0.299174] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10720 15:39:02.932782 <6>[ 0.306394] CPU: All CPU(s) started at EL2
10721 15:39:02.935983 <6>[ 0.310711] alternatives: applying system-wide alternatives
10722 15:39:02.947428 <6>[ 0.321368] devtmpfs: initialized
10723 15:39:02.959860 <6>[ 0.330223] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10724 15:39:02.969370 <6>[ 0.340183] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10725 15:39:02.972915 <6>[ 0.348196] pinctrl core: initialized pinctrl subsystem
10726 15:39:02.981045 <6>[ 0.354865] DMI not present or invalid.
10727 15:39:02.987637 <6>[ 0.359269] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10728 15:39:02.993982 <6>[ 0.366121] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10729 15:39:03.004197 <6>[ 0.373703] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10730 15:39:03.010601 <6>[ 0.381919] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10731 15:39:03.017641 <6>[ 0.390163] audit: initializing netlink subsys (disabled)
10732 15:39:03.023722 <5>[ 0.395860] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10733 15:39:03.030662 <6>[ 0.396564] thermal_sys: Registered thermal governor 'step_wise'
10734 15:39:03.037077 <6>[ 0.403827] thermal_sys: Registered thermal governor 'power_allocator'
10735 15:39:03.040974 <6>[ 0.410084] cpuidle: using governor menu
10736 15:39:03.047385 <6>[ 0.421044] NET: Registered PF_QIPCRTR protocol family
10737 15:39:03.054062 <6>[ 0.426523] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10738 15:39:03.060371 <6>[ 0.433629] ASID allocator initialised with 32768 entries
10739 15:39:03.063918 <6>[ 0.440192] Serial: AMBA PL011 UART driver
10740 15:39:03.075282 <4>[ 0.448991] Trying to register duplicate clock ID: 134
10741 15:39:03.128799 <6>[ 0.506233] KASLR enabled
10742 15:39:03.142807 <6>[ 0.513870] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10743 15:39:03.149504 <6>[ 0.520884] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10744 15:39:03.156488 <6>[ 0.527373] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10745 15:39:03.163196 <6>[ 0.534376] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10746 15:39:03.169709 <6>[ 0.540863] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10747 15:39:03.176250 <6>[ 0.547868] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10748 15:39:03.182590 <6>[ 0.554353] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10749 15:39:03.189345 <6>[ 0.561358] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10750 15:39:03.192616 <6>[ 0.568730] ACPI: Interpreter disabled.
10751 15:39:03.200644 <6>[ 0.575167] iommu: Default domain type: Translated
10752 15:39:03.207250 <6>[ 0.580282] iommu: DMA domain TLB invalidation policy: strict mode
10753 15:39:03.210745 <5>[ 0.586936] SCSI subsystem initialized
10754 15:39:03.217342 <6>[ 0.591181] usbcore: registered new interface driver usbfs
10755 15:39:03.224095 <6>[ 0.596912] usbcore: registered new interface driver hub
10756 15:39:03.227159 <6>[ 0.602464] usbcore: registered new device driver usb
10757 15:39:03.234085 <6>[ 0.608576] pps_core: LinuxPPS API ver. 1 registered
10758 15:39:03.244324 <6>[ 0.613769] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10759 15:39:03.247553 <6>[ 0.623115] PTP clock support registered
10760 15:39:03.250822 <6>[ 0.627354] EDAC MC: Ver: 3.0.0
10761 15:39:03.257827 <6>[ 0.632533] FPGA manager framework
10762 15:39:03.261308 <6>[ 0.636208] Advanced Linux Sound Architecture Driver Initialized.
10763 15:39:03.265632 <6>[ 0.642968] vgaarb: loaded
10764 15:39:03.271918 <6>[ 0.646135] clocksource: Switched to clocksource arch_sys_counter
10765 15:39:03.278457 <5>[ 0.652576] VFS: Disk quotas dquot_6.6.0
10766 15:39:03.285165 <6>[ 0.656763] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10767 15:39:03.288382 <6>[ 0.663953] pnp: PnP ACPI: disabled
10768 15:39:03.295894 <6>[ 0.670548] NET: Registered PF_INET protocol family
10769 15:39:03.306168 <6>[ 0.676131] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10770 15:39:03.317170 <6>[ 0.688415] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10771 15:39:03.327552 <6>[ 0.697231] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10772 15:39:03.333805 <6>[ 0.705202] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10773 15:39:03.340704 <6>[ 0.713899] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10774 15:39:03.352407 <6>[ 0.723646] TCP: Hash tables configured (established 65536 bind 65536)
10775 15:39:03.359254 <6>[ 0.730510] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10776 15:39:03.366083 <6>[ 0.737710] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10777 15:39:03.372358 <6>[ 0.745416] NET: Registered PF_UNIX/PF_LOCAL protocol family
10778 15:39:03.378809 <6>[ 0.751584] RPC: Registered named UNIX socket transport module.
10779 15:39:03.382267 <6>[ 0.757736] RPC: Registered udp transport module.
10780 15:39:03.389123 <6>[ 0.762669] RPC: Registered tcp transport module.
10781 15:39:03.395776 <6>[ 0.767601] RPC: Registered tcp NFSv4.1 backchannel transport module.
10782 15:39:03.398970 <6>[ 0.774268] PCI: CLS 0 bytes, default 64
10783 15:39:03.402270 <6>[ 0.778667] Unpacking initramfs...
10784 15:39:03.419533 <6>[ 0.790784] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10785 15:39:03.429285 <6>[ 0.799438] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10786 15:39:03.432840 <6>[ 0.808299] kvm [1]: IPA Size Limit: 40 bits
10787 15:39:03.439685 <6>[ 0.812826] kvm [1]: GICv3: no GICV resource entry
10788 15:39:03.442639 <6>[ 0.817849] kvm [1]: disabling GICv2 emulation
10789 15:39:03.449540 <6>[ 0.822532] kvm [1]: GIC system register CPU interface enabled
10790 15:39:03.455853 <6>[ 0.830155] kvm [1]: vgic interrupt IRQ18
10791 15:39:03.458918 <6>[ 0.834532] kvm [1]: VHE mode initialized successfully
10792 15:39:03.466232 <5>[ 0.840936] Initialise system trusted keyrings
10793 15:39:03.472913 <6>[ 0.845700] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10794 15:39:03.481074 <6>[ 0.855671] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10795 15:39:03.487569 <5>[ 0.862061] NFS: Registering the id_resolver key type
10796 15:39:03.491319 <5>[ 0.867359] Key type id_resolver registered
10797 15:39:03.497634 <5>[ 0.871772] Key type id_legacy registered
10798 15:39:03.504358 <6>[ 0.876048] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10799 15:39:03.510959 <6>[ 0.882973] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10800 15:39:03.517650 <6>[ 0.890706] 9p: Installing v9fs 9p2000 file system support
10801 15:39:03.555101 <5>[ 0.929413] Key type asymmetric registered
10802 15:39:03.558526 <5>[ 0.933747] Asymmetric key parser 'x509' registered
10803 15:39:03.568310 <6>[ 0.938893] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10804 15:39:03.571494 <6>[ 0.946511] io scheduler mq-deadline registered
10805 15:39:03.575032 <6>[ 0.951277] io scheduler kyber registered
10806 15:39:03.593587 <6>[ 0.968301] EINJ: ACPI disabled.
10807 15:39:03.625661 <4>[ 0.993800] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10808 15:39:03.636063 <4>[ 1.004415] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10809 15:39:03.650494 <6>[ 1.025053] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10810 15:39:03.658164 <6>[ 1.033006] printk: console [ttyS0] disabled
10811 15:39:03.686534 <6>[ 1.057649] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10812 15:39:03.693421 <6>[ 1.067125] printk: console [ttyS0] enabled
10813 15:39:03.696511 <6>[ 1.067125] printk: console [ttyS0] enabled
10814 15:39:03.703347 <6>[ 1.076018] printk: bootconsole [mtk8250] disabled
10815 15:39:03.706966 <6>[ 1.076018] printk: bootconsole [mtk8250] disabled
10816 15:39:03.713119 <6>[ 1.087239] SuperH (H)SCI(F) driver initialized
10817 15:39:03.716290 <6>[ 1.092515] msm_serial: driver initialized
10818 15:39:03.730527 <6>[ 1.101540] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10819 15:39:03.740000 <6>[ 1.110091] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10820 15:39:03.747051 <6>[ 1.118633] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10821 15:39:03.756813 <6>[ 1.127261] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10822 15:39:03.763419 <6>[ 1.135967] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10823 15:39:03.773881 <6>[ 1.144680] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10824 15:39:03.783591 <6>[ 1.153220] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10825 15:39:03.790569 <6>[ 1.162038] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10826 15:39:03.800478 <6>[ 1.170587] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10827 15:39:03.812036 <6>[ 1.186318] loop: module loaded
10828 15:39:03.818797 <6>[ 1.192337] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10829 15:39:03.841063 <4>[ 1.215422] mtk-pmic-keys: Failed to locate of_node [id: -1]
10830 15:39:03.847998 <6>[ 1.222084] megasas: 07.719.03.00-rc1
10831 15:39:03.857507 <6>[ 1.231651] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10832 15:39:03.864013 <6>[ 1.237527] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10833 15:39:03.880272 <6>[ 1.254102] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10834 15:39:03.936613 <6>[ 1.304136] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10835 15:39:07.396441 <6>[ 4.771219] Freeing initrd memory: 96008K
10836 15:39:07.406886 <6>[ 4.781649] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10837 15:39:07.417788 <6>[ 4.792539] tun: Universal TUN/TAP device driver, 1.6
10838 15:39:07.421522 <6>[ 4.798633] thunder_xcv, ver 1.0
10839 15:39:07.424301 <6>[ 4.802138] thunder_bgx, ver 1.0
10840 15:39:07.427480 <6>[ 4.805630] nicpf, ver 1.0
10841 15:39:07.438390 <6>[ 4.809661] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10842 15:39:07.441559 <6>[ 4.817136] hns3: Copyright (c) 2017 Huawei Corporation.
10843 15:39:07.444998 <6>[ 4.822728] hclge is initializing
10844 15:39:07.452185 <6>[ 4.826308] e1000: Intel(R) PRO/1000 Network Driver
10845 15:39:07.458186 <6>[ 4.831438] e1000: Copyright (c) 1999-2006 Intel Corporation.
10846 15:39:07.461529 <6>[ 4.837450] e1000e: Intel(R) PRO/1000 Network Driver
10847 15:39:07.468009 <6>[ 4.842665] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10848 15:39:07.474860 <6>[ 4.848853] igb: Intel(R) Gigabit Ethernet Network Driver
10849 15:39:07.481431 <6>[ 4.854503] igb: Copyright (c) 2007-2014 Intel Corporation.
10850 15:39:07.488374 <6>[ 4.860342] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10851 15:39:07.494464 <6>[ 4.866860] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10852 15:39:07.497821 <6>[ 4.873329] sky2: driver version 1.30
10853 15:39:07.504887 <6>[ 4.878341] VFIO - User Level meta-driver version: 0.3
10854 15:39:07.512193 <6>[ 4.886647] usbcore: registered new interface driver usb-storage
10855 15:39:07.518456 <6>[ 4.893090] usbcore: registered new device driver onboard-usb-hub
10856 15:39:07.527232 <6>[ 4.902214] mt6397-rtc mt6359-rtc: registered as rtc0
10857 15:39:07.537415 <6>[ 4.907672] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-22T15:39:12 UTC (1692718752)
10858 15:39:07.540735 <6>[ 4.917243] i2c_dev: i2c /dev entries driver
10859 15:39:07.557778 <6>[ 4.929035] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10860 15:39:07.577656 <6>[ 4.952036] cpu cpu0: EM: created perf domain
10861 15:39:07.581054 <6>[ 4.957052] cpu cpu4: EM: created perf domain
10862 15:39:07.588148 <6>[ 4.962716] sdhci: Secure Digital Host Controller Interface driver
10863 15:39:07.594543 <6>[ 4.969149] sdhci: Copyright(c) Pierre Ossman
10864 15:39:07.601222 <6>[ 4.974107] Synopsys Designware Multimedia Card Interface Driver
10865 15:39:07.608048 <6>[ 4.980748] sdhci-pltfm: SDHCI platform and OF driver helper
10866 15:39:07.611390 <6>[ 4.980775] mmc0: CQHCI version 5.10
10867 15:39:07.618068 <6>[ 4.990885] ledtrig-cpu: registered to indicate activity on CPUs
10868 15:39:07.624387 <6>[ 4.998053] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10869 15:39:07.631362 <6>[ 5.005112] usbcore: registered new interface driver usbhid
10870 15:39:07.634587 <6>[ 5.010934] usbhid: USB HID core driver
10871 15:39:07.641425 <6>[ 5.015128] spi_master spi0: will run message pump with realtime priority
10872 15:39:07.687222 <6>[ 5.055309] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10873 15:39:07.706878 <6>[ 5.071130] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10874 15:39:07.713543 <6>[ 5.086747] cros-ec-spi spi0.0: Chrome EC device registered
10875 15:39:07.716942 <6>[ 5.086841] mmc0: Command Queue Engine enabled
10876 15:39:07.723487 <6>[ 5.097308] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10877 15:39:07.730417 <6>[ 5.104859] mmcblk0: mmc0:0001 DA4128 116 GiB
10878 15:39:07.740287 <6>[ 5.105811] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10879 15:39:07.743636 <6>[ 5.113928] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10880 15:39:07.750092 <6>[ 5.119902] NET: Registered PF_PACKET protocol family
10881 15:39:07.756724 <6>[ 5.126168] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10882 15:39:07.760432 <6>[ 5.130171] 9pnet: Installing 9P2000 support
10883 15:39:07.767051 <6>[ 5.135968] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10884 15:39:07.770210 <5>[ 5.139840] Key type dns_resolver registered
10885 15:39:07.777089 <6>[ 5.145626] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10886 15:39:07.780138 <6>[ 5.149982] registered taskstats version 1
10887 15:39:07.786669 <5>[ 5.160440] Loading compiled-in X.509 certificates
10888 15:39:07.813679 <4>[ 5.181429] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10889 15:39:07.823812 <4>[ 5.192116] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10890 15:39:07.830143 <3>[ 5.202642] debugfs: File 'uA_load' in directory '/' already present!
10891 15:39:07.836364 <3>[ 5.209340] debugfs: File 'min_uV' in directory '/' already present!
10892 15:39:07.843366 <3>[ 5.215947] debugfs: File 'max_uV' in directory '/' already present!
10893 15:39:07.849980 <3>[ 5.222609] debugfs: File 'constraint_flags' in directory '/' already present!
10894 15:39:07.861936 <3>[ 5.233281] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10895 15:39:07.874189 <6>[ 5.249279] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10896 15:39:07.881294 <6>[ 5.256095] xhci-mtk 11200000.usb: xHCI Host Controller
10897 15:39:07.887897 <6>[ 5.261676] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10898 15:39:07.898303 <6>[ 5.269541] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10899 15:39:07.904418 <6>[ 5.278966] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10900 15:39:07.911084 <6>[ 5.285044] xhci-mtk 11200000.usb: xHCI Host Controller
10901 15:39:07.917695 <6>[ 5.290525] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10902 15:39:07.924422 <6>[ 5.298172] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10903 15:39:07.930956 <6>[ 5.305974] hub 1-0:1.0: USB hub found
10904 15:39:07.934575 <6>[ 5.309995] hub 1-0:1.0: 1 port detected
10905 15:39:07.941584 <6>[ 5.314267] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10906 15:39:07.947960 <6>[ 5.322964] hub 2-0:1.0: USB hub found
10907 15:39:07.951292 <6>[ 5.326985] hub 2-0:1.0: 1 port detected
10908 15:39:07.958803 <6>[ 5.333676] mtk-msdc 11f70000.mmc: Got CD GPIO
10909 15:39:07.969479 <6>[ 5.341209] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10910 15:39:07.976214 <6>[ 5.349230] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10911 15:39:07.985968 <4>[ 5.357123] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10912 15:39:07.995703 <6>[ 5.366651] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10913 15:39:08.002724 <6>[ 5.374727] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10914 15:39:08.009306 <6>[ 5.382769] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10915 15:39:08.019501 <6>[ 5.390686] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10916 15:39:08.026058 <6>[ 5.398503] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10917 15:39:08.035893 <6>[ 5.406321] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10918 15:39:08.046554 <6>[ 5.416753] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10919 15:39:08.052313 <6>[ 5.425110] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10920 15:39:08.062682 <6>[ 5.433455] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10921 15:39:08.069307 <6>[ 5.441794] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10922 15:39:08.079009 <6>[ 5.450132] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10923 15:39:08.085852 <6>[ 5.458470] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10924 15:39:08.096038 <6>[ 5.466808] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10925 15:39:08.102490 <6>[ 5.475148] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10926 15:39:08.112100 <6>[ 5.483486] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10927 15:39:08.118656 <6>[ 5.491825] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10928 15:39:08.128711 <6>[ 5.500162] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10929 15:39:08.138780 <6>[ 5.508500] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10930 15:39:08.145722 <6>[ 5.516838] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10931 15:39:08.155667 <6>[ 5.525177] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10932 15:39:08.161889 <6>[ 5.533514] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10933 15:39:08.168816 <6>[ 5.542279] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10934 15:39:08.175060 <6>[ 5.549422] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10935 15:39:08.182043 <6>[ 5.556202] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10936 15:39:08.188530 <6>[ 5.562956] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10937 15:39:08.195079 <6>[ 5.569929] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10938 15:39:08.205495 <6>[ 5.576776] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10939 15:39:08.215677 <6>[ 5.585908] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10940 15:39:08.225804 <6>[ 5.595032] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10941 15:39:08.235590 <6>[ 5.604328] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10942 15:39:08.242326 <6>[ 5.613796] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10943 15:39:08.251776 <6>[ 5.623263] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10944 15:39:08.261694 <6>[ 5.632383] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10945 15:39:08.271694 <6>[ 5.641849] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10946 15:39:08.281426 <6>[ 5.650969] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10947 15:39:08.291467 <6>[ 5.660264] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10948 15:39:08.301679 <6>[ 5.670424] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10949 15:39:08.311827 <6>[ 5.682498] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10950 15:39:08.354719 <6>[ 5.726372] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10951 15:39:08.507914 <6>[ 5.882622] hub 1-1:1.0: USB hub found
10952 15:39:08.510979 <6>[ 5.887043] hub 1-1:1.0: 4 ports detected
10953 15:39:08.635298 <6>[ 6.006754] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10954 15:39:08.661873 <6>[ 6.036916] hub 2-1:1.0: USB hub found
10955 15:39:08.665948 <6>[ 6.041491] hub 2-1:1.0: 3 ports detected
10956 15:39:08.830985 <6>[ 6.202426] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10957 15:39:08.963086 <6>[ 6.337855] hub 1-1.4:1.0: USB hub found
10958 15:39:08.965945 <6>[ 6.342470] hub 1-1.4:1.0: 2 ports detected
10959 15:39:09.042733 <6>[ 6.414451] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10960 15:39:09.263198 <6>[ 6.634458] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10961 15:39:09.454528 <6>[ 6.826428] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10962 15:39:20.587766 <6>[ 17.967410] ALSA device list:
10963 15:39:20.593838 <6>[ 17.970696] No soundcards found.
10964 15:39:20.601926 <6>[ 17.978622] Freeing unused kernel memory: 8384K
10965 15:39:20.605181 <6>[ 17.983629] Run /init as init process
10966 15:39:20.651978 <6>[ 18.028543] NET: Registered PF_INET6 protocol family
10967 15:39:20.658717 <6>[ 18.035171] Segment Routing with IPv6
10968 15:39:20.661779 <6>[ 18.039130] In-situ OAM (IOAM) with IPv6
10969 15:39:20.694216 <30>[ 18.053778] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10970 15:39:20.701152 <30>[ 18.077608] systemd[1]: Detected architecture arm64.
10971 15:39:20.701458
10972 15:39:20.707994 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10973 15:39:20.708426
10974 15:39:20.722277 <30>[ 18.098462] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10975 15:39:20.867260 <30>[ 18.240255] systemd[1]: Queued start job for default target Graphical Interface.
10976 15:39:20.899091 <30>[ 18.275387] systemd[1]: Created slice system-getty.slice.
10977 15:39:20.905642 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10978 15:39:20.923537 <30>[ 18.299420] systemd[1]: Created slice system-modprobe.slice.
10979 15:39:20.930206 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10980 15:39:20.947760 <30>[ 18.323757] systemd[1]: Created slice system-serial\x2dgetty.slice.
10981 15:39:20.957675 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10982 15:39:20.971007 <30>[ 18.347147] systemd[1]: Created slice User and Session Slice.
10983 15:39:20.977180 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10984 15:39:20.997985 <30>[ 18.370944] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10985 15:39:21.004903 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10986 15:39:21.025928 <30>[ 18.398885] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10987 15:39:21.032723 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10988 15:39:21.052759 <30>[ 18.422365] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10989 15:39:21.059069 <30>[ 18.434400] systemd[1]: Reached target Local Encrypted Volumes.
10990 15:39:21.065924 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10991 15:39:21.082334 <30>[ 18.458750] systemd[1]: Reached target Paths.
10992 15:39:21.085558 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10993 15:39:21.101830 <30>[ 18.478379] systemd[1]: Reached target Remote File Systems.
10994 15:39:21.108751 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10995 15:39:21.121726 <30>[ 18.498342] systemd[1]: Reached target Slices.
10996 15:39:21.125227 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10997 15:39:21.141902 <30>[ 18.518381] systemd[1]: Reached target Swap.
10998 15:39:21.145194 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10999 15:39:21.165835 <30>[ 18.538842] systemd[1]: Listening on initctl Compatibility Named Pipe.
11000 15:39:21.172322 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
11001 15:39:21.186891 <30>[ 18.563220] systemd[1]: Listening on Journal Audit Socket.
11002 15:39:21.193564 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
11003 15:39:21.211175 <30>[ 18.587500] systemd[1]: Listening on Journal Socket (/dev/log).
11004 15:39:21.217798 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
11005 15:39:21.235225 <30>[ 18.611548] systemd[1]: Listening on Journal Socket.
11006 15:39:21.241863 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
11007 15:39:21.254808 <30>[ 18.630896] systemd[1]: Listening on udev Control Socket.
11008 15:39:21.262035 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
11009 15:39:21.279028 <30>[ 18.655373] systemd[1]: Listening on udev Kernel Socket.
11010 15:39:21.285966 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
11011 15:39:21.338944 <30>[ 18.715049] systemd[1]: Mounting Huge Pages File System...
11012 15:39:21.345598 Mounting [0;1;39mHuge Pages File System[0m...
11013 15:39:21.362450 <30>[ 18.738385] systemd[1]: Mounting POSIX Message Queue File System...
11014 15:39:21.369300 Mounting [0;1;39mPOSIX Message Queue File System[0m...
11015 15:39:21.390160 <30>[ 18.766349] systemd[1]: Mounting Kernel Debug File System...
11016 15:39:21.396598 Mounting [0;1;39mKernel Debug File System[0m...
11017 15:39:21.413567 <30>[ 18.786923] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11018 15:39:21.427029 <30>[ 18.800236] systemd[1]: Starting Create list of static device nodes for the current kernel...
11019 15:39:21.433520 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11020 15:39:21.454643 <30>[ 18.831090] systemd[1]: Starting Load Kernel Module configfs...
11021 15:39:21.461219 Starting [0;1;39mLoad Kernel Module configfs[0m...
11022 15:39:21.478160 <30>[ 18.854996] systemd[1]: Starting Load Kernel Module drm...
11023 15:39:21.484898 Starting [0;1;39mLoad Kernel Module drm[0m...
11024 15:39:21.501123 <30>[ 18.874763] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11025 15:39:21.530390 <30>[ 18.907125] systemd[1]: Starting Journal Service...
11026 15:39:21.533832 Starting [0;1;39mJournal Service[0m...
11027 15:39:21.554942 <30>[ 18.931396] systemd[1]: Starting Load Kernel Modules...
11028 15:39:21.561282 Starting [0;1;39mLoad Kernel Modules[0m...
11029 15:39:21.582004 <30>[ 18.955185] systemd[1]: Starting Remount Root and Kernel File Systems...
11030 15:39:21.588615 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11031 15:39:21.605984 <30>[ 18.982364] systemd[1]: Starting Coldplug All udev Devices...
11032 15:39:21.612765 Starting [0;1;39mColdplug All udev Devices[0m...
11033 15:39:21.629313 <30>[ 19.005406] systemd[1]: Started Journal Service.
11034 15:39:21.635511 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11035 15:39:21.652888 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11036 15:39:21.671104 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11037 15:39:21.686675 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11038 15:39:21.707204 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11039 15:39:21.724583 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11040 15:39:21.744607 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11041 15:39:21.762618 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11042 15:39:21.783586 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11043 15:39:21.798085 See 'systemctl status systemd-remount-fs.service' for details.
11044 15:39:21.850744 Mounting [0;1;39mKernel Configuration File System[0m...
11045 15:39:21.868596 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11046 15:39:21.882173 <46>[ 19.255807] systemd-journald[186]: Received client request to flush runtime journal.
11047 15:39:21.891190 Starting [0;1;39mLoad/Save Random Seed[0m...
11048 15:39:21.909659 Starting [0;1;39mApply Kernel Variables[0m...
11049 15:39:21.934320 Starting [0;1;39mCreate System Users[0m...
11050 15:39:21.954855 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11051 15:39:21.974794 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11052 15:39:21.998968 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11053 15:39:22.011723 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11054 15:39:22.027639 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11055 15:39:22.043249 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11056 15:39:22.102284 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11057 15:39:22.123606 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11058 15:39:22.142319 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11059 15:39:22.162129 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11060 15:39:22.218477 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11061 15:39:22.246651 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11062 15:39:22.271098 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11063 15:39:22.291132 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11064 15:39:22.352003 Starting [0;1;39mNetwork Time Synchronization[0m...
11065 15:39:22.379286 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11066 15:39:22.432944 <6>[ 19.805743] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11067 15:39:22.439401 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11068 15:39:22.446272 <6>[ 19.822661] remoteproc remoteproc0: scp is available
11069 15:39:22.452849 <6>[ 19.828457] remoteproc remoteproc0: powering up scp
11070 15:39:22.459348 <6>[ 19.833985] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11071 15:39:22.466203 <6>[ 19.842440] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11072 15:39:22.472918 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11073 15:39:22.502199 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11074 15:39:22.526571 <6>[ 19.899611] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11075 15:39:22.532594 <6>[ 19.907463] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11076 15:39:22.543479 <6>[ 19.916216] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11077 15:39:22.553244 [[0;32m OK [<4>[ 19.925950] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11078 15:39:22.559858 0m] Created slic<6>[ 19.926913] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11079 15:39:22.569690 e [0;1;39msyste<6>[ 19.926949] usbcore: registered new interface driver r8152
11080 15:39:22.576550 <3>[ 19.928335] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11081 15:39:22.586408 <3>[ 19.928351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11082 15:39:22.593202 m-systemd\x2dbac<3>[ 19.928355] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11083 15:39:22.603173 <3>[ 19.930585] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11084 15:39:22.612741 klight.slice[0m<3>[ 19.930597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11085 15:39:22.619359 <3>[ 19.930602] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11086 15:39:22.619799 .
11087 15:39:22.629504 <3>[ 19.930607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11088 15:39:22.635910 <3>[ 19.930611] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11089 15:39:22.646138 <3>[ 19.930638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11090 15:39:22.652951 <3>[ 19.930676] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11091 15:39:22.659449 <3>[ 19.930679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11092 15:39:22.669940 <3>[ 19.930683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11093 15:39:22.676218 <3>[ 19.930707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11094 15:39:22.686629 <3>[ 19.930710] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11095 15:39:22.693828 <3>[ 19.930713] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11096 15:39:22.700586 <3>[ 19.930716] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11097 15:39:22.709918 <3>[ 19.930720] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11098 15:39:22.717402 <3>[ 19.930741] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11099 15:39:22.723479 <4>[ 19.936441] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11100 15:39:22.730180 <6>[ 19.945438] mc: Linux media interface: v0.10
11101 15:39:22.736607 <6>[ 19.975796] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11102 15:39:22.746876 <6>[ 19.975797] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11103 15:39:22.753410 <4>[ 19.994484] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11104 15:39:22.759711 <4>[ 19.994484] Fallback method does not support PEC.
11105 15:39:22.766625 <6>[ 20.001378] remoteproc remoteproc0: remote processor scp is now up
11106 15:39:22.773150 <6>[ 20.018750] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11107 15:39:22.779636 <6>[ 20.027496] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11108 15:39:22.789733 <6>[ 20.042773] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11109 15:39:22.796347 <6>[ 20.056277] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11110 15:39:22.806213 <6>[ 20.060850] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11111 15:39:22.812970 <6>[ 20.066567] pci_bus 0000:00: root bus resource [bus 00-ff]
11112 15:39:22.819287 <6>[ 20.066575] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11113 15:39:22.829573 <6>[ 20.066581] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11114 15:39:22.835939 <6>[ 20.066636] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11115 15:39:22.845886 <6>[ 20.075641] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11116 15:39:22.852416 <6>[ 20.076477] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11117 15:39:22.862674 <3>[ 20.077649] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11118 15:39:22.869844 <4>[ 20.078357] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11119 15:39:22.879615 <4>[ 20.078364] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11120 15:39:22.886437 <6>[ 20.082806] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11121 15:39:22.889500 <6>[ 20.082918] pci 0000:00:00.0: supports D1 D2
11122 15:39:22.896213 <6>[ 20.108302] videodev: Linux video capture interface: v2.00
11123 15:39:22.903367 <6>[ 20.111254] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11124 15:39:22.909633 <6>[ 20.111270] usbcore: registered new interface driver cdc_ether
11125 15:39:22.916022 <6>[ 20.120585] usbcore: registered new interface driver r8153_ecm
11126 15:39:22.919331 <6>[ 20.127692] Bluetooth: Core ver 2.22
11127 15:39:22.929887 <6>[ 20.128226] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11128 15:39:22.932745 <6>[ 20.128338] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11129 15:39:22.942757 <6>[ 20.128366] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11130 15:39:22.949477 <6>[ 20.128385] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11131 15:39:22.956090 <6>[ 20.128400] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11132 15:39:22.962639 <6>[ 20.128510] pci 0000:01:00.0: supports D1 D2
11133 15:39:22.969176 <6>[ 20.128512] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11134 15:39:22.976123 <6>[ 20.138300] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11135 15:39:22.982963 <6>[ 20.138324] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11136 15:39:22.990770 <6>[ 20.138329] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11137 15:39:23.000284 <6>[ 20.138337] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11138 15:39:23.007605 <6>[ 20.138350] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11139 15:39:23.014893 <6>[ 20.138363] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11140 15:39:23.021523 <6>[ 20.138376] pci 0000:00:00.0: PCI bridge to [bus 01]
11141 15:39:23.027814 <6>[ 20.138381] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11142 15:39:23.034620 <6>[ 20.138514] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11143 15:39:23.041226 <6>[ 20.139021] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11144 15:39:23.048031 <6>[ 20.139583] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11145 15:39:23.051207 <6>[ 20.140575] r8152 2-1.3:1.0 eth0: v1.12.13
11146 15:39:23.058317 <6>[ 20.146796] NET: Registered PF_BLUETOOTH protocol family
11147 15:39:23.064845 <5>[ 20.175555] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11148 15:39:23.071380 <6>[ 20.175579] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
11149 15:39:23.077699 <6>[ 20.179049] Bluetooth: HCI device and connection manager initialized
11150 15:39:23.084732 <6>[ 20.195906] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11151 15:39:23.090812 <6>[ 20.201039] Bluetooth: HCI socket layer initialized
11152 15:39:23.097984 <5>[ 20.201898] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11153 15:39:23.107524 <6>[ 20.213945] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11154 15:39:23.114681 <6>[ 20.217188] Bluetooth: L2CAP socket layer initialized
11155 15:39:23.120759 <6>[ 20.218017] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11156 15:39:23.127661 <6>[ 20.226785] usbcore: registered new interface driver uvcvideo
11157 15:39:23.134105 <4>[ 20.230694] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11158 15:39:23.140734 <6>[ 20.230705] cfg80211: failed to load regulatory.db
11159 15:39:23.144314 <6>[ 20.234855] Bluetooth: SCO socket layer initialized
11160 15:39:23.153981 <6>[ 20.299377] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11161 15:39:23.156873 <6>[ 20.350047] usbcore: registered new interface driver btusb
11162 15:39:23.170285 <4>[ 20.351252] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11163 15:39:23.173651 <3>[ 20.351263] Bluetooth: hci0: Failed to load firmware file (-2)
11164 15:39:23.180095 <3>[ 20.351266] Bluetooth: hci0: Failed to set up firmware (-2)
11165 15:39:23.190482 <4>[ 20.351270] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11166 15:39:23.196991 <6>[ 20.356677] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11167 15:39:23.206710 <3>[ 20.379087] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11168 15:39:23.213480 <3>[ 20.379741] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11169 15:39:23.223481 <3>[ 20.397292] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11170 15:39:23.229916 <6>[ 20.398167] mt7921e 0000:01:00.0: ASIC revision: 79610010
11171 15:39:23.236499 <3>[ 20.498452] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11172 15:39:23.249653 <4>[ 20.505942] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11173 15:39:23.252996 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11174 15:39:23.273873 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11175 15:39:23.286712 <3>[ 20.659739] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11176 15:39:23.317184 Starting [0;1;39mLoad/Save Screen …o<3>[ 20.689609] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11177 15:39:23.319948 f leds:white:kbd_backlight[0m...
11178 15:39:23.347078 [[0;32m OK [0m] Finished [0<3>[ 20.719620] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11179 15:39:23.354554 ;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11180 15:39:23.367084 <4>[ 20.736429] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11181 15:39:23.404950 <3>[ 20.778323] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11182 15:39:23.435180 <3>[ 20.808179] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11183 15:39:23.497899 <4>[ 20.867569] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11184 15:39:23.542358 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11185 15:39:23.558581 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11186 15:39:23.577465 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11187 15:39:23.592820 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11188 15:39:23.605719 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11189 15:39:23.626634 <4>[ 20.996844] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11190 15:39:23.638030 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11191 15:39:23.653660 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11192 15:39:23.670261 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11193 15:39:23.689261 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11194 15:39:23.734757 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11195 15:39:23.749127 <4>[ 21.119207] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11196 15:39:23.810748 Starting [0;1;39mUser Login Management[0m...
11197 15:39:23.830216 Starting [0;1;39mPermit User Sessions[0m...
11198 15:39:23.856465 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11199 15:39:23.874843 <4>[ 21.244965] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11200 15:39:23.881495 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11201 15:39:23.898588 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11202 15:39:23.915466 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11203 15:39:23.981592 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11204 15:39:23.999211 <4>[ 21.369470] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11205 15:39:24.055433 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11206 15:39:24.062929 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11207 15:39:24.078467 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11208 15:39:24.093894 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11209 15:39:24.118746 <4>[ 21.488912] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11210 15:39:24.143760 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11211 15:39:24.181298 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11212 15:39:24.195930
11213 15:39:24.196026
11214 15:39:24.199553 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11215 15:39:24.199635
11216 15:39:24.202669 debian-bullseye-arm64 login: root (automatic login)
11217 15:39:24.202779
11218 15:39:24.202877
11219 15:39:24.219130 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Tue Aug 22 15:20:14 UTC 2023 aarch64
11220 15:39:24.219239
11221 15:39:24.225874 The programs included with the Debian GNU/Linux system are free software;
11222 15:39:24.238706 the exact distribution terms for each <4>[ 21.610691] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11223 15:39:24.242311 program are described in the
11224 15:39:24.245627 individual files in /usr/share/doc/*/copyright.
11225 15:39:24.248818
11226 15:39:24.251956 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11227 15:39:24.255549 permitted by applicable law.
11228 15:39:24.255916 Matched prompt #10: / #
11230 15:39:24.256121 Setting prompt string to ['/ #']
11231 15:39:24.256214 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11233 15:39:24.256476 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11234 15:39:24.256622 start: 2.2.6 expect-shell-connection (timeout 00:01:44) [common]
11235 15:39:24.256747 Setting prompt string to ['/ #']
11236 15:39:24.256845 Forcing a shell prompt, looking for ['/ #']
11238 15:39:24.307087 / #
11239 15:39:24.307228 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11240 15:39:24.307334 Waiting using forced prompt support (timeout 00:02:30)
11241 15:39:24.311851
11242 15:39:24.312149 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11243 15:39:24.312244 start: 2.2.7 export-device-env (timeout 00:01:44) [common]
11244 15:39:24.312343 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11245 15:39:24.312471 end: 2.2 depthcharge-retry (duration 00:03:16) [common]
11246 15:39:24.312598 end: 2 depthcharge-action (duration 00:03:16) [common]
11247 15:39:24.312751 start: 3 lava-test-retry (timeout 00:05:00) [common]
11248 15:39:24.312845 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11249 15:39:24.312919 Using namespace: common
11251 15:39:24.413260 / # #
11252 15:39:24.413416 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11253 15:39:24.413564 <4>[ 21.729349] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11254 15:39:24.418598 #
11255 15:39:24.418868 Using /lava-11331384
11257 15:39:24.519225 / # export SHELL=/bin/sh
11258 15:39:24.519919 <3>[ 21.846699] mt7921e 0000:01:00.0: hardware init failed
11259 15:39:24.525928 export SHELL=/bin/sh
11261 15:39:24.627470 / # . /lava-11331384/environment
11262 15:39:24.633548 . /lava-11331384/environment
11264 15:39:24.735011 / # /lava-11331384/bin/lava-test-runner /lava-11331384/0
11265 15:39:24.735600 Test shell timeout: 10s (minimum of the action and connection timeout)
11266 15:39:24.741458 /lava-11331384/bin/lava-test-runner /lava-11331384/0
11267 15:39:24.762455 + export TESTRUN_ID=0_sleep
11268 15:39:24.765985 + cd /lava-11331384/0/tests/0_sleep
11269 15:39:24.769206 + cat uuid
11270 15:39:24.769661 + UUID=11331384_1.5.2.3.1
11271 15:39:24.772431 + set +x
11272 15:39:24.775883 <LAVA_SIGNAL_STARTRUN 0_sleep 11331384_1.5.2.3.1>
11273 15:39:24.776623 Received signal: <STARTRUN> 0_sleep 11331384_1.5.2.3.1
11274 15:39:24.777107 Starting test lava.0_sleep (11331384_1.5.2.3.1)
11275 15:39:24.777533 Skipping test definition patterns.
11276 15:39:24.778990 + ./config/lava/sleep/sleep.sh mem freeze
11277 15:39:24.782903 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11279 15:39:24.785352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11280 15:39:24.788643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11281 15:39:24.789413 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11283 15:39:24.792292 rtcwake: assuming RTC uses UTC ...
11284 15:39:24.802117 rtcwake: wakeup from "mem" using rtc0 at Tue Aug 22 15:39:35<6>[ 22.179844] PM: suspend entry (deep)
11285 15:39:24.805216 <6>[ 22.183760] Filesystems sync: 0.000 seconds
11286 15:39:24.808947 2023
11287 15:39:24.812080 <6>[ 22.190634] Freezing user space processes
11288 15:39:24.823451 <6>[ 22.197104] Freezing user space processes completed (elapsed 0.002 seconds)
11289 15:39:24.826899 <6>[ 22.204357] OOM killer disabled.
11290 15:39:24.830837 <6>[ 22.207849] Freezing remaining freezable tasks
11291 15:39:24.840380 <6>[ 22.213888] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11292 15:39:24.846925 <6>[ 22.221553] printk: Suspending console(s) (use no_console_suspend to debug)
11293 15:39:28.272128 <3>[ 25.422465] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11294 15:39:28.281824 <3>[ 25.422496] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11295 15:39:28.291652 <3>[ 25.422540] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11296 15:39:28.298640 <3>[ 25.422584] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11297 15:39:28.305403 <3>[ 25.422856] PM: Some devices failed to suspend, or early wake event detected
11298 15:39:28.311869 <4>[ 25.441578] typec port0-partner: PM: parent port0 should not be sleeping
11299 15:39:28.315080 <6>[ 25.695558] OOM killer enabled.
11300 15:39:28.325387 <6>[ 25.698973] Restarting tasks ... done.
11301 15:39:28.327952 <5>[ 25.706294] random: crng reseeded on system resumption
11302 15:39:28.332928 <6>[ 25.713124] PM: suspend exit
11303 15:39:28.335541 rtcwake: write error
11304 15:39:28.343370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11305 15:39:28.344034 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11307 15:39:28.346858 rtcwake: assuming RTC uses UTC ...
11308 15:39:28.353195 rtcwake: wakeup from "mem" using rtc0 at Tue Aug 22 15:39:39 2023
11309 15:39:28.365153 <6>[ 25.742420] PM: suspend entry (deep)
11310 15:39:28.368908 <6>[ 25.746320] Filesystems sync: 0.000 seconds
11311 15:39:28.371804 <6>[ 25.751394] Freezing user space processes
11312 15:39:28.383567 <6>[ 25.757292] Freezing user space processes completed (elapsed 0.001 seconds)
11313 15:39:28.386684 <6>[ 25.764522] OOM killer disabled.
11314 15:39:28.390021 <6>[ 25.768002] Freezing remaining freezable tasks
11315 15:39:28.399953 <6>[ 25.773880] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11316 15:39:28.406908 <6>[ 25.781532] printk: Suspending console(s) (use no_console_suspend to debug)
11317 15:39:31.854834 <3>[ 29.006467] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11318 15:39:31.865034 <3>[ 29.006496] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11319 15:39:31.874976 <3>[ 29.006539] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11320 15:39:31.881693 <3>[ 29.006582] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11321 15:39:31.888571 <3>[ 29.006852] PM: Some devices failed to suspend, or early wake event detected
11322 15:39:31.891482 <6>[ 29.272390] OOM killer enabled.
11323 15:39:31.900401 <6>[ 29.275800] Restarting tasks ... done.
11324 15:39:31.903564 <5>[ 29.282054] random: crng reseeded on system resumption
11325 15:39:31.907487 <6>[ 29.288927] PM: suspend exit
11326 15:39:31.911054 rtcwake: write error
11327 15:39:31.918205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11328 15:39:31.918492 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11330 15:39:31.921957 rtcwake: assuming RTC uses UTC ...
11331 15:39:31.928497 rtcwake: wakeup from "mem" using rtc0 at Tue Aug 22 15:39:42 2023
11332 15:39:31.941726 <6>[ 29.319487] PM: suspend entry (deep)
11333 15:39:31.944970 <6>[ 29.323400] Filesystems sync: 0.000 seconds
11334 15:39:31.948037 <6>[ 29.328545] Freezing user space processes
11335 15:39:31.959735 <6>[ 29.334257] Freezing user space processes completed (elapsed 0.001 seconds)
11336 15:39:31.963355 <6>[ 29.341552] OOM killer disabled.
11337 15:39:31.966517 <6>[ 29.345044] Freezing remaining freezable tasks
11338 15:39:31.976784 <6>[ 29.350980] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11339 15:39:31.983329 <6>[ 29.358650] printk: Suspending console(s) (use no_console_suspend to debug)
11340 15:39:35.441798 <3>[ 32.590410] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11341 15:39:35.452102 <3>[ 32.590434] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11342 15:39:35.462209 <3>[ 32.590462] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11343 15:39:35.468828 <3>[ 32.590492] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11344 15:39:35.475645 <3>[ 32.590712] PM: Some devices failed to suspend, or early wake event detected
11345 15:39:35.479293 <6>[ 32.859988] OOM killer enabled.
11346 15:39:35.488098 <6>[ 32.863406] Restarting tasks ... done.
11347 15:39:35.491680 <5>[ 32.869846] random: crng reseeded on system resumption
11348 15:39:35.495228 <6>[ 32.876515] PM: suspend exit
11349 15:39:35.498243 rtcwake: write error
11350 15:39:35.505361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11351 15:39:35.506061 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11353 15:39:35.508988 rtcwake: assuming RTC uses UTC ...
11354 15:39:35.515339 rtcwake: wakeup from "mem" using rtc0 at Tue Aug 22 15:39:46 2023
11355 15:39:35.528824 <6>[ 32.906849] PM: suspend entry (deep)
11356 15:39:35.532202 <6>[ 32.910786] Filesystems sync: 0.000 seconds
11357 15:39:35.539101 <6>[ 32.915936] Freezing user space processes
11358 15:39:35.545886 <6>[ 32.922284] Freezing user space processes completed (elapsed 0.002 seconds)
11359 15:39:35.549466 <6>[ 32.929527] OOM killer disabled.
11360 15:39:35.555735 <6>[ 32.933019] Freezing remaining freezable tasks
11361 15:39:35.563066 <6>[ 32.939041] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11362 15:39:35.572562 <6>[ 32.946710] printk: Suspending console(s) (use no_console_suspend to debug)
11363 15:39:39.025847 <3>[ 36.174490] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11364 15:39:39.036123 <3>[ 36.174521] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11365 15:39:39.046349 <3>[ 36.174561] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11366 15:39:39.053038 <3>[ 36.174596] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11367 15:39:39.059440 <3>[ 36.174884] PM: Some devices failed to suspend, or early wake event detected
11368 15:39:39.062892 <6>[ 36.444058] OOM killer enabled.
11369 15:39:39.071614 <6>[ 36.447471] Restarting tasks ... done.
11370 15:39:39.074981 <5>[ 36.453610] random: crng reseeded on system resumption
11371 15:39:39.078572 <6>[ 36.460402] PM: suspend exit
11372 15:39:39.081913 rtcwake: write error
11373 15:39:39.089388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11374 15:39:39.090156 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11376 15:39:39.091920 rtcwake: assuming RTC uses UTC ...
11377 15:39:39.098620 rtcwake: wakeup from "mem" using rtc0 at Tue Aug 22 15:39:50 2023
11378 15:39:39.111170 <6>[ 36.489384] PM: suspend entry (deep)
11379 15:39:39.115255 <6>[ 36.493280] Filesystems sync: 0.000 seconds
11380 15:39:39.117942 <6>[ 36.498401] Freezing user space processes
11381 15:39:39.129423 <6>[ 36.504285] Freezing user space processes completed (elapsed 0.001 seconds)
11382 15:39:39.133170 <6>[ 36.511511] OOM killer disabled.
11383 15:39:39.136029 <6>[ 36.514992] Freezing remaining freezable tasks
11384 15:39:39.146388 <6>[ 36.520876] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11385 15:39:39.152498 <6>[ 36.528536] printk: Suspending console(s) (use no_console_suspend to debug)
11386 15:39:42.613934 <3>[ 39.758480] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11387 15:39:42.624047 <3>[ 39.758511] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11388 15:39:42.633805 <3>[ 39.758553] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11389 15:39:42.640393 <3>[ 39.758593] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11390 15:39:42.647326 <3>[ 39.758876] PM: Some devices failed to suspend, or early wake event detected
11391 15:39:42.650612 <6>[ 40.032570] OOM killer enabled.
11392 15:39:42.659221 <6>[ 40.035981] Restarting tasks ... done.
11393 15:39:42.666002 <5>[ 40.043394] random: crng reseeded on system resumption
11394 15:39:42.669413 <6>[ 40.050279] PM: suspend exit
11395 15:39:42.672504 rtcwake: write error
11396 15:39:42.679273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11397 15:39:42.680143 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11399 15:39:42.683868 rtcwake: assuming RTC uses UTC ...
11400 15:39:42.689431 rtcwake: wakeup from "mem" using rtc0 at Tue Aug 22 15:39:53 2023
11401 15:39:42.700935 <6>[ 40.079353] PM: suspend entry (deep)
11402 15:39:42.703842 <6>[ 40.083262] Filesystems sync: 0.000 seconds
11403 15:39:42.707438 <6>[ 40.088313] Freezing user space processes
11404 15:39:42.718963 <6>[ 40.094409] Freezing user space processes completed (elapsed 0.001 seconds)
11405 15:39:42.722843 <6>[ 40.101634] OOM killer disabled.
11406 15:39:42.725631 <6>[ 40.105115] Freezing remaining freezable tasks
11407 15:39:42.735527 <6>[ 40.111000] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11408 15:39:42.742457 <6>[ 40.118653] printk: Suspending console(s) (use no_console_suspend to debug)
11409 15:39:46.197342 <3>[ 43.342473] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11410 15:39:46.208108 <3>[ 43.342504] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11411 15:39:46.217727 <3>[ 43.342547] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11412 15:39:46.224454 <3>[ 43.342586] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11413 15:39:46.230924 <3>[ 43.342877] PM: Some devices failed to suspend, or early wake event detected
11414 15:39:46.234515 <6>[ 43.616568] OOM killer enabled.
11415 15:39:46.243145 <6>[ 43.619978] Restarting tasks ... done.
11416 15:39:46.246563 <5>[ 43.626161] random: crng reseeded on system resumption
11417 15:39:46.250211 <6>[ 43.632818] PM: suspend exit
11418 15:39:46.253647 rtcwake: write error
11419 15:39:46.260732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11420 15:39:46.261553 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11422 15:39:46.263934 rtcwake: assuming RTC uses UTC ...
11423 15:39:46.270318 rtcwake: wakeup from "mem" using rtc0 at Tue Aug 22 15:39:57 2023
11424 15:39:46.284336 <6>[ 43.663164] PM: suspend entry (deep)
11425 15:39:46.288030 <6>[ 43.667115] Filesystems sync: 0.000 seconds
11426 15:39:46.290777 <6>[ 43.672270] Freezing user space processes
11427 15:39:46.302464 <6>[ 43.678320] Freezing user space processes completed (elapsed 0.001 seconds)
11428 15:39:46.306031 <6>[ 43.685615] OOM killer disabled.
11429 15:39:46.309578 <6>[ 43.689103] Freezing remaining freezable tasks
11430 15:39:46.319792 <6>[ 43.695159] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11431 15:39:46.326153 <6>[ 43.702833] printk: Suspending console(s) (use no_console_suspend to debug)
11432 15:39:49.780858 <3>[ 46.926466] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11433 15:39:49.791128 <3>[ 46.926504] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11434 15:39:49.800825 <3>[ 46.926538] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11435 15:39:49.807693 <3>[ 46.926570] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11436 15:39:49.814374 <3>[ 46.926932] PM: Some devices failed to suspend, or early wake event detected
11437 15:39:49.817581 <6>[ 47.200070] OOM killer enabled.
11438 15:39:49.825910 <6>[ 47.203483] Restarting tasks ... done.
11439 15:39:49.829292 <5>[ 47.209527] random: crng reseeded on system resumption
11440 15:39:49.833358 <6>[ 47.216165] PM: suspend exit
11441 15:39:49.836430 rtcwake: write error
11442 15:39:49.843962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11443 15:39:49.844834 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11445 15:39:49.847050 rtcwake: assuming RTC uses UTC ...
11446 15:39:49.853494 rtcwake: wakeup from "mem" using rtc0 at Tue Aug 22 15:40:00 2023
11447 15:39:49.865864 <6>[ 47.245302] PM: suspend entry (deep)
11448 15:39:49.869815 <6>[ 47.249198] Filesystems sync: 0.000 seconds
11449 15:39:49.872774 <6>[ 47.254326] Freezing user space processes
11450 15:39:49.884168 <6>[ 47.260308] Freezing user space processes completed (elapsed 0.001 seconds)
11451 15:39:49.888088 <6>[ 47.267543] OOM killer disabled.
11452 15:39:49.891092 <6>[ 47.271025] Freezing remaining freezable tasks
11453 15:39:49.900862 <6>[ 47.277028] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11454 15:39:49.907683 <6>[ 47.284705] printk: Suspending console(s) (use no_console_suspend to debug)
11455 15:39:53.353607 <6>[ 48.206621] vpu: disabling
11456 15:39:53.356857 <6>[ 48.206820] vproc2: disabling
11457 15:39:53.360173 <6>[ 48.206875] vproc1: disabling
11458 15:39:53.364106 <6>[ 48.206930] vaud18: disabling
11459 15:39:53.367459 <6>[ 48.207178] vsram_others: disabling
11460 15:39:53.370114 <6>[ 48.207376] va09: disabling
11461 15:39:53.373565 <6>[ 48.207453] vsram_md: disabling
11462 15:39:53.376725 <6>[ 48.207581] Vgpu: disabling
11463 15:39:53.383429 <3>[ 50.510439] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11464 15:39:53.393528 <3>[ 50.510470] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11465 15:39:53.403131 <3>[ 50.510513] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11466 15:39:53.410141 <3>[ 50.510552] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11467 15:39:53.417112 <3>[ 50.510839] PM: Some devices failed to suspend, or early wake event detected
11468 15:39:53.421087 <6>[ 50.802271] OOM killer enabled.
11469 15:39:53.428624 <6>[ 50.805669] Restarting tasks ... done.
11470 15:39:53.431630 <5>[ 50.812297] random: crng reseeded on system resumption
11471 15:39:53.435780 <6>[ 50.819073] PM: suspend exit
11472 15:39:53.439417 rtcwake: write error
11473 15:39:53.445829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11474 15:39:53.446701 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11476 15:39:53.449688 rtcwake: assuming RTC uses UTC ...
11477 15:39:53.455593 rtcwake: wakeup from "mem" using rtc0 at Tue Aug 22 15:40:04 2023
11478 15:39:53.468037 <6>[ 50.848141] PM: suspend entry (deep)
11479 15:39:53.471622 <6>[ 50.852066] Filesystems sync: 0.000 seconds
11480 15:39:53.474971 <6>[ 50.857138] Freezing user space processes
11481 15:39:53.486496 <6>[ 50.862981] Freezing user space processes completed (elapsed 0.001 seconds)
11482 15:39:53.489716 <6>[ 50.870204] OOM killer disabled.
11483 15:39:53.493322 <6>[ 50.873680] Freezing remaining freezable tasks
11484 15:39:53.503184 <6>[ 50.879717] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11485 15:39:53.509978 <6>[ 50.887394] printk: Suspending console(s) (use no_console_suspend to debug)
11486 15:39:56.948599 <3>[ 54.094438] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11487 15:39:56.958459 <3>[ 54.094469] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11488 15:39:56.968320 <3>[ 54.094511] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11489 15:39:56.975107 <3>[ 54.094551] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11490 15:39:56.982474 <3>[ 54.094793] PM: Some devices failed to suspend, or early wake event detected
11491 15:39:56.984990 <6>[ 54.368568] OOM killer enabled.
11492 15:39:56.994617 <6>[ 54.371979] Restarting tasks ... done.
11493 15:39:56.998289 <5>[ 54.379306] random: crng reseeded on system resumption
11494 15:39:57.002447 <6>[ 54.386047] PM: suspend exit
11495 15:39:57.005657 rtcwake: write error
11496 15:39:57.012878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11497 15:39:57.013674 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11499 15:39:57.015939 rtcwake: assuming RTC uses UTC ...
11500 15:39:57.022722 rtcwake: wakeup from "mem" using rtc0 at Tue Aug 22 15:40:08 2023
11501 15:39:57.035036 <6>[ 54.415160] PM: suspend entry (deep)
11502 15:39:57.038590 <6>[ 54.419051] Filesystems sync: 0.000 seconds
11503 15:39:57.041687 <6>[ 54.424097] Freezing user space processes
11504 15:39:57.053610 <6>[ 54.430114] Freezing user space processes completed (elapsed 0.001 seconds)
11505 15:39:57.056803 <6>[ 54.437343] OOM killer disabled.
11506 15:39:57.060014 <6>[ 54.440826] Freezing remaining freezable tasks
11507 15:39:57.070045 <6>[ 54.446728] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11508 15:39:57.076832 <6>[ 54.454379] printk: Suspending console(s) (use no_console_suspend to debug)
11509 15:40:00.532370 <3>[ 57.678467] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11510 15:40:00.541995 <3>[ 57.678507] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11511 15:40:00.552636 <3>[ 57.678561] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11512 15:40:00.558945 <3>[ 57.678604] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11513 15:40:00.565654 <3>[ 57.678892] PM: Some devices failed to suspend, or early wake event detected
11514 15:40:00.569149 <6>[ 57.952570] OOM killer enabled.
11515 15:40:00.579927 <6>[ 57.955983] Restarting tasks ... done.
11516 15:40:00.583360 <5>[ 57.964452] random: crng reseeded on system resumption
11517 15:40:00.587292 <6>[ 57.971415] PM: suspend exit
11518 15:40:00.590735 rtcwake: write error
11519 15:40:00.597668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11520 15:40:00.598526 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11522 15:40:00.600963 rtcwake: assuming RTC uses UTC ...
11523 15:40:00.608047 rtcwake: wakeup from "freeze" using rtc0 at Tue Aug 22 15:40:11 2023
11524 15:40:00.621287 <6>[ 58.002137] PM: suspend entry (s2idle)
11525 15:40:00.624653 <6>[ 58.006196] Filesystems sync: 0.000 seconds
11526 15:40:00.628377 <6>[ 58.011233] Freezing user space processes
11527 15:40:00.639735 <6>[ 58.017274] Freezing user space processes completed (elapsed 0.001 seconds)
11528 15:40:00.643463 <6>[ 58.024509] OOM killer disabled.
11529 15:40:00.646681 <6>[ 58.027989] Freezing remaining freezable tasks
11530 15:40:00.656861 <6>[ 58.034100] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11531 15:40:00.663508 <6>[ 58.041776] printk: Suspending console(s) (use no_console_suspend to debug)
11532 15:40:04.115541 <3>[ 61.262439] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11533 15:40:04.125506 <3>[ 61.262469] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11534 15:40:04.136074 <3>[ 61.262511] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11535 15:40:04.142263 <3>[ 61.262551] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11536 15:40:04.148998 <3>[ 61.262839] PM: Some devices failed to suspend, or early wake event detected
11537 15:40:04.152319 <6>[ 61.536482] OOM killer enabled.
11538 15:40:04.161556 <6>[ 61.539894] Restarting tasks ... done.
11539 15:40:04.164364 <5>[ 61.546470] random: crng reseeded on system resumption
11540 15:40:04.169563 <6>[ 61.553865] PM: suspend exit
11541 15:40:04.172616 rtcwake: write error
11542 15:40:04.179520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11543 15:40:04.180361 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11545 15:40:04.183333 rtcwake: assuming RTC uses UTC ...
11546 15:40:04.189602 rtcwake: wakeup from "freeze" using rtc0 at Tue Aug 22 15:40:15 2023
11547 15:40:04.201825 <6>[ 61.582965] PM: suspend entry (s2idle)
11548 15:40:04.205303 <6>[ 61.587043] Filesystems sync: 0.000 seconds
11549 15:40:04.208595 <6>[ 61.592098] Freezing user space processes
11550 15:40:04.220036 <6>[ 61.598098] Freezing user space processes completed (elapsed 0.001 seconds)
11551 15:40:04.223991 <6>[ 61.605333] OOM killer disabled.
11552 15:40:04.226813 <6>[ 61.608813] Freezing remaining freezable tasks
11553 15:40:04.237089 <6>[ 61.614726] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11554 15:40:04.244043 <6>[ 61.622380] printk: Suspending console(s) (use no_console_suspend to debug)
11555 15:40:07.698979 <3>[ 64.846437] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11556 15:40:07.709369 <3>[ 64.846468] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11557 15:40:07.719189 <3>[ 64.846511] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11558 15:40:07.725962 <3>[ 64.846551] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11559 15:40:07.732837 <3>[ 64.846843] PM: Some devices failed to suspend, or early wake event detected
11560 15:40:07.736795 <6>[ 65.120475] OOM killer enabled.
11561 15:40:07.744569 <6>[ 65.123898] Restarting tasks ... done.
11562 15:40:07.748125 <5>[ 65.129921] random: crng reseeded on system resumption
11563 15:40:07.751795 <6>[ 65.136731] PM: suspend exit
11564 15:40:07.755236 rtcwake: write error
11565 15:40:07.762373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11566 15:40:07.763147 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11568 15:40:07.765912 rtcwake: assuming RTC uses UTC ...
11569 15:40:07.772376 rtcwake: wakeup from "freeze" using rtc0 at Tue Aug 22 15:40:18 2023
11570 15:40:07.784815 <6>[ 65.166089] PM: suspend entry (s2idle)
11571 15:40:07.788360 <6>[ 65.170182] Filesystems sync: 0.000 seconds
11572 15:40:07.791374 <6>[ 65.175218] Freezing user space processes
11573 15:40:07.803532 <6>[ 65.181189] Freezing user space processes completed (elapsed 0.001 seconds)
11574 15:40:07.806901 <6>[ 65.188418] OOM killer disabled.
11575 15:40:07.809527 <6>[ 65.191899] Freezing remaining freezable tasks
11576 15:40:07.819959 <6>[ 65.197922] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11577 15:40:07.826511 <6>[ 65.205596] printk: Suspending console(s) (use no_console_suspend to debug)
11578 15:40:11.282395 <3>[ 68.430438] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11579 15:40:11.292607 <3>[ 68.430468] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11580 15:40:11.302643 <3>[ 68.430510] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11581 15:40:11.309545 <3>[ 68.430551] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11582 15:40:11.318989 <3>[ 68.430852] PM: Some devices failed to suspend, or early wake event detected
11583 15:40:11.322612 <6>[ 68.704424] OOM killer enabled.
11584 15:40:11.325467 <6>[ 68.707836] Restarting tasks ... done.
11585 15:40:11.332896 <5>[ 68.713608] random: crng reseeded on system resumption
11586 15:40:11.336260 <6>[ 68.720387] PM: suspend exit
11587 15:40:11.338937 rtcwake: write error
11588 15:40:11.346341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11589 15:40:11.347205 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11591 15:40:11.349792 rtcwake: assuming RTC uses UTC ...
11592 15:40:11.356049 rtcwake: wakeup from "freeze" using rtc0 at Tue Aug 22 15:40:22 2023
11593 15:40:11.368093 <6>[ 68.749725] PM: suspend entry (s2idle)
11594 15:40:11.370957 <6>[ 68.753788] Filesystems sync: 0.000 seconds
11595 15:40:11.374674 <6>[ 68.758856] Freezing user space processes
11596 15:40:11.385775 <6>[ 68.764748] Freezing user space processes completed (elapsed 0.001 seconds)
11597 15:40:11.390399 <6>[ 68.771981] OOM killer disabled.
11598 15:40:11.392747 <6>[ 68.775463] Freezing remaining freezable tasks
11599 15:40:11.403222 <6>[ 68.781485] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11600 15:40:11.409464 <6>[ 68.789159] printk: Suspending console(s) (use no_console_suspend to debug)
11601 15:40:14.866057 <3>[ 72.014523] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11602 15:40:14.876177 <3>[ 72.014558] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11603 15:40:14.886354 <3>[ 72.014608] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11604 15:40:14.893310 <3>[ 72.014646] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11605 15:40:14.899716 <3>[ 72.014903] PM: Some devices failed to suspend, or early wake event detected
11606 15:40:14.903670 <6>[ 72.288488] OOM killer enabled.
11607 15:40:14.911678 <6>[ 72.291901] Restarting tasks ... done.
11608 15:40:14.914904 <5>[ 72.297914] random: crng reseeded on system resumption
11609 15:40:14.918829 <6>[ 72.304863] PM: suspend exit
11610 15:40:14.923041 rtcwake: write error
11611 15:40:14.928990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11612 15:40:14.929832 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11614 15:40:14.932307 rtcwake: assuming RTC uses UTC ...
11615 15:40:14.939542 rtcwake: wakeup from "freeze" using rtc0 at Tue Aug 22 15:40:26 2023
11616 15:40:14.951302 <6>[ 72.333850] PM: suspend entry (s2idle)
11617 15:40:14.954799 <6>[ 72.337939] Filesystems sync: 0.000 seconds
11618 15:40:14.958294 <6>[ 72.342985] Freezing user space processes
11619 15:40:14.969898 <6>[ 72.348919] Freezing user space processes completed (elapsed 0.001 seconds)
11620 15:40:14.973417 <6>[ 72.356148] OOM killer disabled.
11621 15:40:14.976743 <6>[ 72.359628] Freezing remaining freezable tasks
11622 15:40:14.986898 <6>[ 72.365652] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11623 15:40:14.993313 <6>[ 72.373320] printk: Suspending console(s) (use no_console_suspend to debug)
11624 15:40:18.449705 <3>[ 75.598439] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11625 15:40:18.459524 <3>[ 75.598469] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11626 15:40:18.469905 <3>[ 75.598511] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11627 15:40:18.476527 <3>[ 75.598552] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11628 15:40:18.483388 <3>[ 75.598848] PM: Some devices failed to suspend, or early wake event detected
11629 15:40:18.486914 <6>[ 75.872467] OOM killer enabled.
11630 15:40:18.495126 <6>[ 75.875880] Restarting tasks ... done.
11631 15:40:18.501874 <5>[ 75.883422] random: crng reseeded on system resumption
11632 15:40:18.504963 <6>[ 75.890177] PM: suspend exit
11633 15:40:18.508643 rtcwake: write error
11634 15:40:18.515511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11635 15:40:18.516421 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11637 15:40:18.518650 rtcwake: assuming RTC uses UTC ...
11638 15:40:18.525665 rtcwake: wakeup from "freeze" using rtc0 at Tue Aug 22 15:40:29 2023
11639 15:40:18.537300 <6>[ 75.919580] PM: suspend entry (s2idle)
11640 15:40:18.540438 <6>[ 75.923645] Filesystems sync: 0.000 seconds
11641 15:40:18.547216 <6>[ 75.928740] Freezing user space processes
11642 15:40:18.553468 <6>[ 75.934231] Freezing user space processes completed (elapsed 0.001 seconds)
11643 15:40:18.557027 <6>[ 75.941457] OOM killer disabled.
11644 15:40:18.560452 <6>[ 75.944936] Freezing remaining freezable tasks
11645 15:40:18.571662 <6>[ 75.950808] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11646 15:40:18.577788 <6>[ 75.958458] printk: Suspending console(s) (use no_console_suspend to debug)
11647 15:40:22.029395 <3>[ 79.182448] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11648 15:40:22.039648 <3>[ 79.182478] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11649 15:40:22.049597 <3>[ 79.182521] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11650 15:40:22.056301 <3>[ 79.182564] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11651 15:40:22.062982 <3>[ 79.182821] PM: Some devices failed to suspend, or early wake event detected
11652 15:40:22.066401 <6>[ 79.452455] OOM killer enabled.
11653 15:40:22.074525 <6>[ 79.455871] Restarting tasks ... done.
11654 15:40:22.081227 <5>[ 79.463182] random: crng reseeded on system resumption
11655 15:40:22.084377 <6>[ 79.469812] PM: suspend exit
11656 15:40:22.087820 rtcwake: write error
11657 15:40:22.094690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11658 15:40:22.095556 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11660 15:40:22.097845 rtcwake: assuming RTC uses UTC ...
11661 15:40:22.104288 rtcwake: wakeup from "freeze" using rtc0 at Tue Aug 22 15:40:33 2023
11662 15:40:22.115715 <6>[ 79.499114] PM: suspend entry (s2idle)
11663 15:40:22.119443 <6>[ 79.503186] Filesystems sync: 0.000 seconds
11664 15:40:22.125359 <6>[ 79.508219] Freezing user space processes
11665 15:40:22.132940 <6>[ 79.514180] Freezing user space processes completed (elapsed 0.001 seconds)
11666 15:40:22.135941 <6>[ 79.521403] OOM killer disabled.
11667 15:40:22.142961 <6>[ 79.524884] Freezing remaining freezable tasks
11668 15:40:22.149168 <6>[ 79.530870] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11669 15:40:22.159070 <6>[ 79.538527] printk: Suspending console(s) (use no_console_suspend to debug)
11670 15:40:25.617226 <3>[ 82.766436] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11671 15:40:25.626689 <3>[ 82.766465] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11672 15:40:25.637306 <3>[ 82.766508] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11673 15:40:25.643647 <3>[ 82.766552] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11674 15:40:25.650905 <3>[ 82.766738] PM: Some devices failed to suspend, or early wake event detected
11675 15:40:25.654092 <6>[ 83.040421] OOM killer enabled.
11676 15:40:25.661797 <6>[ 83.043832] Restarting tasks ... done.
11677 15:40:25.665251 <5>[ 83.049579] random: crng reseeded on system resumption
11678 15:40:25.669170 <6>[ 83.056418] PM: suspend exit
11679 15:40:25.672980 rtcwake: write error
11680 15:40:25.679365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11681 15:40:25.680218 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11683 15:40:25.682898 rtcwake: assuming RTC uses UTC ...
11684 15:40:25.689718 rtcwake: wakeup from "freeze" using rtc0 at Tue Aug 22 15:40:36 2023
11685 15:40:25.701896 <6>[ 83.085485] PM: suspend entry (s2idle)
11686 15:40:25.705132 <6>[ 83.089581] Filesystems sync: 0.000 seconds
11687 15:40:25.711642 <6>[ 83.094796] Freezing user space processes
11688 15:40:25.718453 <6>[ 83.100727] Freezing user space processes completed (elapsed 0.001 seconds)
11689 15:40:25.721751 <6>[ 83.107961] OOM killer disabled.
11690 15:40:25.728571 <6>[ 83.111443] Freezing remaining freezable tasks
11691 15:40:25.735304 <6>[ 83.117500] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11692 15:40:25.745279 <6>[ 83.125173] printk: Suspending console(s) (use no_console_suspend to debug)
11693 15:40:29.200471 <3>[ 86.350506] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11694 15:40:29.210299 <3>[ 86.350546] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11695 15:40:29.220494 <3>[ 86.350599] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11696 15:40:29.227312 <3>[ 86.350644] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11697 15:40:29.234365 <3>[ 86.350947] PM: Some devices failed to suspend, or early wake event detected
11698 15:40:29.236980 <6>[ 86.624470] OOM killer enabled.
11699 15:40:29.245731 <6>[ 86.627882] Restarting tasks ... done.
11700 15:40:29.252612 <5>[ 86.635493] random: crng reseeded on system resumption
11701 15:40:29.255809 <6>[ 86.642452] PM: suspend exit
11702 15:40:29.259575 rtcwake: write error
11703 15:40:29.266106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11704 15:40:29.267004 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11706 15:40:29.269065 rtcwake: assuming RTC uses UTC ...
11707 15:40:29.275896 rtcwake: wakeup from "freeze" using rtc0 at Tue Aug 22 15:40:40 2023
11708 15:40:29.287495 <6>[ 86.671490] PM: suspend entry (s2idle)
11709 15:40:29.290681 <6>[ 86.675569] Filesystems sync: 0.000 seconds
11710 15:40:29.297601 <6>[ 86.680642] Freezing user space processes
11711 15:40:29.304124 <6>[ 86.686227] Freezing user space processes completed (elapsed 0.001 seconds)
11712 15:40:29.308195 <6>[ 86.693444] OOM killer disabled.
11713 15:40:29.314028 <6>[ 86.696923] Freezing remaining freezable tasks
11714 15:40:29.320907 <6>[ 86.702791] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11715 15:40:29.327371 <6>[ 86.710442] printk: Suspending console(s) (use no_console_suspend to debug)
11716 15:40:32.784485 <3>[ 89.934485] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11717 15:40:32.794258 <3>[ 89.934524] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11718 15:40:32.804348 <3>[ 89.934576] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11719 15:40:32.810980 <3>[ 89.934622] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11720 15:40:32.817410 <3>[ 89.934906] PM: Some devices failed to suspend, or early wake event detected
11721 15:40:32.821220 <6>[ 90.208523] OOM killer enabled.
11722 15:40:32.829272 <6>[ 90.211935] Restarting tasks ... done.
11723 15:40:32.832214 <5>[ 90.217684] random: crng reseeded on system resumption
11724 15:40:32.836995 <6>[ 90.224410] PM: suspend exit
11725 15:40:32.839792 rtcwake: write error
11726 15:40:32.847697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11727 15:40:32.848562 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11729 15:40:32.850108 rtcwake: assuming RTC uses UTC ...
11730 15:40:32.856712 rtcwake: wakeup from "freeze" using rtc0 at Tue Aug 22 15:40:43 2023
11731 15:40:32.869454 <6>[ 90.253783] PM: suspend entry (s2idle)
11732 15:40:32.872804 <6>[ 90.257841] Filesystems sync: 0.000 seconds
11733 15:40:32.876460 <6>[ 90.262856] Freezing user space processes
11734 15:40:32.887733 <6>[ 90.268805] Freezing user space processes completed (elapsed 0.001 seconds)
11735 15:40:32.891095 <6>[ 90.276037] OOM killer disabled.
11736 15:40:32.894408 <6>[ 90.279518] Freezing remaining freezable tasks
11737 15:40:32.904513 <6>[ 90.285546] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11738 15:40:32.911458 <6>[ 90.293218] printk: Suspending console(s) (use no_console_suspend to debug)
11739 15:40:36.364157 <3>[ 93.518501] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11740 15:40:36.374339 <3>[ 93.518532] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11741 15:40:36.383451 <3>[ 93.518575] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11742 15:40:36.390201 <3>[ 93.518615] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11743 15:40:36.397268 <3>[ 93.518997] PM: Some devices failed to suspend, or early wake event detected
11744 15:40:36.400116 <6>[ 93.788552] OOM killer enabled.
11745 15:40:36.409609 <6>[ 93.791962] Restarting tasks ... done.
11746 15:40:36.411807 <5>[ 93.797819] random: crng reseeded on system resumption
11747 15:40:36.416134 <6>[ 93.804374] PM: suspend exit
11748 15:40:36.419431 rtcwake: write error
11749 15:40:36.427062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11750 15:40:36.427809 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11752 15:40:36.429933 + set +x
11753 15:40:36.432903 <LAVA_SIGNAL_ENDRUN 0_sleep 11331384_1.5.2.3.1>
11754 15:40:36.433366 <LAVA_TEST_RUNNER EXIT>
11755 15:40:36.433989 Received signal: <ENDRUN> 0_sleep 11331384_1.5.2.3.1
11756 15:40:36.434418 Ending use of test pattern.
11757 15:40:36.434815 Ending test lava.0_sleep (11331384_1.5.2.3.1), duration 71.66
11759 15:40:36.436339 ok: lava_test_shell seems to have completed
11760 15:40:36.437466 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11761 15:40:36.438037 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11762 15:40:36.438522 end: 3 lava-test-retry (duration 00:01:12) [common]
11763 15:40:36.439160 start: 4 finalize (timeout 00:04:57) [common]
11764 15:40:36.439785 start: 4.1 power-off (timeout 00:00:30) [common]
11765 15:40:36.440637 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11766 15:40:36.558858 >> Command sent successfully.
11767 15:40:36.562039 Returned 0 in 0 seconds
11768 15:40:36.662912 end: 4.1 power-off (duration 00:00:00) [common]
11770 15:40:36.664517 start: 4.2 read-feedback (timeout 00:04:57) [common]
11771 15:40:36.665942 Listened to connection for namespace 'common' for up to 1s
11772 15:40:36.666823 Listened to connection for namespace 'common' for up to 1s
11773 15:40:37.666333 Finalising connection for namespace 'common'
11774 15:40:37.666554 Disconnecting from shell: Finalise
11775 15:40:37.666667 / #
11776 15:40:37.767221 end: 4.2 read-feedback (duration 00:00:01) [common]
11777 15:40:37.767704 end: 4 finalize (duration 00:00:01) [common]
11778 15:40:37.768098 Cleaning after the job
11779 15:40:37.768452 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/ramdisk
11780 15:40:37.784852 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/kernel
11781 15:40:37.807472 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/dtb
11782 15:40:37.807685 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331384/tftp-deploy-8yx1oycu/modules
11783 15:40:37.814865 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11331384
11784 15:40:37.981840 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11331384
11785 15:40:37.982023 Job finished correctly