Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 27
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 38
- Errors: 1
1 15:34:56.074563 lava-dispatcher, installed at version: 2023.06
2 15:34:56.074798 start: 0 validate
3 15:34:56.074946 Start time: 2023-08-22 15:34:56.074937+00:00 (UTC)
4 15:34:56.075093 Using caching service: 'http://localhost/cache/?uri=%s'
5 15:34:56.075249 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 15:34:56.336987 Using caching service: 'http://localhost/cache/?uri=%s'
7 15:34:56.337718 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 15:35:19.109708 Using caching service: 'http://localhost/cache/?uri=%s'
9 15:35:19.110472 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 15:35:19.380723 Using caching service: 'http://localhost/cache/?uri=%s'
11 15:35:19.381390 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 15:35:19.909353 Using caching service: 'http://localhost/cache/?uri=%s'
13 15:35:19.910087 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 15:35:25.413441 validate duration: 29.34
16 15:35:25.413703 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 15:35:25.413805 start: 1.1 download-retry (timeout 00:10:00) [common]
18 15:35:25.413892 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 15:35:25.414025 Not decompressing ramdisk as can be used compressed.
20 15:35:25.414112 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 15:35:25.414176 saving as /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/ramdisk/initrd.cpio.gz
22 15:35:25.414241 total size: 4665412 (4 MB)
23 15:35:25.415351 progress 0 % (0 MB)
24 15:35:25.416864 progress 5 % (0 MB)
25 15:35:25.418110 progress 10 % (0 MB)
26 15:35:25.419349 progress 15 % (0 MB)
27 15:35:25.420626 progress 20 % (0 MB)
28 15:35:25.421920 progress 25 % (1 MB)
29 15:35:25.423178 progress 30 % (1 MB)
30 15:35:25.424476 progress 35 % (1 MB)
31 15:35:25.425712 progress 40 % (1 MB)
32 15:35:25.427104 progress 45 % (2 MB)
33 15:35:25.428338 progress 50 % (2 MB)
34 15:35:25.429575 progress 55 % (2 MB)
35 15:35:25.430870 progress 60 % (2 MB)
36 15:35:25.432117 progress 65 % (2 MB)
37 15:35:25.433346 progress 70 % (3 MB)
38 15:35:25.434621 progress 75 % (3 MB)
39 15:35:25.435907 progress 80 % (3 MB)
40 15:35:25.437328 progress 85 % (3 MB)
41 15:35:25.438558 progress 90 % (4 MB)
42 15:35:25.439839 progress 95 % (4 MB)
43 15:35:25.441087 progress 100 % (4 MB)
44 15:35:25.441241 4 MB downloaded in 0.03 s (164.78 MB/s)
45 15:35:25.441431 end: 1.1.1 http-download (duration 00:00:00) [common]
47 15:35:25.441670 end: 1.1 download-retry (duration 00:00:00) [common]
48 15:35:25.441756 start: 1.2 download-retry (timeout 00:10:00) [common]
49 15:35:25.441840 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 15:35:25.441976 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 15:35:25.442045 saving as /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/kernel/Image
52 15:35:25.442105 total size: 49220096 (46 MB)
53 15:35:25.442165 No compression specified
54 15:35:25.443265 progress 0 % (0 MB)
55 15:35:25.456394 progress 5 % (2 MB)
56 15:35:25.469274 progress 10 % (4 MB)
57 15:35:25.482164 progress 15 % (7 MB)
58 15:35:25.495113 progress 20 % (9 MB)
59 15:35:25.507988 progress 25 % (11 MB)
60 15:35:25.520831 progress 30 % (14 MB)
61 15:35:25.533857 progress 35 % (16 MB)
62 15:35:25.546624 progress 40 % (18 MB)
63 15:35:25.559568 progress 45 % (21 MB)
64 15:35:25.572750 progress 50 % (23 MB)
65 15:35:25.585522 progress 55 % (25 MB)
66 15:35:25.598406 progress 60 % (28 MB)
67 15:35:25.611283 progress 65 % (30 MB)
68 15:35:25.624177 progress 70 % (32 MB)
69 15:35:25.637091 progress 75 % (35 MB)
70 15:35:25.649857 progress 80 % (37 MB)
71 15:35:25.662624 progress 85 % (39 MB)
72 15:35:25.675705 progress 90 % (42 MB)
73 15:35:25.688387 progress 95 % (44 MB)
74 15:35:25.701106 progress 100 % (46 MB)
75 15:35:25.701264 46 MB downloaded in 0.26 s (181.13 MB/s)
76 15:35:25.701416 end: 1.2.1 http-download (duration 00:00:00) [common]
78 15:35:25.701649 end: 1.2 download-retry (duration 00:00:00) [common]
79 15:35:25.701736 start: 1.3 download-retry (timeout 00:10:00) [common]
80 15:35:25.701825 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 15:35:25.701953 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 15:35:25.702022 saving as /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/dtb/mt8192-asurada-spherion-r0.dtb
83 15:35:25.702082 total size: 47278 (0 MB)
84 15:35:25.702143 No compression specified
85 15:35:25.703225 progress 69 % (0 MB)
86 15:35:25.703541 progress 100 % (0 MB)
87 15:35:25.703698 0 MB downloaded in 0.00 s (27.94 MB/s)
88 15:35:25.703821 end: 1.3.1 http-download (duration 00:00:00) [common]
90 15:35:25.704046 end: 1.3 download-retry (duration 00:00:00) [common]
91 15:35:25.704131 start: 1.4 download-retry (timeout 00:10:00) [common]
92 15:35:25.704214 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 15:35:25.704325 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 15:35:25.704392 saving as /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/nfsrootfs/full.rootfs.tar
95 15:35:25.704452 total size: 125290964 (119 MB)
96 15:35:25.704513 Using unxz to decompress xz
97 15:35:25.708614 progress 0 % (0 MB)
98 15:35:26.041064 progress 5 % (6 MB)
99 15:35:26.375266 progress 10 % (11 MB)
100 15:35:26.710061 progress 15 % (17 MB)
101 15:35:26.906060 progress 20 % (23 MB)
102 15:35:27.086173 progress 25 % (29 MB)
103 15:35:27.449750 progress 30 % (35 MB)
104 15:35:27.825650 progress 35 % (41 MB)
105 15:35:28.231568 progress 40 % (47 MB)
106 15:35:28.620386 progress 45 % (53 MB)
107 15:35:29.022816 progress 50 % (59 MB)
108 15:35:29.393225 progress 55 % (65 MB)
109 15:35:29.764549 progress 60 % (71 MB)
110 15:35:30.109078 progress 65 % (77 MB)
111 15:35:30.490840 progress 70 % (83 MB)
112 15:35:30.878709 progress 75 % (89 MB)
113 15:35:31.301291 progress 80 % (95 MB)
114 15:35:31.719766 progress 85 % (101 MB)
115 15:35:31.965091 progress 90 % (107 MB)
116 15:35:32.306419 progress 95 % (113 MB)
117 15:35:32.680986 progress 100 % (119 MB)
118 15:35:32.686709 119 MB downloaded in 6.98 s (17.11 MB/s)
119 15:35:32.686969 end: 1.4.1 http-download (duration 00:00:07) [common]
121 15:35:32.687239 end: 1.4 download-retry (duration 00:00:07) [common]
122 15:35:32.687331 start: 1.5 download-retry (timeout 00:09:53) [common]
123 15:35:32.687464 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 15:35:32.687625 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 15:35:32.687697 saving as /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/modules/modules.tar
126 15:35:32.687759 total size: 8608784 (8 MB)
127 15:35:32.687824 Using unxz to decompress xz
128 15:35:32.955227 progress 0 % (0 MB)
129 15:35:32.977325 progress 5 % (0 MB)
130 15:35:32.999829 progress 10 % (0 MB)
131 15:35:33.025872 progress 15 % (1 MB)
132 15:35:33.051114 progress 20 % (1 MB)
133 15:35:33.077201 progress 25 % (2 MB)
134 15:35:33.103629 progress 30 % (2 MB)
135 15:35:33.129116 progress 35 % (2 MB)
136 15:35:33.155849 progress 40 % (3 MB)
137 15:35:33.180356 progress 45 % (3 MB)
138 15:35:33.206958 progress 50 % (4 MB)
139 15:35:33.232120 progress 55 % (4 MB)
140 15:35:33.256998 progress 60 % (4 MB)
141 15:35:33.279876 progress 65 % (5 MB)
142 15:35:33.305413 progress 70 % (5 MB)
143 15:35:33.331665 progress 75 % (6 MB)
144 15:35:33.358016 progress 80 % (6 MB)
145 15:35:33.388408 progress 85 % (7 MB)
146 15:35:33.414945 progress 90 % (7 MB)
147 15:35:33.439174 progress 95 % (7 MB)
148 15:35:33.462175 progress 100 % (8 MB)
149 15:35:33.468074 8 MB downloaded in 0.78 s (10.52 MB/s)
150 15:35:33.468429 end: 1.5.1 http-download (duration 00:00:01) [common]
152 15:35:33.468861 end: 1.5 download-retry (duration 00:00:01) [common]
153 15:35:33.469005 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 15:35:33.469159 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 15:35:35.683866 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11331379/extract-nfsrootfs-uhp87pcj
156 15:35:35.684079 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 15:35:35.684183 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 15:35:35.684359 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0
159 15:35:35.684500 makedir: /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin
160 15:35:35.684606 makedir: /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/tests
161 15:35:35.684708 makedir: /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/results
162 15:35:35.684814 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-add-keys
163 15:35:35.684958 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-add-sources
164 15:35:35.685088 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-background-process-start
165 15:35:35.685216 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-background-process-stop
166 15:35:35.685341 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-common-functions
167 15:35:35.685465 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-echo-ipv4
168 15:35:35.685590 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-install-packages
169 15:35:35.685714 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-installed-packages
170 15:35:35.685837 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-os-build
171 15:35:35.685963 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-probe-channel
172 15:35:35.686090 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-probe-ip
173 15:35:35.686214 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-target-ip
174 15:35:35.686337 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-target-mac
175 15:35:35.686458 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-target-storage
176 15:35:35.686584 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-test-case
177 15:35:35.686708 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-test-event
178 15:35:35.686830 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-test-feedback
179 15:35:35.686954 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-test-raise
180 15:35:35.687079 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-test-reference
181 15:35:35.687204 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-test-runner
182 15:35:35.687326 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-test-set
183 15:35:35.687880 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-test-shell
184 15:35:35.688035 Updating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-install-packages (oe)
185 15:35:35.688196 Updating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/bin/lava-installed-packages (oe)
186 15:35:35.688322 Creating /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/environment
187 15:35:35.688425 LAVA metadata
188 15:35:35.688500 - LAVA_JOB_ID=11331379
189 15:35:35.688565 - LAVA_DISPATCHER_IP=192.168.201.1
190 15:35:35.688676 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 15:35:35.688745 skipped lava-vland-overlay
192 15:35:35.688822 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 15:35:35.688903 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 15:35:35.688965 skipped lava-multinode-overlay
195 15:35:35.689037 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 15:35:35.689115 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 15:35:35.689191 Loading test definitions
198 15:35:35.689284 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 15:35:35.689355 Using /lava-11331379 at stage 0
200 15:35:35.689686 uuid=11331379_1.6.2.3.1 testdef=None
201 15:35:35.689777 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 15:35:35.689863 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 15:35:35.690376 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 15:35:35.690598 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 15:35:35.691248 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 15:35:35.691516 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 15:35:35.692209 runner path: /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/0/tests/0_dmesg test_uuid 11331379_1.6.2.3.1
210 15:35:35.692367 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 15:35:35.692592 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 15:35:35.692664 Using /lava-11331379 at stage 1
214 15:35:35.693029 uuid=11331379_1.6.2.3.5 testdef=None
215 15:35:35.693121 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 15:35:35.693223 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 15:35:35.693699 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 15:35:35.693916 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 15:35:35.694603 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 15:35:35.694830 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 15:35:35.695579 runner path: /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/1/tests/1_bootrr test_uuid 11331379_1.6.2.3.5
224 15:35:35.695734 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 15:35:35.695941 Creating lava-test-runner.conf files
227 15:35:35.696003 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/0 for stage 0
228 15:35:35.696094 - 0_dmesg
229 15:35:35.696174 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11331379/lava-overlay-wko94lo0/lava-11331379/1 for stage 1
230 15:35:35.696265 - 1_bootrr
231 15:35:35.696361 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 15:35:35.696448 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 15:35:35.703988 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 15:35:35.704144 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 15:35:35.704238 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 15:35:35.704328 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 15:35:35.704414 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 15:35:35.830552 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 15:35:35.830959 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 15:35:35.831108 extracting modules file /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11331379/extract-nfsrootfs-uhp87pcj
241 15:35:36.068477 extracting modules file /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11331379/extract-overlay-ramdisk-w947li4b/ramdisk
242 15:35:36.304283 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 15:35:36.304489 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 15:35:36.304621 [common] Applying overlay to NFS
245 15:35:36.304728 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11331379/compress-overlay-i57fbbis/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11331379/extract-nfsrootfs-uhp87pcj
246 15:35:36.313370 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 15:35:36.313555 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 15:35:36.313690 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 15:35:36.313811 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 15:35:36.313925 Building ramdisk /var/lib/lava/dispatcher/tmp/11331379/extract-overlay-ramdisk-w947li4b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11331379/extract-overlay-ramdisk-w947li4b/ramdisk
251 15:35:36.642558 >> 119213 blocks
252 15:35:38.583853 rename /var/lib/lava/dispatcher/tmp/11331379/extract-overlay-ramdisk-w947li4b/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/ramdisk/ramdisk.cpio.gz
253 15:35:38.584430 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 15:35:38.584622 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 15:35:38.584777 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 15:35:38.584931 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/kernel/Image'
257 15:35:51.881549 Returned 0 in 13 seconds
258 15:35:51.982196 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/kernel/image.itb
259 15:35:52.348548 output: FIT description: Kernel Image image with one or more FDT blobs
260 15:35:52.348906 output: Created: Tue Aug 22 16:35:52 2023
261 15:35:52.348984 output: Image 0 (kernel-1)
262 15:35:52.349052 output: Description:
263 15:35:52.349120 output: Created: Tue Aug 22 16:35:52 2023
264 15:35:52.349183 output: Type: Kernel Image
265 15:35:52.349244 output: Compression: lzma compressed
266 15:35:52.349305 output: Data Size: 11035343 Bytes = 10776.70 KiB = 10.52 MiB
267 15:35:52.349366 output: Architecture: AArch64
268 15:35:52.349424 output: OS: Linux
269 15:35:52.349481 output: Load Address: 0x00000000
270 15:35:52.349534 output: Entry Point: 0x00000000
271 15:35:52.349587 output: Hash algo: crc32
272 15:35:52.349641 output: Hash value: fe81bcf6
273 15:35:52.349694 output: Image 1 (fdt-1)
274 15:35:52.349746 output: Description: mt8192-asurada-spherion-r0
275 15:35:52.349798 output: Created: Tue Aug 22 16:35:52 2023
276 15:35:52.349851 output: Type: Flat Device Tree
277 15:35:52.349903 output: Compression: uncompressed
278 15:35:52.349955 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 15:35:52.350007 output: Architecture: AArch64
280 15:35:52.350059 output: Hash algo: crc32
281 15:35:52.350111 output: Hash value: cc4352de
282 15:35:52.350162 output: Image 2 (ramdisk-1)
283 15:35:52.350215 output: Description: unavailable
284 15:35:52.350266 output: Created: Tue Aug 22 16:35:52 2023
285 15:35:52.350318 output: Type: RAMDisk Image
286 15:35:52.350370 output: Compression: Unknown Compression
287 15:35:52.350423 output: Data Size: 17770678 Bytes = 17354.18 KiB = 16.95 MiB
288 15:35:52.350475 output: Architecture: AArch64
289 15:35:52.350527 output: OS: Linux
290 15:35:52.350579 output: Load Address: unavailable
291 15:35:52.350631 output: Entry Point: unavailable
292 15:35:52.350683 output: Hash algo: crc32
293 15:35:52.350734 output: Hash value: 81c35d1b
294 15:35:52.350786 output: Default Configuration: 'conf-1'
295 15:35:52.350838 output: Configuration 0 (conf-1)
296 15:35:52.350890 output: Description: mt8192-asurada-spherion-r0
297 15:35:52.350943 output: Kernel: kernel-1
298 15:35:52.350995 output: Init Ramdisk: ramdisk-1
299 15:35:52.351047 output: FDT: fdt-1
300 15:35:52.351099 output: Loadables: kernel-1
301 15:35:52.351151 output:
302 15:35:52.351364 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
303 15:35:52.351516 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
304 15:35:52.351618 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
305 15:35:52.351715 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
306 15:35:52.351798 No LXC device requested
307 15:35:52.351876 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 15:35:52.351964 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
309 15:35:52.352043 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 15:35:52.352113 Checking files for TFTP limit of 4294967296 bytes.
311 15:35:52.352610 end: 1 tftp-deploy (duration 00:00:27) [common]
312 15:35:52.352715 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 15:35:52.352808 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 15:35:52.352934 substitutions:
315 15:35:52.353002 - {DTB}: 11331379/tftp-deploy-3e8hmdz8/dtb/mt8192-asurada-spherion-r0.dtb
316 15:35:52.353067 - {INITRD}: 11331379/tftp-deploy-3e8hmdz8/ramdisk/ramdisk.cpio.gz
317 15:35:52.353126 - {KERNEL}: 11331379/tftp-deploy-3e8hmdz8/kernel/Image
318 15:35:52.353183 - {LAVA_MAC}: None
319 15:35:52.353239 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11331379/extract-nfsrootfs-uhp87pcj
320 15:35:52.353295 - {NFS_SERVER_IP}: 192.168.201.1
321 15:35:52.353349 - {PRESEED_CONFIG}: None
322 15:35:52.353403 - {PRESEED_LOCAL}: None
323 15:35:52.353456 - {RAMDISK}: 11331379/tftp-deploy-3e8hmdz8/ramdisk/ramdisk.cpio.gz
324 15:35:52.353510 - {ROOT_PART}: None
325 15:35:52.353562 - {ROOT}: None
326 15:35:52.353615 - {SERVER_IP}: 192.168.201.1
327 15:35:52.353667 - {TEE}: None
328 15:35:52.353720 Parsed boot commands:
329 15:35:52.353771 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 15:35:52.353953 Parsed boot commands: tftpboot 192.168.201.1 11331379/tftp-deploy-3e8hmdz8/kernel/image.itb 11331379/tftp-deploy-3e8hmdz8/kernel/cmdline
331 15:35:52.354041 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 15:35:52.354128 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 15:35:52.354219 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 15:35:52.354303 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 15:35:52.354376 Not connected, no need to disconnect.
336 15:35:52.354449 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 15:35:52.354529 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 15:35:52.354594 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
339 15:35:52.358678 Setting prompt string to ['lava-test: # ']
340 15:35:52.359046 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 15:35:52.359153 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 15:35:52.359249 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 15:35:52.359341 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 15:35:52.359593 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
345 15:35:57.494605 >> Command sent successfully.
346 15:35:57.497319 Returned 0 in 5 seconds
347 15:35:57.597851 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 15:35:57.598185 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 15:35:57.598290 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 15:35:57.598380 Setting prompt string to 'Starting depthcharge on Spherion...'
352 15:35:57.598479 Changing prompt to 'Starting depthcharge on Spherion...'
353 15:35:57.598548 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 15:35:57.598854 [Enter `^Ec?' for help]
355 15:35:57.769392
356 15:35:57.769558
357 15:35:57.769667 F0: 102B 0000
358 15:35:57.769785
359 15:35:57.769896 F3: 1001 0000 [0200]
360 15:35:57.770004
361 15:35:57.772982 F3: 1001 0000
362 15:35:57.773066
363 15:35:57.773133 F7: 102D 0000
364 15:35:57.773198
365 15:35:57.773260 F1: 0000 0000
366 15:35:57.776850
367 15:35:57.776967 V0: 0000 0000 [0001]
368 15:35:57.777046
369 15:35:57.777112 00: 0007 8000
370 15:35:57.777178
371 15:35:57.780635 01: 0000 0000
372 15:35:57.780719
373 15:35:57.780786 BP: 0C00 0209 [0000]
374 15:35:57.780848
375 15:35:57.784205 G0: 1182 0000
376 15:35:57.784312
377 15:35:57.784407 EC: 0000 0021 [4000]
378 15:35:57.784498
379 15:35:57.787827 S7: 0000 0000 [0000]
380 15:35:57.787909
381 15:35:57.788017 CC: 0000 0000 [0001]
382 15:35:57.788120
383 15:35:57.791572 T0: 0000 0040 [010F]
384 15:35:57.791654
385 15:35:57.791745 Jump to BL
386 15:35:57.791812
387 15:35:57.816081
388 15:35:57.816190
389 15:35:57.816279
390 15:35:57.822986 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 15:35:57.826624 ARM64: Exception handlers installed.
392 15:35:57.830432 ARM64: Testing exception
393 15:35:57.833763 ARM64: Done test exception
394 15:35:57.840714 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 15:35:57.851613 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 15:35:57.858471 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 15:35:57.868671 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 15:35:57.875276 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 15:35:57.881867 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 15:35:57.893165 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 15:35:57.899604 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 15:35:57.919161 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 15:35:57.922200 WDT: Last reset was cold boot
404 15:35:57.925756 SPI1(PAD0) initialized at 2873684 Hz
405 15:35:57.928642 SPI5(PAD0) initialized at 992727 Hz
406 15:35:57.932051 VBOOT: Loading verstage.
407 15:35:57.938584 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 15:35:57.942065 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 15:35:57.945723 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 15:35:57.948815 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 15:35:57.956814 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 15:35:57.963071 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 15:35:57.973737 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 15:35:57.973847
415 15:35:57.973957
416 15:35:57.984157 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 15:35:57.987657 ARM64: Exception handlers installed.
418 15:35:57.990890 ARM64: Testing exception
419 15:35:57.990977 ARM64: Done test exception
420 15:35:57.998702 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 15:35:58.001711 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 15:35:58.015449 Probing TPM: . done!
423 15:35:58.015539 TPM ready after 0 ms
424 15:35:58.021886 Connected to device vid:did:rid of 1ae0:0028:00
425 15:35:58.028655 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 15:35:58.070739 Initialized TPM device CR50 revision 0
427 15:35:58.083016 tlcl_send_startup: Startup return code is 0
428 15:35:58.083116 TPM: setup succeeded
429 15:35:58.094193 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 15:35:58.103155 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 15:35:58.114785 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 15:35:58.124375 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 15:35:58.127533 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 15:35:58.130821 in-header: 03 07 00 00 08 00 00 00
435 15:35:58.134803 in-data: aa e4 47 04 13 02 00 00
436 15:35:58.138235 Chrome EC: UHEPI supported
437 15:35:58.145530 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 15:35:58.149443 in-header: 03 9d 00 00 08 00 00 00
439 15:35:58.153041 in-data: 10 20 20 08 00 00 00 00
440 15:35:58.153121 Phase 1
441 15:35:58.156222 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 15:35:58.163212 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 15:35:58.170292 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 15:35:58.170407 Recovery requested (1009000e)
445 15:35:58.179042 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 15:35:58.184522 tlcl_extend: response is 0
447 15:35:58.192585 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 15:35:58.197999 tlcl_extend: response is 0
449 15:35:58.204905 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 15:35:58.225182 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 15:35:58.232968 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 15:35:58.233071
453 15:35:58.233196
454 15:35:58.240969 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 15:35:58.244524 ARM64: Exception handlers installed.
456 15:35:58.248017 ARM64: Testing exception
457 15:35:58.251237 ARM64: Done test exception
458 15:35:58.268023 pmic_efuse_setting: Set efuses in 11 msecs
459 15:35:58.276529 pmwrap_interface_init: Select PMIF_VLD_RDY
460 15:35:58.280441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 15:35:58.283900 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 15:35:58.288290 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 15:35:58.294733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 15:35:58.298761 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 15:35:58.302385 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 15:35:58.309945 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 15:35:58.313355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 15:35:58.316763 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 15:35:58.323755 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 15:35:58.326775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 15:35:58.333496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 15:35:58.336649 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 15:35:58.343289 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 15:35:58.350014 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 15:35:58.353061 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 15:35:58.360196 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 15:35:58.366832 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 15:35:58.369984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 15:35:58.377747 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 15:35:58.380886 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 15:35:58.387795 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 15:35:58.394718 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 15:35:58.398740 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 15:35:58.405651 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 15:35:58.408893 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 15:35:58.415562 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 15:35:58.419285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 15:35:58.425667 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 15:35:58.430214 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 15:35:58.433390 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 15:35:58.440829 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 15:35:58.444861 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 15:35:58.448494 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 15:35:58.455666 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 15:35:58.459363 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 15:35:58.465767 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 15:35:58.469580 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 15:35:58.472984 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 15:35:58.479071 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 15:35:58.482763 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 15:35:58.486040 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 15:35:58.492355 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 15:35:58.496020 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 15:35:58.499050 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 15:35:58.505983 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 15:35:58.509007 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 15:35:58.512618 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 15:35:58.515839 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 15:35:58.522633 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 15:35:58.526237 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 15:35:58.532617 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 15:35:58.542571 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 15:35:58.545873 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 15:35:58.555632 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 15:35:58.562683 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 15:35:58.569050 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 15:35:58.572877 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 15:35:58.576094 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 15:35:58.583140 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xf
520 15:35:58.590093 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 15:35:58.593407 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 15:35:58.596604 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 15:35:58.607453 [RTC]rtc_get_frequency_meter,154: input=15, output=793
524 15:35:58.610592 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
525 15:35:58.617582 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
526 15:35:58.620941 [RTC]rtc_boot_common,220: irqsta=1, bbpu=81, con=486
527 15:35:58.624010 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
528 15:35:58.627249 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
529 15:35:58.630925 ADC[4]: Raw value=899630 ID=7
530 15:35:58.633957 ADC[3]: Raw value=213070 ID=1
531 15:35:58.637424 RAM Code: 0x71
532 15:35:58.640726 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
533 15:35:58.644121 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
534 15:35:58.654642 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
535 15:35:58.661360 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
536 15:35:58.664572 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
537 15:35:58.667668 in-header: 03 07 00 00 08 00 00 00
538 15:35:58.671342 in-data: aa e4 47 04 13 02 00 00
539 15:35:58.675394 Chrome EC: UHEPI supported
540 15:35:58.678806 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
541 15:35:58.682780 in-header: 03 d5 00 00 08 00 00 00
542 15:35:58.686058 in-data: 98 20 60 08 00 00 00 00
543 15:35:58.689495 MRC: failed to locate region type 0.
544 15:35:58.696915 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
545 15:35:58.699771 DRAM-K: Running full calibration
546 15:35:58.706811 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
547 15:35:58.706900 header.status = 0x0
548 15:35:58.710423 header.version = 0x6 (expected: 0x6)
549 15:35:58.713965 header.size = 0xd00 (expected: 0xd00)
550 15:35:58.717579 header.flags = 0x0
551 15:35:58.724154 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
552 15:35:58.740090 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
553 15:35:58.746355 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
554 15:35:58.749993 dram_init: ddr_geometry: 2
555 15:35:58.753257 [EMI] MDL number = 2
556 15:35:58.753346 [EMI] Get MDL freq = 0
557 15:35:58.756516 dram_init: ddr_type: 0
558 15:35:58.756600 is_discrete_lpddr4: 1
559 15:35:58.760126 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
560 15:35:58.760213
561 15:35:58.760280
562 15:35:58.763087 [Bian_co] ETT version 0.0.0.1
563 15:35:58.769823 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
564 15:35:58.769908
565 15:35:58.772854 dramc_set_vcore_voltage set vcore to 650000
566 15:35:58.776478 Read voltage for 800, 4
567 15:35:58.776559 Vio18 = 0
568 15:35:58.776625 Vcore = 650000
569 15:35:58.779726 Vdram = 0
570 15:35:58.779801 Vddq = 0
571 15:35:58.779864 Vmddr = 0
572 15:35:58.783153 dram_init: config_dvfs: 1
573 15:35:58.786285 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
574 15:35:58.792730 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
575 15:35:58.796114 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
576 15:35:58.799200 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
577 15:35:58.802597 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
578 15:35:58.809315 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
579 15:35:58.809397 MEM_TYPE=3, freq_sel=18
580 15:35:58.812977 sv_algorithm_assistance_LP4_1600
581 15:35:58.816278 ============ PULL DRAM RESETB DOWN ============
582 15:35:58.822586 ========== PULL DRAM RESETB DOWN end =========
583 15:35:58.826060 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
584 15:35:58.829313 ===================================
585 15:35:58.833088 LPDDR4 DRAM CONFIGURATION
586 15:35:58.836113 ===================================
587 15:35:58.836186 EX_ROW_EN[0] = 0x0
588 15:35:58.839610 EX_ROW_EN[1] = 0x0
589 15:35:58.839687 LP4Y_EN = 0x0
590 15:35:58.842821 WORK_FSP = 0x0
591 15:35:58.842890 WL = 0x2
592 15:35:58.846124 RL = 0x2
593 15:35:58.846212 BL = 0x2
594 15:35:58.849316 RPST = 0x0
595 15:35:58.849395 RD_PRE = 0x0
596 15:35:58.852806 WR_PRE = 0x1
597 15:35:58.852877 WR_PST = 0x0
598 15:35:58.855900 DBI_WR = 0x0
599 15:35:58.859719 DBI_RD = 0x0
600 15:35:58.859800 OTF = 0x1
601 15:35:58.863074 ===================================
602 15:35:58.866009 ===================================
603 15:35:58.866092 ANA top config
604 15:35:58.869236 ===================================
605 15:35:58.872981 DLL_ASYNC_EN = 0
606 15:35:58.876326 ALL_SLAVE_EN = 1
607 15:35:58.879332 NEW_RANK_MODE = 1
608 15:35:58.882928 DLL_IDLE_MODE = 1
609 15:35:58.883010 LP45_APHY_COMB_EN = 1
610 15:35:58.885935 TX_ODT_DIS = 1
611 15:35:58.889746 NEW_8X_MODE = 1
612 15:35:58.893285 ===================================
613 15:35:58.895850 ===================================
614 15:35:58.899795 data_rate = 1600
615 15:35:58.902996 CKR = 1
616 15:35:58.903081 DQ_P2S_RATIO = 8
617 15:35:58.906145 ===================================
618 15:35:58.909475 CA_P2S_RATIO = 8
619 15:35:58.912722 DQ_CA_OPEN = 0
620 15:35:58.915983 DQ_SEMI_OPEN = 0
621 15:35:58.919906 CA_SEMI_OPEN = 0
622 15:35:58.919999 CA_FULL_RATE = 0
623 15:35:58.923086 DQ_CKDIV4_EN = 1
624 15:35:58.926101 CA_CKDIV4_EN = 1
625 15:35:58.929954 CA_PREDIV_EN = 0
626 15:35:58.933237 PH8_DLY = 0
627 15:35:58.936354 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
628 15:35:58.936428 DQ_AAMCK_DIV = 4
629 15:35:58.939894 CA_AAMCK_DIV = 4
630 15:35:58.943865 CA_ADMCK_DIV = 4
631 15:35:58.946793 DQ_TRACK_CA_EN = 0
632 15:35:58.951046 CA_PICK = 800
633 15:35:58.951153 CA_MCKIO = 800
634 15:35:58.954654 MCKIO_SEMI = 0
635 15:35:58.958327 PLL_FREQ = 3068
636 15:35:58.961599 DQ_UI_PI_RATIO = 32
637 15:35:58.961672 CA_UI_PI_RATIO = 0
638 15:35:58.965287 ===================================
639 15:35:58.969111 ===================================
640 15:35:58.973062 memory_type:LPDDR4
641 15:35:58.973142 GP_NUM : 10
642 15:35:58.976598 SRAM_EN : 1
643 15:35:58.976674 MD32_EN : 0
644 15:35:58.979906 ===================================
645 15:35:58.983802 [ANA_INIT] >>>>>>>>>>>>>>
646 15:35:58.987444 <<<<<< [CONFIGURE PHASE]: ANA_TX
647 15:35:58.991191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
648 15:35:58.994844 ===================================
649 15:35:58.994921 data_rate = 1600,PCW = 0X7600
650 15:35:58.998771 ===================================
651 15:35:59.002530 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
652 15:35:59.009708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
653 15:35:59.013051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
654 15:35:59.017006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
655 15:35:59.020848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
656 15:35:59.024040 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
657 15:35:59.028541 [ANA_INIT] flow start
658 15:35:59.028614 [ANA_INIT] PLL >>>>>>>>
659 15:35:59.031662 [ANA_INIT] PLL <<<<<<<<
660 15:35:59.035535 [ANA_INIT] MIDPI >>>>>>>>
661 15:35:59.035611 [ANA_INIT] MIDPI <<<<<<<<
662 15:35:59.039135 [ANA_INIT] DLL >>>>>>>>
663 15:35:59.042581 [ANA_INIT] flow end
664 15:35:59.046305 ============ LP4 DIFF to SE enter ============
665 15:35:59.050144 ============ LP4 DIFF to SE exit ============
666 15:35:59.050263 [ANA_INIT] <<<<<<<<<<<<<
667 15:35:59.053857 [Flow] Enable top DCM control >>>>>
668 15:35:59.057344 [Flow] Enable top DCM control <<<<<
669 15:35:59.060908 Enable DLL master slave shuffle
670 15:35:59.067944 ==============================================================
671 15:35:59.068141 Gating Mode config
672 15:35:59.074558 ==============================================================
673 15:35:59.074697 Config description:
674 15:35:59.084858 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
675 15:35:59.091324 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
676 15:35:59.097562 SELPH_MODE 0: By rank 1: By Phase
677 15:35:59.101289 ==============================================================
678 15:35:59.104611 GAT_TRACK_EN = 1
679 15:35:59.107918 RX_GATING_MODE = 2
680 15:35:59.111074 RX_GATING_TRACK_MODE = 2
681 15:35:59.114493 SELPH_MODE = 1
682 15:35:59.117760 PICG_EARLY_EN = 1
683 15:35:59.121034 VALID_LAT_VALUE = 1
684 15:35:59.125017 ==============================================================
685 15:35:59.128279 Enter into Gating configuration >>>>
686 15:35:59.130922 Exit from Gating configuration <<<<
687 15:35:59.134772 Enter into DVFS_PRE_config >>>>>
688 15:35:59.147766 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
689 15:35:59.151172 Exit from DVFS_PRE_config <<<<<
690 15:35:59.154276 Enter into PICG configuration >>>>
691 15:35:59.154381 Exit from PICG configuration <<<<
692 15:35:59.157530 [RX_INPUT] configuration >>>>>
693 15:35:59.160809 [RX_INPUT] configuration <<<<<
694 15:35:59.167815 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
695 15:35:59.170872 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
696 15:35:59.177661 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
697 15:35:59.184430 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
698 15:35:59.191326 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
699 15:35:59.197459 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
700 15:35:59.201237 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
701 15:35:59.204457 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
702 15:35:59.207563 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
703 15:35:59.214396 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
704 15:35:59.217697 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
705 15:35:59.221003 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
706 15:35:59.224132 ===================================
707 15:35:59.227400 LPDDR4 DRAM CONFIGURATION
708 15:35:59.230635 ===================================
709 15:35:59.234042 EX_ROW_EN[0] = 0x0
710 15:35:59.234147 EX_ROW_EN[1] = 0x0
711 15:35:59.238095 LP4Y_EN = 0x0
712 15:35:59.238179 WORK_FSP = 0x0
713 15:35:59.240731 WL = 0x2
714 15:35:59.240816 RL = 0x2
715 15:35:59.244573 BL = 0x2
716 15:35:59.244657 RPST = 0x0
717 15:35:59.247881 RD_PRE = 0x0
718 15:35:59.247965 WR_PRE = 0x1
719 15:35:59.251151 WR_PST = 0x0
720 15:35:59.251235 DBI_WR = 0x0
721 15:35:59.254385 DBI_RD = 0x0
722 15:35:59.254469 OTF = 0x1
723 15:35:59.257676 ===================================
724 15:35:59.260942 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
725 15:35:59.268020 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
726 15:35:59.271178 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 15:35:59.274297 ===================================
728 15:35:59.277709 LPDDR4 DRAM CONFIGURATION
729 15:35:59.281458 ===================================
730 15:35:59.281555 EX_ROW_EN[0] = 0x10
731 15:35:59.284787 EX_ROW_EN[1] = 0x0
732 15:35:59.284877 LP4Y_EN = 0x0
733 15:35:59.287992 WORK_FSP = 0x0
734 15:35:59.288088 WL = 0x2
735 15:35:59.291127 RL = 0x2
736 15:35:59.291212 BL = 0x2
737 15:35:59.294671 RPST = 0x0
738 15:35:59.297603 RD_PRE = 0x0
739 15:35:59.297693 WR_PRE = 0x1
740 15:35:59.301016 WR_PST = 0x0
741 15:35:59.301112 DBI_WR = 0x0
742 15:35:59.304524 DBI_RD = 0x0
743 15:35:59.304659 OTF = 0x1
744 15:35:59.308361 ===================================
745 15:35:59.314248 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
746 15:35:59.318486 nWR fixed to 40
747 15:35:59.321620 [ModeRegInit_LP4] CH0 RK0
748 15:35:59.321748 [ModeRegInit_LP4] CH0 RK1
749 15:35:59.324925 [ModeRegInit_LP4] CH1 RK0
750 15:35:59.328137 [ModeRegInit_LP4] CH1 RK1
751 15:35:59.328229 match AC timing 13
752 15:35:59.334782 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
753 15:35:59.338026 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
754 15:35:59.341558 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
755 15:35:59.348372 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
756 15:35:59.351770 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
757 15:35:59.351855 [EMI DOE] emi_dcm 0
758 15:35:59.358184 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
759 15:35:59.358292 ==
760 15:35:59.361516 Dram Type= 6, Freq= 0, CH_0, rank 0
761 15:35:59.364720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
762 15:35:59.364802 ==
763 15:35:59.371999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
764 15:35:59.377886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
765 15:35:59.385791 [CA 0] Center 38 (7~69) winsize 63
766 15:35:59.388856 [CA 1] Center 37 (7~68) winsize 62
767 15:35:59.392236 [CA 2] Center 35 (5~66) winsize 62
768 15:35:59.395686 [CA 3] Center 35 (5~66) winsize 62
769 15:35:59.398843 [CA 4] Center 34 (4~65) winsize 62
770 15:35:59.401985 [CA 5] Center 34 (3~65) winsize 63
771 15:35:59.402092
772 15:35:59.405583 [CmdBusTrainingLP45] Vref(ca) range 1: 34
773 15:35:59.405670
774 15:35:59.408547 [CATrainingPosCal] consider 1 rank data
775 15:35:59.412241 u2DelayCellTimex100 = 270/100 ps
776 15:35:59.415275 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
777 15:35:59.422093 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
778 15:35:59.426286 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
779 15:35:59.429729 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
780 15:35:59.433303 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
781 15:35:59.436908 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
782 15:35:59.436991
783 15:35:59.440743 CA PerBit enable=1, Macro0, CA PI delay=34
784 15:35:59.440824
785 15:35:59.440898 [CBTSetCACLKResult] CA Dly = 34
786 15:35:59.443955 CS Dly: 6 (0~37)
787 15:35:59.444060 ==
788 15:35:59.447794 Dram Type= 6, Freq= 0, CH_0, rank 1
789 15:35:59.451018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 15:35:59.451137 ==
791 15:35:59.458783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
792 15:35:59.461428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
793 15:35:59.472732 [CA 0] Center 38 (7~69) winsize 63
794 15:35:59.476006 [CA 1] Center 37 (7~68) winsize 62
795 15:35:59.480079 [CA 2] Center 35 (5~66) winsize 62
796 15:35:59.483356 [CA 3] Center 35 (5~66) winsize 62
797 15:35:59.487405 [CA 4] Center 34 (4~65) winsize 62
798 15:35:59.491269 [CA 5] Center 34 (4~65) winsize 62
799 15:35:59.491359
800 15:35:59.494948 [CmdBusTrainingLP45] Vref(ca) range 1: 32
801 15:35:59.495037
802 15:35:59.498092 [CATrainingPosCal] consider 2 rank data
803 15:35:59.498178 u2DelayCellTimex100 = 270/100 ps
804 15:35:59.502017 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
805 15:35:59.505935 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
806 15:35:59.509206 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
807 15:35:59.512747 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
808 15:35:59.517096 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
809 15:35:59.520829 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
810 15:35:59.520946
811 15:35:59.523838 CA PerBit enable=1, Macro0, CA PI delay=34
812 15:35:59.523947
813 15:35:59.527765 [CBTSetCACLKResult] CA Dly = 34
814 15:35:59.531722 CS Dly: 6 (0~37)
815 15:35:59.531826
816 15:35:59.534756 ----->DramcWriteLeveling(PI) begin...
817 15:35:59.534864 ==
818 15:35:59.539151 Dram Type= 6, Freq= 0, CH_0, rank 0
819 15:35:59.542628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
820 15:35:59.542738 ==
821 15:35:59.546724 Write leveling (Byte 0): 31 => 31
822 15:35:59.546830 Write leveling (Byte 1): 30 => 30
823 15:35:59.550510 DramcWriteLeveling(PI) end<-----
824 15:35:59.550619
825 15:35:59.550712 ==
826 15:35:59.554176 Dram Type= 6, Freq= 0, CH_0, rank 0
827 15:35:59.557928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
828 15:35:59.558047 ==
829 15:35:59.561538 [Gating] SW mode calibration
830 15:35:59.568921 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
831 15:35:59.572301 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
832 15:35:59.576593 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
833 15:35:59.583718 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
834 15:35:59.587049 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
835 15:35:59.591141 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
836 15:35:59.594537 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 15:35:59.598280 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 15:35:59.605419 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 15:35:59.608845 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 15:35:59.612875 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 15:35:59.616747 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 15:35:59.620130 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 15:35:59.627498 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 15:35:59.630999 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 15:35:59.634888 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 15:35:59.638209 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 15:35:59.642683 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 15:35:59.649773 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 15:35:59.653367 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 15:35:59.657163 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
851 15:35:59.660819 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
852 15:35:59.664340 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 15:35:59.671377 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 15:35:59.675674 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 15:35:59.678972 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 15:35:59.682831 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 15:35:59.686912 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 15:35:59.693710 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
859 15:35:59.697597 0 9 12 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
860 15:35:59.701344 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
861 15:35:59.704983 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
862 15:35:59.708972 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
863 15:35:59.712818 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
864 15:35:59.719920 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
865 15:35:59.723734 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
866 15:35:59.726920 0 10 8 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
867 15:35:59.730856 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
868 15:35:59.737876 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 15:35:59.741712 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 15:35:59.745696 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 15:35:59.749564 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 15:35:59.752808 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 15:35:59.759139 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 15:35:59.762960 0 11 8 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
875 15:35:59.766025 0 11 12 | B1->B0 | 3232 3f3f | 0 0 | (0 0) (0 0)
876 15:35:59.772504 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
877 15:35:59.775703 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
878 15:35:59.779353 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
879 15:35:59.785681 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
880 15:35:59.789505 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
881 15:35:59.792355 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
882 15:35:59.796113 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
883 15:35:59.802505 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
884 15:35:59.805765 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 15:35:59.809441 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 15:35:59.815772 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 15:35:59.819080 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 15:35:59.822882 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 15:35:59.829147 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 15:35:59.832745 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 15:35:59.835984 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 15:35:59.842895 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 15:35:59.845997 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 15:35:59.849453 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 15:35:59.855802 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 15:35:59.859743 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 15:35:59.862872 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 15:35:59.869796 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
899 15:35:59.872935 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
900 15:35:59.876194 Total UI for P1: 0, mck2ui 16
901 15:35:59.879352 best dqsien dly found for B0: ( 0, 14, 8)
902 15:35:59.882607 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 15:35:59.885819 Total UI for P1: 0, mck2ui 16
904 15:35:59.889379 best dqsien dly found for B1: ( 0, 14, 12)
905 15:35:59.892486 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
906 15:35:59.895902 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
907 15:35:59.896013
908 15:35:59.899347 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
909 15:35:59.902705 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
910 15:35:59.905799 [Gating] SW calibration Done
911 15:35:59.905885 ==
912 15:35:59.909659 Dram Type= 6, Freq= 0, CH_0, rank 0
913 15:35:59.916426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 15:35:59.916551 ==
915 15:35:59.916648 RX Vref Scan: 0
916 15:35:59.916740
917 15:35:59.919613 RX Vref 0 -> 0, step: 1
918 15:35:59.919691
919 15:35:59.922838 RX Delay -130 -> 252, step: 16
920 15:35:59.926108 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
921 15:35:59.929420 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
922 15:35:59.932649 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
923 15:35:59.935772 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
924 15:35:59.942797 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
925 15:35:59.945726 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
926 15:35:59.949504 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
927 15:35:59.952808 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
928 15:35:59.955766 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
929 15:35:59.962375 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
930 15:35:59.966170 iDelay=206, Bit 10, Center 61 (-66 ~ 189) 256
931 15:35:59.969267 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
932 15:35:59.972345 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
933 15:35:59.979137 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
934 15:35:59.982987 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
935 15:35:59.986297 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
936 15:35:59.986371 ==
937 15:35:59.989240 Dram Type= 6, Freq= 0, CH_0, rank 0
938 15:35:59.992459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
939 15:35:59.992534 ==
940 15:35:59.995656 DQS Delay:
941 15:35:59.995725 DQS0 = 0, DQS1 = 0
942 15:35:59.995786 DQM Delay:
943 15:35:59.999432 DQM0 = 77, DQM1 = 68
944 15:35:59.999513 DQ Delay:
945 15:36:00.002806 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
946 15:36:00.006025 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
947 15:36:00.009106 DQ8 =61, DQ9 =53, DQ10 =61, DQ11 =61
948 15:36:00.012693 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
949 15:36:00.012778
950 15:36:00.012844
951 15:36:00.012903 ==
952 15:36:00.015715 Dram Type= 6, Freq= 0, CH_0, rank 0
953 15:36:00.022609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 15:36:00.022691 ==
955 15:36:00.022756
956 15:36:00.022817
957 15:36:00.022876 TX Vref Scan disable
958 15:36:00.025986 == TX Byte 0 ==
959 15:36:00.029312 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
960 15:36:00.032632 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
961 15:36:00.036440 == TX Byte 1 ==
962 15:36:00.039515 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
963 15:36:00.042698 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
964 15:36:00.046422 ==
965 15:36:00.049581 Dram Type= 6, Freq= 0, CH_0, rank 0
966 15:36:00.052691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 15:36:00.052775 ==
968 15:36:00.065165 TX Vref=22, minBit 7, minWin=26, winSum=433
969 15:36:00.068524 TX Vref=24, minBit 14, minWin=26, winSum=441
970 15:36:00.071776 TX Vref=26, minBit 7, minWin=27, winSum=444
971 15:36:00.075539 TX Vref=28, minBit 5, minWin=27, winSum=444
972 15:36:00.078458 TX Vref=30, minBit 4, minWin=27, winSum=440
973 15:36:00.081713 TX Vref=32, minBit 2, minWin=27, winSum=440
974 15:36:00.088681 [TxChooseVref] Worse bit 7, Min win 27, Win sum 444, Final Vref 26
975 15:36:00.088774
976 15:36:00.091648 Final TX Range 1 Vref 26
977 15:36:00.091756
978 15:36:00.091857 ==
979 15:36:00.094929 Dram Type= 6, Freq= 0, CH_0, rank 0
980 15:36:00.098884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 15:36:00.098966 ==
982 15:36:00.099036
983 15:36:00.102073
984 15:36:00.102154 TX Vref Scan disable
985 15:36:00.105336 == TX Byte 0 ==
986 15:36:00.108554 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
987 15:36:00.111815 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
988 15:36:00.114995 == TX Byte 1 ==
989 15:36:00.118276 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
990 15:36:00.121582 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
991 15:36:00.125139
992 15:36:00.125221 [DATLAT]
993 15:36:00.125295 Freq=800, CH0 RK0
994 15:36:00.125398
995 15:36:00.128297 DATLAT Default: 0xa
996 15:36:00.128382 0, 0xFFFF, sum = 0
997 15:36:00.132191 1, 0xFFFF, sum = 0
998 15:36:00.132274 2, 0xFFFF, sum = 0
999 15:36:00.135018 3, 0xFFFF, sum = 0
1000 15:36:00.135102 4, 0xFFFF, sum = 0
1001 15:36:00.138716 5, 0xFFFF, sum = 0
1002 15:36:00.141671 6, 0xFFFF, sum = 0
1003 15:36:00.141755 7, 0xFFFF, sum = 0
1004 15:36:00.145339 8, 0xFFFF, sum = 0
1005 15:36:00.145422 9, 0x0, sum = 1
1006 15:36:00.145489 10, 0x0, sum = 2
1007 15:36:00.148739 11, 0x0, sum = 3
1008 15:36:00.148826 12, 0x0, sum = 4
1009 15:36:00.151985 best_step = 10
1010 15:36:00.152072
1011 15:36:00.152138 ==
1012 15:36:00.155210 Dram Type= 6, Freq= 0, CH_0, rank 0
1013 15:36:00.158983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1014 15:36:00.159089 ==
1015 15:36:00.161573 RX Vref Scan: 1
1016 15:36:00.161651
1017 15:36:00.161713 Set Vref Range= 32 -> 127
1018 15:36:00.161776
1019 15:36:00.165292 RX Vref 32 -> 127, step: 1
1020 15:36:00.165380
1021 15:36:00.168347 RX Delay -111 -> 252, step: 8
1022 15:36:00.168422
1023 15:36:00.171660 Set Vref, RX VrefLevel [Byte0]: 32
1024 15:36:00.175547 [Byte1]: 32
1025 15:36:00.175625
1026 15:36:00.178748 Set Vref, RX VrefLevel [Byte0]: 33
1027 15:36:00.181977 [Byte1]: 33
1028 15:36:00.185656
1029 15:36:00.185728 Set Vref, RX VrefLevel [Byte0]: 34
1030 15:36:00.189111 [Byte1]: 34
1031 15:36:00.193565
1032 15:36:00.193640 Set Vref, RX VrefLevel [Byte0]: 35
1033 15:36:00.196695 [Byte1]: 35
1034 15:36:00.201241
1035 15:36:00.201321 Set Vref, RX VrefLevel [Byte0]: 36
1036 15:36:00.204407 [Byte1]: 36
1037 15:36:00.208388
1038 15:36:00.208468 Set Vref, RX VrefLevel [Byte0]: 37
1039 15:36:00.212152 [Byte1]: 37
1040 15:36:00.215997
1041 15:36:00.216078 Set Vref, RX VrefLevel [Byte0]: 38
1042 15:36:00.219778 [Byte1]: 38
1043 15:36:00.223663
1044 15:36:00.223744 Set Vref, RX VrefLevel [Byte0]: 39
1045 15:36:00.226784 [Byte1]: 39
1046 15:36:00.231478
1047 15:36:00.231562 Set Vref, RX VrefLevel [Byte0]: 40
1048 15:36:00.234904 [Byte1]: 40
1049 15:36:00.238924
1050 15:36:00.238998 Set Vref, RX VrefLevel [Byte0]: 41
1051 15:36:00.242834 [Byte1]: 41
1052 15:36:00.246994
1053 15:36:00.247066 Set Vref, RX VrefLevel [Byte0]: 42
1054 15:36:00.250125 [Byte1]: 42
1055 15:36:00.254281
1056 15:36:00.254389 Set Vref, RX VrefLevel [Byte0]: 43
1057 15:36:00.257767 [Byte1]: 43
1058 15:36:00.262441
1059 15:36:00.262520 Set Vref, RX VrefLevel [Byte0]: 44
1060 15:36:00.265285 [Byte1]: 44
1061 15:36:00.269707
1062 15:36:00.269792 Set Vref, RX VrefLevel [Byte0]: 45
1063 15:36:00.273073 [Byte1]: 45
1064 15:36:00.278214
1065 15:36:00.278294 Set Vref, RX VrefLevel [Byte0]: 46
1066 15:36:00.281369 [Byte1]: 46
1067 15:36:00.285701
1068 15:36:00.285776 Set Vref, RX VrefLevel [Byte0]: 47
1069 15:36:00.288809 [Byte1]: 47
1070 15:36:00.292691
1071 15:36:00.292763 Set Vref, RX VrefLevel [Byte0]: 48
1072 15:36:00.296284 [Byte1]: 48
1073 15:36:00.300277
1074 15:36:00.300350 Set Vref, RX VrefLevel [Byte0]: 49
1075 15:36:00.304089 [Byte1]: 49
1076 15:36:00.308022
1077 15:36:00.308095 Set Vref, RX VrefLevel [Byte0]: 50
1078 15:36:00.311798 [Byte1]: 50
1079 15:36:00.315519
1080 15:36:00.315589 Set Vref, RX VrefLevel [Byte0]: 51
1081 15:36:00.318828 [Byte1]: 51
1082 15:36:00.323316
1083 15:36:00.323453 Set Vref, RX VrefLevel [Byte0]: 52
1084 15:36:00.326550 [Byte1]: 52
1085 15:36:00.330867
1086 15:36:00.330956 Set Vref, RX VrefLevel [Byte0]: 53
1087 15:36:00.334195 [Byte1]: 53
1088 15:36:00.338597
1089 15:36:00.338702 Set Vref, RX VrefLevel [Byte0]: 54
1090 15:36:00.341850 [Byte1]: 54
1091 15:36:00.346161
1092 15:36:00.346258 Set Vref, RX VrefLevel [Byte0]: 55
1093 15:36:00.349480 [Byte1]: 55
1094 15:36:00.354040
1095 15:36:00.354163 Set Vref, RX VrefLevel [Byte0]: 56
1096 15:36:00.357202 [Byte1]: 56
1097 15:36:00.361730
1098 15:36:00.361871 Set Vref, RX VrefLevel [Byte0]: 57
1099 15:36:00.364745 [Byte1]: 57
1100 15:36:00.369146
1101 15:36:00.369336 Set Vref, RX VrefLevel [Byte0]: 58
1102 15:36:00.372382 [Byte1]: 58
1103 15:36:00.377473
1104 15:36:00.377790 Set Vref, RX VrefLevel [Byte0]: 59
1105 15:36:00.380447 [Byte1]: 59
1106 15:36:00.384778
1107 15:36:00.385165 Set Vref, RX VrefLevel [Byte0]: 60
1108 15:36:00.388068 [Byte1]: 60
1109 15:36:00.392590
1110 15:36:00.393008 Set Vref, RX VrefLevel [Byte0]: 61
1111 15:36:00.395813 [Byte1]: 61
1112 15:36:00.400222
1113 15:36:00.400636 Set Vref, RX VrefLevel [Byte0]: 62
1114 15:36:00.403227 [Byte1]: 62
1115 15:36:00.407517
1116 15:36:00.407933 Set Vref, RX VrefLevel [Byte0]: 63
1117 15:36:00.411449 [Byte1]: 63
1118 15:36:00.415402
1119 15:36:00.415849 Set Vref, RX VrefLevel [Byte0]: 64
1120 15:36:00.418453 [Byte1]: 64
1121 15:36:00.422959
1122 15:36:00.423403 Set Vref, RX VrefLevel [Byte0]: 65
1123 15:36:00.426216 [Byte1]: 65
1124 15:36:00.430802
1125 15:36:00.431268 Set Vref, RX VrefLevel [Byte0]: 66
1126 15:36:00.433948 [Byte1]: 66
1127 15:36:00.438502
1128 15:36:00.438947 Set Vref, RX VrefLevel [Byte0]: 67
1129 15:36:00.441516 [Byte1]: 67
1130 15:36:00.446025
1131 15:36:00.446439 Set Vref, RX VrefLevel [Byte0]: 68
1132 15:36:00.449121 [Byte1]: 68
1133 15:36:00.453666
1134 15:36:00.454080 Set Vref, RX VrefLevel [Byte0]: 69
1135 15:36:00.457001 [Byte1]: 69
1136 15:36:00.461299
1137 15:36:00.461923 Set Vref, RX VrefLevel [Byte0]: 70
1138 15:36:00.464708 [Byte1]: 70
1139 15:36:00.469142
1140 15:36:00.469722 Set Vref, RX VrefLevel [Byte0]: 71
1141 15:36:00.472145 [Byte1]: 71
1142 15:36:00.476399
1143 15:36:00.476986 Set Vref, RX VrefLevel [Byte0]: 72
1144 15:36:00.480241 [Byte1]: 72
1145 15:36:00.483898
1146 15:36:00.484348 Set Vref, RX VrefLevel [Byte0]: 73
1147 15:36:00.487784 [Byte1]: 73
1148 15:36:00.491628
1149 15:36:00.492077 Set Vref, RX VrefLevel [Byte0]: 74
1150 15:36:00.495482 [Byte1]: 74
1151 15:36:00.499141
1152 15:36:00.499620 Set Vref, RX VrefLevel [Byte0]: 75
1153 15:36:00.502781 [Byte1]: 75
1154 15:36:00.507076
1155 15:36:00.507642 Set Vref, RX VrefLevel [Byte0]: 76
1156 15:36:00.510388 [Byte1]: 76
1157 15:36:00.514405
1158 15:36:00.514869 Set Vref, RX VrefLevel [Byte0]: 77
1159 15:36:00.517750 [Byte1]: 77
1160 15:36:00.522663
1161 15:36:00.523116 Set Vref, RX VrefLevel [Byte0]: 78
1162 15:36:00.525741 [Byte1]: 78
1163 15:36:00.529893
1164 15:36:00.530323 Set Vref, RX VrefLevel [Byte0]: 79
1165 15:36:00.533598 [Byte1]: 79
1166 15:36:00.537376
1167 15:36:00.537784 Set Vref, RX VrefLevel [Byte0]: 80
1168 15:36:00.541437 [Byte1]: 80
1169 15:36:00.545243
1170 15:36:00.545706 Final RX Vref Byte 0 = 62 to rank0
1171 15:36:00.548832 Final RX Vref Byte 1 = 59 to rank0
1172 15:36:00.552117 Final RX Vref Byte 0 = 62 to rank1
1173 15:36:00.555358 Final RX Vref Byte 1 = 59 to rank1==
1174 15:36:00.558509 Dram Type= 6, Freq= 0, CH_0, rank 0
1175 15:36:00.565314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 15:36:00.565736 ==
1177 15:36:00.566070 DQS Delay:
1178 15:36:00.566377 DQS0 = 0, DQS1 = 0
1179 15:36:00.568404 DQM Delay:
1180 15:36:00.568818 DQM0 = 82, DQM1 = 68
1181 15:36:00.572127 DQ Delay:
1182 15:36:00.575281 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1183 15:36:00.575730 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1184 15:36:00.578461 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1185 15:36:00.581725 DQ12 =72, DQ13 =76, DQ14 =76, DQ15 =76
1186 15:36:00.585093
1187 15:36:00.585791
1188 15:36:00.591742 [DQSOSCAuto] RK0, (LSB)MR18= 0x2524, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1189 15:36:00.595626 CH0 RK0: MR19=606, MR18=2524
1190 15:36:00.602025 CH0_RK0: MR19=0x606, MR18=0x2524, DQSOSC=400, MR23=63, INC=92, DEC=61
1191 15:36:00.602441
1192 15:36:00.605248 ----->DramcWriteLeveling(PI) begin...
1193 15:36:00.605668 ==
1194 15:36:00.608660 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 15:36:00.611881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 15:36:00.612329 ==
1197 15:36:00.615123 Write leveling (Byte 0): 32 => 32
1198 15:36:00.618833 Write leveling (Byte 1): 29 => 29
1199 15:36:00.621782 DramcWriteLeveling(PI) end<-----
1200 15:36:00.622242
1201 15:36:00.622641 ==
1202 15:36:00.625235 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 15:36:00.628330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 15:36:00.628762 ==
1205 15:36:00.631895 [Gating] SW mode calibration
1206 15:36:00.638380 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1207 15:36:00.645008 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1208 15:36:00.648391 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1209 15:36:00.651948 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1210 15:36:00.658209 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1211 15:36:00.661688 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 15:36:00.665340 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 15:36:00.671475 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 15:36:00.675440 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 15:36:00.678552 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 15:36:00.684882 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 15:36:00.688261 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 15:36:00.692202 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 15:36:00.739165 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 15:36:00.739688 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 15:36:00.740404 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 15:36:00.740753 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 15:36:00.741155 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 15:36:00.741467 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 15:36:00.741852 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1226 15:36:00.742151 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1227 15:36:00.742510 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 15:36:00.742935 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 15:36:00.783015 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 15:36:00.783646 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 15:36:00.784026 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 15:36:00.784403 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 15:36:00.785056 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 15:36:00.785385 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1235 15:36:00.785683 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 15:36:00.785976 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 15:36:00.786262 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 15:36:00.786545 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 15:36:00.786825 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 15:36:00.798983 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 15:36:00.799943 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1242 15:36:00.802763 0 10 8 | B1->B0 | 2f2f 2626 | 1 1 | (1 1) (1 0)
1243 15:36:00.805780 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1244 15:36:00.806300 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 15:36:00.812369 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 15:36:00.816188 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 15:36:00.819461 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 15:36:00.825994 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 15:36:00.829235 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1250 15:36:00.832417 0 11 8 | B1->B0 | 2e2e 3b3b | 1 0 | (1 1) (0 0)
1251 15:36:00.839350 0 11 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
1252 15:36:00.842488 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 15:36:00.845757 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 15:36:00.852630 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 15:36:00.856390 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 15:36:00.860384 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 15:36:00.864457 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1258 15:36:00.867974 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1259 15:36:00.871970 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1260 15:36:00.878319 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 15:36:00.881966 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 15:36:00.885716 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 15:36:00.888967 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 15:36:00.895493 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 15:36:00.898629 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 15:36:00.902378 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 15:36:00.908995 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 15:36:00.912003 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 15:36:00.915626 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 15:36:00.922148 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 15:36:00.925484 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 15:36:00.928815 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 15:36:00.935737 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 15:36:00.939086 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1275 15:36:00.942319 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 15:36:00.945419 Total UI for P1: 0, mck2ui 16
1277 15:36:00.949357 best dqsien dly found for B0: ( 0, 14, 8)
1278 15:36:00.952433 Total UI for P1: 0, mck2ui 16
1279 15:36:00.955459 best dqsien dly found for B1: ( 0, 14, 8)
1280 15:36:00.958827 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1281 15:36:00.962258 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1282 15:36:00.962773
1283 15:36:00.965331 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1284 15:36:00.972296 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1285 15:36:00.972906 [Gating] SW calibration Done
1286 15:36:00.973475 ==
1287 15:36:00.975517 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 15:36:00.982586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 15:36:00.983019 ==
1290 15:36:00.983352 RX Vref Scan: 0
1291 15:36:00.983722
1292 15:36:00.985765 RX Vref 0 -> 0, step: 1
1293 15:36:00.986391
1294 15:36:00.988864 RX Delay -130 -> 252, step: 16
1295 15:36:00.993659 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1296 15:36:00.995914 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1297 15:36:00.999131 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1298 15:36:01.005766 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1299 15:36:01.008596 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1300 15:36:01.011941 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1301 15:36:01.015280 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1302 15:36:01.019199 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1303 15:36:01.021882 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1304 15:36:01.028538 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1305 15:36:01.032138 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1306 15:36:01.035485 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1307 15:36:01.038478 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1308 15:36:01.045482 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1309 15:36:01.048689 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1310 15:36:01.051979 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1311 15:36:01.052560 ==
1312 15:36:01.055169 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 15:36:01.058854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 15:36:01.059475 ==
1315 15:36:01.062085 DQS Delay:
1316 15:36:01.062623 DQS0 = 0, DQS1 = 0
1317 15:36:01.065277 DQM Delay:
1318 15:36:01.065858 DQM0 = 78, DQM1 = 69
1319 15:36:01.066362 DQ Delay:
1320 15:36:01.068513 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1321 15:36:01.071853 DQ4 =77, DQ5 =61, DQ6 =93, DQ7 =93
1322 15:36:01.075058 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1323 15:36:01.078961 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1324 15:36:01.079559
1325 15:36:01.079954
1326 15:36:01.081990 ==
1327 15:36:01.082564 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 15:36:01.088321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 15:36:01.088806 ==
1330 15:36:01.089302
1331 15:36:01.089771
1332 15:36:01.092344 TX Vref Scan disable
1333 15:36:01.092797 == TX Byte 0 ==
1334 15:36:01.095346 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1335 15:36:01.101713 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1336 15:36:01.102180 == TX Byte 1 ==
1337 15:36:01.104821 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1338 15:36:01.112068 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1339 15:36:01.112545 ==
1340 15:36:01.115027 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 15:36:01.117950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 15:36:01.118434 ==
1343 15:36:01.131817 TX Vref=22, minBit 11, minWin=26, winSum=434
1344 15:36:01.135348 TX Vref=24, minBit 0, minWin=27, winSum=437
1345 15:36:01.138434 TX Vref=26, minBit 0, minWin=27, winSum=442
1346 15:36:01.141616 TX Vref=28, minBit 1, minWin=27, winSum=445
1347 15:36:01.144885 TX Vref=30, minBit 2, minWin=27, winSum=445
1348 15:36:01.148777 TX Vref=32, minBit 2, minWin=27, winSum=442
1349 15:36:01.155042 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 28
1350 15:36:01.155681
1351 15:36:01.158771 Final TX Range 1 Vref 28
1352 15:36:01.159185
1353 15:36:01.159551 ==
1354 15:36:01.161856 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 15:36:01.164858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 15:36:01.165153 ==
1357 15:36:01.165386
1358 15:36:01.165601
1359 15:36:01.168726 TX Vref Scan disable
1360 15:36:01.171689 == TX Byte 0 ==
1361 15:36:01.175149 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1362 15:36:01.178183 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1363 15:36:01.181821 == TX Byte 1 ==
1364 15:36:01.185120 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1365 15:36:01.188130 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1366 15:36:01.191936
1367 15:36:01.192245 [DATLAT]
1368 15:36:01.192483 Freq=800, CH0 RK1
1369 15:36:01.192708
1370 15:36:01.195089 DATLAT Default: 0xa
1371 15:36:01.195414 0, 0xFFFF, sum = 0
1372 15:36:01.198217 1, 0xFFFF, sum = 0
1373 15:36:01.198522 2, 0xFFFF, sum = 0
1374 15:36:01.201577 3, 0xFFFF, sum = 0
1375 15:36:01.201879 4, 0xFFFF, sum = 0
1376 15:36:01.204901 5, 0xFFFF, sum = 0
1377 15:36:01.205203 6, 0xFFFF, sum = 0
1378 15:36:01.208504 7, 0xFFFF, sum = 0
1379 15:36:01.211735 8, 0xFFFF, sum = 0
1380 15:36:01.212039 9, 0x0, sum = 1
1381 15:36:01.212281 10, 0x0, sum = 2
1382 15:36:01.215061 11, 0x0, sum = 3
1383 15:36:01.215429 12, 0x0, sum = 4
1384 15:36:01.218073 best_step = 10
1385 15:36:01.218372
1386 15:36:01.218611 ==
1387 15:36:01.221524 Dram Type= 6, Freq= 0, CH_0, rank 1
1388 15:36:01.225322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 15:36:01.225627 ==
1390 15:36:01.228431 RX Vref Scan: 0
1391 15:36:01.228727
1392 15:36:01.228962 RX Vref 0 -> 0, step: 1
1393 15:36:01.229186
1394 15:36:01.231445 RX Delay -111 -> 252, step: 8
1395 15:36:01.238351 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1396 15:36:01.241703 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1397 15:36:01.245123 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1398 15:36:01.247952 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1399 15:36:01.251287 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1400 15:36:01.258116 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1401 15:36:01.261570 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1402 15:36:01.264955 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1403 15:36:01.268233 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1404 15:36:01.271291 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1405 15:36:01.278363 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1406 15:36:01.281538 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1407 15:36:01.284588 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1408 15:36:01.288002 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1409 15:36:01.291715 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1410 15:36:01.298215 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1411 15:36:01.298298 ==
1412 15:36:01.301599 Dram Type= 6, Freq= 0, CH_0, rank 1
1413 15:36:01.305024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 15:36:01.305106 ==
1415 15:36:01.305171 DQS Delay:
1416 15:36:01.308214 DQS0 = 0, DQS1 = 0
1417 15:36:01.308324 DQM Delay:
1418 15:36:01.311484 DQM0 = 78, DQM1 = 70
1419 15:36:01.311565 DQ Delay:
1420 15:36:01.314757 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1421 15:36:01.317935 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1422 15:36:01.321321 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1423 15:36:01.324508 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =80
1424 15:36:01.324590
1425 15:36:01.324654
1426 15:36:01.334995 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a24, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1427 15:36:01.335108 CH0 RK1: MR19=606, MR18=4A24
1428 15:36:01.341314 CH0_RK1: MR19=0x606, MR18=0x4A24, DQSOSC=391, MR23=63, INC=96, DEC=64
1429 15:36:01.344383 [RxdqsGatingPostProcess] freq 800
1430 15:36:01.351361 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1431 15:36:01.354680 Pre-setting of DQS Precalculation
1432 15:36:01.358133 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1433 15:36:01.358219 ==
1434 15:36:01.361596 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 15:36:01.364836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 15:36:01.364927 ==
1437 15:36:01.371294 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1438 15:36:01.377982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1439 15:36:01.386341 [CA 0] Center 36 (6~67) winsize 62
1440 15:36:01.390103 [CA 1] Center 36 (6~67) winsize 62
1441 15:36:01.393271 [CA 2] Center 34 (5~64) winsize 60
1442 15:36:01.396555 [CA 3] Center 34 (4~64) winsize 61
1443 15:36:01.399538 [CA 4] Center 34 (4~64) winsize 61
1444 15:36:01.402946 [CA 5] Center 34 (4~64) winsize 61
1445 15:36:01.403067
1446 15:36:01.406871 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1447 15:36:01.406977
1448 15:36:01.410075 [CATrainingPosCal] consider 1 rank data
1449 15:36:01.413255 u2DelayCellTimex100 = 270/100 ps
1450 15:36:01.416609 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1451 15:36:01.419829 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1452 15:36:01.426302 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1453 15:36:01.430149 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1454 15:36:01.433379 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1455 15:36:01.436498 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1456 15:36:01.436601
1457 15:36:01.439856 CA PerBit enable=1, Macro0, CA PI delay=34
1458 15:36:01.439962
1459 15:36:01.443009 [CBTSetCACLKResult] CA Dly = 34
1460 15:36:01.443110 CS Dly: 5 (0~36)
1461 15:36:01.443202 ==
1462 15:36:01.446330 Dram Type= 6, Freq= 0, CH_1, rank 1
1463 15:36:01.453319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1464 15:36:01.453431 ==
1465 15:36:01.456555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1466 15:36:01.463154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1467 15:36:01.472583 [CA 0] Center 37 (7~67) winsize 61
1468 15:36:01.475675 [CA 1] Center 36 (6~67) winsize 62
1469 15:36:01.479558 [CA 2] Center 34 (4~65) winsize 62
1470 15:36:01.482822 [CA 3] Center 33 (3~64) winsize 62
1471 15:36:01.485760 [CA 4] Center 34 (4~64) winsize 61
1472 15:36:01.489063 [CA 5] Center 33 (3~64) winsize 62
1473 15:36:01.489151
1474 15:36:01.492719 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1475 15:36:01.492810
1476 15:36:01.495877 [CATrainingPosCal] consider 2 rank data
1477 15:36:01.499170 u2DelayCellTimex100 = 270/100 ps
1478 15:36:01.502753 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1479 15:36:01.506088 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1480 15:36:01.512902 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1481 15:36:01.513014 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1482 15:36:01.517176 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1483 15:36:01.524172 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1484 15:36:01.524286
1485 15:36:01.527404 CA PerBit enable=1, Macro0, CA PI delay=34
1486 15:36:01.527492
1487 15:36:01.530630 [CBTSetCACLKResult] CA Dly = 34
1488 15:36:01.530743 CS Dly: 5 (0~37)
1489 15:36:01.530843
1490 15:36:01.534462 ----->DramcWriteLeveling(PI) begin...
1491 15:36:01.534576 ==
1492 15:36:01.537781 Dram Type= 6, Freq= 0, CH_1, rank 0
1493 15:36:01.541580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1494 15:36:01.541667 ==
1495 15:36:01.545540 Write leveling (Byte 0): 28 => 28
1496 15:36:01.548607 Write leveling (Byte 1): 29 => 29
1497 15:36:01.551863 DramcWriteLeveling(PI) end<-----
1498 15:36:01.551947
1499 15:36:01.552014 ==
1500 15:36:01.555821 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 15:36:01.559082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 15:36:01.559167 ==
1503 15:36:01.562291 [Gating] SW mode calibration
1504 15:36:01.568792 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1505 15:36:01.575674 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1506 15:36:01.578495 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1507 15:36:01.581958 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1508 15:36:01.588963 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 15:36:01.592045 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 15:36:01.595330 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 15:36:01.601797 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 15:36:01.605749 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 15:36:01.608955 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 15:36:01.612152 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 15:36:01.618522 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 15:36:01.622111 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 15:36:01.625584 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 15:36:01.631826 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 15:36:01.635419 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 15:36:01.638693 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 15:36:01.645251 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 15:36:01.648500 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 15:36:01.651674 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1524 15:36:01.658543 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1525 15:36:01.661684 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 15:36:01.665083 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 15:36:01.671670 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 15:36:01.675360 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 15:36:01.678675 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 15:36:01.685150 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 15:36:01.688748 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 15:36:01.691541 0 9 8 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
1533 15:36:01.698942 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 15:36:01.701999 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 15:36:01.705332 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 15:36:01.711643 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 15:36:01.714875 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 15:36:01.718616 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 15:36:01.722005 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1540 15:36:01.728775 0 10 8 | B1->B0 | 2f2f 2b2b | 0 0 | (1 1) (1 0)
1541 15:36:01.731676 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 15:36:01.735194 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 15:36:01.741763 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 15:36:01.745223 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 15:36:01.748362 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 15:36:01.755687 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 15:36:01.758638 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1548 15:36:01.761821 0 11 8 | B1->B0 | 3333 3231 | 0 1 | (1 1) (0 0)
1549 15:36:01.768386 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 15:36:01.771530 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 15:36:01.775344 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 15:36:01.781745 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 15:36:01.784889 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 15:36:01.788101 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 15:36:01.795003 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1556 15:36:01.798714 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1557 15:36:01.801668 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 15:36:01.808782 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 15:36:01.811791 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 15:36:01.814967 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 15:36:01.821567 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 15:36:01.824691 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 15:36:01.828398 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 15:36:01.834878 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 15:36:01.838028 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 15:36:01.841783 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 15:36:01.845000 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 15:36:01.851579 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 15:36:01.854509 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 15:36:01.858013 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 15:36:01.864799 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1572 15:36:01.868093 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1573 15:36:01.871403 Total UI for P1: 0, mck2ui 16
1574 15:36:01.874659 best dqsien dly found for B0: ( 0, 14, 4)
1575 15:36:01.878002 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 15:36:01.881179 Total UI for P1: 0, mck2ui 16
1577 15:36:01.884490 best dqsien dly found for B1: ( 0, 14, 8)
1578 15:36:01.887823 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1579 15:36:01.890968 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1580 15:36:01.894836
1581 15:36:01.897993 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1582 15:36:01.901163 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1583 15:36:01.904325 [Gating] SW calibration Done
1584 15:36:01.904432 ==
1585 15:36:01.907469 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 15:36:01.910935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 15:36:01.911059 ==
1588 15:36:01.911166 RX Vref Scan: 0
1589 15:36:01.911257
1590 15:36:01.914322 RX Vref 0 -> 0, step: 1
1591 15:36:01.914426
1592 15:36:01.917578 RX Delay -130 -> 252, step: 16
1593 15:36:01.920809 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1594 15:36:01.923934 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1595 15:36:01.931138 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1596 15:36:01.934471 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1597 15:36:01.937637 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1598 15:36:01.940843 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1599 15:36:01.944017 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1600 15:36:01.950774 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1601 15:36:01.953918 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1602 15:36:01.957680 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1603 15:36:01.961112 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1604 15:36:01.964122 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1605 15:36:01.970855 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1606 15:36:01.974443 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1607 15:36:01.977625 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1608 15:36:01.981156 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1609 15:36:01.981271 ==
1610 15:36:01.984351 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 15:36:01.990945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 15:36:01.991048 ==
1613 15:36:01.991142 DQS Delay:
1614 15:36:01.991231 DQS0 = 0, DQS1 = 0
1615 15:36:01.994175 DQM Delay:
1616 15:36:01.994273 DQM0 = 82, DQM1 = 74
1617 15:36:01.997807 DQ Delay:
1618 15:36:01.997906 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1619 15:36:02.001150 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1620 15:36:02.004481 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1621 15:36:02.007613 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1622 15:36:02.010959
1623 15:36:02.011056
1624 15:36:02.011185 ==
1625 15:36:02.014151 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 15:36:02.017995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 15:36:02.018108 ==
1628 15:36:02.018202
1629 15:36:02.018309
1630 15:36:02.021200 TX Vref Scan disable
1631 15:36:02.021310 == TX Byte 0 ==
1632 15:36:02.027869 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1633 15:36:02.031160 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1634 15:36:02.031300 == TX Byte 1 ==
1635 15:36:02.037391 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1636 15:36:02.041306 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1637 15:36:02.041409 ==
1638 15:36:02.044362 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 15:36:02.047499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 15:36:02.047573 ==
1641 15:36:02.061316 TX Vref=22, minBit 0, minWin=27, winSum=439
1642 15:36:02.064707 TX Vref=24, minBit 0, minWin=27, winSum=440
1643 15:36:02.067949 TX Vref=26, minBit 1, minWin=26, winSum=443
1644 15:36:02.071076 TX Vref=28, minBit 4, minWin=27, winSum=448
1645 15:36:02.074391 TX Vref=30, minBit 5, minWin=27, winSum=448
1646 15:36:02.077604 TX Vref=32, minBit 0, minWin=27, winSum=445
1647 15:36:02.084390 [TxChooseVref] Worse bit 4, Min win 27, Win sum 448, Final Vref 28
1648 15:36:02.084500
1649 15:36:02.087486 Final TX Range 1 Vref 28
1650 15:36:02.087585
1651 15:36:02.087685 ==
1652 15:36:02.091690 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 15:36:02.094935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 15:36:02.095039 ==
1655 15:36:02.095143
1656 15:36:02.095231
1657 15:36:02.098543 TX Vref Scan disable
1658 15:36:02.101535 == TX Byte 0 ==
1659 15:36:02.104729 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1660 15:36:02.108672 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1661 15:36:02.111801 == TX Byte 1 ==
1662 15:36:02.115245 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1663 15:36:02.118541 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1664 15:36:02.118654
1665 15:36:02.121863 [DATLAT]
1666 15:36:02.121970 Freq=800, CH1 RK0
1667 15:36:02.122065
1668 15:36:02.124992 DATLAT Default: 0xa
1669 15:36:02.125094 0, 0xFFFF, sum = 0
1670 15:36:02.128285 1, 0xFFFF, sum = 0
1671 15:36:02.128387 2, 0xFFFF, sum = 0
1672 15:36:02.132125 3, 0xFFFF, sum = 0
1673 15:36:02.132230 4, 0xFFFF, sum = 0
1674 15:36:02.135244 5, 0xFFFF, sum = 0
1675 15:36:02.135345 6, 0xFFFF, sum = 0
1676 15:36:02.138311 7, 0xFFFF, sum = 0
1677 15:36:02.138411 8, 0xFFFF, sum = 0
1678 15:36:02.142027 9, 0x0, sum = 1
1679 15:36:02.142131 10, 0x0, sum = 2
1680 15:36:02.145492 11, 0x0, sum = 3
1681 15:36:02.145591 12, 0x0, sum = 4
1682 15:36:02.148203 best_step = 10
1683 15:36:02.148305
1684 15:36:02.148394 ==
1685 15:36:02.151550 Dram Type= 6, Freq= 0, CH_1, rank 0
1686 15:36:02.154965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1687 15:36:02.155072 ==
1688 15:36:02.155168 RX Vref Scan: 1
1689 15:36:02.155259
1690 15:36:02.158093 Set Vref Range= 32 -> 127
1691 15:36:02.158202
1692 15:36:02.161883 RX Vref 32 -> 127, step: 1
1693 15:36:02.161985
1694 15:36:02.164921 RX Delay -111 -> 252, step: 8
1695 15:36:02.165020
1696 15:36:02.168323 Set Vref, RX VrefLevel [Byte0]: 32
1697 15:36:02.171718 [Byte1]: 32
1698 15:36:02.171820
1699 15:36:02.174882 Set Vref, RX VrefLevel [Byte0]: 33
1700 15:36:02.178113 [Byte1]: 33
1701 15:36:02.178220
1702 15:36:02.181974 Set Vref, RX VrefLevel [Byte0]: 34
1703 15:36:02.185204 [Byte1]: 34
1704 15:36:02.189010
1705 15:36:02.189112 Set Vref, RX VrefLevel [Byte0]: 35
1706 15:36:02.192333 [Byte1]: 35
1707 15:36:02.196847
1708 15:36:02.196964 Set Vref, RX VrefLevel [Byte0]: 36
1709 15:36:02.199946 [Byte1]: 36
1710 15:36:02.204216
1711 15:36:02.204318 Set Vref, RX VrefLevel [Byte0]: 37
1712 15:36:02.207694 [Byte1]: 37
1713 15:36:02.211704
1714 15:36:02.211805 Set Vref, RX VrefLevel [Byte0]: 38
1715 15:36:02.215157 [Byte1]: 38
1716 15:36:02.219876
1717 15:36:02.219960 Set Vref, RX VrefLevel [Byte0]: 39
1718 15:36:02.223248 [Byte1]: 39
1719 15:36:02.227127
1720 15:36:02.227204 Set Vref, RX VrefLevel [Byte0]: 40
1721 15:36:02.230430 [Byte1]: 40
1722 15:36:02.234883
1723 15:36:02.234989 Set Vref, RX VrefLevel [Byte0]: 41
1724 15:36:02.238139 [Byte1]: 41
1725 15:36:02.242535
1726 15:36:02.242641 Set Vref, RX VrefLevel [Byte0]: 42
1727 15:36:02.245706 [Byte1]: 42
1728 15:36:02.249954
1729 15:36:02.250048 Set Vref, RX VrefLevel [Byte0]: 43
1730 15:36:02.253348 [Byte1]: 43
1731 15:36:02.257893
1732 15:36:02.258001 Set Vref, RX VrefLevel [Byte0]: 44
1733 15:36:02.261227 [Byte1]: 44
1734 15:36:02.265353
1735 15:36:02.265454 Set Vref, RX VrefLevel [Byte0]: 45
1736 15:36:02.268886 [Byte1]: 45
1737 15:36:02.273083
1738 15:36:02.273217 Set Vref, RX VrefLevel [Byte0]: 46
1739 15:36:02.276288 [Byte1]: 46
1740 15:36:02.280916
1741 15:36:02.281021 Set Vref, RX VrefLevel [Byte0]: 47
1742 15:36:02.287324 [Byte1]: 47
1743 15:36:02.287460
1744 15:36:02.290381 Set Vref, RX VrefLevel [Byte0]: 48
1745 15:36:02.294302 [Byte1]: 48
1746 15:36:02.294403
1747 15:36:02.297491 Set Vref, RX VrefLevel [Byte0]: 49
1748 15:36:02.300698 [Byte1]: 49
1749 15:36:02.300807
1750 15:36:02.303940 Set Vref, RX VrefLevel [Byte0]: 50
1751 15:36:02.307184 [Byte1]: 50
1752 15:36:02.311647
1753 15:36:02.311755 Set Vref, RX VrefLevel [Byte0]: 51
1754 15:36:02.314828 [Byte1]: 51
1755 15:36:02.319282
1756 15:36:02.319403 Set Vref, RX VrefLevel [Byte0]: 52
1757 15:36:02.322265 [Byte1]: 52
1758 15:36:02.326377
1759 15:36:02.326477 Set Vref, RX VrefLevel [Byte0]: 53
1760 15:36:02.329899 [Byte1]: 53
1761 15:36:02.334305
1762 15:36:02.334409 Set Vref, RX VrefLevel [Byte0]: 54
1763 15:36:02.337459 [Byte1]: 54
1764 15:36:02.341891
1765 15:36:02.341990 Set Vref, RX VrefLevel [Byte0]: 55
1766 15:36:02.345005 [Byte1]: 55
1767 15:36:02.349586
1768 15:36:02.349694 Set Vref, RX VrefLevel [Byte0]: 56
1769 15:36:02.353222 [Byte1]: 56
1770 15:36:02.357062
1771 15:36:02.357169 Set Vref, RX VrefLevel [Byte0]: 57
1772 15:36:02.360844 [Byte1]: 57
1773 15:36:02.365206
1774 15:36:02.365310 Set Vref, RX VrefLevel [Byte0]: 58
1775 15:36:02.368562 [Byte1]: 58
1776 15:36:02.372634
1777 15:36:02.372733 Set Vref, RX VrefLevel [Byte0]: 59
1778 15:36:02.375791 [Byte1]: 59
1779 15:36:02.380567
1780 15:36:02.380668 Set Vref, RX VrefLevel [Byte0]: 60
1781 15:36:02.383508 [Byte1]: 60
1782 15:36:02.388119
1783 15:36:02.388224 Set Vref, RX VrefLevel [Byte0]: 61
1784 15:36:02.390896 [Byte1]: 61
1785 15:36:02.395294
1786 15:36:02.395430 Set Vref, RX VrefLevel [Byte0]: 62
1787 15:36:02.399023 [Byte1]: 62
1788 15:36:02.403016
1789 15:36:02.403123 Set Vref, RX VrefLevel [Byte0]: 63
1790 15:36:02.406700 [Byte1]: 63
1791 15:36:02.410682
1792 15:36:02.410766 Set Vref, RX VrefLevel [Byte0]: 64
1793 15:36:02.414533 [Byte1]: 64
1794 15:36:02.418354
1795 15:36:02.418434 Set Vref, RX VrefLevel [Byte0]: 65
1796 15:36:02.422118 [Byte1]: 65
1797 15:36:02.426129
1798 15:36:02.426203 Set Vref, RX VrefLevel [Byte0]: 66
1799 15:36:02.429323 [Byte1]: 66
1800 15:36:02.433591
1801 15:36:02.433701 Set Vref, RX VrefLevel [Byte0]: 67
1802 15:36:02.437203 [Byte1]: 67
1803 15:36:02.441126
1804 15:36:02.441206 Set Vref, RX VrefLevel [Byte0]: 68
1805 15:36:02.444642 [Byte1]: 68
1806 15:36:02.449310
1807 15:36:02.452490 Set Vref, RX VrefLevel [Byte0]: 69
1808 15:36:02.452580 [Byte1]: 69
1809 15:36:02.457027
1810 15:36:02.457111 Set Vref, RX VrefLevel [Byte0]: 70
1811 15:36:02.460108 [Byte1]: 70
1812 15:36:02.464530
1813 15:36:02.464609 Set Vref, RX VrefLevel [Byte0]: 71
1814 15:36:02.467602 [Byte1]: 71
1815 15:36:02.472159
1816 15:36:02.472242 Set Vref, RX VrefLevel [Byte0]: 72
1817 15:36:02.475311 [Byte1]: 72
1818 15:36:02.479723
1819 15:36:02.479804 Set Vref, RX VrefLevel [Byte0]: 73
1820 15:36:02.482700 [Byte1]: 73
1821 15:36:02.487002
1822 15:36:02.487086 Set Vref, RX VrefLevel [Byte0]: 74
1823 15:36:02.490714 [Byte1]: 74
1824 15:36:02.495059
1825 15:36:02.495143 Set Vref, RX VrefLevel [Byte0]: 75
1826 15:36:02.497977 [Byte1]: 75
1827 15:36:02.502574
1828 15:36:02.502651 Final RX Vref Byte 0 = 59 to rank0
1829 15:36:02.505578 Final RX Vref Byte 1 = 55 to rank0
1830 15:36:02.509330 Final RX Vref Byte 0 = 59 to rank1
1831 15:36:02.512505 Final RX Vref Byte 1 = 55 to rank1==
1832 15:36:02.515770 Dram Type= 6, Freq= 0, CH_1, rank 0
1833 15:36:02.522331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 15:36:02.522431 ==
1835 15:36:02.522540 DQS Delay:
1836 15:36:02.522634 DQS0 = 0, DQS1 = 0
1837 15:36:02.526218 DQM Delay:
1838 15:36:02.526293 DQM0 = 81, DQM1 = 71
1839 15:36:02.529571 DQ Delay:
1840 15:36:02.532697 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1841 15:36:02.532776 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1842 15:36:02.535898 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1843 15:36:02.539144 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1844 15:36:02.542794
1845 15:36:02.542870
1846 15:36:02.548967 [DQSOSCAuto] RK0, (LSB)MR18= 0xe19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1847 15:36:02.552484 CH1 RK0: MR19=606, MR18=E19
1848 15:36:02.559277 CH1_RK0: MR19=0x606, MR18=0xE19, DQSOSC=403, MR23=63, INC=90, DEC=60
1849 15:36:02.559366
1850 15:36:02.562403 ----->DramcWriteLeveling(PI) begin...
1851 15:36:02.562486 ==
1852 15:36:02.566396 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 15:36:02.569396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 15:36:02.569503 ==
1855 15:36:02.572593 Write leveling (Byte 0): 28 => 28
1856 15:36:02.575836 Write leveling (Byte 1): 29 => 29
1857 15:36:02.579118 DramcWriteLeveling(PI) end<-----
1858 15:36:02.579224
1859 15:36:02.579315 ==
1860 15:36:02.582267 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 15:36:02.586057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 15:36:02.586148 ==
1863 15:36:02.589060 [Gating] SW mode calibration
1864 15:36:02.595872 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1865 15:36:02.602974 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1866 15:36:02.606110 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1867 15:36:02.609037 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1868 15:36:02.616146 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 15:36:02.619035 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 15:36:02.622314 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 15:36:02.629494 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 15:36:02.632773 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 15:36:02.636143 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 15:36:02.639268 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 15:36:02.645931 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 15:36:02.649514 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 15:36:02.652752 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 15:36:02.659338 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 15:36:02.662939 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 15:36:02.665807 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 15:36:02.672451 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 15:36:02.676157 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 15:36:02.679177 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1884 15:36:02.686383 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 15:36:02.689482 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 15:36:02.692567 0 8 16 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1887 15:36:02.699239 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 15:36:02.702527 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 15:36:02.706442 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 15:36:02.709636 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 15:36:02.716490 0 9 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1892 15:36:02.719475 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1893 15:36:02.723133 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 15:36:02.729293 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 15:36:02.732976 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 15:36:02.736238 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 15:36:02.742752 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 15:36:02.745881 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 15:36:02.749734 0 10 4 | B1->B0 | 3131 2e2e | 1 1 | (1 1) (1 0)
1900 15:36:02.755937 0 10 8 | B1->B0 | 2828 2323 | 1 0 | (1 0) (1 0)
1901 15:36:02.759216 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 15:36:02.763008 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 15:36:02.769303 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 15:36:02.773000 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 15:36:02.776245 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 15:36:02.782220 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 15:36:02.785619 0 11 4 | B1->B0 | 2626 3636 | 0 0 | (0 0) (0 0)
1908 15:36:02.789186 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1909 15:36:02.795979 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 15:36:02.799147 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 15:36:02.802729 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 15:36:02.809003 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 15:36:02.812171 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 15:36:02.815364 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 15:36:02.822297 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1916 15:36:02.825346 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 15:36:02.828931 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 15:36:02.835674 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 15:36:02.838691 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 15:36:02.842522 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 15:36:02.849092 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 15:36:02.852339 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 15:36:02.855568 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 15:36:02.862004 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 15:36:02.865388 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 15:36:02.869183 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 15:36:02.872268 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 15:36:02.878674 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 15:36:02.881919 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 15:36:02.885146 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 15:36:02.892111 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 15:36:02.895098 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 15:36:02.898572 Total UI for P1: 0, mck2ui 16
1934 15:36:02.902238 best dqsien dly found for B0: ( 0, 14, 6)
1935 15:36:02.905259 Total UI for P1: 0, mck2ui 16
1936 15:36:02.908560 best dqsien dly found for B1: ( 0, 14, 6)
1937 15:36:02.911775 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1938 15:36:02.915367 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1939 15:36:02.915475
1940 15:36:02.918610 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1941 15:36:02.921853 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1942 15:36:02.925758 [Gating] SW calibration Done
1943 15:36:02.925841 ==
1944 15:36:02.928803 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 15:36:02.931765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 15:36:02.935588 ==
1947 15:36:02.935666 RX Vref Scan: 0
1948 15:36:02.935739
1949 15:36:02.938546 RX Vref 0 -> 0, step: 1
1950 15:36:02.938626
1951 15:36:02.942325 RX Delay -130 -> 252, step: 16
1952 15:36:02.945307 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1953 15:36:02.948515 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1954 15:36:02.951979 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1955 15:36:02.955157 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1956 15:36:02.962004 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1957 15:36:02.965348 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1958 15:36:02.968663 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1959 15:36:02.971997 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1960 15:36:02.975231 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1961 15:36:02.982041 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1962 15:36:02.985285 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1963 15:36:02.988426 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1964 15:36:02.991622 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1965 15:36:02.995540 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1966 15:36:03.001840 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1967 15:36:03.005514 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1968 15:36:03.005599 ==
1969 15:36:03.008756 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 15:36:03.011723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 15:36:03.011801 ==
1972 15:36:03.015283 DQS Delay:
1973 15:36:03.015360 DQS0 = 0, DQS1 = 0
1974 15:36:03.015488 DQM Delay:
1975 15:36:03.018822 DQM0 = 80, DQM1 = 73
1976 15:36:03.018905 DQ Delay:
1977 15:36:03.021862 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1978 15:36:03.025393 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1979 15:36:03.028595 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1980 15:36:03.031763 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1981 15:36:03.031857
1982 15:36:03.031935
1983 15:36:03.032052 ==
1984 15:36:03.034902 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 15:36:03.038680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 15:36:03.041828 ==
1987 15:36:03.041944
1988 15:36:03.042009
1989 15:36:03.042107 TX Vref Scan disable
1990 15:36:03.045445 == TX Byte 0 ==
1991 15:36:03.048605 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1992 15:36:03.052300 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1993 15:36:03.055520 == TX Byte 1 ==
1994 15:36:03.058742 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1995 15:36:03.061993 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1996 15:36:03.062102 ==
1997 15:36:03.065162 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 15:36:03.072219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 15:36:03.072302 ==
2000 15:36:03.083891 TX Vref=22, minBit 0, minWin=27, winSum=448
2001 15:36:03.087434 TX Vref=24, minBit 5, minWin=27, winSum=452
2002 15:36:03.090781 TX Vref=26, minBit 0, minWin=28, winSum=455
2003 15:36:03.093880 TX Vref=28, minBit 0, minWin=28, winSum=457
2004 15:36:03.097200 TX Vref=30, minBit 0, minWin=28, winSum=459
2005 15:36:03.100486 TX Vref=32, minBit 1, minWin=27, winSum=458
2006 15:36:03.107305 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
2007 15:36:03.107392
2008 15:36:03.110484 Final TX Range 1 Vref 30
2009 15:36:03.110564
2010 15:36:03.110638 ==
2011 15:36:03.114303 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 15:36:03.117498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 15:36:03.117581 ==
2014 15:36:03.117657
2015 15:36:03.117719
2016 15:36:03.120697 TX Vref Scan disable
2017 15:36:03.124248 == TX Byte 0 ==
2018 15:36:03.127287 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2019 15:36:03.130487 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2020 15:36:03.133924 == TX Byte 1 ==
2021 15:36:03.137822 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2022 15:36:03.140774 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2023 15:36:03.140881
2024 15:36:03.144443 [DATLAT]
2025 15:36:03.144530 Freq=800, CH1 RK1
2026 15:36:03.144601
2027 15:36:03.147459 DATLAT Default: 0xa
2028 15:36:03.147538 0, 0xFFFF, sum = 0
2029 15:36:03.150709 1, 0xFFFF, sum = 0
2030 15:36:03.150791 2, 0xFFFF, sum = 0
2031 15:36:03.154491 3, 0xFFFF, sum = 0
2032 15:36:03.154578 4, 0xFFFF, sum = 0
2033 15:36:03.157622 5, 0xFFFF, sum = 0
2034 15:36:03.157704 6, 0xFFFF, sum = 0
2035 15:36:03.160844 7, 0xFFFF, sum = 0
2036 15:36:03.160953 8, 0xFFFF, sum = 0
2037 15:36:03.164018 9, 0x0, sum = 1
2038 15:36:03.164097 10, 0x0, sum = 2
2039 15:36:03.167134 11, 0x0, sum = 3
2040 15:36:03.167214 12, 0x0, sum = 4
2041 15:36:03.170983 best_step = 10
2042 15:36:03.171060
2043 15:36:03.171134 ==
2044 15:36:03.174298 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 15:36:03.177492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 15:36:03.177575 ==
2047 15:36:03.180738 RX Vref Scan: 0
2048 15:36:03.180815
2049 15:36:03.180890 RX Vref 0 -> 0, step: 1
2050 15:36:03.180952
2051 15:36:03.183978 RX Delay -111 -> 252, step: 8
2052 15:36:03.190822 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2053 15:36:03.194002 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2054 15:36:03.197552 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2055 15:36:03.200744 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2056 15:36:03.203864 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2057 15:36:03.210887 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2058 15:36:03.213880 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2059 15:36:03.217656 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2060 15:36:03.220839 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2061 15:36:03.224020 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2062 15:36:03.231042 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2063 15:36:03.234232 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2064 15:36:03.237505 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2065 15:36:03.240753 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2066 15:36:03.244223 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2067 15:36:03.250883 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2068 15:36:03.250967 ==
2069 15:36:03.253874 Dram Type= 6, Freq= 0, CH_1, rank 1
2070 15:36:03.257127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2071 15:36:03.257207 ==
2072 15:36:03.257270 DQS Delay:
2073 15:36:03.260987 DQS0 = 0, DQS1 = 0
2074 15:36:03.261076 DQM Delay:
2075 15:36:03.263821 DQM0 = 77, DQM1 = 74
2076 15:36:03.263897 DQ Delay:
2077 15:36:03.267665 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2078 15:36:03.270616 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2079 15:36:03.274210 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2080 15:36:03.277465 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2081 15:36:03.277545
2082 15:36:03.277617
2083 15:36:03.283946 [DQSOSCAuto] RK1, (LSB)MR18= 0x2038, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2084 15:36:03.287352 CH1 RK1: MR19=606, MR18=2038
2085 15:36:03.293874 CH1_RK1: MR19=0x606, MR18=0x2038, DQSOSC=395, MR23=63, INC=94, DEC=63
2086 15:36:03.297950 [RxdqsGatingPostProcess] freq 800
2087 15:36:03.303762 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2088 15:36:03.307489 Pre-setting of DQS Precalculation
2089 15:36:03.310720 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2090 15:36:03.317323 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2091 15:36:03.324116 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2092 15:36:03.324223
2093 15:36:03.324293
2094 15:36:03.327610 [Calibration Summary] 1600 Mbps
2095 15:36:03.330791 CH 0, Rank 0
2096 15:36:03.330865 SW Impedance : PASS
2097 15:36:03.334079 DUTY Scan : NO K
2098 15:36:03.337296 ZQ Calibration : PASS
2099 15:36:03.337380 Jitter Meter : NO K
2100 15:36:03.340497 CBT Training : PASS
2101 15:36:03.344491 Write leveling : PASS
2102 15:36:03.344580 RX DQS gating : PASS
2103 15:36:03.347657 RX DQ/DQS(RDDQC) : PASS
2104 15:36:03.347760 TX DQ/DQS : PASS
2105 15:36:03.350689 RX DATLAT : PASS
2106 15:36:03.353908 RX DQ/DQS(Engine): PASS
2107 15:36:03.354029 TX OE : NO K
2108 15:36:03.357658 All Pass.
2109 15:36:03.357762
2110 15:36:03.357879 CH 0, Rank 1
2111 15:36:03.360954 SW Impedance : PASS
2112 15:36:03.361070 DUTY Scan : NO K
2113 15:36:03.364005 ZQ Calibration : PASS
2114 15:36:03.367865 Jitter Meter : NO K
2115 15:36:03.367952 CBT Training : PASS
2116 15:36:03.371041 Write leveling : PASS
2117 15:36:03.373954 RX DQS gating : PASS
2118 15:36:03.374037 RX DQ/DQS(RDDQC) : PASS
2119 15:36:03.377062 TX DQ/DQS : PASS
2120 15:36:03.380810 RX DATLAT : PASS
2121 15:36:03.380924 RX DQ/DQS(Engine): PASS
2122 15:36:03.383667 TX OE : NO K
2123 15:36:03.383753 All Pass.
2124 15:36:03.383833
2125 15:36:03.387213 CH 1, Rank 0
2126 15:36:03.387325 SW Impedance : PASS
2127 15:36:03.390369 DUTY Scan : NO K
2128 15:36:03.393759 ZQ Calibration : PASS
2129 15:36:03.393864 Jitter Meter : NO K
2130 15:36:03.397100 CBT Training : PASS
2131 15:36:03.400399 Write leveling : PASS
2132 15:36:03.400478 RX DQS gating : PASS
2133 15:36:03.403676 RX DQ/DQS(RDDQC) : PASS
2134 15:36:03.403792 TX DQ/DQS : PASS
2135 15:36:03.406972 RX DATLAT : PASS
2136 15:36:03.411057 RX DQ/DQS(Engine): PASS
2137 15:36:03.411161 TX OE : NO K
2138 15:36:03.413940 All Pass.
2139 15:36:03.414017
2140 15:36:03.414081 CH 1, Rank 1
2141 15:36:03.417406 SW Impedance : PASS
2142 15:36:03.417528 DUTY Scan : NO K
2143 15:36:03.420652 ZQ Calibration : PASS
2144 15:36:03.423758 Jitter Meter : NO K
2145 15:36:03.423839 CBT Training : PASS
2146 15:36:03.426998 Write leveling : PASS
2147 15:36:03.430521 RX DQS gating : PASS
2148 15:36:03.430622 RX DQ/DQS(RDDQC) : PASS
2149 15:36:03.433914 TX DQ/DQS : PASS
2150 15:36:03.436977 RX DATLAT : PASS
2151 15:36:03.437078 RX DQ/DQS(Engine): PASS
2152 15:36:03.440208 TX OE : NO K
2153 15:36:03.440284 All Pass.
2154 15:36:03.440354
2155 15:36:03.443402 DramC Write-DBI off
2156 15:36:03.446746 PER_BANK_REFRESH: Hybrid Mode
2157 15:36:03.446829 TX_TRACKING: ON
2158 15:36:03.450551 [GetDramInforAfterCalByMRR] Vendor 6.
2159 15:36:03.453762 [GetDramInforAfterCalByMRR] Revision 606.
2160 15:36:03.456825 [GetDramInforAfterCalByMRR] Revision 2 0.
2161 15:36:03.460637 MR0 0x3b3b
2162 15:36:03.460718 MR8 0x5151
2163 15:36:03.463857 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 15:36:03.463935
2165 15:36:03.464009 MR0 0x3b3b
2166 15:36:03.466934 MR8 0x5151
2167 15:36:03.470513 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2168 15:36:03.470624
2169 15:36:03.480207 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2170 15:36:03.483522 [FAST_K] Save calibration result to emmc
2171 15:36:03.486710 [FAST_K] Save calibration result to emmc
2172 15:36:03.486794 dram_init: config_dvfs: 1
2173 15:36:03.493361 dramc_set_vcore_voltage set vcore to 662500
2174 15:36:03.493441 Read voltage for 1200, 2
2175 15:36:03.496720 Vio18 = 0
2176 15:36:03.496818 Vcore = 662500
2177 15:36:03.496904 Vdram = 0
2178 15:36:03.496964 Vddq = 0
2179 15:36:03.500487 Vmddr = 0
2180 15:36:03.503350 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2181 15:36:03.510325 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2182 15:36:03.513621 MEM_TYPE=3, freq_sel=15
2183 15:36:03.513719 sv_algorithm_assistance_LP4_1600
2184 15:36:03.520534 ============ PULL DRAM RESETB DOWN ============
2185 15:36:03.523469 ========== PULL DRAM RESETB DOWN end =========
2186 15:36:03.527059 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2187 15:36:03.530211 ===================================
2188 15:36:03.533366 LPDDR4 DRAM CONFIGURATION
2189 15:36:03.536973 ===================================
2190 15:36:03.540237 EX_ROW_EN[0] = 0x0
2191 15:36:03.540319 EX_ROW_EN[1] = 0x0
2192 15:36:03.543852 LP4Y_EN = 0x0
2193 15:36:03.543936 WORK_FSP = 0x0
2194 15:36:03.547182 WL = 0x4
2195 15:36:03.547265 RL = 0x4
2196 15:36:03.550338 BL = 0x2
2197 15:36:03.550419 RPST = 0x0
2198 15:36:03.553383 RD_PRE = 0x0
2199 15:36:03.553484 WR_PRE = 0x1
2200 15:36:03.556628 WR_PST = 0x0
2201 15:36:03.556747 DBI_WR = 0x0
2202 15:36:03.560360 DBI_RD = 0x0
2203 15:36:03.560462 OTF = 0x1
2204 15:36:03.563638 ===================================
2205 15:36:03.566763 ===================================
2206 15:36:03.570405 ANA top config
2207 15:36:03.573687 ===================================
2208 15:36:03.576935 DLL_ASYNC_EN = 0
2209 15:36:03.577022 ALL_SLAVE_EN = 0
2210 15:36:03.580280 NEW_RANK_MODE = 1
2211 15:36:03.583595 DLL_IDLE_MODE = 1
2212 15:36:03.586770 LP45_APHY_COMB_EN = 1
2213 15:36:03.586853 TX_ODT_DIS = 1
2214 15:36:03.590024 NEW_8X_MODE = 1
2215 15:36:03.593272 ===================================
2216 15:36:03.597232 ===================================
2217 15:36:03.600326 data_rate = 2400
2218 15:36:03.603524 CKR = 1
2219 15:36:03.606779 DQ_P2S_RATIO = 8
2220 15:36:03.610404 ===================================
2221 15:36:03.613311 CA_P2S_RATIO = 8
2222 15:36:03.613391 DQ_CA_OPEN = 0
2223 15:36:03.616809 DQ_SEMI_OPEN = 0
2224 15:36:03.620490 CA_SEMI_OPEN = 0
2225 15:36:03.623561 CA_FULL_RATE = 0
2226 15:36:03.626750 DQ_CKDIV4_EN = 0
2227 15:36:03.626830 CA_CKDIV4_EN = 0
2228 15:36:03.630434 CA_PREDIV_EN = 0
2229 15:36:03.633403 PH8_DLY = 17
2230 15:36:03.636488 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2231 15:36:03.639999 DQ_AAMCK_DIV = 4
2232 15:36:03.643172 CA_AAMCK_DIV = 4
2233 15:36:03.646719 CA_ADMCK_DIV = 4
2234 15:36:03.646807 DQ_TRACK_CA_EN = 0
2235 15:36:03.650392 CA_PICK = 1200
2236 15:36:03.653580 CA_MCKIO = 1200
2237 15:36:03.656973 MCKIO_SEMI = 0
2238 15:36:03.660042 PLL_FREQ = 2366
2239 15:36:03.663194 DQ_UI_PI_RATIO = 32
2240 15:36:03.666974 CA_UI_PI_RATIO = 0
2241 15:36:03.670081 ===================================
2242 15:36:03.670238 ===================================
2243 15:36:03.673347 memory_type:LPDDR4
2244 15:36:03.677082 GP_NUM : 10
2245 15:36:03.677194 SRAM_EN : 1
2246 15:36:03.680342 MD32_EN : 0
2247 15:36:03.683726 ===================================
2248 15:36:03.686892 [ANA_INIT] >>>>>>>>>>>>>>
2249 15:36:03.690113 <<<<<< [CONFIGURE PHASE]: ANA_TX
2250 15:36:03.693466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2251 15:36:03.696711 ===================================
2252 15:36:03.696825 data_rate = 2400,PCW = 0X5b00
2253 15:36:03.699944 ===================================
2254 15:36:03.703194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2255 15:36:03.710146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 15:36:03.716653 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2257 15:36:03.720360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2258 15:36:03.723450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2259 15:36:03.726508 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2260 15:36:03.730306 [ANA_INIT] flow start
2261 15:36:03.733184 [ANA_INIT] PLL >>>>>>>>
2262 15:36:03.733262 [ANA_INIT] PLL <<<<<<<<
2263 15:36:03.736720 [ANA_INIT] MIDPI >>>>>>>>
2264 15:36:03.740367 [ANA_INIT] MIDPI <<<<<<<<
2265 15:36:03.740462 [ANA_INIT] DLL >>>>>>>>
2266 15:36:03.743208 [ANA_INIT] DLL <<<<<<<<
2267 15:36:03.746726 [ANA_INIT] flow end
2268 15:36:03.749894 ============ LP4 DIFF to SE enter ============
2269 15:36:03.753385 ============ LP4 DIFF to SE exit ============
2270 15:36:03.756587 [ANA_INIT] <<<<<<<<<<<<<
2271 15:36:03.760566 [Flow] Enable top DCM control >>>>>
2272 15:36:03.763869 [Flow] Enable top DCM control <<<<<
2273 15:36:03.767135 Enable DLL master slave shuffle
2274 15:36:03.770130 ==============================================================
2275 15:36:03.773460 Gating Mode config
2276 15:36:03.776710 ==============================================================
2277 15:36:03.780437 Config description:
2278 15:36:03.790462 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2279 15:36:03.797101 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2280 15:36:03.800318 SELPH_MODE 0: By rank 1: By Phase
2281 15:36:03.807037 ==============================================================
2282 15:36:03.810025 GAT_TRACK_EN = 1
2283 15:36:03.813276 RX_GATING_MODE = 2
2284 15:36:03.816969 RX_GATING_TRACK_MODE = 2
2285 15:36:03.820298 SELPH_MODE = 1
2286 15:36:03.823565 PICG_EARLY_EN = 1
2287 15:36:03.823649 VALID_LAT_VALUE = 1
2288 15:36:03.829863 ==============================================================
2289 15:36:03.833709 Enter into Gating configuration >>>>
2290 15:36:03.837089 Exit from Gating configuration <<<<
2291 15:36:03.839958 Enter into DVFS_PRE_config >>>>>
2292 15:36:03.850224 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2293 15:36:03.853180 Exit from DVFS_PRE_config <<<<<
2294 15:36:03.856686 Enter into PICG configuration >>>>
2295 15:36:03.860266 Exit from PICG configuration <<<<
2296 15:36:03.863173 [RX_INPUT] configuration >>>>>
2297 15:36:03.866815 [RX_INPUT] configuration <<<<<
2298 15:36:03.870200 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2299 15:36:03.876549 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2300 15:36:03.883826 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 15:36:03.890086 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 15:36:03.896798 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 15:36:03.900099 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 15:36:03.907119 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2305 15:36:03.910336 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2306 15:36:03.913721 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2307 15:36:03.916909 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2308 15:36:03.920130 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2309 15:36:03.927026 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 15:36:03.930280 ===================================
2311 15:36:03.933543 LPDDR4 DRAM CONFIGURATION
2312 15:36:03.936718 ===================================
2313 15:36:03.936798 EX_ROW_EN[0] = 0x0
2314 15:36:03.940113 EX_ROW_EN[1] = 0x0
2315 15:36:03.940208 LP4Y_EN = 0x0
2316 15:36:03.943290 WORK_FSP = 0x0
2317 15:36:03.943386 WL = 0x4
2318 15:36:03.946614 RL = 0x4
2319 15:36:03.946703 BL = 0x2
2320 15:36:03.950439 RPST = 0x0
2321 15:36:03.950525 RD_PRE = 0x0
2322 15:36:03.953719 WR_PRE = 0x1
2323 15:36:03.953797 WR_PST = 0x0
2324 15:36:03.956766 DBI_WR = 0x0
2325 15:36:03.956855 DBI_RD = 0x0
2326 15:36:03.960377 OTF = 0x1
2327 15:36:03.963192 ===================================
2328 15:36:03.966621 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2329 15:36:03.970002 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2330 15:36:03.976638 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2331 15:36:03.979726 ===================================
2332 15:36:03.979823 LPDDR4 DRAM CONFIGURATION
2333 15:36:03.983506 ===================================
2334 15:36:03.986722 EX_ROW_EN[0] = 0x10
2335 15:36:03.990050 EX_ROW_EN[1] = 0x0
2336 15:36:03.990139 LP4Y_EN = 0x0
2337 15:36:03.993166 WORK_FSP = 0x0
2338 15:36:03.993252 WL = 0x4
2339 15:36:03.996420 RL = 0x4
2340 15:36:03.996501 BL = 0x2
2341 15:36:04.000143 RPST = 0x0
2342 15:36:04.000219 RD_PRE = 0x0
2343 15:36:04.003279 WR_PRE = 0x1
2344 15:36:04.003354 WR_PST = 0x0
2345 15:36:04.006686 DBI_WR = 0x0
2346 15:36:04.006760 DBI_RD = 0x0
2347 15:36:04.009784 OTF = 0x1
2348 15:36:04.013055 ===================================
2349 15:36:04.020068 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2350 15:36:04.020147 ==
2351 15:36:04.023341 Dram Type= 6, Freq= 0, CH_0, rank 0
2352 15:36:04.026754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2353 15:36:04.026873 ==
2354 15:36:04.029999 [Duty_Offset_Calibration]
2355 15:36:04.030085 B0:2 B1:0 CA:3
2356 15:36:04.030153
2357 15:36:04.033208 [DutyScan_Calibration_Flow] k_type=0
2358 15:36:04.043322
2359 15:36:04.043462 ==CLK 0==
2360 15:36:04.046660 Final CLK duty delay cell = 0
2361 15:36:04.049914 [0] MAX Duty = 5062%(X100), DQS PI = 20
2362 15:36:04.053558 [0] MIN Duty = 4906%(X100), DQS PI = 54
2363 15:36:04.053635 [0] AVG Duty = 4984%(X100)
2364 15:36:04.056855
2365 15:36:04.060114 CH0 CLK Duty spec in!! Max-Min= 156%
2366 15:36:04.063459 [DutyScan_Calibration_Flow] ====Done====
2367 15:36:04.063566
2368 15:36:04.066644 [DutyScan_Calibration_Flow] k_type=1
2369 15:36:04.081632
2370 15:36:04.081774 ==DQS 0 ==
2371 15:36:04.085003 Final DQS duty delay cell = 0
2372 15:36:04.088641 [0] MAX Duty = 5062%(X100), DQS PI = 12
2373 15:36:04.091942 [0] MIN Duty = 4907%(X100), DQS PI = 44
2374 15:36:04.095129 [0] AVG Duty = 4984%(X100)
2375 15:36:04.095231
2376 15:36:04.095329 ==DQS 1 ==
2377 15:36:04.098392 Final DQS duty delay cell = -4
2378 15:36:04.101886 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2379 15:36:04.105430 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2380 15:36:04.108450 [-4] AVG Duty = 4922%(X100)
2381 15:36:04.108527
2382 15:36:04.111827 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2383 15:36:04.111915
2384 15:36:04.114945 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2385 15:36:04.118815 [DutyScan_Calibration_Flow] ====Done====
2386 15:36:04.118894
2387 15:36:04.122008 [DutyScan_Calibration_Flow] k_type=3
2388 15:36:04.139598
2389 15:36:04.139682 ==DQM 0 ==
2390 15:36:04.142760 Final DQM duty delay cell = 0
2391 15:36:04.146016 [0] MAX Duty = 5124%(X100), DQS PI = 12
2392 15:36:04.149887 [0] MIN Duty = 4876%(X100), DQS PI = 0
2393 15:36:04.149970 [0] AVG Duty = 5000%(X100)
2394 15:36:04.150038
2395 15:36:04.153135 ==DQM 1 ==
2396 15:36:04.156392 Final DQM duty delay cell = 4
2397 15:36:04.159442 [4] MAX Duty = 5124%(X100), DQS PI = 0
2398 15:36:04.162685 [4] MIN Duty = 5000%(X100), DQS PI = 32
2399 15:36:04.162771 [4] AVG Duty = 5062%(X100)
2400 15:36:04.162836
2401 15:36:04.166609 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2402 15:36:04.169902
2403 15:36:04.173199 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2404 15:36:04.176483 [DutyScan_Calibration_Flow] ====Done====
2405 15:36:04.176568
2406 15:36:04.179716 [DutyScan_Calibration_Flow] k_type=2
2407 15:36:04.194110
2408 15:36:04.194201 ==DQ 0 ==
2409 15:36:04.197494 Final DQ duty delay cell = -4
2410 15:36:04.201115 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2411 15:36:04.204058 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2412 15:36:04.207358 [-4] AVG Duty = 4969%(X100)
2413 15:36:04.207454
2414 15:36:04.207523 ==DQ 1 ==
2415 15:36:04.210624 Final DQ duty delay cell = -4
2416 15:36:04.214251 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2417 15:36:04.217308 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2418 15:36:04.220567 [-4] AVG Duty = 4938%(X100)
2419 15:36:04.220675
2420 15:36:04.224369 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2421 15:36:04.224451
2422 15:36:04.227469 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2423 15:36:04.230761 [DutyScan_Calibration_Flow] ====Done====
2424 15:36:04.230859 ==
2425 15:36:04.233980 Dram Type= 6, Freq= 0, CH_1, rank 0
2426 15:36:04.237335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2427 15:36:04.237418 ==
2428 15:36:04.241252 [Duty_Offset_Calibration]
2429 15:36:04.241332 B0:1 B1:-2 CA:0
2430 15:36:04.241398
2431 15:36:04.244573 [DutyScan_Calibration_Flow] k_type=0
2432 15:36:04.254850
2433 15:36:04.254952 ==CLK 0==
2434 15:36:04.258159 Final CLK duty delay cell = 0
2435 15:36:04.261270 [0] MAX Duty = 5062%(X100), DQS PI = 28
2436 15:36:04.264975 [0] MIN Duty = 4876%(X100), DQS PI = 2
2437 15:36:04.265057 [0] AVG Duty = 4969%(X100)
2438 15:36:04.268267
2439 15:36:04.268348 CH1 CLK Duty spec in!! Max-Min= 186%
2440 15:36:04.274759 [DutyScan_Calibration_Flow] ====Done====
2441 15:36:04.274844
2442 15:36:04.278033 [DutyScan_Calibration_Flow] k_type=1
2443 15:36:04.293242
2444 15:36:04.293343 ==DQS 0 ==
2445 15:36:04.296386 Final DQS duty delay cell = -4
2446 15:36:04.300128 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2447 15:36:04.303091 [-4] MIN Duty = 4876%(X100), DQS PI = 52
2448 15:36:04.306766 [-4] AVG Duty = 4953%(X100)
2449 15:36:04.306848
2450 15:36:04.306960 ==DQS 1 ==
2451 15:36:04.309700 Final DQS duty delay cell = 0
2452 15:36:04.313290 [0] MAX Duty = 5093%(X100), DQS PI = 0
2453 15:36:04.316374 [0] MIN Duty = 4907%(X100), DQS PI = 26
2454 15:36:04.319577 [0] AVG Duty = 5000%(X100)
2455 15:36:04.319657
2456 15:36:04.322961 CH1 DQS 0 Duty spec in!! Max-Min= 155%
2457 15:36:04.323046
2458 15:36:04.326214 CH1 DQS 1 Duty spec in!! Max-Min= 186%
2459 15:36:04.329937 [DutyScan_Calibration_Flow] ====Done====
2460 15:36:04.330021
2461 15:36:04.333193 [DutyScan_Calibration_Flow] k_type=3
2462 15:36:04.350096
2463 15:36:04.350207 ==DQM 0 ==
2464 15:36:04.353375 Final DQM duty delay cell = 0
2465 15:36:04.356475 [0] MAX Duty = 5031%(X100), DQS PI = 24
2466 15:36:04.360342 [0] MIN Duty = 4844%(X100), DQS PI = 54
2467 15:36:04.363450 [0] AVG Duty = 4937%(X100)
2468 15:36:04.363529
2469 15:36:04.363608 ==DQM 1 ==
2470 15:36:04.366709 Final DQM duty delay cell = 0
2471 15:36:04.370030 [0] MAX Duty = 5031%(X100), DQS PI = 36
2472 15:36:04.373289 [0] MIN Duty = 4907%(X100), DQS PI = 4
2473 15:36:04.373373 [0] AVG Duty = 4969%(X100)
2474 15:36:04.376349
2475 15:36:04.380183 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2476 15:36:04.380270
2477 15:36:04.383519 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2478 15:36:04.386644 [DutyScan_Calibration_Flow] ====Done====
2479 15:36:04.386732
2480 15:36:04.389934 [DutyScan_Calibration_Flow] k_type=2
2481 15:36:04.406551
2482 15:36:04.406639 ==DQ 0 ==
2483 15:36:04.409691 Final DQ duty delay cell = 0
2484 15:36:04.412938 [0] MAX Duty = 5093%(X100), DQS PI = 20
2485 15:36:04.416308 [0] MIN Duty = 4907%(X100), DQS PI = 56
2486 15:36:04.416418 [0] AVG Duty = 5000%(X100)
2487 15:36:04.419864
2488 15:36:04.419949 ==DQ 1 ==
2489 15:36:04.422889 Final DQ duty delay cell = 0
2490 15:36:04.426763 [0] MAX Duty = 5125%(X100), DQS PI = 46
2491 15:36:04.429839 [0] MIN Duty = 4969%(X100), DQS PI = 26
2492 15:36:04.429922 [0] AVG Duty = 5047%(X100)
2493 15:36:04.429987
2494 15:36:04.433143 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2495 15:36:04.436465
2496 15:36:04.439558 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2497 15:36:04.442796 [DutyScan_Calibration_Flow] ====Done====
2498 15:36:04.446735 nWR fixed to 30
2499 15:36:04.446811 [ModeRegInit_LP4] CH0 RK0
2500 15:36:04.449876 [ModeRegInit_LP4] CH0 RK1
2501 15:36:04.452942 [ModeRegInit_LP4] CH1 RK0
2502 15:36:04.453024 [ModeRegInit_LP4] CH1 RK1
2503 15:36:04.456243 match AC timing 7
2504 15:36:04.459503 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2505 15:36:04.463212 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2506 15:36:04.469868 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2507 15:36:04.472827 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2508 15:36:04.480003 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2509 15:36:04.480101 ==
2510 15:36:04.483028 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 15:36:04.486215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 15:36:04.486294 ==
2513 15:36:04.492738 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 15:36:04.499326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2515 15:36:04.506371 [CA 0] Center 40 (10~71) winsize 62
2516 15:36:04.510043 [CA 1] Center 39 (9~70) winsize 62
2517 15:36:04.513242 [CA 2] Center 36 (6~66) winsize 61
2518 15:36:04.516566 [CA 3] Center 35 (5~66) winsize 62
2519 15:36:04.519760 [CA 4] Center 34 (4~65) winsize 62
2520 15:36:04.523505 [CA 5] Center 33 (3~63) winsize 61
2521 15:36:04.523609
2522 15:36:04.526444 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2523 15:36:04.526518
2524 15:36:04.529900 [CATrainingPosCal] consider 1 rank data
2525 15:36:04.533191 u2DelayCellTimex100 = 270/100 ps
2526 15:36:04.536841 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2527 15:36:04.539808 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2528 15:36:04.547006 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2529 15:36:04.549786 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2530 15:36:04.552980 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2531 15:36:04.556766 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2532 15:36:04.556842
2533 15:36:04.559681 CA PerBit enable=1, Macro0, CA PI delay=33
2534 15:36:04.559778
2535 15:36:04.563094 [CBTSetCACLKResult] CA Dly = 33
2536 15:36:04.563192 CS Dly: 7 (0~38)
2537 15:36:04.563257 ==
2538 15:36:04.566876 Dram Type= 6, Freq= 0, CH_0, rank 1
2539 15:36:04.573326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 15:36:04.573455 ==
2541 15:36:04.576864 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2542 15:36:04.583524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2543 15:36:04.592767 [CA 0] Center 40 (10~70) winsize 61
2544 15:36:04.595778 [CA 1] Center 39 (9~70) winsize 62
2545 15:36:04.599039 [CA 2] Center 35 (5~66) winsize 62
2546 15:36:04.602789 [CA 3] Center 35 (5~66) winsize 62
2547 15:36:04.605527 [CA 4] Center 34 (3~65) winsize 63
2548 15:36:04.609278 [CA 5] Center 33 (3~64) winsize 62
2549 15:36:04.609360
2550 15:36:04.612494 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2551 15:36:04.612575
2552 15:36:04.615621 [CATrainingPosCal] consider 2 rank data
2553 15:36:04.619426 u2DelayCellTimex100 = 270/100 ps
2554 15:36:04.622633 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2555 15:36:04.629209 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2556 15:36:04.632410 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2557 15:36:04.635535 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2558 15:36:04.639069 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2559 15:36:04.642727 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2560 15:36:04.642809
2561 15:36:04.645512 CA PerBit enable=1, Macro0, CA PI delay=33
2562 15:36:04.645588
2563 15:36:04.649125 [CBTSetCACLKResult] CA Dly = 33
2564 15:36:04.649203 CS Dly: 8 (0~40)
2565 15:36:04.652127
2566 15:36:04.655852 ----->DramcWriteLeveling(PI) begin...
2567 15:36:04.655933 ==
2568 15:36:04.659009 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 15:36:04.662337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 15:36:04.662450 ==
2571 15:36:04.665697 Write leveling (Byte 0): 33 => 33
2572 15:36:04.668909 Write leveling (Byte 1): 29 => 29
2573 15:36:04.672075 DramcWriteLeveling(PI) end<-----
2574 15:36:04.672154
2575 15:36:04.672222 ==
2576 15:36:04.675863 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 15:36:04.679062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 15:36:04.679145 ==
2579 15:36:04.682309 [Gating] SW mode calibration
2580 15:36:04.689251 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2581 15:36:04.695449 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2582 15:36:04.699100 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 15:36:04.702032 0 15 4 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
2584 15:36:04.708965 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 15:36:04.712727 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 15:36:04.716051 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 15:36:04.719119 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 15:36:04.725726 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 15:36:04.728980 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2590 15:36:04.732296 1 0 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (1 0)
2591 15:36:04.739511 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2592 15:36:04.742562 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 15:36:04.745672 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 15:36:04.752543 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 15:36:04.755716 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 15:36:04.758841 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 15:36:04.765769 1 0 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2598 15:36:04.768774 1 1 0 | B1->B0 | 2b2b 3939 | 0 0 | (1 1) (0 0)
2599 15:36:04.772727 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2600 15:36:04.778872 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 15:36:04.782197 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 15:36:04.785486 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 15:36:04.792521 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 15:36:04.795645 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 15:36:04.799523 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2606 15:36:04.802726 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2607 15:36:04.809171 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2608 15:36:04.812260 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 15:36:04.815724 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 15:36:04.822135 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 15:36:04.825613 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 15:36:04.829176 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 15:36:04.836283 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 15:36:04.839521 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 15:36:04.842544 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 15:36:04.849119 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 15:36:04.852285 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 15:36:04.856011 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 15:36:04.862646 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 15:36:04.865999 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 15:36:04.868987 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2622 15:36:04.875938 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2623 15:36:04.879004 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2624 15:36:04.882705 Total UI for P1: 0, mck2ui 16
2625 15:36:04.885753 best dqsien dly found for B0: ( 1, 3, 30)
2626 15:36:04.888946 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 15:36:04.892319 Total UI for P1: 0, mck2ui 16
2628 15:36:04.896150 best dqsien dly found for B1: ( 1, 4, 2)
2629 15:36:04.899393 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2630 15:36:04.902717 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2631 15:36:04.902797
2632 15:36:04.905838 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2633 15:36:04.909149 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2634 15:36:04.912521 [Gating] SW calibration Done
2635 15:36:04.912594 ==
2636 15:36:04.915655 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 15:36:04.922743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 15:36:04.922849 ==
2639 15:36:04.922950 RX Vref Scan: 0
2640 15:36:04.923039
2641 15:36:04.925754 RX Vref 0 -> 0, step: 1
2642 15:36:04.925861
2643 15:36:04.928918 RX Delay -40 -> 252, step: 8
2644 15:36:04.932578 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2645 15:36:04.935438 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2646 15:36:04.939198 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2647 15:36:04.945779 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2648 15:36:04.948754 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2649 15:36:04.952497 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2650 15:36:04.955767 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2651 15:36:04.958886 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2652 15:36:04.961890 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2653 15:36:04.968993 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2654 15:36:04.971994 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2655 15:36:04.975221 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2656 15:36:04.979024 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2657 15:36:04.982192 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2658 15:36:04.988516 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2659 15:36:04.992161 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2660 15:36:04.992246 ==
2661 15:36:04.995327 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 15:36:04.998554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 15:36:04.998635 ==
2664 15:36:05.002213 DQS Delay:
2665 15:36:05.002309 DQS0 = 0, DQS1 = 0
2666 15:36:05.002376 DQM Delay:
2667 15:36:05.005153 DQM0 = 113, DQM1 = 103
2668 15:36:05.005251 DQ Delay:
2669 15:36:05.009093 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =107
2670 15:36:05.012324 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2671 15:36:05.015657 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2672 15:36:05.018924 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2673 15:36:05.021988
2674 15:36:05.022085
2675 15:36:05.022154 ==
2676 15:36:05.025758 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 15:36:05.028924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 15:36:05.029017 ==
2679 15:36:05.029109
2680 15:36:05.029175
2681 15:36:05.032153 TX Vref Scan disable
2682 15:36:05.032247 == TX Byte 0 ==
2683 15:36:05.038927 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2684 15:36:05.041850 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2685 15:36:05.041957 == TX Byte 1 ==
2686 15:36:05.048964 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2687 15:36:05.051814 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2688 15:36:05.051915 ==
2689 15:36:05.055203 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 15:36:05.058521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 15:36:05.058656 ==
2692 15:36:05.071556 TX Vref=22, minBit 1, minWin=25, winSum=420
2693 15:36:05.074762 TX Vref=24, minBit 0, minWin=26, winSum=421
2694 15:36:05.078046 TX Vref=26, minBit 8, minWin=25, winSum=431
2695 15:36:05.081289 TX Vref=28, minBit 1, minWin=27, winSum=434
2696 15:36:05.084982 TX Vref=30, minBit 10, minWin=26, winSum=434
2697 15:36:05.091559 TX Vref=32, minBit 2, minWin=26, winSum=430
2698 15:36:05.094447 [TxChooseVref] Worse bit 1, Min win 27, Win sum 434, Final Vref 28
2699 15:36:05.094569
2700 15:36:05.097692 Final TX Range 1 Vref 28
2701 15:36:05.097777
2702 15:36:05.097846 ==
2703 15:36:05.101405 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 15:36:05.104672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 15:36:05.107917 ==
2706 15:36:05.108009
2707 15:36:05.108084
2708 15:36:05.108160 TX Vref Scan disable
2709 15:36:05.111589 == TX Byte 0 ==
2710 15:36:05.114756 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2711 15:36:05.117961 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2712 15:36:05.121287 == TX Byte 1 ==
2713 15:36:05.124385 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2714 15:36:05.127660 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2715 15:36:05.130914
2716 15:36:05.131001 [DATLAT]
2717 15:36:05.131074 Freq=1200, CH0 RK0
2718 15:36:05.131143
2719 15:36:05.134920 DATLAT Default: 0xd
2720 15:36:05.135054 0, 0xFFFF, sum = 0
2721 15:36:05.138017 1, 0xFFFF, sum = 0
2722 15:36:05.138126 2, 0xFFFF, sum = 0
2723 15:36:05.141168 3, 0xFFFF, sum = 0
2724 15:36:05.141275 4, 0xFFFF, sum = 0
2725 15:36:05.144424 5, 0xFFFF, sum = 0
2726 15:36:05.147562 6, 0xFFFF, sum = 0
2727 15:36:05.147642 7, 0xFFFF, sum = 0
2728 15:36:05.151443 8, 0xFFFF, sum = 0
2729 15:36:05.151556 9, 0xFFFF, sum = 0
2730 15:36:05.154623 10, 0xFFFF, sum = 0
2731 15:36:05.154699 11, 0xFFFF, sum = 0
2732 15:36:05.157697 12, 0x0, sum = 1
2733 15:36:05.157807 13, 0x0, sum = 2
2734 15:36:05.161460 14, 0x0, sum = 3
2735 15:36:05.161549 15, 0x0, sum = 4
2736 15:36:05.161616 best_step = 13
2737 15:36:05.164352
2738 15:36:05.164462 ==
2739 15:36:05.168006 Dram Type= 6, Freq= 0, CH_0, rank 0
2740 15:36:05.170955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2741 15:36:05.171091 ==
2742 15:36:05.171201 RX Vref Scan: 1
2743 15:36:05.171302
2744 15:36:05.174340 Set Vref Range= 32 -> 127
2745 15:36:05.174443
2746 15:36:05.177669 RX Vref 32 -> 127, step: 1
2747 15:36:05.177755
2748 15:36:05.180868 RX Delay -37 -> 252, step: 4
2749 15:36:05.180978
2750 15:36:05.184222 Set Vref, RX VrefLevel [Byte0]: 32
2751 15:36:05.187697 [Byte1]: 32
2752 15:36:05.187804
2753 15:36:05.191139 Set Vref, RX VrefLevel [Byte0]: 33
2754 15:36:05.194165 [Byte1]: 33
2755 15:36:05.198037
2756 15:36:05.198155 Set Vref, RX VrefLevel [Byte0]: 34
2757 15:36:05.201191 [Byte1]: 34
2758 15:36:05.206119
2759 15:36:05.206222 Set Vref, RX VrefLevel [Byte0]: 35
2760 15:36:05.209020 [Byte1]: 35
2761 15:36:05.214169
2762 15:36:05.214302 Set Vref, RX VrefLevel [Byte0]: 36
2763 15:36:05.217280 [Byte1]: 36
2764 15:36:05.221826
2765 15:36:05.221939 Set Vref, RX VrefLevel [Byte0]: 37
2766 15:36:05.225054 [Byte1]: 37
2767 15:36:05.229539
2768 15:36:05.229632 Set Vref, RX VrefLevel [Byte0]: 38
2769 15:36:05.233373 [Byte1]: 38
2770 15:36:05.237741
2771 15:36:05.237838 Set Vref, RX VrefLevel [Byte0]: 39
2772 15:36:05.240933 [Byte1]: 39
2773 15:36:05.246023
2774 15:36:05.246103 Set Vref, RX VrefLevel [Byte0]: 40
2775 15:36:05.249219 [Byte1]: 40
2776 15:36:05.253620
2777 15:36:05.253698 Set Vref, RX VrefLevel [Byte0]: 41
2778 15:36:05.257412 [Byte1]: 41
2779 15:36:05.261815
2780 15:36:05.261895 Set Vref, RX VrefLevel [Byte0]: 42
2781 15:36:05.265156 [Byte1]: 42
2782 15:36:05.270106
2783 15:36:05.270194 Set Vref, RX VrefLevel [Byte0]: 43
2784 15:36:05.273313 [Byte1]: 43
2785 15:36:05.277886
2786 15:36:05.277963 Set Vref, RX VrefLevel [Byte0]: 44
2787 15:36:05.281004 [Byte1]: 44
2788 15:36:05.285981
2789 15:36:05.286067 Set Vref, RX VrefLevel [Byte0]: 45
2790 15:36:05.289036 [Byte1]: 45
2791 15:36:05.293945
2792 15:36:05.294030 Set Vref, RX VrefLevel [Byte0]: 46
2793 15:36:05.297073 [Byte1]: 46
2794 15:36:05.302008
2795 15:36:05.302092 Set Vref, RX VrefLevel [Byte0]: 47
2796 15:36:05.304872 [Byte1]: 47
2797 15:36:05.310003
2798 15:36:05.310079 Set Vref, RX VrefLevel [Byte0]: 48
2799 15:36:05.313442 [Byte1]: 48
2800 15:36:05.318017
2801 15:36:05.318122 Set Vref, RX VrefLevel [Byte0]: 49
2802 15:36:05.321017 [Byte1]: 49
2803 15:36:05.325921
2804 15:36:05.326011 Set Vref, RX VrefLevel [Byte0]: 50
2805 15:36:05.329195 [Byte1]: 50
2806 15:36:05.333737
2807 15:36:05.333826 Set Vref, RX VrefLevel [Byte0]: 51
2808 15:36:05.336818 [Byte1]: 51
2809 15:36:05.342021
2810 15:36:05.342114 Set Vref, RX VrefLevel [Byte0]: 52
2811 15:36:05.345380 [Byte1]: 52
2812 15:36:05.349848
2813 15:36:05.349934 Set Vref, RX VrefLevel [Byte0]: 53
2814 15:36:05.353029 [Byte1]: 53
2815 15:36:05.358113
2816 15:36:05.358198 Set Vref, RX VrefLevel [Byte0]: 54
2817 15:36:05.361243 [Byte1]: 54
2818 15:36:05.365770
2819 15:36:05.365850 Set Vref, RX VrefLevel [Byte0]: 55
2820 15:36:05.368998 [Byte1]: 55
2821 15:36:05.373870
2822 15:36:05.373947 Set Vref, RX VrefLevel [Byte0]: 56
2823 15:36:05.377052 [Byte1]: 56
2824 15:36:05.382090
2825 15:36:05.382172 Set Vref, RX VrefLevel [Byte0]: 57
2826 15:36:05.385241 [Byte1]: 57
2827 15:36:05.389702
2828 15:36:05.389786 Set Vref, RX VrefLevel [Byte0]: 58
2829 15:36:05.393002 [Byte1]: 58
2830 15:36:05.398077
2831 15:36:05.398182 Set Vref, RX VrefLevel [Byte0]: 59
2832 15:36:05.401194 [Byte1]: 59
2833 15:36:05.405797
2834 15:36:05.405940 Set Vref, RX VrefLevel [Byte0]: 60
2835 15:36:05.409114 [Byte1]: 60
2836 15:36:05.413938
2837 15:36:05.414086 Set Vref, RX VrefLevel [Byte0]: 61
2838 15:36:05.417550 [Byte1]: 61
2839 15:36:05.421997
2840 15:36:05.422161 Set Vref, RX VrefLevel [Byte0]: 62
2841 15:36:05.425053 [Byte1]: 62
2842 15:36:05.429911
2843 15:36:05.430077 Set Vref, RX VrefLevel [Byte0]: 63
2844 15:36:05.433212 [Byte1]: 63
2845 15:36:05.437791
2846 15:36:05.437914 Set Vref, RX VrefLevel [Byte0]: 64
2847 15:36:05.441108 [Byte1]: 64
2848 15:36:05.445971
2849 15:36:05.446081 Set Vref, RX VrefLevel [Byte0]: 65
2850 15:36:05.449272 [Byte1]: 65
2851 15:36:05.453987
2852 15:36:05.454104 Set Vref, RX VrefLevel [Byte0]: 66
2853 15:36:05.457133 [Byte1]: 66
2854 15:36:05.461682
2855 15:36:05.461791 Set Vref, RX VrefLevel [Byte0]: 67
2856 15:36:05.465157 [Byte1]: 67
2857 15:36:05.469797
2858 15:36:05.469912 Set Vref, RX VrefLevel [Byte0]: 68
2859 15:36:05.472937 [Byte1]: 68
2860 15:36:05.477963
2861 15:36:05.478071 Set Vref, RX VrefLevel [Byte0]: 69
2862 15:36:05.481026 [Byte1]: 69
2863 15:36:05.486044
2864 15:36:05.486148 Set Vref, RX VrefLevel [Byte0]: 70
2865 15:36:05.489159 [Byte1]: 70
2866 15:36:05.493746
2867 15:36:05.493895 Set Vref, RX VrefLevel [Byte0]: 71
2868 15:36:05.497040 [Byte1]: 71
2869 15:36:05.502056
2870 15:36:05.502205 Set Vref, RX VrefLevel [Byte0]: 72
2871 15:36:05.505162 [Byte1]: 72
2872 15:36:05.509705
2873 15:36:05.509855 Set Vref, RX VrefLevel [Byte0]: 73
2874 15:36:05.513429 [Byte1]: 73
2875 15:36:05.518016
2876 15:36:05.518180 Set Vref, RX VrefLevel [Byte0]: 74
2877 15:36:05.521129 [Byte1]: 74
2878 15:36:05.525486
2879 15:36:05.525607 Final RX Vref Byte 0 = 60 to rank0
2880 15:36:05.529075 Final RX Vref Byte 1 = 58 to rank0
2881 15:36:05.532708 Final RX Vref Byte 0 = 60 to rank1
2882 15:36:05.535822 Final RX Vref Byte 1 = 58 to rank1==
2883 15:36:05.539625 Dram Type= 6, Freq= 0, CH_0, rank 0
2884 15:36:05.546050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 15:36:05.546171 ==
2886 15:36:05.546275 DQS Delay:
2887 15:36:05.546372 DQS0 = 0, DQS1 = 0
2888 15:36:05.549422 DQM Delay:
2889 15:36:05.549533 DQM0 = 111, DQM1 = 102
2890 15:36:05.552408 DQ Delay:
2891 15:36:05.556062 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2892 15:36:05.559059 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2893 15:36:05.562832 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2894 15:36:05.565918 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =108
2895 15:36:05.566029
2896 15:36:05.566129
2897 15:36:05.572469 [DQSOSCAuto] RK0, (LSB)MR18= 0xff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2898 15:36:05.576213 CH0 RK0: MR19=403, MR18=FF
2899 15:36:05.582784 CH0_RK0: MR19=0x403, MR18=0xFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2900 15:36:05.582935
2901 15:36:05.585978 ----->DramcWriteLeveling(PI) begin...
2902 15:36:05.586119 ==
2903 15:36:05.589074 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 15:36:05.592733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 15:36:05.592880 ==
2906 15:36:05.595983 Write leveling (Byte 0): 32 => 32
2907 15:36:05.599190 Write leveling (Byte 1): 31 => 31
2908 15:36:05.602563 DramcWriteLeveling(PI) end<-----
2909 15:36:05.602710
2910 15:36:05.602849 ==
2911 15:36:05.606100 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 15:36:05.609292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 15:36:05.609375 ==
2914 15:36:05.612530 [Gating] SW mode calibration
2915 15:36:05.619035 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2916 15:36:05.626021 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2917 15:36:05.629309 0 15 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2918 15:36:05.635570 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 15:36:05.638998 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 15:36:05.642605 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 15:36:05.648978 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 15:36:05.652135 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 15:36:05.655467 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
2924 15:36:05.662185 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
2925 15:36:05.665880 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2926 15:36:05.668849 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 15:36:05.672486 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 15:36:05.679140 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 15:36:05.682414 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 15:36:05.686138 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 15:36:05.692328 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
2932 15:36:05.696186 1 0 28 | B1->B0 | 2424 4343 | 0 1 | (0 0) (0 0)
2933 15:36:05.699330 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2934 15:36:05.705796 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 15:36:05.709060 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 15:36:05.712885 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 15:36:05.719357 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 15:36:05.722593 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 15:36:05.725734 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 15:36:05.732232 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2941 15:36:05.736198 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2942 15:36:05.739384 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 15:36:05.745600 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 15:36:05.748949 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 15:36:05.752526 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 15:36:05.758875 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 15:36:05.762188 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 15:36:05.765866 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 15:36:05.769052 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 15:36:05.776057 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 15:36:05.779105 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 15:36:05.782531 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 15:36:05.789111 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 15:36:05.792377 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 15:36:05.795530 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2956 15:36:05.802180 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2957 15:36:05.802258 Total UI for P1: 0, mck2ui 16
2958 15:36:05.809272 best dqsien dly found for B0: ( 1, 3, 24)
2959 15:36:05.812436 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 15:36:05.815613 Total UI for P1: 0, mck2ui 16
2961 15:36:05.819233 best dqsien dly found for B1: ( 1, 3, 30)
2962 15:36:05.822548 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2963 15:36:05.825880 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2964 15:36:05.825959
2965 15:36:05.829137 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2966 15:36:05.832236 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2967 15:36:05.836167 [Gating] SW calibration Done
2968 15:36:05.836244 ==
2969 15:36:05.839464 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 15:36:05.842643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 15:36:05.842716 ==
2972 15:36:05.846075 RX Vref Scan: 0
2973 15:36:05.846147
2974 15:36:05.849074 RX Vref 0 -> 0, step: 1
2975 15:36:05.849143
2976 15:36:05.849206 RX Delay -40 -> 252, step: 8
2977 15:36:05.855911 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2978 15:36:05.859455 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2979 15:36:05.862350 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2980 15:36:05.865922 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2981 15:36:05.869076 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2982 15:36:05.876276 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2983 15:36:05.879611 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2984 15:36:05.882798 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2985 15:36:05.886003 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2986 15:36:05.889188 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2987 15:36:05.896280 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2988 15:36:05.899115 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2989 15:36:05.902748 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2990 15:36:05.905967 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2991 15:36:05.909200 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2992 15:36:05.915721 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2993 15:36:05.915800 ==
2994 15:36:05.919545 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 15:36:05.922715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 15:36:05.922794 ==
2997 15:36:05.922856 DQS Delay:
2998 15:36:05.925986 DQS0 = 0, DQS1 = 0
2999 15:36:05.926076 DQM Delay:
3000 15:36:05.929702 DQM0 = 112, DQM1 = 102
3001 15:36:05.929777 DQ Delay:
3002 15:36:05.932949 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3003 15:36:05.936091 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
3004 15:36:05.939542 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3005 15:36:05.942577 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3006 15:36:05.942651
3007 15:36:05.942720
3008 15:36:05.942781 ==
3009 15:36:05.946448 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 15:36:05.952263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 15:36:05.952338 ==
3012 15:36:05.952408
3013 15:36:05.952487
3014 15:36:05.952547 TX Vref Scan disable
3015 15:36:05.956074 == TX Byte 0 ==
3016 15:36:05.959877 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3017 15:36:05.963063 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3018 15:36:05.966253 == TX Byte 1 ==
3019 15:36:05.969285 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3020 15:36:05.973121 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3021 15:36:05.976356 ==
3022 15:36:05.979266 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 15:36:05.982433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 15:36:05.982517 ==
3025 15:36:05.994134 TX Vref=22, minBit 0, minWin=26, winSum=426
3026 15:36:05.997360 TX Vref=24, minBit 5, minWin=26, winSum=429
3027 15:36:06.000724 TX Vref=26, minBit 1, minWin=27, winSum=439
3028 15:36:06.003909 TX Vref=28, minBit 1, minWin=27, winSum=443
3029 15:36:06.007074 TX Vref=30, minBit 1, minWin=27, winSum=442
3030 15:36:06.014087 TX Vref=32, minBit 13, minWin=26, winSum=439
3031 15:36:06.017357 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 28
3032 15:36:06.017437
3033 15:36:06.020614 Final TX Range 1 Vref 28
3034 15:36:06.020690
3035 15:36:06.020750 ==
3036 15:36:06.024226 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 15:36:06.027301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 15:36:06.027385 ==
3039 15:36:06.027450
3040 15:36:06.030579
3041 15:36:06.030653 TX Vref Scan disable
3042 15:36:06.033919 == TX Byte 0 ==
3043 15:36:06.037551 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3044 15:36:06.040712 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3045 15:36:06.043866 == TX Byte 1 ==
3046 15:36:06.047704 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3047 15:36:06.050826 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3048 15:36:06.050901
3049 15:36:06.054102 [DATLAT]
3050 15:36:06.054173 Freq=1200, CH0 RK1
3051 15:36:06.054238
3052 15:36:06.057472 DATLAT Default: 0xd
3053 15:36:06.057546 0, 0xFFFF, sum = 0
3054 15:36:06.060736 1, 0xFFFF, sum = 0
3055 15:36:06.060816 2, 0xFFFF, sum = 0
3056 15:36:06.063958 3, 0xFFFF, sum = 0
3057 15:36:06.064030 4, 0xFFFF, sum = 0
3058 15:36:06.067277 5, 0xFFFF, sum = 0
3059 15:36:06.067356 6, 0xFFFF, sum = 0
3060 15:36:06.070990 7, 0xFFFF, sum = 0
3061 15:36:06.071065 8, 0xFFFF, sum = 0
3062 15:36:06.074262 9, 0xFFFF, sum = 0
3063 15:36:06.077433 10, 0xFFFF, sum = 0
3064 15:36:06.077544 11, 0xFFFF, sum = 0
3065 15:36:06.080501 12, 0x0, sum = 1
3066 15:36:06.080608 13, 0x0, sum = 2
3067 15:36:06.084000 14, 0x0, sum = 3
3068 15:36:06.084088 15, 0x0, sum = 4
3069 15:36:06.084152 best_step = 13
3070 15:36:06.084219
3071 15:36:06.087310 ==
3072 15:36:06.087481 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 15:36:06.094056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 15:36:06.094159 ==
3075 15:36:06.094250 RX Vref Scan: 0
3076 15:36:06.094353
3077 15:36:06.097486 RX Vref 0 -> 0, step: 1
3078 15:36:06.097585
3079 15:36:06.100761 RX Delay -37 -> 252, step: 4
3080 15:36:06.103810 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3081 15:36:06.107637 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3082 15:36:06.114053 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3083 15:36:06.117336 iDelay=195, Bit 3, Center 110 (39 ~ 182) 144
3084 15:36:06.121132 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3085 15:36:06.124319 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3086 15:36:06.127692 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3087 15:36:06.134231 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3088 15:36:06.137387 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3089 15:36:06.140614 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3090 15:36:06.144283 iDelay=195, Bit 10, Center 102 (35 ~ 170) 136
3091 15:36:06.147708 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3092 15:36:06.154072 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3093 15:36:06.157479 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3094 15:36:06.160591 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3095 15:36:06.164031 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3096 15:36:06.164109 ==
3097 15:36:06.167309 Dram Type= 6, Freq= 0, CH_0, rank 1
3098 15:36:06.173797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 15:36:06.173944 ==
3100 15:36:06.174056 DQS Delay:
3101 15:36:06.174159 DQS0 = 0, DQS1 = 0
3102 15:36:06.177563 DQM Delay:
3103 15:36:06.177665 DQM0 = 110, DQM1 = 101
3104 15:36:06.180817 DQ Delay:
3105 15:36:06.184055 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =110
3106 15:36:06.187276 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3107 15:36:06.190984 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =94
3108 15:36:06.193993 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3109 15:36:06.194080
3110 15:36:06.194143
3111 15:36:06.200616 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3112 15:36:06.204276 CH0 RK1: MR19=403, MR18=14FD
3113 15:36:06.210821 CH0_RK1: MR19=0x403, MR18=0x14FD, DQSOSC=402, MR23=63, INC=40, DEC=27
3114 15:36:06.214187 [RxdqsGatingPostProcess] freq 1200
3115 15:36:06.220567 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3116 15:36:06.224150 best DQS0 dly(2T, 0.5T) = (0, 11)
3117 15:36:06.224274 best DQS1 dly(2T, 0.5T) = (0, 12)
3118 15:36:06.227483 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3119 15:36:06.230773 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3120 15:36:06.233971 best DQS0 dly(2T, 0.5T) = (0, 11)
3121 15:36:06.237302 best DQS1 dly(2T, 0.5T) = (0, 11)
3122 15:36:06.240590 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3123 15:36:06.243720 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3124 15:36:06.247690 Pre-setting of DQS Precalculation
3125 15:36:06.253830 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3126 15:36:06.253912 ==
3127 15:36:06.257091 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 15:36:06.260847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 15:36:06.260959 ==
3130 15:36:06.267257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3131 15:36:06.270451 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3132 15:36:06.280174 [CA 0] Center 37 (7~67) winsize 61
3133 15:36:06.283490 [CA 1] Center 37 (7~68) winsize 62
3134 15:36:06.286724 [CA 2] Center 34 (4~64) winsize 61
3135 15:36:06.289933 [CA 3] Center 33 (3~64) winsize 62
3136 15:36:06.293836 [CA 4] Center 34 (4~64) winsize 61
3137 15:36:06.297090 [CA 5] Center 33 (3~63) winsize 61
3138 15:36:06.297166
3139 15:36:06.300165 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3140 15:36:06.300264
3141 15:36:06.303367 [CATrainingPosCal] consider 1 rank data
3142 15:36:06.307009 u2DelayCellTimex100 = 270/100 ps
3143 15:36:06.309811 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3144 15:36:06.313464 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3145 15:36:06.320435 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3146 15:36:06.323824 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3147 15:36:06.326781 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 15:36:06.330018 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3149 15:36:06.330093
3150 15:36:06.333167 CA PerBit enable=1, Macro0, CA PI delay=33
3151 15:36:06.333271
3152 15:36:06.336980 [CBTSetCACLKResult] CA Dly = 33
3153 15:36:06.337078 CS Dly: 6 (0~37)
3154 15:36:06.337181 ==
3155 15:36:06.340120 Dram Type= 6, Freq= 0, CH_1, rank 1
3156 15:36:06.346519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 15:36:06.346594 ==
3158 15:36:06.349825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3159 15:36:06.356484 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3160 15:36:06.365522 [CA 0] Center 37 (7~67) winsize 61
3161 15:36:06.369320 [CA 1] Center 37 (7~68) winsize 62
3162 15:36:06.372524 [CA 2] Center 34 (4~65) winsize 62
3163 15:36:06.375767 [CA 3] Center 33 (3~64) winsize 62
3164 15:36:06.379567 [CA 4] Center 34 (4~64) winsize 61
3165 15:36:06.382173 [CA 5] Center 33 (3~63) winsize 61
3166 15:36:06.382292
3167 15:36:06.385967 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3168 15:36:06.386130
3169 15:36:06.389089 [CATrainingPosCal] consider 2 rank data
3170 15:36:06.392383 u2DelayCellTimex100 = 270/100 ps
3171 15:36:06.396057 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3172 15:36:06.399307 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3173 15:36:06.405446 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3174 15:36:06.409061 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3175 15:36:06.412531 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3176 15:36:06.415493 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3177 15:36:06.415573
3178 15:36:06.418765 CA PerBit enable=1, Macro0, CA PI delay=33
3179 15:36:06.418862
3180 15:36:06.422339 [CBTSetCACLKResult] CA Dly = 33
3181 15:36:06.422413 CS Dly: 7 (0~39)
3182 15:36:06.422484
3183 15:36:06.425356 ----->DramcWriteLeveling(PI) begin...
3184 15:36:06.429094 ==
3185 15:36:06.432269 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 15:36:06.435683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 15:36:06.435803 ==
3188 15:36:06.438663 Write leveling (Byte 0): 25 => 25
3189 15:36:06.442482 Write leveling (Byte 1): 30 => 30
3190 15:36:06.445765 DramcWriteLeveling(PI) end<-----
3191 15:36:06.445869
3192 15:36:06.445961 ==
3193 15:36:06.448900 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 15:36:06.452056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 15:36:06.452172 ==
3196 15:36:06.455953 [Gating] SW mode calibration
3197 15:36:06.462199 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3198 15:36:06.465952 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3199 15:36:06.472334 0 15 0 | B1->B0 | 302f 2a2a | 1 0 | (1 1) (0 0)
3200 15:36:06.475629 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 15:36:06.478925 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 15:36:06.485939 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 15:36:06.489008 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 15:36:06.492185 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 15:36:06.499231 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 15:36:06.502510 0 15 28 | B1->B0 | 2525 2727 | 0 0 | (1 0) (0 0)
3207 15:36:06.505810 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 15:36:06.512782 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 15:36:06.515796 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 15:36:06.518886 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 15:36:06.525546 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 15:36:06.529157 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 15:36:06.532184 1 0 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
3214 15:36:06.539289 1 0 28 | B1->B0 | 3f3f 3a3a | 0 0 | (0 0) (0 0)
3215 15:36:06.542965 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 15:36:06.545836 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 15:36:06.548979 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 15:36:06.555757 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 15:36:06.558821 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 15:36:06.562523 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 15:36:06.568951 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 15:36:06.572598 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3223 15:36:06.575610 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3224 15:36:06.582075 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 15:36:06.585364 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 15:36:06.588692 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 15:36:06.595936 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 15:36:06.599119 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 15:36:06.602252 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 15:36:06.608956 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 15:36:06.612157 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 15:36:06.615740 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 15:36:06.622216 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 15:36:06.625310 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 15:36:06.629177 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 15:36:06.635470 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 15:36:06.639181 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 15:36:06.642476 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3239 15:36:06.645751 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3240 15:36:06.652135 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3241 15:36:06.655875 Total UI for P1: 0, mck2ui 16
3242 15:36:06.658883 best dqsien dly found for B0: ( 1, 3, 30)
3243 15:36:06.662509 Total UI for P1: 0, mck2ui 16
3244 15:36:06.665940 best dqsien dly found for B1: ( 1, 3, 30)
3245 15:36:06.669078 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3246 15:36:06.672157 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3247 15:36:06.672256
3248 15:36:06.675859 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3249 15:36:06.679130 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3250 15:36:06.682613 [Gating] SW calibration Done
3251 15:36:06.682703 ==
3252 15:36:06.685883 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 15:36:06.688975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 15:36:06.689067 ==
3255 15:36:06.692158 RX Vref Scan: 0
3256 15:36:06.692239
3257 15:36:06.692301 RX Vref 0 -> 0, step: 1
3258 15:36:06.692359
3259 15:36:06.695472 RX Delay -40 -> 252, step: 8
3260 15:36:06.699230 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3261 15:36:06.705942 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3262 15:36:06.709066 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3263 15:36:06.712302 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3264 15:36:06.715477 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3265 15:36:06.719163 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3266 15:36:06.725690 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3267 15:36:06.728878 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3268 15:36:06.732880 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3269 15:36:06.735884 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3270 15:36:06.738948 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3271 15:36:06.745737 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3272 15:36:06.749070 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3273 15:36:06.752435 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3274 15:36:06.755651 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3275 15:36:06.758853 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3276 15:36:06.762623 ==
3277 15:36:06.765900 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 15:36:06.769082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 15:36:06.769173 ==
3280 15:36:06.769239 DQS Delay:
3281 15:36:06.772406 DQS0 = 0, DQS1 = 0
3282 15:36:06.772503 DQM Delay:
3283 15:36:06.775479 DQM0 = 114, DQM1 = 106
3284 15:36:06.775569 DQ Delay:
3285 15:36:06.778817 DQ0 =123, DQ1 =107, DQ2 =103, DQ3 =111
3286 15:36:06.782532 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3287 15:36:06.785446 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =103
3288 15:36:06.788924 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3289 15:36:06.788998
3290 15:36:06.789077
3291 15:36:06.789144 ==
3292 15:36:06.792191 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 15:36:06.798835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 15:36:06.798944 ==
3295 15:36:06.799037
3296 15:36:06.799135
3297 15:36:06.799228 TX Vref Scan disable
3298 15:36:06.802096 == TX Byte 0 ==
3299 15:36:06.805432 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3300 15:36:06.809141 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3301 15:36:06.812239 == TX Byte 1 ==
3302 15:36:06.815577 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3303 15:36:06.819193 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3304 15:36:06.822348 ==
3305 15:36:06.825511 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 15:36:06.828792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 15:36:06.828907 ==
3308 15:36:06.840595 TX Vref=22, minBit 1, minWin=25, winSum=414
3309 15:36:06.843811 TX Vref=24, minBit 8, minWin=25, winSum=418
3310 15:36:06.846898 TX Vref=26, minBit 8, minWin=25, winSum=422
3311 15:36:06.850378 TX Vref=28, minBit 1, minWin=26, winSum=428
3312 15:36:06.853659 TX Vref=30, minBit 1, minWin=26, winSum=430
3313 15:36:06.856809 TX Vref=32, minBit 9, minWin=25, winSum=426
3314 15:36:06.864040 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3315 15:36:06.864159
3316 15:36:06.867224 Final TX Range 1 Vref 30
3317 15:36:06.867331
3318 15:36:06.867432 ==
3319 15:36:06.870457 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 15:36:06.873687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 15:36:06.873767 ==
3322 15:36:06.876977
3323 15:36:06.877060
3324 15:36:06.877124 TX Vref Scan disable
3325 15:36:06.880208 == TX Byte 0 ==
3326 15:36:06.883573 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3327 15:36:06.886704 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3328 15:36:06.889993 == TX Byte 1 ==
3329 15:36:06.893706 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3330 15:36:06.897075 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3331 15:36:06.900144
3332 15:36:06.900217 [DATLAT]
3333 15:36:06.900294 Freq=1200, CH1 RK0
3334 15:36:06.900360
3335 15:36:06.903322 DATLAT Default: 0xd
3336 15:36:06.903454 0, 0xFFFF, sum = 0
3337 15:36:06.907069 1, 0xFFFF, sum = 0
3338 15:36:06.907141 2, 0xFFFF, sum = 0
3339 15:36:06.910319 3, 0xFFFF, sum = 0
3340 15:36:06.910421 4, 0xFFFF, sum = 0
3341 15:36:06.913442 5, 0xFFFF, sum = 0
3342 15:36:06.913513 6, 0xFFFF, sum = 0
3343 15:36:06.917082 7, 0xFFFF, sum = 0
3344 15:36:06.920517 8, 0xFFFF, sum = 0
3345 15:36:06.920590 9, 0xFFFF, sum = 0
3346 15:36:06.923763 10, 0xFFFF, sum = 0
3347 15:36:06.923863 11, 0xFFFF, sum = 0
3348 15:36:06.927087 12, 0x0, sum = 1
3349 15:36:06.927162 13, 0x0, sum = 2
3350 15:36:06.930353 14, 0x0, sum = 3
3351 15:36:06.930451 15, 0x0, sum = 4
3352 15:36:06.930543 best_step = 13
3353 15:36:06.930629
3354 15:36:06.933651 ==
3355 15:36:06.933724 Dram Type= 6, Freq= 0, CH_1, rank 0
3356 15:36:06.940105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3357 15:36:06.940181 ==
3358 15:36:06.940241 RX Vref Scan: 1
3359 15:36:06.940299
3360 15:36:06.943510 Set Vref Range= 32 -> 127
3361 15:36:06.943586
3362 15:36:06.947025 RX Vref 32 -> 127, step: 1
3363 15:36:06.947099
3364 15:36:06.950371 RX Delay -21 -> 252, step: 4
3365 15:36:06.950471
3366 15:36:06.953507 Set Vref, RX VrefLevel [Byte0]: 32
3367 15:36:06.956860 [Byte1]: 32
3368 15:36:06.956947
3369 15:36:06.959951 Set Vref, RX VrefLevel [Byte0]: 33
3370 15:36:06.963553 [Byte1]: 33
3371 15:36:06.966735
3372 15:36:06.966812 Set Vref, RX VrefLevel [Byte0]: 34
3373 15:36:06.969985 [Byte1]: 34
3374 15:36:06.974573
3375 15:36:06.974674 Set Vref, RX VrefLevel [Byte0]: 35
3376 15:36:06.977757 [Byte1]: 35
3377 15:36:06.982539
3378 15:36:06.982616 Set Vref, RX VrefLevel [Byte0]: 36
3379 15:36:06.985731 [Byte1]: 36
3380 15:36:06.990266
3381 15:36:06.990343 Set Vref, RX VrefLevel [Byte0]: 37
3382 15:36:06.993392 [Byte1]: 37
3383 15:36:06.997980
3384 15:36:06.998055 Set Vref, RX VrefLevel [Byte0]: 38
3385 15:36:07.001877 [Byte1]: 38
3386 15:36:07.006286
3387 15:36:07.006385 Set Vref, RX VrefLevel [Byte0]: 39
3388 15:36:07.009283 [Byte1]: 39
3389 15:36:07.014575
3390 15:36:07.014663 Set Vref, RX VrefLevel [Byte0]: 40
3391 15:36:07.017130 [Byte1]: 40
3392 15:36:07.022402
3393 15:36:07.022475 Set Vref, RX VrefLevel [Byte0]: 41
3394 15:36:07.025574 [Byte1]: 41
3395 15:36:07.030137
3396 15:36:07.030208 Set Vref, RX VrefLevel [Byte0]: 42
3397 15:36:07.033239 [Byte1]: 42
3398 15:36:07.037864
3399 15:36:07.037953 Set Vref, RX VrefLevel [Byte0]: 43
3400 15:36:07.041034 [Byte1]: 43
3401 15:36:07.045583
3402 15:36:07.045659 Set Vref, RX VrefLevel [Byte0]: 44
3403 15:36:07.049342 [Byte1]: 44
3404 15:36:07.053618
3405 15:36:07.053692 Set Vref, RX VrefLevel [Byte0]: 45
3406 15:36:07.057084 [Byte1]: 45
3407 15:36:07.061352
3408 15:36:07.061464 Set Vref, RX VrefLevel [Byte0]: 46
3409 15:36:07.064781 [Byte1]: 46
3410 15:36:07.069552
3411 15:36:07.069626 Set Vref, RX VrefLevel [Byte0]: 47
3412 15:36:07.072734 [Byte1]: 47
3413 15:36:07.077425
3414 15:36:07.077503 Set Vref, RX VrefLevel [Byte0]: 48
3415 15:36:07.081181 [Byte1]: 48
3416 15:36:07.085514
3417 15:36:07.085595 Set Vref, RX VrefLevel [Byte0]: 49
3418 15:36:07.088586 [Byte1]: 49
3419 15:36:07.093686
3420 15:36:07.093778 Set Vref, RX VrefLevel [Byte0]: 50
3421 15:36:07.096825 [Byte1]: 50
3422 15:36:07.101340
3423 15:36:07.101411 Set Vref, RX VrefLevel [Byte0]: 51
3424 15:36:07.104531 [Byte1]: 51
3425 15:36:07.109083
3426 15:36:07.109160 Set Vref, RX VrefLevel [Byte0]: 52
3427 15:36:07.112272 [Byte1]: 52
3428 15:36:07.117233
3429 15:36:07.117335 Set Vref, RX VrefLevel [Byte0]: 53
3430 15:36:07.120457 [Byte1]: 53
3431 15:36:07.125093
3432 15:36:07.125164 Set Vref, RX VrefLevel [Byte0]: 54
3433 15:36:07.128369 [Byte1]: 54
3434 15:36:07.132784
3435 15:36:07.132856 Set Vref, RX VrefLevel [Byte0]: 55
3436 15:36:07.135972 [Byte1]: 55
3437 15:36:07.141116
3438 15:36:07.141190 Set Vref, RX VrefLevel [Byte0]: 56
3439 15:36:07.144305 [Byte1]: 56
3440 15:36:07.148915
3441 15:36:07.148992 Set Vref, RX VrefLevel [Byte0]: 57
3442 15:36:07.152078 [Byte1]: 57
3443 15:36:07.156487
3444 15:36:07.156558 Set Vref, RX VrefLevel [Byte0]: 58
3445 15:36:07.160613 [Byte1]: 58
3446 15:36:07.164328
3447 15:36:07.164418 Set Vref, RX VrefLevel [Byte0]: 59
3448 15:36:07.168096 [Byte1]: 59
3449 15:36:07.172763
3450 15:36:07.172839 Set Vref, RX VrefLevel [Byte0]: 60
3451 15:36:07.175823 [Byte1]: 60
3452 15:36:07.180238
3453 15:36:07.180318 Set Vref, RX VrefLevel [Byte0]: 61
3454 15:36:07.183490 [Byte1]: 61
3455 15:36:07.188325
3456 15:36:07.188460 Set Vref, RX VrefLevel [Byte0]: 62
3457 15:36:07.191388 [Byte1]: 62
3458 15:36:07.196740
3459 15:36:07.196856 Set Vref, RX VrefLevel [Byte0]: 63
3460 15:36:07.199807 [Byte1]: 63
3461 15:36:07.203939
3462 15:36:07.204028 Set Vref, RX VrefLevel [Byte0]: 64
3463 15:36:07.207532 [Byte1]: 64
3464 15:36:07.212321
3465 15:36:07.212474 Set Vref, RX VrefLevel [Byte0]: 65
3466 15:36:07.215347 [Byte1]: 65
3467 15:36:07.219930
3468 15:36:07.220007 Set Vref, RX VrefLevel [Byte0]: 66
3469 15:36:07.223458 [Byte1]: 66
3470 15:36:07.227859
3471 15:36:07.227934 Set Vref, RX VrefLevel [Byte0]: 67
3472 15:36:07.231162 [Byte1]: 67
3473 15:36:07.235816
3474 15:36:07.235927 Set Vref, RX VrefLevel [Byte0]: 68
3475 15:36:07.238908 [Byte1]: 68
3476 15:36:07.244145
3477 15:36:07.244221 Set Vref, RX VrefLevel [Byte0]: 69
3478 15:36:07.247502 [Byte1]: 69
3479 15:36:07.251975
3480 15:36:07.252057 Final RX Vref Byte 0 = 56 to rank0
3481 15:36:07.255162 Final RX Vref Byte 1 = 55 to rank0
3482 15:36:07.258273 Final RX Vref Byte 0 = 56 to rank1
3483 15:36:07.261487 Final RX Vref Byte 1 = 55 to rank1==
3484 15:36:07.264890 Dram Type= 6, Freq= 0, CH_1, rank 0
3485 15:36:07.271955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 15:36:07.272199 ==
3487 15:36:07.272347 DQS Delay:
3488 15:36:07.272473 DQS0 = 0, DQS1 = 0
3489 15:36:07.275279 DQM Delay:
3490 15:36:07.275453 DQM0 = 115, DQM1 = 107
3491 15:36:07.278360 DQ Delay:
3492 15:36:07.282095 DQ0 =120, DQ1 =110, DQ2 =104, DQ3 =112
3493 15:36:07.285220 DQ4 =112, DQ5 =126, DQ6 =128, DQ7 =112
3494 15:36:07.288588 DQ8 =94, DQ9 =98, DQ10 =106, DQ11 =100
3495 15:36:07.291818 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =114
3496 15:36:07.291937
3497 15:36:07.292030
3498 15:36:07.298206 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3499 15:36:07.302166 CH1 RK0: MR19=303, MR18=ECF3
3500 15:36:07.308593 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3501 15:36:07.308686
3502 15:36:07.311634 ----->DramcWriteLeveling(PI) begin...
3503 15:36:07.311717 ==
3504 15:36:07.315159 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 15:36:07.318753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 15:36:07.321820 ==
3507 15:36:07.321902 Write leveling (Byte 0): 25 => 25
3508 15:36:07.324860 Write leveling (Byte 1): 30 => 30
3509 15:36:07.328520 DramcWriteLeveling(PI) end<-----
3510 15:36:07.328598
3511 15:36:07.328680 ==
3512 15:36:07.331517 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 15:36:07.338451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 15:36:07.338556 ==
3515 15:36:07.338650 [Gating] SW mode calibration
3516 15:36:07.348733 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3517 15:36:07.351584 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3518 15:36:07.355238 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 15:36:07.361607 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 15:36:07.365238 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 15:36:07.368452 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 15:36:07.375515 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 15:36:07.378745 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3524 15:36:07.382056 0 15 24 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
3525 15:36:07.388359 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3526 15:36:07.392155 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 15:36:07.394788 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 15:36:07.401807 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 15:36:07.405095 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 15:36:07.408222 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 15:36:07.415259 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3532 15:36:07.418623 1 0 24 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
3533 15:36:07.421638 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 15:36:07.428193 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 15:36:07.431992 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 15:36:07.435220 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 15:36:07.438346 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 15:36:07.445245 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 15:36:07.448261 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 15:36:07.451782 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3541 15:36:07.458671 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3542 15:36:07.461455 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 15:36:07.465076 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 15:36:07.471547 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 15:36:07.474825 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 15:36:07.478099 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 15:36:07.484612 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 15:36:07.488532 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 15:36:07.491619 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 15:36:07.498165 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 15:36:07.501459 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 15:36:07.504698 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 15:36:07.511182 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 15:36:07.515083 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 15:36:07.518436 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3556 15:36:07.524837 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3557 15:36:07.527995 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3558 15:36:07.531068 Total UI for P1: 0, mck2ui 16
3559 15:36:07.534902 best dqsien dly found for B0: ( 1, 3, 22)
3560 15:36:07.537710 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 15:36:07.541130 Total UI for P1: 0, mck2ui 16
3562 15:36:07.544336 best dqsien dly found for B1: ( 1, 3, 26)
3563 15:36:07.547605 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3564 15:36:07.551433 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3565 15:36:07.551574
3566 15:36:07.557731 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3567 15:36:07.561236 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3568 15:36:07.561358 [Gating] SW calibration Done
3569 15:36:07.564602 ==
3570 15:36:07.567723 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 15:36:07.570722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 15:36:07.570826 ==
3573 15:36:07.570928 RX Vref Scan: 0
3574 15:36:07.571041
3575 15:36:07.573974 RX Vref 0 -> 0, step: 1
3576 15:36:07.574083
3577 15:36:07.577732 RX Delay -40 -> 252, step: 8
3578 15:36:07.580988 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3579 15:36:07.583877 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3580 15:36:07.590926 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3581 15:36:07.593861 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3582 15:36:07.597657 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3583 15:36:07.600858 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3584 15:36:07.604087 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3585 15:36:07.610485 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3586 15:36:07.613679 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3587 15:36:07.616958 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3588 15:36:07.620892 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3589 15:36:07.624038 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3590 15:36:07.627524 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3591 15:36:07.634024 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3592 15:36:07.637027 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3593 15:36:07.640342 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3594 15:36:07.640417 ==
3595 15:36:07.643940 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 15:36:07.650191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 15:36:07.650269 ==
3598 15:36:07.650338 DQS Delay:
3599 15:36:07.650400 DQS0 = 0, DQS1 = 0
3600 15:36:07.653771 DQM Delay:
3601 15:36:07.653852 DQM0 = 110, DQM1 = 109
3602 15:36:07.656973 DQ Delay:
3603 15:36:07.660130 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3604 15:36:07.663435 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3605 15:36:07.666979 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3606 15:36:07.670091 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =115
3607 15:36:07.670239
3608 15:36:07.670336
3609 15:36:07.670425 ==
3610 15:36:07.673259 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 15:36:07.676923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 15:36:07.677049 ==
3613 15:36:07.677119
3614 15:36:07.680223
3615 15:36:07.680316 TX Vref Scan disable
3616 15:36:07.683447 == TX Byte 0 ==
3617 15:36:07.686678 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3618 15:36:07.689843 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3619 15:36:07.693681 == TX Byte 1 ==
3620 15:36:07.696729 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3621 15:36:07.700424 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3622 15:36:07.700505 ==
3623 15:36:07.703302 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 15:36:07.709816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 15:36:07.709961 ==
3626 15:36:07.740658 TX Vref=22, minBit 2, minWin=25, winSum=426
3627 15:36:07.740831 TX Vref=24, minBit 3, minWin=26, winSum=433
3628 15:36:07.740933 TX Vref=26, minBit 8, minWin=26, winSum=439
3629 15:36:07.741039 TX Vref=28, minBit 8, minWin=26, winSum=435
3630 15:36:07.741186 TX Vref=30, minBit 1, minWin=27, winSum=437
3631 15:36:07.741486 TX Vref=32, minBit 1, minWin=26, winSum=434
3632 15:36:07.743772 [TxChooseVref] Worse bit 1, Min win 27, Win sum 437, Final Vref 30
3633 15:36:07.743879
3634 15:36:07.747022 Final TX Range 1 Vref 30
3635 15:36:07.747122
3636 15:36:07.747280 ==
3637 15:36:07.751048 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 15:36:07.754200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 15:36:07.757141 ==
3640 15:36:07.757356
3641 15:36:07.757486
3642 15:36:07.757580 TX Vref Scan disable
3643 15:36:07.760740 == TX Byte 0 ==
3644 15:36:07.763708 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3645 15:36:07.770639 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3646 15:36:07.770738 == TX Byte 1 ==
3647 15:36:07.773883 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3648 15:36:07.780427 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3649 15:36:07.780510
3650 15:36:07.780574 [DATLAT]
3651 15:36:07.780638 Freq=1200, CH1 RK1
3652 15:36:07.780696
3653 15:36:07.783967 DATLAT Default: 0xd
3654 15:36:07.784052 0, 0xFFFF, sum = 0
3655 15:36:07.787123 1, 0xFFFF, sum = 0
3656 15:36:07.790315 2, 0xFFFF, sum = 0
3657 15:36:07.790398 3, 0xFFFF, sum = 0
3658 15:36:07.793683 4, 0xFFFF, sum = 0
3659 15:36:07.793766 5, 0xFFFF, sum = 0
3660 15:36:07.796764 6, 0xFFFF, sum = 0
3661 15:36:07.796849 7, 0xFFFF, sum = 0
3662 15:36:07.800039 8, 0xFFFF, sum = 0
3663 15:36:07.800125 9, 0xFFFF, sum = 0
3664 15:36:07.803332 10, 0xFFFF, sum = 0
3665 15:36:07.803426 11, 0xFFFF, sum = 0
3666 15:36:07.807127 12, 0x0, sum = 1
3667 15:36:07.807213 13, 0x0, sum = 2
3668 15:36:07.810171 14, 0x0, sum = 3
3669 15:36:07.810280 15, 0x0, sum = 4
3670 15:36:07.813788 best_step = 13
3671 15:36:07.813873
3672 15:36:07.813941 ==
3673 15:36:07.816687 Dram Type= 6, Freq= 0, CH_1, rank 1
3674 15:36:07.820069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3675 15:36:07.820152 ==
3676 15:36:07.820217 RX Vref Scan: 0
3677 15:36:07.820282
3678 15:36:07.823846 RX Vref 0 -> 0, step: 1
3679 15:36:07.823932
3680 15:36:07.826879 RX Delay -21 -> 252, step: 4
3681 15:36:07.830103 iDelay=195, Bit 0, Center 112 (39 ~ 186) 148
3682 15:36:07.836503 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3683 15:36:07.840250 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3684 15:36:07.843493 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3685 15:36:07.846599 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3686 15:36:07.849889 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3687 15:36:07.856350 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3688 15:36:07.860205 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3689 15:36:07.863553 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3690 15:36:07.866810 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3691 15:36:07.869716 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3692 15:36:07.876460 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3693 15:36:07.879964 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3694 15:36:07.883014 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3695 15:36:07.886136 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3696 15:36:07.893058 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3697 15:36:07.893147 ==
3698 15:36:07.896590 Dram Type= 6, Freq= 0, CH_1, rank 1
3699 15:36:07.899796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3700 15:36:07.899870 ==
3701 15:36:07.899932 DQS Delay:
3702 15:36:07.902815 DQS0 = 0, DQS1 = 0
3703 15:36:07.902924 DQM Delay:
3704 15:36:07.905997 DQM0 = 111, DQM1 = 111
3705 15:36:07.906094 DQ Delay:
3706 15:36:07.909989 DQ0 =112, DQ1 =110, DQ2 =102, DQ3 =108
3707 15:36:07.912653 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =108
3708 15:36:07.916534 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =104
3709 15:36:07.919718 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =122
3710 15:36:07.919819
3711 15:36:07.919913
3712 15:36:07.929353 [DQSOSCAuto] RK1, (LSB)MR18= 0xf707, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3713 15:36:07.932769 CH1 RK1: MR19=304, MR18=F707
3714 15:36:07.939549 CH1_RK1: MR19=0x304, MR18=0xF707, DQSOSC=407, MR23=63, INC=39, DEC=26
3715 15:36:07.939669 [RxdqsGatingPostProcess] freq 1200
3716 15:36:07.946032 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3717 15:36:07.949436 best DQS0 dly(2T, 0.5T) = (0, 11)
3718 15:36:07.952620 best DQS1 dly(2T, 0.5T) = (0, 11)
3719 15:36:07.955793 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3720 15:36:07.958931 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3721 15:36:07.962656 best DQS0 dly(2T, 0.5T) = (0, 11)
3722 15:36:07.965945 best DQS1 dly(2T, 0.5T) = (0, 11)
3723 15:36:07.969260 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3724 15:36:07.972391 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3725 15:36:07.975498 Pre-setting of DQS Precalculation
3726 15:36:07.978803 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3727 15:36:07.985447 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3728 15:36:07.995508 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3729 15:36:07.995604
3730 15:36:07.995670
3731 15:36:07.998582 [Calibration Summary] 2400 Mbps
3732 15:36:07.998654 CH 0, Rank 0
3733 15:36:08.002105 SW Impedance : PASS
3734 15:36:08.002185 DUTY Scan : NO K
3735 15:36:08.005351 ZQ Calibration : PASS
3736 15:36:08.008735 Jitter Meter : NO K
3737 15:36:08.008822 CBT Training : PASS
3738 15:36:08.011895 Write leveling : PASS
3739 15:36:08.011976 RX DQS gating : PASS
3740 15:36:08.015589 RX DQ/DQS(RDDQC) : PASS
3741 15:36:08.018712 TX DQ/DQS : PASS
3742 15:36:08.018784 RX DATLAT : PASS
3743 15:36:08.022022 RX DQ/DQS(Engine): PASS
3744 15:36:08.025631 TX OE : NO K
3745 15:36:08.025702 All Pass.
3746 15:36:08.025768
3747 15:36:08.025826 CH 0, Rank 1
3748 15:36:08.028878 SW Impedance : PASS
3749 15:36:08.032270 DUTY Scan : NO K
3750 15:36:08.032367 ZQ Calibration : PASS
3751 15:36:08.035527 Jitter Meter : NO K
3752 15:36:08.038496 CBT Training : PASS
3753 15:36:08.038594 Write leveling : PASS
3754 15:36:08.042008 RX DQS gating : PASS
3755 15:36:08.045646 RX DQ/DQS(RDDQC) : PASS
3756 15:36:08.045730 TX DQ/DQS : PASS
3757 15:36:08.048762 RX DATLAT : PASS
3758 15:36:08.051954 RX DQ/DQS(Engine): PASS
3759 15:36:08.052027 TX OE : NO K
3760 15:36:08.052089 All Pass.
3761 15:36:08.055303
3762 15:36:08.055419 CH 1, Rank 0
3763 15:36:08.058507 SW Impedance : PASS
3764 15:36:08.058619 DUTY Scan : NO K
3765 15:36:08.061737 ZQ Calibration : PASS
3766 15:36:08.061845 Jitter Meter : NO K
3767 15:36:08.065034 CBT Training : PASS
3768 15:36:08.068831 Write leveling : PASS
3769 15:36:08.068909 RX DQS gating : PASS
3770 15:36:08.071998 RX DQ/DQS(RDDQC) : PASS
3771 15:36:08.075288 TX DQ/DQS : PASS
3772 15:36:08.075445 RX DATLAT : PASS
3773 15:36:08.078481 RX DQ/DQS(Engine): PASS
3774 15:36:08.081757 TX OE : NO K
3775 15:36:08.081838 All Pass.
3776 15:36:08.081900
3777 15:36:08.081958 CH 1, Rank 1
3778 15:36:08.084986 SW Impedance : PASS
3779 15:36:08.088741 DUTY Scan : NO K
3780 15:36:08.088821 ZQ Calibration : PASS
3781 15:36:08.091551 Jitter Meter : NO K
3782 15:36:08.095359 CBT Training : PASS
3783 15:36:08.095497 Write leveling : PASS
3784 15:36:08.098543 RX DQS gating : PASS
3785 15:36:08.101628 RX DQ/DQS(RDDQC) : PASS
3786 15:36:08.101704 TX DQ/DQS : PASS
3787 15:36:08.104835 RX DATLAT : PASS
3788 15:36:08.108073 RX DQ/DQS(Engine): PASS
3789 15:36:08.108151 TX OE : NO K
3790 15:36:08.108212 All Pass.
3791 15:36:08.111843
3792 15:36:08.111911 DramC Write-DBI off
3793 15:36:08.114834 PER_BANK_REFRESH: Hybrid Mode
3794 15:36:08.114933 TX_TRACKING: ON
3795 15:36:08.125063 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3796 15:36:08.128227 [FAST_K] Save calibration result to emmc
3797 15:36:08.131510 dramc_set_vcore_voltage set vcore to 650000
3798 15:36:08.134637 Read voltage for 600, 5
3799 15:36:08.134709 Vio18 = 0
3800 15:36:08.138453 Vcore = 650000
3801 15:36:08.138525 Vdram = 0
3802 15:36:08.138585 Vddq = 0
3803 15:36:08.138643 Vmddr = 0
3804 15:36:08.144932 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3805 15:36:08.151716 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3806 15:36:08.151852 MEM_TYPE=3, freq_sel=19
3807 15:36:08.154895 sv_algorithm_assistance_LP4_1600
3808 15:36:08.158107 ============ PULL DRAM RESETB DOWN ============
3809 15:36:08.165038 ========== PULL DRAM RESETB DOWN end =========
3810 15:36:08.167807 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3811 15:36:08.171506 ===================================
3812 15:36:08.174700 LPDDR4 DRAM CONFIGURATION
3813 15:36:08.177965 ===================================
3814 15:36:08.178072 EX_ROW_EN[0] = 0x0
3815 15:36:08.181028 EX_ROW_EN[1] = 0x0
3816 15:36:08.184159 LP4Y_EN = 0x0
3817 15:36:08.184233 WORK_FSP = 0x0
3818 15:36:08.188116 WL = 0x2
3819 15:36:08.188222 RL = 0x2
3820 15:36:08.191297 BL = 0x2
3821 15:36:08.191429 RPST = 0x0
3822 15:36:08.194705 RD_PRE = 0x0
3823 15:36:08.194822 WR_PRE = 0x1
3824 15:36:08.197458 WR_PST = 0x0
3825 15:36:08.197563 DBI_WR = 0x0
3826 15:36:08.201105 DBI_RD = 0x0
3827 15:36:08.201211 OTF = 0x1
3828 15:36:08.204312 ===================================
3829 15:36:08.207517 ===================================
3830 15:36:08.210672 ANA top config
3831 15:36:08.213960 ===================================
3832 15:36:08.214048 DLL_ASYNC_EN = 0
3833 15:36:08.217244 ALL_SLAVE_EN = 1
3834 15:36:08.221040 NEW_RANK_MODE = 1
3835 15:36:08.224198 DLL_IDLE_MODE = 1
3836 15:36:08.227317 LP45_APHY_COMB_EN = 1
3837 15:36:08.227448 TX_ODT_DIS = 1
3838 15:36:08.230778 NEW_8X_MODE = 1
3839 15:36:08.234069 ===================================
3840 15:36:08.237195 ===================================
3841 15:36:08.240481 data_rate = 1200
3842 15:36:08.244288 CKR = 1
3843 15:36:08.247493 DQ_P2S_RATIO = 8
3844 15:36:08.250710 ===================================
3845 15:36:08.250818 CA_P2S_RATIO = 8
3846 15:36:08.253836 DQ_CA_OPEN = 0
3847 15:36:08.257520 DQ_SEMI_OPEN = 0
3848 15:36:08.260527 CA_SEMI_OPEN = 0
3849 15:36:08.263828 CA_FULL_RATE = 0
3850 15:36:08.267010 DQ_CKDIV4_EN = 1
3851 15:36:08.267093 CA_CKDIV4_EN = 1
3852 15:36:08.270168 CA_PREDIV_EN = 0
3853 15:36:08.273944 PH8_DLY = 0
3854 15:36:08.277226 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3855 15:36:08.280556 DQ_AAMCK_DIV = 4
3856 15:36:08.284020 CA_AAMCK_DIV = 4
3857 15:36:08.284138 CA_ADMCK_DIV = 4
3858 15:36:08.286976 DQ_TRACK_CA_EN = 0
3859 15:36:08.290222 CA_PICK = 600
3860 15:36:08.293566 CA_MCKIO = 600
3861 15:36:08.296850 MCKIO_SEMI = 0
3862 15:36:08.300073 PLL_FREQ = 2288
3863 15:36:08.303699 DQ_UI_PI_RATIO = 32
3864 15:36:08.303816 CA_UI_PI_RATIO = 0
3865 15:36:08.306684 ===================================
3866 15:36:08.310435 ===================================
3867 15:36:08.313630 memory_type:LPDDR4
3868 15:36:08.316747 GP_NUM : 10
3869 15:36:08.316822 SRAM_EN : 1
3870 15:36:08.320593 MD32_EN : 0
3871 15:36:08.323807 ===================================
3872 15:36:08.327029 [ANA_INIT] >>>>>>>>>>>>>>
3873 15:36:08.330056 <<<<<< [CONFIGURE PHASE]: ANA_TX
3874 15:36:08.333347 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3875 15:36:08.336547 ===================================
3876 15:36:08.336654 data_rate = 1200,PCW = 0X5800
3877 15:36:08.340270 ===================================
3878 15:36:08.346785 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3879 15:36:08.350055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3880 15:36:08.356328 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3881 15:36:08.359527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3882 15:36:08.363384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3883 15:36:08.366599 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3884 15:36:08.369949 [ANA_INIT] flow start
3885 15:36:08.373014 [ANA_INIT] PLL >>>>>>>>
3886 15:36:08.373092 [ANA_INIT] PLL <<<<<<<<
3887 15:36:08.376236 [ANA_INIT] MIDPI >>>>>>>>
3888 15:36:08.379593 [ANA_INIT] MIDPI <<<<<<<<
3889 15:36:08.379706 [ANA_INIT] DLL >>>>>>>>
3890 15:36:08.383316 [ANA_INIT] flow end
3891 15:36:08.386532 ============ LP4 DIFF to SE enter ============
3892 15:36:08.389766 ============ LP4 DIFF to SE exit ============
3893 15:36:08.392716 [ANA_INIT] <<<<<<<<<<<<<
3894 15:36:08.396323 [Flow] Enable top DCM control >>>>>
3895 15:36:08.399685 [Flow] Enable top DCM control <<<<<
3896 15:36:08.402947 Enable DLL master slave shuffle
3897 15:36:08.409945 ==============================================================
3898 15:36:08.410027 Gating Mode config
3899 15:36:08.416615 ==============================================================
3900 15:36:08.419735 Config description:
3901 15:36:08.426137 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3902 15:36:08.432540 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3903 15:36:08.439097 SELPH_MODE 0: By rank 1: By Phase
3904 15:36:08.446176 ==============================================================
3905 15:36:08.446278 GAT_TRACK_EN = 1
3906 15:36:08.449205 RX_GATING_MODE = 2
3907 15:36:08.452391 RX_GATING_TRACK_MODE = 2
3908 15:36:08.455963 SELPH_MODE = 1
3909 15:36:08.459023 PICG_EARLY_EN = 1
3910 15:36:08.462665 VALID_LAT_VALUE = 1
3911 15:36:08.469007 ==============================================================
3912 15:36:08.472331 Enter into Gating configuration >>>>
3913 15:36:08.475489 Exit from Gating configuration <<<<
3914 15:36:08.478804 Enter into DVFS_PRE_config >>>>>
3915 15:36:08.488977 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3916 15:36:08.492131 Exit from DVFS_PRE_config <<<<<
3917 15:36:08.495325 Enter into PICG configuration >>>>
3918 15:36:08.498594 Exit from PICG configuration <<<<
3919 15:36:08.501850 [RX_INPUT] configuration >>>>>
3920 15:36:08.505710 [RX_INPUT] configuration <<<<<
3921 15:36:08.508727 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3922 15:36:08.515337 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3923 15:36:08.521680 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3924 15:36:08.525152 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3925 15:36:08.532138 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3926 15:36:08.538576 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3927 15:36:08.541708 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3928 15:36:08.548182 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3929 15:36:08.551885 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3930 15:36:08.555130 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3931 15:36:08.558337 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3932 15:36:08.564763 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3933 15:36:08.568223 ===================================
3934 15:36:08.568304 LPDDR4 DRAM CONFIGURATION
3935 15:36:08.571841 ===================================
3936 15:36:08.574993 EX_ROW_EN[0] = 0x0
3937 15:36:08.578323 EX_ROW_EN[1] = 0x0
3938 15:36:08.578396 LP4Y_EN = 0x0
3939 15:36:08.581565 WORK_FSP = 0x0
3940 15:36:08.581641 WL = 0x2
3941 15:36:08.584778 RL = 0x2
3942 15:36:08.584850 BL = 0x2
3943 15:36:08.588194 RPST = 0x0
3944 15:36:08.588265 RD_PRE = 0x0
3945 15:36:08.591220 WR_PRE = 0x1
3946 15:36:08.591319 WR_PST = 0x0
3947 15:36:08.594531 DBI_WR = 0x0
3948 15:36:08.594602 DBI_RD = 0x0
3949 15:36:08.597712 OTF = 0x1
3950 15:36:08.601089 ===================================
3951 15:36:08.604920 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3952 15:36:08.607644 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3953 15:36:08.614635 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3954 15:36:08.617662 ===================================
3955 15:36:08.617750 LPDDR4 DRAM CONFIGURATION
3956 15:36:08.621366 ===================================
3957 15:36:08.624352 EX_ROW_EN[0] = 0x10
3958 15:36:08.628126 EX_ROW_EN[1] = 0x0
3959 15:36:08.628204 LP4Y_EN = 0x0
3960 15:36:08.630870 WORK_FSP = 0x0
3961 15:36:08.630949 WL = 0x2
3962 15:36:08.634340 RL = 0x2
3963 15:36:08.634419 BL = 0x2
3964 15:36:08.637520 RPST = 0x0
3965 15:36:08.637607 RD_PRE = 0x0
3966 15:36:08.641175 WR_PRE = 0x1
3967 15:36:08.641249 WR_PST = 0x0
3968 15:36:08.644564 DBI_WR = 0x0
3969 15:36:08.644633 DBI_RD = 0x0
3970 15:36:08.648019 OTF = 0x1
3971 15:36:08.651268 ===================================
3972 15:36:08.657659 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3973 15:36:08.660943 nWR fixed to 30
3974 15:36:08.661016 [ModeRegInit_LP4] CH0 RK0
3975 15:36:08.664241 [ModeRegInit_LP4] CH0 RK1
3976 15:36:08.667576 [ModeRegInit_LP4] CH1 RK0
3977 15:36:08.671061 [ModeRegInit_LP4] CH1 RK1
3978 15:36:08.671136 match AC timing 17
3979 15:36:08.677728 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3980 15:36:08.681302 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3981 15:36:08.684321 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3982 15:36:08.687650 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3983 15:36:08.694643 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3984 15:36:08.694747 ==
3985 15:36:08.697878 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 15:36:08.701106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 15:36:08.701181 ==
3988 15:36:08.707482 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3989 15:36:08.714442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3990 15:36:08.717742 [CA 0] Center 37 (7~67) winsize 61
3991 15:36:08.721092 [CA 1] Center 36 (6~67) winsize 62
3992 15:36:08.724494 [CA 2] Center 35 (5~65) winsize 61
3993 15:36:08.727543 [CA 3] Center 35 (5~65) winsize 61
3994 15:36:08.730746 [CA 4] Center 34 (4~65) winsize 62
3995 15:36:08.734095 [CA 5] Center 33 (3~64) winsize 62
3996 15:36:08.734168
3997 15:36:08.737336 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3998 15:36:08.737412
3999 15:36:08.741155 [CATrainingPosCal] consider 1 rank data
4000 15:36:08.744274 u2DelayCellTimex100 = 270/100 ps
4001 15:36:08.747847 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
4002 15:36:08.751077 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4003 15:36:08.754676 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4004 15:36:08.757920 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
4005 15:36:08.760847 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4006 15:36:08.764091 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4007 15:36:08.764196
4008 15:36:08.770821 CA PerBit enable=1, Macro0, CA PI delay=33
4009 15:36:08.770943
4010 15:36:08.771012 [CBTSetCACLKResult] CA Dly = 33
4011 15:36:08.774011 CS Dly: 7 (0~38)
4012 15:36:08.774097 ==
4013 15:36:08.777720 Dram Type= 6, Freq= 0, CH_0, rank 1
4014 15:36:08.781083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 15:36:08.781171 ==
4016 15:36:08.787208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4017 15:36:08.793740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4018 15:36:08.797553 [CA 0] Center 37 (7~67) winsize 61
4019 15:36:08.800716 [CA 1] Center 36 (6~67) winsize 62
4020 15:36:08.803945 [CA 2] Center 35 (5~65) winsize 61
4021 15:36:08.807324 [CA 3] Center 35 (5~65) winsize 61
4022 15:36:08.810495 [CA 4] Center 34 (4~64) winsize 61
4023 15:36:08.813801 [CA 5] Center 33 (3~64) winsize 62
4024 15:36:08.813874
4025 15:36:08.817100 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4026 15:36:08.817187
4027 15:36:08.820441 [CATrainingPosCal] consider 2 rank data
4028 15:36:08.823709 u2DelayCellTimex100 = 270/100 ps
4029 15:36:08.826852 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
4030 15:36:08.830630 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4031 15:36:08.833967 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4032 15:36:08.837151 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
4033 15:36:08.840462 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4034 15:36:08.846885 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4035 15:36:08.846990
4036 15:36:08.850195 CA PerBit enable=1, Macro0, CA PI delay=33
4037 15:36:08.850267
4038 15:36:08.853353 [CBTSetCACLKResult] CA Dly = 33
4039 15:36:08.853425 CS Dly: 7 (0~38)
4040 15:36:08.853485
4041 15:36:08.857043 ----->DramcWriteLeveling(PI) begin...
4042 15:36:08.857145 ==
4043 15:36:08.860330 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 15:36:08.866724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 15:36:08.866830 ==
4046 15:36:08.870564 Write leveling (Byte 0): 34 => 34
4047 15:36:08.870635 Write leveling (Byte 1): 30 => 30
4048 15:36:08.873744 DramcWriteLeveling(PI) end<-----
4049 15:36:08.873814
4050 15:36:08.873874 ==
4051 15:36:08.876695 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 15:36:08.883646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 15:36:08.883728 ==
4054 15:36:08.886927 [Gating] SW mode calibration
4055 15:36:08.893555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4056 15:36:08.896739 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4057 15:36:08.903419 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 15:36:08.906723 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 15:36:08.910134 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 15:36:08.916521 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4061 15:36:08.920343 0 9 16 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
4062 15:36:08.923648 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4063 15:36:08.930185 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 15:36:08.933418 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 15:36:08.936633 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 15:36:08.939949 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 15:36:08.946933 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 15:36:08.950143 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
4069 15:36:08.953447 0 10 16 | B1->B0 | 2c2c 4040 | 0 1 | (0 0) (0 0)
4070 15:36:08.959738 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 15:36:08.962956 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 15:36:08.966403 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 15:36:08.973288 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 15:36:08.976656 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 15:36:08.980085 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 15:36:08.986637 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4077 15:36:08.989656 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4078 15:36:08.993163 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 15:36:08.999916 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 15:36:09.002990 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 15:36:09.006003 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 15:36:09.012975 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 15:36:09.015856 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 15:36:09.019737 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 15:36:09.026489 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 15:36:09.029770 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 15:36:09.033409 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 15:36:09.039975 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 15:36:09.043267 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 15:36:09.046379 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 15:36:09.052877 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 15:36:09.056028 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 15:36:09.059314 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4094 15:36:09.063056 Total UI for P1: 0, mck2ui 16
4095 15:36:09.066183 best dqsien dly found for B0: ( 0, 13, 14)
4096 15:36:09.069434 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 15:36:09.072622 Total UI for P1: 0, mck2ui 16
4098 15:36:09.076227 best dqsien dly found for B1: ( 0, 13, 16)
4099 15:36:09.082699 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4100 15:36:09.085905 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4101 15:36:09.086013
4102 15:36:09.089048 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4103 15:36:09.092284 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4104 15:36:09.096094 [Gating] SW calibration Done
4105 15:36:09.096175 ==
4106 15:36:09.099100 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 15:36:09.102380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 15:36:09.102460 ==
4109 15:36:09.105646 RX Vref Scan: 0
4110 15:36:09.105723
4111 15:36:09.105790 RX Vref 0 -> 0, step: 1
4112 15:36:09.105849
4113 15:36:09.108823 RX Delay -230 -> 252, step: 16
4114 15:36:09.112684 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4115 15:36:09.119111 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4116 15:36:09.122308 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4117 15:36:09.125759 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4118 15:36:09.129005 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4119 15:36:09.135681 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4120 15:36:09.139226 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4121 15:36:09.142485 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4122 15:36:09.145881 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4123 15:36:09.149275 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4124 15:36:09.155674 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4125 15:36:09.158849 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4126 15:36:09.162137 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4127 15:36:09.165502 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4128 15:36:09.171813 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4129 15:36:09.175619 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4130 15:36:09.175693 ==
4131 15:36:09.178806 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 15:36:09.181840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 15:36:09.181948 ==
4134 15:36:09.185577 DQS Delay:
4135 15:36:09.185704 DQS0 = 0, DQS1 = 0
4136 15:36:09.188985 DQM Delay:
4137 15:36:09.189066 DQM0 = 34, DQM1 = 29
4138 15:36:09.189136 DQ Delay:
4139 15:36:09.192123 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4140 15:36:09.195306 DQ4 =33, DQ5 =25, DQ6 =41, DQ7 =41
4141 15:36:09.198566 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4142 15:36:09.202182 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4143 15:36:09.202307
4144 15:36:09.202409
4145 15:36:09.202520 ==
4146 15:36:09.205325 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 15:36:09.211789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 15:36:09.211873 ==
4149 15:36:09.211938
4150 15:36:09.211998
4151 15:36:09.212063 TX Vref Scan disable
4152 15:36:09.215765 == TX Byte 0 ==
4153 15:36:09.219496 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4154 15:36:09.225701 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4155 15:36:09.225788 == TX Byte 1 ==
4156 15:36:09.229574 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4157 15:36:09.235486 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4158 15:36:09.235563 ==
4159 15:36:09.239298 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 15:36:09.242604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 15:36:09.242680 ==
4162 15:36:09.242744
4163 15:36:09.242811
4164 15:36:09.245576 TX Vref Scan disable
4165 15:36:09.249505 == TX Byte 0 ==
4166 15:36:09.252234 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4167 15:36:09.255440 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4168 15:36:09.259181 == TX Byte 1 ==
4169 15:36:09.262274 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4170 15:36:09.265831 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4171 15:36:09.265910
4172 15:36:09.265974 [DATLAT]
4173 15:36:09.268816 Freq=600, CH0 RK0
4174 15:36:09.268891
4175 15:36:09.272442 DATLAT Default: 0x9
4176 15:36:09.272518 0, 0xFFFF, sum = 0
4177 15:36:09.275668 1, 0xFFFF, sum = 0
4178 15:36:09.275743 2, 0xFFFF, sum = 0
4179 15:36:09.278890 3, 0xFFFF, sum = 0
4180 15:36:09.278967 4, 0xFFFF, sum = 0
4181 15:36:09.282242 5, 0xFFFF, sum = 0
4182 15:36:09.282343 6, 0xFFFF, sum = 0
4183 15:36:09.285331 7, 0xFFFF, sum = 0
4184 15:36:09.285410 8, 0x0, sum = 1
4185 15:36:09.289148 9, 0x0, sum = 2
4186 15:36:09.289226 10, 0x0, sum = 3
4187 15:36:09.289290 11, 0x0, sum = 4
4188 15:36:09.292150 best_step = 9
4189 15:36:09.292251
4190 15:36:09.292324 ==
4191 15:36:09.295305 Dram Type= 6, Freq= 0, CH_0, rank 0
4192 15:36:09.298581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 15:36:09.298649 ==
4194 15:36:09.301814 RX Vref Scan: 1
4195 15:36:09.301882
4196 15:36:09.305796 RX Vref 0 -> 0, step: 1
4197 15:36:09.305867
4198 15:36:09.305925 RX Delay -195 -> 252, step: 8
4199 15:36:09.305982
4200 15:36:09.308728 Set Vref, RX VrefLevel [Byte0]: 60
4201 15:36:09.311723 [Byte1]: 58
4202 15:36:09.316824
4203 15:36:09.316899 Final RX Vref Byte 0 = 60 to rank0
4204 15:36:09.320085 Final RX Vref Byte 1 = 58 to rank0
4205 15:36:09.323403 Final RX Vref Byte 0 = 60 to rank1
4206 15:36:09.326499 Final RX Vref Byte 1 = 58 to rank1==
4207 15:36:09.329615 Dram Type= 6, Freq= 0, CH_0, rank 0
4208 15:36:09.336526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 15:36:09.336630 ==
4210 15:36:09.336721 DQS Delay:
4211 15:36:09.339801 DQS0 = 0, DQS1 = 0
4212 15:36:09.339880 DQM Delay:
4213 15:36:09.339943 DQM0 = 34, DQM1 = 28
4214 15:36:09.343009 DQ Delay:
4215 15:36:09.346326 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =28
4216 15:36:09.349517 DQ4 =36, DQ5 =20, DQ6 =40, DQ7 =44
4217 15:36:09.353194 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4218 15:36:09.356455 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4219 15:36:09.356527
4220 15:36:09.356587
4221 15:36:09.362604 [DQSOSCAuto] RK0, (LSB)MR18= 0x4241, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4222 15:36:09.365891 CH0 RK0: MR19=808, MR18=4241
4223 15:36:09.372532 CH0_RK0: MR19=0x808, MR18=0x4241, DQSOSC=397, MR23=63, INC=166, DEC=110
4224 15:36:09.372642
4225 15:36:09.376052 ----->DramcWriteLeveling(PI) begin...
4226 15:36:09.376155 ==
4227 15:36:09.379472 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 15:36:09.382501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 15:36:09.382576 ==
4230 15:36:09.386110 Write leveling (Byte 0): 33 => 33
4231 15:36:09.389324 Write leveling (Byte 1): 31 => 31
4232 15:36:09.392516 DramcWriteLeveling(PI) end<-----
4233 15:36:09.392592
4234 15:36:09.392655 ==
4235 15:36:09.395656 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 15:36:09.399583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 15:36:09.399711 ==
4238 15:36:09.402677 [Gating] SW mode calibration
4239 15:36:09.409067 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4240 15:36:09.416141 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4241 15:36:09.419154 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4242 15:36:09.425693 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 15:36:09.429000 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 15:36:09.432898 0 9 12 | B1->B0 | 3333 2f2f | 0 1 | (0 0) (1 0)
4245 15:36:09.438965 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
4246 15:36:09.442396 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 15:36:09.445595 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 15:36:09.452108 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 15:36:09.455839 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 15:36:09.458911 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 15:36:09.465284 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 15:36:09.468822 0 10 12 | B1->B0 | 2c2c 3232 | 0 0 | (1 1) (1 1)
4253 15:36:09.472169 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4254 15:36:09.475893 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 15:36:09.482040 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 15:36:09.485786 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 15:36:09.488843 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 15:36:09.495516 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 15:36:09.498742 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 15:36:09.502005 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4261 15:36:09.508984 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4262 15:36:09.512232 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 15:36:09.514960 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 15:36:09.522026 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 15:36:09.524995 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 15:36:09.528241 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 15:36:09.535213 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 15:36:09.538388 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 15:36:09.541585 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 15:36:09.548559 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 15:36:09.551711 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 15:36:09.554932 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 15:36:09.561359 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 15:36:09.564532 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 15:36:09.568286 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 15:36:09.574752 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4277 15:36:09.577875 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4278 15:36:09.581033 Total UI for P1: 0, mck2ui 16
4279 15:36:09.584352 best dqsien dly found for B0: ( 0, 13, 12)
4280 15:36:09.587955 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 15:36:09.591248 Total UI for P1: 0, mck2ui 16
4282 15:36:09.594387 best dqsien dly found for B1: ( 0, 13, 16)
4283 15:36:09.597731 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4284 15:36:09.604680 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4285 15:36:09.604762
4286 15:36:09.607962 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4287 15:36:09.610989 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4288 15:36:09.614202 [Gating] SW calibration Done
4289 15:36:09.614276 ==
4290 15:36:09.617478 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 15:36:09.620665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 15:36:09.620735 ==
4293 15:36:09.620795 RX Vref Scan: 0
4294 15:36:09.624516
4295 15:36:09.624587 RX Vref 0 -> 0, step: 1
4296 15:36:09.624647
4297 15:36:09.627755 RX Delay -230 -> 252, step: 16
4298 15:36:09.630589 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4299 15:36:09.637542 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4300 15:36:09.640708 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4301 15:36:09.644035 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4302 15:36:09.647080 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4303 15:36:09.650772 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4304 15:36:09.657219 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4305 15:36:09.660339 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4306 15:36:09.664155 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4307 15:36:09.667308 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4308 15:36:09.673618 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4309 15:36:09.677436 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4310 15:36:09.680696 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4311 15:36:09.683864 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4312 15:36:09.690195 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4313 15:36:09.693921 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4314 15:36:09.694003 ==
4315 15:36:09.697044 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 15:36:09.700220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 15:36:09.700301 ==
4318 15:36:09.703579 DQS Delay:
4319 15:36:09.703674 DQS0 = 0, DQS1 = 0
4320 15:36:09.703742 DQM Delay:
4321 15:36:09.706718 DQM0 = 40, DQM1 = 29
4322 15:36:09.706840 DQ Delay:
4323 15:36:09.710554 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4324 15:36:09.713805 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4325 15:36:09.716855 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4326 15:36:09.720021 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4327 15:36:09.720102
4328 15:36:09.720232
4329 15:36:09.720337 ==
4330 15:36:09.723222 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 15:36:09.730217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 15:36:09.730327 ==
4333 15:36:09.730453
4334 15:36:09.730541
4335 15:36:09.730614 TX Vref Scan disable
4336 15:36:09.734000 == TX Byte 0 ==
4337 15:36:09.737083 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4338 15:36:09.740575 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4339 15:36:09.743787 == TX Byte 1 ==
4340 15:36:09.747318 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4341 15:36:09.753992 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4342 15:36:09.754073 ==
4343 15:36:09.757273 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 15:36:09.760623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 15:36:09.760704 ==
4346 15:36:09.760768
4347 15:36:09.760826
4348 15:36:09.763853 TX Vref Scan disable
4349 15:36:09.767046 == TX Byte 0 ==
4350 15:36:09.770957 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4351 15:36:09.774037 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4352 15:36:09.777320 == TX Byte 1 ==
4353 15:36:09.780468 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4354 15:36:09.784048 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4355 15:36:09.784131
4356 15:36:09.784205 [DATLAT]
4357 15:36:09.787332 Freq=600, CH0 RK1
4358 15:36:09.787438
4359 15:36:09.787515 DATLAT Default: 0x9
4360 15:36:09.790562 0, 0xFFFF, sum = 0
4361 15:36:09.793808 1, 0xFFFF, sum = 0
4362 15:36:09.793889 2, 0xFFFF, sum = 0
4363 15:36:09.797128 3, 0xFFFF, sum = 0
4364 15:36:09.797222 4, 0xFFFF, sum = 0
4365 15:36:09.800229 5, 0xFFFF, sum = 0
4366 15:36:09.800311 6, 0xFFFF, sum = 0
4367 15:36:09.803733 7, 0xFFFF, sum = 0
4368 15:36:09.803814 8, 0x0, sum = 1
4369 15:36:09.806785 9, 0x0, sum = 2
4370 15:36:09.806868 10, 0x0, sum = 3
4371 15:36:09.806967 11, 0x0, sum = 4
4372 15:36:09.809961 best_step = 9
4373 15:36:09.810055
4374 15:36:09.810120 ==
4375 15:36:09.813779 Dram Type= 6, Freq= 0, CH_0, rank 1
4376 15:36:09.816807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 15:36:09.816897 ==
4378 15:36:09.820034 RX Vref Scan: 0
4379 15:36:09.820126
4380 15:36:09.820190 RX Vref 0 -> 0, step: 1
4381 15:36:09.823213
4382 15:36:09.823292 RX Delay -195 -> 252, step: 8
4383 15:36:09.831351 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4384 15:36:09.834131 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4385 15:36:09.837963 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4386 15:36:09.841149 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4387 15:36:09.847920 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4388 15:36:09.851009 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4389 15:36:09.854124 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4390 15:36:09.857700 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4391 15:36:09.864031 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4392 15:36:09.867245 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4393 15:36:09.870539 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4394 15:36:09.873887 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4395 15:36:09.877480 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4396 15:36:09.884031 iDelay=205, Bit 13, Center 32 (-131 ~ 196) 328
4397 15:36:09.887192 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4398 15:36:09.890959 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4399 15:36:09.891036 ==
4400 15:36:09.894154 Dram Type= 6, Freq= 0, CH_0, rank 1
4401 15:36:09.900604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 15:36:09.900679 ==
4403 15:36:09.900756 DQS Delay:
4404 15:36:09.900857 DQS0 = 0, DQS1 = 0
4405 15:36:09.903715 DQM Delay:
4406 15:36:09.903784 DQM0 = 34, DQM1 = 27
4407 15:36:09.907543 DQ Delay:
4408 15:36:09.910548 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4409 15:36:09.910619 DQ4 =36, DQ5 =20, DQ6 =44, DQ7 =44
4410 15:36:09.914208 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4411 15:36:09.917028 DQ12 =32, DQ13 =32, DQ14 =36, DQ15 =36
4412 15:36:09.920483
4413 15:36:09.920557
4414 15:36:09.927125 [DQSOSCAuto] RK1, (LSB)MR18= 0x7240, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4415 15:36:09.930200 CH0 RK1: MR19=808, MR18=7240
4416 15:36:09.937124 CH0_RK1: MR19=0x808, MR18=0x7240, DQSOSC=388, MR23=63, INC=174, DEC=116
4417 15:36:09.940948 [RxdqsGatingPostProcess] freq 600
4418 15:36:09.943552 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4419 15:36:09.947274 Pre-setting of DQS Precalculation
4420 15:36:09.953557 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4421 15:36:09.953656 ==
4422 15:36:09.957255 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 15:36:09.960389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 15:36:09.960487 ==
4425 15:36:09.966869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 15:36:09.969977 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4427 15:36:09.974360 [CA 0] Center 35 (5~66) winsize 62
4428 15:36:09.978211 [CA 1] Center 35 (5~66) winsize 62
4429 15:36:09.981371 [CA 2] Center 34 (4~65) winsize 62
4430 15:36:09.984450 [CA 3] Center 34 (3~65) winsize 63
4431 15:36:09.988244 [CA 4] Center 34 (4~65) winsize 62
4432 15:36:09.991174 [CA 5] Center 33 (3~64) winsize 62
4433 15:36:09.991282
4434 15:36:09.994877 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4435 15:36:09.994959
4436 15:36:09.998046 [CATrainingPosCal] consider 1 rank data
4437 15:36:10.001143 u2DelayCellTimex100 = 270/100 ps
4438 15:36:10.004396 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 15:36:10.007526 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 15:36:10.014606 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4441 15:36:10.018203 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4442 15:36:10.021289 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4443 15:36:10.024282 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 15:36:10.024365
4445 15:36:10.028025 CA PerBit enable=1, Macro0, CA PI delay=33
4446 15:36:10.028108
4447 15:36:10.031002 [CBTSetCACLKResult] CA Dly = 33
4448 15:36:10.031085 CS Dly: 5 (0~36)
4449 15:36:10.034816 ==
4450 15:36:10.034926 Dram Type= 6, Freq= 0, CH_1, rank 1
4451 15:36:10.041035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 15:36:10.041116 ==
4453 15:36:10.044092 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4454 15:36:10.050950 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4455 15:36:10.054657 [CA 0] Center 36 (6~66) winsize 61
4456 15:36:10.057842 [CA 1] Center 36 (6~66) winsize 61
4457 15:36:10.061598 [CA 2] Center 34 (4~65) winsize 62
4458 15:36:10.064738 [CA 3] Center 34 (3~65) winsize 63
4459 15:36:10.067968 [CA 4] Center 34 (4~65) winsize 62
4460 15:36:10.071419 [CA 5] Center 33 (3~64) winsize 62
4461 15:36:10.071504
4462 15:36:10.074392 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4463 15:36:10.074476
4464 15:36:10.077618 [CATrainingPosCal] consider 2 rank data
4465 15:36:10.081483 u2DelayCellTimex100 = 270/100 ps
4466 15:36:10.084612 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4467 15:36:10.090848 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4468 15:36:10.094887 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4469 15:36:10.097890 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4470 15:36:10.100983 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4471 15:36:10.104263 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4472 15:36:10.104343
4473 15:36:10.107550 CA PerBit enable=1, Macro0, CA PI delay=33
4474 15:36:10.107627
4475 15:36:10.110716 [CBTSetCACLKResult] CA Dly = 33
4476 15:36:10.114412 CS Dly: 5 (0~36)
4477 15:36:10.114496
4478 15:36:10.117725 ----->DramcWriteLeveling(PI) begin...
4479 15:36:10.117812 ==
4480 15:36:10.120784 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 15:36:10.124009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 15:36:10.124094 ==
4483 15:36:10.127573 Write leveling (Byte 0): 30 => 30
4484 15:36:10.130608 Write leveling (Byte 1): 33 => 33
4485 15:36:10.134380 DramcWriteLeveling(PI) end<-----
4486 15:36:10.134465
4487 15:36:10.134530 ==
4488 15:36:10.137346 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 15:36:10.140594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 15:36:10.140683 ==
4491 15:36:10.144350 [Gating] SW mode calibration
4492 15:36:10.150477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4493 15:36:10.157405 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4494 15:36:10.160356 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4495 15:36:10.164038 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 15:36:10.170288 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4497 15:36:10.174084 0 9 12 | B1->B0 | 3333 3030 | 0 0 | (0 0) (1 0)
4498 15:36:10.176885 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 15:36:10.184090 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 15:36:10.187283 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 15:36:10.190486 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 15:36:10.196694 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 15:36:10.200496 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 15:36:10.203658 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 15:36:10.210654 0 10 12 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (0 0)
4506 15:36:10.213674 0 10 16 | B1->B0 | 4545 4242 | 0 1 | (0 0) (0 0)
4507 15:36:10.216924 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 15:36:10.223833 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 15:36:10.227041 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 15:36:10.230131 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 15:36:10.233562 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 15:36:10.240355 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 15:36:10.243476 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4514 15:36:10.246910 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 15:36:10.253417 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 15:36:10.256621 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 15:36:10.260293 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 15:36:10.266439 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 15:36:10.269661 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 15:36:10.273301 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 15:36:10.279736 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 15:36:10.283593 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 15:36:10.286769 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 15:36:10.293268 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 15:36:10.296306 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 15:36:10.300087 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 15:36:10.306197 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 15:36:10.310043 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 15:36:10.313264 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4530 15:36:10.316439 Total UI for P1: 0, mck2ui 16
4531 15:36:10.319750 best dqsien dly found for B0: ( 0, 13, 10)
4532 15:36:10.326063 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 15:36:10.326152 Total UI for P1: 0, mck2ui 16
4534 15:36:10.333293 best dqsien dly found for B1: ( 0, 13, 12)
4535 15:36:10.336336 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4536 15:36:10.339227 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4537 15:36:10.339313
4538 15:36:10.342836 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4539 15:36:10.346118 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4540 15:36:10.349710 [Gating] SW calibration Done
4541 15:36:10.349807 ==
4542 15:36:10.352844 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 15:36:10.356458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 15:36:10.356544 ==
4545 15:36:10.359787 RX Vref Scan: 0
4546 15:36:10.359873
4547 15:36:10.359939 RX Vref 0 -> 0, step: 1
4548 15:36:10.362774
4549 15:36:10.362858 RX Delay -230 -> 252, step: 16
4550 15:36:10.369538 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4551 15:36:10.372675 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4552 15:36:10.375759 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4553 15:36:10.379024 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4554 15:36:10.385863 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4555 15:36:10.388964 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4556 15:36:10.392474 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4557 15:36:10.395604 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4558 15:36:10.398865 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4559 15:36:10.405816 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4560 15:36:10.408922 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4561 15:36:10.412193 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4562 15:36:10.415428 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4563 15:36:10.421865 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4564 15:36:10.425591 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4565 15:36:10.428981 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4566 15:36:10.429072 ==
4567 15:36:10.432153 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 15:36:10.438378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 15:36:10.438499 ==
4570 15:36:10.438603 DQS Delay:
4571 15:36:10.438693 DQS0 = 0, DQS1 = 0
4572 15:36:10.441623 DQM Delay:
4573 15:36:10.441708 DQM0 = 38, DQM1 = 29
4574 15:36:10.445264 DQ Delay:
4575 15:36:10.448305 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4576 15:36:10.451915 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4577 15:36:10.455096 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4578 15:36:10.458414 DQ12 =41, DQ13 =33, DQ14 =33, DQ15 =33
4579 15:36:10.458500
4580 15:36:10.458567
4581 15:36:10.458628 ==
4582 15:36:10.462159 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 15:36:10.465214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 15:36:10.465301 ==
4585 15:36:10.465367
4586 15:36:10.465429
4587 15:36:10.468381 TX Vref Scan disable
4588 15:36:10.468467 == TX Byte 0 ==
4589 15:36:10.474672 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4590 15:36:10.478486 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4591 15:36:10.481706 == TX Byte 1 ==
4592 15:36:10.484860 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4593 15:36:10.488080 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4594 15:36:10.488183 ==
4595 15:36:10.491518 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 15:36:10.494635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 15:36:10.494723 ==
4598 15:36:10.497751
4599 15:36:10.497835
4600 15:36:10.497902 TX Vref Scan disable
4601 15:36:10.501598 == TX Byte 0 ==
4602 15:36:10.504783 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4603 15:36:10.511644 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4604 15:36:10.511733 == TX Byte 1 ==
4605 15:36:10.514941 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4606 15:36:10.521845 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4607 15:36:10.521933
4608 15:36:10.522001 [DATLAT]
4609 15:36:10.522064 Freq=600, CH1 RK0
4610 15:36:10.522125
4611 15:36:10.525117 DATLAT Default: 0x9
4612 15:36:10.525201 0, 0xFFFF, sum = 0
4613 15:36:10.528357 1, 0xFFFF, sum = 0
4614 15:36:10.528442 2, 0xFFFF, sum = 0
4615 15:36:10.531472 3, 0xFFFF, sum = 0
4616 15:36:10.534854 4, 0xFFFF, sum = 0
4617 15:36:10.534945 5, 0xFFFF, sum = 0
4618 15:36:10.537928 6, 0xFFFF, sum = 0
4619 15:36:10.538031 7, 0xFFFF, sum = 0
4620 15:36:10.541774 8, 0x0, sum = 1
4621 15:36:10.541860 9, 0x0, sum = 2
4622 15:36:10.541928 10, 0x0, sum = 3
4623 15:36:10.545074 11, 0x0, sum = 4
4624 15:36:10.545160 best_step = 9
4625 15:36:10.545227
4626 15:36:10.545289 ==
4627 15:36:10.548119 Dram Type= 6, Freq= 0, CH_1, rank 0
4628 15:36:10.554820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 15:36:10.554951 ==
4630 15:36:10.555065 RX Vref Scan: 1
4631 15:36:10.555179
4632 15:36:10.558545 RX Vref 0 -> 0, step: 1
4633 15:36:10.558647
4634 15:36:10.561652 RX Delay -195 -> 252, step: 8
4635 15:36:10.561755
4636 15:36:10.564785 Set Vref, RX VrefLevel [Byte0]: 56
4637 15:36:10.567902 [Byte1]: 55
4638 15:36:10.568018
4639 15:36:10.570856 Final RX Vref Byte 0 = 56 to rank0
4640 15:36:10.574791 Final RX Vref Byte 1 = 55 to rank0
4641 15:36:10.577881 Final RX Vref Byte 0 = 56 to rank1
4642 15:36:10.580934 Final RX Vref Byte 1 = 55 to rank1==
4643 15:36:10.584460 Dram Type= 6, Freq= 0, CH_1, rank 0
4644 15:36:10.587537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 15:36:10.587631 ==
4646 15:36:10.591523 DQS Delay:
4647 15:36:10.591610 DQS0 = 0, DQS1 = 0
4648 15:36:10.594560 DQM Delay:
4649 15:36:10.594641 DQM0 = 40, DQM1 = 28
4650 15:36:10.594728 DQ Delay:
4651 15:36:10.597439 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4652 15:36:10.601033 DQ4 =36, DQ5 =52, DQ6 =52, DQ7 =36
4653 15:36:10.604301 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4654 15:36:10.607461 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4655 15:36:10.607581
4656 15:36:10.607669
4657 15:36:10.617382 [DQSOSCAuto] RK0, (LSB)MR18= 0x2937, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
4658 15:36:10.621053 CH1 RK0: MR19=808, MR18=2937
4659 15:36:10.627573 CH1_RK0: MR19=0x808, MR18=0x2937, DQSOSC=399, MR23=63, INC=164, DEC=109
4660 15:36:10.627659
4661 15:36:10.630774 ----->DramcWriteLeveling(PI) begin...
4662 15:36:10.630883 ==
4663 15:36:10.634567 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 15:36:10.637520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 15:36:10.637627 ==
4666 15:36:10.640756 Write leveling (Byte 0): 29 => 29
4667 15:36:10.644517 Write leveling (Byte 1): 29 => 29
4668 15:36:10.647791 DramcWriteLeveling(PI) end<-----
4669 15:36:10.647872
4670 15:36:10.647937 ==
4671 15:36:10.650916 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 15:36:10.654084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 15:36:10.654162 ==
4674 15:36:10.657809 [Gating] SW mode calibration
4675 15:36:10.664333 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4676 15:36:10.671038 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4677 15:36:10.674108 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4678 15:36:10.677103 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4679 15:36:10.684051 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4680 15:36:10.687284 0 9 12 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 1)
4681 15:36:10.690257 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 15:36:10.697498 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 15:36:10.700383 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 15:36:10.703941 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 15:36:10.710162 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 15:36:10.713970 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 15:36:10.717071 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4688 15:36:10.723528 0 10 12 | B1->B0 | 2d2d 3c3c | 0 1 | (0 0) (0 0)
4689 15:36:10.727212 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
4690 15:36:10.729887 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 15:36:10.736778 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 15:36:10.739983 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 15:36:10.743219 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 15:36:10.750301 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 15:36:10.753459 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4696 15:36:10.756559 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 15:36:10.763614 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 15:36:10.766598 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 15:36:10.769598 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 15:36:10.776854 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 15:36:10.780082 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 15:36:10.783256 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 15:36:10.789468 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 15:36:10.793398 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 15:36:10.796500 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 15:36:10.802983 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 15:36:10.806443 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 15:36:10.810065 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 15:36:10.816085 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 15:36:10.819541 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 15:36:10.823233 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 15:36:10.829512 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4713 15:36:10.829604 Total UI for P1: 0, mck2ui 16
4714 15:36:10.832680 best dqsien dly found for B0: ( 0, 13, 10)
4715 15:36:10.839448 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 15:36:10.842652 Total UI for P1: 0, mck2ui 16
4717 15:36:10.846005 best dqsien dly found for B1: ( 0, 13, 12)
4718 15:36:10.849057 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4719 15:36:10.852257 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4720 15:36:10.852342
4721 15:36:10.856086 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4722 15:36:10.859228 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4723 15:36:10.862341 [Gating] SW calibration Done
4724 15:36:10.862426 ==
4725 15:36:10.865617 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 15:36:10.869399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 15:36:10.869488 ==
4728 15:36:10.872508 RX Vref Scan: 0
4729 15:36:10.872601
4730 15:36:10.875617 RX Vref 0 -> 0, step: 1
4731 15:36:10.875701
4732 15:36:10.879040 RX Delay -230 -> 252, step: 16
4733 15:36:10.882498 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4734 15:36:10.886247 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4735 15:36:10.889257 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4736 15:36:10.892274 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4737 15:36:10.899244 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4738 15:36:10.902550 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4739 15:36:10.905504 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4740 15:36:10.909247 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4741 15:36:10.915386 iDelay=218, Bit 8, Center 9 (-166 ~ 185) 352
4742 15:36:10.918584 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4743 15:36:10.922254 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4744 15:36:10.925198 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4745 15:36:10.932002 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4746 15:36:10.935502 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4747 15:36:10.938897 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4748 15:36:10.942546 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4749 15:36:10.942636 ==
4750 15:36:10.945223 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 15:36:10.952327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 15:36:10.952416 ==
4753 15:36:10.952483 DQS Delay:
4754 15:36:10.952545 DQS0 = 0, DQS1 = 0
4755 15:36:10.955423 DQM Delay:
4756 15:36:10.955507 DQM0 = 37, DQM1 = 28
4757 15:36:10.958445 DQ Delay:
4758 15:36:10.962282 DQ0 =49, DQ1 =33, DQ2 =17, DQ3 =33
4759 15:36:10.965516 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4760 15:36:10.965601 DQ8 =9, DQ9 =17, DQ10 =33, DQ11 =25
4761 15:36:10.971777 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4762 15:36:10.971903
4763 15:36:10.972005
4764 15:36:10.972072 ==
4765 15:36:10.975681 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 15:36:10.978708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 15:36:10.978794 ==
4768 15:36:10.978864
4769 15:36:10.978926
4770 15:36:10.981865 TX Vref Scan disable
4771 15:36:10.981950 == TX Byte 0 ==
4772 15:36:10.988652 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4773 15:36:10.992093 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4774 15:36:10.992181 == TX Byte 1 ==
4775 15:36:10.998720 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4776 15:36:11.001869 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4777 15:36:11.001956 ==
4778 15:36:11.005053 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 15:36:11.008150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 15:36:11.008237 ==
4781 15:36:11.008303
4782 15:36:11.011247
4783 15:36:11.011357 TX Vref Scan disable
4784 15:36:11.014988 == TX Byte 0 ==
4785 15:36:11.018104 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4786 15:36:11.021860 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4787 15:36:11.025069 == TX Byte 1 ==
4788 15:36:11.028427 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4789 15:36:11.031465 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4790 15:36:11.034762
4791 15:36:11.034846 [DATLAT]
4792 15:36:11.034913 Freq=600, CH1 RK1
4793 15:36:11.034975
4794 15:36:11.038538 DATLAT Default: 0x9
4795 15:36:11.038622 0, 0xFFFF, sum = 0
4796 15:36:11.041823 1, 0xFFFF, sum = 0
4797 15:36:11.041908 2, 0xFFFF, sum = 0
4798 15:36:11.044860 3, 0xFFFF, sum = 0
4799 15:36:11.044945 4, 0xFFFF, sum = 0
4800 15:36:11.048554 5, 0xFFFF, sum = 0
4801 15:36:11.051489 6, 0xFFFF, sum = 0
4802 15:36:11.051574 7, 0xFFFF, sum = 0
4803 15:36:11.051656 8, 0x0, sum = 1
4804 15:36:11.055278 9, 0x0, sum = 2
4805 15:36:11.055362 10, 0x0, sum = 3
4806 15:36:11.058213 11, 0x0, sum = 4
4807 15:36:11.058326 best_step = 9
4808 15:36:11.058428
4809 15:36:11.058494 ==
4810 15:36:11.061303 Dram Type= 6, Freq= 0, CH_1, rank 1
4811 15:36:11.068499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4812 15:36:11.068602 ==
4813 15:36:11.068673 RX Vref Scan: 0
4814 15:36:11.068737
4815 15:36:11.071598 RX Vref 0 -> 0, step: 1
4816 15:36:11.071710
4817 15:36:11.074804 RX Delay -211 -> 252, step: 8
4818 15:36:11.077868 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4819 15:36:11.084763 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4820 15:36:11.088057 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4821 15:36:11.091259 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4822 15:36:11.094998 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4823 15:36:11.101239 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4824 15:36:11.104719 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4825 15:36:11.108229 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4826 15:36:11.111175 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4827 15:36:11.114894 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4828 15:36:11.121077 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4829 15:36:11.124557 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4830 15:36:11.127880 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4831 15:36:11.131147 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4832 15:36:11.137558 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4833 15:36:11.141440 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4834 15:36:11.141530 ==
4835 15:36:11.144547 Dram Type= 6, Freq= 0, CH_1, rank 1
4836 15:36:11.147835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4837 15:36:11.147921 ==
4838 15:36:11.150881 DQS Delay:
4839 15:36:11.150965 DQS0 = 0, DQS1 = 0
4840 15:36:11.151033 DQM Delay:
4841 15:36:11.154747 DQM0 = 36, DQM1 = 29
4842 15:36:11.154827 DQ Delay:
4843 15:36:11.157690 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4844 15:36:11.160926 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4845 15:36:11.164313 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =24
4846 15:36:11.167733 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4847 15:36:11.167844
4848 15:36:11.167941
4849 15:36:11.177318 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
4850 15:36:11.181137 CH1 RK1: MR19=808, MR18=3F5F
4851 15:36:11.184269 CH1_RK1: MR19=0x808, MR18=0x3F5F, DQSOSC=391, MR23=63, INC=171, DEC=114
4852 15:36:11.187352 [RxdqsGatingPostProcess] freq 600
4853 15:36:11.194611 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4854 15:36:11.197729 Pre-setting of DQS Precalculation
4855 15:36:11.200895 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4856 15:36:11.207893 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4857 15:36:11.217705 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4858 15:36:11.217805
4859 15:36:11.217873
4860 15:36:11.220922 [Calibration Summary] 1200 Mbps
4861 15:36:11.221007 CH 0, Rank 0
4862 15:36:11.224286 SW Impedance : PASS
4863 15:36:11.224370 DUTY Scan : NO K
4864 15:36:11.227521 ZQ Calibration : PASS
4865 15:36:11.231121 Jitter Meter : NO K
4866 15:36:11.231231 CBT Training : PASS
4867 15:36:11.234268 Write leveling : PASS
4868 15:36:11.234347 RX DQS gating : PASS
4869 15:36:11.237380 RX DQ/DQS(RDDQC) : PASS
4870 15:36:11.240602 TX DQ/DQS : PASS
4871 15:36:11.240683 RX DATLAT : PASS
4872 15:36:11.243739 RX DQ/DQS(Engine): PASS
4873 15:36:11.247358 TX OE : NO K
4874 15:36:11.247463 All Pass.
4875 15:36:11.247530
4876 15:36:11.247592 CH 0, Rank 1
4877 15:36:11.250546 SW Impedance : PASS
4878 15:36:11.253692 DUTY Scan : NO K
4879 15:36:11.253799 ZQ Calibration : PASS
4880 15:36:11.257066 Jitter Meter : NO K
4881 15:36:11.260451 CBT Training : PASS
4882 15:36:11.260536 Write leveling : PASS
4883 15:36:11.264230 RX DQS gating : PASS
4884 15:36:11.267304 RX DQ/DQS(RDDQC) : PASS
4885 15:36:11.267400 TX DQ/DQS : PASS
4886 15:36:11.270376 RX DATLAT : PASS
4887 15:36:11.274142 RX DQ/DQS(Engine): PASS
4888 15:36:11.274230 TX OE : NO K
4889 15:36:11.277142 All Pass.
4890 15:36:11.277227
4891 15:36:11.277293 CH 1, Rank 0
4892 15:36:11.280344 SW Impedance : PASS
4893 15:36:11.280423 DUTY Scan : NO K
4894 15:36:11.283949 ZQ Calibration : PASS
4895 15:36:11.287315 Jitter Meter : NO K
4896 15:36:11.287434 CBT Training : PASS
4897 15:36:11.290282 Write leveling : PASS
4898 15:36:11.293818 RX DQS gating : PASS
4899 15:36:11.293903 RX DQ/DQS(RDDQC) : PASS
4900 15:36:11.297032 TX DQ/DQS : PASS
4901 15:36:11.297131 RX DATLAT : PASS
4902 15:36:11.300355 RX DQ/DQS(Engine): PASS
4903 15:36:11.303490 TX OE : NO K
4904 15:36:11.303575 All Pass.
4905 15:36:11.303640
4906 15:36:11.303701 CH 1, Rank 1
4907 15:36:11.307321 SW Impedance : PASS
4908 15:36:11.310493 DUTY Scan : NO K
4909 15:36:11.310583 ZQ Calibration : PASS
4910 15:36:11.313819 Jitter Meter : NO K
4911 15:36:11.316882 CBT Training : PASS
4912 15:36:11.316968 Write leveling : PASS
4913 15:36:11.320765 RX DQS gating : PASS
4914 15:36:11.323626 RX DQ/DQS(RDDQC) : PASS
4915 15:36:11.323707 TX DQ/DQS : PASS
4916 15:36:11.326986 RX DATLAT : PASS
4917 15:36:11.330181 RX DQ/DQS(Engine): PASS
4918 15:36:11.330289 TX OE : NO K
4919 15:36:11.333699 All Pass.
4920 15:36:11.333793
4921 15:36:11.333860 DramC Write-DBI off
4922 15:36:11.336510 PER_BANK_REFRESH: Hybrid Mode
4923 15:36:11.336606 TX_TRACKING: ON
4924 15:36:11.346882 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4925 15:36:11.349930 [FAST_K] Save calibration result to emmc
4926 15:36:11.353652 dramc_set_vcore_voltage set vcore to 662500
4927 15:36:11.357021 Read voltage for 933, 3
4928 15:36:11.357121 Vio18 = 0
4929 15:36:11.360004 Vcore = 662500
4930 15:36:11.360089 Vdram = 0
4931 15:36:11.360155 Vddq = 0
4932 15:36:11.360216 Vmddr = 0
4933 15:36:11.366938 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4934 15:36:11.373524 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4935 15:36:11.373622 MEM_TYPE=3, freq_sel=17
4936 15:36:11.376511 sv_algorithm_assistance_LP4_1600
4937 15:36:11.379934 ============ PULL DRAM RESETB DOWN ============
4938 15:36:11.386289 ========== PULL DRAM RESETB DOWN end =========
4939 15:36:11.390015 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4940 15:36:11.393168 ===================================
4941 15:36:11.396306 LPDDR4 DRAM CONFIGURATION
4942 15:36:11.400255 ===================================
4943 15:36:11.400348 EX_ROW_EN[0] = 0x0
4944 15:36:11.403104 EX_ROW_EN[1] = 0x0
4945 15:36:11.406265 LP4Y_EN = 0x0
4946 15:36:11.406376 WORK_FSP = 0x0
4947 15:36:11.409481 WL = 0x3
4948 15:36:11.409605 RL = 0x3
4949 15:36:11.413398 BL = 0x2
4950 15:36:11.413507 RPST = 0x0
4951 15:36:11.416624 RD_PRE = 0x0
4952 15:36:11.416728 WR_PRE = 0x1
4953 15:36:11.419779 WR_PST = 0x0
4954 15:36:11.419858 DBI_WR = 0x0
4955 15:36:11.422997 DBI_RD = 0x0
4956 15:36:11.423098 OTF = 0x1
4957 15:36:11.426156 ===================================
4958 15:36:11.429868 ===================================
4959 15:36:11.432886 ANA top config
4960 15:36:11.436145 ===================================
4961 15:36:11.436254 DLL_ASYNC_EN = 0
4962 15:36:11.439722 ALL_SLAVE_EN = 1
4963 15:36:11.442876 NEW_RANK_MODE = 1
4964 15:36:11.446501 DLL_IDLE_MODE = 1
4965 15:36:11.449511 LP45_APHY_COMB_EN = 1
4966 15:36:11.449606 TX_ODT_DIS = 1
4967 15:36:11.453043 NEW_8X_MODE = 1
4968 15:36:11.455997 ===================================
4969 15:36:11.459472 ===================================
4970 15:36:11.462555 data_rate = 1866
4971 15:36:11.465931 CKR = 1
4972 15:36:11.469134 DQ_P2S_RATIO = 8
4973 15:36:11.472367 ===================================
4974 15:36:11.475681 CA_P2S_RATIO = 8
4975 15:36:11.475775 DQ_CA_OPEN = 0
4976 15:36:11.478808 DQ_SEMI_OPEN = 0
4977 15:36:11.482450 CA_SEMI_OPEN = 0
4978 15:36:11.485541 CA_FULL_RATE = 0
4979 15:36:11.489142 DQ_CKDIV4_EN = 1
4980 15:36:11.492677 CA_CKDIV4_EN = 1
4981 15:36:11.492789 CA_PREDIV_EN = 0
4982 15:36:11.495177 PH8_DLY = 0
4983 15:36:11.498851 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4984 15:36:11.502027 DQ_AAMCK_DIV = 4
4985 15:36:11.505106 CA_AAMCK_DIV = 4
4986 15:36:11.508757 CA_ADMCK_DIV = 4
4987 15:36:11.508857 DQ_TRACK_CA_EN = 0
4988 15:36:11.511917 CA_PICK = 933
4989 15:36:11.515662 CA_MCKIO = 933
4990 15:36:11.519077 MCKIO_SEMI = 0
4991 15:36:11.522040 PLL_FREQ = 3732
4992 15:36:11.525307 DQ_UI_PI_RATIO = 32
4993 15:36:11.529094 CA_UI_PI_RATIO = 0
4994 15:36:11.532265 ===================================
4995 15:36:11.535524 ===================================
4996 15:36:11.535629 memory_type:LPDDR4
4997 15:36:11.538779 GP_NUM : 10
4998 15:36:11.541794 SRAM_EN : 1
4999 15:36:11.541897 MD32_EN : 0
5000 15:36:11.545154 ===================================
5001 15:36:11.548613 [ANA_INIT] >>>>>>>>>>>>>>
5002 15:36:11.551882 <<<<<< [CONFIGURE PHASE]: ANA_TX
5003 15:36:11.555491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5004 15:36:11.558456 ===================================
5005 15:36:11.561755 data_rate = 1866,PCW = 0X8f00
5006 15:36:11.564764 ===================================
5007 15:36:11.568374 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5008 15:36:11.572031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5009 15:36:11.578575 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5010 15:36:11.581656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5011 15:36:11.584893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5012 15:36:11.588077 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5013 15:36:11.591850 [ANA_INIT] flow start
5014 15:36:11.594718 [ANA_INIT] PLL >>>>>>>>
5015 15:36:11.594823 [ANA_INIT] PLL <<<<<<<<
5016 15:36:11.598036 [ANA_INIT] MIDPI >>>>>>>>
5017 15:36:11.601093 [ANA_INIT] MIDPI <<<<<<<<
5018 15:36:11.604577 [ANA_INIT] DLL >>>>>>>>
5019 15:36:11.604672 [ANA_INIT] flow end
5020 15:36:11.608043 ============ LP4 DIFF to SE enter ============
5021 15:36:11.614880 ============ LP4 DIFF to SE exit ============
5022 15:36:11.614997 [ANA_INIT] <<<<<<<<<<<<<
5023 15:36:11.617988 [Flow] Enable top DCM control >>>>>
5024 15:36:11.621180 [Flow] Enable top DCM control <<<<<
5025 15:36:11.625057 Enable DLL master slave shuffle
5026 15:36:11.631293 ==============================================================
5027 15:36:11.631420 Gating Mode config
5028 15:36:11.637759 ==============================================================
5029 15:36:11.641016 Config description:
5030 15:36:11.648026 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5031 15:36:11.654491 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5032 15:36:11.661146 SELPH_MODE 0: By rank 1: By Phase
5033 15:36:11.667377 ==============================================================
5034 15:36:11.670720 GAT_TRACK_EN = 1
5035 15:36:11.670845 RX_GATING_MODE = 2
5036 15:36:11.674349 RX_GATING_TRACK_MODE = 2
5037 15:36:11.677358 SELPH_MODE = 1
5038 15:36:11.681053 PICG_EARLY_EN = 1
5039 15:36:11.684319 VALID_LAT_VALUE = 1
5040 15:36:11.690654 ==============================================================
5041 15:36:11.694482 Enter into Gating configuration >>>>
5042 15:36:11.697804 Exit from Gating configuration <<<<
5043 15:36:11.701011 Enter into DVFS_PRE_config >>>>>
5044 15:36:11.710829 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5045 15:36:11.713850 Exit from DVFS_PRE_config <<<<<
5046 15:36:11.717453 Enter into PICG configuration >>>>
5047 15:36:11.720998 Exit from PICG configuration <<<<
5048 15:36:11.724023 [RX_INPUT] configuration >>>>>
5049 15:36:11.727250 [RX_INPUT] configuration <<<<<
5050 15:36:11.730520 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5051 15:36:11.737209 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5052 15:36:11.744229 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5053 15:36:11.747587 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5054 15:36:11.754147 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5055 15:36:11.760431 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5056 15:36:11.764199 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5057 15:36:11.770285 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5058 15:36:11.773816 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5059 15:36:11.777325 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5060 15:36:11.780446 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5061 15:36:11.787183 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5062 15:36:11.790715 ===================================
5063 15:36:11.790804 LPDDR4 DRAM CONFIGURATION
5064 15:36:11.793846 ===================================
5065 15:36:11.797113 EX_ROW_EN[0] = 0x0
5066 15:36:11.800309 EX_ROW_EN[1] = 0x0
5067 15:36:11.800389 LP4Y_EN = 0x0
5068 15:36:11.803574 WORK_FSP = 0x0
5069 15:36:11.803683 WL = 0x3
5070 15:36:11.806985 RL = 0x3
5071 15:36:11.807061 BL = 0x2
5072 15:36:11.810091 RPST = 0x0
5073 15:36:11.810194 RD_PRE = 0x0
5074 15:36:11.813562 WR_PRE = 0x1
5075 15:36:11.813665 WR_PST = 0x0
5076 15:36:11.816673 DBI_WR = 0x0
5077 15:36:11.816750 DBI_RD = 0x0
5078 15:36:11.820484 OTF = 0x1
5079 15:36:11.823281 ===================================
5080 15:36:11.827047 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5081 15:36:11.829950 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5082 15:36:11.836502 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5083 15:36:11.840212 ===================================
5084 15:36:11.840299 LPDDR4 DRAM CONFIGURATION
5085 15:36:11.843466 ===================================
5086 15:36:11.846710 EX_ROW_EN[0] = 0x10
5087 15:36:11.849898 EX_ROW_EN[1] = 0x0
5088 15:36:11.850002 LP4Y_EN = 0x0
5089 15:36:11.853010 WORK_FSP = 0x0
5090 15:36:11.853085 WL = 0x3
5091 15:36:11.856267 RL = 0x3
5092 15:36:11.856341 BL = 0x2
5093 15:36:11.860290 RPST = 0x0
5094 15:36:11.860363 RD_PRE = 0x0
5095 15:36:11.863339 WR_PRE = 0x1
5096 15:36:11.863429 WR_PST = 0x0
5097 15:36:11.866242 DBI_WR = 0x0
5098 15:36:11.866312 DBI_RD = 0x0
5099 15:36:11.870033 OTF = 0x1
5100 15:36:11.873174 ===================================
5101 15:36:11.879602 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5102 15:36:11.883328 nWR fixed to 30
5103 15:36:11.883435 [ModeRegInit_LP4] CH0 RK0
5104 15:36:11.886102 [ModeRegInit_LP4] CH0 RK1
5105 15:36:11.889640 [ModeRegInit_LP4] CH1 RK0
5106 15:36:11.893025 [ModeRegInit_LP4] CH1 RK1
5107 15:36:11.893121 match AC timing 9
5108 15:36:11.899433 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5109 15:36:11.902970 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5110 15:36:11.906194 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5111 15:36:11.913041 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5112 15:36:11.916174 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5113 15:36:11.916257 ==
5114 15:36:11.919286 Dram Type= 6, Freq= 0, CH_0, rank 0
5115 15:36:11.923172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 15:36:11.923281 ==
5117 15:36:11.929604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5118 15:36:11.935972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5119 15:36:11.939753 [CA 0] Center 38 (8~69) winsize 62
5120 15:36:11.942370 [CA 1] Center 38 (7~69) winsize 63
5121 15:36:11.946158 [CA 2] Center 36 (6~66) winsize 61
5122 15:36:11.949105 [CA 3] Center 35 (5~66) winsize 62
5123 15:36:11.953096 [CA 4] Center 34 (4~64) winsize 61
5124 15:36:11.956191 [CA 5] Center 33 (3~64) winsize 62
5125 15:36:11.956271
5126 15:36:11.959343 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5127 15:36:11.959467
5128 15:36:11.962603 [CATrainingPosCal] consider 1 rank data
5129 15:36:11.965787 u2DelayCellTimex100 = 270/100 ps
5130 15:36:11.969634 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5131 15:36:11.972446 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5132 15:36:11.975675 CA2 delay=36 (6~66),Diff = 3 PI (18 cell)
5133 15:36:11.979350 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5134 15:36:11.982685 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5135 15:36:11.985808 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5136 15:36:11.985890
5137 15:36:11.992889 CA PerBit enable=1, Macro0, CA PI delay=33
5138 15:36:11.992973
5139 15:36:11.993038 [CBTSetCACLKResult] CA Dly = 33
5140 15:36:11.996010 CS Dly: 6 (0~37)
5141 15:36:11.996093 ==
5142 15:36:11.998994 Dram Type= 6, Freq= 0, CH_0, rank 1
5143 15:36:12.002542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 15:36:12.002624 ==
5145 15:36:12.009044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5146 15:36:12.016125 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5147 15:36:12.018934 [CA 0] Center 38 (8~69) winsize 62
5148 15:36:12.022554 [CA 1] Center 38 (8~69) winsize 62
5149 15:36:12.025655 [CA 2] Center 35 (5~66) winsize 62
5150 15:36:12.028911 [CA 3] Center 35 (5~66) winsize 62
5151 15:36:12.032135 [CA 4] Center 34 (4~65) winsize 62
5152 15:36:12.036011 [CA 5] Center 33 (3~64) winsize 62
5153 15:36:12.036093
5154 15:36:12.039269 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5155 15:36:12.039359
5156 15:36:12.042344 [CATrainingPosCal] consider 2 rank data
5157 15:36:12.045442 u2DelayCellTimex100 = 270/100 ps
5158 15:36:12.049133 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5159 15:36:12.052055 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5160 15:36:12.055524 CA2 delay=36 (6~66),Diff = 3 PI (18 cell)
5161 15:36:12.058938 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5162 15:36:12.062121 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5163 15:36:12.065449 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5164 15:36:12.069181
5165 15:36:12.072464 CA PerBit enable=1, Macro0, CA PI delay=33
5166 15:36:12.072572
5167 15:36:12.075608 [CBTSetCACLKResult] CA Dly = 33
5168 15:36:12.075694 CS Dly: 7 (0~39)
5169 15:36:12.075764
5170 15:36:12.078589 ----->DramcWriteLeveling(PI) begin...
5171 15:36:12.078669 ==
5172 15:36:12.082438 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 15:36:12.085586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 15:36:12.088882 ==
5175 15:36:12.088972 Write leveling (Byte 0): 30 => 30
5176 15:36:12.092032 Write leveling (Byte 1): 30 => 30
5177 15:36:12.095278 DramcWriteLeveling(PI) end<-----
5178 15:36:12.095401
5179 15:36:12.095468 ==
5180 15:36:12.098347 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 15:36:12.105191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 15:36:12.105279 ==
5183 15:36:12.108453 [Gating] SW mode calibration
5184 15:36:12.114779 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5185 15:36:12.118505 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5186 15:36:12.125095 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5187 15:36:12.128724 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
5188 15:36:12.131619 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 15:36:12.138654 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 15:36:12.141900 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 15:36:12.145078 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 15:36:12.151438 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 15:36:12.155311 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5194 15:36:12.158452 0 15 0 | B1->B0 | 3131 2e2e | 1 0 | (1 1) (1 0)
5195 15:36:12.161713 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5196 15:36:12.168329 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 15:36:12.171342 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 15:36:12.175026 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 15:36:12.181818 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 15:36:12.185095 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 15:36:12.188287 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5202 15:36:12.194652 1 0 0 | B1->B0 | 3030 3b3b | 0 0 | (0 0) (0 0)
5203 15:36:12.197926 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5204 15:36:12.201755 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 15:36:12.208522 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 15:36:12.211775 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 15:36:12.214783 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 15:36:12.221534 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 15:36:12.224945 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5210 15:36:12.227979 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5211 15:36:12.234752 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5212 15:36:12.237911 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 15:36:12.240941 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 15:36:12.247408 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 15:36:12.250958 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 15:36:12.254175 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 15:36:12.260686 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 15:36:12.264418 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 15:36:12.267453 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 15:36:12.274334 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 15:36:12.277927 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 15:36:12.280969 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 15:36:12.287248 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 15:36:12.290537 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 15:36:12.294255 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5226 15:36:12.300461 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5227 15:36:12.300546 Total UI for P1: 0, mck2ui 16
5228 15:36:12.307460 best dqsien dly found for B0: ( 1, 2, 28)
5229 15:36:12.310579 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5230 15:36:12.313884 Total UI for P1: 0, mck2ui 16
5231 15:36:12.317815 best dqsien dly found for B1: ( 1, 3, 0)
5232 15:36:12.320344 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5233 15:36:12.323677 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5234 15:36:12.323825
5235 15:36:12.327233 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5236 15:36:12.330893 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5237 15:36:12.333869 [Gating] SW calibration Done
5238 15:36:12.333989 ==
5239 15:36:12.337190 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 15:36:12.340243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 15:36:12.344065 ==
5242 15:36:12.344171 RX Vref Scan: 0
5243 15:36:12.344262
5244 15:36:12.347009 RX Vref 0 -> 0, step: 1
5245 15:36:12.347089
5246 15:36:12.347151 RX Delay -80 -> 252, step: 8
5247 15:36:12.353662 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5248 15:36:12.357129 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5249 15:36:12.360238 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5250 15:36:12.363973 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5251 15:36:12.366978 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5252 15:36:12.370768 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5253 15:36:12.376903 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5254 15:36:12.380614 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5255 15:36:12.383734 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5256 15:36:12.387122 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5257 15:36:12.390637 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5258 15:36:12.396858 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5259 15:36:12.400119 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5260 15:36:12.403858 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5261 15:36:12.407120 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5262 15:36:12.410449 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5263 15:36:12.413267 ==
5264 15:36:12.417280 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 15:36:12.420476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 15:36:12.420553 ==
5267 15:36:12.420616 DQS Delay:
5268 15:36:12.423819 DQS0 = 0, DQS1 = 0
5269 15:36:12.423895 DQM Delay:
5270 15:36:12.426894 DQM0 = 94, DQM1 = 84
5271 15:36:12.426971 DQ Delay:
5272 15:36:12.430215 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5273 15:36:12.433581 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5274 15:36:12.437063 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5275 15:36:12.440100 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5276 15:36:12.440181
5277 15:36:12.440244
5278 15:36:12.440310 ==
5279 15:36:12.443070 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 15:36:12.446951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 15:36:12.447028 ==
5282 15:36:12.447092
5283 15:36:12.447150
5284 15:36:12.450089 TX Vref Scan disable
5285 15:36:12.453452 == TX Byte 0 ==
5286 15:36:12.456487 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5287 15:36:12.459879 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5288 15:36:12.463083 == TX Byte 1 ==
5289 15:36:12.466843 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5290 15:36:12.469895 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5291 15:36:12.469988 ==
5292 15:36:12.473210 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 15:36:12.479548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 15:36:12.479629 ==
5295 15:36:12.479707
5296 15:36:12.479819
5297 15:36:12.479908 TX Vref Scan disable
5298 15:36:12.484092 == TX Byte 0 ==
5299 15:36:12.487119 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5300 15:36:12.493501 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5301 15:36:12.493594 == TX Byte 1 ==
5302 15:36:12.497114 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5303 15:36:12.503776 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5304 15:36:12.503866
5305 15:36:12.503939 [DATLAT]
5306 15:36:12.504011 Freq=933, CH0 RK0
5307 15:36:12.504073
5308 15:36:12.507219 DATLAT Default: 0xd
5309 15:36:12.507297 0, 0xFFFF, sum = 0
5310 15:36:12.510499 1, 0xFFFF, sum = 0
5311 15:36:12.510584 2, 0xFFFF, sum = 0
5312 15:36:12.513635 3, 0xFFFF, sum = 0
5313 15:36:12.516739 4, 0xFFFF, sum = 0
5314 15:36:12.516823 5, 0xFFFF, sum = 0
5315 15:36:12.520568 6, 0xFFFF, sum = 0
5316 15:36:12.520652 7, 0xFFFF, sum = 0
5317 15:36:12.523725 8, 0xFFFF, sum = 0
5318 15:36:12.523808 9, 0xFFFF, sum = 0
5319 15:36:12.526936 10, 0x0, sum = 1
5320 15:36:12.527009 11, 0x0, sum = 2
5321 15:36:12.527080 12, 0x0, sum = 3
5322 15:36:12.530213 13, 0x0, sum = 4
5323 15:36:12.530288 best_step = 11
5324 15:36:12.530361
5325 15:36:12.533360 ==
5326 15:36:12.533435 Dram Type= 6, Freq= 0, CH_0, rank 0
5327 15:36:12.540500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 15:36:12.540586 ==
5329 15:36:12.540654 RX Vref Scan: 1
5330 15:36:12.540716
5331 15:36:12.543715 RX Vref 0 -> 0, step: 1
5332 15:36:12.543797
5333 15:36:12.547056 RX Delay -69 -> 252, step: 4
5334 15:36:12.547138
5335 15:36:12.550255 Set Vref, RX VrefLevel [Byte0]: 60
5336 15:36:12.553712 [Byte1]: 58
5337 15:36:12.553825
5338 15:36:12.556913 Final RX Vref Byte 0 = 60 to rank0
5339 15:36:12.560373 Final RX Vref Byte 1 = 58 to rank0
5340 15:36:12.563802 Final RX Vref Byte 0 = 60 to rank1
5341 15:36:12.566882 Final RX Vref Byte 1 = 58 to rank1==
5342 15:36:12.570182 Dram Type= 6, Freq= 0, CH_0, rank 0
5343 15:36:12.573672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 15:36:12.573782 ==
5345 15:36:12.576903 DQS Delay:
5346 15:36:12.576983 DQS0 = 0, DQS1 = 0
5347 15:36:12.580317 DQM Delay:
5348 15:36:12.580414 DQM0 = 95, DQM1 = 84
5349 15:36:12.580487 DQ Delay:
5350 15:36:12.583342 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5351 15:36:12.586589 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5352 15:36:12.590276 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =78
5353 15:36:12.593389 DQ12 =90, DQ13 =88, DQ14 =92, DQ15 =90
5354 15:36:12.593471
5355 15:36:12.596682
5356 15:36:12.603610 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5357 15:36:12.606681 CH0 RK0: MR19=505, MR18=1717
5358 15:36:12.613554 CH0_RK0: MR19=0x505, MR18=0x1717, DQSOSC=414, MR23=63, INC=63, DEC=42
5359 15:36:12.613638
5360 15:36:12.616508 ----->DramcWriteLeveling(PI) begin...
5361 15:36:12.616613 ==
5362 15:36:12.620262 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 15:36:12.623283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 15:36:12.623361 ==
5365 15:36:12.626330 Write leveling (Byte 0): 30 => 30
5366 15:36:12.629573 Write leveling (Byte 1): 29 => 29
5367 15:36:12.632819 DramcWriteLeveling(PI) end<-----
5368 15:36:12.632901
5369 15:36:12.633002 ==
5370 15:36:12.636526 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 15:36:12.639734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 15:36:12.639819 ==
5373 15:36:12.642888 [Gating] SW mode calibration
5374 15:36:12.650126 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5375 15:36:12.656406 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5376 15:36:12.659462 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5377 15:36:12.662627 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 15:36:12.669634 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 15:36:12.672737 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 15:36:12.676363 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 15:36:12.682998 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 15:36:12.686136 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5383 15:36:12.689412 0 14 28 | B1->B0 | 3232 2c2c | 1 0 | (1 1) (1 1)
5384 15:36:12.695974 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5385 15:36:12.699619 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5386 15:36:12.702979 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 15:36:12.709163 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 15:36:12.712388 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 15:36:12.715532 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 15:36:12.722683 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 15:36:12.725686 0 15 28 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
5392 15:36:12.729123 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
5393 15:36:12.735637 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 15:36:12.738704 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 15:36:12.742536 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 15:36:12.748882 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 15:36:12.752293 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 15:36:12.756022 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5399 15:36:12.762382 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5400 15:36:12.765498 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5401 15:36:12.769237 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5402 15:36:12.775590 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 15:36:12.778815 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 15:36:12.782616 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 15:36:12.788823 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 15:36:12.792333 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 15:36:12.795820 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 15:36:12.801782 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 15:36:12.805345 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 15:36:12.808944 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 15:36:12.815110 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 15:36:12.818766 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 15:36:12.821905 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 15:36:12.828393 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 15:36:12.832166 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5416 15:36:12.835047 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5417 15:36:12.838564 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 15:36:12.841538 Total UI for P1: 0, mck2ui 16
5419 15:36:12.845254 best dqsien dly found for B0: ( 1, 2, 30)
5420 15:36:12.848302 Total UI for P1: 0, mck2ui 16
5421 15:36:12.851391 best dqsien dly found for B1: ( 1, 3, 0)
5422 15:36:12.854702 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5423 15:36:12.861812 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5424 15:36:12.861902
5425 15:36:12.864978 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5426 15:36:12.868253 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5427 15:36:12.871212 [Gating] SW calibration Done
5428 15:36:12.871294 ==
5429 15:36:12.874989 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 15:36:12.878149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 15:36:12.878264 ==
5432 15:36:12.878332 RX Vref Scan: 0
5433 15:36:12.881317
5434 15:36:12.881394 RX Vref 0 -> 0, step: 1
5435 15:36:12.881470
5436 15:36:12.884490 RX Delay -80 -> 252, step: 8
5437 15:36:12.887839 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5438 15:36:12.891488 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5439 15:36:12.897716 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5440 15:36:12.901161 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5441 15:36:12.904451 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5442 15:36:12.908275 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5443 15:36:12.911604 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5444 15:36:12.914666 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5445 15:36:12.921121 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5446 15:36:12.924283 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5447 15:36:12.927978 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5448 15:36:12.930859 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5449 15:36:12.934749 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5450 15:36:12.941004 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5451 15:36:12.944643 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5452 15:36:12.947665 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5453 15:36:12.947751 ==
5454 15:36:12.951268 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 15:36:12.954443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 15:36:12.954544 ==
5457 15:36:12.957660 DQS Delay:
5458 15:36:12.957751 DQS0 = 0, DQS1 = 0
5459 15:36:12.960772 DQM Delay:
5460 15:36:12.960846 DQM0 = 92, DQM1 = 83
5461 15:36:12.960924 DQ Delay:
5462 15:36:12.964651 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5463 15:36:12.967768 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5464 15:36:12.971104 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5465 15:36:12.974301 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5466 15:36:12.974402
5467 15:36:12.977845
5468 15:36:12.977921 ==
5469 15:36:12.981009 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 15:36:12.984176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 15:36:12.984252 ==
5472 15:36:12.984315
5473 15:36:12.984374
5474 15:36:12.987312 TX Vref Scan disable
5475 15:36:12.987421 == TX Byte 0 ==
5476 15:36:12.994306 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5477 15:36:12.997475 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5478 15:36:12.997580 == TX Byte 1 ==
5479 15:36:13.004134 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5480 15:36:13.007361 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5481 15:36:13.007450 ==
5482 15:36:13.010859 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 15:36:13.014316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 15:36:13.014417 ==
5485 15:36:13.014516
5486 15:36:13.014604
5487 15:36:13.017382 TX Vref Scan disable
5488 15:36:13.020587 == TX Byte 0 ==
5489 15:36:13.024113 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5490 15:36:13.027474 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5491 15:36:13.030592 == TX Byte 1 ==
5492 15:36:13.034061 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5493 15:36:13.037344 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5494 15:36:13.037472
5495 15:36:13.040563 [DATLAT]
5496 15:36:13.040639 Freq=933, CH0 RK1
5497 15:36:13.040704
5498 15:36:13.043755 DATLAT Default: 0xb
5499 15:36:13.043831 0, 0xFFFF, sum = 0
5500 15:36:13.046898 1, 0xFFFF, sum = 0
5501 15:36:13.046983 2, 0xFFFF, sum = 0
5502 15:36:13.050282 3, 0xFFFF, sum = 0
5503 15:36:13.050366 4, 0xFFFF, sum = 0
5504 15:36:13.053908 5, 0xFFFF, sum = 0
5505 15:36:13.053991 6, 0xFFFF, sum = 0
5506 15:36:13.057499 7, 0xFFFF, sum = 0
5507 15:36:13.057583 8, 0xFFFF, sum = 0
5508 15:36:13.060487 9, 0xFFFF, sum = 0
5509 15:36:13.060572 10, 0x0, sum = 1
5510 15:36:13.063605 11, 0x0, sum = 2
5511 15:36:13.063693 12, 0x0, sum = 3
5512 15:36:13.066813 13, 0x0, sum = 4
5513 15:36:13.066902 best_step = 11
5514 15:36:13.066980
5515 15:36:13.067041 ==
5516 15:36:13.070209 Dram Type= 6, Freq= 0, CH_0, rank 1
5517 15:36:13.077448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 15:36:13.077534 ==
5519 15:36:13.077601 RX Vref Scan: 0
5520 15:36:13.077670
5521 15:36:13.080497 RX Vref 0 -> 0, step: 1
5522 15:36:13.080575
5523 15:36:13.083629 RX Delay -77 -> 252, step: 4
5524 15:36:13.086789 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5525 15:36:13.090550 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5526 15:36:13.096889 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5527 15:36:13.099973 iDelay=199, Bit 3, Center 86 (-9 ~ 182) 192
5528 15:36:13.103888 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5529 15:36:13.106963 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5530 15:36:13.110131 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5531 15:36:13.113653 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5532 15:36:13.120072 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5533 15:36:13.123427 iDelay=199, Bit 9, Center 70 (-21 ~ 162) 184
5534 15:36:13.126385 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5535 15:36:13.129751 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5536 15:36:13.136465 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5537 15:36:13.140218 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5538 15:36:13.143765 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5539 15:36:13.147005 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5540 15:36:13.147088 ==
5541 15:36:13.150253 Dram Type= 6, Freq= 0, CH_0, rank 1
5542 15:36:13.153469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 15:36:13.153552 ==
5544 15:36:13.156509 DQS Delay:
5545 15:36:13.156590 DQS0 = 0, DQS1 = 0
5546 15:36:13.159688 DQM Delay:
5547 15:36:13.159769 DQM0 = 92, DQM1 = 84
5548 15:36:13.159834 DQ Delay:
5549 15:36:13.163469 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =86
5550 15:36:13.166435 DQ4 =90, DQ5 =80, DQ6 =106, DQ7 =102
5551 15:36:13.169988 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5552 15:36:13.173209 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5553 15:36:13.173292
5554 15:36:13.176697
5555 15:36:13.183300 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5556 15:36:13.186425 CH0 RK1: MR19=505, MR18=2D0F
5557 15:36:13.192825 CH0_RK1: MR19=0x505, MR18=0x2D0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5558 15:36:13.196568 [RxdqsGatingPostProcess] freq 933
5559 15:36:13.199722 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5560 15:36:13.202852 best DQS0 dly(2T, 0.5T) = (0, 10)
5561 15:36:13.206071 best DQS1 dly(2T, 0.5T) = (0, 11)
5562 15:36:13.209803 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5563 15:36:13.212944 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5564 15:36:13.216029 best DQS0 dly(2T, 0.5T) = (0, 10)
5565 15:36:13.219944 best DQS1 dly(2T, 0.5T) = (0, 11)
5566 15:36:13.222922 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5567 15:36:13.226427 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5568 15:36:13.229598 Pre-setting of DQS Precalculation
5569 15:36:13.232840 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5570 15:36:13.232940 ==
5571 15:36:13.236492 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 15:36:13.239107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 15:36:13.242719 ==
5574 15:36:13.246538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5575 15:36:13.252921 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5576 15:36:13.255895 [CA 0] Center 37 (7~68) winsize 62
5577 15:36:13.259690 [CA 1] Center 37 (7~68) winsize 62
5578 15:36:13.262823 [CA 2] Center 35 (5~65) winsize 61
5579 15:36:13.265789 [CA 3] Center 35 (5~65) winsize 61
5580 15:36:13.269027 [CA 4] Center 35 (5~65) winsize 61
5581 15:36:13.272773 [CA 5] Center 34 (4~64) winsize 61
5582 15:36:13.272864
5583 15:36:13.276013 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5584 15:36:13.276101
5585 15:36:13.279495 [CATrainingPosCal] consider 1 rank data
5586 15:36:13.282645 u2DelayCellTimex100 = 270/100 ps
5587 15:36:13.285760 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5588 15:36:13.289540 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5589 15:36:13.292786 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5590 15:36:13.295999 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5591 15:36:13.302847 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5592 15:36:13.305975 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5593 15:36:13.306054
5594 15:36:13.309149 CA PerBit enable=1, Macro0, CA PI delay=34
5595 15:36:13.309235
5596 15:36:13.312519 [CBTSetCACLKResult] CA Dly = 34
5597 15:36:13.312596 CS Dly: 6 (0~37)
5598 15:36:13.312660 ==
5599 15:36:13.315867 Dram Type= 6, Freq= 0, CH_1, rank 1
5600 15:36:13.322249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 15:36:13.322375 ==
5602 15:36:13.325993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5603 15:36:13.332294 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5604 15:36:13.336168 [CA 0] Center 37 (7~68) winsize 62
5605 15:36:13.339249 [CA 1] Center 37 (7~68) winsize 62
5606 15:36:13.342441 [CA 2] Center 35 (5~65) winsize 61
5607 15:36:13.345416 [CA 3] Center 34 (4~64) winsize 61
5608 15:36:13.349041 [CA 4] Center 35 (5~65) winsize 61
5609 15:36:13.352427 [CA 5] Center 34 (4~64) winsize 61
5610 15:36:13.352505
5611 15:36:13.355734 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5612 15:36:13.355819
5613 15:36:13.358951 [CATrainingPosCal] consider 2 rank data
5614 15:36:13.362353 u2DelayCellTimex100 = 270/100 ps
5615 15:36:13.365856 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5616 15:36:13.368995 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5617 15:36:13.375318 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5618 15:36:13.378552 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5619 15:36:13.382418 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5620 15:36:13.385601 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5621 15:36:13.385676
5622 15:36:13.388608 CA PerBit enable=1, Macro0, CA PI delay=34
5623 15:36:13.388680
5624 15:36:13.391776 [CBTSetCACLKResult] CA Dly = 34
5625 15:36:13.391894 CS Dly: 7 (0~39)
5626 15:36:13.391963
5627 15:36:13.395414 ----->DramcWriteLeveling(PI) begin...
5628 15:36:13.399118 ==
5629 15:36:13.402150 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 15:36:13.405312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 15:36:13.405393 ==
5632 15:36:13.408545 Write leveling (Byte 0): 24 => 24
5633 15:36:13.411689 Write leveling (Byte 1): 30 => 30
5634 15:36:13.414934 DramcWriteLeveling(PI) end<-----
5635 15:36:13.415027
5636 15:36:13.415120 ==
5637 15:36:13.418753 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 15:36:13.421941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 15:36:13.422032 ==
5640 15:36:13.425143 [Gating] SW mode calibration
5641 15:36:13.431528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5642 15:36:13.438223 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5643 15:36:13.441545 0 14 0 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 1)
5644 15:36:13.445258 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 15:36:13.451565 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 15:36:13.454693 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 15:36:13.458480 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 15:36:13.461431 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 15:36:13.468622 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 15:36:13.471829 0 14 28 | B1->B0 | 2e2e 2f2f | 0 0 | (1 0) (0 0)
5651 15:36:13.474746 0 15 0 | B1->B0 | 2727 2525 | 0 0 | (0 0) (1 0)
5652 15:36:13.481572 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 15:36:13.484667 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 15:36:13.487819 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 15:36:13.494757 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 15:36:13.498333 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 15:36:13.501428 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 15:36:13.507812 0 15 28 | B1->B0 | 2e2e 3030 | 0 0 | (0 0) (0 0)
5659 15:36:13.510928 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 15:36:13.514949 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 15:36:13.521336 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 15:36:13.524486 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 15:36:13.527754 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 15:36:13.534618 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 15:36:13.537897 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 15:36:13.540990 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5667 15:36:13.547910 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 15:36:13.551085 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 15:36:13.554298 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 15:36:13.561204 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 15:36:13.564302 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 15:36:13.567872 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 15:36:13.574261 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 15:36:13.577463 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 15:36:13.580799 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 15:36:13.587590 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 15:36:13.590874 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 15:36:13.593894 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 15:36:13.600886 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 15:36:13.603850 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 15:36:13.607677 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 15:36:13.614306 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5683 15:36:13.617564 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 15:36:13.620749 Total UI for P1: 0, mck2ui 16
5685 15:36:13.623863 best dqsien dly found for B0: ( 1, 2, 28)
5686 15:36:13.627687 Total UI for P1: 0, mck2ui 16
5687 15:36:13.631011 best dqsien dly found for B1: ( 1, 2, 28)
5688 15:36:13.634025 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5689 15:36:13.637006 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5690 15:36:13.637093
5691 15:36:13.640677 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5692 15:36:13.643916 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5693 15:36:13.647337 [Gating] SW calibration Done
5694 15:36:13.647473 ==
5695 15:36:13.650527 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 15:36:13.653851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 15:36:13.653951 ==
5698 15:36:13.657625 RX Vref Scan: 0
5699 15:36:13.657711
5700 15:36:13.660814 RX Vref 0 -> 0, step: 1
5701 15:36:13.660893
5702 15:36:13.660965 RX Delay -80 -> 252, step: 8
5703 15:36:13.667613 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5704 15:36:13.670752 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5705 15:36:13.673984 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5706 15:36:13.677145 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5707 15:36:13.680304 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5708 15:36:13.684017 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5709 15:36:13.690663 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5710 15:36:13.693879 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5711 15:36:13.697576 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5712 15:36:13.700438 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5713 15:36:13.703608 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5714 15:36:13.710467 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5715 15:36:13.713679 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5716 15:36:13.717231 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5717 15:36:13.720138 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5718 15:36:13.723243 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5719 15:36:13.723359 ==
5720 15:36:13.726632 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 15:36:13.733591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 15:36:13.733700 ==
5723 15:36:13.733798 DQS Delay:
5724 15:36:13.736906 DQS0 = 0, DQS1 = 0
5725 15:36:13.736991 DQM Delay:
5726 15:36:13.737093 DQM0 = 95, DQM1 = 87
5727 15:36:13.739989 DQ Delay:
5728 15:36:13.743706 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5729 15:36:13.747042 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5730 15:36:13.750105 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5731 15:36:13.753620 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5732 15:36:13.753747
5733 15:36:13.753809
5734 15:36:13.753867 ==
5735 15:36:13.756675 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 15:36:13.759840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 15:36:13.759911 ==
5738 15:36:13.760014
5739 15:36:13.760072
5740 15:36:13.763601 TX Vref Scan disable
5741 15:36:13.766740 == TX Byte 0 ==
5742 15:36:13.769720 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5743 15:36:13.773299 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5744 15:36:13.776565 == TX Byte 1 ==
5745 15:36:13.779609 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5746 15:36:13.782930 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5747 15:36:13.783028 ==
5748 15:36:13.786306 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 15:36:13.792870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 15:36:13.792956 ==
5751 15:36:13.793022
5752 15:36:13.793082
5753 15:36:13.793140 TX Vref Scan disable
5754 15:36:13.796584 == TX Byte 0 ==
5755 15:36:13.800441 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5756 15:36:13.803298 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5757 15:36:13.806586 == TX Byte 1 ==
5758 15:36:13.810186 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5759 15:36:13.816540 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5760 15:36:13.816646
5761 15:36:13.816743 [DATLAT]
5762 15:36:13.816845 Freq=933, CH1 RK0
5763 15:36:13.816934
5764 15:36:13.819699 DATLAT Default: 0xd
5765 15:36:13.819777 0, 0xFFFF, sum = 0
5766 15:36:13.823281 1, 0xFFFF, sum = 0
5767 15:36:13.823391 2, 0xFFFF, sum = 0
5768 15:36:13.826769 3, 0xFFFF, sum = 0
5769 15:36:13.829868 4, 0xFFFF, sum = 0
5770 15:36:13.829947 5, 0xFFFF, sum = 0
5771 15:36:13.833079 6, 0xFFFF, sum = 0
5772 15:36:13.833157 7, 0xFFFF, sum = 0
5773 15:36:13.836420 8, 0xFFFF, sum = 0
5774 15:36:13.836505 9, 0xFFFF, sum = 0
5775 15:36:13.839628 10, 0x0, sum = 1
5776 15:36:13.839712 11, 0x0, sum = 2
5777 15:36:13.842806 12, 0x0, sum = 3
5778 15:36:13.842889 13, 0x0, sum = 4
5779 15:36:13.842956 best_step = 11
5780 15:36:13.846627
5781 15:36:13.846708 ==
5782 15:36:13.849424 Dram Type= 6, Freq= 0, CH_1, rank 0
5783 15:36:13.853490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 15:36:13.853574 ==
5785 15:36:13.853639 RX Vref Scan: 1
5786 15:36:13.853700
5787 15:36:13.856533 RX Vref 0 -> 0, step: 1
5788 15:36:13.856615
5789 15:36:13.859588 RX Delay -69 -> 252, step: 4
5790 15:36:13.859671
5791 15:36:13.863217 Set Vref, RX VrefLevel [Byte0]: 56
5792 15:36:13.866341 [Byte1]: 55
5793 15:36:13.869430
5794 15:36:13.869541 Final RX Vref Byte 0 = 56 to rank0
5795 15:36:13.872788 Final RX Vref Byte 1 = 55 to rank0
5796 15:36:13.875995 Final RX Vref Byte 0 = 56 to rank1
5797 15:36:13.879135 Final RX Vref Byte 1 = 55 to rank1==
5798 15:36:13.882452 Dram Type= 6, Freq= 0, CH_1, rank 0
5799 15:36:13.889707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 15:36:13.889794 ==
5801 15:36:13.889861 DQS Delay:
5802 15:36:13.889922 DQS0 = 0, DQS1 = 0
5803 15:36:13.892674 DQM Delay:
5804 15:36:13.892765 DQM0 = 97, DQM1 = 89
5805 15:36:13.895757 DQ Delay:
5806 15:36:13.899239 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =92
5807 15:36:13.902442 DQ4 =94, DQ5 =108, DQ6 =110, DQ7 =94
5808 15:36:13.906174 DQ8 =80, DQ9 =82, DQ10 =88, DQ11 =84
5809 15:36:13.909116 DQ12 =98, DQ13 =94, DQ14 =94, DQ15 =94
5810 15:36:13.909198
5811 15:36:13.909263
5812 15:36:13.916019 [DQSOSCAuto] RK0, (LSB)MR18= 0x10a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5813 15:36:13.919030 CH1 RK0: MR19=505, MR18=10A
5814 15:36:13.926015 CH1_RK0: MR19=0x505, MR18=0x10A, DQSOSC=418, MR23=63, INC=62, DEC=41
5815 15:36:13.926109
5816 15:36:13.928965 ----->DramcWriteLeveling(PI) begin...
5817 15:36:13.929046 ==
5818 15:36:13.932743 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 15:36:13.935664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 15:36:13.935768 ==
5821 15:36:13.938796 Write leveling (Byte 0): 24 => 24
5822 15:36:13.942620 Write leveling (Byte 1): 30 => 30
5823 15:36:13.945865 DramcWriteLeveling(PI) end<-----
5824 15:36:13.945944
5825 15:36:13.946007 ==
5826 15:36:13.949237 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 15:36:13.952508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 15:36:13.952585 ==
5829 15:36:13.956028 [Gating] SW mode calibration
5830 15:36:13.962683 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5831 15:36:13.968717 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5832 15:36:13.972538 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 15:36:13.978817 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 15:36:13.981980 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 15:36:13.985612 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 15:36:13.988534 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 15:36:13.995496 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 15:36:13.998593 0 14 24 | B1->B0 | 3333 3131 | 0 0 | (1 0) (0 0)
5839 15:36:14.002311 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5840 15:36:14.008819 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 15:36:14.011772 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 15:36:14.015495 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 15:36:14.021920 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 15:36:14.025504 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 15:36:14.028746 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 15:36:14.035492 0 15 24 | B1->B0 | 2525 3737 | 0 0 | (0 0) (0 0)
5847 15:36:14.038696 0 15 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5848 15:36:14.041818 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 15:36:14.048865 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 15:36:14.052085 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 15:36:14.055153 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 15:36:14.061932 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 15:36:14.065132 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 15:36:14.068178 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5855 15:36:14.075042 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5856 15:36:14.078141 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 15:36:14.081408 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 15:36:14.088057 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 15:36:14.091709 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 15:36:14.094713 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 15:36:14.101727 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 15:36:14.104984 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 15:36:14.108391 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 15:36:14.114553 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 15:36:14.117898 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 15:36:14.121622 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 15:36:14.127847 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 15:36:14.131018 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 15:36:14.134657 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 15:36:14.140983 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5871 15:36:14.144853 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5872 15:36:14.148011 Total UI for P1: 0, mck2ui 16
5873 15:36:14.151074 best dqsien dly found for B0: ( 1, 2, 24)
5874 15:36:14.154247 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5875 15:36:14.157516 Total UI for P1: 0, mck2ui 16
5876 15:36:14.160830 best dqsien dly found for B1: ( 1, 2, 28)
5877 15:36:14.164177 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5878 15:36:14.167907 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5879 15:36:14.167987
5880 15:36:14.171046 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5881 15:36:14.177755 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5882 15:36:14.177840 [Gating] SW calibration Done
5883 15:36:14.177906 ==
5884 15:36:14.180978 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 15:36:14.187301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 15:36:14.187389 ==
5887 15:36:14.187455 RX Vref Scan: 0
5888 15:36:14.187515
5889 15:36:14.191137 RX Vref 0 -> 0, step: 1
5890 15:36:14.191215
5891 15:36:14.194222 RX Delay -80 -> 252, step: 8
5892 15:36:14.197473 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5893 15:36:14.201169 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5894 15:36:14.204438 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5895 15:36:14.207549 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5896 15:36:14.214015 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5897 15:36:14.217337 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5898 15:36:14.220933 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5899 15:36:14.223954 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5900 15:36:14.227500 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5901 15:36:14.233727 iDelay=208, Bit 9, Center 79 (-24 ~ 183) 208
5902 15:36:14.237467 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5903 15:36:14.240383 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5904 15:36:14.244124 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5905 15:36:14.247432 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5906 15:36:14.253682 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5907 15:36:14.257445 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5908 15:36:14.257537 ==
5909 15:36:14.260592 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 15:36:14.263677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 15:36:14.263759 ==
5912 15:36:14.263823 DQS Delay:
5913 15:36:14.266947 DQS0 = 0, DQS1 = 0
5914 15:36:14.267029 DQM Delay:
5915 15:36:14.270581 DQM0 = 94, DQM1 = 89
5916 15:36:14.270657 DQ Delay:
5917 15:36:14.273854 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5918 15:36:14.276919 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5919 15:36:14.280583 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5920 15:36:14.283666 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =99
5921 15:36:14.283765
5922 15:36:14.283834
5923 15:36:14.283895 ==
5924 15:36:14.286944 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 15:36:14.290695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 15:36:14.293745 ==
5927 15:36:14.293830
5928 15:36:14.293895
5929 15:36:14.293956 TX Vref Scan disable
5930 15:36:14.297015 == TX Byte 0 ==
5931 15:36:14.300321 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5932 15:36:14.304108 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5933 15:36:14.307225 == TX Byte 1 ==
5934 15:36:14.310476 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5935 15:36:14.313584 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5936 15:36:14.316806 ==
5937 15:36:14.320087 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 15:36:14.324008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 15:36:14.324094 ==
5940 15:36:14.324159
5941 15:36:14.324221
5942 15:36:14.327074 TX Vref Scan disable
5943 15:36:14.327149 == TX Byte 0 ==
5944 15:36:14.333494 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5945 15:36:14.336991 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5946 15:36:14.337076 == TX Byte 1 ==
5947 15:36:14.343175 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5948 15:36:14.346830 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5949 15:36:14.346935
5950 15:36:14.347023 [DATLAT]
5951 15:36:14.350306 Freq=933, CH1 RK1
5952 15:36:14.350390
5953 15:36:14.350472 DATLAT Default: 0xb
5954 15:36:14.353592 0, 0xFFFF, sum = 0
5955 15:36:14.353670 1, 0xFFFF, sum = 0
5956 15:36:14.356824 2, 0xFFFF, sum = 0
5957 15:36:14.356933 3, 0xFFFF, sum = 0
5958 15:36:14.359929 4, 0xFFFF, sum = 0
5959 15:36:14.363107 5, 0xFFFF, sum = 0
5960 15:36:14.363180 6, 0xFFFF, sum = 0
5961 15:36:14.366860 7, 0xFFFF, sum = 0
5962 15:36:14.366951 8, 0xFFFF, sum = 0
5963 15:36:14.370032 9, 0xFFFF, sum = 0
5964 15:36:14.370118 10, 0x0, sum = 1
5965 15:36:14.373187 11, 0x0, sum = 2
5966 15:36:14.373266 12, 0x0, sum = 3
5967 15:36:14.373330 13, 0x0, sum = 4
5968 15:36:14.376340 best_step = 11
5969 15:36:14.376418
5970 15:36:14.376481 ==
5971 15:36:14.379989 Dram Type= 6, Freq= 0, CH_1, rank 1
5972 15:36:14.382871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5973 15:36:14.382974 ==
5974 15:36:14.386690 RX Vref Scan: 0
5975 15:36:14.386768
5976 15:36:14.389813 RX Vref 0 -> 0, step: 1
5977 15:36:14.389888
5978 15:36:14.389950 RX Delay -69 -> 252, step: 4
5979 15:36:14.397144 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5980 15:36:14.400923 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5981 15:36:14.404154 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5982 15:36:14.407121 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5983 15:36:14.410777 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5984 15:36:14.417344 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5985 15:36:14.420622 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5986 15:36:14.423873 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5987 15:36:14.427015 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5988 15:36:14.430884 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5989 15:36:14.434011 iDelay=203, Bit 10, Center 94 (-1 ~ 190) 192
5990 15:36:14.440663 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5991 15:36:14.443583 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5992 15:36:14.446991 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
5993 15:36:14.450642 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5994 15:36:14.453494 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5995 15:36:14.453577 ==
5996 15:36:14.457415 Dram Type= 6, Freq= 0, CH_1, rank 1
5997 15:36:14.463502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5998 15:36:14.463614 ==
5999 15:36:14.463719 DQS Delay:
6000 15:36:14.467469 DQS0 = 0, DQS1 = 0
6001 15:36:14.467552 DQM Delay:
6002 15:36:14.467617 DQM0 = 92, DQM1 = 91
6003 15:36:14.470527 DQ Delay:
6004 15:36:14.473512 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
6005 15:36:14.476849 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
6006 15:36:14.480554 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =84
6007 15:36:14.483622 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =98
6008 15:36:14.483708
6009 15:36:14.483773
6010 15:36:14.490261 [DQSOSCAuto] RK1, (LSB)MR18= 0x1124, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
6011 15:36:14.493414 CH1 RK1: MR19=505, MR18=1124
6012 15:36:14.500455 CH1_RK1: MR19=0x505, MR18=0x1124, DQSOSC=410, MR23=63, INC=64, DEC=42
6013 15:36:14.503255 [RxdqsGatingPostProcess] freq 933
6014 15:36:14.507030 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6015 15:36:14.510165 best DQS0 dly(2T, 0.5T) = (0, 10)
6016 15:36:14.513897 best DQS1 dly(2T, 0.5T) = (0, 10)
6017 15:36:14.516949 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6018 15:36:14.520291 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6019 15:36:14.523591 best DQS0 dly(2T, 0.5T) = (0, 10)
6020 15:36:14.526697 best DQS1 dly(2T, 0.5T) = (0, 10)
6021 15:36:14.529913 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6022 15:36:14.533051 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6023 15:36:14.536937 Pre-setting of DQS Precalculation
6024 15:36:14.540237 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6025 15:36:14.549771 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6026 15:36:14.556350 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6027 15:36:14.556465
6028 15:36:14.556562
6029 15:36:14.559967 [Calibration Summary] 1866 Mbps
6030 15:36:14.560075 CH 0, Rank 0
6031 15:36:14.562843 SW Impedance : PASS
6032 15:36:14.562950 DUTY Scan : NO K
6033 15:36:14.566436 ZQ Calibration : PASS
6034 15:36:14.569626 Jitter Meter : NO K
6035 15:36:14.569710 CBT Training : PASS
6036 15:36:14.573298 Write leveling : PASS
6037 15:36:14.576372 RX DQS gating : PASS
6038 15:36:14.576476 RX DQ/DQS(RDDQC) : PASS
6039 15:36:14.579383 TX DQ/DQS : PASS
6040 15:36:14.583137 RX DATLAT : PASS
6041 15:36:14.583251 RX DQ/DQS(Engine): PASS
6042 15:36:14.586213 TX OE : NO K
6043 15:36:14.586291 All Pass.
6044 15:36:14.586355
6045 15:36:14.589326 CH 0, Rank 1
6046 15:36:14.589398 SW Impedance : PASS
6047 15:36:14.592826 DUTY Scan : NO K
6048 15:36:14.595840 ZQ Calibration : PASS
6049 15:36:14.595922 Jitter Meter : NO K
6050 15:36:14.599754 CBT Training : PASS
6051 15:36:14.603021 Write leveling : PASS
6052 15:36:14.603096 RX DQS gating : PASS
6053 15:36:14.606211 RX DQ/DQS(RDDQC) : PASS
6054 15:36:14.609443 TX DQ/DQS : PASS
6055 15:36:14.609524 RX DATLAT : PASS
6056 15:36:14.612653 RX DQ/DQS(Engine): PASS
6057 15:36:14.615732 TX OE : NO K
6058 15:36:14.615815 All Pass.
6059 15:36:14.615894
6060 15:36:14.615966 CH 1, Rank 0
6061 15:36:14.619331 SW Impedance : PASS
6062 15:36:14.622591 DUTY Scan : NO K
6063 15:36:14.622666 ZQ Calibration : PASS
6064 15:36:14.625931 Jitter Meter : NO K
6065 15:36:14.626018 CBT Training : PASS
6066 15:36:14.628971 Write leveling : PASS
6067 15:36:14.632861 RX DQS gating : PASS
6068 15:36:14.632942 RX DQ/DQS(RDDQC) : PASS
6069 15:36:14.635955 TX DQ/DQS : PASS
6070 15:36:14.639342 RX DATLAT : PASS
6071 15:36:14.639453 RX DQ/DQS(Engine): PASS
6072 15:36:14.642421 TX OE : NO K
6073 15:36:14.642491 All Pass.
6074 15:36:14.642552
6075 15:36:14.645614 CH 1, Rank 1
6076 15:36:14.645687 SW Impedance : PASS
6077 15:36:14.649230 DUTY Scan : NO K
6078 15:36:14.652499 ZQ Calibration : PASS
6079 15:36:14.652580 Jitter Meter : NO K
6080 15:36:14.655680 CBT Training : PASS
6081 15:36:14.659496 Write leveling : PASS
6082 15:36:14.659576 RX DQS gating : PASS
6083 15:36:14.662522 RX DQ/DQS(RDDQC) : PASS
6084 15:36:14.665644 TX DQ/DQS : PASS
6085 15:36:14.665755 RX DATLAT : PASS
6086 15:36:14.669053 RX DQ/DQS(Engine): PASS
6087 15:36:14.669136 TX OE : NO K
6088 15:36:14.672215 All Pass.
6089 15:36:14.672326
6090 15:36:14.672389 DramC Write-DBI off
6091 15:36:14.676082 PER_BANK_REFRESH: Hybrid Mode
6092 15:36:14.679225 TX_TRACKING: ON
6093 15:36:14.686111 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6094 15:36:14.689182 [FAST_K] Save calibration result to emmc
6095 15:36:14.695949 dramc_set_vcore_voltage set vcore to 650000
6096 15:36:14.696086 Read voltage for 400, 6
6097 15:36:14.696193 Vio18 = 0
6098 15:36:14.698936 Vcore = 650000
6099 15:36:14.699090 Vdram = 0
6100 15:36:14.699182 Vddq = 0
6101 15:36:14.702380 Vmddr = 0
6102 15:36:14.705533 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6103 15:36:14.712495 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6104 15:36:14.715675 MEM_TYPE=3, freq_sel=20
6105 15:36:14.715813 sv_algorithm_assistance_LP4_800
6106 15:36:14.722428 ============ PULL DRAM RESETB DOWN ============
6107 15:36:14.725708 ========== PULL DRAM RESETB DOWN end =========
6108 15:36:14.728822 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6109 15:36:14.732127 ===================================
6110 15:36:14.735307 LPDDR4 DRAM CONFIGURATION
6111 15:36:14.738460 ===================================
6112 15:36:14.741717 EX_ROW_EN[0] = 0x0
6113 15:36:14.741817 EX_ROW_EN[1] = 0x0
6114 15:36:14.745510 LP4Y_EN = 0x0
6115 15:36:14.745606 WORK_FSP = 0x0
6116 15:36:14.748808 WL = 0x2
6117 15:36:14.748905 RL = 0x2
6118 15:36:14.751681 BL = 0x2
6119 15:36:14.751788 RPST = 0x0
6120 15:36:14.755554 RD_PRE = 0x0
6121 15:36:14.755641 WR_PRE = 0x1
6122 15:36:14.758729 WR_PST = 0x0
6123 15:36:14.758831 DBI_WR = 0x0
6124 15:36:14.762030 DBI_RD = 0x0
6125 15:36:14.765019 OTF = 0x1
6126 15:36:14.768773 ===================================
6127 15:36:14.768874 ===================================
6128 15:36:14.771756 ANA top config
6129 15:36:14.775254 ===================================
6130 15:36:14.778738 DLL_ASYNC_EN = 0
6131 15:36:14.778835 ALL_SLAVE_EN = 1
6132 15:36:14.781797 NEW_RANK_MODE = 1
6133 15:36:14.784845 DLL_IDLE_MODE = 1
6134 15:36:14.788493 LP45_APHY_COMB_EN = 1
6135 15:36:14.791572 TX_ODT_DIS = 1
6136 15:36:14.791656 NEW_8X_MODE = 1
6137 15:36:14.794678 ===================================
6138 15:36:14.798449 ===================================
6139 15:36:14.801648 data_rate = 800
6140 15:36:14.804879 CKR = 1
6141 15:36:14.808431 DQ_P2S_RATIO = 4
6142 15:36:14.811443 ===================================
6143 15:36:14.814789 CA_P2S_RATIO = 4
6144 15:36:14.817787 DQ_CA_OPEN = 0
6145 15:36:14.817872 DQ_SEMI_OPEN = 1
6146 15:36:14.821370 CA_SEMI_OPEN = 1
6147 15:36:14.824785 CA_FULL_RATE = 0
6148 15:36:14.827756 DQ_CKDIV4_EN = 0
6149 15:36:14.831286 CA_CKDIV4_EN = 1
6150 15:36:14.834543 CA_PREDIV_EN = 0
6151 15:36:14.834629 PH8_DLY = 0
6152 15:36:14.838342 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6153 15:36:14.841573 DQ_AAMCK_DIV = 0
6154 15:36:14.844811 CA_AAMCK_DIV = 0
6155 15:36:14.847987 CA_ADMCK_DIV = 4
6156 15:36:14.851251 DQ_TRACK_CA_EN = 0
6157 15:36:14.851360 CA_PICK = 800
6158 15:36:14.854257 CA_MCKIO = 400
6159 15:36:14.858113 MCKIO_SEMI = 400
6160 15:36:14.861311 PLL_FREQ = 3016
6161 15:36:14.864537 DQ_UI_PI_RATIO = 32
6162 15:36:14.867597 CA_UI_PI_RATIO = 32
6163 15:36:14.870848 ===================================
6164 15:36:14.874860 ===================================
6165 15:36:14.878013 memory_type:LPDDR4
6166 15:36:14.878098 GP_NUM : 10
6167 15:36:14.881056 SRAM_EN : 1
6168 15:36:14.881139 MD32_EN : 0
6169 15:36:14.884079 ===================================
6170 15:36:14.887528 [ANA_INIT] >>>>>>>>>>>>>>
6171 15:36:14.891021 <<<<<< [CONFIGURE PHASE]: ANA_TX
6172 15:36:14.894258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6173 15:36:14.897703 ===================================
6174 15:36:14.900808 data_rate = 800,PCW = 0X7400
6175 15:36:14.904061 ===================================
6176 15:36:14.907165 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6177 15:36:14.910934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6178 15:36:14.923880 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6179 15:36:14.927060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6180 15:36:14.930809 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6181 15:36:14.934244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6182 15:36:14.937020 [ANA_INIT] flow start
6183 15:36:14.940494 [ANA_INIT] PLL >>>>>>>>
6184 15:36:14.940584 [ANA_INIT] PLL <<<<<<<<
6185 15:36:14.943693 [ANA_INIT] MIDPI >>>>>>>>
6186 15:36:14.946985 [ANA_INIT] MIDPI <<<<<<<<
6187 15:36:14.950132 [ANA_INIT] DLL >>>>>>>>
6188 15:36:14.950237 [ANA_INIT] flow end
6189 15:36:14.953819 ============ LP4 DIFF to SE enter ============
6190 15:36:14.960176 ============ LP4 DIFF to SE exit ============
6191 15:36:14.960259 [ANA_INIT] <<<<<<<<<<<<<
6192 15:36:14.964041 [Flow] Enable top DCM control >>>>>
6193 15:36:14.967136 [Flow] Enable top DCM control <<<<<
6194 15:36:14.970268 Enable DLL master slave shuffle
6195 15:36:14.976703 ==============================================================
6196 15:36:14.976829 Gating Mode config
6197 15:36:14.983766 ==============================================================
6198 15:36:14.986976 Config description:
6199 15:36:14.996876 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6200 15:36:15.003384 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6201 15:36:15.007012 SELPH_MODE 0: By rank 1: By Phase
6202 15:36:15.013577 ==============================================================
6203 15:36:15.016588 GAT_TRACK_EN = 0
6204 15:36:15.016713 RX_GATING_MODE = 2
6205 15:36:15.020107 RX_GATING_TRACK_MODE = 2
6206 15:36:15.023296 SELPH_MODE = 1
6207 15:36:15.026832 PICG_EARLY_EN = 1
6208 15:36:15.030025 VALID_LAT_VALUE = 1
6209 15:36:15.036973 ==============================================================
6210 15:36:15.040130 Enter into Gating configuration >>>>
6211 15:36:15.043246 Exit from Gating configuration <<<<
6212 15:36:15.046856 Enter into DVFS_PRE_config >>>>>
6213 15:36:15.056807 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6214 15:36:15.059939 Exit from DVFS_PRE_config <<<<<
6215 15:36:15.063564 Enter into PICG configuration >>>>
6216 15:36:15.066738 Exit from PICG configuration <<<<
6217 15:36:15.070024 [RX_INPUT] configuration >>>>>
6218 15:36:15.073093 [RX_INPUT] configuration <<<<<
6219 15:36:15.076926 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6220 15:36:15.083223 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6221 15:36:15.089610 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6222 15:36:15.092809 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6223 15:36:15.099867 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6224 15:36:15.105971 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6225 15:36:15.109494 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6226 15:36:15.116122 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6227 15:36:15.119626 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6228 15:36:15.123223 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6229 15:36:15.126203 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6230 15:36:15.132523 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6231 15:36:15.135930 ===================================
6232 15:36:15.136019 LPDDR4 DRAM CONFIGURATION
6233 15:36:15.139182 ===================================
6234 15:36:15.142639 EX_ROW_EN[0] = 0x0
6235 15:36:15.145756 EX_ROW_EN[1] = 0x0
6236 15:36:15.145886 LP4Y_EN = 0x0
6237 15:36:15.149492 WORK_FSP = 0x0
6238 15:36:15.149582 WL = 0x2
6239 15:36:15.152660 RL = 0x2
6240 15:36:15.152743 BL = 0x2
6241 15:36:15.155869 RPST = 0x0
6242 15:36:15.155950 RD_PRE = 0x0
6243 15:36:15.159336 WR_PRE = 0x1
6244 15:36:15.159451 WR_PST = 0x0
6245 15:36:15.162644 DBI_WR = 0x0
6246 15:36:15.162726 DBI_RD = 0x0
6247 15:36:15.166122 OTF = 0x1
6248 15:36:15.169087 ===================================
6249 15:36:15.172910 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6250 15:36:15.176291 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6251 15:36:15.182688 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6252 15:36:15.185966 ===================================
6253 15:36:15.186053 LPDDR4 DRAM CONFIGURATION
6254 15:36:15.189079 ===================================
6255 15:36:15.192226 EX_ROW_EN[0] = 0x10
6256 15:36:15.195604 EX_ROW_EN[1] = 0x0
6257 15:36:15.195683 LP4Y_EN = 0x0
6258 15:36:15.198863 WORK_FSP = 0x0
6259 15:36:15.198951 WL = 0x2
6260 15:36:15.202659 RL = 0x2
6261 15:36:15.202736 BL = 0x2
6262 15:36:15.205817 RPST = 0x0
6263 15:36:15.205940 RD_PRE = 0x0
6264 15:36:15.208981 WR_PRE = 0x1
6265 15:36:15.209089 WR_PST = 0x0
6266 15:36:15.212145 DBI_WR = 0x0
6267 15:36:15.212245 DBI_RD = 0x0
6268 15:36:15.215199 OTF = 0x1
6269 15:36:15.219093 ===================================
6270 15:36:15.225667 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6271 15:36:15.228536 nWR fixed to 30
6272 15:36:15.228627 [ModeRegInit_LP4] CH0 RK0
6273 15:36:15.232240 [ModeRegInit_LP4] CH0 RK1
6274 15:36:15.235309 [ModeRegInit_LP4] CH1 RK0
6275 15:36:15.238520 [ModeRegInit_LP4] CH1 RK1
6276 15:36:15.238637 match AC timing 19
6277 15:36:15.245431 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6278 15:36:15.248596 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6279 15:36:15.252062 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6280 15:36:15.258966 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6281 15:36:15.262050 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6282 15:36:15.262131 ==
6283 15:36:15.265824 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 15:36:15.268819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 15:36:15.268911 ==
6286 15:36:15.275291 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6287 15:36:15.281963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6288 15:36:15.285080 [CA 0] Center 36 (8~64) winsize 57
6289 15:36:15.285180 [CA 1] Center 36 (8~64) winsize 57
6290 15:36:15.289034 [CA 2] Center 36 (8~64) winsize 57
6291 15:36:15.292192 [CA 3] Center 36 (8~64) winsize 57
6292 15:36:15.295423 [CA 4] Center 36 (8~64) winsize 57
6293 15:36:15.298699 [CA 5] Center 36 (8~64) winsize 57
6294 15:36:15.298782
6295 15:36:15.301811 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6296 15:36:15.301904
6297 15:36:15.305139 [CATrainingPosCal] consider 1 rank data
6298 15:36:15.308459 u2DelayCellTimex100 = 270/100 ps
6299 15:36:15.311930 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 15:36:15.318324 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 15:36:15.321520 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 15:36:15.325187 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 15:36:15.328451 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 15:36:15.331943 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 15:36:15.332021
6306 15:36:15.335073 CA PerBit enable=1, Macro0, CA PI delay=36
6307 15:36:15.335156
6308 15:36:15.338200 [CBTSetCACLKResult] CA Dly = 36
6309 15:36:15.338299 CS Dly: 1 (0~32)
6310 15:36:15.341688 ==
6311 15:36:15.345415 Dram Type= 6, Freq= 0, CH_0, rank 1
6312 15:36:15.348570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 15:36:15.348654 ==
6314 15:36:15.351422 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6315 15:36:15.357926 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6316 15:36:15.361481 [CA 0] Center 36 (8~64) winsize 57
6317 15:36:15.364725 [CA 1] Center 36 (8~64) winsize 57
6318 15:36:15.368353 [CA 2] Center 36 (8~64) winsize 57
6319 15:36:15.371339 [CA 3] Center 36 (8~64) winsize 57
6320 15:36:15.375005 [CA 4] Center 36 (8~64) winsize 57
6321 15:36:15.378191 [CA 5] Center 36 (8~64) winsize 57
6322 15:36:15.378277
6323 15:36:15.381456 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6324 15:36:15.381549
6325 15:36:15.384406 [CATrainingPosCal] consider 2 rank data
6326 15:36:15.388120 u2DelayCellTimex100 = 270/100 ps
6327 15:36:15.391423 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 15:36:15.394629 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 15:36:15.397907 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 15:36:15.404484 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 15:36:15.408087 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 15:36:15.411492 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 15:36:15.411577
6334 15:36:15.414564 CA PerBit enable=1, Macro0, CA PI delay=36
6335 15:36:15.414646
6336 15:36:15.417593 [CBTSetCACLKResult] CA Dly = 36
6337 15:36:15.417675 CS Dly: 1 (0~32)
6338 15:36:15.417742
6339 15:36:15.421295 ----->DramcWriteLeveling(PI) begin...
6340 15:36:15.421381 ==
6341 15:36:15.424087 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 15:36:15.430736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 15:36:15.430828 ==
6344 15:36:15.434066 Write leveling (Byte 0): 40 => 8
6345 15:36:15.437511 Write leveling (Byte 1): 32 => 0
6346 15:36:15.437595 DramcWriteLeveling(PI) end<-----
6347 15:36:15.440752
6348 15:36:15.440836 ==
6349 15:36:15.443957 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 15:36:15.447509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 15:36:15.447588 ==
6352 15:36:15.451062 [Gating] SW mode calibration
6353 15:36:15.457137 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6354 15:36:15.460974 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6355 15:36:15.467321 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6356 15:36:15.471079 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6357 15:36:15.474212 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6358 15:36:15.480546 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6359 15:36:15.484026 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 15:36:15.487376 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 15:36:15.493670 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 15:36:15.497362 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 15:36:15.500677 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6364 15:36:15.503898 Total UI for P1: 0, mck2ui 16
6365 15:36:15.507309 best dqsien dly found for B0: ( 0, 14, 24)
6366 15:36:15.510877 Total UI for P1: 0, mck2ui 16
6367 15:36:15.513868 best dqsien dly found for B1: ( 0, 14, 24)
6368 15:36:15.517151 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6369 15:36:15.520745 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6370 15:36:15.520836
6371 15:36:15.527041 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6372 15:36:15.530149 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6373 15:36:15.533486 [Gating] SW calibration Done
6374 15:36:15.533592 ==
6375 15:36:15.537323 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 15:36:15.540247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 15:36:15.540326 ==
6378 15:36:15.540391 RX Vref Scan: 0
6379 15:36:15.540502
6380 15:36:15.543710 RX Vref 0 -> 0, step: 1
6381 15:36:15.543822
6382 15:36:15.546880 RX Delay -410 -> 252, step: 16
6383 15:36:15.550008 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6384 15:36:15.556987 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6385 15:36:15.560445 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6386 15:36:15.563358 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6387 15:36:15.567013 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6388 15:36:15.573895 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6389 15:36:15.576973 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6390 15:36:15.580257 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6391 15:36:15.583758 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6392 15:36:15.590393 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6393 15:36:15.593506 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6394 15:36:15.597071 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6395 15:36:15.599886 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6396 15:36:15.606717 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6397 15:36:15.609827 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6398 15:36:15.613734 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6399 15:36:15.613841 ==
6400 15:36:15.616853 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 15:36:15.620149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 15:36:15.623176 ==
6403 15:36:15.623251 DQS Delay:
6404 15:36:15.623314 DQS0 = 59, DQS1 = 59
6405 15:36:15.627182 DQM Delay:
6406 15:36:15.627257 DQM0 = 18, DQM1 = 10
6407 15:36:15.629946 DQ Delay:
6408 15:36:15.633121 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6409 15:36:15.633200 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6410 15:36:15.636992 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6411 15:36:15.640073 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6412 15:36:15.640148
6413 15:36:15.643236
6414 15:36:15.643316 ==
6415 15:36:15.646502 Dram Type= 6, Freq= 0, CH_0, rank 0
6416 15:36:15.649626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 15:36:15.649702 ==
6418 15:36:15.649765
6419 15:36:15.649828
6420 15:36:15.653376 TX Vref Scan disable
6421 15:36:15.653451 == TX Byte 0 ==
6422 15:36:15.656725 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6423 15:36:15.663208 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6424 15:36:15.663292 == TX Byte 1 ==
6425 15:36:15.666849 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6426 15:36:15.673239 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6427 15:36:15.673323 ==
6428 15:36:15.676360 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 15:36:15.679883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 15:36:15.679967 ==
6431 15:36:15.680032
6432 15:36:15.680092
6433 15:36:15.682992 TX Vref Scan disable
6434 15:36:15.683091 == TX Byte 0 ==
6435 15:36:15.686265 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6436 15:36:15.692668 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6437 15:36:15.692746 == TX Byte 1 ==
6438 15:36:15.696348 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6439 15:36:15.702951 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6440 15:36:15.703053
6441 15:36:15.703148 [DATLAT]
6442 15:36:15.706347 Freq=400, CH0 RK0
6443 15:36:15.706444
6444 15:36:15.706532 DATLAT Default: 0xf
6445 15:36:15.709570 0, 0xFFFF, sum = 0
6446 15:36:15.709649 1, 0xFFFF, sum = 0
6447 15:36:15.712814 2, 0xFFFF, sum = 0
6448 15:36:15.712892 3, 0xFFFF, sum = 0
6449 15:36:15.715925 4, 0xFFFF, sum = 0
6450 15:36:15.716001 5, 0xFFFF, sum = 0
6451 15:36:15.719554 6, 0xFFFF, sum = 0
6452 15:36:15.719637 7, 0xFFFF, sum = 0
6453 15:36:15.722849 8, 0xFFFF, sum = 0
6454 15:36:15.722929 9, 0xFFFF, sum = 0
6455 15:36:15.725932 10, 0xFFFF, sum = 0
6456 15:36:15.726033 11, 0xFFFF, sum = 0
6457 15:36:15.729113 12, 0xFFFF, sum = 0
6458 15:36:15.729194 13, 0x0, sum = 1
6459 15:36:15.732758 14, 0x0, sum = 2
6460 15:36:15.732856 15, 0x0, sum = 3
6461 15:36:15.735976 16, 0x0, sum = 4
6462 15:36:15.736062 best_step = 14
6463 15:36:15.736127
6464 15:36:15.736187 ==
6465 15:36:15.739014 Dram Type= 6, Freq= 0, CH_0, rank 0
6466 15:36:15.745930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 15:36:15.746022 ==
6468 15:36:15.746089 RX Vref Scan: 1
6469 15:36:15.746153
6470 15:36:15.748968 RX Vref 0 -> 0, step: 1
6471 15:36:15.749049
6472 15:36:15.752804 RX Delay -359 -> 252, step: 8
6473 15:36:15.752885
6474 15:36:15.756009 Set Vref, RX VrefLevel [Byte0]: 60
6475 15:36:15.759160 [Byte1]: 58
6476 15:36:15.762510
6477 15:36:15.762582 Final RX Vref Byte 0 = 60 to rank0
6478 15:36:15.765769 Final RX Vref Byte 1 = 58 to rank0
6479 15:36:15.769094 Final RX Vref Byte 0 = 60 to rank1
6480 15:36:15.772822 Final RX Vref Byte 1 = 58 to rank1==
6481 15:36:15.775600 Dram Type= 6, Freq= 0, CH_0, rank 0
6482 15:36:15.782622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 15:36:15.782718 ==
6484 15:36:15.782785 DQS Delay:
6485 15:36:15.785648 DQS0 = 60, DQS1 = 68
6486 15:36:15.785720 DQM Delay:
6487 15:36:15.785780 DQM0 = 14, DQM1 = 13
6488 15:36:15.788859 DQ Delay:
6489 15:36:15.792377 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6490 15:36:15.795648 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6491 15:36:15.795808 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6492 15:36:15.798863 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6493 15:36:15.802058
6494 15:36:15.802139
6495 15:36:15.808981 [DQSOSCAuto] RK0, (LSB)MR18= 0x8685, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6496 15:36:15.812182 CH0 RK0: MR19=C0C, MR18=8685
6497 15:36:15.818825 CH0_RK0: MR19=0xC0C, MR18=0x8685, DQSOSC=393, MR23=63, INC=382, DEC=254
6498 15:36:15.818907 ==
6499 15:36:15.822410 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 15:36:15.825866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 15:36:15.825944 ==
6502 15:36:15.828795 [Gating] SW mode calibration
6503 15:36:15.835480 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6504 15:36:15.841808 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6505 15:36:15.845756 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6506 15:36:15.848623 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6507 15:36:15.855520 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 15:36:15.858656 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 15:36:15.861826 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 15:36:15.868826 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 15:36:15.871983 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 15:36:15.875273 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 15:36:15.881913 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6514 15:36:15.881998 Total UI for P1: 0, mck2ui 16
6515 15:36:15.884995 best dqsien dly found for B0: ( 0, 14, 24)
6516 15:36:15.888755 Total UI for P1: 0, mck2ui 16
6517 15:36:15.891721 best dqsien dly found for B1: ( 0, 14, 24)
6518 15:36:15.895301 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6519 15:36:15.902013 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6520 15:36:15.902096
6521 15:36:15.905191 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6522 15:36:15.908581 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6523 15:36:15.911890 [Gating] SW calibration Done
6524 15:36:15.911972 ==
6525 15:36:15.915027 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 15:36:15.918337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 15:36:15.918436 ==
6528 15:36:15.921987 RX Vref Scan: 0
6529 15:36:15.922085
6530 15:36:15.922181 RX Vref 0 -> 0, step: 1
6531 15:36:15.922256
6532 15:36:15.925109 RX Delay -410 -> 252, step: 16
6533 15:36:15.928267 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6534 15:36:15.935523 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6535 15:36:15.938447 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6536 15:36:15.941612 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6537 15:36:15.944732 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6538 15:36:15.951601 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6539 15:36:15.955179 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6540 15:36:15.958251 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6541 15:36:15.961618 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6542 15:36:15.967902 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6543 15:36:15.971279 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6544 15:36:15.974651 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6545 15:36:15.981698 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6546 15:36:15.985044 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6547 15:36:15.988324 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6548 15:36:15.991597 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6549 15:36:15.991680 ==
6550 15:36:15.994596 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 15:36:16.001236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 15:36:16.001321 ==
6553 15:36:16.001387 DQS Delay:
6554 15:36:16.004982 DQS0 = 59, DQS1 = 59
6555 15:36:16.005065 DQM Delay:
6556 15:36:16.007738 DQM0 = 16, DQM1 = 10
6557 15:36:16.007820 DQ Delay:
6558 15:36:16.011549 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6559 15:36:16.014798 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6560 15:36:16.018144 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6561 15:36:16.021196 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6562 15:36:16.021279
6563 15:36:16.021343
6564 15:36:16.021404 ==
6565 15:36:16.024416 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 15:36:16.027999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 15:36:16.028082 ==
6568 15:36:16.028148
6569 15:36:16.028209
6570 15:36:16.031100 TX Vref Scan disable
6571 15:36:16.031209 == TX Byte 0 ==
6572 15:36:16.038173 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6573 15:36:16.041359 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6574 15:36:16.041443 == TX Byte 1 ==
6575 15:36:16.044482 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6576 15:36:16.051190 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6577 15:36:16.051276 ==
6578 15:36:16.054557 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 15:36:16.057628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 15:36:16.057712 ==
6581 15:36:16.057778
6582 15:36:16.057839
6583 15:36:16.061472 TX Vref Scan disable
6584 15:36:16.061564 == TX Byte 0 ==
6585 15:36:16.067810 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6586 15:36:16.071424 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6587 15:36:16.071516 == TX Byte 1 ==
6588 15:36:16.074564 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6589 15:36:16.081135 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6590 15:36:16.081247
6591 15:36:16.081333 [DATLAT]
6592 15:36:16.084584 Freq=400, CH0 RK1
6593 15:36:16.084685
6594 15:36:16.084753 DATLAT Default: 0xe
6595 15:36:16.087511 0, 0xFFFF, sum = 0
6596 15:36:16.087594 1, 0xFFFF, sum = 0
6597 15:36:16.090909 2, 0xFFFF, sum = 0
6598 15:36:16.090991 3, 0xFFFF, sum = 0
6599 15:36:16.094623 4, 0xFFFF, sum = 0
6600 15:36:16.094748 5, 0xFFFF, sum = 0
6601 15:36:16.097698 6, 0xFFFF, sum = 0
6602 15:36:16.097813 7, 0xFFFF, sum = 0
6603 15:36:16.101088 8, 0xFFFF, sum = 0
6604 15:36:16.101171 9, 0xFFFF, sum = 0
6605 15:36:16.104218 10, 0xFFFF, sum = 0
6606 15:36:16.104300 11, 0xFFFF, sum = 0
6607 15:36:16.107498 12, 0xFFFF, sum = 0
6608 15:36:16.107614 13, 0x0, sum = 1
6609 15:36:16.111182 14, 0x0, sum = 2
6610 15:36:16.111265 15, 0x0, sum = 3
6611 15:36:16.114672 16, 0x0, sum = 4
6612 15:36:16.114755 best_step = 14
6613 15:36:16.114861
6614 15:36:16.114969 ==
6615 15:36:16.117650 Dram Type= 6, Freq= 0, CH_0, rank 1
6616 15:36:16.124126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 15:36:16.124208 ==
6618 15:36:16.124273 RX Vref Scan: 0
6619 15:36:16.124334
6620 15:36:16.127316 RX Vref 0 -> 0, step: 1
6621 15:36:16.127437
6622 15:36:16.130592 RX Delay -359 -> 252, step: 8
6623 15:36:16.137282 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6624 15:36:16.140480 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6625 15:36:16.144077 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6626 15:36:16.147274 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6627 15:36:16.154159 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6628 15:36:16.157203 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6629 15:36:16.160457 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6630 15:36:16.167244 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6631 15:36:16.170574 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6632 15:36:16.173753 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6633 15:36:16.176957 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6634 15:36:16.183854 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6635 15:36:16.187105 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6636 15:36:16.190018 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6637 15:36:16.193649 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6638 15:36:16.200194 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6639 15:36:16.200277 ==
6640 15:36:16.203751 Dram Type= 6, Freq= 0, CH_0, rank 1
6641 15:36:16.206520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 15:36:16.206621 ==
6643 15:36:16.206718 DQS Delay:
6644 15:36:16.210089 DQS0 = 60, DQS1 = 68
6645 15:36:16.210196 DQM Delay:
6646 15:36:16.213222 DQM0 = 12, DQM1 = 14
6647 15:36:16.213296 DQ Delay:
6648 15:36:16.217018 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6649 15:36:16.220022 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6650 15:36:16.223349 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6651 15:36:16.226509 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6652 15:36:16.226594
6653 15:36:16.226660
6654 15:36:16.233543 [DQSOSCAuto] RK1, (LSB)MR18= 0xca7e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6655 15:36:16.236922 CH0 RK1: MR19=C0C, MR18=CA7E
6656 15:36:16.243112 CH0_RK1: MR19=0xC0C, MR18=0xCA7E, DQSOSC=384, MR23=63, INC=400, DEC=267
6657 15:36:16.246735 [RxdqsGatingPostProcess] freq 400
6658 15:36:16.253091 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6659 15:36:16.256173 best DQS0 dly(2T, 0.5T) = (0, 10)
6660 15:36:16.259365 best DQS1 dly(2T, 0.5T) = (0, 10)
6661 15:36:16.263052 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6662 15:36:16.266177 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6663 15:36:16.266252 best DQS0 dly(2T, 0.5T) = (0, 10)
6664 15:36:16.269390 best DQS1 dly(2T, 0.5T) = (0, 10)
6665 15:36:16.272742 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6666 15:36:16.275919 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6667 15:36:16.279143 Pre-setting of DQS Precalculation
6668 15:36:16.285933 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6669 15:36:16.286040 ==
6670 15:36:16.289126 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 15:36:16.292388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 15:36:16.292500 ==
6673 15:36:16.299448 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6674 15:36:16.305697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6675 15:36:16.308819 [CA 0] Center 36 (8~64) winsize 57
6676 15:36:16.308902 [CA 1] Center 36 (8~64) winsize 57
6677 15:36:16.312376 [CA 2] Center 36 (8~64) winsize 57
6678 15:36:16.315770 [CA 3] Center 36 (8~64) winsize 57
6679 15:36:16.318865 [CA 4] Center 36 (8~64) winsize 57
6680 15:36:16.322436 [CA 5] Center 36 (8~64) winsize 57
6681 15:36:16.322520
6682 15:36:16.325866 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6683 15:36:16.325948
6684 15:36:16.329106 [CATrainingPosCal] consider 1 rank data
6685 15:36:16.332415 u2DelayCellTimex100 = 270/100 ps
6686 15:36:16.335487 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 15:36:16.342782 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 15:36:16.345618 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 15:36:16.348832 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 15:36:16.352425 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 15:36:16.355586 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 15:36:16.355687
6693 15:36:16.359351 CA PerBit enable=1, Macro0, CA PI delay=36
6694 15:36:16.359463
6695 15:36:16.362343 [CBTSetCACLKResult] CA Dly = 36
6696 15:36:16.362427 CS Dly: 1 (0~32)
6697 15:36:16.365510 ==
6698 15:36:16.365624 Dram Type= 6, Freq= 0, CH_1, rank 1
6699 15:36:16.372347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 15:36:16.372430 ==
6701 15:36:16.375621 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6702 15:36:16.381986 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6703 15:36:16.385829 [CA 0] Center 36 (8~64) winsize 57
6704 15:36:16.388887 [CA 1] Center 36 (8~64) winsize 57
6705 15:36:16.392029 [CA 2] Center 36 (8~64) winsize 57
6706 15:36:16.395785 [CA 3] Center 36 (8~64) winsize 57
6707 15:36:16.398865 [CA 4] Center 36 (8~64) winsize 57
6708 15:36:16.401958 [CA 5] Center 36 (8~64) winsize 57
6709 15:36:16.402034
6710 15:36:16.405184 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6711 15:36:16.405256
6712 15:36:16.408523 [CATrainingPosCal] consider 2 rank data
6713 15:36:16.412222 u2DelayCellTimex100 = 270/100 ps
6714 15:36:16.415474 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 15:36:16.418582 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 15:36:16.421650 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 15:36:16.425434 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 15:36:16.431946 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 15:36:16.435204 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 15:36:16.435305
6721 15:36:16.438596 CA PerBit enable=1, Macro0, CA PI delay=36
6722 15:36:16.438673
6723 15:36:16.442182 [CBTSetCACLKResult] CA Dly = 36
6724 15:36:16.442258 CS Dly: 1 (0~32)
6725 15:36:16.442321
6726 15:36:16.444942 ----->DramcWriteLeveling(PI) begin...
6727 15:36:16.445042 ==
6728 15:36:16.448639 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 15:36:16.455288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 15:36:16.455406 ==
6731 15:36:16.458519 Write leveling (Byte 0): 40 => 8
6732 15:36:16.458604 Write leveling (Byte 1): 40 => 8
6733 15:36:16.462035 DramcWriteLeveling(PI) end<-----
6734 15:36:16.462118
6735 15:36:16.462184 ==
6736 15:36:16.464970 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 15:36:16.471569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 15:36:16.471654 ==
6739 15:36:16.474733 [Gating] SW mode calibration
6740 15:36:16.481584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6741 15:36:16.484703 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6742 15:36:16.491696 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6743 15:36:16.494995 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6744 15:36:16.498063 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6745 15:36:16.504692 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6746 15:36:16.507752 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 15:36:16.511664 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 15:36:16.518036 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 15:36:16.521277 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 15:36:16.524457 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6751 15:36:16.528324 Total UI for P1: 0, mck2ui 16
6752 15:36:16.531347 best dqsien dly found for B0: ( 0, 14, 24)
6753 15:36:16.534628 Total UI for P1: 0, mck2ui 16
6754 15:36:16.538437 best dqsien dly found for B1: ( 0, 14, 24)
6755 15:36:16.541339 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6756 15:36:16.544744 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6757 15:36:16.544845
6758 15:36:16.551593 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6759 15:36:16.554582 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6760 15:36:16.554654 [Gating] SW calibration Done
6761 15:36:16.558119 ==
6762 15:36:16.558190 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 15:36:16.564914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 15:36:16.564987 ==
6765 15:36:16.565049 RX Vref Scan: 0
6766 15:36:16.565107
6767 15:36:16.567816 RX Vref 0 -> 0, step: 1
6768 15:36:16.567902
6769 15:36:16.571273 RX Delay -410 -> 252, step: 16
6770 15:36:16.574477 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6771 15:36:16.577864 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6772 15:36:16.584554 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6773 15:36:16.587923 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6774 15:36:16.591060 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6775 15:36:16.594956 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6776 15:36:16.601084 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6777 15:36:16.604275 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6778 15:36:16.607516 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6779 15:36:16.611232 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6780 15:36:16.617598 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6781 15:36:16.621002 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6782 15:36:16.624813 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6783 15:36:16.627874 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6784 15:36:16.634126 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6785 15:36:16.637826 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6786 15:36:16.637902 ==
6787 15:36:16.640934 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 15:36:16.644330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 15:36:16.644408 ==
6790 15:36:16.647317 DQS Delay:
6791 15:36:16.647428 DQS0 = 51, DQS1 = 67
6792 15:36:16.650875 DQM Delay:
6793 15:36:16.650986 DQM0 = 13, DQM1 = 19
6794 15:36:16.651088 DQ Delay:
6795 15:36:16.654026 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6796 15:36:16.657735 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6797 15:36:16.660972 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6798 15:36:16.663852 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6799 15:36:16.663932
6800 15:36:16.664009
6801 15:36:16.664069 ==
6802 15:36:16.667733 Dram Type= 6, Freq= 0, CH_1, rank 0
6803 15:36:16.674243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 15:36:16.674324 ==
6805 15:36:16.674388
6806 15:36:16.674474
6807 15:36:16.674541 TX Vref Scan disable
6808 15:36:16.677473 == TX Byte 0 ==
6809 15:36:16.680522 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6810 15:36:16.683722 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6811 15:36:16.687269 == TX Byte 1 ==
6812 15:36:16.690346 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6813 15:36:16.693709 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6814 15:36:16.693791 ==
6815 15:36:16.697064 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 15:36:16.703935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 15:36:16.704023 ==
6818 15:36:16.704104
6819 15:36:16.704177
6820 15:36:16.707246 TX Vref Scan disable
6821 15:36:16.707316 == TX Byte 0 ==
6822 15:36:16.710463 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6823 15:36:16.713715 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6824 15:36:16.717340 == TX Byte 1 ==
6825 15:36:16.720624 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6826 15:36:16.723749 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6827 15:36:16.726959
6828 15:36:16.727043 [DATLAT]
6829 15:36:16.727111 Freq=400, CH1 RK0
6830 15:36:16.727175
6831 15:36:16.730702 DATLAT Default: 0xf
6832 15:36:16.730780 0, 0xFFFF, sum = 0
6833 15:36:16.733993 1, 0xFFFF, sum = 0
6834 15:36:16.734070 2, 0xFFFF, sum = 0
6835 15:36:16.737063 3, 0xFFFF, sum = 0
6836 15:36:16.737138 4, 0xFFFF, sum = 0
6837 15:36:16.740261 5, 0xFFFF, sum = 0
6838 15:36:16.740333 6, 0xFFFF, sum = 0
6839 15:36:16.743479 7, 0xFFFF, sum = 0
6840 15:36:16.747395 8, 0xFFFF, sum = 0
6841 15:36:16.747474 9, 0xFFFF, sum = 0
6842 15:36:16.750500 10, 0xFFFF, sum = 0
6843 15:36:16.750619 11, 0xFFFF, sum = 0
6844 15:36:16.753606 12, 0xFFFF, sum = 0
6845 15:36:16.753699 13, 0x0, sum = 1
6846 15:36:16.756751 14, 0x0, sum = 2
6847 15:36:16.756829 15, 0x0, sum = 3
6848 15:36:16.760650 16, 0x0, sum = 4
6849 15:36:16.760735 best_step = 14
6850 15:36:16.760824
6851 15:36:16.760890 ==
6852 15:36:16.763572 Dram Type= 6, Freq= 0, CH_1, rank 0
6853 15:36:16.766972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 15:36:16.767050 ==
6855 15:36:16.770031 RX Vref Scan: 1
6856 15:36:16.770106
6857 15:36:16.773870 RX Vref 0 -> 0, step: 1
6858 15:36:16.773965
6859 15:36:16.774034 RX Delay -375 -> 252, step: 8
6860 15:36:16.774097
6861 15:36:16.777025 Set Vref, RX VrefLevel [Byte0]: 56
6862 15:36:16.780014 [Byte1]: 55
6863 15:36:16.786178
6864 15:36:16.786264 Final RX Vref Byte 0 = 56 to rank0
6865 15:36:16.789271 Final RX Vref Byte 1 = 55 to rank0
6866 15:36:16.792545 Final RX Vref Byte 0 = 56 to rank1
6867 15:36:16.795962 Final RX Vref Byte 1 = 55 to rank1==
6868 15:36:16.799033 Dram Type= 6, Freq= 0, CH_1, rank 0
6869 15:36:16.805774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 15:36:16.805862 ==
6871 15:36:16.805933 DQS Delay:
6872 15:36:16.809393 DQS0 = 52, DQS1 = 64
6873 15:36:16.809476 DQM Delay:
6874 15:36:16.809543 DQM0 = 9, DQM1 = 9
6875 15:36:16.812452 DQ Delay:
6876 15:36:16.812531 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6877 15:36:16.815969 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6878 15:36:16.819530 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6879 15:36:16.822303 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6880 15:36:16.822387
6881 15:36:16.822455
6882 15:36:16.832348 [DQSOSCAuto] RK0, (LSB)MR18= 0x596d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6883 15:36:16.835497 CH1 RK0: MR19=C0C, MR18=596D
6884 15:36:16.839165 CH1_RK0: MR19=0xC0C, MR18=0x596D, DQSOSC=396, MR23=63, INC=376, DEC=251
6885 15:36:16.842740 ==
6886 15:36:16.845970 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 15:36:16.848975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 15:36:16.849052 ==
6889 15:36:16.852147 [Gating] SW mode calibration
6890 15:36:16.859061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6891 15:36:16.862371 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6892 15:36:16.869298 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6893 15:36:16.872279 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6894 15:36:16.875713 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6895 15:36:16.882260 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6896 15:36:16.885435 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 15:36:16.889101 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 15:36:16.895424 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 15:36:16.898746 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 15:36:16.901948 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6901 15:36:16.905745 Total UI for P1: 0, mck2ui 16
6902 15:36:16.908958 best dqsien dly found for B0: ( 0, 14, 24)
6903 15:36:16.911967 Total UI for P1: 0, mck2ui 16
6904 15:36:16.915428 best dqsien dly found for B1: ( 0, 14, 24)
6905 15:36:16.919110 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6906 15:36:16.922089 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6907 15:36:16.922171
6908 15:36:16.928867 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6909 15:36:16.931714 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6910 15:36:16.935070 [Gating] SW calibration Done
6911 15:36:16.935152 ==
6912 15:36:16.938720 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 15:36:16.942063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 15:36:16.942146 ==
6915 15:36:16.942211 RX Vref Scan: 0
6916 15:36:16.942271
6917 15:36:16.945068 RX Vref 0 -> 0, step: 1
6918 15:36:16.945149
6919 15:36:16.948859 RX Delay -410 -> 252, step: 16
6920 15:36:16.952072 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6921 15:36:16.958489 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6922 15:36:16.962034 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6923 15:36:16.965046 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6924 15:36:16.968275 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6925 15:36:16.975143 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6926 15:36:16.978310 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6927 15:36:16.981483 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6928 15:36:16.985156 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6929 15:36:16.988755 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6930 15:36:16.995237 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6931 15:36:16.998190 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6932 15:36:17.001789 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6933 15:36:17.008685 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6934 15:36:17.011783 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6935 15:36:17.015059 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6936 15:36:17.015141 ==
6937 15:36:17.018816 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 15:36:17.021633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 15:36:17.025156 ==
6940 15:36:17.025237 DQS Delay:
6941 15:36:17.025301 DQS0 = 59, DQS1 = 67
6942 15:36:17.028408 DQM Delay:
6943 15:36:17.028489 DQM0 = 19, DQM1 = 21
6944 15:36:17.031896 DQ Delay:
6945 15:36:17.031976 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6946 15:36:17.034714 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6947 15:36:17.037927 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6948 15:36:17.041503 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6949 15:36:17.041584
6950 15:36:17.041647
6951 15:36:17.045051 ==
6952 15:36:17.048071 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 15:36:17.051615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 15:36:17.051694 ==
6955 15:36:17.051758
6956 15:36:17.051819
6957 15:36:17.054512 TX Vref Scan disable
6958 15:36:17.054588 == TX Byte 0 ==
6959 15:36:17.058323 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6960 15:36:17.064919 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6961 15:36:17.064996 == TX Byte 1 ==
6962 15:36:17.067920 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6963 15:36:17.074885 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6964 15:36:17.074973 ==
6965 15:36:17.078110 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 15:36:17.081161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 15:36:17.081237 ==
6968 15:36:17.081382
6969 15:36:17.081461
6970 15:36:17.084488 TX Vref Scan disable
6971 15:36:17.084588 == TX Byte 0 ==
6972 15:36:17.087697 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6973 15:36:17.094652 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6974 15:36:17.094736 == TX Byte 1 ==
6975 15:36:17.097652 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6976 15:36:17.104868 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6977 15:36:17.104954
6978 15:36:17.105038 [DATLAT]
6979 15:36:17.105117 Freq=400, CH1 RK1
6980 15:36:17.105196
6981 15:36:17.107746 DATLAT Default: 0xe
6982 15:36:17.107837 0, 0xFFFF, sum = 0
6983 15:36:17.111222 1, 0xFFFF, sum = 0
6984 15:36:17.114485 2, 0xFFFF, sum = 0
6985 15:36:17.114594 3, 0xFFFF, sum = 0
6986 15:36:17.117866 4, 0xFFFF, sum = 0
6987 15:36:17.117973 5, 0xFFFF, sum = 0
6988 15:36:17.121557 6, 0xFFFF, sum = 0
6989 15:36:17.121653 7, 0xFFFF, sum = 0
6990 15:36:17.124189 8, 0xFFFF, sum = 0
6991 15:36:17.124277 9, 0xFFFF, sum = 0
6992 15:36:17.127861 10, 0xFFFF, sum = 0
6993 15:36:17.127943 11, 0xFFFF, sum = 0
6994 15:36:17.131381 12, 0xFFFF, sum = 0
6995 15:36:17.131497 13, 0x0, sum = 1
6996 15:36:17.134335 14, 0x0, sum = 2
6997 15:36:17.134417 15, 0x0, sum = 3
6998 15:36:17.137570 16, 0x0, sum = 4
6999 15:36:17.137673 best_step = 14
7000 15:36:17.137771
7001 15:36:17.137847 ==
7002 15:36:17.140959 Dram Type= 6, Freq= 0, CH_1, rank 1
7003 15:36:17.144107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7004 15:36:17.147819 ==
7005 15:36:17.147900 RX Vref Scan: 0
7006 15:36:17.147965
7007 15:36:17.150720 RX Vref 0 -> 0, step: 1
7008 15:36:17.150801
7009 15:36:17.154209 RX Delay -375 -> 252, step: 8
7010 15:36:17.160990 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7011 15:36:17.164138 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7012 15:36:17.167704 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7013 15:36:17.170913 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7014 15:36:17.177676 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7015 15:36:17.180853 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7016 15:36:17.183964 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7017 15:36:17.187184 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7018 15:36:17.194083 iDelay=217, Bit 8, Center -68 (-327 ~ 192) 520
7019 15:36:17.197293 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7020 15:36:17.200390 iDelay=217, Bit 10, Center -52 (-311 ~ 208) 520
7021 15:36:17.203959 iDelay=217, Bit 11, Center -56 (-311 ~ 200) 512
7022 15:36:17.210360 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7023 15:36:17.213770 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7024 15:36:17.217188 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7025 15:36:17.220483 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7026 15:36:17.223598 ==
7027 15:36:17.226742 Dram Type= 6, Freq= 0, CH_1, rank 1
7028 15:36:17.230058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7029 15:36:17.230141 ==
7030 15:36:17.230206 DQS Delay:
7031 15:36:17.233772 DQS0 = 60, DQS1 = 68
7032 15:36:17.233854 DQM Delay:
7033 15:36:17.236731 DQM0 = 12, DQM1 = 14
7034 15:36:17.236828 DQ Delay:
7035 15:36:17.240320 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7036 15:36:17.243799 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7037 15:36:17.246953 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
7038 15:36:17.250154 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
7039 15:36:17.250236
7040 15:36:17.250301
7041 15:36:17.256640 [DQSOSCAuto] RK1, (LSB)MR18= 0x76a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
7042 15:36:17.260476 CH1 RK1: MR19=C0C, MR18=76A7
7043 15:36:17.266701 CH1_RK1: MR19=0xC0C, MR18=0x76A7, DQSOSC=389, MR23=63, INC=390, DEC=260
7044 15:36:17.270430 [RxdqsGatingPostProcess] freq 400
7045 15:36:17.276808 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7046 15:36:17.276943 best DQS0 dly(2T, 0.5T) = (0, 10)
7047 15:36:17.279901 best DQS1 dly(2T, 0.5T) = (0, 10)
7048 15:36:17.283148 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7049 15:36:17.286413 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7050 15:36:17.290035 best DQS0 dly(2T, 0.5T) = (0, 10)
7051 15:36:17.293360 best DQS1 dly(2T, 0.5T) = (0, 10)
7052 15:36:17.296511 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7053 15:36:17.299810 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7054 15:36:17.303488 Pre-setting of DQS Precalculation
7055 15:36:17.306764 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7056 15:36:17.316593 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7057 15:36:17.323020 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7058 15:36:17.323101
7059 15:36:17.323217
7060 15:36:17.326540 [Calibration Summary] 800 Mbps
7061 15:36:17.326623 CH 0, Rank 0
7062 15:36:17.329456 SW Impedance : PASS
7063 15:36:17.329543 DUTY Scan : NO K
7064 15:36:17.333187 ZQ Calibration : PASS
7065 15:36:17.336228 Jitter Meter : NO K
7066 15:36:17.336340 CBT Training : PASS
7067 15:36:17.339523 Write leveling : PASS
7068 15:36:17.342867 RX DQS gating : PASS
7069 15:36:17.342951 RX DQ/DQS(RDDQC) : PASS
7070 15:36:17.346064 TX DQ/DQS : PASS
7071 15:36:17.349552 RX DATLAT : PASS
7072 15:36:17.349639 RX DQ/DQS(Engine): PASS
7073 15:36:17.353155 TX OE : NO K
7074 15:36:17.353239 All Pass.
7075 15:36:17.353323
7076 15:36:17.356090 CH 0, Rank 1
7077 15:36:17.356172 SW Impedance : PASS
7078 15:36:17.359765 DUTY Scan : NO K
7079 15:36:17.362982 ZQ Calibration : PASS
7080 15:36:17.363066 Jitter Meter : NO K
7081 15:36:17.365885 CBT Training : PASS
7082 15:36:17.369713 Write leveling : NO K
7083 15:36:17.369823 RX DQS gating : PASS
7084 15:36:17.372931 RX DQ/DQS(RDDQC) : PASS
7085 15:36:17.373012 TX DQ/DQS : PASS
7086 15:36:17.376061 RX DATLAT : PASS
7087 15:36:17.379881 RX DQ/DQS(Engine): PASS
7088 15:36:17.379962 TX OE : NO K
7089 15:36:17.382897 All Pass.
7090 15:36:17.382978
7091 15:36:17.383042 CH 1, Rank 0
7092 15:36:17.385929 SW Impedance : PASS
7093 15:36:17.386010 DUTY Scan : NO K
7094 15:36:17.389066 ZQ Calibration : PASS
7095 15:36:17.392845 Jitter Meter : NO K
7096 15:36:17.392942 CBT Training : PASS
7097 15:36:17.395995 Write leveling : PASS
7098 15:36:17.399324 RX DQS gating : PASS
7099 15:36:17.399432 RX DQ/DQS(RDDQC) : PASS
7100 15:36:17.402449 TX DQ/DQS : PASS
7101 15:36:17.406038 RX DATLAT : PASS
7102 15:36:17.406137 RX DQ/DQS(Engine): PASS
7103 15:36:17.409192 TX OE : NO K
7104 15:36:17.409291 All Pass.
7105 15:36:17.409356
7106 15:36:17.412884 CH 1, Rank 1
7107 15:36:17.412986 SW Impedance : PASS
7108 15:36:17.416134 DUTY Scan : NO K
7109 15:36:17.419504 ZQ Calibration : PASS
7110 15:36:17.419585 Jitter Meter : NO K
7111 15:36:17.422705 CBT Training : PASS
7112 15:36:17.425884 Write leveling : NO K
7113 15:36:17.425979 RX DQS gating : PASS
7114 15:36:17.429026 RX DQ/DQS(RDDQC) : PASS
7115 15:36:17.432390 TX DQ/DQS : PASS
7116 15:36:17.432471 RX DATLAT : PASS
7117 15:36:17.435990 RX DQ/DQS(Engine): PASS
7118 15:36:17.436070 TX OE : NO K
7119 15:36:17.438939 All Pass.
7120 15:36:17.439023
7121 15:36:17.439119 DramC Write-DBI off
7122 15:36:17.442766 PER_BANK_REFRESH: Hybrid Mode
7123 15:36:17.446058 TX_TRACKING: ON
7124 15:36:17.452316 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7125 15:36:17.455696 [FAST_K] Save calibration result to emmc
7126 15:36:17.462063 dramc_set_vcore_voltage set vcore to 725000
7127 15:36:17.462146 Read voltage for 1600, 0
7128 15:36:17.465575 Vio18 = 0
7129 15:36:17.465690 Vcore = 725000
7130 15:36:17.465775 Vdram = 0
7131 15:36:17.465855 Vddq = 0
7132 15:36:17.469024 Vmddr = 0
7133 15:36:17.471956 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7134 15:36:17.478747 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7135 15:36:17.482469 MEM_TYPE=3, freq_sel=13
7136 15:36:17.482551 sv_algorithm_assistance_LP4_3733
7137 15:36:17.488957 ============ PULL DRAM RESETB DOWN ============
7138 15:36:17.492080 ========== PULL DRAM RESETB DOWN end =========
7139 15:36:17.495306 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7140 15:36:17.498792 ===================================
7141 15:36:17.501945 LPDDR4 DRAM CONFIGURATION
7142 15:36:17.505370 ===================================
7143 15:36:17.508876 EX_ROW_EN[0] = 0x0
7144 15:36:17.508993 EX_ROW_EN[1] = 0x0
7145 15:36:17.512055 LP4Y_EN = 0x0
7146 15:36:17.512142 WORK_FSP = 0x1
7147 15:36:17.515003 WL = 0x5
7148 15:36:17.515098 RL = 0x5
7149 15:36:17.518751 BL = 0x2
7150 15:36:17.518849 RPST = 0x0
7151 15:36:17.522055 RD_PRE = 0x0
7152 15:36:17.522158 WR_PRE = 0x1
7153 15:36:17.525482 WR_PST = 0x1
7154 15:36:17.528026 DBI_WR = 0x0
7155 15:36:17.528108 DBI_RD = 0x0
7156 15:36:17.531479 OTF = 0x1
7157 15:36:17.535322 ===================================
7158 15:36:17.538571 ===================================
7159 15:36:17.538686 ANA top config
7160 15:36:17.541555 ===================================
7161 15:36:17.544602 DLL_ASYNC_EN = 0
7162 15:36:17.548168 ALL_SLAVE_EN = 0
7163 15:36:17.548249 NEW_RANK_MODE = 1
7164 15:36:17.551423 DLL_IDLE_MODE = 1
7165 15:36:17.554699 LP45_APHY_COMB_EN = 1
7166 15:36:17.557955 TX_ODT_DIS = 0
7167 15:36:17.558039 NEW_8X_MODE = 1
7168 15:36:17.561245 ===================================
7169 15:36:17.564551 ===================================
7170 15:36:17.568296 data_rate = 3200
7171 15:36:17.571245 CKR = 1
7172 15:36:17.574582 DQ_P2S_RATIO = 8
7173 15:36:17.577871 ===================================
7174 15:36:17.581306 CA_P2S_RATIO = 8
7175 15:36:17.584856 DQ_CA_OPEN = 0
7176 15:36:17.584973 DQ_SEMI_OPEN = 0
7177 15:36:17.588206 CA_SEMI_OPEN = 0
7178 15:36:17.591307 CA_FULL_RATE = 0
7179 15:36:17.594753 DQ_CKDIV4_EN = 0
7180 15:36:17.597899 CA_CKDIV4_EN = 0
7181 15:36:17.601260 CA_PREDIV_EN = 0
7182 15:36:17.601346 PH8_DLY = 12
7183 15:36:17.604580 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7184 15:36:17.607925 DQ_AAMCK_DIV = 4
7185 15:36:17.611098 CA_AAMCK_DIV = 4
7186 15:36:17.614261 CA_ADMCK_DIV = 4
7187 15:36:17.617526 DQ_TRACK_CA_EN = 0
7188 15:36:17.621236 CA_PICK = 1600
7189 15:36:17.621319 CA_MCKIO = 1600
7190 15:36:17.624560 MCKIO_SEMI = 0
7191 15:36:17.627849 PLL_FREQ = 3068
7192 15:36:17.631072 DQ_UI_PI_RATIO = 32
7193 15:36:17.634402 CA_UI_PI_RATIO = 0
7194 15:36:17.637731 ===================================
7195 15:36:17.640856 ===================================
7196 15:36:17.644067 memory_type:LPDDR4
7197 15:36:17.644151 GP_NUM : 10
7198 15:36:17.647648 SRAM_EN : 1
7199 15:36:17.647727 MD32_EN : 0
7200 15:36:17.650681 ===================================
7201 15:36:17.654246 [ANA_INIT] >>>>>>>>>>>>>>
7202 15:36:17.657543 <<<<<< [CONFIGURE PHASE]: ANA_TX
7203 15:36:17.660737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7204 15:36:17.664032 ===================================
7205 15:36:17.667509 data_rate = 3200,PCW = 0X7600
7206 15:36:17.670670 ===================================
7207 15:36:17.673898 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7208 15:36:17.680711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7209 15:36:17.683963 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7210 15:36:17.690579 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7211 15:36:17.693677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7212 15:36:17.697180 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7213 15:36:17.697298 [ANA_INIT] flow start
7214 15:36:17.700205 [ANA_INIT] PLL >>>>>>>>
7215 15:36:17.703451 [ANA_INIT] PLL <<<<<<<<
7216 15:36:17.703559 [ANA_INIT] MIDPI >>>>>>>>
7217 15:36:17.706924 [ANA_INIT] MIDPI <<<<<<<<
7218 15:36:17.710779 [ANA_INIT] DLL >>>>>>>>
7219 15:36:17.713444 [ANA_INIT] DLL <<<<<<<<
7220 15:36:17.713528 [ANA_INIT] flow end
7221 15:36:17.717306 ============ LP4 DIFF to SE enter ============
7222 15:36:17.723747 ============ LP4 DIFF to SE exit ============
7223 15:36:17.723832 [ANA_INIT] <<<<<<<<<<<<<
7224 15:36:17.726677 [Flow] Enable top DCM control >>>>>
7225 15:36:17.730657 [Flow] Enable top DCM control <<<<<
7226 15:36:17.734054 Enable DLL master slave shuffle
7227 15:36:17.740398 ==============================================================
7228 15:36:17.740479 Gating Mode config
7229 15:36:17.747027 ==============================================================
7230 15:36:17.750469 Config description:
7231 15:36:17.760300 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7232 15:36:17.766888 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7233 15:36:17.769927 SELPH_MODE 0: By rank 1: By Phase
7234 15:36:17.776704 ==============================================================
7235 15:36:17.780007 GAT_TRACK_EN = 1
7236 15:36:17.780140 RX_GATING_MODE = 2
7237 15:36:17.783270 RX_GATING_TRACK_MODE = 2
7238 15:36:17.786588 SELPH_MODE = 1
7239 15:36:17.790184 PICG_EARLY_EN = 1
7240 15:36:17.793614 VALID_LAT_VALUE = 1
7241 15:36:17.799907 ==============================================================
7242 15:36:17.803602 Enter into Gating configuration >>>>
7243 15:36:17.806375 Exit from Gating configuration <<<<
7244 15:36:17.809860 Enter into DVFS_PRE_config >>>>>
7245 15:36:17.819892 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7246 15:36:17.823229 Exit from DVFS_PRE_config <<<<<
7247 15:36:17.826272 Enter into PICG configuration >>>>
7248 15:36:17.829900 Exit from PICG configuration <<<<
7249 15:36:17.833039 [RX_INPUT] configuration >>>>>
7250 15:36:17.836193 [RX_INPUT] configuration <<<<<
7251 15:36:17.839482 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7252 15:36:17.846304 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7253 15:36:17.852839 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7254 15:36:17.859497 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7255 15:36:17.862643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7256 15:36:17.869528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7257 15:36:17.872565 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7258 15:36:17.879282 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7259 15:36:17.882718 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7260 15:36:17.885671 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7261 15:36:17.889113 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7262 15:36:17.896150 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7263 15:36:17.899268 ===================================
7264 15:36:17.899347 LPDDR4 DRAM CONFIGURATION
7265 15:36:17.902542 ===================================
7266 15:36:17.905678 EX_ROW_EN[0] = 0x0
7267 15:36:17.909651 EX_ROW_EN[1] = 0x0
7268 15:36:17.909746 LP4Y_EN = 0x0
7269 15:36:17.912935 WORK_FSP = 0x1
7270 15:36:17.913018 WL = 0x5
7271 15:36:17.915803 RL = 0x5
7272 15:36:17.915884 BL = 0x2
7273 15:36:17.919261 RPST = 0x0
7274 15:36:17.919377 RD_PRE = 0x0
7275 15:36:17.922819 WR_PRE = 0x1
7276 15:36:17.922902 WR_PST = 0x1
7277 15:36:17.926161 DBI_WR = 0x0
7278 15:36:17.926259 DBI_RD = 0x0
7279 15:36:17.929090 OTF = 0x1
7280 15:36:17.932394 ===================================
7281 15:36:17.935789 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7282 15:36:17.939722 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7283 15:36:17.946281 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7284 15:36:17.949448 ===================================
7285 15:36:17.949524 LPDDR4 DRAM CONFIGURATION
7286 15:36:17.952710 ===================================
7287 15:36:17.955950 EX_ROW_EN[0] = 0x10
7288 15:36:17.956062 EX_ROW_EN[1] = 0x0
7289 15:36:17.959053 LP4Y_EN = 0x0
7290 15:36:17.962773 WORK_FSP = 0x1
7291 15:36:17.962855 WL = 0x5
7292 15:36:17.965923 RL = 0x5
7293 15:36:17.966004 BL = 0x2
7294 15:36:17.969014 RPST = 0x0
7295 15:36:17.969094 RD_PRE = 0x0
7296 15:36:17.972881 WR_PRE = 0x1
7297 15:36:17.972962 WR_PST = 0x1
7298 15:36:17.975945 DBI_WR = 0x0
7299 15:36:17.976058 DBI_RD = 0x0
7300 15:36:17.979044 OTF = 0x1
7301 15:36:17.982668 ===================================
7302 15:36:17.989468 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7303 15:36:17.989554 ==
7304 15:36:17.992856 Dram Type= 6, Freq= 0, CH_0, rank 0
7305 15:36:17.995961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7306 15:36:17.996046 ==
7307 15:36:17.998919 [Duty_Offset_Calibration]
7308 15:36:17.999004 B0:2 B1:0 CA:3
7309 15:36:17.999071
7310 15:36:18.002401 [DutyScan_Calibration_Flow] k_type=0
7311 15:36:18.012686
7312 15:36:18.012771 ==CLK 0==
7313 15:36:18.015800 Final CLK duty delay cell = 0
7314 15:36:18.019026 [0] MAX Duty = 5031%(X100), DQS PI = 12
7315 15:36:18.022234 [0] MIN Duty = 4907%(X100), DQS PI = 6
7316 15:36:18.022318 [0] AVG Duty = 4969%(X100)
7317 15:36:18.025857
7318 15:36:18.025941 CH0 CLK Duty spec in!! Max-Min= 124%
7319 15:36:18.032552 [DutyScan_Calibration_Flow] ====Done====
7320 15:36:18.032667
7321 15:36:18.035337 [DutyScan_Calibration_Flow] k_type=1
7322 15:36:18.052504
7323 15:36:18.052590 ==DQS 0 ==
7324 15:36:18.055728 Final DQS duty delay cell = 0
7325 15:36:18.058965 [0] MAX Duty = 5094%(X100), DQS PI = 14
7326 15:36:18.062264 [0] MIN Duty = 4875%(X100), DQS PI = 0
7327 15:36:18.065447 [0] AVG Duty = 4984%(X100)
7328 15:36:18.065532
7329 15:36:18.065599 ==DQS 1 ==
7330 15:36:18.068913 Final DQS duty delay cell = 0
7331 15:36:18.072012 [0] MAX Duty = 5156%(X100), DQS PI = 32
7332 15:36:18.075798 [0] MIN Duty = 5062%(X100), DQS PI = 8
7333 15:36:18.079073 [0] AVG Duty = 5109%(X100)
7334 15:36:18.079152
7335 15:36:18.082162 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7336 15:36:18.082238
7337 15:36:18.085208 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7338 15:36:18.089149 [DutyScan_Calibration_Flow] ====Done====
7339 15:36:18.089257
7340 15:36:18.092207 [DutyScan_Calibration_Flow] k_type=3
7341 15:36:18.109673
7342 15:36:18.109767 ==DQM 0 ==
7343 15:36:18.113120 Final DQM duty delay cell = 0
7344 15:36:18.115664 [0] MAX Duty = 5187%(X100), DQS PI = 30
7345 15:36:18.119598 [0] MIN Duty = 4875%(X100), DQS PI = 48
7346 15:36:18.122810 [0] AVG Duty = 5031%(X100)
7347 15:36:18.122917
7348 15:36:18.123025 ==DQM 1 ==
7349 15:36:18.126045 Final DQM duty delay cell = 0
7350 15:36:18.129334 [0] MAX Duty = 4938%(X100), DQS PI = 2
7351 15:36:18.132984 [0] MIN Duty = 4813%(X100), DQS PI = 14
7352 15:36:18.135812 [0] AVG Duty = 4875%(X100)
7353 15:36:18.135923
7354 15:36:18.139131 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7355 15:36:18.139214
7356 15:36:18.142709 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7357 15:36:18.145844 [DutyScan_Calibration_Flow] ====Done====
7358 15:36:18.145927
7359 15:36:18.149063 [DutyScan_Calibration_Flow] k_type=2
7360 15:36:18.165660
7361 15:36:18.165746 ==DQ 0 ==
7362 15:36:18.168751 Final DQ duty delay cell = -4
7363 15:36:18.172632 [-4] MAX Duty = 5000%(X100), DQS PI = 12
7364 15:36:18.175890 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7365 15:36:18.179200 [-4] AVG Duty = 4938%(X100)
7366 15:36:18.179283
7367 15:36:18.179347 ==DQ 1 ==
7368 15:36:18.182449 Final DQ duty delay cell = 0
7369 15:36:18.185650 [0] MAX Duty = 5156%(X100), DQS PI = 60
7370 15:36:18.188851 [0] MIN Duty = 5000%(X100), DQS PI = 14
7371 15:36:18.192226 [0] AVG Duty = 5078%(X100)
7372 15:36:18.192315
7373 15:36:18.195821 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7374 15:36:18.195905
7375 15:36:18.198894 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7376 15:36:18.202107 [DutyScan_Calibration_Flow] ====Done====
7377 15:36:18.202190 ==
7378 15:36:18.205731 Dram Type= 6, Freq= 0, CH_1, rank 0
7379 15:36:18.208929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7380 15:36:18.209035 ==
7381 15:36:18.212286 [Duty_Offset_Calibration]
7382 15:36:18.212401 B0:1 B1:-2 CA:0
7383 15:36:18.212502
7384 15:36:18.215379 [DutyScan_Calibration_Flow] k_type=0
7385 15:36:18.226328
7386 15:36:18.226434 ==CLK 0==
7387 15:36:18.229448 Final CLK duty delay cell = 0
7388 15:36:18.232933 [0] MAX Duty = 5031%(X100), DQS PI = 52
7389 15:36:18.236333 [0] MIN Duty = 4875%(X100), DQS PI = 12
7390 15:36:18.239842 [0] AVG Duty = 4953%(X100)
7391 15:36:18.239935
7392 15:36:18.242916 CH1 CLK Duty spec in!! Max-Min= 156%
7393 15:36:18.246445 [DutyScan_Calibration_Flow] ====Done====
7394 15:36:18.246534
7395 15:36:18.249503 [DutyScan_Calibration_Flow] k_type=1
7396 15:36:18.265852
7397 15:36:18.265943 ==DQS 0 ==
7398 15:36:18.269765 Final DQS duty delay cell = 0
7399 15:36:18.273019 [0] MAX Duty = 5156%(X100), DQS PI = 0
7400 15:36:18.276210 [0] MIN Duty = 5094%(X100), DQS PI = 12
7401 15:36:18.279551 [0] AVG Duty = 5125%(X100)
7402 15:36:18.279634
7403 15:36:18.279700 ==DQS 1 ==
7404 15:36:18.282394 Final DQS duty delay cell = 0
7405 15:36:18.286123 [0] MAX Duty = 5124%(X100), DQS PI = 32
7406 15:36:18.289408 [0] MIN Duty = 4813%(X100), DQS PI = 58
7407 15:36:18.292460 [0] AVG Duty = 4968%(X100)
7408 15:36:18.292548
7409 15:36:18.295696 CH1 DQS 0 Duty spec in!! Max-Min= 62%
7410 15:36:18.295778
7411 15:36:18.299650 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7412 15:36:18.303055 [DutyScan_Calibration_Flow] ====Done====
7413 15:36:18.303129
7414 15:36:18.305527 [DutyScan_Calibration_Flow] k_type=3
7415 15:36:18.322973
7416 15:36:18.323089 ==DQM 0 ==
7417 15:36:18.326330 Final DQM duty delay cell = 0
7418 15:36:18.329695 [0] MAX Duty = 5000%(X100), DQS PI = 0
7419 15:36:18.332569 [0] MIN Duty = 4844%(X100), DQS PI = 22
7420 15:36:18.335795 [0] AVG Duty = 4922%(X100)
7421 15:36:18.335871
7422 15:36:18.335934 ==DQM 1 ==
7423 15:36:18.339172 Final DQM duty delay cell = 0
7424 15:36:18.342801 [0] MAX Duty = 5062%(X100), DQS PI = 4
7425 15:36:18.345926 [0] MIN Duty = 4875%(X100), DQS PI = 36
7426 15:36:18.349036 [0] AVG Duty = 4968%(X100)
7427 15:36:18.349113
7428 15:36:18.352373 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7429 15:36:18.352446
7430 15:36:18.355465 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7431 15:36:18.359279 [DutyScan_Calibration_Flow] ====Done====
7432 15:36:18.359354
7433 15:36:18.362351 [DutyScan_Calibration_Flow] k_type=2
7434 15:36:18.379894
7435 15:36:18.380004 ==DQ 0 ==
7436 15:36:18.383082 Final DQ duty delay cell = 0
7437 15:36:18.386096 [0] MAX Duty = 5093%(X100), DQS PI = 62
7438 15:36:18.389382 [0] MIN Duty = 4938%(X100), DQS PI = 14
7439 15:36:18.389461 [0] AVG Duty = 5015%(X100)
7440 15:36:18.392607
7441 15:36:18.392692 ==DQ 1 ==
7442 15:36:18.396305 Final DQ duty delay cell = 0
7443 15:36:18.399511 [0] MAX Duty = 5156%(X100), DQS PI = 24
7444 15:36:18.402994 [0] MIN Duty = 4969%(X100), DQS PI = 56
7445 15:36:18.403102 [0] AVG Duty = 5062%(X100)
7446 15:36:18.406281
7447 15:36:18.409596 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7448 15:36:18.409678
7449 15:36:18.413006 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7450 15:36:18.416160 [DutyScan_Calibration_Flow] ====Done====
7451 15:36:18.419102 nWR fixed to 30
7452 15:36:18.419180 [ModeRegInit_LP4] CH0 RK0
7453 15:36:18.422813 [ModeRegInit_LP4] CH0 RK1
7454 15:36:18.425721 [ModeRegInit_LP4] CH1 RK0
7455 15:36:18.429652 [ModeRegInit_LP4] CH1 RK1
7456 15:36:18.429731 match AC timing 5
7457 15:36:18.436146 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7458 15:36:18.439381 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7459 15:36:18.442645 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7460 15:36:18.449043 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7461 15:36:18.452253 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7462 15:36:18.452328 [MiockJmeterHQA]
7463 15:36:18.452390
7464 15:36:18.456130 [DramcMiockJmeter] u1RxGatingPI = 0
7465 15:36:18.459165 0 : 4253, 4026
7466 15:36:18.459275 4 : 4252, 4027
7467 15:36:18.462354 8 : 4252, 4027
7468 15:36:18.462431 12 : 4253, 4027
7469 15:36:18.462495 16 : 4252, 4027
7470 15:36:18.465755 20 : 4363, 4137
7471 15:36:18.465836 24 : 4253, 4026
7472 15:36:18.469409 28 : 4363, 4138
7473 15:36:18.469522 32 : 4252, 4027
7474 15:36:18.472441 36 : 4253, 4026
7475 15:36:18.472530 40 : 4252, 4027
7476 15:36:18.475664 44 : 4255, 4029
7477 15:36:18.475741 48 : 4363, 4137
7478 15:36:18.475806 52 : 4252, 4027
7479 15:36:18.478855 56 : 4363, 4137
7480 15:36:18.478931 60 : 4250, 4027
7481 15:36:18.482722 64 : 4250, 4026
7482 15:36:18.482827 68 : 4250, 4027
7483 15:36:18.485876 72 : 4361, 4137
7484 15:36:18.485954 76 : 4250, 4026
7485 15:36:18.489185 80 : 4360, 4138
7486 15:36:18.489265 84 : 4250, 4027
7487 15:36:18.489330 88 : 4250, 4026
7488 15:36:18.492253 92 : 4250, 4027
7489 15:36:18.492330 96 : 4253, 4029
7490 15:36:18.495749 100 : 4361, 4137
7491 15:36:18.495846 104 : 4250, 3702
7492 15:36:18.498814 108 : 4250, 2
7493 15:36:18.498933 112 : 4250, 0
7494 15:36:18.499044 116 : 4360, 0
7495 15:36:18.501996 120 : 4250, 0
7496 15:36:18.502109 124 : 4253, 0
7497 15:36:18.505638 128 : 4250, 0
7498 15:36:18.505751 132 : 4253, 0
7499 15:36:18.505859 136 : 4363, 0
7500 15:36:18.508766 140 : 4250, 0
7501 15:36:18.508870 144 : 4250, 0
7502 15:36:18.511890 148 : 4363, 0
7503 15:36:18.512002 152 : 4361, 0
7504 15:36:18.512106 156 : 4363, 0
7505 15:36:18.515640 160 : 4250, 0
7506 15:36:18.515717 164 : 4361, 0
7507 15:36:18.515781 168 : 4250, 0
7508 15:36:18.518939 172 : 4250, 0
7509 15:36:18.519041 176 : 4250, 0
7510 15:36:18.522022 180 : 4250, 0
7511 15:36:18.522099 184 : 4252, 0
7512 15:36:18.522172 188 : 4250, 0
7513 15:36:18.525318 192 : 4250, 0
7514 15:36:18.525432 196 : 4253, 0
7515 15:36:18.528644 200 : 4250, 0
7516 15:36:18.528751 204 : 4361, 0
7517 15:36:18.528853 208 : 4250, 0
7518 15:36:18.532244 212 : 4250, 0
7519 15:36:18.532350 216 : 4250, 0
7520 15:36:18.535366 220 : 4250, 0
7521 15:36:18.535487 224 : 4250, 0
7522 15:36:18.535587 228 : 4250, 0
7523 15:36:18.538426 232 : 4250, 0
7524 15:36:18.538507 236 : 4253, 964
7525 15:36:18.542152 240 : 4361, 4136
7526 15:36:18.542263 244 : 4250, 4027
7527 15:36:18.545252 248 : 4250, 4027
7528 15:36:18.545357 252 : 4250, 4026
7529 15:36:18.545452 256 : 4250, 4027
7530 15:36:18.548658 260 : 4250, 4027
7531 15:36:18.548766 264 : 4250, 4027
7532 15:36:18.552047 268 : 4252, 4029
7533 15:36:18.552123 272 : 4250, 4027
7534 15:36:18.555186 276 : 4361, 4137
7535 15:36:18.555269 280 : 4361, 4137
7536 15:36:18.558781 284 : 4250, 4026
7537 15:36:18.558883 288 : 4363, 4139
7538 15:36:18.562053 292 : 4361, 4137
7539 15:36:18.562156 296 : 4250, 4027
7540 15:36:18.565058 300 : 4250, 4026
7541 15:36:18.565162 304 : 4253, 4029
7542 15:36:18.568447 308 : 4250, 4027
7543 15:36:18.568568 312 : 4250, 4027
7544 15:36:18.568669 316 : 4250, 4027
7545 15:36:18.572010 320 : 4253, 4029
7546 15:36:18.572115 324 : 4250, 4027
7547 15:36:18.575302 328 : 4360, 4138
7548 15:36:18.575413 332 : 4361, 4137
7549 15:36:18.578597 336 : 4250, 4026
7550 15:36:18.578723 340 : 4363, 4139
7551 15:36:18.581686 344 : 4250, 4027
7552 15:36:18.581794 348 : 4250, 4027
7553 15:36:18.584921 352 : 4250, 4015
7554 15:36:18.585012 356 : 4252, 2695
7555 15:36:18.588674 360 : 4250, 0
7556 15:36:18.588784
7557 15:36:18.588850 MIOCK jitter meter ch=0
7558 15:36:18.588915
7559 15:36:18.591694 1T = (360-108) = 252 dly cells
7560 15:36:18.598402 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7561 15:36:18.598483 ==
7562 15:36:18.601547 Dram Type= 6, Freq= 0, CH_0, rank 0
7563 15:36:18.604886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 15:36:18.604990 ==
7565 15:36:18.611495 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7566 15:36:18.615383 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7567 15:36:18.618417 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7568 15:36:18.624904 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7569 15:36:18.634420 [CA 0] Center 44 (14~75) winsize 62
7570 15:36:18.638043 [CA 1] Center 43 (13~74) winsize 62
7571 15:36:18.640944 [CA 2] Center 39 (10~69) winsize 60
7572 15:36:18.644271 [CA 3] Center 39 (10~68) winsize 59
7573 15:36:18.647448 [CA 4] Center 37 (8~67) winsize 60
7574 15:36:18.651018 [CA 5] Center 37 (7~67) winsize 61
7575 15:36:18.651109
7576 15:36:18.654123 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7577 15:36:18.654231
7578 15:36:18.661180 [CATrainingPosCal] consider 1 rank data
7579 15:36:18.661290 u2DelayCellTimex100 = 258/100 ps
7580 15:36:18.667583 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7581 15:36:18.671052 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7582 15:36:18.674160 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7583 15:36:18.677501 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7584 15:36:18.680760 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7585 15:36:18.684595 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7586 15:36:18.684701
7587 15:36:18.687754 CA PerBit enable=1, Macro0, CA PI delay=37
7588 15:36:18.687867
7589 15:36:18.690982 [CBTSetCACLKResult] CA Dly = 37
7590 15:36:18.694020 CS Dly: 11 (0~42)
7591 15:36:18.697750 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7592 15:36:18.700734 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7593 15:36:18.700839 ==
7594 15:36:18.703930 Dram Type= 6, Freq= 0, CH_0, rank 1
7595 15:36:18.711107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 15:36:18.711228 ==
7597 15:36:18.714208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7598 15:36:18.720898 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7599 15:36:18.724174 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7600 15:36:18.730607 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7601 15:36:18.737955 [CA 0] Center 43 (13~74) winsize 62
7602 15:36:18.741359 [CA 1] Center 43 (13~74) winsize 62
7603 15:36:18.744946 [CA 2] Center 39 (10~68) winsize 59
7604 15:36:18.748467 [CA 3] Center 39 (10~68) winsize 59
7605 15:36:18.751604 [CA 4] Center 36 (6~66) winsize 61
7606 15:36:18.754746 [CA 5] Center 36 (6~66) winsize 61
7607 15:36:18.754855
7608 15:36:18.758370 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7609 15:36:18.758476
7610 15:36:18.764859 [CATrainingPosCal] consider 2 rank data
7611 15:36:18.764963 u2DelayCellTimex100 = 258/100 ps
7612 15:36:18.771087 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7613 15:36:18.774977 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7614 15:36:18.778193 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7615 15:36:18.781396 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7616 15:36:18.784794 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7617 15:36:18.788109 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7618 15:36:18.788194
7619 15:36:18.791214 CA PerBit enable=1, Macro0, CA PI delay=36
7620 15:36:18.791316
7621 15:36:18.794380 [CBTSetCACLKResult] CA Dly = 36
7622 15:36:18.797526 CS Dly: 11 (0~43)
7623 15:36:18.801531 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7624 15:36:18.804450 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7625 15:36:18.804557
7626 15:36:18.807716 ----->DramcWriteLeveling(PI) begin...
7627 15:36:18.807826 ==
7628 15:36:18.810822 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 15:36:18.817810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 15:36:18.817896 ==
7631 15:36:18.820908 Write leveling (Byte 0): 36 => 36
7632 15:36:18.824147 Write leveling (Byte 1): 31 => 31
7633 15:36:18.827248 DramcWriteLeveling(PI) end<-----
7634 15:36:18.827357
7635 15:36:18.827449 ==
7636 15:36:18.830827 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 15:36:18.834098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 15:36:18.834174 ==
7639 15:36:18.837660 [Gating] SW mode calibration
7640 15:36:18.844149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7641 15:36:18.850422 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7642 15:36:18.854162 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 15:36:18.857207 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 15:36:18.863527 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 15:36:18.867089 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 15:36:18.870556 1 4 16 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7647 15:36:18.877407 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7648 15:36:18.880526 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7649 15:36:18.883782 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7650 15:36:18.886915 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7651 15:36:18.893620 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7652 15:36:18.896744 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7653 15:36:18.900568 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7654 15:36:18.906977 1 5 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7655 15:36:18.910199 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7656 15:36:18.913781 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
7657 15:36:18.920497 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 15:36:18.923558 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 15:36:18.926785 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 15:36:18.933210 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 15:36:18.936959 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7662 15:36:18.939956 1 6 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7663 15:36:18.947099 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7664 15:36:18.950167 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7665 15:36:18.953370 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 15:36:18.959971 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 15:36:18.963261 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 15:36:18.966397 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7669 15:36:18.973120 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 15:36:18.976158 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7671 15:36:18.979643 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7672 15:36:18.986385 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7673 15:36:18.989398 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 15:36:18.992913 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 15:36:18.999193 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 15:36:19.003038 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 15:36:19.006409 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 15:36:19.013003 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 15:36:19.016010 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 15:36:19.019537 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 15:36:19.026172 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 15:36:19.029203 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 15:36:19.032432 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 15:36:19.039554 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 15:36:19.042642 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7686 15:36:19.045818 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7687 15:36:19.052902 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7688 15:36:19.056058 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7689 15:36:19.059018 Total UI for P1: 0, mck2ui 16
7690 15:36:19.062304 best dqsien dly found for B0: ( 1, 9, 16)
7691 15:36:19.065972 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7692 15:36:19.069027 Total UI for P1: 0, mck2ui 16
7693 15:36:19.072270 best dqsien dly found for B1: ( 1, 9, 24)
7694 15:36:19.075421 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7695 15:36:19.079426 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7696 15:36:19.079510
7697 15:36:19.085579 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7698 15:36:19.089089 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7699 15:36:19.092156 [Gating] SW calibration Done
7700 15:36:19.092252 ==
7701 15:36:19.095766 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 15:36:19.098690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 15:36:19.098792 ==
7704 15:36:19.098888 RX Vref Scan: 0
7705 15:36:19.098979
7706 15:36:19.102432 RX Vref 0 -> 0, step: 1
7707 15:36:19.102507
7708 15:36:19.105682 RX Delay 0 -> 252, step: 8
7709 15:36:19.108990 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7710 15:36:19.112054 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7711 15:36:19.115379 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7712 15:36:19.121963 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7713 15:36:19.125321 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7714 15:36:19.128912 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7715 15:36:19.131988 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7716 15:36:19.135088 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7717 15:36:19.141940 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7718 15:36:19.145163 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7719 15:36:19.148393 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7720 15:36:19.152029 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7721 15:36:19.158378 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7722 15:36:19.161608 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7723 15:36:19.164881 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7724 15:36:19.168557 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7725 15:36:19.168634 ==
7726 15:36:19.171609 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 15:36:19.178490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 15:36:19.178601 ==
7729 15:36:19.178670 DQS Delay:
7730 15:36:19.178731 DQS0 = 0, DQS1 = 0
7731 15:36:19.181673 DQM Delay:
7732 15:36:19.181776 DQM0 = 128, DQM1 = 124
7733 15:36:19.184960 DQ Delay:
7734 15:36:19.188042 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =123
7735 15:36:19.191824 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7736 15:36:19.194778 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7737 15:36:19.198488 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7738 15:36:19.198589
7739 15:36:19.198679
7740 15:36:19.198768 ==
7741 15:36:19.201340 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 15:36:19.204945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 15:36:19.208040 ==
7744 15:36:19.208117
7745 15:36:19.208180
7746 15:36:19.208239 TX Vref Scan disable
7747 15:36:19.211153 == TX Byte 0 ==
7748 15:36:19.214930 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7749 15:36:19.217639 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7750 15:36:19.221576 == TX Byte 1 ==
7751 15:36:19.224584 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7752 15:36:19.227905 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7753 15:36:19.230980 ==
7754 15:36:19.231081 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 15:36:19.237609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 15:36:19.237689 ==
7757 15:36:19.250126
7758 15:36:19.253498 TX Vref early break, caculate TX vref
7759 15:36:19.257063 TX Vref=16, minBit 4, minWin=23, winSum=375
7760 15:36:19.260064 TX Vref=18, minBit 0, minWin=23, winSum=383
7761 15:36:19.263839 TX Vref=20, minBit 2, minWin=24, winSum=395
7762 15:36:19.267038 TX Vref=22, minBit 4, minWin=24, winSum=401
7763 15:36:19.270105 TX Vref=24, minBit 4, minWin=25, winSum=419
7764 15:36:19.276506 TX Vref=26, minBit 4, minWin=25, winSum=424
7765 15:36:19.280085 TX Vref=28, minBit 4, minWin=25, winSum=422
7766 15:36:19.283404 TX Vref=30, minBit 4, minWin=24, winSum=417
7767 15:36:19.286468 TX Vref=32, minBit 2, minWin=24, winSum=406
7768 15:36:19.290101 TX Vref=34, minBit 8, minWin=23, winSum=399
7769 15:36:19.296940 [TxChooseVref] Worse bit 4, Min win 25, Win sum 424, Final Vref 26
7770 15:36:19.297051
7771 15:36:19.300092 Final TX Range 0 Vref 26
7772 15:36:19.300193
7773 15:36:19.300281 ==
7774 15:36:19.303227 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 15:36:19.306937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 15:36:19.307039 ==
7777 15:36:19.307128
7778 15:36:19.307214
7779 15:36:19.309926 TX Vref Scan disable
7780 15:36:19.316859 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7781 15:36:19.316959 == TX Byte 0 ==
7782 15:36:19.320309 u2DelayCellOfst[0]=15 cells (4 PI)
7783 15:36:19.323468 u2DelayCellOfst[1]=18 cells (5 PI)
7784 15:36:19.326704 u2DelayCellOfst[2]=11 cells (3 PI)
7785 15:36:19.329789 u2DelayCellOfst[3]=11 cells (3 PI)
7786 15:36:19.333391 u2DelayCellOfst[4]=11 cells (3 PI)
7787 15:36:19.336512 u2DelayCellOfst[5]=0 cells (0 PI)
7788 15:36:19.340163 u2DelayCellOfst[6]=22 cells (6 PI)
7789 15:36:19.343293 u2DelayCellOfst[7]=18 cells (5 PI)
7790 15:36:19.346416 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7791 15:36:19.349555 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7792 15:36:19.353442 == TX Byte 1 ==
7793 15:36:19.353552 u2DelayCellOfst[8]=0 cells (0 PI)
7794 15:36:19.356338 u2DelayCellOfst[9]=3 cells (1 PI)
7795 15:36:19.359639 u2DelayCellOfst[10]=11 cells (3 PI)
7796 15:36:19.363535 u2DelayCellOfst[11]=7 cells (2 PI)
7797 15:36:19.366576 u2DelayCellOfst[12]=15 cells (4 PI)
7798 15:36:19.369800 u2DelayCellOfst[13]=15 cells (4 PI)
7799 15:36:19.373022 u2DelayCellOfst[14]=18 cells (5 PI)
7800 15:36:19.376313 u2DelayCellOfst[15]=15 cells (4 PI)
7801 15:36:19.379693 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7802 15:36:19.386666 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7803 15:36:19.386795 DramC Write-DBI on
7804 15:36:19.386908 ==
7805 15:36:19.389754 Dram Type= 6, Freq= 0, CH_0, rank 0
7806 15:36:19.393222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7807 15:36:19.396582 ==
7808 15:36:19.396693
7809 15:36:19.396793
7810 15:36:19.396887 TX Vref Scan disable
7811 15:36:19.399878 == TX Byte 0 ==
7812 15:36:19.403585 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7813 15:36:19.406853 == TX Byte 1 ==
7814 15:36:19.409954 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7815 15:36:19.413169 DramC Write-DBI off
7816 15:36:19.413251
7817 15:36:19.413337 [DATLAT]
7818 15:36:19.413418 Freq=1600, CH0 RK0
7819 15:36:19.413498
7820 15:36:19.416759 DATLAT Default: 0xf
7821 15:36:19.416846 0, 0xFFFF, sum = 0
7822 15:36:19.420053 1, 0xFFFF, sum = 0
7823 15:36:19.423181 2, 0xFFFF, sum = 0
7824 15:36:19.423266 3, 0xFFFF, sum = 0
7825 15:36:19.426535 4, 0xFFFF, sum = 0
7826 15:36:19.426619 5, 0xFFFF, sum = 0
7827 15:36:19.429747 6, 0xFFFF, sum = 0
7828 15:36:19.429841 7, 0xFFFF, sum = 0
7829 15:36:19.432966 8, 0xFFFF, sum = 0
7830 15:36:19.433089 9, 0xFFFF, sum = 0
7831 15:36:19.436150 10, 0xFFFF, sum = 0
7832 15:36:19.436236 11, 0xFFFF, sum = 0
7833 15:36:19.439305 12, 0xFFFF, sum = 0
7834 15:36:19.439402 13, 0xEFFF, sum = 0
7835 15:36:19.442926 14, 0x0, sum = 1
7836 15:36:19.443029 15, 0x0, sum = 2
7837 15:36:19.445985 16, 0x0, sum = 3
7838 15:36:19.446070 17, 0x0, sum = 4
7839 15:36:19.449160 best_step = 15
7840 15:36:19.449279
7841 15:36:19.449349 ==
7842 15:36:19.452855 Dram Type= 6, Freq= 0, CH_0, rank 0
7843 15:36:19.456016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7844 15:36:19.456125 ==
7845 15:36:19.459286 RX Vref Scan: 1
7846 15:36:19.459408
7847 15:36:19.459478 Set Vref Range= 24 -> 127
7848 15:36:19.459542
7849 15:36:19.462382 RX Vref 24 -> 127, step: 1
7850 15:36:19.462498
7851 15:36:19.465785 RX Delay 11 -> 252, step: 4
7852 15:36:19.465893
7853 15:36:19.469539 Set Vref, RX VrefLevel [Byte0]: 24
7854 15:36:19.472566 [Byte1]: 24
7855 15:36:19.472651
7856 15:36:19.475703 Set Vref, RX VrefLevel [Byte0]: 25
7857 15:36:19.479103 [Byte1]: 25
7858 15:36:19.482794
7859 15:36:19.482916 Set Vref, RX VrefLevel [Byte0]: 26
7860 15:36:19.486086 [Byte1]: 26
7861 15:36:19.490250
7862 15:36:19.490361 Set Vref, RX VrefLevel [Byte0]: 27
7863 15:36:19.494046 [Byte1]: 27
7864 15:36:19.498206
7865 15:36:19.498317 Set Vref, RX VrefLevel [Byte0]: 28
7866 15:36:19.501099 [Byte1]: 28
7867 15:36:19.505559
7868 15:36:19.505670 Set Vref, RX VrefLevel [Byte0]: 29
7869 15:36:19.508867 [Byte1]: 29
7870 15:36:19.513717
7871 15:36:19.513827 Set Vref, RX VrefLevel [Byte0]: 30
7872 15:36:19.516698 [Byte1]: 30
7873 15:36:19.520805
7874 15:36:19.520920 Set Vref, RX VrefLevel [Byte0]: 31
7875 15:36:19.524573 [Byte1]: 31
7876 15:36:19.528437
7877 15:36:19.528513 Set Vref, RX VrefLevel [Byte0]: 32
7878 15:36:19.531621 [Byte1]: 32
7879 15:36:19.536000
7880 15:36:19.536111 Set Vref, RX VrefLevel [Byte0]: 33
7881 15:36:19.539194 [Byte1]: 33
7882 15:36:19.543550
7883 15:36:19.543654 Set Vref, RX VrefLevel [Byte0]: 34
7884 15:36:19.546697 [Byte1]: 34
7885 15:36:19.551132
7886 15:36:19.551215 Set Vref, RX VrefLevel [Byte0]: 35
7887 15:36:19.554650 [Byte1]: 35
7888 15:36:19.558756
7889 15:36:19.558839 Set Vref, RX VrefLevel [Byte0]: 36
7890 15:36:19.562433 [Byte1]: 36
7891 15:36:19.566465
7892 15:36:19.566548 Set Vref, RX VrefLevel [Byte0]: 37
7893 15:36:19.569779 [Byte1]: 37
7894 15:36:19.574307
7895 15:36:19.574390 Set Vref, RX VrefLevel [Byte0]: 38
7896 15:36:19.577559 [Byte1]: 38
7897 15:36:19.581412
7898 15:36:19.581495 Set Vref, RX VrefLevel [Byte0]: 39
7899 15:36:19.585196 [Byte1]: 39
7900 15:36:19.589003
7901 15:36:19.589099 Set Vref, RX VrefLevel [Byte0]: 40
7902 15:36:19.592882 [Byte1]: 40
7903 15:36:19.596810
7904 15:36:19.596890 Set Vref, RX VrefLevel [Byte0]: 41
7905 15:36:19.600601 [Byte1]: 41
7906 15:36:19.604523
7907 15:36:19.604614 Set Vref, RX VrefLevel [Byte0]: 42
7908 15:36:19.607802 [Byte1]: 42
7909 15:36:19.612050
7910 15:36:19.612138 Set Vref, RX VrefLevel [Byte0]: 43
7911 15:36:19.615420 [Byte1]: 43
7912 15:36:19.619953
7913 15:36:19.620038 Set Vref, RX VrefLevel [Byte0]: 44
7914 15:36:19.622841 [Byte1]: 44
7915 15:36:19.627193
7916 15:36:19.627309 Set Vref, RX VrefLevel [Byte0]: 45
7917 15:36:19.630678 [Byte1]: 45
7918 15:36:19.634738
7919 15:36:19.634826 Set Vref, RX VrefLevel [Byte0]: 46
7920 15:36:19.638508 [Byte1]: 46
7921 15:36:19.642370
7922 15:36:19.642456 Set Vref, RX VrefLevel [Byte0]: 47
7923 15:36:19.646221 [Byte1]: 47
7924 15:36:19.650191
7925 15:36:19.650272 Set Vref, RX VrefLevel [Byte0]: 48
7926 15:36:19.653371 [Byte1]: 48
7927 15:36:19.657902
7928 15:36:19.657991 Set Vref, RX VrefLevel [Byte0]: 49
7929 15:36:19.660861 [Byte1]: 49
7930 15:36:19.665171
7931 15:36:19.665271 Set Vref, RX VrefLevel [Byte0]: 50
7932 15:36:19.668940 [Byte1]: 50
7933 15:36:19.673419
7934 15:36:19.673536 Set Vref, RX VrefLevel [Byte0]: 51
7935 15:36:19.676446 [Byte1]: 51
7936 15:36:19.680879
7937 15:36:19.681000 Set Vref, RX VrefLevel [Byte0]: 52
7938 15:36:19.684162 [Byte1]: 52
7939 15:36:19.688375
7940 15:36:19.688493 Set Vref, RX VrefLevel [Byte0]: 53
7941 15:36:19.691786 [Byte1]: 53
7942 15:36:19.695782
7943 15:36:19.695873 Set Vref, RX VrefLevel [Byte0]: 54
7944 15:36:19.699003 [Byte1]: 54
7945 15:36:19.703302
7946 15:36:19.703423 Set Vref, RX VrefLevel [Byte0]: 55
7947 15:36:19.706603 [Byte1]: 55
7948 15:36:19.711383
7949 15:36:19.711500 Set Vref, RX VrefLevel [Byte0]: 56
7950 15:36:19.714822 [Byte1]: 56
7951 15:36:19.718664
7952 15:36:19.718748 Set Vref, RX VrefLevel [Byte0]: 57
7953 15:36:19.721705 [Byte1]: 57
7954 15:36:19.726249
7955 15:36:19.726367 Set Vref, RX VrefLevel [Byte0]: 58
7956 15:36:19.729639 [Byte1]: 58
7957 15:36:19.733677
7958 15:36:19.733773 Set Vref, RX VrefLevel [Byte0]: 59
7959 15:36:19.737077 [Byte1]: 59
7960 15:36:19.741285
7961 15:36:19.741399 Set Vref, RX VrefLevel [Byte0]: 60
7962 15:36:19.745104 [Byte1]: 60
7963 15:36:19.749641
7964 15:36:19.749768 Set Vref, RX VrefLevel [Byte0]: 61
7965 15:36:19.752632 [Byte1]: 61
7966 15:36:19.756570
7967 15:36:19.756650 Set Vref, RX VrefLevel [Byte0]: 62
7968 15:36:19.759748 [Byte1]: 62
7969 15:36:19.764065
7970 15:36:19.764154 Set Vref, RX VrefLevel [Byte0]: 63
7971 15:36:19.767753 [Byte1]: 63
7972 15:36:19.771992
7973 15:36:19.772072 Set Vref, RX VrefLevel [Byte0]: 64
7974 15:36:19.775113 [Byte1]: 64
7975 15:36:19.779713
7976 15:36:19.779806 Set Vref, RX VrefLevel [Byte0]: 65
7977 15:36:19.782576 [Byte1]: 65
7978 15:36:19.786995
7979 15:36:19.787117 Set Vref, RX VrefLevel [Byte0]: 66
7980 15:36:19.790288 [Byte1]: 66
7981 15:36:19.794852
7982 15:36:19.794956 Set Vref, RX VrefLevel [Byte0]: 67
7983 15:36:19.798193 [Byte1]: 67
7984 15:36:19.802622
7985 15:36:19.802785 Set Vref, RX VrefLevel [Byte0]: 68
7986 15:36:19.805953 [Byte1]: 68
7987 15:36:19.809719
7988 15:36:19.809848 Set Vref, RX VrefLevel [Byte0]: 69
7989 15:36:19.813040 [Byte1]: 69
7990 15:36:19.817634
7991 15:36:19.817751 Set Vref, RX VrefLevel [Byte0]: 70
7992 15:36:19.820853 [Byte1]: 70
7993 15:36:19.825297
7994 15:36:19.825444 Set Vref, RX VrefLevel [Byte0]: 71
7995 15:36:19.828685 [Byte1]: 71
7996 15:36:19.832630
7997 15:36:19.832758 Set Vref, RX VrefLevel [Byte0]: 72
7998 15:36:19.836159 [Byte1]: 72
7999 15:36:19.840395
8000 15:36:19.840490 Set Vref, RX VrefLevel [Byte0]: 73
8001 15:36:19.843803 [Byte1]: 73
8002 15:36:19.847846
8003 15:36:19.847946 Set Vref, RX VrefLevel [Byte0]: 74
8004 15:36:19.851415 [Byte1]: 74
8005 15:36:19.855551
8006 15:36:19.855677 Final RX Vref Byte 0 = 61 to rank0
8007 15:36:19.859191 Final RX Vref Byte 1 = 60 to rank0
8008 15:36:19.862526 Final RX Vref Byte 0 = 61 to rank1
8009 15:36:19.865850 Final RX Vref Byte 1 = 60 to rank1==
8010 15:36:19.869071 Dram Type= 6, Freq= 0, CH_0, rank 0
8011 15:36:19.875506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 15:36:19.875609 ==
8013 15:36:19.875686 DQS Delay:
8014 15:36:19.875770 DQS0 = 0, DQS1 = 0
8015 15:36:19.878875 DQM Delay:
8016 15:36:19.878966 DQM0 = 126, DQM1 = 120
8017 15:36:19.882570 DQ Delay:
8018 15:36:19.885578 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8019 15:36:19.889164 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =138
8020 15:36:19.892229 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
8021 15:36:19.895289 DQ12 =124, DQ13 =126, DQ14 =130, DQ15 =128
8022 15:36:19.895383
8023 15:36:19.895453
8024 15:36:19.895515
8025 15:36:19.898948 [DramC_TX_OE_Calibration] TA2
8026 15:36:19.902094 Original DQ_B0 (3 6) =30, OEN = 27
8027 15:36:19.905255 Original DQ_B1 (3 6) =30, OEN = 27
8028 15:36:19.908966 24, 0x0, End_B0=24 End_B1=24
8029 15:36:19.909051 25, 0x0, End_B0=25 End_B1=25
8030 15:36:19.912226 26, 0x0, End_B0=26 End_B1=26
8031 15:36:19.915246 27, 0x0, End_B0=27 End_B1=27
8032 15:36:19.918493 28, 0x0, End_B0=28 End_B1=28
8033 15:36:19.921897 29, 0x0, End_B0=29 End_B1=29
8034 15:36:19.921983 30, 0x0, End_B0=30 End_B1=30
8035 15:36:19.925006 31, 0x4141, End_B0=30 End_B1=30
8036 15:36:19.928585 Byte0 end_step=30 best_step=27
8037 15:36:19.931705 Byte1 end_step=30 best_step=27
8038 15:36:19.935541 Byte0 TX OE(2T, 0.5T) = (3, 3)
8039 15:36:19.938618 Byte1 TX OE(2T, 0.5T) = (3, 3)
8040 15:36:19.938701
8041 15:36:19.938766
8042 15:36:19.945198 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8043 15:36:19.948864 CH0 RK0: MR19=303, MR18=1212
8044 15:36:19.955594 CH0_RK0: MR19=0x303, MR18=0x1212, DQSOSC=400, MR23=63, INC=23, DEC=15
8045 15:36:19.955678
8046 15:36:19.958470 ----->DramcWriteLeveling(PI) begin...
8047 15:36:19.958555 ==
8048 15:36:19.962129 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 15:36:19.965088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 15:36:19.965173 ==
8051 15:36:19.968135 Write leveling (Byte 0): 35 => 35
8052 15:36:19.971803 Write leveling (Byte 1): 27 => 27
8053 15:36:19.975028 DramcWriteLeveling(PI) end<-----
8054 15:36:19.975112
8055 15:36:19.975177 ==
8056 15:36:19.978119 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 15:36:19.981833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 15:36:19.981919 ==
8059 15:36:19.984883 [Gating] SW mode calibration
8060 15:36:19.991528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8061 15:36:19.998069 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8062 15:36:20.001248 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 15:36:20.008051 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 15:36:20.011743 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 15:36:20.014764 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
8066 15:36:20.021898 1 4 16 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
8067 15:36:20.024552 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 15:36:20.028418 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 15:36:20.031551 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 15:36:20.038074 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 15:36:20.041704 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 15:36:20.044814 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8073 15:36:20.051785 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8074 15:36:20.054785 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8075 15:36:20.057969 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8076 15:36:20.064448 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 15:36:20.068061 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 15:36:20.071678 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 15:36:20.077645 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 15:36:20.081525 1 6 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8081 15:36:20.084673 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8082 15:36:20.091276 1 6 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8083 15:36:20.094386 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 15:36:20.097486 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 15:36:20.104219 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 15:36:20.107353 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 15:36:20.110517 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 15:36:20.117209 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 15:36:20.120466 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8090 15:36:20.123658 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8091 15:36:20.130867 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 15:36:20.134030 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 15:36:20.137200 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 15:36:20.143526 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 15:36:20.146921 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 15:36:20.150566 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 15:36:20.157414 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 15:36:20.160437 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 15:36:20.163680 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 15:36:20.170393 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 15:36:20.173986 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 15:36:20.177050 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 15:36:20.183682 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 15:36:20.186864 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8105 15:36:20.189996 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8106 15:36:20.196929 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8107 15:36:20.197013 Total UI for P1: 0, mck2ui 16
8108 15:36:20.203675 best dqsien dly found for B0: ( 1, 9, 10)
8109 15:36:20.206859 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 15:36:20.210022 Total UI for P1: 0, mck2ui 16
8111 15:36:20.213294 best dqsien dly found for B1: ( 1, 9, 16)
8112 15:36:20.216503 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8113 15:36:20.220269 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8114 15:36:20.220379
8115 15:36:20.223275 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8116 15:36:20.226952 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8117 15:36:20.230063 [Gating] SW calibration Done
8118 15:36:20.230147 ==
8119 15:36:20.233010 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 15:36:20.236747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 15:36:20.239987 ==
8122 15:36:20.240063 RX Vref Scan: 0
8123 15:36:20.240129
8124 15:36:20.243134 RX Vref 0 -> 0, step: 1
8125 15:36:20.243219
8126 15:36:20.246375 RX Delay 0 -> 252, step: 8
8127 15:36:20.249534 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8128 15:36:20.253347 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8129 15:36:20.256511 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8130 15:36:20.259740 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8131 15:36:20.266597 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8132 15:36:20.269725 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8133 15:36:20.272700 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8134 15:36:20.275818 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8135 15:36:20.279613 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8136 15:36:20.285875 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8137 15:36:20.289208 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8138 15:36:20.292418 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8139 15:36:20.296314 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8140 15:36:20.299579 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8141 15:36:20.305674 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8142 15:36:20.309503 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8143 15:36:20.309586 ==
8144 15:36:20.312361 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 15:36:20.315967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 15:36:20.316049 ==
8147 15:36:20.319287 DQS Delay:
8148 15:36:20.319376 DQS0 = 0, DQS1 = 0
8149 15:36:20.319445 DQM Delay:
8150 15:36:20.322761 DQM0 = 129, DQM1 = 121
8151 15:36:20.322843 DQ Delay:
8152 15:36:20.325957 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8153 15:36:20.329143 DQ4 =131, DQ5 =115, DQ6 =139, DQ7 =139
8154 15:36:20.335662 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8155 15:36:20.339214 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8156 15:36:20.339298
8157 15:36:20.339364
8158 15:36:20.339437 ==
8159 15:36:20.342705 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 15:36:20.345885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 15:36:20.345969 ==
8162 15:36:20.346035
8163 15:36:20.346097
8164 15:36:20.349175 TX Vref Scan disable
8165 15:36:20.352382 == TX Byte 0 ==
8166 15:36:20.355776 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8167 15:36:20.358828 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8168 15:36:20.362426 == TX Byte 1 ==
8169 15:36:20.365649 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8170 15:36:20.368791 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8171 15:36:20.368870 ==
8172 15:36:20.371915 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 15:36:20.375814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 15:36:20.375893 ==
8175 15:36:20.391558
8176 15:36:20.395359 TX Vref early break, caculate TX vref
8177 15:36:20.398751 TX Vref=16, minBit 8, minWin=21, winSum=369
8178 15:36:20.401929 TX Vref=18, minBit 8, minWin=22, winSum=375
8179 15:36:20.405224 TX Vref=20, minBit 1, minWin=23, winSum=383
8180 15:36:20.408434 TX Vref=22, minBit 9, minWin=23, winSum=392
8181 15:36:20.411835 TX Vref=24, minBit 0, minWin=24, winSum=398
8182 15:36:20.418524 TX Vref=26, minBit 8, minWin=24, winSum=412
8183 15:36:20.421688 TX Vref=28, minBit 11, minWin=24, winSum=412
8184 15:36:20.425004 TX Vref=30, minBit 8, minWin=24, winSum=403
8185 15:36:20.428166 TX Vref=32, minBit 8, minWin=22, winSum=397
8186 15:36:20.431497 TX Vref=34, minBit 8, minWin=22, winSum=391
8187 15:36:20.434859 TX Vref=36, minBit 8, minWin=22, winSum=381
8188 15:36:20.441974 [TxChooseVref] Worse bit 8, Min win 24, Win sum 412, Final Vref 26
8189 15:36:20.442082
8190 15:36:20.445104 Final TX Range 0 Vref 26
8191 15:36:20.445216
8192 15:36:20.445314 ==
8193 15:36:20.448288 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 15:36:20.451591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 15:36:20.451676 ==
8196 15:36:20.451743
8197 15:36:20.451804
8198 15:36:20.454990 TX Vref Scan disable
8199 15:36:20.461787 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8200 15:36:20.461871 == TX Byte 0 ==
8201 15:36:20.465007 u2DelayCellOfst[0]=15 cells (4 PI)
8202 15:36:20.468198 u2DelayCellOfst[1]=22 cells (6 PI)
8203 15:36:20.471257 u2DelayCellOfst[2]=15 cells (4 PI)
8204 15:36:20.474463 u2DelayCellOfst[3]=15 cells (4 PI)
8205 15:36:20.477732 u2DelayCellOfst[4]=11 cells (3 PI)
8206 15:36:20.481635 u2DelayCellOfst[5]=0 cells (0 PI)
8207 15:36:20.484692 u2DelayCellOfst[6]=18 cells (5 PI)
8208 15:36:20.487907 u2DelayCellOfst[7]=18 cells (5 PI)
8209 15:36:20.490967 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8210 15:36:20.495002 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8211 15:36:20.497718 == TX Byte 1 ==
8212 15:36:20.501078 u2DelayCellOfst[8]=0 cells (0 PI)
8213 15:36:20.504326 u2DelayCellOfst[9]=0 cells (0 PI)
8214 15:36:20.507602 u2DelayCellOfst[10]=7 cells (2 PI)
8215 15:36:20.510801 u2DelayCellOfst[11]=7 cells (2 PI)
8216 15:36:20.510881 u2DelayCellOfst[12]=15 cells (4 PI)
8217 15:36:20.514739 u2DelayCellOfst[13]=11 cells (3 PI)
8218 15:36:20.517820 u2DelayCellOfst[14]=15 cells (4 PI)
8219 15:36:20.520875 u2DelayCellOfst[15]=11 cells (3 PI)
8220 15:36:20.527691 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8221 15:36:20.531233 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8222 15:36:20.531341 DramC Write-DBI on
8223 15:36:20.534491 ==
8224 15:36:20.534610 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 15:36:20.540980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 15:36:20.541070 ==
8227 15:36:20.541137
8228 15:36:20.541208
8229 15:36:20.544060 TX Vref Scan disable
8230 15:36:20.544139 == TX Byte 0 ==
8231 15:36:20.550917 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8232 15:36:20.551001 == TX Byte 1 ==
8233 15:36:20.554147 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8234 15:36:20.558009 DramC Write-DBI off
8235 15:36:20.558137
8236 15:36:20.558231 [DATLAT]
8237 15:36:20.561125 Freq=1600, CH0 RK1
8238 15:36:20.561236
8239 15:36:20.561347 DATLAT Default: 0xf
8240 15:36:20.564239 0, 0xFFFF, sum = 0
8241 15:36:20.564337 1, 0xFFFF, sum = 0
8242 15:36:20.567360 2, 0xFFFF, sum = 0
8243 15:36:20.567472 3, 0xFFFF, sum = 0
8244 15:36:20.570757 4, 0xFFFF, sum = 0
8245 15:36:20.570880 5, 0xFFFF, sum = 0
8246 15:36:20.573967 6, 0xFFFF, sum = 0
8247 15:36:20.574057 7, 0xFFFF, sum = 0
8248 15:36:20.577712 8, 0xFFFF, sum = 0
8249 15:36:20.577830 9, 0xFFFF, sum = 0
8250 15:36:20.580886 10, 0xFFFF, sum = 0
8251 15:36:20.583921 11, 0xFFFF, sum = 0
8252 15:36:20.584000 12, 0xFFFF, sum = 0
8253 15:36:20.587117 13, 0xCFFF, sum = 0
8254 15:36:20.587238 14, 0x0, sum = 1
8255 15:36:20.590811 15, 0x0, sum = 2
8256 15:36:20.590928 16, 0x0, sum = 3
8257 15:36:20.594042 17, 0x0, sum = 4
8258 15:36:20.594159 best_step = 15
8259 15:36:20.594255
8260 15:36:20.594361 ==
8261 15:36:20.597662 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 15:36:20.600733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 15:36:20.600815 ==
8264 15:36:20.603682 RX Vref Scan: 0
8265 15:36:20.603782
8266 15:36:20.606953 RX Vref 0 -> 0, step: 1
8267 15:36:20.607041
8268 15:36:20.607111 RX Delay 3 -> 252, step: 4
8269 15:36:20.614019 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8270 15:36:20.617912 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8271 15:36:20.621103 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8272 15:36:20.624242 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8273 15:36:20.627694 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8274 15:36:20.634515 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8275 15:36:20.637393 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8276 15:36:20.640621 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8277 15:36:20.644114 iDelay=191, Bit 8, Center 108 (51 ~ 166) 116
8278 15:36:20.647116 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8279 15:36:20.654385 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8280 15:36:20.657283 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8281 15:36:20.660649 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8282 15:36:20.663827 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8283 15:36:20.670473 iDelay=191, Bit 14, Center 126 (67 ~ 186) 120
8284 15:36:20.673969 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8285 15:36:20.674054 ==
8286 15:36:20.677048 Dram Type= 6, Freq= 0, CH_0, rank 1
8287 15:36:20.680729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 15:36:20.680846 ==
8289 15:36:20.684084 DQS Delay:
8290 15:36:20.684170 DQS0 = 0, DQS1 = 0
8291 15:36:20.684239 DQM Delay:
8292 15:36:20.687208 DQM0 = 124, DQM1 = 117
8293 15:36:20.687327 DQ Delay:
8294 15:36:20.690607 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8295 15:36:20.693656 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8296 15:36:20.697187 DQ8 =108, DQ9 =104, DQ10 =120, DQ11 =112
8297 15:36:20.703611 DQ12 =124, DQ13 =122, DQ14 =126, DQ15 =124
8298 15:36:20.703720
8299 15:36:20.703791
8300 15:36:20.703853
8301 15:36:20.706886 [DramC_TX_OE_Calibration] TA2
8302 15:36:20.706965 Original DQ_B0 (3 6) =30, OEN = 27
8303 15:36:20.710492 Original DQ_B1 (3 6) =30, OEN = 27
8304 15:36:20.713631 24, 0x0, End_B0=24 End_B1=24
8305 15:36:20.716908 25, 0x0, End_B0=25 End_B1=25
8306 15:36:20.720224 26, 0x0, End_B0=26 End_B1=26
8307 15:36:20.723517 27, 0x0, End_B0=27 End_B1=27
8308 15:36:20.723629 28, 0x0, End_B0=28 End_B1=28
8309 15:36:20.726730 29, 0x0, End_B0=29 End_B1=29
8310 15:36:20.730677 30, 0x0, End_B0=30 End_B1=30
8311 15:36:20.733283 31, 0x4141, End_B0=30 End_B1=30
8312 15:36:20.736698 Byte0 end_step=30 best_step=27
8313 15:36:20.736781 Byte1 end_step=30 best_step=27
8314 15:36:20.740022 Byte0 TX OE(2T, 0.5T) = (3, 3)
8315 15:36:20.743317 Byte1 TX OE(2T, 0.5T) = (3, 3)
8316 15:36:20.743421
8317 15:36:20.743488
8318 15:36:20.753308 [DQSOSCAuto] RK1, (LSB)MR18= 0x2613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
8319 15:36:20.753394 CH0 RK1: MR19=303, MR18=2613
8320 15:36:20.759788 CH0_RK1: MR19=0x303, MR18=0x2613, DQSOSC=390, MR23=63, INC=24, DEC=16
8321 15:36:20.763273 [RxdqsGatingPostProcess] freq 1600
8322 15:36:20.769799 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8323 15:36:20.773354 best DQS0 dly(2T, 0.5T) = (1, 1)
8324 15:36:20.776645 best DQS1 dly(2T, 0.5T) = (1, 1)
8325 15:36:20.779813 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8326 15:36:20.782899 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8327 15:36:20.786369 best DQS0 dly(2T, 0.5T) = (1, 1)
8328 15:36:20.786452 best DQS1 dly(2T, 0.5T) = (1, 1)
8329 15:36:20.790238 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8330 15:36:20.793441 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8331 15:36:20.796699 Pre-setting of DQS Precalculation
8332 15:36:20.802999 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8333 15:36:20.803092 ==
8334 15:36:20.806961 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 15:36:20.809995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 15:36:20.810093 ==
8337 15:36:20.816688 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 15:36:20.819860 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 15:36:20.823102 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 15:36:20.829446 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 15:36:20.838368 [CA 0] Center 42 (13~71) winsize 59
8342 15:36:20.842121 [CA 1] Center 42 (13~72) winsize 60
8343 15:36:20.845337 [CA 2] Center 38 (9~67) winsize 59
8344 15:36:20.848464 [CA 3] Center 37 (8~66) winsize 59
8345 15:36:20.851825 [CA 4] Center 37 (8~67) winsize 60
8346 15:36:20.854990 [CA 5] Center 36 (7~66) winsize 60
8347 15:36:20.855083
8348 15:36:20.858867 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8349 15:36:20.858969
8350 15:36:20.862026 [CATrainingPosCal] consider 1 rank data
8351 15:36:20.864884 u2DelayCellTimex100 = 258/100 ps
8352 15:36:20.868436 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8353 15:36:20.874976 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8354 15:36:20.878365 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8355 15:36:20.881792 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8356 15:36:20.884763 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8357 15:36:20.888034 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8358 15:36:20.888160
8359 15:36:20.891579 CA PerBit enable=1, Macro0, CA PI delay=36
8360 15:36:20.891685
8361 15:36:20.894858 [CBTSetCACLKResult] CA Dly = 36
8362 15:36:20.898172 CS Dly: 9 (0~40)
8363 15:36:20.901416 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 15:36:20.904841 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 15:36:20.904958 ==
8366 15:36:20.908105 Dram Type= 6, Freq= 0, CH_1, rank 1
8367 15:36:20.911244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 15:36:20.915223 ==
8369 15:36:20.918331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8370 15:36:20.921203 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8371 15:36:20.928062 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8372 15:36:20.931217 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8373 15:36:20.942043 [CA 0] Center 42 (13~71) winsize 59
8374 15:36:20.945065 [CA 1] Center 42 (12~72) winsize 61
8375 15:36:20.948306 [CA 2] Center 38 (9~68) winsize 60
8376 15:36:20.951366 [CA 3] Center 37 (8~66) winsize 59
8377 15:36:20.954609 [CA 4] Center 38 (8~68) winsize 61
8378 15:36:20.958355 [CA 5] Center 37 (7~67) winsize 61
8379 15:36:20.958473
8380 15:36:20.961462 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8381 15:36:20.961569
8382 15:36:20.964600 [CATrainingPosCal] consider 2 rank data
8383 15:36:20.968244 u2DelayCellTimex100 = 258/100 ps
8384 15:36:20.971288 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8385 15:36:20.978235 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8386 15:36:20.981351 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8387 15:36:20.984355 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8388 15:36:20.987990 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8389 15:36:20.991262 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8390 15:36:20.991388
8391 15:36:20.994906 CA PerBit enable=1, Macro0, CA PI delay=36
8392 15:36:20.995016
8393 15:36:20.997976 [CBTSetCACLKResult] CA Dly = 36
8394 15:36:21.001017 CS Dly: 11 (0~44)
8395 15:36:21.004282 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8396 15:36:21.007897 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8397 15:36:21.007984
8398 15:36:21.010898 ----->DramcWriteLeveling(PI) begin...
8399 15:36:21.011009 ==
8400 15:36:21.014392 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 15:36:21.021094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 15:36:21.021199 ==
8403 15:36:21.024682 Write leveling (Byte 0): 26 => 26
8404 15:36:21.024799 Write leveling (Byte 1): 31 => 31
8405 15:36:21.027464 DramcWriteLeveling(PI) end<-----
8406 15:36:21.027557
8407 15:36:21.030966 ==
8408 15:36:21.031047 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 15:36:21.037601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 15:36:21.037720 ==
8411 15:36:21.040890 [Gating] SW mode calibration
8412 15:36:21.047851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8413 15:36:21.051145 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8414 15:36:21.057737 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 15:36:21.060828 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 15:36:21.063838 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 15:36:21.070602 1 4 12 | B1->B0 | 2525 2322 | 0 1 | (0 0) (0 0)
8418 15:36:21.073681 1 4 16 | B1->B0 | 3434 3232 | 1 1 | (0 0) (1 1)
8419 15:36:21.077408 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8420 15:36:21.083883 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 15:36:21.087082 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 15:36:21.090896 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 15:36:21.097173 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 15:36:21.100810 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 15:36:21.103812 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
8426 15:36:21.110816 1 5 16 | B1->B0 | 2828 2626 | 1 1 | (1 0) (1 0)
8427 15:36:21.114025 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 15:36:21.117062 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 15:36:21.123307 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 15:36:21.126797 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 15:36:21.130400 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 15:36:21.137071 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 15:36:21.140055 1 6 12 | B1->B0 | 2a2a 2727 | 1 0 | (0 0) (0 0)
8434 15:36:21.143420 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8435 15:36:21.150124 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 15:36:21.153446 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 15:36:21.156724 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 15:36:21.163099 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 15:36:21.166421 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 15:36:21.170274 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 15:36:21.176522 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8442 15:36:21.180058 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8443 15:36:21.183193 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8444 15:36:21.189915 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 15:36:21.192964 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 15:36:21.196661 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 15:36:21.199814 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 15:36:21.206348 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 15:36:21.209584 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 15:36:21.213026 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 15:36:21.220084 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 15:36:21.223122 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 15:36:21.226333 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 15:36:21.232806 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 15:36:21.236394 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 15:36:21.239885 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 15:36:21.246248 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8458 15:36:21.249405 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8459 15:36:21.252937 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 15:36:21.256652 Total UI for P1: 0, mck2ui 16
8461 15:36:21.259613 best dqsien dly found for B0: ( 1, 9, 14)
8462 15:36:21.262628 Total UI for P1: 0, mck2ui 16
8463 15:36:21.265791 best dqsien dly found for B1: ( 1, 9, 14)
8464 15:36:21.269589 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8465 15:36:21.272793 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8466 15:36:21.275920
8467 15:36:21.279054 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8468 15:36:21.282776 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8469 15:36:21.285777 [Gating] SW calibration Done
8470 15:36:21.285858 ==
8471 15:36:21.288948 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 15:36:21.292769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 15:36:21.292851 ==
8474 15:36:21.292916 RX Vref Scan: 0
8475 15:36:21.295862
8476 15:36:21.295942 RX Vref 0 -> 0, step: 1
8477 15:36:21.296006
8478 15:36:21.298884 RX Delay 0 -> 252, step: 8
8479 15:36:21.302544 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8480 15:36:21.305697 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8481 15:36:21.312689 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8482 15:36:21.315600 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8483 15:36:21.318873 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8484 15:36:21.322453 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8485 15:36:21.325544 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8486 15:36:21.332468 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8487 15:36:21.335595 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8488 15:36:21.338778 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8489 15:36:21.342618 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8490 15:36:21.345475 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8491 15:36:21.351943 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8492 15:36:21.355243 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8493 15:36:21.358767 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8494 15:36:21.361899 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8495 15:36:21.361982 ==
8496 15:36:21.365075 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 15:36:21.371877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 15:36:21.371961 ==
8499 15:36:21.372047 DQS Delay:
8500 15:36:21.375044 DQS0 = 0, DQS1 = 0
8501 15:36:21.375128 DQM Delay:
8502 15:36:21.375213 DQM0 = 133, DQM1 = 126
8503 15:36:21.378803 DQ Delay:
8504 15:36:21.381941 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =131
8505 15:36:21.385166 DQ4 =127, DQ5 =147, DQ6 =147, DQ7 =131
8506 15:36:21.388727 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8507 15:36:21.391808 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8508 15:36:21.391893
8509 15:36:21.391993
8510 15:36:21.392074 ==
8511 15:36:21.395054 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 15:36:21.401967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 15:36:21.402052 ==
8514 15:36:21.402137
8515 15:36:21.402227
8516 15:36:21.402325 TX Vref Scan disable
8517 15:36:21.404930 == TX Byte 0 ==
8518 15:36:21.407942 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8519 15:36:21.414898 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8520 15:36:21.414979 == TX Byte 1 ==
8521 15:36:21.418115 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8522 15:36:21.424972 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8523 15:36:21.425068 ==
8524 15:36:21.428080 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 15:36:21.431129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 15:36:21.431211 ==
8527 15:36:21.444115
8528 15:36:21.447199 TX Vref early break, caculate TX vref
8529 15:36:21.450285 TX Vref=16, minBit 8, minWin=20, winSum=360
8530 15:36:21.453792 TX Vref=18, minBit 11, minWin=21, winSum=367
8531 15:36:21.457211 TX Vref=20, minBit 8, minWin=22, winSum=377
8532 15:36:21.460688 TX Vref=22, minBit 8, minWin=23, winSum=390
8533 15:36:21.464205 TX Vref=24, minBit 11, minWin=23, winSum=398
8534 15:36:21.470251 TX Vref=26, minBit 8, minWin=24, winSum=407
8535 15:36:21.474107 TX Vref=28, minBit 5, minWin=25, winSum=418
8536 15:36:21.477283 TX Vref=30, minBit 8, minWin=24, winSum=407
8537 15:36:21.480444 TX Vref=32, minBit 0, minWin=24, winSum=404
8538 15:36:21.483999 TX Vref=34, minBit 8, minWin=23, winSum=394
8539 15:36:21.490311 [TxChooseVref] Worse bit 5, Min win 25, Win sum 418, Final Vref 28
8540 15:36:21.490395
8541 15:36:21.493961 Final TX Range 0 Vref 28
8542 15:36:21.494043
8543 15:36:21.494107 ==
8544 15:36:21.497160 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 15:36:21.500295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 15:36:21.500390 ==
8547 15:36:21.500455
8548 15:36:21.500518
8549 15:36:21.503499 TX Vref Scan disable
8550 15:36:21.510438 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8551 15:36:21.510554 == TX Byte 0 ==
8552 15:36:21.513390 u2DelayCellOfst[0]=18 cells (5 PI)
8553 15:36:21.516637 u2DelayCellOfst[1]=15 cells (4 PI)
8554 15:36:21.520405 u2DelayCellOfst[2]=0 cells (0 PI)
8555 15:36:21.523705 u2DelayCellOfst[3]=7 cells (2 PI)
8556 15:36:21.526760 u2DelayCellOfst[4]=7 cells (2 PI)
8557 15:36:21.529902 u2DelayCellOfst[5]=18 cells (5 PI)
8558 15:36:21.533741 u2DelayCellOfst[6]=18 cells (5 PI)
8559 15:36:21.536777 u2DelayCellOfst[7]=7 cells (2 PI)
8560 15:36:21.539967 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8561 15:36:21.543216 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8562 15:36:21.546828 == TX Byte 1 ==
8563 15:36:21.546955 u2DelayCellOfst[8]=0 cells (0 PI)
8564 15:36:21.550060 u2DelayCellOfst[9]=7 cells (2 PI)
8565 15:36:21.553205 u2DelayCellOfst[10]=11 cells (3 PI)
8566 15:36:21.556446 u2DelayCellOfst[11]=7 cells (2 PI)
8567 15:36:21.560141 u2DelayCellOfst[12]=11 cells (3 PI)
8568 15:36:21.563279 u2DelayCellOfst[13]=18 cells (5 PI)
8569 15:36:21.566422 u2DelayCellOfst[14]=15 cells (4 PI)
8570 15:36:21.569724 u2DelayCellOfst[15]=15 cells (4 PI)
8571 15:36:21.573228 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8572 15:36:21.579998 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8573 15:36:21.580105 DramC Write-DBI on
8574 15:36:21.580221 ==
8575 15:36:21.583163 Dram Type= 6, Freq= 0, CH_1, rank 0
8576 15:36:21.586834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8577 15:36:21.590236 ==
8578 15:36:21.590323
8579 15:36:21.590410
8580 15:36:21.590493 TX Vref Scan disable
8581 15:36:21.593408 == TX Byte 0 ==
8582 15:36:21.596466 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8583 15:36:21.600243 == TX Byte 1 ==
8584 15:36:21.603680 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8585 15:36:21.606763 DramC Write-DBI off
8586 15:36:21.606849
8587 15:36:21.606951 [DATLAT]
8588 15:36:21.607033 Freq=1600, CH1 RK0
8589 15:36:21.607113
8590 15:36:21.610001 DATLAT Default: 0xf
8591 15:36:21.613204 0, 0xFFFF, sum = 0
8592 15:36:21.613318 1, 0xFFFF, sum = 0
8593 15:36:21.616888 2, 0xFFFF, sum = 0
8594 15:36:21.616971 3, 0xFFFF, sum = 0
8595 15:36:21.619940 4, 0xFFFF, sum = 0
8596 15:36:21.620024 5, 0xFFFF, sum = 0
8597 15:36:21.622996 6, 0xFFFF, sum = 0
8598 15:36:21.623080 7, 0xFFFF, sum = 0
8599 15:36:21.626881 8, 0xFFFF, sum = 0
8600 15:36:21.626965 9, 0xFFFF, sum = 0
8601 15:36:21.630140 10, 0xFFFF, sum = 0
8602 15:36:21.630223 11, 0xFFFF, sum = 0
8603 15:36:21.633211 12, 0xFFFF, sum = 0
8604 15:36:21.633295 13, 0x8FFF, sum = 0
8605 15:36:21.636236 14, 0x0, sum = 1
8606 15:36:21.636320 15, 0x0, sum = 2
8607 15:36:21.639964 16, 0x0, sum = 3
8608 15:36:21.640048 17, 0x0, sum = 4
8609 15:36:21.643040 best_step = 15
8610 15:36:21.643150
8611 15:36:21.643244 ==
8612 15:36:21.646139 Dram Type= 6, Freq= 0, CH_1, rank 0
8613 15:36:21.649808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8614 15:36:21.649891 ==
8615 15:36:21.652951 RX Vref Scan: 1
8616 15:36:21.653033
8617 15:36:21.653098 Set Vref Range= 24 -> 127
8618 15:36:21.653160
8619 15:36:21.656822 RX Vref 24 -> 127, step: 1
8620 15:36:21.656929
8621 15:36:21.659934 RX Delay 11 -> 252, step: 4
8622 15:36:21.660016
8623 15:36:21.663173 Set Vref, RX VrefLevel [Byte0]: 24
8624 15:36:21.666386 [Byte1]: 24
8625 15:36:21.666468
8626 15:36:21.669670 Set Vref, RX VrefLevel [Byte0]: 25
8627 15:36:21.672852 [Byte1]: 25
8628 15:36:21.676450
8629 15:36:21.676533 Set Vref, RX VrefLevel [Byte0]: 26
8630 15:36:21.679410 [Byte1]: 26
8631 15:36:21.683875
8632 15:36:21.683960 Set Vref, RX VrefLevel [Byte0]: 27
8633 15:36:21.686995 [Byte1]: 27
8634 15:36:21.691418
8635 15:36:21.691528 Set Vref, RX VrefLevel [Byte0]: 28
8636 15:36:21.694977 [Byte1]: 28
8637 15:36:21.699008
8638 15:36:21.699117 Set Vref, RX VrefLevel [Byte0]: 29
8639 15:36:21.702103 [Byte1]: 29
8640 15:36:21.706409
8641 15:36:21.706495 Set Vref, RX VrefLevel [Byte0]: 30
8642 15:36:21.709781 [Byte1]: 30
8643 15:36:21.714090
8644 15:36:21.714175 Set Vref, RX VrefLevel [Byte0]: 31
8645 15:36:21.717864 [Byte1]: 31
8646 15:36:21.721541
8647 15:36:21.721649 Set Vref, RX VrefLevel [Byte0]: 32
8648 15:36:21.725239 [Byte1]: 32
8649 15:36:21.729498
8650 15:36:21.729584 Set Vref, RX VrefLevel [Byte0]: 33
8651 15:36:21.732502 [Byte1]: 33
8652 15:36:21.736923
8653 15:36:21.737009 Set Vref, RX VrefLevel [Byte0]: 34
8654 15:36:21.740796 [Byte1]: 34
8655 15:36:21.744549
8656 15:36:21.744634 Set Vref, RX VrefLevel [Byte0]: 35
8657 15:36:21.747756 [Byte1]: 35
8658 15:36:21.752253
8659 15:36:21.752338 Set Vref, RX VrefLevel [Byte0]: 36
8660 15:36:21.755887 [Byte1]: 36
8661 15:36:21.760168
8662 15:36:21.760253 Set Vref, RX VrefLevel [Byte0]: 37
8663 15:36:21.763485 [Byte1]: 37
8664 15:36:21.767841
8665 15:36:21.767925 Set Vref, RX VrefLevel [Byte0]: 38
8666 15:36:21.770978 [Byte1]: 38
8667 15:36:21.775459
8668 15:36:21.775544 Set Vref, RX VrefLevel [Byte0]: 39
8669 15:36:21.778514 [Byte1]: 39
8670 15:36:21.782981
8671 15:36:21.783074 Set Vref, RX VrefLevel [Byte0]: 40
8672 15:36:21.786081 [Byte1]: 40
8673 15:36:21.790211
8674 15:36:21.790321 Set Vref, RX VrefLevel [Byte0]: 41
8675 15:36:21.793496 [Byte1]: 41
8676 15:36:21.798104
8677 15:36:21.798218 Set Vref, RX VrefLevel [Byte0]: 42
8678 15:36:21.801301 [Byte1]: 42
8679 15:36:21.805343
8680 15:36:21.805425 Set Vref, RX VrefLevel [Byte0]: 43
8681 15:36:21.808795 [Byte1]: 43
8682 15:36:21.813425
8683 15:36:21.813507 Set Vref, RX VrefLevel [Byte0]: 44
8684 15:36:21.816599 [Byte1]: 44
8685 15:36:21.821063
8686 15:36:21.821145 Set Vref, RX VrefLevel [Byte0]: 45
8687 15:36:21.824403 [Byte1]: 45
8688 15:36:21.828628
8689 15:36:21.828710 Set Vref, RX VrefLevel [Byte0]: 46
8690 15:36:21.831580 [Byte1]: 46
8691 15:36:21.836133
8692 15:36:21.836215 Set Vref, RX VrefLevel [Byte0]: 47
8693 15:36:21.839055 [Byte1]: 47
8694 15:36:21.843395
8695 15:36:21.843477 Set Vref, RX VrefLevel [Byte0]: 48
8696 15:36:21.847090 [Byte1]: 48
8697 15:36:21.851528
8698 15:36:21.851611 Set Vref, RX VrefLevel [Byte0]: 49
8699 15:36:21.854796 [Byte1]: 49
8700 15:36:21.859155
8701 15:36:21.859241 Set Vref, RX VrefLevel [Byte0]: 50
8702 15:36:21.862325 [Byte1]: 50
8703 15:36:21.866839
8704 15:36:21.866924 Set Vref, RX VrefLevel [Byte0]: 51
8705 15:36:21.870025 [Byte1]: 51
8706 15:36:21.874373
8707 15:36:21.874458 Set Vref, RX VrefLevel [Byte0]: 52
8708 15:36:21.877606 [Byte1]: 52
8709 15:36:21.881929
8710 15:36:21.882014 Set Vref, RX VrefLevel [Byte0]: 53
8711 15:36:21.884990 [Byte1]: 53
8712 15:36:21.889614
8713 15:36:21.889723 Set Vref, RX VrefLevel [Byte0]: 54
8714 15:36:21.892886 [Byte1]: 54
8715 15:36:21.897173
8716 15:36:21.897260 Set Vref, RX VrefLevel [Byte0]: 55
8717 15:36:21.900277 [Byte1]: 55
8718 15:36:21.904716
8719 15:36:21.904820 Set Vref, RX VrefLevel [Byte0]: 56
8720 15:36:21.908047 [Byte1]: 56
8721 15:36:21.912325
8722 15:36:21.912444 Set Vref, RX VrefLevel [Byte0]: 57
8723 15:36:21.915287 [Byte1]: 57
8724 15:36:21.920046
8725 15:36:21.920150 Set Vref, RX VrefLevel [Byte0]: 58
8726 15:36:21.923104 [Byte1]: 58
8727 15:36:21.927499
8728 15:36:21.927581 Set Vref, RX VrefLevel [Byte0]: 59
8729 15:36:21.930725 [Byte1]: 59
8730 15:36:21.934851
8731 15:36:21.934934 Set Vref, RX VrefLevel [Byte0]: 60
8732 15:36:21.938523 [Byte1]: 60
8733 15:36:21.943022
8734 15:36:21.943109 Set Vref, RX VrefLevel [Byte0]: 61
8735 15:36:21.945991 [Byte1]: 61
8736 15:36:21.950072
8737 15:36:21.950155 Set Vref, RX VrefLevel [Byte0]: 62
8738 15:36:21.953649 [Byte1]: 62
8739 15:36:21.958139
8740 15:36:21.958224 Set Vref, RX VrefLevel [Byte0]: 63
8741 15:36:21.961079 [Byte1]: 63
8742 15:36:21.965822
8743 15:36:21.965904 Set Vref, RX VrefLevel [Byte0]: 64
8744 15:36:21.968905 [Byte1]: 64
8745 15:36:21.973061
8746 15:36:21.973144 Set Vref, RX VrefLevel [Byte0]: 65
8747 15:36:21.976225 [Byte1]: 65
8748 15:36:21.980859
8749 15:36:21.980941 Set Vref, RX VrefLevel [Byte0]: 66
8750 15:36:21.984095 [Byte1]: 66
8751 15:36:21.988600
8752 15:36:21.988684 Set Vref, RX VrefLevel [Byte0]: 67
8753 15:36:21.991729 [Byte1]: 67
8754 15:36:21.996181
8755 15:36:21.996263 Set Vref, RX VrefLevel [Byte0]: 68
8756 15:36:21.999404 [Byte1]: 68
8757 15:36:22.003940
8758 15:36:22.004023 Set Vref, RX VrefLevel [Byte0]: 69
8759 15:36:22.007000 [Byte1]: 69
8760 15:36:22.011246
8761 15:36:22.011328 Set Vref, RX VrefLevel [Byte0]: 70
8762 15:36:22.014655 [Byte1]: 70
8763 15:36:22.019100
8764 15:36:22.019210 Final RX Vref Byte 0 = 57 to rank0
8765 15:36:22.022012 Final RX Vref Byte 1 = 56 to rank0
8766 15:36:22.025588 Final RX Vref Byte 0 = 57 to rank1
8767 15:36:22.028657 Final RX Vref Byte 1 = 56 to rank1==
8768 15:36:22.032016 Dram Type= 6, Freq= 0, CH_1, rank 0
8769 15:36:22.038921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 15:36:22.039008 ==
8771 15:36:22.039075 DQS Delay:
8772 15:36:22.041939 DQS0 = 0, DQS1 = 0
8773 15:36:22.042022 DQM Delay:
8774 15:36:22.042087 DQM0 = 131, DQM1 = 123
8775 15:36:22.045207 DQ Delay:
8776 15:36:22.048817 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8777 15:36:22.051769 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8778 15:36:22.054941 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8779 15:36:22.058006 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8780 15:36:22.058117
8781 15:36:22.058226
8782 15:36:22.058318
8783 15:36:22.061598 [DramC_TX_OE_Calibration] TA2
8784 15:36:22.064725 Original DQ_B0 (3 6) =30, OEN = 27
8785 15:36:22.068579 Original DQ_B1 (3 6) =30, OEN = 27
8786 15:36:22.071785 24, 0x0, End_B0=24 End_B1=24
8787 15:36:22.071866 25, 0x0, End_B0=25 End_B1=25
8788 15:36:22.074883 26, 0x0, End_B0=26 End_B1=26
8789 15:36:22.078033 27, 0x0, End_B0=27 End_B1=27
8790 15:36:22.081441 28, 0x0, End_B0=28 End_B1=28
8791 15:36:22.084717 29, 0x0, End_B0=29 End_B1=29
8792 15:36:22.084821 30, 0x0, End_B0=30 End_B1=30
8793 15:36:22.087907 31, 0x4141, End_B0=30 End_B1=30
8794 15:36:22.091580 Byte0 end_step=30 best_step=27
8795 15:36:22.094807 Byte1 end_step=30 best_step=27
8796 15:36:22.097908 Byte0 TX OE(2T, 0.5T) = (3, 3)
8797 15:36:22.101234 Byte1 TX OE(2T, 0.5T) = (3, 3)
8798 15:36:22.101308
8799 15:36:22.101376
8800 15:36:22.108130 [DQSOSCAuto] RK0, (LSB)MR18= 0x70c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8801 15:36:22.111357 CH1 RK0: MR19=303, MR18=70C
8802 15:36:22.118245 CH1_RK0: MR19=0x303, MR18=0x70C, DQSOSC=403, MR23=63, INC=22, DEC=15
8803 15:36:22.118327
8804 15:36:22.121350 ----->DramcWriteLeveling(PI) begin...
8805 15:36:22.121427 ==
8806 15:36:22.124665 Dram Type= 6, Freq= 0, CH_1, rank 1
8807 15:36:22.127813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8808 15:36:22.127930 ==
8809 15:36:22.131350 Write leveling (Byte 0): 23 => 23
8810 15:36:22.134732 Write leveling (Byte 1): 26 => 26
8811 15:36:22.137604 DramcWriteLeveling(PI) end<-----
8812 15:36:22.137681
8813 15:36:22.137751 ==
8814 15:36:22.141297 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 15:36:22.144434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 15:36:22.144515 ==
8817 15:36:22.147927 [Gating] SW mode calibration
8818 15:36:22.154228 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8819 15:36:22.160915 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8820 15:36:22.164645 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 15:36:22.168036 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 15:36:22.174736 1 4 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8823 15:36:22.177926 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8824 15:36:22.181224 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 15:36:22.187727 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 15:36:22.190759 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 15:36:22.194524 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 15:36:22.200958 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 15:36:22.204174 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 15:36:22.207513 1 5 8 | B1->B0 | 3434 2626 | 0 0 | (0 1) (1 0)
8831 15:36:22.214627 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8832 15:36:22.217804 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 15:36:22.220931 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 15:36:22.227686 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 15:36:22.230719 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 15:36:22.233889 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 15:36:22.240944 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8838 15:36:22.243808 1 6 8 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
8839 15:36:22.247279 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8840 15:36:22.253858 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 15:36:22.256967 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 15:36:22.260644 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 15:36:22.267196 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 15:36:22.270803 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 15:36:22.273930 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 15:36:22.280573 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8847 15:36:22.284007 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8848 15:36:22.287144 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 15:36:22.293675 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 15:36:22.297342 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 15:36:22.300434 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 15:36:22.306814 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 15:36:22.310552 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 15:36:22.313869 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 15:36:22.320131 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 15:36:22.323396 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 15:36:22.327254 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 15:36:22.333479 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 15:36:22.336741 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 15:36:22.340648 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 15:36:22.343689 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8862 15:36:22.350213 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8863 15:36:22.353515 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8864 15:36:22.356848 Total UI for P1: 0, mck2ui 16
8865 15:36:22.360052 best dqsien dly found for B0: ( 1, 9, 6)
8866 15:36:22.363788 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 15:36:22.366671 Total UI for P1: 0, mck2ui 16
8868 15:36:22.370128 best dqsien dly found for B1: ( 1, 9, 10)
8869 15:36:22.373171 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8870 15:36:22.379667 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8871 15:36:22.379760
8872 15:36:22.383561 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8873 15:36:22.386526 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8874 15:36:22.389560 [Gating] SW calibration Done
8875 15:36:22.389677 ==
8876 15:36:22.393031 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 15:36:22.396120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 15:36:22.396236 ==
8879 15:36:22.399936 RX Vref Scan: 0
8880 15:36:22.400019
8881 15:36:22.400084 RX Vref 0 -> 0, step: 1
8882 15:36:22.400152
8883 15:36:22.402947 RX Delay 0 -> 252, step: 8
8884 15:36:22.406131 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8885 15:36:22.409923 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8886 15:36:22.416219 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8887 15:36:22.419483 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8888 15:36:22.423180 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8889 15:36:22.426284 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8890 15:36:22.429489 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8891 15:36:22.436313 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8892 15:36:22.439733 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8893 15:36:22.442738 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8894 15:36:22.445925 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8895 15:36:22.449153 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8896 15:36:22.456232 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8897 15:36:22.459313 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8898 15:36:22.462831 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8899 15:36:22.465785 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8900 15:36:22.465860 ==
8901 15:36:22.469292 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 15:36:22.475913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 15:36:22.475993 ==
8904 15:36:22.476057 DQS Delay:
8905 15:36:22.479488 DQS0 = 0, DQS1 = 0
8906 15:36:22.479562 DQM Delay:
8907 15:36:22.482293 DQM0 = 132, DQM1 = 128
8908 15:36:22.482365 DQ Delay:
8909 15:36:22.485977 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8910 15:36:22.489293 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8911 15:36:22.492313 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8912 15:36:22.495414 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8913 15:36:22.495525
8914 15:36:22.495619
8915 15:36:22.495708 ==
8916 15:36:22.498871 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 15:36:22.505878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 15:36:22.505963 ==
8919 15:36:22.506030
8920 15:36:22.506091
8921 15:36:22.506149 TX Vref Scan disable
8922 15:36:22.508737 == TX Byte 0 ==
8923 15:36:22.512699 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8924 15:36:22.518637 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8925 15:36:22.518752 == TX Byte 1 ==
8926 15:36:22.522452 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8927 15:36:22.528998 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8928 15:36:22.529109 ==
8929 15:36:22.532158 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 15:36:22.535382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 15:36:22.535467 ==
8932 15:36:22.549021
8933 15:36:22.552150 TX Vref early break, caculate TX vref
8934 15:36:22.555428 TX Vref=16, minBit 0, minWin=22, winSum=380
8935 15:36:22.559186 TX Vref=18, minBit 0, minWin=22, winSum=390
8936 15:36:22.562448 TX Vref=20, minBit 0, minWin=23, winSum=398
8937 15:36:22.565375 TX Vref=22, minBit 0, minWin=23, winSum=404
8938 15:36:22.569137 TX Vref=24, minBit 0, minWin=25, winSum=419
8939 15:36:22.575397 TX Vref=26, minBit 1, minWin=24, winSum=422
8940 15:36:22.578860 TX Vref=28, minBit 0, minWin=25, winSum=421
8941 15:36:22.582458 TX Vref=30, minBit 5, minWin=24, winSum=419
8942 15:36:22.585601 TX Vref=32, minBit 5, minWin=23, winSum=414
8943 15:36:22.588598 TX Vref=34, minBit 5, minWin=23, winSum=404
8944 15:36:22.592263 TX Vref=36, minBit 1, minWin=22, winSum=397
8945 15:36:22.598380 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8946 15:36:22.598498
8947 15:36:22.602032 Final TX Range 0 Vref 28
8948 15:36:22.602111
8949 15:36:22.602177 ==
8950 15:36:22.605648 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 15:36:22.608785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 15:36:22.608867 ==
8953 15:36:22.608933
8954 15:36:22.612011
8955 15:36:22.612092 TX Vref Scan disable
8956 15:36:22.618573 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8957 15:36:22.618675 == TX Byte 0 ==
8958 15:36:22.621652 u2DelayCellOfst[0]=15 cells (4 PI)
8959 15:36:22.624946 u2DelayCellOfst[1]=11 cells (3 PI)
8960 15:36:22.628564 u2DelayCellOfst[2]=0 cells (0 PI)
8961 15:36:22.631811 u2DelayCellOfst[3]=3 cells (1 PI)
8962 15:36:22.635047 u2DelayCellOfst[4]=7 cells (2 PI)
8963 15:36:22.638214 u2DelayCellOfst[5]=18 cells (5 PI)
8964 15:36:22.641508 u2DelayCellOfst[6]=15 cells (4 PI)
8965 15:36:22.645185 u2DelayCellOfst[7]=3 cells (1 PI)
8966 15:36:22.648184 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8967 15:36:22.651825 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8968 15:36:22.655079 == TX Byte 1 ==
8969 15:36:22.658284 u2DelayCellOfst[8]=0 cells (0 PI)
8970 15:36:22.661510 u2DelayCellOfst[9]=7 cells (2 PI)
8971 15:36:22.661591 u2DelayCellOfst[10]=15 cells (4 PI)
8972 15:36:22.665290 u2DelayCellOfst[11]=7 cells (2 PI)
8973 15:36:22.668443 u2DelayCellOfst[12]=15 cells (4 PI)
8974 15:36:22.671435 u2DelayCellOfst[13]=18 cells (5 PI)
8975 15:36:22.674799 u2DelayCellOfst[14]=18 cells (5 PI)
8976 15:36:22.678653 u2DelayCellOfst[15]=22 cells (6 PI)
8977 15:36:22.685254 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8978 15:36:22.688254 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8979 15:36:22.688391 DramC Write-DBI on
8980 15:36:22.688483 ==
8981 15:36:22.691833 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 15:36:22.698380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 15:36:22.698462 ==
8984 15:36:22.698527
8985 15:36:22.698586
8986 15:36:22.698644 TX Vref Scan disable
8987 15:36:22.702107 == TX Byte 0 ==
8988 15:36:22.705953 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8989 15:36:22.709055 == TX Byte 1 ==
8990 15:36:22.711937 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8991 15:36:22.715522 DramC Write-DBI off
8992 15:36:22.715602
8993 15:36:22.715665 [DATLAT]
8994 15:36:22.715724 Freq=1600, CH1 RK1
8995 15:36:22.715781
8996 15:36:22.719083 DATLAT Default: 0xf
8997 15:36:22.719179 0, 0xFFFF, sum = 0
8998 15:36:22.722194 1, 0xFFFF, sum = 0
8999 15:36:22.725162 2, 0xFFFF, sum = 0
9000 15:36:22.725242 3, 0xFFFF, sum = 0
9001 15:36:22.728665 4, 0xFFFF, sum = 0
9002 15:36:22.728746 5, 0xFFFF, sum = 0
9003 15:36:22.732300 6, 0xFFFF, sum = 0
9004 15:36:22.732409 7, 0xFFFF, sum = 0
9005 15:36:22.735530 8, 0xFFFF, sum = 0
9006 15:36:22.735612 9, 0xFFFF, sum = 0
9007 15:36:22.738693 10, 0xFFFF, sum = 0
9008 15:36:22.738777 11, 0xFFFF, sum = 0
9009 15:36:22.742143 12, 0xFFFF, sum = 0
9010 15:36:22.742252 13, 0x8FFF, sum = 0
9011 15:36:22.745202 14, 0x0, sum = 1
9012 15:36:22.745283 15, 0x0, sum = 2
9013 15:36:22.748219 16, 0x0, sum = 3
9014 15:36:22.748328 17, 0x0, sum = 4
9015 15:36:22.752059 best_step = 15
9016 15:36:22.752168
9017 15:36:22.752276 ==
9018 15:36:22.755055 Dram Type= 6, Freq= 0, CH_1, rank 1
9019 15:36:22.758654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9020 15:36:22.758735 ==
9021 15:36:22.761935 RX Vref Scan: 0
9022 15:36:22.762015
9023 15:36:22.762079 RX Vref 0 -> 0, step: 1
9024 15:36:22.762160
9025 15:36:22.765165 RX Delay 11 -> 252, step: 4
9026 15:36:22.768288 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9027 15:36:22.775210 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9028 15:36:22.778226 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9029 15:36:22.782057 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
9030 15:36:22.785082 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9031 15:36:22.788353 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9032 15:36:22.795141 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9033 15:36:22.798246 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
9034 15:36:22.801531 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
9035 15:36:22.804998 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9036 15:36:22.808482 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9037 15:36:22.814808 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9038 15:36:22.817896 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9039 15:36:22.821297 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9040 15:36:22.825087 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9041 15:36:22.831590 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9042 15:36:22.831677 ==
9043 15:36:22.834858 Dram Type= 6, Freq= 0, CH_1, rank 1
9044 15:36:22.838603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9045 15:36:22.838712 ==
9046 15:36:22.838806 DQS Delay:
9047 15:36:22.841770 DQS0 = 0, DQS1 = 0
9048 15:36:22.841878 DQM Delay:
9049 15:36:22.845180 DQM0 = 130, DQM1 = 125
9050 15:36:22.845263 DQ Delay:
9051 15:36:22.848366 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
9052 15:36:22.851484 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =126
9053 15:36:22.854922 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9054 15:36:22.857998 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =136
9055 15:36:22.858080
9056 15:36:22.858145
9057 15:36:22.858205
9058 15:36:22.861444 [DramC_TX_OE_Calibration] TA2
9059 15:36:22.864692 Original DQ_B0 (3 6) =30, OEN = 27
9060 15:36:22.867815 Original DQ_B1 (3 6) =30, OEN = 27
9061 15:36:22.871103 24, 0x0, End_B0=24 End_B1=24
9062 15:36:22.875012 25, 0x0, End_B0=25 End_B1=25
9063 15:36:22.875096 26, 0x0, End_B0=26 End_B1=26
9064 15:36:22.878003 27, 0x0, End_B0=27 End_B1=27
9065 15:36:22.881309 28, 0x0, End_B0=28 End_B1=28
9066 15:36:22.884738 29, 0x0, End_B0=29 End_B1=29
9067 15:36:22.887848 30, 0x0, End_B0=30 End_B1=30
9068 15:36:22.887932 31, 0x4141, End_B0=30 End_B1=30
9069 15:36:22.891142 Byte0 end_step=30 best_step=27
9070 15:36:22.894780 Byte1 end_step=30 best_step=27
9071 15:36:22.897885 Byte0 TX OE(2T, 0.5T) = (3, 3)
9072 15:36:22.901026 Byte1 TX OE(2T, 0.5T) = (3, 3)
9073 15:36:22.901100
9074 15:36:22.901162
9075 15:36:22.907581 [DQSOSCAuto] RK1, (LSB)MR18= 0x121e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9076 15:36:22.911223 CH1 RK1: MR19=303, MR18=121E
9077 15:36:22.917757 CH1_RK1: MR19=0x303, MR18=0x121E, DQSOSC=394, MR23=63, INC=23, DEC=15
9078 15:36:22.921106 [RxdqsGatingPostProcess] freq 1600
9079 15:36:22.928130 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9080 15:36:22.931146 best DQS0 dly(2T, 0.5T) = (1, 1)
9081 15:36:22.931224 best DQS1 dly(2T, 0.5T) = (1, 1)
9082 15:36:22.934173 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9083 15:36:22.937578 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9084 15:36:22.941361 best DQS0 dly(2T, 0.5T) = (1, 1)
9085 15:36:22.944137 best DQS1 dly(2T, 0.5T) = (1, 1)
9086 15:36:22.947490 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9087 15:36:22.950855 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9088 15:36:22.954432 Pre-setting of DQS Precalculation
9089 15:36:22.957512 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9090 15:36:22.967716 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9091 15:36:22.974118 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9092 15:36:22.974201
9093 15:36:22.974274
9094 15:36:22.977277 [Calibration Summary] 3200 Mbps
9095 15:36:22.977371 CH 0, Rank 0
9096 15:36:22.980363 SW Impedance : PASS
9097 15:36:22.980457 DUTY Scan : NO K
9098 15:36:22.984064 ZQ Calibration : PASS
9099 15:36:22.987280 Jitter Meter : NO K
9100 15:36:22.987409 CBT Training : PASS
9101 15:36:22.990754 Write leveling : PASS
9102 15:36:22.993837 RX DQS gating : PASS
9103 15:36:22.993919 RX DQ/DQS(RDDQC) : PASS
9104 15:36:22.997571 TX DQ/DQS : PASS
9105 15:36:23.000747 RX DATLAT : PASS
9106 15:36:23.000825 RX DQ/DQS(Engine): PASS
9107 15:36:23.003856 TX OE : PASS
9108 15:36:23.003937 All Pass.
9109 15:36:23.004001
9110 15:36:23.007048 CH 0, Rank 1
9111 15:36:23.007152 SW Impedance : PASS
9112 15:36:23.010256 DUTY Scan : NO K
9113 15:36:23.014123 ZQ Calibration : PASS
9114 15:36:23.014232 Jitter Meter : NO K
9115 15:36:23.017239 CBT Training : PASS
9116 15:36:23.020264 Write leveling : PASS
9117 15:36:23.020345 RX DQS gating : PASS
9118 15:36:23.023506 RX DQ/DQS(RDDQC) : PASS
9119 15:36:23.023614 TX DQ/DQS : PASS
9120 15:36:23.027028 RX DATLAT : PASS
9121 15:36:23.030512 RX DQ/DQS(Engine): PASS
9122 15:36:23.030590 TX OE : PASS
9123 15:36:23.033912 All Pass.
9124 15:36:23.033994
9125 15:36:23.034059 CH 1, Rank 0
9126 15:36:23.036948 SW Impedance : PASS
9127 15:36:23.037053 DUTY Scan : NO K
9128 15:36:23.040724 ZQ Calibration : PASS
9129 15:36:23.043703 Jitter Meter : NO K
9130 15:36:23.043785 CBT Training : PASS
9131 15:36:23.046945 Write leveling : PASS
9132 15:36:23.050269 RX DQS gating : PASS
9133 15:36:23.050374 RX DQ/DQS(RDDQC) : PASS
9134 15:36:23.053366 TX DQ/DQS : PASS
9135 15:36:23.056632 RX DATLAT : PASS
9136 15:36:23.056741 RX DQ/DQS(Engine): PASS
9137 15:36:23.060335 TX OE : PASS
9138 15:36:23.060418 All Pass.
9139 15:36:23.060483
9140 15:36:23.063678 CH 1, Rank 1
9141 15:36:23.063765 SW Impedance : PASS
9142 15:36:23.066793 DUTY Scan : NO K
9143 15:36:23.069882 ZQ Calibration : PASS
9144 15:36:23.069965 Jitter Meter : NO K
9145 15:36:23.073590 CBT Training : PASS
9146 15:36:23.076864 Write leveling : PASS
9147 15:36:23.076942 RX DQS gating : PASS
9148 15:36:23.080128 RX DQ/DQS(RDDQC) : PASS
9149 15:36:23.083246 TX DQ/DQS : PASS
9150 15:36:23.083362 RX DATLAT : PASS
9151 15:36:23.086978 RX DQ/DQS(Engine): PASS
9152 15:36:23.087076 TX OE : PASS
9153 15:36:23.090062 All Pass.
9154 15:36:23.090177
9155 15:36:23.090274 DramC Write-DBI on
9156 15:36:23.093376 PER_BANK_REFRESH: Hybrid Mode
9157 15:36:23.096753 TX_TRACKING: ON
9158 15:36:23.103511 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9159 15:36:23.113558 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9160 15:36:23.119994 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9161 15:36:23.123153 [FAST_K] Save calibration result to emmc
9162 15:36:23.126464 sync common calibartion params.
9163 15:36:23.126544 sync cbt_mode0:1, 1:1
9164 15:36:23.129624 dram_init: ddr_geometry: 2
9165 15:36:23.132741 dram_init: ddr_geometry: 2
9166 15:36:23.136645 dram_init: ddr_geometry: 2
9167 15:36:23.136760 0:dram_rank_size:100000000
9168 15:36:23.139596 1:dram_rank_size:100000000
9169 15:36:23.146173 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9170 15:36:23.146280 DFS_SHUFFLE_HW_MODE: ON
9171 15:36:23.152883 dramc_set_vcore_voltage set vcore to 725000
9172 15:36:23.152991 Read voltage for 1600, 0
9173 15:36:23.156096 Vio18 = 0
9174 15:36:23.156176 Vcore = 725000
9175 15:36:23.156240 Vdram = 0
9176 15:36:23.156300 Vddq = 0
9177 15:36:23.159762 Vmddr = 0
9178 15:36:23.159841 switch to 3200 Mbps bootup
9179 15:36:23.163158 [DramcRunTimeConfig]
9180 15:36:23.163238 PHYPLL
9181 15:36:23.166065 DPM_CONTROL_AFTERK: ON
9182 15:36:23.166145 PER_BANK_REFRESH: ON
9183 15:36:23.169547 REFRESH_OVERHEAD_REDUCTION: ON
9184 15:36:23.173252 CMD_PICG_NEW_MODE: OFF
9185 15:36:23.173332 XRTWTW_NEW_MODE: ON
9186 15:36:23.176217 XRTRTR_NEW_MODE: ON
9187 15:36:23.176301 TX_TRACKING: ON
9188 15:36:23.179514 RDSEL_TRACKING: OFF
9189 15:36:23.182678 DQS Precalculation for DVFS: ON
9190 15:36:23.182784 RX_TRACKING: OFF
9191 15:36:23.186509 HW_GATING DBG: ON
9192 15:36:23.186589 ZQCS_ENABLE_LP4: ON
9193 15:36:23.189704 RX_PICG_NEW_MODE: ON
9194 15:36:23.192878 TX_PICG_NEW_MODE: ON
9195 15:36:23.192988 ENABLE_RX_DCM_DPHY: ON
9196 15:36:23.196070 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9197 15:36:23.199251 DUMMY_READ_FOR_TRACKING: OFF
9198 15:36:23.203087 !!! SPM_CONTROL_AFTERK: OFF
9199 15:36:23.203179 !!! SPM could not control APHY
9200 15:36:23.205930 IMPEDANCE_TRACKING: ON
9201 15:36:23.206007 TEMP_SENSOR: ON
9202 15:36:23.209607 HW_SAVE_FOR_SR: OFF
9203 15:36:23.212861 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9204 15:36:23.216072 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9205 15:36:23.219188 Read ODT Tracking: ON
9206 15:36:23.219271 Refresh Rate DeBounce: ON
9207 15:36:23.222511 DFS_NO_QUEUE_FLUSH: ON
9208 15:36:23.226323 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9209 15:36:23.229496 ENABLE_DFS_RUNTIME_MRW: OFF
9210 15:36:23.229604 DDR_RESERVE_NEW_MODE: ON
9211 15:36:23.232746 MR_CBT_SWITCH_FREQ: ON
9212 15:36:23.235785 =========================
9213 15:36:23.254147 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9214 15:36:23.256915 dram_init: ddr_geometry: 2
9215 15:36:23.275067 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9216 15:36:23.278844 dram_init: dram init end (result: 0)
9217 15:36:23.285179 DRAM-K: Full calibration passed in 24573 msecs
9218 15:36:23.288349 MRC: failed to locate region type 0.
9219 15:36:23.288457 DRAM rank0 size:0x100000000,
9220 15:36:23.291496 DRAM rank1 size=0x100000000
9221 15:36:23.301824 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9222 15:36:23.308685 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9223 15:36:23.314699 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9224 15:36:23.321401 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9225 15:36:23.324710 DRAM rank0 size:0x100000000,
9226 15:36:23.327939 DRAM rank1 size=0x100000000
9227 15:36:23.328022 CBMEM:
9228 15:36:23.331767 IMD: root @ 0xfffff000 254 entries.
9229 15:36:23.334910 IMD: root @ 0xffffec00 62 entries.
9230 15:36:23.338095 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9231 15:36:23.344596 WARNING: RO_VPD is uninitialized or empty.
9232 15:36:23.347723 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9233 15:36:23.355606 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9234 15:36:23.368324 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9235 15:36:23.379377 BS: romstage times (exec / console): total (unknown) / 24035 ms
9236 15:36:23.379481
9237 15:36:23.379548
9238 15:36:23.389464 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9239 15:36:23.392572 ARM64: Exception handlers installed.
9240 15:36:23.396134 ARM64: Testing exception
9241 15:36:23.399092 ARM64: Done test exception
9242 15:36:23.399204 Enumerating buses...
9243 15:36:23.402892 Show all devs... Before device enumeration.
9244 15:36:23.406033 Root Device: enabled 1
9245 15:36:23.409422 CPU_CLUSTER: 0: enabled 1
9246 15:36:23.409508 CPU: 00: enabled 1
9247 15:36:23.412970 Compare with tree...
9248 15:36:23.413052 Root Device: enabled 1
9249 15:36:23.416226 CPU_CLUSTER: 0: enabled 1
9250 15:36:23.419342 CPU: 00: enabled 1
9251 15:36:23.419438 Root Device scanning...
9252 15:36:23.422310 scan_static_bus for Root Device
9253 15:36:23.425687 CPU_CLUSTER: 0 enabled
9254 15:36:23.429394 scan_static_bus for Root Device done
9255 15:36:23.432614 scan_bus: bus Root Device finished in 8 msecs
9256 15:36:23.432695 done
9257 15:36:23.438941 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9258 15:36:23.442166 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9259 15:36:23.449237 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9260 15:36:23.452426 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9261 15:36:23.455618 Allocating resources...
9262 15:36:23.458764 Reading resources...
9263 15:36:23.462601 Root Device read_resources bus 0 link: 0
9264 15:36:23.462679 DRAM rank0 size:0x100000000,
9265 15:36:23.465504 DRAM rank1 size=0x100000000
9266 15:36:23.468654 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9267 15:36:23.472332 CPU: 00 missing read_resources
9268 15:36:23.478746 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9269 15:36:23.482377 Root Device read_resources bus 0 link: 0 done
9270 15:36:23.482458 Done reading resources.
9271 15:36:23.488822 Show resources in subtree (Root Device)...After reading.
9272 15:36:23.492101 Root Device child on link 0 CPU_CLUSTER: 0
9273 15:36:23.495704 CPU_CLUSTER: 0 child on link 0 CPU: 00
9274 15:36:23.505453 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9275 15:36:23.505560 CPU: 00
9276 15:36:23.509000 Root Device assign_resources, bus 0 link: 0
9277 15:36:23.512050 CPU_CLUSTER: 0 missing set_resources
9278 15:36:23.518898 Root Device assign_resources, bus 0 link: 0 done
9279 15:36:23.518983 Done setting resources.
9280 15:36:23.525386 Show resources in subtree (Root Device)...After assigning values.
9281 15:36:23.529044 Root Device child on link 0 CPU_CLUSTER: 0
9282 15:36:23.532135 CPU_CLUSTER: 0 child on link 0 CPU: 00
9283 15:36:23.542004 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9284 15:36:23.542112 CPU: 00
9285 15:36:23.545154 Done allocating resources.
9286 15:36:23.548406 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9287 15:36:23.552141 Enabling resources...
9288 15:36:23.552222 done.
9289 15:36:23.558597 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9290 15:36:23.558676 Initializing devices...
9291 15:36:23.561887 Root Device init
9292 15:36:23.561970 init hardware done!
9293 15:36:23.565014 0x00000018: ctrlr->caps
9294 15:36:23.568701 52.000 MHz: ctrlr->f_max
9295 15:36:23.568785 0.400 MHz: ctrlr->f_min
9296 15:36:23.571907 0x40ff8080: ctrlr->voltages
9297 15:36:23.571985 sclk: 390625
9298 15:36:23.574956 Bus Width = 1
9299 15:36:23.575078 sclk: 390625
9300 15:36:23.578686 Bus Width = 1
9301 15:36:23.578785 Early init status = 3
9302 15:36:23.584921 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9303 15:36:23.588635 in-header: 03 fc 00 00 01 00 00 00
9304 15:36:23.588744 in-data: 00
9305 15:36:23.594794 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9306 15:36:23.598400 in-header: 03 fd 00 00 00 00 00 00
9307 15:36:23.602097 in-data:
9308 15:36:23.605084 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9309 15:36:23.608219 in-header: 03 fc 00 00 01 00 00 00
9310 15:36:23.611811 in-data: 00
9311 15:36:23.614846 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9312 15:36:23.620247 in-header: 03 fd 00 00 00 00 00 00
9313 15:36:23.623884 in-data:
9314 15:36:23.626491 [SSUSB] Setting up USB HOST controller...
9315 15:36:23.630142 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9316 15:36:23.633276 [SSUSB] phy power-on done.
9317 15:36:23.636606 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9318 15:36:23.643520 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9319 15:36:23.647055 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9320 15:36:23.653719 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9321 15:36:23.660111 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9322 15:36:23.666658 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9323 15:36:23.673620 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9324 15:36:23.679943 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9325 15:36:23.683594 SPM: binary array size = 0x9dc
9326 15:36:23.686932 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9327 15:36:23.693317 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9328 15:36:23.699966 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9329 15:36:23.703738 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9330 15:36:23.706983 configure_display: Starting display init
9331 15:36:23.743569 anx7625_power_on_init: Init interface.
9332 15:36:23.746728 anx7625_disable_pd_protocol: Disabled PD feature.
9333 15:36:23.749860 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9334 15:36:23.778187 anx7625_start_dp_work: Secure OCM version=00
9335 15:36:23.781294 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9336 15:36:23.795893 sp_tx_get_edid_block: EDID Block = 1
9337 15:36:23.898589 Extracted contents:
9338 15:36:23.901502 header: 00 ff ff ff ff ff ff 00
9339 15:36:23.904927 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9340 15:36:23.908420 version: 01 04
9341 15:36:23.911759 basic params: 95 1f 11 78 0a
9342 15:36:23.914884 chroma info: 76 90 94 55 54 90 27 21 50 54
9343 15:36:23.918189 established: 00 00 00
9344 15:36:23.924803 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9345 15:36:23.931258 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9346 15:36:23.934480 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9347 15:36:23.941470 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9348 15:36:23.947748 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9349 15:36:23.950881 extensions: 00
9350 15:36:23.950985 checksum: fb
9351 15:36:23.951079
9352 15:36:23.954997 Manufacturer: IVO Model 57d Serial Number 0
9353 15:36:23.957932 Made week 0 of 2020
9354 15:36:23.961146 EDID version: 1.4
9355 15:36:23.961251 Digital display
9356 15:36:23.964752 6 bits per primary color channel
9357 15:36:23.964835 DisplayPort interface
9358 15:36:23.967633 Maximum image size: 31 cm x 17 cm
9359 15:36:23.971237 Gamma: 220%
9360 15:36:23.971317 Check DPMS levels
9361 15:36:23.974628 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9362 15:36:23.980776 First detailed timing is preferred timing
9363 15:36:23.980871 Established timings supported:
9364 15:36:23.984492 Standard timings supported:
9365 15:36:23.987525 Detailed timings
9366 15:36:23.990708 Hex of detail: 383680a07038204018303c0035ae10000019
9367 15:36:23.997425 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9368 15:36:24.000675 0780 0798 07c8 0820 hborder 0
9369 15:36:24.004564 0438 043b 0447 0458 vborder 0
9370 15:36:24.007751 -hsync -vsync
9371 15:36:24.007834 Did detailed timing
9372 15:36:24.014530 Hex of detail: 000000000000000000000000000000000000
9373 15:36:24.017828 Manufacturer-specified data, tag 0
9374 15:36:24.020946 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9375 15:36:24.024214 ASCII string: InfoVision
9376 15:36:24.027273 Hex of detail: 000000fe00523134304e574635205248200a
9377 15:36:24.030410 ASCII string: R140NWF5 RH
9378 15:36:24.030492 Checksum
9379 15:36:24.034083 Checksum: 0xfb (valid)
9380 15:36:24.037319 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9381 15:36:24.040452 DSI data_rate: 832800000 bps
9382 15:36:24.047414 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9383 15:36:24.050723 anx7625_parse_edid: pixelclock(138800).
9384 15:36:24.053671 hactive(1920), hsync(48), hfp(24), hbp(88)
9385 15:36:24.056840 vactive(1080), vsync(12), vfp(3), vbp(17)
9386 15:36:24.060606 anx7625_dsi_config: config dsi.
9387 15:36:24.067100 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9388 15:36:24.080368 anx7625_dsi_config: success to config DSI
9389 15:36:24.084131 anx7625_dp_start: MIPI phy setup OK.
9390 15:36:24.087104 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9391 15:36:24.090814 mtk_ddp_mode_set invalid vrefresh 60
9392 15:36:24.093585 main_disp_path_setup
9393 15:36:24.093667 ovl_layer_smi_id_en
9394 15:36:24.096822 ovl_layer_smi_id_en
9395 15:36:24.096905 ccorr_config
9396 15:36:24.096971 aal_config
9397 15:36:24.100672 gamma_config
9398 15:36:24.100785 postmask_config
9399 15:36:24.104015 dither_config
9400 15:36:24.107005 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9401 15:36:24.113807 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9402 15:36:24.116862 Root Device init finished in 552 msecs
9403 15:36:24.116944 CPU_CLUSTER: 0 init
9404 15:36:24.126965 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9405 15:36:24.130762 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9406 15:36:24.133805 APU_MBOX 0x190000b0 = 0x10001
9407 15:36:24.137000 APU_MBOX 0x190001b0 = 0x10001
9408 15:36:24.140612 APU_MBOX 0x190005b0 = 0x10001
9409 15:36:24.143550 APU_MBOX 0x190006b0 = 0x10001
9410 15:36:24.146916 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9411 15:36:24.159871 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9412 15:36:24.171784 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9413 15:36:24.178774 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9414 15:36:24.190121 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9415 15:36:24.199585 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9416 15:36:24.202566 CPU_CLUSTER: 0 init finished in 81 msecs
9417 15:36:24.206621 Devices initialized
9418 15:36:24.209471 Show all devs... After init.
9419 15:36:24.209578 Root Device: enabled 1
9420 15:36:24.212579 CPU_CLUSTER: 0: enabled 1
9421 15:36:24.215889 CPU: 00: enabled 1
9422 15:36:24.219386 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9423 15:36:24.222571 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9424 15:36:24.225580 ELOG: NV offset 0x57f000 size 0x1000
9425 15:36:24.232611 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9426 15:36:24.239021 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9427 15:36:24.242378 ELOG: Event(17) added with size 13 at 2023-08-22 15:36:24 UTC
9428 15:36:24.245504 out: cmd=0x121: 03 db 21 01 00 00 00 00
9429 15:36:24.249868 in-header: 03 5c 00 00 2c 00 00 00
9430 15:36:24.262690 in-data: 02 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9431 15:36:24.269620 ELOG: Event(A1) added with size 10 at 2023-08-22 15:36:24 UTC
9432 15:36:24.275959 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9433 15:36:24.282428 ELOG: Event(A0) added with size 9 at 2023-08-22 15:36:24 UTC
9434 15:36:24.286132 elog_add_boot_reason: Logged dev mode boot
9435 15:36:24.289296 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9436 15:36:24.292960 Finalize devices...
9437 15:36:24.293093 Devices finalized
9438 15:36:24.299181 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9439 15:36:24.302944 Writing coreboot table at 0xffe64000
9440 15:36:24.306117 0. 000000000010a000-0000000000113fff: RAMSTAGE
9441 15:36:24.309205 1. 0000000040000000-00000000400fffff: RAM
9442 15:36:24.312766 2. 0000000040100000-000000004032afff: RAMSTAGE
9443 15:36:24.319297 3. 000000004032b000-00000000545fffff: RAM
9444 15:36:24.322537 4. 0000000054600000-000000005465ffff: BL31
9445 15:36:24.326322 5. 0000000054660000-00000000ffe63fff: RAM
9446 15:36:24.332677 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9447 15:36:24.335877 7. 0000000100000000-000000023fffffff: RAM
9448 15:36:24.335954 Passing 5 GPIOs to payload:
9449 15:36:24.342297 NAME | PORT | POLARITY | VALUE
9450 15:36:24.345552 EC in RW | 0x000000aa | low | undefined
9451 15:36:24.352717 EC interrupt | 0x00000005 | low | undefined
9452 15:36:24.355855 TPM interrupt | 0x000000ab | high | undefined
9453 15:36:24.358841 SD card detect | 0x00000011 | high | undefined
9454 15:36:24.365801 speaker enable | 0x00000093 | high | undefined
9455 15:36:24.369411 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9456 15:36:24.372240 in-header: 03 f9 00 00 02 00 00 00
9457 15:36:24.372345 in-data: 02 00
9458 15:36:24.375868 ADC[4]: Raw value=896300 ID=7
9459 15:36:24.378975 ADC[3]: Raw value=212330 ID=1
9460 15:36:24.379086 RAM Code: 0x71
9461 15:36:24.382491 ADC[6]: Raw value=74722 ID=0
9462 15:36:24.385614 ADC[5]: Raw value=212330 ID=1
9463 15:36:24.385719 SKU Code: 0x1
9464 15:36:24.392444 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 360f
9465 15:36:24.395602 coreboot table: 964 bytes.
9466 15:36:24.398630 IMD ROOT 0. 0xfffff000 0x00001000
9467 15:36:24.402628 IMD SMALL 1. 0xffffe000 0x00001000
9468 15:36:24.405219 RO MCACHE 2. 0xffffc000 0x00001104
9469 15:36:24.408398 CONSOLE 3. 0xfff7c000 0x00080000
9470 15:36:24.412279 FMAP 4. 0xfff7b000 0x00000452
9471 15:36:24.415447 TIME STAMP 5. 0xfff7a000 0x00000910
9472 15:36:24.418656 VBOOT WORK 6. 0xfff66000 0x00014000
9473 15:36:24.422178 RAMOOPS 7. 0xffe66000 0x00100000
9474 15:36:24.425140 COREBOOT 8. 0xffe64000 0x00002000
9475 15:36:24.425256 IMD small region:
9476 15:36:24.428892 IMD ROOT 0. 0xffffec00 0x00000400
9477 15:36:24.431463 VPD 1. 0xffffeb80 0x0000006c
9478 15:36:24.435209 MMC STATUS 2. 0xffffeb60 0x00000004
9479 15:36:24.442033 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9480 15:36:24.445098 Probing TPM: done!
9481 15:36:24.448524 Connected to device vid:did:rid of 1ae0:0028:00
9482 15:36:24.458846 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9483 15:36:24.461946 Initialized TPM device CR50 revision 0
9484 15:36:24.466207 Checking cr50 for pending updates
9485 15:36:24.470015 Reading cr50 TPM mode
9486 15:36:24.477467 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9487 15:36:24.484652 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9488 15:36:24.524462 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9489 15:36:24.527551 Checking segment from ROM address 0x40100000
9490 15:36:24.531208 Checking segment from ROM address 0x4010001c
9491 15:36:24.537393 Loading segment from ROM address 0x40100000
9492 15:36:24.537498 code (compression=0)
9493 15:36:24.547608 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9494 15:36:24.554328 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9495 15:36:24.554424 it's not compressed!
9496 15:36:24.561183 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9497 15:36:24.564092 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9498 15:36:24.584870 Loading segment from ROM address 0x4010001c
9499 15:36:24.584960 Entry Point 0x80000000
9500 15:36:24.587890 Loaded segments
9501 15:36:24.591280 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9502 15:36:24.598082 Jumping to boot code at 0x80000000(0xffe64000)
9503 15:36:24.604418 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9504 15:36:24.611162 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9505 15:36:24.619046 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9506 15:36:24.623029 Checking segment from ROM address 0x40100000
9507 15:36:24.626176 Checking segment from ROM address 0x4010001c
9508 15:36:24.632534 Loading segment from ROM address 0x40100000
9509 15:36:24.632618 code (compression=1)
9510 15:36:24.639457 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9511 15:36:24.649345 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9512 15:36:24.649432 using LZMA
9513 15:36:24.657905 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9514 15:36:24.664053 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9515 15:36:24.667796 Loading segment from ROM address 0x4010001c
9516 15:36:24.667899 Entry Point 0x54601000
9517 15:36:24.670804 Loaded segments
9518 15:36:24.674205 NOTICE: MT8192 bl31_setup
9519 15:36:24.680955 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9520 15:36:24.684382 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9521 15:36:24.687783 WARNING: region 0:
9522 15:36:24.691292 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 15:36:24.691397 WARNING: region 1:
9524 15:36:24.697713 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9525 15:36:24.701142 WARNING: region 2:
9526 15:36:24.704740 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9527 15:36:24.707900 WARNING: region 3:
9528 15:36:24.711069 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9529 15:36:24.714887 WARNING: region 4:
9530 15:36:24.717899 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9531 15:36:24.720947 WARNING: region 5:
9532 15:36:24.724758 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 15:36:24.727968 WARNING: region 6:
9534 15:36:24.730996 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9535 15:36:24.734861 WARNING: region 7:
9536 15:36:24.738032 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 15:36:24.744372 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9538 15:36:24.747818 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9539 15:36:24.750881 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9540 15:36:24.757555 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9541 15:36:24.761428 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9542 15:36:24.764455 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9543 15:36:24.771309 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9544 15:36:24.774318 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9545 15:36:24.781187 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9546 15:36:24.784092 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9547 15:36:24.787863 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9548 15:36:24.794380 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9549 15:36:24.797854 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9550 15:36:24.800899 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9551 15:36:24.807917 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9552 15:36:24.811494 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9553 15:36:24.817930 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9554 15:36:24.821263 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9555 15:36:24.824284 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9556 15:36:24.830929 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9557 15:36:24.834046 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9558 15:36:24.837431 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9559 15:36:24.844371 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9560 15:36:24.847586 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9561 15:36:24.854409 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9562 15:36:24.857454 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9563 15:36:24.860948 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9564 15:36:24.867894 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9565 15:36:24.871027 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9566 15:36:24.877926 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9567 15:36:24.881008 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9568 15:36:24.884139 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9569 15:36:24.890855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9570 15:36:24.894427 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9571 15:36:24.897655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9572 15:36:24.900723 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9573 15:36:24.907364 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9574 15:36:24.911046 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9575 15:36:24.914498 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9576 15:36:24.917694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9577 15:36:24.921037 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9578 15:36:24.927523 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9579 15:36:24.930682 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9580 15:36:24.934416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9581 15:36:24.940703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9582 15:36:24.944462 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9583 15:36:24.947634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9584 15:36:24.950834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9585 15:36:24.957398 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9586 15:36:24.961124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9587 15:36:24.967525 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9588 15:36:24.971251 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9589 15:36:24.974499 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9590 15:36:24.980646 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9591 15:36:24.984390 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9592 15:36:24.991112 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9593 15:36:24.994237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9594 15:36:25.000857 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9595 15:36:25.003891 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9596 15:36:25.007706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9597 15:36:25.014485 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9598 15:36:25.017544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9599 15:36:25.024134 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9600 15:36:25.027747 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9601 15:36:25.034388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9602 15:36:25.037410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9603 15:36:25.044202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9604 15:36:25.047478 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9605 15:36:25.050759 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9606 15:36:25.057738 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9607 15:36:25.061015 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9608 15:36:25.067996 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9609 15:36:25.070963 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9610 15:36:25.074618 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9611 15:36:25.080766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9612 15:36:25.084456 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9613 15:36:25.090951 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9614 15:36:25.094228 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9615 15:36:25.101008 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9616 15:36:25.104489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9617 15:36:25.111069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9618 15:36:25.114077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9619 15:36:25.117181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9620 15:36:25.124146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9621 15:36:25.127132 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9622 15:36:25.133831 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9623 15:36:25.137357 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9624 15:36:25.144049 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9625 15:36:25.147098 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9626 15:36:25.150968 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9627 15:36:25.157211 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9628 15:36:25.160569 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9629 15:36:25.167529 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9630 15:36:25.170583 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9631 15:36:25.177503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9632 15:36:25.180520 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9633 15:36:25.183958 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9634 15:36:25.190934 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9635 15:36:25.194121 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9636 15:36:25.197384 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9637 15:36:25.200619 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9638 15:36:25.207405 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9639 15:36:25.211067 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9640 15:36:25.217540 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9641 15:36:25.220697 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9642 15:36:25.223834 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9643 15:36:25.230643 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9644 15:36:25.233863 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9645 15:36:25.240514 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9646 15:36:25.244028 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9647 15:36:25.247033 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9648 15:36:25.254130 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9649 15:36:25.257191 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9650 15:36:25.264144 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9651 15:36:25.267338 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9652 15:36:25.270435 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9653 15:36:25.273584 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9654 15:36:25.280604 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9655 15:36:25.283873 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9656 15:36:25.287078 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9657 15:36:25.293854 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9658 15:36:25.297092 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9659 15:36:25.300577 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9660 15:36:25.303946 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9661 15:36:25.310376 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9662 15:36:25.314196 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9663 15:36:25.320426 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9664 15:36:25.323943 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9665 15:36:25.327033 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9666 15:36:25.334009 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9667 15:36:25.337300 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9668 15:36:25.343559 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9669 15:36:25.347627 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9670 15:36:25.350660 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9671 15:36:25.357392 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9672 15:36:25.360425 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9673 15:36:25.367408 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9674 15:36:25.370576 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9675 15:36:25.373799 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9676 15:36:25.380334 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9677 15:36:25.384123 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9678 15:36:25.387275 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9679 15:36:25.393632 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9680 15:36:25.396777 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9681 15:36:25.403496 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9682 15:36:25.407056 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9683 15:36:25.410293 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9684 15:36:25.416825 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9685 15:36:25.420572 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9686 15:36:25.427095 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9687 15:36:25.430246 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9688 15:36:25.433580 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9689 15:36:25.440728 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9690 15:36:25.443928 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9691 15:36:25.447096 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9692 15:36:25.453419 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9693 15:36:25.457213 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9694 15:36:25.463536 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9695 15:36:25.467197 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9696 15:36:25.470697 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9697 15:36:25.476911 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9698 15:36:25.480098 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9699 15:36:25.487115 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9700 15:36:25.490331 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9701 15:36:25.493602 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9702 15:36:25.500495 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9703 15:36:25.503767 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9704 15:36:25.509987 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9705 15:36:25.513705 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9706 15:36:25.516750 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9707 15:36:25.523269 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9708 15:36:25.526460 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9709 15:36:25.530063 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9710 15:36:25.536855 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9711 15:36:25.539790 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9712 15:36:25.546666 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9713 15:36:25.549896 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9714 15:36:25.553182 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9715 15:36:25.559914 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9716 15:36:25.563140 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9717 15:36:25.570212 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9718 15:36:25.573179 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9719 15:36:25.576244 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9720 15:36:25.583240 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9721 15:36:25.586128 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9722 15:36:25.592942 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9723 15:36:25.596153 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9724 15:36:25.600007 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9725 15:36:25.606526 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9726 15:36:25.609650 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9727 15:36:25.615808 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9728 15:36:25.619509 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9729 15:36:25.625769 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9730 15:36:25.629376 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9731 15:36:25.632155 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9732 15:36:25.639133 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9733 15:36:25.642170 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9734 15:36:25.649262 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9735 15:36:25.652526 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9736 15:36:25.659302 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9737 15:36:25.662585 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9738 15:36:25.665639 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9739 15:36:25.672169 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9740 15:36:25.675308 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9741 15:36:25.682084 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9742 15:36:25.685288 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9743 15:36:25.688672 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9744 15:36:25.695615 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9745 15:36:25.698620 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9746 15:36:25.705747 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9747 15:36:25.708902 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9748 15:36:25.715403 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9749 15:36:25.718330 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9750 15:36:25.721773 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9751 15:36:25.728099 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9752 15:36:25.731381 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9753 15:36:25.738230 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9754 15:36:25.741588 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9755 15:36:25.748666 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9756 15:36:25.751392 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9757 15:36:25.754904 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9758 15:36:25.761242 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9759 15:36:25.764423 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9760 15:36:25.771490 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9761 15:36:25.774645 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9762 15:36:25.781324 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9763 15:36:25.784478 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9764 15:36:25.787563 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9765 15:36:25.794715 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9766 15:36:25.797882 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9767 15:36:25.801308 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9768 15:36:25.804624 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9769 15:36:25.811434 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9770 15:36:25.814632 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9771 15:36:25.817759 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9772 15:36:25.824533 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9773 15:36:25.827635 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9774 15:36:25.830674 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9775 15:36:25.837643 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9776 15:36:25.840916 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9777 15:36:25.847731 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9778 15:36:25.850913 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9779 15:36:25.854032 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9780 15:36:25.860207 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9781 15:36:25.863702 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9782 15:36:25.867193 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9783 15:36:25.873577 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9784 15:36:25.877090 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9785 15:36:25.880279 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9786 15:36:25.887067 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9787 15:36:25.890058 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9788 15:36:25.896937 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9789 15:36:25.900109 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9790 15:36:25.903185 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9791 15:36:25.909985 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9792 15:36:25.913559 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9793 15:36:25.919893 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9794 15:36:25.923129 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9795 15:36:25.926949 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9796 15:36:25.933240 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9797 15:36:25.936651 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9798 15:36:25.939755 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9799 15:36:25.946664 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9800 15:36:25.950111 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9801 15:36:25.953102 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9802 15:36:25.960067 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9803 15:36:25.963173 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9804 15:36:25.970009 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9805 15:36:25.973202 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9806 15:36:25.976303 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9807 15:36:25.979749 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9808 15:36:25.983023 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9809 15:36:25.989370 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9810 15:36:25.992955 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9811 15:36:25.996126 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9812 15:36:26.003097 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9813 15:36:26.005727 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9814 15:36:26.009641 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9815 15:36:26.012931 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9816 15:36:26.019164 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9817 15:36:26.022544 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9818 15:36:26.025533 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9819 15:36:26.032277 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9820 15:36:26.036111 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9821 15:36:26.039155 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9822 15:36:26.045572 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9823 15:36:26.048851 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9824 15:36:26.055807 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9825 15:36:26.058946 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9826 15:36:26.062075 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9827 15:36:26.068686 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9828 15:36:26.072442 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9829 15:36:26.078790 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9830 15:36:26.081845 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9831 15:36:26.088572 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9832 15:36:26.092466 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9833 15:36:26.095395 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9834 15:36:26.101955 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9835 15:36:26.105359 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9836 15:36:26.112093 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9837 15:36:26.115263 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9838 15:36:26.121732 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9839 15:36:26.124974 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9840 15:36:26.128775 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9841 15:36:26.134878 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9842 15:36:26.138420 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9843 15:36:26.144966 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9844 15:36:26.147906 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9845 15:36:26.151196 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9846 15:36:26.157594 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9847 15:36:26.161437 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9848 15:36:26.167532 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9849 15:36:26.171352 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9850 15:36:26.174423 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9851 15:36:26.180723 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9852 15:36:26.183916 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9853 15:36:26.190904 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9854 15:36:26.194501 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9855 15:36:26.200856 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9856 15:36:26.203815 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9857 15:36:26.207651 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9858 15:36:26.214110 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9859 15:36:26.217647 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9860 15:36:26.224157 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9861 15:36:26.227457 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9862 15:36:26.234183 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9863 15:36:26.237088 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9864 15:36:26.240170 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9865 15:36:26.247237 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9866 15:36:26.250102 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9867 15:36:26.256954 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9868 15:36:26.260207 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9869 15:36:26.263424 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9870 15:36:26.270029 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9871 15:36:26.273643 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9872 15:36:26.280479 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9873 15:36:26.283593 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9874 15:36:26.286833 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9875 15:36:26.293372 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9876 15:36:26.297058 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9877 15:36:26.303282 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9878 15:36:26.306409 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9879 15:36:26.313423 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9880 15:36:26.316424 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9881 15:36:26.319989 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9882 15:36:26.326534 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9883 15:36:26.329958 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9884 15:36:26.336958 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9885 15:36:26.339836 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9886 15:36:26.343485 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9887 15:36:26.350047 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9888 15:36:26.353107 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9889 15:36:26.359613 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9890 15:36:26.362666 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9891 15:36:26.366274 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9892 15:36:26.372894 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9893 15:36:26.375961 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9894 15:36:26.382531 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9895 15:36:26.386182 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9896 15:36:26.392970 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9897 15:36:26.396204 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9898 15:36:26.399272 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9899 15:36:26.406002 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9900 15:36:26.409719 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9901 15:36:26.416091 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9902 15:36:26.419237 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9903 15:36:26.425921 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9904 15:36:26.429301 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9905 15:36:26.435837 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9906 15:36:26.439472 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9907 15:36:26.442367 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9908 15:36:26.449110 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9909 15:36:26.452724 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9910 15:36:26.459442 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9911 15:36:26.462538 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9912 15:36:26.469107 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9913 15:36:26.472130 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9914 15:36:26.475357 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9915 15:36:26.482267 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9916 15:36:26.485452 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9917 15:36:26.492266 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9918 15:36:26.495473 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9919 15:36:26.502229 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9920 15:36:26.505471 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9921 15:36:26.512415 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9922 15:36:26.515556 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9923 15:36:26.518696 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9924 15:36:26.525137 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9925 15:36:26.528755 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9926 15:36:26.535541 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9927 15:36:26.538833 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9928 15:36:26.545373 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9929 15:36:26.548810 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9930 15:36:26.551755 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9931 15:36:26.558598 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9932 15:36:26.561738 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9933 15:36:26.568799 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9934 15:36:26.571814 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9935 15:36:26.578639 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9936 15:36:26.581975 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9937 15:36:26.588509 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9938 15:36:26.591806 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9939 15:36:26.594948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9940 15:36:26.601666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9941 15:36:26.605254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9942 15:36:26.611290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9943 15:36:26.615095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9944 15:36:26.621543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9945 15:36:26.624853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9946 15:36:26.631665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9947 15:36:26.635220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9948 15:36:26.638160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9949 15:36:26.644952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9950 15:36:26.648171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9951 15:36:26.655032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9952 15:36:26.658536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9953 15:36:26.665071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9954 15:36:26.668011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9955 15:36:26.674972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9956 15:36:26.677883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9957 15:36:26.684456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9958 15:36:26.688099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9959 15:36:26.695038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9960 15:36:26.698103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9961 15:36:26.704426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9962 15:36:26.708058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9963 15:36:26.714462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9964 15:36:26.717662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9965 15:36:26.724648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9966 15:36:26.728015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9967 15:36:26.734263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9968 15:36:26.738093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9969 15:36:26.744779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9970 15:36:26.747810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9971 15:36:26.754407 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9972 15:36:26.754513 INFO: [APUAPC] vio 0
9973 15:36:26.761438 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9974 15:36:26.764454 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9975 15:36:26.767347 INFO: [APUAPC] D0_APC_0: 0x400510
9976 15:36:26.770762 INFO: [APUAPC] D0_APC_1: 0x0
9977 15:36:26.774020 INFO: [APUAPC] D0_APC_2: 0x1540
9978 15:36:26.777609 INFO: [APUAPC] D0_APC_3: 0x0
9979 15:36:26.780602 INFO: [APUAPC] D1_APC_0: 0xffffffff
9980 15:36:26.784265 INFO: [APUAPC] D1_APC_1: 0xffffffff
9981 15:36:26.787661 INFO: [APUAPC] D1_APC_2: 0x3fffff
9982 15:36:26.790554 INFO: [APUAPC] D1_APC_3: 0x0
9983 15:36:26.793987 INFO: [APUAPC] D2_APC_0: 0xffffffff
9984 15:36:26.797138 INFO: [APUAPC] D2_APC_1: 0xffffffff
9985 15:36:26.800729 INFO: [APUAPC] D2_APC_2: 0x3fffff
9986 15:36:26.804183 INFO: [APUAPC] D2_APC_3: 0x0
9987 15:36:26.807491 INFO: [APUAPC] D3_APC_0: 0xffffffff
9988 15:36:26.810558 INFO: [APUAPC] D3_APC_1: 0xffffffff
9989 15:36:26.813688 INFO: [APUAPC] D3_APC_2: 0x3fffff
9990 15:36:26.817408 INFO: [APUAPC] D3_APC_3: 0x0
9991 15:36:26.820286 INFO: [APUAPC] D4_APC_0: 0xffffffff
9992 15:36:26.823914 INFO: [APUAPC] D4_APC_1: 0xffffffff
9993 15:36:26.827042 INFO: [APUAPC] D4_APC_2: 0x3fffff
9994 15:36:26.830207 INFO: [APUAPC] D4_APC_3: 0x0
9995 15:36:26.833416 INFO: [APUAPC] D5_APC_0: 0xffffffff
9996 15:36:26.837247 INFO: [APUAPC] D5_APC_1: 0xffffffff
9997 15:36:26.840376 INFO: [APUAPC] D5_APC_2: 0x3fffff
9998 15:36:26.840479 INFO: [APUAPC] D5_APC_3: 0x0
9999 15:36:26.846968 INFO: [APUAPC] D6_APC_0: 0xffffffff
10000 15:36:26.850011 INFO: [APUAPC] D6_APC_1: 0xffffffff
10001 15:36:26.853251 INFO: [APUAPC] D6_APC_2: 0x3fffff
10002 15:36:26.853354 INFO: [APUAPC] D6_APC_3: 0x0
10003 15:36:26.857160 INFO: [APUAPC] D7_APC_0: 0xffffffff
10004 15:36:26.860142 INFO: [APUAPC] D7_APC_1: 0xffffffff
10005 15:36:26.863437 INFO: [APUAPC] D7_APC_2: 0x3fffff
10006 15:36:26.867166 INFO: [APUAPC] D7_APC_3: 0x0
10007 15:36:26.870309 INFO: [APUAPC] D8_APC_0: 0xffffffff
10008 15:36:26.873303 INFO: [APUAPC] D8_APC_1: 0xffffffff
10009 15:36:26.876838 INFO: [APUAPC] D8_APC_2: 0x3fffff
10010 15:36:26.880400 INFO: [APUAPC] D8_APC_3: 0x0
10011 15:36:26.883473 INFO: [APUAPC] D9_APC_0: 0xffffffff
10012 15:36:26.886589 INFO: [APUAPC] D9_APC_1: 0xffffffff
10013 15:36:26.889629 INFO: [APUAPC] D9_APC_2: 0x3fffff
10014 15:36:26.893373 INFO: [APUAPC] D9_APC_3: 0x0
10015 15:36:26.896430 INFO: [APUAPC] D10_APC_0: 0xffffffff
10016 15:36:26.899943 INFO: [APUAPC] D10_APC_1: 0xffffffff
10017 15:36:26.902907 INFO: [APUAPC] D10_APC_2: 0x3fffff
10018 15:36:26.906666 INFO: [APUAPC] D10_APC_3: 0x0
10019 15:36:26.909997 INFO: [APUAPC] D11_APC_0: 0xffffffff
10020 15:36:26.913182 INFO: [APUAPC] D11_APC_1: 0xffffffff
10021 15:36:26.916414 INFO: [APUAPC] D11_APC_2: 0x3fffff
10022 15:36:26.919648 INFO: [APUAPC] D11_APC_3: 0x0
10023 15:36:26.923232 INFO: [APUAPC] D12_APC_0: 0xffffffff
10024 15:36:26.926254 INFO: [APUAPC] D12_APC_1: 0xffffffff
10025 15:36:26.929755 INFO: [APUAPC] D12_APC_2: 0x3fffff
10026 15:36:26.933460 INFO: [APUAPC] D12_APC_3: 0x0
10027 15:36:26.936011 INFO: [APUAPC] D13_APC_0: 0xffffffff
10028 15:36:26.939806 INFO: [APUAPC] D13_APC_1: 0xffffffff
10029 15:36:26.942832 INFO: [APUAPC] D13_APC_2: 0x3fffff
10030 15:36:26.946700 INFO: [APUAPC] D13_APC_3: 0x0
10031 15:36:26.949691 INFO: [APUAPC] D14_APC_0: 0xffffffff
10032 15:36:26.952742 INFO: [APUAPC] D14_APC_1: 0xffffffff
10033 15:36:26.956016 INFO: [APUAPC] D14_APC_2: 0x3fffff
10034 15:36:26.959922 INFO: [APUAPC] D14_APC_3: 0x0
10035 15:36:26.963007 INFO: [APUAPC] D15_APC_0: 0xffffffff
10036 15:36:26.966293 INFO: [APUAPC] D15_APC_1: 0xffffffff
10037 15:36:26.969556 INFO: [APUAPC] D15_APC_2: 0x3fffff
10038 15:36:26.972830 INFO: [APUAPC] D15_APC_3: 0x0
10039 15:36:26.975934 INFO: [APUAPC] APC_CON: 0x4
10040 15:36:26.979706 INFO: [NOCDAPC] D0_APC_0: 0x0
10041 15:36:26.982644 INFO: [NOCDAPC] D0_APC_1: 0x0
10042 15:36:26.986256 INFO: [NOCDAPC] D1_APC_0: 0x0
10043 15:36:26.989215 INFO: [NOCDAPC] D1_APC_1: 0xfff
10044 15:36:26.992789 INFO: [NOCDAPC] D2_APC_0: 0x0
10045 15:36:26.995896 INFO: [NOCDAPC] D2_APC_1: 0xfff
10046 15:36:26.996000 INFO: [NOCDAPC] D3_APC_0: 0x0
10047 15:36:26.999356 INFO: [NOCDAPC] D3_APC_1: 0xfff
10048 15:36:27.002880 INFO: [NOCDAPC] D4_APC_0: 0x0
10049 15:36:27.006024 INFO: [NOCDAPC] D4_APC_1: 0xfff
10050 15:36:27.009397 INFO: [NOCDAPC] D5_APC_0: 0x0
10051 15:36:27.013001 INFO: [NOCDAPC] D5_APC_1: 0xfff
10052 15:36:27.015963 INFO: [NOCDAPC] D6_APC_0: 0x0
10053 15:36:27.019657 INFO: [NOCDAPC] D6_APC_1: 0xfff
10054 15:36:27.022677 INFO: [NOCDAPC] D7_APC_0: 0x0
10055 15:36:27.025859 INFO: [NOCDAPC] D7_APC_1: 0xfff
10056 15:36:27.029083 INFO: [NOCDAPC] D8_APC_0: 0x0
10057 15:36:27.032288 INFO: [NOCDAPC] D8_APC_1: 0xfff
10058 15:36:27.032415 INFO: [NOCDAPC] D9_APC_0: 0x0
10059 15:36:27.036051 INFO: [NOCDAPC] D9_APC_1: 0xfff
10060 15:36:27.039463 INFO: [NOCDAPC] D10_APC_0: 0x0
10061 15:36:27.042430 INFO: [NOCDAPC] D10_APC_1: 0xfff
10062 15:36:27.045733 INFO: [NOCDAPC] D11_APC_0: 0x0
10063 15:36:27.049001 INFO: [NOCDAPC] D11_APC_1: 0xfff
10064 15:36:27.052089 INFO: [NOCDAPC] D12_APC_0: 0x0
10065 15:36:27.055704 INFO: [NOCDAPC] D12_APC_1: 0xfff
10066 15:36:27.058901 INFO: [NOCDAPC] D13_APC_0: 0x0
10067 15:36:27.062613 INFO: [NOCDAPC] D13_APC_1: 0xfff
10068 15:36:27.066042 INFO: [NOCDAPC] D14_APC_0: 0x0
10069 15:36:27.069114 INFO: [NOCDAPC] D14_APC_1: 0xfff
10070 15:36:27.072230 INFO: [NOCDAPC] D15_APC_0: 0x0
10071 15:36:27.075508 INFO: [NOCDAPC] D15_APC_1: 0xfff
10072 15:36:27.075609 INFO: [NOCDAPC] APC_CON: 0x4
10073 15:36:27.078505 INFO: [APUAPC] set_apusys_apc done
10074 15:36:27.082248 INFO: [DEVAPC] devapc_init done
10075 15:36:27.088487 INFO: GICv3 without legacy support detected.
10076 15:36:27.092160 INFO: ARM GICv3 driver initialized in EL3
10077 15:36:27.095398 INFO: Maximum SPI INTID supported: 639
10078 15:36:27.098971 INFO: BL31: Initializing runtime services
10079 15:36:27.105257 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10080 15:36:27.108838 INFO: SPM: enable CPC mode
10081 15:36:27.111816 INFO: mcdi ready for mcusys-off-idle and system suspend
10082 15:36:27.118893 INFO: BL31: Preparing for EL3 exit to normal world
10083 15:36:27.121844 INFO: Entry point address = 0x80000000
10084 15:36:27.121944 INFO: SPSR = 0x8
10085 15:36:27.128879
10086 15:36:27.128963
10087 15:36:27.129030
10088 15:36:27.132540 Starting depthcharge on Spherion...
10089 15:36:27.132625
10090 15:36:27.132692 Wipe memory regions:
10091 15:36:27.132754
10092 15:36:27.133455 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10093 15:36:27.133566 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10094 15:36:27.133918 Setting prompt string to ['asurada:']
10095 15:36:27.134004 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10096 15:36:27.135623 [0x00000040000000, 0x00000054600000)
10097 15:36:27.258135
10098 15:36:27.258276 [0x00000054660000, 0x00000080000000)
10099 15:36:27.518399
10100 15:36:27.518548 [0x000000821a7280, 0x000000ffe64000)
10101 15:36:28.263493
10102 15:36:28.263643 [0x00000100000000, 0x00000240000000)
10103 15:36:30.153486
10104 15:36:30.156586 Initializing XHCI USB controller at 0x11200000.
10105 15:36:31.196171
10106 15:36:31.199331 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10107 15:36:31.199455
10108 15:36:31.199525
10109 15:36:31.199589
10110 15:36:31.199872 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10112 15:36:31.300226 asurada: tftpboot 192.168.201.1 11331379/tftp-deploy-3e8hmdz8/kernel/image.itb 11331379/tftp-deploy-3e8hmdz8/kernel/cmdline
10113 15:36:31.300373 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10114 15:36:31.300486 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10115 15:36:31.304738 tftpboot 192.168.201.1 11331379/tftp-deploy-3e8hmdz8/kernel/image.ittp-deploy-3e8hmdz8/kernel/cmdline
10116 15:36:31.304829
10117 15:36:31.304895 Waiting for link
10118 15:36:31.463467
10119 15:36:31.463607 R8152: Initializing
10120 15:36:31.463675
10121 15:36:31.466539 Version 6 (ocp_data = 5c30)
10122 15:36:31.466623
10123 15:36:31.469780 R8152: Done initializing
10124 15:36:31.469862
10125 15:36:31.469928 Adding net device
10126 15:36:33.375592
10127 15:36:33.375733 done.
10128 15:36:33.375801
10129 15:36:33.375862 MAC: 00:24:32:30:78:ff
10130 15:36:33.375922
10131 15:36:33.378684 Sending DHCP discover... done.
10132 15:36:33.378769
10133 15:36:33.381768 Waiting for reply... done.
10134 15:36:33.381851
10135 15:36:33.385533 Sending DHCP request... done.
10136 15:36:33.385641
10137 15:36:33.390567 Waiting for reply... done.
10138 15:36:33.390649
10139 15:36:33.390713 My ip is 192.168.201.21
10140 15:36:33.390774
10141 15:36:33.393742 The DHCP server ip is 192.168.201.1
10142 15:36:33.393825
10143 15:36:33.400645 TFTP server IP predefined by user: 192.168.201.1
10144 15:36:33.400729
10145 15:36:33.407491 Bootfile predefined by user: 11331379/tftp-deploy-3e8hmdz8/kernel/image.itb
10146 15:36:33.407575
10147 15:36:33.410482 Sending tftp read request... done.
10148 15:36:33.410588
10149 15:36:33.414033 Waiting for the transfer...
10150 15:36:33.414109
10151 15:36:33.973241 00000000 ################################################################
10152 15:36:33.973380
10153 15:36:34.542364 00080000 ################################################################
10154 15:36:34.542524
10155 15:36:35.100137 00100000 ################################################################
10156 15:36:35.100273
10157 15:36:35.638119 00180000 ################################################################
10158 15:36:35.638278
10159 15:36:36.173244 00200000 ################################################################
10160 15:36:36.173415
10161 15:36:36.699192 00280000 ################################################################
10162 15:36:36.699329
10163 15:36:37.238769 00300000 ################################################################
10164 15:36:37.238917
10165 15:36:37.789947 00380000 ################################################################
10166 15:36:37.790096
10167 15:36:38.349509 00400000 ################################################################
10168 15:36:38.349692
10169 15:36:38.908038 00480000 ################################################################
10170 15:36:38.908176
10171 15:36:39.471697 00500000 ################################################################
10172 15:36:39.471861
10173 15:36:40.009537 00580000 ################################################################
10174 15:36:40.009696
10175 15:36:40.548592 00600000 ################################################################
10176 15:36:40.548764
10177 15:36:41.088747 00680000 ################################################################
10178 15:36:41.088887
10179 15:36:41.627618 00700000 ################################################################
10180 15:36:41.627801
10181 15:36:42.158719 00780000 ################################################################
10182 15:36:42.158865
10183 15:36:42.697925 00800000 ################################################################
10184 15:36:42.698071
10185 15:36:43.232170 00880000 ################################################################
10186 15:36:43.232316
10187 15:36:43.799465 00900000 ################################################################
10188 15:36:43.799600
10189 15:36:44.345494 00980000 ################################################################
10190 15:36:44.345628
10191 15:36:44.899766 00a00000 ################################################################
10192 15:36:44.899916
10193 15:36:45.468325 00a80000 ################################################################
10194 15:36:45.468461
10195 15:36:46.050702 00b00000 ################################################################
10196 15:36:46.050843
10197 15:36:46.646554 00b80000 ################################################################
10198 15:36:46.646691
10199 15:36:47.218960 00c00000 ################################################################
10200 15:36:47.219099
10201 15:36:47.803488 00c80000 ################################################################
10202 15:36:47.803623
10203 15:36:48.350151 00d00000 ################################################################
10204 15:36:48.350284
10205 15:36:48.910351 00d80000 ################################################################
10206 15:36:48.910483
10207 15:36:49.494859 00e00000 ################################################################
10208 15:36:49.494995
10209 15:36:50.089221 00e80000 ################################################################
10210 15:36:50.089370
10211 15:36:50.681612 00f00000 ################################################################
10212 15:36:50.681768
10213 15:36:51.281435 00f80000 ################################################################
10214 15:36:51.281588
10215 15:36:51.878632 01000000 ################################################################
10216 15:36:51.878782
10217 15:36:52.473856 01080000 ################################################################
10218 15:36:52.474012
10219 15:36:53.064317 01100000 ################################################################
10220 15:36:53.064452
10221 15:36:53.645056 01180000 ################################################################
10222 15:36:53.645201
10223 15:36:54.224846 01200000 ################################################################
10224 15:36:54.224997
10225 15:36:54.796999 01280000 ################################################################
10226 15:36:54.797152
10227 15:36:55.371648 01300000 ################################################################
10228 15:36:55.371802
10229 15:36:55.924903 01380000 ################################################################
10230 15:36:55.925036
10231 15:36:56.473380 01400000 ################################################################
10232 15:36:56.473516
10233 15:36:57.054514 01480000 ################################################################
10234 15:36:57.054740
10235 15:36:57.770902 01500000 ################################################################
10236 15:36:57.771548
10237 15:36:58.480044 01580000 ################################################################
10238 15:36:58.480554
10239 15:36:59.180542 01600000 ################################################################
10240 15:36:59.181063
10241 15:36:59.877149 01680000 ################################################################
10242 15:36:59.877663
10243 15:37:00.602751 01700000 ################################################################
10244 15:37:00.603286
10245 15:37:01.355658 01780000 ################################################################
10246 15:37:01.356188
10247 15:37:02.100720 01800000 ################################################################
10248 15:37:02.101254
10249 15:37:02.837611 01880000 ################################################################
10250 15:37:02.838166
10251 15:37:03.565129 01900000 ################################################################
10252 15:37:03.565661
10253 15:37:04.272656 01980000 ################################################################
10254 15:37:04.273185
10255 15:37:05.013587 01a00000 ################################################################
10256 15:37:05.014120
10257 15:37:05.747015 01a80000 ################################################################
10258 15:37:05.747701
10259 15:37:06.471145 01b00000 ################################################################
10260 15:37:06.471914
10261 15:37:06.499766 01b80000 ### done.
10262 15:37:06.500276
10263 15:37:06.503214 The bootfile was 28855334 bytes long.
10264 15:37:06.503664
10265 15:37:06.506281 Sending tftp read request... done.
10266 15:37:06.506694
10267 15:37:06.510089 Waiting for the transfer...
10268 15:37:06.510512
10269 15:37:06.510841 00000000 # done.
10270 15:37:06.511158
10271 15:37:06.516800 Command line loaded dynamically from TFTP file: 11331379/tftp-deploy-3e8hmdz8/kernel/cmdline
10272 15:37:06.517222
10273 15:37:06.540293 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11331379/extract-nfsrootfs-uhp87pcj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10274 15:37:06.540820
10275 15:37:06.541157 Loading FIT.
10276 15:37:06.541465
10277 15:37:06.543513 Image ramdisk-1 has 17770678 bytes.
10278 15:37:06.543928
10279 15:37:06.547342 Image fdt-1 has 47278 bytes.
10280 15:37:06.547902
10281 15:37:06.550213 Image kernel-1 has 11035343 bytes.
10282 15:37:06.550728
10283 15:37:06.560285 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10284 15:37:06.560808
10285 15:37:06.577142 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10286 15:37:06.577678
10287 15:37:06.583562 Choosing best match conf-1 for compat google,spherion-rev2.
10288 15:37:06.584084
10289 15:37:06.591219 Connected to device vid:did:rid of 1ae0:0028:00
10290 15:37:06.599042
10291 15:37:06.602425 tpm_get_response: command 0x17b, return code 0x0
10292 15:37:06.602895
10293 15:37:06.605865 ec_init: CrosEC protocol v3 supported (256, 248)
10294 15:37:06.609749
10295 15:37:06.613044 tpm_cleanup: add release locality here.
10296 15:37:06.613461
10297 15:37:06.613837 Shutting down all USB controllers.
10298 15:37:06.616821
10299 15:37:06.617232 Removing current net device
10300 15:37:06.617621
10301 15:37:06.623283 Exiting depthcharge with code 4 at timestamp: 68802881
10302 15:37:06.623738
10303 15:37:06.626801 LZMA decompressing kernel-1 to 0x821a6718
10304 15:37:06.627215
10305 15:37:06.630077 LZMA decompressing kernel-1 to 0x40000000
10306 15:37:08.016112
10307 15:37:08.016603 jumping to kernel
10308 15:37:08.017930 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10309 15:37:08.018411 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10310 15:37:08.018783 Setting prompt string to ['Linux version [0-9]']
10311 15:37:08.019120 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10312 15:37:08.019521 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10313 15:37:08.097827
10314 15:37:08.101145 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10315 15:37:08.104641 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10316 15:37:08.105102 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10317 15:37:08.105464 Setting prompt string to []
10318 15:37:08.105841 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10319 15:37:08.106203 Using line separator: #'\n'#
10320 15:37:08.106502 No login prompt set.
10321 15:37:08.106801 Parsing kernel messages
10322 15:37:08.107077 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10323 15:37:08.107825 [login-action] Waiting for messages, (timeout 00:03:44)
10324 15:37:08.124182 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j17681-arm64-gcc-10-defconfig-arm64-chromebook-c49jr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Aug 22 15:20:14 UTC 2023
10325 15:37:08.127706 [ 0.000000] random: crng init done
10326 15:37:08.134233 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10327 15:37:08.137629 [ 0.000000] efi: UEFI not found.
10328 15:37:08.143750 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10329 15:37:08.150947 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10330 15:37:08.160832 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10331 15:37:08.171120 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10332 15:37:08.177555 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10333 15:37:08.183839 [ 0.000000] printk: bootconsole [mtk8250] enabled
10334 15:37:08.190439 [ 0.000000] NUMA: No NUMA configuration found
10335 15:37:08.197339 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10336 15:37:08.200415 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10337 15:37:08.203664 [ 0.000000] Zone ranges:
10338 15:37:08.210331 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10339 15:37:08.213396 [ 0.000000] DMA32 empty
10340 15:37:08.220156 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10341 15:37:08.223697 [ 0.000000] Movable zone start for each node
10342 15:37:08.226719 [ 0.000000] Early memory node ranges
10343 15:37:08.233817 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10344 15:37:08.240309 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10345 15:37:08.246837 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10346 15:37:08.253463 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10347 15:37:08.256730 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10348 15:37:08.266969 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10349 15:37:08.322204 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10350 15:37:08.328796 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10351 15:37:08.335740 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10352 15:37:08.338823 [ 0.000000] psci: probing for conduit method from DT.
10353 15:37:08.345420 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10354 15:37:08.349090 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10355 15:37:08.355575 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10356 15:37:08.358551 [ 0.000000] psci: SMC Calling Convention v1.2
10357 15:37:08.365444 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10358 15:37:08.368933 [ 0.000000] Detected VIPT I-cache on CPU0
10359 15:37:08.375221 [ 0.000000] CPU features: detected: GIC system register CPU interface
10360 15:37:08.381936 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10361 15:37:08.388095 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10362 15:37:08.395051 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10363 15:37:08.405086 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10364 15:37:08.411540 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10365 15:37:08.414695 [ 0.000000] alternatives: applying boot alternatives
10366 15:37:08.421603 [ 0.000000] Fallback order for Node 0: 0
10367 15:37:08.428360 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10368 15:37:08.431238 [ 0.000000] Policy zone: Normal
10369 15:37:08.454477 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11331379/extract-nfsrootfs-uhp87pcj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10370 15:37:08.464421 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10371 15:37:08.474174 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10372 15:37:08.483685 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10373 15:37:08.490911 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10374 15:37:08.494254 <6>[ 0.000000] software IO TLB: area num 8.
10375 15:37:08.550645 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10376 15:37:08.700022 <6>[ 0.000000] Memory: 7952200K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 400568K reserved, 32768K cma-reserved)
10377 15:37:08.706412 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10378 15:37:08.712886 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10379 15:37:08.716221 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10380 15:37:08.723007 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10381 15:37:08.729471 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10382 15:37:08.732669 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10383 15:37:08.743360 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10384 15:37:08.749864 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10385 15:37:08.756017 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10386 15:37:08.762437 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10387 15:37:08.766189 <6>[ 0.000000] GICv3: 608 SPIs implemented
10388 15:37:08.769384 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10389 15:37:08.775738 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10390 15:37:08.779491 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10391 15:37:08.786034 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10392 15:37:08.799281 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10393 15:37:08.812179 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10394 15:37:08.819551 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10395 15:37:08.826776 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10396 15:37:08.839845 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10397 15:37:08.846393 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10398 15:37:08.853535 <6>[ 0.009182] Console: colour dummy device 80x25
10399 15:37:08.863397 <6>[ 0.013937] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10400 15:37:08.869722 <6>[ 0.024379] pid_max: default: 32768 minimum: 301
10401 15:37:08.872986 <6>[ 0.029251] LSM: Security Framework initializing
10402 15:37:08.879648 <6>[ 0.034189] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 15:37:08.889549 <6>[ 0.042002] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10404 15:37:08.896525 <6>[ 0.051442] cblist_init_generic: Setting adjustable number of callback queues.
10405 15:37:08.902917 <6>[ 0.058934] cblist_init_generic: Setting shift to 3 and lim to 1.
10406 15:37:08.913298 <6>[ 0.065272] cblist_init_generic: Setting adjustable number of callback queues.
10407 15:37:08.919263 <6>[ 0.072744] cblist_init_generic: Setting shift to 3 and lim to 1.
10408 15:37:08.922566 <6>[ 0.079144] rcu: Hierarchical SRCU implementation.
10409 15:37:08.929043 <6>[ 0.084158] rcu: Max phase no-delay instances is 1000.
10410 15:37:08.935659 <6>[ 0.091188] EFI services will not be available.
10411 15:37:08.938781 <6>[ 0.096167] smp: Bringing up secondary CPUs ...
10412 15:37:08.947539 <6>[ 0.101252] Detected VIPT I-cache on CPU1
10413 15:37:08.954233 <6>[ 0.101320] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10414 15:37:08.960731 <6>[ 0.101352] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10415 15:37:08.963651 <6>[ 0.101684] Detected VIPT I-cache on CPU2
10416 15:37:08.970914 <6>[ 0.101734] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10417 15:37:08.980297 <6>[ 0.101749] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10418 15:37:08.983505 <6>[ 0.102012] Detected VIPT I-cache on CPU3
10419 15:37:08.990359 <6>[ 0.102057] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10420 15:37:08.996978 <6>[ 0.102071] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10421 15:37:09.000545 <6>[ 0.102376] CPU features: detected: Spectre-v4
10422 15:37:09.006814 <6>[ 0.102382] CPU features: detected: Spectre-BHB
10423 15:37:09.010420 <6>[ 0.102387] Detected PIPT I-cache on CPU4
10424 15:37:09.016791 <6>[ 0.102444] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10425 15:37:09.023275 <6>[ 0.102461] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10426 15:37:09.030218 <6>[ 0.102750] Detected PIPT I-cache on CPU5
10427 15:37:09.036988 <6>[ 0.102811] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10428 15:37:09.043017 <6>[ 0.102829] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10429 15:37:09.046419 <6>[ 0.103112] Detected PIPT I-cache on CPU6
10430 15:37:09.053839 <6>[ 0.103176] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10431 15:37:09.059850 <6>[ 0.103193] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10432 15:37:09.066784 <6>[ 0.103492] Detected PIPT I-cache on CPU7
10433 15:37:09.072743 <6>[ 0.103556] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10434 15:37:09.079718 <6>[ 0.103573] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10435 15:37:09.083082 <6>[ 0.103620] smp: Brought up 1 node, 8 CPUs
10436 15:37:09.089270 <6>[ 0.244874] SMP: Total of 8 processors activated.
10437 15:37:09.092832 <6>[ 0.249795] CPU features: detected: 32-bit EL0 Support
10438 15:37:09.102585 <6>[ 0.255158] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10439 15:37:09.109797 <6>[ 0.264014] CPU features: detected: Common not Private translations
10440 15:37:09.115986 <6>[ 0.270489] CPU features: detected: CRC32 instructions
10441 15:37:09.119140 <6>[ 0.275841] CPU features: detected: RCpc load-acquire (LDAPR)
10442 15:37:09.126073 <6>[ 0.281838] CPU features: detected: LSE atomic instructions
10443 15:37:09.132336 <6>[ 0.287655] CPU features: detected: Privileged Access Never
10444 15:37:09.138879 <6>[ 0.293471] CPU features: detected: RAS Extension Support
10445 15:37:09.145918 <6>[ 0.299080] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10446 15:37:09.148709 <6>[ 0.306299] CPU: All CPU(s) started at EL2
10447 15:37:09.155434 <6>[ 0.310616] alternatives: applying system-wide alternatives
10448 15:37:09.165799 <6>[ 0.321316] devtmpfs: initialized
10449 15:37:09.177119 <6>[ 0.330168] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10450 15:37:09.187804 <6>[ 0.340128] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10451 15:37:09.194059 <6>[ 0.348276] pinctrl core: initialized pinctrl subsystem
10452 15:37:09.197121 <6>[ 0.354938] DMI not present or invalid.
10453 15:37:09.203791 <6>[ 0.359340] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10454 15:37:09.213797 <6>[ 0.366208] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10455 15:37:09.220138 <6>[ 0.373792] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10456 15:37:09.229819 <6>[ 0.382012] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10457 15:37:09.233190 <6>[ 0.390255] audit: initializing netlink subsys (disabled)
10458 15:37:09.243067 <5>[ 0.395937] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10459 15:37:09.249842 <6>[ 0.396606] thermal_sys: Registered thermal governor 'step_wise'
10460 15:37:09.256423 <6>[ 0.403905] thermal_sys: Registered thermal governor 'power_allocator'
10461 15:37:09.259839 <6>[ 0.410159] cpuidle: using governor menu
10462 15:37:09.266083 <6>[ 0.421116] NET: Registered PF_QIPCRTR protocol family
10463 15:37:09.272938 <6>[ 0.426610] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10464 15:37:09.279560 <6>[ 0.433715] ASID allocator initialised with 32768 entries
10465 15:37:09.282752 <6>[ 0.440276] Serial: AMBA PL011 UART driver
10466 15:37:09.292314 <4>[ 0.449055] Trying to register duplicate clock ID: 134
10467 15:37:09.346946 <6>[ 0.506218] KASLR enabled
10468 15:37:09.361132 <6>[ 0.513818] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10469 15:37:09.367564 <6>[ 0.520831] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10470 15:37:09.374061 <6>[ 0.527320] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10471 15:37:09.380881 <6>[ 0.534324] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10472 15:37:09.387978 <6>[ 0.540811] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10473 15:37:09.393810 <6>[ 0.547816] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10474 15:37:09.400654 <6>[ 0.554307] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10475 15:37:09.407358 <6>[ 0.561313] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10476 15:37:09.410389 <6>[ 0.568761] ACPI: Interpreter disabled.
10477 15:37:09.419101 <6>[ 0.575197] iommu: Default domain type: Translated
10478 15:37:09.425586 <6>[ 0.580310] iommu: DMA domain TLB invalidation policy: strict mode
10479 15:37:09.429393 <5>[ 0.586964] SCSI subsystem initialized
10480 15:37:09.435531 <6>[ 0.591210] usbcore: registered new interface driver usbfs
10481 15:37:09.442251 <6>[ 0.596939] usbcore: registered new interface driver hub
10482 15:37:09.445367 <6>[ 0.602491] usbcore: registered new device driver usb
10483 15:37:09.452455 <6>[ 0.608610] pps_core: LinuxPPS API ver. 1 registered
10484 15:37:09.462266 <6>[ 0.613803] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10485 15:37:09.465348 <6>[ 0.623147] PTP clock support registered
10486 15:37:09.468694 <6>[ 0.627390] EDAC MC: Ver: 3.0.0
10487 15:37:09.476277 <6>[ 0.632567] FPGA manager framework
10488 15:37:09.483022 <6>[ 0.636244] Advanced Linux Sound Architecture Driver Initialized.
10489 15:37:09.486422 <6>[ 0.643002] vgaarb: loaded
10490 15:37:09.493228 <6>[ 0.646182] clocksource: Switched to clocksource arch_sys_counter
10491 15:37:09.496105 <5>[ 0.652633] VFS: Disk quotas dquot_6.6.0
10492 15:37:09.502816 <6>[ 0.656819] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10493 15:37:09.505982 <6>[ 0.663995] pnp: PnP ACPI: disabled
10494 15:37:09.514414 <6>[ 0.670687] NET: Registered PF_INET protocol family
10495 15:37:09.524509 <6>[ 0.676290] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10496 15:37:09.535644 <6>[ 0.688618] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10497 15:37:09.545534 <6>[ 0.697437] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10498 15:37:09.552169 <6>[ 0.705408] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10499 15:37:09.562349 <6>[ 0.714107] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10500 15:37:09.568969 <6>[ 0.723856] TCP: Hash tables configured (established 65536 bind 65536)
10501 15:37:09.575515 <6>[ 0.730709] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10502 15:37:09.585653 <6>[ 0.737909] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10503 15:37:09.588482 <6>[ 0.745600] NET: Registered PF_UNIX/PF_LOCAL protocol family
10504 15:37:09.595428 <6>[ 0.751749] RPC: Registered named UNIX socket transport module.
10505 15:37:09.602239 <6>[ 0.757904] RPC: Registered udp transport module.
10506 15:37:09.605103 <6>[ 0.762836] RPC: Registered tcp transport module.
10507 15:37:09.611870 <6>[ 0.767769] RPC: Registered tcp NFSv4.1 backchannel transport module.
10508 15:37:09.619046 <6>[ 0.774433] PCI: CLS 0 bytes, default 64
10509 15:37:09.621805 <6>[ 0.778790] Unpacking initramfs...
10510 15:37:09.645217 <6>[ 0.798281] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10511 15:37:09.654900 <6>[ 0.806925] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10512 15:37:09.658069 <6>[ 0.815767] kvm [1]: IPA Size Limit: 40 bits
10513 15:37:09.664803 <6>[ 0.820295] kvm [1]: GICv3: no GICV resource entry
10514 15:37:09.668147 <6>[ 0.825317] kvm [1]: disabling GICv2 emulation
10515 15:37:09.674788 <6>[ 0.830000] kvm [1]: GIC system register CPU interface enabled
10516 15:37:09.678461 <6>[ 0.836163] kvm [1]: vgic interrupt IRQ18
10517 15:37:09.684734 <6>[ 0.840519] kvm [1]: VHE mode initialized successfully
10518 15:37:09.691017 <5>[ 0.846976] Initialise system trusted keyrings
10519 15:37:09.697897 <6>[ 0.851785] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10520 15:37:09.705689 <6>[ 0.861861] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10521 15:37:09.711917 <5>[ 0.868247] NFS: Registering the id_resolver key type
10522 15:37:09.715495 <5>[ 0.873550] Key type id_resolver registered
10523 15:37:09.722055 <5>[ 0.877964] Key type id_legacy registered
10524 15:37:09.729046 <6>[ 0.882241] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10525 15:37:09.735135 <6>[ 0.889160] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10526 15:37:09.742371 <6>[ 0.896910] 9p: Installing v9fs 9p2000 file system support
10527 15:37:09.778342 <5>[ 0.934732] Key type asymmetric registered
10528 15:37:09.781847 <5>[ 0.939063] Asymmetric key parser 'x509' registered
10529 15:37:09.791853 <6>[ 0.944209] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10530 15:37:09.795049 <6>[ 0.951830] io scheduler mq-deadline registered
10531 15:37:09.797905 <6>[ 0.956604] io scheduler kyber registered
10532 15:37:09.816898 <6>[ 0.973595] EINJ: ACPI disabled.
10533 15:37:09.848904 <4>[ 0.998738] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10534 15:37:09.859166 <4>[ 1.009368] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10535 15:37:09.873877 <6>[ 1.030111] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10536 15:37:09.881659 <6>[ 1.038112] printk: console [ttyS0] disabled
10537 15:37:09.910318 <6>[ 1.062761] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10538 15:37:09.916334 <6>[ 1.072232] printk: console [ttyS0] enabled
10539 15:37:09.919527 <6>[ 1.072232] printk: console [ttyS0] enabled
10540 15:37:09.926133 <6>[ 1.081127] printk: bootconsole [mtk8250] disabled
10541 15:37:09.929624 <6>[ 1.081127] printk: bootconsole [mtk8250] disabled
10542 15:37:09.935892 <6>[ 1.092431] SuperH (H)SCI(F) driver initialized
10543 15:37:09.939620 <6>[ 1.097725] msm_serial: driver initialized
10544 15:37:09.953595 <6>[ 1.106740] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10545 15:37:09.963340 <6>[ 1.115288] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10546 15:37:09.969888 <6>[ 1.123829] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10547 15:37:09.979927 <6>[ 1.132456] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10548 15:37:09.986690 <6>[ 1.141168] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10549 15:37:09.996439 <6>[ 1.149881] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10550 15:37:10.006554 <6>[ 1.158421] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10551 15:37:10.013258 <6>[ 1.167213] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10552 15:37:10.023447 <6>[ 1.175757] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10553 15:37:10.034878 <6>[ 1.191672] loop: module loaded
10554 15:37:10.041816 <6>[ 1.197719] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10555 15:37:10.064755 <4>[ 1.221342] mtk-pmic-keys: Failed to locate of_node [id: -1]
10556 15:37:10.071906 <6>[ 1.228482] megasas: 07.719.03.00-rc1
10557 15:37:10.081899 <6>[ 1.238276] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10558 15:37:10.088947 <6>[ 1.245582] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10559 15:37:10.106099 <6>[ 1.262289] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10560 15:37:10.162546 <6>[ 1.312409] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10561 15:37:10.359791 <6>[ 1.516123] Freeing initrd memory: 17352K
10562 15:37:10.370375 <6>[ 1.526452] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10563 15:37:10.380774 <6>[ 1.537314] tun: Universal TUN/TAP device driver, 1.6
10564 15:37:10.384178 <6>[ 1.543376] thunder_xcv, ver 1.0
10565 15:37:10.387706 <6>[ 1.546885] thunder_bgx, ver 1.0
10566 15:37:10.390817 <6>[ 1.550380] nicpf, ver 1.0
10567 15:37:10.401511 <6>[ 1.554401] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10568 15:37:10.405235 <6>[ 1.561876] hns3: Copyright (c) 2017 Huawei Corporation.
10569 15:37:10.411237 <6>[ 1.567462] hclge is initializing
10570 15:37:10.414685 <6>[ 1.571042] e1000: Intel(R) PRO/1000 Network Driver
10571 15:37:10.421153 <6>[ 1.576171] e1000: Copyright (c) 1999-2006 Intel Corporation.
10572 15:37:10.424542 <6>[ 1.582185] e1000e: Intel(R) PRO/1000 Network Driver
10573 15:37:10.431438 <6>[ 1.587400] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10574 15:37:10.437593 <6>[ 1.593585] igb: Intel(R) Gigabit Ethernet Network Driver
10575 15:37:10.444619 <6>[ 1.599235] igb: Copyright (c) 2007-2014 Intel Corporation.
10576 15:37:10.450869 <6>[ 1.605074] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10577 15:37:10.457777 <6>[ 1.611592] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10578 15:37:10.461163 <6>[ 1.618056] sky2: driver version 1.30
10579 15:37:10.467543 <6>[ 1.623060] VFIO - User Level meta-driver version: 0.3
10580 15:37:10.475442 <6>[ 1.631318] usbcore: registered new interface driver usb-storage
10581 15:37:10.481723 <6>[ 1.637763] usbcore: registered new device driver onboard-usb-hub
10582 15:37:10.490635 <6>[ 1.646893] mt6397-rtc mt6359-rtc: registered as rtc0
10583 15:37:10.500382 <6>[ 1.652358] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-22T15:37:11 UTC (1692718631)
10584 15:37:10.503723 <6>[ 1.661925] i2c_dev: i2c /dev entries driver
10585 15:37:10.520419 <6>[ 1.673584] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10586 15:37:10.540306 <6>[ 1.696572] cpu cpu0: EM: created perf domain
10587 15:37:10.543194 <6>[ 1.701583] cpu cpu4: EM: created perf domain
10588 15:37:10.550338 <6>[ 1.707199] sdhci: Secure Digital Host Controller Interface driver
10589 15:37:10.557372 <6>[ 1.713633] sdhci: Copyright(c) Pierre Ossman
10590 15:37:10.564133 <6>[ 1.718602] Synopsys Designware Multimedia Card Interface Driver
10591 15:37:10.570796 <6>[ 1.725239] sdhci-pltfm: SDHCI platform and OF driver helper
10592 15:37:10.574011 <6>[ 1.725270] mmc0: CQHCI version 5.10
10593 15:37:10.580340 <6>[ 1.735581] ledtrig-cpu: registered to indicate activity on CPUs
10594 15:37:10.587534 <6>[ 1.742714] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10595 15:37:10.593627 <6>[ 1.749769] usbcore: registered new interface driver usbhid
10596 15:37:10.597099 <6>[ 1.755591] usbhid: USB HID core driver
10597 15:37:10.604089 <6>[ 1.759781] spi_master spi0: will run message pump with realtime priority
10598 15:37:10.648724 <6>[ 1.798565] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10599 15:37:10.668182 <6>[ 1.814475] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10600 15:37:10.671107 <6>[ 1.828012] mmc0: Command Queue Engine enabled
10601 15:37:10.677960 <6>[ 1.832805] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10602 15:37:10.684534 <6>[ 1.840119] mmcblk0: mmc0:0001 DA4128 116 GiB
10603 15:37:10.687688 <6>[ 1.845033] cros-ec-spi spi0.0: Chrome EC device registered
10604 15:37:10.694355 <6>[ 1.849414] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10605 15:37:10.702237 <6>[ 1.858849] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10606 15:37:10.708845 <6>[ 1.864751] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10607 15:37:10.715313 <6>[ 1.870843] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10608 15:37:10.734402 <6>[ 1.888092] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10609 15:37:10.742232 <6>[ 1.898530] NET: Registered PF_PACKET protocol family
10610 15:37:10.745263 <6>[ 1.903915] 9pnet: Installing 9P2000 support
10611 15:37:10.751602 <5>[ 1.908471] Key type dns_resolver registered
10612 15:37:10.755129 <6>[ 1.913441] registered taskstats version 1
10613 15:37:10.761589 <5>[ 1.917820] Loading compiled-in X.509 certificates
10614 15:37:10.793604 <4>[ 1.943289] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10615 15:37:10.803667 <4>[ 1.954009] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10616 15:37:10.809868 <3>[ 1.964553] debugfs: File 'uA_load' in directory '/' already present!
10617 15:37:10.816997 <3>[ 1.971253] debugfs: File 'min_uV' in directory '/' already present!
10618 15:37:10.823689 <3>[ 1.977862] debugfs: File 'max_uV' in directory '/' already present!
10619 15:37:10.830220 <3>[ 1.984468] debugfs: File 'constraint_flags' in directory '/' already present!
10620 15:37:10.841034 <3>[ 1.994328] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10621 15:37:10.850045 <6>[ 2.006822] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10622 15:37:10.857132 <6>[ 2.013673] xhci-mtk 11200000.usb: xHCI Host Controller
10623 15:37:10.863854 <6>[ 2.019162] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10624 15:37:10.873770 <6>[ 2.027009] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10625 15:37:10.880493 <6>[ 2.036424] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10626 15:37:10.886923 <6>[ 2.042499] xhci-mtk 11200000.usb: xHCI Host Controller
10627 15:37:10.893525 <6>[ 2.047975] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10628 15:37:10.900312 <6>[ 2.055622] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10629 15:37:10.907114 <6>[ 2.063253] hub 1-0:1.0: USB hub found
10630 15:37:10.910676 <6>[ 2.067262] hub 1-0:1.0: 1 port detected
10631 15:37:10.917400 <6>[ 2.071524] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10632 15:37:10.923947 <6>[ 2.080062] hub 2-0:1.0: USB hub found
10633 15:37:10.927237 <6>[ 2.084079] hub 2-0:1.0: 1 port detected
10634 15:37:10.934866 <6>[ 2.091540] mtk-msdc 11f70000.mmc: Got CD GPIO
10635 15:37:10.945370 <6>[ 2.097950] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10636 15:37:10.951966 <6>[ 2.105975] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10637 15:37:10.961762 <4>[ 2.113872] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10638 15:37:10.971425 <6>[ 2.123398] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10639 15:37:10.978073 <6>[ 2.131475] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10640 15:37:10.984996 <6>[ 2.139592] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10641 15:37:10.995199 <6>[ 2.147518] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10642 15:37:11.001540 <6>[ 2.155393] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10643 15:37:11.011476 <6>[ 2.163214] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10644 15:37:11.021769 <6>[ 2.173460] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10645 15:37:11.028423 <6>[ 2.181819] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10646 15:37:11.038467 <6>[ 2.190203] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10647 15:37:11.044876 <6>[ 2.198544] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10648 15:37:11.054659 <6>[ 2.206893] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10649 15:37:11.061484 <6>[ 2.215232] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10650 15:37:11.071572 <6>[ 2.223581] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10651 15:37:11.078069 <6>[ 2.231920] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10652 15:37:11.088063 <6>[ 2.240268] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10653 15:37:11.095249 <6>[ 2.248607] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10654 15:37:11.105132 <6>[ 2.256956] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10655 15:37:11.111893 <6>[ 2.265294] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10656 15:37:11.122152 <6>[ 2.273632] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10657 15:37:11.128255 <6>[ 2.281970] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10658 15:37:11.138719 <6>[ 2.290308] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10659 15:37:11.145208 <6>[ 2.299117] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10660 15:37:11.151321 <6>[ 2.306328] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10661 15:37:11.158206 <6>[ 2.313107] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10662 15:37:11.164262 <6>[ 2.319872] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10663 15:37:11.171047 <6>[ 2.326816] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10664 15:37:11.180809 <6>[ 2.333662] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10665 15:37:11.190758 <6>[ 2.342792] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10666 15:37:11.200536 <6>[ 2.351915] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10667 15:37:11.211095 <6>[ 2.361209] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10668 15:37:11.217906 <6>[ 2.370697] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10669 15:37:11.227233 <6>[ 2.380171] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10670 15:37:11.237453 <6>[ 2.389291] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10671 15:37:11.247479 <6>[ 2.398757] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10672 15:37:11.257297 <6>[ 2.407876] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10673 15:37:11.266967 <6>[ 2.417171] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10674 15:37:11.276946 <6>[ 2.427331] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10675 15:37:11.286686 <6>[ 2.438922] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10676 15:37:11.293261 <6>[ 2.448816] Trying to probe devices needed for running init ...
10677 15:37:11.317402 <6>[ 2.470524] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10678 15:37:11.345726 <6>[ 2.501968] hub 2-1:1.0: USB hub found
10679 15:37:11.348968 <6>[ 2.506459] hub 2-1:1.0: 3 ports detected
10680 15:37:11.469684 <6>[ 2.622383] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10681 15:37:11.624827 <6>[ 2.780939] hub 1-1:1.0: USB hub found
10682 15:37:11.628125 <6>[ 2.785432] hub 1-1:1.0: 4 ports detected
10683 15:37:11.701856 <6>[ 2.854741] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10684 15:37:11.949777 <6>[ 3.102504] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10685 15:37:12.081844 <6>[ 3.238433] hub 1-1.4:1.0: USB hub found
10686 15:37:12.085415 <6>[ 3.243106] hub 1-1.4:1.0: 2 ports detected
10687 15:37:12.381389 <6>[ 3.534482] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10688 15:37:12.573276 <6>[ 3.726485] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10689 15:37:23.573794 <6>[ 14.735472] ALSA device list:
10690 15:37:23.580454 <6>[ 14.738767] No soundcards found.
10691 15:37:23.588372 <6>[ 14.746682] Freeing unused kernel memory: 8384K
10692 15:37:23.591862 <6>[ 14.751708] Run /init as init process
10693 15:37:23.603142 Loading, please wait...
10694 15:37:23.624655 Starting version 247.3-7+deb11u2
10695 15:37:23.830615 <6>[ 14.985194] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10696 15:37:23.849187 <6>[ 15.007726] remoteproc remoteproc0: scp is available
10697 15:37:23.856389 <6>[ 15.013138] remoteproc remoteproc0: powering up scp
10698 15:37:23.862872 <6>[ 15.018337] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10699 15:37:23.869278 <6>[ 15.026825] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10700 15:37:23.875806 <6>[ 15.028828] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10701 15:37:23.885773 <6>[ 15.040269] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10702 15:37:23.892790 <6>[ 15.043610] usbcore: registered new interface driver r8152
10703 15:37:23.899406 <6>[ 15.049128] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10704 15:37:23.910238 <3>[ 15.064783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 15:37:23.913062 <6>[ 15.073358] mc: Linux media interface: v0.10
10706 15:37:23.923152 <3>[ 15.074155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 15:37:23.929578 <3>[ 15.086047] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 15:37:23.942526 <3>[ 15.097502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 15:37:23.948931 <3>[ 15.105824] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 15:37:23.955968 <6>[ 15.110095] videodev: Linux video capture interface: v2.00
10711 15:37:23.965291 <6>[ 15.110285] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10712 15:37:23.972326 <3>[ 15.113950] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 15:37:23.978920 <4>[ 15.114830] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10714 15:37:23.985158 <4>[ 15.117507] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10715 15:37:23.995476 <4>[ 15.140471] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10716 15:37:23.998707 <4>[ 15.140471] Fallback method does not support PEC.
10717 15:37:24.009268 <3>[ 15.142781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 15:37:24.016019 <6>[ 15.157724] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10719 15:37:24.023335 <6>[ 15.157734] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10720 15:37:24.033395 <3>[ 15.163707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 15:37:24.039540 <3>[ 15.163792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 15:37:24.049475 <3>[ 15.167565] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10723 15:37:24.056044 <6>[ 15.171823] remoteproc remoteproc0: remote processor scp is now up
10724 15:37:24.062983 <6>[ 15.173006] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10725 15:37:24.072952 <6>[ 15.175417] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10726 15:37:24.079686 <3>[ 15.180514] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 15:37:24.086026 <6>[ 15.187552] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10728 15:37:24.096076 <3>[ 15.195474] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 15:37:24.102468 <3>[ 15.195478] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 15:37:24.112165 <3>[ 15.195929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 15:37:24.116012 <6>[ 15.203623] pci_bus 0000:00: root bus resource [bus 00-ff]
10732 15:37:24.125811 <6>[ 15.203685] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10733 15:37:24.132283 <3>[ 15.212371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 15:37:24.139073 <3>[ 15.212374] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 15:37:24.148768 <3>[ 15.212379] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 15:37:24.155521 <6>[ 15.218818] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10737 15:37:24.165700 <3>[ 15.227083] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10738 15:37:24.171842 <3>[ 15.227103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 15:37:24.181735 <3>[ 15.227142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 15:37:24.191740 <6>[ 15.235499] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10741 15:37:24.201449 <6>[ 15.238137] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10742 15:37:24.208336 <6>[ 15.238694] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10743 15:37:24.218020 <4>[ 15.239126] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10744 15:37:24.228030 <4>[ 15.239132] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10745 15:37:24.234736 <6>[ 15.239284] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10746 15:37:24.241311 <6>[ 15.243792] usbcore: registered new interface driver cdc_ether
10747 15:37:24.247737 <6>[ 15.250922] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10748 15:37:24.254421 <6>[ 15.275512] usbcore: registered new interface driver r8153_ecm
10749 15:37:24.258107 <6>[ 15.275585] Bluetooth: Core ver 2.22
10750 15:37:24.264407 <6>[ 15.275719] NET: Registered PF_BLUETOOTH protocol family
10751 15:37:24.270820 <6>[ 15.275725] Bluetooth: HCI device and connection manager initialized
10752 15:37:24.274491 <6>[ 15.275796] Bluetooth: HCI socket layer initialized
10753 15:37:24.281196 <6>[ 15.275809] Bluetooth: L2CAP socket layer initialized
10754 15:37:24.287883 <6>[ 15.275831] Bluetooth: SCO socket layer initialized
10755 15:37:24.294407 <6>[ 15.280505] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10756 15:37:24.300579 <6>[ 15.297114] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10757 15:37:24.303926 <6>[ 15.303873] pci 0000:00:00.0: supports D1 D2
10758 15:37:24.317158 <6>[ 15.313714] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10759 15:37:24.323728 <6>[ 15.319013] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10760 15:37:24.333857 <6>[ 15.320510] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10761 15:37:24.337041 <6>[ 15.328020] usbcore: registered new interface driver uvcvideo
10762 15:37:24.343570 <6>[ 15.335996] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10763 15:37:24.350209 <6>[ 15.336595] usbcore: registered new interface driver btusb
10764 15:37:24.356679 <6>[ 15.336670] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10765 15:37:24.366557 <4>[ 15.337823] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10766 15:37:24.373133 <3>[ 15.337841] Bluetooth: hci0: Failed to load firmware file (-2)
10767 15:37:24.379915 <3>[ 15.337845] Bluetooth: hci0: Failed to set up firmware (-2)
10768 15:37:24.389633 <4>[ 15.337855] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10769 15:37:24.393191 <6>[ 15.344017] r8152 2-1.3:1.0 eth0: v1.12.13
10770 15:37:24.403189 <6>[ 15.353889] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10771 15:37:24.406449 <6>[ 15.376910] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10772 15:37:24.416216 <6>[ 15.382034] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10773 15:37:24.422666 <6>[ 15.382049] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10774 15:37:24.426305 <6>[ 15.586127] pci 0000:01:00.0: supports D1 D2
10775 15:37:24.432879 <6>[ 15.590649] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10776 15:37:24.451450 <6>[ 15.606378] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10777 15:37:24.457655 <6>[ 15.613285] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10778 15:37:24.464486 <6>[ 15.621367] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10779 15:37:24.474447 <6>[ 15.629364] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10780 15:37:24.480975 <6>[ 15.637365] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10781 15:37:24.490958 <6>[ 15.645365] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10782 15:37:24.494207 <6>[ 15.653365] pci 0000:00:00.0: PCI bridge to [bus 01]
10783 15:37:24.504491 <6>[ 15.658580] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10784 15:37:24.510632 <6>[ 15.666706] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10785 15:37:24.517793 <6>[ 15.673547] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10786 15:37:24.524156 <6>[ 15.680447] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10787 15:37:24.547598 <5>[ 15.702656] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10788 15:37:24.564518 <5>[ 15.719413] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10789 15:37:24.571139 <4>[ 15.726364] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10790 15:37:24.577857 <6>[ 15.735282] cfg80211: failed to load regulatory.db
10791 15:37:24.638090 <6>[ 15.792512] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10792 15:37:24.644043 <6>[ 15.800056] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10793 15:37:24.668699 <6>[ 15.826832] mt7921e 0000:01:00.0: ASIC revision: 79610010
10794 15:37:24.774887 <4>[ 15.926898] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 15:37:24.795143 Begin: Loading essential drivers ... done.
10796 15:37:24.798615 Begin: Running /scripts/init-premount ... done.
10797 15:37:24.805489 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10798 15:37:24.814947 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10799 15:37:24.818094 Device /sys/class/net/enx0024323078ff found
10800 15:37:24.818196 done.
10801 15:37:24.894889 <4>[ 16.046580] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10802 15:37:24.901367 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10803 15:37:25.014396 <4>[ 16.166078] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10804 15:37:25.133662 <4>[ 16.285703] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 15:37:25.253952 <4>[ 16.405860] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10806 15:37:25.373599 <4>[ 16.525705] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10807 15:37:25.493825 <4>[ 16.645863] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 15:37:25.613589 <4>[ 16.765680] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 15:37:25.733634 <4>[ 16.885700] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 15:37:25.803609 <6>[ 16.962227] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10811 15:37:25.854220 <4>[ 17.005710] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 15:37:25.965047 <3>[ 17.123738] mt7921e 0000:01:00.0: hardware init failed
10813 15:37:25.993856 IP-Config: no response after 2 secs - giving up
10814 15:37:26.027422 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10815 15:37:26.030445 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10816 15:37:26.040555 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10817 15:37:26.046870 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10818 15:37:26.053685 host : mt8192-asurada-spherion-r0-cbg-8
10819 15:37:26.060104 domain : lava-rack
10820 15:37:26.063878 rootserver: 192.168.201.1 rootpath:
10821 15:37:26.063964 filename :
10822 15:37:26.107269 done.
10823 15:37:26.114517 Begin: Running /scripts/nfs-bottom ... done.
10824 15:37:26.131294 Begin: Running /scripts/init-bottom ... done.
10825 15:37:27.343710 <6>[ 18.502618] NET: Registered PF_INET6 protocol family
10826 15:37:27.351424 <6>[ 18.510252] Segment Routing with IPv6
10827 15:37:27.354792 <6>[ 18.514235] In-situ OAM (IOAM) with IPv6
10828 15:37:27.483980 <30>[ 18.622914] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10829 15:37:27.490389 <30>[ 18.647387] systemd[1]: Detected architecture arm64.
10830 15:37:27.509976
10831 15:37:27.513348 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10832 15:37:27.513487
10833 15:37:27.534262 <30>[ 18.693099] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10834 15:37:28.386902 <30>[ 19.542371] systemd[1]: Queued start job for default target Graphical Interface.
10835 15:37:28.425837 <30>[ 19.584815] systemd[1]: Created slice system-getty.slice.
10836 15:37:28.432348 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10837 15:37:28.449189 <30>[ 19.607901] systemd[1]: Created slice system-modprobe.slice.
10838 15:37:28.455655 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10839 15:37:28.473779 <30>[ 19.632547] systemd[1]: Created slice system-serial\x2dgetty.slice.
10840 15:37:28.484166 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10841 15:37:28.496788 <30>[ 19.655554] systemd[1]: Created slice User and Session Slice.
10842 15:37:28.503305 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10843 15:37:28.523935 <30>[ 19.679310] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10844 15:37:28.533618 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10845 15:37:28.551747 <30>[ 19.707219] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10846 15:37:28.558079 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10847 15:37:28.582463 <30>[ 19.734650] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10848 15:37:28.589343 <30>[ 19.746800] systemd[1]: Reached target Local Encrypted Volumes.
10849 15:37:28.595775 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10850 15:37:28.612199 <30>[ 19.771044] systemd[1]: Reached target Paths.
10851 15:37:28.618606 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10852 15:37:28.631523 <30>[ 19.790479] systemd[1]: Reached target Remote File Systems.
10853 15:37:28.638036 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10854 15:37:28.655980 <30>[ 19.814823] systemd[1]: Reached target Slices.
10855 15:37:28.662700 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10856 15:37:28.676170 <30>[ 19.834511] systemd[1]: Reached target Swap.
10857 15:37:28.678989 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10858 15:37:28.699216 <30>[ 19.854956] systemd[1]: Listening on initctl Compatibility Named Pipe.
10859 15:37:28.705850 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10860 15:37:28.712757 <30>[ 19.871129] systemd[1]: Listening on Journal Audit Socket.
10861 15:37:28.719167 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10862 15:37:28.736801 <30>[ 19.895826] systemd[1]: Listening on Journal Socket (/dev/log).
10863 15:37:28.743411 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10864 15:37:28.760537 <30>[ 19.919049] systemd[1]: Listening on Journal Socket.
10865 15:37:28.766701 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10866 15:37:28.784389 <30>[ 19.939994] systemd[1]: Listening on Network Service Netlink Socket.
10867 15:37:28.790930 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10868 15:37:28.806836 <30>[ 19.965421] systemd[1]: Listening on udev Control Socket.
10869 15:37:28.813596 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10870 15:37:28.828005 <30>[ 19.986885] systemd[1]: Listening on udev Kernel Socket.
10871 15:37:28.834735 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10872 15:37:28.892243 <30>[ 20.050678] systemd[1]: Mounting Huge Pages File System...
10873 15:37:28.898625 Mounting [0;1;39mHuge Pages File System[0m...
10874 15:37:28.916486 <30>[ 20.075153] systemd[1]: Mounting POSIX Message Queue File System...
10875 15:37:28.923026 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10876 15:37:28.943988 <30>[ 20.102930] systemd[1]: Mounting Kernel Debug File System...
10877 15:37:28.950867 Mounting [0;1;39mKernel Debug File System[0m...
10878 15:37:28.967857 <30>[ 20.123198] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10879 15:37:28.979956 <30>[ 20.135534] systemd[1]: Starting Create list of static device nodes for the current kernel...
10880 15:37:28.986483 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10881 15:37:29.008039 <30>[ 20.166528] systemd[1]: Starting Load Kernel Module configfs...
10882 15:37:29.014342 Starting [0;1;39mLoad Kernel Module configfs[0m...
10883 15:37:29.032281 <30>[ 20.191107] systemd[1]: Starting Load Kernel Module drm...
10884 15:37:29.038678 Starting [0;1;39mLoad Kernel Module drm[0m...
10885 15:37:29.054813 <30>[ 20.213885] systemd[1]: Starting Load Kernel Module fuse...
10886 15:37:29.061761 Starting [0;1;39mLoad Kernel Module fuse[0m...
10887 15:37:29.094557 <6>[ 20.253660] fuse: init (API version 7.37)
10888 15:37:29.104716 <30>[ 20.254414] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10889 15:37:29.117142 <30>[ 20.276209] systemd[1]: Starting Journal Service...
10890 15:37:29.120649 Starting [0;1;39mJournal Service[0m...
10891 15:37:29.146824 <30>[ 20.305666] systemd[1]: Starting Load Kernel Modules...
10892 15:37:29.153222 Starting [0;1;39mLoad Kernel Modules[0m...
10893 15:37:29.176339 <30>[ 20.331980] systemd[1]: Starting Remount Root and Kernel File Systems...
10894 15:37:29.182815 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10895 15:37:29.200032 <30>[ 20.358662] systemd[1]: Starting Coldplug All udev Devices...
10896 15:37:29.206189 Starting [0;1;39mColdplug All udev Devices[0m...
10897 15:37:29.224274 <30>[ 20.383352] systemd[1]: Mounted Huge Pages File System.
10898 15:37:29.231575 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10899 15:37:29.243827 <3>[ 20.399204] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 15:37:29.250298 <30>[ 20.409175] systemd[1]: Mounted POSIX Message Queue File System.
10901 15:37:29.257022 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10902 15:37:29.271991 <30>[ 20.430848] systemd[1]: Mounted Kernel Debug File System.
10903 15:37:29.282107 <3>[ 20.432015] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 15:37:29.289040 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10905 15:37:29.308377 <30>[ 20.463877] systemd[1]: Finished Create list of static device nodes for the current kernel.
10906 15:37:29.315360 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10907 15:37:29.325567 <3>[ 20.481092] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 15:37:29.332648 <30>[ 20.491611] systemd[1]: modprobe@configfs.service: Succeeded.
10909 15:37:29.340297 <30>[ 20.499133] systemd[1]: Finished Load Kernel Module configfs.
10910 15:37:29.347295 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10911 15:37:29.366822 <3>[ 20.522059] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 15:37:29.376534 <30>[ 20.535587] systemd[1]: modprobe@drm.service: Succeeded.
10913 15:37:29.383575 <30>[ 20.542084] systemd[1]: Finished Load Kernel Module drm.
10914 15:37:29.397685 [[0;32m OK [0m] Finished [0<3>[ 20.551847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 15:37:29.400778 ;1;39mLoad Kernel Module drm[0m.
10916 15:37:29.417484 <30>[ 20.576032] systemd[1]: modprobe@fuse.service: Succeeded.
10917 15:37:29.427863 <3>[ 20.581501] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 15:37:29.430897 <30>[ 20.583118] systemd[1]: Finished Load Kernel Module fuse.
10919 15:37:29.437878 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10920 15:37:29.458814 <3>[ 20.614708] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 15:37:29.466153 <30>[ 20.615589] systemd[1]: Finished Load Kernel Modules.
10922 15:37:29.472262 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10923 15:37:29.484708 <30>[ 20.643222] systemd[1]: Finished Remount Root and Kernel File Systems.
10924 15:37:29.494595 <3>[ 20.645029] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 15:37:29.501342 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10926 15:37:29.525688 <3>[ 20.681244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 15:37:29.554043 <30>[ 20.712657] systemd[1]: Mounting FUSE Control File System...
10928 15:37:29.563998 <3>[ 20.714042] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 15:37:29.570201 Mounting [0;1;39mFUSE Control File System[0m...
10930 15:37:29.588739 <30>[ 20.746856] systemd[1]: Mounting Kernel Configuration File System...
10931 15:37:29.594976 Mounting [0;1;39mKernel Configuration File System[0m...
10932 15:37:29.620259 <30>[ 20.775630] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10933 15:37:29.630547 <30>[ 20.784715] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10934 15:37:29.656347 <30>[ 20.815088] systemd[1]: Starting Load/Save Random Seed...
10935 15:37:29.662777 Starting [0;1;39mLoad/Save Random Seed[0m...
10936 15:37:29.678880 <30>[ 20.837608] systemd[1]: Starting Apply Kernel Variables...
10937 15:37:29.685254 Starting [0;1;39mApply Kernel Variables[0m...
10938 15:37:29.705889 <4>[ 20.855198] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10939 15:37:29.716329 <3>[ 20.871191] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10940 15:37:29.719068 <30>[ 20.874662] systemd[1]: Starting Create System Users...
10941 15:37:29.726975 Starting [0;1;39mCreate System Users[0m...
10942 15:37:29.741993 <30>[ 20.900389] systemd[1]: Started Journal Service.
10943 15:37:29.745331 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10944 15:37:29.772022 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10945 15:37:29.783322 See 'systemctl status systemd-udev-trigger.service' for details.
10946 15:37:29.800143 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10947 15:37:29.815981 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10948 15:37:29.833244 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10949 15:37:29.849347 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10950 15:37:29.865267 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10951 15:37:29.916207 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10952 15:37:29.934130 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10953 15:37:29.968877 <46>[ 21.124723] systemd-journald[292]: Received client request to flush runtime journal.
10954 15:37:30.729293 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10955 15:37:30.743897 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10956 15:37:30.759755 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10957 15:37:30.815303 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10958 15:37:31.401272 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10959 15:37:31.444362 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10960 15:37:31.503142 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10961 15:37:31.569438 Starting [0;1;39mNetwork Service[0m...
10962 15:37:31.864632 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10963 15:37:31.897643 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10964 15:37:31.931027 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10965 15:37:32.217776 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10966 15:37:32.235150 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10967 15:37:32.281142 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10968 15:37:32.317730 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10969 15:37:32.340689 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10970 15:37:32.355869 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10971 15:37:32.376178 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10972 15:37:32.448551 Starting [0;1;39mNetwork Name Resolution[0m...
10973 15:37:32.472256 Starting [0;1;39mNetwork Time Synchronization[0m...
10974 15:37:32.490212 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10975 15:37:32.569913 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10976 15:37:32.735552 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10977 15:37:32.751771 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10978 15:37:32.770858 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10979 15:37:32.783626 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10980 15:37:32.799700 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10981 15:37:32.923784 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10982 15:37:32.964648 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10983 15:37:32.994692 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10984 15:37:33.020526 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10985 15:37:33.031601 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10986 15:37:33.054354 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10987 15:37:33.067546 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10988 15:37:33.083363 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10989 15:37:33.132639 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10990 15:37:33.827823 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10991 15:37:34.207976 Starting [0;1;39mUser Login Management[0m...
10992 15:37:34.224968 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10993 15:37:34.242616 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10994 15:37:34.258936 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10995 15:37:34.304196 Starting [0;1;39mPermit User Sessions[0m...
10996 15:37:34.415234 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10997 15:37:34.448880 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10998 15:37:34.480412 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10999 15:37:34.536451 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11000 15:37:34.551006 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11001 15:37:34.568675 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11002 15:37:34.584375 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11003 15:37:34.603138 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11004 15:37:34.656320 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11005 15:37:34.704357 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11006 15:37:34.816926
11007 15:37:34.817075
11008 15:37:34.820374 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11009 15:37:34.820461
11010 15:37:34.823048 debian-bullseye-arm64 login: root (automatic login)
11011 15:37:34.823133
11012 15:37:34.823235
11013 15:37:35.158915 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Tue Aug 22 15:20:14 UTC 2023 aarch64
11014 15:37:35.159066
11015 15:37:35.165328 The programs included with the Debian GNU/Linux system are free software;
11016 15:37:35.171911 the exact distribution terms for each program are described in the
11017 15:37:35.175237 individual files in /usr/share/doc/*/copyright.
11018 15:37:35.175322
11019 15:37:35.181949 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11020 15:37:35.185447 permitted by applicable law.
11021 15:37:35.269308 Matched prompt #10: / #
11023 15:37:35.269624 Setting prompt string to ['/ #']
11024 15:37:35.269742 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11026 15:37:35.269976 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11027 15:37:35.270081 start: 2.2.6 expect-shell-connection (timeout 00:03:17) [common]
11028 15:37:35.270162 Setting prompt string to ['/ #']
11029 15:37:35.270261 Forcing a shell prompt, looking for ['/ #']
11031 15:37:35.320554 / #
11032 15:37:35.320673 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11033 15:37:35.320764 Waiting using forced prompt support (timeout 00:02:30)
11034 15:37:35.325302
11035 15:37:35.325577 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11036 15:37:35.325683 start: 2.2.7 export-device-env (timeout 00:03:17) [common]
11038 15:37:35.426085 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11331379/extract-nfsrootfs-uhp87pcj'
11039 15:37:35.431305 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11331379/extract-nfsrootfs-uhp87pcj'
11041 15:37:35.531884 / # export NFS_SERVER_IP='192.168.201.1'
11042 15:37:35.537193 export NFS_SERVER_IP='192.168.201.1'
11043 15:37:35.537484 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11044 15:37:35.537624 end: 2.2 depthcharge-retry (duration 00:01:43) [common]
11045 15:37:35.537730 end: 2 depthcharge-action (duration 00:01:43) [common]
11046 15:37:35.537839 start: 3 lava-test-retry (timeout 00:01:00) [common]
11047 15:37:35.537946 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11048 15:37:35.538034 Using namespace: common
11050 15:37:35.638414 / # #
11051 15:37:35.638544 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11052 15:37:35.643735 #
11053 15:37:35.644004 Using /lava-11331379
11055 15:37:35.744335 / # export SHELL=/bin/sh
11056 15:37:35.749213 export SHELL=/bin/sh
11058 15:37:35.849746 / # . /lava-11331379/environment
11059 15:37:35.854808 . /lava-11331379/environment
11061 15:37:35.961533 / # /lava-11331379/bin/lava-test-runner /lava-11331379/0
11062 15:37:35.961736 Test shell timeout: 10s (minimum of the action and connection timeout)
11063 15:37:35.966657 /lava-11331379/bin/lava-test-runner /lava-11331379/0
11064 15:37:36.229982 + export TESTRUN_ID=0_dmesg
11065 15:37:36.233021 + cd /lava-11331379/0/tests/0_dmesg
11066 15:37:36.236454 + cat uuid
11067 15:37:36.251916 + UUID=11331379_<8>[ 27.408720] <LAVA_SIGNAL_STARTRUN 0_dmesg 11331379_1.6.2.3.1>
11068 15:37:36.252005 1.6.2.3.1
11069 15:37:36.252094 + set +x
11070 15:37:36.252360 Received signal: <STARTRUN> 0_dmesg 11331379_1.6.2.3.1
11071 15:37:36.252441 Starting test lava.0_dmesg (11331379_1.6.2.3.1)
11072 15:37:36.252551 Skipping test definition patterns.
11073 15:37:36.258817 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11074 15:37:36.360954 <8>[ 27.517331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11075 15:37:36.361258 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11077 15:37:36.438312 <8>[ 27.594629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11078 15:37:36.438633 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11080 15:37:36.524840 <8>[ 27.681328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11081 15:37:36.525160 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11083 15:37:36.531224 + <8>[ 27.691221] <LAVA_SIGNAL_ENDRUN 0_dmesg 11331379_1.6.2.3.1>
11084 15:37:36.531336 set +x
11085 15:37:36.531595 Received signal: <ENDRUN> 0_dmesg 11331379_1.6.2.3.1
11086 15:37:36.531675 Ending use of test pattern.
11087 15:37:36.531738 Ending test lava.0_dmesg (11331379_1.6.2.3.1), duration 0.28
11089 15:37:36.536983 <LAVA_TEST_RUNNER EXIT>
11090 15:37:36.537236 ok: lava_test_shell seems to have completed
11091 15:37:36.537339 alert: pass
crit: pass
emerg: pass
11092 15:37:36.537428 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11093 15:37:36.537513 end: 3 lava-test-retry (duration 00:00:01) [common]
11094 15:37:36.537597 start: 4 lava-test-retry (timeout 00:01:00) [common]
11095 15:37:36.537679 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11096 15:37:36.537744 Using namespace: common
11098 15:37:36.638098 / # #
11099 15:37:36.638232 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11100 15:37:36.638367 Using /lava-11331379
11102 15:37:36.738723 export SHELL=/bin/sh
11103 15:37:36.738923 #
11105 15:37:36.839431 / # export SHELL=/bin/sh. /lava-11331379/environment
11106 15:37:36.839594
11108 15:37:36.940155 / # . /lava-11331379/environment/lava-11331379/bin/lava-test-runner /lava-11331379/1
11109 15:37:36.940288 Test shell timeout: 10s (minimum of the action and connection timeout)
11110 15:37:36.940443
11111 15:37:36.945587 / # /lava-11331379/bin/lava-test-runner /lava-11331379/1
11112 15:37:37.086459 + export TESTRUN_ID=1_bootrr
11113 15:37:37.089775 + cd /lava-11331379/1/tests/1_bootrr
11114 15:37:37.092831 + cat uuid
11115 15:37:37.107981 + UUID=11331379_<8>[ 28.264779] <LAVA_SIGNAL_STARTRUN 1_bootrr 11331379_1.6.2.3.5>
11116 15:37:37.108066 1.6.2.3.5
11117 15:37:37.108134 + set +x
11118 15:37:37.108373 Received signal: <STARTRUN> 1_bootrr 11331379_1.6.2.3.5
11119 15:37:37.108445 Starting test lava.1_bootrr (11331379_1.6.2.3.5)
11120 15:37:37.108523 Skipping test definition patterns.
11121 15:37:37.121679 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11331379/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11122 15:37:37.124728 + cd /opt/bootrr/libexec/bootrr
11123 15:37:37.124807 + sh helpers/bootrr-auto
11124 15:37:37.197928 /lava-11331379/1/../bin/lava-test-case
11125 15:37:37.230094 <8>[ 28.386860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11126 15:37:37.230397 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11128 15:37:37.280228 /lava-11331379/1/../bin/lava-test-case
11129 15:37:37.314680 <8>[ 28.471066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11130 15:37:37.314994 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11132 15:37:37.340803 /lava-11331379/1/../bin/lava-test-case
11133 15:37:37.380579 <8>[ 28.536975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11134 15:37:37.380913 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11136 15:37:37.449750 /lava-11331379/1/../bin/lava-test-case
11137 15:37:37.477947 <8>[ 28.634690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11138 15:37:37.478271 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11140 15:37:37.515052 /lava-11331379/1/../bin/lava-test-case
11141 15:37:37.547043 <8>[ 28.703564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11142 15:37:37.547388 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11144 15:37:37.586876 /lava-11331379/1/../bin/lava-test-case
11145 15:37:37.619945 <8>[ 28.776585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11146 15:37:37.620297 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11148 15:37:37.657587 /lava-11331379/1/../bin/lava-test-case
11149 15:37:37.690650 <8>[ 28.847092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11150 15:37:37.690960 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11152 15:37:37.736002 /lava-11331379/1/../bin/lava-test-case
11153 15:37:37.768050 <8>[ 28.924394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11154 15:37:37.768386 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11156 15:37:37.792295 /lava-11331379/1/../bin/lava-test-case
11157 15:37:37.822444 <8>[ 28.978825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11158 15:37:37.822820 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11160 15:37:37.860269 /lava-11331379/1/../bin/lava-test-case
11161 15:37:37.893143 <8>[ 29.049947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11162 15:37:37.893524 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11164 15:37:37.917221 /lava-11331379/1/../bin/lava-test-case
11165 15:37:37.950629 <8>[ 29.107186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11166 15:37:37.950999 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11168 15:37:37.987544 /lava-11331379/1/../bin/lava-test-case
11169 15:37:38.021468 <8>[ 29.178084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11170 15:37:38.021802 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11172 15:37:38.065320 /lava-11331379/1/../bin/lava-test-case
11173 15:37:38.097161 <8>[ 29.253696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11174 15:37:38.097507 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11176 15:37:38.136638 /lava-11331379/1/../bin/lava-test-case
11177 15:37:38.166442 <8>[ 29.323017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11178 15:37:38.166774 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11180 15:37:38.202379 /lava-11331379/1/../bin/lava-test-case
11181 15:37:38.234753 <8>[ 29.391657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11182 15:37:38.235103 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11184 15:37:38.258062 /lava-11331379/1/../bin/lava-test-case
11185 15:37:38.285187 <8>[ 29.441634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11186 15:37:38.285548 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11188 15:37:38.320154 /lava-11331379/1/../bin/lava-test-case
11189 15:37:38.352434 <8>[ 29.509213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11190 15:37:38.352805 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11192 15:37:38.381978 /lava-11331379/1/../bin/lava-test-case
11193 15:37:38.413468 <8>[ 29.570149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11194 15:37:38.413820 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11196 15:37:38.448916 /lava-11331379/1/../bin/lava-test-case
11197 15:37:38.481092 <8>[ 29.637646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11198 15:37:38.481418 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11200 15:37:38.504536 /lava-11331379/1/../bin/lava-test-case
11201 15:37:38.537601 <8>[ 29.694276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11202 15:37:38.537948 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11204 15:37:38.576213 /lava-11331379/1/../bin/lava-test-case
11205 15:37:38.608082 <8>[ 29.764438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11206 15:37:38.608428 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11208 15:37:38.631266 /lava-11331379/1/../bin/lava-test-case
11209 15:37:38.662724 <8>[ 29.819703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11210 15:37:38.663127 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11212 15:37:38.700796 /lava-11331379/1/../bin/lava-test-case
11213 15:37:38.734987 <8>[ 29.891818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11214 15:37:38.735333 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11216 15:37:38.765617 /lava-11331379/1/../bin/lava-test-case
11217 15:37:38.795654 <8>[ 29.952059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11218 15:37:38.796060 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11220 15:37:38.830148 /lava-11331379/1/../bin/lava-test-case
11221 15:37:38.861863 <8>[ 30.018253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11222 15:37:38.862223 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11224 15:37:38.897384 /lava-11331379/1/../bin/lava-test-case
11225 15:37:38.929841 <8>[ 30.086828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11226 15:37:38.930240 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11228 15:37:38.953459 /lava-11331379/1/../bin/lava-test-case
11229 15:37:38.982041 <8>[ 30.138844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11230 15:37:38.982385 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11232 15:37:39.020249 /lava-11331379/1/../bin/lava-test-case
11233 15:37:39.052778 <8>[ 30.209403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11234 15:37:39.053174 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11236 15:37:39.081418 /lava-11331379/1/../bin/lava-test-case
11237 15:37:39.112834 <8>[ 30.268991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11238 15:37:39.113197 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11240 15:37:39.149586 /lava-11331379/1/../bin/lava-test-case
11241 15:37:39.183933 <8>[ 30.340491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11242 15:37:39.184253 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11244 15:37:39.218841 /lava-11331379/1/../bin/lava-test-case
11245 15:37:39.251056 <8>[ 30.407628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11246 15:37:39.251442 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11248 15:37:39.291500 /lava-11331379/1/../bin/lava-test-case
11249 15:37:39.324867 <8>[ 30.481870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11250 15:37:39.325221 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11252 15:37:39.360862 /lava-11331379/1/../bin/lava-test-case
11253 15:37:39.391711 <8>[ 30.548317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11254 15:37:39.392108 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11256 15:37:39.419725 /lava-11331379/1/../bin/lava-test-case
11257 15:37:39.448471 <8>[ 30.605592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11258 15:37:39.448810 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11260 15:37:39.485882 /lava-11331379/1/../bin/lava-test-case
11261 15:37:39.518968 <8>[ 30.675688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11262 15:37:39.519349 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11264 15:37:39.557062 /lava-11331379/1/../bin/lava-test-case
11265 15:37:39.589281 <8>[ 30.745949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11266 15:37:39.589634 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11268 15:37:39.613373 /lava-11331379/1/../bin/lava-test-case
11269 15:37:39.644503 <8>[ 30.801226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11270 15:37:39.644808 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11272 15:37:39.680260 /lava-11331379/1/../bin/lava-test-case
11273 15:37:39.711821 <8>[ 30.868513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11274 15:37:39.712127 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11276 15:37:39.741703 /lava-11331379/1/../bin/lava-test-case
11277 15:37:39.769241 <8>[ 30.925926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11278 15:37:39.769569 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11280 15:37:39.802701 /lava-11331379/1/../bin/lava-test-case
11281 15:37:39.837257 <8>[ 30.994260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11282 15:37:39.837579 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11284 15:37:39.860231 /lava-11331379/1/../bin/lava-test-case
11285 15:37:39.890323 <8>[ 31.046855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11286 15:37:39.890672 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11288 15:37:39.926651 /lava-11331379/1/../bin/lava-test-case
11289 15:37:39.960796 <8>[ 31.117332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11290 15:37:39.961132 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11292 15:37:39.982400 /lava-11331379/1/../bin/lava-test-case
11293 15:37:40.013227 <8>[ 31.169961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11294 15:37:40.013541 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11296 15:37:40.056250 /lava-11331379/1/../bin/lava-test-case
11297 15:37:40.086661 <8>[ 31.243370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11298 15:37:40.086984 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11300 15:37:40.109364 /lava-11331379/1/../bin/lava-test-case
11301 15:37:40.140118 <8>[ 31.296839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11302 15:37:40.140421 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11304 15:37:40.177530 /lava-11331379/1/../bin/lava-test-case
11305 15:37:40.212565 <8>[ 31.369360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11306 15:37:40.212912 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11308 15:37:40.235487 /lava-11331379/1/../bin/lava-test-case
11309 15:37:40.266668 <8>[ 31.423645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11310 15:37:40.266980 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11312 15:37:40.306423 /lava-11331379/1/../bin/lava-test-case
11313 15:37:40.339709 <8>[ 31.496478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11314 15:37:40.340031 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11316 15:37:40.368190 /lava-11331379/1/../bin/lava-test-case
11317 15:37:40.396095 <8>[ 31.553139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11318 15:37:40.396424 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11320 15:37:40.432159 /lava-11331379/1/../bin/lava-test-case
11321 15:37:40.462627 <8>[ 31.619773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11322 15:37:40.462934 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11324 15:37:40.498104 /lava-11331379/1/../bin/lava-test-case
11325 15:37:40.528527 <8>[ 31.685518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11326 15:37:40.528848 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11328 15:37:40.550976 /lava-11331379/1/../bin/lava-test-case
11329 15:37:40.579459 <8>[ 31.736477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11330 15:37:40.579791 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11332 15:37:40.618165 /lava-11331379/1/../bin/lava-test-case
11333 15:37:40.651136 <8>[ 31.808346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11334 15:37:40.651461 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11336 15:37:40.681158 /lava-11331379/1/../bin/lava-test-case
11337 15:37:40.711841 <8>[ 31.868521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11338 15:37:40.712179 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11340 15:37:40.746094 /lava-11331379/1/../bin/lava-test-case
11341 15:37:40.779529 <8>[ 31.936233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11342 15:37:40.779834 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11344 15:37:40.815898 /lava-11331379/1/../bin/lava-test-case
11345 15:37:40.847476 <8>[ 32.004132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11346 15:37:40.847813 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11348 15:37:40.885084 /lava-11331379/1/../bin/lava-test-case
11349 15:37:40.917239 <8>[ 32.074181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11350 15:37:40.917567 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11352 15:37:40.950144 /lava-11331379/1/../bin/lava-test-case
11353 15:37:40.986538 <8>[ 32.143570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11354 15:37:40.986858 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11356 15:37:41.028799 /lava-11331379/1/../bin/lava-test-case
11357 15:37:41.057296 <8>[ 32.214313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11358 15:37:41.057666 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11360 15:37:41.080205 /lava-11331379/1/../bin/lava-test-case
11361 15:37:41.111280 <8>[ 32.268472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11362 15:37:41.111636 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11364 15:37:41.147411 /lava-11331379/1/../bin/lava-test-case
11365 15:37:41.178377 <8>[ 32.335521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11366 15:37:41.178686 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11368 15:37:41.212850 /lava-11331379/1/../bin/lava-test-case
11369 15:37:41.244030 <8>[ 32.401200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11370 15:37:41.244352 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11372 15:37:41.268880 /lava-11331379/1/../bin/lava-test-case
11373 15:37:41.302918 <8>[ 32.459854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11374 15:37:41.303242 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11376 15:37:41.337865 /lava-11331379/1/../bin/lava-test-case
11377 15:37:41.367984 <8>[ 32.525139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11378 15:37:41.368299 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11380 15:37:41.397286 /lava-11331379/1/../bin/lava-test-case
11381 15:37:41.427194 <8>[ 32.584300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11382 15:37:41.427508 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11384 15:37:41.463117 /lava-11331379/1/../bin/lava-test-case
11385 15:37:41.496391 <8>[ 32.653319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11386 15:37:41.496723 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11388 15:37:41.519443 /lava-11331379/1/../bin/lava-test-case
11389 15:37:41.552978 <8>[ 32.710141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11390 15:37:41.553293 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11392 15:37:41.588824 /lava-11331379/1/../bin/lava-test-case
11393 15:37:41.620998 <8>[ 32.777854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11394 15:37:41.621329 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11396 15:37:41.656832 /lava-11331379/1/../bin/lava-test-case
11397 15:37:41.688324 <8>[ 32.845113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11398 15:37:41.688651 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11400 15:37:41.729178 /lava-11331379/1/../bin/lava-test-case
11401 15:37:41.759862 <8>[ 32.916672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11402 15:37:41.760198 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11404 15:37:41.795002 /lava-11331379/1/../bin/lava-test-case
11405 15:37:41.825240 <8>[ 32.982239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11406 15:37:41.825554 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11408 15:37:41.862111 /lava-11331379/1/../bin/lava-test-case
11409 15:37:41.895922 <8>[ 33.052884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11410 15:37:41.896245 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11412 15:37:41.931658 /lava-11331379/1/../bin/lava-test-case
11413 15:37:41.961906 <8>[ 33.119004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11414 15:37:41.962210 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11416 15:37:41.997246 /lava-11331379/1/../bin/lava-test-case
11417 15:37:42.029169 <8>[ 33.186148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11418 15:37:42.029495 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11420 15:37:42.072857 /lava-11331379/1/../bin/lava-test-case
11421 15:37:42.103896 <8>[ 33.260618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11422 15:37:42.104224 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11424 15:37:42.139841 /lava-11331379/1/../bin/lava-test-case
11425 15:37:42.171128 <8>[ 33.328285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11426 15:37:42.171454 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11428 15:37:42.206477 /lava-11331379/1/../bin/lava-test-case
11429 15:37:42.240234 <8>[ 33.396930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11430 15:37:42.240555 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11432 15:37:42.278410 /lava-11331379/1/../bin/lava-test-case
11433 15:37:42.310351 <8>[ 33.467712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11434 15:37:42.310702 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11436 15:37:42.350268 /lava-11331379/1/../bin/lava-test-case
11437 15:37:42.385284 <8>[ 33.542534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11438 15:37:42.385602 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11440 15:37:42.427853 /lava-11331379/1/../bin/lava-test-case
11441 15:37:42.460070 <8>[ 33.617316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11442 15:37:42.460409 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11444 15:37:42.500726 /lava-11331379/1/../bin/lava-test-case
11445 15:37:42.533130 <8>[ 33.690150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11446 15:37:42.533450 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11448 15:37:42.572145 /lava-11331379/1/../bin/lava-test-case
11449 15:37:42.606321 <8>[ 33.763480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11450 15:37:42.606647 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11452 15:37:42.628608 /lava-11331379/1/../bin/lava-test-case
11453 15:37:42.663330 <8>[ 33.820700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11454 15:37:42.663690 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11456 15:37:42.699501 /lava-11331379/1/../bin/lava-test-case
11457 15:37:42.733539 <8>[ 33.890576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11458 15:37:42.733857 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11460 15:37:42.763201 /lava-11331379/1/../bin/lava-test-case
11461 15:37:42.794552 <8>[ 33.951654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11462 15:37:42.794887 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11464 15:37:42.830953 /lava-11331379/1/../bin/lava-test-case
11465 15:37:42.862514 <8>[ 34.019859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11466 15:37:42.862820 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11468 15:37:42.887522 /lava-11331379/1/../bin/lava-test-case
11469 15:37:42.919286 <8>[ 34.076421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11470 15:37:42.919643 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11472 15:37:42.961461 /lava-11331379/1/../bin/lava-test-case
11473 15:37:42.995758 <8>[ 34.152971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11474 15:37:42.996074 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11476 15:37:43.021553 /lava-11331379/1/../bin/lava-test-case
11477 15:37:43.054164 <8>[ 34.211491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11478 15:37:43.054471 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11480 15:37:43.096807 /lava-11331379/1/../bin/lava-test-case
11481 15:37:43.132483 <8>[ 34.289675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11482 15:37:43.132794 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11484 15:37:43.157649 /lava-11331379/1/../bin/lava-test-case
11485 15:37:43.189230 <8>[ 34.346401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11486 15:37:43.189530 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11488 15:37:43.228734 /lava-11331379/1/../bin/lava-test-case
11489 15:37:43.260715 <8>[ 34.417992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11490 15:37:43.261011 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11492 15:37:43.285147 /lava-11331379/1/../bin/lava-test-case
11493 15:37:43.317106 <8>[ 34.474310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11494 15:37:43.317412 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11496 15:37:43.353578 /lava-11331379/1/../bin/lava-test-case
11497 15:37:43.383898 <8>[ 34.541245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11498 15:37:43.384234 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11500 15:37:43.429732 /lava-11331379/1/../bin/lava-test-case
11501 15:37:43.463562 <8>[ 34.620424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11502 15:37:43.463870 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11504 15:37:43.485571 /lava-11331379/1/../bin/lava-test-case
11505 15:37:43.516663 <8>[ 34.673988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11506 15:37:43.516969 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11508 15:37:43.554563 /lava-11331379/1/../bin/lava-test-case
11509 15:37:43.588464 <8>[ 34.745508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11510 15:37:43.588775 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11512 15:37:43.612240 /lava-11331379/1/../bin/lava-test-case
11513 15:37:43.644593 <8>[ 34.801591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11514 15:37:43.644896 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11516 15:37:43.682419 /lava-11331379/1/../bin/lava-test-case
11517 15:37:43.715557 <8>[ 34.872923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11518 15:37:43.715879 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11520 15:37:43.745870 /lava-11331379/1/../bin/lava-test-case
11521 15:37:43.776417 <8>[ 34.933647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11522 15:37:43.776723 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11524 15:37:44.835958 /lava-11331379/1/../bin/lava-test-case
11525 15:37:44.871484 <8>[ 36.028476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11526 15:37:44.871794 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11528 15:37:44.894268 /lava-11331379/1/../bin/lava-test-case
11529 15:37:44.927859 <8>[ 36.085431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11530 15:37:44.928143 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11532 15:37:45.980185 /lava-11331379/1/../bin/lava-test-case
11533 15:37:46.014520 <8>[ 37.172095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11534 15:37:46.014862 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11536 15:37:46.038149 /lava-11331379/1/../bin/lava-test-case
11537 15:37:46.071046 <8>[ 37.228365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11538 15:37:46.071351 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11540 15:37:47.127163 /lava-11331379/1/../bin/lava-test-case
11541 15:37:47.161065 <8>[ 38.318761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11542 15:37:47.161387 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11544 15:37:47.185327 /lava-11331379/1/../bin/lava-test-case
11545 15:37:47.216934 <8>[ 38.374883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11546 15:37:47.217267 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11548 15:37:48.267356 /lava-11331379/1/../bin/lava-test-case
11549 15:37:48.304030 <8>[ 39.462028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11550 15:37:48.304327 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11552 15:37:48.329154 /lava-11331379/1/../bin/lava-test-case
11553 15:37:48.362655 <8>[ 39.520360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11554 15:37:48.362919 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11556 15:37:49.412201 /lava-11331379/1/../bin/lava-test-case
11557 15:37:49.445669 <8>[ 40.603522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11558 15:37:49.445967 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11560 15:37:49.469313 /lava-11331379/1/../bin/lava-test-case
11561 15:37:49.503532 <8>[ 40.661213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11562 15:37:49.503878 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11564 15:37:50.554743 /lava-11331379/1/../bin/lava-test-case
11565 15:37:50.588866 <8>[ 41.746670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11566 15:37:50.589164 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11568 15:37:50.612383 /lava-11331379/1/../bin/lava-test-case
11569 15:37:50.644408 <8>[ 41.802682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11570 15:37:50.644689 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11572 15:37:51.695835 /lava-11331379/1/../bin/lava-test-case
11573 15:37:51.730489 <8>[ 42.888738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11574 15:37:51.730791 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11576 15:37:51.752037 /lava-11331379/1/../bin/lava-test-case
11577 15:37:51.786600 <8>[ 42.944790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11578 15:37:51.786876 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11580 15:37:51.811156 /lava-11331379/1/../bin/lava-test-case
11581 15:37:51.842999 <8>[ 43.001530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11582 15:37:51.843296 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11584 15:37:52.893081 /lava-11331379/1/../bin/lava-test-case
11585 15:37:52.927139 <8>[ 44.085517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11586 15:37:52.927419 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11588 15:37:52.950977 /lava-11331379/1/../bin/lava-test-case
11589 15:37:52.982640 <8>[ 44.141140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11590 15:37:52.982937 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11592 15:37:53.020122 /lava-11331379/1/../bin/lava-test-case
11593 15:37:53.054690 <8>[ 44.212873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11594 15:37:53.054987 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11596 15:37:53.079354 /lava-11331379/1/../bin/lava-test-case
11597 15:37:53.112068 <8>[ 44.270301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11598 15:37:53.112400 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11600 15:37:53.151760 /lava-11331379/1/../bin/lava-test-case
11601 15:37:53.186675 <8>[ 44.344561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11602 15:37:53.186964 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11604 15:37:53.230935 /lava-11331379/1/../bin/lava-test-case
11605 15:37:53.262996 <8>[ 44.421385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11606 15:37:53.263283 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11608 15:37:53.302494 /lava-11331379/1/../bin/lava-test-case
11609 15:37:53.335239 <8>[ 44.493258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11610 15:37:53.335556 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11612 15:37:53.360896 /lava-11331379/1/../bin/lava-test-case
11613 15:37:53.392651 <8>[ 44.550716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11614 15:37:53.392968 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11616 15:37:53.431280 /lava-11331379/1/../bin/lava-test-case
11617 15:37:53.463636 <8>[ 44.621968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11618 15:37:53.463945 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11620 15:37:53.500551 /lava-11331379/1/../bin/lava-test-case
11621 15:37:53.532514 <8>[ 44.690906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11622 15:37:53.532853 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11624 15:37:53.561832 /lava-11331379/1/../bin/lava-test-case
11625 15:37:53.595573 <8>[ 44.754164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11626 15:37:53.595847 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11628 15:37:53.633441 /lava-11331379/1/../bin/lava-test-case
11629 15:37:53.667250 <8>[ 44.825954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11630 15:37:53.667556 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11632 15:37:53.691110 /lava-11331379/1/../bin/lava-test-case
11633 15:37:53.722198 <8>[ 44.880695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11634 15:37:53.722505 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11636 15:37:53.760508 /lava-11331379/1/../bin/lava-test-case
11637 15:37:53.790956 <8>[ 44.949177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11638 15:37:53.791234 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11640 15:37:53.815214 /lava-11331379/1/../bin/lava-test-case
11641 15:37:53.846102 <8>[ 45.004291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11642 15:37:53.846380 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11644 15:37:53.887019 /lava-11331379/1/../bin/lava-test-case
11645 15:37:53.919562 <8>[ 45.078119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11646 15:37:53.919870 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11648 15:37:53.950106 /lava-11331379/1/../bin/lava-test-case
11649 15:37:53.980539 <8>[ 45.138694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11650 15:37:53.980810 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11652 15:37:54.016336 /lava-11331379/1/../bin/lava-test-case
11653 15:37:54.048709 <8>[ 45.207471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11654 15:37:54.049008 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11656 15:37:54.074173 /lava-11331379/1/../bin/lava-test-case
11657 15:37:54.105779 <8>[ 45.264470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11658 15:37:54.106066 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11660 15:37:54.143692 /lava-11331379/1/../bin/lava-test-case
11661 15:37:54.175922 <8>[ 45.334786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11662 15:37:54.176206 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11664 15:37:54.200174 /lava-11331379/1/../bin/lava-test-case
11665 15:37:54.230734 <8>[ 45.389553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11666 15:37:54.231038 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11668 15:37:54.993718 <6>[ 46.158651] vpu: disabling
11669 15:37:54.996924 <6>[ 46.161770] vproc2: disabling
11670 15:37:55.000374 <6>[ 46.165113] vproc1: disabling
11671 15:37:55.004370 <6>[ 46.169373] vaud18: disabling
11672 15:37:55.011466 <6>[ 46.173126] vsram_others: disabling
11673 15:37:55.014232 <6>[ 46.177326] va09: disabling
11674 15:37:55.017892 <6>[ 46.180811] vsram_md: disabling
11675 15:37:55.020913 <6>[ 46.184615] Vgpu: disabling
11676 15:37:55.281491 /lava-11331379/1/../bin/lava-test-case
11677 15:37:55.322657 <8>[ 46.481467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11678 15:37:55.323007 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11680 15:37:56.375252 /lava-11331379/1/../bin/lava-test-case
11681 15:37:56.407510 <8>[ 47.566383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11682 15:37:56.407803 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11684 15:37:56.432513 /lava-11331379/1/../bin/lava-test-case
11685 15:37:56.464664 <8>[ 47.623586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11686 15:37:56.464943 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11688 15:37:56.502027 /lava-11331379/1/../bin/lava-test-case
11689 15:37:56.532386 <8>[ 47.691484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11690 15:37:56.532688 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11692 15:37:56.556388 /lava-11331379/1/../bin/lava-test-case
11693 15:37:56.587787 <8>[ 47.746636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11694 15:37:56.588134 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11696 15:37:56.624124 /lava-11331379/1/../bin/lava-test-case
11697 15:37:56.653671 <8>[ 47.812658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11698 15:37:56.653977 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11700 15:37:56.675163 /lava-11331379/1/../bin/lava-test-case
11701 15:37:56.706256 <8>[ 47.865029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11702 15:37:56.706537 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11704 15:37:56.751414 /lava-11331379/1/../bin/lava-test-case
11705 15:37:56.784791 <8>[ 47.943696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11706 15:37:56.785073 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11708 15:37:56.808271 /lava-11331379/1/../bin/lava-test-case
11709 15:37:56.838561 <8>[ 47.997620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11710 15:37:56.838861 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11712 15:37:56.875987 /lava-11331379/1/../bin/lava-test-case
11713 15:37:56.909079 <8>[ 48.067621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11714 15:37:56.909355 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11716 15:37:56.934178 /lava-11331379/1/../bin/lava-test-case
11717 15:37:56.961565 <8>[ 48.120659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11718 15:37:56.961852 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11720 15:37:56.996949 /lava-11331379/1/../bin/lava-test-case
11721 15:37:57.026463 <8>[ 48.185284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11722 15:37:57.026742 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11724 15:37:57.049455 /lava-11331379/1/../bin/lava-test-case
11725 15:37:57.078736 <8>[ 48.237688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11726 15:37:57.079018 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11728 15:37:57.123325 /lava-11331379/1/../bin/lava-test-case
11729 15:37:57.154622 <8>[ 48.313432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11730 15:37:57.154938 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11732 15:37:57.176029 /lava-11331379/1/../bin/lava-test-case
11733 15:37:57.207823 <8>[ 48.366749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11734 15:37:57.208103 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11736 15:37:57.245008 /lava-11331379/1/../bin/lava-test-case
11737 15:37:57.278034 <8>[ 48.437070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11738 15:37:57.278308 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11740 15:37:57.301594 /lava-11331379/1/../bin/lava-test-case
11741 15:37:57.333280 <8>[ 48.492523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11742 15:37:57.333564 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11744 15:37:57.371682 /lava-11331379/1/../bin/lava-test-case
11745 15:37:57.405853 <8>[ 48.564314] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11746 15:37:57.406157 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11748 15:37:57.435803 /lava-11331379/1/../bin/lava-test-case
11749 15:37:57.467895 <8>[ 48.626739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11750 15:37:57.468177 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11752 15:37:57.503998 /lava-11331379/1/../bin/lava-test-case
11753 15:37:57.536159 <8>[ 48.694918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11754 15:37:57.536448 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11756 15:37:57.559338 /lava-11331379/1/../bin/lava-test-case
11757 15:37:57.591270 <8>[ 48.749887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11758 15:37:57.591618 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11760 15:37:57.627287 /lava-11331379/1/../bin/lava-test-case
11761 15:37:57.659621 <8>[ 48.818199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11762 15:37:57.659903 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11764 15:37:58.695263 /lava-11331379/1/../bin/lava-test-case
11765 15:37:58.728678 <8>[ 49.887858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11766 15:37:58.728983 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11768 15:37:59.767311 /lava-11331379/1/../bin/lava-test-case
11769 15:37:59.801340 <8>[ 50.960276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11770 15:37:59.801636 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11771 15:37:59.801730 Bad test result: blocked
11772 15:37:59.824239 /lava-11331379/1/../bin/lava-test-case
11773 15:37:59.853468 <8>[ 51.012729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11774 15:37:59.853760 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11776 15:38:00.904506 /lava-11331379/1/../bin/lava-test-case
11777 15:38:00.948353 <8>[ 52.106707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11778 15:38:00.949154 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11780 15:38:00.975996 /lava-11331379/1/../bin/lava-test-case
11781 15:38:01.016039 <8>[ 52.174709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11782 15:38:01.016966 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11784 15:38:01.065684 /lava-11331379/1/../bin/lava-test-case
11785 15:38:01.107788 <8>[ 52.266808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11786 15:38:01.108639 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11788 15:38:01.154584 /lava-11331379/1/../bin/lava-test-case
11789 15:38:01.197545 <8>[ 52.355979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11790 15:38:01.198387 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11792 15:38:01.232974 /lava-11331379/1/../bin/lava-test-case
11793 15:38:01.274109 <8>[ 52.432977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11794 15:38:01.274863 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11796 15:38:01.323548 /lava-11331379/1/../bin/lava-test-case
11797 15:38:01.367023 <8>[ 52.525517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11798 15:38:01.367843 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11800 15:38:01.399130 /lava-11331379/1/../bin/lava-test-case
11801 15:38:01.442267 <8>[ 52.600833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11802 15:38:01.443199 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11804 15:38:02.516100 /lava-11331379/1/../bin/lava-test-case
11805 15:38:02.558923 <8>[ 53.717951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11806 15:38:02.559723 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11808 15:38:02.586658 /lava-11331379/1/../bin/lava-test-case
11809 15:38:02.624831 <8>[ 53.783884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11810 15:38:02.625654 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11812 15:38:03.688909 /lava-11331379/1/../bin/lava-test-case
11813 15:38:03.728831 <8>[ 54.888373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11814 15:38:03.729563 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11816 15:38:03.757513 /lava-11331379/1/../bin/lava-test-case
11817 15:38:03.798654 <8>[ 54.957777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11818 15:38:03.799538 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11820 15:38:04.863917 /lava-11331379/1/../bin/lava-test-case
11821 15:38:04.906371 <8>[ 56.065509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11822 15:38:04.907095 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11824 15:38:04.934240 /lava-11331379/1/../bin/lava-test-case
11825 15:38:04.973821 <8>[ 56.133021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11826 15:38:04.974785 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11828 15:38:06.037441 /lava-11331379/1/../bin/lava-test-case
11829 15:38:06.091140 <8>[ 57.250352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11830 15:38:06.091923 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11832 15:38:06.122102 /lava-11331379/1/../bin/lava-test-case
11833 15:38:06.168602 <8>[ 57.328030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11834 15:38:06.169414 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11836 15:38:06.222609 /lava-11331379/1/../bin/lava-test-case
11837 15:38:06.265959 <8>[ 57.425619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11838 15:38:06.266856 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11840 15:38:06.308276 /lava-11331379/1/../bin/lava-test-case
11841 15:38:06.340544 <8>[ 57.500129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11842 15:38:06.340982 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11844 15:38:06.369510 /lava-11331379/1/../bin/lava-test-case
11845 15:38:06.402252 <8>[ 57.562249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11846 15:38:06.402611 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11848 15:38:06.443288 /lava-11331379/1/../bin/lava-test-case
11849 15:38:06.477835 <8>[ 57.637356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11850 15:38:06.478439 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11852 15:38:06.509491 /lava-11331379/1/../bin/lava-test-case
11853 15:38:06.547498 <8>[ 57.707336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11854 15:38:06.548106 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11856 15:38:06.593829 /lava-11331379/1/../bin/lava-test-case
11857 15:38:06.628769 <8>[ 57.788733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11858 15:38:06.629144 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11860 15:38:06.654860 /lava-11331379/1/../bin/lava-test-case
11861 15:38:06.685899 <8>[ 57.845646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11862 15:38:06.686205 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11864 15:38:06.728950 /lava-11331379/1/../bin/lava-test-case
11865 15:38:06.759622 <8>[ 57.919046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11866 15:38:06.760380 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11868 15:38:06.765818 + set +x
11869 15:38:06.769514 Received signal: <ENDRUN> 1_bootrr 11331379_1.6.2.3.5
11870 15:38:06.770002 Ending use of test pattern.
11871 15:38:06.770354 Ending test lava.1_bootrr (11331379_1.6.2.3.5), duration 29.66
11873 15:38:06.772279 <8>[ 57.931917] <LAVA_SIGNAL_ENDRUN 1_bootrr 11331379_1.6.2.3.5>
11874 15:38:06.778916 <LAVA_TEST_RUNNER EXIT>
11875 15:38:06.779586 ok: lava_test_shell seems to have completed
11876 15:38:06.784496 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11877 15:38:06.785198 end: 4.1 lava-test-shell (duration 00:00:30) [common]
11878 15:38:06.785639 end: 4 lava-test-retry (duration 00:00:30) [common]
11879 15:38:06.786088 start: 5 finalize (timeout 00:07:19) [common]
11880 15:38:06.786557 start: 5.1 power-off (timeout 00:00:30) [common]
11881 15:38:06.787288 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11882 15:38:06.877468 >> Command sent successfully.
11883 15:38:06.883862 Returned 0 in 0 seconds
11884 15:38:06.984984 end: 5.1 power-off (duration 00:00:00) [common]
11886 15:38:06.986437 start: 5.2 read-feedback (timeout 00:07:18) [common]
11887 15:38:06.987753 Listened to connection for namespace 'common' for up to 1s
11888 15:38:07.987625 Finalising connection for namespace 'common'
11889 15:38:07.988382 Disconnecting from shell: Finalise
11890 15:38:07.988887 / #
11891 15:38:08.090078 end: 5.2 read-feedback (duration 00:00:01) [common]
11892 15:38:08.090837 end: 5 finalize (duration 00:00:01) [common]
11893 15:38:08.091587 Cleaning after the job
11894 15:38:08.092085 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/ramdisk
11895 15:38:08.104176 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/kernel
11896 15:38:08.141474 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/dtb
11897 15:38:08.141782 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/nfsrootfs
11898 15:38:08.219838 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331379/tftp-deploy-3e8hmdz8/modules
11899 15:38:08.226956 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11331379
11900 15:38:08.601854 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11331379
11901 15:38:08.602035 Job finished correctly