Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 68
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 34
- Errors: 1
1 15:35:02.794137 lava-dispatcher, installed at version: 2023.06
2 15:35:02.794348 start: 0 validate
3 15:35:02.794480 Start time: 2023-08-22 15:35:02.794471+00:00 (UTC)
4 15:35:02.794614 Using caching service: 'http://localhost/cache/?uri=%s'
5 15:35:02.794755 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 15:35:03.064196 Using caching service: 'http://localhost/cache/?uri=%s'
7 15:35:03.065013 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 15:35:19.073227 Using caching service: 'http://localhost/cache/?uri=%s'
9 15:35:19.073947 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 15:35:19.344892 Using caching service: 'http://localhost/cache/?uri=%s'
11 15:35:19.345584 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.45-cip3-31-gbae6b8e9a2cff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 15:35:22.113778 validate duration: 19.32
14 15:35:22.114134 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 15:35:22.114272 start: 1.1 download-retry (timeout 00:10:00) [common]
16 15:35:22.114414 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 15:35:22.114582 Not decompressing ramdisk as can be used compressed.
18 15:35:22.114710 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 15:35:22.114809 saving as /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/ramdisk/rootfs.cpio.gz
20 15:35:22.114924 total size: 26246609 (25 MB)
21 15:35:22.371802 progress 0 % (0 MB)
22 15:35:22.379406 progress 5 % (1 MB)
23 15:35:22.387008 progress 10 % (2 MB)
24 15:35:22.394744 progress 15 % (3 MB)
25 15:35:22.402252 progress 20 % (5 MB)
26 15:35:22.409783 progress 25 % (6 MB)
27 15:35:22.417331 progress 30 % (7 MB)
28 15:35:22.424685 progress 35 % (8 MB)
29 15:35:22.432082 progress 40 % (10 MB)
30 15:35:22.439457 progress 45 % (11 MB)
31 15:35:22.446743 progress 50 % (12 MB)
32 15:35:22.453973 progress 55 % (13 MB)
33 15:35:22.461323 progress 60 % (15 MB)
34 15:35:22.468687 progress 65 % (16 MB)
35 15:35:22.475930 progress 70 % (17 MB)
36 15:35:22.483026 progress 75 % (18 MB)
37 15:35:22.490241 progress 80 % (20 MB)
38 15:35:22.497665 progress 85 % (21 MB)
39 15:35:22.504990 progress 90 % (22 MB)
40 15:35:22.512157 progress 95 % (23 MB)
41 15:35:22.519191 progress 100 % (25 MB)
42 15:35:22.519461 25 MB downloaded in 0.40 s (61.87 MB/s)
43 15:35:22.519618 end: 1.1.1 http-download (duration 00:00:00) [common]
45 15:35:22.519859 end: 1.1 download-retry (duration 00:00:00) [common]
46 15:35:22.519958 start: 1.2 download-retry (timeout 00:10:00) [common]
47 15:35:22.520043 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 15:35:22.520179 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 15:35:22.520271 saving as /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/kernel/Image
50 15:35:22.520365 total size: 49220096 (46 MB)
51 15:35:22.520451 No compression specified
52 15:35:22.521604 progress 0 % (0 MB)
53 15:35:22.535385 progress 5 % (2 MB)
54 15:35:22.549175 progress 10 % (4 MB)
55 15:35:22.562950 progress 15 % (7 MB)
56 15:35:22.576799 progress 20 % (9 MB)
57 15:35:22.590473 progress 25 % (11 MB)
58 15:35:22.604332 progress 30 % (14 MB)
59 15:35:22.618095 progress 35 % (16 MB)
60 15:35:22.631845 progress 40 % (18 MB)
61 15:35:22.646693 progress 45 % (21 MB)
62 15:35:22.660868 progress 50 % (23 MB)
63 15:35:22.674904 progress 55 % (25 MB)
64 15:35:22.688717 progress 60 % (28 MB)
65 15:35:22.702719 progress 65 % (30 MB)
66 15:35:22.715423 progress 70 % (32 MB)
67 15:35:22.728244 progress 75 % (35 MB)
68 15:35:22.742186 progress 80 % (37 MB)
69 15:35:22.755906 progress 85 % (39 MB)
70 15:35:22.769708 progress 90 % (42 MB)
71 15:35:22.783470 progress 95 % (44 MB)
72 15:35:22.797462 progress 100 % (46 MB)
73 15:35:22.797646 46 MB downloaded in 0.28 s (169.29 MB/s)
74 15:35:22.797846 end: 1.2.1 http-download (duration 00:00:00) [common]
76 15:35:22.798217 end: 1.2 download-retry (duration 00:00:00) [common]
77 15:35:22.798336 start: 1.3 download-retry (timeout 00:09:59) [common]
78 15:35:22.798458 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 15:35:22.798630 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 15:35:22.798725 saving as /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/dtb/mt8192-asurada-spherion-r0.dtb
81 15:35:22.798820 total size: 47278 (0 MB)
82 15:35:22.798918 No compression specified
83 15:35:22.800122 progress 69 % (0 MB)
84 15:35:22.800395 progress 100 % (0 MB)
85 15:35:22.800599 0 MB downloaded in 0.00 s (25.38 MB/s)
86 15:35:22.800769 end: 1.3.1 http-download (duration 00:00:00) [common]
88 15:35:22.801153 end: 1.3 download-retry (duration 00:00:00) [common]
89 15:35:22.801266 start: 1.4 download-retry (timeout 00:09:59) [common]
90 15:35:22.801382 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 15:35:22.801525 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.45-cip3-31-gbae6b8e9a2cff/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 15:35:22.801618 saving as /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/modules/modules.tar
93 15:35:22.801706 total size: 8608784 (8 MB)
94 15:35:22.801786 Using unxz to decompress xz
95 15:35:22.806074 progress 0 % (0 MB)
96 15:35:22.827659 progress 5 % (0 MB)
97 15:35:22.849862 progress 10 % (0 MB)
98 15:35:22.876492 progress 15 % (1 MB)
99 15:35:22.902375 progress 20 % (1 MB)
100 15:35:22.928074 progress 25 % (2 MB)
101 15:35:22.954236 progress 30 % (2 MB)
102 15:35:22.980020 progress 35 % (2 MB)
103 15:35:23.008448 progress 40 % (3 MB)
104 15:35:23.034096 progress 45 % (3 MB)
105 15:35:23.061826 progress 50 % (4 MB)
106 15:35:23.088370 progress 55 % (4 MB)
107 15:35:23.113694 progress 60 % (4 MB)
108 15:35:23.137012 progress 65 % (5 MB)
109 15:35:23.162160 progress 70 % (5 MB)
110 15:35:23.187854 progress 75 % (6 MB)
111 15:35:23.214462 progress 80 % (6 MB)
112 15:35:23.244792 progress 85 % (7 MB)
113 15:35:23.272448 progress 90 % (7 MB)
114 15:35:23.300547 progress 95 % (7 MB)
115 15:35:23.326835 progress 100 % (8 MB)
116 15:35:23.334139 8 MB downloaded in 0.53 s (15.42 MB/s)
117 15:35:23.334420 end: 1.4.1 http-download (duration 00:00:01) [common]
119 15:35:23.334685 end: 1.4 download-retry (duration 00:00:01) [common]
120 15:35:23.334777 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 15:35:23.334875 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 15:35:23.334956 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 15:35:23.335042 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 15:35:23.335272 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4
125 15:35:23.335405 makedir: /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin
126 15:35:23.335587 makedir: /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/tests
127 15:35:23.335724 makedir: /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/results
128 15:35:23.335861 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-add-keys
129 15:35:23.336095 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-add-sources
130 15:35:23.336233 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-background-process-start
131 15:35:23.336364 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-background-process-stop
132 15:35:23.336492 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-common-functions
133 15:35:23.336617 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-echo-ipv4
134 15:35:23.336745 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-install-packages
135 15:35:23.336871 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-installed-packages
136 15:35:23.336996 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-os-build
137 15:35:23.337123 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-probe-channel
138 15:35:23.337249 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-probe-ip
139 15:35:23.337375 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-target-ip
140 15:35:23.337502 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-target-mac
141 15:35:23.337626 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-target-storage
142 15:35:23.337755 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-test-case
143 15:35:23.337888 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-test-event
144 15:35:23.338012 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-test-feedback
145 15:35:23.338137 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-test-raise
146 15:35:23.338263 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-test-reference
147 15:35:23.338386 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-test-runner
148 15:35:23.338512 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-test-set
149 15:35:23.338638 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-test-shell
150 15:35:23.338768 Updating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-install-packages (oe)
151 15:35:23.338926 Updating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/bin/lava-installed-packages (oe)
152 15:35:23.339055 Creating /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/environment
153 15:35:23.339160 LAVA metadata
154 15:35:23.339234 - LAVA_JOB_ID=11331377
155 15:35:23.339299 - LAVA_DISPATCHER_IP=192.168.201.1
156 15:35:23.339400 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 15:35:23.339468 skipped lava-vland-overlay
158 15:35:23.339541 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 15:35:23.339618 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 15:35:23.339683 skipped lava-multinode-overlay
161 15:35:23.339754 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 15:35:23.339871 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 15:35:23.339999 Loading test definitions
164 15:35:23.340093 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 15:35:23.340166 Using /lava-11331377 at stage 0
166 15:35:23.340476 uuid=11331377_1.5.2.3.1 testdef=None
167 15:35:23.340563 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 15:35:23.340647 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 15:35:23.341158 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 15:35:23.341376 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 15:35:23.342023 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 15:35:23.342252 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 15:35:23.342862 runner path: /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11331377_1.5.2.3.1
176 15:35:23.343017 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 15:35:23.343216 Creating lava-test-runner.conf files
179 15:35:23.343278 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11331377/lava-overlay-cznuq6q4/lava-11331377/0 for stage 0
180 15:35:23.343366 - 0_v4l2-compliance-mtk-vcodec-enc
181 15:35:23.343461 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 15:35:23.343548 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 15:35:23.350291 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 15:35:23.350402 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 15:35:23.350487 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 15:35:23.350572 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 15:35:23.350662 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 15:35:24.075671 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 15:35:24.076130 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 15:35:24.076265 extracting modules file /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11331377/extract-overlay-ramdisk-r0ywed1k/ramdisk
191 15:35:24.319575 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 15:35:24.319747 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 15:35:24.319846 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11331377/compress-overlay-7jqsumk3/overlay-1.5.2.4.tar.gz to ramdisk
194 15:35:24.319960 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11331377/compress-overlay-7jqsumk3/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11331377/extract-overlay-ramdisk-r0ywed1k/ramdisk
195 15:35:24.327205 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 15:35:24.327319 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 15:35:24.327414 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 15:35:24.327503 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 15:35:24.327585 Building ramdisk /var/lib/lava/dispatcher/tmp/11331377/extract-overlay-ramdisk-r0ywed1k/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11331377/extract-overlay-ramdisk-r0ywed1k/ramdisk
200 15:35:24.960898 >> 228241 blocks
201 15:35:28.964552 rename /var/lib/lava/dispatcher/tmp/11331377/extract-overlay-ramdisk-r0ywed1k/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/ramdisk/ramdisk.cpio.gz
202 15:35:28.965002 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 15:35:28.965138 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 15:35:28.965242 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 15:35:28.965353 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/kernel/Image'
206 15:35:42.350730 Returned 0 in 13 seconds
207 15:35:42.451455 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/kernel/image.itb
208 15:35:43.091977 output: FIT description: Kernel Image image with one or more FDT blobs
209 15:35:43.092438 output: Created: Tue Aug 22 16:35:42 2023
210 15:35:43.092559 output: Image 0 (kernel-1)
211 15:35:43.092658 output: Description:
212 15:35:43.092752 output: Created: Tue Aug 22 16:35:42 2023
213 15:35:43.092850 output: Type: Kernel Image
214 15:35:43.092944 output: Compression: lzma compressed
215 15:35:43.093040 output: Data Size: 11035343 Bytes = 10776.70 KiB = 10.52 MiB
216 15:35:43.093135 output: Architecture: AArch64
217 15:35:43.093226 output: OS: Linux
218 15:35:43.093317 output: Load Address: 0x00000000
219 15:35:43.093404 output: Entry Point: 0x00000000
220 15:35:43.093491 output: Hash algo: crc32
221 15:35:43.093576 output: Hash value: fe81bcf6
222 15:35:43.093664 output: Image 1 (fdt-1)
223 15:35:43.093750 output: Description: mt8192-asurada-spherion-r0
224 15:35:43.093837 output: Created: Tue Aug 22 16:35:42 2023
225 15:35:43.093933 output: Type: Flat Device Tree
226 15:35:43.094018 output: Compression: uncompressed
227 15:35:43.094103 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 15:35:43.094190 output: Architecture: AArch64
229 15:35:43.094274 output: Hash algo: crc32
230 15:35:43.094359 output: Hash value: cc4352de
231 15:35:43.094444 output: Image 2 (ramdisk-1)
232 15:35:43.094530 output: Description: unavailable
233 15:35:43.094616 output: Created: Tue Aug 22 16:35:42 2023
234 15:35:43.094702 output: Type: RAMDisk Image
235 15:35:43.094788 output: Compression: Unknown Compression
236 15:35:43.094875 output: Data Size: 39335928 Bytes = 38413.99 KiB = 37.51 MiB
237 15:35:43.094961 output: Architecture: AArch64
238 15:35:43.095046 output: OS: Linux
239 15:35:43.095132 output: Load Address: unavailable
240 15:35:43.095218 output: Entry Point: unavailable
241 15:35:43.095304 output: Hash algo: crc32
242 15:35:43.095389 output: Hash value: 53ab86f0
243 15:35:43.095475 output: Default Configuration: 'conf-1'
244 15:35:43.095561 output: Configuration 0 (conf-1)
245 15:35:43.095646 output: Description: mt8192-asurada-spherion-r0
246 15:35:43.095729 output: Kernel: kernel-1
247 15:35:43.095814 output: Init Ramdisk: ramdisk-1
248 15:35:43.095899 output: FDT: fdt-1
249 15:35:43.096024 output: Loadables: kernel-1
250 15:35:43.096111 output:
251 15:35:43.096383 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 15:35:43.096530 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 15:35:43.096676 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 15:35:43.096814 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 15:35:43.096928 No LXC device requested
256 15:35:43.097048 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 15:35:43.097183 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 15:35:43.097301 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 15:35:43.097408 Checking files for TFTP limit of 4294967296 bytes.
260 15:35:43.098106 end: 1 tftp-deploy (duration 00:00:21) [common]
261 15:35:43.098248 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 15:35:43.098376 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 15:35:43.098548 substitutions:
264 15:35:43.098645 - {DTB}: 11331377/tftp-deploy-kvidpy_w/dtb/mt8192-asurada-spherion-r0.dtb
265 15:35:43.098742 - {INITRD}: 11331377/tftp-deploy-kvidpy_w/ramdisk/ramdisk.cpio.gz
266 15:35:43.098833 - {KERNEL}: 11331377/tftp-deploy-kvidpy_w/kernel/Image
267 15:35:43.098923 - {LAVA_MAC}: None
268 15:35:43.099010 - {PRESEED_CONFIG}: None
269 15:35:43.099098 - {PRESEED_LOCAL}: None
270 15:35:43.099186 - {RAMDISK}: 11331377/tftp-deploy-kvidpy_w/ramdisk/ramdisk.cpio.gz
271 15:35:43.099273 - {ROOT_PART}: None
272 15:35:43.099360 - {ROOT}: None
273 15:35:43.099446 - {SERVER_IP}: 192.168.201.1
274 15:35:43.099530 - {TEE}: None
275 15:35:43.099615 Parsed boot commands:
276 15:35:43.099698 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 15:35:43.099999 Parsed boot commands: tftpboot 192.168.201.1 11331377/tftp-deploy-kvidpy_w/kernel/image.itb 11331377/tftp-deploy-kvidpy_w/kernel/cmdline
278 15:35:43.100132 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 15:35:43.100258 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 15:35:43.100432 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 15:35:43.100564 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 15:35:43.100669 Not connected, no need to disconnect.
283 15:35:43.100779 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 15:35:43.100898 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 15:35:43.101004 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 15:35:43.105884 Setting prompt string to ['lava-test: # ']
287 15:35:43.106389 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 15:35:43.106549 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 15:35:43.106727 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 15:35:43.106879 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 15:35:43.107195 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 15:35:48.241390 >> Command sent successfully.
293 15:35:48.243720 Returned 0 in 5 seconds
294 15:35:48.344232 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 15:35:48.345189 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 15:35:48.345437 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 15:35:48.345668 Setting prompt string to 'Starting depthcharge on Spherion...'
299 15:35:48.345843 Changing prompt to 'Starting depthcharge on Spherion...'
300 15:35:48.346012 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 15:35:48.346635 [Enter `^Ec?' for help]
302 15:35:48.522362
303 15:35:48.522515
304 15:35:48.522582 F0: 102B 0000
305 15:35:48.522645
306 15:35:48.522703 F3: 1001 0000 [0200]
307 15:35:48.525538
308 15:35:48.525624 F3: 1001 0000
309 15:35:48.525691
310 15:35:48.525752 F7: 102D 0000
311 15:35:48.525811
312 15:35:48.528824 F1: 0000 0000
313 15:35:48.528907
314 15:35:48.529028 V0: 0000 0000 [0001]
315 15:35:48.529131
316 15:35:48.532359 00: 0007 8000
317 15:35:48.532481
318 15:35:48.532579 01: 0000 0000
319 15:35:48.532673
320 15:35:48.535809 BP: 0C00 0209 [0000]
321 15:35:48.535958
322 15:35:48.536026 G0: 1182 0000
323 15:35:48.536087
324 15:35:48.539245 EC: 0000 0021 [4000]
325 15:35:48.539326
326 15:35:48.539390 S7: 0000 0000 [0000]
327 15:35:48.539449
328 15:35:48.542851 CC: 0000 0000 [0001]
329 15:35:48.542932
330 15:35:48.542996 T0: 0000 0040 [010F]
331 15:35:48.543056
332 15:35:48.543126 Jump to BL
333 15:35:48.543183
334 15:35:48.569503
335 15:35:48.569623
336 15:35:48.569688
337 15:35:48.576821 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 15:35:48.580086 ARM64: Exception handlers installed.
339 15:35:48.584037 ARM64: Testing exception
340 15:35:48.587858 ARM64: Done test exception
341 15:35:48.593975 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 15:35:48.604321 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 15:35:48.610700 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 15:35:48.620588 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 15:35:48.627442 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 15:35:48.637051 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 15:35:48.647834 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 15:35:48.654340 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 15:35:48.672111 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 15:35:48.675867 WDT: Last reset was cold boot
351 15:35:48.679058 SPI1(PAD0) initialized at 2873684 Hz
352 15:35:48.682447 SPI5(PAD0) initialized at 992727 Hz
353 15:35:48.685747 VBOOT: Loading verstage.
354 15:35:48.692306 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 15:35:48.695483 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 15:35:48.699212 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 15:35:48.701927 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 15:35:48.709396 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 15:35:48.716283 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 15:35:48.727070 read SPI 0x96554 0xa1eb: 4593 us, 9024 KB/s, 72.192 Mbps
361 15:35:48.727170
362 15:35:48.727236
363 15:35:48.737085 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 15:35:48.740727 ARM64: Exception handlers installed.
365 15:35:48.743511 ARM64: Testing exception
366 15:35:48.743598 ARM64: Done test exception
367 15:35:48.751224 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 15:35:48.754312 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 15:35:48.768089 Probing TPM: . done!
370 15:35:48.768220 TPM ready after 0 ms
371 15:35:48.775777 Connected to device vid:did:rid of 1ae0:0028:00
372 15:35:48.782372 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 15:35:48.840951 Initialized TPM device CR50 revision 0
374 15:35:48.852224 tlcl_send_startup: Startup return code is 0
375 15:35:48.852593 TPM: setup succeeded
376 15:35:48.864007 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 15:35:48.872679 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 15:35:48.884940 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 15:35:48.894643 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 15:35:48.898186 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 15:35:48.902514 in-header: 03 07 00 00 08 00 00 00
382 15:35:48.905878 in-data: aa e4 47 04 13 02 00 00
383 15:35:48.909718 Chrome EC: UHEPI supported
384 15:35:48.917112 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 15:35:48.920989 in-header: 03 95 00 00 08 00 00 00
386 15:35:48.924469 in-data: 18 20 20 08 00 00 00 00
387 15:35:48.924922 Phase 1
388 15:35:48.928110 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 15:35:48.935765 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 15:35:48.938803 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 15:35:48.943133 Recovery requested (1009000e)
392 15:35:48.951195 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 15:35:48.956435 tlcl_extend: response is 0
394 15:35:48.965542 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 15:35:48.971339 tlcl_extend: response is 0
396 15:35:48.977951 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 15:35:48.997980 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
398 15:35:49.004605 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 15:35:49.005006
400 15:35:49.005312
401 15:35:49.014691 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 15:35:49.018116 ARM64: Exception handlers installed.
403 15:35:49.021764 ARM64: Testing exception
404 15:35:49.022125 ARM64: Done test exception
405 15:35:49.043213 pmic_efuse_setting: Set efuses in 11 msecs
406 15:35:49.046940 pmwrap_interface_init: Select PMIF_VLD_RDY
407 15:35:49.053717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 15:35:49.056592 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 15:35:49.063587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 15:35:49.067360 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 15:35:49.071418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 15:35:49.078269 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 15:35:49.082468 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 15:35:49.085728 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 15:35:49.090600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 15:35:49.097133 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 15:35:49.100503 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 15:35:49.104282 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 15:35:49.108079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 15:35:49.115739 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 15:35:49.123430 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 15:35:49.127165 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 15:35:49.134538 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 15:35:49.138096 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 15:35:49.145046 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 15:35:49.148637 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 15:35:49.156292 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 15:35:49.159952 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 15:35:49.166966 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 15:35:49.170870 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 15:35:49.177754 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 15:35:49.185620 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 15:35:49.188833 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 15:35:49.192082 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 15:35:49.199375 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 15:35:49.203569 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 15:35:49.206457 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 15:35:49.213512 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 15:35:49.217238 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 15:35:49.224576 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 15:35:49.228243 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 15:35:49.231713 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 15:35:49.238859 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 15:35:49.242424 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 15:35:49.246147 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 15:35:49.249865 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 15:35:49.257129 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 15:35:49.260363 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 15:35:49.264192 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 15:35:49.267994 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 15:35:49.271962 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 15:35:49.279688 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 15:35:49.283386 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 15:35:49.286759 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 15:35:49.291090 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 15:35:49.294052 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 15:35:49.297722 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 15:35:49.305260 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 15:35:49.316241 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 15:35:49.319727 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 15:35:49.326616 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 15:35:49.338030 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 15:35:49.341221 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 15:35:49.345555 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 15:35:49.348507 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 15:35:49.356460 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x1b
467 15:35:49.364045 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 15:35:49.367290 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 15:35:49.370631 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 15:35:49.381669 [RTC]rtc_get_frequency_meter,154: input=15, output=852
471 15:35:49.391076 [RTC]rtc_get_frequency_meter,154: input=7, output=726
472 15:35:49.400211 [RTC]rtc_get_frequency_meter,154: input=11, output=789
473 15:35:49.409333 [RTC]rtc_get_frequency_meter,154: input=13, output=819
474 15:35:49.419128 [RTC]rtc_get_frequency_meter,154: input=12, output=805
475 15:35:49.428993 [RTC]rtc_get_frequency_meter,154: input=11, output=789
476 15:35:49.438541 [RTC]rtc_get_frequency_meter,154: input=12, output=805
477 15:35:49.441868 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 15:35:49.448995 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 15:35:49.452658 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 15:35:49.455964 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 15:35:49.459578 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 15:35:49.463533 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 15:35:49.466862 ADC[4]: Raw value=904802 ID=7
484 15:35:49.470381 ADC[3]: Raw value=213916 ID=1
485 15:35:49.470772 RAM Code: 0x71
486 15:35:49.473991 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 15:35:49.481987 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 15:35:49.488853 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 15:35:49.496245 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 15:35:49.499639 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 15:35:49.503851 in-header: 03 07 00 00 08 00 00 00
492 15:35:49.507096 in-data: aa e4 47 04 13 02 00 00
493 15:35:49.507521 Chrome EC: UHEPI supported
494 15:35:49.514667 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 15:35:49.518110 in-header: 03 95 00 00 08 00 00 00
496 15:35:49.522101 in-data: 18 20 20 08 00 00 00 00
497 15:35:49.525651 MRC: failed to locate region type 0.
498 15:35:49.533423 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 15:35:49.533817 DRAM-K: Running full calibration
500 15:35:49.541041 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 15:35:49.544489 header.status = 0x0
502 15:35:49.544880 header.version = 0x6 (expected: 0x6)
503 15:35:49.547889 header.size = 0xd00 (expected: 0xd00)
504 15:35:49.552283 header.flags = 0x0
505 15:35:49.558474 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 15:35:49.575883 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 15:35:49.582874 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 15:35:49.583442 dram_init: ddr_geometry: 2
509 15:35:49.586572 [EMI] MDL number = 2
510 15:35:49.590722 [EMI] Get MDL freq = 0
511 15:35:49.591180 dram_init: ddr_type: 0
512 15:35:49.594570 is_discrete_lpddr4: 1
513 15:35:49.597515 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 15:35:49.597936
515 15:35:49.598300
516 15:35:49.598610 [Bian_co] ETT version 0.0.0.1
517 15:35:49.604722 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 15:35:49.605181
519 15:35:49.608923 dramc_set_vcore_voltage set vcore to 650000
520 15:35:49.609366 Read voltage for 800, 4
521 15:35:49.611431 Vio18 = 0
522 15:35:49.611877 Vcore = 650000
523 15:35:49.612276 Vdram = 0
524 15:35:49.615353 Vddq = 0
525 15:35:49.615880 Vmddr = 0
526 15:35:49.618585 dram_init: config_dvfs: 1
527 15:35:49.622150 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 15:35:49.628701 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 15:35:49.632269 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 15:35:49.635546 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 15:35:49.639061 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 15:35:49.642922 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 15:35:49.646477 MEM_TYPE=3, freq_sel=18
534 15:35:49.647016 sv_algorithm_assistance_LP4_1600
535 15:35:49.652955 ============ PULL DRAM RESETB DOWN ============
536 15:35:49.656582 ========== PULL DRAM RESETB DOWN end =========
537 15:35:49.660280 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 15:35:49.662939 ===================================
539 15:35:49.666501 LPDDR4 DRAM CONFIGURATION
540 15:35:49.669956 ===================================
541 15:35:49.673073 EX_ROW_EN[0] = 0x0
542 15:35:49.673499 EX_ROW_EN[1] = 0x0
543 15:35:49.676183 LP4Y_EN = 0x0
544 15:35:49.676607 WORK_FSP = 0x0
545 15:35:49.679848 WL = 0x2
546 15:35:49.680311 RL = 0x2
547 15:35:49.683011 BL = 0x2
548 15:35:49.683436 RPST = 0x0
549 15:35:49.686337 RD_PRE = 0x0
550 15:35:49.686763 WR_PRE = 0x1
551 15:35:49.689647 WR_PST = 0x0
552 15:35:49.690076 DBI_WR = 0x0
553 15:35:49.692929 DBI_RD = 0x0
554 15:35:49.693448 OTF = 0x1
555 15:35:49.696247 ===================================
556 15:35:49.700236 ===================================
557 15:35:49.703605 ANA top config
558 15:35:49.706499 ===================================
559 15:35:49.709583 DLL_ASYNC_EN = 0
560 15:35:49.710012 ALL_SLAVE_EN = 1
561 15:35:49.712823 NEW_RANK_MODE = 1
562 15:35:49.716434 DLL_IDLE_MODE = 1
563 15:35:49.719808 LP45_APHY_COMB_EN = 1
564 15:35:49.720389 TX_ODT_DIS = 1
565 15:35:49.722835 NEW_8X_MODE = 1
566 15:35:49.726191 ===================================
567 15:35:49.729742 ===================================
568 15:35:49.732737 data_rate = 1600
569 15:35:49.736448 CKR = 1
570 15:35:49.739500 DQ_P2S_RATIO = 8
571 15:35:49.742851 ===================================
572 15:35:49.746177 CA_P2S_RATIO = 8
573 15:35:49.746598 DQ_CA_OPEN = 0
574 15:35:49.750274 DQ_SEMI_OPEN = 0
575 15:35:49.753605 CA_SEMI_OPEN = 0
576 15:35:49.756578 CA_FULL_RATE = 0
577 15:35:49.759974 DQ_CKDIV4_EN = 1
578 15:35:49.760400 CA_CKDIV4_EN = 1
579 15:35:49.763686 CA_PREDIV_EN = 0
580 15:35:49.766660 PH8_DLY = 0
581 15:35:49.770655 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 15:35:49.773274 DQ_AAMCK_DIV = 4
583 15:35:49.776696 CA_AAMCK_DIV = 4
584 15:35:49.777121 CA_ADMCK_DIV = 4
585 15:35:49.780098 DQ_TRACK_CA_EN = 0
586 15:35:49.783686 CA_PICK = 800
587 15:35:49.787109 CA_MCKIO = 800
588 15:35:49.790587 MCKIO_SEMI = 0
589 15:35:49.793997 PLL_FREQ = 3068
590 15:35:49.794424 DQ_UI_PI_RATIO = 32
591 15:35:49.797667 CA_UI_PI_RATIO = 0
592 15:35:49.801795 ===================================
593 15:35:49.804793 ===================================
594 15:35:49.809432 memory_type:LPDDR4
595 15:35:49.809951 GP_NUM : 10
596 15:35:49.812248 SRAM_EN : 1
597 15:35:49.812673 MD32_EN : 0
598 15:35:49.815974 ===================================
599 15:35:49.819249 [ANA_INIT] >>>>>>>>>>>>>>
600 15:35:49.823116 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 15:35:49.826750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 15:35:49.827177 ===================================
603 15:35:49.830034 data_rate = 1600,PCW = 0X7600
604 15:35:49.833659 ===================================
605 15:35:49.836892 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 15:35:49.843304 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 15:35:49.849937 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 15:35:49.853430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 15:35:49.856333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 15:35:49.860076 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 15:35:49.863349 [ANA_INIT] flow start
612 15:35:49.863773 [ANA_INIT] PLL >>>>>>>>
613 15:35:49.866815 [ANA_INIT] PLL <<<<<<<<
614 15:35:49.869903 [ANA_INIT] MIDPI >>>>>>>>
615 15:35:49.870338 [ANA_INIT] MIDPI <<<<<<<<
616 15:35:49.873167 [ANA_INIT] DLL >>>>>>>>
617 15:35:49.876305 [ANA_INIT] flow end
618 15:35:49.880146 ============ LP4 DIFF to SE enter ============
619 15:35:49.883220 ============ LP4 DIFF to SE exit ============
620 15:35:49.886587 [ANA_INIT] <<<<<<<<<<<<<
621 15:35:49.889808 [Flow] Enable top DCM control >>>>>
622 15:35:49.893563 [Flow] Enable top DCM control <<<<<
623 15:35:49.896575 Enable DLL master slave shuffle
624 15:35:49.899679 ==============================================================
625 15:35:49.903072 Gating Mode config
626 15:35:49.909899 ==============================================================
627 15:35:49.910420 Config description:
628 15:35:49.920160 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 15:35:49.926571 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 15:35:49.933452 SELPH_MODE 0: By rank 1: By Phase
631 15:35:49.936202 ==============================================================
632 15:35:49.939707 GAT_TRACK_EN = 1
633 15:35:49.943182 RX_GATING_MODE = 2
634 15:35:49.946364 RX_GATING_TRACK_MODE = 2
635 15:35:49.949656 SELPH_MODE = 1
636 15:35:49.952806 PICG_EARLY_EN = 1
637 15:35:49.956048 VALID_LAT_VALUE = 1
638 15:35:49.959716 ==============================================================
639 15:35:49.963072 Enter into Gating configuration >>>>
640 15:35:49.966429 Exit from Gating configuration <<<<
641 15:35:49.969510 Enter into DVFS_PRE_config >>>>>
642 15:35:49.982717 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 15:35:49.986000 Exit from DVFS_PRE_config <<<<<
644 15:35:49.989490 Enter into PICG configuration >>>>
645 15:35:49.990021 Exit from PICG configuration <<<<
646 15:35:49.992440 [RX_INPUT] configuration >>>>>
647 15:35:49.995802 [RX_INPUT] configuration <<<<<
648 15:35:50.002463 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 15:35:50.006579 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 15:35:50.012763 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 15:35:50.019494 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 15:35:50.026157 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 15:35:50.032566 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 15:35:50.036404 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 15:35:50.039807 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 15:35:50.042852 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 15:35:50.049260 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 15:35:50.052960 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 15:35:50.056027 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 15:35:50.059469 ===================================
661 15:35:50.062611 LPDDR4 DRAM CONFIGURATION
662 15:35:50.065794 ===================================
663 15:35:50.069615 EX_ROW_EN[0] = 0x0
664 15:35:50.070529 EX_ROW_EN[1] = 0x0
665 15:35:50.072534 LP4Y_EN = 0x0
666 15:35:50.072963 WORK_FSP = 0x0
667 15:35:50.075998 WL = 0x2
668 15:35:50.076460 RL = 0x2
669 15:35:50.079756 BL = 0x2
670 15:35:50.080264 RPST = 0x0
671 15:35:50.082242 RD_PRE = 0x0
672 15:35:50.082688 WR_PRE = 0x1
673 15:35:50.086226 WR_PST = 0x0
674 15:35:50.086667 DBI_WR = 0x0
675 15:35:50.089561 DBI_RD = 0x0
676 15:35:50.090081 OTF = 0x1
677 15:35:50.092459 ===================================
678 15:35:50.096164 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 15:35:50.102447 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 15:35:50.106232 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 15:35:50.109433 ===================================
682 15:35:50.112793 LPDDR4 DRAM CONFIGURATION
683 15:35:50.116307 ===================================
684 15:35:50.116773 EX_ROW_EN[0] = 0x10
685 15:35:50.119428 EX_ROW_EN[1] = 0x0
686 15:35:50.122263 LP4Y_EN = 0x0
687 15:35:50.122799 WORK_FSP = 0x0
688 15:35:50.125728 WL = 0x2
689 15:35:50.126191 RL = 0x2
690 15:35:50.129002 BL = 0x2
691 15:35:50.129428 RPST = 0x0
692 15:35:50.132563 RD_PRE = 0x0
693 15:35:50.133024 WR_PRE = 0x1
694 15:35:50.135579 WR_PST = 0x0
695 15:35:50.136217 DBI_WR = 0x0
696 15:35:50.139205 DBI_RD = 0x0
697 15:35:50.139628 OTF = 0x1
698 15:35:50.142302 ===================================
699 15:35:50.148644 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 15:35:50.152774 nWR fixed to 40
701 15:35:50.156366 [ModeRegInit_LP4] CH0 RK0
702 15:35:50.156786 [ModeRegInit_LP4] CH0 RK1
703 15:35:50.159696 [ModeRegInit_LP4] CH1 RK0
704 15:35:50.163117 [ModeRegInit_LP4] CH1 RK1
705 15:35:50.163534 match AC timing 13
706 15:35:50.169769 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 15:35:50.172801 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 15:35:50.176505 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 15:35:50.182814 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 15:35:50.186335 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 15:35:50.186754 [EMI DOE] emi_dcm 0
712 15:35:50.193183 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 15:35:50.193672 ==
714 15:35:50.196670 Dram Type= 6, Freq= 0, CH_0, rank 0
715 15:35:50.200146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 15:35:50.200695 ==
717 15:35:50.206442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 15:35:50.213198 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 15:35:50.220614 [CA 0] Center 38 (7~69) winsize 63
720 15:35:50.224049 [CA 1] Center 37 (6~68) winsize 63
721 15:35:50.227360 [CA 2] Center 34 (4~65) winsize 62
722 15:35:50.230646 [CA 3] Center 34 (4~65) winsize 62
723 15:35:50.234156 [CA 4] Center 33 (3~64) winsize 62
724 15:35:50.237833 [CA 5] Center 33 (3~64) winsize 62
725 15:35:50.238260
726 15:35:50.240510 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 15:35:50.240937
728 15:35:50.244239 [CATrainingPosCal] consider 1 rank data
729 15:35:50.247254 u2DelayCellTimex100 = 270/100 ps
730 15:35:50.250684 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
731 15:35:50.254013 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 15:35:50.261002 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 15:35:50.263977 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 15:35:50.267390 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 15:35:50.270926 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 15:35:50.271369
737 15:35:50.273755 CA PerBit enable=1, Macro0, CA PI delay=33
738 15:35:50.274323
739 15:35:50.277180 [CBTSetCACLKResult] CA Dly = 33
740 15:35:50.277627 CS Dly: 6 (0~37)
741 15:35:50.280485 ==
742 15:35:50.280933 Dram Type= 6, Freq= 0, CH_0, rank 1
743 15:35:50.287314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 15:35:50.287759 ==
745 15:35:50.290424 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 15:35:50.297175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 15:35:50.307021 [CA 0] Center 38 (7~69) winsize 63
748 15:35:50.310484 [CA 1] Center 37 (7~68) winsize 62
749 15:35:50.313517 [CA 2] Center 35 (4~66) winsize 63
750 15:35:50.316979 [CA 3] Center 34 (4~65) winsize 62
751 15:35:50.320168 [CA 4] Center 34 (3~65) winsize 63
752 15:35:50.323498 [CA 5] Center 33 (3~64) winsize 62
753 15:35:50.323956
754 15:35:50.326663 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 15:35:50.327113
756 15:35:50.330182 [CATrainingPosCal] consider 2 rank data
757 15:35:50.333387 u2DelayCellTimex100 = 270/100 ps
758 15:35:50.336780 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
759 15:35:50.343440 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 15:35:50.346652 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 15:35:50.349894 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 15:35:50.352978 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 15:35:50.356414 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 15:35:50.356895
765 15:35:50.359982 CA PerBit enable=1, Macro0, CA PI delay=33
766 15:35:50.360463
767 15:35:50.363067 [CBTSetCACLKResult] CA Dly = 33
768 15:35:50.363547 CS Dly: 6 (0~38)
769 15:35:50.366262
770 15:35:50.370032 ----->DramcWriteLeveling(PI) begin...
771 15:35:50.370548 ==
772 15:35:50.373165 Dram Type= 6, Freq= 0, CH_0, rank 0
773 15:35:50.377154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 15:35:50.377623 ==
775 15:35:50.381070 Write leveling (Byte 0): 32 => 32
776 15:35:50.381514 Write leveling (Byte 1): 27 => 27
777 15:35:50.384706 DramcWriteLeveling(PI) end<-----
778 15:35:50.385193
779 15:35:50.385654 ==
780 15:35:50.388286 Dram Type= 6, Freq= 0, CH_0, rank 0
781 15:35:50.392022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 15:35:50.395480 ==
783 15:35:50.395950 [Gating] SW mode calibration
784 15:35:50.402273 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 15:35:50.409171 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 15:35:50.412341 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 15:35:50.415572 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 15:35:50.422788 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 15:35:50.425614 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 15:35:50.429070 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 15:35:50.435593 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 15:35:50.438814 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 15:35:50.442434 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 15:35:50.449027 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 15:35:50.452633 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 15:35:50.455454 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 15:35:50.461926 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 15:35:50.466068 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 15:35:50.468548 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 15:35:50.475648 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 15:35:50.479178 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 15:35:50.482721 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 15:35:50.488713 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 15:35:50.492033 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 15:35:50.495622 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 15:35:50.502529 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 15:35:50.505192 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 15:35:50.509134 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 15:35:50.515501 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 15:35:50.518879 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 15:35:50.522412 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 15:35:50.525321 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
813 15:35:50.531796 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
814 15:35:50.535252 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 15:35:50.538554 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 15:35:50.545428 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 15:35:50.548674 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 15:35:50.551790 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 15:35:50.558348 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
820 15:35:50.561790 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
821 15:35:50.565101 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
822 15:35:50.571882 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 15:35:50.574881 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 15:35:50.578313 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 15:35:50.585617 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 15:35:50.588843 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 15:35:50.591836 0 11 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
828 15:35:50.598691 0 11 8 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
829 15:35:50.601933 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
830 15:35:50.604733 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 15:35:50.611493 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 15:35:50.614777 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 15:35:50.618301 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 15:35:50.625028 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 15:35:50.628423 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 15:35:50.632298 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 15:35:50.638664 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 15:35:50.641625 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 15:35:50.644712 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 15:35:50.648185 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 15:35:50.655172 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 15:35:50.658330 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 15:35:50.665116 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 15:35:50.668649 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 15:35:50.671435 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 15:35:50.674946 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 15:35:50.681252 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 15:35:50.684584 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 15:35:50.688028 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 15:35:50.695122 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 15:35:50.697717 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 15:35:50.701213 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
853 15:35:50.704277 Total UI for P1: 0, mck2ui 16
854 15:35:50.708205 best dqsien dly found for B0: ( 0, 14, 6)
855 15:35:50.714621 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 15:35:50.717682 Total UI for P1: 0, mck2ui 16
857 15:35:50.721095 best dqsien dly found for B1: ( 0, 14, 10)
858 15:35:50.724420 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 15:35:50.727735 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 15:35:50.728208
861 15:35:50.731192 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 15:35:50.734495 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 15:35:50.738519 [Gating] SW calibration Done
864 15:35:50.738950 ==
865 15:35:50.741241 Dram Type= 6, Freq= 0, CH_0, rank 0
866 15:35:50.745309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 15:35:50.745736 ==
868 15:35:50.746074 RX Vref Scan: 0
869 15:35:50.748383
870 15:35:50.748807 RX Vref 0 -> 0, step: 1
871 15:35:50.749148
872 15:35:50.752128 RX Delay -130 -> 252, step: 16
873 15:35:50.755367 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 15:35:50.758840 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 15:35:50.765303 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
876 15:35:50.768515 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
877 15:35:50.772255 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 15:35:50.775208 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 15:35:50.778512 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 15:35:50.785301 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 15:35:50.788940 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 15:35:50.792162 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 15:35:50.795390 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 15:35:50.798475 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 15:35:50.805242 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 15:35:50.808620 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 15:35:50.811513 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 15:35:50.814975 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 15:35:50.815402 ==
890 15:35:50.818371 Dram Type= 6, Freq= 0, CH_0, rank 0
891 15:35:50.824794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 15:35:50.825224 ==
893 15:35:50.825644 DQS Delay:
894 15:35:50.828415 DQS0 = 0, DQS1 = 0
895 15:35:50.828839 DQM Delay:
896 15:35:50.829176 DQM0 = 92, DQM1 = 75
897 15:35:50.832175 DQ Delay:
898 15:35:50.835201 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
899 15:35:50.838476 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
900 15:35:50.842034 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
901 15:35:50.845074 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 15:35:50.845499
903 15:35:50.845834
904 15:35:50.846143 ==
905 15:35:50.848188 Dram Type= 6, Freq= 0, CH_0, rank 0
906 15:35:50.851718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 15:35:50.852198 ==
908 15:35:50.852539
909 15:35:50.852851
910 15:35:50.855101 TX Vref Scan disable
911 15:35:50.855526 == TX Byte 0 ==
912 15:35:50.862297 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 15:35:50.865556 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 15:35:50.865989 == TX Byte 1 ==
915 15:35:50.871565 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
916 15:35:50.875274 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
917 15:35:50.875699 ==
918 15:35:50.878154 Dram Type= 6, Freq= 0, CH_0, rank 0
919 15:35:50.881831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 15:35:50.882360 ==
921 15:35:50.896028 TX Vref=22, minBit 5, minWin=26, winSum=439
922 15:35:50.899520 TX Vref=24, minBit 0, minWin=27, winSum=440
923 15:35:50.902976 TX Vref=26, minBit 3, minWin=27, winSum=446
924 15:35:50.905977 TX Vref=28, minBit 7, minWin=27, winSum=451
925 15:35:50.909591 TX Vref=30, minBit 1, minWin=27, winSum=447
926 15:35:50.912991 TX Vref=32, minBit 7, minWin=27, winSum=450
927 15:35:50.920074 [TxChooseVref] Worse bit 7, Min win 27, Win sum 451, Final Vref 28
928 15:35:50.920508
929 15:35:50.922725 Final TX Range 1 Vref 28
930 15:35:50.923153
931 15:35:50.923493 ==
932 15:35:50.926097 Dram Type= 6, Freq= 0, CH_0, rank 0
933 15:35:50.929537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 15:35:50.929970 ==
935 15:35:50.932488
936 15:35:50.932912
937 15:35:50.933250 TX Vref Scan disable
938 15:35:50.936473 == TX Byte 0 ==
939 15:35:50.939716 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
940 15:35:50.943054 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
941 15:35:50.946321 == TX Byte 1 ==
942 15:35:50.949590 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
943 15:35:50.955950 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
944 15:35:50.956386
945 15:35:50.956798 [DATLAT]
946 15:35:50.957299 Freq=800, CH0 RK0
947 15:35:50.957628
948 15:35:50.959512 DATLAT Default: 0xa
949 15:35:50.959972 0, 0xFFFF, sum = 0
950 15:35:50.963101 1, 0xFFFF, sum = 0
951 15:35:50.963529 2, 0xFFFF, sum = 0
952 15:35:50.965930 3, 0xFFFF, sum = 0
953 15:35:50.969994 4, 0xFFFF, sum = 0
954 15:35:50.970424 5, 0xFFFF, sum = 0
955 15:35:50.972796 6, 0xFFFF, sum = 0
956 15:35:50.973223 7, 0xFFFF, sum = 0
957 15:35:50.976350 8, 0xFFFF, sum = 0
958 15:35:50.976780 9, 0x0, sum = 1
959 15:35:50.977124 10, 0x0, sum = 2
960 15:35:50.979182 11, 0x0, sum = 3
961 15:35:50.979609 12, 0x0, sum = 4
962 15:35:50.982608 best_step = 10
963 15:35:50.983031
964 15:35:50.983360 ==
965 15:35:50.985950 Dram Type= 6, Freq= 0, CH_0, rank 0
966 15:35:50.989684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 15:35:50.990112 ==
968 15:35:50.993155 RX Vref Scan: 1
969 15:35:50.993673
970 15:35:50.996174 Set Vref Range= 32 -> 127
971 15:35:50.996600
972 15:35:50.997027 RX Vref 32 -> 127, step: 1
973 15:35:50.997352
974 15:35:50.999504 RX Delay -111 -> 252, step: 8
975 15:35:50.999997
976 15:35:51.002576 Set Vref, RX VrefLevel [Byte0]: 32
977 15:35:51.005657 [Byte1]: 32
978 15:35:51.006083
979 15:35:51.009352 Set Vref, RX VrefLevel [Byte0]: 33
980 15:35:51.012351 [Byte1]: 33
981 15:35:51.016824
982 15:35:51.017255 Set Vref, RX VrefLevel [Byte0]: 34
983 15:35:51.020501 [Byte1]: 34
984 15:35:51.024532
985 15:35:51.024957 Set Vref, RX VrefLevel [Byte0]: 35
986 15:35:51.027697 [Byte1]: 35
987 15:35:51.031820
988 15:35:51.032296 Set Vref, RX VrefLevel [Byte0]: 36
989 15:35:51.035480 [Byte1]: 36
990 15:35:51.039635
991 15:35:51.043085 Set Vref, RX VrefLevel [Byte0]: 37
992 15:35:51.043571 [Byte1]: 37
993 15:35:51.047549
994 15:35:51.048039 Set Vref, RX VrefLevel [Byte0]: 38
995 15:35:51.050816 [Byte1]: 38
996 15:35:51.055608
997 15:35:51.056192 Set Vref, RX VrefLevel [Byte0]: 39
998 15:35:51.058968 [Byte1]: 39
999 15:35:51.062975
1000 15:35:51.063445 Set Vref, RX VrefLevel [Byte0]: 40
1001 15:35:51.066432 [Byte1]: 40
1002 15:35:51.070897
1003 15:35:51.071326 Set Vref, RX VrefLevel [Byte0]: 41
1004 15:35:51.074256 [Byte1]: 41
1005 15:35:51.077782
1006 15:35:51.078210 Set Vref, RX VrefLevel [Byte0]: 42
1007 15:35:51.081142 [Byte1]: 42
1008 15:35:51.085180
1009 15:35:51.085603 Set Vref, RX VrefLevel [Byte0]: 43
1010 15:35:51.088504 [Byte1]: 43
1011 15:35:51.093066
1012 15:35:51.093818 Set Vref, RX VrefLevel [Byte0]: 44
1013 15:35:51.096209 [Byte1]: 44
1014 15:35:51.100704
1015 15:35:51.101315 Set Vref, RX VrefLevel [Byte0]: 45
1016 15:35:51.104066 [Byte1]: 45
1017 15:35:51.108426
1018 15:35:51.108840 Set Vref, RX VrefLevel [Byte0]: 46
1019 15:35:51.111659 [Byte1]: 46
1020 15:35:51.115983
1021 15:35:51.116400 Set Vref, RX VrefLevel [Byte0]: 47
1022 15:35:51.119386 [Byte1]: 47
1023 15:35:51.123712
1024 15:35:51.124240 Set Vref, RX VrefLevel [Byte0]: 48
1025 15:35:51.127055 [Byte1]: 48
1026 15:35:51.131668
1027 15:35:51.132302 Set Vref, RX VrefLevel [Byte0]: 49
1028 15:35:51.134725 [Byte1]: 49
1029 15:35:51.138842
1030 15:35:51.139249 Set Vref, RX VrefLevel [Byte0]: 50
1031 15:35:51.142549 [Byte1]: 50
1032 15:35:51.146680
1033 15:35:51.147150 Set Vref, RX VrefLevel [Byte0]: 51
1034 15:35:51.150022 [Byte1]: 51
1035 15:35:51.155199
1036 15:35:51.155612 Set Vref, RX VrefLevel [Byte0]: 52
1037 15:35:51.158206 [Byte1]: 52
1038 15:35:51.161961
1039 15:35:51.162365 Set Vref, RX VrefLevel [Byte0]: 53
1040 15:35:51.165111 [Byte1]: 53
1041 15:35:51.169717
1042 15:35:51.170139 Set Vref, RX VrefLevel [Byte0]: 54
1043 15:35:51.172816 [Byte1]: 54
1044 15:35:51.177312
1045 15:35:51.177732 Set Vref, RX VrefLevel [Byte0]: 55
1046 15:35:51.180498 [Byte1]: 55
1047 15:35:51.185162
1048 15:35:51.185582 Set Vref, RX VrefLevel [Byte0]: 56
1049 15:35:51.188061 [Byte1]: 56
1050 15:35:51.192817
1051 15:35:51.193240 Set Vref, RX VrefLevel [Byte0]: 57
1052 15:35:51.195733 [Byte1]: 57
1053 15:35:51.200229
1054 15:35:51.200649 Set Vref, RX VrefLevel [Byte0]: 58
1055 15:35:51.203759 [Byte1]: 58
1056 15:35:51.207781
1057 15:35:51.208252 Set Vref, RX VrefLevel [Byte0]: 59
1058 15:35:51.210841 [Byte1]: 59
1059 15:35:51.215225
1060 15:35:51.215646 Set Vref, RX VrefLevel [Byte0]: 60
1061 15:35:51.218546 [Byte1]: 60
1062 15:35:51.223680
1063 15:35:51.224214 Set Vref, RX VrefLevel [Byte0]: 61
1064 15:35:51.226492 [Byte1]: 61
1065 15:35:51.230708
1066 15:35:51.231220 Set Vref, RX VrefLevel [Byte0]: 62
1067 15:35:51.233970 [Byte1]: 62
1068 15:35:51.238579
1069 15:35:51.239036 Set Vref, RX VrefLevel [Byte0]: 63
1070 15:35:51.241387 [Byte1]: 63
1071 15:35:51.245774
1072 15:35:51.246194 Set Vref, RX VrefLevel [Byte0]: 64
1073 15:35:51.249354 [Byte1]: 64
1074 15:35:51.253712
1075 15:35:51.254173 Set Vref, RX VrefLevel [Byte0]: 65
1076 15:35:51.256855 [Byte1]: 65
1077 15:35:51.261626
1078 15:35:51.262042 Set Vref, RX VrefLevel [Byte0]: 66
1079 15:35:51.264803 [Byte1]: 66
1080 15:35:51.268979
1081 15:35:51.269398 Set Vref, RX VrefLevel [Byte0]: 67
1082 15:35:51.272322 [Byte1]: 67
1083 15:35:51.277000
1084 15:35:51.277411 Set Vref, RX VrefLevel [Byte0]: 68
1085 15:35:51.279632 [Byte1]: 68
1086 15:35:51.284298
1087 15:35:51.284730 Set Vref, RX VrefLevel [Byte0]: 69
1088 15:35:51.287507 [Byte1]: 69
1089 15:35:51.291730
1090 15:35:51.292186 Set Vref, RX VrefLevel [Byte0]: 70
1091 15:35:51.295224 [Byte1]: 70
1092 15:35:51.299361
1093 15:35:51.299772 Set Vref, RX VrefLevel [Byte0]: 71
1094 15:35:51.302759 [Byte1]: 71
1095 15:35:51.307126
1096 15:35:51.307603 Set Vref, RX VrefLevel [Byte0]: 72
1097 15:35:51.310412 [Byte1]: 72
1098 15:35:51.314780
1099 15:35:51.315209 Set Vref, RX VrefLevel [Byte0]: 73
1100 15:35:51.318016 [Byte1]: 73
1101 15:35:51.322609
1102 15:35:51.323153 Set Vref, RX VrefLevel [Byte0]: 74
1103 15:35:51.326006 [Byte1]: 74
1104 15:35:51.330113
1105 15:35:51.330523 Set Vref, RX VrefLevel [Byte0]: 75
1106 15:35:51.333811 [Byte1]: 75
1107 15:35:51.337537
1108 15:35:51.337947 Set Vref, RX VrefLevel [Byte0]: 76
1109 15:35:51.341052 [Byte1]: 76
1110 15:35:51.345217
1111 15:35:51.345778 Final RX Vref Byte 0 = 56 to rank0
1112 15:35:51.349107 Final RX Vref Byte 1 = 59 to rank0
1113 15:35:51.351991 Final RX Vref Byte 0 = 56 to rank1
1114 15:35:51.355466 Final RX Vref Byte 1 = 59 to rank1==
1115 15:35:51.358508 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 15:35:51.365672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 15:35:51.366096 ==
1118 15:35:51.366426 DQS Delay:
1119 15:35:51.366731 DQS0 = 0, DQS1 = 0
1120 15:35:51.368583 DQM Delay:
1121 15:35:51.368998 DQM0 = 88, DQM1 = 76
1122 15:35:51.372326 DQ Delay:
1123 15:35:51.375077 DQ0 =88, DQ1 =88, DQ2 =88, DQ3 =84
1124 15:35:51.378886 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1125 15:35:51.379341 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1126 15:35:51.385249 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1127 15:35:51.385671
1128 15:35:51.386020
1129 15:35:51.391558 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1130 15:35:51.395004 CH0 RK0: MR19=606, MR18=2D27
1131 15:35:51.401680 CH0_RK0: MR19=0x606, MR18=0x2D27, DQSOSC=398, MR23=63, INC=93, DEC=62
1132 15:35:51.402201
1133 15:35:51.404978 ----->DramcWriteLeveling(PI) begin...
1134 15:35:51.405534 ==
1135 15:35:51.408517 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 15:35:51.411811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 15:35:51.412305 ==
1138 15:35:51.415235 Write leveling (Byte 0): 31 => 31
1139 15:35:51.418360 Write leveling (Byte 1): 30 => 30
1140 15:35:51.421717 DramcWriteLeveling(PI) end<-----
1141 15:35:51.422137
1142 15:35:51.422505 ==
1143 15:35:51.424816 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 15:35:51.428090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 15:35:51.428534 ==
1146 15:35:51.431368 [Gating] SW mode calibration
1147 15:35:51.479317 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 15:35:51.480041 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 15:35:51.480860 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 15:35:51.481238 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 15:35:51.481580 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 15:35:51.481884 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 15:35:51.482202 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 15:35:51.482496 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 15:35:51.482797 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 15:35:51.483091 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 15:35:51.523454 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 15:35:51.524008 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 15:35:51.524761 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 15:35:51.525215 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 15:35:51.525602 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 15:35:51.525917 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 15:35:51.526234 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 15:35:51.526598 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 15:35:51.526939 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 15:35:51.527234 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 15:35:51.535037 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1168 15:35:51.536116 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 15:35:51.538087 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 15:35:51.541627 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 15:35:51.544470 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 15:35:51.551292 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 15:35:51.554451 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 15:35:51.557269 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1175 15:35:51.564062 0 9 8 | B1->B0 | 2424 3434 | 1 0 | (0 0) (0 0)
1176 15:35:51.567339 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1177 15:35:51.570879 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 15:35:51.574423 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 15:35:51.581258 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 15:35:51.584049 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 15:35:51.587643 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 15:35:51.594140 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1183 15:35:51.597414 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1184 15:35:51.600577 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1185 15:35:51.606870 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 15:35:51.610812 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 15:35:51.614055 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 15:35:51.621189 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 15:35:51.625132 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 15:35:51.628717 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1191 15:35:51.632203 0 11 8 | B1->B0 | 3030 4545 | 1 0 | (0 0) (0 0)
1192 15:35:51.635707 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 15:35:51.641973 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 15:35:51.645949 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 15:35:51.649781 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 15:35:51.656165 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 15:35:51.659477 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 15:35:51.662688 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1199 15:35:51.669909 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1200 15:35:51.672734 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1201 15:35:51.676462 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 15:35:51.679651 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 15:35:51.686134 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 15:35:51.689926 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 15:35:51.693024 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 15:35:51.699549 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 15:35:51.702629 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 15:35:51.705885 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 15:35:51.713040 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 15:35:51.715916 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 15:35:51.719349 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 15:35:51.726214 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 15:35:51.729640 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 15:35:51.733119 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1215 15:35:51.739115 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 15:35:51.739234 Total UI for P1: 0, mck2ui 16
1217 15:35:51.746282 best dqsien dly found for B0: ( 0, 14, 4)
1218 15:35:51.749474 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 15:35:51.753073 Total UI for P1: 0, mck2ui 16
1220 15:35:51.756066 best dqsien dly found for B1: ( 0, 14, 8)
1221 15:35:51.759279 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1222 15:35:51.762487 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 15:35:51.762570
1224 15:35:51.766182 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1225 15:35:51.769101 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 15:35:51.772951 [Gating] SW calibration Done
1227 15:35:51.773048 ==
1228 15:35:51.775885 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 15:35:51.778913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 15:35:51.782214 ==
1231 15:35:51.782292 RX Vref Scan: 0
1232 15:35:51.782376
1233 15:35:51.785821 RX Vref 0 -> 0, step: 1
1234 15:35:51.785901
1235 15:35:51.789142 RX Delay -130 -> 252, step: 16
1236 15:35:51.792246 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1237 15:35:51.795553 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1238 15:35:51.799269 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1239 15:35:51.802337 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1240 15:35:51.809146 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1241 15:35:51.812218 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1242 15:35:51.815562 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1243 15:35:51.818977 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1244 15:35:51.822556 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1245 15:35:51.828947 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1246 15:35:51.832606 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1247 15:35:51.835319 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1248 15:35:51.838573 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1249 15:35:51.842030 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1250 15:35:51.848310 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1251 15:35:51.851837 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1252 15:35:51.851942 ==
1253 15:35:51.855213 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 15:35:51.858956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 15:35:51.859059 ==
1256 15:35:51.861961 DQS Delay:
1257 15:35:51.862065 DQS0 = 0, DQS1 = 0
1258 15:35:51.862160 DQM Delay:
1259 15:35:51.865542 DQM0 = 86, DQM1 = 78
1260 15:35:51.865647 DQ Delay:
1261 15:35:51.868693 DQ0 =85, DQ1 =93, DQ2 =77, DQ3 =85
1262 15:35:51.872152 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1263 15:35:51.875156 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =69
1264 15:35:51.878326 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1265 15:35:51.878427
1266 15:35:51.878506
1267 15:35:51.878582 ==
1268 15:35:51.881698 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 15:35:51.888990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 15:35:51.889066 ==
1271 15:35:51.889129
1272 15:35:51.889187
1273 15:35:51.889243 TX Vref Scan disable
1274 15:35:51.892026 == TX Byte 0 ==
1275 15:35:51.895396 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1276 15:35:51.902177 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1277 15:35:51.902254 == TX Byte 1 ==
1278 15:35:51.905343 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1279 15:35:51.911898 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1280 15:35:51.911980 ==
1281 15:35:51.915329 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 15:35:51.919143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 15:35:51.919215 ==
1284 15:35:51.931305 TX Vref=22, minBit 0, minWin=27, winSum=443
1285 15:35:51.934640 TX Vref=24, minBit 2, minWin=27, winSum=448
1286 15:35:51.937576 TX Vref=26, minBit 1, minWin=27, winSum=449
1287 15:35:51.940966 TX Vref=28, minBit 2, minWin=27, winSum=453
1288 15:35:51.944319 TX Vref=30, minBit 0, minWin=28, winSum=455
1289 15:35:51.947717 TX Vref=32, minBit 1, minWin=27, winSum=449
1290 15:35:51.954047 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1291 15:35:51.954122
1292 15:35:51.957316 Final TX Range 1 Vref 30
1293 15:35:51.957391
1294 15:35:51.957452 ==
1295 15:35:51.960921 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 15:35:51.964174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 15:35:51.964247 ==
1298 15:35:51.967358
1299 15:35:51.967428
1300 15:35:51.967487 TX Vref Scan disable
1301 15:35:51.971226 == TX Byte 0 ==
1302 15:35:51.974195 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1303 15:35:51.981050 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1304 15:35:51.981135 == TX Byte 1 ==
1305 15:35:51.984161 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1306 15:35:51.990699 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1307 15:35:51.990799
1308 15:35:51.990877 [DATLAT]
1309 15:35:51.990950 Freq=800, CH0 RK1
1310 15:35:51.991022
1311 15:35:51.994137 DATLAT Default: 0xa
1312 15:35:51.994249 0, 0xFFFF, sum = 0
1313 15:35:51.997897 1, 0xFFFF, sum = 0
1314 15:35:51.997997 2, 0xFFFF, sum = 0
1315 15:35:52.001039 3, 0xFFFF, sum = 0
1316 15:35:52.004476 4, 0xFFFF, sum = 0
1317 15:35:52.004595 5, 0xFFFF, sum = 0
1318 15:35:52.007816 6, 0xFFFF, sum = 0
1319 15:35:52.007950 7, 0xFFFF, sum = 0
1320 15:35:52.010812 8, 0xFFFF, sum = 0
1321 15:35:52.010947 9, 0x0, sum = 1
1322 15:35:52.011057 10, 0x0, sum = 2
1323 15:35:52.014409 11, 0x0, sum = 3
1324 15:35:52.014560 12, 0x0, sum = 4
1325 15:35:52.017340 best_step = 10
1326 15:35:52.017488
1327 15:35:52.017613 ==
1328 15:35:52.020914 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 15:35:52.024376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 15:35:52.024703 ==
1331 15:35:52.027931 RX Vref Scan: 0
1332 15:35:52.028253
1333 15:35:52.028485 RX Vref 0 -> 0, step: 1
1334 15:35:52.028744
1335 15:35:52.031269 RX Delay -95 -> 252, step: 8
1336 15:35:52.037798 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1337 15:35:52.041081 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 15:35:52.044372 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1339 15:35:52.047764 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1340 15:35:52.051195 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 15:35:52.057469 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1342 15:35:52.060680 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 15:35:52.064464 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 15:35:52.067588 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1345 15:35:52.070819 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1346 15:35:52.077924 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 15:35:52.081224 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1348 15:35:52.084246 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1349 15:35:52.087488 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1350 15:35:52.094369 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 15:35:52.097440 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1352 15:35:52.097974 ==
1353 15:35:52.100854 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 15:35:52.104332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 15:35:52.104702 ==
1356 15:35:52.107509 DQS Delay:
1357 15:35:52.108127 DQS0 = 0, DQS1 = 0
1358 15:35:52.108623 DQM Delay:
1359 15:35:52.110616 DQM0 = 86, DQM1 = 76
1360 15:35:52.111287 DQ Delay:
1361 15:35:52.114003 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1362 15:35:52.117415 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1363 15:35:52.121056 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1364 15:35:52.124032 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1365 15:35:52.124596
1366 15:35:52.124931
1367 15:35:52.133787 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1368 15:35:52.134574 CH0 RK1: MR19=606, MR18=2E2B
1369 15:35:52.140686 CH0_RK1: MR19=0x606, MR18=0x2E2B, DQSOSC=398, MR23=63, INC=93, DEC=62
1370 15:35:52.143787 [RxdqsGatingPostProcess] freq 800
1371 15:35:52.151088 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 15:35:52.154032 Pre-setting of DQS Precalculation
1373 15:35:52.157544 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 15:35:52.158029 ==
1375 15:35:52.160345 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 15:35:52.163845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 15:35:52.167375 ==
1378 15:35:52.170501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 15:35:52.177611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 15:35:52.185994 [CA 0] Center 36 (6~67) winsize 62
1381 15:35:52.189267 [CA 1] Center 36 (6~67) winsize 62
1382 15:35:52.192765 [CA 2] Center 35 (5~66) winsize 62
1383 15:35:52.196109 [CA 3] Center 34 (4~65) winsize 62
1384 15:35:52.199688 [CA 4] Center 35 (5~66) winsize 62
1385 15:35:52.202984 [CA 5] Center 34 (4~65) winsize 62
1386 15:35:52.203394
1387 15:35:52.205814 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1388 15:35:52.206261
1389 15:35:52.209300 [CATrainingPosCal] consider 1 rank data
1390 15:35:52.212122 u2DelayCellTimex100 = 270/100 ps
1391 15:35:52.215826 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1392 15:35:52.222540 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1393 15:35:52.225849 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1394 15:35:52.229131 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1395 15:35:52.232415 CA4 delay=35 (5~66),Diff = 1 PI (7 cell)
1396 15:35:52.235399 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 15:35:52.236068
1398 15:35:52.238680 CA PerBit enable=1, Macro0, CA PI delay=34
1399 15:35:52.239225
1400 15:35:52.242391 [CBTSetCACLKResult] CA Dly = 34
1401 15:35:52.245533 CS Dly: 4 (0~35)
1402 15:35:52.245944 ==
1403 15:35:52.249286 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 15:35:52.252147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 15:35:52.252605 ==
1406 15:35:52.258495 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 15:35:52.261974 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 15:35:52.272240 [CA 0] Center 36 (6~67) winsize 62
1409 15:35:52.275569 [CA 1] Center 36 (6~67) winsize 62
1410 15:35:52.279254 [CA 2] Center 35 (4~66) winsize 63
1411 15:35:52.282885 [CA 3] Center 34 (4~65) winsize 62
1412 15:35:52.286357 [CA 4] Center 34 (4~65) winsize 62
1413 15:35:52.289751 [CA 5] Center 34 (4~65) winsize 62
1414 15:35:52.290176
1415 15:35:52.293330 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1416 15:35:52.293877
1417 15:35:52.297299 [CATrainingPosCal] consider 2 rank data
1418 15:35:52.300291 u2DelayCellTimex100 = 270/100 ps
1419 15:35:52.304352 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 15:35:52.307980 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 15:35:52.311481 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1422 15:35:52.315217 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 15:35:52.319656 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1424 15:35:52.322259 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 15:35:52.322669
1426 15:35:52.325477 CA PerBit enable=1, Macro0, CA PI delay=34
1427 15:35:52.325892
1428 15:35:52.329210 [CBTSetCACLKResult] CA Dly = 34
1429 15:35:52.329618 CS Dly: 5 (0~37)
1430 15:35:52.329941
1431 15:35:52.332329 ----->DramcWriteLeveling(PI) begin...
1432 15:35:52.336270 ==
1433 15:35:52.336745 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 15:35:52.342104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 15:35:52.342535 ==
1436 15:35:52.345886 Write leveling (Byte 0): 26 => 26
1437 15:35:52.348912 Write leveling (Byte 1): 27 => 27
1438 15:35:52.353042 DramcWriteLeveling(PI) end<-----
1439 15:35:52.353500
1440 15:35:52.353833 ==
1441 15:35:52.355759 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 15:35:52.358807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 15:35:52.359278 ==
1444 15:35:52.362083 [Gating] SW mode calibration
1445 15:35:52.368851 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 15:35:52.372607 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 15:35:52.378965 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 15:35:52.382047 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1449 15:35:52.386049 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 15:35:52.392434 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 15:35:52.395503 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 15:35:52.398941 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 15:35:52.405803 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 15:35:52.408483 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 15:35:52.411991 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 15:35:52.418948 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 15:35:52.421793 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 15:35:52.424727 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 15:35:52.431583 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 15:35:52.434836 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 15:35:52.438413 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 15:35:52.444548 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 15:35:52.448036 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1464 15:35:52.451346 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1465 15:35:52.458172 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 15:35:52.461171 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 15:35:52.464931 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 15:35:52.471247 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 15:35:52.474777 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 15:35:52.477860 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 15:35:52.484885 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 15:35:52.488080 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 15:35:52.491077 0 9 8 | B1->B0 | 3131 3333 | 0 1 | (0 0) (1 1)
1474 15:35:52.497536 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 15:35:52.501081 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 15:35:52.504307 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 15:35:52.510829 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 15:35:52.514386 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 15:35:52.517927 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 15:35:52.524243 0 10 4 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 1)
1481 15:35:52.527404 0 10 8 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
1482 15:35:52.530904 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 15:35:52.537653 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 15:35:52.540653 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 15:35:52.544465 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 15:35:52.547667 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 15:35:52.553938 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 15:35:52.557405 0 11 4 | B1->B0 | 2525 2e2d | 0 1 | (0 0) (0 0)
1489 15:35:52.560666 0 11 8 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
1490 15:35:52.567228 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 15:35:52.571033 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 15:35:52.574326 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 15:35:52.580854 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 15:35:52.583650 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 15:35:52.587787 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 15:35:52.593931 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1497 15:35:52.597413 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 15:35:52.600422 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 15:35:52.607492 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 15:35:52.610355 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 15:35:52.613842 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 15:35:52.620926 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 15:35:52.623857 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 15:35:52.627845 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 15:35:52.634140 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 15:35:52.637457 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 15:35:52.641039 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 15:35:52.646938 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 15:35:52.650366 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 15:35:52.654008 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 15:35:52.660538 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1512 15:35:52.663492 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1513 15:35:52.666987 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 15:35:52.670624 Total UI for P1: 0, mck2ui 16
1515 15:35:52.674044 best dqsien dly found for B0: ( 0, 14, 2)
1516 15:35:52.677031 Total UI for P1: 0, mck2ui 16
1517 15:35:52.680008 best dqsien dly found for B1: ( 0, 14, 4)
1518 15:35:52.683221 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1519 15:35:52.686540 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1520 15:35:52.687084
1521 15:35:52.693547 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1522 15:35:52.696394 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1523 15:35:52.696959 [Gating] SW calibration Done
1524 15:35:52.699866 ==
1525 15:35:52.703391 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 15:35:52.706976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 15:35:52.707559 ==
1528 15:35:52.708093 RX Vref Scan: 0
1529 15:35:52.708582
1530 15:35:52.709670 RX Vref 0 -> 0, step: 1
1531 15:35:52.710212
1532 15:35:52.713087 RX Delay -130 -> 252, step: 16
1533 15:35:52.716598 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1534 15:35:52.719833 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1535 15:35:52.726537 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1536 15:35:52.730044 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1537 15:35:52.733160 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1538 15:35:52.736795 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1539 15:35:52.739493 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1540 15:35:52.746532 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1541 15:35:52.750191 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1542 15:35:52.753186 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1543 15:35:52.756768 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1544 15:35:52.759622 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1545 15:35:52.766154 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1546 15:35:52.769691 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1547 15:35:52.773001 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1548 15:35:52.776151 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1549 15:35:52.776719 ==
1550 15:35:52.779398 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 15:35:52.786299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 15:35:52.786864 ==
1553 15:35:52.787389 DQS Delay:
1554 15:35:52.789379 DQS0 = 0, DQS1 = 0
1555 15:35:52.789951 DQM Delay:
1556 15:35:52.790448 DQM0 = 88, DQM1 = 80
1557 15:35:52.792984 DQ Delay:
1558 15:35:52.795901 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1559 15:35:52.799449 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1560 15:35:52.802975 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1561 15:35:52.806377 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1562 15:35:52.806886
1563 15:35:52.807402
1564 15:35:52.807718 ==
1565 15:35:52.810106 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 15:35:52.812742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 15:35:52.813260 ==
1568 15:35:52.813615
1569 15:35:52.814033
1570 15:35:52.816031 TX Vref Scan disable
1571 15:35:52.816571 == TX Byte 0 ==
1572 15:35:52.822900 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1573 15:35:52.825809 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1574 15:35:52.829445 == TX Byte 1 ==
1575 15:35:52.832697 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1576 15:35:52.835679 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1577 15:35:52.836138 ==
1578 15:35:52.839110 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 15:35:52.843179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 15:35:52.845561 ==
1581 15:35:52.857127 TX Vref=22, minBit 5, minWin=26, winSum=439
1582 15:35:52.860404 TX Vref=24, minBit 4, minWin=26, winSum=442
1583 15:35:52.863973 TX Vref=26, minBit 1, minWin=27, winSum=448
1584 15:35:52.867361 TX Vref=28, minBit 1, minWin=27, winSum=451
1585 15:35:52.870365 TX Vref=30, minBit 2, minWin=27, winSum=454
1586 15:35:52.874157 TX Vref=32, minBit 1, minWin=27, winSum=453
1587 15:35:52.880408 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 30
1588 15:35:52.880964
1589 15:35:52.883783 Final TX Range 1 Vref 30
1590 15:35:52.884440
1591 15:35:52.884813 ==
1592 15:35:52.887464 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 15:35:52.890823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 15:35:52.891274 ==
1595 15:35:52.891720
1596 15:35:52.892251
1597 15:35:52.893707 TX Vref Scan disable
1598 15:35:52.897354 == TX Byte 0 ==
1599 15:35:52.900782 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1600 15:35:52.903988 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1601 15:35:52.907103 == TX Byte 1 ==
1602 15:35:52.910343 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1603 15:35:52.913751 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1604 15:35:52.914170
1605 15:35:52.917500 [DATLAT]
1606 15:35:52.917915 Freq=800, CH1 RK0
1607 15:35:52.918365
1608 15:35:52.921079 DATLAT Default: 0xa
1609 15:35:52.921522 0, 0xFFFF, sum = 0
1610 15:35:52.923494 1, 0xFFFF, sum = 0
1611 15:35:52.923995 2, 0xFFFF, sum = 0
1612 15:35:52.926943 3, 0xFFFF, sum = 0
1613 15:35:52.927369 4, 0xFFFF, sum = 0
1614 15:35:52.930453 5, 0xFFFF, sum = 0
1615 15:35:52.930968 6, 0xFFFF, sum = 0
1616 15:35:52.934503 7, 0xFFFF, sum = 0
1617 15:35:52.934912 8, 0xFFFF, sum = 0
1618 15:35:52.937326 9, 0x0, sum = 1
1619 15:35:52.937766 10, 0x0, sum = 2
1620 15:35:52.940060 11, 0x0, sum = 3
1621 15:35:52.940501 12, 0x0, sum = 4
1622 15:35:52.943811 best_step = 10
1623 15:35:52.944316
1624 15:35:52.944654 ==
1625 15:35:52.947193 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 15:35:52.950399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 15:35:52.950961 ==
1628 15:35:52.953770 RX Vref Scan: 1
1629 15:35:52.954248
1630 15:35:52.954632 Set Vref Range= 32 -> 127
1631 15:35:52.955080
1632 15:35:52.956992 RX Vref 32 -> 127, step: 1
1633 15:35:52.957522
1634 15:35:52.960429 RX Delay -95 -> 252, step: 8
1635 15:35:52.960982
1636 15:35:52.963597 Set Vref, RX VrefLevel [Byte0]: 32
1637 15:35:52.966640 [Byte1]: 32
1638 15:35:52.966936
1639 15:35:52.970013 Set Vref, RX VrefLevel [Byte0]: 33
1640 15:35:52.973187 [Byte1]: 33
1641 15:35:52.977175
1642 15:35:52.977558 Set Vref, RX VrefLevel [Byte0]: 34
1643 15:35:52.980048 [Byte1]: 34
1644 15:35:52.984313
1645 15:35:52.984682 Set Vref, RX VrefLevel [Byte0]: 35
1646 15:35:52.987677 [Byte1]: 35
1647 15:35:52.992397
1648 15:35:52.992722 Set Vref, RX VrefLevel [Byte0]: 36
1649 15:35:52.995731 [Byte1]: 36
1650 15:35:52.999406
1651 15:35:52.999741 Set Vref, RX VrefLevel [Byte0]: 37
1652 15:35:53.002985 [Byte1]: 37
1653 15:35:53.007519
1654 15:35:53.007832 Set Vref, RX VrefLevel [Byte0]: 38
1655 15:35:53.010838 [Byte1]: 38
1656 15:35:53.014843
1657 15:35:53.015278 Set Vref, RX VrefLevel [Byte0]: 39
1658 15:35:53.018290 [Byte1]: 39
1659 15:35:53.022510
1660 15:35:53.022824 Set Vref, RX VrefLevel [Byte0]: 40
1661 15:35:53.026091 [Byte1]: 40
1662 15:35:53.030096
1663 15:35:53.030512 Set Vref, RX VrefLevel [Byte0]: 41
1664 15:35:53.033601 [Byte1]: 41
1665 15:35:53.038003
1666 15:35:53.038302 Set Vref, RX VrefLevel [Byte0]: 42
1667 15:35:53.040721 [Byte1]: 42
1668 15:35:53.045245
1669 15:35:53.045545 Set Vref, RX VrefLevel [Byte0]: 43
1670 15:35:53.051546 [Byte1]: 43
1671 15:35:53.051860
1672 15:35:53.055129 Set Vref, RX VrefLevel [Byte0]: 44
1673 15:35:53.058637 [Byte1]: 44
1674 15:35:53.058937
1675 15:35:53.061656 Set Vref, RX VrefLevel [Byte0]: 45
1676 15:35:53.064843 [Byte1]: 45
1677 15:35:53.068274
1678 15:35:53.068574 Set Vref, RX VrefLevel [Byte0]: 46
1679 15:35:53.071546 [Byte1]: 46
1680 15:35:53.075583
1681 15:35:53.075882 Set Vref, RX VrefLevel [Byte0]: 47
1682 15:35:53.078970 [Byte1]: 47
1683 15:35:53.083199
1684 15:35:53.083496 Set Vref, RX VrefLevel [Byte0]: 48
1685 15:35:53.086702 [Byte1]: 48
1686 15:35:53.091308
1687 15:35:53.091736 Set Vref, RX VrefLevel [Byte0]: 49
1688 15:35:53.094431 [Byte1]: 49
1689 15:35:53.098717
1690 15:35:53.099141 Set Vref, RX VrefLevel [Byte0]: 50
1691 15:35:53.102097 [Byte1]: 50
1692 15:35:53.106491
1693 15:35:53.106911 Set Vref, RX VrefLevel [Byte0]: 51
1694 15:35:53.110198 [Byte1]: 51
1695 15:35:53.114030
1696 15:35:53.114551 Set Vref, RX VrefLevel [Byte0]: 52
1697 15:35:53.117294 [Byte1]: 52
1698 15:35:53.121714
1699 15:35:53.122137 Set Vref, RX VrefLevel [Byte0]: 53
1700 15:35:53.124655 [Byte1]: 53
1701 15:35:53.129145
1702 15:35:53.129566 Set Vref, RX VrefLevel [Byte0]: 54
1703 15:35:53.132594 [Byte1]: 54
1704 15:35:53.136621
1705 15:35:53.137144 Set Vref, RX VrefLevel [Byte0]: 55
1706 15:35:53.139728 [Byte1]: 55
1707 15:35:53.144005
1708 15:35:53.144582 Set Vref, RX VrefLevel [Byte0]: 56
1709 15:35:53.147836 [Byte1]: 56
1710 15:35:53.152246
1711 15:35:53.152669 Set Vref, RX VrefLevel [Byte0]: 57
1712 15:35:53.154879 [Byte1]: 57
1713 15:35:53.159514
1714 15:35:53.160002 Set Vref, RX VrefLevel [Byte0]: 58
1715 15:35:53.162730 [Byte1]: 58
1716 15:35:53.167128
1717 15:35:53.167720 Set Vref, RX VrefLevel [Byte0]: 59
1718 15:35:53.170861 [Byte1]: 59
1719 15:35:53.174887
1720 15:35:53.175419 Set Vref, RX VrefLevel [Byte0]: 60
1721 15:35:53.178072 [Byte1]: 60
1722 15:35:53.182319
1723 15:35:53.182748 Set Vref, RX VrefLevel [Byte0]: 61
1724 15:35:53.185749 [Byte1]: 61
1725 15:35:53.189961
1726 15:35:53.190373 Set Vref, RX VrefLevel [Byte0]: 62
1727 15:35:53.193058 [Byte1]: 62
1728 15:35:53.197397
1729 15:35:53.197806 Set Vref, RX VrefLevel [Byte0]: 63
1730 15:35:53.200870 [Byte1]: 63
1731 15:35:53.205635
1732 15:35:53.206143 Set Vref, RX VrefLevel [Byte0]: 64
1733 15:35:53.208400 [Byte1]: 64
1734 15:35:53.212841
1735 15:35:53.213327 Set Vref, RX VrefLevel [Byte0]: 65
1736 15:35:53.215976 [Byte1]: 65
1737 15:35:53.220503
1738 15:35:53.220913 Set Vref, RX VrefLevel [Byte0]: 66
1739 15:35:53.223740 [Byte1]: 66
1740 15:35:53.227754
1741 15:35:53.228300 Set Vref, RX VrefLevel [Byte0]: 67
1742 15:35:53.231133 [Byte1]: 67
1743 15:35:53.236031
1744 15:35:53.236551 Set Vref, RX VrefLevel [Byte0]: 68
1745 15:35:53.238941 [Byte1]: 68
1746 15:35:53.243109
1747 15:35:53.243570 Set Vref, RX VrefLevel [Byte0]: 69
1748 15:35:53.246159 [Byte1]: 69
1749 15:35:53.250917
1750 15:35:53.251369 Set Vref, RX VrefLevel [Byte0]: 70
1751 15:35:53.253983 [Byte1]: 70
1752 15:35:53.258469
1753 15:35:53.259162 Set Vref, RX VrefLevel [Byte0]: 71
1754 15:35:53.261796 [Byte1]: 71
1755 15:35:53.266036
1756 15:35:53.266467 Set Vref, RX VrefLevel [Byte0]: 72
1757 15:35:53.268957 [Byte1]: 72
1758 15:35:53.273393
1759 15:35:53.273806 Set Vref, RX VrefLevel [Byte0]: 73
1760 15:35:53.276674 [Byte1]: 73
1761 15:35:53.280763
1762 15:35:53.281171 Set Vref, RX VrefLevel [Byte0]: 74
1763 15:35:53.284858 [Byte1]: 74
1764 15:35:53.288391
1765 15:35:53.288902 Final RX Vref Byte 0 = 59 to rank0
1766 15:35:53.291771 Final RX Vref Byte 1 = 58 to rank0
1767 15:35:53.295562 Final RX Vref Byte 0 = 59 to rank1
1768 15:35:53.299088 Final RX Vref Byte 1 = 58 to rank1==
1769 15:35:53.302425 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 15:35:53.308382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 15:35:53.308809 ==
1772 15:35:53.309177 DQS Delay:
1773 15:35:53.309489 DQS0 = 0, DQS1 = 0
1774 15:35:53.311549 DQM Delay:
1775 15:35:53.312054 DQM0 = 87, DQM1 = 81
1776 15:35:53.315100 DQ Delay:
1777 15:35:53.318504 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1778 15:35:53.321567 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1779 15:35:53.325231 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1780 15:35:53.328276 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1781 15:35:53.328739
1782 15:35:53.329070
1783 15:35:53.334570 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1784 15:35:53.338062 CH1 RK0: MR19=606, MR18=1A2D
1785 15:35:53.344589 CH1_RK0: MR19=0x606, MR18=0x1A2D, DQSOSC=398, MR23=63, INC=93, DEC=62
1786 15:35:53.345051
1787 15:35:53.348048 ----->DramcWriteLeveling(PI) begin...
1788 15:35:53.348518 ==
1789 15:35:53.351349 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 15:35:53.354599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 15:35:53.355081 ==
1792 15:35:53.357982 Write leveling (Byte 0): 25 => 25
1793 15:35:53.361374 Write leveling (Byte 1): 26 => 26
1794 15:35:53.364613 DramcWriteLeveling(PI) end<-----
1795 15:35:53.365236
1796 15:35:53.365809 ==
1797 15:35:53.368218 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 15:35:53.371555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 15:35:53.372022 ==
1800 15:35:53.374482 [Gating] SW mode calibration
1801 15:35:53.381430 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 15:35:53.388720 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 15:35:53.391282 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1804 15:35:53.397789 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1805 15:35:53.400982 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 15:35:53.404441 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 15:35:53.410981 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 15:35:53.414606 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 15:35:53.417451 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 15:35:53.421066 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 15:35:53.428079 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 15:35:53.431325 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 15:35:53.434033 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 15:35:53.440881 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 15:35:53.444417 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 15:35:53.447696 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 15:35:53.454243 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 15:35:53.457442 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 15:35:53.460616 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1820 15:35:53.467480 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1821 15:35:53.470864 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1822 15:35:53.473859 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 15:35:53.480984 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 15:35:53.484016 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 15:35:53.487194 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 15:35:53.494287 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 15:35:53.497685 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 15:35:53.500535 0 9 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
1829 15:35:53.507488 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1830 15:35:53.510843 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 15:35:53.513838 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 15:35:53.520695 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 15:35:53.523561 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 15:35:53.527620 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 15:35:53.533949 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 15:35:53.536721 0 10 4 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 1)
1837 15:35:53.540037 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1838 15:35:53.546739 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 15:35:53.550500 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 15:35:53.553902 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 15:35:53.560492 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 15:35:53.563589 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 15:35:53.566690 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 15:35:53.573373 0 11 4 | B1->B0 | 2525 3939 | 1 0 | (0 0) (1 1)
1845 15:35:53.576950 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1846 15:35:53.580087 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 15:35:53.586857 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 15:35:53.589890 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 15:35:53.593250 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 15:35:53.599994 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 15:35:53.603521 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 15:35:53.606476 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1853 15:35:53.612787 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 15:35:53.616273 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 15:35:53.619795 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 15:35:53.623110 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 15:35:53.629422 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 15:35:53.633504 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 15:35:53.636215 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 15:35:53.642759 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 15:35:53.646208 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 15:35:53.649591 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 15:35:53.656090 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 15:35:53.659447 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 15:35:53.663135 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 15:35:53.669191 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 15:35:53.672377 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 15:35:53.675571 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1869 15:35:53.682699 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 15:35:53.685550 Total UI for P1: 0, mck2ui 16
1871 15:35:53.689199 best dqsien dly found for B0: ( 0, 14, 4)
1872 15:35:53.692117 Total UI for P1: 0, mck2ui 16
1873 15:35:53.695851 best dqsien dly found for B1: ( 0, 14, 6)
1874 15:35:53.699395 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1875 15:35:53.702532 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1876 15:35:53.702645
1877 15:35:53.705344 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1878 15:35:53.709018 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1879 15:35:53.711888 [Gating] SW calibration Done
1880 15:35:53.711983 ==
1881 15:35:53.715638 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 15:35:53.718939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 15:35:53.719022 ==
1884 15:35:53.722162 RX Vref Scan: 0
1885 15:35:53.722236
1886 15:35:53.722319 RX Vref 0 -> 0, step: 1
1887 15:35:53.722441
1888 15:35:53.725413 RX Delay -130 -> 252, step: 16
1889 15:35:53.728798 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1890 15:35:53.735541 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1891 15:35:53.739446 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1892 15:35:53.742446 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1893 15:35:53.745374 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1894 15:35:53.749183 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1895 15:35:53.755765 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1896 15:35:53.758800 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1897 15:35:53.762362 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1898 15:35:53.766090 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1899 15:35:53.769015 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1900 15:35:53.775582 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1901 15:35:53.779047 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1902 15:35:53.782267 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1903 15:35:53.785834 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1904 15:35:53.792305 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1905 15:35:53.792781 ==
1906 15:35:53.795564 Dram Type= 6, Freq= 0, CH_1, rank 1
1907 15:35:53.799051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1908 15:35:53.799606 ==
1909 15:35:53.800155 DQS Delay:
1910 15:35:53.802399 DQS0 = 0, DQS1 = 0
1911 15:35:53.802954 DQM Delay:
1912 15:35:53.805391 DQM0 = 84, DQM1 = 83
1913 15:35:53.805885 DQ Delay:
1914 15:35:53.809532 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1915 15:35:53.812367 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1916 15:35:53.815430 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1917 15:35:53.818898 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1918 15:35:53.819346
1919 15:35:53.819815
1920 15:35:53.820244 ==
1921 15:35:53.822613 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 15:35:53.825558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 15:35:53.826010 ==
1924 15:35:53.826597
1925 15:35:53.827061
1926 15:35:53.829151 TX Vref Scan disable
1927 15:35:53.832013 == TX Byte 0 ==
1928 15:35:53.835295 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1929 15:35:53.838963 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1930 15:35:53.841700 == TX Byte 1 ==
1931 15:35:53.845242 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1932 15:35:53.848424 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1933 15:35:53.848722 ==
1934 15:35:53.852102 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 15:35:53.858311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 15:35:53.858699 ==
1937 15:35:53.870363 TX Vref=22, minBit 1, minWin=26, winSum=441
1938 15:35:53.873565 TX Vref=24, minBit 0, minWin=27, winSum=448
1939 15:35:53.876660 TX Vref=26, minBit 2, minWin=27, winSum=454
1940 15:35:53.880162 TX Vref=28, minBit 2, minWin=27, winSum=454
1941 15:35:53.883606 TX Vref=30, minBit 3, minWin=27, winSum=455
1942 15:35:53.890427 TX Vref=32, minBit 2, minWin=27, winSum=453
1943 15:35:53.893271 [TxChooseVref] Worse bit 3, Min win 27, Win sum 455, Final Vref 30
1944 15:35:53.893579
1945 15:35:53.896700 Final TX Range 1 Vref 30
1946 15:35:53.897057
1947 15:35:53.897298 ==
1948 15:35:53.900146 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 15:35:53.903758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 15:35:53.904214 ==
1951 15:35:53.904563
1952 15:35:53.907109
1953 15:35:53.907413 TX Vref Scan disable
1954 15:35:53.910323 == TX Byte 0 ==
1955 15:35:53.914084 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1956 15:35:53.917145 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1957 15:35:53.919864 == TX Byte 1 ==
1958 15:35:53.923457 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1959 15:35:53.926980 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1960 15:35:53.930015
1961 15:35:53.930308 [DATLAT]
1962 15:35:53.930542 Freq=800, CH1 RK1
1963 15:35:53.930762
1964 15:35:53.933390 DATLAT Default: 0xa
1965 15:35:53.933755 0, 0xFFFF, sum = 0
1966 15:35:53.936464 1, 0xFFFF, sum = 0
1967 15:35:53.936814 2, 0xFFFF, sum = 0
1968 15:35:53.939621 3, 0xFFFF, sum = 0
1969 15:35:53.943454 4, 0xFFFF, sum = 0
1970 15:35:53.943716 5, 0xFFFF, sum = 0
1971 15:35:53.946900 6, 0xFFFF, sum = 0
1972 15:35:53.947054 7, 0xFFFF, sum = 0
1973 15:35:53.950197 8, 0xFFFF, sum = 0
1974 15:35:53.950351 9, 0x0, sum = 1
1975 15:35:53.953110 10, 0x0, sum = 2
1976 15:35:53.953264 11, 0x0, sum = 3
1977 15:35:53.953385 12, 0x0, sum = 4
1978 15:35:53.956304 best_step = 10
1979 15:35:53.956454
1980 15:35:53.956572 ==
1981 15:35:53.959590 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 15:35:53.963463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 15:35:53.963616 ==
1984 15:35:53.966639 RX Vref Scan: 0
1985 15:35:53.966793
1986 15:35:53.966978 RX Vref 0 -> 0, step: 1
1987 15:35:53.969705
1988 15:35:53.969858 RX Delay -95 -> 252, step: 8
1989 15:35:53.976756 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1990 15:35:53.979879 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1991 15:35:53.983330 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1992 15:35:53.986771 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1993 15:35:53.989943 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1994 15:35:53.996795 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
1995 15:35:53.999633 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1996 15:35:54.002948 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1997 15:35:54.006441 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1998 15:35:54.009861 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1999 15:35:54.015985 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2000 15:35:54.020200 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2001 15:35:54.023149 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2002 15:35:54.026591 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2003 15:35:54.032743 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2004 15:35:54.036479 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2005 15:35:54.036919 ==
2006 15:35:54.039487 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 15:35:54.042882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 15:35:54.043454 ==
2009 15:35:54.046454 DQS Delay:
2010 15:35:54.047063 DQS0 = 0, DQS1 = 0
2011 15:35:54.047639 DQM Delay:
2012 15:35:54.049604 DQM0 = 87, DQM1 = 83
2013 15:35:54.050216 DQ Delay:
2014 15:35:54.053119 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2015 15:35:54.056670 DQ4 =84, DQ5 =100, DQ6 =96, DQ7 =84
2016 15:35:54.059418 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
2017 15:35:54.063284 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
2018 15:35:54.063899
2019 15:35:54.064384
2020 15:35:54.073009 [DQSOSCAuto] RK1, (LSB)MR18= 0x2541, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2021 15:35:54.076065 CH1 RK1: MR19=606, MR18=2541
2022 15:35:54.079819 CH1_RK1: MR19=0x606, MR18=0x2541, DQSOSC=393, MR23=63, INC=95, DEC=63
2023 15:35:54.082712 [RxdqsGatingPostProcess] freq 800
2024 15:35:54.089398 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2025 15:35:54.092766 Pre-setting of DQS Precalculation
2026 15:35:54.096182 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2027 15:35:54.106252 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2028 15:35:54.112901 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2029 15:35:54.113363
2030 15:35:54.113720
2031 15:35:54.116291 [Calibration Summary] 1600 Mbps
2032 15:35:54.116812 CH 0, Rank 0
2033 15:35:54.119596 SW Impedance : PASS
2034 15:35:54.120130 DUTY Scan : NO K
2035 15:35:54.122576 ZQ Calibration : PASS
2036 15:35:54.126160 Jitter Meter : NO K
2037 15:35:54.126715 CBT Training : PASS
2038 15:35:54.129544 Write leveling : PASS
2039 15:35:54.132752 RX DQS gating : PASS
2040 15:35:54.133214 RX DQ/DQS(RDDQC) : PASS
2041 15:35:54.135837 TX DQ/DQS : PASS
2042 15:35:54.136522 RX DATLAT : PASS
2043 15:35:54.139204 RX DQ/DQS(Engine): PASS
2044 15:35:54.142647 TX OE : NO K
2045 15:35:54.143071 All Pass.
2046 15:35:54.143439
2047 15:35:54.143767 CH 0, Rank 1
2048 15:35:54.145899 SW Impedance : PASS
2049 15:35:54.149276 DUTY Scan : NO K
2050 15:35:54.149794 ZQ Calibration : PASS
2051 15:35:54.152364 Jitter Meter : NO K
2052 15:35:54.155901 CBT Training : PASS
2053 15:35:54.156405 Write leveling : PASS
2054 15:35:54.159151 RX DQS gating : PASS
2055 15:35:54.162699 RX DQ/DQS(RDDQC) : PASS
2056 15:35:54.163159 TX DQ/DQS : PASS
2057 15:35:54.166028 RX DATLAT : PASS
2058 15:35:54.169606 RX DQ/DQS(Engine): PASS
2059 15:35:54.170026 TX OE : NO K
2060 15:35:54.172258 All Pass.
2061 15:35:54.172673
2062 15:35:54.173040 CH 1, Rank 0
2063 15:35:54.175522 SW Impedance : PASS
2064 15:35:54.176189 DUTY Scan : NO K
2065 15:35:54.179512 ZQ Calibration : PASS
2066 15:35:54.182336 Jitter Meter : NO K
2067 15:35:54.182757 CBT Training : PASS
2068 15:35:54.185593 Write leveling : PASS
2069 15:35:54.189257 RX DQS gating : PASS
2070 15:35:54.189714 RX DQ/DQS(RDDQC) : PASS
2071 15:35:54.192333 TX DQ/DQS : PASS
2072 15:35:54.193135 RX DATLAT : PASS
2073 15:35:54.195483 RX DQ/DQS(Engine): PASS
2074 15:35:54.198849 TX OE : NO K
2075 15:35:54.199274 All Pass.
2076 15:35:54.199635
2077 15:35:54.199992 CH 1, Rank 1
2078 15:35:54.202051 SW Impedance : PASS
2079 15:35:54.205745 DUTY Scan : NO K
2080 15:35:54.206168 ZQ Calibration : PASS
2081 15:35:54.209045 Jitter Meter : NO K
2082 15:35:54.212266 CBT Training : PASS
2083 15:35:54.212731 Write leveling : PASS
2084 15:35:54.215473 RX DQS gating : PASS
2085 15:35:54.218692 RX DQ/DQS(RDDQC) : PASS
2086 15:35:54.218971 TX DQ/DQS : PASS
2087 15:35:54.221821 RX DATLAT : PASS
2088 15:35:54.225455 RX DQ/DQS(Engine): PASS
2089 15:35:54.225704 TX OE : NO K
2090 15:35:54.228590 All Pass.
2091 15:35:54.228814
2092 15:35:54.228990 DramC Write-DBI off
2093 15:35:54.232330 PER_BANK_REFRESH: Hybrid Mode
2094 15:35:54.232560 TX_TRACKING: ON
2095 15:35:54.235444 [GetDramInforAfterCalByMRR] Vendor 6.
2096 15:35:54.242084 [GetDramInforAfterCalByMRR] Revision 606.
2097 15:35:54.245338 [GetDramInforAfterCalByMRR] Revision 2 0.
2098 15:35:54.245564 MR0 0x3b3b
2099 15:35:54.245742 MR8 0x5151
2100 15:35:54.248392 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 15:35:54.248640
2102 15:35:54.251981 MR0 0x3b3b
2103 15:35:54.252206 MR8 0x5151
2104 15:35:54.255491 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 15:35:54.255737
2106 15:35:54.265379 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2107 15:35:54.268308 [FAST_K] Save calibration result to emmc
2108 15:35:54.271707 [FAST_K] Save calibration result to emmc
2109 15:35:54.275085 dram_init: config_dvfs: 1
2110 15:35:54.278493 dramc_set_vcore_voltage set vcore to 662500
2111 15:35:54.281790 Read voltage for 1200, 2
2112 15:35:54.282017 Vio18 = 0
2113 15:35:54.282220 Vcore = 662500
2114 15:35:54.284949 Vdram = 0
2115 15:35:54.285174 Vddq = 0
2116 15:35:54.285373 Vmddr = 0
2117 15:35:54.291806 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2118 15:35:54.294847 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2119 15:35:54.298229 MEM_TYPE=3, freq_sel=15
2120 15:35:54.302028 sv_algorithm_assistance_LP4_1600
2121 15:35:54.305218 ============ PULL DRAM RESETB DOWN ============
2122 15:35:54.308747 ========== PULL DRAM RESETB DOWN end =========
2123 15:35:54.315327 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 15:35:54.318531 ===================================
2125 15:35:54.318951 LPDDR4 DRAM CONFIGURATION
2126 15:35:54.322276 ===================================
2127 15:35:54.325114 EX_ROW_EN[0] = 0x0
2128 15:35:54.328569 EX_ROW_EN[1] = 0x0
2129 15:35:54.329036 LP4Y_EN = 0x0
2130 15:35:54.332382 WORK_FSP = 0x0
2131 15:35:54.332799 WL = 0x4
2132 15:35:54.335192 RL = 0x4
2133 15:35:54.335704 BL = 0x2
2134 15:35:54.338408 RPST = 0x0
2135 15:35:54.338864 RD_PRE = 0x0
2136 15:35:54.341781 WR_PRE = 0x1
2137 15:35:54.342242 WR_PST = 0x0
2138 15:35:54.345181 DBI_WR = 0x0
2139 15:35:54.345641 DBI_RD = 0x0
2140 15:35:54.348758 OTF = 0x1
2141 15:35:54.351754 ===================================
2142 15:35:54.355332 ===================================
2143 15:35:54.355792 ANA top config
2144 15:35:54.358749 ===================================
2145 15:35:54.361473 DLL_ASYNC_EN = 0
2146 15:35:54.365017 ALL_SLAVE_EN = 0
2147 15:35:54.368399 NEW_RANK_MODE = 1
2148 15:35:54.368866 DLL_IDLE_MODE = 1
2149 15:35:54.371276 LP45_APHY_COMB_EN = 1
2150 15:35:54.375032 TX_ODT_DIS = 1
2151 15:35:54.378126 NEW_8X_MODE = 1
2152 15:35:54.381504 ===================================
2153 15:35:54.385091 ===================================
2154 15:35:54.388185 data_rate = 2400
2155 15:35:54.388598 CKR = 1
2156 15:35:54.391219 DQ_P2S_RATIO = 8
2157 15:35:54.394567 ===================================
2158 15:35:54.398515 CA_P2S_RATIO = 8
2159 15:35:54.401306 DQ_CA_OPEN = 0
2160 15:35:54.404884 DQ_SEMI_OPEN = 0
2161 15:35:54.407951 CA_SEMI_OPEN = 0
2162 15:35:54.408362 CA_FULL_RATE = 0
2163 15:35:54.411028 DQ_CKDIV4_EN = 0
2164 15:35:54.414434 CA_CKDIV4_EN = 0
2165 15:35:54.417815 CA_PREDIV_EN = 0
2166 15:35:54.421866 PH8_DLY = 17
2167 15:35:54.424163 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2168 15:35:54.424573 DQ_AAMCK_DIV = 4
2169 15:35:54.427541 CA_AAMCK_DIV = 4
2170 15:35:54.431088 CA_ADMCK_DIV = 4
2171 15:35:54.434408 DQ_TRACK_CA_EN = 0
2172 15:35:54.437926 CA_PICK = 1200
2173 15:35:54.440760 CA_MCKIO = 1200
2174 15:35:54.444312 MCKIO_SEMI = 0
2175 15:35:54.444935 PLL_FREQ = 2366
2176 15:35:54.447519 DQ_UI_PI_RATIO = 32
2177 15:35:54.450841 CA_UI_PI_RATIO = 0
2178 15:35:54.454064 ===================================
2179 15:35:54.457428 ===================================
2180 15:35:54.460862 memory_type:LPDDR4
2181 15:35:54.464188 GP_NUM : 10
2182 15:35:54.464686 SRAM_EN : 1
2183 15:35:54.467462 MD32_EN : 0
2184 15:35:54.471236 ===================================
2185 15:35:54.471693 [ANA_INIT] >>>>>>>>>>>>>>
2186 15:35:54.473896 <<<<<< [CONFIGURE PHASE]: ANA_TX
2187 15:35:54.477320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2188 15:35:54.480846 ===================================
2189 15:35:54.484445 data_rate = 2400,PCW = 0X5b00
2190 15:35:54.487510 ===================================
2191 15:35:54.491089 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2192 15:35:54.497410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 15:35:54.504175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 15:35:54.507304 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2195 15:35:54.511101 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2196 15:35:54.514200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2197 15:35:54.517226 [ANA_INIT] flow start
2198 15:35:54.517637 [ANA_INIT] PLL >>>>>>>>
2199 15:35:54.521008 [ANA_INIT] PLL <<<<<<<<
2200 15:35:54.523939 [ANA_INIT] MIDPI >>>>>>>>
2201 15:35:54.524353 [ANA_INIT] MIDPI <<<<<<<<
2202 15:35:54.527596 [ANA_INIT] DLL >>>>>>>>
2203 15:35:54.530625 [ANA_INIT] DLL <<<<<<<<
2204 15:35:54.531163 [ANA_INIT] flow end
2205 15:35:54.537265 ============ LP4 DIFF to SE enter ============
2206 15:35:54.540725 ============ LP4 DIFF to SE exit ============
2207 15:35:54.543861 [ANA_INIT] <<<<<<<<<<<<<
2208 15:35:54.547489 [Flow] Enable top DCM control >>>>>
2209 15:35:54.550504 [Flow] Enable top DCM control <<<<<
2210 15:35:54.551024 Enable DLL master slave shuffle
2211 15:35:54.557219 ==============================================================
2212 15:35:54.560250 Gating Mode config
2213 15:35:54.563521 ==============================================================
2214 15:35:54.567113 Config description:
2215 15:35:54.577119 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2216 15:35:54.583882 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2217 15:35:54.586778 SELPH_MODE 0: By rank 1: By Phase
2218 15:35:54.593500 ==============================================================
2219 15:35:54.596970 GAT_TRACK_EN = 1
2220 15:35:54.600107 RX_GATING_MODE = 2
2221 15:35:54.603279 RX_GATING_TRACK_MODE = 2
2222 15:35:54.603897 SELPH_MODE = 1
2223 15:35:54.606848 PICG_EARLY_EN = 1
2224 15:35:54.610217 VALID_LAT_VALUE = 1
2225 15:35:54.616495 ==============================================================
2226 15:35:54.619969 Enter into Gating configuration >>>>
2227 15:35:54.623403 Exit from Gating configuration <<<<
2228 15:35:54.626799 Enter into DVFS_PRE_config >>>>>
2229 15:35:54.637212 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2230 15:35:54.640010 Exit from DVFS_PRE_config <<<<<
2231 15:35:54.643488 Enter into PICG configuration >>>>
2232 15:35:54.646440 Exit from PICG configuration <<<<
2233 15:35:54.650167 [RX_INPUT] configuration >>>>>
2234 15:35:54.653667 [RX_INPUT] configuration <<<<<
2235 15:35:54.656407 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2236 15:35:54.663055 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2237 15:35:54.669866 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 15:35:54.676213 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 15:35:54.683431 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 15:35:54.686897 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 15:35:54.692989 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2242 15:35:54.696360 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2243 15:35:54.699447 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2244 15:35:54.702997 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2245 15:35:54.709600 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2246 15:35:54.712899 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2247 15:35:54.716710 ===================================
2248 15:35:54.719372 LPDDR4 DRAM CONFIGURATION
2249 15:35:54.722865 ===================================
2250 15:35:54.723360 EX_ROW_EN[0] = 0x0
2251 15:35:54.726235 EX_ROW_EN[1] = 0x0
2252 15:35:54.726650 LP4Y_EN = 0x0
2253 15:35:54.729345 WORK_FSP = 0x0
2254 15:35:54.729759 WL = 0x4
2255 15:35:54.732680 RL = 0x4
2256 15:35:54.733102 BL = 0x2
2257 15:35:54.735828 RPST = 0x0
2258 15:35:54.736292 RD_PRE = 0x0
2259 15:35:54.739451 WR_PRE = 0x1
2260 15:35:54.742419 WR_PST = 0x0
2261 15:35:54.742834 DBI_WR = 0x0
2262 15:35:54.746392 DBI_RD = 0x0
2263 15:35:54.746808 OTF = 0x1
2264 15:35:54.749706 ===================================
2265 15:35:54.752466 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2266 15:35:54.759069 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2267 15:35:54.762435 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 15:35:54.766209 ===================================
2269 15:35:54.769317 LPDDR4 DRAM CONFIGURATION
2270 15:35:54.772815 ===================================
2271 15:35:54.773412 EX_ROW_EN[0] = 0x10
2272 15:35:54.775617 EX_ROW_EN[1] = 0x0
2273 15:35:54.776074 LP4Y_EN = 0x0
2274 15:35:54.779163 WORK_FSP = 0x0
2275 15:35:54.779580 WL = 0x4
2276 15:35:54.782781 RL = 0x4
2277 15:35:54.783199 BL = 0x2
2278 15:35:54.785748 RPST = 0x0
2279 15:35:54.786212 RD_PRE = 0x0
2280 15:35:54.789208 WR_PRE = 0x1
2281 15:35:54.789630 WR_PST = 0x0
2282 15:35:54.792596 DBI_WR = 0x0
2283 15:35:54.795496 DBI_RD = 0x0
2284 15:35:54.795938 OTF = 0x1
2285 15:35:54.798837 ===================================
2286 15:35:54.805479 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2287 15:35:54.805897 ==
2288 15:35:54.809047 Dram Type= 6, Freq= 0, CH_0, rank 0
2289 15:35:54.812092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2290 15:35:54.812515 ==
2291 15:35:54.815571 [Duty_Offset_Calibration]
2292 15:35:54.816015 B0:2 B1:0 CA:4
2293 15:35:54.818500
2294 15:35:54.822088 [DutyScan_Calibration_Flow] k_type=0
2295 15:35:54.829069
2296 15:35:54.829478 ==CLK 0==
2297 15:35:54.832037 Final CLK duty delay cell = -4
2298 15:35:54.835531 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2299 15:35:54.838956 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2300 15:35:54.842046 [-4] AVG Duty = 4937%(X100)
2301 15:35:54.842460
2302 15:35:54.845805 CH0 CLK Duty spec in!! Max-Min= 187%
2303 15:35:54.848818 [DutyScan_Calibration_Flow] ====Done====
2304 15:35:54.849231
2305 15:35:54.852260 [DutyScan_Calibration_Flow] k_type=1
2306 15:35:54.867864
2307 15:35:54.868309 ==DQS 0 ==
2308 15:35:54.870803 Final DQS duty delay cell = -4
2309 15:35:54.874215 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2310 15:35:54.877742 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2311 15:35:54.881113 [-4] AVG Duty = 4922%(X100)
2312 15:35:54.881562
2313 15:35:54.881905 ==DQS 1 ==
2314 15:35:54.884786 Final DQS duty delay cell = 0
2315 15:35:54.888102 [0] MAX Duty = 5125%(X100), DQS PI = 4
2316 15:35:54.890976 [0] MIN Duty = 5000%(X100), DQS PI = 0
2317 15:35:54.894578 [0] AVG Duty = 5062%(X100)
2318 15:35:54.895171
2319 15:35:54.897884 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2320 15:35:54.898299
2321 15:35:54.900718 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2322 15:35:54.904540 [DutyScan_Calibration_Flow] ====Done====
2323 15:35:54.904985
2324 15:35:54.907983 [DutyScan_Calibration_Flow] k_type=3
2325 15:35:54.924527
2326 15:35:54.924975 ==DQM 0 ==
2327 15:35:54.927588 Final DQM duty delay cell = 0
2328 15:35:54.930989 [0] MAX Duty = 5093%(X100), DQS PI = 18
2329 15:35:54.934539 [0] MIN Duty = 4844%(X100), DQS PI = 50
2330 15:35:54.934977 [0] AVG Duty = 4968%(X100)
2331 15:35:54.938020
2332 15:35:54.938522 ==DQM 1 ==
2333 15:35:54.941002 Final DQM duty delay cell = 0
2334 15:35:54.944349 [0] MAX Duty = 4969%(X100), DQS PI = 2
2335 15:35:54.947841 [0] MIN Duty = 4875%(X100), DQS PI = 20
2336 15:35:54.948329 [0] AVG Duty = 4922%(X100)
2337 15:35:54.951078
2338 15:35:54.954574 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2339 15:35:54.955007
2340 15:35:54.958089 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2341 15:35:54.961151 [DutyScan_Calibration_Flow] ====Done====
2342 15:35:54.961587
2343 15:35:54.964183 [DutyScan_Calibration_Flow] k_type=2
2344 15:35:54.980740
2345 15:35:54.981177 ==DQ 0 ==
2346 15:35:54.984137 Final DQ duty delay cell = 0
2347 15:35:54.987681 [0] MAX Duty = 5125%(X100), DQS PI = 18
2348 15:35:54.990459 [0] MIN Duty = 4969%(X100), DQS PI = 52
2349 15:35:54.990877 [0] AVG Duty = 5047%(X100)
2350 15:35:54.993952
2351 15:35:54.994379 ==DQ 1 ==
2352 15:35:54.997363 Final DQ duty delay cell = 0
2353 15:35:55.000955 [0] MAX Duty = 5125%(X100), DQS PI = 4
2354 15:35:55.003732 [0] MIN Duty = 4938%(X100), DQS PI = 14
2355 15:35:55.004251 [0] AVG Duty = 5031%(X100)
2356 15:35:55.004596
2357 15:35:55.007379 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2358 15:35:55.010644
2359 15:35:55.013868 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2360 15:35:55.017233 [DutyScan_Calibration_Flow] ====Done====
2361 15:35:55.017656 ==
2362 15:35:55.020432 Dram Type= 6, Freq= 0, CH_1, rank 0
2363 15:35:55.023849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 15:35:55.024354 ==
2365 15:35:55.027417 [Duty_Offset_Calibration]
2366 15:35:55.027829 B0:0 B1:-1 CA:3
2367 15:35:55.028343
2368 15:35:55.030623 [DutyScan_Calibration_Flow] k_type=0
2369 15:35:55.039549
2370 15:35:55.039655 ==CLK 0==
2371 15:35:55.043037 Final CLK duty delay cell = -4
2372 15:35:55.046334 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2373 15:35:55.049434 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2374 15:35:55.052704 [-4] AVG Duty = 4938%(X100)
2375 15:35:55.052780
2376 15:35:55.056258 CH1 CLK Duty spec in!! Max-Min= 124%
2377 15:35:55.059701 [DutyScan_Calibration_Flow] ====Done====
2378 15:35:55.059803
2379 15:35:55.063174 [DutyScan_Calibration_Flow] k_type=1
2380 15:35:55.078978
2381 15:35:55.079089 ==DQS 0 ==
2382 15:35:55.082298 Final DQS duty delay cell = 0
2383 15:35:55.085950 [0] MAX Duty = 5187%(X100), DQS PI = 18
2384 15:35:55.089086 [0] MIN Duty = 4907%(X100), DQS PI = 38
2385 15:35:55.089166 [0] AVG Duty = 5047%(X100)
2386 15:35:55.092542
2387 15:35:55.092617 ==DQS 1 ==
2388 15:35:55.095646 Final DQS duty delay cell = 0
2389 15:35:55.099159 [0] MAX Duty = 5156%(X100), DQS PI = 8
2390 15:35:55.102568 [0] MIN Duty = 5031%(X100), DQS PI = 20
2391 15:35:55.102657 [0] AVG Duty = 5093%(X100)
2392 15:35:55.105940
2393 15:35:55.109593 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2394 15:35:55.109674
2395 15:35:55.112382 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2396 15:35:55.115706 [DutyScan_Calibration_Flow] ====Done====
2397 15:35:55.115817
2398 15:35:55.119354 [DutyScan_Calibration_Flow] k_type=3
2399 15:35:55.135619
2400 15:35:55.135701 ==DQM 0 ==
2401 15:35:55.139083 Final DQM duty delay cell = 0
2402 15:35:55.142026 [0] MAX Duty = 5031%(X100), DQS PI = 26
2403 15:35:55.145776 [0] MIN Duty = 4813%(X100), DQS PI = 38
2404 15:35:55.148662 [0] AVG Duty = 4922%(X100)
2405 15:35:55.148738
2406 15:35:55.148807 ==DQM 1 ==
2407 15:35:55.152729 Final DQM duty delay cell = 0
2408 15:35:55.155375 [0] MAX Duty = 5000%(X100), DQS PI = 32
2409 15:35:55.158670 [0] MIN Duty = 4844%(X100), DQS PI = 0
2410 15:35:55.162024 [0] AVG Duty = 4922%(X100)
2411 15:35:55.162121
2412 15:35:55.165607 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2413 15:35:55.165679
2414 15:35:55.168799 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2415 15:35:55.172366 [DutyScan_Calibration_Flow] ====Done====
2416 15:35:55.172448
2417 15:35:55.175618 [DutyScan_Calibration_Flow] k_type=2
2418 15:35:55.191539
2419 15:35:55.191647 ==DQ 0 ==
2420 15:35:55.194290 Final DQ duty delay cell = -4
2421 15:35:55.197659 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2422 15:35:55.201601 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2423 15:35:55.204612 [-4] AVG Duty = 4937%(X100)
2424 15:35:55.204688
2425 15:35:55.204752 ==DQ 1 ==
2426 15:35:55.208184 Final DQ duty delay cell = 0
2427 15:35:55.210892 [0] MAX Duty = 5031%(X100), DQS PI = 34
2428 15:35:55.214315 [0] MIN Duty = 4844%(X100), DQS PI = 62
2429 15:35:55.217811 [0] AVG Duty = 4937%(X100)
2430 15:35:55.217909
2431 15:35:55.221359 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2432 15:35:55.221458
2433 15:35:55.224509 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2434 15:35:55.227760 [DutyScan_Calibration_Flow] ====Done====
2435 15:35:55.230706 nWR fixed to 30
2436 15:35:55.234404 [ModeRegInit_LP4] CH0 RK0
2437 15:35:55.234506 [ModeRegInit_LP4] CH0 RK1
2438 15:35:55.237840 [ModeRegInit_LP4] CH1 RK0
2439 15:35:55.240640 [ModeRegInit_LP4] CH1 RK1
2440 15:35:55.240714 match AC timing 7
2441 15:35:55.247533 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2442 15:35:55.250552 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2443 15:35:55.254021 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2444 15:35:55.261058 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2445 15:35:55.264101 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2446 15:35:55.264202 ==
2447 15:35:55.267527 Dram Type= 6, Freq= 0, CH_0, rank 0
2448 15:35:55.270443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 15:35:55.270548 ==
2450 15:35:55.277142 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2451 15:35:55.283981 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2452 15:35:55.291430 [CA 0] Center 39 (9~70) winsize 62
2453 15:35:55.295078 [CA 1] Center 38 (8~69) winsize 62
2454 15:35:55.298535 [CA 2] Center 35 (5~66) winsize 62
2455 15:35:55.301393 [CA 3] Center 35 (5~66) winsize 62
2456 15:35:55.304658 [CA 4] Center 33 (3~64) winsize 62
2457 15:35:55.308661 [CA 5] Center 33 (3~64) winsize 62
2458 15:35:55.308768
2459 15:35:55.311564 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2460 15:35:55.311660
2461 15:35:55.315166 [CATrainingPosCal] consider 1 rank data
2462 15:35:55.318000 u2DelayCellTimex100 = 270/100 ps
2463 15:35:55.321481 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2464 15:35:55.328050 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2465 15:35:55.331280 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2466 15:35:55.334726 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2467 15:35:55.338475 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2468 15:35:55.341344 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2469 15:35:55.341448
2470 15:35:55.344747 CA PerBit enable=1, Macro0, CA PI delay=33
2471 15:35:55.344849
2472 15:35:55.348442 [CBTSetCACLKResult] CA Dly = 33
2473 15:35:55.348545 CS Dly: 7 (0~38)
2474 15:35:55.351638 ==
2475 15:35:55.354532 Dram Type= 6, Freq= 0, CH_0, rank 1
2476 15:35:55.358276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 15:35:55.358385 ==
2478 15:35:55.361730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 15:35:55.367965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2480 15:35:55.377709 [CA 0] Center 39 (9~70) winsize 62
2481 15:35:55.381288 [CA 1] Center 39 (9~70) winsize 62
2482 15:35:55.383745 [CA 2] Center 35 (5~66) winsize 62
2483 15:35:55.387059 [CA 3] Center 35 (5~66) winsize 62
2484 15:35:55.390682 [CA 4] Center 34 (4~65) winsize 62
2485 15:35:55.393859 [CA 5] Center 33 (3~64) winsize 62
2486 15:35:55.393958
2487 15:35:55.397331 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2488 15:35:55.397416
2489 15:35:55.400261 [CATrainingPosCal] consider 2 rank data
2490 15:35:55.403556 u2DelayCellTimex100 = 270/100 ps
2491 15:35:55.407148 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2492 15:35:55.414056 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2493 15:35:55.416622 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2494 15:35:55.420652 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2495 15:35:55.423563 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2496 15:35:55.426982 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2497 15:35:55.427063
2498 15:35:55.430106 CA PerBit enable=1, Macro0, CA PI delay=33
2499 15:35:55.430188
2500 15:35:55.433215 [CBTSetCACLKResult] CA Dly = 33
2501 15:35:55.436758 CS Dly: 8 (0~41)
2502 15:35:55.436865
2503 15:35:55.439926 ----->DramcWriteLeveling(PI) begin...
2504 15:35:55.440024 ==
2505 15:35:55.443508 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 15:35:55.446733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 15:35:55.446812 ==
2508 15:35:55.450090 Write leveling (Byte 0): 31 => 31
2509 15:35:55.452977 Write leveling (Byte 1): 27 => 27
2510 15:35:55.456353 DramcWriteLeveling(PI) end<-----
2511 15:35:55.456426
2512 15:35:55.456486 ==
2513 15:35:55.459800 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 15:35:55.463447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 15:35:55.463520 ==
2516 15:35:55.466391 [Gating] SW mode calibration
2517 15:35:55.473134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2518 15:35:55.479848 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2519 15:35:55.483543 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2520 15:35:55.486433 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2521 15:35:55.493226 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 15:35:55.496340 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 15:35:55.500246 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 15:35:55.506435 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 15:35:55.509913 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2526 15:35:55.513217 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2527 15:35:55.520284 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2528 15:35:55.523035 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2529 15:35:55.526543 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 15:35:55.533320 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 15:35:55.536413 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 15:35:55.539457 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 15:35:55.546300 1 0 24 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
2534 15:35:55.549522 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2535 15:35:55.553008 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2536 15:35:55.560039 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 15:35:55.563253 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 15:35:55.566626 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 15:35:55.569581 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 15:35:55.576428 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 15:35:55.579293 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 15:35:55.582610 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2543 15:35:55.589482 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2544 15:35:55.592813 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 15:35:55.595833 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 15:35:55.602643 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 15:35:55.605905 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 15:35:55.609350 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 15:35:55.616114 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 15:35:55.619334 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 15:35:55.622399 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 15:35:55.629185 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 15:35:55.632602 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 15:35:55.635969 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 15:35:55.642747 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 15:35:55.646708 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 15:35:55.649122 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 15:35:55.655895 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2559 15:35:55.659263 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2560 15:35:55.662399 Total UI for P1: 0, mck2ui 16
2561 15:35:55.665564 best dqsien dly found for B0: ( 1, 3, 28)
2562 15:35:55.669286 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 15:35:55.672347 Total UI for P1: 0, mck2ui 16
2564 15:35:55.675976 best dqsien dly found for B1: ( 1, 4, 0)
2565 15:35:55.679375 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2566 15:35:55.682188 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2567 15:35:55.682270
2568 15:35:55.685885 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2569 15:35:55.692031 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2570 15:35:55.692112 [Gating] SW calibration Done
2571 15:35:55.692203 ==
2572 15:35:55.695664 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 15:35:55.702953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 15:35:55.703035 ==
2575 15:35:55.703099 RX Vref Scan: 0
2576 15:35:55.703158
2577 15:35:55.705318 RX Vref 0 -> 0, step: 1
2578 15:35:55.705399
2579 15:35:55.708707 RX Delay -40 -> 252, step: 8
2580 15:35:55.711880 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2581 15:35:55.715485 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2582 15:35:55.718873 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2583 15:35:55.725669 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2584 15:35:55.728698 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2585 15:35:55.732084 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2586 15:35:55.735547 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2587 15:35:55.738874 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2588 15:35:55.745790 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2589 15:35:55.748945 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2590 15:35:55.752109 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2591 15:35:55.755247 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2592 15:35:55.758966 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2593 15:35:55.765316 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2594 15:35:55.768670 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2595 15:35:55.772407 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2596 15:35:55.772509 ==
2597 15:35:55.775545 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 15:35:55.778583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 15:35:55.778691 ==
2600 15:35:55.781593 DQS Delay:
2601 15:35:55.781694 DQS0 = 0, DQS1 = 0
2602 15:35:55.785174 DQM Delay:
2603 15:35:55.785270 DQM0 = 117, DQM1 = 107
2604 15:35:55.788336 DQ Delay:
2605 15:35:55.791700 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2606 15:35:55.795174 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2607 15:35:55.798389 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2608 15:35:55.801896 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =111
2609 15:35:55.801969
2610 15:35:55.802037
2611 15:35:55.802097 ==
2612 15:35:55.805336 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 15:35:55.808812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 15:35:55.808884 ==
2615 15:35:55.808947
2616 15:35:55.809007
2617 15:35:55.811821 TX Vref Scan disable
2618 15:35:55.815021 == TX Byte 0 ==
2619 15:35:55.818663 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2620 15:35:55.821868 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2621 15:35:55.825119 == TX Byte 1 ==
2622 15:35:55.828077 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2623 15:35:55.831765 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2624 15:35:55.831863 ==
2625 15:35:55.835106 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 15:35:55.838098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 15:35:55.841576 ==
2628 15:35:55.852226 TX Vref=22, minBit 0, minWin=25, winSum=413
2629 15:35:55.855638 TX Vref=24, minBit 4, minWin=25, winSum=418
2630 15:35:55.858554 TX Vref=26, minBit 7, minWin=25, winSum=425
2631 15:35:55.862042 TX Vref=28, minBit 1, minWin=26, winSum=432
2632 15:35:55.865164 TX Vref=30, minBit 4, minWin=26, winSum=429
2633 15:35:55.871943 TX Vref=32, minBit 2, minWin=26, winSum=428
2634 15:35:55.875326 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 28
2635 15:35:55.875428
2636 15:35:55.878512 Final TX Range 1 Vref 28
2637 15:35:55.878626
2638 15:35:55.878719 ==
2639 15:35:55.881738 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 15:35:55.885322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 15:35:55.885423 ==
2642 15:35:55.888879
2643 15:35:55.888952
2644 15:35:55.889012 TX Vref Scan disable
2645 15:35:55.892125 == TX Byte 0 ==
2646 15:35:55.895218 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2647 15:35:55.901561 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2648 15:35:55.901665 == TX Byte 1 ==
2649 15:35:55.904925 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2650 15:35:55.911875 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2651 15:35:55.911996
2652 15:35:55.912087 [DATLAT]
2653 15:35:55.912175 Freq=1200, CH0 RK0
2654 15:35:55.912250
2655 15:35:55.914769 DATLAT Default: 0xd
2656 15:35:55.914867 0, 0xFFFF, sum = 0
2657 15:35:55.918198 1, 0xFFFF, sum = 0
2658 15:35:55.918298 2, 0xFFFF, sum = 0
2659 15:35:55.921733 3, 0xFFFF, sum = 0
2660 15:35:55.925073 4, 0xFFFF, sum = 0
2661 15:35:55.925159 5, 0xFFFF, sum = 0
2662 15:35:55.928783 6, 0xFFFF, sum = 0
2663 15:35:55.928856 7, 0xFFFF, sum = 0
2664 15:35:55.931579 8, 0xFFFF, sum = 0
2665 15:35:55.931685 9, 0xFFFF, sum = 0
2666 15:35:55.935130 10, 0xFFFF, sum = 0
2667 15:35:55.935232 11, 0xFFFF, sum = 0
2668 15:35:55.938220 12, 0x0, sum = 1
2669 15:35:55.938332 13, 0x0, sum = 2
2670 15:35:55.941743 14, 0x0, sum = 3
2671 15:35:55.941818 15, 0x0, sum = 4
2672 15:35:55.944530 best_step = 13
2673 15:35:55.944628
2674 15:35:55.944717 ==
2675 15:35:55.948033 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 15:35:55.951340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 15:35:55.951453 ==
2678 15:35:55.951547 RX Vref Scan: 1
2679 15:35:55.951636
2680 15:35:55.955149 Set Vref Range= 32 -> 127
2681 15:35:55.955250
2682 15:35:55.958070 RX Vref 32 -> 127, step: 1
2683 15:35:55.958168
2684 15:35:55.961602 RX Delay -21 -> 252, step: 4
2685 15:35:55.961674
2686 15:35:55.964837 Set Vref, RX VrefLevel [Byte0]: 32
2687 15:35:55.968059 [Byte1]: 32
2688 15:35:55.968140
2689 15:35:55.971829 Set Vref, RX VrefLevel [Byte0]: 33
2690 15:35:55.974629 [Byte1]: 33
2691 15:35:55.978504
2692 15:35:55.978607 Set Vref, RX VrefLevel [Byte0]: 34
2693 15:35:55.981365 [Byte1]: 34
2694 15:35:55.985941
2695 15:35:55.986043 Set Vref, RX VrefLevel [Byte0]: 35
2696 15:35:55.989472 [Byte1]: 35
2697 15:35:55.994278
2698 15:35:55.994380 Set Vref, RX VrefLevel [Byte0]: 36
2699 15:35:55.997054 [Byte1]: 36
2700 15:35:56.002092
2701 15:35:56.002166 Set Vref, RX VrefLevel [Byte0]: 37
2702 15:35:56.005398 [Byte1]: 37
2703 15:35:56.009753
2704 15:35:56.009827 Set Vref, RX VrefLevel [Byte0]: 38
2705 15:35:56.013016 [Byte1]: 38
2706 15:35:56.017832
2707 15:35:56.017918 Set Vref, RX VrefLevel [Byte0]: 39
2708 15:35:56.021079 [Byte1]: 39
2709 15:35:56.025847
2710 15:35:56.025924 Set Vref, RX VrefLevel [Byte0]: 40
2711 15:35:56.029191 [Byte1]: 40
2712 15:35:56.033719
2713 15:35:56.033793 Set Vref, RX VrefLevel [Byte0]: 41
2714 15:35:56.037169 [Byte1]: 41
2715 15:35:56.041702
2716 15:35:56.041782 Set Vref, RX VrefLevel [Byte0]: 42
2717 15:35:56.045140 [Byte1]: 42
2718 15:35:56.049409
2719 15:35:56.049490 Set Vref, RX VrefLevel [Byte0]: 43
2720 15:35:56.052706 [Byte1]: 43
2721 15:35:56.057732
2722 15:35:56.057812 Set Vref, RX VrefLevel [Byte0]: 44
2723 15:35:56.060734 [Byte1]: 44
2724 15:35:56.065664
2725 15:35:56.065769 Set Vref, RX VrefLevel [Byte0]: 45
2726 15:35:56.069063 [Byte1]: 45
2727 15:35:56.073560
2728 15:35:56.073641 Set Vref, RX VrefLevel [Byte0]: 46
2729 15:35:56.076942 [Byte1]: 46
2730 15:35:56.081366
2731 15:35:56.081446 Set Vref, RX VrefLevel [Byte0]: 47
2732 15:35:56.084513 [Byte1]: 47
2733 15:35:56.089298
2734 15:35:56.089400 Set Vref, RX VrefLevel [Byte0]: 48
2735 15:35:56.092595 [Byte1]: 48
2736 15:35:56.097276
2737 15:35:56.097375 Set Vref, RX VrefLevel [Byte0]: 49
2738 15:35:56.100258 [Byte1]: 49
2739 15:35:56.105174
2740 15:35:56.105275 Set Vref, RX VrefLevel [Byte0]: 50
2741 15:35:56.108440 [Byte1]: 50
2742 15:35:56.113203
2743 15:35:56.113283 Set Vref, RX VrefLevel [Byte0]: 51
2744 15:35:56.116063 [Byte1]: 51
2745 15:35:56.120710
2746 15:35:56.120783 Set Vref, RX VrefLevel [Byte0]: 52
2747 15:35:56.124078 [Byte1]: 52
2748 15:35:56.128752
2749 15:35:56.128827 Set Vref, RX VrefLevel [Byte0]: 53
2750 15:35:56.132131 [Byte1]: 53
2751 15:35:56.136826
2752 15:35:56.136902 Set Vref, RX VrefLevel [Byte0]: 54
2753 15:35:56.140293 [Byte1]: 54
2754 15:35:56.144765
2755 15:35:56.144867 Set Vref, RX VrefLevel [Byte0]: 55
2756 15:35:56.147768 [Byte1]: 55
2757 15:35:56.152756
2758 15:35:56.152856 Set Vref, RX VrefLevel [Byte0]: 56
2759 15:35:56.156251 [Byte1]: 56
2760 15:35:56.160624
2761 15:35:56.160697 Set Vref, RX VrefLevel [Byte0]: 57
2762 15:35:56.163782 [Byte1]: 57
2763 15:35:56.168300
2764 15:35:56.168375 Set Vref, RX VrefLevel [Byte0]: 58
2765 15:35:56.172247 [Byte1]: 58
2766 15:35:56.176173
2767 15:35:56.176296 Set Vref, RX VrefLevel [Byte0]: 59
2768 15:35:56.179567 [Byte1]: 59
2769 15:35:56.184590
2770 15:35:56.184694 Set Vref, RX VrefLevel [Byte0]: 60
2771 15:35:56.187504 [Byte1]: 60
2772 15:35:56.191878
2773 15:35:56.191996 Set Vref, RX VrefLevel [Byte0]: 61
2774 15:35:56.195181 [Byte1]: 61
2775 15:35:56.199928
2776 15:35:56.200014 Set Vref, RX VrefLevel [Byte0]: 62
2777 15:35:56.203625 [Byte1]: 62
2778 15:35:56.207882
2779 15:35:56.207980 Set Vref, RX VrefLevel [Byte0]: 63
2780 15:35:56.211163 [Byte1]: 63
2781 15:35:56.215870
2782 15:35:56.215995 Set Vref, RX VrefLevel [Byte0]: 64
2783 15:35:56.219703 [Byte1]: 64
2784 15:35:56.223830
2785 15:35:56.223981 Set Vref, RX VrefLevel [Byte0]: 65
2786 15:35:56.226933 [Byte1]: 65
2787 15:35:56.231715
2788 15:35:56.231851 Set Vref, RX VrefLevel [Byte0]: 66
2789 15:35:56.235151 [Byte1]: 66
2790 15:35:56.239763
2791 15:35:56.239871 Set Vref, RX VrefLevel [Byte0]: 67
2792 15:35:56.243192 [Byte1]: 67
2793 15:35:56.247779
2794 15:35:56.247888 Set Vref, RX VrefLevel [Byte0]: 68
2795 15:35:56.251160 [Byte1]: 68
2796 15:35:56.255809
2797 15:35:56.256001 Set Vref, RX VrefLevel [Byte0]: 69
2798 15:35:56.258784 [Byte1]: 69
2799 15:35:56.263611
2800 15:35:56.263716 Final RX Vref Byte 0 = 52 to rank0
2801 15:35:56.266529 Final RX Vref Byte 1 = 59 to rank0
2802 15:35:56.270144 Final RX Vref Byte 0 = 52 to rank1
2803 15:35:56.273290 Final RX Vref Byte 1 = 59 to rank1==
2804 15:35:56.276707 Dram Type= 6, Freq= 0, CH_0, rank 0
2805 15:35:56.283303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2806 15:35:56.283407 ==
2807 15:35:56.283500 DQS Delay:
2808 15:35:56.286577 DQS0 = 0, DQS1 = 0
2809 15:35:56.286676 DQM Delay:
2810 15:35:56.286768 DQM0 = 117, DQM1 = 105
2811 15:35:56.289909 DQ Delay:
2812 15:35:56.293287 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2813 15:35:56.296785 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2814 15:35:56.300127 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2815 15:35:56.303706 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2816 15:35:56.303806
2817 15:35:56.303895
2818 15:35:56.309905 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2819 15:35:56.313443 CH0 RK0: MR19=403, MR18=1FC
2820 15:35:56.320142 CH0_RK0: MR19=0x403, MR18=0x1FC, DQSOSC=409, MR23=63, INC=39, DEC=26
2821 15:35:56.320220
2822 15:35:56.323545 ----->DramcWriteLeveling(PI) begin...
2823 15:35:56.323623 ==
2824 15:35:56.326790 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 15:35:56.329817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 15:35:56.333282 ==
2827 15:35:56.333361 Write leveling (Byte 0): 32 => 32
2828 15:35:56.336451 Write leveling (Byte 1): 28 => 28
2829 15:35:56.339814 DramcWriteLeveling(PI) end<-----
2830 15:35:56.339926
2831 15:35:56.340007 ==
2832 15:35:56.343108 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 15:35:56.349680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 15:35:56.349794 ==
2835 15:35:56.349888 [Gating] SW mode calibration
2836 15:35:56.359730 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2837 15:35:56.363177 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2838 15:35:56.369836 0 15 0 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
2839 15:35:56.373057 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 15:35:56.376183 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 15:35:56.383057 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 15:35:56.385885 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 15:35:56.389406 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 15:35:56.396064 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2845 15:35:56.399370 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
2846 15:35:56.402600 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2847 15:35:56.405944 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 15:35:56.412552 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 15:35:56.416064 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 15:35:56.419174 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 15:35:56.426022 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 15:35:56.429579 1 0 24 | B1->B0 | 2323 3939 | 0 0 | (0 0) (1 1)
2853 15:35:56.432606 1 0 28 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2854 15:35:56.439333 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2855 15:35:56.442763 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 15:35:56.445933 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 15:35:56.452742 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 15:35:56.456460 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 15:35:56.459393 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 15:35:56.466228 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2861 15:35:56.469325 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2862 15:35:56.472153 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 15:35:56.479087 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2864 15:35:56.482357 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 15:35:56.485839 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 15:35:56.492131 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 15:35:56.495689 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 15:35:56.499258 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 15:35:56.505355 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 15:35:56.508848 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 15:35:56.512160 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 15:35:56.519000 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 15:35:56.521903 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 15:35:56.525555 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 15:35:56.532176 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2876 15:35:56.535465 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2877 15:35:56.538695 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2878 15:35:56.541683 Total UI for P1: 0, mck2ui 16
2879 15:35:56.544993 best dqsien dly found for B0: ( 1, 3, 22)
2880 15:35:56.551401 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2881 15:35:56.554742 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 15:35:56.558310 Total UI for P1: 0, mck2ui 16
2883 15:35:56.561467 best dqsien dly found for B1: ( 1, 3, 30)
2884 15:35:56.565126 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2885 15:35:56.568586 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2886 15:35:56.568680
2887 15:35:56.571817 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2888 15:35:56.575235 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2889 15:35:56.578498 [Gating] SW calibration Done
2890 15:35:56.578602 ==
2891 15:35:56.581822 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 15:35:56.585002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 15:35:56.585104 ==
2894 15:35:56.588580 RX Vref Scan: 0
2895 15:35:56.588654
2896 15:35:56.591396 RX Vref 0 -> 0, step: 1
2897 15:35:56.591496
2898 15:35:56.591585 RX Delay -40 -> 252, step: 8
2899 15:35:56.598459 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2900 15:35:56.601797 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2901 15:35:56.605254 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2902 15:35:56.608175 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2903 15:35:56.611704 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2904 15:35:56.618254 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2905 15:35:56.621540 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2906 15:35:56.624826 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2907 15:35:56.627952 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2908 15:35:56.631412 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2909 15:35:56.638225 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2910 15:35:56.641297 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2911 15:35:56.644976 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2912 15:35:56.647807 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
2913 15:35:56.651316 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2914 15:35:56.657766 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2915 15:35:56.657847 ==
2916 15:35:56.661244 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 15:35:56.664552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 15:35:56.664633 ==
2919 15:35:56.664697 DQS Delay:
2920 15:35:56.667690 DQS0 = 0, DQS1 = 0
2921 15:35:56.667770 DQM Delay:
2922 15:35:56.671286 DQM0 = 115, DQM1 = 109
2923 15:35:56.671367 DQ Delay:
2924 15:35:56.674549 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2925 15:35:56.678235 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2926 15:35:56.681236 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2927 15:35:56.684744 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2928 15:35:56.688373
2929 15:35:56.688447
2930 15:35:56.688513 ==
2931 15:35:56.691021 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 15:35:56.694621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 15:35:56.694725 ==
2934 15:35:56.694814
2935 15:35:56.694901
2936 15:35:56.697904 TX Vref Scan disable
2937 15:35:56.698001 == TX Byte 0 ==
2938 15:35:56.704197 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2939 15:35:56.707576 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2940 15:35:56.707676 == TX Byte 1 ==
2941 15:35:56.714783 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2942 15:35:56.717622 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2943 15:35:56.717721 ==
2944 15:35:56.720995 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 15:35:56.724546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 15:35:56.724619 ==
2947 15:35:56.737456 TX Vref=22, minBit 1, minWin=26, winSum=422
2948 15:35:56.740367 TX Vref=24, minBit 1, minWin=26, winSum=424
2949 15:35:56.744049 TX Vref=26, minBit 2, minWin=26, winSum=428
2950 15:35:56.746740 TX Vref=28, minBit 5, minWin=26, winSum=430
2951 15:35:56.750238 TX Vref=30, minBit 10, minWin=25, winSum=430
2952 15:35:56.756963 TX Vref=32, minBit 14, minWin=25, winSum=430
2953 15:35:56.760121 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 28
2954 15:35:56.760200
2955 15:35:56.763452 Final TX Range 1 Vref 28
2956 15:35:56.763555
2957 15:35:56.763646 ==
2958 15:35:56.766969 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 15:35:56.770761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 15:35:56.773675 ==
2961 15:35:56.773771
2962 15:35:56.773858
2963 15:35:56.773946 TX Vref Scan disable
2964 15:35:56.777118 == TX Byte 0 ==
2965 15:35:56.780089 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2966 15:35:56.783517 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2967 15:35:56.787042 == TX Byte 1 ==
2968 15:35:56.790197 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2969 15:35:56.794096 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2970 15:35:56.797009
2971 15:35:56.797106 [DATLAT]
2972 15:35:56.797195 Freq=1200, CH0 RK1
2973 15:35:56.797283
2974 15:35:56.800426 DATLAT Default: 0xd
2975 15:35:56.800511 0, 0xFFFF, sum = 0
2976 15:35:56.803823 1, 0xFFFF, sum = 0
2977 15:35:56.803911 2, 0xFFFF, sum = 0
2978 15:35:56.806720 3, 0xFFFF, sum = 0
2979 15:35:56.810234 4, 0xFFFF, sum = 0
2980 15:35:56.810330 5, 0xFFFF, sum = 0
2981 15:35:56.813411 6, 0xFFFF, sum = 0
2982 15:35:56.813511 7, 0xFFFF, sum = 0
2983 15:35:56.816490 8, 0xFFFF, sum = 0
2984 15:35:56.816565 9, 0xFFFF, sum = 0
2985 15:35:56.820094 10, 0xFFFF, sum = 0
2986 15:35:56.820163 11, 0xFFFF, sum = 0
2987 15:35:56.823467 12, 0x0, sum = 1
2988 15:35:56.823562 13, 0x0, sum = 2
2989 15:35:56.826343 14, 0x0, sum = 3
2990 15:35:56.826439 15, 0x0, sum = 4
2991 15:35:56.829807 best_step = 13
2992 15:35:56.829880
2993 15:35:56.829969 ==
2994 15:35:56.833388 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 15:35:56.836721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 15:35:56.836790 ==
2997 15:35:56.836849 RX Vref Scan: 0
2998 15:35:56.840082
2999 15:35:56.840146 RX Vref 0 -> 0, step: 1
3000 15:35:56.840208
3001 15:35:56.842907 RX Delay -21 -> 252, step: 4
3002 15:35:56.849757 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3003 15:35:56.852816 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3004 15:35:56.856767 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3005 15:35:56.859639 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3006 15:35:56.862895 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3007 15:35:56.866672 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3008 15:35:56.873231 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3009 15:35:56.876037 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3010 15:35:56.879727 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3011 15:35:56.882951 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3012 15:35:56.886091 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3013 15:35:56.892797 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3014 15:35:56.896300 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3015 15:35:56.899408 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3016 15:35:56.902535 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3017 15:35:56.909454 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3018 15:35:56.909555 ==
3019 15:35:56.912927 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 15:35:56.916047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 15:35:56.916116 ==
3022 15:35:56.916177 DQS Delay:
3023 15:35:56.919535 DQS0 = 0, DQS1 = 0
3024 15:35:56.919627 DQM Delay:
3025 15:35:56.923266 DQM0 = 115, DQM1 = 106
3026 15:35:56.923333 DQ Delay:
3027 15:35:56.926023 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3028 15:35:56.929556 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3029 15:35:56.932762 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3030 15:35:56.936461 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3031 15:35:56.936529
3032 15:35:56.936592
3033 15:35:56.946222 [DQSOSCAuto] RK1, (LSB)MR18= 0x1fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3034 15:35:56.946323 CH0 RK1: MR19=403, MR18=1FE
3035 15:35:56.952891 CH0_RK1: MR19=0x403, MR18=0x1FE, DQSOSC=409, MR23=63, INC=39, DEC=26
3036 15:35:56.956108 [RxdqsGatingPostProcess] freq 1200
3037 15:35:56.962650 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3038 15:35:56.966078 best DQS0 dly(2T, 0.5T) = (0, 11)
3039 15:35:56.969486 best DQS1 dly(2T, 0.5T) = (0, 12)
3040 15:35:56.972704 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3041 15:35:56.976228 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3042 15:35:56.979396 best DQS0 dly(2T, 0.5T) = (0, 11)
3043 15:35:56.979498 best DQS1 dly(2T, 0.5T) = (0, 11)
3044 15:35:56.982667 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3045 15:35:56.986121 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3046 15:35:56.989535 Pre-setting of DQS Precalculation
3047 15:35:56.995866 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3048 15:35:56.995990 ==
3049 15:35:56.999142 Dram Type= 6, Freq= 0, CH_1, rank 0
3050 15:35:57.002378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 15:35:57.002476 ==
3052 15:35:57.009106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3053 15:35:57.015906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3054 15:35:57.023044 [CA 0] Center 38 (8~68) winsize 61
3055 15:35:57.026533 [CA 1] Center 37 (7~68) winsize 62
3056 15:35:57.030085 [CA 2] Center 35 (5~65) winsize 61
3057 15:35:57.032802 [CA 3] Center 34 (4~64) winsize 61
3058 15:35:57.036455 [CA 4] Center 35 (5~65) winsize 61
3059 15:35:57.039778 [CA 5] Center 33 (3~64) winsize 62
3060 15:35:57.039871
3061 15:35:57.042777 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3062 15:35:57.042873
3063 15:35:57.046179 [CATrainingPosCal] consider 1 rank data
3064 15:35:57.049446 u2DelayCellTimex100 = 270/100 ps
3065 15:35:57.053303 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3066 15:35:57.059538 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3067 15:35:57.062855 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3068 15:35:57.066154 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3069 15:35:57.069616 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3070 15:35:57.072580 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3071 15:35:57.072653
3072 15:35:57.075851 CA PerBit enable=1, Macro0, CA PI delay=33
3073 15:35:57.076012
3074 15:35:57.079335 [CBTSetCACLKResult] CA Dly = 33
3075 15:35:57.079438 CS Dly: 5 (0~36)
3076 15:35:57.082822 ==
3077 15:35:57.086197 Dram Type= 6, Freq= 0, CH_1, rank 1
3078 15:35:57.089110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 15:35:57.089218 ==
3080 15:35:57.092828 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3081 15:35:57.099331 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3082 15:35:57.108741 [CA 0] Center 37 (7~68) winsize 62
3083 15:35:57.111701 [CA 1] Center 38 (8~68) winsize 61
3084 15:35:57.115331 [CA 2] Center 35 (5~65) winsize 61
3085 15:35:57.118746 [CA 3] Center 33 (3~64) winsize 62
3086 15:35:57.121825 [CA 4] Center 34 (4~64) winsize 61
3087 15:35:57.125020 [CA 5] Center 33 (3~64) winsize 62
3088 15:35:57.125097
3089 15:35:57.128763 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3090 15:35:57.128837
3091 15:35:57.131754 [CATrainingPosCal] consider 2 rank data
3092 15:35:57.135476 u2DelayCellTimex100 = 270/100 ps
3093 15:35:57.138989 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3094 15:35:57.144953 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3095 15:35:57.148342 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3096 15:35:57.151821 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 15:35:57.155191 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3098 15:35:57.158599 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3099 15:35:57.158676
3100 15:35:57.161888 CA PerBit enable=1, Macro0, CA PI delay=33
3101 15:35:57.161963
3102 15:35:57.164820 [CBTSetCACLKResult] CA Dly = 33
3103 15:35:57.164918 CS Dly: 6 (0~38)
3104 15:35:57.168312
3105 15:35:57.168387 ----->DramcWriteLeveling(PI) begin...
3106 15:35:57.171922 ==
3107 15:35:57.175330 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 15:35:57.178446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 15:35:57.178552 ==
3110 15:35:57.181940 Write leveling (Byte 0): 26 => 26
3111 15:35:57.185284 Write leveling (Byte 1): 26 => 26
3112 15:35:57.188653 DramcWriteLeveling(PI) end<-----
3113 15:35:57.188726
3114 15:35:57.188794 ==
3115 15:35:57.191703 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 15:35:57.194973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 15:35:57.195050 ==
3118 15:35:57.198329 [Gating] SW mode calibration
3119 15:35:57.204965 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3120 15:35:57.212166 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3121 15:35:57.215336 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3122 15:35:57.218340 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 15:35:57.221489 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 15:35:57.228328 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 15:35:57.231868 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 15:35:57.235379 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 15:35:57.241534 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 15:35:57.245053 0 15 28 | B1->B0 | 2828 2424 | 0 0 | (1 0) (1 0)
3129 15:35:57.248413 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 15:35:57.254718 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 15:35:57.258109 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 15:35:57.261779 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 15:35:57.268729 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 15:35:57.271380 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 15:35:57.274862 1 0 24 | B1->B0 | 2727 3636 | 0 0 | (0 0) (1 1)
3136 15:35:57.281697 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3137 15:35:57.284676 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 15:35:57.288383 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 15:35:57.294907 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 15:35:57.298109 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 15:35:57.301682 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 15:35:57.307940 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 15:35:57.311095 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3144 15:35:57.314482 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3145 15:35:57.321264 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3146 15:35:57.324370 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 15:35:57.327756 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 15:35:57.334459 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 15:35:57.337737 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 15:35:57.340994 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 15:35:57.347556 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 15:35:57.350988 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 15:35:57.354384 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 15:35:57.360613 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 15:35:57.364080 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 15:35:57.367482 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 15:35:57.373776 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 15:35:57.377484 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 15:35:57.380318 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3160 15:35:57.387179 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3161 15:35:57.390533 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 15:35:57.393446 Total UI for P1: 0, mck2ui 16
3163 15:35:57.396727 best dqsien dly found for B0: ( 1, 3, 26)
3164 15:35:57.400141 Total UI for P1: 0, mck2ui 16
3165 15:35:57.403506 best dqsien dly found for B1: ( 1, 3, 26)
3166 15:35:57.407010 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3167 15:35:57.410148 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3168 15:35:57.410252
3169 15:35:57.413131 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3170 15:35:57.416443 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3171 15:35:57.420001 [Gating] SW calibration Done
3172 15:35:57.420081 ==
3173 15:35:57.423054 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 15:35:57.429903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 15:35:57.429980 ==
3176 15:35:57.430042 RX Vref Scan: 0
3177 15:35:57.430105
3178 15:35:57.432951 RX Vref 0 -> 0, step: 1
3179 15:35:57.433024
3180 15:35:57.436654 RX Delay -40 -> 252, step: 8
3181 15:35:57.439849 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3182 15:35:57.443454 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3183 15:35:57.446292 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3184 15:35:57.449998 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3185 15:35:57.456733 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3186 15:35:57.459801 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3187 15:35:57.463324 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3188 15:35:57.466531 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3189 15:35:57.469529 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3190 15:35:57.476356 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3191 15:35:57.479847 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3192 15:35:57.482723 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3193 15:35:57.486197 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3194 15:35:57.492618 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3195 15:35:57.495669 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3196 15:35:57.498999 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3197 15:35:57.499074 ==
3198 15:35:57.502414 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 15:35:57.505899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 15:35:57.505980 ==
3201 15:35:57.509126 DQS Delay:
3202 15:35:57.509198 DQS0 = 0, DQS1 = 0
3203 15:35:57.512648 DQM Delay:
3204 15:35:57.512748 DQM0 = 115, DQM1 = 112
3205 15:35:57.512838 DQ Delay:
3206 15:35:57.515611 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3207 15:35:57.522463 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3208 15:35:57.526003 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3209 15:35:57.528997 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3210 15:35:57.529095
3211 15:35:57.529177
3212 15:35:57.529236 ==
3213 15:35:57.532391 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 15:35:57.535808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 15:35:57.535929 ==
3216 15:35:57.536038
3217 15:35:57.536125
3218 15:35:57.538769 TX Vref Scan disable
3219 15:35:57.542510 == TX Byte 0 ==
3220 15:35:57.545323 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3221 15:35:57.548907 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3222 15:35:57.552156 == TX Byte 1 ==
3223 15:35:57.555606 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3224 15:35:57.558908 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3225 15:35:57.559006 ==
3226 15:35:57.562224 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 15:35:57.565404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 15:35:57.568901 ==
3229 15:35:57.578605 TX Vref=22, minBit 9, minWin=23, winSum=406
3230 15:35:57.582099 TX Vref=24, minBit 9, minWin=24, winSum=414
3231 15:35:57.585478 TX Vref=26, minBit 2, minWin=25, winSum=418
3232 15:35:57.588932 TX Vref=28, minBit 9, minWin=25, winSum=426
3233 15:35:57.592029 TX Vref=30, minBit 9, minWin=25, winSum=425
3234 15:35:57.595258 TX Vref=32, minBit 9, minWin=24, winSum=424
3235 15:35:57.601628 [TxChooseVref] Worse bit 9, Min win 25, Win sum 426, Final Vref 28
3236 15:35:57.601726
3237 15:35:57.605878 Final TX Range 1 Vref 28
3238 15:35:57.605949
3239 15:35:57.606037 ==
3240 15:35:57.608350 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 15:35:57.611750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 15:35:57.611847 ==
3243 15:35:57.615163
3244 15:35:57.615261
3245 15:35:57.615353 TX Vref Scan disable
3246 15:35:57.618289 == TX Byte 0 ==
3247 15:35:57.621683 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3248 15:35:57.625266 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3249 15:35:57.628969 == TX Byte 1 ==
3250 15:35:57.631922 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3251 15:35:57.635256 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3252 15:35:57.638304
3253 15:35:57.638400 [DATLAT]
3254 15:35:57.638492 Freq=1200, CH1 RK0
3255 15:35:57.638580
3256 15:35:57.641600 DATLAT Default: 0xd
3257 15:35:57.641687 0, 0xFFFF, sum = 0
3258 15:35:57.644940 1, 0xFFFF, sum = 0
3259 15:35:57.645010 2, 0xFFFF, sum = 0
3260 15:35:57.648296 3, 0xFFFF, sum = 0
3261 15:35:57.648370 4, 0xFFFF, sum = 0
3262 15:35:57.651765 5, 0xFFFF, sum = 0
3263 15:35:57.654805 6, 0xFFFF, sum = 0
3264 15:35:57.654877 7, 0xFFFF, sum = 0
3265 15:35:57.658270 8, 0xFFFF, sum = 0
3266 15:35:57.658367 9, 0xFFFF, sum = 0
3267 15:35:57.661533 10, 0xFFFF, sum = 0
3268 15:35:57.661631 11, 0xFFFF, sum = 0
3269 15:35:57.664969 12, 0x0, sum = 1
3270 15:35:57.665039 13, 0x0, sum = 2
3271 15:35:57.668338 14, 0x0, sum = 3
3272 15:35:57.668410 15, 0x0, sum = 4
3273 15:35:57.668476 best_step = 13
3274 15:35:57.671355
3275 15:35:57.671448 ==
3276 15:35:57.674640 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 15:35:57.678224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 15:35:57.678345 ==
3279 15:35:57.678440 RX Vref Scan: 1
3280 15:35:57.678528
3281 15:35:57.681249 Set Vref Range= 32 -> 127
3282 15:35:57.681351
3283 15:35:57.685012 RX Vref 32 -> 127, step: 1
3284 15:35:57.685089
3285 15:35:57.688318 RX Delay -13 -> 252, step: 4
3286 15:35:57.688394
3287 15:35:57.691206 Set Vref, RX VrefLevel [Byte0]: 32
3288 15:35:57.694824 [Byte1]: 32
3289 15:35:57.694896
3290 15:35:57.698085 Set Vref, RX VrefLevel [Byte0]: 33
3291 15:35:57.701144 [Byte1]: 33
3292 15:35:57.704962
3293 15:35:57.705035 Set Vref, RX VrefLevel [Byte0]: 34
3294 15:35:57.708459 [Byte1]: 34
3295 15:35:57.712377
3296 15:35:57.712448 Set Vref, RX VrefLevel [Byte0]: 35
3297 15:35:57.716040 [Byte1]: 35
3298 15:35:57.720710
3299 15:35:57.720782 Set Vref, RX VrefLevel [Byte0]: 36
3300 15:35:57.723660 [Byte1]: 36
3301 15:35:57.728718
3302 15:35:57.728818 Set Vref, RX VrefLevel [Byte0]: 37
3303 15:35:57.731696 [Byte1]: 37
3304 15:35:57.736364
3305 15:35:57.736442 Set Vref, RX VrefLevel [Byte0]: 38
3306 15:35:57.739438 [Byte1]: 38
3307 15:35:57.744378
3308 15:35:57.744459 Set Vref, RX VrefLevel [Byte0]: 39
3309 15:35:57.747436 [Byte1]: 39
3310 15:35:57.751732
3311 15:35:57.751840 Set Vref, RX VrefLevel [Byte0]: 40
3312 15:35:57.755117 [Byte1]: 40
3313 15:35:57.759606
3314 15:35:57.759703 Set Vref, RX VrefLevel [Byte0]: 41
3315 15:35:57.762963 [Byte1]: 41
3316 15:35:57.767417
3317 15:35:57.767489 Set Vref, RX VrefLevel [Byte0]: 42
3318 15:35:57.770904 [Byte1]: 42
3319 15:35:57.775459
3320 15:35:57.775556 Set Vref, RX VrefLevel [Byte0]: 43
3321 15:35:57.778980 [Byte1]: 43
3322 15:35:57.783608
3323 15:35:57.783710 Set Vref, RX VrefLevel [Byte0]: 44
3324 15:35:57.786927 [Byte1]: 44
3325 15:35:57.791303
3326 15:35:57.791402 Set Vref, RX VrefLevel [Byte0]: 45
3327 15:35:57.794639 [Byte1]: 45
3328 15:35:57.799323
3329 15:35:57.799423 Set Vref, RX VrefLevel [Byte0]: 46
3330 15:35:57.802672 [Byte1]: 46
3331 15:35:57.806840
3332 15:35:57.806937 Set Vref, RX VrefLevel [Byte0]: 47
3333 15:35:57.810627 [Byte1]: 47
3334 15:35:57.815506
3335 15:35:57.815607 Set Vref, RX VrefLevel [Byte0]: 48
3336 15:35:57.818304 [Byte1]: 48
3337 15:35:57.822786
3338 15:35:57.822887 Set Vref, RX VrefLevel [Byte0]: 49
3339 15:35:57.826230 [Byte1]: 49
3340 15:35:57.831127
3341 15:35:57.831225 Set Vref, RX VrefLevel [Byte0]: 50
3342 15:35:57.834235 [Byte1]: 50
3343 15:35:57.838572
3344 15:35:57.838661 Set Vref, RX VrefLevel [Byte0]: 51
3345 15:35:57.841899 [Byte1]: 51
3346 15:35:57.846687
3347 15:35:57.846796 Set Vref, RX VrefLevel [Byte0]: 52
3348 15:35:57.849704 [Byte1]: 52
3349 15:35:57.854269
3350 15:35:57.854373 Set Vref, RX VrefLevel [Byte0]: 53
3351 15:35:57.857881 [Byte1]: 53
3352 15:35:57.862089
3353 15:35:57.862163 Set Vref, RX VrefLevel [Byte0]: 54
3354 15:35:57.865544 [Byte1]: 54
3355 15:35:57.870029
3356 15:35:57.870103 Set Vref, RX VrefLevel [Byte0]: 55
3357 15:35:57.873636 [Byte1]: 55
3358 15:35:57.878199
3359 15:35:57.878310 Set Vref, RX VrefLevel [Byte0]: 56
3360 15:35:57.881089 [Byte1]: 56
3361 15:35:57.886140
3362 15:35:57.886217 Set Vref, RX VrefLevel [Byte0]: 57
3363 15:35:57.889151 [Byte1]: 57
3364 15:35:57.894013
3365 15:35:57.894086 Set Vref, RX VrefLevel [Byte0]: 58
3366 15:35:57.897606 [Byte1]: 58
3367 15:35:57.901669
3368 15:35:57.901744 Set Vref, RX VrefLevel [Byte0]: 59
3369 15:35:57.904760 [Byte1]: 59
3370 15:35:57.909286
3371 15:35:57.909365 Set Vref, RX VrefLevel [Byte0]: 60
3372 15:35:57.912670 [Byte1]: 60
3373 15:35:57.917305
3374 15:35:57.917376 Set Vref, RX VrefLevel [Byte0]: 61
3375 15:35:57.920657 [Byte1]: 61
3376 15:35:57.925227
3377 15:35:57.925306 Set Vref, RX VrefLevel [Byte0]: 62
3378 15:35:57.928675 [Byte1]: 62
3379 15:35:57.933409
3380 15:35:57.933482 Set Vref, RX VrefLevel [Byte0]: 63
3381 15:35:57.936914 [Byte1]: 63
3382 15:35:57.941306
3383 15:35:57.941403 Set Vref, RX VrefLevel [Byte0]: 64
3384 15:35:57.944385 [Byte1]: 64
3385 15:35:57.948940
3386 15:35:57.949046 Final RX Vref Byte 0 = 51 to rank0
3387 15:35:57.952620 Final RX Vref Byte 1 = 50 to rank0
3388 15:35:57.955365 Final RX Vref Byte 0 = 51 to rank1
3389 15:35:57.958776 Final RX Vref Byte 1 = 50 to rank1==
3390 15:35:57.962186 Dram Type= 6, Freq= 0, CH_1, rank 0
3391 15:35:57.968867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3392 15:35:57.968952 ==
3393 15:35:57.969016 DQS Delay:
3394 15:35:57.969075 DQS0 = 0, DQS1 = 0
3395 15:35:57.971859 DQM Delay:
3396 15:35:57.971986 DQM0 = 114, DQM1 = 112
3397 15:35:57.975601 DQ Delay:
3398 15:35:57.978464 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3399 15:35:57.982348 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3400 15:35:57.985360 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3401 15:35:57.988675 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3402 15:35:57.988753
3403 15:35:57.988815
3404 15:35:57.998797 [DQSOSCAuto] RK0, (LSB)MR18= 0xf400, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3405 15:35:57.998904 CH1 RK0: MR19=304, MR18=F400
3406 15:35:58.005387 CH1_RK0: MR19=0x304, MR18=0xF400, DQSOSC=410, MR23=63, INC=39, DEC=26
3407 15:35:58.005465
3408 15:35:58.008564 ----->DramcWriteLeveling(PI) begin...
3409 15:35:58.008651 ==
3410 15:35:58.012097 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 15:35:58.018455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3412 15:35:58.018533 ==
3413 15:35:58.021693 Write leveling (Byte 0): 25 => 25
3414 15:35:58.021763 Write leveling (Byte 1): 29 => 29
3415 15:35:58.025144 DramcWriteLeveling(PI) end<-----
3416 15:35:58.025224
3417 15:35:58.028595 ==
3418 15:35:58.028669 Dram Type= 6, Freq= 0, CH_1, rank 1
3419 15:35:58.034975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3420 15:35:58.035066 ==
3421 15:35:58.038545 [Gating] SW mode calibration
3422 15:35:58.045161 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3423 15:35:58.048064 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3424 15:35:58.055026 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3425 15:35:58.058486 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3426 15:35:58.062102 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 15:35:58.068387 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 15:35:58.072208 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 15:35:58.075099 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 15:35:58.081267 0 15 24 | B1->B0 | 3434 2626 | 1 1 | (1 0) (1 0)
3431 15:35:58.084729 0 15 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
3432 15:35:58.088157 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3433 15:35:58.094783 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 15:35:58.098231 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 15:35:58.101355 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 15:35:58.107771 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 15:35:58.111281 1 0 20 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
3438 15:35:58.114362 1 0 24 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
3439 15:35:58.121499 1 0 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3440 15:35:58.124541 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 15:35:58.127367 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 15:35:58.134017 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 15:35:58.137588 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 15:35:58.140668 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 15:35:58.147648 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 15:35:58.150512 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3447 15:35:58.153640 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3448 15:35:58.160294 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3449 15:35:58.163360 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 15:35:58.166963 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 15:35:58.173335 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 15:35:58.176538 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 15:35:58.180037 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 15:35:58.186741 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 15:35:58.190092 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 15:35:58.193323 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 15:35:58.200408 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 15:35:58.203245 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 15:35:58.206586 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 15:35:58.213183 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 15:35:58.216119 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3462 15:35:58.219607 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3463 15:35:58.226087 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3464 15:35:58.229345 Total UI for P1: 0, mck2ui 16
3465 15:35:58.232510 best dqsien dly found for B0: ( 1, 3, 22)
3466 15:35:58.236021 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3467 15:35:58.239328 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 15:35:58.242232 Total UI for P1: 0, mck2ui 16
3469 15:35:58.245698 best dqsien dly found for B1: ( 1, 3, 30)
3470 15:35:58.248595 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3471 15:35:58.255486 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3472 15:35:58.255592
3473 15:35:58.258769 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3474 15:35:58.262384 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3475 15:35:58.265524 [Gating] SW calibration Done
3476 15:35:58.265622 ==
3477 15:35:58.268683 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 15:35:58.272252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 15:35:58.272353 ==
3480 15:35:58.275112 RX Vref Scan: 0
3481 15:35:58.275203
3482 15:35:58.275296 RX Vref 0 -> 0, step: 1
3483 15:35:58.275383
3484 15:35:58.278573 RX Delay -40 -> 252, step: 8
3485 15:35:58.282035 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3486 15:35:58.288227 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3487 15:35:58.291932 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3488 15:35:58.294789 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3489 15:35:58.298022 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3490 15:35:58.301454 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3491 15:35:58.308126 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3492 15:35:58.311068 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3493 15:35:58.314396 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3494 15:35:58.317830 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3495 15:35:58.321165 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3496 15:35:58.328220 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3497 15:35:58.331283 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3498 15:35:58.334199 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3499 15:35:58.337423 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3500 15:35:58.344164 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3501 15:35:58.344247 ==
3502 15:35:58.347187 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 15:35:58.350985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 15:35:58.351089 ==
3505 15:35:58.351186 DQS Delay:
3506 15:35:58.354110 DQS0 = 0, DQS1 = 0
3507 15:35:58.354284 DQM Delay:
3508 15:35:58.357539 DQM0 = 114, DQM1 = 111
3509 15:35:58.357653 DQ Delay:
3510 15:35:58.360534 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3511 15:35:58.363742 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =111
3512 15:35:58.367623 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3513 15:35:58.370254 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3514 15:35:58.370354
3515 15:35:58.370443
3516 15:35:58.373583 ==
3517 15:35:58.376968 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 15:35:58.380343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 15:35:58.380473 ==
3520 15:35:58.380583
3521 15:35:58.380677
3522 15:35:58.383413 TX Vref Scan disable
3523 15:35:58.383526 == TX Byte 0 ==
3524 15:35:58.390174 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3525 15:35:58.393548 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3526 15:35:58.393653 == TX Byte 1 ==
3527 15:35:58.399893 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3528 15:35:58.403450 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3529 15:35:58.403557 ==
3530 15:35:58.407450 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 15:35:58.410034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 15:35:58.410114 ==
3533 15:35:58.422741 TX Vref=22, minBit 2, minWin=25, winSum=419
3534 15:35:58.425788 TX Vref=24, minBit 3, minWin=25, winSum=425
3535 15:35:58.428955 TX Vref=26, minBit 1, minWin=26, winSum=428
3536 15:35:58.432147 TX Vref=28, minBit 1, minWin=26, winSum=430
3537 15:35:58.435692 TX Vref=30, minBit 0, minWin=26, winSum=431
3538 15:35:58.442055 TX Vref=32, minBit 2, minWin=26, winSum=432
3539 15:35:58.446004 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 32
3540 15:35:58.446115
3541 15:35:58.449032 Final TX Range 1 Vref 32
3542 15:35:58.449135
3543 15:35:58.449237 ==
3544 15:35:58.452328 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 15:35:58.455150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 15:35:58.458374 ==
3547 15:35:58.458474
3548 15:35:58.458578
3549 15:35:58.458700 TX Vref Scan disable
3550 15:35:58.461994 == TX Byte 0 ==
3551 15:35:58.465269 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3552 15:35:58.471875 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3553 15:35:58.472002 == TX Byte 1 ==
3554 15:35:58.475335 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3555 15:35:58.482189 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3556 15:35:58.482314
3557 15:35:58.482407 [DATLAT]
3558 15:35:58.482476 Freq=1200, CH1 RK1
3559 15:35:58.482536
3560 15:35:58.485667 DATLAT Default: 0xd
3561 15:35:58.485765 0, 0xFFFF, sum = 0
3562 15:35:58.488604 1, 0xFFFF, sum = 0
3563 15:35:58.492059 2, 0xFFFF, sum = 0
3564 15:35:58.492160 3, 0xFFFF, sum = 0
3565 15:35:58.495537 4, 0xFFFF, sum = 0
3566 15:35:58.495637 5, 0xFFFF, sum = 0
3567 15:35:58.498518 6, 0xFFFF, sum = 0
3568 15:35:58.498628 7, 0xFFFF, sum = 0
3569 15:35:58.502076 8, 0xFFFF, sum = 0
3570 15:35:58.502179 9, 0xFFFF, sum = 0
3571 15:35:58.505695 10, 0xFFFF, sum = 0
3572 15:35:58.505808 11, 0xFFFF, sum = 0
3573 15:35:58.508528 12, 0x0, sum = 1
3574 15:35:58.508606 13, 0x0, sum = 2
3575 15:35:58.511966 14, 0x0, sum = 3
3576 15:35:58.512048 15, 0x0, sum = 4
3577 15:35:58.514895 best_step = 13
3578 15:35:58.515001
3579 15:35:58.515102 ==
3580 15:35:58.518860 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 15:35:58.522030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 15:35:58.522139 ==
3583 15:35:58.522232 RX Vref Scan: 0
3584 15:35:58.524970
3585 15:35:58.525046 RX Vref 0 -> 0, step: 1
3586 15:35:58.525126
3587 15:35:58.528160 RX Delay -13 -> 252, step: 4
3588 15:35:58.534838 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3589 15:35:58.538090 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3590 15:35:58.541248 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3591 15:35:58.544500 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3592 15:35:58.548242 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3593 15:35:58.554629 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3594 15:35:58.557685 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3595 15:35:58.561126 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3596 15:35:58.564843 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3597 15:35:58.567624 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3598 15:35:58.574379 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3599 15:35:58.577830 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3600 15:35:58.581628 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3601 15:35:58.584546 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3602 15:35:58.590787 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3603 15:35:58.594261 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3604 15:35:58.594367 ==
3605 15:35:58.597733 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 15:35:58.601409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 15:35:58.601510 ==
3608 15:35:58.601601 DQS Delay:
3609 15:35:58.604584 DQS0 = 0, DQS1 = 0
3610 15:35:58.604686 DQM Delay:
3611 15:35:58.607431 DQM0 = 115, DQM1 = 112
3612 15:35:58.607529 DQ Delay:
3613 15:35:58.610894 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3614 15:35:58.614360 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3615 15:35:58.617766 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3616 15:35:58.623732 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3617 15:35:58.623834
3618 15:35:58.623958
3619 15:35:58.630170 [DQSOSCAuto] RK1, (LSB)MR18= 0xf709, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3620 15:35:58.633594 CH1 RK1: MR19=304, MR18=F709
3621 15:35:58.640230 CH1_RK1: MR19=0x304, MR18=0xF709, DQSOSC=406, MR23=63, INC=39, DEC=26
3622 15:35:58.643624 [RxdqsGatingPostProcess] freq 1200
3623 15:35:58.647026 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3624 15:35:58.650167 best DQS0 dly(2T, 0.5T) = (0, 11)
3625 15:35:58.653646 best DQS1 dly(2T, 0.5T) = (0, 11)
3626 15:35:58.656847 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3627 15:35:58.660148 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3628 15:35:58.663165 best DQS0 dly(2T, 0.5T) = (0, 11)
3629 15:35:58.666843 best DQS1 dly(2T, 0.5T) = (0, 11)
3630 15:35:58.669842 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3631 15:35:58.673569 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3632 15:35:58.676397 Pre-setting of DQS Precalculation
3633 15:35:58.680144 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3634 15:35:58.689739 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3635 15:35:58.696088 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3636 15:35:58.696171
3637 15:35:58.696266
3638 15:35:58.699542 [Calibration Summary] 2400 Mbps
3639 15:35:58.699641 CH 0, Rank 0
3640 15:35:58.703097 SW Impedance : PASS
3641 15:35:58.706611 DUTY Scan : NO K
3642 15:35:58.706715 ZQ Calibration : PASS
3643 15:35:58.709451 Jitter Meter : NO K
3644 15:35:58.709545 CBT Training : PASS
3645 15:35:58.712915 Write leveling : PASS
3646 15:35:58.716459 RX DQS gating : PASS
3647 15:35:58.716535 RX DQ/DQS(RDDQC) : PASS
3648 15:35:58.719237 TX DQ/DQS : PASS
3649 15:35:58.722616 RX DATLAT : PASS
3650 15:35:58.722713 RX DQ/DQS(Engine): PASS
3651 15:35:58.725919 TX OE : NO K
3652 15:35:58.726018 All Pass.
3653 15:35:58.726108
3654 15:35:58.729436 CH 0, Rank 1
3655 15:35:58.729547 SW Impedance : PASS
3656 15:35:58.732842 DUTY Scan : NO K
3657 15:35:58.736034 ZQ Calibration : PASS
3658 15:35:58.736113 Jitter Meter : NO K
3659 15:35:58.739236 CBT Training : PASS
3660 15:35:58.742701 Write leveling : PASS
3661 15:35:58.742805 RX DQS gating : PASS
3662 15:35:58.745507 RX DQ/DQS(RDDQC) : PASS
3663 15:35:58.748885 TX DQ/DQS : PASS
3664 15:35:58.748994 RX DATLAT : PASS
3665 15:35:58.752058 RX DQ/DQS(Engine): PASS
3666 15:35:58.755502 TX OE : NO K
3667 15:35:58.755602 All Pass.
3668 15:35:58.755693
3669 15:35:58.755782 CH 1, Rank 0
3670 15:35:58.758991 SW Impedance : PASS
3671 15:35:58.762616 DUTY Scan : NO K
3672 15:35:58.762717 ZQ Calibration : PASS
3673 15:35:58.765527 Jitter Meter : NO K
3674 15:35:58.769259 CBT Training : PASS
3675 15:35:58.769365 Write leveling : PASS
3676 15:35:58.771912 RX DQS gating : PASS
3677 15:35:58.775287 RX DQ/DQS(RDDQC) : PASS
3678 15:35:58.775387 TX DQ/DQS : PASS
3679 15:35:58.779197 RX DATLAT : PASS
3680 15:35:58.779323 RX DQ/DQS(Engine): PASS
3681 15:35:58.782136 TX OE : NO K
3682 15:35:58.782239 All Pass.
3683 15:35:58.782344
3684 15:35:58.785908 CH 1, Rank 1
3685 15:35:58.788872 SW Impedance : PASS
3686 15:35:58.788968 DUTY Scan : NO K
3687 15:35:58.791894 ZQ Calibration : PASS
3688 15:35:58.792024 Jitter Meter : NO K
3689 15:35:58.795047 CBT Training : PASS
3690 15:35:58.798842 Write leveling : PASS
3691 15:35:58.798946 RX DQS gating : PASS
3692 15:35:58.801691 RX DQ/DQS(RDDQC) : PASS
3693 15:35:58.804994 TX DQ/DQS : PASS
3694 15:35:58.805068 RX DATLAT : PASS
3695 15:35:58.808806 RX DQ/DQS(Engine): PASS
3696 15:35:58.811827 TX OE : NO K
3697 15:35:58.811962 All Pass.
3698 15:35:58.812026
3699 15:35:58.814794 DramC Write-DBI off
3700 15:35:58.814901 PER_BANK_REFRESH: Hybrid Mode
3701 15:35:58.818125 TX_TRACKING: ON
3702 15:35:58.828464 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3703 15:35:58.831209 [FAST_K] Save calibration result to emmc
3704 15:35:58.834863 dramc_set_vcore_voltage set vcore to 650000
3705 15:35:58.838095 Read voltage for 600, 5
3706 15:35:58.838194 Vio18 = 0
3707 15:35:58.838296 Vcore = 650000
3708 15:35:58.838385 Vdram = 0
3709 15:35:58.842114 Vddq = 0
3710 15:35:58.842215 Vmddr = 0
3711 15:35:58.847786 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3712 15:35:58.851173 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3713 15:35:58.854717 MEM_TYPE=3, freq_sel=19
3714 15:35:58.857705 sv_algorithm_assistance_LP4_1600
3715 15:35:58.860945 ============ PULL DRAM RESETB DOWN ============
3716 15:35:58.864606 ========== PULL DRAM RESETB DOWN end =========
3717 15:35:58.871074 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3718 15:35:58.874137 ===================================
3719 15:35:58.874249 LPDDR4 DRAM CONFIGURATION
3720 15:35:58.877765 ===================================
3721 15:35:58.881022 EX_ROW_EN[0] = 0x0
3722 15:35:58.884177 EX_ROW_EN[1] = 0x0
3723 15:35:58.884309 LP4Y_EN = 0x0
3724 15:35:58.887734 WORK_FSP = 0x0
3725 15:35:58.887853 WL = 0x2
3726 15:35:58.890500 RL = 0x2
3727 15:35:58.890598 BL = 0x2
3728 15:35:58.893924 RPST = 0x0
3729 15:35:58.894022 RD_PRE = 0x0
3730 15:35:58.897392 WR_PRE = 0x1
3731 15:35:58.897491 WR_PST = 0x0
3732 15:35:58.900425 DBI_WR = 0x0
3733 15:35:58.900520 DBI_RD = 0x0
3734 15:35:58.903832 OTF = 0x1
3735 15:35:58.907197 ===================================
3736 15:35:58.910323 ===================================
3737 15:35:58.910418 ANA top config
3738 15:35:58.913844 ===================================
3739 15:35:58.916699 DLL_ASYNC_EN = 0
3740 15:35:58.920165 ALL_SLAVE_EN = 1
3741 15:35:58.923368 NEW_RANK_MODE = 1
3742 15:35:58.923480 DLL_IDLE_MODE = 1
3743 15:35:58.926774 LP45_APHY_COMB_EN = 1
3744 15:35:58.929840 TX_ODT_DIS = 1
3745 15:35:58.933391 NEW_8X_MODE = 1
3746 15:35:58.936587 ===================================
3747 15:35:58.939779 ===================================
3748 15:35:58.943050 data_rate = 1200
3749 15:35:58.946598 CKR = 1
3750 15:35:58.946738 DQ_P2S_RATIO = 8
3751 15:35:58.949663 ===================================
3752 15:35:58.953029 CA_P2S_RATIO = 8
3753 15:35:58.956368 DQ_CA_OPEN = 0
3754 15:35:58.959649 DQ_SEMI_OPEN = 0
3755 15:35:58.963218 CA_SEMI_OPEN = 0
3756 15:35:58.966235 CA_FULL_RATE = 0
3757 15:35:58.966335 DQ_CKDIV4_EN = 1
3758 15:35:58.969506 CA_CKDIV4_EN = 1
3759 15:35:58.972919 CA_PREDIV_EN = 0
3760 15:35:58.976389 PH8_DLY = 0
3761 15:35:58.979411 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3762 15:35:58.982755 DQ_AAMCK_DIV = 4
3763 15:35:58.982864 CA_AAMCK_DIV = 4
3764 15:35:58.986179 CA_ADMCK_DIV = 4
3765 15:35:58.989549 DQ_TRACK_CA_EN = 0
3766 15:35:58.992482 CA_PICK = 600
3767 15:35:58.995819 CA_MCKIO = 600
3768 15:35:58.999240 MCKIO_SEMI = 0
3769 15:35:59.002394 PLL_FREQ = 2288
3770 15:35:59.005657 DQ_UI_PI_RATIO = 32
3771 15:35:59.005759 CA_UI_PI_RATIO = 0
3772 15:35:59.009143 ===================================
3773 15:35:59.012345 ===================================
3774 15:35:59.015877 memory_type:LPDDR4
3775 15:35:59.019148 GP_NUM : 10
3776 15:35:59.019252 SRAM_EN : 1
3777 15:35:59.022639 MD32_EN : 0
3778 15:35:59.025535 ===================================
3779 15:35:59.029072 [ANA_INIT] >>>>>>>>>>>>>>
3780 15:35:59.032062 <<<<<< [CONFIGURE PHASE]: ANA_TX
3781 15:35:59.035569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3782 15:35:59.038469 ===================================
3783 15:35:59.038575 data_rate = 1200,PCW = 0X5800
3784 15:35:59.042160 ===================================
3785 15:35:59.045186 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3786 15:35:59.052606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3787 15:35:59.058540 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3788 15:35:59.061496 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3789 15:35:59.064829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3790 15:35:59.068567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3791 15:35:59.071753 [ANA_INIT] flow start
3792 15:35:59.075214 [ANA_INIT] PLL >>>>>>>>
3793 15:35:59.075318 [ANA_INIT] PLL <<<<<<<<
3794 15:35:59.078059 [ANA_INIT] MIDPI >>>>>>>>
3795 15:35:59.081379 [ANA_INIT] MIDPI <<<<<<<<
3796 15:35:59.081487 [ANA_INIT] DLL >>>>>>>>
3797 15:35:59.084762 [ANA_INIT] flow end
3798 15:35:59.088140 ============ LP4 DIFF to SE enter ============
3799 15:35:59.094544 ============ LP4 DIFF to SE exit ============
3800 15:35:59.094657 [ANA_INIT] <<<<<<<<<<<<<
3801 15:35:59.097885 [Flow] Enable top DCM control >>>>>
3802 15:35:59.101074 [Flow] Enable top DCM control <<<<<
3803 15:35:59.104485 Enable DLL master slave shuffle
3804 15:35:59.110928 ==============================================================
3805 15:35:59.111009 Gating Mode config
3806 15:35:59.117861 ==============================================================
3807 15:35:59.121158 Config description:
3808 15:35:59.131155 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3809 15:35:59.137581 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3810 15:35:59.140860 SELPH_MODE 0: By rank 1: By Phase
3811 15:35:59.147032 ==============================================================
3812 15:35:59.151108 GAT_TRACK_EN = 1
3813 15:35:59.154272 RX_GATING_MODE = 2
3814 15:35:59.154356 RX_GATING_TRACK_MODE = 2
3815 15:35:59.157536 SELPH_MODE = 1
3816 15:35:59.160401 PICG_EARLY_EN = 1
3817 15:35:59.163810 VALID_LAT_VALUE = 1
3818 15:35:59.170425 ==============================================================
3819 15:35:59.173634 Enter into Gating configuration >>>>
3820 15:35:59.176977 Exit from Gating configuration <<<<
3821 15:35:59.180141 Enter into DVFS_PRE_config >>>>>
3822 15:35:59.189898 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3823 15:35:59.193275 Exit from DVFS_PRE_config <<<<<
3824 15:35:59.196535 Enter into PICG configuration >>>>
3825 15:35:59.199966 Exit from PICG configuration <<<<
3826 15:35:59.203767 [RX_INPUT] configuration >>>>>
3827 15:35:59.206572 [RX_INPUT] configuration <<<<<
3828 15:35:59.210144 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3829 15:35:59.216379 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3830 15:35:59.223273 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3831 15:35:59.229678 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3832 15:35:59.236427 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3833 15:35:59.239732 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3834 15:35:59.245957 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3835 15:35:59.249358 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3836 15:35:59.252692 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3837 15:35:59.256136 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3838 15:35:59.262553 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3839 15:35:59.265838 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3840 15:35:59.269128 ===================================
3841 15:35:59.272546 LPDDR4 DRAM CONFIGURATION
3842 15:35:59.275742 ===================================
3843 15:35:59.275855 EX_ROW_EN[0] = 0x0
3844 15:35:59.279042 EX_ROW_EN[1] = 0x0
3845 15:35:59.279145 LP4Y_EN = 0x0
3846 15:35:59.282562 WORK_FSP = 0x0
3847 15:35:59.282685 WL = 0x2
3848 15:35:59.285518 RL = 0x2
3849 15:35:59.285636 BL = 0x2
3850 15:35:59.289077 RPST = 0x0
3851 15:35:59.292132 RD_PRE = 0x0
3852 15:35:59.292222 WR_PRE = 0x1
3853 15:35:59.295925 WR_PST = 0x0
3854 15:35:59.296018 DBI_WR = 0x0
3855 15:35:59.299005 DBI_RD = 0x0
3856 15:35:59.299109 OTF = 0x1
3857 15:35:59.301939 ===================================
3858 15:35:59.305312 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3859 15:35:59.312013 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3860 15:35:59.315294 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3861 15:35:59.318794 ===================================
3862 15:35:59.321792 LPDDR4 DRAM CONFIGURATION
3863 15:35:59.325078 ===================================
3864 15:35:59.325153 EX_ROW_EN[0] = 0x10
3865 15:35:59.328223 EX_ROW_EN[1] = 0x0
3866 15:35:59.328296 LP4Y_EN = 0x0
3867 15:35:59.331558 WORK_FSP = 0x0
3868 15:35:59.334785 WL = 0x2
3869 15:35:59.334883 RL = 0x2
3870 15:35:59.337993 BL = 0x2
3871 15:35:59.338100 RPST = 0x0
3872 15:35:59.341589 RD_PRE = 0x0
3873 15:35:59.341659 WR_PRE = 0x1
3874 15:35:59.344852 WR_PST = 0x0
3875 15:35:59.344967 DBI_WR = 0x0
3876 15:35:59.347879 DBI_RD = 0x0
3877 15:35:59.347997 OTF = 0x1
3878 15:35:59.351373 ===================================
3879 15:35:59.358250 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3880 15:35:59.362032 nWR fixed to 30
3881 15:35:59.365886 [ModeRegInit_LP4] CH0 RK0
3882 15:35:59.366004 [ModeRegInit_LP4] CH0 RK1
3883 15:35:59.368533 [ModeRegInit_LP4] CH1 RK0
3884 15:35:59.371932 [ModeRegInit_LP4] CH1 RK1
3885 15:35:59.372032 match AC timing 17
3886 15:35:59.378383 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3887 15:35:59.381801 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3888 15:35:59.385804 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3889 15:35:59.391941 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3890 15:35:59.395024 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3891 15:35:59.395143 ==
3892 15:35:59.398294 Dram Type= 6, Freq= 0, CH_0, rank 0
3893 15:35:59.401378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3894 15:35:59.404998 ==
3895 15:35:59.408396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3896 15:35:59.414753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3897 15:35:59.418264 [CA 0] Center 36 (6~67) winsize 62
3898 15:35:59.421101 [CA 1] Center 36 (5~67) winsize 63
3899 15:35:59.424588 [CA 2] Center 34 (4~65) winsize 62
3900 15:35:59.428021 [CA 3] Center 34 (3~65) winsize 63
3901 15:35:59.431623 [CA 4] Center 33 (3~64) winsize 62
3902 15:35:59.434198 [CA 5] Center 33 (3~64) winsize 62
3903 15:35:59.434295
3904 15:35:59.437838 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3905 15:35:59.437932
3906 15:35:59.440794 [CATrainingPosCal] consider 1 rank data
3907 15:35:59.444435 u2DelayCellTimex100 = 270/100 ps
3908 15:35:59.447316 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3909 15:35:59.450683 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3910 15:35:59.457952 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3911 15:35:59.460682 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3912 15:35:59.464306 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3913 15:35:59.467710 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3914 15:35:59.467815
3915 15:35:59.470834 CA PerBit enable=1, Macro0, CA PI delay=33
3916 15:35:59.470950
3917 15:35:59.474190 [CBTSetCACLKResult] CA Dly = 33
3918 15:35:59.474300 CS Dly: 4 (0~35)
3919 15:35:59.477988 ==
3920 15:35:59.478124 Dram Type= 6, Freq= 0, CH_0, rank 1
3921 15:35:59.483729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3922 15:35:59.483854 ==
3923 15:35:59.487190 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3924 15:35:59.493791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3925 15:35:59.497524 [CA 0] Center 36 (6~67) winsize 62
3926 15:35:59.500695 [CA 1] Center 36 (6~67) winsize 62
3927 15:35:59.504096 [CA 2] Center 34 (4~65) winsize 62
3928 15:35:59.507491 [CA 3] Center 34 (4~65) winsize 62
3929 15:35:59.510761 [CA 4] Center 33 (3~64) winsize 62
3930 15:35:59.513812 [CA 5] Center 33 (3~64) winsize 62
3931 15:35:59.513948
3932 15:35:59.517297 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3933 15:35:59.517416
3934 15:35:59.520579 [CATrainingPosCal] consider 2 rank data
3935 15:35:59.524103 u2DelayCellTimex100 = 270/100 ps
3936 15:35:59.527166 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3937 15:35:59.533629 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3938 15:35:59.537436 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3939 15:35:59.540504 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3940 15:35:59.543761 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3941 15:35:59.547181 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3942 15:35:59.547281
3943 15:35:59.550789 CA PerBit enable=1, Macro0, CA PI delay=33
3944 15:35:59.550897
3945 15:35:59.553487 [CBTSetCACLKResult] CA Dly = 33
3946 15:35:59.557231 CS Dly: 5 (0~38)
3947 15:35:59.557332
3948 15:35:59.559829 ----->DramcWriteLeveling(PI) begin...
3949 15:35:59.559959 ==
3950 15:35:59.563653 Dram Type= 6, Freq= 0, CH_0, rank 0
3951 15:35:59.566456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 15:35:59.566561 ==
3953 15:35:59.569928 Write leveling (Byte 0): 34 => 34
3954 15:35:59.573344 Write leveling (Byte 1): 30 => 30
3955 15:35:59.576808 DramcWriteLeveling(PI) end<-----
3956 15:35:59.576916
3957 15:35:59.577012 ==
3958 15:35:59.579742 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 15:35:59.583090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 15:35:59.583216 ==
3961 15:35:59.586491 [Gating] SW mode calibration
3962 15:35:59.593071 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3963 15:35:59.599287 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3964 15:35:59.603122 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3965 15:35:59.606161 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 15:35:59.613044 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3967 15:35:59.616046 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3968 15:35:59.619739 0 9 16 | B1->B0 | 2d2d 2626 | 1 0 | (1 0) (0 0)
3969 15:35:59.626060 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 15:35:59.629558 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 15:35:59.632632 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 15:35:59.639313 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 15:35:59.642425 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 15:35:59.645758 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 15:35:59.652502 0 10 12 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
3976 15:35:59.656078 0 10 16 | B1->B0 | 3939 4040 | 0 0 | (0 0) (0 0)
3977 15:35:59.658914 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 15:35:59.666204 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 15:35:59.668546 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 15:35:59.675481 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 15:35:59.678978 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 15:35:59.681634 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 15:35:59.688515 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 15:35:59.691880 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3985 15:35:59.694874 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 15:35:59.702074 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 15:35:59.704873 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 15:35:59.708137 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 15:35:59.714651 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 15:35:59.718107 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 15:35:59.721410 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 15:35:59.727969 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 15:35:59.731391 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 15:35:59.734827 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 15:35:59.740998 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 15:35:59.744501 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 15:35:59.748022 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 15:35:59.754712 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 15:35:59.757721 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 15:35:59.760649 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4001 15:35:59.764069 Total UI for P1: 0, mck2ui 16
4002 15:35:59.767508 best dqsien dly found for B0: ( 0, 13, 14)
4003 15:35:59.773992 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 15:35:59.774099 Total UI for P1: 0, mck2ui 16
4005 15:35:59.777507 best dqsien dly found for B1: ( 0, 13, 16)
4006 15:35:59.783832 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4007 15:35:59.787381 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4008 15:35:59.787486
4009 15:35:59.790439 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4010 15:35:59.793681 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4011 15:35:59.797114 [Gating] SW calibration Done
4012 15:35:59.797215 ==
4013 15:35:59.800172 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 15:35:59.803399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 15:35:59.803497 ==
4016 15:35:59.806768 RX Vref Scan: 0
4017 15:35:59.806869
4018 15:35:59.806961 RX Vref 0 -> 0, step: 1
4019 15:35:59.807058
4020 15:35:59.810126 RX Delay -230 -> 252, step: 16
4021 15:35:59.816987 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4022 15:35:59.820092 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4023 15:35:59.823041 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4024 15:35:59.826528 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4025 15:35:59.833390 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4026 15:35:59.836719 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4027 15:35:59.839787 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4028 15:35:59.843241 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4029 15:35:59.846815 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4030 15:35:59.852861 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4031 15:35:59.856338 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4032 15:35:59.859726 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4033 15:35:59.862618 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4034 15:35:59.869723 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4035 15:35:59.872602 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4036 15:35:59.875952 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4037 15:35:59.876033 ==
4038 15:35:59.879559 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 15:35:59.885793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 15:35:59.885876 ==
4041 15:35:59.885940 DQS Delay:
4042 15:35:59.888869 DQS0 = 0, DQS1 = 0
4043 15:35:59.888949 DQM Delay:
4044 15:35:59.889012 DQM0 = 45, DQM1 = 34
4045 15:35:59.892095 DQ Delay:
4046 15:35:59.895344 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4047 15:35:59.899396 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4048 15:35:59.902085 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4049 15:35:59.905932 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4050 15:35:59.906041
4051 15:35:59.906142
4052 15:35:59.906237 ==
4053 15:35:59.908649 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 15:35:59.912336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 15:35:59.912434 ==
4056 15:35:59.912511
4057 15:35:59.912601
4058 15:35:59.915317 TX Vref Scan disable
4059 15:35:59.918738 == TX Byte 0 ==
4060 15:35:59.921740 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4061 15:35:59.924976 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4062 15:35:59.928742 == TX Byte 1 ==
4063 15:35:59.932167 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4064 15:35:59.934705 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4065 15:35:59.934812 ==
4066 15:35:59.938230 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 15:35:59.944813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 15:35:59.944915 ==
4069 15:35:59.945025
4070 15:35:59.945115
4071 15:35:59.945203 TX Vref Scan disable
4072 15:35:59.949258 == TX Byte 0 ==
4073 15:35:59.952376 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4074 15:35:59.959054 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4075 15:35:59.959136 == TX Byte 1 ==
4076 15:35:59.962507 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4077 15:35:59.968788 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4078 15:35:59.968870
4079 15:35:59.968933 [DATLAT]
4080 15:35:59.968991 Freq=600, CH0 RK0
4081 15:35:59.969049
4082 15:35:59.972412 DATLAT Default: 0x9
4083 15:35:59.975423 0, 0xFFFF, sum = 0
4084 15:35:59.975504 1, 0xFFFF, sum = 0
4085 15:35:59.978673 2, 0xFFFF, sum = 0
4086 15:35:59.978784 3, 0xFFFF, sum = 0
4087 15:35:59.982172 4, 0xFFFF, sum = 0
4088 15:35:59.982277 5, 0xFFFF, sum = 0
4089 15:35:59.985315 6, 0xFFFF, sum = 0
4090 15:35:59.985425 7, 0xFFFF, sum = 0
4091 15:35:59.988261 8, 0x0, sum = 1
4092 15:35:59.988383 9, 0x0, sum = 2
4093 15:35:59.991718 10, 0x0, sum = 3
4094 15:35:59.991841 11, 0x0, sum = 4
4095 15:35:59.991977 best_step = 9
4096 15:35:59.992078
4097 15:35:59.995307 ==
4098 15:35:59.998143 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 15:36:00.001531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 15:36:00.001633 ==
4101 15:36:00.001726 RX Vref Scan: 1
4102 15:36:00.001814
4103 15:36:00.004713 RX Vref 0 -> 0, step: 1
4104 15:36:00.004812
4105 15:36:00.008460 RX Delay -195 -> 252, step: 8
4106 15:36:00.008558
4107 15:36:00.011417 Set Vref, RX VrefLevel [Byte0]: 52
4108 15:36:00.014510 [Byte1]: 59
4109 15:36:00.014609
4110 15:36:00.018636 Final RX Vref Byte 0 = 52 to rank0
4111 15:36:00.021214 Final RX Vref Byte 1 = 59 to rank0
4112 15:36:00.024370 Final RX Vref Byte 0 = 52 to rank1
4113 15:36:00.027708 Final RX Vref Byte 1 = 59 to rank1==
4114 15:36:00.031162 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 15:36:00.037551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 15:36:00.037657 ==
4117 15:36:00.037764 DQS Delay:
4118 15:36:00.040917 DQS0 = 0, DQS1 = 0
4119 15:36:00.041017 DQM Delay:
4120 15:36:00.041106 DQM0 = 41, DQM1 = 33
4121 15:36:00.044240 DQ Delay:
4122 15:36:00.047569 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4123 15:36:00.050924 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4124 15:36:00.054589 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4125 15:36:00.057208 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4126 15:36:00.057314
4127 15:36:00.057407
4128 15:36:00.064031 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4129 15:36:00.067495 CH0 RK0: MR19=808, MR18=4B43
4130 15:36:00.074036 CH0_RK0: MR19=0x808, MR18=0x4B43, DQSOSC=395, MR23=63, INC=168, DEC=112
4131 15:36:00.074145
4132 15:36:00.077487 ----->DramcWriteLeveling(PI) begin...
4133 15:36:00.077586 ==
4134 15:36:00.080715 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 15:36:00.083803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 15:36:00.083938 ==
4137 15:36:00.086991 Write leveling (Byte 0): 34 => 34
4138 15:36:00.090242 Write leveling (Byte 1): 29 => 29
4139 15:36:00.093547 DramcWriteLeveling(PI) end<-----
4140 15:36:00.093647
4141 15:36:00.093736 ==
4142 15:36:00.097108 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 15:36:00.100432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 15:36:00.103275 ==
4145 15:36:00.103384 [Gating] SW mode calibration
4146 15:36:00.113940 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4147 15:36:00.116638 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4148 15:36:00.120377 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4149 15:36:00.126324 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4150 15:36:00.129667 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4151 15:36:00.133077 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4152 15:36:00.139882 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4153 15:36:00.142809 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 15:36:00.146371 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 15:36:00.152533 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 15:36:00.156207 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 15:36:00.163030 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 15:36:00.165656 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 15:36:00.169342 0 10 12 | B1->B0 | 2525 3838 | 1 0 | (0 0) (0 0)
4160 15:36:00.175632 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
4161 15:36:00.179034 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 15:36:00.182608 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 15:36:00.189202 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 15:36:00.192031 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 15:36:00.195544 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 15:36:00.201808 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4167 15:36:00.205335 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4168 15:36:00.208729 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 15:36:00.214849 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 15:36:00.218415 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 15:36:00.222159 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 15:36:00.228132 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 15:36:00.231724 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 15:36:00.235243 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 15:36:00.241436 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 15:36:00.244709 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 15:36:00.248132 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 15:36:00.254863 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 15:36:00.257966 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 15:36:00.261249 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 15:36:00.267697 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 15:36:00.270944 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 15:36:00.274378 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4184 15:36:00.281020 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 15:36:00.281131 Total UI for P1: 0, mck2ui 16
4186 15:36:00.287594 best dqsien dly found for B0: ( 0, 13, 12)
4187 15:36:00.287676 Total UI for P1: 0, mck2ui 16
4188 15:36:00.291115 best dqsien dly found for B1: ( 0, 13, 14)
4189 15:36:00.297249 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4190 15:36:00.300842 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4191 15:36:00.300941
4192 15:36:00.304348 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4193 15:36:00.307153 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4194 15:36:00.310651 [Gating] SW calibration Done
4195 15:36:00.310756 ==
4196 15:36:00.313776 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 15:36:00.317238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 15:36:00.317340 ==
4199 15:36:00.320649 RX Vref Scan: 0
4200 15:36:00.320758
4201 15:36:00.320852 RX Vref 0 -> 0, step: 1
4202 15:36:00.320939
4203 15:36:00.323546 RX Delay -230 -> 252, step: 16
4204 15:36:00.330309 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4205 15:36:00.333735 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4206 15:36:00.337168 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4207 15:36:00.340312 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4208 15:36:00.346783 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4209 15:36:00.350509 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4210 15:36:00.353053 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4211 15:36:00.356544 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4212 15:36:00.359810 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4213 15:36:00.366390 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4214 15:36:00.369649 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4215 15:36:00.373177 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4216 15:36:00.376598 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4217 15:36:00.382947 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4218 15:36:00.386376 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4219 15:36:00.389637 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4220 15:36:00.389738 ==
4221 15:36:00.392801 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 15:36:00.399643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 15:36:00.399746 ==
4224 15:36:00.399839 DQS Delay:
4225 15:36:00.402865 DQS0 = 0, DQS1 = 0
4226 15:36:00.402962 DQM Delay:
4227 15:36:00.403064 DQM0 = 41, DQM1 = 34
4228 15:36:00.405758 DQ Delay:
4229 15:36:00.409497 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4230 15:36:00.412711 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4231 15:36:00.415833 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4232 15:36:00.419009 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4233 15:36:00.419112
4234 15:36:00.419202
4235 15:36:00.419299 ==
4236 15:36:00.422742 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 15:36:00.426045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 15:36:00.426147 ==
4239 15:36:00.426240
4240 15:36:00.426327
4241 15:36:00.429232 TX Vref Scan disable
4242 15:36:00.432048 == TX Byte 0 ==
4243 15:36:00.435480 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4244 15:36:00.438759 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4245 15:36:00.442104 == TX Byte 1 ==
4246 15:36:00.445765 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4247 15:36:00.448953 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4248 15:36:00.449055 ==
4249 15:36:00.452439 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 15:36:00.455775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 15:36:00.458850 ==
4252 15:36:00.458947
4253 15:36:00.459010
4254 15:36:00.459097 TX Vref Scan disable
4255 15:36:00.462749 == TX Byte 0 ==
4256 15:36:00.466113 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4257 15:36:00.472802 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4258 15:36:00.472888 == TX Byte 1 ==
4259 15:36:00.475850 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4260 15:36:00.482550 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4261 15:36:00.482661
4262 15:36:00.482758 [DATLAT]
4263 15:36:00.482847 Freq=600, CH0 RK1
4264 15:36:00.482944
4265 15:36:00.485747 DATLAT Default: 0x9
4266 15:36:00.485852 0, 0xFFFF, sum = 0
4267 15:36:00.489309 1, 0xFFFF, sum = 0
4268 15:36:00.492666 2, 0xFFFF, sum = 0
4269 15:36:00.492775 3, 0xFFFF, sum = 0
4270 15:36:00.496395 4, 0xFFFF, sum = 0
4271 15:36:00.496513 5, 0xFFFF, sum = 0
4272 15:36:00.499388 6, 0xFFFF, sum = 0
4273 15:36:00.499479 7, 0xFFFF, sum = 0
4274 15:36:00.502709 8, 0x0, sum = 1
4275 15:36:00.502791 9, 0x0, sum = 2
4276 15:36:00.502855 10, 0x0, sum = 3
4277 15:36:00.506546 11, 0x0, sum = 4
4278 15:36:00.506629 best_step = 9
4279 15:36:00.506691
4280 15:36:00.506750 ==
4281 15:36:00.508914 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 15:36:00.515848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 15:36:00.515992 ==
4284 15:36:00.516077 RX Vref Scan: 0
4285 15:36:00.516138
4286 15:36:00.519347 RX Vref 0 -> 0, step: 1
4287 15:36:00.519442
4288 15:36:00.522200 RX Delay -179 -> 252, step: 8
4289 15:36:00.525763 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4290 15:36:00.532457 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4291 15:36:00.535646 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4292 15:36:00.539024 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4293 15:36:00.542246 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4294 15:36:00.549135 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4295 15:36:00.551978 iDelay=197, Bit 6, Center 52 (-91 ~ 196) 288
4296 15:36:00.555653 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4297 15:36:00.558731 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4298 15:36:00.562024 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4299 15:36:00.568864 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4300 15:36:00.572157 iDelay=197, Bit 11, Center 24 (-131 ~ 180) 312
4301 15:36:00.575743 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4302 15:36:00.578425 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4303 15:36:00.585623 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4304 15:36:00.588845 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4305 15:36:00.588959 ==
4306 15:36:00.591758 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 15:36:00.595211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 15:36:00.595312 ==
4309 15:36:00.598285 DQS Delay:
4310 15:36:00.598363 DQS0 = 0, DQS1 = 0
4311 15:36:00.598432 DQM Delay:
4312 15:36:00.601647 DQM0 = 41, DQM1 = 33
4313 15:36:00.601763 DQ Delay:
4314 15:36:00.605077 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4315 15:36:00.608490 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =48
4316 15:36:00.611351 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4317 15:36:00.614757 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4318 15:36:00.614853
4319 15:36:00.614928
4320 15:36:00.624670 [DQSOSCAuto] RK1, (LSB)MR18= 0x4945, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
4321 15:36:00.628186 CH0 RK1: MR19=808, MR18=4945
4322 15:36:00.634507 CH0_RK1: MR19=0x808, MR18=0x4945, DQSOSC=396, MR23=63, INC=167, DEC=111
4323 15:36:00.634609 [RxdqsGatingPostProcess] freq 600
4324 15:36:00.641065 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4325 15:36:00.644177 Pre-setting of DQS Precalculation
4326 15:36:00.651004 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4327 15:36:00.651106 ==
4328 15:36:00.654201 Dram Type= 6, Freq= 0, CH_1, rank 0
4329 15:36:00.657493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 15:36:00.657593 ==
4331 15:36:00.664079 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4332 15:36:00.667542 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4333 15:36:00.671417 [CA 0] Center 35 (5~66) winsize 62
4334 15:36:00.674626 [CA 1] Center 35 (5~66) winsize 62
4335 15:36:00.677966 [CA 2] Center 34 (4~65) winsize 62
4336 15:36:00.681255 [CA 3] Center 34 (4~65) winsize 62
4337 15:36:00.684616 [CA 4] Center 34 (4~65) winsize 62
4338 15:36:00.688020 [CA 5] Center 33 (3~64) winsize 62
4339 15:36:00.688126
4340 15:36:00.691368 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4341 15:36:00.691484
4342 15:36:00.694317 [CATrainingPosCal] consider 1 rank data
4343 15:36:00.697715 u2DelayCellTimex100 = 270/100 ps
4344 15:36:00.700896 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4345 15:36:00.708026 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4346 15:36:00.710646 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4347 15:36:00.713806 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4348 15:36:00.717299 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4349 15:36:00.720792 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4350 15:36:00.720890
4351 15:36:00.723748 CA PerBit enable=1, Macro0, CA PI delay=33
4352 15:36:00.723849
4353 15:36:00.727262 [CBTSetCACLKResult] CA Dly = 33
4354 15:36:00.730872 CS Dly: 4 (0~35)
4355 15:36:00.730973 ==
4356 15:36:00.733735 Dram Type= 6, Freq= 0, CH_1, rank 1
4357 15:36:00.737053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 15:36:00.737158 ==
4359 15:36:00.744211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4360 15:36:00.750095 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4361 15:36:00.753818 [CA 0] Center 35 (5~66) winsize 62
4362 15:36:00.757188 [CA 1] Center 35 (5~66) winsize 62
4363 15:36:00.760279 [CA 2] Center 34 (4~65) winsize 62
4364 15:36:00.763607 [CA 3] Center 33 (3~64) winsize 62
4365 15:36:00.766764 [CA 4] Center 34 (3~65) winsize 63
4366 15:36:00.769806 [CA 5] Center 33 (3~64) winsize 62
4367 15:36:00.769895
4368 15:36:00.773427 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4369 15:36:00.773523
4370 15:36:00.776381 [CATrainingPosCal] consider 2 rank data
4371 15:36:00.779806 u2DelayCellTimex100 = 270/100 ps
4372 15:36:00.783304 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4373 15:36:00.786486 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4374 15:36:00.789666 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4375 15:36:00.793083 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4376 15:36:00.796660 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 15:36:00.799496 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4378 15:36:00.799600
4379 15:36:00.806609 CA PerBit enable=1, Macro0, CA PI delay=33
4380 15:36:00.806699
4381 15:36:00.806763 [CBTSetCACLKResult] CA Dly = 33
4382 15:36:00.809679 CS Dly: 5 (0~37)
4383 15:36:00.809776
4384 15:36:00.812843 ----->DramcWriteLeveling(PI) begin...
4385 15:36:00.812952 ==
4386 15:36:00.816318 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 15:36:00.819269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 15:36:00.819369 ==
4389 15:36:00.822854 Write leveling (Byte 0): 28 => 28
4390 15:36:00.825779 Write leveling (Byte 1): 31 => 31
4391 15:36:00.829326 DramcWriteLeveling(PI) end<-----
4392 15:36:00.829402
4393 15:36:00.829500 ==
4394 15:36:00.832922 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 15:36:00.839117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 15:36:00.839201 ==
4397 15:36:00.839264 [Gating] SW mode calibration
4398 15:36:00.849470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4399 15:36:00.852592 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4400 15:36:00.856021 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4401 15:36:00.862458 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 15:36:00.865736 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 15:36:00.869328 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4404 15:36:00.875595 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 15:36:00.878901 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 15:36:00.882119 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 15:36:00.888661 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 15:36:00.891968 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 15:36:00.895648 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 15:36:00.901703 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4411 15:36:00.905028 0 10 12 | B1->B0 | 3737 3939 | 1 0 | (0 0) (1 1)
4412 15:36:00.911798 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 15:36:00.915264 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 15:36:00.918443 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 15:36:00.924584 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 15:36:00.928192 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 15:36:00.931480 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 15:36:00.934943 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 15:36:00.941528 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4420 15:36:00.944770 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 15:36:00.951359 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 15:36:00.954527 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 15:36:00.957800 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 15:36:00.964536 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 15:36:00.967929 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 15:36:00.971036 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 15:36:00.977290 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 15:36:00.980839 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 15:36:00.983865 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 15:36:00.990510 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 15:36:00.993721 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 15:36:00.997133 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 15:36:01.003621 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 15:36:01.007194 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 15:36:01.010402 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4436 15:36:01.017078 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4437 15:36:01.017187 Total UI for P1: 0, mck2ui 16
4438 15:36:01.023517 best dqsien dly found for B0: ( 0, 13, 12)
4439 15:36:01.026659 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 15:36:01.030163 Total UI for P1: 0, mck2ui 16
4441 15:36:01.033354 best dqsien dly found for B1: ( 0, 13, 16)
4442 15:36:01.037028 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4443 15:36:01.039703 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4444 15:36:01.039803
4445 15:36:01.043320 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4446 15:36:01.046949 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4447 15:36:01.050046 [Gating] SW calibration Done
4448 15:36:01.050155 ==
4449 15:36:01.053143 Dram Type= 6, Freq= 0, CH_1, rank 0
4450 15:36:01.056366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 15:36:01.059793 ==
4452 15:36:01.059893 RX Vref Scan: 0
4453 15:36:01.060012
4454 15:36:01.063262 RX Vref 0 -> 0, step: 1
4455 15:36:01.063357
4456 15:36:01.066423 RX Delay -230 -> 252, step: 16
4457 15:36:01.069942 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4458 15:36:01.072752 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4459 15:36:01.076343 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4460 15:36:01.082589 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4461 15:36:01.086207 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4462 15:36:01.089686 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4463 15:36:01.092547 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4464 15:36:01.099124 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4465 15:36:01.102443 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4466 15:36:01.106127 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4467 15:36:01.109489 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4468 15:36:01.112891 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4469 15:36:01.119134 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4470 15:36:01.122500 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4471 15:36:01.125608 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4472 15:36:01.132088 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4473 15:36:01.132180 ==
4474 15:36:01.135562 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 15:36:01.138801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 15:36:01.138908 ==
4477 15:36:01.138998 DQS Delay:
4478 15:36:01.141907 DQS0 = 0, DQS1 = 0
4479 15:36:01.142013 DQM Delay:
4480 15:36:01.145469 DQM0 = 43, DQM1 = 38
4481 15:36:01.145549 DQ Delay:
4482 15:36:01.148763 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4483 15:36:01.152032 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4484 15:36:01.155017 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4485 15:36:01.158295 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4486 15:36:01.158380
4487 15:36:01.158443
4488 15:36:01.158502 ==
4489 15:36:01.161908 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 15:36:01.165178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 15:36:01.165280 ==
4492 15:36:01.165372
4493 15:36:01.168248
4494 15:36:01.168321 TX Vref Scan disable
4495 15:36:01.171455 == TX Byte 0 ==
4496 15:36:01.174728 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4497 15:36:01.178218 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4498 15:36:01.181927 == TX Byte 1 ==
4499 15:36:01.185400 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4500 15:36:01.187942 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4501 15:36:01.191356 ==
4502 15:36:01.191457 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 15:36:01.197692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 15:36:01.197799 ==
4505 15:36:01.197890
4506 15:36:01.197967
4507 15:36:01.201126 TX Vref Scan disable
4508 15:36:01.201206 == TX Byte 0 ==
4509 15:36:01.208072 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4510 15:36:01.211048 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4511 15:36:01.211148 == TX Byte 1 ==
4512 15:36:01.217877 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4513 15:36:01.221407 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4514 15:36:01.221487
4515 15:36:01.221558 [DATLAT]
4516 15:36:01.224183 Freq=600, CH1 RK0
4517 15:36:01.224259
4518 15:36:01.224325 DATLAT Default: 0x9
4519 15:36:01.227860 0, 0xFFFF, sum = 0
4520 15:36:01.227987 1, 0xFFFF, sum = 0
4521 15:36:01.231123 2, 0xFFFF, sum = 0
4522 15:36:01.234368 3, 0xFFFF, sum = 0
4523 15:36:01.234471 4, 0xFFFF, sum = 0
4524 15:36:01.237502 5, 0xFFFF, sum = 0
4525 15:36:01.237605 6, 0xFFFF, sum = 0
4526 15:36:01.240759 7, 0xFFFF, sum = 0
4527 15:36:01.240837 8, 0x0, sum = 1
4528 15:36:01.240900 9, 0x0, sum = 2
4529 15:36:01.244536 10, 0x0, sum = 3
4530 15:36:01.244681 11, 0x0, sum = 4
4531 15:36:01.247453 best_step = 9
4532 15:36:01.247560
4533 15:36:01.247654 ==
4534 15:36:01.250776 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 15:36:01.254246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 15:36:01.254366 ==
4537 15:36:01.257565 RX Vref Scan: 1
4538 15:36:01.257673
4539 15:36:01.257765 RX Vref 0 -> 0, step: 1
4540 15:36:01.257861
4541 15:36:01.260668 RX Delay -179 -> 252, step: 8
4542 15:36:01.260775
4543 15:36:01.263949 Set Vref, RX VrefLevel [Byte0]: 51
4544 15:36:01.267489 [Byte1]: 50
4545 15:36:01.271516
4546 15:36:01.271620 Final RX Vref Byte 0 = 51 to rank0
4547 15:36:01.275282 Final RX Vref Byte 1 = 50 to rank0
4548 15:36:01.278690 Final RX Vref Byte 0 = 51 to rank1
4549 15:36:01.281659 Final RX Vref Byte 1 = 50 to rank1==
4550 15:36:01.285170 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 15:36:01.291549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 15:36:01.291653 ==
4553 15:36:01.291754 DQS Delay:
4554 15:36:01.295399 DQS0 = 0, DQS1 = 0
4555 15:36:01.295501 DQM Delay:
4556 15:36:01.295594 DQM0 = 42, DQM1 = 34
4557 15:36:01.297889 DQ Delay:
4558 15:36:01.301649 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4559 15:36:01.304475 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4560 15:36:01.307863 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4561 15:36:01.311413 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4562 15:36:01.311513
4563 15:36:01.311603
4564 15:36:01.317574 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e48, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4565 15:36:01.321122 CH1 RK0: MR19=808, MR18=2E48
4566 15:36:01.327575 CH1_RK0: MR19=0x808, MR18=0x2E48, DQSOSC=396, MR23=63, INC=167, DEC=111
4567 15:36:01.327655
4568 15:36:01.330928 ----->DramcWriteLeveling(PI) begin...
4569 15:36:01.331029 ==
4570 15:36:01.334079 Dram Type= 6, Freq= 0, CH_1, rank 1
4571 15:36:01.337482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 15:36:01.337582 ==
4573 15:36:01.340959 Write leveling (Byte 0): 29 => 29
4574 15:36:01.344147 Write leveling (Byte 1): 29 => 29
4575 15:36:01.347194 DramcWriteLeveling(PI) end<-----
4576 15:36:01.347292
4577 15:36:01.347383 ==
4578 15:36:01.350507 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 15:36:01.357057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 15:36:01.357175 ==
4581 15:36:01.357275 [Gating] SW mode calibration
4582 15:36:01.367460 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4583 15:36:01.370477 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4584 15:36:01.373691 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4585 15:36:01.380214 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4586 15:36:01.383701 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4587 15:36:01.387056 0 9 12 | B1->B0 | 3131 2d2d | 1 1 | (1 0) (1 0)
4588 15:36:01.393677 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 15:36:01.396955 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 15:36:01.400243 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 15:36:01.406604 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 15:36:01.410045 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 15:36:01.412941 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 15:36:01.420194 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4595 15:36:01.422978 0 10 12 | B1->B0 | 3333 3f3f | 0 0 | (0 0) (0 0)
4596 15:36:01.426458 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 15:36:01.433084 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 15:36:01.436006 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 15:36:01.439695 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 15:36:01.446050 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 15:36:01.449269 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 15:36:01.455910 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 15:36:01.459245 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4604 15:36:01.462335 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 15:36:01.469062 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 15:36:01.472273 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 15:36:01.476661 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 15:36:01.479484 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 15:36:01.485765 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 15:36:01.489027 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 15:36:01.492290 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 15:36:01.498745 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 15:36:01.501772 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 15:36:01.508688 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 15:36:01.512272 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 15:36:01.514970 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 15:36:01.522044 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 15:36:01.524958 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4619 15:36:01.528236 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4620 15:36:01.534970 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 15:36:01.535071 Total UI for P1: 0, mck2ui 16
4622 15:36:01.538538 best dqsien dly found for B0: ( 0, 13, 10)
4623 15:36:01.542083 Total UI for P1: 0, mck2ui 16
4624 15:36:01.544908 best dqsien dly found for B1: ( 0, 13, 12)
4625 15:36:01.551713 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4626 15:36:01.554511 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4627 15:36:01.554605
4628 15:36:01.558132 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4629 15:36:01.561366 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4630 15:36:01.564768 [Gating] SW calibration Done
4631 15:36:01.564859 ==
4632 15:36:01.567874 Dram Type= 6, Freq= 0, CH_1, rank 1
4633 15:36:01.570942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 15:36:01.571038 ==
4635 15:36:01.574188 RX Vref Scan: 0
4636 15:36:01.574264
4637 15:36:01.574346 RX Vref 0 -> 0, step: 1
4638 15:36:01.574436
4639 15:36:01.577768 RX Delay -230 -> 252, step: 16
4640 15:36:01.584464 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4641 15:36:01.587524 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4642 15:36:01.590857 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4643 15:36:01.594114 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4644 15:36:01.597122 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4645 15:36:01.604092 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4646 15:36:01.607496 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4647 15:36:01.610760 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4648 15:36:01.613839 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4649 15:36:01.620546 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4650 15:36:01.623865 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4651 15:36:01.626984 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4652 15:36:01.630219 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4653 15:36:01.637250 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4654 15:36:01.640171 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4655 15:36:01.643525 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4656 15:36:01.643626 ==
4657 15:36:01.646999 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 15:36:01.650472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 15:36:01.653772 ==
4660 15:36:01.653874 DQS Delay:
4661 15:36:01.653972 DQS0 = 0, DQS1 = 0
4662 15:36:01.656685 DQM Delay:
4663 15:36:01.656787 DQM0 = 39, DQM1 = 38
4664 15:36:01.659756 DQ Delay:
4665 15:36:01.663582 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4666 15:36:01.663687 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4667 15:36:01.666612 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4668 15:36:01.673235 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4669 15:36:01.673335
4670 15:36:01.673430
4671 15:36:01.673517 ==
4672 15:36:01.676466 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 15:36:01.679717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 15:36:01.679820 ==
4675 15:36:01.679916
4676 15:36:01.679977
4677 15:36:01.682888 TX Vref Scan disable
4678 15:36:01.682986 == TX Byte 0 ==
4679 15:36:01.689801 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4680 15:36:01.693358 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4681 15:36:01.693473 == TX Byte 1 ==
4682 15:36:01.699223 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4683 15:36:01.703238 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4684 15:36:01.703340 ==
4685 15:36:01.706520 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 15:36:01.709763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 15:36:01.709863 ==
4688 15:36:01.712504
4689 15:36:01.712603
4690 15:36:01.712694 TX Vref Scan disable
4691 15:36:01.716052 == TX Byte 0 ==
4692 15:36:01.719464 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4693 15:36:01.726319 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4694 15:36:01.726432 == TX Byte 1 ==
4695 15:36:01.729663 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4696 15:36:01.735791 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4697 15:36:01.735926
4698 15:36:01.736069 [DATLAT]
4699 15:36:01.736162 Freq=600, CH1 RK1
4700 15:36:01.736250
4701 15:36:01.739576 DATLAT Default: 0x9
4702 15:36:01.742538 0, 0xFFFF, sum = 0
4703 15:36:01.742647 1, 0xFFFF, sum = 0
4704 15:36:01.746066 2, 0xFFFF, sum = 0
4705 15:36:01.746159 3, 0xFFFF, sum = 0
4706 15:36:01.748949 4, 0xFFFF, sum = 0
4707 15:36:01.749023 5, 0xFFFF, sum = 0
4708 15:36:01.752573 6, 0xFFFF, sum = 0
4709 15:36:01.752654 7, 0xFFFF, sum = 0
4710 15:36:01.755853 8, 0x0, sum = 1
4711 15:36:01.755954 9, 0x0, sum = 2
4712 15:36:01.759133 10, 0x0, sum = 3
4713 15:36:01.759223 11, 0x0, sum = 4
4714 15:36:01.759289 best_step = 9
4715 15:36:01.759348
4716 15:36:01.762320 ==
4717 15:36:01.765719 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 15:36:01.768562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 15:36:01.768634 ==
4720 15:36:01.768693 RX Vref Scan: 0
4721 15:36:01.768751
4722 15:36:01.771937 RX Vref 0 -> 0, step: 1
4723 15:36:01.772040
4724 15:36:01.775441 RX Delay -179 -> 252, step: 8
4725 15:36:01.781704 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4726 15:36:01.785498 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4727 15:36:01.788263 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4728 15:36:01.791653 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4729 15:36:01.798233 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4730 15:36:01.801674 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4731 15:36:01.805047 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4732 15:36:01.808458 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4733 15:36:01.812669 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4734 15:36:01.818861 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4735 15:36:01.821621 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4736 15:36:01.824717 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4737 15:36:01.827900 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4738 15:36:01.834794 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4739 15:36:01.837843 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4740 15:36:01.841233 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4741 15:36:01.841333 ==
4742 15:36:01.844546 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 15:36:01.851090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 15:36:01.851198 ==
4745 15:36:01.851292 DQS Delay:
4746 15:36:01.854262 DQS0 = 0, DQS1 = 0
4747 15:36:01.854361 DQM Delay:
4748 15:36:01.854454 DQM0 = 38, DQM1 = 35
4749 15:36:01.857822 DQ Delay:
4750 15:36:01.860694 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =40
4751 15:36:01.864333 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4752 15:36:01.867775 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4753 15:36:01.870791 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4754 15:36:01.870868
4755 15:36:01.870964
4756 15:36:01.877490 [DQSOSCAuto] RK1, (LSB)MR18= 0x365b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4757 15:36:01.880918 CH1 RK1: MR19=808, MR18=365B
4758 15:36:01.887389 CH1_RK1: MR19=0x808, MR18=0x365B, DQSOSC=392, MR23=63, INC=170, DEC=113
4759 15:36:01.890701 [RxdqsGatingPostProcess] freq 600
4760 15:36:01.894140 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4761 15:36:01.897066 Pre-setting of DQS Precalculation
4762 15:36:01.904085 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4763 15:36:01.910064 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4764 15:36:01.916751 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4765 15:36:01.916852
4766 15:36:01.916924
4767 15:36:01.919991 [Calibration Summary] 1200 Mbps
4768 15:36:01.923753 CH 0, Rank 0
4769 15:36:01.923857 SW Impedance : PASS
4770 15:36:01.926665 DUTY Scan : NO K
4771 15:36:01.926772 ZQ Calibration : PASS
4772 15:36:01.929742 Jitter Meter : NO K
4773 15:36:01.933402 CBT Training : PASS
4774 15:36:01.933500 Write leveling : PASS
4775 15:36:01.936405 RX DQS gating : PASS
4776 15:36:01.939886 RX DQ/DQS(RDDQC) : PASS
4777 15:36:01.940024 TX DQ/DQS : PASS
4778 15:36:01.942943 RX DATLAT : PASS
4779 15:36:01.946205 RX DQ/DQS(Engine): PASS
4780 15:36:01.946314 TX OE : NO K
4781 15:36:01.949587 All Pass.
4782 15:36:01.949692
4783 15:36:01.949790 CH 0, Rank 1
4784 15:36:01.953040 SW Impedance : PASS
4785 15:36:01.953151 DUTY Scan : NO K
4786 15:36:01.956531 ZQ Calibration : PASS
4787 15:36:01.959587 Jitter Meter : NO K
4788 15:36:01.959698 CBT Training : PASS
4789 15:36:01.963531 Write leveling : PASS
4790 15:36:01.966434 RX DQS gating : PASS
4791 15:36:01.966535 RX DQ/DQS(RDDQC) : PASS
4792 15:36:01.969617 TX DQ/DQS : PASS
4793 15:36:01.973203 RX DATLAT : PASS
4794 15:36:01.973290 RX DQ/DQS(Engine): PASS
4795 15:36:01.976038 TX OE : NO K
4796 15:36:01.976136 All Pass.
4797 15:36:01.976233
4798 15:36:01.979608 CH 1, Rank 0
4799 15:36:01.979709 SW Impedance : PASS
4800 15:36:01.983035 DUTY Scan : NO K
4801 15:36:01.985764 ZQ Calibration : PASS
4802 15:36:01.985862 Jitter Meter : NO K
4803 15:36:01.989394 CBT Training : PASS
4804 15:36:01.993063 Write leveling : PASS
4805 15:36:01.993137 RX DQS gating : PASS
4806 15:36:01.995816 RX DQ/DQS(RDDQC) : PASS
4807 15:36:01.999346 TX DQ/DQS : PASS
4808 15:36:01.999419 RX DATLAT : PASS
4809 15:36:02.002472 RX DQ/DQS(Engine): PASS
4810 15:36:02.005641 TX OE : NO K
4811 15:36:02.005711 All Pass.
4812 15:36:02.005774
4813 15:36:02.005831 CH 1, Rank 1
4814 15:36:02.009278 SW Impedance : PASS
4815 15:36:02.012161 DUTY Scan : NO K
4816 15:36:02.012231 ZQ Calibration : PASS
4817 15:36:02.015486 Jitter Meter : NO K
4818 15:36:02.018877 CBT Training : PASS
4819 15:36:02.018950 Write leveling : PASS
4820 15:36:02.022141 RX DQS gating : PASS
4821 15:36:02.025656 RX DQ/DQS(RDDQC) : PASS
4822 15:36:02.025735 TX DQ/DQS : PASS
4823 15:36:02.028322 RX DATLAT : PASS
4824 15:36:02.032036 RX DQ/DQS(Engine): PASS
4825 15:36:02.032124 TX OE : NO K
4826 15:36:02.032218 All Pass.
4827 15:36:02.035216
4828 15:36:02.035323 DramC Write-DBI off
4829 15:36:02.038274 PER_BANK_REFRESH: Hybrid Mode
4830 15:36:02.038371 TX_TRACKING: ON
4831 15:36:02.048469 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4832 15:36:02.051285 [FAST_K] Save calibration result to emmc
4833 15:36:02.055051 dramc_set_vcore_voltage set vcore to 662500
4834 15:36:02.058001 Read voltage for 933, 3
4835 15:36:02.058110 Vio18 = 0
4836 15:36:02.061161 Vcore = 662500
4837 15:36:02.061263 Vdram = 0
4838 15:36:02.061354 Vddq = 0
4839 15:36:02.061442 Vmddr = 0
4840 15:36:02.068143 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4841 15:36:02.074600 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4842 15:36:02.074701 MEM_TYPE=3, freq_sel=17
4843 15:36:02.078025 sv_algorithm_assistance_LP4_1600
4844 15:36:02.080897 ============ PULL DRAM RESETB DOWN ============
4845 15:36:02.087348 ========== PULL DRAM RESETB DOWN end =========
4846 15:36:02.090815 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4847 15:36:02.094159 ===================================
4848 15:36:02.097656 LPDDR4 DRAM CONFIGURATION
4849 15:36:02.100634 ===================================
4850 15:36:02.100739 EX_ROW_EN[0] = 0x0
4851 15:36:02.104065 EX_ROW_EN[1] = 0x0
4852 15:36:02.106971 LP4Y_EN = 0x0
4853 15:36:02.107073 WORK_FSP = 0x0
4854 15:36:02.110837 WL = 0x3
4855 15:36:02.110945 RL = 0x3
4856 15:36:02.113730 BL = 0x2
4857 15:36:02.113830 RPST = 0x0
4858 15:36:02.117295 RD_PRE = 0x0
4859 15:36:02.117399 WR_PRE = 0x1
4860 15:36:02.120387 WR_PST = 0x0
4861 15:36:02.120485 DBI_WR = 0x0
4862 15:36:02.124050 DBI_RD = 0x0
4863 15:36:02.124128 OTF = 0x1
4864 15:36:02.126938 ===================================
4865 15:36:02.130487 ===================================
4866 15:36:02.133930 ANA top config
4867 15:36:02.136936 ===================================
4868 15:36:02.140068 DLL_ASYNC_EN = 0
4869 15:36:02.140173 ALL_SLAVE_EN = 1
4870 15:36:02.143576 NEW_RANK_MODE = 1
4871 15:36:02.146471 DLL_IDLE_MODE = 1
4872 15:36:02.150125 LP45_APHY_COMB_EN = 1
4873 15:36:02.153041 TX_ODT_DIS = 1
4874 15:36:02.153141 NEW_8X_MODE = 1
4875 15:36:02.156428 ===================================
4876 15:36:02.159712 ===================================
4877 15:36:02.163320 data_rate = 1866
4878 15:36:02.166206 CKR = 1
4879 15:36:02.169489 DQ_P2S_RATIO = 8
4880 15:36:02.173129 ===================================
4881 15:36:02.176168 CA_P2S_RATIO = 8
4882 15:36:02.179577 DQ_CA_OPEN = 0
4883 15:36:02.179676 DQ_SEMI_OPEN = 0
4884 15:36:02.182841 CA_SEMI_OPEN = 0
4885 15:36:02.186335 CA_FULL_RATE = 0
4886 15:36:02.189371 DQ_CKDIV4_EN = 1
4887 15:36:02.192882 CA_CKDIV4_EN = 1
4888 15:36:02.195812 CA_PREDIV_EN = 0
4889 15:36:02.195940 PH8_DLY = 0
4890 15:36:02.199325 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4891 15:36:02.202558 DQ_AAMCK_DIV = 4
4892 15:36:02.205754 CA_AAMCK_DIV = 4
4893 15:36:02.209062 CA_ADMCK_DIV = 4
4894 15:36:02.212765 DQ_TRACK_CA_EN = 0
4895 15:36:02.212865 CA_PICK = 933
4896 15:36:02.215780 CA_MCKIO = 933
4897 15:36:02.219502 MCKIO_SEMI = 0
4898 15:36:02.222698 PLL_FREQ = 3732
4899 15:36:02.225997 DQ_UI_PI_RATIO = 32
4900 15:36:02.229188 CA_UI_PI_RATIO = 0
4901 15:36:02.232654 ===================================
4902 15:36:02.235536 ===================================
4903 15:36:02.239725 memory_type:LPDDR4
4904 15:36:02.239831 GP_NUM : 10
4905 15:36:02.242736 SRAM_EN : 1
4906 15:36:02.242844 MD32_EN : 0
4907 15:36:02.245671 ===================================
4908 15:36:02.249364 [ANA_INIT] >>>>>>>>>>>>>>
4909 15:36:02.252113 <<<<<< [CONFIGURE PHASE]: ANA_TX
4910 15:36:02.255726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4911 15:36:02.258752 ===================================
4912 15:36:02.261677 data_rate = 1866,PCW = 0X8f00
4913 15:36:02.265285 ===================================
4914 15:36:02.268861 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4915 15:36:02.275377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4916 15:36:02.278259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4917 15:36:02.284666 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4918 15:36:02.288275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4919 15:36:02.291366 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4920 15:36:02.291465 [ANA_INIT] flow start
4921 15:36:02.294691 [ANA_INIT] PLL >>>>>>>>
4922 15:36:02.297868 [ANA_INIT] PLL <<<<<<<<
4923 15:36:02.297964 [ANA_INIT] MIDPI >>>>>>>>
4924 15:36:02.301575 [ANA_INIT] MIDPI <<<<<<<<
4925 15:36:02.304677 [ANA_INIT] DLL >>>>>>>>
4926 15:36:02.304782 [ANA_INIT] flow end
4927 15:36:02.311410 ============ LP4 DIFF to SE enter ============
4928 15:36:02.314570 ============ LP4 DIFF to SE exit ============
4929 15:36:02.317601 [ANA_INIT] <<<<<<<<<<<<<
4930 15:36:02.321382 [Flow] Enable top DCM control >>>>>
4931 15:36:02.324640 [Flow] Enable top DCM control <<<<<
4932 15:36:02.327724 Enable DLL master slave shuffle
4933 15:36:02.330829 ==============================================================
4934 15:36:02.334348 Gating Mode config
4935 15:36:02.337881 ==============================================================
4936 15:36:02.341276 Config description:
4937 15:36:02.350698 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4938 15:36:02.357497 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4939 15:36:02.361048 SELPH_MODE 0: By rank 1: By Phase
4940 15:36:02.367397 ==============================================================
4941 15:36:02.370857 GAT_TRACK_EN = 1
4942 15:36:02.373714 RX_GATING_MODE = 2
4943 15:36:02.377568 RX_GATING_TRACK_MODE = 2
4944 15:36:02.380898 SELPH_MODE = 1
4945 15:36:02.383871 PICG_EARLY_EN = 1
4946 15:36:02.387470 VALID_LAT_VALUE = 1
4947 15:36:02.390309 ==============================================================
4948 15:36:02.393618 Enter into Gating configuration >>>>
4949 15:36:02.396929 Exit from Gating configuration <<<<
4950 15:36:02.400587 Enter into DVFS_PRE_config >>>>>
4951 15:36:02.413779 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4952 15:36:02.416609 Exit from DVFS_PRE_config <<<<<
4953 15:36:02.416721 Enter into PICG configuration >>>>
4954 15:36:02.420097 Exit from PICG configuration <<<<
4955 15:36:02.423076 [RX_INPUT] configuration >>>>>
4956 15:36:02.426614 [RX_INPUT] configuration <<<<<
4957 15:36:02.433093 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4958 15:36:02.436609 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4959 15:36:02.443221 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4960 15:36:02.449690 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4961 15:36:02.456159 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4962 15:36:02.462554 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4963 15:36:02.466061 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4964 15:36:02.469713 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4965 15:36:02.476086 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4966 15:36:02.479172 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4967 15:36:02.482713 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4968 15:36:02.485596 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4969 15:36:02.489574 ===================================
4970 15:36:02.492235 LPDDR4 DRAM CONFIGURATION
4971 15:36:02.495531 ===================================
4972 15:36:02.499524 EX_ROW_EN[0] = 0x0
4973 15:36:02.499600 EX_ROW_EN[1] = 0x0
4974 15:36:02.502091 LP4Y_EN = 0x0
4975 15:36:02.502197 WORK_FSP = 0x0
4976 15:36:02.505713 WL = 0x3
4977 15:36:02.505814 RL = 0x3
4978 15:36:02.509006 BL = 0x2
4979 15:36:02.511886 RPST = 0x0
4980 15:36:02.511986 RD_PRE = 0x0
4981 15:36:02.515389 WR_PRE = 0x1
4982 15:36:02.515486 WR_PST = 0x0
4983 15:36:02.518826 DBI_WR = 0x0
4984 15:36:02.518906 DBI_RD = 0x0
4985 15:36:02.521818 OTF = 0x1
4986 15:36:02.525118 ===================================
4987 15:36:02.528691 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4988 15:36:02.532263 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4989 15:36:02.538091 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4990 15:36:02.541791 ===================================
4991 15:36:02.541901 LPDDR4 DRAM CONFIGURATION
4992 15:36:02.545087 ===================================
4993 15:36:02.548492 EX_ROW_EN[0] = 0x10
4994 15:36:02.548604 EX_ROW_EN[1] = 0x0
4995 15:36:02.551373 LP4Y_EN = 0x0
4996 15:36:02.551453 WORK_FSP = 0x0
4997 15:36:02.555076 WL = 0x3
4998 15:36:02.558454 RL = 0x3
4999 15:36:02.558555 BL = 0x2
5000 15:36:02.561664 RPST = 0x0
5001 15:36:02.561762 RD_PRE = 0x0
5002 15:36:02.564543 WR_PRE = 0x1
5003 15:36:02.564651 WR_PST = 0x0
5004 15:36:02.568330 DBI_WR = 0x0
5005 15:36:02.568402 DBI_RD = 0x0
5006 15:36:02.571342 OTF = 0x1
5007 15:36:02.574751 ===================================
5008 15:36:02.581288 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5009 15:36:02.584616 nWR fixed to 30
5010 15:36:02.584739 [ModeRegInit_LP4] CH0 RK0
5011 15:36:02.587837 [ModeRegInit_LP4] CH0 RK1
5012 15:36:02.591037 [ModeRegInit_LP4] CH1 RK0
5013 15:36:02.591144 [ModeRegInit_LP4] CH1 RK1
5014 15:36:02.594586 match AC timing 9
5015 15:36:02.597709 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5016 15:36:02.600953 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5017 15:36:02.607536 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5018 15:36:02.610991 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5019 15:36:02.617411 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5020 15:36:02.617490 ==
5021 15:36:02.621096 Dram Type= 6, Freq= 0, CH_0, rank 0
5022 15:36:02.624442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5023 15:36:02.624518 ==
5024 15:36:02.630775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5025 15:36:02.637156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5026 15:36:02.640514 [CA 0] Center 37 (7~68) winsize 62
5027 15:36:02.643640 [CA 1] Center 37 (7~68) winsize 62
5028 15:36:02.646958 [CA 2] Center 34 (4~64) winsize 61
5029 15:36:02.650501 [CA 3] Center 34 (4~65) winsize 62
5030 15:36:02.653448 [CA 4] Center 32 (2~63) winsize 62
5031 15:36:02.656735 [CA 5] Center 32 (2~63) winsize 62
5032 15:36:02.656818
5033 15:36:02.660254 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5034 15:36:02.660336
5035 15:36:02.663774 [CATrainingPosCal] consider 1 rank data
5036 15:36:02.667018 u2DelayCellTimex100 = 270/100 ps
5037 15:36:02.670333 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5038 15:36:02.673874 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5039 15:36:02.676552 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5040 15:36:02.679894 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5041 15:36:02.683674 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5042 15:36:02.686732 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5043 15:36:02.689671
5044 15:36:02.693393 CA PerBit enable=1, Macro0, CA PI delay=32
5045 15:36:02.693484
5046 15:36:02.696890 [CBTSetCACLKResult] CA Dly = 32
5047 15:36:02.696970 CS Dly: 6 (0~37)
5048 15:36:02.697047 ==
5049 15:36:02.699840 Dram Type= 6, Freq= 0, CH_0, rank 1
5050 15:36:02.702891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5051 15:36:02.702975 ==
5052 15:36:02.710070 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5053 15:36:02.716135 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5054 15:36:02.719491 [CA 0] Center 37 (7~68) winsize 62
5055 15:36:02.723190 [CA 1] Center 37 (7~68) winsize 62
5056 15:36:02.726323 [CA 2] Center 35 (5~65) winsize 61
5057 15:36:02.729470 [CA 3] Center 34 (4~65) winsize 62
5058 15:36:02.733262 [CA 4] Center 33 (3~64) winsize 62
5059 15:36:02.736544 [CA 5] Center 32 (2~63) winsize 62
5060 15:36:02.736619
5061 15:36:02.739308 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5062 15:36:02.739377
5063 15:36:02.742673 [CATrainingPosCal] consider 2 rank data
5064 15:36:02.745952 u2DelayCellTimex100 = 270/100 ps
5065 15:36:02.749400 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5066 15:36:02.752285 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5067 15:36:02.758885 CA2 delay=34 (5~64),Diff = 2 PI (12 cell)
5068 15:36:02.762183 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5069 15:36:02.765934 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5070 15:36:02.769134 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5071 15:36:02.769215
5072 15:36:02.772554 CA PerBit enable=1, Macro0, CA PI delay=32
5073 15:36:02.772635
5074 15:36:02.775486 [CBTSetCACLKResult] CA Dly = 32
5075 15:36:02.775567 CS Dly: 7 (0~39)
5076 15:36:02.775632
5077 15:36:02.779205 ----->DramcWriteLeveling(PI) begin...
5078 15:36:02.782229 ==
5079 15:36:02.785594 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 15:36:02.788486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 15:36:02.788595 ==
5082 15:36:02.792237 Write leveling (Byte 0): 31 => 31
5083 15:36:02.795347 Write leveling (Byte 1): 27 => 27
5084 15:36:02.798622 DramcWriteLeveling(PI) end<-----
5085 15:36:02.798704
5086 15:36:02.798767 ==
5087 15:36:02.801887 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 15:36:02.805196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 15:36:02.805286 ==
5090 15:36:02.808369 [Gating] SW mode calibration
5091 15:36:02.815375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5092 15:36:02.821731 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5093 15:36:02.824792 0 14 0 | B1->B0 | 2626 3333 | 0 1 | (0 0) (1 1)
5094 15:36:02.827985 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 15:36:02.834612 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 15:36:02.837904 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 15:36:02.841477 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 15:36:02.847992 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 15:36:02.851200 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5100 15:36:02.854404 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
5101 15:36:02.861167 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5102 15:36:02.864265 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 15:36:02.867627 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 15:36:02.874283 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 15:36:02.877752 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 15:36:02.880931 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 15:36:02.887288 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5108 15:36:02.890512 0 15 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
5109 15:36:02.894108 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
5110 15:36:02.900935 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 15:36:02.903632 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 15:36:02.906977 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 15:36:02.913594 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 15:36:02.917103 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 15:36:02.920502 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 15:36:02.926727 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5117 15:36:02.930212 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5118 15:36:02.933571 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5119 15:36:02.939845 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 15:36:02.943379 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 15:36:02.946919 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 15:36:02.953479 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 15:36:02.956387 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 15:36:02.959758 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 15:36:02.966100 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 15:36:02.969722 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 15:36:02.973075 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 15:36:02.980221 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 15:36:02.983143 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 15:36:02.986592 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 15:36:02.992755 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 15:36:02.995731 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5133 15:36:02.999070 Total UI for P1: 0, mck2ui 16
5134 15:36:03.002657 best dqsien dly found for B0: ( 1, 2, 26)
5135 15:36:03.006199 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5136 15:36:03.012603 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 15:36:03.012684 Total UI for P1: 0, mck2ui 16
5138 15:36:03.019199 best dqsien dly found for B1: ( 1, 3, 2)
5139 15:36:03.022785 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5140 15:36:03.026020 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5141 15:36:03.026103
5142 15:36:03.028829 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5143 15:36:03.032427 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5144 15:36:03.035830 [Gating] SW calibration Done
5145 15:36:03.035920 ==
5146 15:36:03.038950 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 15:36:03.042419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 15:36:03.042493 ==
5149 15:36:03.045754 RX Vref Scan: 0
5150 15:36:03.045829
5151 15:36:03.045895 RX Vref 0 -> 0, step: 1
5152 15:36:03.045957
5153 15:36:03.048862 RX Delay -80 -> 252, step: 8
5154 15:36:03.051983 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5155 15:36:03.058640 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5156 15:36:03.062016 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5157 15:36:03.065488 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5158 15:36:03.068456 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5159 15:36:03.072019 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5160 15:36:03.075250 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5161 15:36:03.082033 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5162 15:36:03.085302 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5163 15:36:03.088604 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5164 15:36:03.092157 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5165 15:36:03.094856 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5166 15:36:03.101459 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5167 15:36:03.105127 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5168 15:36:03.108338 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5169 15:36:03.111643 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5170 15:36:03.111752 ==
5171 15:36:03.114705 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 15:36:03.118468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 15:36:03.121651 ==
5174 15:36:03.121733 DQS Delay:
5175 15:36:03.121804 DQS0 = 0, DQS1 = 0
5176 15:36:03.124953 DQM Delay:
5177 15:36:03.125036 DQM0 = 99, DQM1 = 88
5178 15:36:03.127719 DQ Delay:
5179 15:36:03.131055 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5180 15:36:03.134509 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =111
5181 15:36:03.137975 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5182 15:36:03.141212 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5183 15:36:03.141294
5184 15:36:03.141359
5185 15:36:03.141418 ==
5186 15:36:03.144665 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 15:36:03.147606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 15:36:03.147688 ==
5189 15:36:03.147753
5190 15:36:03.147813
5191 15:36:03.151026 TX Vref Scan disable
5192 15:36:03.151107 == TX Byte 0 ==
5193 15:36:03.157584 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5194 15:36:03.160669 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5195 15:36:03.164098 == TX Byte 1 ==
5196 15:36:03.167613 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5197 15:36:03.170983 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5198 15:36:03.171065 ==
5199 15:36:03.174050 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 15:36:03.177372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 15:36:03.177455 ==
5202 15:36:03.180332
5203 15:36:03.180414
5204 15:36:03.180483 TX Vref Scan disable
5205 15:36:03.183840 == TX Byte 0 ==
5206 15:36:03.187284 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5207 15:36:03.194092 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5208 15:36:03.194174 == TX Byte 1 ==
5209 15:36:03.197029 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5210 15:36:03.203534 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5211 15:36:03.203616
5212 15:36:03.203681 [DATLAT]
5213 15:36:03.203751 Freq=933, CH0 RK0
5214 15:36:03.203817
5215 15:36:03.207223 DATLAT Default: 0xd
5216 15:36:03.210464 0, 0xFFFF, sum = 0
5217 15:36:03.210547 1, 0xFFFF, sum = 0
5218 15:36:03.213654 2, 0xFFFF, sum = 0
5219 15:36:03.213739 3, 0xFFFF, sum = 0
5220 15:36:03.217027 4, 0xFFFF, sum = 0
5221 15:36:03.217110 5, 0xFFFF, sum = 0
5222 15:36:03.220254 6, 0xFFFF, sum = 0
5223 15:36:03.220338 7, 0xFFFF, sum = 0
5224 15:36:03.223536 8, 0xFFFF, sum = 0
5225 15:36:03.223620 9, 0xFFFF, sum = 0
5226 15:36:03.227137 10, 0x0, sum = 1
5227 15:36:03.227247 11, 0x0, sum = 2
5228 15:36:03.230313 12, 0x0, sum = 3
5229 15:36:03.230397 13, 0x0, sum = 4
5230 15:36:03.233590 best_step = 11
5231 15:36:03.233718
5232 15:36:03.233814 ==
5233 15:36:03.236685 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 15:36:03.240140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 15:36:03.240239 ==
5236 15:36:03.240309 RX Vref Scan: 1
5237 15:36:03.243271
5238 15:36:03.243382 RX Vref 0 -> 0, step: 1
5239 15:36:03.243479
5240 15:36:03.246680 RX Delay -61 -> 252, step: 4
5241 15:36:03.246794
5242 15:36:03.249893 Set Vref, RX VrefLevel [Byte0]: 52
5243 15:36:03.253706 [Byte1]: 59
5244 15:36:03.256613
5245 15:36:03.256737 Final RX Vref Byte 0 = 52 to rank0
5246 15:36:03.260265 Final RX Vref Byte 1 = 59 to rank0
5247 15:36:03.262867 Final RX Vref Byte 0 = 52 to rank1
5248 15:36:03.266598 Final RX Vref Byte 1 = 59 to rank1==
5249 15:36:03.269529 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 15:36:03.276338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 15:36:03.276416 ==
5252 15:36:03.276487 DQS Delay:
5253 15:36:03.279767 DQS0 = 0, DQS1 = 0
5254 15:36:03.279872 DQM Delay:
5255 15:36:03.279975 DQM0 = 99, DQM1 = 88
5256 15:36:03.282686 DQ Delay:
5257 15:36:03.286193 DQ0 =100, DQ1 =102, DQ2 =94, DQ3 =96
5258 15:36:03.289527 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5259 15:36:03.292645 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =84
5260 15:36:03.296102 DQ12 =96, DQ13 =90, DQ14 =98, DQ15 =94
5261 15:36:03.296191
5262 15:36:03.296279
5263 15:36:03.302858 [DQSOSCAuto] RK0, (LSB)MR18= 0x1712, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5264 15:36:03.305757 CH0 RK0: MR19=505, MR18=1712
5265 15:36:03.312412 CH0_RK0: MR19=0x505, MR18=0x1712, DQSOSC=414, MR23=63, INC=63, DEC=42
5266 15:36:03.312516
5267 15:36:03.315869 ----->DramcWriteLeveling(PI) begin...
5268 15:36:03.315974 ==
5269 15:36:03.318849 Dram Type= 6, Freq= 0, CH_0, rank 1
5270 15:36:03.322176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 15:36:03.325730 ==
5272 15:36:03.325808 Write leveling (Byte 0): 31 => 31
5273 15:36:03.328725 Write leveling (Byte 1): 30 => 30
5274 15:36:03.331951 DramcWriteLeveling(PI) end<-----
5275 15:36:03.332037
5276 15:36:03.332100 ==
5277 15:36:03.335858 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 15:36:03.341726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 15:36:03.341802 ==
5280 15:36:03.345346 [Gating] SW mode calibration
5281 15:36:03.352603 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5282 15:36:03.355039 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5283 15:36:03.361881 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5284 15:36:03.365474 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 15:36:03.368684 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 15:36:03.375092 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 15:36:03.378597 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 15:36:03.382045 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 15:36:03.388289 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 15:36:03.391713 0 14 28 | B1->B0 | 3434 2929 | 0 0 | (0 1) (0 0)
5291 15:36:03.395320 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5292 15:36:03.401690 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 15:36:03.404484 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 15:36:03.407742 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 15:36:03.414429 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 15:36:03.417981 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 15:36:03.420870 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5298 15:36:03.427299 0 15 28 | B1->B0 | 2d2d 3e3e | 0 0 | (0 0) (0 0)
5299 15:36:03.431364 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5300 15:36:03.434694 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 15:36:03.440732 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 15:36:03.443856 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 15:36:03.447226 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 15:36:03.453774 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 15:36:03.457370 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5306 15:36:03.460395 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5307 15:36:03.467274 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5308 15:36:03.470373 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 15:36:03.473813 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 15:36:03.480293 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 15:36:03.483999 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 15:36:03.486817 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 15:36:03.493392 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 15:36:03.497256 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 15:36:03.500072 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 15:36:03.506540 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 15:36:03.509875 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 15:36:03.513320 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 15:36:03.519918 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 15:36:03.522911 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 15:36:03.526584 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 15:36:03.532803 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5323 15:36:03.536048 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 15:36:03.539546 Total UI for P1: 0, mck2ui 16
5325 15:36:03.542947 best dqsien dly found for B0: ( 1, 2, 28)
5326 15:36:03.546202 Total UI for P1: 0, mck2ui 16
5327 15:36:03.549664 best dqsien dly found for B1: ( 1, 2, 28)
5328 15:36:03.552691 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5329 15:36:03.556090 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5330 15:36:03.556174
5331 15:36:03.559397 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5332 15:36:03.562663 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5333 15:36:03.565792 [Gating] SW calibration Done
5334 15:36:03.565875 ==
5335 15:36:03.569522 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 15:36:03.576062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 15:36:03.576166 ==
5338 15:36:03.576231 RX Vref Scan: 0
5339 15:36:03.576301
5340 15:36:03.579424 RX Vref 0 -> 0, step: 1
5341 15:36:03.579508
5342 15:36:03.582174 RX Delay -80 -> 252, step: 8
5343 15:36:03.585638 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5344 15:36:03.589322 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5345 15:36:03.592139 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5346 15:36:03.595567 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5347 15:36:03.598958 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5348 15:36:03.605529 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5349 15:36:03.608804 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5350 15:36:03.612038 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5351 15:36:03.615214 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5352 15:36:03.618625 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5353 15:36:03.625409 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5354 15:36:03.628411 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5355 15:36:03.631641 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5356 15:36:03.635094 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5357 15:36:03.638595 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5358 15:36:03.641788 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5359 15:36:03.644687 ==
5360 15:36:03.648013 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 15:36:03.651652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 15:36:03.651733 ==
5363 15:36:03.651801 DQS Delay:
5364 15:36:03.654425 DQS0 = 0, DQS1 = 0
5365 15:36:03.654497 DQM Delay:
5366 15:36:03.658269 DQM0 = 97, DQM1 = 89
5367 15:36:03.658351 DQ Delay:
5368 15:36:03.661391 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5369 15:36:03.664576 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5370 15:36:03.668149 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5371 15:36:03.670931 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5372 15:36:03.671001
5373 15:36:03.671062
5374 15:36:03.671119 ==
5375 15:36:03.674772 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 15:36:03.677640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 15:36:03.681027 ==
5378 15:36:03.681104
5379 15:36:03.681227
5380 15:36:03.681339 TX Vref Scan disable
5381 15:36:03.684363 == TX Byte 0 ==
5382 15:36:03.687585 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5383 15:36:03.690807 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5384 15:36:03.694278 == TX Byte 1 ==
5385 15:36:03.697553 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5386 15:36:03.700903 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5387 15:36:03.704038 ==
5388 15:36:03.707328 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 15:36:03.710675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 15:36:03.710783 ==
5391 15:36:03.710876
5392 15:36:03.710965
5393 15:36:03.713920 TX Vref Scan disable
5394 15:36:03.714006 == TX Byte 0 ==
5395 15:36:03.720562 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5396 15:36:03.723572 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5397 15:36:03.723665 == TX Byte 1 ==
5398 15:36:03.730358 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5399 15:36:03.733534 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5400 15:36:03.733624
5401 15:36:03.733697 [DATLAT]
5402 15:36:03.737243 Freq=933, CH0 RK1
5403 15:36:03.737323
5404 15:36:03.737394 DATLAT Default: 0xb
5405 15:36:03.740287 0, 0xFFFF, sum = 0
5406 15:36:03.740375 1, 0xFFFF, sum = 0
5407 15:36:03.743581 2, 0xFFFF, sum = 0
5408 15:36:03.743697 3, 0xFFFF, sum = 0
5409 15:36:03.746904 4, 0xFFFF, sum = 0
5410 15:36:03.750228 5, 0xFFFF, sum = 0
5411 15:36:03.750332 6, 0xFFFF, sum = 0
5412 15:36:03.753469 7, 0xFFFF, sum = 0
5413 15:36:03.753544 8, 0xFFFF, sum = 0
5414 15:36:03.756657 9, 0xFFFF, sum = 0
5415 15:36:03.756764 10, 0x0, sum = 1
5416 15:36:03.760401 11, 0x0, sum = 2
5417 15:36:03.760477 12, 0x0, sum = 3
5418 15:36:03.762987 13, 0x0, sum = 4
5419 15:36:03.763062 best_step = 11
5420 15:36:03.763123
5421 15:36:03.763181 ==
5422 15:36:03.766686 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 15:36:03.769740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 15:36:03.769820 ==
5425 15:36:03.773016 RX Vref Scan: 0
5426 15:36:03.773090
5427 15:36:03.776422 RX Vref 0 -> 0, step: 1
5428 15:36:03.776498
5429 15:36:03.776565 RX Delay -53 -> 252, step: 4
5430 15:36:03.784001 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5431 15:36:03.787420 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5432 15:36:03.790847 iDelay=195, Bit 2, Center 94 (3 ~ 186) 184
5433 15:36:03.794271 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5434 15:36:03.797798 iDelay=195, Bit 4, Center 100 (7 ~ 194) 188
5435 15:36:03.800411 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5436 15:36:03.807670 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5437 15:36:03.810375 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5438 15:36:03.813864 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5439 15:36:03.817162 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5440 15:36:03.820137 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5441 15:36:03.827048 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5442 15:36:03.830536 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5443 15:36:03.833802 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5444 15:36:03.837004 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5445 15:36:03.839889 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5446 15:36:03.840008 ==
5447 15:36:03.843441 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 15:36:03.850018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 15:36:03.850096 ==
5450 15:36:03.850161 DQS Delay:
5451 15:36:03.853125 DQS0 = 0, DQS1 = 0
5452 15:36:03.853199 DQM Delay:
5453 15:36:03.853282 DQM0 = 97, DQM1 = 88
5454 15:36:03.856322 DQ Delay:
5455 15:36:03.859912 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =94
5456 15:36:03.863347 DQ4 =100, DQ5 =86, DQ6 =108, DQ7 =104
5457 15:36:03.866453 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5458 15:36:03.869729 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =94
5459 15:36:03.869810
5460 15:36:03.869874
5461 15:36:03.876243 [DQSOSCAuto] RK1, (LSB)MR18= 0x1210, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5462 15:36:03.879438 CH0 RK1: MR19=505, MR18=1210
5463 15:36:03.885879 CH0_RK1: MR19=0x505, MR18=0x1210, DQSOSC=416, MR23=63, INC=62, DEC=41
5464 15:36:03.889464 [RxdqsGatingPostProcess] freq 933
5465 15:36:03.896225 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5466 15:36:03.899215 best DQS0 dly(2T, 0.5T) = (0, 10)
5467 15:36:03.899292 best DQS1 dly(2T, 0.5T) = (0, 11)
5468 15:36:03.902911 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5469 15:36:03.905604 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5470 15:36:03.909132 best DQS0 dly(2T, 0.5T) = (0, 10)
5471 15:36:03.912477 best DQS1 dly(2T, 0.5T) = (0, 10)
5472 15:36:03.915507 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5473 15:36:03.918737 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5474 15:36:03.922247 Pre-setting of DQS Precalculation
5475 15:36:03.929064 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5476 15:36:03.929147 ==
5477 15:36:03.932281 Dram Type= 6, Freq= 0, CH_1, rank 0
5478 15:36:03.935460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 15:36:03.935544 ==
5480 15:36:03.942536 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5481 15:36:03.948356 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5482 15:36:03.951548 [CA 0] Center 36 (6~67) winsize 62
5483 15:36:03.955376 [CA 1] Center 36 (6~67) winsize 62
5484 15:36:03.958596 [CA 2] Center 34 (4~65) winsize 62
5485 15:36:03.961575 [CA 3] Center 34 (3~65) winsize 63
5486 15:36:03.964876 [CA 4] Center 34 (3~65) winsize 63
5487 15:36:03.968111 [CA 5] Center 33 (3~64) winsize 62
5488 15:36:03.968192
5489 15:36:03.971666 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5490 15:36:03.971748
5491 15:36:03.975119 [CATrainingPosCal] consider 1 rank data
5492 15:36:03.978274 u2DelayCellTimex100 = 270/100 ps
5493 15:36:03.981266 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5494 15:36:03.984509 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5495 15:36:03.987853 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5496 15:36:03.991137 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5497 15:36:03.995187 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5498 15:36:03.997531 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5499 15:36:03.997636
5500 15:36:04.004814 CA PerBit enable=1, Macro0, CA PI delay=33
5501 15:36:04.004891
5502 15:36:04.007703 [CBTSetCACLKResult] CA Dly = 33
5503 15:36:04.007786 CS Dly: 5 (0~36)
5504 15:36:04.007852 ==
5505 15:36:04.011188 Dram Type= 6, Freq= 0, CH_1, rank 1
5506 15:36:04.014381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 15:36:04.014465 ==
5508 15:36:04.020791 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5509 15:36:04.027681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5510 15:36:04.031306 [CA 0] Center 36 (6~67) winsize 62
5511 15:36:04.033935 [CA 1] Center 36 (6~67) winsize 62
5512 15:36:04.037503 [CA 2] Center 34 (4~65) winsize 62
5513 15:36:04.040576 [CA 3] Center 33 (3~64) winsize 62
5514 15:36:04.043677 [CA 4] Center 33 (3~64) winsize 62
5515 15:36:04.047284 [CA 5] Center 33 (3~64) winsize 62
5516 15:36:04.047357
5517 15:36:04.050720 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5518 15:36:04.050801
5519 15:36:04.053973 [CATrainingPosCal] consider 2 rank data
5520 15:36:04.057263 u2DelayCellTimex100 = 270/100 ps
5521 15:36:04.060246 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5522 15:36:04.063541 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5523 15:36:04.066957 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5524 15:36:04.070460 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5525 15:36:04.076850 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5526 15:36:04.080246 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5527 15:36:04.080357
5528 15:36:04.083260 CA PerBit enable=1, Macro0, CA PI delay=33
5529 15:36:04.083337
5530 15:36:04.086877 [CBTSetCACLKResult] CA Dly = 33
5531 15:36:04.086961 CS Dly: 6 (0~38)
5532 15:36:04.087027
5533 15:36:04.090054 ----->DramcWriteLeveling(PI) begin...
5534 15:36:04.090133 ==
5535 15:36:04.093649 Dram Type= 6, Freq= 0, CH_1, rank 0
5536 15:36:04.100516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 15:36:04.100597 ==
5538 15:36:04.103422 Write leveling (Byte 0): 26 => 26
5539 15:36:04.107070 Write leveling (Byte 1): 27 => 27
5540 15:36:04.110548 DramcWriteLeveling(PI) end<-----
5541 15:36:04.110628
5542 15:36:04.110693 ==
5543 15:36:04.113849 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 15:36:04.116490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 15:36:04.116591 ==
5546 15:36:04.119815 [Gating] SW mode calibration
5547 15:36:04.126403 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5548 15:36:04.129477 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5549 15:36:04.136187 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 15:36:04.139673 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 15:36:04.143192 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 15:36:04.149191 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 15:36:04.152533 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 15:36:04.159408 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 15:36:04.162355 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5556 15:36:04.165939 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
5557 15:36:04.172186 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5558 15:36:04.175785 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 15:36:04.179149 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 15:36:04.185555 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 15:36:04.189205 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 15:36:04.192439 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 15:36:04.198630 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5564 15:36:04.202130 0 15 28 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
5565 15:36:04.206054 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 15:36:04.209015 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 15:36:04.215850 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 15:36:04.218453 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 15:36:04.222008 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 15:36:04.228630 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 15:36:04.232197 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 15:36:04.235271 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5573 15:36:04.241887 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 15:36:04.245175 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 15:36:04.248381 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 15:36:04.254770 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 15:36:04.258083 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 15:36:04.264580 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 15:36:04.268128 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 15:36:04.271177 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 15:36:04.278034 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 15:36:04.281162 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 15:36:04.285118 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 15:36:04.291299 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 15:36:04.294153 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 15:36:04.297683 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 15:36:04.304023 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 15:36:04.307299 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5589 15:36:04.310770 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5590 15:36:04.317507 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 15:36:04.317594 Total UI for P1: 0, mck2ui 16
5592 15:36:04.320613 best dqsien dly found for B0: ( 1, 2, 30)
5593 15:36:04.324236 Total UI for P1: 0, mck2ui 16
5594 15:36:04.327654 best dqsien dly found for B1: ( 1, 2, 30)
5595 15:36:04.333784 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5596 15:36:04.337058 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5597 15:36:04.337130
5598 15:36:04.340380 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5599 15:36:04.343828 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5600 15:36:04.346880 [Gating] SW calibration Done
5601 15:36:04.346964 ==
5602 15:36:04.350716 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 15:36:04.353650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 15:36:04.353727 ==
5605 15:36:04.357035 RX Vref Scan: 0
5606 15:36:04.357113
5607 15:36:04.357175 RX Vref 0 -> 0, step: 1
5608 15:36:04.357238
5609 15:36:04.360064 RX Delay -80 -> 252, step: 8
5610 15:36:04.363419 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5611 15:36:04.370415 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5612 15:36:04.373832 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5613 15:36:04.376831 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5614 15:36:04.380079 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5615 15:36:04.383579 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5616 15:36:04.387045 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5617 15:36:04.393118 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5618 15:36:04.396685 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5619 15:36:04.399990 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5620 15:36:04.403190 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5621 15:36:04.406236 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5622 15:36:04.413192 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5623 15:36:04.416130 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5624 15:36:04.419644 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5625 15:36:04.422900 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5626 15:36:04.422977 ==
5627 15:36:04.425876 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 15:36:04.429745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 15:36:04.432470 ==
5630 15:36:04.432553 DQS Delay:
5631 15:36:04.432639 DQS0 = 0, DQS1 = 0
5632 15:36:04.435911 DQM Delay:
5633 15:36:04.436017 DQM0 = 98, DQM1 = 95
5634 15:36:04.439336 DQ Delay:
5635 15:36:04.442486 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5636 15:36:04.442584 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5637 15:36:04.446241 DQ8 =83, DQ9 =87, DQ10 =91, DQ11 =87
5638 15:36:04.452723 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5639 15:36:04.452823
5640 15:36:04.452892
5641 15:36:04.452952 ==
5642 15:36:04.456032 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 15:36:04.459233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 15:36:04.459332 ==
5645 15:36:04.459434
5646 15:36:04.459525
5647 15:36:04.462092 TX Vref Scan disable
5648 15:36:04.465668 == TX Byte 0 ==
5649 15:36:04.468752 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5650 15:36:04.472432 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5651 15:36:04.475795 == TX Byte 1 ==
5652 15:36:04.478820 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5653 15:36:04.482134 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5654 15:36:04.482234 ==
5655 15:36:04.485665 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 15:36:04.488889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 15:36:04.492006 ==
5658 15:36:04.492098
5659 15:36:04.492163
5660 15:36:04.492234 TX Vref Scan disable
5661 15:36:04.495789 == TX Byte 0 ==
5662 15:36:04.498650 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5663 15:36:04.505399 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5664 15:36:04.505478 == TX Byte 1 ==
5665 15:36:04.508426 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5666 15:36:04.515216 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5667 15:36:04.515311
5668 15:36:04.515379 [DATLAT]
5669 15:36:04.515441 Freq=933, CH1 RK0
5670 15:36:04.515504
5671 15:36:04.518571 DATLAT Default: 0xd
5672 15:36:04.522362 0, 0xFFFF, sum = 0
5673 15:36:04.522444 1, 0xFFFF, sum = 0
5674 15:36:04.524937 2, 0xFFFF, sum = 0
5675 15:36:04.525023 3, 0xFFFF, sum = 0
5676 15:36:04.528346 4, 0xFFFF, sum = 0
5677 15:36:04.528466 5, 0xFFFF, sum = 0
5678 15:36:04.531778 6, 0xFFFF, sum = 0
5679 15:36:04.531897 7, 0xFFFF, sum = 0
5680 15:36:04.534596 8, 0xFFFF, sum = 0
5681 15:36:04.534683 9, 0xFFFF, sum = 0
5682 15:36:04.538037 10, 0x0, sum = 1
5683 15:36:04.538120 11, 0x0, sum = 2
5684 15:36:04.541413 12, 0x0, sum = 3
5685 15:36:04.541491 13, 0x0, sum = 4
5686 15:36:04.544571 best_step = 11
5687 15:36:04.544650
5688 15:36:04.544714 ==
5689 15:36:04.548380 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 15:36:04.551337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 15:36:04.551418 ==
5692 15:36:04.551489 RX Vref Scan: 1
5693 15:36:04.554856
5694 15:36:04.554935 RX Vref 0 -> 0, step: 1
5695 15:36:04.554999
5696 15:36:04.558098 RX Delay -53 -> 252, step: 4
5697 15:36:04.558179
5698 15:36:04.561225 Set Vref, RX VrefLevel [Byte0]: 51
5699 15:36:04.564823 [Byte1]: 50
5700 15:36:04.567755
5701 15:36:04.567836 Final RX Vref Byte 0 = 51 to rank0
5702 15:36:04.571315 Final RX Vref Byte 1 = 50 to rank0
5703 15:36:04.574616 Final RX Vref Byte 0 = 51 to rank1
5704 15:36:04.577718 Final RX Vref Byte 1 = 50 to rank1==
5705 15:36:04.581233 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 15:36:04.587556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 15:36:04.587637 ==
5708 15:36:04.587702 DQS Delay:
5709 15:36:04.590879 DQS0 = 0, DQS1 = 0
5710 15:36:04.590986 DQM Delay:
5711 15:36:04.591065 DQM0 = 98, DQM1 = 94
5712 15:36:04.594193 DQ Delay:
5713 15:36:04.597690 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =98
5714 15:36:04.601184 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5715 15:36:04.604030 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5716 15:36:04.607519 DQ12 =100, DQ13 =104, DQ14 =100, DQ15 =102
5717 15:36:04.607600
5718 15:36:04.607667
5719 15:36:04.614415 [DQSOSCAuto] RK0, (LSB)MR18= 0x515, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 420 ps
5720 15:36:04.617480 CH1 RK0: MR19=505, MR18=515
5721 15:36:04.623910 CH1_RK0: MR19=0x505, MR18=0x515, DQSOSC=415, MR23=63, INC=62, DEC=41
5722 15:36:04.623993
5723 15:36:04.627061 ----->DramcWriteLeveling(PI) begin...
5724 15:36:04.627136 ==
5725 15:36:04.631480 Dram Type= 6, Freq= 0, CH_1, rank 1
5726 15:36:04.633930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 15:36:04.634020 ==
5728 15:36:04.637078 Write leveling (Byte 0): 25 => 25
5729 15:36:04.640555 Write leveling (Byte 1): 26 => 26
5730 15:36:04.643688 DramcWriteLeveling(PI) end<-----
5731 15:36:04.643770
5732 15:36:04.643849 ==
5733 15:36:04.647380 Dram Type= 6, Freq= 0, CH_1, rank 1
5734 15:36:04.653602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 15:36:04.653687 ==
5736 15:36:04.653755 [Gating] SW mode calibration
5737 15:36:04.663324 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5738 15:36:04.666669 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5739 15:36:04.673365 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 15:36:04.676780 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 15:36:04.680234 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 15:36:04.686569 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 15:36:04.689506 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 15:36:04.693030 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5745 15:36:04.699922 0 14 24 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (1 1)
5746 15:36:04.702751 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5747 15:36:04.706409 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 15:36:04.712926 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 15:36:04.716420 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 15:36:04.719296 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 15:36:04.725994 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 15:36:04.729740 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 15:36:04.732833 0 15 24 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (0 0)
5754 15:36:04.739328 0 15 28 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
5755 15:36:04.742419 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 15:36:04.746355 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 15:36:04.752390 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 15:36:04.755480 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 15:36:04.759097 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 15:36:04.765681 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 15:36:04.769131 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5762 15:36:04.772500 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 15:36:04.776066 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 15:36:04.782407 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 15:36:04.785667 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 15:36:04.791848 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 15:36:04.795109 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 15:36:04.798578 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 15:36:04.804933 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 15:36:04.808107 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 15:36:04.811602 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 15:36:04.818047 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 15:36:04.821530 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 15:36:04.824745 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 15:36:04.831513 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 15:36:04.834499 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 15:36:04.838107 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 15:36:04.844880 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5779 15:36:04.844967 Total UI for P1: 0, mck2ui 16
5780 15:36:04.851173 best dqsien dly found for B0: ( 1, 2, 26)
5781 15:36:04.854692 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 15:36:04.857822 Total UI for P1: 0, mck2ui 16
5783 15:36:04.861209 best dqsien dly found for B1: ( 1, 2, 28)
5784 15:36:04.864818 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5785 15:36:04.867774 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5786 15:36:04.867860
5787 15:36:04.871313 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5788 15:36:04.874197 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5789 15:36:04.877685 [Gating] SW calibration Done
5790 15:36:04.877770 ==
5791 15:36:04.880727 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 15:36:04.883981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 15:36:04.887217 ==
5794 15:36:04.887302 RX Vref Scan: 0
5795 15:36:04.887390
5796 15:36:04.890901 RX Vref 0 -> 0, step: 1
5797 15:36:04.891021
5798 15:36:04.891123 RX Delay -80 -> 252, step: 8
5799 15:36:04.897712 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5800 15:36:04.900956 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5801 15:36:04.904097 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5802 15:36:04.907631 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5803 15:36:04.910634 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5804 15:36:04.917671 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5805 15:36:04.920725 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5806 15:36:04.924113 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5807 15:36:04.927572 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5808 15:36:04.930304 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5809 15:36:04.933837 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5810 15:36:04.940170 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5811 15:36:04.943476 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5812 15:36:04.946909 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5813 15:36:04.950158 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5814 15:36:04.953446 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5815 15:36:04.956425 ==
5816 15:36:04.956538 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 15:36:04.963286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 15:36:04.963376 ==
5819 15:36:04.963448 DQS Delay:
5820 15:36:04.966537 DQS0 = 0, DQS1 = 0
5821 15:36:04.966618 DQM Delay:
5822 15:36:04.969773 DQM0 = 97, DQM1 = 94
5823 15:36:04.969848 DQ Delay:
5824 15:36:04.973366 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5825 15:36:04.976134 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5826 15:36:04.979689 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5827 15:36:04.983058 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5828 15:36:04.983137
5829 15:36:04.983226
5830 15:36:04.983306 ==
5831 15:36:04.986128 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 15:36:04.990053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 15:36:04.992671 ==
5834 15:36:04.992771
5835 15:36:04.992859
5836 15:36:04.992942 TX Vref Scan disable
5837 15:36:04.996423 == TX Byte 0 ==
5838 15:36:04.999765 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5839 15:36:05.002923 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5840 15:36:05.006148 == TX Byte 1 ==
5841 15:36:05.009639 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5842 15:36:05.013130 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5843 15:36:05.013215 ==
5844 15:36:05.015882 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 15:36:05.022492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 15:36:05.022578 ==
5847 15:36:05.022679
5848 15:36:05.022784
5849 15:36:05.025997 TX Vref Scan disable
5850 15:36:05.026078 == TX Byte 0 ==
5851 15:36:05.032332 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5852 15:36:05.035678 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5853 15:36:05.035766 == TX Byte 1 ==
5854 15:36:05.042038 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5855 15:36:05.045462 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5856 15:36:05.045551
5857 15:36:05.045617 [DATLAT]
5858 15:36:05.048480 Freq=933, CH1 RK1
5859 15:36:05.048580
5860 15:36:05.048646 DATLAT Default: 0xb
5861 15:36:05.051785 0, 0xFFFF, sum = 0
5862 15:36:05.051895 1, 0xFFFF, sum = 0
5863 15:36:05.055147 2, 0xFFFF, sum = 0
5864 15:36:05.055231 3, 0xFFFF, sum = 0
5865 15:36:05.058967 4, 0xFFFF, sum = 0
5866 15:36:05.061573 5, 0xFFFF, sum = 0
5867 15:36:05.061658 6, 0xFFFF, sum = 0
5868 15:36:05.065062 7, 0xFFFF, sum = 0
5869 15:36:05.065145 8, 0xFFFF, sum = 0
5870 15:36:05.068578 9, 0xFFFF, sum = 0
5871 15:36:05.068674 10, 0x0, sum = 1
5872 15:36:05.071544 11, 0x0, sum = 2
5873 15:36:05.071654 12, 0x0, sum = 3
5874 15:36:05.074720 13, 0x0, sum = 4
5875 15:36:05.074804 best_step = 11
5876 15:36:05.074869
5877 15:36:05.074930 ==
5878 15:36:05.078151 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 15:36:05.081253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 15:36:05.081344 ==
5881 15:36:05.085357 RX Vref Scan: 0
5882 15:36:05.085439
5883 15:36:05.088157 RX Vref 0 -> 0, step: 1
5884 15:36:05.088273
5885 15:36:05.088374 RX Delay -53 -> 252, step: 4
5886 15:36:05.095914 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5887 15:36:05.099456 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5888 15:36:05.102821 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5889 15:36:05.105746 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5890 15:36:05.109152 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5891 15:36:05.115536 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5892 15:36:05.119287 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5893 15:36:05.122550 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5894 15:36:05.125401 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5895 15:36:05.128750 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5896 15:36:05.132197 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5897 15:36:05.138892 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5898 15:36:05.142126 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5899 15:36:05.145582 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5900 15:36:05.148578 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5901 15:36:05.155214 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5902 15:36:05.155341 ==
5903 15:36:05.158598 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 15:36:05.161804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 15:36:05.161893 ==
5906 15:36:05.161960 DQS Delay:
5907 15:36:05.165367 DQS0 = 0, DQS1 = 0
5908 15:36:05.165442 DQM Delay:
5909 15:36:05.168633 DQM0 = 97, DQM1 = 92
5910 15:36:05.168705 DQ Delay:
5911 15:36:05.171493 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =94
5912 15:36:05.174951 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =94
5913 15:36:05.178186 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =84
5914 15:36:05.181874 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5915 15:36:05.181956
5916 15:36:05.182042
5917 15:36:05.191511 [DQSOSCAuto] RK1, (LSB)MR18= 0xe24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5918 15:36:05.191600 CH1 RK1: MR19=505, MR18=E24
5919 15:36:05.198410 CH1_RK1: MR19=0x505, MR18=0xE24, DQSOSC=410, MR23=63, INC=64, DEC=42
5920 15:36:05.201287 [RxdqsGatingPostProcess] freq 933
5921 15:36:05.208392 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5922 15:36:05.211512 best DQS0 dly(2T, 0.5T) = (0, 10)
5923 15:36:05.215179 best DQS1 dly(2T, 0.5T) = (0, 10)
5924 15:36:05.218029 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5925 15:36:05.221284 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5926 15:36:05.224469 best DQS0 dly(2T, 0.5T) = (0, 10)
5927 15:36:05.224554 best DQS1 dly(2T, 0.5T) = (0, 10)
5928 15:36:05.227622 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5929 15:36:05.231162 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5930 15:36:05.234236 Pre-setting of DQS Precalculation
5931 15:36:05.240982 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5932 15:36:05.247505 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5933 15:36:05.253999 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5934 15:36:05.254086
5935 15:36:05.254177
5936 15:36:05.257668 [Calibration Summary] 1866 Mbps
5937 15:36:05.260510 CH 0, Rank 0
5938 15:36:05.260596 SW Impedance : PASS
5939 15:36:05.264177 DUTY Scan : NO K
5940 15:36:05.267147 ZQ Calibration : PASS
5941 15:36:05.267229 Jitter Meter : NO K
5942 15:36:05.270385 CBT Training : PASS
5943 15:36:05.273946 Write leveling : PASS
5944 15:36:05.274032 RX DQS gating : PASS
5945 15:36:05.277128 RX DQ/DQS(RDDQC) : PASS
5946 15:36:05.277206 TX DQ/DQS : PASS
5947 15:36:05.280653 RX DATLAT : PASS
5948 15:36:05.283642 RX DQ/DQS(Engine): PASS
5949 15:36:05.283722 TX OE : NO K
5950 15:36:05.287009 All Pass.
5951 15:36:05.287086
5952 15:36:05.287173 CH 0, Rank 1
5953 15:36:05.290389 SW Impedance : PASS
5954 15:36:05.290472 DUTY Scan : NO K
5955 15:36:05.293402 ZQ Calibration : PASS
5956 15:36:05.296661 Jitter Meter : NO K
5957 15:36:05.296747 CBT Training : PASS
5958 15:36:05.300723 Write leveling : PASS
5959 15:36:05.303474 RX DQS gating : PASS
5960 15:36:05.303653 RX DQ/DQS(RDDQC) : PASS
5961 15:36:05.307083 TX DQ/DQS : PASS
5962 15:36:05.309886 RX DATLAT : PASS
5963 15:36:05.310017 RX DQ/DQS(Engine): PASS
5964 15:36:05.313283 TX OE : NO K
5965 15:36:05.313353 All Pass.
5966 15:36:05.313415
5967 15:36:05.316773 CH 1, Rank 0
5968 15:36:05.316841 SW Impedance : PASS
5969 15:36:05.319849 DUTY Scan : NO K
5970 15:36:05.322971 ZQ Calibration : PASS
5971 15:36:05.323038 Jitter Meter : NO K
5972 15:36:05.326691 CBT Training : PASS
5973 15:36:05.329655 Write leveling : PASS
5974 15:36:05.329757 RX DQS gating : PASS
5975 15:36:05.332936 RX DQ/DQS(RDDQC) : PASS
5976 15:36:05.336326 TX DQ/DQS : PASS
5977 15:36:05.336403 RX DATLAT : PASS
5978 15:36:05.339739 RX DQ/DQS(Engine): PASS
5979 15:36:05.343181 TX OE : NO K
5980 15:36:05.343290 All Pass.
5981 15:36:05.343407
5982 15:36:05.343504 CH 1, Rank 1
5983 15:36:05.346576 SW Impedance : PASS
5984 15:36:05.349861 DUTY Scan : NO K
5985 15:36:05.349941 ZQ Calibration : PASS
5986 15:36:05.352736 Jitter Meter : NO K
5987 15:36:05.356456 CBT Training : PASS
5988 15:36:05.356543 Write leveling : PASS
5989 15:36:05.359479 RX DQS gating : PASS
5990 15:36:05.359594 RX DQ/DQS(RDDQC) : PASS
5991 15:36:05.362796 TX DQ/DQS : PASS
5992 15:36:05.366303 RX DATLAT : PASS
5993 15:36:05.366379 RX DQ/DQS(Engine): PASS
5994 15:36:05.369660 TX OE : NO K
5995 15:36:05.369762 All Pass.
5996 15:36:05.369828
5997 15:36:05.372702 DramC Write-DBI off
5998 15:36:05.375898 PER_BANK_REFRESH: Hybrid Mode
5999 15:36:05.376008 TX_TRACKING: ON
6000 15:36:05.385508 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6001 15:36:05.389123 [FAST_K] Save calibration result to emmc
6002 15:36:05.392112 dramc_set_vcore_voltage set vcore to 650000
6003 15:36:05.395811 Read voltage for 400, 6
6004 15:36:05.395939 Vio18 = 0
6005 15:36:05.398689 Vcore = 650000
6006 15:36:05.398792 Vdram = 0
6007 15:36:05.398884 Vddq = 0
6008 15:36:05.398967 Vmddr = 0
6009 15:36:05.405465 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6010 15:36:05.411966 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6011 15:36:05.412047 MEM_TYPE=3, freq_sel=20
6012 15:36:05.415393 sv_algorithm_assistance_LP4_800
6013 15:36:05.418798 ============ PULL DRAM RESETB DOWN ============
6014 15:36:05.425224 ========== PULL DRAM RESETB DOWN end =========
6015 15:36:05.428628 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6016 15:36:05.431690 ===================================
6017 15:36:05.435352 LPDDR4 DRAM CONFIGURATION
6018 15:36:05.438845 ===================================
6019 15:36:05.438947 EX_ROW_EN[0] = 0x0
6020 15:36:05.442253 EX_ROW_EN[1] = 0x0
6021 15:36:05.442364 LP4Y_EN = 0x0
6022 15:36:05.445477 WORK_FSP = 0x0
6023 15:36:05.448794 WL = 0x2
6024 15:36:05.448906 RL = 0x2
6025 15:36:05.451555 BL = 0x2
6026 15:36:05.451630 RPST = 0x0
6027 15:36:05.454889 RD_PRE = 0x0
6028 15:36:05.454990 WR_PRE = 0x1
6029 15:36:05.458333 WR_PST = 0x0
6030 15:36:05.458428 DBI_WR = 0x0
6031 15:36:05.461850 DBI_RD = 0x0
6032 15:36:05.461945 OTF = 0x1
6033 15:36:05.465148 ===================================
6034 15:36:05.468603 ===================================
6035 15:36:05.471395 ANA top config
6036 15:36:05.474589 ===================================
6037 15:36:05.474704 DLL_ASYNC_EN = 0
6038 15:36:05.478255 ALL_SLAVE_EN = 1
6039 15:36:05.481128 NEW_RANK_MODE = 1
6040 15:36:05.484580 DLL_IDLE_MODE = 1
6041 15:36:05.487977 LP45_APHY_COMB_EN = 1
6042 15:36:05.488083 TX_ODT_DIS = 1
6043 15:36:05.491699 NEW_8X_MODE = 1
6044 15:36:05.494314 ===================================
6045 15:36:05.497782 ===================================
6046 15:36:05.501474 data_rate = 800
6047 15:36:05.504297 CKR = 1
6048 15:36:05.507760 DQ_P2S_RATIO = 4
6049 15:36:05.510873 ===================================
6050 15:36:05.514415 CA_P2S_RATIO = 4
6051 15:36:05.514494 DQ_CA_OPEN = 0
6052 15:36:05.517784 DQ_SEMI_OPEN = 1
6053 15:36:05.521054 CA_SEMI_OPEN = 1
6054 15:36:05.524312 CA_FULL_RATE = 0
6055 15:36:05.527793 DQ_CKDIV4_EN = 0
6056 15:36:05.530697 CA_CKDIV4_EN = 1
6057 15:36:05.530771 CA_PREDIV_EN = 0
6058 15:36:05.534003 PH8_DLY = 0
6059 15:36:05.537343 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6060 15:36:05.540592 DQ_AAMCK_DIV = 0
6061 15:36:05.544132 CA_AAMCK_DIV = 0
6062 15:36:05.546800 CA_ADMCK_DIV = 4
6063 15:36:05.546901 DQ_TRACK_CA_EN = 0
6064 15:36:05.550469 CA_PICK = 800
6065 15:36:05.553555 CA_MCKIO = 400
6066 15:36:05.556931 MCKIO_SEMI = 400
6067 15:36:05.560293 PLL_FREQ = 3016
6068 15:36:05.563663 DQ_UI_PI_RATIO = 32
6069 15:36:05.567014 CA_UI_PI_RATIO = 32
6070 15:36:05.570376 ===================================
6071 15:36:05.573671 ===================================
6072 15:36:05.576621 memory_type:LPDDR4
6073 15:36:05.576712 GP_NUM : 10
6074 15:36:05.580235 SRAM_EN : 1
6075 15:36:05.580309 MD32_EN : 0
6076 15:36:05.583486 ===================================
6077 15:36:05.586491 [ANA_INIT] >>>>>>>>>>>>>>
6078 15:36:05.590083 <<<<<< [CONFIGURE PHASE]: ANA_TX
6079 15:36:05.593705 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6080 15:36:05.596420 ===================================
6081 15:36:05.600067 data_rate = 800,PCW = 0X7400
6082 15:36:05.603696 ===================================
6083 15:36:05.606610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6084 15:36:05.610080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6085 15:36:05.622988 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6086 15:36:05.626980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6087 15:36:05.629967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6088 15:36:05.634250 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6089 15:36:05.636231 [ANA_INIT] flow start
6090 15:36:05.639510 [ANA_INIT] PLL >>>>>>>>
6091 15:36:05.639607 [ANA_INIT] PLL <<<<<<<<
6092 15:36:05.643284 [ANA_INIT] MIDPI >>>>>>>>
6093 15:36:05.646128 [ANA_INIT] MIDPI <<<<<<<<
6094 15:36:05.649419 [ANA_INIT] DLL >>>>>>>>
6095 15:36:05.649514 [ANA_INIT] flow end
6096 15:36:05.652890 ============ LP4 DIFF to SE enter ============
6097 15:36:05.659226 ============ LP4 DIFF to SE exit ============
6098 15:36:05.659306 [ANA_INIT] <<<<<<<<<<<<<
6099 15:36:05.663024 [Flow] Enable top DCM control >>>>>
6100 15:36:05.666169 [Flow] Enable top DCM control <<<<<
6101 15:36:05.669153 Enable DLL master slave shuffle
6102 15:36:05.675621 ==============================================================
6103 15:36:05.675728 Gating Mode config
6104 15:36:05.682550 ==============================================================
6105 15:36:05.685835 Config description:
6106 15:36:05.695307 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6107 15:36:05.701968 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6108 15:36:05.705554 SELPH_MODE 0: By rank 1: By Phase
6109 15:36:05.711813 ==============================================================
6110 15:36:05.715379 GAT_TRACK_EN = 0
6111 15:36:05.718849 RX_GATING_MODE = 2
6112 15:36:05.722117 RX_GATING_TRACK_MODE = 2
6113 15:36:05.722198 SELPH_MODE = 1
6114 15:36:05.725745 PICG_EARLY_EN = 1
6115 15:36:05.728685 VALID_LAT_VALUE = 1
6116 15:36:05.734962 ==============================================================
6117 15:36:05.738334 Enter into Gating configuration >>>>
6118 15:36:05.741789 Exit from Gating configuration <<<<
6119 15:36:05.745201 Enter into DVFS_PRE_config >>>>>
6120 15:36:05.754853 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6121 15:36:05.758417 Exit from DVFS_PRE_config <<<<<
6122 15:36:05.761472 Enter into PICG configuration >>>>
6123 15:36:05.764780 Exit from PICG configuration <<<<
6124 15:36:05.768432 [RX_INPUT] configuration >>>>>
6125 15:36:05.771282 [RX_INPUT] configuration <<<<<
6126 15:36:05.774553 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6127 15:36:05.781286 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6128 15:36:05.787628 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6129 15:36:05.794237 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6130 15:36:05.800983 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6131 15:36:05.807467 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6132 15:36:05.811232 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6133 15:36:05.814115 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6134 15:36:05.817716 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6135 15:36:05.824458 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6136 15:36:05.827457 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6137 15:36:05.830874 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6138 15:36:05.834228 ===================================
6139 15:36:05.837516 LPDDR4 DRAM CONFIGURATION
6140 15:36:05.840514 ===================================
6141 15:36:05.840620 EX_ROW_EN[0] = 0x0
6142 15:36:05.843778 EX_ROW_EN[1] = 0x0
6143 15:36:05.843886 LP4Y_EN = 0x0
6144 15:36:05.847312 WORK_FSP = 0x0
6145 15:36:05.851039 WL = 0x2
6146 15:36:05.851146 RL = 0x2
6147 15:36:05.853721 BL = 0x2
6148 15:36:05.853827 RPST = 0x0
6149 15:36:05.856849 RD_PRE = 0x0
6150 15:36:05.856958 WR_PRE = 0x1
6151 15:36:05.860520 WR_PST = 0x0
6152 15:36:05.860634 DBI_WR = 0x0
6153 15:36:05.863878 DBI_RD = 0x0
6154 15:36:05.863997 OTF = 0x1
6155 15:36:05.867279 ===================================
6156 15:36:05.870154 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6157 15:36:05.876636 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6158 15:36:05.879847 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6159 15:36:05.883654 ===================================
6160 15:36:05.886597 LPDDR4 DRAM CONFIGURATION
6161 15:36:05.889945 ===================================
6162 15:36:05.890052 EX_ROW_EN[0] = 0x10
6163 15:36:05.893426 EX_ROW_EN[1] = 0x0
6164 15:36:05.897056 LP4Y_EN = 0x0
6165 15:36:05.897168 WORK_FSP = 0x0
6166 15:36:05.899615 WL = 0x2
6167 15:36:05.899717 RL = 0x2
6168 15:36:05.903238 BL = 0x2
6169 15:36:05.903319 RPST = 0x0
6170 15:36:05.906597 RD_PRE = 0x0
6171 15:36:05.906703 WR_PRE = 0x1
6172 15:36:05.909899 WR_PST = 0x0
6173 15:36:05.910002 DBI_WR = 0x0
6174 15:36:05.913351 DBI_RD = 0x0
6175 15:36:05.913454 OTF = 0x1
6176 15:36:05.916294 ===================================
6177 15:36:05.922939 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6178 15:36:05.927245 nWR fixed to 30
6179 15:36:05.930324 [ModeRegInit_LP4] CH0 RK0
6180 15:36:05.930428 [ModeRegInit_LP4] CH0 RK1
6181 15:36:05.933747 [ModeRegInit_LP4] CH1 RK0
6182 15:36:05.937326 [ModeRegInit_LP4] CH1 RK1
6183 15:36:05.937423 match AC timing 19
6184 15:36:05.944075 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6185 15:36:05.947003 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6186 15:36:05.950461 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6187 15:36:05.956741 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6188 15:36:05.960609 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6189 15:36:05.960718 ==
6190 15:36:05.963497 Dram Type= 6, Freq= 0, CH_0, rank 0
6191 15:36:05.966826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6192 15:36:05.966929 ==
6193 15:36:05.973086 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6194 15:36:05.979812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6195 15:36:05.983168 [CA 0] Center 36 (8~64) winsize 57
6196 15:36:05.986708 [CA 1] Center 36 (8~64) winsize 57
6197 15:36:05.989666 [CA 2] Center 36 (8~64) winsize 57
6198 15:36:05.993338 [CA 3] Center 36 (8~64) winsize 57
6199 15:36:05.996339 [CA 4] Center 36 (8~64) winsize 57
6200 15:36:05.999979 [CA 5] Center 36 (8~64) winsize 57
6201 15:36:06.000057
6202 15:36:06.003194 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6203 15:36:06.003267
6204 15:36:06.006220 [CATrainingPosCal] consider 1 rank data
6205 15:36:06.009691 u2DelayCellTimex100 = 270/100 ps
6206 15:36:06.012756 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 15:36:06.016088 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 15:36:06.019888 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 15:36:06.022502 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 15:36:06.025897 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 15:36:06.029208 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 15:36:06.029288
6213 15:36:06.035926 CA PerBit enable=1, Macro0, CA PI delay=36
6214 15:36:06.036009
6215 15:36:06.036076 [CBTSetCACLKResult] CA Dly = 36
6216 15:36:06.039280 CS Dly: 1 (0~32)
6217 15:36:06.039349 ==
6218 15:36:06.042288 Dram Type= 6, Freq= 0, CH_0, rank 1
6219 15:36:06.045479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6220 15:36:06.045559 ==
6221 15:36:06.052503 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6222 15:36:06.059106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6223 15:36:06.062426 [CA 0] Center 36 (8~64) winsize 57
6224 15:36:06.065366 [CA 1] Center 36 (8~64) winsize 57
6225 15:36:06.069048 [CA 2] Center 36 (8~64) winsize 57
6226 15:36:06.071888 [CA 3] Center 36 (8~64) winsize 57
6227 15:36:06.075479 [CA 4] Center 36 (8~64) winsize 57
6228 15:36:06.075582 [CA 5] Center 36 (8~64) winsize 57
6229 15:36:06.078591
6230 15:36:06.082099 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6231 15:36:06.082202
6232 15:36:06.085016 [CATrainingPosCal] consider 2 rank data
6233 15:36:06.088841 u2DelayCellTimex100 = 270/100 ps
6234 15:36:06.091821 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 15:36:06.095159 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 15:36:06.098453 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 15:36:06.101990 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 15:36:06.105271 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 15:36:06.108157 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 15:36:06.108231
6241 15:36:06.111456 CA PerBit enable=1, Macro0, CA PI delay=36
6242 15:36:06.111553
6243 15:36:06.114723 [CBTSetCACLKResult] CA Dly = 36
6244 15:36:06.118054 CS Dly: 1 (0~32)
6245 15:36:06.118158
6246 15:36:06.121489 ----->DramcWriteLeveling(PI) begin...
6247 15:36:06.121594 ==
6248 15:36:06.125002 Dram Type= 6, Freq= 0, CH_0, rank 0
6249 15:36:06.128065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 15:36:06.128165 ==
6251 15:36:06.131378 Write leveling (Byte 0): 40 => 8
6252 15:36:06.134911 Write leveling (Byte 1): 40 => 8
6253 15:36:06.137946 DramcWriteLeveling(PI) end<-----
6254 15:36:06.138046
6255 15:36:06.138137 ==
6256 15:36:06.141477 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 15:36:06.144346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 15:36:06.144448 ==
6259 15:36:06.147869 [Gating] SW mode calibration
6260 15:36:06.154326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6261 15:36:06.160867 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6262 15:36:06.164341 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6263 15:36:06.171537 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6264 15:36:06.174560 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6265 15:36:06.177750 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 15:36:06.184071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 15:36:06.187603 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 15:36:06.190663 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 15:36:06.197260 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 15:36:06.200541 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 15:36:06.204061 Total UI for P1: 0, mck2ui 16
6272 15:36:06.206975 best dqsien dly found for B0: ( 0, 14, 24)
6273 15:36:06.210527 Total UI for P1: 0, mck2ui 16
6274 15:36:06.213994 best dqsien dly found for B1: ( 0, 14, 24)
6275 15:36:06.216949 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6276 15:36:06.220476 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6277 15:36:06.220576
6278 15:36:06.223494 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6279 15:36:06.226741 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6280 15:36:06.230006 [Gating] SW calibration Done
6281 15:36:06.230079 ==
6282 15:36:06.233613 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 15:36:06.239959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 15:36:06.240037 ==
6285 15:36:06.240109 RX Vref Scan: 0
6286 15:36:06.240174
6287 15:36:06.243448 RX Vref 0 -> 0, step: 1
6288 15:36:06.243546
6289 15:36:06.246786 RX Delay -410 -> 252, step: 16
6290 15:36:06.249990 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6291 15:36:06.253448 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6292 15:36:06.259777 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6293 15:36:06.263175 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6294 15:36:06.266836 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6295 15:36:06.270145 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6296 15:36:06.276144 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6297 15:36:06.279460 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6298 15:36:06.283219 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6299 15:36:06.286223 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6300 15:36:06.292784 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6301 15:36:06.296179 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6302 15:36:06.299331 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6303 15:36:06.305590 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6304 15:36:06.309051 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6305 15:36:06.312547 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6306 15:36:06.312650 ==
6307 15:36:06.315497 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 15:36:06.318929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 15:36:06.322427 ==
6310 15:36:06.322530 DQS Delay:
6311 15:36:06.322622 DQS0 = 35, DQS1 = 51
6312 15:36:06.326105 DQM Delay:
6313 15:36:06.326208 DQM0 = 4, DQM1 = 11
6314 15:36:06.329006 DQ Delay:
6315 15:36:06.329103 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6316 15:36:06.332680 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6317 15:36:06.335596 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6318 15:36:06.338834 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6319 15:36:06.338933
6320 15:36:06.339027
6321 15:36:06.339115 ==
6322 15:36:06.342093 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 15:36:06.348510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 15:36:06.348615 ==
6325 15:36:06.348710
6326 15:36:06.348801
6327 15:36:06.348888 TX Vref Scan disable
6328 15:36:06.352492 == TX Byte 0 ==
6329 15:36:06.355710 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6330 15:36:06.358857 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6331 15:36:06.361936 == TX Byte 1 ==
6332 15:36:06.365208 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6333 15:36:06.368643 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6334 15:36:06.371830 ==
6335 15:36:06.374844 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 15:36:06.378715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 15:36:06.378818 ==
6338 15:36:06.378912
6339 15:36:06.379003
6340 15:36:06.382272 TX Vref Scan disable
6341 15:36:06.382370 == TX Byte 0 ==
6342 15:36:06.384858 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 15:36:06.392051 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 15:36:06.392172 == TX Byte 1 ==
6345 15:36:06.394975 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 15:36:06.401733 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 15:36:06.401839
6348 15:36:06.401929 [DATLAT]
6349 15:36:06.402016 Freq=400, CH0 RK0
6350 15:36:06.402105
6351 15:36:06.404950 DATLAT Default: 0xf
6352 15:36:06.405048 0, 0xFFFF, sum = 0
6353 15:36:06.408245 1, 0xFFFF, sum = 0
6354 15:36:06.411482 2, 0xFFFF, sum = 0
6355 15:36:06.411596 3, 0xFFFF, sum = 0
6356 15:36:06.414982 4, 0xFFFF, sum = 0
6357 15:36:06.415082 5, 0xFFFF, sum = 0
6358 15:36:06.418049 6, 0xFFFF, sum = 0
6359 15:36:06.418147 7, 0xFFFF, sum = 0
6360 15:36:06.421817 8, 0xFFFF, sum = 0
6361 15:36:06.421915 9, 0xFFFF, sum = 0
6362 15:36:06.425105 10, 0xFFFF, sum = 0
6363 15:36:06.425206 11, 0xFFFF, sum = 0
6364 15:36:06.428045 12, 0xFFFF, sum = 0
6365 15:36:06.428120 13, 0x0, sum = 1
6366 15:36:06.431376 14, 0x0, sum = 2
6367 15:36:06.431476 15, 0x0, sum = 3
6368 15:36:06.434797 16, 0x0, sum = 4
6369 15:36:06.434916 best_step = 14
6370 15:36:06.435012
6371 15:36:06.435101 ==
6372 15:36:06.438341 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 15:36:06.441425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 15:36:06.444519 ==
6375 15:36:06.444593 RX Vref Scan: 1
6376 15:36:06.444654
6377 15:36:06.447727 RX Vref 0 -> 0, step: 1
6378 15:36:06.447834
6379 15:36:06.451356 RX Delay -343 -> 252, step: 8
6380 15:36:06.451454
6381 15:36:06.454649 Set Vref, RX VrefLevel [Byte0]: 52
6382 15:36:06.457843 [Byte1]: 59
6383 15:36:06.457953
6384 15:36:06.460950 Final RX Vref Byte 0 = 52 to rank0
6385 15:36:06.464474 Final RX Vref Byte 1 = 59 to rank0
6386 15:36:06.467712 Final RX Vref Byte 0 = 52 to rank1
6387 15:36:06.470738 Final RX Vref Byte 1 = 59 to rank1==
6388 15:36:06.474312 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 15:36:06.477517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 15:36:06.480560 ==
6391 15:36:06.480668 DQS Delay:
6392 15:36:06.480767 DQS0 = 44, DQS1 = 60
6393 15:36:06.484225 DQM Delay:
6394 15:36:06.484326 DQM0 = 10, DQM1 = 16
6395 15:36:06.487520 DQ Delay:
6396 15:36:06.490588 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6397 15:36:06.490730 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6398 15:36:06.494004 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6399 15:36:06.497142 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6400 15:36:06.497245
6401 15:36:06.500908
6402 15:36:06.507261 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c90, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 390 ps
6403 15:36:06.510784 CH0 RK0: MR19=C0C, MR18=9C90
6404 15:36:06.517828 CH0_RK0: MR19=0xC0C, MR18=0x9C90, DQSOSC=390, MR23=63, INC=388, DEC=258
6405 15:36:06.517933 ==
6406 15:36:06.520679 Dram Type= 6, Freq= 0, CH_0, rank 1
6407 15:36:06.524081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 15:36:06.524187 ==
6409 15:36:06.526662 [Gating] SW mode calibration
6410 15:36:06.533512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6411 15:36:06.539898 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6412 15:36:06.543325 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6413 15:36:06.546618 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6414 15:36:06.553502 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6415 15:36:06.556528 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6416 15:36:06.559819 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 15:36:06.566584 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 15:36:06.569905 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6419 15:36:06.572845 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 15:36:06.579534 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 15:36:06.579687 Total UI for P1: 0, mck2ui 16
6422 15:36:06.586265 best dqsien dly found for B0: ( 0, 14, 24)
6423 15:36:06.586366 Total UI for P1: 0, mck2ui 16
6424 15:36:06.592418 best dqsien dly found for B1: ( 0, 14, 24)
6425 15:36:06.596135 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6426 15:36:06.599134 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6427 15:36:06.599233
6428 15:36:06.602278 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6429 15:36:06.605628 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6430 15:36:06.609280 [Gating] SW calibration Done
6431 15:36:06.609380 ==
6432 15:36:06.612680 Dram Type= 6, Freq= 0, CH_0, rank 1
6433 15:36:06.615459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 15:36:06.615555 ==
6435 15:36:06.619147 RX Vref Scan: 0
6436 15:36:06.619245
6437 15:36:06.622207 RX Vref 0 -> 0, step: 1
6438 15:36:06.622305
6439 15:36:06.622399 RX Delay -410 -> 252, step: 16
6440 15:36:06.629522 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6441 15:36:06.632271 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6442 15:36:06.635576 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6443 15:36:06.638568 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6444 15:36:06.645614 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6445 15:36:06.648633 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6446 15:36:06.651858 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6447 15:36:06.658974 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6448 15:36:06.661676 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6449 15:36:06.664949 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6450 15:36:06.668486 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6451 15:36:06.674819 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6452 15:36:06.677941 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6453 15:36:06.681681 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6454 15:36:06.684731 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6455 15:36:06.690976 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6456 15:36:06.691104 ==
6457 15:36:06.694761 Dram Type= 6, Freq= 0, CH_0, rank 1
6458 15:36:06.698270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 15:36:06.698379 ==
6460 15:36:06.700960 DQS Delay:
6461 15:36:06.701070 DQS0 = 35, DQS1 = 59
6462 15:36:06.701162 DQM Delay:
6463 15:36:06.704417 DQM0 = 6, DQM1 = 16
6464 15:36:06.704535 DQ Delay:
6465 15:36:06.708008 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6466 15:36:06.710992 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6467 15:36:06.714445 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6468 15:36:06.717781 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6469 15:36:06.717880
6470 15:36:06.717972
6471 15:36:06.718070 ==
6472 15:36:06.720790 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 15:36:06.724071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 15:36:06.727430 ==
6475 15:36:06.727520
6476 15:36:06.727583
6477 15:36:06.727642 TX Vref Scan disable
6478 15:36:06.730991 == TX Byte 0 ==
6479 15:36:06.733868 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6480 15:36:06.737112 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6481 15:36:06.740325 == TX Byte 1 ==
6482 15:36:06.743811 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6483 15:36:06.747073 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6484 15:36:06.747149 ==
6485 15:36:06.750977 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 15:36:06.756993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 15:36:06.757108 ==
6488 15:36:06.757212
6489 15:36:06.757312
6490 15:36:06.757398 TX Vref Scan disable
6491 15:36:06.760432 == TX Byte 0 ==
6492 15:36:06.763759 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6493 15:36:06.766888 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6494 15:36:06.770197 == TX Byte 1 ==
6495 15:36:06.773457 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6496 15:36:06.776412 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6497 15:36:06.776500
6498 15:36:06.779739 [DATLAT]
6499 15:36:06.779837 Freq=400, CH0 RK1
6500 15:36:06.779950
6501 15:36:06.783091 DATLAT Default: 0xe
6502 15:36:06.783212 0, 0xFFFF, sum = 0
6503 15:36:06.786725 1, 0xFFFF, sum = 0
6504 15:36:06.786833 2, 0xFFFF, sum = 0
6505 15:36:06.789747 3, 0xFFFF, sum = 0
6506 15:36:06.789856 4, 0xFFFF, sum = 0
6507 15:36:06.793304 5, 0xFFFF, sum = 0
6508 15:36:06.793442 6, 0xFFFF, sum = 0
6509 15:36:06.796445 7, 0xFFFF, sum = 0
6510 15:36:06.796550 8, 0xFFFF, sum = 0
6511 15:36:06.799846 9, 0xFFFF, sum = 0
6512 15:36:06.802830 10, 0xFFFF, sum = 0
6513 15:36:06.802947 11, 0xFFFF, sum = 0
6514 15:36:06.806539 12, 0xFFFF, sum = 0
6515 15:36:06.806664 13, 0x0, sum = 1
6516 15:36:06.809413 14, 0x0, sum = 2
6517 15:36:06.809524 15, 0x0, sum = 3
6518 15:36:06.812673 16, 0x0, sum = 4
6519 15:36:06.812787 best_step = 14
6520 15:36:06.812889
6521 15:36:06.812978 ==
6522 15:36:06.816513 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 15:36:06.819993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 15:36:06.820099 ==
6525 15:36:06.822835 RX Vref Scan: 0
6526 15:36:06.822937
6527 15:36:06.826178 RX Vref 0 -> 0, step: 1
6528 15:36:06.826274
6529 15:36:06.826369 RX Delay -359 -> 252, step: 8
6530 15:36:06.834642 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6531 15:36:06.838135 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6532 15:36:06.841863 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6533 15:36:06.847869 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6534 15:36:06.851188 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6535 15:36:06.854808 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6536 15:36:06.857803 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6537 15:36:06.864238 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6538 15:36:06.867766 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6539 15:36:06.870956 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6540 15:36:06.874472 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6541 15:36:06.880768 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6542 15:36:06.883886 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6543 15:36:06.887193 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6544 15:36:06.893816 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6545 15:36:06.896873 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6546 15:36:06.896977 ==
6547 15:36:06.900398 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 15:36:06.903910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 15:36:06.904003 ==
6550 15:36:06.907542 DQS Delay:
6551 15:36:06.907648 DQS0 = 44, DQS1 = 60
6552 15:36:06.907740 DQM Delay:
6553 15:36:06.910345 DQM0 = 9, DQM1 = 16
6554 15:36:06.910443 DQ Delay:
6555 15:36:06.913445 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6556 15:36:06.916642 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6557 15:36:06.920182 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6558 15:36:06.923453 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6559 15:36:06.923551
6560 15:36:06.923640
6561 15:36:06.933222 [DQSOSCAuto] RK1, (LSB)MR18= 0x8a84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6562 15:36:06.933329 CH0 RK1: MR19=C0C, MR18=8A84
6563 15:36:06.939730 CH0_RK1: MR19=0xC0C, MR18=0x8A84, DQSOSC=392, MR23=63, INC=384, DEC=256
6564 15:36:06.943071 [RxdqsGatingPostProcess] freq 400
6565 15:36:06.949571 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6566 15:36:06.953072 best DQS0 dly(2T, 0.5T) = (0, 10)
6567 15:36:06.956318 best DQS1 dly(2T, 0.5T) = (0, 10)
6568 15:36:06.959753 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6569 15:36:06.962587 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6570 15:36:06.966630 best DQS0 dly(2T, 0.5T) = (0, 10)
6571 15:36:06.969426 best DQS1 dly(2T, 0.5T) = (0, 10)
6572 15:36:06.972761 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6573 15:36:06.976130 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6574 15:36:06.979622 Pre-setting of DQS Precalculation
6575 15:36:06.982292 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6576 15:36:06.982365 ==
6577 15:36:06.985831 Dram Type= 6, Freq= 0, CH_1, rank 0
6578 15:36:06.989246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 15:36:06.989347 ==
6580 15:36:06.995646 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6581 15:36:07.002645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6582 15:36:07.005921 [CA 0] Center 36 (8~64) winsize 57
6583 15:36:07.008800 [CA 1] Center 36 (8~64) winsize 57
6584 15:36:07.012033 [CA 2] Center 36 (8~64) winsize 57
6585 15:36:07.015147 [CA 3] Center 36 (8~64) winsize 57
6586 15:36:07.018465 [CA 4] Center 36 (8~64) winsize 57
6587 15:36:07.022374 [CA 5] Center 36 (8~64) winsize 57
6588 15:36:07.022484
6589 15:36:07.025020 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6590 15:36:07.025093
6591 15:36:07.028622 [CATrainingPosCal] consider 1 rank data
6592 15:36:07.031776 u2DelayCellTimex100 = 270/100 ps
6593 15:36:07.035130 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 15:36:07.038698 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 15:36:07.041870 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 15:36:07.045034 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 15:36:07.048054 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 15:36:07.051470 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 15:36:07.051571
6600 15:36:07.058560 CA PerBit enable=1, Macro0, CA PI delay=36
6601 15:36:07.058662
6602 15:36:07.058759 [CBTSetCACLKResult] CA Dly = 36
6603 15:36:07.061489 CS Dly: 1 (0~32)
6604 15:36:07.061639 ==
6605 15:36:07.064770 Dram Type= 6, Freq= 0, CH_1, rank 1
6606 15:36:07.068224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 15:36:07.068301 ==
6608 15:36:07.074526 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6609 15:36:07.081648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6610 15:36:07.084553 [CA 0] Center 36 (8~64) winsize 57
6611 15:36:07.087998 [CA 1] Center 36 (8~64) winsize 57
6612 15:36:07.091413 [CA 2] Center 36 (8~64) winsize 57
6613 15:36:07.094377 [CA 3] Center 36 (8~64) winsize 57
6614 15:36:07.097687 [CA 4] Center 36 (8~64) winsize 57
6615 15:36:07.100873 [CA 5] Center 36 (8~64) winsize 57
6616 15:36:07.100986
6617 15:36:07.104276 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6618 15:36:07.104393
6619 15:36:07.107689 [CATrainingPosCal] consider 2 rank data
6620 15:36:07.110656 u2DelayCellTimex100 = 270/100 ps
6621 15:36:07.114314 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 15:36:07.117022 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 15:36:07.120803 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 15:36:07.123674 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 15:36:07.127437 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 15:36:07.130811 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 15:36:07.130922
6628 15:36:07.137050 CA PerBit enable=1, Macro0, CA PI delay=36
6629 15:36:07.137152
6630 15:36:07.137243 [CBTSetCACLKResult] CA Dly = 36
6631 15:36:07.140551 CS Dly: 1 (0~32)
6632 15:36:07.140648
6633 15:36:07.143811 ----->DramcWriteLeveling(PI) begin...
6634 15:36:07.143923 ==
6635 15:36:07.146796 Dram Type= 6, Freq= 0, CH_1, rank 0
6636 15:36:07.149932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 15:36:07.150038 ==
6638 15:36:07.153435 Write leveling (Byte 0): 40 => 8
6639 15:36:07.157061 Write leveling (Byte 1): 40 => 8
6640 15:36:07.160386 DramcWriteLeveling(PI) end<-----
6641 15:36:07.160469
6642 15:36:07.160537 ==
6643 15:36:07.163541 Dram Type= 6, Freq= 0, CH_1, rank 0
6644 15:36:07.166923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 15:36:07.170175 ==
6646 15:36:07.170266 [Gating] SW mode calibration
6647 15:36:07.180045 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6648 15:36:07.182968 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6649 15:36:07.186273 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6650 15:36:07.193147 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6651 15:36:07.196102 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6652 15:36:07.199598 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 15:36:07.206165 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 15:36:07.209536 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 15:36:07.212570 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 15:36:07.219504 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 15:36:07.222892 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 15:36:07.226144 Total UI for P1: 0, mck2ui 16
6659 15:36:07.229027 best dqsien dly found for B0: ( 0, 14, 24)
6660 15:36:07.232709 Total UI for P1: 0, mck2ui 16
6661 15:36:07.235890 best dqsien dly found for B1: ( 0, 14, 24)
6662 15:36:07.239277 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6663 15:36:07.242813 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6664 15:36:07.242911
6665 15:36:07.245676 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6666 15:36:07.252342 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6667 15:36:07.252443 [Gating] SW calibration Done
6668 15:36:07.252533 ==
6669 15:36:07.255556 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 15:36:07.262155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 15:36:07.262274 ==
6672 15:36:07.262368 RX Vref Scan: 0
6673 15:36:07.262456
6674 15:36:07.265591 RX Vref 0 -> 0, step: 1
6675 15:36:07.265669
6676 15:36:07.268667 RX Delay -410 -> 252, step: 16
6677 15:36:07.271883 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6678 15:36:07.275311 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6679 15:36:07.281925 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6680 15:36:07.285277 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6681 15:36:07.288670 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6682 15:36:07.292244 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6683 15:36:07.298752 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6684 15:36:07.301609 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6685 15:36:07.305185 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6686 15:36:07.308303 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6687 15:36:07.549160 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6688 15:36:07.549571 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6689 15:36:07.549686 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6690 15:36:07.549789 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6691 15:36:07.549890 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6692 15:36:07.549986 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6693 15:36:07.550051 ==
6694 15:36:07.550127 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 15:36:07.550210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 15:36:07.550303 ==
6697 15:36:07.550394 DQS Delay:
6698 15:36:07.550486 DQS0 = 35, DQS1 = 51
6699 15:36:07.550577 DQM Delay:
6700 15:36:07.550669 DQM0 = 6, DQM1 = 13
6701 15:36:07.550761 DQ Delay:
6702 15:36:07.550853 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6703 15:36:07.550946 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6704 15:36:07.551039 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6705 15:36:07.551130 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6706 15:36:07.551221
6707 15:36:07.551313
6708 15:36:07.551403 ==
6709 15:36:07.551495 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 15:36:07.551588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 15:36:07.551680 ==
6712 15:36:07.551771
6713 15:36:07.551861
6714 15:36:07.551983 TX Vref Scan disable
6715 15:36:07.552078 == TX Byte 0 ==
6716 15:36:07.552179 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6717 15:36:07.552283 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6718 15:36:07.552387 == TX Byte 1 ==
6719 15:36:07.552478 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6720 15:36:07.552567 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6721 15:36:07.552652 ==
6722 15:36:07.552737 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 15:36:07.552831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 15:36:07.552915 ==
6725 15:36:07.552997
6726 15:36:07.553079
6727 15:36:07.553160 TX Vref Scan disable
6728 15:36:07.553242 == TX Byte 0 ==
6729 15:36:07.553325 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 15:36:07.553408 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 15:36:07.553490 == TX Byte 1 ==
6732 15:36:07.553572 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 15:36:07.553655 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 15:36:07.553736
6735 15:36:07.553817 [DATLAT]
6736 15:36:07.553899 Freq=400, CH1 RK0
6737 15:36:07.553981
6738 15:36:07.554062 DATLAT Default: 0xf
6739 15:36:07.554144 0, 0xFFFF, sum = 0
6740 15:36:07.554228 1, 0xFFFF, sum = 0
6741 15:36:07.554312 2, 0xFFFF, sum = 0
6742 15:36:07.554395 3, 0xFFFF, sum = 0
6743 15:36:07.554479 4, 0xFFFF, sum = 0
6744 15:36:07.554562 5, 0xFFFF, sum = 0
6745 15:36:07.554646 6, 0xFFFF, sum = 0
6746 15:36:07.554729 7, 0xFFFF, sum = 0
6747 15:36:07.554813 8, 0xFFFF, sum = 0
6748 15:36:07.554902 9, 0xFFFF, sum = 0
6749 15:36:07.554991 10, 0xFFFF, sum = 0
6750 15:36:07.555081 11, 0xFFFF, sum = 0
6751 15:36:07.555170 12, 0xFFFF, sum = 0
6752 15:36:07.555233 13, 0x0, sum = 1
6753 15:36:07.555288 14, 0x0, sum = 2
6754 15:36:07.555342 15, 0x0, sum = 3
6755 15:36:07.555395 16, 0x0, sum = 4
6756 15:36:07.555448 best_step = 14
6757 15:36:07.555500
6758 15:36:07.555565 ==
6759 15:36:07.555637 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 15:36:07.555701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 15:36:07.555755 ==
6762 15:36:07.555808 RX Vref Scan: 1
6763 15:36:07.555861
6764 15:36:07.555935 RX Vref 0 -> 0, step: 1
6765 15:36:07.555999
6766 15:36:07.556052 RX Delay -343 -> 252, step: 8
6767 15:36:07.556105
6768 15:36:07.556167 Set Vref, RX VrefLevel [Byte0]: 51
6769 15:36:07.556220 [Byte1]: 50
6770 15:36:07.556273
6771 15:36:07.556325 Final RX Vref Byte 0 = 51 to rank0
6772 15:36:07.556378 Final RX Vref Byte 1 = 50 to rank0
6773 15:36:07.556430 Final RX Vref Byte 0 = 51 to rank1
6774 15:36:07.556483 Final RX Vref Byte 1 = 50 to rank1==
6775 15:36:07.556535 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 15:36:07.556588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 15:36:07.556641 ==
6778 15:36:07.556693 DQS Delay:
6779 15:36:07.556744 DQS0 = 44, DQS1 = 56
6780 15:36:07.556796 DQM Delay:
6781 15:36:07.556849 DQM0 = 9, DQM1 = 13
6782 15:36:07.556901 DQ Delay:
6783 15:36:07.556953 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6784 15:36:07.557005 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6785 15:36:07.557057 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6786 15:36:07.557109 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6787 15:36:07.557161
6788 15:36:07.557213
6789 15:36:07.557265 [DQSOSCAuto] RK0, (LSB)MR18= 0x678e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 396 ps
6790 15:36:07.557319 CH1 RK0: MR19=C0C, MR18=678E
6791 15:36:07.557371 CH1_RK0: MR19=0xC0C, MR18=0x678E, DQSOSC=392, MR23=63, INC=384, DEC=256
6792 15:36:07.557425 ==
6793 15:36:07.557485 Dram Type= 6, Freq= 0, CH_1, rank 1
6794 15:36:07.557539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 15:36:07.557592 ==
6796 15:36:07.557645 [Gating] SW mode calibration
6797 15:36:07.557714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6798 15:36:07.561695 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6799 15:36:07.565270 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6800 15:36:07.568381 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6801 15:36:07.575037 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6802 15:36:07.578441 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6803 15:36:07.581617 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 15:36:07.588257 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 15:36:07.591355 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6806 15:36:07.594771 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 15:36:07.601287 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 15:36:07.604525 Total UI for P1: 0, mck2ui 16
6809 15:36:07.608050 best dqsien dly found for B0: ( 0, 14, 24)
6810 15:36:07.611564 Total UI for P1: 0, mck2ui 16
6811 15:36:07.614766 best dqsien dly found for B1: ( 0, 14, 24)
6812 15:36:07.618216 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6813 15:36:07.621341 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6814 15:36:07.621424
6815 15:36:07.624592 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6816 15:36:07.627930 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6817 15:36:07.631398 [Gating] SW calibration Done
6818 15:36:07.631482 ==
6819 15:36:07.634282 Dram Type= 6, Freq= 0, CH_1, rank 1
6820 15:36:07.637691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 15:36:07.637774 ==
6822 15:36:07.640716 RX Vref Scan: 0
6823 15:36:07.640799
6824 15:36:07.644060 RX Vref 0 -> 0, step: 1
6825 15:36:07.644143
6826 15:36:07.644207 RX Delay -410 -> 252, step: 16
6827 15:36:07.651451 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6828 15:36:07.654630 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6829 15:36:07.657384 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6830 15:36:07.664077 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6831 15:36:07.667504 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6832 15:36:07.671192 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6833 15:36:07.674000 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6834 15:36:07.680351 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6835 15:36:07.683787 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6836 15:36:07.687475 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6837 15:36:07.690902 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6838 15:36:07.697212 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6839 15:36:07.700237 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6840 15:36:07.703708 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6841 15:36:07.707157 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6842 15:36:07.714383 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6843 15:36:07.714460 ==
6844 15:36:07.716614 Dram Type= 6, Freq= 0, CH_1, rank 1
6845 15:36:07.720806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 15:36:07.720928 ==
6847 15:36:07.721043 DQS Delay:
6848 15:36:07.723721 DQS0 = 43, DQS1 = 51
6849 15:36:07.723817 DQM Delay:
6850 15:36:07.726775 DQM0 = 9, DQM1 = 13
6851 15:36:07.726917 DQ Delay:
6852 15:36:07.729910 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6853 15:36:07.733212 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6854 15:36:07.736824 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6855 15:36:07.739652 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6856 15:36:07.739748
6857 15:36:07.739835
6858 15:36:07.739968 ==
6859 15:36:07.743279 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 15:36:07.746432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 15:36:07.746535 ==
6862 15:36:07.746623
6863 15:36:07.749919
6864 15:36:07.749999 TX Vref Scan disable
6865 15:36:07.753032 == TX Byte 0 ==
6866 15:36:07.756388 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6867 15:36:07.760244 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6868 15:36:07.762909 == TX Byte 1 ==
6869 15:36:07.766347 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6870 15:36:07.769750 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6871 15:36:07.769831 ==
6872 15:36:07.772819 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 15:36:07.776431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 15:36:07.779915 ==
6875 15:36:07.780009
6876 15:36:07.780072
6877 15:36:07.780132 TX Vref Scan disable
6878 15:36:07.782591 == TX Byte 0 ==
6879 15:36:07.785972 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6880 15:36:07.789721 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6881 15:36:07.792525 == TX Byte 1 ==
6882 15:36:07.796095 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6883 15:36:07.799151 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6884 15:36:07.799234
6885 15:36:07.802698 [DATLAT]
6886 15:36:07.802806 Freq=400, CH1 RK1
6887 15:36:07.802900
6888 15:36:07.805616 DATLAT Default: 0xe
6889 15:36:07.805698 0, 0xFFFF, sum = 0
6890 15:36:07.809042 1, 0xFFFF, sum = 0
6891 15:36:07.809126 2, 0xFFFF, sum = 0
6892 15:36:07.812355 3, 0xFFFF, sum = 0
6893 15:36:07.812439 4, 0xFFFF, sum = 0
6894 15:36:07.815758 5, 0xFFFF, sum = 0
6895 15:36:07.815841 6, 0xFFFF, sum = 0
6896 15:36:07.819244 7, 0xFFFF, sum = 0
6897 15:36:07.819328 8, 0xFFFF, sum = 0
6898 15:36:07.822620 9, 0xFFFF, sum = 0
6899 15:36:07.822704 10, 0xFFFF, sum = 0
6900 15:36:07.825710 11, 0xFFFF, sum = 0
6901 15:36:07.825797 12, 0xFFFF, sum = 0
6902 15:36:07.829277 13, 0x0, sum = 1
6903 15:36:07.829354 14, 0x0, sum = 2
6904 15:36:07.832439 15, 0x0, sum = 3
6905 15:36:07.832567 16, 0x0, sum = 4
6906 15:36:07.835273 best_step = 14
6907 15:36:07.835346
6908 15:36:07.835408 ==
6909 15:36:07.838933 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 15:36:07.842166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 15:36:07.842246 ==
6912 15:36:07.845221 RX Vref Scan: 0
6913 15:36:07.845293
6914 15:36:07.845353 RX Vref 0 -> 0, step: 1
6915 15:36:07.845411
6916 15:36:07.848862 RX Delay -343 -> 252, step: 8
6917 15:36:07.857227 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6918 15:36:07.860120 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6919 15:36:07.863451 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6920 15:36:07.870066 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6921 15:36:07.873120 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6922 15:36:07.876363 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6923 15:36:07.879608 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6924 15:36:07.886549 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6925 15:36:07.889789 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6926 15:36:07.893123 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6927 15:36:07.896540 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6928 15:36:07.902746 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6929 15:36:07.905889 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6930 15:36:07.909435 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6931 15:36:07.915718 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6932 15:36:07.918901 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6933 15:36:07.919001 ==
6934 15:36:07.922648 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 15:36:07.925866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 15:36:07.925982 ==
6937 15:36:07.928735 DQS Delay:
6938 15:36:07.928843 DQS0 = 48, DQS1 = 56
6939 15:36:07.928937 DQM Delay:
6940 15:36:07.932198 DQM0 = 11, DQM1 = 14
6941 15:36:07.932311 DQ Delay:
6942 15:36:07.935748 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6943 15:36:07.938646 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6944 15:36:07.942000 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6945 15:36:07.945778 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6946 15:36:07.945898
6947 15:36:07.945993
6948 15:36:07.955145 [DQSOSCAuto] RK1, (LSB)MR18= 0x79b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6949 15:36:07.955253 CH1 RK1: MR19=C0C, MR18=79B0
6950 15:36:07.961678 CH1_RK1: MR19=0xC0C, MR18=0x79B0, DQSOSC=387, MR23=63, INC=394, DEC=262
6951 15:36:07.965054 [RxdqsGatingPostProcess] freq 400
6952 15:36:07.971527 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6953 15:36:07.974892 best DQS0 dly(2T, 0.5T) = (0, 10)
6954 15:36:07.978422 best DQS1 dly(2T, 0.5T) = (0, 10)
6955 15:36:07.981303 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6956 15:36:07.984652 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6957 15:36:07.988090 best DQS0 dly(2T, 0.5T) = (0, 10)
6958 15:36:07.991466 best DQS1 dly(2T, 0.5T) = (0, 10)
6959 15:36:07.994594 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6960 15:36:07.998021 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6961 15:36:08.001369 Pre-setting of DQS Precalculation
6962 15:36:08.004503 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6963 15:36:08.010788 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6964 15:36:08.017917 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6965 15:36:08.021342
6966 15:36:08.021475
6967 15:36:08.021571 [Calibration Summary] 800 Mbps
6968 15:36:08.023882 CH 0, Rank 0
6969 15:36:08.023974 SW Impedance : PASS
6970 15:36:08.027476 DUTY Scan : NO K
6971 15:36:08.030926 ZQ Calibration : PASS
6972 15:36:08.031045 Jitter Meter : NO K
6973 15:36:08.034371 CBT Training : PASS
6974 15:36:08.037254 Write leveling : PASS
6975 15:36:08.037371 RX DQS gating : PASS
6976 15:36:08.040750 RX DQ/DQS(RDDQC) : PASS
6977 15:36:08.043662 TX DQ/DQS : PASS
6978 15:36:08.043762 RX DATLAT : PASS
6979 15:36:08.047538 RX DQ/DQS(Engine): PASS
6980 15:36:08.050516 TX OE : NO K
6981 15:36:08.050599 All Pass.
6982 15:36:08.050664
6983 15:36:08.050725 CH 0, Rank 1
6984 15:36:08.053765 SW Impedance : PASS
6985 15:36:08.057369 DUTY Scan : NO K
6986 15:36:08.057451 ZQ Calibration : PASS
6987 15:36:08.060372 Jitter Meter : NO K
6988 15:36:08.063638 CBT Training : PASS
6989 15:36:08.063749 Write leveling : NO K
6990 15:36:08.067096 RX DQS gating : PASS
6991 15:36:08.070428 RX DQ/DQS(RDDQC) : PASS
6992 15:36:08.070513 TX DQ/DQS : PASS
6993 15:36:08.073901 RX DATLAT : PASS
6994 15:36:08.076955 RX DQ/DQS(Engine): PASS
6995 15:36:08.077041 TX OE : NO K
6996 15:36:08.077114 All Pass.
6997 15:36:08.080472
6998 15:36:08.080551 CH 1, Rank 0
6999 15:36:08.083771 SW Impedance : PASS
7000 15:36:08.083886 DUTY Scan : NO K
7001 15:36:08.086812 ZQ Calibration : PASS
7002 15:36:08.086890 Jitter Meter : NO K
7003 15:36:08.090213 CBT Training : PASS
7004 15:36:08.093176 Write leveling : PASS
7005 15:36:08.093258 RX DQS gating : PASS
7006 15:36:08.096559 RX DQ/DQS(RDDQC) : PASS
7007 15:36:08.099888 TX DQ/DQS : PASS
7008 15:36:08.099992 RX DATLAT : PASS
7009 15:36:08.103384 RX DQ/DQS(Engine): PASS
7010 15:36:08.106533 TX OE : NO K
7011 15:36:08.106615 All Pass.
7012 15:36:08.106700
7013 15:36:08.106816 CH 1, Rank 1
7014 15:36:08.109912 SW Impedance : PASS
7015 15:36:08.113232 DUTY Scan : NO K
7016 15:36:08.113316 ZQ Calibration : PASS
7017 15:36:08.116541 Jitter Meter : NO K
7018 15:36:08.119586 CBT Training : PASS
7019 15:36:08.119675 Write leveling : NO K
7020 15:36:08.123408 RX DQS gating : PASS
7021 15:36:08.126842 RX DQ/DQS(RDDQC) : PASS
7022 15:36:08.126931 TX DQ/DQS : PASS
7023 15:36:08.129710 RX DATLAT : PASS
7024 15:36:08.133435 RX DQ/DQS(Engine): PASS
7025 15:36:08.133524 TX OE : NO K
7026 15:36:08.136176 All Pass.
7027 15:36:08.136257
7028 15:36:08.136348 DramC Write-DBI off
7029 15:36:08.139722 PER_BANK_REFRESH: Hybrid Mode
7030 15:36:08.139809 TX_TRACKING: ON
7031 15:36:08.149655 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7032 15:36:08.152730 [FAST_K] Save calibration result to emmc
7033 15:36:08.156476 dramc_set_vcore_voltage set vcore to 725000
7034 15:36:08.159068 Read voltage for 1600, 0
7035 15:36:08.159158 Vio18 = 0
7036 15:36:08.162985 Vcore = 725000
7037 15:36:08.163105 Vdram = 0
7038 15:36:08.163202 Vddq = 0
7039 15:36:08.166118 Vmddr = 0
7040 15:36:08.169496 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7041 15:36:08.175708 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7042 15:36:08.175808 MEM_TYPE=3, freq_sel=13
7043 15:36:08.179046 sv_algorithm_assistance_LP4_3733
7044 15:36:08.185826 ============ PULL DRAM RESETB DOWN ============
7045 15:36:08.189176 ========== PULL DRAM RESETB DOWN end =========
7046 15:36:08.192282 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7047 15:36:08.195848 ===================================
7048 15:36:08.198721 LPDDR4 DRAM CONFIGURATION
7049 15:36:08.202761 ===================================
7050 15:36:08.205616 EX_ROW_EN[0] = 0x0
7051 15:36:08.205726 EX_ROW_EN[1] = 0x0
7052 15:36:08.208938 LP4Y_EN = 0x0
7053 15:36:08.209047 WORK_FSP = 0x1
7054 15:36:08.212304 WL = 0x5
7055 15:36:08.212387 RL = 0x5
7056 15:36:08.215675 BL = 0x2
7057 15:36:08.215797 RPST = 0x0
7058 15:36:08.218809 RD_PRE = 0x0
7059 15:36:08.218885 WR_PRE = 0x1
7060 15:36:08.222158 WR_PST = 0x1
7061 15:36:08.222236 DBI_WR = 0x0
7062 15:36:08.225467 DBI_RD = 0x0
7063 15:36:08.225551 OTF = 0x1
7064 15:36:08.228886 ===================================
7065 15:36:08.231670 ===================================
7066 15:36:08.235099 ANA top config
7067 15:36:08.238735 ===================================
7068 15:36:08.241737 DLL_ASYNC_EN = 0
7069 15:36:08.241816 ALL_SLAVE_EN = 0
7070 15:36:08.245301 NEW_RANK_MODE = 1
7071 15:36:08.248651 DLL_IDLE_MODE = 1
7072 15:36:08.251528 LP45_APHY_COMB_EN = 1
7073 15:36:08.255019 TX_ODT_DIS = 0
7074 15:36:08.255102 NEW_8X_MODE = 1
7075 15:36:08.258067 ===================================
7076 15:36:08.261312 ===================================
7077 15:36:08.264902 data_rate = 3200
7078 15:36:08.268190 CKR = 1
7079 15:36:08.271454 DQ_P2S_RATIO = 8
7080 15:36:08.274833 ===================================
7081 15:36:08.277863 CA_P2S_RATIO = 8
7082 15:36:08.281253 DQ_CA_OPEN = 0
7083 15:36:08.281339 DQ_SEMI_OPEN = 0
7084 15:36:08.284524 CA_SEMI_OPEN = 0
7085 15:36:08.287651 CA_FULL_RATE = 0
7086 15:36:08.290958 DQ_CKDIV4_EN = 0
7087 15:36:08.294564 CA_CKDIV4_EN = 0
7088 15:36:08.298006 CA_PREDIV_EN = 0
7089 15:36:08.298089 PH8_DLY = 12
7090 15:36:08.300729 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7091 15:36:08.304578 DQ_AAMCK_DIV = 4
7092 15:36:08.307808 CA_AAMCK_DIV = 4
7093 15:36:08.310751 CA_ADMCK_DIV = 4
7094 15:36:08.314097 DQ_TRACK_CA_EN = 0
7095 15:36:08.317671 CA_PICK = 1600
7096 15:36:08.320656 CA_MCKIO = 1600
7097 15:36:08.320740 MCKIO_SEMI = 0
7098 15:36:08.324237 PLL_FREQ = 3068
7099 15:36:08.327497 DQ_UI_PI_RATIO = 32
7100 15:36:08.330694 CA_UI_PI_RATIO = 0
7101 15:36:08.334175 ===================================
7102 15:36:08.337481 ===================================
7103 15:36:08.340551 memory_type:LPDDR4
7104 15:36:08.340633 GP_NUM : 10
7105 15:36:08.343935 SRAM_EN : 1
7106 15:36:08.346897 MD32_EN : 0
7107 15:36:08.350546 ===================================
7108 15:36:08.350631 [ANA_INIT] >>>>>>>>>>>>>>
7109 15:36:08.353625 <<<<<< [CONFIGURE PHASE]: ANA_TX
7110 15:36:08.356625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7111 15:36:08.359878 ===================================
7112 15:36:08.363356 data_rate = 3200,PCW = 0X7600
7113 15:36:08.366711 ===================================
7114 15:36:08.369782 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7115 15:36:08.376625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7116 15:36:08.379968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7117 15:36:08.386256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7118 15:36:08.390072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7119 15:36:08.393429 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7120 15:36:08.396104 [ANA_INIT] flow start
7121 15:36:08.396180 [ANA_INIT] PLL >>>>>>>>
7122 15:36:08.399468 [ANA_INIT] PLL <<<<<<<<
7123 15:36:08.402984 [ANA_INIT] MIDPI >>>>>>>>
7124 15:36:08.403061 [ANA_INIT] MIDPI <<<<<<<<
7125 15:36:08.406144 [ANA_INIT] DLL >>>>>>>>
7126 15:36:08.409717 [ANA_INIT] DLL <<<<<<<<
7127 15:36:08.409793 [ANA_INIT] flow end
7128 15:36:08.416329 ============ LP4 DIFF to SE enter ============
7129 15:36:08.419204 ============ LP4 DIFF to SE exit ============
7130 15:36:08.422619 [ANA_INIT] <<<<<<<<<<<<<
7131 15:36:08.426037 [Flow] Enable top DCM control >>>>>
7132 15:36:08.429798 [Flow] Enable top DCM control <<<<<
7133 15:36:08.429874 Enable DLL master slave shuffle
7134 15:36:08.435743 ==============================================================
7135 15:36:08.439246 Gating Mode config
7136 15:36:08.442277 ==============================================================
7137 15:36:08.445617 Config description:
7138 15:36:08.455414 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7139 15:36:08.462223 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7140 15:36:08.465633 SELPH_MODE 0: By rank 1: By Phase
7141 15:36:08.472436 ==============================================================
7142 15:36:08.475116 GAT_TRACK_EN = 1
7143 15:36:08.478725 RX_GATING_MODE = 2
7144 15:36:08.481812 RX_GATING_TRACK_MODE = 2
7145 15:36:08.485331 SELPH_MODE = 1
7146 15:36:08.488230 PICG_EARLY_EN = 1
7147 15:36:08.491681 VALID_LAT_VALUE = 1
7148 15:36:08.495400 ==============================================================
7149 15:36:08.498142 Enter into Gating configuration >>>>
7150 15:36:08.501613 Exit from Gating configuration <<<<
7151 15:36:08.504595 Enter into DVFS_PRE_config >>>>>
7152 15:36:08.517907 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7153 15:36:08.517996 Exit from DVFS_PRE_config <<<<<
7154 15:36:08.521455 Enter into PICG configuration >>>>
7155 15:36:08.524857 Exit from PICG configuration <<<<
7156 15:36:08.527948 [RX_INPUT] configuration >>>>>
7157 15:36:08.531234 [RX_INPUT] configuration <<<<<
7158 15:36:08.538048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7159 15:36:08.541278 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7160 15:36:08.547786 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7161 15:36:08.554438 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7162 15:36:08.560560 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7163 15:36:08.567020 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7164 15:36:08.570949 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7165 15:36:08.574154 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7166 15:36:08.580201 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7167 15:36:08.584385 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7168 15:36:08.586776 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7169 15:36:08.590358 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7170 15:36:08.594111 ===================================
7171 15:36:08.596624 LPDDR4 DRAM CONFIGURATION
7172 15:36:08.599968 ===================================
7173 15:36:08.603305 EX_ROW_EN[0] = 0x0
7174 15:36:08.603412 EX_ROW_EN[1] = 0x0
7175 15:36:08.607132 LP4Y_EN = 0x0
7176 15:36:08.607248 WORK_FSP = 0x1
7177 15:36:08.609979 WL = 0x5
7178 15:36:08.610052 RL = 0x5
7179 15:36:08.613266 BL = 0x2
7180 15:36:08.613348 RPST = 0x0
7181 15:36:08.616753 RD_PRE = 0x0
7182 15:36:08.616831 WR_PRE = 0x1
7183 15:36:08.620263 WR_PST = 0x1
7184 15:36:08.623321 DBI_WR = 0x0
7185 15:36:08.623401 DBI_RD = 0x0
7186 15:36:08.626748 OTF = 0x1
7187 15:36:08.630022 ===================================
7188 15:36:08.632977 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7189 15:36:08.636436 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7190 15:36:08.640307 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7191 15:36:08.643308 ===================================
7192 15:36:08.646766 LPDDR4 DRAM CONFIGURATION
7193 15:36:08.650002 ===================================
7194 15:36:08.653338 EX_ROW_EN[0] = 0x10
7195 15:36:08.653413 EX_ROW_EN[1] = 0x0
7196 15:36:08.656632 LP4Y_EN = 0x0
7197 15:36:08.656714 WORK_FSP = 0x1
7198 15:36:08.659767 WL = 0x5
7199 15:36:08.659846 RL = 0x5
7200 15:36:08.663048 BL = 0x2
7201 15:36:08.663170 RPST = 0x0
7202 15:36:08.666302 RD_PRE = 0x0
7203 15:36:08.666383 WR_PRE = 0x1
7204 15:36:08.670012 WR_PST = 0x1
7205 15:36:08.670085 DBI_WR = 0x0
7206 15:36:08.673005 DBI_RD = 0x0
7207 15:36:08.675968 OTF = 0x1
7208 15:36:08.679393 ===================================
7209 15:36:08.682709 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7210 15:36:08.682784 ==
7211 15:36:08.686282 Dram Type= 6, Freq= 0, CH_0, rank 0
7212 15:36:08.692867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7213 15:36:08.692971 ==
7214 15:36:08.695827 [Duty_Offset_Calibration]
7215 15:36:08.695967 B0:2 B1:0 CA:4
7216 15:36:08.696041
7217 15:36:08.699323 [DutyScan_Calibration_Flow] k_type=0
7218 15:36:08.708522
7219 15:36:08.708604 ==CLK 0==
7220 15:36:08.712016 Final CLK duty delay cell = -4
7221 15:36:08.714771 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7222 15:36:08.718175 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7223 15:36:08.721358 [-4] AVG Duty = 4922%(X100)
7224 15:36:08.721433
7225 15:36:08.724459 CH0 CLK Duty spec in!! Max-Min= 218%
7226 15:36:08.727748 [DutyScan_Calibration_Flow] ====Done====
7227 15:36:08.727851
7228 15:36:08.731103 [DutyScan_Calibration_Flow] k_type=1
7229 15:36:08.748525
7230 15:36:08.748605 ==DQS 0 ==
7231 15:36:08.751678 Final DQS duty delay cell = 0
7232 15:36:08.755021 [0] MAX Duty = 5218%(X100), DQS PI = 38
7233 15:36:08.758509 [0] MIN Duty = 5093%(X100), DQS PI = 12
7234 15:36:08.761734 [0] AVG Duty = 5155%(X100)
7235 15:36:08.761809
7236 15:36:08.761879 ==DQS 1 ==
7237 15:36:08.765209 Final DQS duty delay cell = 0
7238 15:36:08.768477 [0] MAX Duty = 5187%(X100), DQS PI = 0
7239 15:36:08.771402 [0] MIN Duty = 4969%(X100), DQS PI = 12
7240 15:36:08.774562 [0] AVG Duty = 5078%(X100)
7241 15:36:08.774650
7242 15:36:08.777780 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7243 15:36:08.777861
7244 15:36:08.781323 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7245 15:36:08.785216 [DutyScan_Calibration_Flow] ====Done====
7246 15:36:08.785305
7247 15:36:08.787662 [DutyScan_Calibration_Flow] k_type=3
7248 15:36:08.805578
7249 15:36:08.805673 ==DQM 0 ==
7250 15:36:08.809184 Final DQM duty delay cell = 0
7251 15:36:08.812145 [0] MAX Duty = 5124%(X100), DQS PI = 20
7252 15:36:08.815407 [0] MIN Duty = 4875%(X100), DQS PI = 56
7253 15:36:08.818918 [0] AVG Duty = 4999%(X100)
7254 15:36:08.819006
7255 15:36:08.819089 ==DQM 1 ==
7256 15:36:08.822201 Final DQM duty delay cell = 0
7257 15:36:08.825569 [0] MAX Duty = 5000%(X100), DQS PI = 4
7258 15:36:08.828475 [0] MIN Duty = 4844%(X100), DQS PI = 16
7259 15:36:08.831685 [0] AVG Duty = 4922%(X100)
7260 15:36:08.831762
7261 15:36:08.834909 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7262 15:36:08.834986
7263 15:36:08.838705 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7264 15:36:08.841480 [DutyScan_Calibration_Flow] ====Done====
7265 15:36:08.841589
7266 15:36:08.844689 [DutyScan_Calibration_Flow] k_type=2
7267 15:36:08.862505
7268 15:36:08.862585 ==DQ 0 ==
7269 15:36:08.866022 Final DQ duty delay cell = 0
7270 15:36:08.869265 [0] MAX Duty = 5124%(X100), DQS PI = 20
7271 15:36:08.872739 [0] MIN Duty = 4938%(X100), DQS PI = 12
7272 15:36:08.875811 [0] AVG Duty = 5031%(X100)
7273 15:36:08.875955
7274 15:36:08.876021 ==DQ 1 ==
7275 15:36:08.879453 Final DQ duty delay cell = 0
7276 15:36:08.882722 [0] MAX Duty = 5187%(X100), DQS PI = 2
7277 15:36:08.885869 [0] MIN Duty = 4938%(X100), DQS PI = 12
7278 15:36:08.885944 [0] AVG Duty = 5062%(X100)
7279 15:36:08.888840
7280 15:36:08.892316 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7281 15:36:08.892394
7282 15:36:08.895866 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7283 15:36:08.898812 [DutyScan_Calibration_Flow] ====Done====
7284 15:36:08.898896 ==
7285 15:36:08.902115 Dram Type= 6, Freq= 0, CH_1, rank 0
7286 15:36:08.905683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7287 15:36:08.905763 ==
7288 15:36:08.909099 [Duty_Offset_Calibration]
7289 15:36:08.909176 B0:0 B1:-1 CA:3
7290 15:36:08.909275
7291 15:36:08.912390 [DutyScan_Calibration_Flow] k_type=0
7292 15:36:08.922296
7293 15:36:08.922402 ==CLK 0==
7294 15:36:08.925576 Final CLK duty delay cell = -4
7295 15:36:08.928498 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7296 15:36:08.932495 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7297 15:36:08.935598 [-4] AVG Duty = 4937%(X100)
7298 15:36:08.935706
7299 15:36:08.938628 CH1 CLK Duty spec in!! Max-Min= 125%
7300 15:36:08.941895 [DutyScan_Calibration_Flow] ====Done====
7301 15:36:08.941970
7302 15:36:08.945018 [DutyScan_Calibration_Flow] k_type=1
7303 15:36:08.961265
7304 15:36:08.961372 ==DQS 0 ==
7305 15:36:08.964491 Final DQS duty delay cell = 0
7306 15:36:08.968177 [0] MAX Duty = 5250%(X100), DQS PI = 28
7307 15:36:08.971330 [0] MIN Duty = 4938%(X100), DQS PI = 56
7308 15:36:08.974217 [0] AVG Duty = 5094%(X100)
7309 15:36:08.974324
7310 15:36:08.974395 ==DQS 1 ==
7311 15:36:08.977845 Final DQS duty delay cell = -4
7312 15:36:08.980987 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7313 15:36:08.984396 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7314 15:36:08.987784 [-4] AVG Duty = 4922%(X100)
7315 15:36:08.987881
7316 15:36:08.991198 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7317 15:36:08.991272
7318 15:36:08.994453 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7319 15:36:08.997530 [DutyScan_Calibration_Flow] ====Done====
7320 15:36:08.997621
7321 15:36:09.000902 [DutyScan_Calibration_Flow] k_type=3
7322 15:36:09.018513
7323 15:36:09.018600 ==DQM 0 ==
7324 15:36:09.021624 Final DQM duty delay cell = 0
7325 15:36:09.025188 [0] MAX Duty = 5062%(X100), DQS PI = 30
7326 15:36:09.028717 [0] MIN Duty = 4782%(X100), DQS PI = 38
7327 15:36:09.031898 [0] AVG Duty = 4922%(X100)
7328 15:36:09.031983
7329 15:36:09.032052 ==DQM 1 ==
7330 15:36:09.035335 Final DQM duty delay cell = 0
7331 15:36:09.038732 [0] MAX Duty = 5000%(X100), DQS PI = 30
7332 15:36:09.041672 [0] MIN Duty = 4782%(X100), DQS PI = 0
7333 15:36:09.045085 [0] AVG Duty = 4891%(X100)
7334 15:36:09.045166
7335 15:36:09.048428 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7336 15:36:09.048512
7337 15:36:09.051305 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7338 15:36:09.054448 [DutyScan_Calibration_Flow] ====Done====
7339 15:36:09.054525
7340 15:36:09.058257 [DutyScan_Calibration_Flow] k_type=2
7341 15:36:09.074892
7342 15:36:09.074976 ==DQ 0 ==
7343 15:36:09.078166 Final DQ duty delay cell = -4
7344 15:36:09.081258 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7345 15:36:09.084317 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7346 15:36:09.087811 [-4] AVG Duty = 4891%(X100)
7347 15:36:09.087924
7348 15:36:09.088023 ==DQ 1 ==
7349 15:36:09.090828 Final DQ duty delay cell = 0
7350 15:36:09.094337 [0] MAX Duty = 5031%(X100), DQS PI = 30
7351 15:36:09.097743 [0] MIN Duty = 4875%(X100), DQS PI = 56
7352 15:36:09.100859 [0] AVG Duty = 4953%(X100)
7353 15:36:09.100942
7354 15:36:09.104094 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7355 15:36:09.104176
7356 15:36:09.108115 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7357 15:36:09.110857 [DutyScan_Calibration_Flow] ====Done====
7358 15:36:09.113953 nWR fixed to 30
7359 15:36:09.117266 [ModeRegInit_LP4] CH0 RK0
7360 15:36:09.117340 [ModeRegInit_LP4] CH0 RK1
7361 15:36:09.120409 [ModeRegInit_LP4] CH1 RK0
7362 15:36:09.124205 [ModeRegInit_LP4] CH1 RK1
7363 15:36:09.124276 match AC timing 5
7364 15:36:09.130354 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7365 15:36:09.134014 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7366 15:36:09.137246 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7367 15:36:09.143493 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7368 15:36:09.146958 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7369 15:36:09.150490 [MiockJmeterHQA]
7370 15:36:09.150563
7371 15:36:09.153706 [DramcMiockJmeter] u1RxGatingPI = 0
7372 15:36:09.153778 0 : 4368, 4139
7373 15:36:09.153864 4 : 4252, 4026
7374 15:36:09.157016 8 : 4363, 4137
7375 15:36:09.157089 12 : 4252, 4027
7376 15:36:09.160392 16 : 4363, 4138
7377 15:36:09.160465 20 : 4253, 4026
7378 15:36:09.163507 24 : 4363, 4137
7379 15:36:09.163589 28 : 4253, 4027
7380 15:36:09.163653 32 : 4363, 4137
7381 15:36:09.166792 36 : 4363, 4138
7382 15:36:09.166868 40 : 4253, 4026
7383 15:36:09.170140 44 : 4252, 4027
7384 15:36:09.170221 48 : 4250, 4027
7385 15:36:09.173562 52 : 4250, 4026
7386 15:36:09.173645 56 : 4250, 4027
7387 15:36:09.176861 60 : 4250, 4027
7388 15:36:09.176938 64 : 4255, 4029
7389 15:36:09.177000 68 : 4255, 4029
7390 15:36:09.180044 72 : 4250, 4026
7391 15:36:09.180124 76 : 4252, 4029
7392 15:36:09.183464 80 : 4250, 4027
7393 15:36:09.183609 84 : 4363, 4137
7394 15:36:09.186589 88 : 4360, 4137
7395 15:36:09.186670 92 : 4250, 4027
7396 15:36:09.189805 96 : 4250, 3534
7397 15:36:09.189880 100 : 4250, 0
7398 15:36:09.189951 104 : 4363, 0
7399 15:36:09.193049 108 : 4253, 0
7400 15:36:09.193123 112 : 4253, 0
7401 15:36:09.196497 116 : 4250, 0
7402 15:36:09.196591 120 : 4253, 0
7403 15:36:09.196655 124 : 4250, 0
7404 15:36:09.199801 128 : 4250, 0
7405 15:36:09.199921 132 : 4250, 0
7406 15:36:09.199989 136 : 4360, 0
7407 15:36:09.203298 140 : 4250, 0
7408 15:36:09.203372 144 : 4250, 0
7409 15:36:09.206232 148 : 4250, 0
7410 15:36:09.206365 152 : 4361, 0
7411 15:36:09.206485 156 : 4250, 0
7412 15:36:09.209560 160 : 4250, 0
7413 15:36:09.209648 164 : 4250, 0
7414 15:36:09.213157 168 : 4250, 0
7415 15:36:09.213241 172 : 4250, 0
7416 15:36:09.213327 176 : 4249, 0
7417 15:36:09.216108 180 : 4250, 0
7418 15:36:09.216188 184 : 4250, 0
7419 15:36:09.219399 188 : 4363, 0
7420 15:36:09.219479 192 : 4250, 0
7421 15:36:09.219564 196 : 4250, 0
7422 15:36:09.222920 200 : 4255, 0
7423 15:36:09.223002 204 : 4250, 0
7424 15:36:09.226064 208 : 4363, 0
7425 15:36:09.226144 212 : 4255, 0
7426 15:36:09.226241 216 : 4250, 0
7427 15:36:09.229532 220 : 4250, 200
7428 15:36:09.229621 224 : 4361, 3884
7429 15:36:09.232988 228 : 4252, 4029
7430 15:36:09.233101 232 : 4252, 4029
7431 15:36:09.236073 236 : 4253, 4029
7432 15:36:09.236153 240 : 4250, 4026
7433 15:36:09.239538 244 : 4250, 4026
7434 15:36:09.239621 248 : 4252, 4030
7435 15:36:09.242505 252 : 4249, 4027
7436 15:36:09.242581 256 : 4250, 4026
7437 15:36:09.242653 260 : 4360, 4137
7438 15:36:09.245681 264 : 4250, 4027
7439 15:36:09.245758 268 : 4360, 4138
7440 15:36:09.249459 272 : 4250, 4026
7441 15:36:09.249537 276 : 4249, 4027
7442 15:36:09.252239 280 : 4250, 4026
7443 15:36:09.252316 284 : 4252, 4030
7444 15:36:09.255657 288 : 4360, 4137
7445 15:36:09.255761 292 : 4250, 4027
7446 15:36:09.259099 296 : 4250, 4027
7447 15:36:09.259185 300 : 4253, 4029
7448 15:36:09.262546 304 : 4250, 4027
7449 15:36:09.262635 308 : 4250, 4027
7450 15:36:09.265514 312 : 4360, 4137
7451 15:36:09.265598 316 : 4250, 4027
7452 15:36:09.268783 320 : 4361, 4137
7453 15:36:09.268864 324 : 4250, 4026
7454 15:36:09.272083 328 : 4250, 4027
7455 15:36:09.272172 332 : 4250, 4019
7456 15:36:09.272261 336 : 4250, 2161
7457 15:36:09.275356 340 : 4250, 31
7458 15:36:09.275434
7459 15:36:09.278671 MIOCK jitter meter ch=0
7460 15:36:09.278756
7461 15:36:09.278840 1T = (340-100) = 240 dly cells
7462 15:36:09.285288 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7463 15:36:09.285376 ==
7464 15:36:09.288693 Dram Type= 6, Freq= 0, CH_0, rank 0
7465 15:36:09.295283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7466 15:36:09.295366 ==
7467 15:36:09.298476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7468 15:36:09.304757 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7469 15:36:09.308490 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7470 15:36:09.314726 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7471 15:36:09.322774 [CA 0] Center 44 (14~74) winsize 61
7472 15:36:09.325660 [CA 1] Center 43 (13~74) winsize 62
7473 15:36:09.329206 [CA 2] Center 39 (10~68) winsize 59
7474 15:36:09.332496 [CA 3] Center 38 (9~68) winsize 60
7475 15:36:09.335856 [CA 4] Center 36 (7~66) winsize 60
7476 15:36:09.339174 [CA 5] Center 36 (6~66) winsize 61
7477 15:36:09.339254
7478 15:36:09.342151 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7479 15:36:09.342253
7480 15:36:09.348750 [CATrainingPosCal] consider 1 rank data
7481 15:36:09.348835 u2DelayCellTimex100 = 271/100 ps
7482 15:36:09.355491 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7483 15:36:09.358768 CA1 delay=43 (13~74),Diff = 7 PI (25 cell)
7484 15:36:09.362208 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7485 15:36:09.365470 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7486 15:36:09.368703 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7487 15:36:09.372045 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7488 15:36:09.372132
7489 15:36:09.375498 CA PerBit enable=1, Macro0, CA PI delay=36
7490 15:36:09.375574
7491 15:36:09.378400 [CBTSetCACLKResult] CA Dly = 36
7492 15:36:09.381852 CS Dly: 11 (0~42)
7493 15:36:09.384920 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7494 15:36:09.388257 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7495 15:36:09.388346 ==
7496 15:36:09.391486 Dram Type= 6, Freq= 0, CH_0, rank 1
7497 15:36:09.398608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7498 15:36:09.398709 ==
7499 15:36:09.401739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7500 15:36:09.408416 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7501 15:36:09.411595 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7502 15:36:09.418096 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7503 15:36:09.426467 [CA 0] Center 43 (13~74) winsize 62
7504 15:36:09.429530 [CA 1] Center 43 (13~73) winsize 61
7505 15:36:09.432856 [CA 2] Center 38 (9~68) winsize 60
7506 15:36:09.436293 [CA 3] Center 38 (9~68) winsize 60
7507 15:36:09.439557 [CA 4] Center 36 (6~67) winsize 62
7508 15:36:09.442958 [CA 5] Center 36 (6~66) winsize 61
7509 15:36:09.443038
7510 15:36:09.445963 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7511 15:36:09.446037
7512 15:36:09.449423 [CATrainingPosCal] consider 2 rank data
7513 15:36:09.452377 u2DelayCellTimex100 = 271/100 ps
7514 15:36:09.459252 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7515 15:36:09.462342 CA1 delay=43 (13~73),Diff = 7 PI (25 cell)
7516 15:36:09.465915 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7517 15:36:09.469358 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7518 15:36:09.472642 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7519 15:36:09.475548 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7520 15:36:09.475638
7521 15:36:09.479222 CA PerBit enable=1, Macro0, CA PI delay=36
7522 15:36:09.479314
7523 15:36:09.482425 [CBTSetCACLKResult] CA Dly = 36
7524 15:36:09.485780 CS Dly: 11 (0~43)
7525 15:36:09.489323 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7526 15:36:09.491926 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7527 15:36:09.492020
7528 15:36:09.495627 ----->DramcWriteLeveling(PI) begin...
7529 15:36:09.495719 ==
7530 15:36:09.498891 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 15:36:09.505644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 15:36:09.505747 ==
7533 15:36:09.509350 Write leveling (Byte 0): 35 => 35
7534 15:36:09.512260 Write leveling (Byte 1): 29 => 29
7535 15:36:09.515006 DramcWriteLeveling(PI) end<-----
7536 15:36:09.515117
7537 15:36:09.515202 ==
7538 15:36:09.518507 Dram Type= 6, Freq= 0, CH_0, rank 0
7539 15:36:09.521666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 15:36:09.521760 ==
7541 15:36:09.525171 [Gating] SW mode calibration
7542 15:36:09.531626 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7543 15:36:09.538582 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7544 15:36:09.542087 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7545 15:36:09.545065 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7546 15:36:09.551811 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 15:36:09.554610 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7548 15:36:09.558137 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7549 15:36:09.564537 1 4 20 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
7550 15:36:09.567881 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7551 15:36:09.571409 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7552 15:36:09.577613 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7553 15:36:09.581145 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7554 15:36:09.584241 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 15:36:09.591177 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
7556 15:36:09.594591 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7557 15:36:09.597441 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
7558 15:36:09.604311 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 15:36:09.607244 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 15:36:09.610629 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 15:36:09.617602 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 15:36:09.620429 1 6 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7563 15:36:09.623972 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7564 15:36:09.630527 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7565 15:36:09.633770 1 6 20 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
7566 15:36:09.636833 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 15:36:09.643527 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 15:36:09.647041 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 15:36:09.650420 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 15:36:09.657164 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 15:36:09.659970 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7572 15:36:09.663437 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7573 15:36:09.669875 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7574 15:36:09.673512 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7575 15:36:09.676644 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 15:36:09.682761 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 15:36:09.686464 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 15:36:09.689425 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 15:36:09.696286 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 15:36:09.699727 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 15:36:09.702550 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 15:36:09.709479 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 15:36:09.712587 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 15:36:09.715870 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 15:36:09.722227 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 15:36:09.725930 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 15:36:09.729071 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7588 15:36:09.732064 Total UI for P1: 0, mck2ui 16
7589 15:36:09.735544 best dqsien dly found for B0: ( 1, 9, 10)
7590 15:36:09.742432 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7591 15:36:09.745684 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7592 15:36:09.749036 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7593 15:36:09.755354 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 15:36:09.755450 Total UI for P1: 0, mck2ui 16
7595 15:36:09.762069 best dqsien dly found for B1: ( 1, 9, 22)
7596 15:36:09.764946 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7597 15:36:09.768745 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7598 15:36:09.768822
7599 15:36:09.771591 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7600 15:36:09.774838 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7601 15:36:09.778321 [Gating] SW calibration Done
7602 15:36:09.778415 ==
7603 15:36:09.781660 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 15:36:09.785106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 15:36:09.785181 ==
7606 15:36:09.788055 RX Vref Scan: 0
7607 15:36:09.788128
7608 15:36:09.791838 RX Vref 0 -> 0, step: 1
7609 15:36:09.791961
7610 15:36:09.792048 RX Delay 0 -> 252, step: 8
7611 15:36:09.798186 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7612 15:36:09.801653 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7613 15:36:09.804673 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7614 15:36:09.807980 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7615 15:36:09.811408 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7616 15:36:09.817899 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7617 15:36:09.820974 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7618 15:36:09.824573 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7619 15:36:09.827501 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7620 15:36:09.830970 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7621 15:36:09.837426 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7622 15:36:09.840844 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7623 15:36:09.844253 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7624 15:36:09.847551 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7625 15:36:09.853965 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7626 15:36:09.857551 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7627 15:36:09.857632 ==
7628 15:36:09.860654 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 15:36:09.864152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 15:36:09.864240 ==
7631 15:36:09.866958 DQS Delay:
7632 15:36:09.867037 DQS0 = 0, DQS1 = 0
7633 15:36:09.867128 DQM Delay:
7634 15:36:09.870564 DQM0 = 131, DQM1 = 126
7635 15:36:09.870644 DQ Delay:
7636 15:36:09.873766 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =123
7637 15:36:09.876883 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7638 15:36:09.880247 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7639 15:36:09.886714 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7640 15:36:09.886796
7641 15:36:09.886908
7642 15:36:09.886991 ==
7643 15:36:09.890603 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 15:36:09.893507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 15:36:09.893601 ==
7646 15:36:09.893668
7647 15:36:09.893729
7648 15:36:09.896504 TX Vref Scan disable
7649 15:36:09.896595 == TX Byte 0 ==
7650 15:36:09.903209 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7651 15:36:09.906884 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7652 15:36:09.910200 == TX Byte 1 ==
7653 15:36:09.913293 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7654 15:36:09.916640 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7655 15:36:09.916723 ==
7656 15:36:09.919883 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 15:36:09.923339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 15:36:09.923442 ==
7659 15:36:09.937834
7660 15:36:09.941005 TX Vref early break, caculate TX vref
7661 15:36:09.944713 TX Vref=16, minBit 8, minWin=21, winSum=369
7662 15:36:09.947693 TX Vref=18, minBit 1, minWin=23, winSum=385
7663 15:36:09.950913 TX Vref=20, minBit 7, minWin=23, winSum=389
7664 15:36:09.954269 TX Vref=22, minBit 1, minWin=24, winSum=402
7665 15:36:09.958166 TX Vref=24, minBit 1, minWin=25, winSum=412
7666 15:36:09.964151 TX Vref=26, minBit 8, minWin=24, winSum=415
7667 15:36:09.967378 TX Vref=28, minBit 1, minWin=25, winSum=421
7668 15:36:09.971022 TX Vref=30, minBit 1, minWin=25, winSum=419
7669 15:36:09.974164 TX Vref=32, minBit 1, minWin=24, winSum=410
7670 15:36:09.977533 TX Vref=34, minBit 0, minWin=24, winSum=396
7671 15:36:09.984233 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
7672 15:36:09.984311
7673 15:36:09.987773 Final TX Range 0 Vref 28
7674 15:36:09.987876
7675 15:36:09.987958 ==
7676 15:36:09.990819 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 15:36:09.994069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 15:36:09.994184 ==
7679 15:36:09.994281
7680 15:36:09.994379
7681 15:36:09.997487 TX Vref Scan disable
7682 15:36:10.003881 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7683 15:36:10.003983 == TX Byte 0 ==
7684 15:36:10.007446 u2DelayCellOfst[0]=10 cells (3 PI)
7685 15:36:10.010919 u2DelayCellOfst[1]=18 cells (5 PI)
7686 15:36:10.014270 u2DelayCellOfst[2]=7 cells (2 PI)
7687 15:36:10.017326 u2DelayCellOfst[3]=10 cells (3 PI)
7688 15:36:10.020604 u2DelayCellOfst[4]=7 cells (2 PI)
7689 15:36:10.024141 u2DelayCellOfst[5]=0 cells (0 PI)
7690 15:36:10.027009 u2DelayCellOfst[6]=18 cells (5 PI)
7691 15:36:10.030549 u2DelayCellOfst[7]=14 cells (4 PI)
7692 15:36:10.033721 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7693 15:36:10.037097 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7694 15:36:10.040206 == TX Byte 1 ==
7695 15:36:10.043564 u2DelayCellOfst[8]=0 cells (0 PI)
7696 15:36:10.047094 u2DelayCellOfst[9]=0 cells (0 PI)
7697 15:36:10.047195 u2DelayCellOfst[10]=7 cells (2 PI)
7698 15:36:10.050324 u2DelayCellOfst[11]=3 cells (1 PI)
7699 15:36:10.053441 u2DelayCellOfst[12]=10 cells (3 PI)
7700 15:36:10.056733 u2DelayCellOfst[13]=10 cells (3 PI)
7701 15:36:10.059901 u2DelayCellOfst[14]=14 cells (4 PI)
7702 15:36:10.063266 u2DelayCellOfst[15]=10 cells (3 PI)
7703 15:36:10.069614 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7704 15:36:10.073194 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7705 15:36:10.073297 DramC Write-DBI on
7706 15:36:10.073386 ==
7707 15:36:10.076444 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 15:36:10.083071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 15:36:10.083146 ==
7710 15:36:10.083219
7711 15:36:10.083278
7712 15:36:10.085888 TX Vref Scan disable
7713 15:36:10.085969 == TX Byte 0 ==
7714 15:36:10.092503 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7715 15:36:10.092579 == TX Byte 1 ==
7716 15:36:10.095992 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7717 15:36:10.099664 DramC Write-DBI off
7718 15:36:10.099776
7719 15:36:10.099875 [DATLAT]
7720 15:36:10.102907 Freq=1600, CH0 RK0
7721 15:36:10.102986
7722 15:36:10.103048 DATLAT Default: 0xf
7723 15:36:10.105842 0, 0xFFFF, sum = 0
7724 15:36:10.105918 1, 0xFFFF, sum = 0
7725 15:36:10.109530 2, 0xFFFF, sum = 0
7726 15:36:10.109603 3, 0xFFFF, sum = 0
7727 15:36:10.112968 4, 0xFFFF, sum = 0
7728 15:36:10.113043 5, 0xFFFF, sum = 0
7729 15:36:10.115596 6, 0xFFFF, sum = 0
7730 15:36:10.115670 7, 0xFFFF, sum = 0
7731 15:36:10.119151 8, 0xFFFF, sum = 0
7732 15:36:10.122630 9, 0xFFFF, sum = 0
7733 15:36:10.122721 10, 0xFFFF, sum = 0
7734 15:36:10.125539 11, 0xFFFF, sum = 0
7735 15:36:10.125616 12, 0xFFFF, sum = 0
7736 15:36:10.129106 13, 0xFFFF, sum = 0
7737 15:36:10.129180 14, 0x0, sum = 1
7738 15:36:10.132334 15, 0x0, sum = 2
7739 15:36:10.132412 16, 0x0, sum = 3
7740 15:36:10.135900 17, 0x0, sum = 4
7741 15:36:10.135996 best_step = 15
7742 15:36:10.136061
7743 15:36:10.136124 ==
7744 15:36:10.139269 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 15:36:10.142396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 15:36:10.145709 ==
7747 15:36:10.145789 RX Vref Scan: 1
7748 15:36:10.145852
7749 15:36:10.149004 Set Vref Range= 24 -> 127
7750 15:36:10.149096
7751 15:36:10.149160 RX Vref 24 -> 127, step: 1
7752 15:36:10.152251
7753 15:36:10.152338 RX Delay 11 -> 252, step: 4
7754 15:36:10.152410
7755 15:36:10.155339 Set Vref, RX VrefLevel [Byte0]: 24
7756 15:36:10.158899 [Byte1]: 24
7757 15:36:10.162204
7758 15:36:10.162293 Set Vref, RX VrefLevel [Byte0]: 25
7759 15:36:10.165665 [Byte1]: 25
7760 15:36:10.170143
7761 15:36:10.170266 Set Vref, RX VrefLevel [Byte0]: 26
7762 15:36:10.173286 [Byte1]: 26
7763 15:36:10.177887
7764 15:36:10.177988 Set Vref, RX VrefLevel [Byte0]: 27
7765 15:36:10.180946 [Byte1]: 27
7766 15:36:10.185650
7767 15:36:10.185741 Set Vref, RX VrefLevel [Byte0]: 28
7768 15:36:10.188496 [Byte1]: 28
7769 15:36:10.192865
7770 15:36:10.192939 Set Vref, RX VrefLevel [Byte0]: 29
7771 15:36:10.196343 [Byte1]: 29
7772 15:36:10.200277
7773 15:36:10.200390 Set Vref, RX VrefLevel [Byte0]: 30
7774 15:36:10.203491 [Byte1]: 30
7775 15:36:10.208433
7776 15:36:10.208509 Set Vref, RX VrefLevel [Byte0]: 31
7777 15:36:10.211058 [Byte1]: 31
7778 15:36:10.216021
7779 15:36:10.216097 Set Vref, RX VrefLevel [Byte0]: 32
7780 15:36:10.219096 [Byte1]: 32
7781 15:36:10.223079
7782 15:36:10.223170 Set Vref, RX VrefLevel [Byte0]: 33
7783 15:36:10.226509 [Byte1]: 33
7784 15:36:10.230836
7785 15:36:10.230917 Set Vref, RX VrefLevel [Byte0]: 34
7786 15:36:10.234148 [Byte1]: 34
7787 15:36:10.238466
7788 15:36:10.238547 Set Vref, RX VrefLevel [Byte0]: 35
7789 15:36:10.242070 [Byte1]: 35
7790 15:36:10.246256
7791 15:36:10.246334 Set Vref, RX VrefLevel [Byte0]: 36
7792 15:36:10.249535 [Byte1]: 36
7793 15:36:10.254173
7794 15:36:10.254253 Set Vref, RX VrefLevel [Byte0]: 37
7795 15:36:10.256977 [Byte1]: 37
7796 15:36:10.261300
7797 15:36:10.261377 Set Vref, RX VrefLevel [Byte0]: 38
7798 15:36:10.264860 [Byte1]: 38
7799 15:36:10.268785
7800 15:36:10.268860 Set Vref, RX VrefLevel [Byte0]: 39
7801 15:36:10.272139 [Byte1]: 39
7802 15:36:10.276873
7803 15:36:10.276955 Set Vref, RX VrefLevel [Byte0]: 40
7804 15:36:10.279648 [Byte1]: 40
7805 15:36:10.284414
7806 15:36:10.284488 Set Vref, RX VrefLevel [Byte0]: 41
7807 15:36:10.287757 [Byte1]: 41
7808 15:36:10.291990
7809 15:36:10.292099 Set Vref, RX VrefLevel [Byte0]: 42
7810 15:36:10.295180 [Byte1]: 42
7811 15:36:10.299624
7812 15:36:10.299754 Set Vref, RX VrefLevel [Byte0]: 43
7813 15:36:10.302875 [Byte1]: 43
7814 15:36:10.307052
7815 15:36:10.307127 Set Vref, RX VrefLevel [Byte0]: 44
7816 15:36:10.310559 [Byte1]: 44
7817 15:36:10.314819
7818 15:36:10.314896 Set Vref, RX VrefLevel [Byte0]: 45
7819 15:36:10.317955 [Byte1]: 45
7820 15:36:10.322465
7821 15:36:10.322544 Set Vref, RX VrefLevel [Byte0]: 46
7822 15:36:10.325547 [Byte1]: 46
7823 15:36:10.330285
7824 15:36:10.330380 Set Vref, RX VrefLevel [Byte0]: 47
7825 15:36:10.333165 [Byte1]: 47
7826 15:36:10.337268
7827 15:36:10.337425 Set Vref, RX VrefLevel [Byte0]: 48
7828 15:36:10.340803 [Byte1]: 48
7829 15:36:10.345258
7830 15:36:10.345339 Set Vref, RX VrefLevel [Byte0]: 49
7831 15:36:10.348153 [Byte1]: 49
7832 15:36:10.352794
7833 15:36:10.352869 Set Vref, RX VrefLevel [Byte0]: 50
7834 15:36:10.356096 [Byte1]: 50
7835 15:36:10.360487
7836 15:36:10.360569 Set Vref, RX VrefLevel [Byte0]: 51
7837 15:36:10.363418 [Byte1]: 51
7838 15:36:10.368273
7839 15:36:10.368355 Set Vref, RX VrefLevel [Byte0]: 52
7840 15:36:10.371457 [Byte1]: 52
7841 15:36:10.375426
7842 15:36:10.375505 Set Vref, RX VrefLevel [Byte0]: 53
7843 15:36:10.378887 [Byte1]: 53
7844 15:36:10.383521
7845 15:36:10.386322 Set Vref, RX VrefLevel [Byte0]: 54
7846 15:36:10.389973 [Byte1]: 54
7847 15:36:10.390057
7848 15:36:10.392900 Set Vref, RX VrefLevel [Byte0]: 55
7849 15:36:10.396283 [Byte1]: 55
7850 15:36:10.396405
7851 15:36:10.399819 Set Vref, RX VrefLevel [Byte0]: 56
7852 15:36:10.402664 [Byte1]: 56
7853 15:36:10.406112
7854 15:36:10.406186 Set Vref, RX VrefLevel [Byte0]: 57
7855 15:36:10.409005 [Byte1]: 57
7856 15:36:10.413481
7857 15:36:10.413562 Set Vref, RX VrefLevel [Byte0]: 58
7858 15:36:10.416944 [Byte1]: 58
7859 15:36:10.421493
7860 15:36:10.421578 Set Vref, RX VrefLevel [Byte0]: 59
7861 15:36:10.424470 [Byte1]: 59
7862 15:36:10.428563
7863 15:36:10.428638 Set Vref, RX VrefLevel [Byte0]: 60
7864 15:36:10.431924 [Byte1]: 60
7865 15:36:10.436533
7866 15:36:10.436614 Set Vref, RX VrefLevel [Byte0]: 61
7867 15:36:10.439679 [Byte1]: 61
7868 15:36:10.444182
7869 15:36:10.444263 Set Vref, RX VrefLevel [Byte0]: 62
7870 15:36:10.447524 [Byte1]: 62
7871 15:36:10.451917
7872 15:36:10.451998 Set Vref, RX VrefLevel [Byte0]: 63
7873 15:36:10.454926 [Byte1]: 63
7874 15:36:10.459484
7875 15:36:10.459565 Set Vref, RX VrefLevel [Byte0]: 64
7876 15:36:10.462653 [Byte1]: 64
7877 15:36:10.466703
7878 15:36:10.466785 Set Vref, RX VrefLevel [Byte0]: 65
7879 15:36:10.470512 [Byte1]: 65
7880 15:36:10.474507
7881 15:36:10.474615 Set Vref, RX VrefLevel [Byte0]: 66
7882 15:36:10.478148 [Byte1]: 66
7883 15:36:10.482576
7884 15:36:10.482657 Set Vref, RX VrefLevel [Byte0]: 67
7885 15:36:10.485346 [Byte1]: 67
7886 15:36:10.489977
7887 15:36:10.490058 Set Vref, RX VrefLevel [Byte0]: 68
7888 15:36:10.492897 [Byte1]: 68
7889 15:36:10.497603
7890 15:36:10.497684 Set Vref, RX VrefLevel [Byte0]: 69
7891 15:36:10.500486 [Byte1]: 69
7892 15:36:10.505407
7893 15:36:10.505486 Set Vref, RX VrefLevel [Byte0]: 70
7894 15:36:10.508435 [Byte1]: 70
7895 15:36:10.512426
7896 15:36:10.512506 Set Vref, RX VrefLevel [Byte0]: 71
7897 15:36:10.515888 [Byte1]: 71
7898 15:36:10.520484
7899 15:36:10.520564 Set Vref, RX VrefLevel [Byte0]: 72
7900 15:36:10.523587 [Byte1]: 72
7901 15:36:10.527778
7902 15:36:10.527885 Final RX Vref Byte 0 = 56 to rank0
7903 15:36:10.531157 Final RX Vref Byte 1 = 61 to rank0
7904 15:36:10.534353 Final RX Vref Byte 0 = 56 to rank1
7905 15:36:10.537634 Final RX Vref Byte 1 = 61 to rank1==
7906 15:36:10.541061 Dram Type= 6, Freq= 0, CH_0, rank 0
7907 15:36:10.547361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7908 15:36:10.547441 ==
7909 15:36:10.547505 DQS Delay:
7910 15:36:10.550689 DQS0 = 0, DQS1 = 0
7911 15:36:10.550770 DQM Delay:
7912 15:36:10.550832 DQM0 = 128, DQM1 = 124
7913 15:36:10.554245 DQ Delay:
7914 15:36:10.557657 DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =124
7915 15:36:10.560964 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7916 15:36:10.564098 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =120
7917 15:36:10.567256 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =128
7918 15:36:10.567336
7919 15:36:10.567399
7920 15:36:10.567456
7921 15:36:10.570473 [DramC_TX_OE_Calibration] TA2
7922 15:36:10.573640 Original DQ_B0 (3 6) =30, OEN = 27
7923 15:36:10.577101 Original DQ_B1 (3 6) =30, OEN = 27
7924 15:36:10.580419 24, 0x0, End_B0=24 End_B1=24
7925 15:36:10.583932 25, 0x0, End_B0=25 End_B1=25
7926 15:36:10.584027 26, 0x0, End_B0=26 End_B1=26
7927 15:36:10.587132 27, 0x0, End_B0=27 End_B1=27
7928 15:36:10.590368 28, 0x0, End_B0=28 End_B1=28
7929 15:36:10.593961 29, 0x0, End_B0=29 End_B1=29
7930 15:36:10.594042 30, 0x0, End_B0=30 End_B1=30
7931 15:36:10.597107 31, 0x4141, End_B0=30 End_B1=30
7932 15:36:10.600131 Byte0 end_step=30 best_step=27
7933 15:36:10.603489 Byte1 end_step=30 best_step=27
7934 15:36:10.607036 Byte0 TX OE(2T, 0.5T) = (3, 3)
7935 15:36:10.610542 Byte1 TX OE(2T, 0.5T) = (3, 3)
7936 15:36:10.610621
7937 15:36:10.610685
7938 15:36:10.616694 [DQSOSCAuto] RK0, (LSB)MR18= 0x1715, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
7939 15:36:10.620153 CH0 RK0: MR19=303, MR18=1715
7940 15:36:10.627224 CH0_RK0: MR19=0x303, MR18=0x1715, DQSOSC=398, MR23=63, INC=23, DEC=15
7941 15:36:10.627301
7942 15:36:10.629940 ----->DramcWriteLeveling(PI) begin...
7943 15:36:10.630017 ==
7944 15:36:10.633104 Dram Type= 6, Freq= 0, CH_0, rank 1
7945 15:36:10.636673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7946 15:36:10.636753 ==
7947 15:36:10.639796 Write leveling (Byte 0): 32 => 32
7948 15:36:10.643076 Write leveling (Byte 1): 28 => 28
7949 15:36:10.646742 DramcWriteLeveling(PI) end<-----
7950 15:36:10.646849
7951 15:36:10.646912 ==
7952 15:36:10.649965 Dram Type= 6, Freq= 0, CH_0, rank 1
7953 15:36:10.652885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 15:36:10.656250 ==
7955 15:36:10.656334 [Gating] SW mode calibration
7956 15:36:10.666096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7957 15:36:10.669673 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7958 15:36:10.672494 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7959 15:36:10.679288 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7960 15:36:10.682858 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7961 15:36:10.688866 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7962 15:36:10.692410 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7963 15:36:10.696071 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7964 15:36:10.702264 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7965 15:36:10.705569 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7966 15:36:10.708960 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7967 15:36:10.715178 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7968 15:36:10.718678 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
7969 15:36:10.721668 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
7970 15:36:10.728775 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7971 15:36:10.731950 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7972 15:36:10.735155 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 15:36:10.741472 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7974 15:36:10.745013 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7975 15:36:10.748578 1 6 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7976 15:36:10.754781 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7977 15:36:10.758193 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7978 15:36:10.761308 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7979 15:36:10.767815 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7980 15:36:10.771301 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 15:36:10.774826 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7982 15:36:10.781049 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 15:36:10.784125 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 15:36:10.787301 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7985 15:36:10.794249 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7986 15:36:10.797146 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7987 15:36:10.800880 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7988 15:36:10.807226 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7989 15:36:10.810303 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 15:36:10.813652 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 15:36:10.820456 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 15:36:10.823940 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 15:36:10.826724 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 15:36:10.833651 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 15:36:10.836924 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 15:36:10.840293 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 15:36:10.846470 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 15:36:10.849774 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 15:36:10.853125 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8000 15:36:10.860088 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8001 15:36:10.863328 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8002 15:36:10.866585 Total UI for P1: 0, mck2ui 16
8003 15:36:10.870070 best dqsien dly found for B0: ( 1, 9, 6)
8004 15:36:10.873109 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8005 15:36:10.880036 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8006 15:36:10.882724 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 15:36:10.886167 Total UI for P1: 0, mck2ui 16
8008 15:36:10.889570 best dqsien dly found for B1: ( 1, 9, 18)
8009 15:36:10.892914 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8010 15:36:10.895989 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8011 15:36:10.896061
8012 15:36:10.899088 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8013 15:36:10.902773 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8014 15:36:10.905663 [Gating] SW calibration Done
8015 15:36:10.905748 ==
8016 15:36:10.909278 Dram Type= 6, Freq= 0, CH_0, rank 1
8017 15:36:10.916128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8018 15:36:10.916201 ==
8019 15:36:10.916276 RX Vref Scan: 0
8020 15:36:10.916340
8021 15:36:10.918776 RX Vref 0 -> 0, step: 1
8022 15:36:10.918843
8023 15:36:10.922366 RX Delay 0 -> 252, step: 8
8024 15:36:10.925568 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8025 15:36:10.929112 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8026 15:36:10.931970 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8027 15:36:10.935395 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8028 15:36:10.942471 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8029 15:36:10.945928 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8030 15:36:10.948558 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8031 15:36:10.952095 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8032 15:36:10.955642 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8033 15:36:10.962127 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8034 15:36:10.965574 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8035 15:36:10.968634 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8036 15:36:10.972154 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8037 15:36:10.978235 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8038 15:36:10.981799 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8039 15:36:10.984804 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8040 15:36:10.984878 ==
8041 15:36:10.988199 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 15:36:10.991596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 15:36:10.995007 ==
8044 15:36:10.995086 DQS Delay:
8045 15:36:10.995157 DQS0 = 0, DQS1 = 0
8046 15:36:10.997926 DQM Delay:
8047 15:36:10.998044 DQM0 = 131, DQM1 = 125
8048 15:36:11.001149 DQ Delay:
8049 15:36:11.004424 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
8050 15:36:11.007732 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =135
8051 15:36:11.011341 DQ8 =115, DQ9 =111, DQ10 =131, DQ11 =119
8052 15:36:11.014472 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8053 15:36:11.014582
8054 15:36:11.014680
8055 15:36:11.014768 ==
8056 15:36:11.017894 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 15:36:11.020915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 15:36:11.020994 ==
8059 15:36:11.024105
8060 15:36:11.024177
8061 15:36:11.024254 TX Vref Scan disable
8062 15:36:11.027586 == TX Byte 0 ==
8063 15:36:11.031059 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8064 15:36:11.034550 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8065 15:36:11.037332 == TX Byte 1 ==
8066 15:36:11.040959 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8067 15:36:11.044106 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8068 15:36:11.044184 ==
8069 15:36:11.047947 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 15:36:11.053702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 15:36:11.053782 ==
8072 15:36:11.066255
8073 15:36:11.069328 TX Vref early break, caculate TX vref
8074 15:36:11.073090 TX Vref=16, minBit 1, minWin=23, winSum=381
8075 15:36:11.076043 TX Vref=18, minBit 8, minWin=23, winSum=390
8076 15:36:11.079546 TX Vref=20, minBit 1, minWin=24, winSum=396
8077 15:36:11.082987 TX Vref=22, minBit 0, minWin=24, winSum=408
8078 15:36:11.085916 TX Vref=24, minBit 1, minWin=25, winSum=414
8079 15:36:11.093009 TX Vref=26, minBit 4, minWin=25, winSum=427
8080 15:36:11.095915 TX Vref=28, minBit 4, minWin=25, winSum=423
8081 15:36:11.099263 TX Vref=30, minBit 1, minWin=25, winSum=415
8082 15:36:11.102367 TX Vref=32, minBit 0, minWin=25, winSum=409
8083 15:36:11.105692 TX Vref=34, minBit 1, minWin=24, winSum=404
8084 15:36:11.112634 [TxChooseVref] Worse bit 4, Min win 25, Win sum 427, Final Vref 26
8085 15:36:11.112738
8086 15:36:11.115814 Final TX Range 0 Vref 26
8087 15:36:11.115919
8088 15:36:11.115993 ==
8089 15:36:11.119582 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 15:36:11.122604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 15:36:11.122701 ==
8092 15:36:11.122795
8093 15:36:11.122881
8094 15:36:11.126147 TX Vref Scan disable
8095 15:36:11.132286 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8096 15:36:11.132359 == TX Byte 0 ==
8097 15:36:11.135606 u2DelayCellOfst[0]=14 cells (4 PI)
8098 15:36:11.139186 u2DelayCellOfst[1]=18 cells (5 PI)
8099 15:36:11.142180 u2DelayCellOfst[2]=10 cells (3 PI)
8100 15:36:11.145453 u2DelayCellOfst[3]=14 cells (4 PI)
8101 15:36:11.149189 u2DelayCellOfst[4]=10 cells (3 PI)
8102 15:36:11.152490 u2DelayCellOfst[5]=0 cells (0 PI)
8103 15:36:11.155308 u2DelayCellOfst[6]=18 cells (5 PI)
8104 15:36:11.158623 u2DelayCellOfst[7]=18 cells (5 PI)
8105 15:36:11.162382 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8106 15:36:11.165383 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8107 15:36:11.168552 == TX Byte 1 ==
8108 15:36:11.172181 u2DelayCellOfst[8]=0 cells (0 PI)
8109 15:36:11.172265 u2DelayCellOfst[9]=0 cells (0 PI)
8110 15:36:11.175475 u2DelayCellOfst[10]=3 cells (1 PI)
8111 15:36:11.178500 u2DelayCellOfst[11]=3 cells (1 PI)
8112 15:36:11.181897 u2DelayCellOfst[12]=10 cells (3 PI)
8113 15:36:11.185429 u2DelayCellOfst[13]=10 cells (3 PI)
8114 15:36:11.188557 u2DelayCellOfst[14]=14 cells (4 PI)
8115 15:36:11.192147 u2DelayCellOfst[15]=10 cells (3 PI)
8116 15:36:11.195260 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8117 15:36:11.202007 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8118 15:36:11.202092 DramC Write-DBI on
8119 15:36:11.202158 ==
8120 15:36:11.205111 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 15:36:11.211861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 15:36:11.211978 ==
8123 15:36:11.212073
8124 15:36:11.212151
8125 15:36:11.212210 TX Vref Scan disable
8126 15:36:11.215748 == TX Byte 0 ==
8127 15:36:11.219223 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
8128 15:36:11.222726 == TX Byte 1 ==
8129 15:36:11.225496 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8130 15:36:11.229038 DramC Write-DBI off
8131 15:36:11.229119
8132 15:36:11.229183 [DATLAT]
8133 15:36:11.229243 Freq=1600, CH0 RK1
8134 15:36:11.229301
8135 15:36:11.232248 DATLAT Default: 0xf
8136 15:36:11.232337 0, 0xFFFF, sum = 0
8137 15:36:11.235849 1, 0xFFFF, sum = 0
8138 15:36:11.238937 2, 0xFFFF, sum = 0
8139 15:36:11.239020 3, 0xFFFF, sum = 0
8140 15:36:11.242088 4, 0xFFFF, sum = 0
8141 15:36:11.242171 5, 0xFFFF, sum = 0
8142 15:36:11.245423 6, 0xFFFF, sum = 0
8143 15:36:11.245505 7, 0xFFFF, sum = 0
8144 15:36:11.248888 8, 0xFFFF, sum = 0
8145 15:36:11.248971 9, 0xFFFF, sum = 0
8146 15:36:11.252306 10, 0xFFFF, sum = 0
8147 15:36:11.252389 11, 0xFFFF, sum = 0
8148 15:36:11.255619 12, 0xFFFF, sum = 0
8149 15:36:11.255721 13, 0xFFFF, sum = 0
8150 15:36:11.258433 14, 0x0, sum = 1
8151 15:36:11.258508 15, 0x0, sum = 2
8152 15:36:11.261894 16, 0x0, sum = 3
8153 15:36:11.261997 17, 0x0, sum = 4
8154 15:36:11.265145 best_step = 15
8155 15:36:11.265242
8156 15:36:11.265330 ==
8157 15:36:11.268274 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 15:36:11.271726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 15:36:11.271830 ==
8160 15:36:11.275085 RX Vref Scan: 0
8161 15:36:11.275164
8162 15:36:11.275243 RX Vref 0 -> 0, step: 1
8163 15:36:11.275333
8164 15:36:11.278307 RX Delay 11 -> 252, step: 4
8165 15:36:11.285169 iDelay=187, Bit 0, Center 128 (79 ~ 178) 100
8166 15:36:11.288037 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8167 15:36:11.291451 iDelay=187, Bit 2, Center 126 (75 ~ 178) 104
8168 15:36:11.294851 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8169 15:36:11.298254 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8170 15:36:11.305014 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8171 15:36:11.308180 iDelay=187, Bit 6, Center 138 (91 ~ 186) 96
8172 15:36:11.311073 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8173 15:36:11.315093 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8174 15:36:11.317964 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8175 15:36:11.324671 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8176 15:36:11.327600 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8177 15:36:11.331046 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8178 15:36:11.334081 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8179 15:36:11.341112 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8180 15:36:11.344441 iDelay=187, Bit 15, Center 130 (75 ~ 186) 112
8181 15:36:11.344524 ==
8182 15:36:11.347647 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 15:36:11.350907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 15:36:11.350991 ==
8185 15:36:11.354702 DQS Delay:
8186 15:36:11.354785 DQS0 = 0, DQS1 = 0
8187 15:36:11.354851 DQM Delay:
8188 15:36:11.357197 DQM0 = 129, DQM1 = 123
8189 15:36:11.357279 DQ Delay:
8190 15:36:11.360628 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =126
8191 15:36:11.363750 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8192 15:36:11.367425 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8193 15:36:11.373733 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8194 15:36:11.373817
8195 15:36:11.373882
8196 15:36:11.373947
8197 15:36:11.377148 [DramC_TX_OE_Calibration] TA2
8198 15:36:11.377234 Original DQ_B0 (3 6) =30, OEN = 27
8199 15:36:11.380753 Original DQ_B1 (3 6) =30, OEN = 27
8200 15:36:11.383981 24, 0x0, End_B0=24 End_B1=24
8201 15:36:11.387128 25, 0x0, End_B0=25 End_B1=25
8202 15:36:11.390232 26, 0x0, End_B0=26 End_B1=26
8203 15:36:11.393920 27, 0x0, End_B0=27 End_B1=27
8204 15:36:11.394004 28, 0x0, End_B0=28 End_B1=28
8205 15:36:11.396860 29, 0x0, End_B0=29 End_B1=29
8206 15:36:11.400419 30, 0x0, End_B0=30 End_B1=30
8207 15:36:11.403788 31, 0x4141, End_B0=30 End_B1=30
8208 15:36:11.406665 Byte0 end_step=30 best_step=27
8209 15:36:11.406749 Byte1 end_step=30 best_step=27
8210 15:36:11.410736 Byte0 TX OE(2T, 0.5T) = (3, 3)
8211 15:36:11.413546 Byte1 TX OE(2T, 0.5T) = (3, 3)
8212 15:36:11.413661
8213 15:36:11.413758
8214 15:36:11.423643 [DQSOSCAuto] RK1, (LSB)MR18= 0x1413, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8215 15:36:11.423734 CH0 RK1: MR19=303, MR18=1413
8216 15:36:11.430228 CH0_RK1: MR19=0x303, MR18=0x1413, DQSOSC=399, MR23=63, INC=23, DEC=15
8217 15:36:11.433181 [RxdqsGatingPostProcess] freq 1600
8218 15:36:11.440072 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8219 15:36:11.443575 best DQS0 dly(2T, 0.5T) = (1, 1)
8220 15:36:11.446491 best DQS1 dly(2T, 0.5T) = (1, 1)
8221 15:36:11.449636 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8222 15:36:11.453419 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8223 15:36:11.456248 best DQS0 dly(2T, 0.5T) = (1, 1)
8224 15:36:11.456359 best DQS1 dly(2T, 0.5T) = (1, 1)
8225 15:36:11.459995 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8226 15:36:11.462967 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8227 15:36:11.466725 Pre-setting of DQS Precalculation
8228 15:36:11.472912 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8229 15:36:11.472996 ==
8230 15:36:11.476191 Dram Type= 6, Freq= 0, CH_1, rank 0
8231 15:36:11.479412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 15:36:11.479496 ==
8233 15:36:11.486200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8234 15:36:11.489461 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8235 15:36:11.492472 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8236 15:36:11.499349 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8237 15:36:11.508908 [CA 0] Center 42 (13~72) winsize 60
8238 15:36:11.512140 [CA 1] Center 42 (13~72) winsize 60
8239 15:36:11.515525 [CA 2] Center 38 (9~68) winsize 60
8240 15:36:11.518670 [CA 3] Center 37 (8~67) winsize 60
8241 15:36:11.521817 [CA 4] Center 38 (8~68) winsize 61
8242 15:36:11.525124 [CA 5] Center 37 (7~67) winsize 61
8243 15:36:11.525212
8244 15:36:11.528498 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8245 15:36:11.528579
8246 15:36:11.534832 [CATrainingPosCal] consider 1 rank data
8247 15:36:11.534936 u2DelayCellTimex100 = 271/100 ps
8248 15:36:11.541800 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8249 15:36:11.544713 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8250 15:36:11.548332 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8251 15:36:11.551397 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8252 15:36:11.554607 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8253 15:36:11.558299 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8254 15:36:11.558369
8255 15:36:11.561705 CA PerBit enable=1, Macro0, CA PI delay=37
8256 15:36:11.561787
8257 15:36:11.564835 [CBTSetCACLKResult] CA Dly = 37
8258 15:36:11.567749 CS Dly: 8 (0~39)
8259 15:36:11.571187 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8260 15:36:11.574613 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8261 15:36:11.574688 ==
8262 15:36:11.577926 Dram Type= 6, Freq= 0, CH_1, rank 1
8263 15:36:11.584444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 15:36:11.584527 ==
8265 15:36:11.587636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 15:36:11.594345 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 15:36:11.597582 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 15:36:11.604028 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 15:36:11.611846 [CA 0] Center 42 (12~72) winsize 61
8270 15:36:11.614985 [CA 1] Center 42 (13~72) winsize 60
8271 15:36:11.618539 [CA 2] Center 38 (9~68) winsize 60
8272 15:36:11.621673 [CA 3] Center 37 (8~66) winsize 59
8273 15:36:11.625448 [CA 4] Center 38 (8~68) winsize 61
8274 15:36:11.628655 [CA 5] Center 37 (8~67) winsize 60
8275 15:36:11.628737
8276 15:36:11.631723 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8277 15:36:11.631831
8278 15:36:11.635064 [CATrainingPosCal] consider 2 rank data
8279 15:36:11.638415 u2DelayCellTimex100 = 271/100 ps
8280 15:36:11.644867 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8281 15:36:11.648108 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8282 15:36:11.651191 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8283 15:36:11.655309 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8284 15:36:11.658019 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8285 15:36:11.661477 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8286 15:36:11.661563
8287 15:36:11.664953 CA PerBit enable=1, Macro0, CA PI delay=37
8288 15:36:11.665039
8289 15:36:11.668086 [CBTSetCACLKResult] CA Dly = 37
8290 15:36:11.671512 CS Dly: 9 (0~42)
8291 15:36:11.674529 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 15:36:11.677934 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 15:36:11.678042
8294 15:36:11.681409 ----->DramcWriteLeveling(PI) begin...
8295 15:36:11.681494 ==
8296 15:36:11.684300 Dram Type= 6, Freq= 0, CH_1, rank 0
8297 15:36:11.691332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 15:36:11.691422 ==
8299 15:36:11.694326 Write leveling (Byte 0): 25 => 25
8300 15:36:11.697753 Write leveling (Byte 1): 27 => 27
8301 15:36:11.697858 DramcWriteLeveling(PI) end<-----
8302 15:36:11.697926
8303 15:36:11.701001 ==
8304 15:36:11.704234 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 15:36:11.707621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 15:36:11.707704 ==
8307 15:36:11.710746 [Gating] SW mode calibration
8308 15:36:11.717179 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8309 15:36:11.720440 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8310 15:36:11.726955 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8311 15:36:11.730587 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8312 15:36:11.733789 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 15:36:11.740171 1 4 12 | B1->B0 | 2727 3232 | 0 1 | (0 0) (1 1)
8314 15:36:11.743709 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 15:36:11.746700 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 15:36:11.753477 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 15:36:11.757034 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 15:36:11.760257 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 15:36:11.766771 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 15:36:11.769954 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8321 15:36:11.773204 1 5 12 | B1->B0 | 3333 2828 | 1 1 | (1 0) (1 0)
8322 15:36:11.779926 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 15:36:11.782812 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 15:36:11.789700 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 15:36:11.792983 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 15:36:11.795975 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 15:36:11.803212 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 15:36:11.805995 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 15:36:11.809664 1 6 12 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8330 15:36:11.816004 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 15:36:11.819661 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 15:36:11.822590 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 15:36:11.829034 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 15:36:11.832479 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 15:36:11.835847 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 15:36:11.842102 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8337 15:36:11.845942 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8338 15:36:11.849078 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8339 15:36:11.855282 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 15:36:11.858742 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 15:36:11.861883 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 15:36:11.868316 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 15:36:11.871991 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 15:36:11.875055 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 15:36:11.881754 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 15:36:11.884913 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 15:36:11.888269 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 15:36:11.894855 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 15:36:11.898215 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 15:36:11.901690 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 15:36:11.908345 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 15:36:11.911576 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8353 15:36:11.915261 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8354 15:36:11.921459 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8355 15:36:11.921563 Total UI for P1: 0, mck2ui 16
8356 15:36:11.924974 best dqsien dly found for B0: ( 1, 9, 10)
8357 15:36:11.931794 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 15:36:11.934653 Total UI for P1: 0, mck2ui 16
8359 15:36:11.937663 best dqsien dly found for B1: ( 1, 9, 12)
8360 15:36:11.940875 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8361 15:36:11.944431 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8362 15:36:11.944523
8363 15:36:11.947953 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8364 15:36:11.950912 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8365 15:36:11.954506 [Gating] SW calibration Done
8366 15:36:11.954603 ==
8367 15:36:11.957571 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 15:36:11.960766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 15:36:11.964080 ==
8370 15:36:11.964158 RX Vref Scan: 0
8371 15:36:11.964235
8372 15:36:11.967710 RX Vref 0 -> 0, step: 1
8373 15:36:11.967815
8374 15:36:11.971000 RX Delay 0 -> 252, step: 8
8375 15:36:11.974318 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8376 15:36:11.977863 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8377 15:36:11.980453 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8378 15:36:11.984204 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8379 15:36:11.990227 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8380 15:36:11.993699 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8381 15:36:11.997252 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8382 15:36:12.000200 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8383 15:36:12.004066 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8384 15:36:12.010462 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8385 15:36:12.013314 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8386 15:36:12.016743 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8387 15:36:12.019916 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8388 15:36:12.023678 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8389 15:36:12.030050 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8390 15:36:12.033553 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8391 15:36:12.033654 ==
8392 15:36:12.036563 Dram Type= 6, Freq= 0, CH_1, rank 0
8393 15:36:12.040154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8394 15:36:12.040261 ==
8395 15:36:12.043424 DQS Delay:
8396 15:36:12.043523 DQS0 = 0, DQS1 = 0
8397 15:36:12.046707 DQM Delay:
8398 15:36:12.046783 DQM0 = 134, DQM1 = 129
8399 15:36:12.046847 DQ Delay:
8400 15:36:12.049655 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8401 15:36:12.056875 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8402 15:36:12.059869 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =123
8403 15:36:12.063564 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8404 15:36:12.063664
8405 15:36:12.063767
8406 15:36:12.063871 ==
8407 15:36:12.066694 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 15:36:12.069923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 15:36:12.070030 ==
8410 15:36:12.070128
8411 15:36:12.070217
8412 15:36:12.073055 TX Vref Scan disable
8413 15:36:12.076518 == TX Byte 0 ==
8414 15:36:12.079463 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8415 15:36:12.083608 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8416 15:36:12.086247 == TX Byte 1 ==
8417 15:36:12.089444 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8418 15:36:12.092826 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8419 15:36:12.092914 ==
8420 15:36:12.096244 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 15:36:12.102493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 15:36:12.102601 ==
8423 15:36:12.114738
8424 15:36:12.118185 TX Vref early break, caculate TX vref
8425 15:36:12.121887 TX Vref=16, minBit 8, minWin=21, winSum=367
8426 15:36:12.124944 TX Vref=18, minBit 8, minWin=22, winSum=373
8427 15:36:12.128095 TX Vref=20, minBit 8, minWin=22, winSum=386
8428 15:36:12.131343 TX Vref=22, minBit 8, minWin=23, winSum=393
8429 15:36:12.135014 TX Vref=24, minBit 8, minWin=24, winSum=408
8430 15:36:12.141393 TX Vref=26, minBit 9, minWin=24, winSum=414
8431 15:36:12.145108 TX Vref=28, minBit 9, minWin=24, winSum=414
8432 15:36:12.148194 TX Vref=30, minBit 0, minWin=25, winSum=416
8433 15:36:12.151222 TX Vref=32, minBit 5, minWin=24, winSum=406
8434 15:36:12.154388 TX Vref=34, minBit 0, minWin=23, winSum=395
8435 15:36:12.157740 TX Vref=36, minBit 9, minWin=22, winSum=385
8436 15:36:12.164419 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 30
8437 15:36:12.164518
8438 15:36:12.167994 Final TX Range 0 Vref 30
8439 15:36:12.168098
8440 15:36:12.168165 ==
8441 15:36:12.170962 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 15:36:12.174060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 15:36:12.174170 ==
8444 15:36:12.177366
8445 15:36:12.177439
8446 15:36:12.177500 TX Vref Scan disable
8447 15:36:12.184298 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8448 15:36:12.184378 == TX Byte 0 ==
8449 15:36:12.187933 u2DelayCellOfst[0]=14 cells (4 PI)
8450 15:36:12.190903 u2DelayCellOfst[1]=10 cells (3 PI)
8451 15:36:12.194604 u2DelayCellOfst[2]=0 cells (0 PI)
8452 15:36:12.197283 u2DelayCellOfst[3]=7 cells (2 PI)
8453 15:36:12.200607 u2DelayCellOfst[4]=10 cells (3 PI)
8454 15:36:12.203744 u2DelayCellOfst[5]=18 cells (5 PI)
8455 15:36:12.207194 u2DelayCellOfst[6]=18 cells (5 PI)
8456 15:36:12.210426 u2DelayCellOfst[7]=7 cells (2 PI)
8457 15:36:12.213950 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8458 15:36:12.217614 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8459 15:36:12.220245 == TX Byte 1 ==
8460 15:36:12.223636 u2DelayCellOfst[8]=0 cells (0 PI)
8461 15:36:12.227281 u2DelayCellOfst[9]=3 cells (1 PI)
8462 15:36:12.230851 u2DelayCellOfst[10]=14 cells (4 PI)
8463 15:36:12.233563 u2DelayCellOfst[11]=7 cells (2 PI)
8464 15:36:12.237073 u2DelayCellOfst[12]=14 cells (4 PI)
8465 15:36:12.240427 u2DelayCellOfst[13]=18 cells (5 PI)
8466 15:36:12.240504 u2DelayCellOfst[14]=18 cells (5 PI)
8467 15:36:12.243752 u2DelayCellOfst[15]=18 cells (5 PI)
8468 15:36:12.250234 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8469 15:36:12.253655 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8470 15:36:12.256481 DramC Write-DBI on
8471 15:36:12.256566 ==
8472 15:36:12.260110 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 15:36:12.263442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 15:36:12.263543 ==
8475 15:36:12.263632
8476 15:36:12.263721
8477 15:36:12.266467 TX Vref Scan disable
8478 15:36:12.266560 == TX Byte 0 ==
8479 15:36:12.273351 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8480 15:36:12.273454 == TX Byte 1 ==
8481 15:36:12.276457 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8482 15:36:12.279782 DramC Write-DBI off
8483 15:36:12.279896
8484 15:36:12.280015 [DATLAT]
8485 15:36:12.283058 Freq=1600, CH1 RK0
8486 15:36:12.283144
8487 15:36:12.283209 DATLAT Default: 0xf
8488 15:36:12.286493 0, 0xFFFF, sum = 0
8489 15:36:12.289424 1, 0xFFFF, sum = 0
8490 15:36:12.289516 2, 0xFFFF, sum = 0
8491 15:36:12.292854 3, 0xFFFF, sum = 0
8492 15:36:12.292929 4, 0xFFFF, sum = 0
8493 15:36:12.296583 5, 0xFFFF, sum = 0
8494 15:36:12.296680 6, 0xFFFF, sum = 0
8495 15:36:12.299452 7, 0xFFFF, sum = 0
8496 15:36:12.299540 8, 0xFFFF, sum = 0
8497 15:36:12.302916 9, 0xFFFF, sum = 0
8498 15:36:12.302997 10, 0xFFFF, sum = 0
8499 15:36:12.306058 11, 0xFFFF, sum = 0
8500 15:36:12.306139 12, 0xFFFF, sum = 0
8501 15:36:12.309280 13, 0xFFFF, sum = 0
8502 15:36:12.309362 14, 0x0, sum = 1
8503 15:36:12.312487 15, 0x0, sum = 2
8504 15:36:12.312589 16, 0x0, sum = 3
8505 15:36:12.316065 17, 0x0, sum = 4
8506 15:36:12.316165 best_step = 15
8507 15:36:12.316256
8508 15:36:12.316334 ==
8509 15:36:12.319478 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 15:36:12.323203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 15:36:12.326081 ==
8512 15:36:12.326183 RX Vref Scan: 1
8513 15:36:12.326275
8514 15:36:12.329412 Set Vref Range= 24 -> 127
8515 15:36:12.329492
8516 15:36:12.332362 RX Vref 24 -> 127, step: 1
8517 15:36:12.332461
8518 15:36:12.332552 RX Delay 11 -> 252, step: 4
8519 15:36:12.332639
8520 15:36:12.335799 Set Vref, RX VrefLevel [Byte0]: 24
8521 15:36:12.339622 [Byte1]: 24
8522 15:36:12.343756
8523 15:36:12.343843 Set Vref, RX VrefLevel [Byte0]: 25
8524 15:36:12.346965 [Byte1]: 25
8525 15:36:12.350988
8526 15:36:12.351093 Set Vref, RX VrefLevel [Byte0]: 26
8527 15:36:12.354464 [Byte1]: 26
8528 15:36:12.358548
8529 15:36:12.358664 Set Vref, RX VrefLevel [Byte0]: 27
8530 15:36:12.361747 [Byte1]: 27
8531 15:36:12.366272
8532 15:36:12.366355 Set Vref, RX VrefLevel [Byte0]: 28
8533 15:36:12.369651 [Byte1]: 28
8534 15:36:12.373588
8535 15:36:12.373671 Set Vref, RX VrefLevel [Byte0]: 29
8536 15:36:12.377250 [Byte1]: 29
8537 15:36:12.381100
8538 15:36:12.381183 Set Vref, RX VrefLevel [Byte0]: 30
8539 15:36:12.384439 [Byte1]: 30
8540 15:36:12.388801
8541 15:36:12.392144 Set Vref, RX VrefLevel [Byte0]: 31
8542 15:36:12.395401 [Byte1]: 31
8543 15:36:12.395510
8544 15:36:12.398656 Set Vref, RX VrefLevel [Byte0]: 32
8545 15:36:12.401970 [Byte1]: 32
8546 15:36:12.402054
8547 15:36:12.405331 Set Vref, RX VrefLevel [Byte0]: 33
8548 15:36:12.408747 [Byte1]: 33
8549 15:36:12.412015
8550 15:36:12.412097 Set Vref, RX VrefLevel [Byte0]: 34
8551 15:36:12.415301 [Byte1]: 34
8552 15:36:12.419259
8553 15:36:12.419342 Set Vref, RX VrefLevel [Byte0]: 35
8554 15:36:12.423099 [Byte1]: 35
8555 15:36:12.427400
8556 15:36:12.427482 Set Vref, RX VrefLevel [Byte0]: 36
8557 15:36:12.430276 [Byte1]: 36
8558 15:36:12.434796
8559 15:36:12.434878 Set Vref, RX VrefLevel [Byte0]: 37
8560 15:36:12.437817 [Byte1]: 37
8561 15:36:12.442264
8562 15:36:12.442347 Set Vref, RX VrefLevel [Byte0]: 38
8563 15:36:12.445747 [Byte1]: 38
8564 15:36:12.449830
8565 15:36:12.449912 Set Vref, RX VrefLevel [Byte0]: 39
8566 15:36:12.454186 [Byte1]: 39
8567 15:36:12.457627
8568 15:36:12.457709 Set Vref, RX VrefLevel [Byte0]: 40
8569 15:36:12.460667 [Byte1]: 40
8570 15:36:12.465055
8571 15:36:12.465138 Set Vref, RX VrefLevel [Byte0]: 41
8572 15:36:12.468625 [Byte1]: 41
8573 15:36:12.473123
8574 15:36:12.473206 Set Vref, RX VrefLevel [Byte0]: 42
8575 15:36:12.475912 [Byte1]: 42
8576 15:36:12.480519
8577 15:36:12.480601 Set Vref, RX VrefLevel [Byte0]: 43
8578 15:36:12.483436 [Byte1]: 43
8579 15:36:12.487835
8580 15:36:12.487923 Set Vref, RX VrefLevel [Byte0]: 44
8581 15:36:12.491499 [Byte1]: 44
8582 15:36:12.495456
8583 15:36:12.495539 Set Vref, RX VrefLevel [Byte0]: 45
8584 15:36:12.498664 [Byte1]: 45
8585 15:36:12.503113
8586 15:36:12.503199 Set Vref, RX VrefLevel [Byte0]: 46
8587 15:36:12.506789 [Byte1]: 46
8588 15:36:12.510696
8589 15:36:12.510778 Set Vref, RX VrefLevel [Byte0]: 47
8590 15:36:12.514220 [Byte1]: 47
8591 15:36:12.518606
8592 15:36:12.518686 Set Vref, RX VrefLevel [Byte0]: 48
8593 15:36:12.521945 [Byte1]: 48
8594 15:36:12.525976
8595 15:36:12.526057 Set Vref, RX VrefLevel [Byte0]: 49
8596 15:36:12.529454 [Byte1]: 49
8597 15:36:12.533464
8598 15:36:12.533544 Set Vref, RX VrefLevel [Byte0]: 50
8599 15:36:12.536971 [Byte1]: 50
8600 15:36:12.541392
8601 15:36:12.541473 Set Vref, RX VrefLevel [Byte0]: 51
8602 15:36:12.544544 [Byte1]: 51
8603 15:36:12.548722
8604 15:36:12.548803 Set Vref, RX VrefLevel [Byte0]: 52
8605 15:36:12.552426 [Byte1]: 52
8606 15:36:12.556674
8607 15:36:12.556755 Set Vref, RX VrefLevel [Byte0]: 53
8608 15:36:12.559914 [Byte1]: 53
8609 15:36:12.564055
8610 15:36:12.564136 Set Vref, RX VrefLevel [Byte0]: 54
8611 15:36:12.567531 [Byte1]: 54
8612 15:36:12.571586
8613 15:36:12.571694 Set Vref, RX VrefLevel [Byte0]: 55
8614 15:36:12.575352 [Byte1]: 55
8615 15:36:12.579143
8616 15:36:12.579238 Set Vref, RX VrefLevel [Byte0]: 56
8617 15:36:12.582556 [Byte1]: 56
8618 15:36:12.587204
8619 15:36:12.587284 Set Vref, RX VrefLevel [Byte0]: 57
8620 15:36:12.590172 [Byte1]: 57
8621 15:36:12.594770
8622 15:36:12.594851 Set Vref, RX VrefLevel [Byte0]: 58
8623 15:36:12.598014 [Byte1]: 58
8624 15:36:12.601953
8625 15:36:12.602034 Set Vref, RX VrefLevel [Byte0]: 59
8626 15:36:12.605426 [Byte1]: 59
8627 15:36:12.609753
8628 15:36:12.609833 Set Vref, RX VrefLevel [Byte0]: 60
8629 15:36:12.612770 [Byte1]: 60
8630 15:36:12.617295
8631 15:36:12.617380 Set Vref, RX VrefLevel [Byte0]: 61
8632 15:36:12.620668 [Byte1]: 61
8633 15:36:12.624940
8634 15:36:12.625020 Set Vref, RX VrefLevel [Byte0]: 62
8635 15:36:12.628122 [Byte1]: 62
8636 15:36:12.632841
8637 15:36:12.632922 Set Vref, RX VrefLevel [Byte0]: 63
8638 15:36:12.635835 [Byte1]: 63
8639 15:36:12.640327
8640 15:36:12.640413 Set Vref, RX VrefLevel [Byte0]: 64
8641 15:36:12.643855 [Byte1]: 64
8642 15:36:12.647720
8643 15:36:12.647828 Set Vref, RX VrefLevel [Byte0]: 65
8644 15:36:12.651269 [Byte1]: 65
8645 15:36:12.655183
8646 15:36:12.655264 Set Vref, RX VrefLevel [Byte0]: 66
8647 15:36:12.658556 [Byte1]: 66
8648 15:36:12.663531
8649 15:36:12.663625 Set Vref, RX VrefLevel [Byte0]: 67
8650 15:36:12.666227 [Byte1]: 67
8651 15:36:12.671275
8652 15:36:12.671395 Set Vref, RX VrefLevel [Byte0]: 68
8653 15:36:12.673719 [Byte1]: 68
8654 15:36:12.678537
8655 15:36:12.678649 Set Vref, RX VrefLevel [Byte0]: 69
8656 15:36:12.681573 [Byte1]: 69
8657 15:36:12.686016
8658 15:36:12.686096 Set Vref, RX VrefLevel [Byte0]: 70
8659 15:36:12.689030 [Byte1]: 70
8660 15:36:12.693350
8661 15:36:12.693430 Final RX Vref Byte 0 = 54 to rank0
8662 15:36:12.696511 Final RX Vref Byte 1 = 62 to rank0
8663 15:36:12.700128 Final RX Vref Byte 0 = 54 to rank1
8664 15:36:12.703406 Final RX Vref Byte 1 = 62 to rank1==
8665 15:36:12.706665 Dram Type= 6, Freq= 0, CH_1, rank 0
8666 15:36:12.713063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8667 15:36:12.713145 ==
8668 15:36:12.713210 DQS Delay:
8669 15:36:12.716554 DQS0 = 0, DQS1 = 0
8670 15:36:12.716634 DQM Delay:
8671 15:36:12.716698 DQM0 = 132, DQM1 = 128
8672 15:36:12.719749 DQ Delay:
8673 15:36:12.723002 DQ0 =140, DQ1 =130, DQ2 =116, DQ3 =130
8674 15:36:12.726547 DQ4 =128, DQ5 =144, DQ6 =144, DQ7 =126
8675 15:36:12.729899 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8676 15:36:12.733123 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8677 15:36:12.733271
8678 15:36:12.733369
8679 15:36:12.733454
8680 15:36:12.736375 [DramC_TX_OE_Calibration] TA2
8681 15:36:12.739624 Original DQ_B0 (3 6) =30, OEN = 27
8682 15:36:12.742850 Original DQ_B1 (3 6) =30, OEN = 27
8683 15:36:12.746084 24, 0x0, End_B0=24 End_B1=24
8684 15:36:12.749711 25, 0x0, End_B0=25 End_B1=25
8685 15:36:12.749793 26, 0x0, End_B0=26 End_B1=26
8686 15:36:12.753122 27, 0x0, End_B0=27 End_B1=27
8687 15:36:12.756147 28, 0x0, End_B0=28 End_B1=28
8688 15:36:12.759582 29, 0x0, End_B0=29 End_B1=29
8689 15:36:12.759664 30, 0x0, End_B0=30 End_B1=30
8690 15:36:12.762782 31, 0x4141, End_B0=30 End_B1=30
8691 15:36:12.766117 Byte0 end_step=30 best_step=27
8692 15:36:12.769164 Byte1 end_step=30 best_step=27
8693 15:36:12.772498 Byte0 TX OE(2T, 0.5T) = (3, 3)
8694 15:36:12.775900 Byte1 TX OE(2T, 0.5T) = (3, 3)
8695 15:36:12.776022
8696 15:36:12.776099
8697 15:36:12.782589 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8698 15:36:12.785869 CH1 RK0: MR19=303, MR18=C16
8699 15:36:12.792247 CH1_RK0: MR19=0x303, MR18=0xC16, DQSOSC=398, MR23=63, INC=23, DEC=15
8700 15:36:12.792344
8701 15:36:12.795448 ----->DramcWriteLeveling(PI) begin...
8702 15:36:12.795530 ==
8703 15:36:12.799031 Dram Type= 6, Freq= 0, CH_1, rank 1
8704 15:36:12.802588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8705 15:36:12.802670 ==
8706 15:36:12.805551 Write leveling (Byte 0): 24 => 24
8707 15:36:12.808648 Write leveling (Byte 1): 25 => 25
8708 15:36:12.811930 DramcWriteLeveling(PI) end<-----
8709 15:36:12.812043
8710 15:36:12.812109 ==
8711 15:36:12.815589 Dram Type= 6, Freq= 0, CH_1, rank 1
8712 15:36:12.818483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8713 15:36:12.822444 ==
8714 15:36:12.822524 [Gating] SW mode calibration
8715 15:36:12.828759 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8716 15:36:12.835370 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8717 15:36:12.838747 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8718 15:36:12.845156 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8719 15:36:12.848030 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8720 15:36:12.851937 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8721 15:36:12.858622 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8722 15:36:12.861949 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8723 15:36:12.864917 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8724 15:36:12.871722 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8725 15:36:12.874982 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8726 15:36:12.877855 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8727 15:36:12.884608 1 5 8 | B1->B0 | 3434 2323 | 1 1 | (1 1) (1 0)
8728 15:36:12.888238 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8729 15:36:12.891472 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8730 15:36:12.898510 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 15:36:12.901117 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 15:36:12.904734 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8733 15:36:12.911113 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8734 15:36:12.914360 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8735 15:36:12.917399 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8736 15:36:12.924358 1 6 12 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8737 15:36:12.927338 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8738 15:36:12.930828 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8739 15:36:12.936992 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8740 15:36:12.940426 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8741 15:36:12.943878 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8742 15:36:12.950151 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8743 15:36:12.953867 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8744 15:36:12.957229 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8745 15:36:12.963465 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8746 15:36:12.966799 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 15:36:12.970021 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 15:36:12.976537 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 15:36:12.979850 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 15:36:12.983068 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 15:36:12.989902 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 15:36:12.992899 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 15:36:12.996725 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 15:36:13.002962 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 15:36:13.006340 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 15:36:13.010036 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 15:36:13.016228 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 15:36:13.019429 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8759 15:36:13.022887 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8760 15:36:13.029440 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8761 15:36:13.032903 Total UI for P1: 0, mck2ui 16
8762 15:36:13.035857 best dqsien dly found for B0: ( 1, 9, 6)
8763 15:36:13.039209 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 15:36:13.042825 Total UI for P1: 0, mck2ui 16
8765 15:36:13.046407 best dqsien dly found for B1: ( 1, 9, 12)
8766 15:36:13.049318 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8767 15:36:13.053113 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8768 15:36:13.053194
8769 15:36:13.055804 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8770 15:36:13.059224 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8771 15:36:13.062474 [Gating] SW calibration Done
8772 15:36:13.062555 ==
8773 15:36:13.065707 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 15:36:13.072568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 15:36:13.072650 ==
8776 15:36:13.072714 RX Vref Scan: 0
8777 15:36:13.072774
8778 15:36:13.075506 RX Vref 0 -> 0, step: 1
8779 15:36:13.075619
8780 15:36:13.079149 RX Delay 0 -> 252, step: 8
8781 15:36:13.082041 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8782 15:36:13.085493 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8783 15:36:13.088930 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8784 15:36:13.092093 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8785 15:36:13.098882 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8786 15:36:13.102286 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8787 15:36:13.105420 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8788 15:36:13.108444 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8789 15:36:13.115223 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8790 15:36:13.118716 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8791 15:36:13.121599 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8792 15:36:13.124890 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8793 15:36:13.128515 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8794 15:36:13.134770 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8795 15:36:13.138013 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8796 15:36:13.141806 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8797 15:36:13.141887 ==
8798 15:36:13.144804 Dram Type= 6, Freq= 0, CH_1, rank 1
8799 15:36:13.148071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 15:36:13.151195 ==
8801 15:36:13.151276 DQS Delay:
8802 15:36:13.151340 DQS0 = 0, DQS1 = 0
8803 15:36:13.154390 DQM Delay:
8804 15:36:13.154471 DQM0 = 133, DQM1 = 131
8805 15:36:13.157676 DQ Delay:
8806 15:36:13.161179 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8807 15:36:13.164283 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8808 15:36:13.167885 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8809 15:36:13.171832 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8810 15:36:13.171933
8811 15:36:13.172011
8812 15:36:13.172070 ==
8813 15:36:13.174174 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 15:36:13.177381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 15:36:13.180764 ==
8816 15:36:13.180844
8817 15:36:13.180908
8818 15:36:13.180967 TX Vref Scan disable
8819 15:36:13.184229 == TX Byte 0 ==
8820 15:36:13.187178 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8821 15:36:13.190654 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8822 15:36:13.194490 == TX Byte 1 ==
8823 15:36:13.197160 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8824 15:36:13.200490 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8825 15:36:13.203859 ==
8826 15:36:13.207165 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 15:36:13.210507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 15:36:13.210589 ==
8829 15:36:13.223290
8830 15:36:13.226796 TX Vref early break, caculate TX vref
8831 15:36:13.230605 TX Vref=16, minBit 9, minWin=21, winSum=376
8832 15:36:13.233160 TX Vref=18, minBit 9, minWin=22, winSum=386
8833 15:36:13.236498 TX Vref=20, minBit 9, minWin=22, winSum=391
8834 15:36:13.239875 TX Vref=22, minBit 9, minWin=22, winSum=403
8835 15:36:13.243293 TX Vref=24, minBit 9, minWin=24, winSum=410
8836 15:36:13.250112 TX Vref=26, minBit 9, minWin=24, winSum=418
8837 15:36:13.253075 TX Vref=28, minBit 9, minWin=25, winSum=420
8838 15:36:13.256530 TX Vref=30, minBit 9, minWin=25, winSum=420
8839 15:36:13.259967 TX Vref=32, minBit 9, minWin=24, winSum=408
8840 15:36:13.263244 TX Vref=34, minBit 9, minWin=23, winSum=401
8841 15:36:13.269611 TX Vref=36, minBit 8, minWin=23, winSum=393
8842 15:36:13.272904 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 28
8843 15:36:13.272986
8844 15:36:13.276344 Final TX Range 0 Vref 28
8845 15:36:13.276425
8846 15:36:13.276489 ==
8847 15:36:13.279483 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 15:36:13.282894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 15:36:13.282975 ==
8850 15:36:13.285895
8851 15:36:13.285976
8852 15:36:13.286039 TX Vref Scan disable
8853 15:36:13.292773 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8854 15:36:13.292854 == TX Byte 0 ==
8855 15:36:13.296011 u2DelayCellOfst[0]=14 cells (4 PI)
8856 15:36:13.299341 u2DelayCellOfst[1]=10 cells (3 PI)
8857 15:36:13.302857 u2DelayCellOfst[2]=0 cells (0 PI)
8858 15:36:13.305547 u2DelayCellOfst[3]=7 cells (2 PI)
8859 15:36:13.309128 u2DelayCellOfst[4]=10 cells (3 PI)
8860 15:36:13.312054 u2DelayCellOfst[5]=14 cells (4 PI)
8861 15:36:13.316074 u2DelayCellOfst[6]=18 cells (5 PI)
8862 15:36:13.319152 u2DelayCellOfst[7]=3 cells (1 PI)
8863 15:36:13.322330 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8864 15:36:13.325273 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8865 15:36:13.328759 == TX Byte 1 ==
8866 15:36:13.332234 u2DelayCellOfst[8]=0 cells (0 PI)
8867 15:36:13.335291 u2DelayCellOfst[9]=0 cells (0 PI)
8868 15:36:13.338641 u2DelayCellOfst[10]=10 cells (3 PI)
8869 15:36:13.341724 u2DelayCellOfst[11]=3 cells (1 PI)
8870 15:36:13.345103 u2DelayCellOfst[12]=14 cells (4 PI)
8871 15:36:13.348557 u2DelayCellOfst[13]=14 cells (4 PI)
8872 15:36:13.351916 u2DelayCellOfst[14]=18 cells (5 PI)
8873 15:36:13.355250 u2DelayCellOfst[15]=18 cells (5 PI)
8874 15:36:13.358671 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8875 15:36:13.361697 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8876 15:36:13.365159 DramC Write-DBI on
8877 15:36:13.365288 ==
8878 15:36:13.368775 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 15:36:13.371680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 15:36:13.371782 ==
8881 15:36:13.371874
8882 15:36:13.371972
8883 15:36:13.374984 TX Vref Scan disable
8884 15:36:13.375122 == TX Byte 0 ==
8885 15:36:13.382079 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8886 15:36:13.382199 == TX Byte 1 ==
8887 15:36:13.387706 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8888 15:36:13.387813 DramC Write-DBI off
8889 15:36:13.387931
8890 15:36:13.388010 [DATLAT]
8891 15:36:13.391333 Freq=1600, CH1 RK1
8892 15:36:13.391413
8893 15:36:13.394720 DATLAT Default: 0xf
8894 15:36:13.394824 0, 0xFFFF, sum = 0
8895 15:36:13.398064 1, 0xFFFF, sum = 0
8896 15:36:13.398166 2, 0xFFFF, sum = 0
8897 15:36:13.401437 3, 0xFFFF, sum = 0
8898 15:36:13.401539 4, 0xFFFF, sum = 0
8899 15:36:13.404408 5, 0xFFFF, sum = 0
8900 15:36:13.404493 6, 0xFFFF, sum = 0
8901 15:36:13.407625 7, 0xFFFF, sum = 0
8902 15:36:13.407736 8, 0xFFFF, sum = 0
8903 15:36:13.410995 9, 0xFFFF, sum = 0
8904 15:36:13.411111 10, 0xFFFF, sum = 0
8905 15:36:13.414614 11, 0xFFFF, sum = 0
8906 15:36:13.414725 12, 0xFFFF, sum = 0
8907 15:36:13.417836 13, 0xFFFF, sum = 0
8908 15:36:13.417920 14, 0x0, sum = 1
8909 15:36:13.421278 15, 0x0, sum = 2
8910 15:36:13.421389 16, 0x0, sum = 3
8911 15:36:13.424269 17, 0x0, sum = 4
8912 15:36:13.424344 best_step = 15
8913 15:36:13.424406
8914 15:36:13.424465 ==
8915 15:36:13.427754 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 15:36:13.434160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 15:36:13.434240 ==
8918 15:36:13.434303 RX Vref Scan: 0
8919 15:36:13.434362
8920 15:36:13.437468 RX Vref 0 -> 0, step: 1
8921 15:36:13.437537
8922 15:36:13.440581 RX Delay 19 -> 252, step: 4
8923 15:36:13.443684 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8924 15:36:13.447155 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8925 15:36:13.454067 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8926 15:36:13.456986 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8927 15:36:13.460315 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8928 15:36:13.463466 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8929 15:36:13.466955 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8930 15:36:13.473376 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8931 15:36:13.476881 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8932 15:36:13.480202 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8933 15:36:13.483571 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8934 15:36:13.486804 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8935 15:36:13.493221 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8936 15:36:13.496685 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8937 15:36:13.499566 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8938 15:36:13.502896 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8939 15:36:13.506329 ==
8940 15:36:13.506405 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 15:36:13.512739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 15:36:13.512815 ==
8943 15:36:13.512877 DQS Delay:
8944 15:36:13.516081 DQS0 = 0, DQS1 = 0
8945 15:36:13.516156 DQM Delay:
8946 15:36:13.519583 DQM0 = 131, DQM1 = 128
8947 15:36:13.519657 DQ Delay:
8948 15:36:13.522902 DQ0 =134, DQ1 =128, DQ2 =120, DQ3 =128
8949 15:36:13.526167 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
8950 15:36:13.529702 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
8951 15:36:13.532549 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =136
8952 15:36:13.532621
8953 15:36:13.532685
8954 15:36:13.532743
8955 15:36:13.536040 [DramC_TX_OE_Calibration] TA2
8956 15:36:13.539079 Original DQ_B0 (3 6) =30, OEN = 27
8957 15:36:13.542281 Original DQ_B1 (3 6) =30, OEN = 27
8958 15:36:13.545610 24, 0x0, End_B0=24 End_B1=24
8959 15:36:13.549114 25, 0x0, End_B0=25 End_B1=25
8960 15:36:13.549214 26, 0x0, End_B0=26 End_B1=26
8961 15:36:13.552336 27, 0x0, End_B0=27 End_B1=27
8962 15:36:13.555769 28, 0x0, End_B0=28 End_B1=28
8963 15:36:13.559261 29, 0x0, End_B0=29 End_B1=29
8964 15:36:13.562346 30, 0x0, End_B0=30 End_B1=30
8965 15:36:13.562449 31, 0x4141, End_B0=30 End_B1=30
8966 15:36:13.565575 Byte0 end_step=30 best_step=27
8967 15:36:13.568595 Byte1 end_step=30 best_step=27
8968 15:36:13.572179 Byte0 TX OE(2T, 0.5T) = (3, 3)
8969 15:36:13.575561 Byte1 TX OE(2T, 0.5T) = (3, 3)
8970 15:36:13.575659
8971 15:36:13.575757
8972 15:36:13.582043 [DQSOSCAuto] RK1, (LSB)MR18= 0x121f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
8973 15:36:13.585313 CH1 RK1: MR19=303, MR18=121F
8974 15:36:13.591476 CH1_RK1: MR19=0x303, MR18=0x121F, DQSOSC=394, MR23=63, INC=23, DEC=15
8975 15:36:13.595119 [RxdqsGatingPostProcess] freq 1600
8976 15:36:13.601387 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8977 15:36:13.604677 best DQS0 dly(2T, 0.5T) = (1, 1)
8978 15:36:13.608078 best DQS1 dly(2T, 0.5T) = (1, 1)
8979 15:36:13.608155 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8980 15:36:13.611573 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8981 15:36:13.615193 best DQS0 dly(2T, 0.5T) = (1, 1)
8982 15:36:13.618774 best DQS1 dly(2T, 0.5T) = (1, 1)
8983 15:36:13.621800 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8984 15:36:13.624975 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8985 15:36:13.628213 Pre-setting of DQS Precalculation
8986 15:36:13.634897 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8987 15:36:13.640964 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8988 15:36:13.648117 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8989 15:36:13.648228
8990 15:36:13.648307
8991 15:36:13.651081 [Calibration Summary] 3200 Mbps
8992 15:36:13.651162 CH 0, Rank 0
8993 15:36:13.654138 SW Impedance : PASS
8994 15:36:13.657961 DUTY Scan : NO K
8995 15:36:13.658043 ZQ Calibration : PASS
8996 15:36:13.661016 Jitter Meter : NO K
8997 15:36:13.664373 CBT Training : PASS
8998 15:36:13.664456 Write leveling : PASS
8999 15:36:13.667923 RX DQS gating : PASS
9000 15:36:13.671125 RX DQ/DQS(RDDQC) : PASS
9001 15:36:13.671207 TX DQ/DQS : PASS
9002 15:36:13.674482 RX DATLAT : PASS
9003 15:36:13.677704 RX DQ/DQS(Engine): PASS
9004 15:36:13.677812 TX OE : PASS
9005 15:36:13.677906 All Pass.
9006 15:36:13.680608
9007 15:36:13.680689 CH 0, Rank 1
9008 15:36:13.684008 SW Impedance : PASS
9009 15:36:13.684089 DUTY Scan : NO K
9010 15:36:13.687118 ZQ Calibration : PASS
9011 15:36:13.690694 Jitter Meter : NO K
9012 15:36:13.690775 CBT Training : PASS
9013 15:36:13.693867 Write leveling : PASS
9014 15:36:13.693947 RX DQS gating : PASS
9015 15:36:13.697016 RX DQ/DQS(RDDQC) : PASS
9016 15:36:13.700369 TX DQ/DQS : PASS
9017 15:36:13.700451 RX DATLAT : PASS
9018 15:36:13.703815 RX DQ/DQS(Engine): PASS
9019 15:36:13.707644 TX OE : PASS
9020 15:36:13.707725 All Pass.
9021 15:36:13.707790
9022 15:36:13.707850 CH 1, Rank 0
9023 15:36:13.710352 SW Impedance : PASS
9024 15:36:13.713843 DUTY Scan : NO K
9025 15:36:13.713954 ZQ Calibration : PASS
9026 15:36:13.716883 Jitter Meter : NO K
9027 15:36:13.720329 CBT Training : PASS
9028 15:36:13.720410 Write leveling : PASS
9029 15:36:13.723779 RX DQS gating : PASS
9030 15:36:13.727127 RX DQ/DQS(RDDQC) : PASS
9031 15:36:13.727208 TX DQ/DQS : PASS
9032 15:36:13.730480 RX DATLAT : PASS
9033 15:36:13.733271 RX DQ/DQS(Engine): PASS
9034 15:36:13.733352 TX OE : PASS
9035 15:36:13.736867 All Pass.
9036 15:36:13.736948
9037 15:36:13.737011 CH 1, Rank 1
9038 15:36:13.740202 SW Impedance : PASS
9039 15:36:13.740284 DUTY Scan : NO K
9040 15:36:13.743484 ZQ Calibration : PASS
9041 15:36:13.747072 Jitter Meter : NO K
9042 15:36:13.747153 CBT Training : PASS
9043 15:36:13.749829 Write leveling : PASS
9044 15:36:13.753262 RX DQS gating : PASS
9045 15:36:13.753343 RX DQ/DQS(RDDQC) : PASS
9046 15:36:13.756743 TX DQ/DQS : PASS
9047 15:36:13.759742 RX DATLAT : PASS
9048 15:36:13.759823 RX DQ/DQS(Engine): PASS
9049 15:36:13.763195 TX OE : PASS
9050 15:36:13.763276 All Pass.
9051 15:36:13.763340
9052 15:36:13.766742 DramC Write-DBI on
9053 15:36:13.769996 PER_BANK_REFRESH: Hybrid Mode
9054 15:36:13.770078 TX_TRACKING: ON
9055 15:36:13.779899 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9056 15:36:13.786170 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9057 15:36:13.792492 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9058 15:36:13.796090 [FAST_K] Save calibration result to emmc
9059 15:36:13.799213 sync common calibartion params.
9060 15:36:13.802419 sync cbt_mode0:1, 1:1
9061 15:36:13.805921 dram_init: ddr_geometry: 2
9062 15:36:13.806004 dram_init: ddr_geometry: 2
9063 15:36:13.808860 dram_init: ddr_geometry: 2
9064 15:36:13.812369 0:dram_rank_size:100000000
9065 15:36:13.815838 1:dram_rank_size:100000000
9066 15:36:13.819021 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9067 15:36:13.822146 DFS_SHUFFLE_HW_MODE: ON
9068 15:36:13.825853 dramc_set_vcore_voltage set vcore to 725000
9069 15:36:13.828595 Read voltage for 1600, 0
9070 15:36:13.828676 Vio18 = 0
9071 15:36:13.828739 Vcore = 725000
9072 15:36:13.832119 Vdram = 0
9073 15:36:13.832200 Vddq = 0
9074 15:36:13.832279 Vmddr = 0
9075 15:36:13.835794 switch to 3200 Mbps bootup
9076 15:36:13.838566 [DramcRunTimeConfig]
9077 15:36:13.838648 PHYPLL
9078 15:36:13.838712 DPM_CONTROL_AFTERK: ON
9079 15:36:13.842274 PER_BANK_REFRESH: ON
9080 15:36:13.845639 REFRESH_OVERHEAD_REDUCTION: ON
9081 15:36:13.849054 CMD_PICG_NEW_MODE: OFF
9082 15:36:13.849134 XRTWTW_NEW_MODE: ON
9083 15:36:13.852484 XRTRTR_NEW_MODE: ON
9084 15:36:13.852638 TX_TRACKING: ON
9085 15:36:13.855124 RDSEL_TRACKING: OFF
9086 15:36:13.855205 DQS Precalculation for DVFS: ON
9087 15:36:13.858321 RX_TRACKING: OFF
9088 15:36:13.858401 HW_GATING DBG: ON
9089 15:36:13.861574 ZQCS_ENABLE_LP4: ON
9090 15:36:13.865063 RX_PICG_NEW_MODE: ON
9091 15:36:13.865144 TX_PICG_NEW_MODE: ON
9092 15:36:13.868339 ENABLE_RX_DCM_DPHY: ON
9093 15:36:13.871946 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9094 15:36:13.872056 DUMMY_READ_FOR_TRACKING: OFF
9095 15:36:13.874998 !!! SPM_CONTROL_AFTERK: OFF
9096 15:36:13.877928 !!! SPM could not control APHY
9097 15:36:13.881617 IMPEDANCE_TRACKING: ON
9098 15:36:13.881698 TEMP_SENSOR: ON
9099 15:36:13.885120 HW_SAVE_FOR_SR: OFF
9100 15:36:13.888263 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9101 15:36:13.891607 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9102 15:36:13.891710 Read ODT Tracking: ON
9103 15:36:13.894509 Refresh Rate DeBounce: ON
9104 15:36:13.898036 DFS_NO_QUEUE_FLUSH: ON
9105 15:36:13.901539 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9106 15:36:13.901636 ENABLE_DFS_RUNTIME_MRW: OFF
9107 15:36:13.904405 DDR_RESERVE_NEW_MODE: ON
9108 15:36:13.907805 MR_CBT_SWITCH_FREQ: ON
9109 15:36:13.907901 =========================
9110 15:36:13.928051 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9111 15:36:13.931174 dram_init: ddr_geometry: 2
9112 15:36:13.949403 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9113 15:36:13.952955 dram_init: dram init end (result: 0)
9114 15:36:13.959239 DRAM-K: Full calibration passed in 24413 msecs
9115 15:36:13.962831 MRC: failed to locate region type 0.
9116 15:36:13.962913 DRAM rank0 size:0x100000000,
9117 15:36:13.965794 DRAM rank1 size=0x100000000
9118 15:36:13.975651 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9119 15:36:13.982452 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9120 15:36:13.989349 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9121 15:36:13.999143 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9122 15:36:13.999224 DRAM rank0 size:0x100000000,
9123 15:36:14.002308 DRAM rank1 size=0x100000000
9124 15:36:14.002390 CBMEM:
9125 15:36:14.005294 IMD: root @ 0xfffff000 254 entries.
9126 15:36:14.008822 IMD: root @ 0xffffec00 62 entries.
9127 15:36:14.012216 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9128 15:36:14.018682 WARNING: RO_VPD is uninitialized or empty.
9129 15:36:14.022016 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9130 15:36:14.029894 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9131 15:36:14.042248 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9132 15:36:14.054099 BS: romstage times (exec / console): total (unknown) / 23947 ms
9133 15:36:14.054182
9134 15:36:14.054245
9135 15:36:14.063804 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9136 15:36:14.066968 ARM64: Exception handlers installed.
9137 15:36:14.070749 ARM64: Testing exception
9138 15:36:14.073507 ARM64: Done test exception
9139 15:36:14.073607 Enumerating buses...
9140 15:36:14.076921 Show all devs... Before device enumeration.
9141 15:36:14.080410 Root Device: enabled 1
9142 15:36:14.083689 CPU_CLUSTER: 0: enabled 1
9143 15:36:14.083789 CPU: 00: enabled 1
9144 15:36:14.087009 Compare with tree...
9145 15:36:14.087110 Root Device: enabled 1
9146 15:36:14.090153 CPU_CLUSTER: 0: enabled 1
9147 15:36:14.093553 CPU: 00: enabled 1
9148 15:36:14.093628 Root Device scanning...
9149 15:36:14.096645 scan_static_bus for Root Device
9150 15:36:14.099848 CPU_CLUSTER: 0 enabled
9151 15:36:14.103071 scan_static_bus for Root Device done
9152 15:36:14.106550 scan_bus: bus Root Device finished in 8 msecs
9153 15:36:14.106652 done
9154 15:36:14.112767 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9155 15:36:14.116420 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9156 15:36:14.122846 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9157 15:36:14.129584 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9158 15:36:14.129660 Allocating resources...
9159 15:36:14.132940 Reading resources...
9160 15:36:14.135885 Root Device read_resources bus 0 link: 0
9161 15:36:14.139463 DRAM rank0 size:0x100000000,
9162 15:36:14.139567 DRAM rank1 size=0x100000000
9163 15:36:14.146097 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9164 15:36:14.146180 CPU: 00 missing read_resources
9165 15:36:14.152587 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9166 15:36:14.155523 Root Device read_resources bus 0 link: 0 done
9167 15:36:14.158956 Done reading resources.
9168 15:36:14.162282 Show resources in subtree (Root Device)...After reading.
9169 15:36:14.165600 Root Device child on link 0 CPU_CLUSTER: 0
9170 15:36:14.168902 CPU_CLUSTER: 0 child on link 0 CPU: 00
9171 15:36:14.179015 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9172 15:36:14.179122 CPU: 00
9173 15:36:14.185510 Root Device assign_resources, bus 0 link: 0
9174 15:36:14.188801 CPU_CLUSTER: 0 missing set_resources
9175 15:36:14.191667 Root Device assign_resources, bus 0 link: 0 done
9176 15:36:14.194988 Done setting resources.
9177 15:36:14.198873 Show resources in subtree (Root Device)...After assigning values.
9178 15:36:14.204872 Root Device child on link 0 CPU_CLUSTER: 0
9179 15:36:14.208527 CPU_CLUSTER: 0 child on link 0 CPU: 00
9180 15:36:14.215065 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9181 15:36:14.218080 CPU: 00
9182 15:36:14.218163 Done allocating resources.
9183 15:36:14.224515 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9184 15:36:14.227997 Enabling resources...
9185 15:36:14.228082 done.
9186 15:36:14.231253 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9187 15:36:14.235023 Initializing devices...
9188 15:36:14.235106 Root Device init
9189 15:36:14.238215 init hardware done!
9190 15:36:14.241110 0x00000018: ctrlr->caps
9191 15:36:14.241195 52.000 MHz: ctrlr->f_max
9192 15:36:14.244647 0.400 MHz: ctrlr->f_min
9193 15:36:14.248216 0x40ff8080: ctrlr->voltages
9194 15:36:14.248299 sclk: 390625
9195 15:36:14.248364 Bus Width = 1
9196 15:36:14.251155 sclk: 390625
9197 15:36:14.251295 Bus Width = 1
9198 15:36:14.254608 Early init status = 3
9199 15:36:14.257655 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9200 15:36:14.262598 in-header: 03 fc 00 00 01 00 00 00
9201 15:36:14.265820 in-data: 00
9202 15:36:14.269147 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9203 15:36:14.274857 in-header: 03 fd 00 00 00 00 00 00
9204 15:36:14.277703 in-data:
9205 15:36:14.281100 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9206 15:36:14.285790 in-header: 03 fc 00 00 01 00 00 00
9207 15:36:14.288962 in-data: 00
9208 15:36:14.292055 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9209 15:36:14.297669 in-header: 03 fd 00 00 00 00 00 00
9210 15:36:14.300958 in-data:
9211 15:36:14.304205 [SSUSB] Setting up USB HOST controller...
9212 15:36:14.307701 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9213 15:36:14.311217 [SSUSB] phy power-on done.
9214 15:36:14.314466 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9215 15:36:14.320875 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9216 15:36:14.324325 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9217 15:36:14.330687 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9218 15:36:14.337149 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9219 15:36:14.343706 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9220 15:36:14.350904 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9221 15:36:14.356918 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9222 15:36:14.360266 SPM: binary array size = 0x9dc
9223 15:36:14.363865 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9224 15:36:14.370470 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9225 15:36:14.376623 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9226 15:36:14.383556 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9227 15:36:14.386471 configure_display: Starting display init
9228 15:36:14.421272 anx7625_power_on_init: Init interface.
9229 15:36:14.424590 anx7625_disable_pd_protocol: Disabled PD feature.
9230 15:36:14.427535 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9231 15:36:14.455162 anx7625_start_dp_work: Secure OCM version=00
9232 15:36:14.458737 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9233 15:36:14.473497 sp_tx_get_edid_block: EDID Block = 1
9234 15:36:14.576127 Extracted contents:
9235 15:36:14.579551 header: 00 ff ff ff ff ff ff 00
9236 15:36:14.582694 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9237 15:36:14.585875 version: 01 04
9238 15:36:14.589125 basic params: 95 1f 11 78 0a
9239 15:36:14.592874 chroma info: 76 90 94 55 54 90 27 21 50 54
9240 15:36:14.595578 established: 00 00 00
9241 15:36:14.602258 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9242 15:36:14.609049 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9243 15:36:14.612284 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9244 15:36:14.619100 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9245 15:36:14.625792 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9246 15:36:14.628833 extensions: 00
9247 15:36:14.628907 checksum: fb
9248 15:36:14.628969
9249 15:36:14.635723 Manufacturer: IVO Model 57d Serial Number 0
9250 15:36:14.635825 Made week 0 of 2020
9251 15:36:14.638476 EDID version: 1.4
9252 15:36:14.638548 Digital display
9253 15:36:14.642288 6 bits per primary color channel
9254 15:36:14.645231 DisplayPort interface
9255 15:36:14.645307 Maximum image size: 31 cm x 17 cm
9256 15:36:14.648990 Gamma: 220%
9257 15:36:14.649068 Check DPMS levels
9258 15:36:14.655058 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9259 15:36:14.658214 First detailed timing is preferred timing
9260 15:36:14.661490 Established timings supported:
9261 15:36:14.661564 Standard timings supported:
9262 15:36:14.664880 Detailed timings
9263 15:36:14.668465 Hex of detail: 383680a07038204018303c0035ae10000019
9264 15:36:14.675225 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9265 15:36:14.678063 0780 0798 07c8 0820 hborder 0
9266 15:36:14.681578 0438 043b 0447 0458 vborder 0
9267 15:36:14.684679 -hsync -vsync
9268 15:36:14.684752 Did detailed timing
9269 15:36:14.691348 Hex of detail: 000000000000000000000000000000000000
9270 15:36:14.694530 Manufacturer-specified data, tag 0
9271 15:36:14.697865 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9272 15:36:14.701320 ASCII string: InfoVision
9273 15:36:14.704772 Hex of detail: 000000fe00523134304e574635205248200a
9274 15:36:14.708320 ASCII string: R140NWF5 RH
9275 15:36:14.708400 Checksum
9276 15:36:14.711205 Checksum: 0xfb (valid)
9277 15:36:14.715107 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9278 15:36:14.717921 DSI data_rate: 832800000 bps
9279 15:36:14.724641 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9280 15:36:14.728132 anx7625_parse_edid: pixelclock(138800).
9281 15:36:14.730955 hactive(1920), hsync(48), hfp(24), hbp(88)
9282 15:36:14.734607 vactive(1080), vsync(12), vfp(3), vbp(17)
9283 15:36:14.737577 anx7625_dsi_config: config dsi.
9284 15:36:14.744134 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9285 15:36:14.758165 anx7625_dsi_config: success to config DSI
9286 15:36:14.761269 anx7625_dp_start: MIPI phy setup OK.
9287 15:36:14.765071 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9288 15:36:14.768140 mtk_ddp_mode_set invalid vrefresh 60
9289 15:36:14.771393 main_disp_path_setup
9290 15:36:14.771471 ovl_layer_smi_id_en
9291 15:36:14.774712 ovl_layer_smi_id_en
9292 15:36:14.774786 ccorr_config
9293 15:36:14.774855 aal_config
9294 15:36:14.777775 gamma_config
9295 15:36:14.777841 postmask_config
9296 15:36:14.781804 dither_config
9297 15:36:14.784381 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9298 15:36:14.791181 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9299 15:36:14.794002 Root Device init finished in 555 msecs
9300 15:36:14.797558 CPU_CLUSTER: 0 init
9301 15:36:14.804924 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9302 15:36:14.811084 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9303 15:36:14.811165 APU_MBOX 0x190000b0 = 0x10001
9304 15:36:14.813946 APU_MBOX 0x190001b0 = 0x10001
9305 15:36:14.817415 APU_MBOX 0x190005b0 = 0x10001
9306 15:36:14.820672 APU_MBOX 0x190006b0 = 0x10001
9307 15:36:14.827237 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9308 15:36:14.837166 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9309 15:36:14.849566 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9310 15:36:14.856078 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9311 15:36:14.867572 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9312 15:36:14.876644 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9313 15:36:14.880121 CPU_CLUSTER: 0 init finished in 81 msecs
9314 15:36:14.883440 Devices initialized
9315 15:36:14.886792 Show all devs... After init.
9316 15:36:14.886869 Root Device: enabled 1
9317 15:36:14.890009 CPU_CLUSTER: 0: enabled 1
9318 15:36:14.893518 CPU: 00: enabled 1
9319 15:36:14.896621 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9320 15:36:14.900027 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9321 15:36:14.903666 ELOG: NV offset 0x57f000 size 0x1000
9322 15:36:14.910003 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9323 15:36:14.916839 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9324 15:36:14.919669 ELOG: Event(17) added with size 13 at 2023-08-22 15:36:19 UTC
9325 15:36:14.926630 out: cmd=0x121: 03 db 21 01 00 00 00 00
9326 15:36:14.929754 in-header: 03 37 00 00 2c 00 00 00
9327 15:36:14.939877 in-data: 28 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9328 15:36:14.946405 ELOG: Event(A1) added with size 10 at 2023-08-22 15:36:19 UTC
9329 15:36:14.952738 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9330 15:36:14.959192 ELOG: Event(A0) added with size 9 at 2023-08-22 15:36:19 UTC
9331 15:36:14.962846 elog_add_boot_reason: Logged dev mode boot
9332 15:36:14.969662 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9333 15:36:14.969770 Finalize devices...
9334 15:36:14.972441 Devices finalized
9335 15:36:14.976036 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9336 15:36:14.979228 Writing coreboot table at 0xffe64000
9337 15:36:14.982978 0. 000000000010a000-0000000000113fff: RAMSTAGE
9338 15:36:14.989072 1. 0000000040000000-00000000400fffff: RAM
9339 15:36:14.992436 2. 0000000040100000-000000004032afff: RAMSTAGE
9340 15:36:14.995743 3. 000000004032b000-00000000545fffff: RAM
9341 15:36:14.999062 4. 0000000054600000-000000005465ffff: BL31
9342 15:36:15.001825 5. 0000000054660000-00000000ffe63fff: RAM
9343 15:36:15.008775 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9344 15:36:15.012044 7. 0000000100000000-000000023fffffff: RAM
9345 15:36:15.015309 Passing 5 GPIOs to payload:
9346 15:36:15.018727 NAME | PORT | POLARITY | VALUE
9347 15:36:15.025128 EC in RW | 0x000000aa | low | undefined
9348 15:36:15.028787 EC interrupt | 0x00000005 | low | undefined
9349 15:36:15.035156 TPM interrupt | 0x000000ab | high | undefined
9350 15:36:15.038445 SD card detect | 0x00000011 | high | undefined
9351 15:36:15.041580 speaker enable | 0x00000093 | high | undefined
9352 15:36:15.044650 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9353 15:36:15.049122 in-header: 03 f9 00 00 02 00 00 00
9354 15:36:15.052507 in-data: 02 00
9355 15:36:15.055703 ADC[4]: Raw value=903325 ID=7
9356 15:36:15.059016 ADC[3]: Raw value=213546 ID=1
9357 15:36:15.059088 RAM Code: 0x71
9358 15:36:15.062395 ADC[6]: Raw value=75000 ID=0
9359 15:36:15.065902 ADC[5]: Raw value=213177 ID=1
9360 15:36:15.065970 SKU Code: 0x1
9361 15:36:15.072549 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 955a
9362 15:36:15.072624 coreboot table: 964 bytes.
9363 15:36:15.076204 IMD ROOT 0. 0xfffff000 0x00001000
9364 15:36:15.078829 IMD SMALL 1. 0xffffe000 0x00001000
9365 15:36:15.082860 RO MCACHE 2. 0xffffc000 0x00001104
9366 15:36:15.085698 CONSOLE 3. 0xfff7c000 0x00080000
9367 15:36:15.089067 FMAP 4. 0xfff7b000 0x00000452
9368 15:36:15.092302 TIME STAMP 5. 0xfff7a000 0x00000910
9369 15:36:15.095184 VBOOT WORK 6. 0xfff66000 0x00014000
9370 15:36:15.098951 RAMOOPS 7. 0xffe66000 0x00100000
9371 15:36:15.102211 COREBOOT 8. 0xffe64000 0x00002000
9372 15:36:15.105615 IMD small region:
9373 15:36:15.108432 IMD ROOT 0. 0xffffec00 0x00000400
9374 15:36:15.111944 VPD 1. 0xffffeb80 0x0000006c
9375 15:36:15.115246 MMC STATUS 2. 0xffffeb60 0x00000004
9376 15:36:15.121794 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9377 15:36:15.121924 Probing TPM: done!
9378 15:36:15.128921 Connected to device vid:did:rid of 1ae0:0028:00
9379 15:36:15.135336 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9380 15:36:15.138802 Initialized TPM device CR50 revision 0
9381 15:36:15.141953 Checking cr50 for pending updates
9382 15:36:15.147530 Reading cr50 TPM mode
9383 15:36:15.156103 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9384 15:36:15.162729 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9385 15:36:15.202556 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9386 15:36:15.205950 Checking segment from ROM address 0x40100000
9387 15:36:15.209479 Checking segment from ROM address 0x4010001c
9388 15:36:15.215763 Loading segment from ROM address 0x40100000
9389 15:36:15.215869 code (compression=0)
9390 15:36:15.225778 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9391 15:36:15.232480 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9392 15:36:15.232570 it's not compressed!
9393 15:36:15.239252 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9394 15:36:15.245434 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9395 15:36:15.263552 Loading segment from ROM address 0x4010001c
9396 15:36:15.263636 Entry Point 0x80000000
9397 15:36:15.266842 Loaded segments
9398 15:36:15.270147 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9399 15:36:15.276352 Jumping to boot code at 0x80000000(0xffe64000)
9400 15:36:15.283139 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9401 15:36:15.289842 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9402 15:36:15.297544 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9403 15:36:15.300874 Checking segment from ROM address 0x40100000
9404 15:36:15.304339 Checking segment from ROM address 0x4010001c
9405 15:36:15.310762 Loading segment from ROM address 0x40100000
9406 15:36:15.310842 code (compression=1)
9407 15:36:15.317308 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9408 15:36:15.327114 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9409 15:36:15.327219 using LZMA
9410 15:36:15.335897 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9411 15:36:15.342641 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9412 15:36:15.345574 Loading segment from ROM address 0x4010001c
9413 15:36:15.348753 Entry Point 0x54601000
9414 15:36:15.348830 Loaded segments
9415 15:36:15.352289 NOTICE: MT8192 bl31_setup
9416 15:36:15.359836 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9417 15:36:15.362667 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9418 15:36:15.366251 WARNING: region 0:
9419 15:36:15.369460 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9420 15:36:15.369566 WARNING: region 1:
9421 15:36:15.376638 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9422 15:36:15.379717 WARNING: region 2:
9423 15:36:15.382817 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9424 15:36:15.385871 WARNING: region 3:
9425 15:36:15.389161 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9426 15:36:15.393136 WARNING: region 4:
9427 15:36:15.399580 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9428 15:36:15.399686 WARNING: region 5:
9429 15:36:15.402798 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9430 15:36:15.406067 WARNING: region 6:
9431 15:36:15.409268 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9432 15:36:15.412976 WARNING: region 7:
9433 15:36:15.415877 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9434 15:36:15.422239 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9435 15:36:15.425636 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9436 15:36:15.429017 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9437 15:36:15.435625 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9438 15:36:15.439514 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9439 15:36:15.445970 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9440 15:36:15.448864 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9441 15:36:15.452192 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9442 15:36:15.459056 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9443 15:36:15.462639 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9444 15:36:15.465465 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9445 15:36:15.472263 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9446 15:36:15.475496 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9447 15:36:15.482337 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9448 15:36:15.485995 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9449 15:36:15.488850 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9450 15:36:15.495599 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9451 15:36:15.499054 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9452 15:36:15.502451 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9453 15:36:15.508838 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9454 15:36:15.512073 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9455 15:36:15.518957 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9456 15:36:15.522282 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9457 15:36:15.525264 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9458 15:36:15.532116 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9459 15:36:15.535376 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9460 15:36:15.542474 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9461 15:36:15.545284 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9462 15:36:15.548677 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9463 15:36:15.555646 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9464 15:36:15.558871 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9465 15:36:15.565299 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9466 15:36:15.568758 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9467 15:36:15.571839 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9468 15:36:15.575457 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9469 15:36:15.581856 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9470 15:36:15.585447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9471 15:36:15.588543 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9472 15:36:15.592102 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9473 15:36:15.598317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9474 15:36:15.602176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9475 15:36:15.605418 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9476 15:36:15.608453 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9477 15:36:15.615466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9478 15:36:15.618438 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9479 15:36:15.621714 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9480 15:36:15.625166 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9481 15:36:15.631746 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9482 15:36:15.635148 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9483 15:36:15.641702 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9484 15:36:15.644901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9485 15:36:15.648165 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9486 15:36:15.654821 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9487 15:36:15.658339 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9488 15:36:15.664891 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9489 15:36:15.667965 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9490 15:36:15.674854 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9491 15:36:15.678177 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9492 15:36:15.681617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9493 15:36:15.688019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9494 15:36:15.691265 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9495 15:36:15.697976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9496 15:36:15.701728 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9497 15:36:15.708231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9498 15:36:15.711253 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9499 15:36:15.715006 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9500 15:36:15.721078 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9501 15:36:15.724527 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9502 15:36:15.731463 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9503 15:36:15.734970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9504 15:36:15.741066 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9505 15:36:15.744788 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9506 15:36:15.751054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9507 15:36:15.754566 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9508 15:36:15.758033 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9509 15:36:15.764314 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9510 15:36:15.767603 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9511 15:36:15.774502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9512 15:36:15.778209 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9513 15:36:15.784215 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9514 15:36:15.787758 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9515 15:36:15.794157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9516 15:36:15.797386 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9517 15:36:15.801232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9518 15:36:15.807468 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9519 15:36:15.810735 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9520 15:36:15.817400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9521 15:36:15.820940 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9522 15:36:15.827224 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9523 15:36:15.830935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9524 15:36:15.833925 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9525 15:36:15.840672 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9526 15:36:15.844186 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9527 15:36:15.850722 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9528 15:36:15.854219 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9529 15:36:15.860475 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9530 15:36:15.863751 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9531 15:36:15.867488 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9532 15:36:15.870631 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9533 15:36:15.877237 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9534 15:36:15.881143 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9535 15:36:15.884237 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9536 15:36:15.890484 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9537 15:36:15.894475 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9538 15:36:15.900525 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9539 15:36:15.903765 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9540 15:36:15.907324 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9541 15:36:15.913829 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9542 15:36:15.917800 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9543 15:36:15.924003 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9544 15:36:15.927846 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9545 15:36:15.930423 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9546 15:36:15.937748 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9547 15:36:15.940299 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9548 15:36:15.947091 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9549 15:36:15.950662 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9550 15:36:15.953542 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9551 15:36:15.956904 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9552 15:36:15.963685 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9553 15:36:15.967024 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9554 15:36:15.970475 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9555 15:36:15.973941 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9556 15:36:15.980785 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9557 15:36:15.983546 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9558 15:36:15.986983 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9559 15:36:15.993871 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9560 15:36:15.997608 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9561 15:36:16.003668 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9562 15:36:16.006955 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9563 15:36:16.010455 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9564 15:36:16.017099 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9565 15:36:16.020619 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9566 15:36:16.027239 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9567 15:36:16.030540 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9568 15:36:16.033553 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9569 15:36:16.040558 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9570 15:36:16.043759 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9571 15:36:16.047576 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9572 15:36:16.054021 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9573 15:36:16.057180 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9574 15:36:16.063331 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9575 15:36:16.066969 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9576 15:36:16.070021 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9577 15:36:16.077276 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9578 15:36:16.079868 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9579 15:36:16.086972 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9580 15:36:16.089815 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9581 15:36:16.093165 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9582 15:36:16.099780 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9583 15:36:16.103394 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9584 15:36:16.109942 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9585 15:36:16.113377 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9586 15:36:16.116745 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9587 15:36:16.123006 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9588 15:36:16.126361 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9589 15:36:16.133034 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9590 15:36:16.136385 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9591 15:36:16.140046 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9592 15:36:16.146576 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9593 15:36:16.149721 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9594 15:36:16.156170 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9595 15:36:16.159598 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9596 15:36:16.162766 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9597 15:36:16.169605 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9598 15:36:16.172979 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9599 15:36:16.179488 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9600 15:36:16.182408 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9601 15:36:16.185752 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9602 15:36:16.192614 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9603 15:36:16.195660 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9604 15:36:16.202571 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9605 15:36:16.205824 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9606 15:36:16.209252 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9607 15:36:16.215296 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9608 15:36:16.218773 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9609 15:36:16.225339 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9610 15:36:16.228397 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9611 15:36:16.231768 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9612 15:36:16.238559 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9613 15:36:16.241624 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9614 15:36:16.248353 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9615 15:36:16.251801 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9616 15:36:16.255479 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9617 15:36:16.261451 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9618 15:36:16.264889 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9619 15:36:16.271186 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9620 15:36:16.274496 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9621 15:36:16.278013 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9622 15:36:16.284560 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9623 15:36:16.287705 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9624 15:36:16.294263 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9625 15:36:16.297651 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9626 15:36:16.304135 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9627 15:36:16.307464 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9628 15:36:16.310585 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9629 15:36:16.317276 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9630 15:36:16.320748 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9631 15:36:16.327405 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9632 15:36:16.330643 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9633 15:36:16.336898 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9634 15:36:16.340261 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9635 15:36:16.343734 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9636 15:36:16.350255 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9637 15:36:16.353724 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9638 15:36:16.360145 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9639 15:36:16.363273 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9640 15:36:16.369702 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9641 15:36:16.373233 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9642 15:36:16.376488 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9643 15:36:16.383152 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9644 15:36:16.386476 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9645 15:36:16.393233 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9646 15:36:16.396263 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9647 15:36:16.402874 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9648 15:36:16.406546 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9649 15:36:16.409369 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9650 15:36:16.416511 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9651 15:36:16.419262 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9652 15:36:16.426260 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9653 15:36:16.429517 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9654 15:36:16.436008 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9655 15:36:16.438920 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9656 15:36:16.442223 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9657 15:36:16.448955 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9658 15:36:16.452639 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9659 15:36:16.458830 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9660 15:36:16.462588 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9661 15:36:16.469115 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9662 15:36:16.472036 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9663 15:36:16.475631 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9664 15:36:16.478633 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9665 15:36:16.485283 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9666 15:36:16.488808 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9667 15:36:16.492334 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9668 15:36:16.498750 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9669 15:36:16.501406 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9670 15:36:16.504855 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9671 15:36:16.511201 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9672 15:36:16.514736 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9673 15:36:16.518175 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9674 15:36:16.524762 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9675 15:36:16.527762 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9676 15:36:16.534631 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9677 15:36:16.538115 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9678 15:36:16.541023 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9679 15:36:16.547847 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9680 15:36:16.550982 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9681 15:36:16.557748 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9682 15:36:16.561116 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9683 15:36:16.564580 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9684 15:36:16.571015 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9685 15:36:16.574071 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9686 15:36:16.577252 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9687 15:36:16.584388 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9688 15:36:16.587507 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9689 15:36:16.593724 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9690 15:36:16.597447 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9691 15:36:16.600178 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9692 15:36:16.607009 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9693 15:36:16.610106 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9694 15:36:16.613541 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9695 15:36:16.620527 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9696 15:36:16.623531 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9697 15:36:16.626777 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9698 15:36:16.633430 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9699 15:36:16.636490 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9700 15:36:16.643942 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9701 15:36:16.646743 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9702 15:36:16.650402 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9703 15:36:16.656255 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9704 15:36:16.659650 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9705 15:36:16.662746 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9706 15:36:16.666440 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9707 15:36:16.669668 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9708 15:36:16.676967 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9709 15:36:16.679664 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9710 15:36:16.682688 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9711 15:36:16.689293 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9712 15:36:16.692693 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9713 15:36:16.695773 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9714 15:36:16.699628 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9715 15:36:16.705907 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9716 15:36:16.708919 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9717 15:36:16.716384 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9718 15:36:16.719558 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9719 15:36:16.722225 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9720 15:36:16.729145 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9721 15:36:16.732610 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9722 15:36:16.738846 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9723 15:36:16.742224 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9724 15:36:16.745726 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9725 15:36:16.752258 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9726 15:36:16.755363 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9727 15:36:16.761785 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9728 15:36:16.765429 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9729 15:36:16.772049 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9730 15:36:16.775509 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9731 15:36:16.778617 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9732 15:36:16.785503 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9733 15:36:16.788628 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9734 15:36:16.795378 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9735 15:36:16.798109 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9736 15:36:16.804648 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9737 15:36:16.808284 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9738 15:36:16.811040 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9739 15:36:16.817937 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9740 15:36:16.821175 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9741 15:36:16.828083 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9742 15:36:16.830952 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9743 15:36:16.834155 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9744 15:36:16.841168 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9745 15:36:16.844202 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9746 15:36:16.851081 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9747 15:36:16.854395 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9748 15:36:16.857286 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9749 15:36:16.864217 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9750 15:36:16.867722 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9751 15:36:16.873838 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9752 15:36:16.877183 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9753 15:36:16.884112 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9754 15:36:16.887510 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9755 15:36:16.890183 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9756 15:36:16.897056 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9757 15:36:16.900899 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9758 15:36:16.906621 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9759 15:36:16.910116 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9760 15:36:16.916537 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9761 15:36:16.919772 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9762 15:36:16.923080 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9763 15:36:16.930274 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9764 15:36:16.933444 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9765 15:36:16.939932 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9766 15:36:16.943509 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9767 15:36:16.949749 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9768 15:36:16.952848 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9769 15:36:16.956656 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9770 15:36:16.962832 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9771 15:36:16.966358 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9772 15:36:16.972718 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9773 15:36:16.976235 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9774 15:36:16.979564 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9775 15:36:16.986008 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9776 15:36:16.989424 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9777 15:36:16.996503 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9778 15:36:16.999241 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9779 15:36:17.006107 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9780 15:36:17.009449 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9781 15:36:17.012403 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9782 15:36:17.019381 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9783 15:36:17.022202 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9784 15:36:17.028718 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9785 15:36:17.032498 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9786 15:36:17.039107 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9787 15:36:17.041976 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9788 15:36:17.045636 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9789 15:36:17.052496 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9790 15:36:17.055498 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9791 15:36:17.062187 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9792 15:36:17.065188 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9793 15:36:17.071767 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9794 15:36:17.075181 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9795 15:36:17.078139 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9796 15:36:17.084797 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9797 15:36:17.088384 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9798 15:36:17.094937 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9799 15:36:17.098363 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9800 15:36:17.104484 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9801 15:36:17.108057 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9802 15:36:17.114857 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9803 15:36:17.118141 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9804 15:36:17.121107 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9805 15:36:17.128044 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9806 15:36:17.131172 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9807 15:36:17.137878 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9808 15:36:17.141024 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9809 15:36:17.147411 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9810 15:36:17.150988 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9811 15:36:17.157386 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9812 15:36:17.160672 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9813 15:36:17.167520 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9814 15:36:17.170291 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9815 15:36:17.174294 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9816 15:36:17.180560 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9817 15:36:17.183765 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9818 15:36:17.190316 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9819 15:36:17.193859 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9820 15:36:17.200349 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9821 15:36:17.203702 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9822 15:36:17.210372 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9823 15:36:17.213265 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9824 15:36:17.216552 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9825 15:36:17.223090 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9826 15:36:17.226610 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9827 15:36:17.233041 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9828 15:36:17.236903 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9829 15:36:17.242970 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9830 15:36:17.246358 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9831 15:36:17.252867 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9832 15:36:17.256578 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9833 15:36:17.259527 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9834 15:36:17.266106 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9835 15:36:17.269547 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9836 15:36:17.276106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9837 15:36:17.279184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9838 15:36:17.285595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9839 15:36:17.288839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9840 15:36:17.295857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9841 15:36:17.299323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9842 15:36:17.305593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9843 15:36:17.309100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9844 15:36:17.312208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9845 15:36:17.319012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9846 15:36:17.322359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9847 15:36:17.328616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9848 15:36:17.332175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9849 15:36:17.338520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9850 15:36:17.341964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9851 15:36:17.348517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9852 15:36:17.352102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9853 15:36:17.358564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9854 15:36:17.361982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9855 15:36:17.368622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9856 15:36:17.371571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9857 15:36:17.378423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9858 15:36:17.381473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9859 15:36:17.388012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9860 15:36:17.391524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9861 15:36:17.397938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9862 15:36:17.401044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9863 15:36:17.407796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9864 15:36:17.414512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9865 15:36:17.417611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9866 15:36:17.424259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9867 15:36:17.427525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9868 15:36:17.430665 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9869 15:36:17.433944 INFO: [APUAPC] vio 0
9870 15:36:17.437539 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9871 15:36:17.444436 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9872 15:36:17.447979 INFO: [APUAPC] D0_APC_0: 0x400510
9873 15:36:17.450763 INFO: [APUAPC] D0_APC_1: 0x0
9874 15:36:17.454125 INFO: [APUAPC] D0_APC_2: 0x1540
9875 15:36:17.454580 INFO: [APUAPC] D0_APC_3: 0x0
9876 15:36:17.457723 INFO: [APUAPC] D1_APC_0: 0xffffffff
9877 15:36:17.464334 INFO: [APUAPC] D1_APC_1: 0xffffffff
9878 15:36:17.467853 INFO: [APUAPC] D1_APC_2: 0x3fffff
9879 15:36:17.468376 INFO: [APUAPC] D1_APC_3: 0x0
9880 15:36:17.470602 INFO: [APUAPC] D2_APC_0: 0xffffffff
9881 15:36:17.473827 INFO: [APUAPC] D2_APC_1: 0xffffffff
9882 15:36:17.477436 INFO: [APUAPC] D2_APC_2: 0x3fffff
9883 15:36:17.480710 INFO: [APUAPC] D2_APC_3: 0x0
9884 15:36:17.484232 INFO: [APUAPC] D3_APC_0: 0xffffffff
9885 15:36:17.487231 INFO: [APUAPC] D3_APC_1: 0xffffffff
9886 15:36:17.490490 INFO: [APUAPC] D3_APC_2: 0x3fffff
9887 15:36:17.494227 INFO: [APUAPC] D3_APC_3: 0x0
9888 15:36:17.496900 INFO: [APUAPC] D4_APC_0: 0xffffffff
9889 15:36:17.500318 INFO: [APUAPC] D4_APC_1: 0xffffffff
9890 15:36:17.503363 INFO: [APUAPC] D4_APC_2: 0x3fffff
9891 15:36:17.507359 INFO: [APUAPC] D4_APC_3: 0x0
9892 15:36:17.510436 INFO: [APUAPC] D5_APC_0: 0xffffffff
9893 15:36:17.513452 INFO: [APUAPC] D5_APC_1: 0xffffffff
9894 15:36:17.516921 INFO: [APUAPC] D5_APC_2: 0x3fffff
9895 15:36:17.520242 INFO: [APUAPC] D5_APC_3: 0x0
9896 15:36:17.522943 INFO: [APUAPC] D6_APC_0: 0xffffffff
9897 15:36:17.526447 INFO: [APUAPC] D6_APC_1: 0xffffffff
9898 15:36:17.530107 INFO: [APUAPC] D6_APC_2: 0x3fffff
9899 15:36:17.533749 INFO: [APUAPC] D6_APC_3: 0x0
9900 15:36:17.536152 INFO: [APUAPC] D7_APC_0: 0xffffffff
9901 15:36:17.539854 INFO: [APUAPC] D7_APC_1: 0xffffffff
9902 15:36:17.542902 INFO: [APUAPC] D7_APC_2: 0x3fffff
9903 15:36:17.546293 INFO: [APUAPC] D7_APC_3: 0x0
9904 15:36:17.549530 INFO: [APUAPC] D8_APC_0: 0xffffffff
9905 15:36:17.552793 INFO: [APUAPC] D8_APC_1: 0xffffffff
9906 15:36:17.555724 INFO: [APUAPC] D8_APC_2: 0x3fffff
9907 15:36:17.559250 INFO: [APUAPC] D8_APC_3: 0x0
9908 15:36:17.562452 INFO: [APUAPC] D9_APC_0: 0xffffffff
9909 15:36:17.565563 INFO: [APUAPC] D9_APC_1: 0xffffffff
9910 15:36:17.568931 INFO: [APUAPC] D9_APC_2: 0x3fffff
9911 15:36:17.572315 INFO: [APUAPC] D9_APC_3: 0x0
9912 15:36:17.576015 INFO: [APUAPC] D10_APC_0: 0xffffffff
9913 15:36:17.579024 INFO: [APUAPC] D10_APC_1: 0xffffffff
9914 15:36:17.582206 INFO: [APUAPC] D10_APC_2: 0x3fffff
9915 15:36:17.585588 INFO: [APUAPC] D10_APC_3: 0x0
9916 15:36:17.589140 INFO: [APUAPC] D11_APC_0: 0xffffffff
9917 15:36:17.592096 INFO: [APUAPC] D11_APC_1: 0xffffffff
9918 15:36:17.595777 INFO: [APUAPC] D11_APC_2: 0x3fffff
9919 15:36:17.599296 INFO: [APUAPC] D11_APC_3: 0x0
9920 15:36:17.602034 INFO: [APUAPC] D12_APC_0: 0xffffffff
9921 15:36:17.605412 INFO: [APUAPC] D12_APC_1: 0xffffffff
9922 15:36:17.608964 INFO: [APUAPC] D12_APC_2: 0x3fffff
9923 15:36:17.611844 INFO: [APUAPC] D12_APC_3: 0x0
9924 15:36:17.615382 INFO: [APUAPC] D13_APC_0: 0xffffffff
9925 15:36:17.618839 INFO: [APUAPC] D13_APC_1: 0xffffffff
9926 15:36:17.622045 INFO: [APUAPC] D13_APC_2: 0x3fffff
9927 15:36:17.625103 INFO: [APUAPC] D13_APC_3: 0x0
9928 15:36:17.629132 INFO: [APUAPC] D14_APC_0: 0xffffffff
9929 15:36:17.631655 INFO: [APUAPC] D14_APC_1: 0xffffffff
9930 15:36:17.634895 INFO: [APUAPC] D14_APC_2: 0x3fffff
9931 15:36:17.638327 INFO: [APUAPC] D14_APC_3: 0x0
9932 15:36:17.641722 INFO: [APUAPC] D15_APC_0: 0xffffffff
9933 15:36:17.645209 INFO: [APUAPC] D15_APC_1: 0xffffffff
9934 15:36:17.651696 INFO: [APUAPC] D15_APC_2: 0x3fffff
9935 15:36:17.652210 INFO: [APUAPC] D15_APC_3: 0x0
9936 15:36:17.654888 INFO: [APUAPC] APC_CON: 0x4
9937 15:36:17.658535 INFO: [NOCDAPC] D0_APC_0: 0x0
9938 15:36:17.662016 INFO: [NOCDAPC] D0_APC_1: 0x0
9939 15:36:17.665000 INFO: [NOCDAPC] D1_APC_0: 0x0
9940 15:36:17.668059 INFO: [NOCDAPC] D1_APC_1: 0xfff
9941 15:36:17.671653 INFO: [NOCDAPC] D2_APC_0: 0x0
9942 15:36:17.674604 INFO: [NOCDAPC] D2_APC_1: 0xfff
9943 15:36:17.678112 INFO: [NOCDAPC] D3_APC_0: 0x0
9944 15:36:17.681681 INFO: [NOCDAPC] D3_APC_1: 0xfff
9945 15:36:17.682110 INFO: [NOCDAPC] D4_APC_0: 0x0
9946 15:36:17.684435 INFO: [NOCDAPC] D4_APC_1: 0xfff
9947 15:36:17.687722 INFO: [NOCDAPC] D5_APC_0: 0x0
9948 15:36:17.690927 INFO: [NOCDAPC] D5_APC_1: 0xfff
9949 15:36:17.694358 INFO: [NOCDAPC] D6_APC_0: 0x0
9950 15:36:17.698033 INFO: [NOCDAPC] D6_APC_1: 0xfff
9951 15:36:17.701357 INFO: [NOCDAPC] D7_APC_0: 0x0
9952 15:36:17.704145 INFO: [NOCDAPC] D7_APC_1: 0xfff
9953 15:36:17.707875 INFO: [NOCDAPC] D8_APC_0: 0x0
9954 15:36:17.710733 INFO: [NOCDAPC] D8_APC_1: 0xfff
9955 15:36:17.714231 INFO: [NOCDAPC] D9_APC_0: 0x0
9956 15:36:17.714644 INFO: [NOCDAPC] D9_APC_1: 0xfff
9957 15:36:17.717636 INFO: [NOCDAPC] D10_APC_0: 0x0
9958 15:36:17.721117 INFO: [NOCDAPC] D10_APC_1: 0xfff
9959 15:36:17.724135 INFO: [NOCDAPC] D11_APC_0: 0x0
9960 15:36:17.727517 INFO: [NOCDAPC] D11_APC_1: 0xfff
9961 15:36:17.730768 INFO: [NOCDAPC] D12_APC_0: 0x0
9962 15:36:17.734203 INFO: [NOCDAPC] D12_APC_1: 0xfff
9963 15:36:17.737543 INFO: [NOCDAPC] D13_APC_0: 0x0
9964 15:36:17.740400 INFO: [NOCDAPC] D13_APC_1: 0xfff
9965 15:36:17.743638 INFO: [NOCDAPC] D14_APC_0: 0x0
9966 15:36:17.747087 INFO: [NOCDAPC] D14_APC_1: 0xfff
9967 15:36:17.750353 INFO: [NOCDAPC] D15_APC_0: 0x0
9968 15:36:17.754034 INFO: [NOCDAPC] D15_APC_1: 0xfff
9969 15:36:17.756840 INFO: [NOCDAPC] APC_CON: 0x4
9970 15:36:17.760477 INFO: [APUAPC] set_apusys_apc done
9971 15:36:17.763456 INFO: [DEVAPC] devapc_init done
9972 15:36:17.767037 INFO: GICv3 without legacy support detected.
9973 15:36:17.770337 INFO: ARM GICv3 driver initialized in EL3
9974 15:36:17.773247 INFO: Maximum SPI INTID supported: 639
9975 15:36:17.776585 INFO: BL31: Initializing runtime services
9976 15:36:17.783371 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9977 15:36:17.786945 INFO: SPM: enable CPC mode
9978 15:36:17.793285 INFO: mcdi ready for mcusys-off-idle and system suspend
9979 15:36:17.796616 INFO: BL31: Preparing for EL3 exit to normal world
9980 15:36:17.799842 INFO: Entry point address = 0x80000000
9981 15:36:17.803534 INFO: SPSR = 0x8
9982 15:36:17.807880
9983 15:36:17.808336
9984 15:36:17.808665
9985 15:36:17.811212 Starting depthcharge on Spherion...
9986 15:36:17.811646
9987 15:36:17.812030 Wipe memory regions:
9988 15:36:17.812349
9989 15:36:17.814907 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9990 15:36:17.815437 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9991 15:36:17.815962 Setting prompt string to ['asurada:']
9992 15:36:17.816420 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9993 15:36:17.817219 [0x00000040000000, 0x00000054600000)
9994 15:36:17.937036
9995 15:36:17.937545 [0x00000054660000, 0x00000080000000)
9996 15:36:18.197561
9997 15:36:18.198070 [0x000000821a7280, 0x000000ffe64000)
9998 15:36:18.942123
9999 15:36:18.942373 [0x00000100000000, 0x00000240000000)
10000 15:36:20.832351
10001 15:36:20.835821 Initializing XHCI USB controller at 0x11200000.
10002 15:36:21.873343
10003 15:36:21.876731 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10004 15:36:21.876837
10005 15:36:21.876932
10006 15:36:21.877020
10007 15:36:21.877335 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10009 15:36:21.977702 asurada: tftpboot 192.168.201.1 11331377/tftp-deploy-kvidpy_w/kernel/image.itb 11331377/tftp-deploy-kvidpy_w/kernel/cmdline
10010 15:36:21.977869 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10011 15:36:21.977962 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10012 15:36:21.982655 tftpboot 192.168.201.1 11331377/tftp-deploy-kvidpy_w/kernel/image.ittp-deploy-kvidpy_w/kernel/cmdline
10013 15:36:21.982767
10014 15:36:21.982859 Waiting for link
10015 15:36:22.142994
10016 15:36:22.143128 R8152: Initializing
10017 15:36:22.143196
10018 15:36:22.146068 Version 6 (ocp_data = 5c30)
10019 15:36:22.146169
10020 15:36:22.149423 R8152: Done initializing
10021 15:36:22.149496
10022 15:36:22.149558 Adding net device
10023 15:36:24.130723
10024 15:36:24.131222 done.
10025 15:36:24.131552
10026 15:36:24.131875 MAC: 00:24:32:30:7c:7b
10027 15:36:24.132250
10028 15:36:24.134124 Sending DHCP discover... done.
10029 15:36:24.134570
10030 15:36:24.137459 Waiting for reply... done.
10031 15:36:24.137869
10032 15:36:24.140555 Sending DHCP request... done.
10033 15:36:24.140966
10034 15:36:24.144790 Waiting for reply... done.
10035 15:36:24.145198
10036 15:36:24.145521 My ip is 192.168.201.14
10037 15:36:24.145822
10038 15:36:24.147953 The DHCP server ip is 192.168.201.1
10039 15:36:24.148367
10040 15:36:24.154321 TFTP server IP predefined by user: 192.168.201.1
10041 15:36:24.154734
10042 15:36:24.161208 Bootfile predefined by user: 11331377/tftp-deploy-kvidpy_w/kernel/image.itb
10043 15:36:24.161618
10044 15:36:24.164505 Sending tftp read request... done.
10045 15:36:24.164914
10046 15:36:24.170934 Waiting for the transfer...
10047 15:36:24.171344
10048 15:36:24.850460 00000000 ################################################################
10049 15:36:24.850952
10050 15:36:25.524841 00080000 ################################################################
10051 15:36:25.525527
10052 15:36:26.225912 00100000 ################################################################
10053 15:36:26.226434
10054 15:36:26.892521 00180000 ################################################################
10055 15:36:26.893098
10056 15:36:27.595096 00200000 ################################################################
10057 15:36:27.595600
10058 15:36:28.222241 00280000 ################################################################
10059 15:36:28.222466
10060 15:36:28.942231 00300000 ################################################################
10061 15:36:28.942756
10062 15:36:29.670565 00380000 ################################################################
10063 15:36:29.671071
10064 15:36:30.411314 00400000 ################################################################
10065 15:36:30.411827
10066 15:36:31.132700 00480000 ################################################################
10067 15:36:31.133208
10068 15:36:31.847542 00500000 ################################################################
10069 15:36:31.848128
10070 15:36:32.584838 00580000 ################################################################
10071 15:36:32.585389
10072 15:36:33.306930 00600000 ################################################################
10073 15:36:33.307083
10074 15:36:33.999970 00680000 ################################################################
10075 15:36:34.000491
10076 15:36:34.686390 00700000 ################################################################
10077 15:36:34.686871
10078 15:36:35.287437 00780000 ################################################################
10079 15:36:35.287571
10080 15:36:35.934790 00800000 ################################################################
10081 15:36:35.935432
10082 15:36:36.552020 00880000 ################################################################
10083 15:36:36.552317
10084 15:36:37.199076 00900000 ################################################################
10085 15:36:37.199227
10086 15:36:37.747526 00980000 ################################################################
10087 15:36:37.747676
10088 15:36:38.284178 00a00000 ################################################################
10089 15:36:38.284326
10090 15:36:38.856656 00a80000 ################################################################
10091 15:36:38.856822
10092 15:36:39.427676 00b00000 ################################################################
10093 15:36:39.427839
10094 15:36:40.060517 00b80000 ################################################################
10095 15:36:40.060678
10096 15:36:40.655853 00c00000 ################################################################
10097 15:36:40.656410
10098 15:36:41.263018 00c80000 ################################################################
10099 15:36:41.263521
10100 15:36:41.869235 00d00000 ################################################################
10101 15:36:41.869759
10102 15:36:42.501743 00d80000 ################################################################
10103 15:36:42.501890
10104 15:36:43.071275 00e00000 ################################################################
10105 15:36:43.071418
10106 15:36:43.638644 00e80000 ################################################################
10107 15:36:43.638774
10108 15:36:44.178301 00f00000 ################################################################
10109 15:36:44.178787
10110 15:36:44.742257 00f80000 ################################################################
10111 15:36:44.742387
10112 15:36:45.324027 01000000 ################################################################
10113 15:36:45.324165
10114 15:36:45.920955 01080000 ################################################################
10115 15:36:45.921090
10116 15:36:46.483441 01100000 ################################################################
10117 15:36:46.483571
10118 15:36:47.047731 01180000 ################################################################
10119 15:36:47.047886
10120 15:36:47.654236 01200000 ################################################################
10121 15:36:47.654371
10122 15:36:48.227864 01280000 ################################################################
10123 15:36:48.228020
10124 15:36:48.808701 01300000 ################################################################
10125 15:36:48.808836
10126 15:36:49.378594 01380000 ################################################################
10127 15:36:49.378723
10128 15:36:49.952423 01400000 ################################################################
10129 15:36:49.952987
10130 15:36:50.543845 01480000 ################################################################
10131 15:36:50.544008
10132 15:36:51.106616 01500000 ################################################################
10133 15:36:51.106756
10134 15:36:51.805267 01580000 ################################################################
10135 15:36:51.805801
10136 15:36:52.511011 01600000 ################################################################
10137 15:36:52.511552
10138 15:36:53.239068 01680000 ################################################################
10139 15:36:53.239597
10140 15:36:53.925902 01700000 ################################################################
10141 15:36:53.926551
10142 15:36:54.624953 01780000 ################################################################
10143 15:36:54.625483
10144 15:36:55.343713 01800000 ################################################################
10145 15:36:55.344304
10146 15:36:55.975119 01880000 ################################################################
10147 15:36:55.975294
10148 15:36:56.599697 01900000 ################################################################
10149 15:36:56.600280
10150 15:36:57.296948 01980000 ################################################################
10151 15:36:57.297478
10152 15:36:58.015348 01a00000 ################################################################
10153 15:36:58.015588
10154 15:36:58.607836 01a80000 ################################################################
10155 15:36:58.608412
10156 15:36:59.263452 01b00000 ################################################################
10157 15:36:59.263986
10158 15:36:59.996643 01b80000 ################################################################
10159 15:36:59.997177
10160 15:37:00.740489 01c00000 ################################################################
10161 15:37:00.741029
10162 15:37:01.467005 01c80000 ################################################################
10163 15:37:01.467529
10164 15:37:02.180505 01d00000 ################################################################
10165 15:37:02.181007
10166 15:37:02.887789 01d80000 ################################################################
10167 15:37:02.887961
10168 15:37:03.607810 01e00000 ################################################################
10169 15:37:03.608354
10170 15:37:04.341561 01e80000 ################################################################
10171 15:37:04.342084
10172 15:37:05.062032 01f00000 ################################################################
10173 15:37:05.062550
10174 15:37:05.776764 01f80000 ################################################################
10175 15:37:05.777279
10176 15:37:06.483363 02000000 ################################################################
10177 15:37:06.483865
10178 15:37:07.212027 02080000 ################################################################
10179 15:37:07.212535
10180 15:37:07.934578 02100000 ################################################################
10181 15:37:07.935102
10182 15:37:08.658382 02180000 ################################################################
10183 15:37:08.658939
10184 15:37:09.384367 02200000 ################################################################
10185 15:37:09.384937
10186 15:37:10.110205 02280000 ################################################################
10187 15:37:10.110706
10188 15:37:10.809568 02300000 ################################################################
10189 15:37:10.810129
10190 15:37:11.528776 02380000 ################################################################
10191 15:37:11.529296
10192 15:37:12.238146 02400000 ################################################################
10193 15:37:12.238659
10194 15:37:12.950142 02480000 ################################################################
10195 15:37:12.950483
10196 15:37:13.671862 02500000 ################################################################
10197 15:37:13.672436
10198 15:37:14.389534 02580000 ################################################################
10199 15:37:14.390122
10200 15:37:15.099817 02600000 ################################################################
10201 15:37:15.100361
10202 15:37:15.829683 02680000 ################################################################
10203 15:37:15.830279
10204 15:37:16.573298 02700000 ################################################################
10205 15:37:16.573840
10206 15:37:17.307821 02780000 ################################################################
10207 15:37:17.308408
10208 15:37:18.057528 02800000 ################################################################
10209 15:37:18.058243
10210 15:37:18.793870 02880000 ################################################################
10211 15:37:18.794357
10212 15:37:19.496766 02900000 ################################################################
10213 15:37:19.497272
10214 15:37:20.183836 02980000 ################################################################
10215 15:37:20.184017
10216 15:37:20.854142 02a00000 ################################################################
10217 15:37:20.854678
10218 15:37:21.572751 02a80000 ################################################################
10219 15:37:21.573266
10220 15:37:22.279401 02b00000 ################################################################
10221 15:37:22.280111
10222 15:37:22.960505 02b80000 ################################################################
10223 15:37:22.961057
10224 15:37:23.662505 02c00000 ################################################################
10225 15:37:23.663004
10226 15:37:24.269135 02c80000 ################################################################
10227 15:37:24.269311
10228 15:37:24.853511 02d00000 ################################################################
10229 15:37:24.853668
10230 15:37:25.443867 02d80000 ################################################################
10231 15:37:25.444057
10232 15:37:26.042743 02e00000 ################################################################
10233 15:37:26.042892
10234 15:37:26.641679 02e80000 ################################################################
10235 15:37:26.641828
10236 15:37:27.225349 02f00000 ################################################################
10237 15:37:27.225531
10238 15:37:27.816114 02f80000 ################################################################
10239 15:37:27.816267
10240 15:37:27.919764 03000000 ########### done.
10241 15:37:27.919893
10242 15:37:27.923178 The bootfile was 50420582 bytes long.
10243 15:37:27.923262
10244 15:37:27.926210 Sending tftp read request... done.
10245 15:37:27.926295
10246 15:37:27.926418 Waiting for the transfer...
10247 15:37:27.926517
10248 15:37:27.929562 00000000 # done.
10249 15:37:27.929645
10250 15:37:27.936302 Command line loaded dynamically from TFTP file: 11331377/tftp-deploy-kvidpy_w/kernel/cmdline
10251 15:37:27.936383
10252 15:37:27.949895 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10253 15:37:27.952898
10254 15:37:27.952978 Loading FIT.
10255 15:37:27.953041
10256 15:37:27.956057 Image ramdisk-1 has 39335928 bytes.
10257 15:37:27.956138
10258 15:37:27.959104 Image fdt-1 has 47278 bytes.
10259 15:37:27.959184
10260 15:37:27.962175 Image kernel-1 has 11035343 bytes.
10261 15:37:27.962255
10262 15:37:27.968761 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10263 15:37:27.968842
10264 15:37:27.988721 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10265 15:37:27.988808
10266 15:37:27.992022 Choosing best match conf-1 for compat google,spherion-rev2.
10267 15:37:27.996949
10268 15:37:28.001490 Connected to device vid:did:rid of 1ae0:0028:00
10269 15:37:28.008905
10270 15:37:28.011678 tpm_get_response: command 0x17b, return code 0x0
10271 15:37:28.011757
10272 15:37:28.018033 ec_init: CrosEC protocol v3 supported (256, 248)
10273 15:37:28.018128
10274 15:37:28.021510 tpm_cleanup: add release locality here.
10275 15:37:28.021589
10276 15:37:28.025146 Shutting down all USB controllers.
10277 15:37:28.025226
10278 15:37:28.028222 Removing current net device
10279 15:37:28.028345
10280 15:37:28.031432 Exiting depthcharge with code 4 at timestamp: 99461227
10281 15:37:28.034574
10282 15:37:28.037980 LZMA decompressing kernel-1 to 0x821a6718
10283 15:37:28.038145
10284 15:37:28.041715 LZMA decompressing kernel-1 to 0x40000000
10285 15:37:29.428349
10286 15:37:29.428502 jumping to kernel
10287 15:37:29.428917 end: 2.2.4 bootloader-commands (duration 00:01:12) [common]
10288 15:37:29.429015 start: 2.2.5 auto-login-action (timeout 00:03:14) [common]
10289 15:37:29.429088 Setting prompt string to ['Linux version [0-9]']
10290 15:37:29.429155 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10291 15:37:29.429219 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10292 15:37:29.509840
10293 15:37:29.513285 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10294 15:37:29.516833 start: 2.2.5.1 login-action (timeout 00:03:14) [common]
10295 15:37:29.516931 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10296 15:37:29.517002 Setting prompt string to []
10297 15:37:29.517081 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10298 15:37:29.517157 Using line separator: #'\n'#
10299 15:37:29.517216 No login prompt set.
10300 15:37:29.517275 Parsing kernel messages
10301 15:37:29.517328 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10302 15:37:29.517425 [login-action] Waiting for messages, (timeout 00:03:14)
10303 15:37:29.536145 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j17681-arm64-gcc-10-defconfig-arm64-chromebook-c49jr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Aug 22 15:20:14 UTC 2023
10304 15:37:29.539610 [ 0.000000] random: crng init done
10305 15:37:29.546752 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10306 15:37:29.549979 [ 0.000000] efi: UEFI not found.
10307 15:37:29.555895 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10308 15:37:29.562325 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10309 15:37:29.572369 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10310 15:37:29.582374 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10311 15:37:29.588961 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10312 15:37:29.595590 [ 0.000000] printk: bootconsole [mtk8250] enabled
10313 15:37:29.601796 [ 0.000000] NUMA: No NUMA configuration found
10314 15:37:29.608931 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10315 15:37:29.615699 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10316 15:37:29.615778 [ 0.000000] Zone ranges:
10317 15:37:29.621732 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10318 15:37:29.625052 [ 0.000000] DMA32 empty
10319 15:37:29.631489 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10320 15:37:29.634592 [ 0.000000] Movable zone start for each node
10321 15:37:29.638829 [ 0.000000] Early memory node ranges
10322 15:37:29.644503 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10323 15:37:29.651509 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10324 15:37:29.658010 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10325 15:37:29.664426 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10326 15:37:29.671099 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10327 15:37:29.677458 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10328 15:37:29.734384 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10329 15:37:29.741080 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10330 15:37:29.747467 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10331 15:37:29.750888 [ 0.000000] psci: probing for conduit method from DT.
10332 15:37:29.757306 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10333 15:37:29.760661 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10334 15:37:29.767073 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10335 15:37:29.770261 [ 0.000000] psci: SMC Calling Convention v1.2
10336 15:37:29.776932 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10337 15:37:29.780890 [ 0.000000] Detected VIPT I-cache on CPU0
10338 15:37:29.786904 [ 0.000000] CPU features: detected: GIC system register CPU interface
10339 15:37:29.794588 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10340 15:37:29.800224 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10341 15:37:29.806824 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10342 15:37:29.816538 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10343 15:37:29.823417 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10344 15:37:29.826421 [ 0.000000] alternatives: applying boot alternatives
10345 15:37:29.832894 [ 0.000000] Fallback order for Node 0: 0
10346 15:37:29.839732 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10347 15:37:29.843082 [ 0.000000] Policy zone: Normal
10348 15:37:29.856671 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10349 15:37:29.866508 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10350 15:37:29.878809 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10351 15:37:29.888296 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10352 15:37:29.895389 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10353 15:37:29.898203 <6>[ 0.000000] software IO TLB: area num 8.
10354 15:37:29.955551 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10355 15:37:30.105267 <6>[ 0.000000] Memory: 7931136K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 421632K reserved, 32768K cma-reserved)
10356 15:37:30.111759 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10357 15:37:30.118334 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10358 15:37:30.121462 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10359 15:37:30.127783 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10360 15:37:30.134715 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10361 15:37:30.138239 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10362 15:37:30.148187 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10363 15:37:30.154645 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10364 15:37:30.160800 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10365 15:37:30.167603 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10366 15:37:30.171130 <6>[ 0.000000] GICv3: 608 SPIs implemented
10367 15:37:30.173989 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10368 15:37:30.180999 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10369 15:37:30.184206 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10370 15:37:30.190853 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10371 15:37:30.203795 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10372 15:37:30.216454 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10373 15:37:30.224148 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10374 15:37:30.231837 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10375 15:37:30.245028 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10376 15:37:30.251428 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10377 15:37:30.258406 <6>[ 0.009180] Console: colour dummy device 80x25
10378 15:37:30.267849 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10379 15:37:30.274455 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10380 15:37:30.277610 <6>[ 0.029220] LSM: Security Framework initializing
10381 15:37:30.284813 <6>[ 0.034158] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10382 15:37:30.294463 <6>[ 0.042019] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10383 15:37:30.304223 <6>[ 0.051459] cblist_init_generic: Setting adjustable number of callback queues.
10384 15:37:30.310687 <6>[ 0.058949] cblist_init_generic: Setting shift to 3 and lim to 1.
10385 15:37:30.317266 <6>[ 0.065286] cblist_init_generic: Setting adjustable number of callback queues.
10386 15:37:30.324020 <6>[ 0.072712] cblist_init_generic: Setting shift to 3 and lim to 1.
10387 15:37:30.327049 <6>[ 0.079111] rcu: Hierarchical SRCU implementation.
10388 15:37:30.334202 <6>[ 0.084155] rcu: Max phase no-delay instances is 1000.
10389 15:37:30.340268 <6>[ 0.091184] EFI services will not be available.
10390 15:37:30.343430 <6>[ 0.096155] smp: Bringing up secondary CPUs ...
10391 15:37:30.352137 <6>[ 0.101241] Detected VIPT I-cache on CPU1
10392 15:37:30.359147 <6>[ 0.101309] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10393 15:37:30.366169 <6>[ 0.101340] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10394 15:37:30.369269 <6>[ 0.101681] Detected VIPT I-cache on CPU2
10395 15:37:30.378864 <6>[ 0.101734] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10396 15:37:30.385514 <6>[ 0.101752] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10397 15:37:30.388623 <6>[ 0.102012] Detected VIPT I-cache on CPU3
10398 15:37:30.395021 <6>[ 0.102059] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10399 15:37:30.402350 <6>[ 0.102072] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10400 15:37:30.408167 <6>[ 0.102378] CPU features: detected: Spectre-v4
10401 15:37:30.411478 <6>[ 0.102385] CPU features: detected: Spectre-BHB
10402 15:37:30.415195 <6>[ 0.102389] Detected PIPT I-cache on CPU4
10403 15:37:30.425214 <6>[ 0.102445] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10404 15:37:30.431172 <6>[ 0.102461] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10405 15:37:30.434612 <6>[ 0.102757] Detected PIPT I-cache on CPU5
10406 15:37:30.441191 <6>[ 0.102819] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10407 15:37:30.448191 <6>[ 0.102835] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10408 15:37:30.451094 <6>[ 0.103119] Detected PIPT I-cache on CPU6
10409 15:37:30.461224 <6>[ 0.103183] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10410 15:37:30.467611 <6>[ 0.103200] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10411 15:37:30.470868 <6>[ 0.103501] Detected PIPT I-cache on CPU7
10412 15:37:30.477773 <6>[ 0.103565] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10413 15:37:30.483878 <6>[ 0.103581] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10414 15:37:30.487245 <6>[ 0.103628] smp: Brought up 1 node, 8 CPUs
10415 15:37:30.493516 <6>[ 0.244993] SMP: Total of 8 processors activated.
10416 15:37:30.500366 <6>[ 0.249925] CPU features: detected: 32-bit EL0 Support
10417 15:37:30.507499 <6>[ 0.255287] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10418 15:37:30.513604 <6>[ 0.264087] CPU features: detected: Common not Private translations
10419 15:37:30.520517 <6>[ 0.270563] CPU features: detected: CRC32 instructions
10420 15:37:30.527201 <6>[ 0.275915] CPU features: detected: RCpc load-acquire (LDAPR)
10421 15:37:30.530390 <6>[ 0.281875] CPU features: detected: LSE atomic instructions
10422 15:37:30.536855 <6>[ 0.287657] CPU features: detected: Privileged Access Never
10423 15:37:30.543323 <6>[ 0.293437] CPU features: detected: RAS Extension Support
10424 15:37:30.549950 <6>[ 0.299046] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10425 15:37:30.553258 <6>[ 0.306266] CPU: All CPU(s) started at EL2
10426 15:37:30.559809 <6>[ 0.310583] alternatives: applying system-wide alternatives
10427 15:37:30.569591 <6>[ 0.321267] devtmpfs: initialized
10428 15:37:30.585328 <6>[ 0.330126] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10429 15:37:30.592128 <6>[ 0.340088] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10430 15:37:30.599473 <6>[ 0.348102] pinctrl core: initialized pinctrl subsystem
10431 15:37:30.602732 <6>[ 0.354780] DMI not present or invalid.
10432 15:37:30.608426 <6>[ 0.359188] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10433 15:37:30.618671 <6>[ 0.366042] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10434 15:37:30.625113 <6>[ 0.373624] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10435 15:37:30.635065 <6>[ 0.381837] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10436 15:37:30.638425 <6>[ 0.390078] audit: initializing netlink subsys (disabled)
10437 15:37:30.648571 <5>[ 0.395772] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10438 15:37:30.654663 <6>[ 0.396478] thermal_sys: Registered thermal governor 'step_wise'
10439 15:37:30.661483 <6>[ 0.403741] thermal_sys: Registered thermal governor 'power_allocator'
10440 15:37:30.664700 <6>[ 0.409997] cpuidle: using governor menu
10441 15:37:30.671274 <6>[ 0.420958] NET: Registered PF_QIPCRTR protocol family
10442 15:37:30.678241 <6>[ 0.426433] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10443 15:37:30.684274 <6>[ 0.433533] ASID allocator initialised with 32768 entries
10444 15:37:30.687900 <6>[ 0.440106] Serial: AMBA PL011 UART driver
10445 15:37:30.697391 <4>[ 0.448895] Trying to register duplicate clock ID: 134
10446 15:37:30.751642 <6>[ 0.506154] KASLR enabled
10447 15:37:30.765651 <6>[ 0.513786] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10448 15:37:30.772204 <6>[ 0.520799] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10449 15:37:30.778956 <6>[ 0.527287] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10450 15:37:30.785385 <6>[ 0.534291] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10451 15:37:30.792739 <6>[ 0.540778] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10452 15:37:30.798886 <6>[ 0.547782] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10453 15:37:30.805887 <6>[ 0.554269] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10454 15:37:30.812160 <6>[ 0.561275] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10455 15:37:30.815251 <6>[ 0.568694] ACPI: Interpreter disabled.
10456 15:37:30.823818 <6>[ 0.575127] iommu: Default domain type: Translated
10457 15:37:30.830239 <6>[ 0.580242] iommu: DMA domain TLB invalidation policy: strict mode
10458 15:37:30.833833 <5>[ 0.586898] SCSI subsystem initialized
10459 15:37:30.840261 <6>[ 0.591143] usbcore: registered new interface driver usbfs
10460 15:37:30.847482 <6>[ 0.596872] usbcore: registered new interface driver hub
10461 15:37:30.850399 <6>[ 0.602426] usbcore: registered new device driver usb
10462 15:37:30.857749 <6>[ 0.608544] pps_core: LinuxPPS API ver. 1 registered
10463 15:37:30.867516 <6>[ 0.613738] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10464 15:37:30.870495 <6>[ 0.623079] PTP clock support registered
10465 15:37:30.873638 <6>[ 0.627322] EDAC MC: Ver: 3.0.0
10466 15:37:30.881190 <6>[ 0.632510] FPGA manager framework
10467 15:37:30.888209 <6>[ 0.636186] Advanced Linux Sound Architecture Driver Initialized.
10468 15:37:30.891302 <6>[ 0.642951] vgaarb: loaded
10469 15:37:30.898079 <6>[ 0.646115] clocksource: Switched to clocksource arch_sys_counter
10470 15:37:30.901219 <5>[ 0.652562] VFS: Disk quotas dquot_6.6.0
10471 15:37:30.907488 <6>[ 0.656750] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10472 15:37:30.910697 <6>[ 0.663938] pnp: PnP ACPI: disabled
10473 15:37:30.919815 <6>[ 0.670562] NET: Registered PF_INET protocol family
10474 15:37:30.930320 <6>[ 0.676149] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10475 15:37:30.940169 <6>[ 0.688435] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10476 15:37:30.950295 <6>[ 0.697247] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10477 15:37:30.956741 <6>[ 0.705218] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10478 15:37:30.966446 <6>[ 0.713917] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10479 15:37:30.973280 <6>[ 0.723661] TCP: Hash tables configured (established 65536 bind 65536)
10480 15:37:30.979835 <6>[ 0.730530] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10481 15:37:30.990655 <6>[ 0.737729] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10482 15:37:30.996370 <6>[ 0.745431] NET: Registered PF_UNIX/PF_LOCAL protocol family
10483 15:37:31.002826 <6>[ 0.751590] RPC: Registered named UNIX socket transport module.
10484 15:37:31.006165 <6>[ 0.757742] RPC: Registered udp transport module.
10485 15:37:31.012594 <6>[ 0.762675] RPC: Registered tcp transport module.
10486 15:37:31.019558 <6>[ 0.767606] RPC: Registered tcp NFSv4.1 backchannel transport module.
10487 15:37:31.023259 <6>[ 0.774274] PCI: CLS 0 bytes, default 64
10488 15:37:31.025891 <6>[ 0.778680] Unpacking initramfs...
10489 15:37:31.050131 <6>[ 0.798282] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10490 15:37:31.060301 <6>[ 0.806927] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10491 15:37:31.063211 <6>[ 0.815770] kvm [1]: IPA Size Limit: 40 bits
10492 15:37:31.070426 <6>[ 0.820297] kvm [1]: GICv3: no GICV resource entry
10493 15:37:31.073151 <6>[ 0.825319] kvm [1]: disabling GICv2 emulation
10494 15:37:31.080168 <6>[ 0.830004] kvm [1]: GIC system register CPU interface enabled
10495 15:37:31.083072 <6>[ 0.836162] kvm [1]: vgic interrupt IRQ18
10496 15:37:31.089966 <6>[ 0.840520] kvm [1]: VHE mode initialized successfully
10497 15:37:31.096148 <5>[ 0.847003] Initialise system trusted keyrings
10498 15:37:31.103446 <6>[ 0.851827] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10499 15:37:31.110557 <6>[ 0.861782] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10500 15:37:31.116906 <5>[ 0.868162] NFS: Registering the id_resolver key type
10501 15:37:31.120513 <5>[ 0.873463] Key type id_resolver registered
10502 15:37:31.127166 <5>[ 0.877878] Key type id_legacy registered
10503 15:37:31.133996 <6>[ 0.882162] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10504 15:37:31.140032 <6>[ 0.889084] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10505 15:37:31.147186 <6>[ 0.896803] 9p: Installing v9fs 9p2000 file system support
10506 15:37:31.183752 <5>[ 0.934598] Key type asymmetric registered
10507 15:37:31.186569 <5>[ 0.938927] Asymmetric key parser 'x509' registered
10508 15:37:31.196826 <6>[ 0.944065] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10509 15:37:31.200511 <6>[ 0.951695] io scheduler mq-deadline registered
10510 15:37:31.203608 <6>[ 0.956477] io scheduler kyber registered
10511 15:37:31.221882 <6>[ 0.973393] EINJ: ACPI disabled.
10512 15:37:31.253776 <4>[ 0.998650] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10513 15:37:31.263715 <4>[ 1.009271] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10514 15:37:31.278405 <6>[ 1.029942] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10515 15:37:31.286368 <6>[ 1.037844] printk: console [ttyS0] disabled
10516 15:37:31.314322 <6>[ 1.062489] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10517 15:37:31.321736 <6>[ 1.071986] printk: console [ttyS0] enabled
10518 15:37:31.324624 <6>[ 1.071986] printk: console [ttyS0] enabled
10519 15:37:31.330959 <6>[ 1.080882] printk: bootconsole [mtk8250] disabled
10520 15:37:31.334655 <6>[ 1.080882] printk: bootconsole [mtk8250] disabled
10521 15:37:31.340948 <6>[ 1.092110] SuperH (H)SCI(F) driver initialized
10522 15:37:31.343787 <6>[ 1.097379] msm_serial: driver initialized
10523 15:37:31.358351 <6>[ 1.106393] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10524 15:37:31.368617 <6>[ 1.114937] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10525 15:37:31.375455 <6>[ 1.123479] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10526 15:37:31.385556 <6>[ 1.132107] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10527 15:37:31.394762 <6>[ 1.140815] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10528 15:37:31.401607 <6>[ 1.149541] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10529 15:37:31.411166 <6>[ 1.158082] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10530 15:37:31.417791 <6>[ 1.166888] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10531 15:37:31.427942 <6>[ 1.175431] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10532 15:37:31.439590 <6>[ 1.190965] loop: module loaded
10533 15:37:31.445960 <6>[ 1.196937] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10534 15:37:31.468908 <4>[ 1.220243] mtk-pmic-keys: Failed to locate of_node [id: -1]
10535 15:37:31.475883 <6>[ 1.227079] megasas: 07.719.03.00-rc1
10536 15:37:31.485576 <6>[ 1.236747] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10537 15:37:31.494204 <6>[ 1.245504] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10538 15:37:31.511155 <6>[ 1.262307] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10539 15:37:31.567887 <6>[ 1.312421] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10540 15:37:32.616283 <6>[ 2.367355] Freeing initrd memory: 38412K
10541 15:37:32.626078 <6>[ 2.377539] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10542 15:37:32.637298 <6>[ 2.388688] tun: Universal TUN/TAP device driver, 1.6
10543 15:37:32.640754 <6>[ 2.394777] thunder_xcv, ver 1.0
10544 15:37:32.643739 <6>[ 2.398280] thunder_bgx, ver 1.0
10545 15:37:32.648456 <6>[ 2.401773] nicpf, ver 1.0
10546 15:37:32.658041 <6>[ 2.405811] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10547 15:37:32.661620 <6>[ 2.413286] hns3: Copyright (c) 2017 Huawei Corporation.
10548 15:37:32.667972 <6>[ 2.418874] hclge is initializing
10549 15:37:32.670835 <6>[ 2.422454] e1000: Intel(R) PRO/1000 Network Driver
10550 15:37:32.677620 <6>[ 2.427582] e1000: Copyright (c) 1999-2006 Intel Corporation.
10551 15:37:32.680765 <6>[ 2.433597] e1000e: Intel(R) PRO/1000 Network Driver
10552 15:37:32.687701 <6>[ 2.438813] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10553 15:37:32.694333 <6>[ 2.444997] igb: Intel(R) Gigabit Ethernet Network Driver
10554 15:37:32.700627 <6>[ 2.450647] igb: Copyright (c) 2007-2014 Intel Corporation.
10555 15:37:32.707461 <6>[ 2.456482] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10556 15:37:32.714657 <6>[ 2.463001] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10557 15:37:32.717380 <6>[ 2.469491] sky2: driver version 1.30
10558 15:37:32.724039 <6>[ 2.474506] VFIO - User Level meta-driver version: 0.3
10559 15:37:32.731260 <6>[ 2.482786] usbcore: registered new interface driver usb-storage
10560 15:37:32.738204 <6>[ 2.489229] usbcore: registered new device driver onboard-usb-hub
10561 15:37:32.746733 <6>[ 2.498367] mt6397-rtc mt6359-rtc: registered as rtc0
10562 15:37:32.756684 <6>[ 2.503828] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-22T15:37:37 UTC (1692718657)
10563 15:37:32.760841 <6>[ 2.513401] i2c_dev: i2c /dev entries driver
10564 15:37:32.776820 <6>[ 2.525239] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10565 15:37:32.797889 <6>[ 2.549225] cpu cpu0: EM: created perf domain
10566 15:37:32.800878 <6>[ 2.554253] cpu cpu4: EM: created perf domain
10567 15:37:32.808856 <6>[ 2.559942] sdhci: Secure Digital Host Controller Interface driver
10568 15:37:32.814859 <6>[ 2.566377] sdhci: Copyright(c) Pierre Ossman
10569 15:37:32.821484 <6>[ 2.571339] Synopsys Designware Multimedia Card Interface Driver
10570 15:37:32.828836 <6>[ 2.577972] sdhci-pltfm: SDHCI platform and OF driver helper
10571 15:37:32.831379 <6>[ 2.578006] mmc0: CQHCI version 5.10
10572 15:37:32.838565 <6>[ 2.588022] ledtrig-cpu: registered to indicate activity on CPUs
10573 15:37:32.844657 <6>[ 2.595149] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10574 15:37:32.851739 <6>[ 2.602217] usbcore: registered new interface driver usbhid
10575 15:37:32.855057 <6>[ 2.608039] usbhid: USB HID core driver
10576 15:37:32.861211 <6>[ 2.612205] spi_master spi0: will run message pump with realtime priority
10577 15:37:32.903900 <6>[ 2.648906] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10578 15:37:32.922313 <6>[ 2.663933] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10579 15:37:32.929423 <6>[ 2.678866] cros-ec-spi spi0.0: Chrome EC device registered
10580 15:37:32.933678 <6>[ 2.684903] mmc0: Command Queue Engine enabled
10581 15:37:32.939211 <6>[ 2.689661] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10582 15:37:32.947179 <6>[ 2.697479] mmcblk0: mmc0:0001 DA4128 116 GiB
10583 15:37:32.955219 <6>[ 2.706816] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10584 15:37:32.962548 <6>[ 2.713940] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10585 15:37:32.973088 <6>[ 2.717575] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10586 15:37:32.976070 <6>[ 2.719893] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10587 15:37:32.982058 <6>[ 2.729578] NET: Registered PF_PACKET protocol family
10588 15:37:32.988909 <6>[ 2.734442] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10589 15:37:32.992047 <6>[ 2.739082] 9pnet: Installing 9P2000 support
10590 15:37:32.998953 <5>[ 2.750101] Key type dns_resolver registered
10591 15:37:33.002121 <6>[ 2.755081] registered taskstats version 1
10592 15:37:33.009126 <5>[ 2.759466] Loading compiled-in X.509 certificates
10593 15:37:33.037519 <4>[ 2.781893] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 15:37:33.047023 <4>[ 2.792719] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 15:37:33.053540 <3>[ 2.803276] debugfs: File 'uA_load' in directory '/' already present!
10596 15:37:33.060116 <3>[ 2.810043] debugfs: File 'min_uV' in directory '/' already present!
10597 15:37:33.066956 <3>[ 2.816677] debugfs: File 'max_uV' in directory '/' already present!
10598 15:37:33.074877 <3>[ 2.823306] debugfs: File 'constraint_flags' in directory '/' already present!
10599 15:37:33.084907 <3>[ 2.833089] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10600 15:37:33.093886 <6>[ 2.845533] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10601 15:37:33.100735 <6>[ 2.852383] xhci-mtk 11200000.usb: xHCI Host Controller
10602 15:37:33.107863 <6>[ 2.857894] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10603 15:37:33.117529 <6>[ 2.865750] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10604 15:37:33.124162 <6>[ 2.875191] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10605 15:37:33.131205 <6>[ 2.881255] xhci-mtk 11200000.usb: xHCI Host Controller
10606 15:37:33.137594 <6>[ 2.886730] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10607 15:37:33.143891 <6>[ 2.894385] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10608 15:37:33.150782 <6>[ 2.901982] hub 1-0:1.0: USB hub found
10609 15:37:33.153962 <6>[ 2.905991] hub 1-0:1.0: 1 port detected
10610 15:37:33.160478 <6>[ 2.910245] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10611 15:37:33.167875 <6>[ 2.918771] hub 2-0:1.0: USB hub found
10612 15:37:33.170306 <6>[ 2.922774] hub 2-0:1.0: 1 port detected
10613 15:37:33.179084 <6>[ 2.930647] mtk-msdc 11f70000.mmc: Got CD GPIO
10614 15:37:33.189982 <6>[ 2.937014] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10615 15:37:33.195579 <6>[ 2.945048] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10616 15:37:33.205723 <4>[ 2.952942] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10617 15:37:33.215384 <6>[ 2.962466] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10618 15:37:33.222375 <6>[ 2.970544] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10619 15:37:33.228276 <6>[ 2.978568] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10620 15:37:33.238315 <6>[ 2.986488] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10621 15:37:33.245575 <6>[ 2.994305] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10622 15:37:33.254692 <6>[ 3.002125] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10623 15:37:33.265159 <6>[ 3.012544] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10624 15:37:33.271577 <6>[ 3.020904] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10625 15:37:33.281230 <6>[ 3.029246] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10626 15:37:33.287940 <6>[ 3.037585] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10627 15:37:33.297724 <6>[ 3.045923] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10628 15:37:33.304755 <6>[ 3.054263] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10629 15:37:33.314297 <6>[ 3.062600] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10630 15:37:33.324370 <6>[ 3.070939] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10631 15:37:33.330761 <6>[ 3.079277] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10632 15:37:33.341043 <6>[ 3.087615] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10633 15:37:33.347373 <6>[ 3.095953] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10634 15:37:33.357239 <6>[ 3.104291] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10635 15:37:33.363699 <6>[ 3.112629] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10636 15:37:33.373602 <6>[ 3.120967] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10637 15:37:33.380135 <6>[ 3.129305] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10638 15:37:33.387034 <6>[ 3.138055] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10639 15:37:33.394152 <6>[ 3.145183] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10640 15:37:33.400162 <6>[ 3.151941] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10641 15:37:33.410424 <6>[ 3.158718] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10642 15:37:33.417448 <6>[ 3.165641] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10643 15:37:33.423721 <6>[ 3.172485] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10644 15:37:33.433997 <6>[ 3.181614] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10645 15:37:33.444281 <6>[ 3.190734] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10646 15:37:33.453653 <6>[ 3.200029] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10647 15:37:33.463437 <6>[ 3.209497] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10648 15:37:33.473322 <6>[ 3.218965] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10649 15:37:33.480198 <6>[ 3.228084] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10650 15:37:33.489479 <6>[ 3.237551] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10651 15:37:33.499621 <6>[ 3.246671] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10652 15:37:33.509351 <6>[ 3.255971] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10653 15:37:33.519312 <6>[ 3.266130] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10654 15:37:33.529813 <6>[ 3.278125] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10655 15:37:33.581832 <6>[ 3.330387] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10656 15:37:33.736114 <6>[ 3.487709] hub 1-1:1.0: USB hub found
10657 15:37:33.739277 <6>[ 3.492199] hub 1-1:1.0: 4 ports detected
10658 15:37:33.862536 <6>[ 3.610550] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10659 15:37:33.889078 <6>[ 3.640133] hub 2-1:1.0: USB hub found
10660 15:37:33.891638 <6>[ 3.644652] hub 2-1:1.0: 3 ports detected
10661 15:37:34.062092 <6>[ 3.810399] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10662 15:37:34.193885 <6>[ 3.945714] hub 1-1.4:1.0: USB hub found
10663 15:37:34.197109 <6>[ 3.950327] hub 1-1.4:1.0: 2 ports detected
10664 15:37:34.274204 <6>[ 4.022430] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10665 15:37:34.494098 <6>[ 4.242433] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10666 15:37:34.685968 <6>[ 4.434426] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10667 15:37:45.811219 <6>[ 15.567395] ALSA device list:
10668 15:37:45.817800 <6>[ 15.570681] No soundcards found.
10669 15:37:45.824838 <6>[ 15.577936] Freeing unused kernel memory: 8384K
10670 15:37:45.828837 <6>[ 15.582961] Run /init as init process
10671 15:37:45.875541 <6>[ 15.628749] NET: Registered PF_INET6 protocol family
10672 15:37:45.882415 <6>[ 15.634955] Segment Routing with IPv6
10673 15:37:45.885510 <6>[ 15.638927] In-situ OAM (IOAM) with IPv6
10674 15:37:45.920003 <30>[ 15.653106] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10675 15:37:45.923263 <30>[ 15.676816] systemd[1]: Detected architecture arm64.
10676 15:37:45.923407
10677 15:37:45.929641 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10678 15:37:45.929751
10679 15:37:45.945397 <30>[ 15.698365] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10680 15:37:46.114069 <30>[ 15.862836] systemd[1]: Queued start job for default target Graphical Interface.
10681 15:37:46.162705 <30>[ 15.914820] systemd[1]: Created slice system-getty.slice.
10682 15:37:46.168957 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10683 15:37:46.186179 <30>[ 15.938659] systemd[1]: Created slice system-modprobe.slice.
10684 15:37:46.192686 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10685 15:37:46.210967 <30>[ 15.962890] systemd[1]: Created slice system-serial\x2dgetty.slice.
10686 15:37:46.220504 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10687 15:37:46.234787 <30>[ 15.986857] systemd[1]: Created slice User and Session Slice.
10688 15:37:46.241225 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10689 15:37:46.262077 <30>[ 16.010981] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10690 15:37:46.271455 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10691 15:37:46.289390 <30>[ 16.038528] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10692 15:37:46.295720 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10693 15:37:46.316288 <30>[ 16.062464] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10694 15:37:46.323423 <30>[ 16.074589] systemd[1]: Reached target Local Encrypted Volumes.
10695 15:37:46.329934 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10696 15:37:46.345930 <30>[ 16.098490] systemd[1]: Reached target Paths.
10697 15:37:46.349512 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10698 15:37:46.366303 <30>[ 16.118401] systemd[1]: Reached target Remote File Systems.
10699 15:37:46.372568 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10700 15:37:46.390643 <30>[ 16.142709] systemd[1]: Reached target Slices.
10701 15:37:46.396844 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10702 15:37:46.410171 <30>[ 16.162412] systemd[1]: Reached target Swap.
10703 15:37:46.413681 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10704 15:37:46.433881 <30>[ 16.182878] systemd[1]: Listening on initctl Compatibility Named Pipe.
10705 15:37:46.440461 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10706 15:37:46.446877 <30>[ 16.198036] systemd[1]: Listening on Journal Audit Socket.
10707 15:37:46.453161 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10708 15:37:46.466700 <30>[ 16.218870] systemd[1]: Listening on Journal Socket (/dev/log).
10709 15:37:46.473333 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10710 15:37:46.490924 <30>[ 16.243503] systemd[1]: Listening on Journal Socket.
10711 15:37:46.497989 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10712 15:37:46.513875 <30>[ 16.263059] systemd[1]: Listening on Network Service Netlink Socket.
10713 15:37:46.520874 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10714 15:37:46.534922 <30>[ 16.287493] systemd[1]: Listening on udev Control Socket.
10715 15:37:46.541630 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10716 15:37:46.559218 <30>[ 16.311360] systemd[1]: Listening on udev Kernel Socket.
10717 15:37:46.565552 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10718 15:37:46.605744 <30>[ 16.358547] systemd[1]: Mounting Huge Pages File System...
10719 15:37:46.612875 Mounting [0;1;39mHuge Pages File System[0m...
10720 15:37:46.627767 <30>[ 16.379937] systemd[1]: Mounting POSIX Message Queue File System...
10721 15:37:46.634308 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10722 15:37:46.652002 <30>[ 16.403993] systemd[1]: Mounting Kernel Debug File System...
10723 15:37:46.658597 Mounting [0;1;39mKernel Debug File System[0m...
10724 15:37:46.677824 <30>[ 16.426498] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10725 15:37:46.688855 <30>[ 16.437801] systemd[1]: Starting Create list of static device nodes for the current kernel...
10726 15:37:46.695299 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10727 15:37:46.714075 <30>[ 16.466426] systemd[1]: Starting Load Kernel Module configfs...
10728 15:37:46.720742 Starting [0;1;39mLoad Kernel Module configfs[0m...
10729 15:37:46.738796 <30>[ 16.490630] systemd[1]: Starting Load Kernel Module drm...
10730 15:37:46.744798 Starting [0;1;39mLoad Kernel Module drm[0m...
10731 15:37:46.761672 <30>[ 16.510738] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10732 15:37:46.814738 <30>[ 16.567081] systemd[1]: Starting Journal Service...
10733 15:37:46.818481 Starting [0;1;39mJournal Service[0m...
10734 15:37:46.838345 <30>[ 16.590855] systemd[1]: Starting Load Kernel Modules...
10735 15:37:46.845129 Starting [0;1;39mLoad Kernel Modules[0m...
10736 15:37:46.865153 <30>[ 16.614355] systemd[1]: Starting Remount Root and Kernel File Systems...
10737 15:37:46.871803 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10738 15:37:46.889759 <30>[ 16.642094] systemd[1]: Starting Coldplug All udev Devices...
10739 15:37:46.896450 Starting [0;1;39mColdplug All udev Devices[0m...
10740 15:37:46.913062 <30>[ 16.664965] systemd[1]: Started Journal Service.
10741 15:37:46.918978 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10742 15:37:46.935168 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10743 15:37:46.950652 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10744 15:37:46.966472 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10745 15:37:46.986627 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10746 15:37:47.003261 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10747 15:37:47.020564 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10748 15:37:47.039682 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10749 15:37:47.060031 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10750 15:37:47.074332 See 'systemctl status systemd-remount-fs.service' for details.
10751 15:37:47.129984 Mounting [0;1;39mKernel Configuration File System[0m...
10752 15:37:47.148338 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10753 15:37:47.158424 <46>[ 16.907571] systemd-journald[185]: Received client request to flush runtime journal.
10754 15:37:47.165331 Starting [0;1;39mLoad/Save Random Seed[0m...
10755 15:37:47.184486 Starting [0;1;39mApply Kernel Variables[0m...
10756 15:37:47.201022 Starting [0;1;39mCreate System Users[0m...
10757 15:37:47.216042 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10758 15:37:47.234582 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10759 15:37:47.258899 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10760 15:37:47.271945 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10761 15:37:47.291799 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10762 15:37:47.308231 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10763 15:37:47.354495 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10764 15:37:47.382321 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10765 15:37:47.394385 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10766 15:37:47.409972 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10767 15:37:47.454710 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10768 15:37:47.477851 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10769 15:37:47.498491 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10770 15:37:47.518046 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10771 15:37:47.561553 Starting [0;1;39mNetwork Service[0m...
10772 15:37:47.579594 Starting [0;1;39mNetwork Time Synchronization[0m...
10773 15:37:47.592521 <6>[ 17.342037] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10774 15:37:47.599967 <6>[ 17.352634] remoteproc remoteproc0: scp is available
10775 15:37:47.606814 Startin<6>[ 17.358407] remoteproc remoteproc0: powering up scp
10776 15:37:47.617162 g [0;1;39mUpdat<6>[ 17.364781] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10777 15:37:47.626595 e UTMP about Sys<3>[ 17.365935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10778 15:37:47.632574 tem Boot/Shutdow<6>[ 17.374581] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10779 15:37:47.633068 n[0m...
10780 15:37:47.642926 <6>[ 17.379954] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10781 15:37:47.649976 <3>[ 17.383866] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10782 15:37:47.656602 <6>[ 17.391184] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10783 15:37:47.666333 <3>[ 17.399473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 15:37:47.670475 <6>[ 17.403615] usbcore: registered new interface driver r8152
10785 15:37:47.679473 <6>[ 17.407495] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10786 15:37:47.689595 <6>[ 17.407500] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10787 15:37:47.696272 <4>[ 17.407786] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10788 15:37:47.699645 <6>[ 17.410256] mc: Linux media interface: v0.10
10789 15:37:47.709510 <4>[ 17.413637] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10790 15:37:47.712580 <4>[ 17.413637] Fallback method does not support PEC.
10791 15:37:47.722459 <3>[ 17.415235] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10792 15:37:47.729379 <4>[ 17.423581] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10793 15:37:47.739035 <3>[ 17.429183] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10794 15:37:47.745589 <3>[ 17.430191] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10795 15:37:47.755989 <3>[ 17.430198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10796 15:37:47.762129 <3>[ 17.430202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10797 15:37:47.772518 <3>[ 17.430205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10798 15:37:47.779265 <3>[ 17.430719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10799 15:37:47.785224 <3>[ 17.430747] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10800 15:37:47.795429 <3>[ 17.430750] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10801 15:37:47.802309 <3>[ 17.430753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10802 15:37:47.812537 <3>[ 17.430779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10803 15:37:47.819681 <3>[ 17.430782] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10804 15:37:47.826324 <3>[ 17.430784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10805 15:37:47.836892 <3>[ 17.430787] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10806 15:37:47.843759 <3>[ 17.430790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10807 15:37:47.850594 <3>[ 17.430799] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10808 15:37:47.857013 <6>[ 17.438550] videodev: Linux video capture interface: v2.00
10809 15:37:47.864287 <6>[ 17.482411] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10810 15:37:47.870999 <6>[ 17.527437] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10811 15:37:47.877461 <6>[ 17.528481] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10812 15:37:47.887597 <6>[ 17.528520] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10813 15:37:47.894301 <6>[ 17.528525] remoteproc remoteproc0: remote processor scp is now up
10814 15:37:47.898001 <6>[ 17.536516] pci_bus 0000:00: root bus resource [bus 00-ff]
10815 15:37:47.908436 <6>[ 17.536518] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10816 15:37:47.917869 <6>[ 17.536521] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10817 15:37:47.924001 <6>[ 17.550588] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10818 15:37:47.931376 <6>[ 17.552697] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10819 15:37:47.941095 <6>[ 17.553215] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10820 15:37:47.951273 <6>[ 17.553540] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10821 15:37:47.958053 <6>[ 17.568856] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10822 15:37:47.968198 <3>[ 17.574199] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10823 15:37:47.974685 <3>[ 17.574993] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10824 15:37:47.984998 <6>[ 17.576926] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10825 15:37:47.988761 <6>[ 17.576990] pci 0000:00:00.0: supports D1 D2
10826 15:37:47.998377 <4>[ 17.582468] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10827 15:37:48.005054 <4>[ 17.582478] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10828 15:37:48.015364 <3>[ 17.583537] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10829 15:37:48.022205 <3>[ 17.584510] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10830 15:37:48.025541 <6>[ 17.585573] Bluetooth: Core ver 2.22
10831 15:37:48.032346 <6>[ 17.585597] usbcore: registered new interface driver cdc_ether
10832 15:37:48.038993 <6>[ 17.587753] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10833 15:37:48.045614 <6>[ 17.593113] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10834 15:37:48.056697 <6>[ 17.593926] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10835 15:37:48.060241 <6>[ 17.601324] usbcore: registered new interface driver r8153_ecm
10836 15:37:48.066818 <6>[ 17.601655] NET: Registered PF_BLUETOOTH protocol family
10837 15:37:48.073966 <6>[ 17.601657] Bluetooth: HCI device and connection manager initialized
10838 15:37:48.077935 <6>[ 17.601665] Bluetooth: HCI socket layer initialized
10839 15:37:48.084004 <6>[ 17.601668] Bluetooth: L2CAP socket layer initialized
10840 15:37:48.091054 <6>[ 17.601673] Bluetooth: SCO socket layer initialized
10841 15:37:48.097383 <3>[ 17.604938] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10842 15:37:48.104143 <6>[ 17.609360] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10843 15:37:48.113949 <3>[ 17.626996] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10844 15:37:48.120627 <6>[ 17.629021] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10845 15:37:48.127343 <6>[ 17.629771] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10846 15:37:48.130188 <6>[ 17.630304] r8152 2-1.3:1.0 eth0: v1.12.13
10847 15:37:48.143643 <6>[ 17.631170] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10848 15:37:48.149723 <6>[ 17.631313] usbcore: registered new interface driver uvcvideo
10849 15:37:48.156757 <6>[ 17.639133] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10850 15:37:48.164184 <6>[ 17.644558] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10851 15:37:48.173807 <3>[ 17.657600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10852 15:37:48.180292 <6>[ 17.663854] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10853 15:37:48.182830 <6>[ 17.663958] pci 0000:01:00.0: supports D1 D2
10854 15:37:48.189446 <6>[ 17.664246] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10855 15:37:48.195780 <6>[ 17.664253] usbcore: registered new interface driver btusb
10856 15:37:48.205945 <4>[ 17.664751] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10857 15:37:48.212332 <3>[ 17.664760] Bluetooth: hci0: Failed to load firmware file (-2)
10858 15:37:48.218948 <3>[ 17.664764] Bluetooth: hci0: Failed to set up firmware (-2)
10859 15:37:48.228978 <4>[ 17.664767] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10860 15:37:48.238599 <3>[ 17.697118] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10861 15:37:48.245700 <6>[ 17.699377] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10862 15:37:48.251593 <6>[ 17.714205] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10863 15:37:48.261690 <3>[ 17.739009] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10864 15:37:48.268230 <6>[ 17.741173] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10865 15:37:48.275478 <6>[ 18.026666] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10866 15:37:48.285327 [[0;32m OK [<6>[ 18.034793] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10867 15:37:48.295247 0m] Started [0;<6>[ 18.044174] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10868 15:37:48.305552 1;39mNetwork Tim<6>[ 18.053523] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10869 15:37:48.311405 e Synchronizatio<6>[ 18.062943] pci 0000:00:00.0: PCI bridge to [bus 01]
10870 15:37:48.311524 n[0m.
10871 15:37:48.321113 <6>[ 18.069606] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10872 15:37:48.328447 <6>[ 18.078368] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10873 15:37:48.334442 [[0;32m OK [<6>[ 18.085417] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10874 15:37:48.341008 0m] Started [0;<6>[ 18.092805] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10875 15:37:48.344694 1;39mNetwork Service[0m.
10876 15:37:48.365167 <5>[ 18.115149] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10877 15:37:48.379898 <5>[ 18.129583] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10878 15:37:48.386731 <4>[ 18.136492] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10879 15:37:48.392629 <6>[ 18.145392] cfg80211: failed to load regulatory.db
10880 15:37:48.409658 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10881 15:37:48.434513 <6>[ 18.184401] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10882 15:37:48.440816 <6>[ 18.191974] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10883 15:37:48.444482 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10884 15:37:48.465241 <6>[ 18.218311] mt7921e 0000:01:00.0: ASIC revision: 79610010
10885 15:37:48.560955 <4>[ 18.307682] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10886 15:37:48.606155 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10887 15:37:48.621475 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10888 15:37:48.637836 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10889 15:37:48.653857 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10890 15:37:48.667965 <4>[ 18.414046] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10891 15:37:48.678062 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10892 15:37:48.717942 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10893 15:37:48.740648 Starting [0;1;39mNetwork Name Resolution[0m...
10894 15:37:48.759751 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10895 15:37:48.773964 <4>[ 18.520634] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10896 15:37:48.780801 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10897 15:37:48.802504 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10898 15:37:48.817209 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10899 15:37:48.829457 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10900 15:37:48.849612 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10901 15:37:48.865553 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10902 15:37:48.872443 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10903 15:37:48.882452 <4>[ 18.630146] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10904 15:37:48.921974 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10905 15:37:48.952295 Starting [0;1;39mUser Login Management[0m...
10906 15:37:48.969712 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10907 15:37:48.993712 [[0;32m OK [<4>[ 18.740575] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10908 15:37:49.000391 0m] Started [0;1;39mNetwork Name Resolution[0m.
10909 15:37:49.006478 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10910 15:37:49.022276 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10911 15:37:49.040925 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10912 15:37:49.078023 Starting [0;1;39mPermit User Sessions[0m...
10913 15:37:49.106721 [[0;32m OK [0m] Finished [0<4>[ 18.852026] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10914 15:37:49.109676 ;1;39mPermit User Sessions[0m.
10915 15:37:49.118715 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10916 15:37:49.162967 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10917 15:37:49.180223 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10918 15:37:49.198265 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10919 15:37:49.215401 <4>[ 18.961651] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10920 15:37:49.221811 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10921 15:37:49.238278 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10922 15:37:49.274565 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10923 15:37:49.315105 [[0;32m OK [0m] Finished [0<4>[ 19.060478] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10924 15:37:49.318629 ;1;39mUpdate UTMP about System Runlevel Changes[0m.
10925 15:37:49.357201
10926 15:37:49.357688
10927 15:37:49.360338 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10928 15:37:49.360757
10929 15:37:49.363540 debian-bullseye-arm64 login: root (automatic login)
10930 15:37:49.364044
10931 15:37:49.364384
10932 15:37:49.374215 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Tue Aug 22 15:20:14 UTC 2023 aarch64
10933 15:37:49.374632
10934 15:37:49.381267 The programs included with the Debian GNU/Linux system are free software;
10935 15:37:49.388205 the exact distribution terms for each program are described in the
10936 15:37:49.390945 individual files in /usr/share/doc/*/copyright.
10937 15:37:49.391360
10938 15:37:49.397651 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10939 15:37:49.401146 permitted by applicable law.
10940 15:37:49.402224 Matched prompt #10: / #
10942 15:37:49.403211 Setting prompt string to ['/ #']
10943 15:37:49.403678 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10945 15:37:49.404788 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10946 15:37:49.404893 start: 2.2.6 expect-shell-connection (timeout 00:02:54) [common]
10947 15:37:49.404974 Setting prompt string to ['/ #']
10948 15:37:49.405049 Forcing a shell prompt, looking for ['/ #']
10950 15:37:49.455322 / #
10951 15:37:49.455524 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10952 15:37:49.455661 Waiting using forced prompt support (timeout 00:02:30)
10953 15:37:49.455861 <4>[ 19.177010] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10954 15:37:49.460452
10955 15:37:49.460814 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10956 15:37:49.461004 start: 2.2.7 export-device-env (timeout 00:02:54) [common]
10957 15:37:49.461162 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10958 15:37:49.461312 end: 2.2 depthcharge-retry (duration 00:02:06) [common]
10959 15:37:49.461463 end: 2 depthcharge-action (duration 00:02:06) [common]
10960 15:37:49.461631 start: 3 lava-test-retry (timeout 00:07:33) [common]
10961 15:37:49.461799 start: 3.1 lava-test-shell (timeout 00:07:33) [common]
10962 15:37:49.461935 Using namespace: common
10964 15:37:49.562680 / # #
10965 15:37:49.563307 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10966 15:37:49.563982 #<6>[ 19.288959] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307c7b: link becomes ready
10967 15:37:49.564372 <6>[ 19.296944] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10968 15:37:49.564800 <4>[ 19.302567] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10969 15:37:49.568936
10970 15:37:49.569676 Using /lava-11331377
10972 15:37:49.670902 / # export SHELL=/bin/sh
10973 15:37:49.671753 export SHELL=/bin/sh<3>[ 19.406749] mt7921e 0000:01:00.0: hardware init failed
10974 15:37:49.677220
10976 15:37:49.778680 / # . /lava-11331377/environment
10977 15:37:49.784902 . /lava-11331377/environment
10979 15:37:49.886406 / # /lava-11331377/bin/lava-test-runner /lava-11331377/0
10980 15:37:49.886976 Test shell timeout: 10s (minimum of the action and connection timeout)
10981 15:37:49.892615 /lava-11331377/bin/lava-test-runner /lava-11331377/0
10982 15:37:49.915467 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10983 15:37:49.922618 + cd /lava-11331377/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10984 15:37:49.923178 + cat uuid
10985 15:37:49.925231 + UUID=11331377_1.5.2.3.1
10986 15:37:49.925693 + set +x
10987 15:37:49.931606 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11331377_1.5.2.3.1>
10988 15:37:49.932576 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11331377_1.5.2.3.1
10989 15:37:49.933140 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11331377_1.5.2.3.1)
10990 15:37:49.933755 Skipping test definition patterns.
10991 15:37:49.935103 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
10992 15:37:49.993824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10993 15:37:49.994614 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10995 15:37:49.996734 device: /dev/video2
10996 15:37:50.019277 <4>[ 19.769158] use of bytesused == 0 is deprecated and will be removed in the future,
10997 15:37:50.022848 <4>[ 19.777101] use the actual size instead.
10998 15:37:50.030964 <4>[ 19.783001] ------------[ cut here ]------------
10999 15:37:50.036422 <4>[ 19.787962] get_vaddr_frames() cannot follow VM_IO mapping
11000 15:37:50.046582 <4>[ 19.788040] WARNING: CPU: 0 PID: 311 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11001 15:37:50.096243 <4>[ 19.806145] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 btusb mtk_vcodec_enc mtk_vcodec_common btintel mtk_vpu btmtk uvcvideo btrtl v4l2_mem2mem btbcm videobuf2_vmalloc videobuf2_dma_contig videobuf2_memops r8153_ecm cdc_ether videobuf2_v4l2 bluetooth usbnet videobuf2_common ecdh_generic cros_ec_rpmsg crct10dif_ce videodev elants_i2c elan_i2c mc pcie_mediatek_gen3 r8152 ecc rfkill sbs_battery cros_ec_chardev hid_google_hammer hid_vivaldi_common cros_ec_typec mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11002 15:37:50.106016 <4>[ 19.855537] CPU: 0 PID: 311 Comm: v4l2-compliance Not tainted 6.1.45-cip3 #1
11003 15:37:50.109081 <4>[ 19.862835] Hardware name: Google Spherion (rev0 - 3) (DT)
11004 15:37:50.119231 <4>[ 19.868570] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11005 15:37:50.122694 <4>[ 19.875783] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11006 15:37:50.129346 <4>[ 19.881876] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11007 15:37:50.132521 <4>[ 19.887969] sp : ffff8000091fb850
11008 15:37:50.143024 <4>[ 19.891532] x29: ffff8000091fb850 x28: ffffdbda0d248000 x27: ffffdbda0d244238
11009 15:37:50.148788 <4>[ 19.898922] x26: 0000000000000000 x25: ffffdbda5f02c0e0 x24: ffff525f0eb69298
11010 15:37:50.155552 <4>[ 19.906310] x23: ffff525f00b1c800 x22: ffff525f00d48410 x21: 0000000000000000
11011 15:37:50.162681 <4>[ 19.913698] x20: 00000000fffffff2 x19: ffff525f0d80f400 x18: fffffffffffe9768
11012 15:37:50.172248 <4>[ 19.921086] x17: 0000000000000000 x16: ffffdbda5ce8bb90 x15: 0000000000000038
11013 15:37:50.178778 <4>[ 19.928473] x14: 0000000000000031 x13: 0000000000000001 x12: 0000000000000001
11014 15:37:50.185131 <4>[ 19.935862] x11: 0000000000000000 x10: 0000000000000a60 x9 : ffff8000091fb700
11015 15:37:50.192274 <4>[ 19.943249] x8 : ffff525f0c49c5c0 x7 : ffff52603ef1be40 x6 : 00000000ffffffff
11016 15:37:50.199161 <4>[ 19.950637] x5 : 00000000410fd050 x4 : 0000000000c0000e x3 : 0000000000200000
11017 15:37:50.208443 <4>[ 19.958024] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff525f0c49bb00
11018 15:37:50.212305 <4>[ 19.965412] Call trace:
11019 15:37:50.215056 <4>[ 19.968109] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11020 15:37:50.222166 <4>[ 19.973855] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11021 15:37:50.228497 <4>[ 19.979858] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11022 15:37:50.235062 <4>[ 19.986212] __prepare_userptr+0x280/0x410 [videobuf2_common]
11023 15:37:50.241716 <4>[ 19.992217] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11024 15:37:50.244518 <4>[ 19.997876] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11025 15:37:50.251405 <4>[ 20.004054] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11026 15:37:50.258427 <4>[ 20.009557] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11027 15:37:50.264740 <4>[ 20.015331] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11028 15:37:50.267699 <4>[ 20.021598] v4l_prepare_buf+0x48/0x60 [videodev]
11029 15:37:50.275483 <4>[ 20.026592] __video_do_ioctl+0x184/0x3d0 [videodev]
11030 15:37:50.278679 <4>[ 20.031842] video_usercopy+0x358/0x680 [videodev]
11031 15:37:50.284365 <4>[ 20.036918] video_ioctl2+0x18/0x30 [videodev]
11032 15:37:50.288080 <4>[ 20.041646] v4l2_ioctl+0x40/0x60 [videodev]
11033 15:37:50.291638 <4>[ 20.046200] __arm64_sys_ioctl+0xa8/0xf0
11034 15:37:50.297652 <4>[ 20.050380] invoke_syscall+0x48/0x114
11035 15:37:50.301270 <4>[ 20.054384] el0_svc_common.constprop.0+0x44/0xec
11036 15:37:50.304613 <4>[ 20.059340] do_el0_svc+0x2c/0xd0
11037 15:37:50.307734 <4>[ 20.062907] el0_svc+0x2c/0x84
11038 15:37:50.311106 <4>[ 20.066214] el0t_64_sync_handler+0xb8/0xc0
11039 15:37:50.318090 <4>[ 20.070649] el0t_64_sync+0x18c/0x190
11040 15:37:50.320898 <4>[ 20.074564] ---[ end trace 0000000000000000 ]---
11041 15:37:50.332633 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11042 15:37:50.341534 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11043 15:37:50.348726
11044 15:37:50.365982 Compliance test for mtk-vcodec-enc device /dev/video2:
11045 15:37:50.374471
11046 15:37:50.388847 Driver Info:
11047 15:37:50.399322 Driver name : mtk-vcodec-enc
11048 15:37:50.413909 Card type : MT8192 video encoder
11049 15:37:50.428303 Bus info : platform:17020000.vcodec
11050 15:37:50.436063 Driver version : 6.1.45
11051 15:37:50.449350 Capabilities : 0x84204000
11052 15:37:50.460718 Video Memory-to-Memory Multiplanar
11053 15:37:50.474779 Streaming
11054 15:37:50.485301 Extended Pix Format
11055 15:37:50.494780 Device Capabilities
11056 15:37:50.503898 Device Caps : 0x04204000
11057 15:37:50.517463 Video Memory-to-Memory Multiplanar
11058 15:37:50.526237 Streaming
11059 15:37:50.535517 Extended Pix Format
11060 15:37:50.546191 Detected Stateful Encoder
11061 15:37:50.556604
11062 15:37:50.565845 Required ioctls:
11063 15:37:50.580104 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11064 15:37:50.580669 test VIDIOC_QUERYCAP: OK
11065 15:37:50.581374 Received signal: <TESTSET> START Required-ioctls
11066 15:37:50.581780 Starting test_set Required-ioctls
11067 15:37:50.601034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11068 15:37:50.601872 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11070 15:37:50.603708 test invalid ioctls: OK
11071 15:37:50.622238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11072 15:37:50.622797
11073 15:37:50.623436 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11075 15:37:50.631824 Allow for multiple opens:
11076 15:37:50.642090 <LAVA_SIGNAL_TESTSET STOP>
11077 15:37:50.642930 Received signal: <TESTSET> STOP
11078 15:37:50.643332 Closing test_set Required-ioctls
11079 15:37:50.652268 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11080 15:37:50.653084 Received signal: <TESTSET> START Allow-for-multiple-opens
11081 15:37:50.653498 Starting test_set Allow-for-multiple-opens
11082 15:37:50.655489 test second /dev/video2 open: OK
11083 15:37:50.674585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11084 15:37:50.675413 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11086 15:37:50.677948 test VIDIOC_QUERYCAP: OK
11087 15:37:50.696415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11088 15:37:50.697248 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11090 15:37:50.699392 test VIDIOC_G/S_PRIORITY: OK
11091 15:37:50.717768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11092 15:37:50.718618 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11094 15:37:50.720615 test for unlimited opens: OK
11095 15:37:50.739385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11096 15:37:50.739987
11097 15:37:50.740647 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11099 15:37:50.749642 Debug ioctls:
11100 15:37:50.758354 <LAVA_SIGNAL_TESTSET STOP>
11101 15:37:50.759179 Received signal: <TESTSET> STOP
11102 15:37:50.759571 Closing test_set Allow-for-multiple-opens
11103 15:37:50.768396 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11104 15:37:50.769249 Received signal: <TESTSET> START Debug-ioctls
11105 15:37:50.769642 Starting test_set Debug-ioctls
11106 15:37:50.772046 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11107 15:37:50.789906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11108 15:37:50.790748 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11110 15:37:50.796800 test VIDIOC_LOG_STATUS: OK (Not Supported)
11111 15:37:50.813931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11112 15:37:50.814495
11113 15:37:50.815134 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11115 15:37:50.823378 Input ioctls:
11116 15:37:50.830839 <LAVA_SIGNAL_TESTSET STOP>
11117 15:37:50.831505 Received signal: <TESTSET> STOP
11118 15:37:50.831851 Closing test_set Debug-ioctls
11119 15:37:50.839869 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11120 15:37:50.840689 Received signal: <TESTSET> START Input-ioctls
11121 15:37:50.841043 Starting test_set Input-ioctls
11122 15:37:50.843317 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11123 15:37:50.866093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11124 15:37:50.866912 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11126 15:37:50.869191 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11127 15:37:50.886774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11128 15:37:50.887561 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11130 15:37:50.893535 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11131 15:37:50.911214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11132 15:37:50.911900 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11134 15:37:50.917287 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11135 15:37:50.933010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11136 15:37:50.933835 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11138 15:37:50.936118 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11139 15:37:50.955041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11140 15:37:50.955864 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11142 15:37:50.958421 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11143 15:37:50.977159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11144 15:37:50.977999 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11146 15:37:50.979890 Inputs: 0 Audio Inputs: 0 Tuners: 0
11147 15:37:50.987066
11148 15:37:51.007241 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11149 15:37:51.026968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11150 15:37:51.027798 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11152 15:37:51.033933 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11153 15:37:51.047154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11154 15:37:51.048084 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11156 15:37:51.053452 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11157 15:37:51.069576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11158 15:37:51.070390 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11160 15:37:51.075856 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11161 15:37:51.091822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11162 15:37:51.092794 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11164 15:37:51.098175 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11165 15:37:51.115962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11166 15:37:51.116531
11167 15:37:51.117182 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11169 15:37:51.136156 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11170 15:37:51.157518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11171 15:37:51.158337 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11173 15:37:51.164884 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11174 15:37:51.182528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11175 15:37:51.183347 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11177 15:37:51.185670 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11178 15:37:51.205509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11179 15:37:51.206437 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11181 15:37:51.208370 test VIDIOC_G/S_EDID: OK (Not Supported)
11182 15:37:51.227434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11183 15:37:51.228035
11184 15:37:51.228679 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11186 15:37:51.236247 Control ioctls:
11187 15:37:51.243407 <LAVA_SIGNAL_TESTSET STOP>
11188 15:37:51.244077 Received signal: <TESTSET> STOP
11189 15:37:51.244434 Closing test_set Input-ioctls
11190 15:37:51.252139 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11191 15:37:51.252813 Received signal: <TESTSET> START Control-ioctls
11192 15:37:51.253169 Starting test_set Control-ioctls
11193 15:37:51.255142 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11194 15:37:51.278047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11195 15:37:51.278487 test VIDIOC_QUERYCTRL: OK
11196 15:37:51.279077 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11198 15:37:51.296434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11199 15:37:51.297243 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11201 15:37:51.299488 test VIDIOC_G/S_CTRL: OK
11202 15:37:51.318340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11203 15:37:51.319016 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11205 15:37:51.322120 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11206 15:37:51.339384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11207 15:37:51.340068 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11209 15:37:51.349160 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11210 15:37:51.352475 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11211 15:37:51.378816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11212 15:37:51.379589 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11214 15:37:51.381469 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11215 15:37:51.396965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11216 15:37:51.397639 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11218 15:37:51.400353 Standard Controls: 16 Private Controls: 0
11219 15:37:51.405174
11220 15:37:51.415736 Format ioctls:
11221 15:37:51.426279 <LAVA_SIGNAL_TESTSET STOP>
11222 15:37:51.427077 Received signal: <TESTSET> STOP
11223 15:37:51.427439 Closing test_set Control-ioctls
11224 15:37:51.434847 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11225 15:37:51.435627 Received signal: <TESTSET> START Format-ioctls
11226 15:37:51.436020 Starting test_set Format-ioctls
11227 15:37:51.438237 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11228 15:37:51.458824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11229 15:37:51.459628 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11231 15:37:51.461982 test VIDIOC_G/S_PARM: OK
11232 15:37:51.475380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11233 15:37:51.476125 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11235 15:37:51.479315 test VIDIOC_G_FBUF: OK (Not Supported)
11236 15:37:51.500170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11237 15:37:51.501007 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11239 15:37:51.503233 test VIDIOC_G_FMT: OK
11240 15:37:51.520571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11241 15:37:51.521370 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11243 15:37:51.523820 test VIDIOC_TRY_FMT: OK
11244 15:37:51.542657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11245 15:37:51.543447 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11247 15:37:51.552562 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11248 15:37:51.553145 test VIDIOC_S_FMT: FAIL
11249 15:37:51.577314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11250 15:37:51.578135 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11252 15:37:51.581390 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11253 15:37:51.599319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11254 15:37:51.600158 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11256 15:37:51.602716 test Cropping: OK
11257 15:37:51.624015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11258 15:37:51.624861 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11260 15:37:51.626491 test Composing: OK (Not Supported)
11261 15:37:51.645447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11262 15:37:51.646402 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11264 15:37:51.648672 test Scaling: OK (Not Supported)
11265 15:37:51.667504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11266 15:37:51.668044
11267 15:37:51.668645 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11269 15:37:51.676649 Codec ioctls:
11270 15:37:51.683169 <LAVA_SIGNAL_TESTSET STOP>
11271 15:37:51.684026 Received signal: <TESTSET> STOP
11272 15:37:51.684400 Closing test_set Format-ioctls
11273 15:37:51.691537 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11274 15:37:51.692390 Received signal: <TESTSET> START Codec-ioctls
11275 15:37:51.692803 Starting test_set Codec-ioctls
11276 15:37:51.694862 test VIDIOC_(TRY_)ENCODER_CMD: OK
11277 15:37:51.714888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11278 15:37:51.715761 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11280 15:37:51.721309 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11281 15:37:51.735769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11282 15:37:51.736763 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11284 15:37:51.741690 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11285 15:37:51.757832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11286 15:37:51.758513
11287 15:37:51.759296 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11289 15:37:51.768761 Buffer ioctls:
11290 15:37:51.776796 <LAVA_SIGNAL_TESTSET STOP>
11291 15:37:51.777635 Received signal: <TESTSET> STOP
11292 15:37:51.778033 Closing test_set Codec-ioctls
11293 15:37:51.788106 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11294 15:37:51.789147 Received signal: <TESTSET> START Buffer-ioctls
11295 15:37:51.789557 Starting test_set Buffer-ioctls
11296 15:37:51.790928 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11297 15:37:51.813222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11298 15:37:51.813849 test VIDIOC_EXPBUF: OK
11299 15:37:51.814496 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11301 15:37:51.834458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11302 15:37:51.835333 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11304 15:37:51.838277 test Requests: OK (Not Supported)
11305 15:37:51.857808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11306 15:37:51.858361
11307 15:37:51.859065 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11309 15:37:51.868049 Test input 0:
11310 15:37:51.878432
11311 15:37:51.889126 Streaming ioctls:
11312 15:37:51.897956 <LAVA_SIGNAL_TESTSET STOP>
11313 15:37:51.898795 Received signal: <TESTSET> STOP
11314 15:37:51.899199 Closing test_set Buffer-ioctls
11315 15:37:51.907853 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11316 15:37:51.908741 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11317 15:37:51.909138 Starting test_set Streaming-ioctls_Test-input-0
11318 15:37:51.911053 test read/write: OK (Not Supported)
11319 15:37:51.929430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11320 15:37:51.930229 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11322 15:37:51.936775 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11323 15:37:51.945859 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11324 15:37:51.951637 test blocking wait: FAIL
11325 15:37:51.976186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11326 15:37:51.976971 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11328 15:37:51.986140 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11329 15:37:51.986566 test MMAP (select): FAIL
11330 15:37:52.014523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11331 15:37:52.015320 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11333 15:37:52.021320 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11334 15:37:52.024750 test MMAP (epoll): FAIL
11335 15:37:52.048899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11336 15:37:52.049750 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11338 15:37:52.058073 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11339 15:37:52.064801 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11340 15:37:52.068086 test USERPTR (select): FAIL
11341 15:37:52.093675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11342 15:37:52.094427 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11344 15:37:52.100050 test DMABUF: Cannot test, specify --expbuf-device
11345 15:37:52.100474
11346 15:37:52.118765 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11347 15:37:52.121754 <LAVA_TEST_RUNNER EXIT>
11348 15:37:52.122436 ok: lava_test_shell seems to have completed
11349 15:37:52.122808 Marking unfinished test run as failed
11351 15:37:52.127160 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11352 15:37:52.127739 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11353 15:37:52.128192 end: 3 lava-test-retry (duration 00:00:03) [common]
11354 15:37:52.128613 start: 4 finalize (timeout 00:07:30) [common]
11355 15:37:52.129055 start: 4.1 power-off (timeout 00:00:30) [common]
11356 15:37:52.129822 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11357 15:37:52.249140 >> Command sent successfully.
11358 15:37:52.252945 Returned 0 in 0 seconds
11359 15:37:52.353866 end: 4.1 power-off (duration 00:00:00) [common]
11361 15:37:52.355572 start: 4.2 read-feedback (timeout 00:07:30) [common]
11362 15:37:52.356938 Listened to connection for namespace 'common' for up to 1s
11363 15:37:53.357520 Finalising connection for namespace 'common'
11364 15:37:53.358140 Disconnecting from shell: Finalise
11365 15:37:53.358528 / #
11366 15:37:53.459574 end: 4.2 read-feedback (duration 00:00:01) [common]
11367 15:37:53.460335 end: 4 finalize (duration 00:00:01) [common]
11368 15:37:53.460892 Cleaning after the job
11369 15:37:53.461370 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/ramdisk
11370 15:37:53.485916 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/kernel
11371 15:37:53.507039 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/dtb
11372 15:37:53.507334 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11331377/tftp-deploy-kvidpy_w/modules
11373 15:37:53.518053 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11331377
11374 15:37:53.584979 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11331377
11375 15:37:53.585140 Job finished correctly